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KVM: Update Posted-Interrupts Descriptor when vCPU is preempted
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
af658dca 31#include <linux/trace_events.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
28b835d6 38#include <asm/cpu.h>
6aa8b732 39#include <asm/io.h>
3b3be0d1 40#include <asm/desc.h>
13673a90 41#include <asm/vmx.h>
6210e37b 42#include <asm/virtext.h>
a0861c02 43#include <asm/mce.h>
952f07ec 44#include <asm/fpu/internal.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
dab2087d 48#include <asm/apic.h>
efc64404 49#include <asm/irq_remapping.h>
6aa8b732 50
229456fc 51#include "trace.h"
25462f7f 52#include "pmu.h"
229456fc 53
4ecac3fd 54#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 55#define __ex_clear(x, reg) \
56 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 57
6aa8b732
AK		 58MODULE_AUTHOR("Qumranet");
59MODULE_LICENSE("GPL");
60
e9bda3b3
JT		 61static const struct x86_cpu_id vmx_cpu_id[] = {
62 X86_FEATURE_MATCH(X86_FEATURE_VMX),
63 {}
64};
65MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
66
476bc001 67static bool __read_mostly enable_vpid = 1;
736caefe 68module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 69
476bc001 70static bool __read_mostly flexpriority_enabled = 1;
736caefe 71module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 72
476bc001 73static bool __read_mostly enable_ept = 1;
736caefe 74module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 75
476bc001 76static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 77module_param_named(unrestricted_guest,
78 enable_unrestricted_guest, bool, S_IRUGO);
79
83c3a331
XH		 80static bool __read_mostly enable_ept_ad_bits = 1;
81module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
82
a27685c3 83static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 84module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 85
476bc001 86static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 87module_param(vmm_exclusive, bool, S_IRUGO);
88
476bc001 89static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 90module_param(fasteoi, bool, S_IRUGO);
91
5a71785d 92static bool __read_mostly enable_apicv = 1;
01e439be 93module_param(enable_apicv, bool, S_IRUGO);
83d4c286 94
abc4fc58
AG		 95static bool __read_mostly enable_shadow_vmcs = 1;
96module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 97/*
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
101 */
476bc001 102static bool __read_mostly nested = 0;
801d3424
NHE		 103module_param(nested, bool, S_IRUGO);
104
20300099
WL		 105static u64 __read_mostly host_xss;
106
843e4330
KH		 107static bool __read_mostly enable_pml = 1;
108module_param_named(pml, enable_pml, bool, S_IRUGO);
109
5037878e
GN		 110#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
111#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 112#define KVM_VM_CR0_ALWAYS_ON \
113 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 114#define KVM_CR4_GUEST_OWNED_BITS \
115 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 116 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 117
cdc0e244
AK		 118#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
119#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
120
78ac8b47
AK		 121#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
122
f4124500
JK		 123#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
124
4b8d54f9
ZE		 125/*
126 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
127 * ple_gap: upper bound on the amount of time between two successive
128 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 129 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 130 * ple_window: upper bound on the amount of time a guest is allowed to execute
131 * in a PAUSE loop. Tests indicate that most spinlocks are held for
132 * less than 2^12 cycles
133 * Time is measured based on a counter that runs at the same rate as the TSC,
134 * refer SDM volume 3b section 21.6.13 & 22.1.3.
135 */
b4a2d31d
RK		 136#define KVM_VMX_DEFAULT_PLE_GAP 128
137#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
138#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
139#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
140#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
141 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
142
4b8d54f9
ZE		 143static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
144module_param(ple_gap, int, S_IRUGO);
145
146static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
147module_param(ple_window, int, S_IRUGO);
148
b4a2d31d
RK		 149/* Default doubles per-vcpu window every exit. */
150static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
151module_param(ple_window_grow, int, S_IRUGO);
152
153/* Default resets per-vcpu window every exit to ple_window. */
154static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
155module_param(ple_window_shrink, int, S_IRUGO);
156
157/* Default is to compute the maximum so we can never overflow. */
158static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
159static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
160module_param(ple_window_max, int, S_IRUGO);
161
83287ea4
AK		 162extern const ulong vmx_return;
163
8bf00a52 164#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 165#define VMCS02_POOL_SIZE 1
61d2ef2c 166
a2fa3e9f
GH		 167struct vmcs {
168 u32 revision_id;
169 u32 abort;
170 char data[0];
171};
172
d462b819
NHE		 173/*
174 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
175 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
176 * loaded on this CPU (so we can clear them if the CPU goes down).
177 */
178struct loaded_vmcs {
179 struct vmcs *vmcs;
180 int cpu;
181 int launched;
182 struct list_head loaded_vmcss_on_cpu_link;
183};
184
26bb0981
AK		 185struct shared_msr_entry {
186 unsigned index;
187 u64 data;
d5696725 188 u64 mask;
26bb0981
AK		 189};
190
a9d30f33
NHE		 191/*
192 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
193 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
194 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
195 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
196 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
197 * More than one of these structures may exist, if L1 runs multiple L2 guests.
198 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
199 * underlying hardware which will be used to run L2.
200 * This structure is packed to ensure that its layout is identical across
201 * machines (necessary for live migration).
202 * If there are changes in this struct, VMCS12_REVISION must be changed.
203 */
22bd0358 204typedef u64 natural_width;
a9d30f33
NHE		 205struct __packed vmcs12 {
206 /* According to the Intel spec, a VMCS region must start with the
207 * following two fields. Then follow implementation-specific data.
208 */
209 u32 revision_id;
210 u32 abort;
22bd0358 211
27d6c865
NHE		 212 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
213 u32 padding[7]; /* room for future expansion */
214
22bd0358
NHE		 215 u64 io_bitmap_a;
216 u64 io_bitmap_b;
217 u64 msr_bitmap;
218 u64 vm_exit_msr_store_addr;
219 u64 vm_exit_msr_load_addr;
220 u64 vm_entry_msr_load_addr;
221 u64 tsc_offset;
222 u64 virtual_apic_page_addr;
223 u64 apic_access_addr;
705699a1 224 u64 posted_intr_desc_addr;
22bd0358 225 u64 ept_pointer;
608406e2
WV		 226 u64 eoi_exit_bitmap0;
227 u64 eoi_exit_bitmap1;
228 u64 eoi_exit_bitmap2;
229 u64 eoi_exit_bitmap3;
81dc01f7 230 u64 xss_exit_bitmap;
22bd0358
NHE		 231 u64 guest_physical_address;
232 u64 vmcs_link_pointer;
233 u64 guest_ia32_debugctl;
234 u64 guest_ia32_pat;
235 u64 guest_ia32_efer;
236 u64 guest_ia32_perf_global_ctrl;
237 u64 guest_pdptr0;
238 u64 guest_pdptr1;
239 u64 guest_pdptr2;
240 u64 guest_pdptr3;
36be0b9d 241 u64 guest_bndcfgs;
22bd0358
NHE		 242 u64 host_ia32_pat;
243 u64 host_ia32_efer;
244 u64 host_ia32_perf_global_ctrl;
245 u64 padding64[8]; /* room for future expansion */
246 /*
247 * To allow migration of L1 (complete with its L2 guests) between
248 * machines of different natural widths (32 or 64 bit), we cannot have
249 * unsigned long fields with no explict size. We use u64 (aliased
250 * natural_width) instead. Luckily, x86 is little-endian.
251 */
252 natural_width cr0_guest_host_mask;
253 natural_width cr4_guest_host_mask;
254 natural_width cr0_read_shadow;
255 natural_width cr4_read_shadow;
256 natural_width cr3_target_value0;
257 natural_width cr3_target_value1;
258 natural_width cr3_target_value2;
259 natural_width cr3_target_value3;
260 natural_width exit_qualification;
261 natural_width guest_linear_address;
262 natural_width guest_cr0;
263 natural_width guest_cr3;
264 natural_width guest_cr4;
265 natural_width guest_es_base;
266 natural_width guest_cs_base;
267 natural_width guest_ss_base;
268 natural_width guest_ds_base;
269 natural_width guest_fs_base;
270 natural_width guest_gs_base;
271 natural_width guest_ldtr_base;
272 natural_width guest_tr_base;
273 natural_width guest_gdtr_base;
274 natural_width guest_idtr_base;
275 natural_width guest_dr7;
276 natural_width guest_rsp;
277 natural_width guest_rip;
278 natural_width guest_rflags;
279 natural_width guest_pending_dbg_exceptions;
280 natural_width guest_sysenter_esp;
281 natural_width guest_sysenter_eip;
282 natural_width host_cr0;
283 natural_width host_cr3;
284 natural_width host_cr4;
285 natural_width host_fs_base;
286 natural_width host_gs_base;
287 natural_width host_tr_base;
288 natural_width host_gdtr_base;
289 natural_width host_idtr_base;
290 natural_width host_ia32_sysenter_esp;
291 natural_width host_ia32_sysenter_eip;
292 natural_width host_rsp;
293 natural_width host_rip;
294 natural_width paddingl[8]; /* room for future expansion */
295 u32 pin_based_vm_exec_control;
296 u32 cpu_based_vm_exec_control;
297 u32 exception_bitmap;
298 u32 page_fault_error_code_mask;
299 u32 page_fault_error_code_match;
300 u32 cr3_target_count;
301 u32 vm_exit_controls;
302 u32 vm_exit_msr_store_count;
303 u32 vm_exit_msr_load_count;
304 u32 vm_entry_controls;
305 u32 vm_entry_msr_load_count;
306 u32 vm_entry_intr_info_field;
307 u32 vm_entry_exception_error_code;
308 u32 vm_entry_instruction_len;
309 u32 tpr_threshold;
310 u32 secondary_vm_exec_control;
311 u32 vm_instruction_error;
312 u32 vm_exit_reason;
313 u32 vm_exit_intr_info;
314 u32 vm_exit_intr_error_code;
315 u32 idt_vectoring_info_field;
316 u32 idt_vectoring_error_code;
317 u32 vm_exit_instruction_len;
318 u32 vmx_instruction_info;
319 u32 guest_es_limit;
320 u32 guest_cs_limit;
321 u32 guest_ss_limit;
322 u32 guest_ds_limit;
323 u32 guest_fs_limit;
324 u32 guest_gs_limit;
325 u32 guest_ldtr_limit;
326 u32 guest_tr_limit;
327 u32 guest_gdtr_limit;
328 u32 guest_idtr_limit;
329 u32 guest_es_ar_bytes;
330 u32 guest_cs_ar_bytes;
331 u32 guest_ss_ar_bytes;
332 u32 guest_ds_ar_bytes;
333 u32 guest_fs_ar_bytes;
334 u32 guest_gs_ar_bytes;
335 u32 guest_ldtr_ar_bytes;
336 u32 guest_tr_ar_bytes;
337 u32 guest_interruptibility_info;
338 u32 guest_activity_state;
339 u32 guest_sysenter_cs;
340 u32 host_ia32_sysenter_cs;
0238ea91
JK		 341 u32 vmx_preemption_timer_value;
342 u32 padding32[7]; /* room for future expansion */
22bd0358 343 u16 virtual_processor_id;
705699a1 344 u16 posted_intr_nv;
22bd0358
NHE		 345 u16 guest_es_selector;
346 u16 guest_cs_selector;
347 u16 guest_ss_selector;
348 u16 guest_ds_selector;
349 u16 guest_fs_selector;
350 u16 guest_gs_selector;
351 u16 guest_ldtr_selector;
352 u16 guest_tr_selector;
608406e2 353 u16 guest_intr_status;
22bd0358
NHE		 354 u16 host_es_selector;
355 u16 host_cs_selector;
356 u16 host_ss_selector;
357 u16 host_ds_selector;
358 u16 host_fs_selector;
359 u16 host_gs_selector;
360 u16 host_tr_selector;
a9d30f33
NHE		 361};
362
363/*
364 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
365 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
366 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
367 */
368#define VMCS12_REVISION 0x11e57ed0
369
370/*
371 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
372 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
373 * current implementation, 4K are reserved to avoid future complications.
374 */
375#define VMCS12_SIZE 0x1000
376
ff2f6fe9
NHE		 377/* Used to remember the last vmcs02 used for some recently used vmcs12s */
378struct vmcs02_list {
379 struct list_head list;
380 gpa_t vmptr;
381 struct loaded_vmcs vmcs02;
382};
383
ec378aee
NHE		 384/*
385 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
386 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
387 */
388struct nested_vmx {
389 /* Has the level1 guest done vmxon? */
390 bool vmxon;
3573e22c 391 gpa_t vmxon_ptr;
a9d30f33
NHE		 392
393 /* The guest-physical address of the current VMCS L1 keeps for L2 */
394 gpa_t current_vmptr;
395 /* The host-usable pointer to the above */
396 struct page *current_vmcs12_page;
397 struct vmcs12 *current_vmcs12;
8de48833 398 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 399 /*
400 * Indicates if the shadow vmcs must be updated with the
401 * data hold by vmcs12
402 */
403 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 404
405 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
406 struct list_head vmcs02_pool;
407 int vmcs02_num;
fe3ef05c 408 u64 vmcs01_tsc_offset;
644d711a
NHE		 409 /* L2 must run next, and mustn't decide to exit to L1. */
410 bool nested_run_pending;
fe3ef05c
NHE		 411 /*
412 * Guest pages referred to in vmcs02 with host-physical pointers, so
413 * we must keep them pinned while L2 runs.
414 */
415 struct page *apic_access_page;
a7c0b07d 416 struct page *virtual_apic_page;
705699a1
WV		 417 struct page *pi_desc_page;
418 struct pi_desc *pi_desc;
419 bool pi_pending;
420 u16 posted_intr_nv;
b3897a49 421 u64 msr_ia32_feature_control;
f4124500
JK		 422
423 struct hrtimer preemption_timer;
424 bool preemption_timer_expired;
2996fca0
JK		 425
426 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
427 u64 vmcs01_debugctl;
b9c237bb
WV		 428
429 u32 nested_vmx_procbased_ctls_low;
430 u32 nested_vmx_procbased_ctls_high;
431 u32 nested_vmx_true_procbased_ctls_low;
432 u32 nested_vmx_secondary_ctls_low;
433 u32 nested_vmx_secondary_ctls_high;
434 u32 nested_vmx_pinbased_ctls_low;
435 u32 nested_vmx_pinbased_ctls_high;
436 u32 nested_vmx_exit_ctls_low;
437 u32 nested_vmx_exit_ctls_high;
438 u32 nested_vmx_true_exit_ctls_low;
439 u32 nested_vmx_entry_ctls_low;
440 u32 nested_vmx_entry_ctls_high;
441 u32 nested_vmx_true_entry_ctls_low;
442 u32 nested_vmx_misc_low;
443 u32 nested_vmx_misc_high;
444 u32 nested_vmx_ept_caps;
ec378aee
NHE		 445};
446
01e439be 447#define POSTED_INTR_ON 0
ebbfc765
FW		 448#define POSTED_INTR_SN 1
449
01e439be
YZ		 450/* Posted-Interrupt Descriptor */
451struct pi_desc {
452 u32 pir[8]; /* Posted interrupt requested */
6ef1522f
FW		 453 union {
454 struct {
455 /* bit 256 - Outstanding Notification */
456 u16 on : 1,
457 /* bit 257 - Suppress Notification */
458 sn : 1,
459 /* bit 271:258 - Reserved */
460 rsvd_1 : 14;
461 /* bit 279:272 - Notification Vector */
462 u8 nv;
463 /* bit 287:280 - Reserved */
464 u8 rsvd_2;
465 /* bit 319:288 - Notification Destination */
466 u32 ndst;
467 };
468 u64 control;
469 };
470 u32 rsvd[6];
01e439be
YZ		 471} __aligned(64);
472
a20ed54d
YZ		 473static bool pi_test_and_set_on(struct pi_desc *pi_desc)
474{
475 return test_and_set_bit(POSTED_INTR_ON,
476 (unsigned long *)&pi_desc->control);
477}
478
479static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
480{
481 return test_and_clear_bit(POSTED_INTR_ON,
482 (unsigned long *)&pi_desc->control);
483}
484
485static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
486{
487 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
488}
489
ebbfc765
FW		 490static inline void pi_clear_sn(struct pi_desc *pi_desc)
491{
492 return clear_bit(POSTED_INTR_SN,
493 (unsigned long *)&pi_desc->control);
494}
495
496static inline void pi_set_sn(struct pi_desc *pi_desc)
497{
498 return set_bit(POSTED_INTR_SN,
499 (unsigned long *)&pi_desc->control);
500}
501
502static inline int pi_test_on(struct pi_desc *pi_desc)
503{
504 return test_bit(POSTED_INTR_ON,
505 (unsigned long *)&pi_desc->control);
506}
507
508static inline int pi_test_sn(struct pi_desc *pi_desc)
509{
510 return test_bit(POSTED_INTR_SN,
511 (unsigned long *)&pi_desc->control);
512}
513
a2fa3e9f 514struct vcpu_vmx {
fb3f0f51 515 struct kvm_vcpu vcpu;
313dbd49 516 unsigned long host_rsp;
29bd8a78 517 u8 fail;
9d58b931 518 bool nmi_known_unmasked;
51aa01d1 519 u32 exit_intr_info;
1155f76a 520 u32 idt_vectoring_info;
6de12732 521 ulong rflags;
26bb0981 522 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 523 int nmsrs;
524 int save_nmsrs;
a547c6db 525 unsigned long host_idt_base;
a2fa3e9f 526#ifdef CONFIG_X86_64
44ea2b17
AK		 527 u64 msr_host_kernel_gs_base;
528 u64 msr_guest_kernel_gs_base;
a2fa3e9f 529#endif
2961e876
GN		 530 u32 vm_entry_controls_shadow;
531 u32 vm_exit_controls_shadow;
d462b819
NHE		 532 /*
533 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
534 * non-nested (L1) guest, it always points to vmcs01. For a nested
535 * guest (L2), it points to a different VMCS.
536 */
537 struct loaded_vmcs vmcs01;
538 struct loaded_vmcs *loaded_vmcs;
539 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 540 struct msr_autoload {
541 unsigned nr;
542 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
543 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
544 } msr_autoload;
a2fa3e9f
GH		 545 struct {
546 int loaded;
547 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 548#ifdef CONFIG_X86_64
549 u16 ds_sel, es_sel;
550#endif
152d3f2f
LV		 551 int gs_ldt_reload_needed;
552 int fs_reload_needed;
da8999d3 553 u64 msr_host_bndcfgs;
d974baa3 554 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 555 } host_state;
9c8cba37 556 struct {
7ffd92c5 557 int vm86_active;
78ac8b47 558 ulong save_rflags;
f5f7b2fe
AK		 559 struct kvm_segment segs[8];
560 } rmode;
561 struct {
562 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 563 struct kvm_save_segment {
564 u16 selector;
565 unsigned long base;
566 u32 limit;
567 u32 ar;
f5f7b2fe 568 } seg[8];
2fb92db1 569 } segment_cache;
2384d2b3 570 int vpid;
04fa4d32 571 bool emulation_required;
3b86cd99
JK		 572
573 /* Support for vnmi-less CPUs */
574 int soft_vnmi_blocked;
575 ktime_t entry_time;
576 s64 vnmi_blocked_time;
a0861c02 577 u32 exit_reason;
4e47c7a6 578
01e439be
YZ		 579 /* Posted interrupt descriptor */
580 struct pi_desc pi_desc;
581
ec378aee
NHE		 582 /* Support for a guest hypervisor (nested VMX) */
583 struct nested_vmx nested;
a7653ecd
RK		 584
585 /* Dynamic PLE window. */
586 int ple_window;
587 bool ple_window_dirty;
843e4330
KH		 588
589 /* Support for PML */
590#define PML_ENTITY_NUM 512
591 struct page *pml_pg;
a2fa3e9f
GH		 592};
593
2fb92db1
AK		 594enum segment_cache_field {
595 SEG_FIELD_SEL = 0,
596 SEG_FIELD_BASE = 1,
597 SEG_FIELD_LIMIT = 2,
598 SEG_FIELD_AR = 3,
599
600 SEG_FIELD_NR = 4
601};
602
a2fa3e9f
GH		 603static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
604{
fb3f0f51 605 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 606}
607
efc64404
FW		 608static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
609{
610 return &(to_vmx(vcpu)->pi_desc);
611}
612
22bd0358
NHE		 613#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
614#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
615#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
616 [number##_HIGH] = VMCS12_OFFSET(name)+4
617
4607c2d7 618
fe2b201b 619static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 620 /*
621 * We do NOT shadow fields that are modified when L0
622 * traps and emulates any vmx instruction (e.g. VMPTRLD,
623 * VMXON...) executed by L1.
624 * For example, VM_INSTRUCTION_ERROR is read
625 * by L1 if a vmx instruction fails (part of the error path).
626 * Note the code assumes this logic. If for some reason
627 * we start shadowing these fields then we need to
628 * force a shadow sync when L0 emulates vmx instructions
629 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
630 * by nested_vmx_failValid)
631 */
632 VM_EXIT_REASON,
633 VM_EXIT_INTR_INFO,
634 VM_EXIT_INSTRUCTION_LEN,
635 IDT_VECTORING_INFO_FIELD,
636 IDT_VECTORING_ERROR_CODE,
637 VM_EXIT_INTR_ERROR_CODE,
638 EXIT_QUALIFICATION,
639 GUEST_LINEAR_ADDRESS,
640 GUEST_PHYSICAL_ADDRESS
641};
fe2b201b 642static int max_shadow_read_only_fields =
4607c2d7
AG		 643 ARRAY_SIZE(shadow_read_only_fields);
644
fe2b201b 645static unsigned long shadow_read_write_fields[] = {
a7c0b07d 646 TPR_THRESHOLD,
4607c2d7
AG		 647 GUEST_RIP,
648 GUEST_RSP,
649 GUEST_CR0,
650 GUEST_CR3,
651 GUEST_CR4,
652 GUEST_INTERRUPTIBILITY_INFO,
653 GUEST_RFLAGS,
654 GUEST_CS_SELECTOR,
655 GUEST_CS_AR_BYTES,
656 GUEST_CS_LIMIT,
657 GUEST_CS_BASE,
658 GUEST_ES_BASE,
36be0b9d 659 GUEST_BNDCFGS,
4607c2d7
AG		 660 CR0_GUEST_HOST_MASK,
661 CR0_READ_SHADOW,
662 CR4_READ_SHADOW,
663 TSC_OFFSET,
664 EXCEPTION_BITMAP,
665 CPU_BASED_VM_EXEC_CONTROL,
666 VM_ENTRY_EXCEPTION_ERROR_CODE,
667 VM_ENTRY_INTR_INFO_FIELD,
668 VM_ENTRY_INSTRUCTION_LEN,
669 VM_ENTRY_EXCEPTION_ERROR_CODE,
670 HOST_FS_BASE,
671 HOST_GS_BASE,
672 HOST_FS_SELECTOR,
673 HOST_GS_SELECTOR
674};
fe2b201b 675static int max_shadow_read_write_fields =
4607c2d7
AG		 676 ARRAY_SIZE(shadow_read_write_fields);
677
772e0318 678static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 679 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 680 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE		 681 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
682 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
683 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
684 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
685 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
686 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
687 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
688 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 689 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 690 FIELD(HOST_ES_SELECTOR, host_es_selector),
691 FIELD(HOST_CS_SELECTOR, host_cs_selector),
692 FIELD(HOST_SS_SELECTOR, host_ss_selector),
693 FIELD(HOST_DS_SELECTOR, host_ds_selector),
694 FIELD(HOST_FS_SELECTOR, host_fs_selector),
695 FIELD(HOST_GS_SELECTOR, host_gs_selector),
696 FIELD(HOST_TR_SELECTOR, host_tr_selector),
697 FIELD64(IO_BITMAP_A, io_bitmap_a),
698 FIELD64(IO_BITMAP_B, io_bitmap_b),
699 FIELD64(MSR_BITMAP, msr_bitmap),
700 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
701 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
702 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
703 FIELD64(TSC_OFFSET, tsc_offset),
704 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
705 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 706 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 707 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 708 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
709 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
710 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
711 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 712 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 713 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
714 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
715 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
716 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
717 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
718 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
719 FIELD64(GUEST_PDPTR0, guest_pdptr0),
720 FIELD64(GUEST_PDPTR1, guest_pdptr1),
721 FIELD64(GUEST_PDPTR2, guest_pdptr2),
722 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 723 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 724 FIELD64(HOST_IA32_PAT, host_ia32_pat),
725 FIELD64(HOST_IA32_EFER, host_ia32_efer),
726 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
727 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
728 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
729 FIELD(EXCEPTION_BITMAP, exception_bitmap),
730 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
731 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
732 FIELD(CR3_TARGET_COUNT, cr3_target_count),
733 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
734 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
735 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
736 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
737 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
738 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
739 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
740 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
741 FIELD(TPR_THRESHOLD, tpr_threshold),
742 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
743 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
744 FIELD(VM_EXIT_REASON, vm_exit_reason),
745 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
746 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
747 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
748 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
749 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
750 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
751 FIELD(GUEST_ES_LIMIT, guest_es_limit),
752 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
753 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
754 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
755 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
756 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
757 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
758 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
759 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
760 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
761 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
762 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
763 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
764 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
765 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
766 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
767 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
768 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
769 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
770 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
771 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
772 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 773 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 774 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
775 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
776 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
777 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
778 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
779 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
780 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
781 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
782 FIELD(EXIT_QUALIFICATION, exit_qualification),
783 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
784 FIELD(GUEST_CR0, guest_cr0),
785 FIELD(GUEST_CR3, guest_cr3),
786 FIELD(GUEST_CR4, guest_cr4),
787 FIELD(GUEST_ES_BASE, guest_es_base),
788 FIELD(GUEST_CS_BASE, guest_cs_base),
789 FIELD(GUEST_SS_BASE, guest_ss_base),
790 FIELD(GUEST_DS_BASE, guest_ds_base),
791 FIELD(GUEST_FS_BASE, guest_fs_base),
792 FIELD(GUEST_GS_BASE, guest_gs_base),
793 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
794 FIELD(GUEST_TR_BASE, guest_tr_base),
795 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
796 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
797 FIELD(GUEST_DR7, guest_dr7),
798 FIELD(GUEST_RSP, guest_rsp),
799 FIELD(GUEST_RIP, guest_rip),
800 FIELD(GUEST_RFLAGS, guest_rflags),
801 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
802 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
803 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
804 FIELD(HOST_CR0, host_cr0),
805 FIELD(HOST_CR3, host_cr3),
806 FIELD(HOST_CR4, host_cr4),
807 FIELD(HOST_FS_BASE, host_fs_base),
808 FIELD(HOST_GS_BASE, host_gs_base),
809 FIELD(HOST_TR_BASE, host_tr_base),
810 FIELD(HOST_GDTR_BASE, host_gdtr_base),
811 FIELD(HOST_IDTR_BASE, host_idtr_base),
812 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
813 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
814 FIELD(HOST_RSP, host_rsp),
815 FIELD(HOST_RIP, host_rip),
816};
22bd0358
NHE		 817
818static inline short vmcs_field_to_offset(unsigned long field)
819{
a2ae9df7
PB		 820 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
821
822 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
823 vmcs_field_to_offset_table[field] == 0)
824 return -ENOENT;
825
22bd0358
NHE		 826 return vmcs_field_to_offset_table[field];
827}
828
a9d30f33
NHE		 829static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
830{
831 return to_vmx(vcpu)->nested.current_vmcs12;
832}
833
834static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
835{
54bf36aa 836 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 837 if (is_error_page(page))
a9d30f33 838 return NULL;
32cad84f 839
a9d30f33
NHE		 840 return page;
841}
842
843static void nested_release_page(struct page *page)
844{
845 kvm_release_page_dirty(page);
846}
847
848static void nested_release_page_clean(struct page *page)
849{
850 kvm_release_page_clean(page);
851}
852
bfd0a56b 853static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 854static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 855static void kvm_cpu_vmxon(u64 addr);
856static void kvm_cpu_vmxoff(void);
93c4adc7 857static bool vmx_mpx_supported(void);
f53cd63c 858static bool vmx_xsaves_supported(void);
d50ab6c1 859static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
776e58ea 860static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 861static void vmx_set_segment(struct kvm_vcpu *vcpu,
862 struct kvm_segment *var, int seg);
863static void vmx_get_segment(struct kvm_vcpu *vcpu,
864 struct kvm_segment *var, int seg);
d99e4152
GN		 865static bool guest_state_valid(struct kvm_vcpu *vcpu);
866static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 867static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 868static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 869static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 870static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 871
6aa8b732
AK		 872static DEFINE_PER_CPU(struct vmcs *, vmxarea);
873static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 874/*
875 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
876 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
877 */
878static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 879static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 880
3e7c73e9
AK		 881static unsigned long *vmx_io_bitmap_a;
882static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 883static unsigned long *vmx_msr_bitmap_legacy;
884static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 885static unsigned long *vmx_msr_bitmap_legacy_x2apic;
886static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 887static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 888static unsigned long *vmx_vmread_bitmap;
889static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 890
110312c8 891static bool cpu_has_load_ia32_efer;
8bf00a52 892static bool cpu_has_load_perf_global_ctrl;
110312c8 893
2384d2b3
SY		 894static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
895static DEFINE_SPINLOCK(vmx_vpid_lock);
896
1c3d14fe 897static struct vmcs_config {
6aa8b732
AK		 898 int size;
899 int order;
900 u32 revision_id;
1c3d14fe
YS		 901 u32 pin_based_exec_ctrl;
902 u32 cpu_based_exec_ctrl;
f78e0e2e 903 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 904 u32 vmexit_ctrl;
905 u32 vmentry_ctrl;
906} vmcs_config;
6aa8b732 907
efff9e53 908static struct vmx_capability {
d56f546d
SY		 909 u32 ept;
910 u32 vpid;
911} vmx_capability;
912
6aa8b732
AK		 913#define VMX_SEGMENT_FIELD(seg) \
914 [VCPU_SREG_##seg] = { \
915 .selector = GUEST_##seg##_SELECTOR, \
916 .base = GUEST_##seg##_BASE, \
917 .limit = GUEST_##seg##_LIMIT, \
918 .ar_bytes = GUEST_##seg##_AR_BYTES, \
919 }
920
772e0318 921static const struct kvm_vmx_segment_field {
6aa8b732
AK		 922 unsigned selector;
923 unsigned base;
924 unsigned limit;
925 unsigned ar_bytes;
926} kvm_vmx_segment_fields[] = {
927 VMX_SEGMENT_FIELD(CS),
928 VMX_SEGMENT_FIELD(DS),
929 VMX_SEGMENT_FIELD(ES),
930 VMX_SEGMENT_FIELD(FS),
931 VMX_SEGMENT_FIELD(GS),
932 VMX_SEGMENT_FIELD(SS),
933 VMX_SEGMENT_FIELD(TR),
934 VMX_SEGMENT_FIELD(LDTR),
935};
936
26bb0981
AK		 937static u64 host_efer;
938
6de4f3ad
AK		 939static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
940
4d56c8a7 941/*
8c06585d 942 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 943 * away by decrementing the array size.
944 */
6aa8b732 945static const u32 vmx_msr_index[] = {
05b3e0c2 946#ifdef CONFIG_X86_64
44ea2b17 947 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 948#endif
8c06585d 949 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 950};
6aa8b732 951
31299944 952static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 953{
954 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
955 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 956 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 957}
958
31299944 959static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 960{
961 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
962 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 963 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 964}
965
31299944 966static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 967{
968 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
969 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 970 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 971}
972
31299944 973static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 974{
975 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
976 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
977}
978
31299944 979static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 980{
981 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
982 INTR_INFO_VALID_MASK)) ==
983 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
984}
985
31299944 986static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 987{
04547156 988 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 989}
990
31299944 991static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 992{
04547156 993 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 994}
995
35754c98 996static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 997{
35754c98 998 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS		 999}
1000
31299944 1001static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 1002{
04547156
SY		 1003 return vmcs_config.cpu_based_exec_ctrl &
1004 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 1005}
1006
774ead3a 1007static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 1008{
04547156
SY		 1009 return vmcs_config.cpu_based_2nd_exec_ctrl &
1010 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1011}
1012
8d14695f
YZ		 1013static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1014{
1015 return vmcs_config.cpu_based_2nd_exec_ctrl &
1016 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1017}
1018
83d4c286
YZ		 1019static inline bool cpu_has_vmx_apic_register_virt(void)
1020{
1021 return vmcs_config.cpu_based_2nd_exec_ctrl &
1022 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1023}
1024
c7c9c56c
YZ		 1025static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1026{
1027 return vmcs_config.cpu_based_2nd_exec_ctrl &
1028 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1029}
1030
01e439be
YZ		 1031static inline bool cpu_has_vmx_posted_intr(void)
1032{
d6a858d1
PB		 1033 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1034 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ		 1035}
1036
1037static inline bool cpu_has_vmx_apicv(void)
1038{
1039 return cpu_has_vmx_apic_register_virt() &&
1040 cpu_has_vmx_virtual_intr_delivery() &&
1041 cpu_has_vmx_posted_intr();
1042}
1043
04547156
SY		 1044static inline bool cpu_has_vmx_flexpriority(void)
1045{
1046 return cpu_has_vmx_tpr_shadow() &&
1047 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 1048}
1049
e799794e
MT		 1050static inline bool cpu_has_vmx_ept_execute_only(void)
1051{
31299944 1052 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 1053}
1054
e799794e
MT		 1055static inline bool cpu_has_vmx_ept_2m_page(void)
1056{
31299944 1057 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1058}
1059
878403b7
SY		 1060static inline bool cpu_has_vmx_ept_1g_page(void)
1061{
31299944 1062 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1063}
1064
4bc9b982
SY		 1065static inline bool cpu_has_vmx_ept_4levels(void)
1066{
1067 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1068}
1069
83c3a331
XH		 1070static inline bool cpu_has_vmx_ept_ad_bits(void)
1071{
1072 return vmx_capability.ept & VMX_EPT_AD_BIT;
1073}
1074
31299944 1075static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1076{
31299944 1077 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1078}
1079
31299944 1080static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1081{
31299944 1082 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1083}
1084
518c8aee
GJ		 1085static inline bool cpu_has_vmx_invvpid_single(void)
1086{
1087 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1088}
1089
b9d762fa
GJ		 1090static inline bool cpu_has_vmx_invvpid_global(void)
1091{
1092 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1093}
1094
31299944 1095static inline bool cpu_has_vmx_ept(void)
d56f546d 1096{
04547156
SY		 1097 return vmcs_config.cpu_based_2nd_exec_ctrl &
1098 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1099}
1100
31299944 1101static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1102{
1103 return vmcs_config.cpu_based_2nd_exec_ctrl &
1104 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1105}
1106
31299944 1107static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1108{
1109 return vmcs_config.cpu_based_2nd_exec_ctrl &
1110 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1111}
1112
35754c98 1113static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1114{
35754c98 1115 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 1116}
1117
31299944 1118static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1119{
04547156
SY		 1120 return vmcs_config.cpu_based_2nd_exec_ctrl &
1121 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1122}
1123
31299944 1124static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1125{
1126 return vmcs_config.cpu_based_2nd_exec_ctrl &
1127 SECONDARY_EXEC_RDTSCP;
1128}
1129
ad756a16
MJ		 1130static inline bool cpu_has_vmx_invpcid(void)
1131{
1132 return vmcs_config.cpu_based_2nd_exec_ctrl &
1133 SECONDARY_EXEC_ENABLE_INVPCID;
1134}
1135
31299944 1136static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1137{
1138 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1139}
1140
f5f48ee1
SY		 1141static inline bool cpu_has_vmx_wbinvd_exit(void)
1142{
1143 return vmcs_config.cpu_based_2nd_exec_ctrl &
1144 SECONDARY_EXEC_WBINVD_EXITING;
1145}
1146
abc4fc58
AG		 1147static inline bool cpu_has_vmx_shadow_vmcs(void)
1148{
1149 u64 vmx_msr;
1150 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1151 /* check if the cpu supports writing r/o exit information fields */
1152 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1153 return false;
1154
1155 return vmcs_config.cpu_based_2nd_exec_ctrl &
1156 SECONDARY_EXEC_SHADOW_VMCS;
1157}
1158
843e4330
KH		 1159static inline bool cpu_has_vmx_pml(void)
1160{
1161 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1162}
1163
04547156
SY		 1164static inline bool report_flexpriority(void)
1165{
1166 return flexpriority_enabled;
1167}
1168
fe3ef05c
NHE		 1169static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1170{
1171 return vmcs12->cpu_based_vm_exec_control & bit;
1172}
1173
1174static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1175{
1176 return (vmcs12->cpu_based_vm_exec_control &
1177 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1178 (vmcs12->secondary_vm_exec_control & bit);
1179}
1180
f5c4368f 1181static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1182{
1183 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1184}
1185
f4124500
JK		 1186static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1187{
1188 return vmcs12->pin_based_vm_exec_control &
1189 PIN_BASED_VMX_PREEMPTION_TIMER;
1190}
1191
155a97a3
NHE		 1192static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1193{
1194 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1195}
1196
81dc01f7
WL		 1197static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1198{
1199 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1200 vmx_xsaves_supported();
1201}
1202
f2b93280
WV		 1203static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1204{
1205 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1206}
1207
82f0dd4b
WV		 1208static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1209{
1210 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1211}
1212
608406e2
WV		 1213static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1214{
1215 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1216}
1217
705699a1
WV		 1218static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1219{
1220 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1221}
1222
644d711a
NHE		 1223static inline bool is_exception(u32 intr_info)
1224{
1225 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1226 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1227}
1228
533558bc
JK		 1229static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1230 u32 exit_intr_info,
1231 unsigned long exit_qualification);
7c177938
NHE		 1232static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1233 struct vmcs12 *vmcs12,
1234 u32 reason, unsigned long qualification);
1235
8b9cf98c 1236static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1237{
1238 int i;
1239
a2fa3e9f 1240 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1241 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1242 return i;
1243 return -1;
1244}
1245
2384d2b3
SY		 1246static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1247{
1248 struct {
1249 u64 vpid : 16;
1250 u64 rsvd : 48;
1251 u64 gva;
1252 } operand = { vpid, 0, gva };
1253
4ecac3fd 1254 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1255 /* CF==1 or ZF==1 --> rc = -1 */
1256 "; ja 1f ; ud2 ; 1:"
1257 : : "a"(&operand), "c"(ext) : "cc", "memory");
1258}
1259
1439442c
SY		 1260static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1261{
1262 struct {
1263 u64 eptp, gpa;
1264 } operand = {eptp, gpa};
1265
4ecac3fd 1266 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1267 /* CF==1 or ZF==1 --> rc = -1 */
1268 "; ja 1f ; ud2 ; 1:\n"
1269 : : "a" (&operand), "c" (ext) : "cc", "memory");
1270}
1271
26bb0981 1272static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1273{
1274 int i;
1275
8b9cf98c 1276 i = __find_msr_index(vmx, msr);
a75beee6 1277 if (i >= 0)
a2fa3e9f 1278 return &vmx->guest_msrs[i];
8b6d44c7 1279 return NULL;
7725f0ba
AK		 1280}
1281
6aa8b732
AK		 1282static void vmcs_clear(struct vmcs *vmcs)
1283{
1284 u64 phys_addr = __pa(vmcs);
1285 u8 error;
1286
4ecac3fd 1287 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1288 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1289 : "cc", "memory");
1290 if (error)
1291 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1292 vmcs, phys_addr);
1293}
1294
d462b819
NHE		 1295static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1296{
1297 vmcs_clear(loaded_vmcs->vmcs);
1298 loaded_vmcs->cpu = -1;
1299 loaded_vmcs->launched = 0;
1300}
1301
7725b894
DX		 1302static void vmcs_load(struct vmcs *vmcs)
1303{
1304 u64 phys_addr = __pa(vmcs);
1305 u8 error;
1306
1307 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1308 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1309 : "cc", "memory");
1310 if (error)
2844d849 1311 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1312 vmcs, phys_addr);
1313}
1314
2965faa5 1315#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 1316/*
1317 * This bitmap is used to indicate whether the vmclear
1318 * operation is enabled on all cpus. All disabled by
1319 * default.
1320 */
1321static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1322
1323static inline void crash_enable_local_vmclear(int cpu)
1324{
1325 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1326}
1327
1328static inline void crash_disable_local_vmclear(int cpu)
1329{
1330 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1331}
1332
1333static inline int crash_local_vmclear_enabled(int cpu)
1334{
1335 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1336}
1337
1338static void crash_vmclear_local_loaded_vmcss(void)
1339{
1340 int cpu = raw_smp_processor_id();
1341 struct loaded_vmcs *v;
1342
1343 if (!crash_local_vmclear_enabled(cpu))
1344 return;
1345
1346 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1347 loaded_vmcss_on_cpu_link)
1348 vmcs_clear(v->vmcs);
1349}
1350#else
1351static inline void crash_enable_local_vmclear(int cpu) { }
1352static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1353#endif /* CONFIG_KEXEC_CORE */
8f536b76 1354
d462b819 1355static void __loaded_vmcs_clear(void *arg)
6aa8b732 1356{
d462b819 1357 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1358 int cpu = raw_smp_processor_id();
6aa8b732 1359
d462b819
NHE		 1360 if (loaded_vmcs->cpu != cpu)
1361 return; /* vcpu migration can race with cpu offline */
1362 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1363 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1364 crash_disable_local_vmclear(cpu);
d462b819 1365 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1366
1367 /*
1368 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1369 * is before setting loaded_vmcs->vcpu to -1 which is done in
1370 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1371 * then adds the vmcs into percpu list before it is deleted.
1372 */
1373 smp_wmb();
1374
d462b819 1375 loaded_vmcs_init(loaded_vmcs);
8f536b76 1376 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1377}
1378
d462b819 1379static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1380{
e6c7d321
XG		 1381 int cpu = loaded_vmcs->cpu;
1382
1383 if (cpu != -1)
1384 smp_call_function_single(cpu,
1385 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1386}
1387
1760dd49 1388static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1389{
1390 if (vmx->vpid == 0)
1391 return;
1392
518c8aee
GJ		 1393 if (cpu_has_vmx_invvpid_single())
1394 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1395}
1396
b9d762fa
GJ		 1397static inline void vpid_sync_vcpu_global(void)
1398{
1399 if (cpu_has_vmx_invvpid_global())
1400 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1401}
1402
1403static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1404{
1405 if (cpu_has_vmx_invvpid_single())
1760dd49 1406 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1407 else
1408 vpid_sync_vcpu_global();
1409}
1410
1439442c
SY		 1411static inline void ept_sync_global(void)
1412{
1413 if (cpu_has_vmx_invept_global())
1414 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1415}
1416
1417static inline void ept_sync_context(u64 eptp)
1418{
089d034e 1419 if (enable_ept) {
1439442c
SY		 1420 if (cpu_has_vmx_invept_context())
1421 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1422 else
1423 ept_sync_global();
1424 }
1425}
1426
96304217 1427static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1428{
5e520e62 1429 unsigned long value;
6aa8b732 1430
5e520e62
AK		 1431 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1432 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1433 return value;
1434}
1435
96304217 1436static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1437{
1438 return vmcs_readl(field);
1439}
1440
96304217 1441static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1442{
1443 return vmcs_readl(field);
1444}
1445
96304217 1446static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1447{
05b3e0c2 1448#ifdef CONFIG_X86_64
6aa8b732
AK		 1449 return vmcs_readl(field);
1450#else
1451 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1452#endif
1453}
1454
e52de1b8
AK		 1455static noinline void vmwrite_error(unsigned long field, unsigned long value)
1456{
1457 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1458 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1459 dump_stack();
1460}
1461
6aa8b732
AK		 1462static void vmcs_writel(unsigned long field, unsigned long value)
1463{
1464 u8 error;
1465
4ecac3fd 1466 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1467 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1468 if (unlikely(error))
1469 vmwrite_error(field, value);
6aa8b732
AK		 1470}
1471
1472static void vmcs_write16(unsigned long field, u16 value)
1473{
1474 vmcs_writel(field, value);
1475}
1476
1477static void vmcs_write32(unsigned long field, u32 value)
1478{
1479 vmcs_writel(field, value);
1480}
1481
1482static void vmcs_write64(unsigned long field, u64 value)
1483{
6aa8b732 1484 vmcs_writel(field, value);
7682f2d0 1485#ifndef CONFIG_X86_64
6aa8b732
AK		 1486 asm volatile ("");
1487 vmcs_writel(field+1, value >> 32);
1488#endif
1489}
1490
2ab455cc
AL		 1491static void vmcs_clear_bits(unsigned long field, u32 mask)
1492{
1493 vmcs_writel(field, vmcs_readl(field) & ~mask);
1494}
1495
1496static void vmcs_set_bits(unsigned long field, u32 mask)
1497{
1498 vmcs_writel(field, vmcs_readl(field) | mask);
1499}
1500
2961e876
GN		 1501static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1502{
1503 vmcs_write32(VM_ENTRY_CONTROLS, val);
1504 vmx->vm_entry_controls_shadow = val;
1505}
1506
1507static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1508{
1509 if (vmx->vm_entry_controls_shadow != val)
1510 vm_entry_controls_init(vmx, val);
1511}
1512
1513static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1514{
1515 return vmx->vm_entry_controls_shadow;
1516}
1517
1518
1519static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1520{
1521 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1522}
1523
1524static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1525{
1526 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1527}
1528
1529static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1530{
1531 vmcs_write32(VM_EXIT_CONTROLS, val);
1532 vmx->vm_exit_controls_shadow = val;
1533}
1534
1535static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1536{
1537 if (vmx->vm_exit_controls_shadow != val)
1538 vm_exit_controls_init(vmx, val);
1539}
1540
1541static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1542{
1543 return vmx->vm_exit_controls_shadow;
1544}
1545
1546
1547static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1548{
1549 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1550}
1551
1552static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1553{
1554 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1555}
1556
2fb92db1
AK		 1557static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1558{
1559 vmx->segment_cache.bitmask = 0;
1560}
1561
1562static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1563 unsigned field)
1564{
1565 bool ret;
1566 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1567
1568 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1569 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1570 vmx->segment_cache.bitmask = 0;
1571 }
1572 ret = vmx->segment_cache.bitmask & mask;
1573 vmx->segment_cache.bitmask |= mask;
1574 return ret;
1575}
1576
1577static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1578{
1579 u16 *p = &vmx->segment_cache.seg[seg].selector;
1580
1581 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1582 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1583 return *p;
1584}
1585
1586static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1587{
1588 ulong *p = &vmx->segment_cache.seg[seg].base;
1589
1590 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1591 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1592 return *p;
1593}
1594
1595static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1596{
1597 u32 *p = &vmx->segment_cache.seg[seg].limit;
1598
1599 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1600 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1601 return *p;
1602}
1603
1604static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1605{
1606 u32 *p = &vmx->segment_cache.seg[seg].ar;
1607
1608 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1609 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1610 return *p;
1611}
1612
abd3f2d6
AK		 1613static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1614{
1615 u32 eb;
1616
fd7373cc
JK		 1617 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1618 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1619 if ((vcpu->guest_debug &
1620 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1621 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1622 eb |= 1u << BP_VECTOR;
7ffd92c5 1623 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1624 eb = ~0;
089d034e 1625 if (enable_ept)
1439442c 1626 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1627 if (vcpu->fpu_active)
1628 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1629
1630 /* When we are running a nested L2 guest and L1 specified for it a
1631 * certain exception bitmap, we must trap the same exceptions and pass
1632 * them to L1. When running L2, we will only handle the exceptions
1633 * specified above if L1 did not want them.
1634 */
1635 if (is_guest_mode(vcpu))
1636 eb |= get_vmcs12(vcpu)->exception_bitmap;
1637
abd3f2d6
AK		 1638 vmcs_write32(EXCEPTION_BITMAP, eb);
1639}
1640
2961e876
GN		 1641static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1642 unsigned long entry, unsigned long exit)
8bf00a52 1643{
2961e876
GN		 1644 vm_entry_controls_clearbit(vmx, entry);
1645 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1646}
1647
61d2ef2c
AK		 1648static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1649{
1650 unsigned i;
1651 struct msr_autoload *m = &vmx->msr_autoload;
1652
8bf00a52
GN		 1653 switch (msr) {
1654 case MSR_EFER:
1655 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1656 clear_atomic_switch_msr_special(vmx,
1657 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1658 VM_EXIT_LOAD_IA32_EFER);
1659 return;
1660 }
1661 break;
1662 case MSR_CORE_PERF_GLOBAL_CTRL:
1663 if (cpu_has_load_perf_global_ctrl) {
2961e876 1664 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1665 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1666 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1667 return;
1668 }
1669 break;
110312c8
AK		 1670 }
1671
61d2ef2c
AK		 1672 for (i = 0; i < m->nr; ++i)
1673 if (m->guest[i].index == msr)
1674 break;
1675
1676 if (i == m->nr)
1677 return;
1678 --m->nr;
1679 m->guest[i] = m->guest[m->nr];
1680 m->host[i] = m->host[m->nr];
1681 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1682 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1683}
1684
2961e876
GN		 1685static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1686 unsigned long entry, unsigned long exit,
1687 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1688 u64 guest_val, u64 host_val)
8bf00a52
GN		 1689{
1690 vmcs_write64(guest_val_vmcs, guest_val);
1691 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1692 vm_entry_controls_setbit(vmx, entry);
1693 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1694}
1695
61d2ef2c
AK		 1696static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1697 u64 guest_val, u64 host_val)
1698{
1699 unsigned i;
1700 struct msr_autoload *m = &vmx->msr_autoload;
1701
8bf00a52
GN		 1702 switch (msr) {
1703 case MSR_EFER:
1704 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1705 add_atomic_switch_msr_special(vmx,
1706 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1707 VM_EXIT_LOAD_IA32_EFER,
1708 GUEST_IA32_EFER,
1709 HOST_IA32_EFER,
1710 guest_val, host_val);
1711 return;
1712 }
1713 break;
1714 case MSR_CORE_PERF_GLOBAL_CTRL:
1715 if (cpu_has_load_perf_global_ctrl) {
2961e876 1716 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1717 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1718 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1719 GUEST_IA32_PERF_GLOBAL_CTRL,
1720 HOST_IA32_PERF_GLOBAL_CTRL,
1721 guest_val, host_val);
1722 return;
1723 }
1724 break;
110312c8
AK		 1725 }
1726
61d2ef2c
AK		 1727 for (i = 0; i < m->nr; ++i)
1728 if (m->guest[i].index == msr)
1729 break;
1730
e7fc6f93 1731 if (i == NR_AUTOLOAD_MSRS) {
60266204 1732 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1733 "Can't add msr %x\n", msr);
1734 return;
1735 } else if (i == m->nr) {
61d2ef2c
AK		 1736 ++m->nr;
1737 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1738 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1739 }
1740
1741 m->guest[i].index = msr;
1742 m->guest[i].value = guest_val;
1743 m->host[i].index = msr;
1744 m->host[i].value = host_val;
1745}
1746
33ed6329
AK		 1747static void reload_tss(void)
1748{
33ed6329
AK		 1749 /*
1750 * VT restores TR but not its size. Useless.
1751 */
89cbc767 1752 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1753 struct desc_struct *descs;
33ed6329 1754
d359192f 1755 descs = (void *)gdt->address;
33ed6329
AK		 1756 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1757 load_TR_desc();
33ed6329
AK		 1758}
1759
92c0d900 1760static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1761{
3a34a881 1762 u64 guest_efer;
51c6cf66
AK		 1763 u64 ignore_bits;
1764
f6801dff 1765 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1766
51c6cf66 1767 /*
0fa06071 1768 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1769 * outside long mode
1770 */
1771 ignore_bits = EFER_NX | EFER_SCE;
1772#ifdef CONFIG_X86_64
1773 ignore_bits |= EFER_LMA | EFER_LME;
1774 /* SCE is meaningful only in long mode on Intel */
1775 if (guest_efer & EFER_LMA)
1776 ignore_bits &= ~(u64)EFER_SCE;
1777#endif
51c6cf66
AK		 1778 guest_efer &= ~ignore_bits;
1779 guest_efer |= host_efer & ignore_bits;
26bb0981 1780 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1781 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1782
1783 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1784
1785 /*
1786 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1787 * On CPUs that support "load IA32_EFER", always switch EFER
1788 * atomically, since it's faster than switching it manually.
1789 */
1790 if (cpu_has_load_ia32_efer ||
1791 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1792 guest_efer = vmx->vcpu.arch.efer;
1793 if (!(guest_efer & EFER_LMA))
1794 guest_efer &= ~EFER_LME;
54b98bff
AL		 1795 if (guest_efer != host_efer)
1796 add_atomic_switch_msr(vmx, MSR_EFER,
1797 guest_efer, host_efer);
84ad33ef
AK		 1798 return false;
1799 }
1800
26bb0981 1801 return true;
51c6cf66
AK		 1802}
1803
2d49ec72
GN		 1804static unsigned long segment_base(u16 selector)
1805{
89cbc767 1806 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1807 struct desc_struct *d;
1808 unsigned long table_base;
1809 unsigned long v;
1810
1811 if (!(selector & ~3))
1812 return 0;
1813
d359192f 1814 table_base = gdt->address;
2d49ec72
GN		 1815
1816 if (selector & 4) { /* from ldt */
1817 u16 ldt_selector = kvm_read_ldt();
1818
1819 if (!(ldt_selector & ~3))
1820 return 0;
1821
1822 table_base = segment_base(ldt_selector);
1823 }
1824 d = (struct desc_struct *)(table_base + (selector & ~7));
1825 v = get_desc_base(d);
1826#ifdef CONFIG_X86_64
1827 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1828 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1829#endif
1830 return v;
1831}
1832
1833static inline unsigned long kvm_read_tr_base(void)
1834{
1835 u16 tr;
1836 asm("str %0" : "=g"(tr));
1837 return segment_base(tr);
1838}
1839
04d2cc77 1840static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1841{
04d2cc77 1842 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1843 int i;
04d2cc77 1844
a2fa3e9f 1845 if (vmx->host_state.loaded)
33ed6329
AK		 1846 return;
1847
a2fa3e9f 1848 vmx->host_state.loaded = 1;
33ed6329
AK		 1849 /*
1850 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1851 * allow segment selectors with cpl > 0 or ti == 1.
1852 */
d6e88aec 1853 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1854 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1855 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1856 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1857 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1858 vmx->host_state.fs_reload_needed = 0;
1859 } else {
33ed6329 1860 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1861 vmx->host_state.fs_reload_needed = 1;
33ed6329 1862 }
9581d442 1863 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1864 if (!(vmx->host_state.gs_sel & 7))
1865 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1866 else {
1867 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1868 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1869 }
1870
b2da15ac
AK		 1871#ifdef CONFIG_X86_64
1872 savesegment(ds, vmx->host_state.ds_sel);
1873 savesegment(es, vmx->host_state.es_sel);
1874#endif
1875
33ed6329
AK		 1876#ifdef CONFIG_X86_64
1877 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1878 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1879#else
a2fa3e9f
GH		 1880 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1881 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1882#endif
707c0874
AK		 1883
1884#ifdef CONFIG_X86_64
c8770e7b
AK		 1885 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1886 if (is_long_mode(&vmx->vcpu))
44ea2b17 1887 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1888#endif
da8999d3
LJ		 1889 if (boot_cpu_has(X86_FEATURE_MPX))
1890 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1891 for (i = 0; i < vmx->save_nmsrs; ++i)
1892 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1893 vmx->guest_msrs[i].data,
1894 vmx->guest_msrs[i].mask);
33ed6329
AK		 1895}
1896
a9b21b62 1897static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1898{
a2fa3e9f 1899 if (!vmx->host_state.loaded)
33ed6329
AK		 1900 return;
1901
e1beb1d3 1902 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1903 vmx->host_state.loaded = 0;
c8770e7b
AK		 1904#ifdef CONFIG_X86_64
1905 if (is_long_mode(&vmx->vcpu))
1906 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1907#endif
152d3f2f 1908 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1909 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1910#ifdef CONFIG_X86_64
9581d442 1911 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1912#else
1913 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1914#endif
33ed6329 1915 }
0a77fe4c
AK		 1916 if (vmx->host_state.fs_reload_needed)
1917 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1918#ifdef CONFIG_X86_64
1919 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1920 loadsegment(ds, vmx->host_state.ds_sel);
1921 loadsegment(es, vmx->host_state.es_sel);
1922 }
b2da15ac 1923#endif
152d3f2f 1924 reload_tss();
44ea2b17 1925#ifdef CONFIG_X86_64
c8770e7b 1926 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1927#endif
da8999d3
LJ		 1928 if (vmx->host_state.msr_host_bndcfgs)
1929 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1930 /*
1931 * If the FPU is not active (through the host task or
1932 * the guest vcpu), then restore the cr0.TS bit.
1933 */
3c6dffa9 1934 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
b1a74bf8 1935 stts();
89cbc767 1936 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1937}
1938
a9b21b62
AK		 1939static void vmx_load_host_state(struct vcpu_vmx *vmx)
1940{
1941 preempt_disable();
1942 __vmx_load_host_state(vmx);
1943 preempt_enable();
1944}
1945
28b835d6
FW		 1946static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1947{
1948 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1949 struct pi_desc old, new;
1950 unsigned int dest;
1951
1952 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1953 !irq_remapping_cap(IRQ_POSTING_CAP))
1954 return;
1955
1956 do {
1957 old.control = new.control = pi_desc->control;
1958
1959 /*
1960 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
1961 * are two possible cases:
1962 * 1. After running 'pre_block', context switch
1963 * happened. For this case, 'sn' was set in
1964 * vmx_vcpu_put(), so we need to clear it here.
1965 * 2. After running 'pre_block', we were blocked,
1966 * and woken up by some other guy. For this case,
1967 * we don't need to do anything, 'pi_post_block'
1968 * will do everything for us. However, we cannot
1969 * check whether it is case #1 or case #2 here
1970 * (maybe, not needed), so we also clear sn here,
1971 * I think it is not a big deal.
1972 */
1973 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
1974 if (vcpu->cpu != cpu) {
1975 dest = cpu_physical_id(cpu);
1976
1977 if (x2apic_enabled())
1978 new.ndst = dest;
1979 else
1980 new.ndst = (dest << 8) & 0xFF00;
1981 }
1982
1983 /* set 'NV' to 'notification vector' */
1984 new.nv = POSTED_INTR_VECTOR;
1985 }
1986
1987 /* Allow posting non-urgent interrupts */
1988 new.sn = 0;
1989 } while (cmpxchg(&pi_desc->control, old.control,
1990 new.control) != old.control);
1991}
6aa8b732
AK		 1992/*
1993 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1994 * vcpu mutex is already taken.
1995 */
15ad7146 1996static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1997{
a2fa3e9f 1998 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1999 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 2000
4610c9cc
DX		 2001 if (!vmm_exclusive)
2002 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 2003 else if (vmx->loaded_vmcs->cpu != cpu)
2004 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 2005
d462b819
NHE		 2006 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2007 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2008 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 2009 }
2010
d462b819 2011 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 2012 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 2013 unsigned long sysenter_esp;
2014
a8eeb04a 2015 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 2016 local_irq_disable();
8f536b76 2017 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 2018
2019 /*
2020 * Read loaded_vmcs->cpu should be before fetching
2021 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2022 * See the comments in __loaded_vmcs_clear().
2023 */
2024 smp_rmb();
2025
d462b819
NHE		 2026 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2027 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 2028 crash_enable_local_vmclear(cpu);
92fe13be
DX		 2029 local_irq_enable();
2030
6aa8b732
AK		 2031 /*
2032 * Linux uses per-cpu TSS and GDT, so set these when switching
2033 * processors.
2034 */
d6e88aec 2035 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 2036 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 2037
2038 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2039 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 2040 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 2041 }
28b835d6
FW		 2042
2043 vmx_vcpu_pi_load(vcpu, cpu);
2044}
2045
2046static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2047{
2048 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2049
2050 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2051 !irq_remapping_cap(IRQ_POSTING_CAP))
2052 return;
2053
2054 /* Set SN when the vCPU is preempted */
2055 if (vcpu->preempted)
2056 pi_set_sn(pi_desc);
6aa8b732
AK		 2057}
2058
2059static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2060{
28b835d6
FW		 2061 vmx_vcpu_pi_put(vcpu);
2062
a9b21b62 2063 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 2064 if (!vmm_exclusive) {
d462b819
NHE		 2065 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2066 vcpu->cpu = -1;
4610c9cc
DX		 2067 kvm_cpu_vmxoff();
2068 }
6aa8b732
AK		 2069}
2070
5fd86fcf
AK		 2071static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2072{
81231c69
AK		 2073 ulong cr0;
2074
5fd86fcf
AK		 2075 if (vcpu->fpu_active)
2076 return;
2077 vcpu->fpu_active = 1;
81231c69
AK		 2078 cr0 = vmcs_readl(GUEST_CR0);
2079 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2080 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2081 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 2082 update_exception_bitmap(vcpu);
edcafe3c 2083 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 2084 if (is_guest_mode(vcpu))
2085 vcpu->arch.cr0_guest_owned_bits &=
2086 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 2087 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 2088}
2089
edcafe3c
AK		 2090static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2091
fe3ef05c
NHE		 2092/*
2093 * Return the cr0 value that a nested guest would read. This is a combination
2094 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2095 * its hypervisor (cr0_read_shadow).
2096 */
2097static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2098{
2099 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2100 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2101}
2102static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2103{
2104 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2105 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2106}
2107
5fd86fcf
AK		 2108static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2109{
36cf24e0
NHE		 2110 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2111 * set this *before* calling this function.
2112 */
edcafe3c 2113 vmx_decache_cr0_guest_bits(vcpu);
81231c69 2114 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 2115 update_exception_bitmap(vcpu);
edcafe3c
AK		 2116 vcpu->arch.cr0_guest_owned_bits = 0;
2117 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 2118 if (is_guest_mode(vcpu)) {
2119 /*
2120 * L1's specified read shadow might not contain the TS bit,
2121 * so now that we turned on shadowing of this bit, we need to
2122 * set this bit of the shadow. Like in nested_vmx_run we need
2123 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2124 * up-to-date here because we just decached cr0.TS (and we'll
2125 * only update vmcs12->guest_cr0 on nested exit).
2126 */
2127 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2128 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2129 (vcpu->arch.cr0 & X86_CR0_TS);
2130 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2131 } else
2132 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2133}
2134
6aa8b732
AK		 2135static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2136{
78ac8b47 2137 unsigned long rflags, save_rflags;
345dcaa8 2138
6de12732
AK		 2139 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2140 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2141 rflags = vmcs_readl(GUEST_RFLAGS);
2142 if (to_vmx(vcpu)->rmode.vm86_active) {
2143 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2144 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2145 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2146 }
2147 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2148 }
6de12732 2149 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2150}
2151
2152static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2153{
6de12732
AK		 2154 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2155 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2156 if (to_vmx(vcpu)->rmode.vm86_active) {
2157 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2158 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2159 }
6aa8b732
AK		 2160 vmcs_writel(GUEST_RFLAGS, rflags);
2161}
2162
37ccdcbe 2163static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2164{
2165 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2166 int ret = 0;
2167
2168 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2169 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2170 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2171 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2172
37ccdcbe 2173 return ret;
2809f5d2
GC		 2174}
2175
2176static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2177{
2178 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2179 u32 interruptibility = interruptibility_old;
2180
2181 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2182
48005f64 2183 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2184 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2185 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2186 interruptibility |= GUEST_INTR_STATE_STI;
2187
2188 if ((interruptibility != interruptibility_old))
2189 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2190}
2191
6aa8b732
AK		 2192static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2193{
2194 unsigned long rip;
6aa8b732 2195
5fdbf976 2196 rip = kvm_rip_read(vcpu);
6aa8b732 2197 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2198 kvm_rip_write(vcpu, rip);
6aa8b732 2199
2809f5d2
GC		 2200 /* skipping an emulated instruction also counts */
2201 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2202}
2203
0b6ac343
NHE		 2204/*
2205 * KVM wants to inject page-faults which it got to the guest. This function
2206 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2207 */
e011c663 2208static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2209{
2210 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2211
e011c663 2212 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2213 return 0;
2214
533558bc
JK		 2215 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2216 vmcs_read32(VM_EXIT_INTR_INFO),
2217 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2218 return 1;
2219}
2220
298101da 2221static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2222 bool has_error_code, u32 error_code,
2223 bool reinject)
298101da 2224{
77ab6db0 2225 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2226 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2227
e011c663
GN		 2228 if (!reinject && is_guest_mode(vcpu) &&
2229 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2230 return;
2231
8ab2d2e2 2232 if (has_error_code) {
77ab6db0 2233 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2234 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2235 }
77ab6db0 2236
7ffd92c5 2237 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2238 int inc_eip = 0;
2239 if (kvm_exception_is_soft(nr))
2240 inc_eip = vcpu->arch.event_exit_inst_len;
2241 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2242 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2243 return;
2244 }
2245
66fd3f7f
GN		 2246 if (kvm_exception_is_soft(nr)) {
2247 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2248 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2249 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2250 } else
2251 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2252
2253 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2254}
2255
4e47c7a6
SY		 2256static bool vmx_rdtscp_supported(void)
2257{
2258 return cpu_has_vmx_rdtscp();
2259}
2260
ad756a16
MJ		 2261static bool vmx_invpcid_supported(void)
2262{
2263 return cpu_has_vmx_invpcid() && enable_ept;
2264}
2265
a75beee6
ED		 2266/*
2267 * Swap MSR entry in host/guest MSR entry array.
2268 */
8b9cf98c 2269static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2270{
26bb0981 2271 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2272
2273 tmp = vmx->guest_msrs[to];
2274 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2275 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2276}
2277
8d14695f
YZ		 2278static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2279{
2280 unsigned long *msr_bitmap;
2281
670125bd
WV		 2282 if (is_guest_mode(vcpu))
2283 msr_bitmap = vmx_msr_bitmap_nested;
8a9781f7 2284 else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
8d14695f
YZ		 2285 if (is_long_mode(vcpu))
2286 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2287 else
2288 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2289 } else {
2290 if (is_long_mode(vcpu))
2291 msr_bitmap = vmx_msr_bitmap_longmode;
2292 else
2293 msr_bitmap = vmx_msr_bitmap_legacy;
2294 }
2295
2296 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2297}
2298
e38aea3e
AK		 2299/*
2300 * Set up the vmcs to automatically save and restore system
2301 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2302 * mode, as fiddling with msrs is very expensive.
2303 */
8b9cf98c 2304static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2305{
26bb0981 2306 int save_nmsrs, index;
e38aea3e 2307
a75beee6
ED		 2308 save_nmsrs = 0;
2309#ifdef CONFIG_X86_64
8b9cf98c 2310 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2311 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2312 if (index >= 0)
8b9cf98c
RR		 2313 move_msr_up(vmx, index, save_nmsrs++);
2314 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2315 if (index >= 0)
8b9cf98c
RR		 2316 move_msr_up(vmx, index, save_nmsrs++);
2317 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2318 if (index >= 0)
8b9cf98c 2319 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6 2320 index = __find_msr_index(vmx, MSR_TSC_AUX);
1cea0ce6 2321 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
4e47c7a6 2322 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2323 /*
8c06585d 2324 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2325 * if efer.sce is enabled.
2326 */
8c06585d 2327 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2328 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2329 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2330 }
2331#endif
92c0d900
AK		 2332 index = __find_msr_index(vmx, MSR_EFER);
2333 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2334 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2335
26bb0981 2336 vmx->save_nmsrs = save_nmsrs;
5897297b 2337
8d14695f
YZ		 2338 if (cpu_has_vmx_msr_bitmap())
2339 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2340}
2341
6aa8b732
AK		 2342/*
2343 * reads and returns guest's timestamp counter "register"
2344 * guest_tsc = host_tsc + tsc_offset -- 21.3
2345 */
2346static u64 guest_read_tsc(void)
2347{
2348 u64 host_tsc, tsc_offset;
2349
4ea1636b 2350 host_tsc = rdtsc();
6aa8b732
AK		 2351 tsc_offset = vmcs_read64(TSC_OFFSET);
2352 return host_tsc + tsc_offset;
2353}
2354
d5c1785d
NHE		 2355/*
2356 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2357 * counter, even if a nested guest (L2) is currently running.
2358 */
48d89b92 2359static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2360{
886b470c 2361 u64 tsc_offset;
d5c1785d 2362
d5c1785d
NHE		 2363 tsc_offset = is_guest_mode(vcpu) ?
2364 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2365 vmcs_read64(TSC_OFFSET);
2366 return host_tsc + tsc_offset;
2367}
2368
4051b188 2369/*
cc578287
ZA		 2370 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2371 * software catchup for faster rates on slower CPUs.
4051b188 2372 */
cc578287 2373static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2374{
cc578287
ZA		 2375 if (!scale)
2376 return;
2377
2378 if (user_tsc_khz > tsc_khz) {
2379 vcpu->arch.tsc_catchup = 1;
2380 vcpu->arch.tsc_always_catchup = 1;
2381 } else
2382 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2383}
2384
ba904635
WA		 2385static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2386{
2387 return vmcs_read64(TSC_OFFSET);
2388}
2389
6aa8b732 2390/*
99e3e30a 2391 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2392 */
99e3e30a 2393static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2394{
27fc51b2 2395 if (is_guest_mode(vcpu)) {
7991825b 2396 /*
27fc51b2
NHE		 2397 * We're here if L1 chose not to trap WRMSR to TSC. According
2398 * to the spec, this should set L1's TSC; The offset that L1
2399 * set for L2 remains unchanged, and still needs to be added
2400 * to the newly set TSC to get L2's TSC.
7991825b 2401 */
27fc51b2
NHE		 2402 struct vmcs12 *vmcs12;
2403 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2404 /* recalculate vmcs02.TSC_OFFSET: */
2405 vmcs12 = get_vmcs12(vcpu);
2406 vmcs_write64(TSC_OFFSET, offset +
2407 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2408 vmcs12->tsc_offset : 0));
2409 } else {
489223ed
YY		 2410 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2411 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2412 vmcs_write64(TSC_OFFSET, offset);
2413 }
6aa8b732
AK		 2414}
2415
f1e2b260 2416static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2417{
2418 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2419
e48672fa 2420 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2421 if (is_guest_mode(vcpu)) {
2422 /* Even when running L2, the adjustment needs to apply to L1 */
2423 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2424 } else
2425 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2426 offset + adjustment);
e48672fa
ZA		 2427}
2428
857e4099
JR		 2429static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2430{
4ea1636b 2431 return target_tsc - rdtsc();
857e4099
JR		 2432}
2433
801d3424
NHE		 2434static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2435{
2436 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2437 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2438}
2439
2440/*
2441 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2442 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2443 * all guests if the "nested" module option is off, and can also be disabled
2444 * for a single guest by disabling its VMX cpuid bit.
2445 */
2446static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2447{
2448 return nested && guest_cpuid_has_vmx(vcpu);
2449}
2450
b87a51ae
NHE		 2451/*
2452 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2453 * returned for the various VMX controls MSRs when nested VMX is enabled.
2454 * The same values should also be used to verify that vmcs12 control fields are
2455 * valid during nested entry from L1 to L2.
2456 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2457 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2458 * bit in the high half is on if the corresponding bit in the control field
2459 * may be on. See also vmx_control_verify().
b87a51ae 2460 */
b9c237bb 2461static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2462{
2463 /*
2464 * Note that as a general rule, the high half of the MSRs (bits in
2465 * the control fields which may be 1) should be initialized by the
2466 * intersection of the underlying hardware's MSR (i.e., features which
2467 * can be supported) and the list of features we want to expose -
2468 * because they are known to be properly supported in our code.
2469 * Also, usually, the low half of the MSRs (bits which must be 1) can
2470 * be set to 0, meaning that L1 may turn off any of these bits. The
2471 * reason is that if one of these bits is necessary, it will appear
2472 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2473 * fields of vmcs01 and vmcs02, will turn these bits off - and
2474 * nested_vmx_exit_handled() will not pass related exits to L1.
2475 * These rules have exceptions below.
2476 */
2477
2478 /* pin-based controls */
eabeaacc 2479 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2480 vmx->nested.nested_vmx_pinbased_ctls_low,
2481 vmx->nested.nested_vmx_pinbased_ctls_high);
2482 vmx->nested.nested_vmx_pinbased_ctls_low |=
2483 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2484 vmx->nested.nested_vmx_pinbased_ctls_high &=
2485 PIN_BASED_EXT_INTR_MASK |
2486 PIN_BASED_NMI_EXITING |
2487 PIN_BASED_VIRTUAL_NMIS;
2488 vmx->nested.nested_vmx_pinbased_ctls_high |=
2489 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2490 PIN_BASED_VMX_PREEMPTION_TIMER;
35754c98 2491 if (vmx_cpu_uses_apicv(&vmx->vcpu))
705699a1
WV		 2492 vmx->nested.nested_vmx_pinbased_ctls_high |=
2493 PIN_BASED_POSTED_INTR;
b87a51ae 2494
3dbcd8da 2495 /* exit controls */
c0dfee58 2496 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2497 vmx->nested.nested_vmx_exit_ctls_low,
2498 vmx->nested.nested_vmx_exit_ctls_high);
2499 vmx->nested.nested_vmx_exit_ctls_low =
2500 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2501
b9c237bb 2502 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2503#ifdef CONFIG_X86_64
c0dfee58 2504 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2505#endif
f4124500 2506 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2507 vmx->nested.nested_vmx_exit_ctls_high |=
2508 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2509 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2510 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2511
36be0b9d 2512 if (vmx_mpx_supported())
b9c237bb 2513 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2514
2996fca0 2515 /* We support free control of debug control saving. */
b9c237bb
WV		 2516 vmx->nested.nested_vmx_true_exit_ctls_low =
2517 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2518 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2519
b87a51ae
NHE		 2520 /* entry controls */
2521 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2522 vmx->nested.nested_vmx_entry_ctls_low,
2523 vmx->nested.nested_vmx_entry_ctls_high);
2524 vmx->nested.nested_vmx_entry_ctls_low =
2525 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2526 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2527#ifdef CONFIG_X86_64
2528 VM_ENTRY_IA32E_MODE |
2529#endif
2530 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2531 vmx->nested.nested_vmx_entry_ctls_high |=
2532 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2533 if (vmx_mpx_supported())
b9c237bb 2534 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2535
2996fca0 2536 /* We support free control of debug control loading. */
b9c237bb
WV		 2537 vmx->nested.nested_vmx_true_entry_ctls_low =
2538 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2539 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2540
b87a51ae
NHE		 2541 /* cpu-based controls */
2542 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2543 vmx->nested.nested_vmx_procbased_ctls_low,
2544 vmx->nested.nested_vmx_procbased_ctls_high);
2545 vmx->nested.nested_vmx_procbased_ctls_low =
2546 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2547 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2548 CPU_BASED_VIRTUAL_INTR_PENDING |
2549 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2550 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2551 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2552 CPU_BASED_CR3_STORE_EXITING |
2553#ifdef CONFIG_X86_64
2554 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2555#endif
2556 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD		 2557 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2558 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2559 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2560 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE		 2561 /*
2562 * We can allow some features even when not supported by the
2563 * hardware. For example, L1 can specify an MSR bitmap - and we
2564 * can use it to avoid exits to L1 - even when L0 runs L2
2565 * without MSR bitmaps.
2566 */
b9c237bb
WV		 2567 vmx->nested.nested_vmx_procbased_ctls_high |=
2568 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2569 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2570
3dcdf3ec 2571 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2572 vmx->nested.nested_vmx_true_procbased_ctls_low =
2573 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2574 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2575
b87a51ae
NHE		 2576 /* secondary cpu-based controls */
2577 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2578 vmx->nested.nested_vmx_secondary_ctls_low,
2579 vmx->nested.nested_vmx_secondary_ctls_high);
2580 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2581 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2582 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2583 SECONDARY_EXEC_RDTSCP |
f2b93280 2584 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2585 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2586 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7 2587 SECONDARY_EXEC_WBINVD_EXITING |
8b3e34e4
XG		 2588 SECONDARY_EXEC_XSAVES |
2589 SECONDARY_EXEC_PCOMMIT;
c18911a2 2590
afa61f75
NHE		 2591 if (enable_ept) {
2592 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2593 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2594 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2595 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2596 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2597 VMX_EPT_INVEPT_BIT;
b9c237bb 2598 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2599 /*
4b855078
BD		 2600 * For nested guests, we don't do anything specific
2601 * for single context invalidation. Hence, only advertise
2602 * support for global context invalidation.
afa61f75 2603 */
b9c237bb 2604 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2605 } else
b9c237bb 2606 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2607
0790ec17
RK		 2608 if (enable_unrestricted_guest)
2609 vmx->nested.nested_vmx_secondary_ctls_high |=
2610 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2611
c18911a2 2612 /* miscellaneous data */
b9c237bb
WV		 2613 rdmsr(MSR_IA32_VMX_MISC,
2614 vmx->nested.nested_vmx_misc_low,
2615 vmx->nested.nested_vmx_misc_high);
2616 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2617 vmx->nested.nested_vmx_misc_low |=
2618 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2619 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2620 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2621}
2622
2623static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2624{
2625 /*
2626 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2627 */
2628 return ((control & high) | low) == control;
2629}
2630
2631static inline u64 vmx_control_msr(u32 low, u32 high)
2632{
2633 return low | ((u64)high << 32);
2634}
2635
cae50139 2636/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2637static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2638{
b9c237bb
WV		 2639 struct vcpu_vmx *vmx = to_vmx(vcpu);
2640
b87a51ae 2641 switch (msr_index) {
b87a51ae
NHE		 2642 case MSR_IA32_VMX_BASIC:
2643 /*
2644 * This MSR reports some information about VMX support. We
2645 * should return information about the VMX we emulate for the
2646 * guest, and the VMCS structure we give it - not about the
2647 * VMX support of the underlying hardware.
2648 */
3dbcd8da 2649 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2650 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2651 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2652 break;
2653 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2654 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2655 *pdata = vmx_control_msr(
2656 vmx->nested.nested_vmx_pinbased_ctls_low,
2657 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2658 break;
2659 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2660 *pdata = vmx_control_msr(
2661 vmx->nested.nested_vmx_true_procbased_ctls_low,
2662 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2663 break;
b87a51ae 2664 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2665 *pdata = vmx_control_msr(
2666 vmx->nested.nested_vmx_procbased_ctls_low,
2667 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2668 break;
2669 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2670 *pdata = vmx_control_msr(
2671 vmx->nested.nested_vmx_true_exit_ctls_low,
2672 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2673 break;
b87a51ae 2674 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2675 *pdata = vmx_control_msr(
2676 vmx->nested.nested_vmx_exit_ctls_low,
2677 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2678 break;
2679 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2680 *pdata = vmx_control_msr(
2681 vmx->nested.nested_vmx_true_entry_ctls_low,
2682 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2683 break;
b87a51ae 2684 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2685 *pdata = vmx_control_msr(
2686 vmx->nested.nested_vmx_entry_ctls_low,
2687 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2688 break;
2689 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2690 *pdata = vmx_control_msr(
2691 vmx->nested.nested_vmx_misc_low,
2692 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2693 break;
2694 /*
2695 * These MSRs specify bits which the guest must keep fixed (on or off)
2696 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2697 * We picked the standard core2 setting.
2698 */
2699#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2700#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2701 case MSR_IA32_VMX_CR0_FIXED0:
2702 *pdata = VMXON_CR0_ALWAYSON;
2703 break;
2704 case MSR_IA32_VMX_CR0_FIXED1:
2705 *pdata = -1ULL;
2706 break;
2707 case MSR_IA32_VMX_CR4_FIXED0:
2708 *pdata = VMXON_CR4_ALWAYSON;
2709 break;
2710 case MSR_IA32_VMX_CR4_FIXED1:
2711 *pdata = -1ULL;
2712 break;
2713 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2714 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2715 break;
2716 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2717 *pdata = vmx_control_msr(
2718 vmx->nested.nested_vmx_secondary_ctls_low,
2719 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2720 break;
2721 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2722 /* Currently, no nested vpid support */
b9c237bb 2723 *pdata = vmx->nested.nested_vmx_ept_caps;
b87a51ae
NHE		 2724 break;
2725 default:
b87a51ae 2726 return 1;
b3897a49
NHE		 2727 }
2728
b87a51ae
NHE		 2729 return 0;
2730}
2731
6aa8b732
AK		 2732/*
2733 * Reads an msr value (of 'msr_index') into 'pdata'.
2734 * Returns 0 on success, non-0 otherwise.
2735 * Assumes vcpu_load() was already called.
2736 */
609e36d3 2737static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2738{
26bb0981 2739 struct shared_msr_entry *msr;
6aa8b732 2740
609e36d3 2741 switch (msr_info->index) {
05b3e0c2 2742#ifdef CONFIG_X86_64
6aa8b732 2743 case MSR_FS_BASE:
609e36d3 2744 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK		 2745 break;
2746 case MSR_GS_BASE:
609e36d3 2747 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 2748 break;
44ea2b17
AK		 2749 case MSR_KERNEL_GS_BASE:
2750 vmx_load_host_state(to_vmx(vcpu));
609e36d3 2751 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 2752 break;
26bb0981 2753#endif
6aa8b732 2754 case MSR_EFER:
609e36d3 2755 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 2756 case MSR_IA32_TSC:
609e36d3 2757 msr_info->data = guest_read_tsc();
6aa8b732
AK		 2758 break;
2759 case MSR_IA32_SYSENTER_CS:
609e36d3 2760 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 2761 break;
2762 case MSR_IA32_SYSENTER_EIP:
609e36d3 2763 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2764 break;
2765 case MSR_IA32_SYSENTER_ESP:
609e36d3 2766 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2767 break;
0dd376e7 2768 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2769 if (!vmx_mpx_supported())
2770 return 1;
609e36d3 2771 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 2772 break;
cae50139
JK		 2773 case MSR_IA32_FEATURE_CONTROL:
2774 if (!nested_vmx_allowed(vcpu))
2775 return 1;
609e36d3 2776 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
cae50139
JK		 2777 break;
2778 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2779 if (!nested_vmx_allowed(vcpu))
2780 return 1;
609e36d3 2781 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL		 2782 case MSR_IA32_XSS:
2783 if (!vmx_xsaves_supported())
2784 return 1;
609e36d3 2785 msr_info->data = vcpu->arch.ia32_xss;
20300099 2786 break;
4e47c7a6 2787 case MSR_TSC_AUX:
1cea0ce6 2788 if (!guest_cpuid_has_rdtscp(vcpu))
4e47c7a6
SY		 2789 return 1;
2790 /* Otherwise falls through */
6aa8b732 2791 default:
609e36d3 2792 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 2793 if (msr) {
609e36d3 2794 msr_info->data = msr->data;
3bab1f5d 2795 break;
6aa8b732 2796 }
609e36d3 2797 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2798 }
2799
6aa8b732
AK		 2800 return 0;
2801}
2802
cae50139
JK		 2803static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2804
6aa8b732
AK		 2805/*
2806 * Writes msr value into into the appropriate "register".
2807 * Returns 0 on success, non-0 otherwise.
2808 * Assumes vcpu_load() was already called.
2809 */
8fe8ab46 2810static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2811{
a2fa3e9f 2812 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2813 struct shared_msr_entry *msr;
2cc51560 2814 int ret = 0;
8fe8ab46
WA		 2815 u32 msr_index = msr_info->index;
2816 u64 data = msr_info->data;
2cc51560 2817
6aa8b732 2818 switch (msr_index) {
3bab1f5d 2819 case MSR_EFER:
8fe8ab46 2820 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2821 break;
16175a79 2822#ifdef CONFIG_X86_64
6aa8b732 2823 case MSR_FS_BASE:
2fb92db1 2824 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2825 vmcs_writel(GUEST_FS_BASE, data);
2826 break;
2827 case MSR_GS_BASE:
2fb92db1 2828 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2829 vmcs_writel(GUEST_GS_BASE, data);
2830 break;
44ea2b17
AK		 2831 case MSR_KERNEL_GS_BASE:
2832 vmx_load_host_state(vmx);
2833 vmx->msr_guest_kernel_gs_base = data;
2834 break;
6aa8b732
AK		 2835#endif
2836 case MSR_IA32_SYSENTER_CS:
2837 vmcs_write32(GUEST_SYSENTER_CS, data);
2838 break;
2839 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2840 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2841 break;
2842 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2843 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2844 break;
0dd376e7 2845 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2846 if (!vmx_mpx_supported())
2847 return 1;
0dd376e7
LJ		 2848 vmcs_write64(GUEST_BNDCFGS, data);
2849 break;
af24a4e4 2850 case MSR_IA32_TSC:
8fe8ab46 2851 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2852 break;
468d472f
SY		 2853 case MSR_IA32_CR_PAT:
2854 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2855 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2856 return 1;
468d472f
SY		 2857 vmcs_write64(GUEST_IA32_PAT, data);
2858 vcpu->arch.pat = data;
2859 break;
2860 }
8fe8ab46 2861 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2862 break;
ba904635
WA		 2863 case MSR_IA32_TSC_ADJUST:
2864 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2865 break;
cae50139
JK		 2866 case MSR_IA32_FEATURE_CONTROL:
2867 if (!nested_vmx_allowed(vcpu) ||
2868 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2869 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2870 return 1;
2871 vmx->nested.msr_ia32_feature_control = data;
2872 if (msr_info->host_initiated && data == 0)
2873 vmx_leave_nested(vcpu);
2874 break;
2875 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2876 return 1; /* they are read-only */
20300099
WL		 2877 case MSR_IA32_XSS:
2878 if (!vmx_xsaves_supported())
2879 return 1;
2880 /*
2881 * The only supported bit as of Skylake is bit 8, but
2882 * it is not supported on KVM.
2883 */
2884 if (data != 0)
2885 return 1;
2886 vcpu->arch.ia32_xss = data;
2887 if (vcpu->arch.ia32_xss != host_xss)
2888 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2889 vcpu->arch.ia32_xss, host_xss);
2890 else
2891 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2892 break;
4e47c7a6 2893 case MSR_TSC_AUX:
1cea0ce6 2894 if (!guest_cpuid_has_rdtscp(vcpu))
4e47c7a6
SY		 2895 return 1;
2896 /* Check reserved bit, higher 32 bits should be zero */
2897 if ((data >> 32) != 0)
2898 return 1;
2899 /* Otherwise falls through */
6aa8b732 2900 default:
8b9cf98c 2901 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2902 if (msr) {
8b3c3104 2903 u64 old_msr_data = msr->data;
3bab1f5d 2904 msr->data = data;
2225fd56
AK		 2905 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2906 preempt_disable();
8b3c3104
AH		 2907 ret = kvm_set_shared_msr(msr->index, msr->data,
2908 msr->mask);
2225fd56 2909 preempt_enable();
8b3c3104
AH		 2910 if (ret)
2911 msr->data = old_msr_data;
2225fd56 2912 }
3bab1f5d 2913 break;
6aa8b732 2914 }
8fe8ab46 2915 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2916 }
2917
2cc51560 2918 return ret;
6aa8b732
AK		 2919}
2920
5fdbf976 2921static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2922{
5fdbf976
MT		 2923 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2924 switch (reg) {
2925 case VCPU_REGS_RSP:
2926 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2927 break;
2928 case VCPU_REGS_RIP:
2929 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2930 break;
6de4f3ad
AK		 2931 case VCPU_EXREG_PDPTR:
2932 if (enable_ept)
2933 ept_save_pdptrs(vcpu);
2934 break;
5fdbf976
MT		 2935 default:
2936 break;
2937 }
6aa8b732
AK		 2938}
2939
6aa8b732
AK		 2940static __init int cpu_has_kvm_support(void)
2941{
6210e37b 2942 return cpu_has_vmx();
6aa8b732
AK		 2943}
2944
2945static __init int vmx_disabled_by_bios(void)
2946{
2947 u64 msr;
2948
2949 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2950 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2951 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2952 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2953 && tboot_enabled())
2954 return 1;
23f3e991 2955 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2956 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2957 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2958 && !tboot_enabled()) {
2959 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2960 "activate TXT before enabling KVM\n");
cafd6659 2961 return 1;
f9335afe 2962 }
23f3e991
JC		 2963 /* launched w/o TXT and VMX disabled */
2964 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2965 && !tboot_enabled())
2966 return 1;
cafd6659
SW		 2967 }
2968
2969 return 0;
6aa8b732
AK		 2970}
2971
7725b894
DX		 2972static void kvm_cpu_vmxon(u64 addr)
2973{
2974 asm volatile (ASM_VMX_VMXON_RAX
2975 : : "a"(&addr), "m"(addr)
2976 : "memory", "cc");
2977}
2978
13a34e06 2979static int hardware_enable(void)
6aa8b732
AK		 2980{
2981 int cpu = raw_smp_processor_id();
2982 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2983 u64 old, test_bits;
6aa8b732 2984
1e02ce4c 2985 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2986 return -EBUSY;
2987
d462b819 2988 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2989
2990 /*
2991 * Now we can enable the vmclear operation in kdump
2992 * since the loaded_vmcss_on_cpu list on this cpu
2993 * has been initialized.
2994 *
2995 * Though the cpu is not in VMX operation now, there
2996 * is no problem to enable the vmclear operation
2997 * for the loaded_vmcss_on_cpu list is empty!
2998 */
2999 crash_enable_local_vmclear(cpu);
3000
6aa8b732 3001 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 3002
3003 test_bits = FEATURE_CONTROL_LOCKED;
3004 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3005 if (tboot_enabled())
3006 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3007
3008 if ((old & test_bits) != test_bits) {
6aa8b732 3009 /* enable and lock */
cafd6659
SW		 3010 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3011 }
375074cc 3012 cr4_set_bits(X86_CR4_VMXE);
10474ae8 3013
4610c9cc
DX		 3014 if (vmm_exclusive) {
3015 kvm_cpu_vmxon(phys_addr);
3016 ept_sync_global();
3017 }
10474ae8 3018
89cbc767 3019 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 3020
10474ae8 3021 return 0;
6aa8b732
AK		 3022}
3023
d462b819 3024static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 3025{
3026 int cpu = raw_smp_processor_id();
d462b819 3027 struct loaded_vmcs *v, *n;
543e4243 3028
d462b819
NHE		 3029 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3030 loaded_vmcss_on_cpu_link)
3031 __loaded_vmcs_clear(v);
543e4243
AK		 3032}
3033
710ff4a8
EH		 3034
3035/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3036 * tricks.
3037 */
3038static void kvm_cpu_vmxoff(void)
6aa8b732 3039{
4ecac3fd 3040 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 3041}
3042
13a34e06 3043static void hardware_disable(void)
710ff4a8 3044{
4610c9cc 3045 if (vmm_exclusive) {
d462b819 3046 vmclear_local_loaded_vmcss();
4610c9cc
DX		 3047 kvm_cpu_vmxoff();
3048 }
375074cc 3049 cr4_clear_bits(X86_CR4_VMXE);
710ff4a8
EH		 3050}
3051
1c3d14fe 3052static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 3053 u32 msr, u32 *result)
1c3d14fe
YS		 3054{
3055 u32 vmx_msr_low, vmx_msr_high;
3056 u32 ctl = ctl_min | ctl_opt;
3057
3058 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3059
3060 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3061 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3062
3063 /* Ensure minimum (required) set of control bits are supported. */
3064 if (ctl_min & ~ctl)
002c7f7c 3065 return -EIO;
1c3d14fe
YS		 3066
3067 *result = ctl;
3068 return 0;
3069}
3070
110312c8
AK		 3071static __init bool allow_1_setting(u32 msr, u32 ctl)
3072{
3073 u32 vmx_msr_low, vmx_msr_high;
3074
3075 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3076 return vmx_msr_high & ctl;
3077}
3078
002c7f7c 3079static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 3080{
3081 u32 vmx_msr_low, vmx_msr_high;
d56f546d 3082 u32 min, opt, min2, opt2;
1c3d14fe
YS		 3083 u32 _pin_based_exec_control = 0;
3084 u32 _cpu_based_exec_control = 0;
f78e0e2e 3085 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 3086 u32 _vmexit_control = 0;
3087 u32 _vmentry_control = 0;
3088
10166744 3089 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 3090#ifdef CONFIG_X86_64
3091 CPU_BASED_CR8_LOAD_EXITING |
3092 CPU_BASED_CR8_STORE_EXITING |
3093#endif
d56f546d
SY		 3094 CPU_BASED_CR3_LOAD_EXITING |
3095 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 3096 CPU_BASED_USE_IO_BITMAPS |
3097 CPU_BASED_MOV_DR_EXITING |
a7052897 3098 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 3099 CPU_BASED_MWAIT_EXITING |
3100 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 3101 CPU_BASED_INVLPG_EXITING |
3102 CPU_BASED_RDPMC_EXITING;
443381a8 3103
f78e0e2e 3104 opt = CPU_BASED_TPR_SHADOW |
25c5f225 3105 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 3106 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 3107 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3108 &_cpu_based_exec_control) < 0)
002c7f7c 3109 return -EIO;
6e5d865c
YS		 3110#ifdef CONFIG_X86_64
3111 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3112 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3113 ~CPU_BASED_CR8_STORE_EXITING;
3114#endif
f78e0e2e 3115 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 3116 min2 = 0;
3117 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3118 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3119 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3120 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3121 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3122 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3123 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3124 SECONDARY_EXEC_RDTSCP |
83d4c286 3125 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3126 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3127 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3128 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 3129 SECONDARY_EXEC_XSAVES |
8b3e34e4
XG		 3130 SECONDARY_EXEC_ENABLE_PML |
3131 SECONDARY_EXEC_PCOMMIT;
d56f546d
SY		 3132 if (adjust_vmx_controls(min2, opt2,
3133 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3134 &_cpu_based_2nd_exec_control) < 0)
3135 return -EIO;
3136 }
3137#ifndef CONFIG_X86_64
3138 if (!(_cpu_based_2nd_exec_control &
3139 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3140 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3141#endif
83d4c286
YZ		 3142
3143 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3144 _cpu_based_2nd_exec_control &= ~(
8d14695f 3145 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3146 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3147 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3148
d56f546d 3149 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3150 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3151 enabled */
5fff7d27
GN		 3152 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3153 CPU_BASED_CR3_STORE_EXITING |
3154 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3155 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3156 vmx_capability.ept, vmx_capability.vpid);
3157 }
1c3d14fe 3158
81908bf4 3159 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3160#ifdef CONFIG_X86_64
3161 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3162#endif
a547c6db 3163 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3164 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3165 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3166 &_vmexit_control) < 0)
002c7f7c 3167 return -EIO;
1c3d14fe 3168
01e439be
YZ		 3169 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3170 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3171 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3172 &_pin_based_exec_control) < 0)
3173 return -EIO;
3174
3175 if (!(_cpu_based_2nd_exec_control &
3176 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3177 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3178 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3179
c845f9c6 3180 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3181 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3182 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3183 &_vmentry_control) < 0)
002c7f7c 3184 return -EIO;
6aa8b732 3185
c68876fd 3186 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3187
3188 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3189 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3190 return -EIO;
1c3d14fe
YS		 3191
3192#ifdef CONFIG_X86_64
3193 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3194 if (vmx_msr_high & (1u<<16))
002c7f7c 3195 return -EIO;
1c3d14fe
YS		 3196#endif
3197
3198 /* Require Write-Back (WB) memory type for VMCS accesses. */
3199 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3200 return -EIO;
1c3d14fe 3201
002c7f7c
YS		 3202 vmcs_conf->size = vmx_msr_high & 0x1fff;
3203 vmcs_conf->order = get_order(vmcs_config.size);
3204 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3205
002c7f7c
YS		 3206 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3207 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3208 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3209 vmcs_conf->vmexit_ctrl = _vmexit_control;
3210 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3211
110312c8
AK		 3212 cpu_has_load_ia32_efer =
3213 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3214 VM_ENTRY_LOAD_IA32_EFER)
3215 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3216 VM_EXIT_LOAD_IA32_EFER);
3217
8bf00a52
GN		 3218 cpu_has_load_perf_global_ctrl =
3219 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3220 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3221 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3222 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3223
3224 /*
3225 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3226 * but due to arrata below it can't be used. Workaround is to use
3227 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3228 *
3229 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3230 *
3231 * AAK155 (model 26)
3232 * AAP115 (model 30)
3233 * AAT100 (model 37)
3234 * BC86,AAY89,BD102 (model 44)
3235 * BA97 (model 46)
3236 *
3237 */
3238 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3239 switch (boot_cpu_data.x86_model) {
3240 case 26:
3241 case 30:
3242 case 37:
3243 case 44:
3244 case 46:
3245 cpu_has_load_perf_global_ctrl = false;
3246 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3247 "does not work properly. Using workaround\n");
3248 break;
3249 default:
3250 break;
3251 }
3252 }
3253
20300099
WL		 3254 if (cpu_has_xsaves)
3255 rdmsrl(MSR_IA32_XSS, host_xss);
3256
1c3d14fe 3257 return 0;
c68876fd 3258}
6aa8b732
AK		 3259
3260static struct vmcs *alloc_vmcs_cpu(int cpu)
3261{
3262 int node = cpu_to_node(cpu);
3263 struct page *pages;
3264 struct vmcs *vmcs;
3265
96db800f 3266 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3267 if (!pages)
3268 return NULL;
3269 vmcs = page_address(pages);
1c3d14fe
YS		 3270 memset(vmcs, 0, vmcs_config.size);
3271 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3272 return vmcs;
3273}
3274
3275static struct vmcs *alloc_vmcs(void)
3276{
d3b2c338 3277 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3278}
3279
3280static void free_vmcs(struct vmcs *vmcs)
3281{
1c3d14fe 3282 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3283}
3284
d462b819
NHE		 3285/*
3286 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3287 */
3288static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3289{
3290 if (!loaded_vmcs->vmcs)
3291 return;
3292 loaded_vmcs_clear(loaded_vmcs);
3293 free_vmcs(loaded_vmcs->vmcs);
3294 loaded_vmcs->vmcs = NULL;
3295}
3296
39959588 3297static void free_kvm_area(void)
6aa8b732
AK		 3298{
3299 int cpu;
3300
3230bb47 3301 for_each_possible_cpu(cpu) {
6aa8b732 3302 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3303 per_cpu(vmxarea, cpu) = NULL;
3304 }
6aa8b732
AK		 3305}
3306
fe2b201b
BD		 3307static void init_vmcs_shadow_fields(void)
3308{
3309 int i, j;
3310
3311 /* No checks for read only fields yet */
3312
3313 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3314 switch (shadow_read_write_fields[i]) {
3315 case GUEST_BNDCFGS:
3316 if (!vmx_mpx_supported())
3317 continue;
3318 break;
3319 default:
3320 break;
3321 }
3322
3323 if (j < i)
3324 shadow_read_write_fields[j] =
3325 shadow_read_write_fields[i];
3326 j++;
3327 }
3328 max_shadow_read_write_fields = j;
3329
3330 /* shadowed fields guest access without vmexit */
3331 for (i = 0; i < max_shadow_read_write_fields; i++) {
3332 clear_bit(shadow_read_write_fields[i],
3333 vmx_vmwrite_bitmap);
3334 clear_bit(shadow_read_write_fields[i],
3335 vmx_vmread_bitmap);
3336 }
3337 for (i = 0; i < max_shadow_read_only_fields; i++)
3338 clear_bit(shadow_read_only_fields[i],
3339 vmx_vmread_bitmap);
3340}
3341
6aa8b732
AK		 3342static __init int alloc_kvm_area(void)
3343{
3344 int cpu;
3345
3230bb47 3346 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3347 struct vmcs *vmcs;
3348
3349 vmcs = alloc_vmcs_cpu(cpu);
3350 if (!vmcs) {
3351 free_kvm_area();
3352 return -ENOMEM;
3353 }
3354
3355 per_cpu(vmxarea, cpu) = vmcs;
3356 }
3357 return 0;
3358}
3359
14168786
GN		 3360static bool emulation_required(struct kvm_vcpu *vcpu)
3361{
3362 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3363}
3364
91b0aa2c 3365static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3366 struct kvm_segment *save)
6aa8b732 3367{
d99e4152
GN		 3368 if (!emulate_invalid_guest_state) {
3369 /*
3370 * CS and SS RPL should be equal during guest entry according
3371 * to VMX spec, but in reality it is not always so. Since vcpu
3372 * is in the middle of the transition from real mode to
3373 * protected mode it is safe to assume that RPL 0 is a good
3374 * default value.
3375 */
3376 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 3377 save->selector &= ~SEGMENT_RPL_MASK;
3378 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3379 save->s = 1;
6aa8b732 3380 }
d99e4152 3381 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3382}
3383
3384static void enter_pmode(struct kvm_vcpu *vcpu)
3385{
3386 unsigned long flags;
a89a8fb9 3387 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3388
d99e4152
GN		 3389 /*
3390 * Update real mode segment cache. It may be not up-to-date if sement
3391 * register was written while vcpu was in a guest mode.
3392 */
3393 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3394 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3395 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3396 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3397 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3398 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3399
7ffd92c5 3400 vmx->rmode.vm86_active = 0;
6aa8b732 3401
2fb92db1
AK		 3402 vmx_segment_cache_clear(vmx);
3403
f5f7b2fe 3404 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3405
3406 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3407 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3408 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3409 vmcs_writel(GUEST_RFLAGS, flags);
3410
66aee91a
RR		 3411 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3412 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3413
3414 update_exception_bitmap(vcpu);
3415
91b0aa2c
GN		 3416 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3417 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3418 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3419 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3420 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3421 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3422}
3423
f5f7b2fe 3424static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3425{
772e0318 3426 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3427 struct kvm_segment var = *save;
3428
3429 var.dpl = 0x3;
3430 if (seg == VCPU_SREG_CS)
3431 var.type = 0x3;
3432
3433 if (!emulate_invalid_guest_state) {
3434 var.selector = var.base >> 4;
3435 var.base = var.base & 0xffff0;
3436 var.limit = 0xffff;
3437 var.g = 0;
3438 var.db = 0;
3439 var.present = 1;
3440 var.s = 1;
3441 var.l = 0;
3442 var.unusable = 0;
3443 var.type = 0x3;
3444 var.avl = 0;
3445 if (save->base & 0xf)
3446 printk_once(KERN_WARNING "kvm: segment base is not "
3447 "paragraph aligned when entering "
3448 "protected mode (seg=%d)", seg);
3449 }
6aa8b732 3450
d99e4152
GN		 3451 vmcs_write16(sf->selector, var.selector);
3452 vmcs_write32(sf->base, var.base);
3453 vmcs_write32(sf->limit, var.limit);
3454 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3455}
3456
3457static void enter_rmode(struct kvm_vcpu *vcpu)
3458{
3459 unsigned long flags;
a89a8fb9 3460 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3461
f5f7b2fe
AK		 3462 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3463 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3464 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3465 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3466 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3467 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3468 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3469
7ffd92c5 3470 vmx->rmode.vm86_active = 1;
6aa8b732 3471
776e58ea
GN		 3472 /*
3473 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3474 * vcpu. Warn the user that an update is overdue.
776e58ea 3475 */
4918c6ca 3476 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3477 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3478 "called before entering vcpu\n");
776e58ea 3479
2fb92db1
AK		 3480 vmx_segment_cache_clear(vmx);
3481
4918c6ca 3482 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3483 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3484 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3485
3486 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3487 vmx->rmode.save_rflags = flags;
6aa8b732 3488
053de044 3489 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3490
3491 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3492 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3493 update_exception_bitmap(vcpu);
3494
d99e4152
GN		 3495 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3496 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3497 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3498 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3499 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3500 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3501
8668a3c4 3502 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3503}
3504
401d10de
AS		 3505static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3506{
3507 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3508 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3509
3510 if (!msr)
3511 return;
401d10de 3512
44ea2b17
AK		 3513 /*
3514 * Force kernel_gs_base reloading before EFER changes, as control
3515 * of this msr depends on is_long_mode().
3516 */
3517 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3518 vcpu->arch.efer = efer;
401d10de 3519 if (efer & EFER_LMA) {
2961e876 3520 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3521 msr->data = efer;
3522 } else {
2961e876 3523 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3524
3525 msr->data = efer & ~EFER_LME;
3526 }
3527 setup_msrs(vmx);
3528}
3529
05b3e0c2 3530#ifdef CONFIG_X86_64
6aa8b732
AK		 3531
3532static void enter_lmode(struct kvm_vcpu *vcpu)
3533{
3534 u32 guest_tr_ar;
3535
2fb92db1
AK		 3536 vmx_segment_cache_clear(to_vmx(vcpu));
3537
6aa8b732 3538 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 3539 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3540 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3541 __func__);
6aa8b732 3542 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 3543 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3544 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 3545 }
da38f438 3546 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3547}
3548
3549static void exit_lmode(struct kvm_vcpu *vcpu)
3550{
2961e876 3551 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3552 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3553}
3554
3555#endif
3556
2384d2b3
SY		 3557static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3558{
b9d762fa 3559 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3560 if (enable_ept) {
3561 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3562 return;
4e1096d2 3563 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3564 }
2384d2b3
SY		 3565}
3566
e8467fda
AK		 3567static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3568{
3569 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3570
3571 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3572 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3573}
3574
aff48baa
AK		 3575static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3576{
3577 if (enable_ept && is_paging(vcpu))
3578 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3579 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3580}
3581
25c4c276 3582static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3583{
fc78f519
AK		 3584 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3585
3586 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3587 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3588}
3589
1439442c
SY		 3590static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3591{
d0d538b9
GN		 3592 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3593
6de4f3ad
AK		 3594 if (!test_bit(VCPU_EXREG_PDPTR,
3595 (unsigned long *)&vcpu->arch.regs_dirty))
3596 return;
3597
1439442c 3598 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3599 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3600 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3601 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3602 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3603 }
3604}
3605
8f5d549f
AK		 3606static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3607{
d0d538b9
GN		 3608 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3609
8f5d549f 3610 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3611 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3612 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3613 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3614 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3615 }
6de4f3ad
AK		 3616
3617 __set_bit(VCPU_EXREG_PDPTR,
3618 (unsigned long *)&vcpu->arch.regs_avail);
3619 __set_bit(VCPU_EXREG_PDPTR,
3620 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3621}
3622
5e1746d6 3623static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3624
3625static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3626 unsigned long cr0,
3627 struct kvm_vcpu *vcpu)
3628{
5233dd51
MT		 3629 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3630 vmx_decache_cr3(vcpu);
1439442c
SY		 3631 if (!(cr0 & X86_CR0_PG)) {
3632 /* From paging/starting to nonpaging */
3633 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3634 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3635 (CPU_BASED_CR3_LOAD_EXITING |
3636 CPU_BASED_CR3_STORE_EXITING));
3637 vcpu->arch.cr0 = cr0;
fc78f519 3638 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3639 } else if (!is_paging(vcpu)) {
3640 /* From nonpaging to paging */
3641 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3642 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3643 ~(CPU_BASED_CR3_LOAD_EXITING |
3644 CPU_BASED_CR3_STORE_EXITING));
3645 vcpu->arch.cr0 = cr0;
fc78f519 3646 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3647 }
95eb84a7
SY		 3648
3649 if (!(cr0 & X86_CR0_WP))
3650 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3651}
3652
6aa8b732
AK		 3653static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3654{
7ffd92c5 3655 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3656 unsigned long hw_cr0;
3657
5037878e 3658 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3659 if (enable_unrestricted_guest)
5037878e 3660 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3661 else {
5037878e 3662 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3663
218e763f
GN		 3664 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3665 enter_pmode(vcpu);
6aa8b732 3666
218e763f
GN		 3667 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3668 enter_rmode(vcpu);
3669 }
6aa8b732 3670
05b3e0c2 3671#ifdef CONFIG_X86_64
f6801dff 3672 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3673 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3674 enter_lmode(vcpu);
707d92fa 3675 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3676 exit_lmode(vcpu);
3677 }
3678#endif
3679
089d034e 3680 if (enable_ept)
1439442c
SY		 3681 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3682
02daab21 3683 if (!vcpu->fpu_active)
81231c69 3684 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3685
6aa8b732 3686 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3687 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3688 vcpu->arch.cr0 = cr0;
14168786
GN		 3689
3690 /* depends on vcpu->arch.cr0 to be set to a new value */
3691 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3692}
3693
1439442c
SY		 3694static u64 construct_eptp(unsigned long root_hpa)
3695{
3696 u64 eptp;
3697
3698 /* TODO write the value reading from MSR */
3699 eptp = VMX_EPT_DEFAULT_MT |
3700 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3701 if (enable_ept_ad_bits)
3702 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3703 eptp |= (root_hpa & PAGE_MASK);
3704
3705 return eptp;
3706}
3707
6aa8b732
AK		 3708static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3709{
1439442c
SY		 3710 unsigned long guest_cr3;
3711 u64 eptp;
3712
3713 guest_cr3 = cr3;
089d034e 3714 if (enable_ept) {
1439442c
SY		 3715 eptp = construct_eptp(cr3);
3716 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3717 if (is_paging(vcpu) || is_guest_mode(vcpu))
3718 guest_cr3 = kvm_read_cr3(vcpu);
3719 else
3720 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3721 ept_load_pdptrs(vcpu);
1439442c
SY		 3722 }
3723
2384d2b3 3724 vmx_flush_tlb(vcpu);
1439442c 3725 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3726}
3727
5e1746d6 3728static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3729{
085e68ee
BS		 3730 /*
3731 * Pass through host's Machine Check Enable value to hw_cr4, which
3732 * is in force while we are in guest mode. Do not let guests control
3733 * this bit, even if host CR4.MCE == 0.
3734 */
3735 unsigned long hw_cr4 =
3736 (cr4_read_shadow() & X86_CR4_MCE) |
3737 (cr4 & ~X86_CR4_MCE) |
3738 (to_vmx(vcpu)->rmode.vm86_active ?
3739 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 3740
5e1746d6
NHE		 3741 if (cr4 & X86_CR4_VMXE) {
3742 /*
3743 * To use VMXON (and later other VMX instructions), a guest
3744 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3745 * So basically the check on whether to allow nested VMX
3746 * is here.
3747 */
3748 if (!nested_vmx_allowed(vcpu))
3749 return 1;
1a0d74e6
JK		 3750 }
3751 if (to_vmx(vcpu)->nested.vmxon &&
3752 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3753 return 1;
3754
ad312c7c 3755 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3756 if (enable_ept) {
3757 if (!is_paging(vcpu)) {
3758 hw_cr4 &= ~X86_CR4_PAE;
3759 hw_cr4 |= X86_CR4_PSE;
c08800a5 3760 /*
e1e746b3
FW		 3761 * SMEP/SMAP is disabled if CPU is in non-paging mode
3762 * in hardware. However KVM always uses paging mode to
c08800a5 3763 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3764 * To emulate this behavior, SMEP/SMAP needs to be
3765 * manually disabled when guest switches to non-paging
3766 * mode.
c08800a5 3767 */
e1e746b3 3768 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3769 } else if (!(cr4 & X86_CR4_PAE)) {
3770 hw_cr4 &= ~X86_CR4_PAE;
3771 }
3772 }
1439442c
SY		 3773
3774 vmcs_writel(CR4_READ_SHADOW, cr4);
3775 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3776 return 0;
6aa8b732
AK		 3777}
3778
6aa8b732
AK		 3779static void vmx_get_segment(struct kvm_vcpu *vcpu,
3780 struct kvm_segment *var, int seg)
3781{
a9179499 3782 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3783 u32 ar;
3784
c6ad1153 3785 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3786 *var = vmx->rmode.segs[seg];
a9179499 3787 if (seg == VCPU_SREG_TR
2fb92db1 3788 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3789 return;
1390a28b
AK		 3790 var->base = vmx_read_guest_seg_base(vmx, seg);
3791 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3792 return;
a9179499 3793 }
2fb92db1
AK		 3794 var->base = vmx_read_guest_seg_base(vmx, seg);
3795 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3796 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3797 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3798 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3799 var->type = ar & 15;
3800 var->s = (ar >> 4) & 1;
3801 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3802 /*
3803 * Some userspaces do not preserve unusable property. Since usable
3804 * segment has to be present according to VMX spec we can use present
3805 * property to amend userspace bug by making unusable segment always
3806 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3807 * segment as unusable.
3808 */
3809 var->present = !var->unusable;
6aa8b732
AK		 3810 var->avl = (ar >> 12) & 1;
3811 var->l = (ar >> 13) & 1;
3812 var->db = (ar >> 14) & 1;
3813 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3814}
3815
a9179499
AK		 3816static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3817{
a9179499
AK		 3818 struct kvm_segment s;
3819
3820 if (to_vmx(vcpu)->rmode.vm86_active) {
3821 vmx_get_segment(vcpu, &s, seg);
3822 return s.base;
3823 }
2fb92db1 3824 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3825}
3826
b09408d0 3827static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3828{
b09408d0
MT		 3829 struct vcpu_vmx *vmx = to_vmx(vcpu);
3830
ae9fedc7 3831 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3832 return 0;
ae9fedc7
PB		 3833 else {
3834 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3835 return VMX_AR_DPL(ar);
69c73028 3836 }
69c73028
AK		 3837}
3838
653e3108 3839static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3840{
6aa8b732
AK		 3841 u32 ar;
3842
f0495f9b 3843 if (var->unusable || !var->present)
6aa8b732
AK		 3844 ar = 1 << 16;
3845 else {
3846 ar = var->type & 15;
3847 ar |= (var->s & 1) << 4;
3848 ar |= (var->dpl & 3) << 5;
3849 ar |= (var->present & 1) << 7;
3850 ar |= (var->avl & 1) << 12;
3851 ar |= (var->l & 1) << 13;
3852 ar |= (var->db & 1) << 14;
3853 ar |= (var->g & 1) << 15;
3854 }
653e3108
AK		 3855
3856 return ar;
3857}
3858
3859static void vmx_set_segment(struct kvm_vcpu *vcpu,
3860 struct kvm_segment *var, int seg)
3861{
7ffd92c5 3862 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3863 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3864
2fb92db1
AK		 3865 vmx_segment_cache_clear(vmx);
3866
1ecd50a9
GN		 3867 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3868 vmx->rmode.segs[seg] = *var;
3869 if (seg == VCPU_SREG_TR)
3870 vmcs_write16(sf->selector, var->selector);
3871 else if (var->s)
3872 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3873 goto out;
653e3108 3874 }
1ecd50a9 3875
653e3108
AK		 3876 vmcs_writel(sf->base, var->base);
3877 vmcs_write32(sf->limit, var->limit);
3878 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3879
3880 /*
3881 * Fix the "Accessed" bit in AR field of segment registers for older
3882 * qemu binaries.
3883 * IA32 arch specifies that at the time of processor reset the
3884 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3885 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3886 * state vmexit when "unrestricted guest" mode is turned on.
3887 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3888 * tree. Newer qemu binaries with that qemu fix would not need this
3889 * kvm hack.
3890 */
3891 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3892 var->type |= 0x1; /* Accessed */
3a624e29 3893
f924d66d 3894 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3895
3896out:
98eb2f8b 3897 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3898}
3899
6aa8b732
AK		 3900static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3901{
2fb92db1 3902 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3903
3904 *db = (ar >> 14) & 1;
3905 *l = (ar >> 13) & 1;
3906}
3907
89a27f4d 3908static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3909{
89a27f4d
GN		 3910 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3911 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3912}
3913
89a27f4d 3914static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3915{
89a27f4d
GN		 3916 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3917 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3918}
3919
89a27f4d 3920static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3921{
89a27f4d
GN		 3922 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3923 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3924}
3925
89a27f4d 3926static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3927{
89a27f4d
GN		 3928 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3929 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3930}
3931
648dfaa7
MG		 3932static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3933{
3934 struct kvm_segment var;
3935 u32 ar;
3936
3937 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3938 var.dpl = 0x3;
0647f4aa
GN		 3939 if (seg == VCPU_SREG_CS)
3940 var.type = 0x3;
648dfaa7
MG		 3941 ar = vmx_segment_access_rights(&var);
3942
3943 if (var.base != (var.selector << 4))
3944 return false;
89efbed0 3945 if (var.limit != 0xffff)
648dfaa7 3946 return false;
07f42f5f 3947 if (ar != 0xf3)
648dfaa7
MG		 3948 return false;
3949
3950 return true;
3951}
3952
3953static bool code_segment_valid(struct kvm_vcpu *vcpu)
3954{
3955 struct kvm_segment cs;
3956 unsigned int cs_rpl;
3957
3958 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3959 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3960
1872a3f4
AK		 3961 if (cs.unusable)
3962 return false;
4d283ec9 3963 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3964 return false;
3965 if (!cs.s)
3966 return false;
4d283ec9 3967 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3968 if (cs.dpl > cs_rpl)
3969 return false;
1872a3f4 3970 } else {
648dfaa7
MG		 3971 if (cs.dpl != cs_rpl)
3972 return false;
3973 }
3974 if (!cs.present)
3975 return false;
3976
3977 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3978 return true;
3979}
3980
3981static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3982{
3983 struct kvm_segment ss;
3984 unsigned int ss_rpl;
3985
3986 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3987 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3988
1872a3f4
AK		 3989 if (ss.unusable)
3990 return true;
3991 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3992 return false;
3993 if (!ss.s)
3994 return false;
3995 if (ss.dpl != ss_rpl) /* DPL != RPL */
3996 return false;
3997 if (!ss.present)
3998 return false;
3999
4000 return true;
4001}
4002
4003static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4004{
4005 struct kvm_segment var;
4006 unsigned int rpl;
4007
4008 vmx_get_segment(vcpu, &var, seg);
b32a9918 4009 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 4010
1872a3f4
AK		 4011 if (var.unusable)
4012 return true;
648dfaa7
MG		 4013 if (!var.s)
4014 return false;
4015 if (!var.present)
4016 return false;
4d283ec9 4017 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 4018 if (var.dpl < rpl) /* DPL < RPL */
4019 return false;
4020 }
4021
4022 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4023 * rights flags
4024 */
4025 return true;
4026}
4027
4028static bool tr_valid(struct kvm_vcpu *vcpu)
4029{
4030 struct kvm_segment tr;
4031
4032 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4033
1872a3f4
AK		 4034 if (tr.unusable)
4035 return false;
b32a9918 4036 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 4037 return false;
1872a3f4 4038 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 4039 return false;
4040 if (!tr.present)
4041 return false;
4042
4043 return true;
4044}
4045
4046static bool ldtr_valid(struct kvm_vcpu *vcpu)
4047{
4048 struct kvm_segment ldtr;
4049
4050 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4051
1872a3f4
AK		 4052 if (ldtr.unusable)
4053 return true;
b32a9918 4054 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 4055 return false;
4056 if (ldtr.type != 2)
4057 return false;
4058 if (!ldtr.present)
4059 return false;
4060
4061 return true;
4062}
4063
4064static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4065{
4066 struct kvm_segment cs, ss;
4067
4068 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4069 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4070
b32a9918
NA		 4071 return ((cs.selector & SEGMENT_RPL_MASK) ==
4072 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 4073}
4074
4075/*
4076 * Check if guest state is valid. Returns true if valid, false if
4077 * not.
4078 * We assume that registers are always usable
4079 */
4080static bool guest_state_valid(struct kvm_vcpu *vcpu)
4081{
c5e97c80
GN		 4082 if (enable_unrestricted_guest)
4083 return true;
4084
648dfaa7 4085 /* real mode guest state checks */
f13882d8 4086 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 4087 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4088 return false;
4089 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4090 return false;
4091 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4092 return false;
4093 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4094 return false;
4095 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4096 return false;
4097 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4098 return false;
4099 } else {
4100 /* protected mode guest state checks */
4101 if (!cs_ss_rpl_check(vcpu))
4102 return false;
4103 if (!code_segment_valid(vcpu))
4104 return false;
4105 if (!stack_segment_valid(vcpu))
4106 return false;
4107 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4108 return false;
4109 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4110 return false;
4111 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4112 return false;
4113 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4114 return false;
4115 if (!tr_valid(vcpu))
4116 return false;
4117 if (!ldtr_valid(vcpu))
4118 return false;
4119 }
4120 /* TODO:
4121 * - Add checks on RIP
4122 * - Add checks on RFLAGS
4123 */
4124
4125 return true;
4126}
4127
d77c26fc 4128static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4129{
40dcaa9f 4130 gfn_t fn;
195aefde 4131 u16 data = 0;
1f755a82 4132 int idx, r;
6aa8b732 4133
40dcaa9f 4134 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4135 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 4136 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4137 if (r < 0)
10589a46 4138 goto out;
195aefde 4139 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4140 r = kvm_write_guest_page(kvm, fn++, &data,
4141 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4142 if (r < 0)
10589a46 4143 goto out;
195aefde
IE		 4144 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4145 if (r < 0)
10589a46 4146 goto out;
195aefde
IE		 4147 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4148 if (r < 0)
10589a46 4149 goto out;
195aefde 4150 data = ~0;
10589a46
MT		 4151 r = kvm_write_guest_page(kvm, fn, &data,
4152 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4153 sizeof(u8));
10589a46 4154out:
40dcaa9f 4155 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4156 return r;
6aa8b732
AK		 4157}
4158
b7ebfb05
SY		 4159static int init_rmode_identity_map(struct kvm *kvm)
4160{
f51770ed 4161 int i, idx, r = 0;
b7ebfb05
SY		 4162 pfn_t identity_map_pfn;
4163 u32 tmp;
4164
089d034e 4165 if (!enable_ept)
f51770ed 4166 return 0;
a255d479
TC		 4167
4168 /* Protect kvm->arch.ept_identity_pagetable_done. */
4169 mutex_lock(&kvm->slots_lock);
4170
f51770ed 4171 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4172 goto out2;
a255d479 4173
b927a3ce 4174 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4175
4176 r = alloc_identity_pagetable(kvm);
f51770ed 4177 if (r < 0)
a255d479
TC		 4178 goto out2;
4179
40dcaa9f 4180 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4181 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4182 if (r < 0)
4183 goto out;
4184 /* Set up identity-mapping pagetable for EPT in real mode */
4185 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4186 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4187 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4188 r = kvm_write_guest_page(kvm, identity_map_pfn,
4189 &tmp, i * sizeof(tmp), sizeof(tmp));
4190 if (r < 0)
4191 goto out;
4192 }
4193 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4194
b7ebfb05 4195out:
40dcaa9f 4196 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4197
4198out2:
4199 mutex_unlock(&kvm->slots_lock);
f51770ed 4200 return r;
b7ebfb05
SY		 4201}
4202
6aa8b732
AK		 4203static void seg_setup(int seg)
4204{
772e0318 4205 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4206 unsigned int ar;
6aa8b732
AK		 4207
4208 vmcs_write16(sf->selector, 0);
4209 vmcs_writel(sf->base, 0);
4210 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4211 ar = 0x93;
4212 if (seg == VCPU_SREG_CS)
4213 ar |= 0x08; /* code segment */
3a624e29
NK		 4214
4215 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4216}
4217
f78e0e2e
SY		 4218static int alloc_apic_access_page(struct kvm *kvm)
4219{
4484141a 4220 struct page *page;
f78e0e2e
SY		 4221 struct kvm_userspace_memory_region kvm_userspace_mem;
4222 int r = 0;
4223
79fac95e 4224 mutex_lock(&kvm->slots_lock);
c24ae0dc 4225 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4226 goto out;
4227 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4228 kvm_userspace_mem.flags = 0;
73a6d941 4229 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4230 kvm_userspace_mem.memory_size = PAGE_SIZE;
9da0e4d5 4231 r = __x86_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4232 if (r)
4233 goto out;
72dc67a6 4234
73a6d941 4235 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4236 if (is_error_page(page)) {
4237 r = -EFAULT;
4238 goto out;
4239 }
4240
c24ae0dc
TC		 4241 /*
4242 * Do not pin the page in memory, so that memory hot-unplug
4243 * is able to migrate it.
4244 */
4245 put_page(page);
4246 kvm->arch.apic_access_page_done = true;
f78e0e2e 4247out:
79fac95e 4248 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4249 return r;
4250}
4251
b7ebfb05
SY		 4252static int alloc_identity_pagetable(struct kvm *kvm)
4253{
a255d479
TC		 4254 /* Called with kvm->slots_lock held. */
4255
b7ebfb05
SY		 4256 struct kvm_userspace_memory_region kvm_userspace_mem;
4257 int r = 0;
4258
a255d479
TC		 4259 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4260
b7ebfb05
SY		 4261 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4262 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4263 kvm_userspace_mem.guest_phys_addr =
4264 kvm->arch.ept_identity_map_addr;
b7ebfb05 4265 kvm_userspace_mem.memory_size = PAGE_SIZE;
9da0e4d5 4266 r = __x86_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4267
b7ebfb05
SY		 4268 return r;
4269}
4270
2384d2b3
SY		 4271static void allocate_vpid(struct vcpu_vmx *vmx)
4272{
4273 int vpid;
4274
4275 vmx->vpid = 0;
919818ab 4276 if (!enable_vpid)
2384d2b3
SY		 4277 return;
4278 spin_lock(&vmx_vpid_lock);
4279 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4280 if (vpid < VMX_NR_VPIDS) {
4281 vmx->vpid = vpid;
4282 __set_bit(vpid, vmx_vpid_bitmap);
4283 }
4284 spin_unlock(&vmx_vpid_lock);
4285}
4286
cdbecfc3
LJ		 4287static void free_vpid(struct vcpu_vmx *vmx)
4288{
4289 if (!enable_vpid)
4290 return;
4291 spin_lock(&vmx_vpid_lock);
4292 if (vmx->vpid != 0)
4293 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4294 spin_unlock(&vmx_vpid_lock);
4295}
4296
8d14695f
YZ		 4297#define MSR_TYPE_R 1
4298#define MSR_TYPE_W 2
4299static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4300 u32 msr, int type)
25c5f225 4301{
3e7c73e9 4302 int f = sizeof(unsigned long);
25c5f225
SY		 4303
4304 if (!cpu_has_vmx_msr_bitmap())
4305 return;
4306
4307 /*
4308 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4309 * have the write-low and read-high bitmap offsets the wrong way round.
4310 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4311 */
25c5f225 4312 if (msr <= 0x1fff) {
8d14695f
YZ		 4313 if (type & MSR_TYPE_R)
4314 /* read-low */
4315 __clear_bit(msr, msr_bitmap + 0x000 / f);
4316
4317 if (type & MSR_TYPE_W)
4318 /* write-low */
4319 __clear_bit(msr, msr_bitmap + 0x800 / f);
4320
25c5f225
SY		 4321 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4322 msr &= 0x1fff;
8d14695f
YZ		 4323 if (type & MSR_TYPE_R)
4324 /* read-high */
4325 __clear_bit(msr, msr_bitmap + 0x400 / f);
4326
4327 if (type & MSR_TYPE_W)
4328 /* write-high */
4329 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4330
4331 }
4332}
4333
4334static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4335 u32 msr, int type)
4336{
4337 int f = sizeof(unsigned long);
4338
4339 if (!cpu_has_vmx_msr_bitmap())
4340 return;
4341
4342 /*
4343 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4344 * have the write-low and read-high bitmap offsets the wrong way round.
4345 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4346 */
4347 if (msr <= 0x1fff) {
4348 if (type & MSR_TYPE_R)
4349 /* read-low */
4350 __set_bit(msr, msr_bitmap + 0x000 / f);
4351
4352 if (type & MSR_TYPE_W)
4353 /* write-low */
4354 __set_bit(msr, msr_bitmap + 0x800 / f);
4355
4356 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4357 msr &= 0x1fff;
4358 if (type & MSR_TYPE_R)
4359 /* read-high */
4360 __set_bit(msr, msr_bitmap + 0x400 / f);
4361
4362 if (type & MSR_TYPE_W)
4363 /* write-high */
4364 __set_bit(msr, msr_bitmap + 0xc00 / f);
4365
25c5f225 4366 }
25c5f225
SY		 4367}
4368
f2b93280
WV		 4369/*
4370 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4371 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4372 */
4373static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4374 unsigned long *msr_bitmap_nested,
4375 u32 msr, int type)
4376{
4377 int f = sizeof(unsigned long);
4378
4379 if (!cpu_has_vmx_msr_bitmap()) {
4380 WARN_ON(1);
4381 return;
4382 }
4383
4384 /*
4385 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4386 * have the write-low and read-high bitmap offsets the wrong way round.
4387 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4388 */
4389 if (msr <= 0x1fff) {
4390 if (type & MSR_TYPE_R &&
4391 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4392 /* read-low */
4393 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4394
4395 if (type & MSR_TYPE_W &&
4396 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4397 /* write-low */
4398 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4399
4400 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4401 msr &= 0x1fff;
4402 if (type & MSR_TYPE_R &&
4403 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4404 /* read-high */
4405 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4406
4407 if (type & MSR_TYPE_W &&
4408 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4409 /* write-high */
4410 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4411
4412 }
4413}
4414
5897297b
AK		 4415static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4416{
4417 if (!longmode_only)
8d14695f
YZ		 4418 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4419 msr, MSR_TYPE_R | MSR_TYPE_W);
4420 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4421 msr, MSR_TYPE_R | MSR_TYPE_W);
4422}
4423
4424static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4425{
4426 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4427 msr, MSR_TYPE_R);
4428 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4429 msr, MSR_TYPE_R);
4430}
4431
4432static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4433{
4434 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4435 msr, MSR_TYPE_R);
4436 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4437 msr, MSR_TYPE_R);
4438}
4439
4440static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4441{
4442 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4443 msr, MSR_TYPE_W);
4444 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4445 msr, MSR_TYPE_W);
5897297b
AK		 4446}
4447
d50ab6c1
PB		 4448static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4449{
35754c98 4450 return enable_apicv && lapic_in_kernel(vcpu);
d50ab6c1
PB		 4451}
4452
705699a1
WV		 4453static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4454{
4455 struct vcpu_vmx *vmx = to_vmx(vcpu);
4456 int max_irr;
4457 void *vapic_page;
4458 u16 status;
4459
4460 if (vmx->nested.pi_desc &&
4461 vmx->nested.pi_pending) {
4462 vmx->nested.pi_pending = false;
4463 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4464 return 0;
4465
4466 max_irr = find_last_bit(
4467 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4468
4469 if (max_irr == 256)
4470 return 0;
4471
4472 vapic_page = kmap(vmx->nested.virtual_apic_page);
4473 if (!vapic_page) {
4474 WARN_ON(1);
4475 return -ENOMEM;
4476 }
4477 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4478 kunmap(vmx->nested.virtual_apic_page);
4479
4480 status = vmcs_read16(GUEST_INTR_STATUS);
4481 if ((u8)max_irr > ((u8)status & 0xff)) {
4482 status &= ~0xff;
4483 status |= (u8)max_irr;
4484 vmcs_write16(GUEST_INTR_STATUS, status);
4485 }
4486 }
4487 return 0;
4488}
4489
21bc8dc5
RK		 4490static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4491{
4492#ifdef CONFIG_SMP
4493 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6
FW		 4494 struct vcpu_vmx *vmx = to_vmx(vcpu);
4495
4496 /*
4497 * Currently, we don't support urgent interrupt,
4498 * all interrupts are recognized as non-urgent
4499 * interrupt, so we cannot post interrupts when
4500 * 'SN' is set.
4501 *
4502 * If the vcpu is in guest mode, it means it is
4503 * running instead of being scheduled out and
4504 * waiting in the run queue, and that's the only
4505 * case when 'SN' is set currently, warning if
4506 * 'SN' is set.
4507 */
4508 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4509
21bc8dc5
RK		 4510 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4511 POSTED_INTR_VECTOR);
4512 return true;
4513 }
4514#endif
4515 return false;
4516}
4517
705699a1
WV		 4518static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4519 int vector)
4520{
4521 struct vcpu_vmx *vmx = to_vmx(vcpu);
4522
4523 if (is_guest_mode(vcpu) &&
4524 vector == vmx->nested.posted_intr_nv) {
4525 /* the PIR and ON have been set by L1. */
21bc8dc5 4526 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV		 4527 /*
4528 * If a posted intr is not recognized by hardware,
4529 * we will accomplish it in the next vmentry.
4530 */
4531 vmx->nested.pi_pending = true;
4532 kvm_make_request(KVM_REQ_EVENT, vcpu);
4533 return 0;
4534 }
4535 return -1;
4536}
a20ed54d
YZ		 4537/*
4538 * Send interrupt to vcpu via posted interrupt way.
4539 * 1. If target vcpu is running(non-root mode), send posted interrupt
4540 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4541 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4542 * interrupt from PIR in next vmentry.
4543 */
4544static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4545{
4546 struct vcpu_vmx *vmx = to_vmx(vcpu);
4547 int r;
4548
705699a1
WV		 4549 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4550 if (!r)
4551 return;
4552
a20ed54d
YZ		 4553 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4554 return;
4555
4556 r = pi_test_and_set_on(&vmx->pi_desc);
4557 kvm_make_request(KVM_REQ_EVENT, vcpu);
21bc8dc5 4558 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ		 4559 kvm_vcpu_kick(vcpu);
4560}
4561
4562static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4563{
4564 struct vcpu_vmx *vmx = to_vmx(vcpu);
4565
4566 if (!pi_test_and_clear_on(&vmx->pi_desc))
4567 return;
4568
4569 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4570}
4571
4572static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4573{
4574 return;
4575}
4576
a3a8ff8e
NHE		 4577/*
4578 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4579 * will not change in the lifetime of the guest.
4580 * Note that host-state that does change is set elsewhere. E.g., host-state
4581 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4582 */
a547c6db 4583static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4584{
4585 u32 low32, high32;
4586 unsigned long tmpl;
4587 struct desc_ptr dt;
d974baa3 4588 unsigned long cr4;
a3a8ff8e 4589
b1a74bf8 4590 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4591 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4592
d974baa3 4593 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 4594 cr4 = cr4_read_shadow();
d974baa3
AL		 4595 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4596 vmx->host_state.vmcs_host_cr4 = cr4;
4597
a3a8ff8e 4598 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4599#ifdef CONFIG_X86_64
4600 /*
4601 * Load null selectors, so we can avoid reloading them in
4602 * __vmx_load_host_state(), in case userspace uses the null selectors
4603 * too (the expected case).
4604 */
4605 vmcs_write16(HOST_DS_SELECTOR, 0);
4606 vmcs_write16(HOST_ES_SELECTOR, 0);
4607#else
a3a8ff8e
NHE		 4608 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4609 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4610#endif
a3a8ff8e
NHE		 4611 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4612 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4613
4614 native_store_idt(&dt);
4615 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4616 vmx->host_idt_base = dt.address;
a3a8ff8e 4617
83287ea4 4618 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4619
4620 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4621 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4622 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4623 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4624
4625 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4626 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4627 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4628 }
4629}
4630
bf8179a0
NHE		 4631static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4632{
4633 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4634 if (enable_ept)
4635 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4636 if (is_guest_mode(&vmx->vcpu))
4637 vmx->vcpu.arch.cr4_guest_owned_bits &=
4638 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4639 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4640}
4641
01e439be
YZ		 4642static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4643{
4644 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4645
35754c98 4646 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
01e439be
YZ		 4647 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4648 return pin_based_exec_ctrl;
4649}
4650
bf8179a0
NHE		 4651static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4652{
4653 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4654
4655 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4656 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4657
35754c98 4658 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE		 4659 exec_control &= ~CPU_BASED_TPR_SHADOW;
4660#ifdef CONFIG_X86_64
4661 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4662 CPU_BASED_CR8_LOAD_EXITING;
4663#endif
4664 }
4665 if (!enable_ept)
4666 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4667 CPU_BASED_CR3_LOAD_EXITING |
4668 CPU_BASED_INVLPG_EXITING;
4669 return exec_control;
4670}
4671
4672static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4673{
4674 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 4675 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE		 4676 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4677 if (vmx->vpid == 0)
4678 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4679 if (!enable_ept) {
4680 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4681 enable_unrestricted_guest = 0;
ad756a16
MJ		 4682 /* Enable INVPCID for non-ept guests may cause performance regression. */
4683 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4684 }
4685 if (!enable_unrestricted_guest)
4686 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4687 if (!ple_gap)
4688 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
35754c98 4689 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
c7c9c56c
YZ		 4690 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4691 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4692 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4693 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4694 (handle_vmptrld).
4695 We can NOT enable shadow_vmcs here because we don't have yet
4696 a current VMCS12
4697 */
4698 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4699 /* PML is enabled/disabled in creating/destorying vcpu */
4700 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4701
8b3e34e4
XG		 4702 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4703 exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4704
bf8179a0
NHE		 4705 return exec_control;
4706}
4707
ce88decf
XG		 4708static void ept_set_mmio_spte_mask(void)
4709{
4710 /*
4711 * EPT Misconfigurations can be generated if the value of bits 2:0
4712 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4713 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4714 * spte.
4715 */
885032b9 4716 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4717}
4718
f53cd63c 4719#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4720/*
4721 * Sets up the vmcs for emulated real mode.
4722 */
8b9cf98c 4723static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4724{
2e4ce7f5 4725#ifdef CONFIG_X86_64
6aa8b732 4726 unsigned long a;
2e4ce7f5 4727#endif
6aa8b732 4728 int i;
6aa8b732 4729
6aa8b732 4730 /* I/O */
3e7c73e9
AK		 4731 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4732 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4733
4607c2d7
AG		 4734 if (enable_shadow_vmcs) {
4735 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4736 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4737 }
25c5f225 4738 if (cpu_has_vmx_msr_bitmap())
5897297b 4739 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4740
6aa8b732
AK		 4741 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4742
6aa8b732 4743 /* Control */
01e439be 4744 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4745
bf8179a0 4746 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4747
8b3e34e4 4748 if (cpu_has_secondary_exec_ctrls())
bf8179a0
NHE		 4749 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4750 vmx_secondary_exec_control(vmx));
f78e0e2e 4751
35754c98 4752 if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
c7c9c56c
YZ		 4753 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4754 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4755 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4756 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4757
4758 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4759
4760 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4761 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4762 }
4763
4b8d54f9
ZE		 4764 if (ple_gap) {
4765 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4766 vmx->ple_window = ple_window;
4767 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4768 }
4769
c3707958
XG		 4770 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4771 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4772 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4773
9581d442
AK		 4774 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4775 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4776 vmx_set_constant_host_state(vmx);
05b3e0c2 4777#ifdef CONFIG_X86_64
6aa8b732
AK		 4778 rdmsrl(MSR_FS_BASE, a);
4779 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4780 rdmsrl(MSR_GS_BASE, a);
4781 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4782#else
4783 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4784 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4785#endif
4786
2cc51560
ED		 4787 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4788 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4789 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4790 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4791 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4792
74545705
RK		 4793 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4794 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4795
03916db9 4796 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4797 u32 index = vmx_msr_index[i];
4798 u32 data_low, data_high;
a2fa3e9f 4799 int j = vmx->nmsrs;
6aa8b732
AK		 4800
4801 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4802 continue;
432bd6cb
AK		 4803 if (wrmsr_safe(index, data_low, data_high) < 0)
4804 continue;
26bb0981
AK		 4805 vmx->guest_msrs[j].index = i;
4806 vmx->guest_msrs[j].data = 0;
d5696725 4807 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4808 ++vmx->nmsrs;
6aa8b732 4809 }
6aa8b732 4810
2961e876
GN		 4811
4812 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4813
4814 /* 22.2.1, 20.8.1 */
2961e876 4815 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4816
e00c8cf2 4817 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4818 set_cr4_guest_host_mask(vmx);
e00c8cf2 4819
f53cd63c
WL		 4820 if (vmx_xsaves_supported())
4821 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4822
e00c8cf2
AK		 4823 return 0;
4824}
4825
d28bc9dd 4826static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4827{
4828 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4829 struct msr_data apic_base_msr;
d28bc9dd 4830 u64 cr0;
e00c8cf2 4831
7ffd92c5 4832 vmx->rmode.vm86_active = 0;
e00c8cf2 4833
3b86cd99
JK		 4834 vmx->soft_vnmi_blocked = 0;
4835
ad312c7c 4836 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 4837 kvm_set_cr8(vcpu, 0);
4838
4839 if (!init_event) {
4840 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4841 MSR_IA32_APICBASE_ENABLE;
4842 if (kvm_vcpu_is_reset_bsp(vcpu))
4843 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4844 apic_base_msr.host_initiated = true;
4845 kvm_set_apic_base(vcpu, &apic_base_msr);
4846 }
e00c8cf2 4847
2fb92db1
AK		 4848 vmx_segment_cache_clear(vmx);
4849
5706be0d 4850 seg_setup(VCPU_SREG_CS);
66450a21 4851 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4852 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4853
4854 seg_setup(VCPU_SREG_DS);
4855 seg_setup(VCPU_SREG_ES);
4856 seg_setup(VCPU_SREG_FS);
4857 seg_setup(VCPU_SREG_GS);
4858 seg_setup(VCPU_SREG_SS);
4859
4860 vmcs_write16(GUEST_TR_SELECTOR, 0);
4861 vmcs_writel(GUEST_TR_BASE, 0);
4862 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4863 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4864
4865 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4866 vmcs_writel(GUEST_LDTR_BASE, 0);
4867 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4868 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4869
d28bc9dd
NA		 4870 if (!init_event) {
4871 vmcs_write32(GUEST_SYSENTER_CS, 0);
4872 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4873 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4874 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4875 }
e00c8cf2
AK		 4876
4877 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4878 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4879
e00c8cf2
AK		 4880 vmcs_writel(GUEST_GDTR_BASE, 0);
4881 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4882
4883 vmcs_writel(GUEST_IDTR_BASE, 0);
4884 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4885
443381a8 4886 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4887 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4888 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4889
e00c8cf2
AK		 4890 setup_msrs(vmx);
4891
6aa8b732
AK		 4892 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4893
d28bc9dd 4894 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4895 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4896 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4897 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4898 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4899 vmcs_write32(TPR_THRESHOLD, 0);
4900 }
4901
a73896cb 4902 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4903
35754c98 4904 if (vmx_cpu_uses_apicv(vcpu))
01e439be
YZ		 4905 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4906
2384d2b3
SY		 4907 if (vmx->vpid != 0)
4908 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4909
d28bc9dd
NA		 4910 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4911 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4912 vmx->vcpu.arch.cr0 = cr0;
4913 vmx_set_cr4(vcpu, 0);
4914 if (!init_event)
4915 vmx_set_efer(vcpu, 0);
4916 vmx_fpu_activate(vcpu);
4917 update_exception_bitmap(vcpu);
6aa8b732 4918
b9d762fa 4919 vpid_sync_context(vmx);
6aa8b732
AK		 4920}
4921
b6f1250e
NHE		 4922/*
4923 * In nested virtualization, check if L1 asked to exit on external interrupts.
4924 * For most existing hypervisors, this will always return true.
4925 */
4926static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4927{
4928 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4929 PIN_BASED_EXT_INTR_MASK;
4930}
4931
77b0f5d6
BD		 4932/*
4933 * In nested virtualization, check if L1 has set
4934 * VM_EXIT_ACK_INTR_ON_EXIT
4935 */
4936static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4937{
4938 return get_vmcs12(vcpu)->vm_exit_controls &
4939 VM_EXIT_ACK_INTR_ON_EXIT;
4940}
4941
ea8ceb83
JK		 4942static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4943{
4944 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4945 PIN_BASED_NMI_EXITING;
4946}
4947
c9a7953f 4948static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4949{
4950 u32 cpu_based_vm_exec_control;
730dca42 4951
3b86cd99
JK		 4952 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4953 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4954 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4955}
4956
c9a7953f 4957static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4958{
4959 u32 cpu_based_vm_exec_control;
4960
c9a7953f
JK		 4961 if (!cpu_has_virtual_nmis() ||
4962 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4963 enable_irq_window(vcpu);
4964 return;
4965 }
3b86cd99
JK		 4966
4967 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4968 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4969 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4970}
4971
66fd3f7f 4972static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4973{
9c8cba37 4974 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4975 uint32_t intr;
4976 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4977
229456fc 4978 trace_kvm_inj_virq(irq);
2714d1d3 4979
fa89a817 4980 ++vcpu->stat.irq_injections;
7ffd92c5 4981 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4982 int inc_eip = 0;
4983 if (vcpu->arch.interrupt.soft)
4984 inc_eip = vcpu->arch.event_exit_inst_len;
4985 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4986 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4987 return;
4988 }
66fd3f7f
GN		 4989 intr = irq | INTR_INFO_VALID_MASK;
4990 if (vcpu->arch.interrupt.soft) {
4991 intr |= INTR_TYPE_SOFT_INTR;
4992 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4993 vmx->vcpu.arch.event_exit_inst_len);
4994 } else
4995 intr |= INTR_TYPE_EXT_INTR;
4996 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4997}
4998
f08864b4
SY		 4999static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5000{
66a5a347
JK		 5001 struct vcpu_vmx *vmx = to_vmx(vcpu);
5002
0b6ac343
NHE		 5003 if (is_guest_mode(vcpu))
5004 return;
5005
3b86cd99
JK		 5006 if (!cpu_has_virtual_nmis()) {
5007 /*
5008 * Tracking the NMI-blocked state in software is built upon
5009 * finding the next open IRQ window. This, in turn, depends on
5010 * well-behaving guests: They have to keep IRQs disabled at
5011 * least as long as the NMI handler runs. Otherwise we may
5012 * cause NMI nesting, maybe breaking the guest. But as this is
5013 * highly unlikely, we can live with the residual risk.
5014 */
5015 vmx->soft_vnmi_blocked = 1;
5016 vmx->vnmi_blocked_time = 0;
5017 }
5018
487b391d 5019 ++vcpu->stat.nmi_injections;
9d58b931 5020 vmx->nmi_known_unmasked = false;
7ffd92c5 5021 if (vmx->rmode.vm86_active) {
71f9833b 5022 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 5023 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 5024 return;
5025 }
f08864b4
SY		 5026 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5027 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 5028}
5029
3cfc3092
JK		 5030static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5031{
5032 if (!cpu_has_virtual_nmis())
5033 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 5034 if (to_vmx(vcpu)->nmi_known_unmasked)
5035 return false;
c332c83a 5036 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 5037}
5038
5039static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5040{
5041 struct vcpu_vmx *vmx = to_vmx(vcpu);
5042
5043 if (!cpu_has_virtual_nmis()) {
5044 if (vmx->soft_vnmi_blocked != masked) {
5045 vmx->soft_vnmi_blocked = masked;
5046 vmx->vnmi_blocked_time = 0;
5047 }
5048 } else {
9d58b931 5049 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 5050 if (masked)
5051 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5052 GUEST_INTR_STATE_NMI);
5053 else
5054 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5055 GUEST_INTR_STATE_NMI);
5056 }
5057}
5058
2505dc9f
JK		 5059static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5060{
b6b8a145
JK		 5061 if (to_vmx(vcpu)->nested.nested_run_pending)
5062 return 0;
ea8ceb83 5063
2505dc9f
JK		 5064 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5065 return 0;
5066
5067 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5068 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5069 | GUEST_INTR_STATE_NMI));
5070}
5071
78646121
GN		 5072static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5073{
b6b8a145
JK		 5074 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5075 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 5076 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5077 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 5078}
5079
cbc94022
IE		 5080static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5081{
5082 int ret;
5083 struct kvm_userspace_memory_region tss_mem = {
6fe63979 5084 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 5085 .guest_phys_addr = addr,
5086 .memory_size = PAGE_SIZE * 3,
5087 .flags = 0,
5088 };
5089
9da0e4d5 5090 ret = x86_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 5091 if (ret)
5092 return ret;
bfc6d222 5093 kvm->arch.tss_addr = addr;
1f755a82 5094 return init_rmode_tss(kvm);
cbc94022
IE		 5095}
5096
0ca1b4f4 5097static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 5098{
77ab6db0 5099 switch (vec) {
77ab6db0 5100 case BP_VECTOR:
c573cd22
JK		 5101 /*
5102 * Update instruction length as we may reinject the exception
5103 * from user space while in guest debugging mode.
5104 */
5105 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5106 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 5107 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 5108 return false;
5109 /* fall through */
5110 case DB_VECTOR:
5111 if (vcpu->guest_debug &
5112 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5113 return false;
d0bfb940
JK		 5114 /* fall through */
5115 case DE_VECTOR:
77ab6db0
JK		 5116 case OF_VECTOR:
5117 case BR_VECTOR:
5118 case UD_VECTOR:
5119 case DF_VECTOR:
5120 case SS_VECTOR:
5121 case GP_VECTOR:
5122 case MF_VECTOR:
0ca1b4f4
GN		 5123 return true;
5124 break;
77ab6db0 5125 }
0ca1b4f4
GN		 5126 return false;
5127}
5128
5129static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5130 int vec, u32 err_code)
5131{
5132 /*
5133 * Instruction with address size override prefix opcode 0x67
5134 * Cause the #SS fault with 0 error code in VM86 mode.
5135 */
5136 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5137 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5138 if (vcpu->arch.halt_request) {
5139 vcpu->arch.halt_request = 0;
5cb56059 5140 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 5141 }
5142 return 1;
5143 }
5144 return 0;
5145 }
5146
5147 /*
5148 * Forward all other exceptions that are valid in real mode.
5149 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5150 * the required debugging infrastructure rework.
5151 */
5152 kvm_queue_exception(vcpu, vec);
5153 return 1;
6aa8b732
AK		 5154}
5155
a0861c02
AK		 5156/*
5157 * Trigger machine check on the host. We assume all the MSRs are already set up
5158 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5159 * We pass a fake environment to the machine check handler because we want
5160 * the guest to be always treated like user space, no matter what context
5161 * it used internally.
5162 */
5163static void kvm_machine_check(void)
5164{
5165#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5166 struct pt_regs regs = {
5167 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5168 .flags = X86_EFLAGS_IF,
5169 };
5170
5171 do_machine_check(&regs, 0);
5172#endif
5173}
5174
851ba692 5175static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 5176{
5177 /* already handled by vcpu_run */
5178 return 1;
5179}
5180
851ba692 5181static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5182{
1155f76a 5183 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5184 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5185 u32 intr_info, ex_no, error_code;
42dbaa5a 5186 unsigned long cr2, rip, dr6;
6aa8b732
AK		 5187 u32 vect_info;
5188 enum emulation_result er;
5189
1155f76a 5190 vect_info = vmx->idt_vectoring_info;
88786475 5191 intr_info = vmx->exit_intr_info;
6aa8b732 5192
a0861c02 5193 if (is_machine_check(intr_info))
851ba692 5194 return handle_machine_check(vcpu);
a0861c02 5195
e4a41889 5196 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 5197 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 5198
5199 if (is_no_device(intr_info)) {
5fd86fcf 5200 vmx_fpu_activate(vcpu);
2ab455cc
AL		 5201 return 1;
5202 }
5203
7aa81cc0 5204 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK		 5205 if (is_guest_mode(vcpu)) {
5206 kvm_queue_exception(vcpu, UD_VECTOR);
5207 return 1;
5208 }
51d8b661 5209 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5210 if (er != EMULATE_DONE)
7ee5d940 5211 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 5212 return 1;
5213 }
5214
6aa8b732 5215 error_code = 0;
2e11384c 5216 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5217 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 5218
5219 /*
5220 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5221 * MMIO, it is better to report an internal error.
5222 * See the comments in vmx_handle_exit.
5223 */
5224 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5225 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5226 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5227 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5228 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 5229 vcpu->run->internal.data[0] = vect_info;
5230 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5231 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 5232 return 0;
5233 }
5234
6aa8b732 5235 if (is_page_fault(intr_info)) {
1439442c 5236 /* EPT won't cause page fault directly */
cf3ace79 5237 BUG_ON(enable_ept);
6aa8b732 5238 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5239 trace_kvm_page_fault(cr2, error_code);
5240
3298b75c 5241 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5242 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5243 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5244 }
5245
d0bfb940 5246 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5247
5248 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5249 return handle_rmode_exception(vcpu, ex_no, error_code);
5250
42dbaa5a
JK		 5251 switch (ex_no) {
5252 case DB_VECTOR:
5253 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5254 if (!(vcpu->guest_debug &
5255 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5256 vcpu->arch.dr6 &= ~15;
6f43ed01 5257 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5258 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5259 skip_emulated_instruction(vcpu);
5260
42dbaa5a
JK		 5261 kvm_queue_exception(vcpu, DB_VECTOR);
5262 return 1;
5263 }
5264 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5265 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5266 /* fall through */
5267 case BP_VECTOR:
c573cd22
JK		 5268 /*
5269 * Update instruction length as we may reinject #BP from
5270 * user space while in guest debugging mode. Reading it for
5271 * #DB as well causes no harm, it is not used in that case.
5272 */
5273 vmx->vcpu.arch.event_exit_inst_len =
5274 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5275 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5276 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5277 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5278 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5279 break;
5280 default:
d0bfb940
JK		 5281 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5282 kvm_run->ex.exception = ex_no;
5283 kvm_run->ex.error_code = error_code;
42dbaa5a 5284 break;
6aa8b732 5285 }
6aa8b732
AK		 5286 return 0;
5287}
5288
851ba692 5289static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5290{
1165f5fe 5291 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5292 return 1;
5293}
5294
851ba692 5295static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5296{
851ba692 5297 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5298 return 0;
5299}
6aa8b732 5300
851ba692 5301static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5302{
bfdaab09 5303 unsigned long exit_qualification;
34c33d16 5304 int size, in, string;
039576c0 5305 unsigned port;
6aa8b732 5306
bfdaab09 5307 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5308 string = (exit_qualification & 16) != 0;
cf8f70bf 5309 in = (exit_qualification & 8) != 0;
e70669ab 5310
cf8f70bf 5311 ++vcpu->stat.io_exits;
e70669ab 5312
cf8f70bf 5313 if (string || in)
51d8b661 5314 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5315
cf8f70bf
GN		 5316 port = exit_qualification >> 16;
5317 size = (exit_qualification & 7) + 1;
e93f36bc 5318 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5319
5320 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5321}
5322
102d8325
IM		 5323static void
5324vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5325{
5326 /*
5327 * Patch in the VMCALL instruction:
5328 */
5329 hypercall[0] = 0x0f;
5330 hypercall[1] = 0x01;
5331 hypercall[2] = 0xc1;
102d8325
IM		 5332}
5333
b9c237bb 5334static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5335{
5336 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5337 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5338
b9c237bb 5339 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5340 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5341 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5342 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5343 return (val & always_on) == always_on;
5344}
5345
0fa06071 5346/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5347static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5348{
eeadf9e7 5349 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5350 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5351 unsigned long orig_val = val;
5352
eeadf9e7
NHE		 5353 /*
5354 * We get here when L2 changed cr0 in a way that did not change
5355 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5356 * but did change L0 shadowed bits. So we first calculate the
5357 * effective cr0 value that L1 would like to write into the
5358 * hardware. It consists of the L2-owned bits from the new
5359 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5360 */
1a0d74e6
JK		 5361 val = (val & ~vmcs12->cr0_guest_host_mask) |
5362 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5363
b9c237bb 5364 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5365 return 1;
1a0d74e6
JK		 5366
5367 if (kvm_set_cr0(vcpu, val))
5368 return 1;
5369 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5370 return 0;
1a0d74e6
JK		 5371 } else {
5372 if (to_vmx(vcpu)->nested.vmxon &&
5373 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5374 return 1;
eeadf9e7 5375 return kvm_set_cr0(vcpu, val);
1a0d74e6 5376 }
eeadf9e7
NHE		 5377}
5378
5379static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5380{
5381 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5382 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5383 unsigned long orig_val = val;
5384
5385 /* analogously to handle_set_cr0 */
5386 val = (val & ~vmcs12->cr4_guest_host_mask) |
5387 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5388 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5389 return 1;
1a0d74e6 5390 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5391 return 0;
5392 } else
5393 return kvm_set_cr4(vcpu, val);
5394}
5395
5396/* called to set cr0 as approriate for clts instruction exit. */
5397static void handle_clts(struct kvm_vcpu *vcpu)
5398{
5399 if (is_guest_mode(vcpu)) {
5400 /*
5401 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5402 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5403 * just pretend it's off (also in arch.cr0 for fpu_activate).
5404 */
5405 vmcs_writel(CR0_READ_SHADOW,
5406 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5407 vcpu->arch.cr0 &= ~X86_CR0_TS;
5408 } else
5409 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5410}
5411
851ba692 5412static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5413{
229456fc 5414 unsigned long exit_qualification, val;
6aa8b732
AK		 5415 int cr;
5416 int reg;
49a9b07e 5417 int err;
6aa8b732 5418
bfdaab09 5419 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5420 cr = exit_qualification & 15;
5421 reg = (exit_qualification >> 8) & 15;
5422 switch ((exit_qualification >> 4) & 3) {
5423 case 0: /* mov to cr */
1e32c079 5424 val = kvm_register_readl(vcpu, reg);
229456fc 5425 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5426 switch (cr) {
5427 case 0:
eeadf9e7 5428 err = handle_set_cr0(vcpu, val);
db8fcefa 5429 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5430 return 1;
5431 case 3:
2390218b 5432 err = kvm_set_cr3(vcpu, val);
db8fcefa 5433 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5434 return 1;
5435 case 4:
eeadf9e7 5436 err = handle_set_cr4(vcpu, val);
db8fcefa 5437 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5438 return 1;
0a5fff19
GN		 5439 case 8: {
5440 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5441 u8 cr8 = (u8)val;
eea1cff9 5442 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5443 kvm_complete_insn_gp(vcpu, err);
35754c98 5444 if (lapic_in_kernel(vcpu))
0a5fff19
GN		 5445 return 1;
5446 if (cr8_prev <= cr8)
5447 return 1;
851ba692 5448 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5449 return 0;
5450 }
4b8073e4 5451 }
6aa8b732 5452 break;
25c4c276 5453 case 2: /* clts */
eeadf9e7 5454 handle_clts(vcpu);
4d4ec087 5455 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5456 skip_emulated_instruction(vcpu);
6b52d186 5457 vmx_fpu_activate(vcpu);
25c4c276 5458 return 1;
6aa8b732
AK		 5459 case 1: /*mov from cr*/
5460 switch (cr) {
5461 case 3:
9f8fe504
AK		 5462 val = kvm_read_cr3(vcpu);
5463 kvm_register_write(vcpu, reg, val);
5464 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5465 skip_emulated_instruction(vcpu);
5466 return 1;
5467 case 8:
229456fc
MT		 5468 val = kvm_get_cr8(vcpu);
5469 kvm_register_write(vcpu, reg, val);
5470 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5471 skip_emulated_instruction(vcpu);
5472 return 1;
5473 }
5474 break;
5475 case 3: /* lmsw */
a1f83a74 5476 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5477 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5478 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5479
5480 skip_emulated_instruction(vcpu);
5481 return 1;
5482 default:
5483 break;
5484 }
851ba692 5485 vcpu->run->exit_reason = 0;
a737f256 5486 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5487 (int)(exit_qualification >> 4) & 3, cr);
5488 return 0;
5489}
5490
851ba692 5491static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5492{
bfdaab09 5493 unsigned long exit_qualification;
16f8a6f9
NA		 5494 int dr, dr7, reg;
5495
5496 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5497 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5498
5499 /* First, if DR does not exist, trigger UD */
5500 if (!kvm_require_dr(vcpu, dr))
5501 return 1;
6aa8b732 5502
f2483415 5503 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5504 if (!kvm_require_cpl(vcpu, 0))
5505 return 1;
16f8a6f9
NA		 5506 dr7 = vmcs_readl(GUEST_DR7);
5507 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5508 /*
5509 * As the vm-exit takes precedence over the debug trap, we
5510 * need to emulate the latter, either for the host or the
5511 * guest debugging itself.
5512 */
5513 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5514 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5515 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5516 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5517 vcpu->run->debug.arch.exception = DB_VECTOR;
5518 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5519 return 0;
5520 } else {
7305eb5d 5521 vcpu->arch.dr6 &= ~15;
6f43ed01 5522 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5523 kvm_queue_exception(vcpu, DB_VECTOR);
5524 return 1;
5525 }
5526 }
5527
81908bf4
PB		 5528 if (vcpu->guest_debug == 0) {
5529 u32 cpu_based_vm_exec_control;
5530
5531 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5532 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5533 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5534
5535 /*
5536 * No more DR vmexits; force a reload of the debug registers
5537 * and reenter on this instruction. The next vmexit will
5538 * retrieve the full state of the debug registers.
5539 */
5540 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5541 return 1;
5542 }
5543
42dbaa5a
JK		 5544 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5545 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5546 unsigned long val;
4c4d563b
JK		 5547
5548 if (kvm_get_dr(vcpu, dr, &val))
5549 return 1;
5550 kvm_register_write(vcpu, reg, val);
020df079 5551 } else
5777392e 5552 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5553 return 1;
5554
6aa8b732
AK		 5555 skip_emulated_instruction(vcpu);
5556 return 1;
5557}
5558
73aaf249
JK		 5559static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5560{
5561 return vcpu->arch.dr6;
5562}
5563
5564static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5565{
5566}
5567
81908bf4
PB		 5568static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5569{
5570 u32 cpu_based_vm_exec_control;
5571
5572 get_debugreg(vcpu->arch.db[0], 0);
5573 get_debugreg(vcpu->arch.db[1], 1);
5574 get_debugreg(vcpu->arch.db[2], 2);
5575 get_debugreg(vcpu->arch.db[3], 3);
5576 get_debugreg(vcpu->arch.dr6, 6);
5577 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5578
5579 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5580
5581 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5582 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5583 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5584}
5585
020df079
GN		 5586static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5587{
5588 vmcs_writel(GUEST_DR7, val);
5589}
5590
851ba692 5591static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5592{
06465c5a
AK		 5593 kvm_emulate_cpuid(vcpu);
5594 return 1;
6aa8b732
AK		 5595}
5596
851ba692 5597static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5598{
ad312c7c 5599 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 5600 struct msr_data msr_info;
6aa8b732 5601
609e36d3
PB		 5602 msr_info.index = ecx;
5603 msr_info.host_initiated = false;
5604 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 5605 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5606 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5607 return 1;
5608 }
5609
609e36d3 5610 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 5611
6aa8b732 5612 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB		 5613 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5614 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6aa8b732
AK		 5615 skip_emulated_instruction(vcpu);
5616 return 1;
5617}
5618
851ba692 5619static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5620{
8fe8ab46 5621 struct msr_data msr;
ad312c7c
ZX		 5622 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5623 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5624 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5625
8fe8ab46
WA		 5626 msr.data = data;
5627 msr.index = ecx;
5628 msr.host_initiated = false;
854e8bb1 5629 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5630 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5631 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5632 return 1;
5633 }
5634
59200273 5635 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5636 skip_emulated_instruction(vcpu);
5637 return 1;
5638}
5639
851ba692 5640static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5641{
3842d135 5642 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5643 return 1;
5644}
5645
851ba692 5646static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5647{
85f455f7
ED		 5648 u32 cpu_based_vm_exec_control;
5649
5650 /* clear pending irq */
5651 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5652 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5653 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5654
3842d135
AK		 5655 kvm_make_request(KVM_REQ_EVENT, vcpu);
5656
a26bf12a 5657 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 5658 return 1;
5659}
5660
851ba692 5661static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 5662{
d3bef15f 5663 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5664}
5665
851ba692 5666static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5667{
7aa81cc0
AL		 5668 kvm_emulate_hypercall(vcpu);
5669 return 1;
c21415e8
IM		 5670}
5671
ec25d5e6
GN		 5672static int handle_invd(struct kvm_vcpu *vcpu)
5673{
51d8b661 5674 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5675}
5676
851ba692 5677static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5678{
f9c617f6 5679 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5680
5681 kvm_mmu_invlpg(vcpu, exit_qualification);
5682 skip_emulated_instruction(vcpu);
5683 return 1;
5684}
5685
fee84b07
AK		 5686static int handle_rdpmc(struct kvm_vcpu *vcpu)
5687{
5688 int err;
5689
5690 err = kvm_rdpmc(vcpu);
5691 kvm_complete_insn_gp(vcpu, err);
5692
5693 return 1;
5694}
5695
851ba692 5696static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5697{
f5f48ee1 5698 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5699 return 1;
5700}
5701
2acf923e
DC		 5702static int handle_xsetbv(struct kvm_vcpu *vcpu)
5703{
5704 u64 new_bv = kvm_read_edx_eax(vcpu);
5705 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5706
5707 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5708 skip_emulated_instruction(vcpu);
5709 return 1;
5710}
5711
f53cd63c
WL		 5712static int handle_xsaves(struct kvm_vcpu *vcpu)
5713{
5714 skip_emulated_instruction(vcpu);
5715 WARN(1, "this should never happen\n");
5716 return 1;
5717}
5718
5719static int handle_xrstors(struct kvm_vcpu *vcpu)
5720{
5721 skip_emulated_instruction(vcpu);
5722 WARN(1, "this should never happen\n");
5723 return 1;
5724}
5725
851ba692 5726static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5727{
58fbbf26
KT		 5728 if (likely(fasteoi)) {
5729 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5730 int access_type, offset;
5731
5732 access_type = exit_qualification & APIC_ACCESS_TYPE;
5733 offset = exit_qualification & APIC_ACCESS_OFFSET;
5734 /*
5735 * Sane guest uses MOV to write EOI, with written value
5736 * not cared. So make a short-circuit here by avoiding
5737 * heavy instruction emulation.
5738 */
5739 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5740 (offset == APIC_EOI)) {
5741 kvm_lapic_set_eoi(vcpu);
5742 skip_emulated_instruction(vcpu);
5743 return 1;
5744 }
5745 }
51d8b661 5746 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5747}
5748
c7c9c56c
YZ		 5749static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5750{
5751 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5752 int vector = exit_qualification & 0xff;
5753
5754 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5755 kvm_apic_set_eoi_accelerated(vcpu, vector);
5756 return 1;
5757}
5758
83d4c286
YZ		 5759static int handle_apic_write(struct kvm_vcpu *vcpu)
5760{
5761 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5762 u32 offset = exit_qualification & 0xfff;
5763
5764 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5765 kvm_apic_write_nodecode(vcpu, offset);
5766 return 1;
5767}
5768
851ba692 5769static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5770{
60637aac 5771 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5772 unsigned long exit_qualification;
e269fb21
JK		 5773 bool has_error_code = false;
5774 u32 error_code = 0;
37817f29 5775 u16 tss_selector;
7f3d35fd 5776 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5777
5778 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5779 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5780 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5781
5782 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5783
5784 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5785 if (reason == TASK_SWITCH_GATE && idt_v) {
5786 switch (type) {
5787 case INTR_TYPE_NMI_INTR:
5788 vcpu->arch.nmi_injected = false;
654f06fc 5789 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5790 break;
5791 case INTR_TYPE_EXT_INTR:
66fd3f7f 5792 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5793 kvm_clear_interrupt_queue(vcpu);
5794 break;
5795 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5796 if (vmx->idt_vectoring_info &
5797 VECTORING_INFO_DELIVER_CODE_MASK) {
5798 has_error_code = true;
5799 error_code =
5800 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5801 }
5802 /* fall through */
64a7ec06
GN		 5803 case INTR_TYPE_SOFT_EXCEPTION:
5804 kvm_clear_exception_queue(vcpu);
5805 break;
5806 default:
5807 break;
5808 }
60637aac 5809 }
37817f29
IE		 5810 tss_selector = exit_qualification;
5811
64a7ec06
GN		 5812 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5813 type != INTR_TYPE_EXT_INTR &&
5814 type != INTR_TYPE_NMI_INTR))
5815 skip_emulated_instruction(vcpu);
5816
7f3d35fd
KW		 5817 if (kvm_task_switch(vcpu, tss_selector,
5818 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5819 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5820 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5821 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5822 vcpu->run->internal.ndata = 0;
42dbaa5a 5823 return 0;
acb54517 5824 }
42dbaa5a 5825
42dbaa5a
JK		 5826 /*
5827 * TODO: What about debug traps on tss switch?
5828 * Are we supposed to inject them and update dr6?
5829 */
5830
5831 return 1;
37817f29
IE		 5832}
5833
851ba692 5834static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5835{
f9c617f6 5836 unsigned long exit_qualification;
1439442c 5837 gpa_t gpa;
4f5982a5 5838 u32 error_code;
1439442c 5839 int gla_validity;
1439442c 5840
f9c617f6 5841 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5842
1439442c
SY		 5843 gla_validity = (exit_qualification >> 7) & 0x3;
5844 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5845 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5846 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5847 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5848 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5849 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5850 (long unsigned int)exit_qualification);
851ba692
AK		 5851 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5852 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5853 return 0;
1439442c
SY		 5854 }
5855
0be9c7a8
GN		 5856 /*
5857 * EPT violation happened while executing iret from NMI,
5858 * "blocked by NMI" bit has to be set before next VM entry.
5859 * There are errata that may cause this bit to not be set:
5860 * AAK134, BY25.
5861 */
bcd1c294
GN		 5862 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5863 cpu_has_virtual_nmis() &&
5864 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5865 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5866
1439442c 5867 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5868 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5869
5870 /* It is a write fault? */
81ed33e4 5871 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5872 /* It is a fetch fault? */
81ed33e4 5873 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5874 /* ept page table is present? */
81ed33e4 5875 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5876
25d92081
YZ		 5877 vcpu->arch.exit_qualification = exit_qualification;
5878
4f5982a5 5879 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5880}
5881
851ba692 5882static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5883{
f735d4af 5884 int ret;
68f89400
MT		 5885 gpa_t gpa;
5886
5887 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 5888 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
68c3b4d1 5889 skip_emulated_instruction(vcpu);
931c33b1 5890 trace_kvm_fast_mmio(gpa);
68c3b4d1
MT		 5891 return 1;
5892 }
68f89400 5893
ce88decf 5894 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5895 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5896 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5897 EMULATE_DONE;
f8f55942
XG		 5898
5899 if (unlikely(ret == RET_MMIO_PF_INVALID))
5900 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5901
b37fbea6 5902 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5903 return 1;
5904
5905 /* It is the real ept misconfig */
f735d4af 5906 WARN_ON(1);
68f89400 5907
851ba692
AK		 5908 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5909 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5910
5911 return 0;
5912}
5913
851ba692 5914static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5915{
5916 u32 cpu_based_vm_exec_control;
5917
5918 /* clear pending NMI */
5919 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5920 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5921 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5922 ++vcpu->stat.nmi_window_exits;
3842d135 5923 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5924
5925 return 1;
5926}
5927
80ced186 5928static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5929{
8b3079a5
AK		 5930 struct vcpu_vmx *vmx = to_vmx(vcpu);
5931 enum emulation_result err = EMULATE_DONE;
80ced186 5932 int ret = 1;
49e9d557
AK		 5933 u32 cpu_exec_ctrl;
5934 bool intr_window_requested;
b8405c18 5935 unsigned count = 130;
49e9d557
AK		 5936
5937 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5938 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5939
98eb2f8b 5940 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5941 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5942 return handle_interrupt_window(&vmx->vcpu);
5943
de87dcdd
AK		 5944 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5945 return 1;
5946
991eebf9 5947 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5948
ac0a48c3 5949 if (err == EMULATE_USER_EXIT) {
94452b9e 5950 ++vcpu->stat.mmio_exits;
80ced186
MG		 5951 ret = 0;
5952 goto out;
5953 }
1d5a4d9b 5954
de5f70e0
AK		 5955 if (err != EMULATE_DONE) {
5956 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5957 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5958 vcpu->run->internal.ndata = 0;
6d77dbfc 5959 return 0;
de5f70e0 5960 }
ea953ef0 5961
8d76c49e
GN		 5962 if (vcpu->arch.halt_request) {
5963 vcpu->arch.halt_request = 0;
5cb56059 5964 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5965 goto out;
5966 }
5967
ea953ef0 5968 if (signal_pending(current))
80ced186 5969 goto out;
ea953ef0
MG		 5970 if (need_resched())
5971 schedule();
5972 }
5973
80ced186
MG		 5974out:
5975 return ret;
ea953ef0
MG		 5976}
5977
b4a2d31d
RK		 5978static int __grow_ple_window(int val)
5979{
5980 if (ple_window_grow < 1)
5981 return ple_window;
5982
5983 val = min(val, ple_window_actual_max);
5984
5985 if (ple_window_grow < ple_window)
5986 val *= ple_window_grow;
5987 else
5988 val += ple_window_grow;
5989
5990 return val;
5991}
5992
5993static int __shrink_ple_window(int val, int modifier, int minimum)
5994{
5995 if (modifier < 1)
5996 return ple_window;
5997
5998 if (modifier < ple_window)
5999 val /= modifier;
6000 else
6001 val -= modifier;
6002
6003 return max(val, minimum);
6004}
6005
6006static void grow_ple_window(struct kvm_vcpu *vcpu)
6007{
6008 struct vcpu_vmx *vmx = to_vmx(vcpu);
6009 int old = vmx->ple_window;
6010
6011 vmx->ple_window = __grow_ple_window(old);
6012
6013 if (vmx->ple_window != old)
6014 vmx->ple_window_dirty = true;
7b46268d
RK		 6015
6016 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 6017}
6018
6019static void shrink_ple_window(struct kvm_vcpu *vcpu)
6020{
6021 struct vcpu_vmx *vmx = to_vmx(vcpu);
6022 int old = vmx->ple_window;
6023
6024 vmx->ple_window = __shrink_ple_window(old,
6025 ple_window_shrink, ple_window);
6026
6027 if (vmx->ple_window != old)
6028 vmx->ple_window_dirty = true;
7b46268d
RK		 6029
6030 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 6031}
6032
6033/*
6034 * ple_window_actual_max is computed to be one grow_ple_window() below
6035 * ple_window_max. (See __grow_ple_window for the reason.)
6036 * This prevents overflows, because ple_window_max is int.
6037 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6038 * this process.
6039 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6040 */
6041static void update_ple_window_actual_max(void)
6042{
6043 ple_window_actual_max =
6044 __shrink_ple_window(max(ple_window_max, ple_window),
6045 ple_window_grow, INT_MIN);
6046}
6047
f2c7648d
TC		 6048static __init int hardware_setup(void)
6049{
34a1cd60
TC		 6050 int r = -ENOMEM, i, msr;
6051
6052 rdmsrl_safe(MSR_EFER, &host_efer);
6053
6054 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6055 kvm_define_shared_msr(i, vmx_msr_index[i]);
6056
6057 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6058 if (!vmx_io_bitmap_a)
6059 return r;
6060
6061 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6062 if (!vmx_io_bitmap_b)
6063 goto out;
6064
6065 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6066 if (!vmx_msr_bitmap_legacy)
6067 goto out1;
6068
6069 vmx_msr_bitmap_legacy_x2apic =
6070 (unsigned long *)__get_free_page(GFP_KERNEL);
6071 if (!vmx_msr_bitmap_legacy_x2apic)
6072 goto out2;
6073
6074 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6075 if (!vmx_msr_bitmap_longmode)
6076 goto out3;
6077
6078 vmx_msr_bitmap_longmode_x2apic =
6079 (unsigned long *)__get_free_page(GFP_KERNEL);
6080 if (!vmx_msr_bitmap_longmode_x2apic)
6081 goto out4;
3af18d9c
WV		 6082
6083 if (nested) {
6084 vmx_msr_bitmap_nested =
6085 (unsigned long *)__get_free_page(GFP_KERNEL);
6086 if (!vmx_msr_bitmap_nested)
6087 goto out5;
6088 }
6089
34a1cd60
TC		 6090 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6091 if (!vmx_vmread_bitmap)
3af18d9c 6092 goto out6;
34a1cd60
TC		 6093
6094 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6095 if (!vmx_vmwrite_bitmap)
3af18d9c 6096 goto out7;
34a1cd60
TC		 6097
6098 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6099 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6100
6101 /*
6102 * Allow direct access to the PC debug port (it is often used for I/O
6103 * delays, but the vmexits simply slow things down).
6104 */
6105 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6106 clear_bit(0x80, vmx_io_bitmap_a);
6107
6108 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6109
6110 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6111 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 6112 if (nested)
6113 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 6114
34a1cd60
TC		 6115 if (setup_vmcs_config(&vmcs_config) < 0) {
6116 r = -EIO;
3af18d9c 6117 goto out8;
baa03522 6118 }
f2c7648d
TC		 6119
6120 if (boot_cpu_has(X86_FEATURE_NX))
6121 kvm_enable_efer_bits(EFER_NX);
6122
6123 if (!cpu_has_vmx_vpid())
6124 enable_vpid = 0;
6125 if (!cpu_has_vmx_shadow_vmcs())
6126 enable_shadow_vmcs = 0;
6127 if (enable_shadow_vmcs)
6128 init_vmcs_shadow_fields();
6129
6130 if (!cpu_has_vmx_ept() ||
6131 !cpu_has_vmx_ept_4levels()) {
6132 enable_ept = 0;
6133 enable_unrestricted_guest = 0;
6134 enable_ept_ad_bits = 0;
6135 }
6136
6137 if (!cpu_has_vmx_ept_ad_bits())
6138 enable_ept_ad_bits = 0;
6139
6140 if (!cpu_has_vmx_unrestricted_guest())
6141 enable_unrestricted_guest = 0;
6142
ad15a296 6143 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6144 flexpriority_enabled = 0;
6145
ad15a296
PB		 6146 /*
6147 * set_apic_access_page_addr() is used to reload apic access
6148 * page upon invalidation. No need to do anything if not
6149 * using the APIC_ACCESS_ADDR VMCS field.
6150 */
6151 if (!flexpriority_enabled)
f2c7648d 6152 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6153
6154 if (!cpu_has_vmx_tpr_shadow())
6155 kvm_x86_ops->update_cr8_intercept = NULL;
6156
6157 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6158 kvm_disable_largepages();
6159
6160 if (!cpu_has_vmx_ple())
6161 ple_gap = 0;
6162
6163 if (!cpu_has_vmx_apicv())
6164 enable_apicv = 0;
6165
6166 if (enable_apicv)
6167 kvm_x86_ops->update_cr8_intercept = NULL;
6168 else {
6169 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6170 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6171 kvm_x86_ops->deliver_posted_interrupt = NULL;
6172 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6173 }
6174
baa03522
TC		 6175 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6176 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6177 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6178 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6179 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6180 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6181 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6182
6183 memcpy(vmx_msr_bitmap_legacy_x2apic,
6184 vmx_msr_bitmap_legacy, PAGE_SIZE);
6185 memcpy(vmx_msr_bitmap_longmode_x2apic,
6186 vmx_msr_bitmap_longmode, PAGE_SIZE);
6187
04bb92e4
WL		 6188 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6189
baa03522
TC		 6190 if (enable_apicv) {
6191 for (msr = 0x800; msr <= 0x8ff; msr++)
6192 vmx_disable_intercept_msr_read_x2apic(msr);
6193
6194 /* According SDM, in x2apic mode, the whole id reg is used.
6195 * But in KVM, it only use the highest eight bits. Need to
6196 * intercept it */
6197 vmx_enable_intercept_msr_read_x2apic(0x802);
6198 /* TMCCT */
6199 vmx_enable_intercept_msr_read_x2apic(0x839);
6200 /* TPR */
6201 vmx_disable_intercept_msr_write_x2apic(0x808);
6202 /* EOI */
6203 vmx_disable_intercept_msr_write_x2apic(0x80b);
6204 /* SELF-IPI */
6205 vmx_disable_intercept_msr_write_x2apic(0x83f);
6206 }
6207
6208 if (enable_ept) {
6209 kvm_mmu_set_mask_ptes(0ull,
6210 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6211 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6212 0ull, VMX_EPT_EXECUTABLE_MASK);
6213 ept_set_mmio_spte_mask();
6214 kvm_enable_tdp();
6215 } else
6216 kvm_disable_tdp();
6217
6218 update_ple_window_actual_max();
6219
843e4330
KH		 6220 /*
6221 * Only enable PML when hardware supports PML feature, and both EPT
6222 * and EPT A/D bit features are enabled -- PML depends on them to work.
6223 */
6224 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6225 enable_pml = 0;
6226
6227 if (!enable_pml) {
6228 kvm_x86_ops->slot_enable_log_dirty = NULL;
6229 kvm_x86_ops->slot_disable_log_dirty = NULL;
6230 kvm_x86_ops->flush_log_dirty = NULL;
6231 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6232 }
6233
f2c7648d 6234 return alloc_kvm_area();
34a1cd60 6235
3af18d9c 6236out8:
34a1cd60 6237 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6238out7:
34a1cd60 6239 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6240out6:
6241 if (nested)
6242 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6243out5:
6244 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6245out4:
6246 free_page((unsigned long)vmx_msr_bitmap_longmode);
6247out3:
6248 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6249out2:
6250 free_page((unsigned long)vmx_msr_bitmap_legacy);
6251out1:
6252 free_page((unsigned long)vmx_io_bitmap_b);
6253out:
6254 free_page((unsigned long)vmx_io_bitmap_a);
6255
6256 return r;
f2c7648d
TC		 6257}
6258
6259static __exit void hardware_unsetup(void)
6260{
34a1cd60
TC		 6261 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6262 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6263 free_page((unsigned long)vmx_msr_bitmap_legacy);
6264 free_page((unsigned long)vmx_msr_bitmap_longmode);
6265 free_page((unsigned long)vmx_io_bitmap_b);
6266 free_page((unsigned long)vmx_io_bitmap_a);
6267 free_page((unsigned long)vmx_vmwrite_bitmap);
6268 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6269 if (nested)
6270 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6271
f2c7648d
TC		 6272 free_kvm_area();
6273}
6274
4b8d54f9
ZE		 6275/*
6276 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6277 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6278 */
9fb41ba8 6279static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6280{
b4a2d31d
RK		 6281 if (ple_gap)
6282 grow_ple_window(vcpu);
6283
4b8d54f9
ZE		 6284 skip_emulated_instruction(vcpu);
6285 kvm_vcpu_on_spin(vcpu);
6286
6287 return 1;
6288}
6289
87c00572 6290static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6291{
87c00572 6292 skip_emulated_instruction(vcpu);
59708670
SY		 6293 return 1;
6294}
6295
87c00572
GS		 6296static int handle_mwait(struct kvm_vcpu *vcpu)
6297{
6298 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6299 return handle_nop(vcpu);
6300}
6301
5f3d45e7
MD		 6302static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6303{
6304 return 1;
6305}
6306
87c00572
GS		 6307static int handle_monitor(struct kvm_vcpu *vcpu)
6308{
6309 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6310 return handle_nop(vcpu);
6311}
6312
ff2f6fe9
NHE		 6313/*
6314 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6315 * We could reuse a single VMCS for all the L2 guests, but we also want the
6316 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6317 * allows keeping them loaded on the processor, and in the future will allow
6318 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6319 * every entry if they never change.
6320 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6321 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6322 *
6323 * The following functions allocate and free a vmcs02 in this pool.
6324 */
6325
6326/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6327static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6328{
6329 struct vmcs02_list *item;
6330 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6331 if (item->vmptr == vmx->nested.current_vmptr) {
6332 list_move(&item->list, &vmx->nested.vmcs02_pool);
6333 return &item->vmcs02;
6334 }
6335
6336 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6337 /* Recycle the least recently used VMCS. */
6338 item = list_entry(vmx->nested.vmcs02_pool.prev,
6339 struct vmcs02_list, list);
6340 item->vmptr = vmx->nested.current_vmptr;
6341 list_move(&item->list, &vmx->nested.vmcs02_pool);
6342 return &item->vmcs02;
6343 }
6344
6345 /* Create a new VMCS */
0fa24ce3 6346 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6347 if (!item)
6348 return NULL;
6349 item->vmcs02.vmcs = alloc_vmcs();
6350 if (!item->vmcs02.vmcs) {
6351 kfree(item);
6352 return NULL;
6353 }
6354 loaded_vmcs_init(&item->vmcs02);
6355 item->vmptr = vmx->nested.current_vmptr;
6356 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6357 vmx->nested.vmcs02_num++;
6358 return &item->vmcs02;
6359}
6360
6361/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6362static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6363{
6364 struct vmcs02_list *item;
6365 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6366 if (item->vmptr == vmptr) {
6367 free_loaded_vmcs(&item->vmcs02);
6368 list_del(&item->list);
6369 kfree(item);
6370 vmx->nested.vmcs02_num--;
6371 return;
6372 }
6373}
6374
6375/*
6376 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6377 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6378 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6379 */
6380static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6381{
6382 struct vmcs02_list *item, *n;
4fa7734c
PB		 6383
6384 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6385 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6386 /*
6387 * Something will leak if the above WARN triggers. Better than
6388 * a use-after-free.
6389 */
6390 if (vmx->loaded_vmcs == &item->vmcs02)
6391 continue;
6392
6393 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6394 list_del(&item->list);
6395 kfree(item);
4fa7734c 6396 vmx->nested.vmcs02_num--;
ff2f6fe9 6397 }
ff2f6fe9
NHE		 6398}
6399
0658fbaa
ACL		 6400/*
6401 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6402 * set the success or error code of an emulated VMX instruction, as specified
6403 * by Vol 2B, VMX Instruction Reference, "Conventions".
6404 */
6405static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6406{
6407 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6408 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6409 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6410}
6411
6412static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6413{
6414 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6415 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6416 X86_EFLAGS_SF | X86_EFLAGS_OF))
6417 | X86_EFLAGS_CF);
6418}
6419
145c28dd 6420static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6421 u32 vm_instruction_error)
6422{
6423 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6424 /*
6425 * failValid writes the error number to the current VMCS, which
6426 * can't be done there isn't a current VMCS.
6427 */
6428 nested_vmx_failInvalid(vcpu);
6429 return;
6430 }
6431 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6432 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6433 X86_EFLAGS_SF | X86_EFLAGS_OF))
6434 | X86_EFLAGS_ZF);
6435 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6436 /*
6437 * We don't need to force a shadow sync because
6438 * VM_INSTRUCTION_ERROR is not shadowed
6439 */
6440}
145c28dd 6441
ff651cb6
WV		 6442static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6443{
6444 /* TODO: not to reset guest simply here. */
6445 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6446 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6447}
6448
f4124500
JK		 6449static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6450{
6451 struct vcpu_vmx *vmx =
6452 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6453
6454 vmx->nested.preemption_timer_expired = true;
6455 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6456 kvm_vcpu_kick(&vmx->vcpu);
6457
6458 return HRTIMER_NORESTART;
6459}
6460
19677e32
BD		 6461/*
6462 * Decode the memory-address operand of a vmx instruction, as recorded on an
6463 * exit caused by such an instruction (run by a guest hypervisor).
6464 * On success, returns 0. When the operand is invalid, returns 1 and throws
6465 * #UD or #GP.
6466 */
6467static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6468 unsigned long exit_qualification,
f9eb4af6 6469 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6470{
f9eb4af6
EK		 6471 gva_t off;
6472 bool exn;
6473 struct kvm_segment s;
6474
19677e32
BD		 6475 /*
6476 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6477 * Execution", on an exit, vmx_instruction_info holds most of the
6478 * addressing components of the operand. Only the displacement part
6479 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6480 * For how an actual address is calculated from all these components,
6481 * refer to Vol. 1, "Operand Addressing".
6482 */
6483 int scaling = vmx_instruction_info & 3;
6484 int addr_size = (vmx_instruction_info >> 7) & 7;
6485 bool is_reg = vmx_instruction_info & (1u << 10);
6486 int seg_reg = (vmx_instruction_info >> 15) & 7;
6487 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6488 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6489 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6490 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6491
6492 if (is_reg) {
6493 kvm_queue_exception(vcpu, UD_VECTOR);
6494 return 1;
6495 }
6496
6497 /* Addr = segment_base + offset */
6498 /* offset = base + [index * scale] + displacement */
f9eb4af6 6499 off = exit_qualification; /* holds the displacement */
19677e32 6500 if (base_is_valid)
f9eb4af6 6501 off += kvm_register_read(vcpu, base_reg);
19677e32 6502 if (index_is_valid)
f9eb4af6
EK		 6503 off += kvm_register_read(vcpu, index_reg)<<scaling;
6504 vmx_get_segment(vcpu, &s, seg_reg);
6505 *ret = s.base + off;
19677e32
BD		 6506
6507 if (addr_size == 1) /* 32 bit */
6508 *ret &= 0xffffffff;
6509
f9eb4af6
EK		 6510 /* Checks for #GP/#SS exceptions. */
6511 exn = false;
6512 if (is_protmode(vcpu)) {
6513 /* Protected mode: apply checks for segment validity in the
6514 * following order:
6515 * - segment type check (#GP(0) may be thrown)
6516 * - usability check (#GP(0)/#SS(0))
6517 * - limit check (#GP(0)/#SS(0))
6518 */
6519 if (wr)
6520 /* #GP(0) if the destination operand is located in a
6521 * read-only data segment or any code segment.
6522 */
6523 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6524 else
6525 /* #GP(0) if the source operand is located in an
6526 * execute-only code segment
6527 */
6528 exn = ((s.type & 0xa) == 8);
6529 }
6530 if (exn) {
6531 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6532 return 1;
6533 }
6534 if (is_long_mode(vcpu)) {
6535 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6536 * non-canonical form. This is an only check for long mode.
6537 */
6538 exn = is_noncanonical_address(*ret);
6539 } else if (is_protmode(vcpu)) {
6540 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6541 */
6542 exn = (s.unusable != 0);
6543 /* Protected mode: #GP(0)/#SS(0) if the memory
6544 * operand is outside the segment limit.
6545 */
6546 exn = exn || (off + sizeof(u64) > s.limit);
6547 }
6548 if (exn) {
6549 kvm_queue_exception_e(vcpu,
6550 seg_reg == VCPU_SREG_SS ?
6551 SS_VECTOR : GP_VECTOR,
6552 0);
6553 return 1;
6554 }
6555
19677e32
BD		 6556 return 0;
6557}
6558
3573e22c
BD		 6559/*
6560 * This function performs the various checks including
6561 * - if it's 4KB aligned
6562 * - No bits beyond the physical address width are set
6563 * - Returns 0 on success or else 1
4291b588 6564 * (Intel SDM Section 30.3)
3573e22c 6565 */
4291b588
BD		 6566static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6567 gpa_t *vmpointer)
3573e22c
BD		 6568{
6569 gva_t gva;
6570 gpa_t vmptr;
6571 struct x86_exception e;
6572 struct page *page;
6573 struct vcpu_vmx *vmx = to_vmx(vcpu);
6574 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6575
6576 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 6577 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD		 6578 return 1;
6579
6580 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6581 sizeof(vmptr), &e)) {
6582 kvm_inject_page_fault(vcpu, &e);
6583 return 1;
6584 }
6585
6586 switch (exit_reason) {
6587 case EXIT_REASON_VMON:
6588 /*
6589 * SDM 3: 24.11.5
6590 * The first 4 bytes of VMXON region contain the supported
6591 * VMCS revision identifier
6592 *
6593 * Note - IA32_VMX_BASIC[48] will never be 1
6594 * for the nested case;
6595 * which replaces physical address width with 32
6596 *
6597 */
bc39c4db 6598 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6599 nested_vmx_failInvalid(vcpu);
6600 skip_emulated_instruction(vcpu);
6601 return 1;
6602 }
6603
6604 page = nested_get_page(vcpu, vmptr);
6605 if (page == NULL ||
6606 *(u32 *)kmap(page) != VMCS12_REVISION) {
6607 nested_vmx_failInvalid(vcpu);
6608 kunmap(page);
6609 skip_emulated_instruction(vcpu);
6610 return 1;
6611 }
6612 kunmap(page);
6613 vmx->nested.vmxon_ptr = vmptr;
6614 break;
4291b588 6615 case EXIT_REASON_VMCLEAR:
bc39c4db 6616 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6617 nested_vmx_failValid(vcpu,
6618 VMXERR_VMCLEAR_INVALID_ADDRESS);
6619 skip_emulated_instruction(vcpu);
6620 return 1;
6621 }
6622
6623 if (vmptr == vmx->nested.vmxon_ptr) {
6624 nested_vmx_failValid(vcpu,
6625 VMXERR_VMCLEAR_VMXON_POINTER);
6626 skip_emulated_instruction(vcpu);
6627 return 1;
6628 }
6629 break;
6630 case EXIT_REASON_VMPTRLD:
bc39c4db 6631 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6632 nested_vmx_failValid(vcpu,
6633 VMXERR_VMPTRLD_INVALID_ADDRESS);
6634 skip_emulated_instruction(vcpu);
6635 return 1;
6636 }
3573e22c 6637
4291b588
BD		 6638 if (vmptr == vmx->nested.vmxon_ptr) {
6639 nested_vmx_failValid(vcpu,
6640 VMXERR_VMCLEAR_VMXON_POINTER);
6641 skip_emulated_instruction(vcpu);
6642 return 1;
6643 }
6644 break;
3573e22c
BD		 6645 default:
6646 return 1; /* shouldn't happen */
6647 }
6648
4291b588
BD		 6649 if (vmpointer)
6650 *vmpointer = vmptr;
3573e22c
BD		 6651 return 0;
6652}
6653
ec378aee
NHE		 6654/*
6655 * Emulate the VMXON instruction.
6656 * Currently, we just remember that VMX is active, and do not save or even
6657 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6658 * do not currently need to store anything in that guest-allocated memory
6659 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6660 * argument is different from the VMXON pointer (which the spec says they do).
6661 */
6662static int handle_vmon(struct kvm_vcpu *vcpu)
6663{
6664 struct kvm_segment cs;
6665 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6666 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6667 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6668 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6669
6670 /* The Intel VMX Instruction Reference lists a bunch of bits that
6671 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6672 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6673 * Otherwise, we should fail with #UD. We test these now:
6674 */
6675 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6676 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6677 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6678 kvm_queue_exception(vcpu, UD_VECTOR);
6679 return 1;
6680 }
6681
6682 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6683 if (is_long_mode(vcpu) && !cs.l) {
6684 kvm_queue_exception(vcpu, UD_VECTOR);
6685 return 1;
6686 }
6687
6688 if (vmx_get_cpl(vcpu)) {
6689 kvm_inject_gp(vcpu, 0);
6690 return 1;
6691 }
3573e22c 6692
4291b588 6693 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6694 return 1;
6695
145c28dd
AG		 6696 if (vmx->nested.vmxon) {
6697 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6698 skip_emulated_instruction(vcpu);
6699 return 1;
6700 }
b3897a49
NHE		 6701
6702 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6703 != VMXON_NEEDED_FEATURES) {
6704 kvm_inject_gp(vcpu, 0);
6705 return 1;
6706 }
6707
8de48833
AG		 6708 if (enable_shadow_vmcs) {
6709 shadow_vmcs = alloc_vmcs();
6710 if (!shadow_vmcs)
6711 return -ENOMEM;
6712 /* mark vmcs as shadow */
6713 shadow_vmcs->revision_id |= (1u << 31);
6714 /* init shadow vmcs */
6715 vmcs_clear(shadow_vmcs);
6716 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6717 }
ec378aee 6718
ff2f6fe9
NHE		 6719 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6720 vmx->nested.vmcs02_num = 0;
6721
f4124500
JK		 6722 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6723 HRTIMER_MODE_REL);
6724 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6725
ec378aee
NHE		 6726 vmx->nested.vmxon = true;
6727
6728 skip_emulated_instruction(vcpu);
a25eb114 6729 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6730 return 1;
6731}
6732
6733/*
6734 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6735 * for running VMX instructions (except VMXON, whose prerequisites are
6736 * slightly different). It also specifies what exception to inject otherwise.
6737 */
6738static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6739{
6740 struct kvm_segment cs;
6741 struct vcpu_vmx *vmx = to_vmx(vcpu);
6742
6743 if (!vmx->nested.vmxon) {
6744 kvm_queue_exception(vcpu, UD_VECTOR);
6745 return 0;
6746 }
6747
6748 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6749 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6750 (is_long_mode(vcpu) && !cs.l)) {
6751 kvm_queue_exception(vcpu, UD_VECTOR);
6752 return 0;
6753 }
6754
6755 if (vmx_get_cpl(vcpu)) {
6756 kvm_inject_gp(vcpu, 0);
6757 return 0;
6758 }
6759
6760 return 1;
6761}
6762
e7953d7f
AG		 6763static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6764{
9a2a05b9
PB		 6765 if (vmx->nested.current_vmptr == -1ull)
6766 return;
6767
6768 /* current_vmptr and current_vmcs12 are always set/reset together */
6769 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6770 return;
6771
012f83cb 6772 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6773 /* copy to memory all shadowed fields in case
6774 they were modified */
6775 copy_shadow_to_vmcs12(vmx);
6776 vmx->nested.sync_shadow_vmcs = false;
7ec36296
XG		 6777 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6778 SECONDARY_EXEC_SHADOW_VMCS);
9a2a05b9 6779 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6780 }
705699a1 6781 vmx->nested.posted_intr_nv = -1;
e7953d7f
AG		 6782 kunmap(vmx->nested.current_vmcs12_page);
6783 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6784 vmx->nested.current_vmptr = -1ull;
6785 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6786}
6787
ec378aee
NHE		 6788/*
6789 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6790 * just stops using VMX.
6791 */
6792static void free_nested(struct vcpu_vmx *vmx)
6793{
6794 if (!vmx->nested.vmxon)
6795 return;
9a2a05b9 6796
ec378aee 6797 vmx->nested.vmxon = false;
9a2a05b9 6798 nested_release_vmcs12(vmx);
e7953d7f
AG		 6799 if (enable_shadow_vmcs)
6800 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6801 /* Unpin physical memory we referred to in current vmcs02 */
6802 if (vmx->nested.apic_access_page) {
6803 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6804 vmx->nested.apic_access_page = NULL;
fe3ef05c 6805 }
a7c0b07d
WL		 6806 if (vmx->nested.virtual_apic_page) {
6807 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6808 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6809 }
705699a1
WV		 6810 if (vmx->nested.pi_desc_page) {
6811 kunmap(vmx->nested.pi_desc_page);
6812 nested_release_page(vmx->nested.pi_desc_page);
6813 vmx->nested.pi_desc_page = NULL;
6814 vmx->nested.pi_desc = NULL;
6815 }
ff2f6fe9
NHE		 6816
6817 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6818}
6819
6820/* Emulate the VMXOFF instruction */
6821static int handle_vmoff(struct kvm_vcpu *vcpu)
6822{
6823 if (!nested_vmx_check_permission(vcpu))
6824 return 1;
6825 free_nested(to_vmx(vcpu));
6826 skip_emulated_instruction(vcpu);
a25eb114 6827 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6828 return 1;
6829}
6830
27d6c865
NHE		 6831/* Emulate the VMCLEAR instruction */
6832static int handle_vmclear(struct kvm_vcpu *vcpu)
6833{
6834 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6835 gpa_t vmptr;
6836 struct vmcs12 *vmcs12;
6837 struct page *page;
27d6c865
NHE		 6838
6839 if (!nested_vmx_check_permission(vcpu))
6840 return 1;
6841
4291b588 6842 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6843 return 1;
27d6c865 6844
9a2a05b9 6845 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6846 nested_release_vmcs12(vmx);
27d6c865
NHE		 6847
6848 page = nested_get_page(vcpu, vmptr);
6849 if (page == NULL) {
6850 /*
6851 * For accurate processor emulation, VMCLEAR beyond available
6852 * physical memory should do nothing at all. However, it is
6853 * possible that a nested vmx bug, not a guest hypervisor bug,
6854 * resulted in this case, so let's shut down before doing any
6855 * more damage:
6856 */
6857 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6858 return 1;
6859 }
6860 vmcs12 = kmap(page);
6861 vmcs12->launch_state = 0;
6862 kunmap(page);
6863 nested_release_page(page);
6864
6865 nested_free_vmcs02(vmx, vmptr);
6866
6867 skip_emulated_instruction(vcpu);
6868 nested_vmx_succeed(vcpu);
6869 return 1;
6870}
6871
cd232ad0
NHE		 6872static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6873
6874/* Emulate the VMLAUNCH instruction */
6875static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6876{
6877 return nested_vmx_run(vcpu, true);
6878}
6879
6880/* Emulate the VMRESUME instruction */
6881static int handle_vmresume(struct kvm_vcpu *vcpu)
6882{
6883
6884 return nested_vmx_run(vcpu, false);
6885}
6886
49f705c5
NHE		 6887enum vmcs_field_type {
6888 VMCS_FIELD_TYPE_U16 = 0,
6889 VMCS_FIELD_TYPE_U64 = 1,
6890 VMCS_FIELD_TYPE_U32 = 2,
6891 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6892};
6893
6894static inline int vmcs_field_type(unsigned long field)
6895{
6896 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6897 return VMCS_FIELD_TYPE_U32;
6898 return (field >> 13) & 0x3 ;
6899}
6900
6901static inline int vmcs_field_readonly(unsigned long field)
6902{
6903 return (((field >> 10) & 0x3) == 1);
6904}
6905
6906/*
6907 * Read a vmcs12 field. Since these can have varying lengths and we return
6908 * one type, we chose the biggest type (u64) and zero-extend the return value
6909 * to that size. Note that the caller, handle_vmread, might need to use only
6910 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6911 * 64-bit fields are to be returned).
6912 */
a2ae9df7
PB		 6913static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6914 unsigned long field, u64 *ret)
49f705c5
NHE		 6915{
6916 short offset = vmcs_field_to_offset(field);
6917 char *p;
6918
6919 if (offset < 0)
a2ae9df7 6920 return offset;
49f705c5
NHE		 6921
6922 p = ((char *)(get_vmcs12(vcpu))) + offset;
6923
6924 switch (vmcs_field_type(field)) {
6925 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6926 *ret = *((natural_width *)p);
a2ae9df7 6927 return 0;
49f705c5
NHE		 6928 case VMCS_FIELD_TYPE_U16:
6929 *ret = *((u16 *)p);
a2ae9df7 6930 return 0;
49f705c5
NHE		 6931 case VMCS_FIELD_TYPE_U32:
6932 *ret = *((u32 *)p);
a2ae9df7 6933 return 0;
49f705c5
NHE		 6934 case VMCS_FIELD_TYPE_U64:
6935 *ret = *((u64 *)p);
a2ae9df7 6936 return 0;
49f705c5 6937 default:
a2ae9df7
PB		 6938 WARN_ON(1);
6939 return -ENOENT;
49f705c5
NHE		 6940 }
6941}
6942
20b97fea 6943
a2ae9df7
PB		 6944static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6945 unsigned long field, u64 field_value){
20b97fea
AG		 6946 short offset = vmcs_field_to_offset(field);
6947 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6948 if (offset < 0)
a2ae9df7 6949 return offset;
20b97fea
AG		 6950
6951 switch (vmcs_field_type(field)) {
6952 case VMCS_FIELD_TYPE_U16:
6953 *(u16 *)p = field_value;
a2ae9df7 6954 return 0;
20b97fea
AG		 6955 case VMCS_FIELD_TYPE_U32:
6956 *(u32 *)p = field_value;
a2ae9df7 6957 return 0;
20b97fea
AG		 6958 case VMCS_FIELD_TYPE_U64:
6959 *(u64 *)p = field_value;
a2ae9df7 6960 return 0;
20b97fea
AG		 6961 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6962 *(natural_width *)p = field_value;
a2ae9df7 6963 return 0;
20b97fea 6964 default:
a2ae9df7
PB		 6965 WARN_ON(1);
6966 return -ENOENT;
20b97fea
AG		 6967 }
6968
6969}
6970
16f5b903
AG		 6971static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6972{
6973 int i;
6974 unsigned long field;
6975 u64 field_value;
6976 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6977 const unsigned long *fields = shadow_read_write_fields;
6978 const int num_fields = max_shadow_read_write_fields;
16f5b903 6979
282da870
JK		 6980 preempt_disable();
6981
16f5b903
AG		 6982 vmcs_load(shadow_vmcs);
6983
6984 for (i = 0; i < num_fields; i++) {
6985 field = fields[i];
6986 switch (vmcs_field_type(field)) {
6987 case VMCS_FIELD_TYPE_U16:
6988 field_value = vmcs_read16(field);
6989 break;
6990 case VMCS_FIELD_TYPE_U32:
6991 field_value = vmcs_read32(field);
6992 break;
6993 case VMCS_FIELD_TYPE_U64:
6994 field_value = vmcs_read64(field);
6995 break;
6996 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6997 field_value = vmcs_readl(field);
6998 break;
a2ae9df7
PB		 6999 default:
7000 WARN_ON(1);
7001 continue;
16f5b903
AG		 7002 }
7003 vmcs12_write_any(&vmx->vcpu, field, field_value);
7004 }
7005
7006 vmcs_clear(shadow_vmcs);
7007 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 7008
7009 preempt_enable();
16f5b903
AG		 7010}
7011
c3114420
AG		 7012static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7013{
c2bae893
MK		 7014 const unsigned long *fields[] = {
7015 shadow_read_write_fields,
7016 shadow_read_only_fields
c3114420 7017 };
c2bae893 7018 const int max_fields[] = {
c3114420
AG		 7019 max_shadow_read_write_fields,
7020 max_shadow_read_only_fields
7021 };
7022 int i, q;
7023 unsigned long field;
7024 u64 field_value = 0;
7025 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7026
7027 vmcs_load(shadow_vmcs);
7028
c2bae893 7029 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 7030 for (i = 0; i < max_fields[q]; i++) {
7031 field = fields[q][i];
7032 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7033
7034 switch (vmcs_field_type(field)) {
7035 case VMCS_FIELD_TYPE_U16:
7036 vmcs_write16(field, (u16)field_value);
7037 break;
7038 case VMCS_FIELD_TYPE_U32:
7039 vmcs_write32(field, (u32)field_value);
7040 break;
7041 case VMCS_FIELD_TYPE_U64:
7042 vmcs_write64(field, (u64)field_value);
7043 break;
7044 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7045 vmcs_writel(field, (long)field_value);
7046 break;
a2ae9df7
PB		 7047 default:
7048 WARN_ON(1);
7049 break;
c3114420
AG		 7050 }
7051 }
7052 }
7053
7054 vmcs_clear(shadow_vmcs);
7055 vmcs_load(vmx->loaded_vmcs->vmcs);
7056}
7057
49f705c5
NHE		 7058/*
7059 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7060 * used before) all generate the same failure when it is missing.
7061 */
7062static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7063{
7064 struct vcpu_vmx *vmx = to_vmx(vcpu);
7065 if (vmx->nested.current_vmptr == -1ull) {
7066 nested_vmx_failInvalid(vcpu);
7067 skip_emulated_instruction(vcpu);
7068 return 0;
7069 }
7070 return 1;
7071}
7072
7073static int handle_vmread(struct kvm_vcpu *vcpu)
7074{
7075 unsigned long field;
7076 u64 field_value;
7077 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7078 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7079 gva_t gva = 0;
7080
7081 if (!nested_vmx_check_permission(vcpu) ||
7082 !nested_vmx_check_vmcs12(vcpu))
7083 return 1;
7084
7085 /* Decode instruction info and find the field to read */
27e6fb5d 7086 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 7087 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 7088 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 7089 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7090 skip_emulated_instruction(vcpu);
7091 return 1;
7092 }
7093 /*
7094 * Now copy part of this value to register or memory, as requested.
7095 * Note that the number of bits actually copied is 32 or 64 depending
7096 * on the guest's mode (32 or 64 bit), not on the given field's length.
7097 */
7098 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 7099 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 7100 field_value);
7101 } else {
7102 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7103 vmx_instruction_info, true, &gva))
49f705c5
NHE		 7104 return 1;
7105 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7106 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7107 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7108 }
7109
7110 nested_vmx_succeed(vcpu);
7111 skip_emulated_instruction(vcpu);
7112 return 1;
7113}
7114
7115
7116static int handle_vmwrite(struct kvm_vcpu *vcpu)
7117{
7118 unsigned long field;
7119 gva_t gva;
7120 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7121 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 7122 /* The value to write might be 32 or 64 bits, depending on L1's long
7123 * mode, and eventually we need to write that into a field of several
7124 * possible lengths. The code below first zero-extends the value to 64
7125 * bit (field_value), and then copies only the approriate number of
7126 * bits into the vmcs12 field.
7127 */
7128 u64 field_value = 0;
7129 struct x86_exception e;
7130
7131 if (!nested_vmx_check_permission(vcpu) ||
7132 !nested_vmx_check_vmcs12(vcpu))
7133 return 1;
7134
7135 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7136 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 7137 (((vmx_instruction_info) >> 3) & 0xf));
7138 else {
7139 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7140 vmx_instruction_info, false, &gva))
49f705c5
NHE		 7141 return 1;
7142 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7143 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 7144 kvm_inject_page_fault(vcpu, &e);
7145 return 1;
7146 }
7147 }
7148
7149
27e6fb5d 7150 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 7151 if (vmcs_field_readonly(field)) {
7152 nested_vmx_failValid(vcpu,
7153 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7154 skip_emulated_instruction(vcpu);
7155 return 1;
7156 }
7157
a2ae9df7 7158 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 7159 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7160 skip_emulated_instruction(vcpu);
7161 return 1;
7162 }
7163
7164 nested_vmx_succeed(vcpu);
7165 skip_emulated_instruction(vcpu);
7166 return 1;
7167}
7168
63846663
NHE		 7169/* Emulate the VMPTRLD instruction */
7170static int handle_vmptrld(struct kvm_vcpu *vcpu)
7171{
7172 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7173 gpa_t vmptr;
63846663
NHE		 7174
7175 if (!nested_vmx_check_permission(vcpu))
7176 return 1;
7177
4291b588 7178 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 7179 return 1;
63846663
NHE		 7180
7181 if (vmx->nested.current_vmptr != vmptr) {
7182 struct vmcs12 *new_vmcs12;
7183 struct page *page;
7184 page = nested_get_page(vcpu, vmptr);
7185 if (page == NULL) {
7186 nested_vmx_failInvalid(vcpu);
7187 skip_emulated_instruction(vcpu);
7188 return 1;
7189 }
7190 new_vmcs12 = kmap(page);
7191 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7192 kunmap(page);
7193 nested_release_page_clean(page);
7194 nested_vmx_failValid(vcpu,
7195 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7196 skip_emulated_instruction(vcpu);
7197 return 1;
7198 }
63846663 7199
9a2a05b9 7200 nested_release_vmcs12(vmx);
63846663
NHE		 7201 vmx->nested.current_vmptr = vmptr;
7202 vmx->nested.current_vmcs12 = new_vmcs12;
7203 vmx->nested.current_vmcs12_page = page;
012f83cb 7204 if (enable_shadow_vmcs) {
7ec36296
XG		 7205 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7206 SECONDARY_EXEC_SHADOW_VMCS);
8a1b9dd0
AG		 7207 vmcs_write64(VMCS_LINK_POINTER,
7208 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 7209 vmx->nested.sync_shadow_vmcs = true;
7210 }
63846663
NHE		 7211 }
7212
7213 nested_vmx_succeed(vcpu);
7214 skip_emulated_instruction(vcpu);
7215 return 1;
7216}
7217
6a4d7550
NHE		 7218/* Emulate the VMPTRST instruction */
7219static int handle_vmptrst(struct kvm_vcpu *vcpu)
7220{
7221 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7222 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7223 gva_t vmcs_gva;
7224 struct x86_exception e;
7225
7226 if (!nested_vmx_check_permission(vcpu))
7227 return 1;
7228
7229 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7230 vmx_instruction_info, true, &vmcs_gva))
6a4d7550
NHE		 7231 return 1;
7232 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7233 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7234 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7235 sizeof(u64), &e)) {
7236 kvm_inject_page_fault(vcpu, &e);
7237 return 1;
7238 }
7239 nested_vmx_succeed(vcpu);
7240 skip_emulated_instruction(vcpu);
7241 return 1;
7242}
7243
bfd0a56b
NHE		 7244/* Emulate the INVEPT instruction */
7245static int handle_invept(struct kvm_vcpu *vcpu)
7246{
b9c237bb 7247 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7248 u32 vmx_instruction_info, types;
7249 unsigned long type;
7250 gva_t gva;
7251 struct x86_exception e;
7252 struct {
7253 u64 eptp, gpa;
7254 } operand;
bfd0a56b 7255
b9c237bb
WV		 7256 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7257 SECONDARY_EXEC_ENABLE_EPT) ||
7258 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7259 kvm_queue_exception(vcpu, UD_VECTOR);
7260 return 1;
7261 }
7262
7263 if (!nested_vmx_check_permission(vcpu))
7264 return 1;
7265
7266 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7267 kvm_queue_exception(vcpu, UD_VECTOR);
7268 return 1;
7269 }
7270
7271 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7272 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7273
b9c237bb 7274 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7275
7276 if (!(types & (1UL << type))) {
7277 nested_vmx_failValid(vcpu,
7278 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7279 return 1;
7280 }
7281
7282 /* According to the Intel VMX instruction reference, the memory
7283 * operand is read even if it isn't needed (e.g., for type==global)
7284 */
7285 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7286 vmx_instruction_info, false, &gva))
bfd0a56b
NHE		 7287 return 1;
7288 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7289 sizeof(operand), &e)) {
7290 kvm_inject_page_fault(vcpu, &e);
7291 return 1;
7292 }
7293
7294 switch (type) {
bfd0a56b
NHE		 7295 case VMX_EPT_EXTENT_GLOBAL:
7296 kvm_mmu_sync_roots(vcpu);
77c3913b 7297 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7298 nested_vmx_succeed(vcpu);
7299 break;
7300 default:
4b855078 7301 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7302 BUG_ON(1);
7303 break;
7304 }
7305
7306 skip_emulated_instruction(vcpu);
7307 return 1;
7308}
7309
a642fc30
PM		 7310static int handle_invvpid(struct kvm_vcpu *vcpu)
7311{
7312 kvm_queue_exception(vcpu, UD_VECTOR);
7313 return 1;
7314}
7315
843e4330
KH		 7316static int handle_pml_full(struct kvm_vcpu *vcpu)
7317{
7318 unsigned long exit_qualification;
7319
7320 trace_kvm_pml_full(vcpu->vcpu_id);
7321
7322 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7323
7324 /*
7325 * PML buffer FULL happened while executing iret from NMI,
7326 * "blocked by NMI" bit has to be set before next VM entry.
7327 */
7328 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7329 cpu_has_virtual_nmis() &&
7330 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7331 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7332 GUEST_INTR_STATE_NMI);
7333
7334 /*
7335 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7336 * here.., and there's no userspace involvement needed for PML.
7337 */
7338 return 1;
7339}
7340
8b3e34e4
XG		 7341static int handle_pcommit(struct kvm_vcpu *vcpu)
7342{
7343 /* we never catch pcommit instruct for L1 guest. */
7344 WARN_ON(1);
7345 return 1;
7346}
7347
6aa8b732
AK		 7348/*
7349 * The exit handlers return 1 if the exit was handled fully and guest execution
7350 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7351 * to be done to userspace and return 0.
7352 */
772e0318 7353static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7354 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7355 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7356 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7357 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7358 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7359 [EXIT_REASON_CR_ACCESS] = handle_cr,
7360 [EXIT_REASON_DR_ACCESS] = handle_dr,
7361 [EXIT_REASON_CPUID] = handle_cpuid,
7362 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7363 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7364 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7365 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7366 [EXIT_REASON_INVD] = handle_invd,
a7052897 7367 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7368 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7369 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7370 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7371 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7372 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7373 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7374 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7375 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7376 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7377 [EXIT_REASON_VMOFF] = handle_vmoff,
7378 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7379 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7380 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7381 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7382 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7383 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7384 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7385 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7386 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7387 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7388 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7389 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7390 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7391 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7392 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7393 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7394 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7395 [EXIT_REASON_XSAVES] = handle_xsaves,
7396 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7397 [EXIT_REASON_PML_FULL] = handle_pml_full,
8b3e34e4 7398 [EXIT_REASON_PCOMMIT] = handle_pcommit,
6aa8b732
AK		 7399};
7400
7401static const int kvm_vmx_max_exit_handlers =
50a3485c 7402 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7403
908a7bdd
JK		 7404static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7405 struct vmcs12 *vmcs12)
7406{
7407 unsigned long exit_qualification;
7408 gpa_t bitmap, last_bitmap;
7409 unsigned int port;
7410 int size;
7411 u8 b;
7412
908a7bdd 7413 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7414 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7415
7416 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7417
7418 port = exit_qualification >> 16;
7419 size = (exit_qualification & 7) + 1;
7420
7421 last_bitmap = (gpa_t)-1;
7422 b = -1;
7423
7424 while (size > 0) {
7425 if (port < 0x8000)
7426 bitmap = vmcs12->io_bitmap_a;
7427 else if (port < 0x10000)
7428 bitmap = vmcs12->io_bitmap_b;
7429 else
1d804d07 7430 return true;
908a7bdd
JK		 7431 bitmap += (port & 0x7fff) / 8;
7432
7433 if (last_bitmap != bitmap)
54bf36aa 7434 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7435 return true;
908a7bdd 7436 if (b & (1 << (port & 7)))
1d804d07 7437 return true;
908a7bdd
JK		 7438
7439 port++;
7440 size--;
7441 last_bitmap = bitmap;
7442 }
7443
1d804d07 7444 return false;
908a7bdd
JK		 7445}
7446
644d711a
NHE		 7447/*
7448 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7449 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7450 * disinterest in the current event (read or write a specific MSR) by using an
7451 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7452 */
7453static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7454 struct vmcs12 *vmcs12, u32 exit_reason)
7455{
7456 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7457 gpa_t bitmap;
7458
cbd29cb6 7459 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7460 return true;
644d711a
NHE		 7461
7462 /*
7463 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7464 * for the four combinations of read/write and low/high MSR numbers.
7465 * First we need to figure out which of the four to use:
7466 */
7467 bitmap = vmcs12->msr_bitmap;
7468 if (exit_reason == EXIT_REASON_MSR_WRITE)
7469 bitmap += 2048;
7470 if (msr_index >= 0xc0000000) {
7471 msr_index -= 0xc0000000;
7472 bitmap += 1024;
7473 }
7474
7475 /* Then read the msr_index'th bit from this bitmap: */
7476 if (msr_index < 1024*8) {
7477 unsigned char b;
54bf36aa 7478 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7479 return true;
644d711a
NHE		 7480 return 1 & (b >> (msr_index & 7));
7481 } else
1d804d07 7482 return true; /* let L1 handle the wrong parameter */
644d711a
NHE		 7483}
7484
7485/*
7486 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7487 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7488 * intercept (via guest_host_mask etc.) the current event.
7489 */
7490static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7491 struct vmcs12 *vmcs12)
7492{
7493 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7494 int cr = exit_qualification & 15;
7495 int reg = (exit_qualification >> 8) & 15;
1e32c079 7496 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7497
7498 switch ((exit_qualification >> 4) & 3) {
7499 case 0: /* mov to cr */
7500 switch (cr) {
7501 case 0:
7502 if (vmcs12->cr0_guest_host_mask &
7503 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7504 return true;
644d711a
NHE		 7505 break;
7506 case 3:
7507 if ((vmcs12->cr3_target_count >= 1 &&
7508 vmcs12->cr3_target_value0 == val) ||
7509 (vmcs12->cr3_target_count >= 2 &&
7510 vmcs12->cr3_target_value1 == val) ||
7511 (vmcs12->cr3_target_count >= 3 &&
7512 vmcs12->cr3_target_value2 == val) ||
7513 (vmcs12->cr3_target_count >= 4 &&
7514 vmcs12->cr3_target_value3 == val))
1d804d07 7515 return false;
644d711a 7516 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7517 return true;
644d711a
NHE		 7518 break;
7519 case 4:
7520 if (vmcs12->cr4_guest_host_mask &
7521 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7522 return true;
644d711a
NHE		 7523 break;
7524 case 8:
7525 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7526 return true;
644d711a
NHE		 7527 break;
7528 }
7529 break;
7530 case 2: /* clts */
7531 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7532 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7533 return true;
644d711a
NHE		 7534 break;
7535 case 1: /* mov from cr */
7536 switch (cr) {
7537 case 3:
7538 if (vmcs12->cpu_based_vm_exec_control &
7539 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7540 return true;
644d711a
NHE		 7541 break;
7542 case 8:
7543 if (vmcs12->cpu_based_vm_exec_control &
7544 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7545 return true;
644d711a
NHE		 7546 break;
7547 }
7548 break;
7549 case 3: /* lmsw */
7550 /*
7551 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7552 * cr0. Other attempted changes are ignored, with no exit.
7553 */
7554 if (vmcs12->cr0_guest_host_mask & 0xe &
7555 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7556 return true;
644d711a
NHE		 7557 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7558 !(vmcs12->cr0_read_shadow & 0x1) &&
7559 (val & 0x1))
1d804d07 7560 return true;
644d711a
NHE		 7561 break;
7562 }
1d804d07 7563 return false;
644d711a
NHE		 7564}
7565
7566/*
7567 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7568 * should handle it ourselves in L0 (and then continue L2). Only call this
7569 * when in is_guest_mode (L2).
7570 */
7571static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7572{
644d711a
NHE		 7573 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7574 struct vcpu_vmx *vmx = to_vmx(vcpu);
7575 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7576 u32 exit_reason = vmx->exit_reason;
644d711a 7577
542060ea
JK		 7578 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7579 vmcs_readl(EXIT_QUALIFICATION),
7580 vmx->idt_vectoring_info,
7581 intr_info,
7582 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7583 KVM_ISA_VMX);
7584
644d711a 7585 if (vmx->nested.nested_run_pending)
1d804d07 7586 return false;
644d711a
NHE		 7587
7588 if (unlikely(vmx->fail)) {
bd80158a
JK		 7589 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7590 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 7591 return true;
644d711a
NHE		 7592 }
7593
7594 switch (exit_reason) {
7595 case EXIT_REASON_EXCEPTION_NMI:
7596 if (!is_exception(intr_info))
1d804d07 7597 return false;
644d711a
NHE		 7598 else if (is_page_fault(intr_info))
7599 return enable_ept;
e504c909 7600 else if (is_no_device(intr_info) &&
ccf9844e 7601 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 7602 return false;
644d711a
NHE		 7603 return vmcs12->exception_bitmap &
7604 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7605 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 7606 return false;
644d711a 7607 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 7608 return true;
644d711a 7609 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7610 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7611 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7612 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 7613 case EXIT_REASON_TASK_SWITCH:
1d804d07 7614 return true;
644d711a 7615 case EXIT_REASON_CPUID:
bc613494 7616 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
1d804d07
JP		 7617 return false;
7618 return true;
644d711a
NHE		 7619 case EXIT_REASON_HLT:
7620 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7621 case EXIT_REASON_INVD:
1d804d07 7622 return true;
644d711a
NHE		 7623 case EXIT_REASON_INVLPG:
7624 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7625 case EXIT_REASON_RDPMC:
7626 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
b3a2a907 7627 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE		 7628 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7629 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7630 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7631 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7632 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7633 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7634 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7635 /*
7636 * VMX instructions trap unconditionally. This allows L1 to
7637 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7638 */
1d804d07 7639 return true;
644d711a
NHE		 7640 case EXIT_REASON_CR_ACCESS:
7641 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7642 case EXIT_REASON_DR_ACCESS:
7643 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7644 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7645 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7646 case EXIT_REASON_MSR_READ:
7647 case EXIT_REASON_MSR_WRITE:
7648 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7649 case EXIT_REASON_INVALID_STATE:
1d804d07 7650 return true;
644d711a
NHE		 7651 case EXIT_REASON_MWAIT_INSTRUCTION:
7652 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD		 7653 case EXIT_REASON_MONITOR_TRAP_FLAG:
7654 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE		 7655 case EXIT_REASON_MONITOR_INSTRUCTION:
7656 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7657 case EXIT_REASON_PAUSE_INSTRUCTION:
7658 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7659 nested_cpu_has2(vmcs12,
7660 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7661 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 7662 return false;
644d711a 7663 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7664 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7665 case EXIT_REASON_APIC_ACCESS:
7666 return nested_cpu_has2(vmcs12,
7667 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 7668 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 7669 case EXIT_REASON_EOI_INDUCED:
7670 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 7671 return true;
644d711a 7672 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7673 /*
7674 * L0 always deals with the EPT violation. If nested EPT is
7675 * used, and the nested mmu code discovers that the address is
7676 * missing in the guest EPT table (EPT12), the EPT violation
7677 * will be injected with nested_ept_inject_page_fault()
7678 */
1d804d07 7679 return false;
644d711a 7680 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7681 /*
7682 * L2 never uses directly L1's EPT, but rather L0's own EPT
7683 * table (shadow on EPT) or a merged EPT table that L0 built
7684 * (EPT on EPT). So any problems with the structure of the
7685 * table is L0's fault.
7686 */
1d804d07 7687 return false;
644d711a
NHE		 7688 case EXIT_REASON_WBINVD:
7689 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7690 case EXIT_REASON_XSETBV:
1d804d07 7691 return true;
81dc01f7
WL		 7692 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7693 /*
7694 * This should never happen, since it is not possible to
7695 * set XSS to a non-zero value---neither in L1 nor in L2.
7696 * If if it were, XSS would have to be checked against
7697 * the XSS exit bitmap in vmcs12.
7698 */
7699 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8b3e34e4
XG		 7700 case EXIT_REASON_PCOMMIT:
7701 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
644d711a 7702 default:
1d804d07 7703 return true;
644d711a
NHE		 7704 }
7705}
7706
586f9607
AK		 7707static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7708{
7709 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7710 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7711}
7712
843e4330
KH		 7713static int vmx_enable_pml(struct vcpu_vmx *vmx)
7714{
7715 struct page *pml_pg;
843e4330
KH		 7716
7717 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7718 if (!pml_pg)
7719 return -ENOMEM;
7720
7721 vmx->pml_pg = pml_pg;
7722
7723 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7724 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7725
7ec36296 7726 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_ENABLE_PML);
843e4330
KH		 7727
7728 return 0;
7729}
7730
7731static void vmx_disable_pml(struct vcpu_vmx *vmx)
7732{
843e4330
KH		 7733 ASSERT(vmx->pml_pg);
7734 __free_page(vmx->pml_pg);
7735 vmx->pml_pg = NULL;
7736
7ec36296 7737 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_ENABLE_PML);
843e4330
KH		 7738}
7739
54bf36aa 7740static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 7741{
54bf36aa 7742 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH		 7743 u64 *pml_buf;
7744 u16 pml_idx;
7745
7746 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7747
7748 /* Do nothing if PML buffer is empty */
7749 if (pml_idx == (PML_ENTITY_NUM - 1))
7750 return;
7751
7752 /* PML index always points to next available PML buffer entity */
7753 if (pml_idx >= PML_ENTITY_NUM)
7754 pml_idx = 0;
7755 else
7756 pml_idx++;
7757
7758 pml_buf = page_address(vmx->pml_pg);
7759 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7760 u64 gpa;
7761
7762 gpa = pml_buf[pml_idx];
7763 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 7764 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH		 7765 }
7766
7767 /* reset PML index */
7768 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7769}
7770
7771/*
7772 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7773 * Called before reporting dirty_bitmap to userspace.
7774 */
7775static void kvm_flush_pml_buffers(struct kvm *kvm)
7776{
7777 int i;
7778 struct kvm_vcpu *vcpu;
7779 /*
7780 * We only need to kick vcpu out of guest mode here, as PML buffer
7781 * is flushed at beginning of all VMEXITs, and it's obvious that only
7782 * vcpus running in guest are possible to have unflushed GPAs in PML
7783 * buffer.
7784 */
7785 kvm_for_each_vcpu(i, vcpu, kvm)
7786 kvm_vcpu_kick(vcpu);
7787}
7788
4eb64dce
PB		 7789static void vmx_dump_sel(char *name, uint32_t sel)
7790{
7791 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7792 name, vmcs_read32(sel),
7793 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7794 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7795 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7796}
7797
7798static void vmx_dump_dtsel(char *name, uint32_t limit)
7799{
7800 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7801 name, vmcs_read32(limit),
7802 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7803}
7804
7805static void dump_vmcs(void)
7806{
7807 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7808 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7809 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7810 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7811 u32 secondary_exec_control = 0;
7812 unsigned long cr4 = vmcs_readl(GUEST_CR4);
7813 u64 efer = vmcs_readl(GUEST_IA32_EFER);
7814 int i, n;
7815
7816 if (cpu_has_secondary_exec_ctrls())
7817 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7818
7819 pr_err("*** Guest State ***\n");
7820 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7821 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7822 vmcs_readl(CR0_GUEST_HOST_MASK));
7823 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7824 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7825 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7826 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7827 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7828 {
7829 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7830 vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7831 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7832 vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7833 }
7834 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7835 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7836 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7837 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7838 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7839 vmcs_readl(GUEST_SYSENTER_ESP),
7840 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7841 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
7842 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
7843 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
7844 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
7845 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
7846 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
7847 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7848 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7849 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7850 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
7851 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7852 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7853 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7854 efer, vmcs_readl(GUEST_IA32_PAT));
7855 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7856 vmcs_readl(GUEST_IA32_DEBUGCTL),
7857 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7858 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7859 pr_err("PerfGlobCtl = 0x%016lx\n",
7860 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7861 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7862 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7863 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7864 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7865 vmcs_read32(GUEST_ACTIVITY_STATE));
7866 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7867 pr_err("InterruptStatus = %04x\n",
7868 vmcs_read16(GUEST_INTR_STATUS));
7869
7870 pr_err("*** Host State ***\n");
7871 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7872 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7873 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7874 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7875 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7876 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7877 vmcs_read16(HOST_TR_SELECTOR));
7878 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7879 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7880 vmcs_readl(HOST_TR_BASE));
7881 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7882 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7883 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7884 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7885 vmcs_readl(HOST_CR4));
7886 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7887 vmcs_readl(HOST_IA32_SYSENTER_ESP),
7888 vmcs_read32(HOST_IA32_SYSENTER_CS),
7889 vmcs_readl(HOST_IA32_SYSENTER_EIP));
7890 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7891 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7892 vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7893 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7894 pr_err("PerfGlobCtl = 0x%016lx\n",
7895 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7896
7897 pr_err("*** Control State ***\n");
7898 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7899 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7900 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7901 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7902 vmcs_read32(EXCEPTION_BITMAP),
7903 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7904 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7905 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7906 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7907 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
7908 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
7909 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
7910 vmcs_read32(VM_EXIT_INTR_INFO),
7911 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7912 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
7913 pr_err(" reason=%08x qualification=%016lx\n",
7914 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
7915 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
7916 vmcs_read32(IDT_VECTORING_INFO_FIELD),
7917 vmcs_read32(IDT_VECTORING_ERROR_CODE));
7918 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
7919 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
7920 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
7921 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
7922 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
7923 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
7924 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
7925 n = vmcs_read32(CR3_TARGET_COUNT);
7926 for (i = 0; i + 1 < n; i += 4)
7927 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
7928 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
7929 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
7930 if (i < n)
7931 pr_err("CR3 target%u=%016lx\n",
7932 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
7933 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
7934 pr_err("PLE Gap=%08x Window=%08x\n",
7935 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
7936 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
7937 pr_err("Virtual processor ID = 0x%04x\n",
7938 vmcs_read16(VIRTUAL_PROCESSOR_ID));
7939}
7940
6aa8b732
AK		 7941/*
7942 * The guest has exited. See if we can fix it or if we need userspace
7943 * assistance.
7944 */
851ba692 7945static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7946{
29bd8a78 7947 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7948 u32 exit_reason = vmx->exit_reason;
1155f76a 7949 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7950
843e4330
KH		 7951 /*
7952 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7953 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7954 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7955 * mode as if vcpus is in root mode, the PML buffer must has been
7956 * flushed already.
7957 */
7958 if (enable_pml)
54bf36aa 7959 vmx_flush_pml_buffer(vcpu);
843e4330 7960
80ced186 7961 /* If guest state is invalid, start emulating */
14168786 7962 if (vmx->emulation_required)
80ced186 7963 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7964
644d711a 7965 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7966 nested_vmx_vmexit(vcpu, exit_reason,
7967 vmcs_read32(VM_EXIT_INTR_INFO),
7968 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7969 return 1;
7970 }
7971
5120702e 7972 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 7973 dump_vmcs();
5120702e
MG		 7974 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7975 vcpu->run->fail_entry.hardware_entry_failure_reason
7976 = exit_reason;
7977 return 0;
7978 }
7979
29bd8a78 7980 if (unlikely(vmx->fail)) {
851ba692
AK		 7981 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7982 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7983 = vmcs_read32(VM_INSTRUCTION_ERROR);
7984 return 0;
7985 }
6aa8b732 7986
b9bf6882
XG		 7987 /*
7988 * Note:
7989 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7990 * delivery event since it indicates guest is accessing MMIO.
7991 * The vm-exit can be triggered again after return to guest that
7992 * will cause infinite loop.
7993 */
d77c26fc 7994 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7995 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7996 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7997 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7998 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7999 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8000 vcpu->run->internal.ndata = 2;
8001 vcpu->run->internal.data[0] = vectoring_info;
8002 vcpu->run->internal.data[1] = exit_reason;
8003 return 0;
8004 }
3b86cd99 8005
644d711a
NHE		 8006 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8007 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 8008 get_vmcs12(vcpu))))) {
c4282df9 8009 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 8010 vmx->soft_vnmi_blocked = 0;
3b86cd99 8011 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 8012 vcpu->arch.nmi_pending) {
3b86cd99
JK		 8013 /*
8014 * This CPU don't support us in finding the end of an
8015 * NMI-blocked window if the guest runs with IRQs
8016 * disabled. So we pull the trigger after 1 s of
8017 * futile waiting, but inform the user about this.
8018 */
8019 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8020 "state on VCPU %d after 1 s timeout\n",
8021 __func__, vcpu->vcpu_id);
8022 vmx->soft_vnmi_blocked = 0;
3b86cd99 8023 }
3b86cd99
JK		 8024 }
8025
6aa8b732
AK		 8026 if (exit_reason < kvm_vmx_max_exit_handlers
8027 && kvm_vmx_exit_handlers[exit_reason])
851ba692 8028 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 8029 else {
2bc19dc3
MT		 8030 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8031 kvm_queue_exception(vcpu, UD_VECTOR);
8032 return 1;
6aa8b732 8033 }
6aa8b732
AK		 8034}
8035
95ba8273 8036static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 8037{
a7c0b07d
WL		 8038 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8039
8040 if (is_guest_mode(vcpu) &&
8041 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8042 return;
8043
95ba8273 8044 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 8045 vmcs_write32(TPR_THRESHOLD, 0);
8046 return;
8047 }
8048
95ba8273 8049 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 8050}
8051
8d14695f
YZ		 8052static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8053{
8054 u32 sec_exec_control;
8055
8056 /*
8057 * There is not point to enable virtualize x2apic without enable
8058 * apicv
8059 */
c7c9c56c 8060 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
35754c98 8061 !vmx_cpu_uses_apicv(vcpu))
8d14695f
YZ		 8062 return;
8063
35754c98 8064 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ		 8065 return;
8066
8067 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8068
8069 if (set) {
8070 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8071 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8072 } else {
8073 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8074 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8075 }
8076 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8077
8078 vmx_set_msr_bitmap(vcpu);
8079}
8080
38b99173
TC		 8081static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8082{
8083 struct vcpu_vmx *vmx = to_vmx(vcpu);
8084
8085 /*
8086 * Currently we do not handle the nested case where L2 has an
8087 * APIC access page of its own; that page is still pinned.
8088 * Hence, we skip the case where the VCPU is in guest mode _and_
8089 * L1 prepared an APIC access page for L2.
8090 *
8091 * For the case where L1 and L2 share the same APIC access page
8092 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8093 * in the vmcs12), this function will only update either the vmcs01
8094 * or the vmcs02. If the former, the vmcs02 will be updated by
8095 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8096 * the next L2->L1 exit.
8097 */
8098 if (!is_guest_mode(vcpu) ||
8099 !nested_cpu_has2(vmx->nested.current_vmcs12,
8100 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8101 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8102}
8103
c7c9c56c
YZ		 8104static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8105{
8106 u16 status;
8107 u8 old;
8108
c7c9c56c
YZ		 8109 if (isr == -1)
8110 isr = 0;
8111
8112 status = vmcs_read16(GUEST_INTR_STATUS);
8113 old = status >> 8;
8114 if (isr != old) {
8115 status &= 0xff;
8116 status |= isr << 8;
8117 vmcs_write16(GUEST_INTR_STATUS, status);
8118 }
8119}
8120
8121static void vmx_set_rvi(int vector)
8122{
8123 u16 status;
8124 u8 old;
8125
4114c27d
WW		 8126 if (vector == -1)
8127 vector = 0;
8128
c7c9c56c
YZ		 8129 status = vmcs_read16(GUEST_INTR_STATUS);
8130 old = (u8)status & 0xff;
8131 if ((u8)vector != old) {
8132 status &= ~0xff;
8133 status |= (u8)vector;
8134 vmcs_write16(GUEST_INTR_STATUS, status);
8135 }
8136}
8137
8138static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8139{
4114c27d
WW		 8140 if (!is_guest_mode(vcpu)) {
8141 vmx_set_rvi(max_irr);
8142 return;
8143 }
8144
c7c9c56c
YZ		 8145 if (max_irr == -1)
8146 return;
8147
963fee16 8148 /*
4114c27d
WW		 8149 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8150 * handles it.
963fee16 8151 */
4114c27d 8152 if (nested_exit_on_intr(vcpu))
963fee16
WL		 8153 return;
8154
963fee16 8155 /*
4114c27d 8156 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 8157 * is run without virtual interrupt delivery.
8158 */
8159 if (!kvm_event_needs_reinjection(vcpu) &&
8160 vmx_interrupt_allowed(vcpu)) {
8161 kvm_queue_interrupt(vcpu, max_irr, false);
8162 vmx_inject_irq(vcpu);
8163 }
c7c9c56c
YZ		 8164}
8165
3bb345f3 8166static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
c7c9c56c 8167{
3bb345f3 8168 u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
35754c98 8169 if (!vmx_cpu_uses_apicv(vcpu))
3d81bc7e
YZ		 8170 return;
8171
c7c9c56c
YZ		 8172 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8173 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8174 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8175 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8176}
8177
51aa01d1 8178static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8179{
00eba012
AK		 8180 u32 exit_intr_info;
8181
8182 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8183 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8184 return;
8185
c5ca8e57 8186 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 8187 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 8188
8189 /* Handle machine checks before interrupts are enabled */
00eba012 8190 if (is_machine_check(exit_intr_info))
a0861c02
AK		 8191 kvm_machine_check();
8192
20f65983 8193 /* We need to handle NMIs before interrupts are enabled */
00eba012 8194 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 8195 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8196 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8197 asm("int $2");
ff9d07a0
ZY		 8198 kvm_after_handle_nmi(&vmx->vcpu);
8199 }
51aa01d1 8200}
20f65983 8201
a547c6db
YZ		 8202static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8203{
8204 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8205
8206 /*
8207 * If external interrupt exists, IF bit is set in rflags/eflags on the
8208 * interrupt stack frame, and interrupt will be enabled on a return
8209 * from interrupt handler.
8210 */
8211 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8212 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8213 unsigned int vector;
8214 unsigned long entry;
8215 gate_desc *desc;
8216 struct vcpu_vmx *vmx = to_vmx(vcpu);
8217#ifdef CONFIG_X86_64
8218 unsigned long tmp;
8219#endif
8220
8221 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8222 desc = (gate_desc *)vmx->host_idt_base + vector;
8223 entry = gate_offset(*desc);
8224 asm volatile(
8225#ifdef CONFIG_X86_64
8226 "mov %%" _ASM_SP ", %[sp]\n\t"
8227 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8228 "push $%c[ss]\n\t"
8229 "push %[sp]\n\t"
8230#endif
8231 "pushf\n\t"
8232 "orl $0x200, (%%" _ASM_SP ")\n\t"
8233 __ASM_SIZE(push) " $%c[cs]\n\t"
8234 "call *%[entry]\n\t"
8235 :
8236#ifdef CONFIG_X86_64
8237 [sp]"=&r"(tmp)
8238#endif
8239 :
8240 [entry]"r"(entry),
8241 [ss]"i"(__KERNEL_DS),
8242 [cs]"i"(__KERNEL_CS)
8243 );
8244 } else
8245 local_irq_enable();
8246}
8247
6d396b55
PB		 8248static bool vmx_has_high_real_mode_segbase(void)
8249{
8250 return enable_unrestricted_guest || emulate_invalid_guest_state;
8251}
8252
da8999d3
LJ		 8253static bool vmx_mpx_supported(void)
8254{
8255 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8256 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8257}
8258
55412b2e
WL		 8259static bool vmx_xsaves_supported(void)
8260{
8261 return vmcs_config.cpu_based_2nd_exec_ctrl &
8262 SECONDARY_EXEC_XSAVES;
8263}
8264
51aa01d1
AK		 8265static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8266{
c5ca8e57 8267 u32 exit_intr_info;
51aa01d1
AK		 8268 bool unblock_nmi;
8269 u8 vector;
8270 bool idtv_info_valid;
8271
8272 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8273
cf393f75 8274 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 8275 if (vmx->nmi_known_unmasked)
8276 return;
c5ca8e57
AK		 8277 /*
8278 * Can't use vmx->exit_intr_info since we're not sure what
8279 * the exit reason is.
8280 */
8281 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 8282 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8283 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8284 /*
7b4a25cb 8285 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 8286 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8287 * a guest IRET fault.
7b4a25cb
GN		 8288 * SDM 3: 23.2.2 (September 2008)
8289 * Bit 12 is undefined in any of the following cases:
8290 * If the VM exit sets the valid bit in the IDT-vectoring
8291 * information field.
8292 * If the VM exit is due to a double fault.
cf393f75 8293 */
7b4a25cb
GN		 8294 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8295 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 8296 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8297 GUEST_INTR_STATE_NMI);
9d58b931
AK		 8298 else
8299 vmx->nmi_known_unmasked =
8300 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8301 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 8302 } else if (unlikely(vmx->soft_vnmi_blocked))
8303 vmx->vnmi_blocked_time +=
8304 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 8305}
8306
3ab66e8a 8307static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 8308 u32 idt_vectoring_info,
8309 int instr_len_field,
8310 int error_code_field)
51aa01d1 8311{
51aa01d1
AK		 8312 u8 vector;
8313 int type;
8314 bool idtv_info_valid;
8315
8316 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8317
3ab66e8a
JK		 8318 vcpu->arch.nmi_injected = false;
8319 kvm_clear_exception_queue(vcpu);
8320 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 8321
8322 if (!idtv_info_valid)
8323 return;
8324
3ab66e8a 8325 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8326
668f612f
AK		 8327 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8328 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8329
64a7ec06 8330 switch (type) {
37b96e98 8331 case INTR_TYPE_NMI_INTR:
3ab66e8a 8332 vcpu->arch.nmi_injected = true;
668f612f 8333 /*
7b4a25cb 8334 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 8335 * Clear bit "block by NMI" before VM entry if a NMI
8336 * delivery faulted.
668f612f 8337 */
3ab66e8a 8338 vmx_set_nmi_mask(vcpu, false);
37b96e98 8339 break;
37b96e98 8340 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8341 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 8342 /* fall through */
8343 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8344 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8345 u32 err = vmcs_read32(error_code_field);
851eb667 8346 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8347 } else
851eb667 8348 kvm_requeue_exception(vcpu, vector);
37b96e98 8349 break;
66fd3f7f 8350 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8351 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8352 /* fall through */
37b96e98 8353 case INTR_TYPE_EXT_INTR:
3ab66e8a 8354 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 8355 break;
8356 default:
8357 break;
f7d9238f 8358 }
cf393f75
AK		 8359}
8360
83422e17
AK		 8361static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8362{
3ab66e8a 8363 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8364 VM_EXIT_INSTRUCTION_LEN,
8365 IDT_VECTORING_ERROR_CODE);
8366}
8367
b463a6f7
AK		 8368static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8369{
3ab66e8a 8370 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8371 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8372 VM_ENTRY_INSTRUCTION_LEN,
8373 VM_ENTRY_EXCEPTION_ERROR_CODE);
8374
8375 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8376}
8377
d7cd9796
GN		 8378static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8379{
8380 int i, nr_msrs;
8381 struct perf_guest_switch_msr *msrs;
8382
8383 msrs = perf_guest_get_msrs(&nr_msrs);
8384
8385 if (!msrs)
8386 return;
8387
8388 for (i = 0; i < nr_msrs; i++)
8389 if (msrs[i].host == msrs[i].guest)
8390 clear_atomic_switch_msr(vmx, msrs[i].msr);
8391 else
8392 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8393 msrs[i].host);
8394}
8395
a3b5ba49 8396static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8397{
a2fa3e9f 8398 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8399 unsigned long debugctlmsr, cr4;
104f226b
AK		 8400
8401 /* Record the guest's net vcpu time for enforced NMI injections. */
8402 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8403 vmx->entry_time = ktime_get();
8404
8405 /* Don't enter VMX if guest state is invalid, let the exit handler
8406 start emulation until we arrive back to a valid state */
14168786 8407 if (vmx->emulation_required)
104f226b
AK		 8408 return;
8409
a7653ecd
RK		 8410 if (vmx->ple_window_dirty) {
8411 vmx->ple_window_dirty = false;
8412 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8413 }
8414
012f83cb
AG		 8415 if (vmx->nested.sync_shadow_vmcs) {
8416 copy_vmcs12_to_shadow(vmx);
8417 vmx->nested.sync_shadow_vmcs = false;
8418 }
8419
104f226b
AK		 8420 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8421 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8422 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8423 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8424
1e02ce4c 8425 cr4 = cr4_read_shadow();
d974baa3
AL		 8426 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8427 vmcs_writel(HOST_CR4, cr4);
8428 vmx->host_state.vmcs_host_cr4 = cr4;
8429 }
8430
104f226b
AK		 8431 /* When single-stepping over STI and MOV SS, we must clear the
8432 * corresponding interruptibility bits in the guest state. Otherwise
8433 * vmentry fails as it then expects bit 14 (BS) in pending debug
8434 * exceptions being set, but that's not correct for the guest debugging
8435 * case. */
8436 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8437 vmx_set_interrupt_shadow(vcpu, 0);
8438
d7cd9796 8439 atomic_switch_perf_msrs(vmx);
2a7921b7 8440 debugctlmsr = get_debugctlmsr();
d7cd9796 8441
d462b819 8442 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8443 asm(
6aa8b732 8444 /* Store host registers */
b188c81f
AK		 8445 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8446 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8447 "push %%" _ASM_CX " \n\t"
8448 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8449 "je 1f \n\t"
b188c81f 8450 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8451 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8452 "1: \n\t"
d3edefc0 8453 /* Reload cr2 if changed */
b188c81f
AK		 8454 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8455 "mov %%cr2, %%" _ASM_DX " \n\t"
8456 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8457 "je 2f \n\t"
b188c81f 8458 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8459 "2: \n\t"
6aa8b732 8460 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8461 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8462 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8463 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8464 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8465 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8466 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8467 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8468 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8469#ifdef CONFIG_X86_64
e08aa78a
AK		 8470 "mov %c[r8](%0), %%r8 \n\t"
8471 "mov %c[r9](%0), %%r9 \n\t"
8472 "mov %c[r10](%0), %%r10 \n\t"
8473 "mov %c[r11](%0), %%r11 \n\t"
8474 "mov %c[r12](%0), %%r12 \n\t"
8475 "mov %c[r13](%0), %%r13 \n\t"
8476 "mov %c[r14](%0), %%r14 \n\t"
8477 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8478#endif
b188c81f 8479 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8480
6aa8b732 8481 /* Enter guest mode */
83287ea4 8482 "jne 1f \n\t"
4ecac3fd 8483 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8484 "jmp 2f \n\t"
8485 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8486 "2: "
6aa8b732 8487 /* Save guest registers, load host registers, keep flags */
b188c81f 8488 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8489 "pop %0 \n\t"
b188c81f
AK		 8490 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8491 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8492 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8493 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8494 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8495 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8496 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8497#ifdef CONFIG_X86_64
e08aa78a
AK		 8498 "mov %%r8, %c[r8](%0) \n\t"
8499 "mov %%r9, %c[r9](%0) \n\t"
8500 "mov %%r10, %c[r10](%0) \n\t"
8501 "mov %%r11, %c[r11](%0) \n\t"
8502 "mov %%r12, %c[r12](%0) \n\t"
8503 "mov %%r13, %c[r13](%0) \n\t"
8504 "mov %%r14, %c[r14](%0) \n\t"
8505 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8506#endif
b188c81f
AK		 8507 "mov %%cr2, %%" _ASM_AX " \n\t"
8508 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8509
b188c81f 8510 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8511 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8512 ".pushsection .rodata \n\t"
8513 ".global vmx_return \n\t"
8514 "vmx_return: " _ASM_PTR " 2b \n\t"
8515 ".popsection"
e08aa78a 8516 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8517 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8518 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8519 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8520 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8521 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8522 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8523 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8524 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8525 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8526 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8527#ifdef CONFIG_X86_64
ad312c7c
ZX		 8528 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8529 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8530 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8531 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8532 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8533 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8534 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8535 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8536#endif
40712fae
AK		 8537 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8538 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8539 : "cc", "memory"
8540#ifdef CONFIG_X86_64
b188c81f 8541 , "rax", "rbx", "rdi", "rsi"
c2036300 8542 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8543#else
8544 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8545#endif
8546 );
6aa8b732 8547
2a7921b7
GN		 8548 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8549 if (debugctlmsr)
8550 update_debugctlmsr(debugctlmsr);
8551
aa67f609
AK		 8552#ifndef CONFIG_X86_64
8553 /*
8554 * The sysexit path does not restore ds/es, so we must set them to
8555 * a reasonable value ourselves.
8556 *
8557 * We can't defer this to vmx_load_host_state() since that function
8558 * may be executed in interrupt context, which saves and restore segments
8559 * around it, nullifying its effect.
8560 */
8561 loadsegment(ds, __USER_DS);
8562 loadsegment(es, __USER_DS);
8563#endif
8564
6de4f3ad 8565 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8566 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8567 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8568 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8569 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8570 vcpu->arch.regs_dirty = 0;
8571
1155f76a
AK		 8572 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8573
d462b819 8574 vmx->loaded_vmcs->launched = 1;
1b6269db 8575
51aa01d1 8576 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8577 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8578
e0b890d3
GN		 8579 /*
8580 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8581 * we did not inject a still-pending event to L1 now because of
8582 * nested_run_pending, we need to re-enable this bit.
8583 */
8584 if (vmx->nested.nested_run_pending)
8585 kvm_make_request(KVM_REQ_EVENT, vcpu);
8586
8587 vmx->nested.nested_run_pending = 0;
8588
51aa01d1
AK		 8589 vmx_complete_atomic_exit(vmx);
8590 vmx_recover_nmi_blocking(vmx);
cf393f75 8591 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8592}
8593
4fa7734c
PB		 8594static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8595{
8596 struct vcpu_vmx *vmx = to_vmx(vcpu);
8597 int cpu;
8598
8599 if (vmx->loaded_vmcs == &vmx->vmcs01)
8600 return;
8601
8602 cpu = get_cpu();
8603 vmx->loaded_vmcs = &vmx->vmcs01;
8604 vmx_vcpu_put(vcpu);
8605 vmx_vcpu_load(vcpu, cpu);
8606 vcpu->cpu = cpu;
8607 put_cpu();
8608}
8609
6aa8b732
AK		 8610static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8611{
fb3f0f51
RR		 8612 struct vcpu_vmx *vmx = to_vmx(vcpu);
8613
843e4330
KH		 8614 if (enable_pml)
8615 vmx_disable_pml(vmx);
cdbecfc3 8616 free_vpid(vmx);
4fa7734c
PB		 8617 leave_guest_mode(vcpu);
8618 vmx_load_vmcs01(vcpu);
26a865f4 8619 free_nested(vmx);
4fa7734c 8620 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8621 kfree(vmx->guest_msrs);
8622 kvm_vcpu_uninit(vcpu);
a4770347 8623 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8624}
8625
fb3f0f51 8626static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8627{
fb3f0f51 8628 int err;
c16f862d 8629 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8630 int cpu;
6aa8b732 8631
a2fa3e9f 8632 if (!vmx)
fb3f0f51
RR		 8633 return ERR_PTR(-ENOMEM);
8634
2384d2b3
SY		 8635 allocate_vpid(vmx);
8636
fb3f0f51
RR		 8637 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8638 if (err)
8639 goto free_vcpu;
965b58a5 8640
a2fa3e9f 8641 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8642 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8643 > PAGE_SIZE);
0123be42 8644
be6d05cf 8645 err = -ENOMEM;
fb3f0f51 8646 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8647 goto uninit_vcpu;
8648 }
965b58a5 8649
d462b819
NHE		 8650 vmx->loaded_vmcs = &vmx->vmcs01;
8651 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8652 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8653 goto free_msrs;
d462b819
NHE		 8654 if (!vmm_exclusive)
8655 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8656 loaded_vmcs_init(vmx->loaded_vmcs);
8657 if (!vmm_exclusive)
8658 kvm_cpu_vmxoff();
a2fa3e9f 8659
15ad7146
AK		 8660 cpu = get_cpu();
8661 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8662 vmx->vcpu.cpu = cpu;
8b9cf98c 8663 err = vmx_vcpu_setup(vmx);
fb3f0f51 8664 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8665 put_cpu();
fb3f0f51
RR		 8666 if (err)
8667 goto free_vmcs;
35754c98 8668 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK		 8669 err = alloc_apic_access_page(kvm);
8670 if (err)
5e4a0b3c 8671 goto free_vmcs;
a63cb560 8672 }
fb3f0f51 8673
b927a3ce
SY		 8674 if (enable_ept) {
8675 if (!kvm->arch.ept_identity_map_addr)
8676 kvm->arch.ept_identity_map_addr =
8677 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8678 err = init_rmode_identity_map(kvm);
8679 if (err)
93ea5388 8680 goto free_vmcs;
b927a3ce 8681 }
b7ebfb05 8682
b9c237bb
WV		 8683 if (nested)
8684 nested_vmx_setup_ctls_msrs(vmx);
8685
705699a1 8686 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE		 8687 vmx->nested.current_vmptr = -1ull;
8688 vmx->nested.current_vmcs12 = NULL;
8689
843e4330
KH		 8690 /*
8691 * If PML is turned on, failure on enabling PML just results in failure
8692 * of creating the vcpu, therefore we can simplify PML logic (by
8693 * avoiding dealing with cases, such as enabling PML partially on vcpus
8694 * for the guest, etc.
8695 */
8696 if (enable_pml) {
8697 err = vmx_enable_pml(vmx);
8698 if (err)
8699 goto free_vmcs;
8700 }
8701
fb3f0f51
RR		 8702 return &vmx->vcpu;
8703
8704free_vmcs:
5f3fbc34 8705 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8706free_msrs:
fb3f0f51
RR		 8707 kfree(vmx->guest_msrs);
8708uninit_vcpu:
8709 kvm_vcpu_uninit(&vmx->vcpu);
8710free_vcpu:
cdbecfc3 8711 free_vpid(vmx);
a4770347 8712 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8713 return ERR_PTR(err);
6aa8b732
AK		 8714}
8715
002c7f7c
YS		 8716static void __init vmx_check_processor_compat(void *rtn)
8717{
8718 struct vmcs_config vmcs_conf;
8719
8720 *(int *)rtn = 0;
8721 if (setup_vmcs_config(&vmcs_conf) < 0)
8722 *(int *)rtn = -EIO;
8723 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8724 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8725 smp_processor_id());
8726 *(int *)rtn = -EIO;
8727 }
8728}
8729
67253af5
SY		 8730static int get_ept_level(void)
8731{
8732 return VMX_EPT_DEFAULT_GAW + 1;
8733}
8734
4b12f0de 8735static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8736{
b18d5431
XG		 8737 u8 cache;
8738 u64 ipat = 0;
4b12f0de 8739
522c68c4 8740 /* For VT-d and EPT combination
606decd6 8741 * 1. MMIO: always map as UC
522c68c4
SY		 8742 * 2. EPT with VT-d:
8743 * a. VT-d without snooping control feature: can't guarantee the
606decd6 8744 * result, try to trust guest.
522c68c4
SY		 8745 * b. VT-d with snooping control feature: snooping control feature of
8746 * VT-d engine can guarantee the cache correctness. Just set it
8747 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8748 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8749 * consistent with host MTRR
8750 */
606decd6
PB		 8751 if (is_mmio) {
8752 cache = MTRR_TYPE_UNCACHABLE;
8753 goto exit;
8754 }
8755
8756 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG		 8757 ipat = VMX_EPT_IPAT_BIT;
8758 cache = MTRR_TYPE_WRBACK;
8759 goto exit;
8760 }
8761
8762 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8763 ipat = VMX_EPT_IPAT_BIT;
0da029ed 8764 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG		 8765 cache = MTRR_TYPE_WRBACK;
8766 else
8767 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG		 8768 goto exit;
8769 }
8770
ff53604b 8771 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG		 8772
8773exit:
8774 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY		 8775}
8776
17cc3935 8777static int vmx_get_lpage_level(void)
344f414f 8778{
878403b7
SY		 8779 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8780 return PT_DIRECTORY_LEVEL;
8781 else
8782 /* For shadow and EPT supported 1GB page */
8783 return PT_PDPE_LEVEL;
344f414f
JR		 8784}
8785
feda805f
XG		 8786static void vmcs_set_secondary_exec_control(u32 new_ctl)
8787{
8788 /*
8789 * These bits in the secondary execution controls field
8790 * are dynamic, the others are mostly based on the hypervisor
8791 * architecture and the guest's CPUID. Do not touch the
8792 * dynamic bits.
8793 */
8794 u32 mask =
8795 SECONDARY_EXEC_SHADOW_VMCS |
8796 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8797 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8798
8799 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8800
8801 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8802 (new_ctl & ~mask) | (cur_ctl & mask));
8803}
8804
0e851880
SY		 8805static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8806{
4e47c7a6
SY		 8807 struct kvm_cpuid_entry2 *best;
8808 struct vcpu_vmx *vmx = to_vmx(vcpu);
feda805f 8809 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
4e47c7a6 8810
4e47c7a6 8811 if (vmx_rdtscp_supported()) {
1cea0ce6
XG		 8812 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8813 if (!rdtscp_enabled)
feda805f 8814 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
f36201e5 8815
8b97265a 8816 if (nested) {
1cea0ce6 8817 if (rdtscp_enabled)
8b97265a
PB		 8818 vmx->nested.nested_vmx_secondary_ctls_high |=
8819 SECONDARY_EXEC_RDTSCP;
8820 else
8821 vmx->nested.nested_vmx_secondary_ctls_high &=
8822 ~SECONDARY_EXEC_RDTSCP;
8823 }
4e47c7a6 8824 }
ad756a16 8825
ad756a16
MJ		 8826 /* Exposing INVPCID only when PCID is exposed */
8827 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8828 if (vmx_invpcid_supported() &&
29541bb8
XG		 8829 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8830 !guest_cpuid_has_pcid(vcpu))) {
feda805f 8831 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
29541bb8 8832
ad756a16 8833 if (best)
4f977045 8834 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8835 }
8b3e34e4 8836
feda805f
XG		 8837 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8838
8b3e34e4
XG		 8839 if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8840 if (guest_cpuid_has_pcommit(vcpu))
8841 vmx->nested.nested_vmx_secondary_ctls_high |=
8842 SECONDARY_EXEC_PCOMMIT;
8843 else
8844 vmx->nested.nested_vmx_secondary_ctls_high &=
8845 ~SECONDARY_EXEC_PCOMMIT;
8846 }
0e851880
SY		 8847}
8848
d4330ef2
JR		 8849static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8850{
7b8050f5
NHE		 8851 if (func == 1 && nested)
8852 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8853}
8854
25d92081
YZ		 8855static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8856 struct x86_exception *fault)
8857{
533558bc
JK		 8858 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8859 u32 exit_reason;
25d92081
YZ		 8860
8861 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8862 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8863 else
533558bc
JK		 8864 exit_reason = EXIT_REASON_EPT_VIOLATION;
8865 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8866 vmcs12->guest_physical_address = fault->address;
8867}
8868
155a97a3
NHE		 8869/* Callbacks for nested_ept_init_mmu_context: */
8870
8871static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8872{
8873 /* return the page table to be shadowed - in our case, EPT12 */
8874 return get_vmcs12(vcpu)->ept_pointer;
8875}
8876
8a3c1a33 8877static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8878{
ad896af0
PB		 8879 WARN_ON(mmu_is_nested(vcpu));
8880 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8881 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8882 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8883 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8884 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8885 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8886
8887 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8888}
8889
8890static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8891{
8892 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8893}
8894
19d5f10b
EK		 8895static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8896 u16 error_code)
8897{
8898 bool inequality, bit;
8899
8900 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8901 inequality =
8902 (error_code & vmcs12->page_fault_error_code_mask) !=
8903 vmcs12->page_fault_error_code_match;
8904 return inequality ^ bit;
8905}
8906
feaf0c7d
GN		 8907static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8908 struct x86_exception *fault)
8909{
8910 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8911
8912 WARN_ON(!is_guest_mode(vcpu));
8913
19d5f10b 8914 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8915 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8916 vmcs_read32(VM_EXIT_INTR_INFO),
8917 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8918 else
8919 kvm_inject_page_fault(vcpu, fault);
8920}
8921
a2bcba50
WL		 8922static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8923 struct vmcs12 *vmcs12)
8924{
8925 struct vcpu_vmx *vmx = to_vmx(vcpu);
9090422f 8926 int maxphyaddr = cpuid_maxphyaddr(vcpu);
a2bcba50
WL		 8927
8928 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9090422f
EK		 8929 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8930 vmcs12->apic_access_addr >> maxphyaddr)
a2bcba50
WL		 8931 return false;
8932
8933 /*
8934 * Translate L1 physical address to host physical
8935 * address for vmcs02. Keep the page pinned, so this
8936 * physical address remains valid. We keep a reference
8937 * to it so we can release it later.
8938 */
8939 if (vmx->nested.apic_access_page) /* shouldn't happen */
8940 nested_release_page(vmx->nested.apic_access_page);
8941 vmx->nested.apic_access_page =
8942 nested_get_page(vcpu, vmcs12->apic_access_addr);
8943 }
a7c0b07d
WL		 8944
8945 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9090422f
EK		 8946 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8947 vmcs12->virtual_apic_page_addr >> maxphyaddr)
a7c0b07d
WL		 8948 return false;
8949
8950 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8951 nested_release_page(vmx->nested.virtual_apic_page);
8952 vmx->nested.virtual_apic_page =
8953 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8954
8955 /*
8956 * Failing the vm entry is _not_ what the processor does
8957 * but it's basically the only possibility we have.
8958 * We could still enter the guest if CR8 load exits are
8959 * enabled, CR8 store exits are enabled, and virtualize APIC
8960 * access is disabled; in this case the processor would never
8961 * use the TPR shadow and we could simply clear the bit from
8962 * the execution control. But such a configuration is useless,
8963 * so let's keep the code simple.
8964 */
8965 if (!vmx->nested.virtual_apic_page)
8966 return false;
8967 }
8968
705699a1 8969 if (nested_cpu_has_posted_intr(vmcs12)) {
9090422f
EK		 8970 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8971 vmcs12->posted_intr_desc_addr >> maxphyaddr)
705699a1
WV		 8972 return false;
8973
8974 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8975 kunmap(vmx->nested.pi_desc_page);
8976 nested_release_page(vmx->nested.pi_desc_page);
8977 }
8978 vmx->nested.pi_desc_page =
8979 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8980 if (!vmx->nested.pi_desc_page)
8981 return false;
8982
8983 vmx->nested.pi_desc =
8984 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8985 if (!vmx->nested.pi_desc) {
8986 nested_release_page_clean(vmx->nested.pi_desc_page);
8987 return false;
8988 }
8989 vmx->nested.pi_desc =
8990 (struct pi_desc *)((void *)vmx->nested.pi_desc +
8991 (unsigned long)(vmcs12->posted_intr_desc_addr &
8992 (PAGE_SIZE - 1)));
8993 }
8994
a2bcba50
WL		 8995 return true;
8996}
8997
f4124500
JK		 8998static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8999{
9000 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9001 struct vcpu_vmx *vmx = to_vmx(vcpu);
9002
9003 if (vcpu->arch.virtual_tsc_khz == 0)
9004 return;
9005
9006 /* Make sure short timeouts reliably trigger an immediate vmexit.
9007 * hrtimer_start does not guarantee this. */
9008 if (preemption_timeout <= 1) {
9009 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9010 return;
9011 }
9012
9013 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9014 preemption_timeout *= 1000000;
9015 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9016 hrtimer_start(&vmx->nested.preemption_timer,
9017 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9018}
9019
3af18d9c
WV		 9020static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9021 struct vmcs12 *vmcs12)
9022{
9023 int maxphyaddr;
9024 u64 addr;
9025
9026 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9027 return 0;
9028
9029 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9030 WARN_ON(1);
9031 return -EINVAL;
9032 }
9033 maxphyaddr = cpuid_maxphyaddr(vcpu);
9034
9035 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9036 ((addr + PAGE_SIZE) >> maxphyaddr))
9037 return -EINVAL;
9038
9039 return 0;
9040}
9041
9042/*
9043 * Merge L0's and L1's MSR bitmap, return false to indicate that
9044 * we do not use the hardware.
9045 */
9046static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9047 struct vmcs12 *vmcs12)
9048{
82f0dd4b 9049 int msr;
f2b93280
WV		 9050 struct page *page;
9051 unsigned long *msr_bitmap;
9052
9053 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9054 return false;
9055
9056 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9057 if (!page) {
9058 WARN_ON(1);
9059 return false;
9060 }
9061 msr_bitmap = (unsigned long *)kmap(page);
9062 if (!msr_bitmap) {
9063 nested_release_page_clean(page);
9064 WARN_ON(1);
9065 return false;
9066 }
9067
9068 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 9069 if (nested_cpu_has_apic_reg_virt(vmcs12))
9070 for (msr = 0x800; msr <= 0x8ff; msr++)
9071 nested_vmx_disable_intercept_for_msr(
9072 msr_bitmap,
9073 vmx_msr_bitmap_nested,
9074 msr, MSR_TYPE_R);
f2b93280
WV		 9075 /* TPR is allowed */
9076 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9077 vmx_msr_bitmap_nested,
9078 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9079 MSR_TYPE_R | MSR_TYPE_W);
608406e2
WV		 9080 if (nested_cpu_has_vid(vmcs12)) {
9081 /* EOI and self-IPI are allowed */
9082 nested_vmx_disable_intercept_for_msr(
9083 msr_bitmap,
9084 vmx_msr_bitmap_nested,
9085 APIC_BASE_MSR + (APIC_EOI >> 4),
9086 MSR_TYPE_W);
9087 nested_vmx_disable_intercept_for_msr(
9088 msr_bitmap,
9089 vmx_msr_bitmap_nested,
9090 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9091 MSR_TYPE_W);
9092 }
82f0dd4b
WV		 9093 } else {
9094 /*
9095 * Enable reading intercept of all the x2apic
9096 * MSRs. We should not rely on vmcs12 to do any
9097 * optimizations here, it may have been modified
9098 * by L1.
9099 */
9100 for (msr = 0x800; msr <= 0x8ff; msr++)
9101 __vmx_enable_intercept_for_msr(
9102 vmx_msr_bitmap_nested,
9103 msr,
9104 MSR_TYPE_R);
9105
f2b93280
WV		 9106 __vmx_enable_intercept_for_msr(
9107 vmx_msr_bitmap_nested,
9108 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
82f0dd4b 9109 MSR_TYPE_W);
608406e2
WV		 9110 __vmx_enable_intercept_for_msr(
9111 vmx_msr_bitmap_nested,
9112 APIC_BASE_MSR + (APIC_EOI >> 4),
9113 MSR_TYPE_W);
9114 __vmx_enable_intercept_for_msr(
9115 vmx_msr_bitmap_nested,
9116 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9117 MSR_TYPE_W);
82f0dd4b 9118 }
f2b93280
WV		 9119 kunmap(page);
9120 nested_release_page_clean(page);
9121
9122 return true;
9123}
9124
9125static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9126 struct vmcs12 *vmcs12)
9127{
82f0dd4b 9128 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 9129 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV		 9130 !nested_cpu_has_vid(vmcs12) &&
9131 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV		 9132 return 0;
9133
9134 /*
9135 * If virtualize x2apic mode is enabled,
9136 * virtualize apic access must be disabled.
9137 */
82f0dd4b
WV		 9138 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9139 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 9140 return -EINVAL;
9141
608406e2
WV		 9142 /*
9143 * If virtual interrupt delivery is enabled,
9144 * we must exit on external interrupts.
9145 */
9146 if (nested_cpu_has_vid(vmcs12) &&
9147 !nested_exit_on_intr(vcpu))
9148 return -EINVAL;
9149
705699a1
WV		 9150 /*
9151 * bits 15:8 should be zero in posted_intr_nv,
9152 * the descriptor address has been already checked
9153 * in nested_get_vmcs12_pages.
9154 */
9155 if (nested_cpu_has_posted_intr(vmcs12) &&
9156 (!nested_cpu_has_vid(vmcs12) ||
9157 !nested_exit_intr_ack_set(vcpu) ||
9158 vmcs12->posted_intr_nv & 0xff00))
9159 return -EINVAL;
9160
f2b93280
WV		 9161 /* tpr shadow is needed by all apicv features. */
9162 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9163 return -EINVAL;
9164
9165 return 0;
3af18d9c
WV		 9166}
9167
e9ac033e
EK		 9168static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9169 unsigned long count_field,
92d71bc6 9170 unsigned long addr_field)
ff651cb6 9171{
92d71bc6 9172 int maxphyaddr;
e9ac033e
EK		 9173 u64 count, addr;
9174
9175 if (vmcs12_read_any(vcpu, count_field, &count) ||
9176 vmcs12_read_any(vcpu, addr_field, &addr)) {
9177 WARN_ON(1);
9178 return -EINVAL;
9179 }
9180 if (count == 0)
9181 return 0;
92d71bc6 9182 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK		 9183 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9184 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9185 pr_warn_ratelimited(
9186 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9187 addr_field, maxphyaddr, count, addr);
9188 return -EINVAL;
9189 }
9190 return 0;
9191}
9192
9193static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9194 struct vmcs12 *vmcs12)
9195{
e9ac033e
EK		 9196 if (vmcs12->vm_exit_msr_load_count == 0 &&
9197 vmcs12->vm_exit_msr_store_count == 0 &&
9198 vmcs12->vm_entry_msr_load_count == 0)
9199 return 0; /* Fast path */
e9ac033e 9200 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9201 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9202 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9203 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9204 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9205 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK		 9206 return -EINVAL;
9207 return 0;
9208}
9209
9210static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9211 struct vmx_msr_entry *e)
9212{
9213 /* x2APIC MSR accesses are not allowed */
8a9781f7 9214 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK		 9215 return -EINVAL;
9216 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9217 e->index == MSR_IA32_UCODE_REV)
9218 return -EINVAL;
9219 if (e->reserved != 0)
ff651cb6
WV		 9220 return -EINVAL;
9221 return 0;
9222}
9223
e9ac033e
EK		 9224static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9225 struct vmx_msr_entry *e)
ff651cb6
WV		 9226{
9227 if (e->index == MSR_FS_BASE ||
9228 e->index == MSR_GS_BASE ||
e9ac033e
EK		 9229 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9230 nested_vmx_msr_check_common(vcpu, e))
9231 return -EINVAL;
9232 return 0;
9233}
9234
9235static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9236 struct vmx_msr_entry *e)
9237{
9238 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9239 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 9240 return -EINVAL;
9241 return 0;
9242}
9243
9244/*
9245 * Load guest's/host's msr at nested entry/exit.
9246 * return 0 for success, entry index for failure.
9247 */
9248static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9249{
9250 u32 i;
9251 struct vmx_msr_entry e;
9252 struct msr_data msr;
9253
9254 msr.host_initiated = false;
9255 for (i = 0; i < count; i++) {
54bf36aa
PB		 9256 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9257 &e, sizeof(e))) {
e9ac033e
EK		 9258 pr_warn_ratelimited(
9259 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9260 __func__, i, gpa + i * sizeof(e));
ff651cb6 9261 goto fail;
e9ac033e
EK		 9262 }
9263 if (nested_vmx_load_msr_check(vcpu, &e)) {
9264 pr_warn_ratelimited(
9265 "%s check failed (%u, 0x%x, 0x%x)\n",
9266 __func__, i, e.index, e.reserved);
9267 goto fail;
9268 }
ff651cb6
WV		 9269 msr.index = e.index;
9270 msr.data = e.value;
e9ac033e
EK		 9271 if (kvm_set_msr(vcpu, &msr)) {
9272 pr_warn_ratelimited(
9273 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9274 __func__, i, e.index, e.value);
ff651cb6 9275 goto fail;
e9ac033e 9276 }
ff651cb6
WV		 9277 }
9278 return 0;
9279fail:
9280 return i + 1;
9281}
9282
9283static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9284{
9285 u32 i;
9286 struct vmx_msr_entry e;
9287
9288 for (i = 0; i < count; i++) {
609e36d3 9289 struct msr_data msr_info;
54bf36aa
PB		 9290 if (kvm_vcpu_read_guest(vcpu,
9291 gpa + i * sizeof(e),
9292 &e, 2 * sizeof(u32))) {
e9ac033e
EK		 9293 pr_warn_ratelimited(
9294 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9295 __func__, i, gpa + i * sizeof(e));
ff651cb6 9296 return -EINVAL;
e9ac033e
EK		 9297 }
9298 if (nested_vmx_store_msr_check(vcpu, &e)) {
9299 pr_warn_ratelimited(
9300 "%s check failed (%u, 0x%x, 0x%x)\n",
9301 __func__, i, e.index, e.reserved);
ff651cb6 9302 return -EINVAL;
e9ac033e 9303 }
609e36d3
PB		 9304 msr_info.host_initiated = false;
9305 msr_info.index = e.index;
9306 if (kvm_get_msr(vcpu, &msr_info)) {
e9ac033e
EK		 9307 pr_warn_ratelimited(
9308 "%s cannot read MSR (%u, 0x%x)\n",
9309 __func__, i, e.index);
9310 return -EINVAL;
9311 }
54bf36aa
PB		 9312 if (kvm_vcpu_write_guest(vcpu,
9313 gpa + i * sizeof(e) +
9314 offsetof(struct vmx_msr_entry, value),
9315 &msr_info.data, sizeof(msr_info.data))) {
e9ac033e
EK		 9316 pr_warn_ratelimited(
9317 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9318 __func__, i, e.index, msr_info.data);
e9ac033e
EK		 9319 return -EINVAL;
9320 }
ff651cb6
WV		 9321 }
9322 return 0;
9323}
9324
fe3ef05c
NHE		 9325/*
9326 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9327 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9328 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 9329 * guest in a way that will both be appropriate to L1's requests, and our
9330 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9331 * function also has additional necessary side-effects, like setting various
9332 * vcpu->arch fields.
9333 */
9334static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9335{
9336 struct vcpu_vmx *vmx = to_vmx(vcpu);
9337 u32 exec_control;
9338
9339 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9340 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9341 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9342 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9343 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9344 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9345 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9346 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9347 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9348 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9349 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9350 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9351 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9352 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9353 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9354 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9355 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9356 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9357 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9358 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9359 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9360 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9361 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9362 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9363 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9364 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9365 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9366 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9367 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9368 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9369 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9370 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9371 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9372 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9373 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9374 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9375
2996fca0
JK		 9376 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9377 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9378 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9379 } else {
9380 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9381 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9382 }
fe3ef05c
NHE		 9383 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9384 vmcs12->vm_entry_intr_info_field);
9385 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9386 vmcs12->vm_entry_exception_error_code);
9387 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9388 vmcs12->vm_entry_instruction_len);
9389 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9390 vmcs12->guest_interruptibility_info);
fe3ef05c 9391 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9392 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 9393 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9394 vmcs12->guest_pending_dbg_exceptions);
9395 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9396 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9397
81dc01f7
WL		 9398 if (nested_cpu_has_xsaves(vmcs12))
9399 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 9400 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9401
f4124500
JK		 9402 exec_control = vmcs12->pin_based_vm_exec_control;
9403 exec_control |= vmcs_config.pin_based_exec_ctrl;
705699a1
WV		 9404 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9405
9406 if (nested_cpu_has_posted_intr(vmcs12)) {
9407 /*
9408 * Note that we use L0's vector here and in
9409 * vmx_deliver_nested_posted_interrupt.
9410 */
9411 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9412 vmx->nested.pi_pending = false;
9413 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9414 vmcs_write64(POSTED_INTR_DESC_ADDR,
9415 page_to_phys(vmx->nested.pi_desc_page) +
9416 (unsigned long)(vmcs12->posted_intr_desc_addr &
9417 (PAGE_SIZE - 1)));
9418 } else
9419 exec_control &= ~PIN_BASED_POSTED_INTR;
9420
f4124500 9421 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 9422
f4124500
JK		 9423 vmx->nested.preemption_timer_expired = false;
9424 if (nested_cpu_has_preemption_timer(vmcs12))
9425 vmx_start_preemption_timer(vcpu);
0238ea91 9426
fe3ef05c
NHE		 9427 /*
9428 * Whether page-faults are trapped is determined by a combination of
9429 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9430 * If enable_ept, L0 doesn't care about page faults and we should
9431 * set all of these to L1's desires. However, if !enable_ept, L0 does
9432 * care about (at least some) page faults, and because it is not easy
9433 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9434 * to exit on each and every L2 page fault. This is done by setting
9435 * MASK=MATCH=0 and (see below) EB.PF=1.
9436 * Note that below we don't need special code to set EB.PF beyond the
9437 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9438 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9439 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9440 *
9441 * A problem with this approach (when !enable_ept) is that L1 may be
9442 * injected with more page faults than it asked for. This could have
9443 * caused problems, but in practice existing hypervisors don't care.
9444 * To fix this, we will need to emulate the PFEC checking (on the L1
9445 * page tables), using walk_addr(), when injecting PFs to L1.
9446 */
9447 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9448 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9449 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9450 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9451
9452 if (cpu_has_secondary_exec_ctrls()) {
f4124500 9453 exec_control = vmx_secondary_exec_control(vmx);
e2821620 9454
fe3ef05c 9455 /* Take the following fields only from vmcs12 */
696dfd95 9456 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 9457 SECONDARY_EXEC_RDTSCP |
696dfd95 9458 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8b3e34e4
XG		 9459 SECONDARY_EXEC_APIC_REGISTER_VIRT |
9460 SECONDARY_EXEC_PCOMMIT);
fe3ef05c
NHE		 9461 if (nested_cpu_has(vmcs12,
9462 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9463 exec_control |= vmcs12->secondary_vm_exec_control;
9464
9465 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 9466 /*
9467 * If translation failed, no matter: This feature asks
9468 * to exit when accessing the given address, and if it
9469 * can never be accessed, this feature won't do
9470 * anything anyway.
9471 */
9472 if (!vmx->nested.apic_access_page)
9473 exec_control &=
9474 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9475 else
9476 vmcs_write64(APIC_ACCESS_ADDR,
9477 page_to_phys(vmx->nested.apic_access_page));
f2b93280 9478 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
35754c98 9479 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
ca3f257a
JK		 9480 exec_control |=
9481 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 9482 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 9483 }
9484
608406e2
WV		 9485 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9486 vmcs_write64(EOI_EXIT_BITMAP0,
9487 vmcs12->eoi_exit_bitmap0);
9488 vmcs_write64(EOI_EXIT_BITMAP1,
9489 vmcs12->eoi_exit_bitmap1);
9490 vmcs_write64(EOI_EXIT_BITMAP2,
9491 vmcs12->eoi_exit_bitmap2);
9492 vmcs_write64(EOI_EXIT_BITMAP3,
9493 vmcs12->eoi_exit_bitmap3);
9494 vmcs_write16(GUEST_INTR_STATUS,
9495 vmcs12->guest_intr_status);
9496 }
9497
fe3ef05c
NHE		 9498 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9499 }
9500
9501
9502 /*
9503 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9504 * Some constant fields are set here by vmx_set_constant_host_state().
9505 * Other fields are different per CPU, and will be set later when
9506 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9507 */
a547c6db 9508 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 9509
9510 /*
9511 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9512 * entry, but only if the current (host) sp changed from the value
9513 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9514 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9515 * here we just force the write to happen on entry.
9516 */
9517 vmx->host_rsp = 0;
9518
9519 exec_control = vmx_exec_control(vmx); /* L0's desires */
9520 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9521 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9522 exec_control &= ~CPU_BASED_TPR_SHADOW;
9523 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 9524
9525 if (exec_control & CPU_BASED_TPR_SHADOW) {
9526 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9527 page_to_phys(vmx->nested.virtual_apic_page));
9528 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9529 }
9530
3af18d9c 9531 if (cpu_has_vmx_msr_bitmap() &&
670125bd
WV		 9532 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9533 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9534 /* MSR_BITMAP will be set by following vmx_set_efer. */
3af18d9c
WV		 9535 } else
9536 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9537
fe3ef05c 9538 /*
3af18d9c 9539 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 9540 * Rather, exit every time.
9541 */
fe3ef05c
NHE		 9542 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9543 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9544
9545 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9546
9547 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9548 * bitwise-or of what L1 wants to trap for L2, and what we want to
9549 * trap. Note that CR0.TS also needs updating - we do this later.
9550 */
9551 update_exception_bitmap(vcpu);
9552 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9553 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9554
8049d651
NHE		 9555 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9556 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9557 * bits are further modified by vmx_set_efer() below.
9558 */
f4124500 9559 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9560
9561 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9562 * emulated by vmx_set_efer(), below.
9563 */
2961e876 9564 vm_entry_controls_init(vmx,
8049d651
NHE		 9565 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9566 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9567 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9568
44811c02 9569 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9570 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9571 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9572 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9573 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9574
9575
9576 set_cr4_guest_host_mask(vmx);
9577
36be0b9d
PB		 9578 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9579 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9580
27fc51b2
NHE		 9581 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9582 vmcs_write64(TSC_OFFSET,
9583 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9584 else
9585 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9586
9587 if (enable_vpid) {
9588 /*
9589 * Trivially support vpid by letting L2s share their parent
9590 * L1's vpid. TODO: move to a more elaborate solution, giving
9591 * each L2 its own vpid and exposing the vpid feature to L1.
9592 */
9593 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9594 vmx_flush_tlb(vcpu);
9595 }
9596
155a97a3
NHE		 9597 if (nested_cpu_has_ept(vmcs12)) {
9598 kvm_mmu_unload(vcpu);
9599 nested_ept_init_mmu_context(vcpu);
9600 }
9601
fe3ef05c
NHE		 9602 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9603 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9604 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9605 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9606 else
9607 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9608 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9609 vmx_set_efer(vcpu, vcpu->arch.efer);
9610
9611 /*
9612 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9613 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9614 * The CR0_READ_SHADOW is what L2 should have expected to read given
9615 * the specifications by L1; It's not enough to take
9616 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9617 * have more bits than L1 expected.
9618 */
9619 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9620 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9621
9622 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9623 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9624
9625 /* shadow page tables on either EPT or shadow page tables */
9626 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9627 kvm_mmu_reset_context(vcpu);
9628
feaf0c7d
GN		 9629 if (!enable_ept)
9630 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9631
3633cfc3
NHE		 9632 /*
9633 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9634 */
9635 if (enable_ept) {
9636 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9637 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9638 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9639 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9640 }
9641
fe3ef05c
NHE		 9642 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9643 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9644}
9645
cd232ad0
NHE		 9646/*
9647 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9648 * for running an L2 nested guest.
9649 */
9650static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9651{
9652 struct vmcs12 *vmcs12;
9653 struct vcpu_vmx *vmx = to_vmx(vcpu);
9654 int cpu;
9655 struct loaded_vmcs *vmcs02;
384bb783 9656 bool ia32e;
ff651cb6 9657 u32 msr_entry_idx;
cd232ad0
NHE		 9658
9659 if (!nested_vmx_check_permission(vcpu) ||
9660 !nested_vmx_check_vmcs12(vcpu))
9661 return 1;
9662
9663 skip_emulated_instruction(vcpu);
9664 vmcs12 = get_vmcs12(vcpu);
9665
012f83cb
AG		 9666 if (enable_shadow_vmcs)
9667 copy_shadow_to_vmcs12(vmx);
9668
7c177938
NHE		 9669 /*
9670 * The nested entry process starts with enforcing various prerequisites
9671 * on vmcs12 as required by the Intel SDM, and act appropriately when
9672 * they fail: As the SDM explains, some conditions should cause the
9673 * instruction to fail, while others will cause the instruction to seem
9674 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9675 * To speed up the normal (success) code path, we should avoid checking
9676 * for misconfigurations which will anyway be caught by the processor
9677 * when using the merged vmcs02.
9678 */
9679 if (vmcs12->launch_state == launch) {
9680 nested_vmx_failValid(vcpu,
9681 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9682 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9683 return 1;
9684 }
9685
6dfacadd
JK		 9686 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9687 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9688 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9689 return 1;
9690 }
9691
3af18d9c 9692 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9693 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9694 return 1;
9695 }
9696
3af18d9c 9697 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9698 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9699 return 1;
9700 }
9701
f2b93280
WV		 9702 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9703 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9704 return 1;
9705 }
9706
e9ac033e
EK		 9707 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9708 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9709 return 1;
9710 }
9711
7c177938 9712 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9713 vmx->nested.nested_vmx_true_procbased_ctls_low,
9714 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9715 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9716 vmx->nested.nested_vmx_secondary_ctls_low,
9717 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9718 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9719 vmx->nested.nested_vmx_pinbased_ctls_low,
9720 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9721 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9722 vmx->nested.nested_vmx_true_exit_ctls_low,
9723 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9724 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9725 vmx->nested.nested_vmx_true_entry_ctls_low,
9726 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9727 {
9728 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9729 return 1;
9730 }
9731
9732 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9733 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9734 nested_vmx_failValid(vcpu,
9735 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9736 return 1;
9737 }
9738
b9c237bb 9739 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9740 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9741 nested_vmx_entry_failure(vcpu, vmcs12,
9742 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9743 return 1;
9744 }
9745 if (vmcs12->vmcs_link_pointer != -1ull) {
9746 nested_vmx_entry_failure(vcpu, vmcs12,
9747 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9748 return 1;
9749 }
9750
384bb783 9751 /*
cb0c8cda 9752 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9753 * are performed on the field for the IA32_EFER MSR:
9754 * - Bits reserved in the IA32_EFER MSR must be 0.
9755 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9756 * the IA-32e mode guest VM-exit control. It must also be identical
9757 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9758 * CR0.PG) is 1.
9759 */
9760 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9761 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9762 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9763 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9764 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9765 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9766 nested_vmx_entry_failure(vcpu, vmcs12,
9767 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9768 return 1;
9769 }
9770 }
9771
9772 /*
9773 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9774 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9775 * the values of the LMA and LME bits in the field must each be that of
9776 * the host address-space size VM-exit control.
9777 */
9778 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9779 ia32e = (vmcs12->vm_exit_controls &
9780 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9781 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9782 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9783 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9784 nested_vmx_entry_failure(vcpu, vmcs12,
9785 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9786 return 1;
9787 }
9788 }
9789
7c177938
NHE		 9790 /*
9791 * We're finally done with prerequisite checking, and can start with
9792 * the nested entry.
9793 */
9794
cd232ad0
NHE		 9795 vmcs02 = nested_get_current_vmcs02(vmx);
9796 if (!vmcs02)
9797 return -ENOMEM;
9798
9799 enter_guest_mode(vcpu);
9800
9801 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9802
2996fca0
JK		 9803 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9804 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9805
cd232ad0
NHE		 9806 cpu = get_cpu();
9807 vmx->loaded_vmcs = vmcs02;
9808 vmx_vcpu_put(vcpu);
9809 vmx_vcpu_load(vcpu, cpu);
9810 vcpu->cpu = cpu;
9811 put_cpu();
9812
36c3cc42
JK		 9813 vmx_segment_cache_clear(vmx);
9814
cd232ad0
NHE		 9815 prepare_vmcs02(vcpu, vmcs12);
9816
ff651cb6
WV		 9817 msr_entry_idx = nested_vmx_load_msr(vcpu,
9818 vmcs12->vm_entry_msr_load_addr,
9819 vmcs12->vm_entry_msr_load_count);
9820 if (msr_entry_idx) {
9821 leave_guest_mode(vcpu);
9822 vmx_load_vmcs01(vcpu);
9823 nested_vmx_entry_failure(vcpu, vmcs12,
9824 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9825 return 1;
9826 }
9827
9828 vmcs12->launch_state = 1;
9829
6dfacadd 9830 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 9831 return kvm_vcpu_halt(vcpu);
6dfacadd 9832
7af40ad3
JK		 9833 vmx->nested.nested_run_pending = 1;
9834
cd232ad0
NHE		 9835 /*
9836 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9837 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9838 * returned as far as L1 is concerned. It will only return (and set
9839 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9840 */
9841 return 1;
9842}
9843
4704d0be
NHE		 9844/*
9845 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9846 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9847 * This function returns the new value we should put in vmcs12.guest_cr0.
9848 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9849 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9850 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9851 * didn't trap the bit, because if L1 did, so would L0).
9852 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9853 * been modified by L2, and L1 knows it. So just leave the old value of
9854 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9855 * isn't relevant, because if L0 traps this bit it can set it to anything.
9856 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9857 * changed these bits, and therefore they need to be updated, but L0
9858 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9859 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9860 */
9861static inline unsigned long
9862vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9863{
9864 return
9865 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9866 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9867 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9868 vcpu->arch.cr0_guest_owned_bits));
9869}
9870
9871static inline unsigned long
9872vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9873{
9874 return
9875 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9876 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9877 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9878 vcpu->arch.cr4_guest_owned_bits));
9879}
9880
5f3d5799
JK		 9881static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9882 struct vmcs12 *vmcs12)
9883{
9884 u32 idt_vectoring;
9885 unsigned int nr;
9886
851eb667 9887 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9888 nr = vcpu->arch.exception.nr;
9889 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9890
9891 if (kvm_exception_is_soft(nr)) {
9892 vmcs12->vm_exit_instruction_len =
9893 vcpu->arch.event_exit_inst_len;
9894 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9895 } else
9896 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9897
9898 if (vcpu->arch.exception.has_error_code) {
9899 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9900 vmcs12->idt_vectoring_error_code =
9901 vcpu->arch.exception.error_code;
9902 }
9903
9904 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9905 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9906 vmcs12->idt_vectoring_info_field =
9907 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9908 } else if (vcpu->arch.interrupt.pending) {
9909 nr = vcpu->arch.interrupt.nr;
9910 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9911
9912 if (vcpu->arch.interrupt.soft) {
9913 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9914 vmcs12->vm_entry_instruction_len =
9915 vcpu->arch.event_exit_inst_len;
9916 } else
9917 idt_vectoring |= INTR_TYPE_EXT_INTR;
9918
9919 vmcs12->idt_vectoring_info_field = idt_vectoring;
9920 }
9921}
9922
b6b8a145
JK		 9923static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9924{
9925 struct vcpu_vmx *vmx = to_vmx(vcpu);
9926
f4124500
JK		 9927 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9928 vmx->nested.preemption_timer_expired) {
9929 if (vmx->nested.nested_run_pending)
9930 return -EBUSY;
9931 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9932 return 0;
9933 }
9934
b6b8a145 9935 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9936 if (vmx->nested.nested_run_pending ||
9937 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9938 return -EBUSY;
9939 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9940 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9941 INTR_INFO_VALID_MASK, 0);
9942 /*
9943 * The NMI-triggered VM exit counts as injection:
9944 * clear this one and block further NMIs.
9945 */
9946 vcpu->arch.nmi_pending = 0;
9947 vmx_set_nmi_mask(vcpu, true);
9948 return 0;
9949 }
9950
9951 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9952 nested_exit_on_intr(vcpu)) {
9953 if (vmx->nested.nested_run_pending)
9954 return -EBUSY;
9955 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 9956 return 0;
b6b8a145
JK		 9957 }
9958
705699a1 9959 return vmx_complete_nested_posted_interrupt(vcpu);
b6b8a145
JK		 9960}
9961
f4124500
JK		 9962static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9963{
9964 ktime_t remaining =
9965 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9966 u64 value;
9967
9968 if (ktime_to_ns(remaining) <= 0)
9969 return 0;
9970
9971 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9972 do_div(value, 1000000);
9973 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9974}
9975
4704d0be
NHE		 9976/*
9977 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9978 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9979 * and this function updates it to reflect the changes to the guest state while
9980 * L2 was running (and perhaps made some exits which were handled directly by L0
9981 * without going back to L1), and to reflect the exit reason.
9982 * Note that we do not have to copy here all VMCS fields, just those that
9983 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9984 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9985 * which already writes to vmcs12 directly.
9986 */
533558bc
JK		 9987static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9988 u32 exit_reason, u32 exit_intr_info,
9989 unsigned long exit_qualification)
4704d0be
NHE		 9990{
9991 /* update guest state fields: */
9992 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9993 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9994
4704d0be
NHE		 9995 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9996 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9997 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9998
9999 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10000 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10001 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10002 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10003 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10004 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10005 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10006 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10007 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10008 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10009 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10010 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10011 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10012 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10013 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10014 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10015 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10016 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10017 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10018 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10019 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10020 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10021 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10022 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10023 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10024 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10025 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10026 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10027 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10028 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10029 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10030 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10031 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10032 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10033 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10034 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10035
4704d0be
NHE		 10036 vmcs12->guest_interruptibility_info =
10037 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10038 vmcs12->guest_pending_dbg_exceptions =
10039 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 10040 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10041 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10042 else
10043 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 10044
f4124500
JK		 10045 if (nested_cpu_has_preemption_timer(vmcs12)) {
10046 if (vmcs12->vm_exit_controls &
10047 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10048 vmcs12->vmx_preemption_timer_value =
10049 vmx_get_preemption_timer_value(vcpu);
10050 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10051 }
7854cbca 10052
3633cfc3
NHE		 10053 /*
10054 * In some cases (usually, nested EPT), L2 is allowed to change its
10055 * own CR3 without exiting. If it has changed it, we must keep it.
10056 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10057 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10058 *
10059 * Additionally, restore L2's PDPTR to vmcs12.
10060 */
10061 if (enable_ept) {
10062 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10063 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10064 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10065 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10066 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10067 }
10068
608406e2
WV		 10069 if (nested_cpu_has_vid(vmcs12))
10070 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10071
c18911a2
JK		 10072 vmcs12->vm_entry_controls =
10073 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 10074 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 10075
2996fca0
JK		 10076 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10077 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10078 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10079 }
10080
4704d0be
NHE		 10081 /* TODO: These cannot have changed unless we have MSR bitmaps and
10082 * the relevant bit asks not to trap the change */
b8c07d55 10083 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 10084 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 10085 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10086 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 10087 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10088 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10089 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 10090 if (vmx_mpx_supported())
10091 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 10092 if (nested_cpu_has_xsaves(vmcs12))
10093 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 10094
10095 /* update exit information fields: */
10096
533558bc
JK		 10097 vmcs12->vm_exit_reason = exit_reason;
10098 vmcs12->exit_qualification = exit_qualification;
4704d0be 10099
533558bc 10100 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 10101 if ((vmcs12->vm_exit_intr_info &
10102 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10103 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10104 vmcs12->vm_exit_intr_error_code =
10105 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 10106 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 10107 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10108 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10109
5f3d5799
JK		 10110 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10111 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10112 * instead of reading the real value. */
4704d0be 10113 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 10114
10115 /*
10116 * Transfer the event that L0 or L1 may wanted to inject into
10117 * L2 to IDT_VECTORING_INFO_FIELD.
10118 */
10119 vmcs12_save_pending_event(vcpu, vmcs12);
10120 }
10121
10122 /*
10123 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10124 * preserved above and would only end up incorrectly in L1.
10125 */
10126 vcpu->arch.nmi_injected = false;
10127 kvm_clear_exception_queue(vcpu);
10128 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 10129}
10130
10131/*
10132 * A part of what we need to when the nested L2 guest exits and we want to
10133 * run its L1 parent, is to reset L1's guest state to the host state specified
10134 * in vmcs12.
10135 * This function is to be called not only on normal nested exit, but also on
10136 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10137 * Failures During or After Loading Guest State").
10138 * This function should be called when the active VMCS is L1's (vmcs01).
10139 */
733568f9
JK		 10140static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10141 struct vmcs12 *vmcs12)
4704d0be 10142{
21feb4eb
ACL		 10143 struct kvm_segment seg;
10144
4704d0be
NHE		 10145 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10146 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10147 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 10148 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10149 else
10150 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10151 vmx_set_efer(vcpu, vcpu->arch.efer);
10152
10153 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10154 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10155 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 10156 /*
10157 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10158 * actually changed, because it depends on the current state of
10159 * fpu_active (which may have changed).
10160 * Note that vmx_set_cr0 refers to efer set above.
10161 */
9e3e4dbf 10162 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 10163 /*
10164 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10165 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10166 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10167 */
10168 update_exception_bitmap(vcpu);
10169 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10170 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10171
10172 /*
10173 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10174 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10175 */
10176 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10177 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10178
29bf08f1 10179 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10180
4704d0be
NHE		 10181 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10182 kvm_mmu_reset_context(vcpu);
10183
feaf0c7d
GN		 10184 if (!enable_ept)
10185 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10186
4704d0be
NHE		 10187 if (enable_vpid) {
10188 /*
10189 * Trivially support vpid by letting L2s share their parent
10190 * L1's vpid. TODO: move to a more elaborate solution, giving
10191 * each L2 its own vpid and exposing the vpid feature to L1.
10192 */
10193 vmx_flush_tlb(vcpu);
10194 }
10195
10196
10197 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10198 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10199 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10200 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10201 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10202
36be0b9d
PB		 10203 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10204 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10205 vmcs_write64(GUEST_BNDCFGS, 0);
10206
44811c02 10207 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10208 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 10209 vcpu->arch.pat = vmcs12->host_ia32_pat;
10210 }
4704d0be
NHE		 10211 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10212 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10213 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10214
21feb4eb
ACL		 10215 /* Set L1 segment info according to Intel SDM
10216 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10217 seg = (struct kvm_segment) {
10218 .base = 0,
10219 .limit = 0xFFFFFFFF,
10220 .selector = vmcs12->host_cs_selector,
10221 .type = 11,
10222 .present = 1,
10223 .s = 1,
10224 .g = 1
10225 };
10226 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10227 seg.l = 1;
10228 else
10229 seg.db = 1;
10230 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10231 seg = (struct kvm_segment) {
10232 .base = 0,
10233 .limit = 0xFFFFFFFF,
10234 .type = 3,
10235 .present = 1,
10236 .s = 1,
10237 .db = 1,
10238 .g = 1
10239 };
10240 seg.selector = vmcs12->host_ds_selector;
10241 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10242 seg.selector = vmcs12->host_es_selector;
10243 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10244 seg.selector = vmcs12->host_ss_selector;
10245 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10246 seg.selector = vmcs12->host_fs_selector;
10247 seg.base = vmcs12->host_fs_base;
10248 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10249 seg.selector = vmcs12->host_gs_selector;
10250 seg.base = vmcs12->host_gs_base;
10251 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10252 seg = (struct kvm_segment) {
205befd9 10253 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 10254 .limit = 0x67,
10255 .selector = vmcs12->host_tr_selector,
10256 .type = 11,
10257 .present = 1
10258 };
10259 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10260
503cd0c5
JK		 10261 kvm_set_dr(vcpu, 7, 0x400);
10262 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 10263
3af18d9c
WV		 10264 if (cpu_has_vmx_msr_bitmap())
10265 vmx_set_msr_bitmap(vcpu);
10266
ff651cb6
WV		 10267 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10268 vmcs12->vm_exit_msr_load_count))
10269 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 10270}
10271
10272/*
10273 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10274 * and modify vmcs12 to make it see what it would expect to see there if
10275 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10276 */
533558bc
JK		 10277static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10278 u32 exit_intr_info,
10279 unsigned long exit_qualification)
4704d0be
NHE		 10280{
10281 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 10282 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10283
5f3d5799
JK		 10284 /* trying to cancel vmlaunch/vmresume is a bug */
10285 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10286
4704d0be 10287 leave_guest_mode(vcpu);
533558bc
JK		 10288 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10289 exit_qualification);
4704d0be 10290
ff651cb6
WV		 10291 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10292 vmcs12->vm_exit_msr_store_count))
10293 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10294
f3380ca5
WL		 10295 vmx_load_vmcs01(vcpu);
10296
77b0f5d6
BD		 10297 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10298 && nested_exit_intr_ack_set(vcpu)) {
10299 int irq = kvm_cpu_get_interrupt(vcpu);
10300 WARN_ON(irq < 0);
10301 vmcs12->vm_exit_intr_info = irq |
10302 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10303 }
10304
542060ea
JK		 10305 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10306 vmcs12->exit_qualification,
10307 vmcs12->idt_vectoring_info_field,
10308 vmcs12->vm_exit_intr_info,
10309 vmcs12->vm_exit_intr_error_code,
10310 KVM_ISA_VMX);
4704d0be 10311
2961e876
GN		 10312 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10313 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 10314 vmx_segment_cache_clear(vmx);
10315
4704d0be
NHE		 10316 /* if no vmcs02 cache requested, remove the one we used */
10317 if (VMCS02_POOL_SIZE == 0)
10318 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10319
10320 load_vmcs12_host_state(vcpu, vmcs12);
10321
27fc51b2 10322 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 10323 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10324
10325 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10326 vmx->host_rsp = 0;
10327
10328 /* Unpin physical memory we referred to in vmcs02 */
10329 if (vmx->nested.apic_access_page) {
10330 nested_release_page(vmx->nested.apic_access_page);
48d89b92 10331 vmx->nested.apic_access_page = NULL;
4704d0be 10332 }
a7c0b07d
WL		 10333 if (vmx->nested.virtual_apic_page) {
10334 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 10335 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 10336 }
705699a1
WV		 10337 if (vmx->nested.pi_desc_page) {
10338 kunmap(vmx->nested.pi_desc_page);
10339 nested_release_page(vmx->nested.pi_desc_page);
10340 vmx->nested.pi_desc_page = NULL;
10341 vmx->nested.pi_desc = NULL;
10342 }
4704d0be 10343
38b99173
TC		 10344 /*
10345 * We are now running in L2, mmu_notifier will force to reload the
10346 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10347 */
10348 kvm_vcpu_reload_apic_access_page(vcpu);
10349
4704d0be
NHE		 10350 /*
10351 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10352 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10353 * success or failure flag accordingly.
10354 */
10355 if (unlikely(vmx->fail)) {
10356 vmx->fail = 0;
10357 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10358 } else
10359 nested_vmx_succeed(vcpu);
012f83cb
AG		 10360 if (enable_shadow_vmcs)
10361 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 10362
10363 /* in case we halted in L2 */
10364 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 10365}
10366
42124925
JK		 10367/*
10368 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10369 */
10370static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10371{
10372 if (is_guest_mode(vcpu))
533558bc 10373 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 10374 free_nested(to_vmx(vcpu));
10375}
10376
7c177938
NHE		 10377/*
10378 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10379 * 23.7 "VM-entry failures during or after loading guest state" (this also
10380 * lists the acceptable exit-reason and exit-qualification parameters).
10381 * It should only be called before L2 actually succeeded to run, and when
10382 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10383 */
10384static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10385 struct vmcs12 *vmcs12,
10386 u32 reason, unsigned long qualification)
10387{
10388 load_vmcs12_host_state(vcpu, vmcs12);
10389 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10390 vmcs12->exit_qualification = qualification;
10391 nested_vmx_succeed(vcpu);
012f83cb
AG		 10392 if (enable_shadow_vmcs)
10393 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 10394}
10395
8a76d7f2
JR		 10396static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10397 struct x86_instruction_info *info,
10398 enum x86_intercept_stage stage)
10399{
10400 return X86EMUL_CONTINUE;
10401}
10402
48d89b92 10403static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 10404{
b4a2d31d
RK		 10405 if (ple_gap)
10406 shrink_ple_window(vcpu);
ae97a3b8
RK		 10407}
10408
843e4330
KH		 10409static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10410 struct kvm_memory_slot *slot)
10411{
10412 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10413 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10414}
10415
10416static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10417 struct kvm_memory_slot *slot)
10418{
10419 kvm_mmu_slot_set_dirty(kvm, slot);
10420}
10421
10422static void vmx_flush_log_dirty(struct kvm *kvm)
10423{
10424 kvm_flush_pml_buffers(kvm);
10425}
10426
10427static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10428 struct kvm_memory_slot *memslot,
10429 gfn_t offset, unsigned long mask)
10430{
10431 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10432}
10433
efc64404
FW		 10434/*
10435 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10436 *
10437 * @kvm: kvm
10438 * @host_irq: host irq of the interrupt
10439 * @guest_irq: gsi of the interrupt
10440 * @set: set or unset PI
10441 * returns 0 on success, < 0 on failure
10442 */
10443static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10444 uint32_t guest_irq, bool set)
10445{
10446 struct kvm_kernel_irq_routing_entry *e;
10447 struct kvm_irq_routing_table *irq_rt;
10448 struct kvm_lapic_irq irq;
10449 struct kvm_vcpu *vcpu;
10450 struct vcpu_data vcpu_info;
10451 int idx, ret = -EINVAL;
10452
10453 if (!kvm_arch_has_assigned_device(kvm) ||
10454 !irq_remapping_cap(IRQ_POSTING_CAP))
10455 return 0;
10456
10457 idx = srcu_read_lock(&kvm->irq_srcu);
10458 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10459 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10460
10461 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10462 if (e->type != KVM_IRQ_ROUTING_MSI)
10463 continue;
10464 /*
10465 * VT-d PI cannot support posting multicast/broadcast
10466 * interrupts to a vCPU, we still use interrupt remapping
10467 * for these kind of interrupts.
10468 *
10469 * For lowest-priority interrupts, we only support
10470 * those with single CPU as the destination, e.g. user
10471 * configures the interrupts via /proc/irq or uses
10472 * irqbalance to make the interrupts single-CPU.
10473 *
10474 * We will support full lowest-priority interrupt later.
10475 */
10476
10477 kvm_set_msi_irq(e, &irq);
10478 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10479 continue;
10480
10481 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10482 vcpu_info.vector = irq.vector;
10483
10484 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10485 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10486
10487 if (set)
10488 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10489 else {
10490 /* suppress notification event before unposting */
10491 pi_set_sn(vcpu_to_pi_desc(vcpu));
10492 ret = irq_set_vcpu_affinity(host_irq, NULL);
10493 pi_clear_sn(vcpu_to_pi_desc(vcpu));
10494 }
10495
10496 if (ret < 0) {
10497 printk(KERN_INFO "%s: failed to update PI IRTE\n",
10498 __func__);
10499 goto out;
10500 }
10501 }
10502
10503 ret = 0;
10504out:
10505 srcu_read_unlock(&kvm->irq_srcu, idx);
10506 return ret;
10507}
10508
cbdd1bea 10509static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 10510 .cpu_has_kvm_support = cpu_has_kvm_support,
10511 .disabled_by_bios = vmx_disabled_by_bios,
10512 .hardware_setup = hardware_setup,
10513 .hardware_unsetup = hardware_unsetup,
002c7f7c 10514 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 10515 .hardware_enable = hardware_enable,
10516 .hardware_disable = hardware_disable,
04547156 10517 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 10518 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK		 10519
10520 .vcpu_create = vmx_create_vcpu,
10521 .vcpu_free = vmx_free_vcpu,
04d2cc77 10522 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 10523
04d2cc77 10524 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 10525 .vcpu_load = vmx_vcpu_load,
10526 .vcpu_put = vmx_vcpu_put,
10527
c8639010 10528 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 10529 .get_msr = vmx_get_msr,
10530 .set_msr = vmx_set_msr,
10531 .get_segment_base = vmx_get_segment_base,
10532 .get_segment = vmx_get_segment,
10533 .set_segment = vmx_set_segment,
2e4d2653 10534 .get_cpl = vmx_get_cpl,
6aa8b732 10535 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 10536 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 10537 .decache_cr3 = vmx_decache_cr3,
25c4c276 10538 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 10539 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 10540 .set_cr3 = vmx_set_cr3,
10541 .set_cr4 = vmx_set_cr4,
6aa8b732 10542 .set_efer = vmx_set_efer,
6aa8b732
AK		 10543 .get_idt = vmx_get_idt,
10544 .set_idt = vmx_set_idt,
10545 .get_gdt = vmx_get_gdt,
10546 .set_gdt = vmx_set_gdt,
73aaf249
JK		 10547 .get_dr6 = vmx_get_dr6,
10548 .set_dr6 = vmx_set_dr6,
020df079 10549 .set_dr7 = vmx_set_dr7,
81908bf4 10550 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 10551 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 10552 .get_rflags = vmx_get_rflags,
10553 .set_rflags = vmx_set_rflags,
0fdd74f7 10554 .fpu_activate = vmx_fpu_activate,
02daab21 10555 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 10556
10557 .tlb_flush = vmx_flush_tlb,
6aa8b732 10558
6aa8b732 10559 .run = vmx_vcpu_run,
6062d012 10560 .handle_exit = vmx_handle_exit,
6aa8b732 10561 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 10562 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10563 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 10564 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 10565 .set_irq = vmx_inject_irq,
95ba8273 10566 .set_nmi = vmx_inject_nmi,
298101da 10567 .queue_exception = vmx_queue_exception,
b463a6f7 10568 .cancel_injection = vmx_cancel_injection,
78646121 10569 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 10570 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 10571 .get_nmi_mask = vmx_get_nmi_mask,
10572 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 10573 .enable_nmi_window = enable_nmi_window,
10574 .enable_irq_window = enable_irq_window,
10575 .update_cr8_intercept = update_cr8_intercept,
8d14695f 10576 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 10577 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d50ab6c1 10578 .cpu_uses_apicv = vmx_cpu_uses_apicv,
c7c9c56c
YZ		 10579 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10580 .hwapic_irr_update = vmx_hwapic_irr_update,
10581 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 10582 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10583 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 10584
cbc94022 10585 .set_tss_addr = vmx_set_tss_addr,
67253af5 10586 .get_tdp_level = get_ept_level,
4b12f0de 10587 .get_mt_mask = vmx_get_mt_mask,
229456fc 10588
586f9607 10589 .get_exit_info = vmx_get_exit_info,
586f9607 10590
17cc3935 10591 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 10592
10593 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 10594
10595 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 10596 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 10597
10598 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 10599
10600 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 10601
4051b188 10602 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 10603 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 10604 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 10605 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 10606 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 10607 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 10608
10609 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 10610
10611 .check_intercept = vmx_check_intercept,
a547c6db 10612 .handle_external_intr = vmx_handle_external_intr,
da8999d3 10613 .mpx_supported = vmx_mpx_supported,
55412b2e 10614 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 10615
10616 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 10617
10618 .sched_in = vmx_sched_in,
843e4330
KH		 10619
10620 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10621 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10622 .flush_log_dirty = vmx_flush_log_dirty,
10623 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
25462f7f
WH		 10624
10625 .pmu_ops = &intel_pmu_ops,
efc64404
FW		 10626
10627 .update_pi_irte = vmx_update_pi_irte,
6aa8b732
AK		 10628};
10629
10630static int __init vmx_init(void)
10631{
34a1cd60
TC		 10632 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10633 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 10634 if (r)
34a1cd60 10635 return r;
25c5f225 10636
2965faa5 10637#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 10638 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10639 crash_vmclear_local_loaded_vmcss);
10640#endif
10641
fdef3ad1 10642 return 0;
6aa8b732
AK		 10643}
10644
10645static void __exit vmx_exit(void)
10646{
2965faa5 10647#ifdef CONFIG_KEXEC_CORE
3b63a43f 10648 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10649 synchronize_rcu();
10650#endif
10651
cb498ea2 10652 kvm_exit();
6aa8b732
AK		 10653}
10654
10655module_init(vmx_init)
10656module_exit(vmx_exit)
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