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vfio: Register/unregister irq_bypass_producer
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
af658dca 31#include <linux/trace_events.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
952f07ec 43#include <asm/fpu/internal.h>
d7cd9796 44#include <asm/perf_event.h>
81908bf4 45#include <asm/debugreg.h>
8f536b76 46#include <asm/kexec.h>
dab2087d 47#include <asm/apic.h>
6aa8b732 48
229456fc 49#include "trace.h"
25462f7f 50#include "pmu.h"
229456fc 51
4ecac3fd 52#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 53#define __ex_clear(x, reg) \
54 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 55
6aa8b732
AK		 56MODULE_AUTHOR("Qumranet");
57MODULE_LICENSE("GPL");
58
e9bda3b3
JT		 59static const struct x86_cpu_id vmx_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_VMX),
61 {}
62};
63MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
64
476bc001 65static bool __read_mostly enable_vpid = 1;
736caefe 66module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 67
476bc001 68static bool __read_mostly flexpriority_enabled = 1;
736caefe 69module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 70
476bc001 71static bool __read_mostly enable_ept = 1;
736caefe 72module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 73
476bc001 74static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 75module_param_named(unrestricted_guest,
76 enable_unrestricted_guest, bool, S_IRUGO);
77
83c3a331
XH		 78static bool __read_mostly enable_ept_ad_bits = 1;
79module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
80
a27685c3 81static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 82module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 83
476bc001 84static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 85module_param(vmm_exclusive, bool, S_IRUGO);
86
476bc001 87static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 88module_param(fasteoi, bool, S_IRUGO);
89
5a71785d 90static bool __read_mostly enable_apicv = 1;
01e439be 91module_param(enable_apicv, bool, S_IRUGO);
83d4c286 92
abc4fc58
AG		 93static bool __read_mostly enable_shadow_vmcs = 1;
94module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 95/*
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
99 */
476bc001 100static bool __read_mostly nested = 0;
801d3424
NHE		 101module_param(nested, bool, S_IRUGO);
102
20300099
WL		 103static u64 __read_mostly host_xss;
104
843e4330
KH		 105static bool __read_mostly enable_pml = 1;
106module_param_named(pml, enable_pml, bool, S_IRUGO);
107
5037878e
GN		 108#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 110#define KVM_VM_CR0_ALWAYS_ON \
111 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 112#define KVM_CR4_GUEST_OWNED_BITS \
113 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 114 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 115
cdc0e244
AK		 116#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
118
78ac8b47
AK		 119#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
120
f4124500
JK		 121#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
122
4b8d54f9
ZE		 123/*
124 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125 * ple_gap: upper bound on the amount of time between two successive
126 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 127 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 128 * ple_window: upper bound on the amount of time a guest is allowed to execute
129 * in a PAUSE loop. Tests indicate that most spinlocks are held for
130 * less than 2^12 cycles
131 * Time is measured based on a counter that runs at the same rate as the TSC,
132 * refer SDM volume 3b section 21.6.13 & 22.1.3.
133 */
b4a2d31d
RK		 134#define KVM_VMX_DEFAULT_PLE_GAP 128
135#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
136#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
137#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
139 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
140
4b8d54f9
ZE		 141static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
142module_param(ple_gap, int, S_IRUGO);
143
144static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
145module_param(ple_window, int, S_IRUGO);
146
b4a2d31d
RK		 147/* Default doubles per-vcpu window every exit. */
148static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
149module_param(ple_window_grow, int, S_IRUGO);
150
151/* Default resets per-vcpu window every exit to ple_window. */
152static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
153module_param(ple_window_shrink, int, S_IRUGO);
154
155/* Default is to compute the maximum so we can never overflow. */
156static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
158module_param(ple_window_max, int, S_IRUGO);
159
83287ea4
AK		 160extern const ulong vmx_return;
161
8bf00a52 162#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 163#define VMCS02_POOL_SIZE 1
61d2ef2c 164
a2fa3e9f
GH		 165struct vmcs {
166 u32 revision_id;
167 u32 abort;
168 char data[0];
169};
170
d462b819
NHE		 171/*
172 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174 * loaded on this CPU (so we can clear them if the CPU goes down).
175 */
176struct loaded_vmcs {
177 struct vmcs *vmcs;
178 int cpu;
179 int launched;
180 struct list_head loaded_vmcss_on_cpu_link;
181};
182
26bb0981
AK		 183struct shared_msr_entry {
184 unsigned index;
185 u64 data;
d5696725 186 u64 mask;
26bb0981
AK		 187};
188
a9d30f33
NHE		 189/*
190 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195 * More than one of these structures may exist, if L1 runs multiple L2 guests.
196 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197 * underlying hardware which will be used to run L2.
198 * This structure is packed to ensure that its layout is identical across
199 * machines (necessary for live migration).
200 * If there are changes in this struct, VMCS12_REVISION must be changed.
201 */
22bd0358 202typedef u64 natural_width;
a9d30f33
NHE		 203struct __packed vmcs12 {
204 /* According to the Intel spec, a VMCS region must start with the
205 * following two fields. Then follow implementation-specific data.
206 */
207 u32 revision_id;
208 u32 abort;
22bd0358 209
27d6c865
NHE		 210 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211 u32 padding[7]; /* room for future expansion */
212
22bd0358
NHE		 213 u64 io_bitmap_a;
214 u64 io_bitmap_b;
215 u64 msr_bitmap;
216 u64 vm_exit_msr_store_addr;
217 u64 vm_exit_msr_load_addr;
218 u64 vm_entry_msr_load_addr;
219 u64 tsc_offset;
220 u64 virtual_apic_page_addr;
221 u64 apic_access_addr;
705699a1 222 u64 posted_intr_desc_addr;
22bd0358 223 u64 ept_pointer;
608406e2
WV		 224 u64 eoi_exit_bitmap0;
225 u64 eoi_exit_bitmap1;
226 u64 eoi_exit_bitmap2;
227 u64 eoi_exit_bitmap3;
81dc01f7 228 u64 xss_exit_bitmap;
22bd0358
NHE		 229 u64 guest_physical_address;
230 u64 vmcs_link_pointer;
231 u64 guest_ia32_debugctl;
232 u64 guest_ia32_pat;
233 u64 guest_ia32_efer;
234 u64 guest_ia32_perf_global_ctrl;
235 u64 guest_pdptr0;
236 u64 guest_pdptr1;
237 u64 guest_pdptr2;
238 u64 guest_pdptr3;
36be0b9d 239 u64 guest_bndcfgs;
22bd0358
NHE		 240 u64 host_ia32_pat;
241 u64 host_ia32_efer;
242 u64 host_ia32_perf_global_ctrl;
243 u64 padding64[8]; /* room for future expansion */
244 /*
245 * To allow migration of L1 (complete with its L2 guests) between
246 * machines of different natural widths (32 or 64 bit), we cannot have
247 * unsigned long fields with no explict size. We use u64 (aliased
248 * natural_width) instead. Luckily, x86 is little-endian.
249 */
250 natural_width cr0_guest_host_mask;
251 natural_width cr4_guest_host_mask;
252 natural_width cr0_read_shadow;
253 natural_width cr4_read_shadow;
254 natural_width cr3_target_value0;
255 natural_width cr3_target_value1;
256 natural_width cr3_target_value2;
257 natural_width cr3_target_value3;
258 natural_width exit_qualification;
259 natural_width guest_linear_address;
260 natural_width guest_cr0;
261 natural_width guest_cr3;
262 natural_width guest_cr4;
263 natural_width guest_es_base;
264 natural_width guest_cs_base;
265 natural_width guest_ss_base;
266 natural_width guest_ds_base;
267 natural_width guest_fs_base;
268 natural_width guest_gs_base;
269 natural_width guest_ldtr_base;
270 natural_width guest_tr_base;
271 natural_width guest_gdtr_base;
272 natural_width guest_idtr_base;
273 natural_width guest_dr7;
274 natural_width guest_rsp;
275 natural_width guest_rip;
276 natural_width guest_rflags;
277 natural_width guest_pending_dbg_exceptions;
278 natural_width guest_sysenter_esp;
279 natural_width guest_sysenter_eip;
280 natural_width host_cr0;
281 natural_width host_cr3;
282 natural_width host_cr4;
283 natural_width host_fs_base;
284 natural_width host_gs_base;
285 natural_width host_tr_base;
286 natural_width host_gdtr_base;
287 natural_width host_idtr_base;
288 natural_width host_ia32_sysenter_esp;
289 natural_width host_ia32_sysenter_eip;
290 natural_width host_rsp;
291 natural_width host_rip;
292 natural_width paddingl[8]; /* room for future expansion */
293 u32 pin_based_vm_exec_control;
294 u32 cpu_based_vm_exec_control;
295 u32 exception_bitmap;
296 u32 page_fault_error_code_mask;
297 u32 page_fault_error_code_match;
298 u32 cr3_target_count;
299 u32 vm_exit_controls;
300 u32 vm_exit_msr_store_count;
301 u32 vm_exit_msr_load_count;
302 u32 vm_entry_controls;
303 u32 vm_entry_msr_load_count;
304 u32 vm_entry_intr_info_field;
305 u32 vm_entry_exception_error_code;
306 u32 vm_entry_instruction_len;
307 u32 tpr_threshold;
308 u32 secondary_vm_exec_control;
309 u32 vm_instruction_error;
310 u32 vm_exit_reason;
311 u32 vm_exit_intr_info;
312 u32 vm_exit_intr_error_code;
313 u32 idt_vectoring_info_field;
314 u32 idt_vectoring_error_code;
315 u32 vm_exit_instruction_len;
316 u32 vmx_instruction_info;
317 u32 guest_es_limit;
318 u32 guest_cs_limit;
319 u32 guest_ss_limit;
320 u32 guest_ds_limit;
321 u32 guest_fs_limit;
322 u32 guest_gs_limit;
323 u32 guest_ldtr_limit;
324 u32 guest_tr_limit;
325 u32 guest_gdtr_limit;
326 u32 guest_idtr_limit;
327 u32 guest_es_ar_bytes;
328 u32 guest_cs_ar_bytes;
329 u32 guest_ss_ar_bytes;
330 u32 guest_ds_ar_bytes;
331 u32 guest_fs_ar_bytes;
332 u32 guest_gs_ar_bytes;
333 u32 guest_ldtr_ar_bytes;
334 u32 guest_tr_ar_bytes;
335 u32 guest_interruptibility_info;
336 u32 guest_activity_state;
337 u32 guest_sysenter_cs;
338 u32 host_ia32_sysenter_cs;
0238ea91
JK		 339 u32 vmx_preemption_timer_value;
340 u32 padding32[7]; /* room for future expansion */
22bd0358 341 u16 virtual_processor_id;
705699a1 342 u16 posted_intr_nv;
22bd0358
NHE		 343 u16 guest_es_selector;
344 u16 guest_cs_selector;
345 u16 guest_ss_selector;
346 u16 guest_ds_selector;
347 u16 guest_fs_selector;
348 u16 guest_gs_selector;
349 u16 guest_ldtr_selector;
350 u16 guest_tr_selector;
608406e2 351 u16 guest_intr_status;
22bd0358
NHE		 352 u16 host_es_selector;
353 u16 host_cs_selector;
354 u16 host_ss_selector;
355 u16 host_ds_selector;
356 u16 host_fs_selector;
357 u16 host_gs_selector;
358 u16 host_tr_selector;
a9d30f33
NHE		 359};
360
361/*
362 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
365 */
366#define VMCS12_REVISION 0x11e57ed0
367
368/*
369 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371 * current implementation, 4K are reserved to avoid future complications.
372 */
373#define VMCS12_SIZE 0x1000
374
ff2f6fe9
NHE		 375/* Used to remember the last vmcs02 used for some recently used vmcs12s */
376struct vmcs02_list {
377 struct list_head list;
378 gpa_t vmptr;
379 struct loaded_vmcs vmcs02;
380};
381
ec378aee
NHE		 382/*
383 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
385 */
386struct nested_vmx {
387 /* Has the level1 guest done vmxon? */
388 bool vmxon;
3573e22c 389 gpa_t vmxon_ptr;
a9d30f33
NHE		 390
391 /* The guest-physical address of the current VMCS L1 keeps for L2 */
392 gpa_t current_vmptr;
393 /* The host-usable pointer to the above */
394 struct page *current_vmcs12_page;
395 struct vmcs12 *current_vmcs12;
8de48833 396 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 397 /*
398 * Indicates if the shadow vmcs must be updated with the
399 * data hold by vmcs12
400 */
401 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 402
403 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404 struct list_head vmcs02_pool;
405 int vmcs02_num;
fe3ef05c 406 u64 vmcs01_tsc_offset;
644d711a
NHE		 407 /* L2 must run next, and mustn't decide to exit to L1. */
408 bool nested_run_pending;
fe3ef05c
NHE		 409 /*
410 * Guest pages referred to in vmcs02 with host-physical pointers, so
411 * we must keep them pinned while L2 runs.
412 */
413 struct page *apic_access_page;
a7c0b07d 414 struct page *virtual_apic_page;
705699a1
WV		 415 struct page *pi_desc_page;
416 struct pi_desc *pi_desc;
417 bool pi_pending;
418 u16 posted_intr_nv;
b3897a49 419 u64 msr_ia32_feature_control;
f4124500
JK		 420
421 struct hrtimer preemption_timer;
422 bool preemption_timer_expired;
2996fca0
JK		 423
424 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
425 u64 vmcs01_debugctl;
b9c237bb
WV		 426
427 u32 nested_vmx_procbased_ctls_low;
428 u32 nested_vmx_procbased_ctls_high;
429 u32 nested_vmx_true_procbased_ctls_low;
430 u32 nested_vmx_secondary_ctls_low;
431 u32 nested_vmx_secondary_ctls_high;
432 u32 nested_vmx_pinbased_ctls_low;
433 u32 nested_vmx_pinbased_ctls_high;
434 u32 nested_vmx_exit_ctls_low;
435 u32 nested_vmx_exit_ctls_high;
436 u32 nested_vmx_true_exit_ctls_low;
437 u32 nested_vmx_entry_ctls_low;
438 u32 nested_vmx_entry_ctls_high;
439 u32 nested_vmx_true_entry_ctls_low;
440 u32 nested_vmx_misc_low;
441 u32 nested_vmx_misc_high;
442 u32 nested_vmx_ept_caps;
ec378aee
NHE		 443};
444
01e439be 445#define POSTED_INTR_ON 0
ebbfc765
FW		 446#define POSTED_INTR_SN 1
447
01e439be
YZ		 448/* Posted-Interrupt Descriptor */
449struct pi_desc {
450 u32 pir[8]; /* Posted interrupt requested */
6ef1522f
FW		 451 union {
452 struct {
453 /* bit 256 - Outstanding Notification */
454 u16 on : 1,
455 /* bit 257 - Suppress Notification */
456 sn : 1,
457 /* bit 271:258 - Reserved */
458 rsvd_1 : 14;
459 /* bit 279:272 - Notification Vector */
460 u8 nv;
461 /* bit 287:280 - Reserved */
462 u8 rsvd_2;
463 /* bit 319:288 - Notification Destination */
464 u32 ndst;
465 };
466 u64 control;
467 };
468 u32 rsvd[6];
01e439be
YZ		 469} __aligned(64);
470
a20ed54d
YZ		 471static bool pi_test_and_set_on(struct pi_desc *pi_desc)
472{
473 return test_and_set_bit(POSTED_INTR_ON,
474 (unsigned long *)&pi_desc->control);
475}
476
477static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
478{
479 return test_and_clear_bit(POSTED_INTR_ON,
480 (unsigned long *)&pi_desc->control);
481}
482
483static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
484{
485 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
486}
487
ebbfc765
FW		 488static inline void pi_clear_sn(struct pi_desc *pi_desc)
489{
490 return clear_bit(POSTED_INTR_SN,
491 (unsigned long *)&pi_desc->control);
492}
493
494static inline void pi_set_sn(struct pi_desc *pi_desc)
495{
496 return set_bit(POSTED_INTR_SN,
497 (unsigned long *)&pi_desc->control);
498}
499
500static inline int pi_test_on(struct pi_desc *pi_desc)
501{
502 return test_bit(POSTED_INTR_ON,
503 (unsigned long *)&pi_desc->control);
504}
505
506static inline int pi_test_sn(struct pi_desc *pi_desc)
507{
508 return test_bit(POSTED_INTR_SN,
509 (unsigned long *)&pi_desc->control);
510}
511
a2fa3e9f 512struct vcpu_vmx {
fb3f0f51 513 struct kvm_vcpu vcpu;
313dbd49 514 unsigned long host_rsp;
29bd8a78 515 u8 fail;
9d58b931 516 bool nmi_known_unmasked;
51aa01d1 517 u32 exit_intr_info;
1155f76a 518 u32 idt_vectoring_info;
6de12732 519 ulong rflags;
26bb0981 520 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 521 int nmsrs;
522 int save_nmsrs;
a547c6db 523 unsigned long host_idt_base;
a2fa3e9f 524#ifdef CONFIG_X86_64
44ea2b17
AK		 525 u64 msr_host_kernel_gs_base;
526 u64 msr_guest_kernel_gs_base;
a2fa3e9f 527#endif
2961e876
GN		 528 u32 vm_entry_controls_shadow;
529 u32 vm_exit_controls_shadow;
d462b819
NHE		 530 /*
531 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
532 * non-nested (L1) guest, it always points to vmcs01. For a nested
533 * guest (L2), it points to a different VMCS.
534 */
535 struct loaded_vmcs vmcs01;
536 struct loaded_vmcs *loaded_vmcs;
537 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 538 struct msr_autoload {
539 unsigned nr;
540 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
541 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
542 } msr_autoload;
a2fa3e9f
GH		 543 struct {
544 int loaded;
545 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 546#ifdef CONFIG_X86_64
547 u16 ds_sel, es_sel;
548#endif
152d3f2f
LV		 549 int gs_ldt_reload_needed;
550 int fs_reload_needed;
da8999d3 551 u64 msr_host_bndcfgs;
d974baa3 552 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 553 } host_state;
9c8cba37 554 struct {
7ffd92c5 555 int vm86_active;
78ac8b47 556 ulong save_rflags;
f5f7b2fe
AK		 557 struct kvm_segment segs[8];
558 } rmode;
559 struct {
560 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 561 struct kvm_save_segment {
562 u16 selector;
563 unsigned long base;
564 u32 limit;
565 u32 ar;
f5f7b2fe 566 } seg[8];
2fb92db1 567 } segment_cache;
2384d2b3 568 int vpid;
04fa4d32 569 bool emulation_required;
3b86cd99
JK		 570
571 /* Support for vnmi-less CPUs */
572 int soft_vnmi_blocked;
573 ktime_t entry_time;
574 s64 vnmi_blocked_time;
a0861c02 575 u32 exit_reason;
4e47c7a6 576
01e439be
YZ		 577 /* Posted interrupt descriptor */
578 struct pi_desc pi_desc;
579
ec378aee
NHE		 580 /* Support for a guest hypervisor (nested VMX) */
581 struct nested_vmx nested;
a7653ecd
RK		 582
583 /* Dynamic PLE window. */
584 int ple_window;
585 bool ple_window_dirty;
843e4330
KH		 586
587 /* Support for PML */
588#define PML_ENTITY_NUM 512
589 struct page *pml_pg;
a2fa3e9f
GH		 590};
591
2fb92db1
AK		 592enum segment_cache_field {
593 SEG_FIELD_SEL = 0,
594 SEG_FIELD_BASE = 1,
595 SEG_FIELD_LIMIT = 2,
596 SEG_FIELD_AR = 3,
597
598 SEG_FIELD_NR = 4
599};
600
a2fa3e9f
GH		 601static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
602{
fb3f0f51 603 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 604}
605
22bd0358
NHE		 606#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
607#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
608#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
609 [number##_HIGH] = VMCS12_OFFSET(name)+4
610
4607c2d7 611
fe2b201b 612static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 613 /*
614 * We do NOT shadow fields that are modified when L0
615 * traps and emulates any vmx instruction (e.g. VMPTRLD,
616 * VMXON...) executed by L1.
617 * For example, VM_INSTRUCTION_ERROR is read
618 * by L1 if a vmx instruction fails (part of the error path).
619 * Note the code assumes this logic. If for some reason
620 * we start shadowing these fields then we need to
621 * force a shadow sync when L0 emulates vmx instructions
622 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
623 * by nested_vmx_failValid)
624 */
625 VM_EXIT_REASON,
626 VM_EXIT_INTR_INFO,
627 VM_EXIT_INSTRUCTION_LEN,
628 IDT_VECTORING_INFO_FIELD,
629 IDT_VECTORING_ERROR_CODE,
630 VM_EXIT_INTR_ERROR_CODE,
631 EXIT_QUALIFICATION,
632 GUEST_LINEAR_ADDRESS,
633 GUEST_PHYSICAL_ADDRESS
634};
fe2b201b 635static int max_shadow_read_only_fields =
4607c2d7
AG		 636 ARRAY_SIZE(shadow_read_only_fields);
637
fe2b201b 638static unsigned long shadow_read_write_fields[] = {
a7c0b07d 639 TPR_THRESHOLD,
4607c2d7
AG		 640 GUEST_RIP,
641 GUEST_RSP,
642 GUEST_CR0,
643 GUEST_CR3,
644 GUEST_CR4,
645 GUEST_INTERRUPTIBILITY_INFO,
646 GUEST_RFLAGS,
647 GUEST_CS_SELECTOR,
648 GUEST_CS_AR_BYTES,
649 GUEST_CS_LIMIT,
650 GUEST_CS_BASE,
651 GUEST_ES_BASE,
36be0b9d 652 GUEST_BNDCFGS,
4607c2d7
AG		 653 CR0_GUEST_HOST_MASK,
654 CR0_READ_SHADOW,
655 CR4_READ_SHADOW,
656 TSC_OFFSET,
657 EXCEPTION_BITMAP,
658 CPU_BASED_VM_EXEC_CONTROL,
659 VM_ENTRY_EXCEPTION_ERROR_CODE,
660 VM_ENTRY_INTR_INFO_FIELD,
661 VM_ENTRY_INSTRUCTION_LEN,
662 VM_ENTRY_EXCEPTION_ERROR_CODE,
663 HOST_FS_BASE,
664 HOST_GS_BASE,
665 HOST_FS_SELECTOR,
666 HOST_GS_SELECTOR
667};
fe2b201b 668static int max_shadow_read_write_fields =
4607c2d7
AG		 669 ARRAY_SIZE(shadow_read_write_fields);
670
772e0318 671static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 672 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 673 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE		 674 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
675 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
676 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
677 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
678 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
679 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
680 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
681 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 682 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 683 FIELD(HOST_ES_SELECTOR, host_es_selector),
684 FIELD(HOST_CS_SELECTOR, host_cs_selector),
685 FIELD(HOST_SS_SELECTOR, host_ss_selector),
686 FIELD(HOST_DS_SELECTOR, host_ds_selector),
687 FIELD(HOST_FS_SELECTOR, host_fs_selector),
688 FIELD(HOST_GS_SELECTOR, host_gs_selector),
689 FIELD(HOST_TR_SELECTOR, host_tr_selector),
690 FIELD64(IO_BITMAP_A, io_bitmap_a),
691 FIELD64(IO_BITMAP_B, io_bitmap_b),
692 FIELD64(MSR_BITMAP, msr_bitmap),
693 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
694 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
695 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
696 FIELD64(TSC_OFFSET, tsc_offset),
697 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
698 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 699 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 700 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 701 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
702 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
703 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
704 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 705 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 706 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
707 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
708 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
709 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
710 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
711 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
712 FIELD64(GUEST_PDPTR0, guest_pdptr0),
713 FIELD64(GUEST_PDPTR1, guest_pdptr1),
714 FIELD64(GUEST_PDPTR2, guest_pdptr2),
715 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 716 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 717 FIELD64(HOST_IA32_PAT, host_ia32_pat),
718 FIELD64(HOST_IA32_EFER, host_ia32_efer),
719 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
720 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
721 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
722 FIELD(EXCEPTION_BITMAP, exception_bitmap),
723 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
724 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
725 FIELD(CR3_TARGET_COUNT, cr3_target_count),
726 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
727 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
728 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
729 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
730 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
731 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
732 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
733 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
734 FIELD(TPR_THRESHOLD, tpr_threshold),
735 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
736 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
737 FIELD(VM_EXIT_REASON, vm_exit_reason),
738 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
739 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
740 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
741 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
742 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
743 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
744 FIELD(GUEST_ES_LIMIT, guest_es_limit),
745 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
746 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
747 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
748 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
749 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
750 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
751 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
752 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
753 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
754 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
755 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
756 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
757 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
758 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
759 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
760 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
761 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
762 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
763 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
764 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
765 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 766 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 767 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
768 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
769 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
770 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
771 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
772 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
773 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
774 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
775 FIELD(EXIT_QUALIFICATION, exit_qualification),
776 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
777 FIELD(GUEST_CR0, guest_cr0),
778 FIELD(GUEST_CR3, guest_cr3),
779 FIELD(GUEST_CR4, guest_cr4),
780 FIELD(GUEST_ES_BASE, guest_es_base),
781 FIELD(GUEST_CS_BASE, guest_cs_base),
782 FIELD(GUEST_SS_BASE, guest_ss_base),
783 FIELD(GUEST_DS_BASE, guest_ds_base),
784 FIELD(GUEST_FS_BASE, guest_fs_base),
785 FIELD(GUEST_GS_BASE, guest_gs_base),
786 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
787 FIELD(GUEST_TR_BASE, guest_tr_base),
788 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
789 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
790 FIELD(GUEST_DR7, guest_dr7),
791 FIELD(GUEST_RSP, guest_rsp),
792 FIELD(GUEST_RIP, guest_rip),
793 FIELD(GUEST_RFLAGS, guest_rflags),
794 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
795 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
796 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
797 FIELD(HOST_CR0, host_cr0),
798 FIELD(HOST_CR3, host_cr3),
799 FIELD(HOST_CR4, host_cr4),
800 FIELD(HOST_FS_BASE, host_fs_base),
801 FIELD(HOST_GS_BASE, host_gs_base),
802 FIELD(HOST_TR_BASE, host_tr_base),
803 FIELD(HOST_GDTR_BASE, host_gdtr_base),
804 FIELD(HOST_IDTR_BASE, host_idtr_base),
805 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
806 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
807 FIELD(HOST_RSP, host_rsp),
808 FIELD(HOST_RIP, host_rip),
809};
22bd0358
NHE		 810
811static inline short vmcs_field_to_offset(unsigned long field)
812{
a2ae9df7
PB		 813 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
814
815 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
816 vmcs_field_to_offset_table[field] == 0)
817 return -ENOENT;
818
22bd0358
NHE		 819 return vmcs_field_to_offset_table[field];
820}
821
a9d30f33
NHE		 822static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
823{
824 return to_vmx(vcpu)->nested.current_vmcs12;
825}
826
827static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
828{
54bf36aa 829 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 830 if (is_error_page(page))
a9d30f33 831 return NULL;
32cad84f 832
a9d30f33
NHE		 833 return page;
834}
835
836static void nested_release_page(struct page *page)
837{
838 kvm_release_page_dirty(page);
839}
840
841static void nested_release_page_clean(struct page *page)
842{
843 kvm_release_page_clean(page);
844}
845
bfd0a56b 846static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 847static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 848static void kvm_cpu_vmxon(u64 addr);
849static void kvm_cpu_vmxoff(void);
93c4adc7 850static bool vmx_mpx_supported(void);
f53cd63c 851static bool vmx_xsaves_supported(void);
d50ab6c1 852static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
776e58ea 853static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 854static void vmx_set_segment(struct kvm_vcpu *vcpu,
855 struct kvm_segment *var, int seg);
856static void vmx_get_segment(struct kvm_vcpu *vcpu,
857 struct kvm_segment *var, int seg);
d99e4152
GN		 858static bool guest_state_valid(struct kvm_vcpu *vcpu);
859static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 860static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 861static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 862static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 863static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 864
6aa8b732
AK		 865static DEFINE_PER_CPU(struct vmcs *, vmxarea);
866static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 867/*
868 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
869 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
870 */
871static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 872static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 873
3e7c73e9
AK		 874static unsigned long *vmx_io_bitmap_a;
875static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 876static unsigned long *vmx_msr_bitmap_legacy;
877static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 878static unsigned long *vmx_msr_bitmap_legacy_x2apic;
879static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 880static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 881static unsigned long *vmx_vmread_bitmap;
882static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 883
110312c8 884static bool cpu_has_load_ia32_efer;
8bf00a52 885static bool cpu_has_load_perf_global_ctrl;
110312c8 886
2384d2b3
SY		 887static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
888static DEFINE_SPINLOCK(vmx_vpid_lock);
889
1c3d14fe 890static struct vmcs_config {
6aa8b732
AK		 891 int size;
892 int order;
893 u32 revision_id;
1c3d14fe
YS		 894 u32 pin_based_exec_ctrl;
895 u32 cpu_based_exec_ctrl;
f78e0e2e 896 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 897 u32 vmexit_ctrl;
898 u32 vmentry_ctrl;
899} vmcs_config;
6aa8b732 900
efff9e53 901static struct vmx_capability {
d56f546d
SY		 902 u32 ept;
903 u32 vpid;
904} vmx_capability;
905
6aa8b732
AK		 906#define VMX_SEGMENT_FIELD(seg) \
907 [VCPU_SREG_##seg] = { \
908 .selector = GUEST_##seg##_SELECTOR, \
909 .base = GUEST_##seg##_BASE, \
910 .limit = GUEST_##seg##_LIMIT, \
911 .ar_bytes = GUEST_##seg##_AR_BYTES, \
912 }
913
772e0318 914static const struct kvm_vmx_segment_field {
6aa8b732
AK		 915 unsigned selector;
916 unsigned base;
917 unsigned limit;
918 unsigned ar_bytes;
919} kvm_vmx_segment_fields[] = {
920 VMX_SEGMENT_FIELD(CS),
921 VMX_SEGMENT_FIELD(DS),
922 VMX_SEGMENT_FIELD(ES),
923 VMX_SEGMENT_FIELD(FS),
924 VMX_SEGMENT_FIELD(GS),
925 VMX_SEGMENT_FIELD(SS),
926 VMX_SEGMENT_FIELD(TR),
927 VMX_SEGMENT_FIELD(LDTR),
928};
929
26bb0981
AK		 930static u64 host_efer;
931
6de4f3ad
AK		 932static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
933
4d56c8a7 934/*
8c06585d 935 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 936 * away by decrementing the array size.
937 */
6aa8b732 938static const u32 vmx_msr_index[] = {
05b3e0c2 939#ifdef CONFIG_X86_64
44ea2b17 940 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 941#endif
8c06585d 942 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 943};
6aa8b732 944
31299944 945static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 946{
947 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
948 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 949 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 950}
951
31299944 952static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 953{
954 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
955 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 956 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 957}
958
31299944 959static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 960{
961 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
962 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 963 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 964}
965
31299944 966static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 967{
968 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
969 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
970}
971
31299944 972static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 973{
974 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
975 INTR_INFO_VALID_MASK)) ==
976 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
977}
978
31299944 979static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 980{
04547156 981 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 982}
983
31299944 984static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 985{
04547156 986 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 987}
988
35754c98 989static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 990{
35754c98 991 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS		 992}
993
31299944 994static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 995{
04547156
SY		 996 return vmcs_config.cpu_based_exec_ctrl &
997 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 998}
999
774ead3a 1000static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 1001{
04547156
SY		 1002 return vmcs_config.cpu_based_2nd_exec_ctrl &
1003 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1004}
1005
8d14695f
YZ		 1006static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1007{
1008 return vmcs_config.cpu_based_2nd_exec_ctrl &
1009 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1010}
1011
83d4c286
YZ		 1012static inline bool cpu_has_vmx_apic_register_virt(void)
1013{
1014 return vmcs_config.cpu_based_2nd_exec_ctrl &
1015 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1016}
1017
c7c9c56c
YZ		 1018static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1019{
1020 return vmcs_config.cpu_based_2nd_exec_ctrl &
1021 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1022}
1023
01e439be
YZ		 1024static inline bool cpu_has_vmx_posted_intr(void)
1025{
d6a858d1
PB		 1026 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1027 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ		 1028}
1029
1030static inline bool cpu_has_vmx_apicv(void)
1031{
1032 return cpu_has_vmx_apic_register_virt() &&
1033 cpu_has_vmx_virtual_intr_delivery() &&
1034 cpu_has_vmx_posted_intr();
1035}
1036
04547156
SY		 1037static inline bool cpu_has_vmx_flexpriority(void)
1038{
1039 return cpu_has_vmx_tpr_shadow() &&
1040 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 1041}
1042
e799794e
MT		 1043static inline bool cpu_has_vmx_ept_execute_only(void)
1044{
31299944 1045 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 1046}
1047
e799794e
MT		 1048static inline bool cpu_has_vmx_ept_2m_page(void)
1049{
31299944 1050 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1051}
1052
878403b7
SY		 1053static inline bool cpu_has_vmx_ept_1g_page(void)
1054{
31299944 1055 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1056}
1057
4bc9b982
SY		 1058static inline bool cpu_has_vmx_ept_4levels(void)
1059{
1060 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1061}
1062
83c3a331
XH		 1063static inline bool cpu_has_vmx_ept_ad_bits(void)
1064{
1065 return vmx_capability.ept & VMX_EPT_AD_BIT;
1066}
1067
31299944 1068static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1069{
31299944 1070 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1071}
1072
31299944 1073static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1074{
31299944 1075 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1076}
1077
518c8aee
GJ		 1078static inline bool cpu_has_vmx_invvpid_single(void)
1079{
1080 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1081}
1082
b9d762fa
GJ		 1083static inline bool cpu_has_vmx_invvpid_global(void)
1084{
1085 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1086}
1087
31299944 1088static inline bool cpu_has_vmx_ept(void)
d56f546d 1089{
04547156
SY		 1090 return vmcs_config.cpu_based_2nd_exec_ctrl &
1091 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1092}
1093
31299944 1094static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1095{
1096 return vmcs_config.cpu_based_2nd_exec_ctrl &
1097 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1098}
1099
31299944 1100static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1101{
1102 return vmcs_config.cpu_based_2nd_exec_ctrl &
1103 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1104}
1105
35754c98 1106static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1107{
35754c98 1108 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 1109}
1110
31299944 1111static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1112{
04547156
SY		 1113 return vmcs_config.cpu_based_2nd_exec_ctrl &
1114 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1115}
1116
31299944 1117static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1118{
1119 return vmcs_config.cpu_based_2nd_exec_ctrl &
1120 SECONDARY_EXEC_RDTSCP;
1121}
1122
ad756a16
MJ		 1123static inline bool cpu_has_vmx_invpcid(void)
1124{
1125 return vmcs_config.cpu_based_2nd_exec_ctrl &
1126 SECONDARY_EXEC_ENABLE_INVPCID;
1127}
1128
31299944 1129static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1130{
1131 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1132}
1133
f5f48ee1
SY		 1134static inline bool cpu_has_vmx_wbinvd_exit(void)
1135{
1136 return vmcs_config.cpu_based_2nd_exec_ctrl &
1137 SECONDARY_EXEC_WBINVD_EXITING;
1138}
1139
abc4fc58
AG		 1140static inline bool cpu_has_vmx_shadow_vmcs(void)
1141{
1142 u64 vmx_msr;
1143 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1144 /* check if the cpu supports writing r/o exit information fields */
1145 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1146 return false;
1147
1148 return vmcs_config.cpu_based_2nd_exec_ctrl &
1149 SECONDARY_EXEC_SHADOW_VMCS;
1150}
1151
843e4330
KH		 1152static inline bool cpu_has_vmx_pml(void)
1153{
1154 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1155}
1156
04547156
SY		 1157static inline bool report_flexpriority(void)
1158{
1159 return flexpriority_enabled;
1160}
1161
fe3ef05c
NHE		 1162static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1163{
1164 return vmcs12->cpu_based_vm_exec_control & bit;
1165}
1166
1167static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1168{
1169 return (vmcs12->cpu_based_vm_exec_control &
1170 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1171 (vmcs12->secondary_vm_exec_control & bit);
1172}
1173
f5c4368f 1174static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1175{
1176 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1177}
1178
f4124500
JK		 1179static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1180{
1181 return vmcs12->pin_based_vm_exec_control &
1182 PIN_BASED_VMX_PREEMPTION_TIMER;
1183}
1184
155a97a3
NHE		 1185static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1186{
1187 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1188}
1189
81dc01f7
WL		 1190static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1191{
1192 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1193 vmx_xsaves_supported();
1194}
1195
f2b93280
WV		 1196static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1197{
1198 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1199}
1200
82f0dd4b
WV		 1201static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1202{
1203 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1204}
1205
608406e2
WV		 1206static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1207{
1208 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1209}
1210
705699a1
WV		 1211static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1212{
1213 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1214}
1215
644d711a
NHE		 1216static inline bool is_exception(u32 intr_info)
1217{
1218 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1219 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1220}
1221
533558bc
JK		 1222static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1223 u32 exit_intr_info,
1224 unsigned long exit_qualification);
7c177938
NHE		 1225static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1226 struct vmcs12 *vmcs12,
1227 u32 reason, unsigned long qualification);
1228
8b9cf98c 1229static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1230{
1231 int i;
1232
a2fa3e9f 1233 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1234 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1235 return i;
1236 return -1;
1237}
1238
2384d2b3
SY		 1239static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1240{
1241 struct {
1242 u64 vpid : 16;
1243 u64 rsvd : 48;
1244 u64 gva;
1245 } operand = { vpid, 0, gva };
1246
4ecac3fd 1247 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1248 /* CF==1 or ZF==1 --> rc = -1 */
1249 "; ja 1f ; ud2 ; 1:"
1250 : : "a"(&operand), "c"(ext) : "cc", "memory");
1251}
1252
1439442c
SY		 1253static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1254{
1255 struct {
1256 u64 eptp, gpa;
1257 } operand = {eptp, gpa};
1258
4ecac3fd 1259 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1260 /* CF==1 or ZF==1 --> rc = -1 */
1261 "; ja 1f ; ud2 ; 1:\n"
1262 : : "a" (&operand), "c" (ext) : "cc", "memory");
1263}
1264
26bb0981 1265static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1266{
1267 int i;
1268
8b9cf98c 1269 i = __find_msr_index(vmx, msr);
a75beee6 1270 if (i >= 0)
a2fa3e9f 1271 return &vmx->guest_msrs[i];
8b6d44c7 1272 return NULL;
7725f0ba
AK		 1273}
1274
6aa8b732
AK		 1275static void vmcs_clear(struct vmcs *vmcs)
1276{
1277 u64 phys_addr = __pa(vmcs);
1278 u8 error;
1279
4ecac3fd 1280 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1281 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1282 : "cc", "memory");
1283 if (error)
1284 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1285 vmcs, phys_addr);
1286}
1287
d462b819
NHE		 1288static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1289{
1290 vmcs_clear(loaded_vmcs->vmcs);
1291 loaded_vmcs->cpu = -1;
1292 loaded_vmcs->launched = 0;
1293}
1294
7725b894
DX		 1295static void vmcs_load(struct vmcs *vmcs)
1296{
1297 u64 phys_addr = __pa(vmcs);
1298 u8 error;
1299
1300 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1301 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1302 : "cc", "memory");
1303 if (error)
2844d849 1304 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1305 vmcs, phys_addr);
1306}
1307
2965faa5 1308#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 1309/*
1310 * This bitmap is used to indicate whether the vmclear
1311 * operation is enabled on all cpus. All disabled by
1312 * default.
1313 */
1314static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1315
1316static inline void crash_enable_local_vmclear(int cpu)
1317{
1318 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1319}
1320
1321static inline void crash_disable_local_vmclear(int cpu)
1322{
1323 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1324}
1325
1326static inline int crash_local_vmclear_enabled(int cpu)
1327{
1328 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1329}
1330
1331static void crash_vmclear_local_loaded_vmcss(void)
1332{
1333 int cpu = raw_smp_processor_id();
1334 struct loaded_vmcs *v;
1335
1336 if (!crash_local_vmclear_enabled(cpu))
1337 return;
1338
1339 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1340 loaded_vmcss_on_cpu_link)
1341 vmcs_clear(v->vmcs);
1342}
1343#else
1344static inline void crash_enable_local_vmclear(int cpu) { }
1345static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1346#endif /* CONFIG_KEXEC_CORE */
8f536b76 1347
d462b819 1348static void __loaded_vmcs_clear(void *arg)
6aa8b732 1349{
d462b819 1350 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1351 int cpu = raw_smp_processor_id();
6aa8b732 1352
d462b819
NHE		 1353 if (loaded_vmcs->cpu != cpu)
1354 return; /* vcpu migration can race with cpu offline */
1355 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1356 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1357 crash_disable_local_vmclear(cpu);
d462b819 1358 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1359
1360 /*
1361 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1362 * is before setting loaded_vmcs->vcpu to -1 which is done in
1363 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1364 * then adds the vmcs into percpu list before it is deleted.
1365 */
1366 smp_wmb();
1367
d462b819 1368 loaded_vmcs_init(loaded_vmcs);
8f536b76 1369 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1370}
1371
d462b819 1372static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1373{
e6c7d321
XG		 1374 int cpu = loaded_vmcs->cpu;
1375
1376 if (cpu != -1)
1377 smp_call_function_single(cpu,
1378 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1379}
1380
1760dd49 1381static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1382{
1383 if (vmx->vpid == 0)
1384 return;
1385
518c8aee
GJ		 1386 if (cpu_has_vmx_invvpid_single())
1387 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1388}
1389
b9d762fa
GJ		 1390static inline void vpid_sync_vcpu_global(void)
1391{
1392 if (cpu_has_vmx_invvpid_global())
1393 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1394}
1395
1396static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1397{
1398 if (cpu_has_vmx_invvpid_single())
1760dd49 1399 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1400 else
1401 vpid_sync_vcpu_global();
1402}
1403
1439442c
SY		 1404static inline void ept_sync_global(void)
1405{
1406 if (cpu_has_vmx_invept_global())
1407 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1408}
1409
1410static inline void ept_sync_context(u64 eptp)
1411{
089d034e 1412 if (enable_ept) {
1439442c
SY		 1413 if (cpu_has_vmx_invept_context())
1414 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1415 else
1416 ept_sync_global();
1417 }
1418}
1419
96304217 1420static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1421{
5e520e62 1422 unsigned long value;
6aa8b732 1423
5e520e62
AK		 1424 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1425 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1426 return value;
1427}
1428
96304217 1429static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1430{
1431 return vmcs_readl(field);
1432}
1433
96304217 1434static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1435{
1436 return vmcs_readl(field);
1437}
1438
96304217 1439static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1440{
05b3e0c2 1441#ifdef CONFIG_X86_64
6aa8b732
AK		 1442 return vmcs_readl(field);
1443#else
1444 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1445#endif
1446}
1447
e52de1b8
AK		 1448static noinline void vmwrite_error(unsigned long field, unsigned long value)
1449{
1450 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1451 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1452 dump_stack();
1453}
1454
6aa8b732
AK		 1455static void vmcs_writel(unsigned long field, unsigned long value)
1456{
1457 u8 error;
1458
4ecac3fd 1459 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1460 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1461 if (unlikely(error))
1462 vmwrite_error(field, value);
6aa8b732
AK		 1463}
1464
1465static void vmcs_write16(unsigned long field, u16 value)
1466{
1467 vmcs_writel(field, value);
1468}
1469
1470static void vmcs_write32(unsigned long field, u32 value)
1471{
1472 vmcs_writel(field, value);
1473}
1474
1475static void vmcs_write64(unsigned long field, u64 value)
1476{
6aa8b732 1477 vmcs_writel(field, value);
7682f2d0 1478#ifndef CONFIG_X86_64
6aa8b732
AK		 1479 asm volatile ("");
1480 vmcs_writel(field+1, value >> 32);
1481#endif
1482}
1483
2ab455cc
AL		 1484static void vmcs_clear_bits(unsigned long field, u32 mask)
1485{
1486 vmcs_writel(field, vmcs_readl(field) & ~mask);
1487}
1488
1489static void vmcs_set_bits(unsigned long field, u32 mask)
1490{
1491 vmcs_writel(field, vmcs_readl(field) | mask);
1492}
1493
2961e876
GN		 1494static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1495{
1496 vmcs_write32(VM_ENTRY_CONTROLS, val);
1497 vmx->vm_entry_controls_shadow = val;
1498}
1499
1500static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1501{
1502 if (vmx->vm_entry_controls_shadow != val)
1503 vm_entry_controls_init(vmx, val);
1504}
1505
1506static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1507{
1508 return vmx->vm_entry_controls_shadow;
1509}
1510
1511
1512static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1513{
1514 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1515}
1516
1517static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1518{
1519 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1520}
1521
1522static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1523{
1524 vmcs_write32(VM_EXIT_CONTROLS, val);
1525 vmx->vm_exit_controls_shadow = val;
1526}
1527
1528static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1529{
1530 if (vmx->vm_exit_controls_shadow != val)
1531 vm_exit_controls_init(vmx, val);
1532}
1533
1534static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1535{
1536 return vmx->vm_exit_controls_shadow;
1537}
1538
1539
1540static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1541{
1542 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1543}
1544
1545static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1546{
1547 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1548}
1549
2fb92db1
AK		 1550static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1551{
1552 vmx->segment_cache.bitmask = 0;
1553}
1554
1555static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1556 unsigned field)
1557{
1558 bool ret;
1559 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1560
1561 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1562 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1563 vmx->segment_cache.bitmask = 0;
1564 }
1565 ret = vmx->segment_cache.bitmask & mask;
1566 vmx->segment_cache.bitmask |= mask;
1567 return ret;
1568}
1569
1570static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1571{
1572 u16 *p = &vmx->segment_cache.seg[seg].selector;
1573
1574 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1575 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1576 return *p;
1577}
1578
1579static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1580{
1581 ulong *p = &vmx->segment_cache.seg[seg].base;
1582
1583 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1584 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1585 return *p;
1586}
1587
1588static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1589{
1590 u32 *p = &vmx->segment_cache.seg[seg].limit;
1591
1592 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1593 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1594 return *p;
1595}
1596
1597static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1598{
1599 u32 *p = &vmx->segment_cache.seg[seg].ar;
1600
1601 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1602 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1603 return *p;
1604}
1605
abd3f2d6
AK		 1606static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1607{
1608 u32 eb;
1609
fd7373cc
JK		 1610 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1611 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1612 if ((vcpu->guest_debug &
1613 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1614 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1615 eb |= 1u << BP_VECTOR;
7ffd92c5 1616 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1617 eb = ~0;
089d034e 1618 if (enable_ept)
1439442c 1619 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1620 if (vcpu->fpu_active)
1621 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1622
1623 /* When we are running a nested L2 guest and L1 specified for it a
1624 * certain exception bitmap, we must trap the same exceptions and pass
1625 * them to L1. When running L2, we will only handle the exceptions
1626 * specified above if L1 did not want them.
1627 */
1628 if (is_guest_mode(vcpu))
1629 eb |= get_vmcs12(vcpu)->exception_bitmap;
1630
abd3f2d6
AK		 1631 vmcs_write32(EXCEPTION_BITMAP, eb);
1632}
1633
2961e876
GN		 1634static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1635 unsigned long entry, unsigned long exit)
8bf00a52 1636{
2961e876
GN		 1637 vm_entry_controls_clearbit(vmx, entry);
1638 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1639}
1640
61d2ef2c
AK		 1641static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1642{
1643 unsigned i;
1644 struct msr_autoload *m = &vmx->msr_autoload;
1645
8bf00a52
GN		 1646 switch (msr) {
1647 case MSR_EFER:
1648 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1649 clear_atomic_switch_msr_special(vmx,
1650 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1651 VM_EXIT_LOAD_IA32_EFER);
1652 return;
1653 }
1654 break;
1655 case MSR_CORE_PERF_GLOBAL_CTRL:
1656 if (cpu_has_load_perf_global_ctrl) {
2961e876 1657 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1658 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1659 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1660 return;
1661 }
1662 break;
110312c8
AK		 1663 }
1664
61d2ef2c
AK		 1665 for (i = 0; i < m->nr; ++i)
1666 if (m->guest[i].index == msr)
1667 break;
1668
1669 if (i == m->nr)
1670 return;
1671 --m->nr;
1672 m->guest[i] = m->guest[m->nr];
1673 m->host[i] = m->host[m->nr];
1674 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1675 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1676}
1677
2961e876
GN		 1678static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1679 unsigned long entry, unsigned long exit,
1680 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1681 u64 guest_val, u64 host_val)
8bf00a52
GN		 1682{
1683 vmcs_write64(guest_val_vmcs, guest_val);
1684 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1685 vm_entry_controls_setbit(vmx, entry);
1686 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1687}
1688
61d2ef2c
AK		 1689static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1690 u64 guest_val, u64 host_val)
1691{
1692 unsigned i;
1693 struct msr_autoload *m = &vmx->msr_autoload;
1694
8bf00a52
GN		 1695 switch (msr) {
1696 case MSR_EFER:
1697 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1698 add_atomic_switch_msr_special(vmx,
1699 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1700 VM_EXIT_LOAD_IA32_EFER,
1701 GUEST_IA32_EFER,
1702 HOST_IA32_EFER,
1703 guest_val, host_val);
1704 return;
1705 }
1706 break;
1707 case MSR_CORE_PERF_GLOBAL_CTRL:
1708 if (cpu_has_load_perf_global_ctrl) {
2961e876 1709 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1710 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1711 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1712 GUEST_IA32_PERF_GLOBAL_CTRL,
1713 HOST_IA32_PERF_GLOBAL_CTRL,
1714 guest_val, host_val);
1715 return;
1716 }
1717 break;
110312c8
AK		 1718 }
1719
61d2ef2c
AK		 1720 for (i = 0; i < m->nr; ++i)
1721 if (m->guest[i].index == msr)
1722 break;
1723
e7fc6f93 1724 if (i == NR_AUTOLOAD_MSRS) {
60266204 1725 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1726 "Can't add msr %x\n", msr);
1727 return;
1728 } else if (i == m->nr) {
61d2ef2c
AK		 1729 ++m->nr;
1730 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1731 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1732 }
1733
1734 m->guest[i].index = msr;
1735 m->guest[i].value = guest_val;
1736 m->host[i].index = msr;
1737 m->host[i].value = host_val;
1738}
1739
33ed6329
AK		 1740static void reload_tss(void)
1741{
33ed6329
AK		 1742 /*
1743 * VT restores TR but not its size. Useless.
1744 */
89cbc767 1745 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1746 struct desc_struct *descs;
33ed6329 1747
d359192f 1748 descs = (void *)gdt->address;
33ed6329
AK		 1749 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1750 load_TR_desc();
33ed6329
AK		 1751}
1752
92c0d900 1753static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1754{
3a34a881 1755 u64 guest_efer;
51c6cf66
AK		 1756 u64 ignore_bits;
1757
f6801dff 1758 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1759
51c6cf66 1760 /*
0fa06071 1761 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1762 * outside long mode
1763 */
1764 ignore_bits = EFER_NX | EFER_SCE;
1765#ifdef CONFIG_X86_64
1766 ignore_bits |= EFER_LMA | EFER_LME;
1767 /* SCE is meaningful only in long mode on Intel */
1768 if (guest_efer & EFER_LMA)
1769 ignore_bits &= ~(u64)EFER_SCE;
1770#endif
51c6cf66
AK		 1771 guest_efer &= ~ignore_bits;
1772 guest_efer |= host_efer & ignore_bits;
26bb0981 1773 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1774 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1775
1776 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1777
1778 /*
1779 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1780 * On CPUs that support "load IA32_EFER", always switch EFER
1781 * atomically, since it's faster than switching it manually.
1782 */
1783 if (cpu_has_load_ia32_efer ||
1784 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1785 guest_efer = vmx->vcpu.arch.efer;
1786 if (!(guest_efer & EFER_LMA))
1787 guest_efer &= ~EFER_LME;
54b98bff
AL		 1788 if (guest_efer != host_efer)
1789 add_atomic_switch_msr(vmx, MSR_EFER,
1790 guest_efer, host_efer);
84ad33ef
AK		 1791 return false;
1792 }
1793
26bb0981 1794 return true;
51c6cf66
AK		 1795}
1796
2d49ec72
GN		 1797static unsigned long segment_base(u16 selector)
1798{
89cbc767 1799 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1800 struct desc_struct *d;
1801 unsigned long table_base;
1802 unsigned long v;
1803
1804 if (!(selector & ~3))
1805 return 0;
1806
d359192f 1807 table_base = gdt->address;
2d49ec72
GN		 1808
1809 if (selector & 4) { /* from ldt */
1810 u16 ldt_selector = kvm_read_ldt();
1811
1812 if (!(ldt_selector & ~3))
1813 return 0;
1814
1815 table_base = segment_base(ldt_selector);
1816 }
1817 d = (struct desc_struct *)(table_base + (selector & ~7));
1818 v = get_desc_base(d);
1819#ifdef CONFIG_X86_64
1820 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1821 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1822#endif
1823 return v;
1824}
1825
1826static inline unsigned long kvm_read_tr_base(void)
1827{
1828 u16 tr;
1829 asm("str %0" : "=g"(tr));
1830 return segment_base(tr);
1831}
1832
04d2cc77 1833static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1834{
04d2cc77 1835 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1836 int i;
04d2cc77 1837
a2fa3e9f 1838 if (vmx->host_state.loaded)
33ed6329
AK		 1839 return;
1840
a2fa3e9f 1841 vmx->host_state.loaded = 1;
33ed6329
AK		 1842 /*
1843 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1844 * allow segment selectors with cpl > 0 or ti == 1.
1845 */
d6e88aec 1846 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1847 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1848 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1849 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1850 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1851 vmx->host_state.fs_reload_needed = 0;
1852 } else {
33ed6329 1853 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1854 vmx->host_state.fs_reload_needed = 1;
33ed6329 1855 }
9581d442 1856 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1857 if (!(vmx->host_state.gs_sel & 7))
1858 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1859 else {
1860 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1861 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1862 }
1863
b2da15ac
AK		 1864#ifdef CONFIG_X86_64
1865 savesegment(ds, vmx->host_state.ds_sel);
1866 savesegment(es, vmx->host_state.es_sel);
1867#endif
1868
33ed6329
AK		 1869#ifdef CONFIG_X86_64
1870 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1871 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1872#else
a2fa3e9f
GH		 1873 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1874 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1875#endif
707c0874
AK		 1876
1877#ifdef CONFIG_X86_64
c8770e7b
AK		 1878 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1879 if (is_long_mode(&vmx->vcpu))
44ea2b17 1880 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1881#endif
da8999d3
LJ		 1882 if (boot_cpu_has(X86_FEATURE_MPX))
1883 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1884 for (i = 0; i < vmx->save_nmsrs; ++i)
1885 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1886 vmx->guest_msrs[i].data,
1887 vmx->guest_msrs[i].mask);
33ed6329
AK		 1888}
1889
a9b21b62 1890static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1891{
a2fa3e9f 1892 if (!vmx->host_state.loaded)
33ed6329
AK		 1893 return;
1894
e1beb1d3 1895 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1896 vmx->host_state.loaded = 0;
c8770e7b
AK		 1897#ifdef CONFIG_X86_64
1898 if (is_long_mode(&vmx->vcpu))
1899 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1900#endif
152d3f2f 1901 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1902 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1903#ifdef CONFIG_X86_64
9581d442 1904 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1905#else
1906 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1907#endif
33ed6329 1908 }
0a77fe4c
AK		 1909 if (vmx->host_state.fs_reload_needed)
1910 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1911#ifdef CONFIG_X86_64
1912 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1913 loadsegment(ds, vmx->host_state.ds_sel);
1914 loadsegment(es, vmx->host_state.es_sel);
1915 }
b2da15ac 1916#endif
152d3f2f 1917 reload_tss();
44ea2b17 1918#ifdef CONFIG_X86_64
c8770e7b 1919 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1920#endif
da8999d3
LJ		 1921 if (vmx->host_state.msr_host_bndcfgs)
1922 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1923 /*
1924 * If the FPU is not active (through the host task or
1925 * the guest vcpu), then restore the cr0.TS bit.
1926 */
3c6dffa9 1927 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
b1a74bf8 1928 stts();
89cbc767 1929 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1930}
1931
a9b21b62
AK		 1932static void vmx_load_host_state(struct vcpu_vmx *vmx)
1933{
1934 preempt_disable();
1935 __vmx_load_host_state(vmx);
1936 preempt_enable();
1937}
1938
6aa8b732
AK		 1939/*
1940 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1941 * vcpu mutex is already taken.
1942 */
15ad7146 1943static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1944{
a2fa3e9f 1945 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1946 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1947
4610c9cc
DX		 1948 if (!vmm_exclusive)
1949 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1950 else if (vmx->loaded_vmcs->cpu != cpu)
1951 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1952
d462b819
NHE		 1953 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1954 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1955 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1956 }
1957
d462b819 1958 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1959 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1960 unsigned long sysenter_esp;
1961
a8eeb04a 1962 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1963 local_irq_disable();
8f536b76 1964 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1965
1966 /*
1967 * Read loaded_vmcs->cpu should be before fetching
1968 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1969 * See the comments in __loaded_vmcs_clear().
1970 */
1971 smp_rmb();
1972
d462b819
NHE		 1973 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1974 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1975 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1976 local_irq_enable();
1977
6aa8b732
AK		 1978 /*
1979 * Linux uses per-cpu TSS and GDT, so set these when switching
1980 * processors.
1981 */
d6e88aec 1982 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1983 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1984
1985 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1986 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1987 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1988 }
6aa8b732
AK		 1989}
1990
1991static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1992{
a9b21b62 1993 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1994 if (!vmm_exclusive) {
d462b819
NHE		 1995 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1996 vcpu->cpu = -1;
4610c9cc
DX		 1997 kvm_cpu_vmxoff();
1998 }
6aa8b732
AK		 1999}
2000
5fd86fcf
AK		 2001static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2002{
81231c69
AK		 2003 ulong cr0;
2004
5fd86fcf
AK		 2005 if (vcpu->fpu_active)
2006 return;
2007 vcpu->fpu_active = 1;
81231c69
AK		 2008 cr0 = vmcs_readl(GUEST_CR0);
2009 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2010 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2011 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 2012 update_exception_bitmap(vcpu);
edcafe3c 2013 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 2014 if (is_guest_mode(vcpu))
2015 vcpu->arch.cr0_guest_owned_bits &=
2016 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 2017 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 2018}
2019
edcafe3c
AK		 2020static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2021
fe3ef05c
NHE		 2022/*
2023 * Return the cr0 value that a nested guest would read. This is a combination
2024 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2025 * its hypervisor (cr0_read_shadow).
2026 */
2027static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2028{
2029 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2030 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2031}
2032static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2033{
2034 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2035 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2036}
2037
5fd86fcf
AK		 2038static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2039{
36cf24e0
NHE		 2040 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2041 * set this *before* calling this function.
2042 */
edcafe3c 2043 vmx_decache_cr0_guest_bits(vcpu);
81231c69 2044 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 2045 update_exception_bitmap(vcpu);
edcafe3c
AK		 2046 vcpu->arch.cr0_guest_owned_bits = 0;
2047 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 2048 if (is_guest_mode(vcpu)) {
2049 /*
2050 * L1's specified read shadow might not contain the TS bit,
2051 * so now that we turned on shadowing of this bit, we need to
2052 * set this bit of the shadow. Like in nested_vmx_run we need
2053 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2054 * up-to-date here because we just decached cr0.TS (and we'll
2055 * only update vmcs12->guest_cr0 on nested exit).
2056 */
2057 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2058 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2059 (vcpu->arch.cr0 & X86_CR0_TS);
2060 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2061 } else
2062 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2063}
2064
6aa8b732
AK		 2065static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2066{
78ac8b47 2067 unsigned long rflags, save_rflags;
345dcaa8 2068
6de12732
AK		 2069 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2070 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2071 rflags = vmcs_readl(GUEST_RFLAGS);
2072 if (to_vmx(vcpu)->rmode.vm86_active) {
2073 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2074 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2075 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2076 }
2077 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2078 }
6de12732 2079 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2080}
2081
2082static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2083{
6de12732
AK		 2084 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2085 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2086 if (to_vmx(vcpu)->rmode.vm86_active) {
2087 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2088 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2089 }
6aa8b732
AK		 2090 vmcs_writel(GUEST_RFLAGS, rflags);
2091}
2092
37ccdcbe 2093static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2094{
2095 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2096 int ret = 0;
2097
2098 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2099 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2100 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2101 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2102
37ccdcbe 2103 return ret;
2809f5d2
GC		 2104}
2105
2106static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2107{
2108 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2109 u32 interruptibility = interruptibility_old;
2110
2111 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2112
48005f64 2113 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2114 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2115 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2116 interruptibility |= GUEST_INTR_STATE_STI;
2117
2118 if ((interruptibility != interruptibility_old))
2119 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2120}
2121
6aa8b732
AK		 2122static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2123{
2124 unsigned long rip;
6aa8b732 2125
5fdbf976 2126 rip = kvm_rip_read(vcpu);
6aa8b732 2127 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2128 kvm_rip_write(vcpu, rip);
6aa8b732 2129
2809f5d2
GC		 2130 /* skipping an emulated instruction also counts */
2131 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2132}
2133
0b6ac343
NHE		 2134/*
2135 * KVM wants to inject page-faults which it got to the guest. This function
2136 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2137 */
e011c663 2138static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2139{
2140 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2141
e011c663 2142 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2143 return 0;
2144
533558bc
JK		 2145 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2146 vmcs_read32(VM_EXIT_INTR_INFO),
2147 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2148 return 1;
2149}
2150
298101da 2151static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2152 bool has_error_code, u32 error_code,
2153 bool reinject)
298101da 2154{
77ab6db0 2155 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2156 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2157
e011c663
GN		 2158 if (!reinject && is_guest_mode(vcpu) &&
2159 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2160 return;
2161
8ab2d2e2 2162 if (has_error_code) {
77ab6db0 2163 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2164 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2165 }
77ab6db0 2166
7ffd92c5 2167 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2168 int inc_eip = 0;
2169 if (kvm_exception_is_soft(nr))
2170 inc_eip = vcpu->arch.event_exit_inst_len;
2171 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2172 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2173 return;
2174 }
2175
66fd3f7f
GN		 2176 if (kvm_exception_is_soft(nr)) {
2177 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2178 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2179 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2180 } else
2181 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2182
2183 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2184}
2185
4e47c7a6
SY		 2186static bool vmx_rdtscp_supported(void)
2187{
2188 return cpu_has_vmx_rdtscp();
2189}
2190
ad756a16
MJ		 2191static bool vmx_invpcid_supported(void)
2192{
2193 return cpu_has_vmx_invpcid() && enable_ept;
2194}
2195
a75beee6
ED		 2196/*
2197 * Swap MSR entry in host/guest MSR entry array.
2198 */
8b9cf98c 2199static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2200{
26bb0981 2201 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2202
2203 tmp = vmx->guest_msrs[to];
2204 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2205 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2206}
2207
8d14695f
YZ		 2208static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2209{
2210 unsigned long *msr_bitmap;
2211
670125bd
WV		 2212 if (is_guest_mode(vcpu))
2213 msr_bitmap = vmx_msr_bitmap_nested;
8a9781f7 2214 else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
8d14695f
YZ		 2215 if (is_long_mode(vcpu))
2216 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2217 else
2218 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2219 } else {
2220 if (is_long_mode(vcpu))
2221 msr_bitmap = vmx_msr_bitmap_longmode;
2222 else
2223 msr_bitmap = vmx_msr_bitmap_legacy;
2224 }
2225
2226 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2227}
2228
e38aea3e
AK		 2229/*
2230 * Set up the vmcs to automatically save and restore system
2231 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2232 * mode, as fiddling with msrs is very expensive.
2233 */
8b9cf98c 2234static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2235{
26bb0981 2236 int save_nmsrs, index;
e38aea3e 2237
a75beee6
ED		 2238 save_nmsrs = 0;
2239#ifdef CONFIG_X86_64
8b9cf98c 2240 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2241 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2242 if (index >= 0)
8b9cf98c
RR		 2243 move_msr_up(vmx, index, save_nmsrs++);
2244 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2245 if (index >= 0)
8b9cf98c
RR		 2246 move_msr_up(vmx, index, save_nmsrs++);
2247 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2248 if (index >= 0)
8b9cf98c 2249 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6 2250 index = __find_msr_index(vmx, MSR_TSC_AUX);
1cea0ce6 2251 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
4e47c7a6 2252 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2253 /*
8c06585d 2254 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2255 * if efer.sce is enabled.
2256 */
8c06585d 2257 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2258 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2259 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2260 }
2261#endif
92c0d900
AK		 2262 index = __find_msr_index(vmx, MSR_EFER);
2263 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2264 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2265
26bb0981 2266 vmx->save_nmsrs = save_nmsrs;
5897297b 2267
8d14695f
YZ		 2268 if (cpu_has_vmx_msr_bitmap())
2269 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2270}
2271
6aa8b732
AK		 2272/*
2273 * reads and returns guest's timestamp counter "register"
2274 * guest_tsc = host_tsc + tsc_offset -- 21.3
2275 */
2276static u64 guest_read_tsc(void)
2277{
2278 u64 host_tsc, tsc_offset;
2279
4ea1636b 2280 host_tsc = rdtsc();
6aa8b732
AK		 2281 tsc_offset = vmcs_read64(TSC_OFFSET);
2282 return host_tsc + tsc_offset;
2283}
2284
d5c1785d
NHE		 2285/*
2286 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2287 * counter, even if a nested guest (L2) is currently running.
2288 */
48d89b92 2289static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2290{
886b470c 2291 u64 tsc_offset;
d5c1785d 2292
d5c1785d
NHE		 2293 tsc_offset = is_guest_mode(vcpu) ?
2294 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2295 vmcs_read64(TSC_OFFSET);
2296 return host_tsc + tsc_offset;
2297}
2298
4051b188 2299/*
cc578287
ZA		 2300 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2301 * software catchup for faster rates on slower CPUs.
4051b188 2302 */
cc578287 2303static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2304{
cc578287
ZA		 2305 if (!scale)
2306 return;
2307
2308 if (user_tsc_khz > tsc_khz) {
2309 vcpu->arch.tsc_catchup = 1;
2310 vcpu->arch.tsc_always_catchup = 1;
2311 } else
2312 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2313}
2314
ba904635
WA		 2315static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2316{
2317 return vmcs_read64(TSC_OFFSET);
2318}
2319
6aa8b732 2320/*
99e3e30a 2321 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2322 */
99e3e30a 2323static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2324{
27fc51b2 2325 if (is_guest_mode(vcpu)) {
7991825b 2326 /*
27fc51b2
NHE		 2327 * We're here if L1 chose not to trap WRMSR to TSC. According
2328 * to the spec, this should set L1's TSC; The offset that L1
2329 * set for L2 remains unchanged, and still needs to be added
2330 * to the newly set TSC to get L2's TSC.
7991825b 2331 */
27fc51b2
NHE		 2332 struct vmcs12 *vmcs12;
2333 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2334 /* recalculate vmcs02.TSC_OFFSET: */
2335 vmcs12 = get_vmcs12(vcpu);
2336 vmcs_write64(TSC_OFFSET, offset +
2337 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2338 vmcs12->tsc_offset : 0));
2339 } else {
489223ed
YY		 2340 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2341 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2342 vmcs_write64(TSC_OFFSET, offset);
2343 }
6aa8b732
AK		 2344}
2345
f1e2b260 2346static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2347{
2348 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2349
e48672fa 2350 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2351 if (is_guest_mode(vcpu)) {
2352 /* Even when running L2, the adjustment needs to apply to L1 */
2353 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2354 } else
2355 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2356 offset + adjustment);
e48672fa
ZA		 2357}
2358
857e4099
JR		 2359static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2360{
4ea1636b 2361 return target_tsc - rdtsc();
857e4099
JR		 2362}
2363
801d3424
NHE		 2364static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2365{
2366 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2367 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2368}
2369
2370/*
2371 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2372 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2373 * all guests if the "nested" module option is off, and can also be disabled
2374 * for a single guest by disabling its VMX cpuid bit.
2375 */
2376static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2377{
2378 return nested && guest_cpuid_has_vmx(vcpu);
2379}
2380
b87a51ae
NHE		 2381/*
2382 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2383 * returned for the various VMX controls MSRs when nested VMX is enabled.
2384 * The same values should also be used to verify that vmcs12 control fields are
2385 * valid during nested entry from L1 to L2.
2386 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2387 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2388 * bit in the high half is on if the corresponding bit in the control field
2389 * may be on. See also vmx_control_verify().
b87a51ae 2390 */
b9c237bb 2391static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2392{
2393 /*
2394 * Note that as a general rule, the high half of the MSRs (bits in
2395 * the control fields which may be 1) should be initialized by the
2396 * intersection of the underlying hardware's MSR (i.e., features which
2397 * can be supported) and the list of features we want to expose -
2398 * because they are known to be properly supported in our code.
2399 * Also, usually, the low half of the MSRs (bits which must be 1) can
2400 * be set to 0, meaning that L1 may turn off any of these bits. The
2401 * reason is that if one of these bits is necessary, it will appear
2402 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2403 * fields of vmcs01 and vmcs02, will turn these bits off - and
2404 * nested_vmx_exit_handled() will not pass related exits to L1.
2405 * These rules have exceptions below.
2406 */
2407
2408 /* pin-based controls */
eabeaacc 2409 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2410 vmx->nested.nested_vmx_pinbased_ctls_low,
2411 vmx->nested.nested_vmx_pinbased_ctls_high);
2412 vmx->nested.nested_vmx_pinbased_ctls_low |=
2413 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2414 vmx->nested.nested_vmx_pinbased_ctls_high &=
2415 PIN_BASED_EXT_INTR_MASK |
2416 PIN_BASED_NMI_EXITING |
2417 PIN_BASED_VIRTUAL_NMIS;
2418 vmx->nested.nested_vmx_pinbased_ctls_high |=
2419 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2420 PIN_BASED_VMX_PREEMPTION_TIMER;
35754c98 2421 if (vmx_cpu_uses_apicv(&vmx->vcpu))
705699a1
WV		 2422 vmx->nested.nested_vmx_pinbased_ctls_high |=
2423 PIN_BASED_POSTED_INTR;
b87a51ae 2424
3dbcd8da 2425 /* exit controls */
c0dfee58 2426 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2427 vmx->nested.nested_vmx_exit_ctls_low,
2428 vmx->nested.nested_vmx_exit_ctls_high);
2429 vmx->nested.nested_vmx_exit_ctls_low =
2430 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2431
b9c237bb 2432 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2433#ifdef CONFIG_X86_64
c0dfee58 2434 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2435#endif
f4124500 2436 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2437 vmx->nested.nested_vmx_exit_ctls_high |=
2438 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2439 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2440 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2441
36be0b9d 2442 if (vmx_mpx_supported())
b9c237bb 2443 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2444
2996fca0 2445 /* We support free control of debug control saving. */
b9c237bb
WV		 2446 vmx->nested.nested_vmx_true_exit_ctls_low =
2447 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2448 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2449
b87a51ae
NHE		 2450 /* entry controls */
2451 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2452 vmx->nested.nested_vmx_entry_ctls_low,
2453 vmx->nested.nested_vmx_entry_ctls_high);
2454 vmx->nested.nested_vmx_entry_ctls_low =
2455 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2456 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2457#ifdef CONFIG_X86_64
2458 VM_ENTRY_IA32E_MODE |
2459#endif
2460 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2461 vmx->nested.nested_vmx_entry_ctls_high |=
2462 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2463 if (vmx_mpx_supported())
b9c237bb 2464 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2465
2996fca0 2466 /* We support free control of debug control loading. */
b9c237bb
WV		 2467 vmx->nested.nested_vmx_true_entry_ctls_low =
2468 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2469 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2470
b87a51ae
NHE		 2471 /* cpu-based controls */
2472 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2473 vmx->nested.nested_vmx_procbased_ctls_low,
2474 vmx->nested.nested_vmx_procbased_ctls_high);
2475 vmx->nested.nested_vmx_procbased_ctls_low =
2476 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2477 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2478 CPU_BASED_VIRTUAL_INTR_PENDING |
2479 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2480 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2481 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2482 CPU_BASED_CR3_STORE_EXITING |
2483#ifdef CONFIG_X86_64
2484 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2485#endif
2486 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD		 2487 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2488 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2489 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2490 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE		 2491 /*
2492 * We can allow some features even when not supported by the
2493 * hardware. For example, L1 can specify an MSR bitmap - and we
2494 * can use it to avoid exits to L1 - even when L0 runs L2
2495 * without MSR bitmaps.
2496 */
b9c237bb
WV		 2497 vmx->nested.nested_vmx_procbased_ctls_high |=
2498 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2499 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2500
3dcdf3ec 2501 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2502 vmx->nested.nested_vmx_true_procbased_ctls_low =
2503 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2504 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2505
b87a51ae
NHE		 2506 /* secondary cpu-based controls */
2507 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2508 vmx->nested.nested_vmx_secondary_ctls_low,
2509 vmx->nested.nested_vmx_secondary_ctls_high);
2510 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2511 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2512 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2513 SECONDARY_EXEC_RDTSCP |
f2b93280 2514 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2515 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2516 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7 2517 SECONDARY_EXEC_WBINVD_EXITING |
8b3e34e4
XG		 2518 SECONDARY_EXEC_XSAVES |
2519 SECONDARY_EXEC_PCOMMIT;
c18911a2 2520
afa61f75
NHE		 2521 if (enable_ept) {
2522 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2523 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2524 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2525 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2526 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2527 VMX_EPT_INVEPT_BIT;
b9c237bb 2528 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2529 /*
4b855078
BD		 2530 * For nested guests, we don't do anything specific
2531 * for single context invalidation. Hence, only advertise
2532 * support for global context invalidation.
afa61f75 2533 */
b9c237bb 2534 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2535 } else
b9c237bb 2536 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2537
0790ec17
RK		 2538 if (enable_unrestricted_guest)
2539 vmx->nested.nested_vmx_secondary_ctls_high |=
2540 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2541
c18911a2 2542 /* miscellaneous data */
b9c237bb
WV		 2543 rdmsr(MSR_IA32_VMX_MISC,
2544 vmx->nested.nested_vmx_misc_low,
2545 vmx->nested.nested_vmx_misc_high);
2546 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2547 vmx->nested.nested_vmx_misc_low |=
2548 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2549 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2550 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2551}
2552
2553static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2554{
2555 /*
2556 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2557 */
2558 return ((control & high) | low) == control;
2559}
2560
2561static inline u64 vmx_control_msr(u32 low, u32 high)
2562{
2563 return low | ((u64)high << 32);
2564}
2565
cae50139 2566/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2567static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2568{
b9c237bb
WV		 2569 struct vcpu_vmx *vmx = to_vmx(vcpu);
2570
b87a51ae 2571 switch (msr_index) {
b87a51ae
NHE		 2572 case MSR_IA32_VMX_BASIC:
2573 /*
2574 * This MSR reports some information about VMX support. We
2575 * should return information about the VMX we emulate for the
2576 * guest, and the VMCS structure we give it - not about the
2577 * VMX support of the underlying hardware.
2578 */
3dbcd8da 2579 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2580 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2581 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2582 break;
2583 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2584 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2585 *pdata = vmx_control_msr(
2586 vmx->nested.nested_vmx_pinbased_ctls_low,
2587 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2588 break;
2589 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2590 *pdata = vmx_control_msr(
2591 vmx->nested.nested_vmx_true_procbased_ctls_low,
2592 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2593 break;
b87a51ae 2594 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2595 *pdata = vmx_control_msr(
2596 vmx->nested.nested_vmx_procbased_ctls_low,
2597 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2598 break;
2599 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2600 *pdata = vmx_control_msr(
2601 vmx->nested.nested_vmx_true_exit_ctls_low,
2602 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2603 break;
b87a51ae 2604 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2605 *pdata = vmx_control_msr(
2606 vmx->nested.nested_vmx_exit_ctls_low,
2607 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2608 break;
2609 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2610 *pdata = vmx_control_msr(
2611 vmx->nested.nested_vmx_true_entry_ctls_low,
2612 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2613 break;
b87a51ae 2614 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2615 *pdata = vmx_control_msr(
2616 vmx->nested.nested_vmx_entry_ctls_low,
2617 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2618 break;
2619 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2620 *pdata = vmx_control_msr(
2621 vmx->nested.nested_vmx_misc_low,
2622 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2623 break;
2624 /*
2625 * These MSRs specify bits which the guest must keep fixed (on or off)
2626 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2627 * We picked the standard core2 setting.
2628 */
2629#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2630#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2631 case MSR_IA32_VMX_CR0_FIXED0:
2632 *pdata = VMXON_CR0_ALWAYSON;
2633 break;
2634 case MSR_IA32_VMX_CR0_FIXED1:
2635 *pdata = -1ULL;
2636 break;
2637 case MSR_IA32_VMX_CR4_FIXED0:
2638 *pdata = VMXON_CR4_ALWAYSON;
2639 break;
2640 case MSR_IA32_VMX_CR4_FIXED1:
2641 *pdata = -1ULL;
2642 break;
2643 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2644 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2645 break;
2646 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2647 *pdata = vmx_control_msr(
2648 vmx->nested.nested_vmx_secondary_ctls_low,
2649 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2650 break;
2651 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2652 /* Currently, no nested vpid support */
b9c237bb 2653 *pdata = vmx->nested.nested_vmx_ept_caps;
b87a51ae
NHE		 2654 break;
2655 default:
b87a51ae 2656 return 1;
b3897a49
NHE		 2657 }
2658
b87a51ae
NHE		 2659 return 0;
2660}
2661
6aa8b732
AK		 2662/*
2663 * Reads an msr value (of 'msr_index') into 'pdata'.
2664 * Returns 0 on success, non-0 otherwise.
2665 * Assumes vcpu_load() was already called.
2666 */
609e36d3 2667static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2668{
26bb0981 2669 struct shared_msr_entry *msr;
6aa8b732 2670
609e36d3 2671 switch (msr_info->index) {
05b3e0c2 2672#ifdef CONFIG_X86_64
6aa8b732 2673 case MSR_FS_BASE:
609e36d3 2674 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK		 2675 break;
2676 case MSR_GS_BASE:
609e36d3 2677 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 2678 break;
44ea2b17
AK		 2679 case MSR_KERNEL_GS_BASE:
2680 vmx_load_host_state(to_vmx(vcpu));
609e36d3 2681 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 2682 break;
26bb0981 2683#endif
6aa8b732 2684 case MSR_EFER:
609e36d3 2685 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 2686 case MSR_IA32_TSC:
609e36d3 2687 msr_info->data = guest_read_tsc();
6aa8b732
AK		 2688 break;
2689 case MSR_IA32_SYSENTER_CS:
609e36d3 2690 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 2691 break;
2692 case MSR_IA32_SYSENTER_EIP:
609e36d3 2693 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2694 break;
2695 case MSR_IA32_SYSENTER_ESP:
609e36d3 2696 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2697 break;
0dd376e7 2698 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2699 if (!vmx_mpx_supported())
2700 return 1;
609e36d3 2701 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 2702 break;
cae50139
JK		 2703 case MSR_IA32_FEATURE_CONTROL:
2704 if (!nested_vmx_allowed(vcpu))
2705 return 1;
609e36d3 2706 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
cae50139
JK		 2707 break;
2708 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2709 if (!nested_vmx_allowed(vcpu))
2710 return 1;
609e36d3 2711 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL		 2712 case MSR_IA32_XSS:
2713 if (!vmx_xsaves_supported())
2714 return 1;
609e36d3 2715 msr_info->data = vcpu->arch.ia32_xss;
20300099 2716 break;
4e47c7a6 2717 case MSR_TSC_AUX:
1cea0ce6 2718 if (!guest_cpuid_has_rdtscp(vcpu))
4e47c7a6
SY		 2719 return 1;
2720 /* Otherwise falls through */
6aa8b732 2721 default:
609e36d3 2722 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 2723 if (msr) {
609e36d3 2724 msr_info->data = msr->data;
3bab1f5d 2725 break;
6aa8b732 2726 }
609e36d3 2727 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2728 }
2729
6aa8b732
AK		 2730 return 0;
2731}
2732
cae50139
JK		 2733static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2734
6aa8b732
AK		 2735/*
2736 * Writes msr value into into the appropriate "register".
2737 * Returns 0 on success, non-0 otherwise.
2738 * Assumes vcpu_load() was already called.
2739 */
8fe8ab46 2740static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2741{
a2fa3e9f 2742 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2743 struct shared_msr_entry *msr;
2cc51560 2744 int ret = 0;
8fe8ab46
WA		 2745 u32 msr_index = msr_info->index;
2746 u64 data = msr_info->data;
2cc51560 2747
6aa8b732 2748 switch (msr_index) {
3bab1f5d 2749 case MSR_EFER:
8fe8ab46 2750 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2751 break;
16175a79 2752#ifdef CONFIG_X86_64
6aa8b732 2753 case MSR_FS_BASE:
2fb92db1 2754 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2755 vmcs_writel(GUEST_FS_BASE, data);
2756 break;
2757 case MSR_GS_BASE:
2fb92db1 2758 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2759 vmcs_writel(GUEST_GS_BASE, data);
2760 break;
44ea2b17
AK		 2761 case MSR_KERNEL_GS_BASE:
2762 vmx_load_host_state(vmx);
2763 vmx->msr_guest_kernel_gs_base = data;
2764 break;
6aa8b732
AK		 2765#endif
2766 case MSR_IA32_SYSENTER_CS:
2767 vmcs_write32(GUEST_SYSENTER_CS, data);
2768 break;
2769 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2770 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2771 break;
2772 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2773 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2774 break;
0dd376e7 2775 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2776 if (!vmx_mpx_supported())
2777 return 1;
0dd376e7
LJ		 2778 vmcs_write64(GUEST_BNDCFGS, data);
2779 break;
af24a4e4 2780 case MSR_IA32_TSC:
8fe8ab46 2781 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2782 break;
468d472f
SY		 2783 case MSR_IA32_CR_PAT:
2784 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2785 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2786 return 1;
468d472f
SY		 2787 vmcs_write64(GUEST_IA32_PAT, data);
2788 vcpu->arch.pat = data;
2789 break;
2790 }
8fe8ab46 2791 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2792 break;
ba904635
WA		 2793 case MSR_IA32_TSC_ADJUST:
2794 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2795 break;
cae50139
JK		 2796 case MSR_IA32_FEATURE_CONTROL:
2797 if (!nested_vmx_allowed(vcpu) ||
2798 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2799 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2800 return 1;
2801 vmx->nested.msr_ia32_feature_control = data;
2802 if (msr_info->host_initiated && data == 0)
2803 vmx_leave_nested(vcpu);
2804 break;
2805 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2806 return 1; /* they are read-only */
20300099
WL		 2807 case MSR_IA32_XSS:
2808 if (!vmx_xsaves_supported())
2809 return 1;
2810 /*
2811 * The only supported bit as of Skylake is bit 8, but
2812 * it is not supported on KVM.
2813 */
2814 if (data != 0)
2815 return 1;
2816 vcpu->arch.ia32_xss = data;
2817 if (vcpu->arch.ia32_xss != host_xss)
2818 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2819 vcpu->arch.ia32_xss, host_xss);
2820 else
2821 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2822 break;
4e47c7a6 2823 case MSR_TSC_AUX:
1cea0ce6 2824 if (!guest_cpuid_has_rdtscp(vcpu))
4e47c7a6
SY		 2825 return 1;
2826 /* Check reserved bit, higher 32 bits should be zero */
2827 if ((data >> 32) != 0)
2828 return 1;
2829 /* Otherwise falls through */
6aa8b732 2830 default:
8b9cf98c 2831 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2832 if (msr) {
8b3c3104 2833 u64 old_msr_data = msr->data;
3bab1f5d 2834 msr->data = data;
2225fd56
AK		 2835 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2836 preempt_disable();
8b3c3104
AH		 2837 ret = kvm_set_shared_msr(msr->index, msr->data,
2838 msr->mask);
2225fd56 2839 preempt_enable();
8b3c3104
AH		 2840 if (ret)
2841 msr->data = old_msr_data;
2225fd56 2842 }
3bab1f5d 2843 break;
6aa8b732 2844 }
8fe8ab46 2845 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2846 }
2847
2cc51560 2848 return ret;
6aa8b732
AK		 2849}
2850
5fdbf976 2851static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2852{
5fdbf976
MT		 2853 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2854 switch (reg) {
2855 case VCPU_REGS_RSP:
2856 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2857 break;
2858 case VCPU_REGS_RIP:
2859 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2860 break;
6de4f3ad
AK		 2861 case VCPU_EXREG_PDPTR:
2862 if (enable_ept)
2863 ept_save_pdptrs(vcpu);
2864 break;
5fdbf976
MT		 2865 default:
2866 break;
2867 }
6aa8b732
AK		 2868}
2869
6aa8b732
AK		 2870static __init int cpu_has_kvm_support(void)
2871{
6210e37b 2872 return cpu_has_vmx();
6aa8b732
AK		 2873}
2874
2875static __init int vmx_disabled_by_bios(void)
2876{
2877 u64 msr;
2878
2879 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2880 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2881 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2882 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2883 && tboot_enabled())
2884 return 1;
23f3e991 2885 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2886 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2887 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2888 && !tboot_enabled()) {
2889 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2890 "activate TXT before enabling KVM\n");
cafd6659 2891 return 1;
f9335afe 2892 }
23f3e991
JC		 2893 /* launched w/o TXT and VMX disabled */
2894 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2895 && !tboot_enabled())
2896 return 1;
cafd6659
SW		 2897 }
2898
2899 return 0;
6aa8b732
AK		 2900}
2901
7725b894
DX		 2902static void kvm_cpu_vmxon(u64 addr)
2903{
2904 asm volatile (ASM_VMX_VMXON_RAX
2905 : : "a"(&addr), "m"(addr)
2906 : "memory", "cc");
2907}
2908
13a34e06 2909static int hardware_enable(void)
6aa8b732
AK		 2910{
2911 int cpu = raw_smp_processor_id();
2912 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2913 u64 old, test_bits;
6aa8b732 2914
1e02ce4c 2915 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2916 return -EBUSY;
2917
d462b819 2918 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2919
2920 /*
2921 * Now we can enable the vmclear operation in kdump
2922 * since the loaded_vmcss_on_cpu list on this cpu
2923 * has been initialized.
2924 *
2925 * Though the cpu is not in VMX operation now, there
2926 * is no problem to enable the vmclear operation
2927 * for the loaded_vmcss_on_cpu list is empty!
2928 */
2929 crash_enable_local_vmclear(cpu);
2930
6aa8b732 2931 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2932
2933 test_bits = FEATURE_CONTROL_LOCKED;
2934 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2935 if (tboot_enabled())
2936 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2937
2938 if ((old & test_bits) != test_bits) {
6aa8b732 2939 /* enable and lock */
cafd6659
SW		 2940 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2941 }
375074cc 2942 cr4_set_bits(X86_CR4_VMXE);
10474ae8 2943
4610c9cc
DX		 2944 if (vmm_exclusive) {
2945 kvm_cpu_vmxon(phys_addr);
2946 ept_sync_global();
2947 }
10474ae8 2948
89cbc767 2949 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2950
10474ae8 2951 return 0;
6aa8b732
AK		 2952}
2953
d462b819 2954static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2955{
2956 int cpu = raw_smp_processor_id();
d462b819 2957 struct loaded_vmcs *v, *n;
543e4243 2958
d462b819
NHE		 2959 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2960 loaded_vmcss_on_cpu_link)
2961 __loaded_vmcs_clear(v);
543e4243
AK		 2962}
2963
710ff4a8
EH		 2964
2965/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2966 * tricks.
2967 */
2968static void kvm_cpu_vmxoff(void)
6aa8b732 2969{
4ecac3fd 2970 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2971}
2972
13a34e06 2973static void hardware_disable(void)
710ff4a8 2974{
4610c9cc 2975 if (vmm_exclusive) {
d462b819 2976 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2977 kvm_cpu_vmxoff();
2978 }
375074cc 2979 cr4_clear_bits(X86_CR4_VMXE);
710ff4a8
EH		 2980}
2981
1c3d14fe 2982static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2983 u32 msr, u32 *result)
1c3d14fe
YS		 2984{
2985 u32 vmx_msr_low, vmx_msr_high;
2986 u32 ctl = ctl_min | ctl_opt;
2987
2988 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2989
2990 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2991 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2992
2993 /* Ensure minimum (required) set of control bits are supported. */
2994 if (ctl_min & ~ctl)
002c7f7c 2995 return -EIO;
1c3d14fe
YS		 2996
2997 *result = ctl;
2998 return 0;
2999}
3000
110312c8
AK		 3001static __init bool allow_1_setting(u32 msr, u32 ctl)
3002{
3003 u32 vmx_msr_low, vmx_msr_high;
3004
3005 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3006 return vmx_msr_high & ctl;
3007}
3008
002c7f7c 3009static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 3010{
3011 u32 vmx_msr_low, vmx_msr_high;
d56f546d 3012 u32 min, opt, min2, opt2;
1c3d14fe
YS		 3013 u32 _pin_based_exec_control = 0;
3014 u32 _cpu_based_exec_control = 0;
f78e0e2e 3015 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 3016 u32 _vmexit_control = 0;
3017 u32 _vmentry_control = 0;
3018
10166744 3019 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 3020#ifdef CONFIG_X86_64
3021 CPU_BASED_CR8_LOAD_EXITING |
3022 CPU_BASED_CR8_STORE_EXITING |
3023#endif
d56f546d
SY		 3024 CPU_BASED_CR3_LOAD_EXITING |
3025 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 3026 CPU_BASED_USE_IO_BITMAPS |
3027 CPU_BASED_MOV_DR_EXITING |
a7052897 3028 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 3029 CPU_BASED_MWAIT_EXITING |
3030 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 3031 CPU_BASED_INVLPG_EXITING |
3032 CPU_BASED_RDPMC_EXITING;
443381a8 3033
f78e0e2e 3034 opt = CPU_BASED_TPR_SHADOW |
25c5f225 3035 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 3036 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 3037 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3038 &_cpu_based_exec_control) < 0)
002c7f7c 3039 return -EIO;
6e5d865c
YS		 3040#ifdef CONFIG_X86_64
3041 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3042 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3043 ~CPU_BASED_CR8_STORE_EXITING;
3044#endif
f78e0e2e 3045 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 3046 min2 = 0;
3047 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3048 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3049 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3050 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3051 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3052 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3053 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3054 SECONDARY_EXEC_RDTSCP |
83d4c286 3055 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3056 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3057 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3058 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 3059 SECONDARY_EXEC_XSAVES |
8b3e34e4
XG		 3060 SECONDARY_EXEC_ENABLE_PML |
3061 SECONDARY_EXEC_PCOMMIT;
d56f546d
SY		 3062 if (adjust_vmx_controls(min2, opt2,
3063 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3064 &_cpu_based_2nd_exec_control) < 0)
3065 return -EIO;
3066 }
3067#ifndef CONFIG_X86_64
3068 if (!(_cpu_based_2nd_exec_control &
3069 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3070 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3071#endif
83d4c286
YZ		 3072
3073 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3074 _cpu_based_2nd_exec_control &= ~(
8d14695f 3075 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3076 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3077 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3078
d56f546d 3079 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3080 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3081 enabled */
5fff7d27
GN		 3082 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3083 CPU_BASED_CR3_STORE_EXITING |
3084 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3085 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3086 vmx_capability.ept, vmx_capability.vpid);
3087 }
1c3d14fe 3088
81908bf4 3089 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3090#ifdef CONFIG_X86_64
3091 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3092#endif
a547c6db 3093 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3094 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3095 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3096 &_vmexit_control) < 0)
002c7f7c 3097 return -EIO;
1c3d14fe 3098
01e439be
YZ		 3099 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3100 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3101 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3102 &_pin_based_exec_control) < 0)
3103 return -EIO;
3104
3105 if (!(_cpu_based_2nd_exec_control &
3106 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3107 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3108 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3109
c845f9c6 3110 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3111 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3112 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3113 &_vmentry_control) < 0)
002c7f7c 3114 return -EIO;
6aa8b732 3115
c68876fd 3116 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3117
3118 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3119 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3120 return -EIO;
1c3d14fe
YS		 3121
3122#ifdef CONFIG_X86_64
3123 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3124 if (vmx_msr_high & (1u<<16))
002c7f7c 3125 return -EIO;
1c3d14fe
YS		 3126#endif
3127
3128 /* Require Write-Back (WB) memory type for VMCS accesses. */
3129 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3130 return -EIO;
1c3d14fe 3131
002c7f7c
YS		 3132 vmcs_conf->size = vmx_msr_high & 0x1fff;
3133 vmcs_conf->order = get_order(vmcs_config.size);
3134 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3135
002c7f7c
YS		 3136 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3137 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3138 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3139 vmcs_conf->vmexit_ctrl = _vmexit_control;
3140 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3141
110312c8
AK		 3142 cpu_has_load_ia32_efer =
3143 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3144 VM_ENTRY_LOAD_IA32_EFER)
3145 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3146 VM_EXIT_LOAD_IA32_EFER);
3147
8bf00a52
GN		 3148 cpu_has_load_perf_global_ctrl =
3149 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3150 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3151 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3152 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3153
3154 /*
3155 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3156 * but due to arrata below it can't be used. Workaround is to use
3157 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3158 *
3159 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3160 *
3161 * AAK155 (model 26)
3162 * AAP115 (model 30)
3163 * AAT100 (model 37)
3164 * BC86,AAY89,BD102 (model 44)
3165 * BA97 (model 46)
3166 *
3167 */
3168 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3169 switch (boot_cpu_data.x86_model) {
3170 case 26:
3171 case 30:
3172 case 37:
3173 case 44:
3174 case 46:
3175 cpu_has_load_perf_global_ctrl = false;
3176 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3177 "does not work properly. Using workaround\n");
3178 break;
3179 default:
3180 break;
3181 }
3182 }
3183
20300099
WL		 3184 if (cpu_has_xsaves)
3185 rdmsrl(MSR_IA32_XSS, host_xss);
3186
1c3d14fe 3187 return 0;
c68876fd 3188}
6aa8b732
AK		 3189
3190static struct vmcs *alloc_vmcs_cpu(int cpu)
3191{
3192 int node = cpu_to_node(cpu);
3193 struct page *pages;
3194 struct vmcs *vmcs;
3195
96db800f 3196 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3197 if (!pages)
3198 return NULL;
3199 vmcs = page_address(pages);
1c3d14fe
YS		 3200 memset(vmcs, 0, vmcs_config.size);
3201 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3202 return vmcs;
3203}
3204
3205static struct vmcs *alloc_vmcs(void)
3206{
d3b2c338 3207 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3208}
3209
3210static void free_vmcs(struct vmcs *vmcs)
3211{
1c3d14fe 3212 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3213}
3214
d462b819
NHE		 3215/*
3216 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3217 */
3218static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3219{
3220 if (!loaded_vmcs->vmcs)
3221 return;
3222 loaded_vmcs_clear(loaded_vmcs);
3223 free_vmcs(loaded_vmcs->vmcs);
3224 loaded_vmcs->vmcs = NULL;
3225}
3226
39959588 3227static void free_kvm_area(void)
6aa8b732
AK		 3228{
3229 int cpu;
3230
3230bb47 3231 for_each_possible_cpu(cpu) {
6aa8b732 3232 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3233 per_cpu(vmxarea, cpu) = NULL;
3234 }
6aa8b732
AK		 3235}
3236
fe2b201b
BD		 3237static void init_vmcs_shadow_fields(void)
3238{
3239 int i, j;
3240
3241 /* No checks for read only fields yet */
3242
3243 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3244 switch (shadow_read_write_fields[i]) {
3245 case GUEST_BNDCFGS:
3246 if (!vmx_mpx_supported())
3247 continue;
3248 break;
3249 default:
3250 break;
3251 }
3252
3253 if (j < i)
3254 shadow_read_write_fields[j] =
3255 shadow_read_write_fields[i];
3256 j++;
3257 }
3258 max_shadow_read_write_fields = j;
3259
3260 /* shadowed fields guest access without vmexit */
3261 for (i = 0; i < max_shadow_read_write_fields; i++) {
3262 clear_bit(shadow_read_write_fields[i],
3263 vmx_vmwrite_bitmap);
3264 clear_bit(shadow_read_write_fields[i],
3265 vmx_vmread_bitmap);
3266 }
3267 for (i = 0; i < max_shadow_read_only_fields; i++)
3268 clear_bit(shadow_read_only_fields[i],
3269 vmx_vmread_bitmap);
3270}
3271
6aa8b732
AK		 3272static __init int alloc_kvm_area(void)
3273{
3274 int cpu;
3275
3230bb47 3276 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3277 struct vmcs *vmcs;
3278
3279 vmcs = alloc_vmcs_cpu(cpu);
3280 if (!vmcs) {
3281 free_kvm_area();
3282 return -ENOMEM;
3283 }
3284
3285 per_cpu(vmxarea, cpu) = vmcs;
3286 }
3287 return 0;
3288}
3289
14168786
GN		 3290static bool emulation_required(struct kvm_vcpu *vcpu)
3291{
3292 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3293}
3294
91b0aa2c 3295static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3296 struct kvm_segment *save)
6aa8b732 3297{
d99e4152
GN		 3298 if (!emulate_invalid_guest_state) {
3299 /*
3300 * CS and SS RPL should be equal during guest entry according
3301 * to VMX spec, but in reality it is not always so. Since vcpu
3302 * is in the middle of the transition from real mode to
3303 * protected mode it is safe to assume that RPL 0 is a good
3304 * default value.
3305 */
3306 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 3307 save->selector &= ~SEGMENT_RPL_MASK;
3308 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3309 save->s = 1;
6aa8b732 3310 }
d99e4152 3311 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3312}
3313
3314static void enter_pmode(struct kvm_vcpu *vcpu)
3315{
3316 unsigned long flags;
a89a8fb9 3317 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3318
d99e4152
GN		 3319 /*
3320 * Update real mode segment cache. It may be not up-to-date if sement
3321 * register was written while vcpu was in a guest mode.
3322 */
3323 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3324 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3325 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3326 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3327 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3328 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3329
7ffd92c5 3330 vmx->rmode.vm86_active = 0;
6aa8b732 3331
2fb92db1
AK		 3332 vmx_segment_cache_clear(vmx);
3333
f5f7b2fe 3334 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3335
3336 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3337 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3338 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3339 vmcs_writel(GUEST_RFLAGS, flags);
3340
66aee91a
RR		 3341 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3342 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3343
3344 update_exception_bitmap(vcpu);
3345
91b0aa2c
GN		 3346 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3347 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3348 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3349 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3350 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3351 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3352}
3353
f5f7b2fe 3354static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3355{
772e0318 3356 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3357 struct kvm_segment var = *save;
3358
3359 var.dpl = 0x3;
3360 if (seg == VCPU_SREG_CS)
3361 var.type = 0x3;
3362
3363 if (!emulate_invalid_guest_state) {
3364 var.selector = var.base >> 4;
3365 var.base = var.base & 0xffff0;
3366 var.limit = 0xffff;
3367 var.g = 0;
3368 var.db = 0;
3369 var.present = 1;
3370 var.s = 1;
3371 var.l = 0;
3372 var.unusable = 0;
3373 var.type = 0x3;
3374 var.avl = 0;
3375 if (save->base & 0xf)
3376 printk_once(KERN_WARNING "kvm: segment base is not "
3377 "paragraph aligned when entering "
3378 "protected mode (seg=%d)", seg);
3379 }
6aa8b732 3380
d99e4152
GN		 3381 vmcs_write16(sf->selector, var.selector);
3382 vmcs_write32(sf->base, var.base);
3383 vmcs_write32(sf->limit, var.limit);
3384 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3385}
3386
3387static void enter_rmode(struct kvm_vcpu *vcpu)
3388{
3389 unsigned long flags;
a89a8fb9 3390 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3391
f5f7b2fe
AK		 3392 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3393 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3394 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3395 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3396 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3397 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3398 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3399
7ffd92c5 3400 vmx->rmode.vm86_active = 1;
6aa8b732 3401
776e58ea
GN		 3402 /*
3403 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3404 * vcpu. Warn the user that an update is overdue.
776e58ea 3405 */
4918c6ca 3406 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3407 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3408 "called before entering vcpu\n");
776e58ea 3409
2fb92db1
AK		 3410 vmx_segment_cache_clear(vmx);
3411
4918c6ca 3412 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3413 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3414 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3415
3416 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3417 vmx->rmode.save_rflags = flags;
6aa8b732 3418
053de044 3419 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3420
3421 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3422 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3423 update_exception_bitmap(vcpu);
3424
d99e4152
GN		 3425 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3426 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3427 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3428 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3429 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3430 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3431
8668a3c4 3432 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3433}
3434
401d10de
AS		 3435static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3436{
3437 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3438 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3439
3440 if (!msr)
3441 return;
401d10de 3442
44ea2b17
AK		 3443 /*
3444 * Force kernel_gs_base reloading before EFER changes, as control
3445 * of this msr depends on is_long_mode().
3446 */
3447 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3448 vcpu->arch.efer = efer;
401d10de 3449 if (efer & EFER_LMA) {
2961e876 3450 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3451 msr->data = efer;
3452 } else {
2961e876 3453 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3454
3455 msr->data = efer & ~EFER_LME;
3456 }
3457 setup_msrs(vmx);
3458}
3459
05b3e0c2 3460#ifdef CONFIG_X86_64
6aa8b732
AK		 3461
3462static void enter_lmode(struct kvm_vcpu *vcpu)
3463{
3464 u32 guest_tr_ar;
3465
2fb92db1
AK		 3466 vmx_segment_cache_clear(to_vmx(vcpu));
3467
6aa8b732 3468 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 3469 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3470 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3471 __func__);
6aa8b732 3472 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 3473 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3474 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 3475 }
da38f438 3476 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3477}
3478
3479static void exit_lmode(struct kvm_vcpu *vcpu)
3480{
2961e876 3481 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3482 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3483}
3484
3485#endif
3486
2384d2b3
SY		 3487static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3488{
b9d762fa 3489 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3490 if (enable_ept) {
3491 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3492 return;
4e1096d2 3493 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3494 }
2384d2b3
SY		 3495}
3496
e8467fda
AK		 3497static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3498{
3499 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3500
3501 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3502 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3503}
3504
aff48baa
AK		 3505static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3506{
3507 if (enable_ept && is_paging(vcpu))
3508 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3509 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3510}
3511
25c4c276 3512static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3513{
fc78f519
AK		 3514 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3515
3516 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3517 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3518}
3519
1439442c
SY		 3520static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3521{
d0d538b9
GN		 3522 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3523
6de4f3ad
AK		 3524 if (!test_bit(VCPU_EXREG_PDPTR,
3525 (unsigned long *)&vcpu->arch.regs_dirty))
3526 return;
3527
1439442c 3528 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3529 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3530 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3531 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3532 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3533 }
3534}
3535
8f5d549f
AK		 3536static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3537{
d0d538b9
GN		 3538 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3539
8f5d549f 3540 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3541 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3542 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3543 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3544 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3545 }
6de4f3ad
AK		 3546
3547 __set_bit(VCPU_EXREG_PDPTR,
3548 (unsigned long *)&vcpu->arch.regs_avail);
3549 __set_bit(VCPU_EXREG_PDPTR,
3550 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3551}
3552
5e1746d6 3553static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3554
3555static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3556 unsigned long cr0,
3557 struct kvm_vcpu *vcpu)
3558{
5233dd51
MT		 3559 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3560 vmx_decache_cr3(vcpu);
1439442c
SY		 3561 if (!(cr0 & X86_CR0_PG)) {
3562 /* From paging/starting to nonpaging */
3563 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3564 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3565 (CPU_BASED_CR3_LOAD_EXITING |
3566 CPU_BASED_CR3_STORE_EXITING));
3567 vcpu->arch.cr0 = cr0;
fc78f519 3568 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3569 } else if (!is_paging(vcpu)) {
3570 /* From nonpaging to paging */
3571 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3572 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3573 ~(CPU_BASED_CR3_LOAD_EXITING |
3574 CPU_BASED_CR3_STORE_EXITING));
3575 vcpu->arch.cr0 = cr0;
fc78f519 3576 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3577 }
95eb84a7
SY		 3578
3579 if (!(cr0 & X86_CR0_WP))
3580 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3581}
3582
6aa8b732
AK		 3583static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3584{
7ffd92c5 3585 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3586 unsigned long hw_cr0;
3587
5037878e 3588 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3589 if (enable_unrestricted_guest)
5037878e 3590 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3591 else {
5037878e 3592 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3593
218e763f
GN		 3594 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3595 enter_pmode(vcpu);
6aa8b732 3596
218e763f
GN		 3597 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3598 enter_rmode(vcpu);
3599 }
6aa8b732 3600
05b3e0c2 3601#ifdef CONFIG_X86_64
f6801dff 3602 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3604 enter_lmode(vcpu);
707d92fa 3605 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3606 exit_lmode(vcpu);
3607 }
3608#endif
3609
089d034e 3610 if (enable_ept)
1439442c
SY		 3611 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3612
02daab21 3613 if (!vcpu->fpu_active)
81231c69 3614 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3615
6aa8b732 3616 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3617 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3618 vcpu->arch.cr0 = cr0;
14168786
GN		 3619
3620 /* depends on vcpu->arch.cr0 to be set to a new value */
3621 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3622}
3623
1439442c
SY		 3624static u64 construct_eptp(unsigned long root_hpa)
3625{
3626 u64 eptp;
3627
3628 /* TODO write the value reading from MSR */
3629 eptp = VMX_EPT_DEFAULT_MT |
3630 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3631 if (enable_ept_ad_bits)
3632 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3633 eptp |= (root_hpa & PAGE_MASK);
3634
3635 return eptp;
3636}
3637
6aa8b732
AK		 3638static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3639{
1439442c
SY		 3640 unsigned long guest_cr3;
3641 u64 eptp;
3642
3643 guest_cr3 = cr3;
089d034e 3644 if (enable_ept) {
1439442c
SY		 3645 eptp = construct_eptp(cr3);
3646 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3647 if (is_paging(vcpu) || is_guest_mode(vcpu))
3648 guest_cr3 = kvm_read_cr3(vcpu);
3649 else
3650 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3651 ept_load_pdptrs(vcpu);
1439442c
SY		 3652 }
3653
2384d2b3 3654 vmx_flush_tlb(vcpu);
1439442c 3655 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3656}
3657
5e1746d6 3658static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3659{
085e68ee
BS		 3660 /*
3661 * Pass through host's Machine Check Enable value to hw_cr4, which
3662 * is in force while we are in guest mode. Do not let guests control
3663 * this bit, even if host CR4.MCE == 0.
3664 */
3665 unsigned long hw_cr4 =
3666 (cr4_read_shadow() & X86_CR4_MCE) |
3667 (cr4 & ~X86_CR4_MCE) |
3668 (to_vmx(vcpu)->rmode.vm86_active ?
3669 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 3670
5e1746d6
NHE		 3671 if (cr4 & X86_CR4_VMXE) {
3672 /*
3673 * To use VMXON (and later other VMX instructions), a guest
3674 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3675 * So basically the check on whether to allow nested VMX
3676 * is here.
3677 */
3678 if (!nested_vmx_allowed(vcpu))
3679 return 1;
1a0d74e6
JK		 3680 }
3681 if (to_vmx(vcpu)->nested.vmxon &&
3682 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3683 return 1;
3684
ad312c7c 3685 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3686 if (enable_ept) {
3687 if (!is_paging(vcpu)) {
3688 hw_cr4 &= ~X86_CR4_PAE;
3689 hw_cr4 |= X86_CR4_PSE;
c08800a5 3690 /*
e1e746b3
FW		 3691 * SMEP/SMAP is disabled if CPU is in non-paging mode
3692 * in hardware. However KVM always uses paging mode to
c08800a5 3693 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3694 * To emulate this behavior, SMEP/SMAP needs to be
3695 * manually disabled when guest switches to non-paging
3696 * mode.
c08800a5 3697 */
e1e746b3 3698 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3699 } else if (!(cr4 & X86_CR4_PAE)) {
3700 hw_cr4 &= ~X86_CR4_PAE;
3701 }
3702 }
1439442c
SY		 3703
3704 vmcs_writel(CR4_READ_SHADOW, cr4);
3705 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3706 return 0;
6aa8b732
AK		 3707}
3708
6aa8b732
AK		 3709static void vmx_get_segment(struct kvm_vcpu *vcpu,
3710 struct kvm_segment *var, int seg)
3711{
a9179499 3712 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3713 u32 ar;
3714
c6ad1153 3715 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3716 *var = vmx->rmode.segs[seg];
a9179499 3717 if (seg == VCPU_SREG_TR
2fb92db1 3718 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3719 return;
1390a28b
AK		 3720 var->base = vmx_read_guest_seg_base(vmx, seg);
3721 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3722 return;
a9179499 3723 }
2fb92db1
AK		 3724 var->base = vmx_read_guest_seg_base(vmx, seg);
3725 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3726 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3727 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3728 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3729 var->type = ar & 15;
3730 var->s = (ar >> 4) & 1;
3731 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3732 /*
3733 * Some userspaces do not preserve unusable property. Since usable
3734 * segment has to be present according to VMX spec we can use present
3735 * property to amend userspace bug by making unusable segment always
3736 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3737 * segment as unusable.
3738 */
3739 var->present = !var->unusable;
6aa8b732
AK		 3740 var->avl = (ar >> 12) & 1;
3741 var->l = (ar >> 13) & 1;
3742 var->db = (ar >> 14) & 1;
3743 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3744}
3745
a9179499
AK		 3746static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3747{
a9179499
AK		 3748 struct kvm_segment s;
3749
3750 if (to_vmx(vcpu)->rmode.vm86_active) {
3751 vmx_get_segment(vcpu, &s, seg);
3752 return s.base;
3753 }
2fb92db1 3754 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3755}
3756
b09408d0 3757static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3758{
b09408d0
MT		 3759 struct vcpu_vmx *vmx = to_vmx(vcpu);
3760
ae9fedc7 3761 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3762 return 0;
ae9fedc7
PB		 3763 else {
3764 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3765 return VMX_AR_DPL(ar);
69c73028 3766 }
69c73028
AK		 3767}
3768
653e3108 3769static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3770{
6aa8b732
AK		 3771 u32 ar;
3772
f0495f9b 3773 if (var->unusable || !var->present)
6aa8b732
AK		 3774 ar = 1 << 16;
3775 else {
3776 ar = var->type & 15;
3777 ar |= (var->s & 1) << 4;
3778 ar |= (var->dpl & 3) << 5;
3779 ar |= (var->present & 1) << 7;
3780 ar |= (var->avl & 1) << 12;
3781 ar |= (var->l & 1) << 13;
3782 ar |= (var->db & 1) << 14;
3783 ar |= (var->g & 1) << 15;
3784 }
653e3108
AK		 3785
3786 return ar;
3787}
3788
3789static void vmx_set_segment(struct kvm_vcpu *vcpu,
3790 struct kvm_segment *var, int seg)
3791{
7ffd92c5 3792 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3793 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3794
2fb92db1
AK		 3795 vmx_segment_cache_clear(vmx);
3796
1ecd50a9
GN		 3797 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3798 vmx->rmode.segs[seg] = *var;
3799 if (seg == VCPU_SREG_TR)
3800 vmcs_write16(sf->selector, var->selector);
3801 else if (var->s)
3802 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3803 goto out;
653e3108 3804 }
1ecd50a9 3805
653e3108
AK		 3806 vmcs_writel(sf->base, var->base);
3807 vmcs_write32(sf->limit, var->limit);
3808 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3809
3810 /*
3811 * Fix the "Accessed" bit in AR field of segment registers for older
3812 * qemu binaries.
3813 * IA32 arch specifies that at the time of processor reset the
3814 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3815 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3816 * state vmexit when "unrestricted guest" mode is turned on.
3817 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3818 * tree. Newer qemu binaries with that qemu fix would not need this
3819 * kvm hack.
3820 */
3821 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3822 var->type |= 0x1; /* Accessed */
3a624e29 3823
f924d66d 3824 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3825
3826out:
98eb2f8b 3827 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3828}
3829
6aa8b732
AK		 3830static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3831{
2fb92db1 3832 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3833
3834 *db = (ar >> 14) & 1;
3835 *l = (ar >> 13) & 1;
3836}
3837
89a27f4d 3838static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3839{
89a27f4d
GN		 3840 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3841 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3842}
3843
89a27f4d 3844static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3845{
89a27f4d
GN		 3846 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3847 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3848}
3849
89a27f4d 3850static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3851{
89a27f4d
GN		 3852 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3853 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3854}
3855
89a27f4d 3856static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3857{
89a27f4d
GN		 3858 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3859 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3860}
3861
648dfaa7
MG		 3862static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3863{
3864 struct kvm_segment var;
3865 u32 ar;
3866
3867 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3868 var.dpl = 0x3;
0647f4aa
GN		 3869 if (seg == VCPU_SREG_CS)
3870 var.type = 0x3;
648dfaa7
MG		 3871 ar = vmx_segment_access_rights(&var);
3872
3873 if (var.base != (var.selector << 4))
3874 return false;
89efbed0 3875 if (var.limit != 0xffff)
648dfaa7 3876 return false;
07f42f5f 3877 if (ar != 0xf3)
648dfaa7
MG		 3878 return false;
3879
3880 return true;
3881}
3882
3883static bool code_segment_valid(struct kvm_vcpu *vcpu)
3884{
3885 struct kvm_segment cs;
3886 unsigned int cs_rpl;
3887
3888 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3889 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3890
1872a3f4
AK		 3891 if (cs.unusable)
3892 return false;
4d283ec9 3893 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3894 return false;
3895 if (!cs.s)
3896 return false;
4d283ec9 3897 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3898 if (cs.dpl > cs_rpl)
3899 return false;
1872a3f4 3900 } else {
648dfaa7
MG		 3901 if (cs.dpl != cs_rpl)
3902 return false;
3903 }
3904 if (!cs.present)
3905 return false;
3906
3907 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3908 return true;
3909}
3910
3911static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3912{
3913 struct kvm_segment ss;
3914 unsigned int ss_rpl;
3915
3916 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3917 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3918
1872a3f4
AK		 3919 if (ss.unusable)
3920 return true;
3921 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3922 return false;
3923 if (!ss.s)
3924 return false;
3925 if (ss.dpl != ss_rpl) /* DPL != RPL */
3926 return false;
3927 if (!ss.present)
3928 return false;
3929
3930 return true;
3931}
3932
3933static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3934{
3935 struct kvm_segment var;
3936 unsigned int rpl;
3937
3938 vmx_get_segment(vcpu, &var, seg);
b32a9918 3939 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3940
1872a3f4
AK		 3941 if (var.unusable)
3942 return true;
648dfaa7
MG		 3943 if (!var.s)
3944 return false;
3945 if (!var.present)
3946 return false;
4d283ec9 3947 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3948 if (var.dpl < rpl) /* DPL < RPL */
3949 return false;
3950 }
3951
3952 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3953 * rights flags
3954 */
3955 return true;
3956}
3957
3958static bool tr_valid(struct kvm_vcpu *vcpu)
3959{
3960 struct kvm_segment tr;
3961
3962 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3963
1872a3f4
AK		 3964 if (tr.unusable)
3965 return false;
b32a9918 3966 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3967 return false;
1872a3f4 3968 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3969 return false;
3970 if (!tr.present)
3971 return false;
3972
3973 return true;
3974}
3975
3976static bool ldtr_valid(struct kvm_vcpu *vcpu)
3977{
3978 struct kvm_segment ldtr;
3979
3980 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3981
1872a3f4
AK		 3982 if (ldtr.unusable)
3983 return true;
b32a9918 3984 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3985 return false;
3986 if (ldtr.type != 2)
3987 return false;
3988 if (!ldtr.present)
3989 return false;
3990
3991 return true;
3992}
3993
3994static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3995{
3996 struct kvm_segment cs, ss;
3997
3998 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3999 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4000
b32a9918
NA		 4001 return ((cs.selector & SEGMENT_RPL_MASK) ==
4002 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 4003}
4004
4005/*
4006 * Check if guest state is valid. Returns true if valid, false if
4007 * not.
4008 * We assume that registers are always usable
4009 */
4010static bool guest_state_valid(struct kvm_vcpu *vcpu)
4011{
c5e97c80
GN		 4012 if (enable_unrestricted_guest)
4013 return true;
4014
648dfaa7 4015 /* real mode guest state checks */
f13882d8 4016 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 4017 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4018 return false;
4019 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4020 return false;
4021 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4022 return false;
4023 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4024 return false;
4025 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4026 return false;
4027 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4028 return false;
4029 } else {
4030 /* protected mode guest state checks */
4031 if (!cs_ss_rpl_check(vcpu))
4032 return false;
4033 if (!code_segment_valid(vcpu))
4034 return false;
4035 if (!stack_segment_valid(vcpu))
4036 return false;
4037 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4038 return false;
4039 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4040 return false;
4041 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4042 return false;
4043 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4044 return false;
4045 if (!tr_valid(vcpu))
4046 return false;
4047 if (!ldtr_valid(vcpu))
4048 return false;
4049 }
4050 /* TODO:
4051 * - Add checks on RIP
4052 * - Add checks on RFLAGS
4053 */
4054
4055 return true;
4056}
4057
d77c26fc 4058static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4059{
40dcaa9f 4060 gfn_t fn;
195aefde 4061 u16 data = 0;
1f755a82 4062 int idx, r;
6aa8b732 4063
40dcaa9f 4064 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4065 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 4066 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4067 if (r < 0)
10589a46 4068 goto out;
195aefde 4069 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4070 r = kvm_write_guest_page(kvm, fn++, &data,
4071 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4072 if (r < 0)
10589a46 4073 goto out;
195aefde
IE		 4074 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4075 if (r < 0)
10589a46 4076 goto out;
195aefde
IE		 4077 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4078 if (r < 0)
10589a46 4079 goto out;
195aefde 4080 data = ~0;
10589a46
MT		 4081 r = kvm_write_guest_page(kvm, fn, &data,
4082 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4083 sizeof(u8));
10589a46 4084out:
40dcaa9f 4085 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4086 return r;
6aa8b732
AK		 4087}
4088
b7ebfb05
SY		 4089static int init_rmode_identity_map(struct kvm *kvm)
4090{
f51770ed 4091 int i, idx, r = 0;
b7ebfb05
SY		 4092 pfn_t identity_map_pfn;
4093 u32 tmp;
4094
089d034e 4095 if (!enable_ept)
f51770ed 4096 return 0;
a255d479
TC		 4097
4098 /* Protect kvm->arch.ept_identity_pagetable_done. */
4099 mutex_lock(&kvm->slots_lock);
4100
f51770ed 4101 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4102 goto out2;
a255d479 4103
b927a3ce 4104 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4105
4106 r = alloc_identity_pagetable(kvm);
f51770ed 4107 if (r < 0)
a255d479
TC		 4108 goto out2;
4109
40dcaa9f 4110 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4111 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4112 if (r < 0)
4113 goto out;
4114 /* Set up identity-mapping pagetable for EPT in real mode */
4115 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4116 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4117 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4118 r = kvm_write_guest_page(kvm, identity_map_pfn,
4119 &tmp, i * sizeof(tmp), sizeof(tmp));
4120 if (r < 0)
4121 goto out;
4122 }
4123 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4124
b7ebfb05 4125out:
40dcaa9f 4126 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4127
4128out2:
4129 mutex_unlock(&kvm->slots_lock);
f51770ed 4130 return r;
b7ebfb05
SY		 4131}
4132
6aa8b732
AK		 4133static void seg_setup(int seg)
4134{
772e0318 4135 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4136 unsigned int ar;
6aa8b732
AK		 4137
4138 vmcs_write16(sf->selector, 0);
4139 vmcs_writel(sf->base, 0);
4140 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4141 ar = 0x93;
4142 if (seg == VCPU_SREG_CS)
4143 ar |= 0x08; /* code segment */
3a624e29
NK		 4144
4145 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4146}
4147
f78e0e2e
SY		 4148static int alloc_apic_access_page(struct kvm *kvm)
4149{
4484141a 4150 struct page *page;
f78e0e2e
SY		 4151 struct kvm_userspace_memory_region kvm_userspace_mem;
4152 int r = 0;
4153
79fac95e 4154 mutex_lock(&kvm->slots_lock);
c24ae0dc 4155 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4156 goto out;
4157 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4158 kvm_userspace_mem.flags = 0;
73a6d941 4159 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4160 kvm_userspace_mem.memory_size = PAGE_SIZE;
9da0e4d5 4161 r = __x86_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4162 if (r)
4163 goto out;
72dc67a6 4164
73a6d941 4165 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4166 if (is_error_page(page)) {
4167 r = -EFAULT;
4168 goto out;
4169 }
4170
c24ae0dc
TC		 4171 /*
4172 * Do not pin the page in memory, so that memory hot-unplug
4173 * is able to migrate it.
4174 */
4175 put_page(page);
4176 kvm->arch.apic_access_page_done = true;
f78e0e2e 4177out:
79fac95e 4178 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4179 return r;
4180}
4181
b7ebfb05
SY		 4182static int alloc_identity_pagetable(struct kvm *kvm)
4183{
a255d479
TC		 4184 /* Called with kvm->slots_lock held. */
4185
b7ebfb05
SY		 4186 struct kvm_userspace_memory_region kvm_userspace_mem;
4187 int r = 0;
4188
a255d479
TC		 4189 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4190
b7ebfb05
SY		 4191 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4192 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4193 kvm_userspace_mem.guest_phys_addr =
4194 kvm->arch.ept_identity_map_addr;
b7ebfb05 4195 kvm_userspace_mem.memory_size = PAGE_SIZE;
9da0e4d5 4196 r = __x86_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4197
b7ebfb05
SY		 4198 return r;
4199}
4200
2384d2b3
SY		 4201static void allocate_vpid(struct vcpu_vmx *vmx)
4202{
4203 int vpid;
4204
4205 vmx->vpid = 0;
919818ab 4206 if (!enable_vpid)
2384d2b3
SY		 4207 return;
4208 spin_lock(&vmx_vpid_lock);
4209 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4210 if (vpid < VMX_NR_VPIDS) {
4211 vmx->vpid = vpid;
4212 __set_bit(vpid, vmx_vpid_bitmap);
4213 }
4214 spin_unlock(&vmx_vpid_lock);
4215}
4216
cdbecfc3
LJ		 4217static void free_vpid(struct vcpu_vmx *vmx)
4218{
4219 if (!enable_vpid)
4220 return;
4221 spin_lock(&vmx_vpid_lock);
4222 if (vmx->vpid != 0)
4223 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4224 spin_unlock(&vmx_vpid_lock);
4225}
4226
8d14695f
YZ		 4227#define MSR_TYPE_R 1
4228#define MSR_TYPE_W 2
4229static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4230 u32 msr, int type)
25c5f225 4231{
3e7c73e9 4232 int f = sizeof(unsigned long);
25c5f225
SY		 4233
4234 if (!cpu_has_vmx_msr_bitmap())
4235 return;
4236
4237 /*
4238 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4239 * have the write-low and read-high bitmap offsets the wrong way round.
4240 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4241 */
25c5f225 4242 if (msr <= 0x1fff) {
8d14695f
YZ		 4243 if (type & MSR_TYPE_R)
4244 /* read-low */
4245 __clear_bit(msr, msr_bitmap + 0x000 / f);
4246
4247 if (type & MSR_TYPE_W)
4248 /* write-low */
4249 __clear_bit(msr, msr_bitmap + 0x800 / f);
4250
25c5f225
SY		 4251 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4252 msr &= 0x1fff;
8d14695f
YZ		 4253 if (type & MSR_TYPE_R)
4254 /* read-high */
4255 __clear_bit(msr, msr_bitmap + 0x400 / f);
4256
4257 if (type & MSR_TYPE_W)
4258 /* write-high */
4259 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4260
4261 }
4262}
4263
4264static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4265 u32 msr, int type)
4266{
4267 int f = sizeof(unsigned long);
4268
4269 if (!cpu_has_vmx_msr_bitmap())
4270 return;
4271
4272 /*
4273 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4274 * have the write-low and read-high bitmap offsets the wrong way round.
4275 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4276 */
4277 if (msr <= 0x1fff) {
4278 if (type & MSR_TYPE_R)
4279 /* read-low */
4280 __set_bit(msr, msr_bitmap + 0x000 / f);
4281
4282 if (type & MSR_TYPE_W)
4283 /* write-low */
4284 __set_bit(msr, msr_bitmap + 0x800 / f);
4285
4286 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4287 msr &= 0x1fff;
4288 if (type & MSR_TYPE_R)
4289 /* read-high */
4290 __set_bit(msr, msr_bitmap + 0x400 / f);
4291
4292 if (type & MSR_TYPE_W)
4293 /* write-high */
4294 __set_bit(msr, msr_bitmap + 0xc00 / f);
4295
25c5f225 4296 }
25c5f225
SY		 4297}
4298
f2b93280
WV		 4299/*
4300 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4301 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4302 */
4303static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4304 unsigned long *msr_bitmap_nested,
4305 u32 msr, int type)
4306{
4307 int f = sizeof(unsigned long);
4308
4309 if (!cpu_has_vmx_msr_bitmap()) {
4310 WARN_ON(1);
4311 return;
4312 }
4313
4314 /*
4315 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4316 * have the write-low and read-high bitmap offsets the wrong way round.
4317 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4318 */
4319 if (msr <= 0x1fff) {
4320 if (type & MSR_TYPE_R &&
4321 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4322 /* read-low */
4323 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4324
4325 if (type & MSR_TYPE_W &&
4326 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4327 /* write-low */
4328 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4329
4330 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4331 msr &= 0x1fff;
4332 if (type & MSR_TYPE_R &&
4333 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4334 /* read-high */
4335 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4336
4337 if (type & MSR_TYPE_W &&
4338 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4339 /* write-high */
4340 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4341
4342 }
4343}
4344
5897297b
AK		 4345static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4346{
4347 if (!longmode_only)
8d14695f
YZ		 4348 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4349 msr, MSR_TYPE_R | MSR_TYPE_W);
4350 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4351 msr, MSR_TYPE_R | MSR_TYPE_W);
4352}
4353
4354static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4355{
4356 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4357 msr, MSR_TYPE_R);
4358 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4359 msr, MSR_TYPE_R);
4360}
4361
4362static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4363{
4364 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4365 msr, MSR_TYPE_R);
4366 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4367 msr, MSR_TYPE_R);
4368}
4369
4370static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4371{
4372 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4373 msr, MSR_TYPE_W);
4374 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4375 msr, MSR_TYPE_W);
5897297b
AK		 4376}
4377
d50ab6c1
PB		 4378static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4379{
35754c98 4380 return enable_apicv && lapic_in_kernel(vcpu);
d50ab6c1
PB		 4381}
4382
705699a1
WV		 4383static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4384{
4385 struct vcpu_vmx *vmx = to_vmx(vcpu);
4386 int max_irr;
4387 void *vapic_page;
4388 u16 status;
4389
4390 if (vmx->nested.pi_desc &&
4391 vmx->nested.pi_pending) {
4392 vmx->nested.pi_pending = false;
4393 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4394 return 0;
4395
4396 max_irr = find_last_bit(
4397 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4398
4399 if (max_irr == 256)
4400 return 0;
4401
4402 vapic_page = kmap(vmx->nested.virtual_apic_page);
4403 if (!vapic_page) {
4404 WARN_ON(1);
4405 return -ENOMEM;
4406 }
4407 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4408 kunmap(vmx->nested.virtual_apic_page);
4409
4410 status = vmcs_read16(GUEST_INTR_STATUS);
4411 if ((u8)max_irr > ((u8)status & 0xff)) {
4412 status &= ~0xff;
4413 status |= (u8)max_irr;
4414 vmcs_write16(GUEST_INTR_STATUS, status);
4415 }
4416 }
4417 return 0;
4418}
4419
21bc8dc5
RK		 4420static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4421{
4422#ifdef CONFIG_SMP
4423 if (vcpu->mode == IN_GUEST_MODE) {
4424 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4425 POSTED_INTR_VECTOR);
4426 return true;
4427 }
4428#endif
4429 return false;
4430}
4431
705699a1
WV		 4432static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4433 int vector)
4434{
4435 struct vcpu_vmx *vmx = to_vmx(vcpu);
4436
4437 if (is_guest_mode(vcpu) &&
4438 vector == vmx->nested.posted_intr_nv) {
4439 /* the PIR and ON have been set by L1. */
21bc8dc5 4440 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV		 4441 /*
4442 * If a posted intr is not recognized by hardware,
4443 * we will accomplish it in the next vmentry.
4444 */
4445 vmx->nested.pi_pending = true;
4446 kvm_make_request(KVM_REQ_EVENT, vcpu);
4447 return 0;
4448 }
4449 return -1;
4450}
a20ed54d
YZ		 4451/*
4452 * Send interrupt to vcpu via posted interrupt way.
4453 * 1. If target vcpu is running(non-root mode), send posted interrupt
4454 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4455 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4456 * interrupt from PIR in next vmentry.
4457 */
4458static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4459{
4460 struct vcpu_vmx *vmx = to_vmx(vcpu);
4461 int r;
4462
705699a1
WV		 4463 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4464 if (!r)
4465 return;
4466
a20ed54d
YZ		 4467 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4468 return;
4469
4470 r = pi_test_and_set_on(&vmx->pi_desc);
4471 kvm_make_request(KVM_REQ_EVENT, vcpu);
21bc8dc5 4472 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ		 4473 kvm_vcpu_kick(vcpu);
4474}
4475
4476static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4477{
4478 struct vcpu_vmx *vmx = to_vmx(vcpu);
4479
4480 if (!pi_test_and_clear_on(&vmx->pi_desc))
4481 return;
4482
4483 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4484}
4485
4486static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4487{
4488 return;
4489}
4490
a3a8ff8e
NHE		 4491/*
4492 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4493 * will not change in the lifetime of the guest.
4494 * Note that host-state that does change is set elsewhere. E.g., host-state
4495 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4496 */
a547c6db 4497static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4498{
4499 u32 low32, high32;
4500 unsigned long tmpl;
4501 struct desc_ptr dt;
d974baa3 4502 unsigned long cr4;
a3a8ff8e 4503
b1a74bf8 4504 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4505 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4506
d974baa3 4507 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 4508 cr4 = cr4_read_shadow();
d974baa3
AL		 4509 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4510 vmx->host_state.vmcs_host_cr4 = cr4;
4511
a3a8ff8e 4512 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4513#ifdef CONFIG_X86_64
4514 /*
4515 * Load null selectors, so we can avoid reloading them in
4516 * __vmx_load_host_state(), in case userspace uses the null selectors
4517 * too (the expected case).
4518 */
4519 vmcs_write16(HOST_DS_SELECTOR, 0);
4520 vmcs_write16(HOST_ES_SELECTOR, 0);
4521#else
a3a8ff8e
NHE		 4522 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4523 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4524#endif
a3a8ff8e
NHE		 4525 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4526 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4527
4528 native_store_idt(&dt);
4529 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4530 vmx->host_idt_base = dt.address;
a3a8ff8e 4531
83287ea4 4532 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4533
4534 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4535 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4536 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4537 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4538
4539 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4540 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4541 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4542 }
4543}
4544
bf8179a0
NHE		 4545static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4546{
4547 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4548 if (enable_ept)
4549 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4550 if (is_guest_mode(&vmx->vcpu))
4551 vmx->vcpu.arch.cr4_guest_owned_bits &=
4552 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4553 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4554}
4555
01e439be
YZ		 4556static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4557{
4558 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4559
35754c98 4560 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
01e439be
YZ		 4561 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4562 return pin_based_exec_ctrl;
4563}
4564
bf8179a0
NHE		 4565static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4566{
4567 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4568
4569 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4570 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4571
35754c98 4572 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE		 4573 exec_control &= ~CPU_BASED_TPR_SHADOW;
4574#ifdef CONFIG_X86_64
4575 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4576 CPU_BASED_CR8_LOAD_EXITING;
4577#endif
4578 }
4579 if (!enable_ept)
4580 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4581 CPU_BASED_CR3_LOAD_EXITING |
4582 CPU_BASED_INVLPG_EXITING;
4583 return exec_control;
4584}
4585
4586static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4587{
4588 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 4589 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE		 4590 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4591 if (vmx->vpid == 0)
4592 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4593 if (!enable_ept) {
4594 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4595 enable_unrestricted_guest = 0;
ad756a16
MJ		 4596 /* Enable INVPCID for non-ept guests may cause performance regression. */
4597 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4598 }
4599 if (!enable_unrestricted_guest)
4600 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4601 if (!ple_gap)
4602 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
35754c98 4603 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
c7c9c56c
YZ		 4604 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4605 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4606 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4607 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4608 (handle_vmptrld).
4609 We can NOT enable shadow_vmcs here because we don't have yet
4610 a current VMCS12
4611 */
4612 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4613 /* PML is enabled/disabled in creating/destorying vcpu */
4614 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4615
8b3e34e4
XG		 4616 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4617 exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4618
bf8179a0
NHE		 4619 return exec_control;
4620}
4621
ce88decf
XG		 4622static void ept_set_mmio_spte_mask(void)
4623{
4624 /*
4625 * EPT Misconfigurations can be generated if the value of bits 2:0
4626 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4627 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4628 * spte.
4629 */
885032b9 4630 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4631}
4632
f53cd63c 4633#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4634/*
4635 * Sets up the vmcs for emulated real mode.
4636 */
8b9cf98c 4637static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4638{
2e4ce7f5 4639#ifdef CONFIG_X86_64
6aa8b732 4640 unsigned long a;
2e4ce7f5 4641#endif
6aa8b732 4642 int i;
6aa8b732 4643
6aa8b732 4644 /* I/O */
3e7c73e9
AK		 4645 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4646 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4647
4607c2d7
AG		 4648 if (enable_shadow_vmcs) {
4649 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4650 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4651 }
25c5f225 4652 if (cpu_has_vmx_msr_bitmap())
5897297b 4653 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4654
6aa8b732
AK		 4655 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4656
6aa8b732 4657 /* Control */
01e439be 4658 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4659
bf8179a0 4660 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4661
8b3e34e4 4662 if (cpu_has_secondary_exec_ctrls())
bf8179a0
NHE		 4663 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4664 vmx_secondary_exec_control(vmx));
f78e0e2e 4665
35754c98 4666 if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
c7c9c56c
YZ		 4667 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4668 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4669 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4670 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4671
4672 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4673
4674 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4675 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4676 }
4677
4b8d54f9
ZE		 4678 if (ple_gap) {
4679 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4680 vmx->ple_window = ple_window;
4681 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4682 }
4683
c3707958
XG		 4684 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4685 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4686 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4687
9581d442
AK		 4688 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4689 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4690 vmx_set_constant_host_state(vmx);
05b3e0c2 4691#ifdef CONFIG_X86_64
6aa8b732
AK		 4692 rdmsrl(MSR_FS_BASE, a);
4693 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4694 rdmsrl(MSR_GS_BASE, a);
4695 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4696#else
4697 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4698 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4699#endif
4700
2cc51560
ED		 4701 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4702 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4703 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4704 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4705 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4706
74545705
RK		 4707 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4708 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4709
03916db9 4710 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4711 u32 index = vmx_msr_index[i];
4712 u32 data_low, data_high;
a2fa3e9f 4713 int j = vmx->nmsrs;
6aa8b732
AK		 4714
4715 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4716 continue;
432bd6cb
AK		 4717 if (wrmsr_safe(index, data_low, data_high) < 0)
4718 continue;
26bb0981
AK		 4719 vmx->guest_msrs[j].index = i;
4720 vmx->guest_msrs[j].data = 0;
d5696725 4721 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4722 ++vmx->nmsrs;
6aa8b732 4723 }
6aa8b732 4724
2961e876
GN		 4725
4726 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4727
4728 /* 22.2.1, 20.8.1 */
2961e876 4729 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4730
e00c8cf2 4731 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4732 set_cr4_guest_host_mask(vmx);
e00c8cf2 4733
f53cd63c
WL		 4734 if (vmx_xsaves_supported())
4735 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4736
e00c8cf2
AK		 4737 return 0;
4738}
4739
d28bc9dd 4740static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4741{
4742 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4743 struct msr_data apic_base_msr;
d28bc9dd 4744 u64 cr0;
e00c8cf2 4745
7ffd92c5 4746 vmx->rmode.vm86_active = 0;
e00c8cf2 4747
3b86cd99
JK		 4748 vmx->soft_vnmi_blocked = 0;
4749
ad312c7c 4750 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 4751 kvm_set_cr8(vcpu, 0);
4752
4753 if (!init_event) {
4754 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4755 MSR_IA32_APICBASE_ENABLE;
4756 if (kvm_vcpu_is_reset_bsp(vcpu))
4757 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4758 apic_base_msr.host_initiated = true;
4759 kvm_set_apic_base(vcpu, &apic_base_msr);
4760 }
e00c8cf2 4761
2fb92db1
AK		 4762 vmx_segment_cache_clear(vmx);
4763
5706be0d 4764 seg_setup(VCPU_SREG_CS);
66450a21 4765 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4766 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4767
4768 seg_setup(VCPU_SREG_DS);
4769 seg_setup(VCPU_SREG_ES);
4770 seg_setup(VCPU_SREG_FS);
4771 seg_setup(VCPU_SREG_GS);
4772 seg_setup(VCPU_SREG_SS);
4773
4774 vmcs_write16(GUEST_TR_SELECTOR, 0);
4775 vmcs_writel(GUEST_TR_BASE, 0);
4776 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4777 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4778
4779 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4780 vmcs_writel(GUEST_LDTR_BASE, 0);
4781 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4782 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4783
d28bc9dd
NA		 4784 if (!init_event) {
4785 vmcs_write32(GUEST_SYSENTER_CS, 0);
4786 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4787 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4788 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4789 }
e00c8cf2
AK		 4790
4791 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4792 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4793
e00c8cf2
AK		 4794 vmcs_writel(GUEST_GDTR_BASE, 0);
4795 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4796
4797 vmcs_writel(GUEST_IDTR_BASE, 0);
4798 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4799
443381a8 4800 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4801 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4802 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4803
e00c8cf2
AK		 4804 setup_msrs(vmx);
4805
6aa8b732
AK		 4806 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4807
d28bc9dd 4808 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4809 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4810 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4811 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4812 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4813 vmcs_write32(TPR_THRESHOLD, 0);
4814 }
4815
a73896cb 4816 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4817
35754c98 4818 if (vmx_cpu_uses_apicv(vcpu))
01e439be
YZ		 4819 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4820
2384d2b3
SY		 4821 if (vmx->vpid != 0)
4822 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4823
d28bc9dd
NA		 4824 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4825 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4826 vmx->vcpu.arch.cr0 = cr0;
4827 vmx_set_cr4(vcpu, 0);
4828 if (!init_event)
4829 vmx_set_efer(vcpu, 0);
4830 vmx_fpu_activate(vcpu);
4831 update_exception_bitmap(vcpu);
6aa8b732 4832
b9d762fa 4833 vpid_sync_context(vmx);
6aa8b732
AK		 4834}
4835
b6f1250e
NHE		 4836/*
4837 * In nested virtualization, check if L1 asked to exit on external interrupts.
4838 * For most existing hypervisors, this will always return true.
4839 */
4840static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4841{
4842 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4843 PIN_BASED_EXT_INTR_MASK;
4844}
4845
77b0f5d6
BD		 4846/*
4847 * In nested virtualization, check if L1 has set
4848 * VM_EXIT_ACK_INTR_ON_EXIT
4849 */
4850static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4851{
4852 return get_vmcs12(vcpu)->vm_exit_controls &
4853 VM_EXIT_ACK_INTR_ON_EXIT;
4854}
4855
ea8ceb83
JK		 4856static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4857{
4858 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4859 PIN_BASED_NMI_EXITING;
4860}
4861
c9a7953f 4862static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4863{
4864 u32 cpu_based_vm_exec_control;
730dca42 4865
3b86cd99
JK		 4866 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4867 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4868 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4869}
4870
c9a7953f 4871static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4872{
4873 u32 cpu_based_vm_exec_control;
4874
c9a7953f
JK		 4875 if (!cpu_has_virtual_nmis() ||
4876 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4877 enable_irq_window(vcpu);
4878 return;
4879 }
3b86cd99
JK		 4880
4881 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4882 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4883 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4884}
4885
66fd3f7f 4886static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4887{
9c8cba37 4888 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4889 uint32_t intr;
4890 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4891
229456fc 4892 trace_kvm_inj_virq(irq);
2714d1d3 4893
fa89a817 4894 ++vcpu->stat.irq_injections;
7ffd92c5 4895 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4896 int inc_eip = 0;
4897 if (vcpu->arch.interrupt.soft)
4898 inc_eip = vcpu->arch.event_exit_inst_len;
4899 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4900 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4901 return;
4902 }
66fd3f7f
GN		 4903 intr = irq | INTR_INFO_VALID_MASK;
4904 if (vcpu->arch.interrupt.soft) {
4905 intr |= INTR_TYPE_SOFT_INTR;
4906 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4907 vmx->vcpu.arch.event_exit_inst_len);
4908 } else
4909 intr |= INTR_TYPE_EXT_INTR;
4910 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4911}
4912
f08864b4
SY		 4913static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4914{
66a5a347
JK		 4915 struct vcpu_vmx *vmx = to_vmx(vcpu);
4916
0b6ac343
NHE		 4917 if (is_guest_mode(vcpu))
4918 return;
4919
3b86cd99
JK		 4920 if (!cpu_has_virtual_nmis()) {
4921 /*
4922 * Tracking the NMI-blocked state in software is built upon
4923 * finding the next open IRQ window. This, in turn, depends on
4924 * well-behaving guests: They have to keep IRQs disabled at
4925 * least as long as the NMI handler runs. Otherwise we may
4926 * cause NMI nesting, maybe breaking the guest. But as this is
4927 * highly unlikely, we can live with the residual risk.
4928 */
4929 vmx->soft_vnmi_blocked = 1;
4930 vmx->vnmi_blocked_time = 0;
4931 }
4932
487b391d 4933 ++vcpu->stat.nmi_injections;
9d58b931 4934 vmx->nmi_known_unmasked = false;
7ffd92c5 4935 if (vmx->rmode.vm86_active) {
71f9833b 4936 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4937 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4938 return;
4939 }
f08864b4
SY		 4940 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4941 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4942}
4943
3cfc3092
JK		 4944static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4945{
4946 if (!cpu_has_virtual_nmis())
4947 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4948 if (to_vmx(vcpu)->nmi_known_unmasked)
4949 return false;
c332c83a 4950 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4951}
4952
4953static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4954{
4955 struct vcpu_vmx *vmx = to_vmx(vcpu);
4956
4957 if (!cpu_has_virtual_nmis()) {
4958 if (vmx->soft_vnmi_blocked != masked) {
4959 vmx->soft_vnmi_blocked = masked;
4960 vmx->vnmi_blocked_time = 0;
4961 }
4962 } else {
9d58b931 4963 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4964 if (masked)
4965 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4966 GUEST_INTR_STATE_NMI);
4967 else
4968 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4969 GUEST_INTR_STATE_NMI);
4970 }
4971}
4972
2505dc9f
JK		 4973static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4974{
b6b8a145
JK		 4975 if (to_vmx(vcpu)->nested.nested_run_pending)
4976 return 0;
ea8ceb83 4977
2505dc9f
JK		 4978 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4979 return 0;
4980
4981 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4982 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4983 | GUEST_INTR_STATE_NMI));
4984}
4985
78646121
GN		 4986static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4987{
b6b8a145
JK		 4988 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4989 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4990 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4991 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4992}
4993
cbc94022
IE		 4994static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4995{
4996 int ret;
4997 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4998 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4999 .guest_phys_addr = addr,
5000 .memory_size = PAGE_SIZE * 3,
5001 .flags = 0,
5002 };
5003
9da0e4d5 5004 ret = x86_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 5005 if (ret)
5006 return ret;
bfc6d222 5007 kvm->arch.tss_addr = addr;
1f755a82 5008 return init_rmode_tss(kvm);
cbc94022
IE		 5009}
5010
0ca1b4f4 5011static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 5012{
77ab6db0 5013 switch (vec) {
77ab6db0 5014 case BP_VECTOR:
c573cd22
JK		 5015 /*
5016 * Update instruction length as we may reinject the exception
5017 * from user space while in guest debugging mode.
5018 */
5019 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5020 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 5021 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 5022 return false;
5023 /* fall through */
5024 case DB_VECTOR:
5025 if (vcpu->guest_debug &
5026 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5027 return false;
d0bfb940
JK		 5028 /* fall through */
5029 case DE_VECTOR:
77ab6db0
JK		 5030 case OF_VECTOR:
5031 case BR_VECTOR:
5032 case UD_VECTOR:
5033 case DF_VECTOR:
5034 case SS_VECTOR:
5035 case GP_VECTOR:
5036 case MF_VECTOR:
0ca1b4f4
GN		 5037 return true;
5038 break;
77ab6db0 5039 }
0ca1b4f4
GN		 5040 return false;
5041}
5042
5043static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5044 int vec, u32 err_code)
5045{
5046 /*
5047 * Instruction with address size override prefix opcode 0x67
5048 * Cause the #SS fault with 0 error code in VM86 mode.
5049 */
5050 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5051 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5052 if (vcpu->arch.halt_request) {
5053 vcpu->arch.halt_request = 0;
5cb56059 5054 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 5055 }
5056 return 1;
5057 }
5058 return 0;
5059 }
5060
5061 /*
5062 * Forward all other exceptions that are valid in real mode.
5063 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5064 * the required debugging infrastructure rework.
5065 */
5066 kvm_queue_exception(vcpu, vec);
5067 return 1;
6aa8b732
AK		 5068}
5069
a0861c02
AK		 5070/*
5071 * Trigger machine check on the host. We assume all the MSRs are already set up
5072 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5073 * We pass a fake environment to the machine check handler because we want
5074 * the guest to be always treated like user space, no matter what context
5075 * it used internally.
5076 */
5077static void kvm_machine_check(void)
5078{
5079#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5080 struct pt_regs regs = {
5081 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5082 .flags = X86_EFLAGS_IF,
5083 };
5084
5085 do_machine_check(&regs, 0);
5086#endif
5087}
5088
851ba692 5089static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 5090{
5091 /* already handled by vcpu_run */
5092 return 1;
5093}
5094
851ba692 5095static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5096{
1155f76a 5097 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5098 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5099 u32 intr_info, ex_no, error_code;
42dbaa5a 5100 unsigned long cr2, rip, dr6;
6aa8b732
AK		 5101 u32 vect_info;
5102 enum emulation_result er;
5103
1155f76a 5104 vect_info = vmx->idt_vectoring_info;
88786475 5105 intr_info = vmx->exit_intr_info;
6aa8b732 5106
a0861c02 5107 if (is_machine_check(intr_info))
851ba692 5108 return handle_machine_check(vcpu);
a0861c02 5109
e4a41889 5110 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 5111 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 5112
5113 if (is_no_device(intr_info)) {
5fd86fcf 5114 vmx_fpu_activate(vcpu);
2ab455cc
AL		 5115 return 1;
5116 }
5117
7aa81cc0 5118 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK		 5119 if (is_guest_mode(vcpu)) {
5120 kvm_queue_exception(vcpu, UD_VECTOR);
5121 return 1;
5122 }
51d8b661 5123 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5124 if (er != EMULATE_DONE)
7ee5d940 5125 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 5126 return 1;
5127 }
5128
6aa8b732 5129 error_code = 0;
2e11384c 5130 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5131 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 5132
5133 /*
5134 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5135 * MMIO, it is better to report an internal error.
5136 * See the comments in vmx_handle_exit.
5137 */
5138 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5139 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5140 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5141 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5142 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 5143 vcpu->run->internal.data[0] = vect_info;
5144 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5145 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 5146 return 0;
5147 }
5148
6aa8b732 5149 if (is_page_fault(intr_info)) {
1439442c 5150 /* EPT won't cause page fault directly */
cf3ace79 5151 BUG_ON(enable_ept);
6aa8b732 5152 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5153 trace_kvm_page_fault(cr2, error_code);
5154
3298b75c 5155 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5156 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5157 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5158 }
5159
d0bfb940 5160 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5161
5162 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5163 return handle_rmode_exception(vcpu, ex_no, error_code);
5164
42dbaa5a
JK		 5165 switch (ex_no) {
5166 case DB_VECTOR:
5167 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5168 if (!(vcpu->guest_debug &
5169 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5170 vcpu->arch.dr6 &= ~15;
6f43ed01 5171 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5172 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5173 skip_emulated_instruction(vcpu);
5174
42dbaa5a
JK		 5175 kvm_queue_exception(vcpu, DB_VECTOR);
5176 return 1;
5177 }
5178 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5179 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5180 /* fall through */
5181 case BP_VECTOR:
c573cd22
JK		 5182 /*
5183 * Update instruction length as we may reinject #BP from
5184 * user space while in guest debugging mode. Reading it for
5185 * #DB as well causes no harm, it is not used in that case.
5186 */
5187 vmx->vcpu.arch.event_exit_inst_len =
5188 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5189 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5190 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5191 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5192 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5193 break;
5194 default:
d0bfb940
JK		 5195 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5196 kvm_run->ex.exception = ex_no;
5197 kvm_run->ex.error_code = error_code;
42dbaa5a 5198 break;
6aa8b732 5199 }
6aa8b732
AK		 5200 return 0;
5201}
5202
851ba692 5203static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5204{
1165f5fe 5205 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5206 return 1;
5207}
5208
851ba692 5209static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5210{
851ba692 5211 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5212 return 0;
5213}
6aa8b732 5214
851ba692 5215static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5216{
bfdaab09 5217 unsigned long exit_qualification;
34c33d16 5218 int size, in, string;
039576c0 5219 unsigned port;
6aa8b732 5220
bfdaab09 5221 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5222 string = (exit_qualification & 16) != 0;
cf8f70bf 5223 in = (exit_qualification & 8) != 0;
e70669ab 5224
cf8f70bf 5225 ++vcpu->stat.io_exits;
e70669ab 5226
cf8f70bf 5227 if (string || in)
51d8b661 5228 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5229
cf8f70bf
GN		 5230 port = exit_qualification >> 16;
5231 size = (exit_qualification & 7) + 1;
e93f36bc 5232 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5233
5234 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5235}
5236
102d8325
IM		 5237static void
5238vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5239{
5240 /*
5241 * Patch in the VMCALL instruction:
5242 */
5243 hypercall[0] = 0x0f;
5244 hypercall[1] = 0x01;
5245 hypercall[2] = 0xc1;
102d8325
IM		 5246}
5247
b9c237bb 5248static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5249{
5250 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5251 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5252
b9c237bb 5253 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5254 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5255 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5256 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5257 return (val & always_on) == always_on;
5258}
5259
0fa06071 5260/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5261static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5262{
eeadf9e7 5263 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5264 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5265 unsigned long orig_val = val;
5266
eeadf9e7
NHE		 5267 /*
5268 * We get here when L2 changed cr0 in a way that did not change
5269 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5270 * but did change L0 shadowed bits. So we first calculate the
5271 * effective cr0 value that L1 would like to write into the
5272 * hardware. It consists of the L2-owned bits from the new
5273 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5274 */
1a0d74e6
JK		 5275 val = (val & ~vmcs12->cr0_guest_host_mask) |
5276 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5277
b9c237bb 5278 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5279 return 1;
1a0d74e6
JK		 5280
5281 if (kvm_set_cr0(vcpu, val))
5282 return 1;
5283 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5284 return 0;
1a0d74e6
JK		 5285 } else {
5286 if (to_vmx(vcpu)->nested.vmxon &&
5287 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5288 return 1;
eeadf9e7 5289 return kvm_set_cr0(vcpu, val);
1a0d74e6 5290 }
eeadf9e7
NHE		 5291}
5292
5293static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5294{
5295 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5296 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5297 unsigned long orig_val = val;
5298
5299 /* analogously to handle_set_cr0 */
5300 val = (val & ~vmcs12->cr4_guest_host_mask) |
5301 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5302 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5303 return 1;
1a0d74e6 5304 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5305 return 0;
5306 } else
5307 return kvm_set_cr4(vcpu, val);
5308}
5309
5310/* called to set cr0 as approriate for clts instruction exit. */
5311static void handle_clts(struct kvm_vcpu *vcpu)
5312{
5313 if (is_guest_mode(vcpu)) {
5314 /*
5315 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5316 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5317 * just pretend it's off (also in arch.cr0 for fpu_activate).
5318 */
5319 vmcs_writel(CR0_READ_SHADOW,
5320 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5321 vcpu->arch.cr0 &= ~X86_CR0_TS;
5322 } else
5323 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5324}
5325
851ba692 5326static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5327{
229456fc 5328 unsigned long exit_qualification, val;
6aa8b732
AK		 5329 int cr;
5330 int reg;
49a9b07e 5331 int err;
6aa8b732 5332
bfdaab09 5333 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5334 cr = exit_qualification & 15;
5335 reg = (exit_qualification >> 8) & 15;
5336 switch ((exit_qualification >> 4) & 3) {
5337 case 0: /* mov to cr */
1e32c079 5338 val = kvm_register_readl(vcpu, reg);
229456fc 5339 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5340 switch (cr) {
5341 case 0:
eeadf9e7 5342 err = handle_set_cr0(vcpu, val);
db8fcefa 5343 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5344 return 1;
5345 case 3:
2390218b 5346 err = kvm_set_cr3(vcpu, val);
db8fcefa 5347 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5348 return 1;
5349 case 4:
eeadf9e7 5350 err = handle_set_cr4(vcpu, val);
db8fcefa 5351 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5352 return 1;
0a5fff19
GN		 5353 case 8: {
5354 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5355 u8 cr8 = (u8)val;
eea1cff9 5356 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5357 kvm_complete_insn_gp(vcpu, err);
35754c98 5358 if (lapic_in_kernel(vcpu))
0a5fff19
GN		 5359 return 1;
5360 if (cr8_prev <= cr8)
5361 return 1;
851ba692 5362 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5363 return 0;
5364 }
4b8073e4 5365 }
6aa8b732 5366 break;
25c4c276 5367 case 2: /* clts */
eeadf9e7 5368 handle_clts(vcpu);
4d4ec087 5369 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5370 skip_emulated_instruction(vcpu);
6b52d186 5371 vmx_fpu_activate(vcpu);
25c4c276 5372 return 1;
6aa8b732
AK		 5373 case 1: /*mov from cr*/
5374 switch (cr) {
5375 case 3:
9f8fe504
AK		 5376 val = kvm_read_cr3(vcpu);
5377 kvm_register_write(vcpu, reg, val);
5378 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5379 skip_emulated_instruction(vcpu);
5380 return 1;
5381 case 8:
229456fc
MT		 5382 val = kvm_get_cr8(vcpu);
5383 kvm_register_write(vcpu, reg, val);
5384 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5385 skip_emulated_instruction(vcpu);
5386 return 1;
5387 }
5388 break;
5389 case 3: /* lmsw */
a1f83a74 5390 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5391 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5392 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5393
5394 skip_emulated_instruction(vcpu);
5395 return 1;
5396 default:
5397 break;
5398 }
851ba692 5399 vcpu->run->exit_reason = 0;
a737f256 5400 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5401 (int)(exit_qualification >> 4) & 3, cr);
5402 return 0;
5403}
5404
851ba692 5405static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5406{
bfdaab09 5407 unsigned long exit_qualification;
16f8a6f9
NA		 5408 int dr, dr7, reg;
5409
5410 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5411 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5412
5413 /* First, if DR does not exist, trigger UD */
5414 if (!kvm_require_dr(vcpu, dr))
5415 return 1;
6aa8b732 5416
f2483415 5417 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5418 if (!kvm_require_cpl(vcpu, 0))
5419 return 1;
16f8a6f9
NA		 5420 dr7 = vmcs_readl(GUEST_DR7);
5421 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5422 /*
5423 * As the vm-exit takes precedence over the debug trap, we
5424 * need to emulate the latter, either for the host or the
5425 * guest debugging itself.
5426 */
5427 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5428 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5429 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5430 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5431 vcpu->run->debug.arch.exception = DB_VECTOR;
5432 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5433 return 0;
5434 } else {
7305eb5d 5435 vcpu->arch.dr6 &= ~15;
6f43ed01 5436 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5437 kvm_queue_exception(vcpu, DB_VECTOR);
5438 return 1;
5439 }
5440 }
5441
81908bf4
PB		 5442 if (vcpu->guest_debug == 0) {
5443 u32 cpu_based_vm_exec_control;
5444
5445 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5446 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5447 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5448
5449 /*
5450 * No more DR vmexits; force a reload of the debug registers
5451 * and reenter on this instruction. The next vmexit will
5452 * retrieve the full state of the debug registers.
5453 */
5454 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5455 return 1;
5456 }
5457
42dbaa5a
JK		 5458 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5459 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5460 unsigned long val;
4c4d563b
JK		 5461
5462 if (kvm_get_dr(vcpu, dr, &val))
5463 return 1;
5464 kvm_register_write(vcpu, reg, val);
020df079 5465 } else
5777392e 5466 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5467 return 1;
5468
6aa8b732
AK		 5469 skip_emulated_instruction(vcpu);
5470 return 1;
5471}
5472
73aaf249
JK		 5473static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5474{
5475 return vcpu->arch.dr6;
5476}
5477
5478static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5479{
5480}
5481
81908bf4
PB		 5482static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5483{
5484 u32 cpu_based_vm_exec_control;
5485
5486 get_debugreg(vcpu->arch.db[0], 0);
5487 get_debugreg(vcpu->arch.db[1], 1);
5488 get_debugreg(vcpu->arch.db[2], 2);
5489 get_debugreg(vcpu->arch.db[3], 3);
5490 get_debugreg(vcpu->arch.dr6, 6);
5491 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5492
5493 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5494
5495 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5496 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5497 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5498}
5499
020df079
GN		 5500static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5501{
5502 vmcs_writel(GUEST_DR7, val);
5503}
5504
851ba692 5505static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5506{
06465c5a
AK		 5507 kvm_emulate_cpuid(vcpu);
5508 return 1;
6aa8b732
AK		 5509}
5510
851ba692 5511static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5512{
ad312c7c 5513 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 5514 struct msr_data msr_info;
6aa8b732 5515
609e36d3
PB		 5516 msr_info.index = ecx;
5517 msr_info.host_initiated = false;
5518 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 5519 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5520 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5521 return 1;
5522 }
5523
609e36d3 5524 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 5525
6aa8b732 5526 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB		 5527 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5528 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6aa8b732
AK		 5529 skip_emulated_instruction(vcpu);
5530 return 1;
5531}
5532
851ba692 5533static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5534{
8fe8ab46 5535 struct msr_data msr;
ad312c7c
ZX		 5536 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5537 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5538 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5539
8fe8ab46
WA		 5540 msr.data = data;
5541 msr.index = ecx;
5542 msr.host_initiated = false;
854e8bb1 5543 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5544 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5545 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5546 return 1;
5547 }
5548
59200273 5549 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5550 skip_emulated_instruction(vcpu);
5551 return 1;
5552}
5553
851ba692 5554static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5555{
3842d135 5556 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5557 return 1;
5558}
5559
851ba692 5560static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5561{
85f455f7
ED		 5562 u32 cpu_based_vm_exec_control;
5563
5564 /* clear pending irq */
5565 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5566 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5567 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5568
3842d135
AK		 5569 kvm_make_request(KVM_REQ_EVENT, vcpu);
5570
a26bf12a 5571 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 5572 return 1;
5573}
5574
851ba692 5575static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 5576{
d3bef15f 5577 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5578}
5579
851ba692 5580static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5581{
7aa81cc0
AL		 5582 kvm_emulate_hypercall(vcpu);
5583 return 1;
c21415e8
IM		 5584}
5585
ec25d5e6
GN		 5586static int handle_invd(struct kvm_vcpu *vcpu)
5587{
51d8b661 5588 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5589}
5590
851ba692 5591static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5592{
f9c617f6 5593 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5594
5595 kvm_mmu_invlpg(vcpu, exit_qualification);
5596 skip_emulated_instruction(vcpu);
5597 return 1;
5598}
5599
fee84b07
AK		 5600static int handle_rdpmc(struct kvm_vcpu *vcpu)
5601{
5602 int err;
5603
5604 err = kvm_rdpmc(vcpu);
5605 kvm_complete_insn_gp(vcpu, err);
5606
5607 return 1;
5608}
5609
851ba692 5610static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5611{
f5f48ee1 5612 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5613 return 1;
5614}
5615
2acf923e
DC		 5616static int handle_xsetbv(struct kvm_vcpu *vcpu)
5617{
5618 u64 new_bv = kvm_read_edx_eax(vcpu);
5619 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5620
5621 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5622 skip_emulated_instruction(vcpu);
5623 return 1;
5624}
5625
f53cd63c
WL		 5626static int handle_xsaves(struct kvm_vcpu *vcpu)
5627{
5628 skip_emulated_instruction(vcpu);
5629 WARN(1, "this should never happen\n");
5630 return 1;
5631}
5632
5633static int handle_xrstors(struct kvm_vcpu *vcpu)
5634{
5635 skip_emulated_instruction(vcpu);
5636 WARN(1, "this should never happen\n");
5637 return 1;
5638}
5639
851ba692 5640static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5641{
58fbbf26
KT		 5642 if (likely(fasteoi)) {
5643 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5644 int access_type, offset;
5645
5646 access_type = exit_qualification & APIC_ACCESS_TYPE;
5647 offset = exit_qualification & APIC_ACCESS_OFFSET;
5648 /*
5649 * Sane guest uses MOV to write EOI, with written value
5650 * not cared. So make a short-circuit here by avoiding
5651 * heavy instruction emulation.
5652 */
5653 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5654 (offset == APIC_EOI)) {
5655 kvm_lapic_set_eoi(vcpu);
5656 skip_emulated_instruction(vcpu);
5657 return 1;
5658 }
5659 }
51d8b661 5660 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5661}
5662
c7c9c56c
YZ		 5663static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5664{
5665 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5666 int vector = exit_qualification & 0xff;
5667
5668 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5669 kvm_apic_set_eoi_accelerated(vcpu, vector);
5670 return 1;
5671}
5672
83d4c286
YZ		 5673static int handle_apic_write(struct kvm_vcpu *vcpu)
5674{
5675 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5676 u32 offset = exit_qualification & 0xfff;
5677
5678 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5679 kvm_apic_write_nodecode(vcpu, offset);
5680 return 1;
5681}
5682
851ba692 5683static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5684{
60637aac 5685 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5686 unsigned long exit_qualification;
e269fb21
JK		 5687 bool has_error_code = false;
5688 u32 error_code = 0;
37817f29 5689 u16 tss_selector;
7f3d35fd 5690 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5691
5692 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5693 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5694 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5695
5696 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5697
5698 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5699 if (reason == TASK_SWITCH_GATE && idt_v) {
5700 switch (type) {
5701 case INTR_TYPE_NMI_INTR:
5702 vcpu->arch.nmi_injected = false;
654f06fc 5703 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5704 break;
5705 case INTR_TYPE_EXT_INTR:
66fd3f7f 5706 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5707 kvm_clear_interrupt_queue(vcpu);
5708 break;
5709 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5710 if (vmx->idt_vectoring_info &
5711 VECTORING_INFO_DELIVER_CODE_MASK) {
5712 has_error_code = true;
5713 error_code =
5714 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5715 }
5716 /* fall through */
64a7ec06
GN		 5717 case INTR_TYPE_SOFT_EXCEPTION:
5718 kvm_clear_exception_queue(vcpu);
5719 break;
5720 default:
5721 break;
5722 }
60637aac 5723 }
37817f29
IE		 5724 tss_selector = exit_qualification;
5725
64a7ec06
GN		 5726 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5727 type != INTR_TYPE_EXT_INTR &&
5728 type != INTR_TYPE_NMI_INTR))
5729 skip_emulated_instruction(vcpu);
5730
7f3d35fd
KW		 5731 if (kvm_task_switch(vcpu, tss_selector,
5732 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5733 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5734 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5735 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5736 vcpu->run->internal.ndata = 0;
42dbaa5a 5737 return 0;
acb54517 5738 }
42dbaa5a 5739
42dbaa5a
JK		 5740 /*
5741 * TODO: What about debug traps on tss switch?
5742 * Are we supposed to inject them and update dr6?
5743 */
5744
5745 return 1;
37817f29
IE		 5746}
5747
851ba692 5748static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5749{
f9c617f6 5750 unsigned long exit_qualification;
1439442c 5751 gpa_t gpa;
4f5982a5 5752 u32 error_code;
1439442c 5753 int gla_validity;
1439442c 5754
f9c617f6 5755 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5756
1439442c
SY		 5757 gla_validity = (exit_qualification >> 7) & 0x3;
5758 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5759 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5760 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5761 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5762 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5763 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5764 (long unsigned int)exit_qualification);
851ba692
AK		 5765 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5766 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5767 return 0;
1439442c
SY		 5768 }
5769
0be9c7a8
GN		 5770 /*
5771 * EPT violation happened while executing iret from NMI,
5772 * "blocked by NMI" bit has to be set before next VM entry.
5773 * There are errata that may cause this bit to not be set:
5774 * AAK134, BY25.
5775 */
bcd1c294
GN		 5776 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5777 cpu_has_virtual_nmis() &&
5778 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5779 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5780
1439442c 5781 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5782 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5783
5784 /* It is a write fault? */
81ed33e4 5785 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5786 /* It is a fetch fault? */
81ed33e4 5787 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5788 /* ept page table is present? */
81ed33e4 5789 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5790
25d92081
YZ		 5791 vcpu->arch.exit_qualification = exit_qualification;
5792
4f5982a5 5793 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5794}
5795
851ba692 5796static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5797{
f735d4af 5798 int ret;
68f89400
MT		 5799 gpa_t gpa;
5800
5801 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 5802 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
68c3b4d1 5803 skip_emulated_instruction(vcpu);
931c33b1 5804 trace_kvm_fast_mmio(gpa);
68c3b4d1
MT		 5805 return 1;
5806 }
68f89400 5807
ce88decf 5808 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5809 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5810 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5811 EMULATE_DONE;
f8f55942
XG		 5812
5813 if (unlikely(ret == RET_MMIO_PF_INVALID))
5814 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5815
b37fbea6 5816 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5817 return 1;
5818
5819 /* It is the real ept misconfig */
f735d4af 5820 WARN_ON(1);
68f89400 5821
851ba692
AK		 5822 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5823 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5824
5825 return 0;
5826}
5827
851ba692 5828static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5829{
5830 u32 cpu_based_vm_exec_control;
5831
5832 /* clear pending NMI */
5833 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5834 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5835 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5836 ++vcpu->stat.nmi_window_exits;
3842d135 5837 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5838
5839 return 1;
5840}
5841
80ced186 5842static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5843{
8b3079a5
AK		 5844 struct vcpu_vmx *vmx = to_vmx(vcpu);
5845 enum emulation_result err = EMULATE_DONE;
80ced186 5846 int ret = 1;
49e9d557
AK		 5847 u32 cpu_exec_ctrl;
5848 bool intr_window_requested;
b8405c18 5849 unsigned count = 130;
49e9d557
AK		 5850
5851 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5852 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5853
98eb2f8b 5854 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5855 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5856 return handle_interrupt_window(&vmx->vcpu);
5857
de87dcdd
AK		 5858 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5859 return 1;
5860
991eebf9 5861 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5862
ac0a48c3 5863 if (err == EMULATE_USER_EXIT) {
94452b9e 5864 ++vcpu->stat.mmio_exits;
80ced186
MG		 5865 ret = 0;
5866 goto out;
5867 }
1d5a4d9b 5868
de5f70e0
AK		 5869 if (err != EMULATE_DONE) {
5870 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5871 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5872 vcpu->run->internal.ndata = 0;
6d77dbfc 5873 return 0;
de5f70e0 5874 }
ea953ef0 5875
8d76c49e
GN		 5876 if (vcpu->arch.halt_request) {
5877 vcpu->arch.halt_request = 0;
5cb56059 5878 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5879 goto out;
5880 }
5881
ea953ef0 5882 if (signal_pending(current))
80ced186 5883 goto out;
ea953ef0
MG		 5884 if (need_resched())
5885 schedule();
5886 }
5887
80ced186
MG		 5888out:
5889 return ret;
ea953ef0
MG		 5890}
5891
b4a2d31d
RK		 5892static int __grow_ple_window(int val)
5893{
5894 if (ple_window_grow < 1)
5895 return ple_window;
5896
5897 val = min(val, ple_window_actual_max);
5898
5899 if (ple_window_grow < ple_window)
5900 val *= ple_window_grow;
5901 else
5902 val += ple_window_grow;
5903
5904 return val;
5905}
5906
5907static int __shrink_ple_window(int val, int modifier, int minimum)
5908{
5909 if (modifier < 1)
5910 return ple_window;
5911
5912 if (modifier < ple_window)
5913 val /= modifier;
5914 else
5915 val -= modifier;
5916
5917 return max(val, minimum);
5918}
5919
5920static void grow_ple_window(struct kvm_vcpu *vcpu)
5921{
5922 struct vcpu_vmx *vmx = to_vmx(vcpu);
5923 int old = vmx->ple_window;
5924
5925 vmx->ple_window = __grow_ple_window(old);
5926
5927 if (vmx->ple_window != old)
5928 vmx->ple_window_dirty = true;
7b46268d
RK		 5929
5930 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5931}
5932
5933static void shrink_ple_window(struct kvm_vcpu *vcpu)
5934{
5935 struct vcpu_vmx *vmx = to_vmx(vcpu);
5936 int old = vmx->ple_window;
5937
5938 vmx->ple_window = __shrink_ple_window(old,
5939 ple_window_shrink, ple_window);
5940
5941 if (vmx->ple_window != old)
5942 vmx->ple_window_dirty = true;
7b46268d
RK		 5943
5944 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5945}
5946
5947/*
5948 * ple_window_actual_max is computed to be one grow_ple_window() below
5949 * ple_window_max. (See __grow_ple_window for the reason.)
5950 * This prevents overflows, because ple_window_max is int.
5951 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5952 * this process.
5953 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5954 */
5955static void update_ple_window_actual_max(void)
5956{
5957 ple_window_actual_max =
5958 __shrink_ple_window(max(ple_window_max, ple_window),
5959 ple_window_grow, INT_MIN);
5960}
5961
f2c7648d
TC		 5962static __init int hardware_setup(void)
5963{
34a1cd60
TC		 5964 int r = -ENOMEM, i, msr;
5965
5966 rdmsrl_safe(MSR_EFER, &host_efer);
5967
5968 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5969 kvm_define_shared_msr(i, vmx_msr_index[i]);
5970
5971 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5972 if (!vmx_io_bitmap_a)
5973 return r;
5974
5975 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5976 if (!vmx_io_bitmap_b)
5977 goto out;
5978
5979 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5980 if (!vmx_msr_bitmap_legacy)
5981 goto out1;
5982
5983 vmx_msr_bitmap_legacy_x2apic =
5984 (unsigned long *)__get_free_page(GFP_KERNEL);
5985 if (!vmx_msr_bitmap_legacy_x2apic)
5986 goto out2;
5987
5988 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5989 if (!vmx_msr_bitmap_longmode)
5990 goto out3;
5991
5992 vmx_msr_bitmap_longmode_x2apic =
5993 (unsigned long *)__get_free_page(GFP_KERNEL);
5994 if (!vmx_msr_bitmap_longmode_x2apic)
5995 goto out4;
3af18d9c
WV		 5996
5997 if (nested) {
5998 vmx_msr_bitmap_nested =
5999 (unsigned long *)__get_free_page(GFP_KERNEL);
6000 if (!vmx_msr_bitmap_nested)
6001 goto out5;
6002 }
6003
34a1cd60
TC		 6004 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6005 if (!vmx_vmread_bitmap)
3af18d9c 6006 goto out6;
34a1cd60
TC		 6007
6008 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6009 if (!vmx_vmwrite_bitmap)
3af18d9c 6010 goto out7;
34a1cd60
TC		 6011
6012 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6013 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6014
6015 /*
6016 * Allow direct access to the PC debug port (it is often used for I/O
6017 * delays, but the vmexits simply slow things down).
6018 */
6019 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6020 clear_bit(0x80, vmx_io_bitmap_a);
6021
6022 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6023
6024 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6025 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 6026 if (nested)
6027 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 6028
34a1cd60
TC		 6029 if (setup_vmcs_config(&vmcs_config) < 0) {
6030 r = -EIO;
3af18d9c 6031 goto out8;
baa03522 6032 }
f2c7648d
TC		 6033
6034 if (boot_cpu_has(X86_FEATURE_NX))
6035 kvm_enable_efer_bits(EFER_NX);
6036
6037 if (!cpu_has_vmx_vpid())
6038 enable_vpid = 0;
6039 if (!cpu_has_vmx_shadow_vmcs())
6040 enable_shadow_vmcs = 0;
6041 if (enable_shadow_vmcs)
6042 init_vmcs_shadow_fields();
6043
6044 if (!cpu_has_vmx_ept() ||
6045 !cpu_has_vmx_ept_4levels()) {
6046 enable_ept = 0;
6047 enable_unrestricted_guest = 0;
6048 enable_ept_ad_bits = 0;
6049 }
6050
6051 if (!cpu_has_vmx_ept_ad_bits())
6052 enable_ept_ad_bits = 0;
6053
6054 if (!cpu_has_vmx_unrestricted_guest())
6055 enable_unrestricted_guest = 0;
6056
ad15a296 6057 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6058 flexpriority_enabled = 0;
6059
ad15a296
PB		 6060 /*
6061 * set_apic_access_page_addr() is used to reload apic access
6062 * page upon invalidation. No need to do anything if not
6063 * using the APIC_ACCESS_ADDR VMCS field.
6064 */
6065 if (!flexpriority_enabled)
f2c7648d 6066 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6067
6068 if (!cpu_has_vmx_tpr_shadow())
6069 kvm_x86_ops->update_cr8_intercept = NULL;
6070
6071 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6072 kvm_disable_largepages();
6073
6074 if (!cpu_has_vmx_ple())
6075 ple_gap = 0;
6076
6077 if (!cpu_has_vmx_apicv())
6078 enable_apicv = 0;
6079
6080 if (enable_apicv)
6081 kvm_x86_ops->update_cr8_intercept = NULL;
6082 else {
6083 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6084 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6085 kvm_x86_ops->deliver_posted_interrupt = NULL;
6086 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6087 }
6088
baa03522
TC		 6089 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6090 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6091 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6092 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6093 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6094 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6095 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6096
6097 memcpy(vmx_msr_bitmap_legacy_x2apic,
6098 vmx_msr_bitmap_legacy, PAGE_SIZE);
6099 memcpy(vmx_msr_bitmap_longmode_x2apic,
6100 vmx_msr_bitmap_longmode, PAGE_SIZE);
6101
04bb92e4
WL		 6102 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6103
baa03522
TC		 6104 if (enable_apicv) {
6105 for (msr = 0x800; msr <= 0x8ff; msr++)
6106 vmx_disable_intercept_msr_read_x2apic(msr);
6107
6108 /* According SDM, in x2apic mode, the whole id reg is used.
6109 * But in KVM, it only use the highest eight bits. Need to
6110 * intercept it */
6111 vmx_enable_intercept_msr_read_x2apic(0x802);
6112 /* TMCCT */
6113 vmx_enable_intercept_msr_read_x2apic(0x839);
6114 /* TPR */
6115 vmx_disable_intercept_msr_write_x2apic(0x808);
6116 /* EOI */
6117 vmx_disable_intercept_msr_write_x2apic(0x80b);
6118 /* SELF-IPI */
6119 vmx_disable_intercept_msr_write_x2apic(0x83f);
6120 }
6121
6122 if (enable_ept) {
6123 kvm_mmu_set_mask_ptes(0ull,
6124 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6125 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6126 0ull, VMX_EPT_EXECUTABLE_MASK);
6127 ept_set_mmio_spte_mask();
6128 kvm_enable_tdp();
6129 } else
6130 kvm_disable_tdp();
6131
6132 update_ple_window_actual_max();
6133
843e4330
KH		 6134 /*
6135 * Only enable PML when hardware supports PML feature, and both EPT
6136 * and EPT A/D bit features are enabled -- PML depends on them to work.
6137 */
6138 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6139 enable_pml = 0;
6140
6141 if (!enable_pml) {
6142 kvm_x86_ops->slot_enable_log_dirty = NULL;
6143 kvm_x86_ops->slot_disable_log_dirty = NULL;
6144 kvm_x86_ops->flush_log_dirty = NULL;
6145 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6146 }
6147
f2c7648d 6148 return alloc_kvm_area();
34a1cd60 6149
3af18d9c 6150out8:
34a1cd60 6151 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6152out7:
34a1cd60 6153 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6154out6:
6155 if (nested)
6156 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6157out5:
6158 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6159out4:
6160 free_page((unsigned long)vmx_msr_bitmap_longmode);
6161out3:
6162 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6163out2:
6164 free_page((unsigned long)vmx_msr_bitmap_legacy);
6165out1:
6166 free_page((unsigned long)vmx_io_bitmap_b);
6167out:
6168 free_page((unsigned long)vmx_io_bitmap_a);
6169
6170 return r;
f2c7648d
TC		 6171}
6172
6173static __exit void hardware_unsetup(void)
6174{
34a1cd60
TC		 6175 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6176 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6177 free_page((unsigned long)vmx_msr_bitmap_legacy);
6178 free_page((unsigned long)vmx_msr_bitmap_longmode);
6179 free_page((unsigned long)vmx_io_bitmap_b);
6180 free_page((unsigned long)vmx_io_bitmap_a);
6181 free_page((unsigned long)vmx_vmwrite_bitmap);
6182 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6183 if (nested)
6184 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6185
f2c7648d
TC		 6186 free_kvm_area();
6187}
6188
4b8d54f9
ZE		 6189/*
6190 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6191 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6192 */
9fb41ba8 6193static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6194{
b4a2d31d
RK		 6195 if (ple_gap)
6196 grow_ple_window(vcpu);
6197
4b8d54f9
ZE		 6198 skip_emulated_instruction(vcpu);
6199 kvm_vcpu_on_spin(vcpu);
6200
6201 return 1;
6202}
6203
87c00572 6204static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6205{
87c00572 6206 skip_emulated_instruction(vcpu);
59708670
SY		 6207 return 1;
6208}
6209
87c00572
GS		 6210static int handle_mwait(struct kvm_vcpu *vcpu)
6211{
6212 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6213 return handle_nop(vcpu);
6214}
6215
5f3d45e7
MD		 6216static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6217{
6218 return 1;
6219}
6220
87c00572
GS		 6221static int handle_monitor(struct kvm_vcpu *vcpu)
6222{
6223 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6224 return handle_nop(vcpu);
6225}
6226
ff2f6fe9
NHE		 6227/*
6228 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6229 * We could reuse a single VMCS for all the L2 guests, but we also want the
6230 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6231 * allows keeping them loaded on the processor, and in the future will allow
6232 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6233 * every entry if they never change.
6234 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6235 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6236 *
6237 * The following functions allocate and free a vmcs02 in this pool.
6238 */
6239
6240/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6241static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6242{
6243 struct vmcs02_list *item;
6244 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6245 if (item->vmptr == vmx->nested.current_vmptr) {
6246 list_move(&item->list, &vmx->nested.vmcs02_pool);
6247 return &item->vmcs02;
6248 }
6249
6250 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6251 /* Recycle the least recently used VMCS. */
6252 item = list_entry(vmx->nested.vmcs02_pool.prev,
6253 struct vmcs02_list, list);
6254 item->vmptr = vmx->nested.current_vmptr;
6255 list_move(&item->list, &vmx->nested.vmcs02_pool);
6256 return &item->vmcs02;
6257 }
6258
6259 /* Create a new VMCS */
0fa24ce3 6260 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6261 if (!item)
6262 return NULL;
6263 item->vmcs02.vmcs = alloc_vmcs();
6264 if (!item->vmcs02.vmcs) {
6265 kfree(item);
6266 return NULL;
6267 }
6268 loaded_vmcs_init(&item->vmcs02);
6269 item->vmptr = vmx->nested.current_vmptr;
6270 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6271 vmx->nested.vmcs02_num++;
6272 return &item->vmcs02;
6273}
6274
6275/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6276static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6277{
6278 struct vmcs02_list *item;
6279 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6280 if (item->vmptr == vmptr) {
6281 free_loaded_vmcs(&item->vmcs02);
6282 list_del(&item->list);
6283 kfree(item);
6284 vmx->nested.vmcs02_num--;
6285 return;
6286 }
6287}
6288
6289/*
6290 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6291 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6292 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6293 */
6294static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6295{
6296 struct vmcs02_list *item, *n;
4fa7734c
PB		 6297
6298 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6299 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6300 /*
6301 * Something will leak if the above WARN triggers. Better than
6302 * a use-after-free.
6303 */
6304 if (vmx->loaded_vmcs == &item->vmcs02)
6305 continue;
6306
6307 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6308 list_del(&item->list);
6309 kfree(item);
4fa7734c 6310 vmx->nested.vmcs02_num--;
ff2f6fe9 6311 }
ff2f6fe9
NHE		 6312}
6313
0658fbaa
ACL		 6314/*
6315 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6316 * set the success or error code of an emulated VMX instruction, as specified
6317 * by Vol 2B, VMX Instruction Reference, "Conventions".
6318 */
6319static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6320{
6321 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6322 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6323 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6324}
6325
6326static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6327{
6328 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6329 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6330 X86_EFLAGS_SF | X86_EFLAGS_OF))
6331 | X86_EFLAGS_CF);
6332}
6333
145c28dd 6334static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6335 u32 vm_instruction_error)
6336{
6337 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6338 /*
6339 * failValid writes the error number to the current VMCS, which
6340 * can't be done there isn't a current VMCS.
6341 */
6342 nested_vmx_failInvalid(vcpu);
6343 return;
6344 }
6345 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6346 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6347 X86_EFLAGS_SF | X86_EFLAGS_OF))
6348 | X86_EFLAGS_ZF);
6349 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6350 /*
6351 * We don't need to force a shadow sync because
6352 * VM_INSTRUCTION_ERROR is not shadowed
6353 */
6354}
145c28dd 6355
ff651cb6
WV		 6356static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6357{
6358 /* TODO: not to reset guest simply here. */
6359 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6360 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6361}
6362
f4124500
JK		 6363static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6364{
6365 struct vcpu_vmx *vmx =
6366 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6367
6368 vmx->nested.preemption_timer_expired = true;
6369 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6370 kvm_vcpu_kick(&vmx->vcpu);
6371
6372 return HRTIMER_NORESTART;
6373}
6374
19677e32
BD		 6375/*
6376 * Decode the memory-address operand of a vmx instruction, as recorded on an
6377 * exit caused by such an instruction (run by a guest hypervisor).
6378 * On success, returns 0. When the operand is invalid, returns 1 and throws
6379 * #UD or #GP.
6380 */
6381static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6382 unsigned long exit_qualification,
f9eb4af6 6383 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6384{
f9eb4af6
EK		 6385 gva_t off;
6386 bool exn;
6387 struct kvm_segment s;
6388
19677e32
BD		 6389 /*
6390 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6391 * Execution", on an exit, vmx_instruction_info holds most of the
6392 * addressing components of the operand. Only the displacement part
6393 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6394 * For how an actual address is calculated from all these components,
6395 * refer to Vol. 1, "Operand Addressing".
6396 */
6397 int scaling = vmx_instruction_info & 3;
6398 int addr_size = (vmx_instruction_info >> 7) & 7;
6399 bool is_reg = vmx_instruction_info & (1u << 10);
6400 int seg_reg = (vmx_instruction_info >> 15) & 7;
6401 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6402 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6403 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6404 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6405
6406 if (is_reg) {
6407 kvm_queue_exception(vcpu, UD_VECTOR);
6408 return 1;
6409 }
6410
6411 /* Addr = segment_base + offset */
6412 /* offset = base + [index * scale] + displacement */
f9eb4af6 6413 off = exit_qualification; /* holds the displacement */
19677e32 6414 if (base_is_valid)
f9eb4af6 6415 off += kvm_register_read(vcpu, base_reg);
19677e32 6416 if (index_is_valid)
f9eb4af6
EK		 6417 off += kvm_register_read(vcpu, index_reg)<<scaling;
6418 vmx_get_segment(vcpu, &s, seg_reg);
6419 *ret = s.base + off;
19677e32
BD		 6420
6421 if (addr_size == 1) /* 32 bit */
6422 *ret &= 0xffffffff;
6423
f9eb4af6
EK		 6424 /* Checks for #GP/#SS exceptions. */
6425 exn = false;
6426 if (is_protmode(vcpu)) {
6427 /* Protected mode: apply checks for segment validity in the
6428 * following order:
6429 * - segment type check (#GP(0) may be thrown)
6430 * - usability check (#GP(0)/#SS(0))
6431 * - limit check (#GP(0)/#SS(0))
6432 */
6433 if (wr)
6434 /* #GP(0) if the destination operand is located in a
6435 * read-only data segment or any code segment.
6436 */
6437 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6438 else
6439 /* #GP(0) if the source operand is located in an
6440 * execute-only code segment
6441 */
6442 exn = ((s.type & 0xa) == 8);
6443 }
6444 if (exn) {
6445 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6446 return 1;
6447 }
6448 if (is_long_mode(vcpu)) {
6449 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6450 * non-canonical form. This is an only check for long mode.
6451 */
6452 exn = is_noncanonical_address(*ret);
6453 } else if (is_protmode(vcpu)) {
6454 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6455 */
6456 exn = (s.unusable != 0);
6457 /* Protected mode: #GP(0)/#SS(0) if the memory
6458 * operand is outside the segment limit.
6459 */
6460 exn = exn || (off + sizeof(u64) > s.limit);
6461 }
6462 if (exn) {
6463 kvm_queue_exception_e(vcpu,
6464 seg_reg == VCPU_SREG_SS ?
6465 SS_VECTOR : GP_VECTOR,
6466 0);
6467 return 1;
6468 }
6469
19677e32
BD		 6470 return 0;
6471}
6472
3573e22c
BD		 6473/*
6474 * This function performs the various checks including
6475 * - if it's 4KB aligned
6476 * - No bits beyond the physical address width are set
6477 * - Returns 0 on success or else 1
4291b588 6478 * (Intel SDM Section 30.3)
3573e22c 6479 */
4291b588
BD		 6480static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6481 gpa_t *vmpointer)
3573e22c
BD		 6482{
6483 gva_t gva;
6484 gpa_t vmptr;
6485 struct x86_exception e;
6486 struct page *page;
6487 struct vcpu_vmx *vmx = to_vmx(vcpu);
6488 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6489
6490 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 6491 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD		 6492 return 1;
6493
6494 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6495 sizeof(vmptr), &e)) {
6496 kvm_inject_page_fault(vcpu, &e);
6497 return 1;
6498 }
6499
6500 switch (exit_reason) {
6501 case EXIT_REASON_VMON:
6502 /*
6503 * SDM 3: 24.11.5
6504 * The first 4 bytes of VMXON region contain the supported
6505 * VMCS revision identifier
6506 *
6507 * Note - IA32_VMX_BASIC[48] will never be 1
6508 * for the nested case;
6509 * which replaces physical address width with 32
6510 *
6511 */
bc39c4db 6512 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6513 nested_vmx_failInvalid(vcpu);
6514 skip_emulated_instruction(vcpu);
6515 return 1;
6516 }
6517
6518 page = nested_get_page(vcpu, vmptr);
6519 if (page == NULL ||
6520 *(u32 *)kmap(page) != VMCS12_REVISION) {
6521 nested_vmx_failInvalid(vcpu);
6522 kunmap(page);
6523 skip_emulated_instruction(vcpu);
6524 return 1;
6525 }
6526 kunmap(page);
6527 vmx->nested.vmxon_ptr = vmptr;
6528 break;
4291b588 6529 case EXIT_REASON_VMCLEAR:
bc39c4db 6530 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6531 nested_vmx_failValid(vcpu,
6532 VMXERR_VMCLEAR_INVALID_ADDRESS);
6533 skip_emulated_instruction(vcpu);
6534 return 1;
6535 }
6536
6537 if (vmptr == vmx->nested.vmxon_ptr) {
6538 nested_vmx_failValid(vcpu,
6539 VMXERR_VMCLEAR_VMXON_POINTER);
6540 skip_emulated_instruction(vcpu);
6541 return 1;
6542 }
6543 break;
6544 case EXIT_REASON_VMPTRLD:
bc39c4db 6545 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6546 nested_vmx_failValid(vcpu,
6547 VMXERR_VMPTRLD_INVALID_ADDRESS);
6548 skip_emulated_instruction(vcpu);
6549 return 1;
6550 }
3573e22c 6551
4291b588
BD		 6552 if (vmptr == vmx->nested.vmxon_ptr) {
6553 nested_vmx_failValid(vcpu,
6554 VMXERR_VMCLEAR_VMXON_POINTER);
6555 skip_emulated_instruction(vcpu);
6556 return 1;
6557 }
6558 break;
3573e22c
BD		 6559 default:
6560 return 1; /* shouldn't happen */
6561 }
6562
4291b588
BD		 6563 if (vmpointer)
6564 *vmpointer = vmptr;
3573e22c
BD		 6565 return 0;
6566}
6567
ec378aee
NHE		 6568/*
6569 * Emulate the VMXON instruction.
6570 * Currently, we just remember that VMX is active, and do not save or even
6571 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6572 * do not currently need to store anything in that guest-allocated memory
6573 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6574 * argument is different from the VMXON pointer (which the spec says they do).
6575 */
6576static int handle_vmon(struct kvm_vcpu *vcpu)
6577{
6578 struct kvm_segment cs;
6579 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6580 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6581 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6582 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6583
6584 /* The Intel VMX Instruction Reference lists a bunch of bits that
6585 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6586 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6587 * Otherwise, we should fail with #UD. We test these now:
6588 */
6589 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6590 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6591 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6592 kvm_queue_exception(vcpu, UD_VECTOR);
6593 return 1;
6594 }
6595
6596 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6597 if (is_long_mode(vcpu) && !cs.l) {
6598 kvm_queue_exception(vcpu, UD_VECTOR);
6599 return 1;
6600 }
6601
6602 if (vmx_get_cpl(vcpu)) {
6603 kvm_inject_gp(vcpu, 0);
6604 return 1;
6605 }
3573e22c 6606
4291b588 6607 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6608 return 1;
6609
145c28dd
AG		 6610 if (vmx->nested.vmxon) {
6611 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6612 skip_emulated_instruction(vcpu);
6613 return 1;
6614 }
b3897a49
NHE		 6615
6616 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6617 != VMXON_NEEDED_FEATURES) {
6618 kvm_inject_gp(vcpu, 0);
6619 return 1;
6620 }
6621
8de48833
AG		 6622 if (enable_shadow_vmcs) {
6623 shadow_vmcs = alloc_vmcs();
6624 if (!shadow_vmcs)
6625 return -ENOMEM;
6626 /* mark vmcs as shadow */
6627 shadow_vmcs->revision_id |= (1u << 31);
6628 /* init shadow vmcs */
6629 vmcs_clear(shadow_vmcs);
6630 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6631 }
ec378aee 6632
ff2f6fe9
NHE		 6633 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6634 vmx->nested.vmcs02_num = 0;
6635
f4124500
JK		 6636 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6637 HRTIMER_MODE_REL);
6638 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6639
ec378aee
NHE		 6640 vmx->nested.vmxon = true;
6641
6642 skip_emulated_instruction(vcpu);
a25eb114 6643 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6644 return 1;
6645}
6646
6647/*
6648 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6649 * for running VMX instructions (except VMXON, whose prerequisites are
6650 * slightly different). It also specifies what exception to inject otherwise.
6651 */
6652static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6653{
6654 struct kvm_segment cs;
6655 struct vcpu_vmx *vmx = to_vmx(vcpu);
6656
6657 if (!vmx->nested.vmxon) {
6658 kvm_queue_exception(vcpu, UD_VECTOR);
6659 return 0;
6660 }
6661
6662 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6663 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6664 (is_long_mode(vcpu) && !cs.l)) {
6665 kvm_queue_exception(vcpu, UD_VECTOR);
6666 return 0;
6667 }
6668
6669 if (vmx_get_cpl(vcpu)) {
6670 kvm_inject_gp(vcpu, 0);
6671 return 0;
6672 }
6673
6674 return 1;
6675}
6676
e7953d7f
AG		 6677static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6678{
9a2a05b9
PB		 6679 if (vmx->nested.current_vmptr == -1ull)
6680 return;
6681
6682 /* current_vmptr and current_vmcs12 are always set/reset together */
6683 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6684 return;
6685
012f83cb 6686 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6687 /* copy to memory all shadowed fields in case
6688 they were modified */
6689 copy_shadow_to_vmcs12(vmx);
6690 vmx->nested.sync_shadow_vmcs = false;
7ec36296
XG		 6691 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6692 SECONDARY_EXEC_SHADOW_VMCS);
9a2a05b9 6693 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6694 }
705699a1 6695 vmx->nested.posted_intr_nv = -1;
e7953d7f
AG		 6696 kunmap(vmx->nested.current_vmcs12_page);
6697 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6698 vmx->nested.current_vmptr = -1ull;
6699 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6700}
6701
ec378aee
NHE		 6702/*
6703 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6704 * just stops using VMX.
6705 */
6706static void free_nested(struct vcpu_vmx *vmx)
6707{
6708 if (!vmx->nested.vmxon)
6709 return;
9a2a05b9 6710
ec378aee 6711 vmx->nested.vmxon = false;
9a2a05b9 6712 nested_release_vmcs12(vmx);
e7953d7f
AG		 6713 if (enable_shadow_vmcs)
6714 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6715 /* Unpin physical memory we referred to in current vmcs02 */
6716 if (vmx->nested.apic_access_page) {
6717 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6718 vmx->nested.apic_access_page = NULL;
fe3ef05c 6719 }
a7c0b07d
WL		 6720 if (vmx->nested.virtual_apic_page) {
6721 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6722 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6723 }
705699a1
WV		 6724 if (vmx->nested.pi_desc_page) {
6725 kunmap(vmx->nested.pi_desc_page);
6726 nested_release_page(vmx->nested.pi_desc_page);
6727 vmx->nested.pi_desc_page = NULL;
6728 vmx->nested.pi_desc = NULL;
6729 }
ff2f6fe9
NHE		 6730
6731 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6732}
6733
6734/* Emulate the VMXOFF instruction */
6735static int handle_vmoff(struct kvm_vcpu *vcpu)
6736{
6737 if (!nested_vmx_check_permission(vcpu))
6738 return 1;
6739 free_nested(to_vmx(vcpu));
6740 skip_emulated_instruction(vcpu);
a25eb114 6741 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6742 return 1;
6743}
6744
27d6c865
NHE		 6745/* Emulate the VMCLEAR instruction */
6746static int handle_vmclear(struct kvm_vcpu *vcpu)
6747{
6748 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6749 gpa_t vmptr;
6750 struct vmcs12 *vmcs12;
6751 struct page *page;
27d6c865
NHE		 6752
6753 if (!nested_vmx_check_permission(vcpu))
6754 return 1;
6755
4291b588 6756 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6757 return 1;
27d6c865 6758
9a2a05b9 6759 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6760 nested_release_vmcs12(vmx);
27d6c865
NHE		 6761
6762 page = nested_get_page(vcpu, vmptr);
6763 if (page == NULL) {
6764 /*
6765 * For accurate processor emulation, VMCLEAR beyond available
6766 * physical memory should do nothing at all. However, it is
6767 * possible that a nested vmx bug, not a guest hypervisor bug,
6768 * resulted in this case, so let's shut down before doing any
6769 * more damage:
6770 */
6771 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6772 return 1;
6773 }
6774 vmcs12 = kmap(page);
6775 vmcs12->launch_state = 0;
6776 kunmap(page);
6777 nested_release_page(page);
6778
6779 nested_free_vmcs02(vmx, vmptr);
6780
6781 skip_emulated_instruction(vcpu);
6782 nested_vmx_succeed(vcpu);
6783 return 1;
6784}
6785
cd232ad0
NHE		 6786static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6787
6788/* Emulate the VMLAUNCH instruction */
6789static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6790{
6791 return nested_vmx_run(vcpu, true);
6792}
6793
6794/* Emulate the VMRESUME instruction */
6795static int handle_vmresume(struct kvm_vcpu *vcpu)
6796{
6797
6798 return nested_vmx_run(vcpu, false);
6799}
6800
49f705c5
NHE		 6801enum vmcs_field_type {
6802 VMCS_FIELD_TYPE_U16 = 0,
6803 VMCS_FIELD_TYPE_U64 = 1,
6804 VMCS_FIELD_TYPE_U32 = 2,
6805 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6806};
6807
6808static inline int vmcs_field_type(unsigned long field)
6809{
6810 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6811 return VMCS_FIELD_TYPE_U32;
6812 return (field >> 13) & 0x3 ;
6813}
6814
6815static inline int vmcs_field_readonly(unsigned long field)
6816{
6817 return (((field >> 10) & 0x3) == 1);
6818}
6819
6820/*
6821 * Read a vmcs12 field. Since these can have varying lengths and we return
6822 * one type, we chose the biggest type (u64) and zero-extend the return value
6823 * to that size. Note that the caller, handle_vmread, might need to use only
6824 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6825 * 64-bit fields are to be returned).
6826 */
a2ae9df7
PB		 6827static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6828 unsigned long field, u64 *ret)
49f705c5
NHE		 6829{
6830 short offset = vmcs_field_to_offset(field);
6831 char *p;
6832
6833 if (offset < 0)
a2ae9df7 6834 return offset;
49f705c5
NHE		 6835
6836 p = ((char *)(get_vmcs12(vcpu))) + offset;
6837
6838 switch (vmcs_field_type(field)) {
6839 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6840 *ret = *((natural_width *)p);
a2ae9df7 6841 return 0;
49f705c5
NHE		 6842 case VMCS_FIELD_TYPE_U16:
6843 *ret = *((u16 *)p);
a2ae9df7 6844 return 0;
49f705c5
NHE		 6845 case VMCS_FIELD_TYPE_U32:
6846 *ret = *((u32 *)p);
a2ae9df7 6847 return 0;
49f705c5
NHE		 6848 case VMCS_FIELD_TYPE_U64:
6849 *ret = *((u64 *)p);
a2ae9df7 6850 return 0;
49f705c5 6851 default:
a2ae9df7
PB		 6852 WARN_ON(1);
6853 return -ENOENT;
49f705c5
NHE		 6854 }
6855}
6856
20b97fea 6857
a2ae9df7
PB		 6858static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6859 unsigned long field, u64 field_value){
20b97fea
AG		 6860 short offset = vmcs_field_to_offset(field);
6861 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6862 if (offset < 0)
a2ae9df7 6863 return offset;
20b97fea
AG		 6864
6865 switch (vmcs_field_type(field)) {
6866 case VMCS_FIELD_TYPE_U16:
6867 *(u16 *)p = field_value;
a2ae9df7 6868 return 0;
20b97fea
AG		 6869 case VMCS_FIELD_TYPE_U32:
6870 *(u32 *)p = field_value;
a2ae9df7 6871 return 0;
20b97fea
AG		 6872 case VMCS_FIELD_TYPE_U64:
6873 *(u64 *)p = field_value;
a2ae9df7 6874 return 0;
20b97fea
AG		 6875 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6876 *(natural_width *)p = field_value;
a2ae9df7 6877 return 0;
20b97fea 6878 default:
a2ae9df7
PB		 6879 WARN_ON(1);
6880 return -ENOENT;
20b97fea
AG		 6881 }
6882
6883}
6884
16f5b903
AG		 6885static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6886{
6887 int i;
6888 unsigned long field;
6889 u64 field_value;
6890 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6891 const unsigned long *fields = shadow_read_write_fields;
6892 const int num_fields = max_shadow_read_write_fields;
16f5b903 6893
282da870
JK		 6894 preempt_disable();
6895
16f5b903
AG		 6896 vmcs_load(shadow_vmcs);
6897
6898 for (i = 0; i < num_fields; i++) {
6899 field = fields[i];
6900 switch (vmcs_field_type(field)) {
6901 case VMCS_FIELD_TYPE_U16:
6902 field_value = vmcs_read16(field);
6903 break;
6904 case VMCS_FIELD_TYPE_U32:
6905 field_value = vmcs_read32(field);
6906 break;
6907 case VMCS_FIELD_TYPE_U64:
6908 field_value = vmcs_read64(field);
6909 break;
6910 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6911 field_value = vmcs_readl(field);
6912 break;
a2ae9df7
PB		 6913 default:
6914 WARN_ON(1);
6915 continue;
16f5b903
AG		 6916 }
6917 vmcs12_write_any(&vmx->vcpu, field, field_value);
6918 }
6919
6920 vmcs_clear(shadow_vmcs);
6921 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6922
6923 preempt_enable();
16f5b903
AG		 6924}
6925
c3114420
AG		 6926static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6927{
c2bae893
MK		 6928 const unsigned long *fields[] = {
6929 shadow_read_write_fields,
6930 shadow_read_only_fields
c3114420 6931 };
c2bae893 6932 const int max_fields[] = {
c3114420
AG		 6933 max_shadow_read_write_fields,
6934 max_shadow_read_only_fields
6935 };
6936 int i, q;
6937 unsigned long field;
6938 u64 field_value = 0;
6939 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6940
6941 vmcs_load(shadow_vmcs);
6942
c2bae893 6943 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6944 for (i = 0; i < max_fields[q]; i++) {
6945 field = fields[q][i];
6946 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6947
6948 switch (vmcs_field_type(field)) {
6949 case VMCS_FIELD_TYPE_U16:
6950 vmcs_write16(field, (u16)field_value);
6951 break;
6952 case VMCS_FIELD_TYPE_U32:
6953 vmcs_write32(field, (u32)field_value);
6954 break;
6955 case VMCS_FIELD_TYPE_U64:
6956 vmcs_write64(field, (u64)field_value);
6957 break;
6958 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6959 vmcs_writel(field, (long)field_value);
6960 break;
a2ae9df7
PB		 6961 default:
6962 WARN_ON(1);
6963 break;
c3114420
AG		 6964 }
6965 }
6966 }
6967
6968 vmcs_clear(shadow_vmcs);
6969 vmcs_load(vmx->loaded_vmcs->vmcs);
6970}
6971
49f705c5
NHE		 6972/*
6973 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6974 * used before) all generate the same failure when it is missing.
6975 */
6976static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6977{
6978 struct vcpu_vmx *vmx = to_vmx(vcpu);
6979 if (vmx->nested.current_vmptr == -1ull) {
6980 nested_vmx_failInvalid(vcpu);
6981 skip_emulated_instruction(vcpu);
6982 return 0;
6983 }
6984 return 1;
6985}
6986
6987static int handle_vmread(struct kvm_vcpu *vcpu)
6988{
6989 unsigned long field;
6990 u64 field_value;
6991 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6992 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6993 gva_t gva = 0;
6994
6995 if (!nested_vmx_check_permission(vcpu) ||
6996 !nested_vmx_check_vmcs12(vcpu))
6997 return 1;
6998
6999 /* Decode instruction info and find the field to read */
27e6fb5d 7000 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 7001 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 7002 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 7003 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7004 skip_emulated_instruction(vcpu);
7005 return 1;
7006 }
7007 /*
7008 * Now copy part of this value to register or memory, as requested.
7009 * Note that the number of bits actually copied is 32 or 64 depending
7010 * on the guest's mode (32 or 64 bit), not on the given field's length.
7011 */
7012 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 7013 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 7014 field_value);
7015 } else {
7016 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7017 vmx_instruction_info, true, &gva))
49f705c5
NHE		 7018 return 1;
7019 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7020 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7021 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7022 }
7023
7024 nested_vmx_succeed(vcpu);
7025 skip_emulated_instruction(vcpu);
7026 return 1;
7027}
7028
7029
7030static int handle_vmwrite(struct kvm_vcpu *vcpu)
7031{
7032 unsigned long field;
7033 gva_t gva;
7034 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7035 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 7036 /* The value to write might be 32 or 64 bits, depending on L1's long
7037 * mode, and eventually we need to write that into a field of several
7038 * possible lengths. The code below first zero-extends the value to 64
7039 * bit (field_value), and then copies only the approriate number of
7040 * bits into the vmcs12 field.
7041 */
7042 u64 field_value = 0;
7043 struct x86_exception e;
7044
7045 if (!nested_vmx_check_permission(vcpu) ||
7046 !nested_vmx_check_vmcs12(vcpu))
7047 return 1;
7048
7049 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7050 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 7051 (((vmx_instruction_info) >> 3) & 0xf));
7052 else {
7053 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7054 vmx_instruction_info, false, &gva))
49f705c5
NHE		 7055 return 1;
7056 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7057 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 7058 kvm_inject_page_fault(vcpu, &e);
7059 return 1;
7060 }
7061 }
7062
7063
27e6fb5d 7064 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 7065 if (vmcs_field_readonly(field)) {
7066 nested_vmx_failValid(vcpu,
7067 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7068 skip_emulated_instruction(vcpu);
7069 return 1;
7070 }
7071
a2ae9df7 7072 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 7073 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7074 skip_emulated_instruction(vcpu);
7075 return 1;
7076 }
7077
7078 nested_vmx_succeed(vcpu);
7079 skip_emulated_instruction(vcpu);
7080 return 1;
7081}
7082
63846663
NHE		 7083/* Emulate the VMPTRLD instruction */
7084static int handle_vmptrld(struct kvm_vcpu *vcpu)
7085{
7086 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7087 gpa_t vmptr;
63846663
NHE		 7088
7089 if (!nested_vmx_check_permission(vcpu))
7090 return 1;
7091
4291b588 7092 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 7093 return 1;
63846663
NHE		 7094
7095 if (vmx->nested.current_vmptr != vmptr) {
7096 struct vmcs12 *new_vmcs12;
7097 struct page *page;
7098 page = nested_get_page(vcpu, vmptr);
7099 if (page == NULL) {
7100 nested_vmx_failInvalid(vcpu);
7101 skip_emulated_instruction(vcpu);
7102 return 1;
7103 }
7104 new_vmcs12 = kmap(page);
7105 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7106 kunmap(page);
7107 nested_release_page_clean(page);
7108 nested_vmx_failValid(vcpu,
7109 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7110 skip_emulated_instruction(vcpu);
7111 return 1;
7112 }
63846663 7113
9a2a05b9 7114 nested_release_vmcs12(vmx);
63846663
NHE		 7115 vmx->nested.current_vmptr = vmptr;
7116 vmx->nested.current_vmcs12 = new_vmcs12;
7117 vmx->nested.current_vmcs12_page = page;
012f83cb 7118 if (enable_shadow_vmcs) {
7ec36296
XG		 7119 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7120 SECONDARY_EXEC_SHADOW_VMCS);
8a1b9dd0
AG		 7121 vmcs_write64(VMCS_LINK_POINTER,
7122 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 7123 vmx->nested.sync_shadow_vmcs = true;
7124 }
63846663
NHE		 7125 }
7126
7127 nested_vmx_succeed(vcpu);
7128 skip_emulated_instruction(vcpu);
7129 return 1;
7130}
7131
6a4d7550
NHE		 7132/* Emulate the VMPTRST instruction */
7133static int handle_vmptrst(struct kvm_vcpu *vcpu)
7134{
7135 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7136 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7137 gva_t vmcs_gva;
7138 struct x86_exception e;
7139
7140 if (!nested_vmx_check_permission(vcpu))
7141 return 1;
7142
7143 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7144 vmx_instruction_info, true, &vmcs_gva))
6a4d7550
NHE		 7145 return 1;
7146 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7147 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7148 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7149 sizeof(u64), &e)) {
7150 kvm_inject_page_fault(vcpu, &e);
7151 return 1;
7152 }
7153 nested_vmx_succeed(vcpu);
7154 skip_emulated_instruction(vcpu);
7155 return 1;
7156}
7157
bfd0a56b
NHE		 7158/* Emulate the INVEPT instruction */
7159static int handle_invept(struct kvm_vcpu *vcpu)
7160{
b9c237bb 7161 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7162 u32 vmx_instruction_info, types;
7163 unsigned long type;
7164 gva_t gva;
7165 struct x86_exception e;
7166 struct {
7167 u64 eptp, gpa;
7168 } operand;
bfd0a56b 7169
b9c237bb
WV		 7170 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7171 SECONDARY_EXEC_ENABLE_EPT) ||
7172 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7173 kvm_queue_exception(vcpu, UD_VECTOR);
7174 return 1;
7175 }
7176
7177 if (!nested_vmx_check_permission(vcpu))
7178 return 1;
7179
7180 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7181 kvm_queue_exception(vcpu, UD_VECTOR);
7182 return 1;
7183 }
7184
7185 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7186 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7187
b9c237bb 7188 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7189
7190 if (!(types & (1UL << type))) {
7191 nested_vmx_failValid(vcpu,
7192 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7193 return 1;
7194 }
7195
7196 /* According to the Intel VMX instruction reference, the memory
7197 * operand is read even if it isn't needed (e.g., for type==global)
7198 */
7199 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7200 vmx_instruction_info, false, &gva))
bfd0a56b
NHE		 7201 return 1;
7202 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7203 sizeof(operand), &e)) {
7204 kvm_inject_page_fault(vcpu, &e);
7205 return 1;
7206 }
7207
7208 switch (type) {
bfd0a56b
NHE		 7209 case VMX_EPT_EXTENT_GLOBAL:
7210 kvm_mmu_sync_roots(vcpu);
77c3913b 7211 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7212 nested_vmx_succeed(vcpu);
7213 break;
7214 default:
4b855078 7215 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7216 BUG_ON(1);
7217 break;
7218 }
7219
7220 skip_emulated_instruction(vcpu);
7221 return 1;
7222}
7223
a642fc30
PM		 7224static int handle_invvpid(struct kvm_vcpu *vcpu)
7225{
7226 kvm_queue_exception(vcpu, UD_VECTOR);
7227 return 1;
7228}
7229
843e4330
KH		 7230static int handle_pml_full(struct kvm_vcpu *vcpu)
7231{
7232 unsigned long exit_qualification;
7233
7234 trace_kvm_pml_full(vcpu->vcpu_id);
7235
7236 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7237
7238 /*
7239 * PML buffer FULL happened while executing iret from NMI,
7240 * "blocked by NMI" bit has to be set before next VM entry.
7241 */
7242 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7243 cpu_has_virtual_nmis() &&
7244 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7245 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7246 GUEST_INTR_STATE_NMI);
7247
7248 /*
7249 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7250 * here.., and there's no userspace involvement needed for PML.
7251 */
7252 return 1;
7253}
7254
8b3e34e4
XG		 7255static int handle_pcommit(struct kvm_vcpu *vcpu)
7256{
7257 /* we never catch pcommit instruct for L1 guest. */
7258 WARN_ON(1);
7259 return 1;
7260}
7261
6aa8b732
AK		 7262/*
7263 * The exit handlers return 1 if the exit was handled fully and guest execution
7264 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7265 * to be done to userspace and return 0.
7266 */
772e0318 7267static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7268 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7269 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7270 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7271 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7272 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7273 [EXIT_REASON_CR_ACCESS] = handle_cr,
7274 [EXIT_REASON_DR_ACCESS] = handle_dr,
7275 [EXIT_REASON_CPUID] = handle_cpuid,
7276 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7277 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7278 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7279 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7280 [EXIT_REASON_INVD] = handle_invd,
a7052897 7281 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7282 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7283 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7284 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7285 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7286 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7287 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7288 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7289 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7290 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7291 [EXIT_REASON_VMOFF] = handle_vmoff,
7292 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7293 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7294 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7295 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7296 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7297 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7298 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7299 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7300 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7301 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7302 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7303 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7304 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7305 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7306 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7307 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7308 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7309 [EXIT_REASON_XSAVES] = handle_xsaves,
7310 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7311 [EXIT_REASON_PML_FULL] = handle_pml_full,
8b3e34e4 7312 [EXIT_REASON_PCOMMIT] = handle_pcommit,
6aa8b732
AK		 7313};
7314
7315static const int kvm_vmx_max_exit_handlers =
50a3485c 7316 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7317
908a7bdd
JK		 7318static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7319 struct vmcs12 *vmcs12)
7320{
7321 unsigned long exit_qualification;
7322 gpa_t bitmap, last_bitmap;
7323 unsigned int port;
7324 int size;
7325 u8 b;
7326
908a7bdd 7327 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7328 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7329
7330 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7331
7332 port = exit_qualification >> 16;
7333 size = (exit_qualification & 7) + 1;
7334
7335 last_bitmap = (gpa_t)-1;
7336 b = -1;
7337
7338 while (size > 0) {
7339 if (port < 0x8000)
7340 bitmap = vmcs12->io_bitmap_a;
7341 else if (port < 0x10000)
7342 bitmap = vmcs12->io_bitmap_b;
7343 else
1d804d07 7344 return true;
908a7bdd
JK		 7345 bitmap += (port & 0x7fff) / 8;
7346
7347 if (last_bitmap != bitmap)
54bf36aa 7348 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7349 return true;
908a7bdd 7350 if (b & (1 << (port & 7)))
1d804d07 7351 return true;
908a7bdd
JK		 7352
7353 port++;
7354 size--;
7355 last_bitmap = bitmap;
7356 }
7357
1d804d07 7358 return false;
908a7bdd
JK		 7359}
7360
644d711a
NHE		 7361/*
7362 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7363 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7364 * disinterest in the current event (read or write a specific MSR) by using an
7365 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7366 */
7367static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7368 struct vmcs12 *vmcs12, u32 exit_reason)
7369{
7370 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7371 gpa_t bitmap;
7372
cbd29cb6 7373 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7374 return true;
644d711a
NHE		 7375
7376 /*
7377 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7378 * for the four combinations of read/write and low/high MSR numbers.
7379 * First we need to figure out which of the four to use:
7380 */
7381 bitmap = vmcs12->msr_bitmap;
7382 if (exit_reason == EXIT_REASON_MSR_WRITE)
7383 bitmap += 2048;
7384 if (msr_index >= 0xc0000000) {
7385 msr_index -= 0xc0000000;
7386 bitmap += 1024;
7387 }
7388
7389 /* Then read the msr_index'th bit from this bitmap: */
7390 if (msr_index < 1024*8) {
7391 unsigned char b;
54bf36aa 7392 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7393 return true;
644d711a
NHE		 7394 return 1 & (b >> (msr_index & 7));
7395 } else
1d804d07 7396 return true; /* let L1 handle the wrong parameter */
644d711a
NHE		 7397}
7398
7399/*
7400 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7401 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7402 * intercept (via guest_host_mask etc.) the current event.
7403 */
7404static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7405 struct vmcs12 *vmcs12)
7406{
7407 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7408 int cr = exit_qualification & 15;
7409 int reg = (exit_qualification >> 8) & 15;
1e32c079 7410 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7411
7412 switch ((exit_qualification >> 4) & 3) {
7413 case 0: /* mov to cr */
7414 switch (cr) {
7415 case 0:
7416 if (vmcs12->cr0_guest_host_mask &
7417 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7418 return true;
644d711a
NHE		 7419 break;
7420 case 3:
7421 if ((vmcs12->cr3_target_count >= 1 &&
7422 vmcs12->cr3_target_value0 == val) ||
7423 (vmcs12->cr3_target_count >= 2 &&
7424 vmcs12->cr3_target_value1 == val) ||
7425 (vmcs12->cr3_target_count >= 3 &&
7426 vmcs12->cr3_target_value2 == val) ||
7427 (vmcs12->cr3_target_count >= 4 &&
7428 vmcs12->cr3_target_value3 == val))
1d804d07 7429 return false;
644d711a 7430 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7431 return true;
644d711a
NHE		 7432 break;
7433 case 4:
7434 if (vmcs12->cr4_guest_host_mask &
7435 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7436 return true;
644d711a
NHE		 7437 break;
7438 case 8:
7439 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7440 return true;
644d711a
NHE		 7441 break;
7442 }
7443 break;
7444 case 2: /* clts */
7445 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7446 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7447 return true;
644d711a
NHE		 7448 break;
7449 case 1: /* mov from cr */
7450 switch (cr) {
7451 case 3:
7452 if (vmcs12->cpu_based_vm_exec_control &
7453 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7454 return true;
644d711a
NHE		 7455 break;
7456 case 8:
7457 if (vmcs12->cpu_based_vm_exec_control &
7458 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7459 return true;
644d711a
NHE		 7460 break;
7461 }
7462 break;
7463 case 3: /* lmsw */
7464 /*
7465 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7466 * cr0. Other attempted changes are ignored, with no exit.
7467 */
7468 if (vmcs12->cr0_guest_host_mask & 0xe &
7469 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7470 return true;
644d711a
NHE		 7471 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7472 !(vmcs12->cr0_read_shadow & 0x1) &&
7473 (val & 0x1))
1d804d07 7474 return true;
644d711a
NHE		 7475 break;
7476 }
1d804d07 7477 return false;
644d711a
NHE		 7478}
7479
7480/*
7481 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7482 * should handle it ourselves in L0 (and then continue L2). Only call this
7483 * when in is_guest_mode (L2).
7484 */
7485static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7486{
644d711a
NHE		 7487 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7488 struct vcpu_vmx *vmx = to_vmx(vcpu);
7489 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7490 u32 exit_reason = vmx->exit_reason;
644d711a 7491
542060ea
JK		 7492 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7493 vmcs_readl(EXIT_QUALIFICATION),
7494 vmx->idt_vectoring_info,
7495 intr_info,
7496 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7497 KVM_ISA_VMX);
7498
644d711a 7499 if (vmx->nested.nested_run_pending)
1d804d07 7500 return false;
644d711a
NHE		 7501
7502 if (unlikely(vmx->fail)) {
bd80158a
JK		 7503 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7504 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 7505 return true;
644d711a
NHE		 7506 }
7507
7508 switch (exit_reason) {
7509 case EXIT_REASON_EXCEPTION_NMI:
7510 if (!is_exception(intr_info))
1d804d07 7511 return false;
644d711a
NHE		 7512 else if (is_page_fault(intr_info))
7513 return enable_ept;
e504c909 7514 else if (is_no_device(intr_info) &&
ccf9844e 7515 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 7516 return false;
644d711a
NHE		 7517 return vmcs12->exception_bitmap &
7518 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7519 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 7520 return false;
644d711a 7521 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 7522 return true;
644d711a 7523 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7524 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7525 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7526 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 7527 case EXIT_REASON_TASK_SWITCH:
1d804d07 7528 return true;
644d711a 7529 case EXIT_REASON_CPUID:
bc613494 7530 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
1d804d07
JP		 7531 return false;
7532 return true;
644d711a
NHE		 7533 case EXIT_REASON_HLT:
7534 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7535 case EXIT_REASON_INVD:
1d804d07 7536 return true;
644d711a
NHE		 7537 case EXIT_REASON_INVLPG:
7538 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7539 case EXIT_REASON_RDPMC:
7540 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
b3a2a907 7541 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE		 7542 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7543 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7544 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7545 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7546 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7547 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7548 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7549 /*
7550 * VMX instructions trap unconditionally. This allows L1 to
7551 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7552 */
1d804d07 7553 return true;
644d711a
NHE		 7554 case EXIT_REASON_CR_ACCESS:
7555 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7556 case EXIT_REASON_DR_ACCESS:
7557 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7558 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7559 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7560 case EXIT_REASON_MSR_READ:
7561 case EXIT_REASON_MSR_WRITE:
7562 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7563 case EXIT_REASON_INVALID_STATE:
1d804d07 7564 return true;
644d711a
NHE		 7565 case EXIT_REASON_MWAIT_INSTRUCTION:
7566 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD		 7567 case EXIT_REASON_MONITOR_TRAP_FLAG:
7568 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE		 7569 case EXIT_REASON_MONITOR_INSTRUCTION:
7570 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7571 case EXIT_REASON_PAUSE_INSTRUCTION:
7572 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7573 nested_cpu_has2(vmcs12,
7574 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7575 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 7576 return false;
644d711a 7577 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7578 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7579 case EXIT_REASON_APIC_ACCESS:
7580 return nested_cpu_has2(vmcs12,
7581 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 7582 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 7583 case EXIT_REASON_EOI_INDUCED:
7584 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 7585 return true;
644d711a 7586 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7587 /*
7588 * L0 always deals with the EPT violation. If nested EPT is
7589 * used, and the nested mmu code discovers that the address is
7590 * missing in the guest EPT table (EPT12), the EPT violation
7591 * will be injected with nested_ept_inject_page_fault()
7592 */
1d804d07 7593 return false;
644d711a 7594 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7595 /*
7596 * L2 never uses directly L1's EPT, but rather L0's own EPT
7597 * table (shadow on EPT) or a merged EPT table that L0 built
7598 * (EPT on EPT). So any problems with the structure of the
7599 * table is L0's fault.
7600 */
1d804d07 7601 return false;
644d711a
NHE		 7602 case EXIT_REASON_WBINVD:
7603 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7604 case EXIT_REASON_XSETBV:
1d804d07 7605 return true;
81dc01f7
WL		 7606 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7607 /*
7608 * This should never happen, since it is not possible to
7609 * set XSS to a non-zero value---neither in L1 nor in L2.
7610 * If if it were, XSS would have to be checked against
7611 * the XSS exit bitmap in vmcs12.
7612 */
7613 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8b3e34e4
XG		 7614 case EXIT_REASON_PCOMMIT:
7615 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
644d711a 7616 default:
1d804d07 7617 return true;
644d711a
NHE		 7618 }
7619}
7620
586f9607
AK		 7621static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7622{
7623 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7624 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7625}
7626
843e4330
KH		 7627static int vmx_enable_pml(struct vcpu_vmx *vmx)
7628{
7629 struct page *pml_pg;
843e4330
KH		 7630
7631 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7632 if (!pml_pg)
7633 return -ENOMEM;
7634
7635 vmx->pml_pg = pml_pg;
7636
7637 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7638 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7639
7ec36296 7640 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_ENABLE_PML);
843e4330
KH		 7641
7642 return 0;
7643}
7644
7645static void vmx_disable_pml(struct vcpu_vmx *vmx)
7646{
843e4330
KH		 7647 ASSERT(vmx->pml_pg);
7648 __free_page(vmx->pml_pg);
7649 vmx->pml_pg = NULL;
7650
7ec36296 7651 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_ENABLE_PML);
843e4330
KH		 7652}
7653
54bf36aa 7654static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 7655{
54bf36aa 7656 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH		 7657 u64 *pml_buf;
7658 u16 pml_idx;
7659
7660 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7661
7662 /* Do nothing if PML buffer is empty */
7663 if (pml_idx == (PML_ENTITY_NUM - 1))
7664 return;
7665
7666 /* PML index always points to next available PML buffer entity */
7667 if (pml_idx >= PML_ENTITY_NUM)
7668 pml_idx = 0;
7669 else
7670 pml_idx++;
7671
7672 pml_buf = page_address(vmx->pml_pg);
7673 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7674 u64 gpa;
7675
7676 gpa = pml_buf[pml_idx];
7677 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 7678 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH		 7679 }
7680
7681 /* reset PML index */
7682 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7683}
7684
7685/*
7686 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7687 * Called before reporting dirty_bitmap to userspace.
7688 */
7689static void kvm_flush_pml_buffers(struct kvm *kvm)
7690{
7691 int i;
7692 struct kvm_vcpu *vcpu;
7693 /*
7694 * We only need to kick vcpu out of guest mode here, as PML buffer
7695 * is flushed at beginning of all VMEXITs, and it's obvious that only
7696 * vcpus running in guest are possible to have unflushed GPAs in PML
7697 * buffer.
7698 */
7699 kvm_for_each_vcpu(i, vcpu, kvm)
7700 kvm_vcpu_kick(vcpu);
7701}
7702
4eb64dce
PB		 7703static void vmx_dump_sel(char *name, uint32_t sel)
7704{
7705 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7706 name, vmcs_read32(sel),
7707 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7708 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7709 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7710}
7711
7712static void vmx_dump_dtsel(char *name, uint32_t limit)
7713{
7714 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7715 name, vmcs_read32(limit),
7716 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7717}
7718
7719static void dump_vmcs(void)
7720{
7721 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7722 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7723 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7724 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7725 u32 secondary_exec_control = 0;
7726 unsigned long cr4 = vmcs_readl(GUEST_CR4);
7727 u64 efer = vmcs_readl(GUEST_IA32_EFER);
7728 int i, n;
7729
7730 if (cpu_has_secondary_exec_ctrls())
7731 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7732
7733 pr_err("*** Guest State ***\n");
7734 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7735 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7736 vmcs_readl(CR0_GUEST_HOST_MASK));
7737 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7738 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7739 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7740 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7741 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7742 {
7743 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7744 vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7745 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7746 vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7747 }
7748 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7749 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7750 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7751 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7752 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7753 vmcs_readl(GUEST_SYSENTER_ESP),
7754 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7755 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
7756 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
7757 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
7758 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
7759 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
7760 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
7761 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7762 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7763 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7764 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
7765 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7766 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7767 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7768 efer, vmcs_readl(GUEST_IA32_PAT));
7769 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7770 vmcs_readl(GUEST_IA32_DEBUGCTL),
7771 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7772 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7773 pr_err("PerfGlobCtl = 0x%016lx\n",
7774 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7775 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7776 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7777 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7778 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7779 vmcs_read32(GUEST_ACTIVITY_STATE));
7780 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7781 pr_err("InterruptStatus = %04x\n",
7782 vmcs_read16(GUEST_INTR_STATUS));
7783
7784 pr_err("*** Host State ***\n");
7785 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7786 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7787 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7788 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7789 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7790 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7791 vmcs_read16(HOST_TR_SELECTOR));
7792 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7793 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7794 vmcs_readl(HOST_TR_BASE));
7795 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7796 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7797 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7798 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7799 vmcs_readl(HOST_CR4));
7800 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7801 vmcs_readl(HOST_IA32_SYSENTER_ESP),
7802 vmcs_read32(HOST_IA32_SYSENTER_CS),
7803 vmcs_readl(HOST_IA32_SYSENTER_EIP));
7804 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7805 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7806 vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7807 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7808 pr_err("PerfGlobCtl = 0x%016lx\n",
7809 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7810
7811 pr_err("*** Control State ***\n");
7812 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7813 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7814 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7815 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7816 vmcs_read32(EXCEPTION_BITMAP),
7817 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7818 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7819 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7820 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7821 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
7822 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
7823 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
7824 vmcs_read32(VM_EXIT_INTR_INFO),
7825 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7826 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
7827 pr_err(" reason=%08x qualification=%016lx\n",
7828 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
7829 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
7830 vmcs_read32(IDT_VECTORING_INFO_FIELD),
7831 vmcs_read32(IDT_VECTORING_ERROR_CODE));
7832 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
7833 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
7834 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
7835 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
7836 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
7837 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
7838 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
7839 n = vmcs_read32(CR3_TARGET_COUNT);
7840 for (i = 0; i + 1 < n; i += 4)
7841 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
7842 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
7843 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
7844 if (i < n)
7845 pr_err("CR3 target%u=%016lx\n",
7846 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
7847 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
7848 pr_err("PLE Gap=%08x Window=%08x\n",
7849 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
7850 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
7851 pr_err("Virtual processor ID = 0x%04x\n",
7852 vmcs_read16(VIRTUAL_PROCESSOR_ID));
7853}
7854
6aa8b732
AK		 7855/*
7856 * The guest has exited. See if we can fix it or if we need userspace
7857 * assistance.
7858 */
851ba692 7859static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7860{
29bd8a78 7861 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7862 u32 exit_reason = vmx->exit_reason;
1155f76a 7863 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7864
843e4330
KH		 7865 /*
7866 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7867 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7868 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7869 * mode as if vcpus is in root mode, the PML buffer must has been
7870 * flushed already.
7871 */
7872 if (enable_pml)
54bf36aa 7873 vmx_flush_pml_buffer(vcpu);
843e4330 7874
80ced186 7875 /* If guest state is invalid, start emulating */
14168786 7876 if (vmx->emulation_required)
80ced186 7877 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7878
644d711a 7879 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7880 nested_vmx_vmexit(vcpu, exit_reason,
7881 vmcs_read32(VM_EXIT_INTR_INFO),
7882 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7883 return 1;
7884 }
7885
5120702e 7886 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 7887 dump_vmcs();
5120702e
MG		 7888 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7889 vcpu->run->fail_entry.hardware_entry_failure_reason
7890 = exit_reason;
7891 return 0;
7892 }
7893
29bd8a78 7894 if (unlikely(vmx->fail)) {
851ba692
AK		 7895 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7896 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7897 = vmcs_read32(VM_INSTRUCTION_ERROR);
7898 return 0;
7899 }
6aa8b732 7900
b9bf6882
XG		 7901 /*
7902 * Note:
7903 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7904 * delivery event since it indicates guest is accessing MMIO.
7905 * The vm-exit can be triggered again after return to guest that
7906 * will cause infinite loop.
7907 */
d77c26fc 7908 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7909 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7910 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7911 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7912 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7913 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7914 vcpu->run->internal.ndata = 2;
7915 vcpu->run->internal.data[0] = vectoring_info;
7916 vcpu->run->internal.data[1] = exit_reason;
7917 return 0;
7918 }
3b86cd99 7919
644d711a
NHE		 7920 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7921 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7922 get_vmcs12(vcpu))))) {
c4282df9 7923 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7924 vmx->soft_vnmi_blocked = 0;
3b86cd99 7925 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7926 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7927 /*
7928 * This CPU don't support us in finding the end of an
7929 * NMI-blocked window if the guest runs with IRQs
7930 * disabled. So we pull the trigger after 1 s of
7931 * futile waiting, but inform the user about this.
7932 */
7933 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7934 "state on VCPU %d after 1 s timeout\n",
7935 __func__, vcpu->vcpu_id);
7936 vmx->soft_vnmi_blocked = 0;
3b86cd99 7937 }
3b86cd99
JK		 7938 }
7939
6aa8b732
AK		 7940 if (exit_reason < kvm_vmx_max_exit_handlers
7941 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7942 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7943 else {
2bc19dc3
MT		 7944 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7945 kvm_queue_exception(vcpu, UD_VECTOR);
7946 return 1;
6aa8b732 7947 }
6aa8b732
AK		 7948}
7949
95ba8273 7950static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7951{
a7c0b07d
WL		 7952 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7953
7954 if (is_guest_mode(vcpu) &&
7955 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7956 return;
7957
95ba8273 7958 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7959 vmcs_write32(TPR_THRESHOLD, 0);
7960 return;
7961 }
7962
95ba8273 7963 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7964}
7965
8d14695f
YZ		 7966static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7967{
7968 u32 sec_exec_control;
7969
7970 /*
7971 * There is not point to enable virtualize x2apic without enable
7972 * apicv
7973 */
c7c9c56c 7974 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
35754c98 7975 !vmx_cpu_uses_apicv(vcpu))
8d14695f
YZ		 7976 return;
7977
35754c98 7978 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ		 7979 return;
7980
7981 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7982
7983 if (set) {
7984 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7985 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7986 } else {
7987 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7988 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7989 }
7990 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7991
7992 vmx_set_msr_bitmap(vcpu);
7993}
7994
38b99173
TC		 7995static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7996{
7997 struct vcpu_vmx *vmx = to_vmx(vcpu);
7998
7999 /*
8000 * Currently we do not handle the nested case where L2 has an
8001 * APIC access page of its own; that page is still pinned.
8002 * Hence, we skip the case where the VCPU is in guest mode _and_
8003 * L1 prepared an APIC access page for L2.
8004 *
8005 * For the case where L1 and L2 share the same APIC access page
8006 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8007 * in the vmcs12), this function will only update either the vmcs01
8008 * or the vmcs02. If the former, the vmcs02 will be updated by
8009 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8010 * the next L2->L1 exit.
8011 */
8012 if (!is_guest_mode(vcpu) ||
8013 !nested_cpu_has2(vmx->nested.current_vmcs12,
8014 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8015 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8016}
8017
c7c9c56c
YZ		 8018static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8019{
8020 u16 status;
8021 u8 old;
8022
c7c9c56c
YZ		 8023 if (isr == -1)
8024 isr = 0;
8025
8026 status = vmcs_read16(GUEST_INTR_STATUS);
8027 old = status >> 8;
8028 if (isr != old) {
8029 status &= 0xff;
8030 status |= isr << 8;
8031 vmcs_write16(GUEST_INTR_STATUS, status);
8032 }
8033}
8034
8035static void vmx_set_rvi(int vector)
8036{
8037 u16 status;
8038 u8 old;
8039
4114c27d
WW		 8040 if (vector == -1)
8041 vector = 0;
8042
c7c9c56c
YZ		 8043 status = vmcs_read16(GUEST_INTR_STATUS);
8044 old = (u8)status & 0xff;
8045 if ((u8)vector != old) {
8046 status &= ~0xff;
8047 status |= (u8)vector;
8048 vmcs_write16(GUEST_INTR_STATUS, status);
8049 }
8050}
8051
8052static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8053{
4114c27d
WW		 8054 if (!is_guest_mode(vcpu)) {
8055 vmx_set_rvi(max_irr);
8056 return;
8057 }
8058
c7c9c56c
YZ		 8059 if (max_irr == -1)
8060 return;
8061
963fee16 8062 /*
4114c27d
WW		 8063 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8064 * handles it.
963fee16 8065 */
4114c27d 8066 if (nested_exit_on_intr(vcpu))
963fee16
WL		 8067 return;
8068
963fee16 8069 /*
4114c27d 8070 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 8071 * is run without virtual interrupt delivery.
8072 */
8073 if (!kvm_event_needs_reinjection(vcpu) &&
8074 vmx_interrupt_allowed(vcpu)) {
8075 kvm_queue_interrupt(vcpu, max_irr, false);
8076 vmx_inject_irq(vcpu);
8077 }
c7c9c56c
YZ		 8078}
8079
3bb345f3 8080static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
c7c9c56c 8081{
3bb345f3 8082 u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
35754c98 8083 if (!vmx_cpu_uses_apicv(vcpu))
3d81bc7e
YZ		 8084 return;
8085
c7c9c56c
YZ		 8086 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8087 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8088 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8089 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8090}
8091
51aa01d1 8092static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8093{
00eba012
AK		 8094 u32 exit_intr_info;
8095
8096 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8097 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8098 return;
8099
c5ca8e57 8100 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 8101 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 8102
8103 /* Handle machine checks before interrupts are enabled */
00eba012 8104 if (is_machine_check(exit_intr_info))
a0861c02
AK		 8105 kvm_machine_check();
8106
20f65983 8107 /* We need to handle NMIs before interrupts are enabled */
00eba012 8108 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 8109 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8110 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8111 asm("int $2");
ff9d07a0
ZY		 8112 kvm_after_handle_nmi(&vmx->vcpu);
8113 }
51aa01d1 8114}
20f65983 8115
a547c6db
YZ		 8116static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8117{
8118 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8119
8120 /*
8121 * If external interrupt exists, IF bit is set in rflags/eflags on the
8122 * interrupt stack frame, and interrupt will be enabled on a return
8123 * from interrupt handler.
8124 */
8125 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8126 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8127 unsigned int vector;
8128 unsigned long entry;
8129 gate_desc *desc;
8130 struct vcpu_vmx *vmx = to_vmx(vcpu);
8131#ifdef CONFIG_X86_64
8132 unsigned long tmp;
8133#endif
8134
8135 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8136 desc = (gate_desc *)vmx->host_idt_base + vector;
8137 entry = gate_offset(*desc);
8138 asm volatile(
8139#ifdef CONFIG_X86_64
8140 "mov %%" _ASM_SP ", %[sp]\n\t"
8141 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8142 "push $%c[ss]\n\t"
8143 "push %[sp]\n\t"
8144#endif
8145 "pushf\n\t"
8146 "orl $0x200, (%%" _ASM_SP ")\n\t"
8147 __ASM_SIZE(push) " $%c[cs]\n\t"
8148 "call *%[entry]\n\t"
8149 :
8150#ifdef CONFIG_X86_64
8151 [sp]"=&r"(tmp)
8152#endif
8153 :
8154 [entry]"r"(entry),
8155 [ss]"i"(__KERNEL_DS),
8156 [cs]"i"(__KERNEL_CS)
8157 );
8158 } else
8159 local_irq_enable();
8160}
8161
6d396b55
PB		 8162static bool vmx_has_high_real_mode_segbase(void)
8163{
8164 return enable_unrestricted_guest || emulate_invalid_guest_state;
8165}
8166
da8999d3
LJ		 8167static bool vmx_mpx_supported(void)
8168{
8169 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8170 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8171}
8172
55412b2e
WL		 8173static bool vmx_xsaves_supported(void)
8174{
8175 return vmcs_config.cpu_based_2nd_exec_ctrl &
8176 SECONDARY_EXEC_XSAVES;
8177}
8178
51aa01d1
AK		 8179static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8180{
c5ca8e57 8181 u32 exit_intr_info;
51aa01d1
AK		 8182 bool unblock_nmi;
8183 u8 vector;
8184 bool idtv_info_valid;
8185
8186 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8187
cf393f75 8188 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 8189 if (vmx->nmi_known_unmasked)
8190 return;
c5ca8e57
AK		 8191 /*
8192 * Can't use vmx->exit_intr_info since we're not sure what
8193 * the exit reason is.
8194 */
8195 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 8196 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8197 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8198 /*
7b4a25cb 8199 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 8200 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8201 * a guest IRET fault.
7b4a25cb
GN		 8202 * SDM 3: 23.2.2 (September 2008)
8203 * Bit 12 is undefined in any of the following cases:
8204 * If the VM exit sets the valid bit in the IDT-vectoring
8205 * information field.
8206 * If the VM exit is due to a double fault.
cf393f75 8207 */
7b4a25cb
GN		 8208 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8209 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 8210 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8211 GUEST_INTR_STATE_NMI);
9d58b931
AK		 8212 else
8213 vmx->nmi_known_unmasked =
8214 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8215 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 8216 } else if (unlikely(vmx->soft_vnmi_blocked))
8217 vmx->vnmi_blocked_time +=
8218 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 8219}
8220
3ab66e8a 8221static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 8222 u32 idt_vectoring_info,
8223 int instr_len_field,
8224 int error_code_field)
51aa01d1 8225{
51aa01d1
AK		 8226 u8 vector;
8227 int type;
8228 bool idtv_info_valid;
8229
8230 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8231
3ab66e8a
JK		 8232 vcpu->arch.nmi_injected = false;
8233 kvm_clear_exception_queue(vcpu);
8234 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 8235
8236 if (!idtv_info_valid)
8237 return;
8238
3ab66e8a 8239 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8240
668f612f
AK		 8241 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8242 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8243
64a7ec06 8244 switch (type) {
37b96e98 8245 case INTR_TYPE_NMI_INTR:
3ab66e8a 8246 vcpu->arch.nmi_injected = true;
668f612f 8247 /*
7b4a25cb 8248 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 8249 * Clear bit "block by NMI" before VM entry if a NMI
8250 * delivery faulted.
668f612f 8251 */
3ab66e8a 8252 vmx_set_nmi_mask(vcpu, false);
37b96e98 8253 break;
37b96e98 8254 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8255 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 8256 /* fall through */
8257 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8258 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8259 u32 err = vmcs_read32(error_code_field);
851eb667 8260 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8261 } else
851eb667 8262 kvm_requeue_exception(vcpu, vector);
37b96e98 8263 break;
66fd3f7f 8264 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8265 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8266 /* fall through */
37b96e98 8267 case INTR_TYPE_EXT_INTR:
3ab66e8a 8268 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 8269 break;
8270 default:
8271 break;
f7d9238f 8272 }
cf393f75
AK		 8273}
8274
83422e17
AK		 8275static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8276{
3ab66e8a 8277 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8278 VM_EXIT_INSTRUCTION_LEN,
8279 IDT_VECTORING_ERROR_CODE);
8280}
8281
b463a6f7
AK		 8282static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8283{
3ab66e8a 8284 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8285 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8286 VM_ENTRY_INSTRUCTION_LEN,
8287 VM_ENTRY_EXCEPTION_ERROR_CODE);
8288
8289 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8290}
8291
d7cd9796
GN		 8292static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8293{
8294 int i, nr_msrs;
8295 struct perf_guest_switch_msr *msrs;
8296
8297 msrs = perf_guest_get_msrs(&nr_msrs);
8298
8299 if (!msrs)
8300 return;
8301
8302 for (i = 0; i < nr_msrs; i++)
8303 if (msrs[i].host == msrs[i].guest)
8304 clear_atomic_switch_msr(vmx, msrs[i].msr);
8305 else
8306 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8307 msrs[i].host);
8308}
8309
a3b5ba49 8310static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8311{
a2fa3e9f 8312 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8313 unsigned long debugctlmsr, cr4;
104f226b
AK		 8314
8315 /* Record the guest's net vcpu time for enforced NMI injections. */
8316 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8317 vmx->entry_time = ktime_get();
8318
8319 /* Don't enter VMX if guest state is invalid, let the exit handler
8320 start emulation until we arrive back to a valid state */
14168786 8321 if (vmx->emulation_required)
104f226b
AK		 8322 return;
8323
a7653ecd
RK		 8324 if (vmx->ple_window_dirty) {
8325 vmx->ple_window_dirty = false;
8326 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8327 }
8328
012f83cb
AG		 8329 if (vmx->nested.sync_shadow_vmcs) {
8330 copy_vmcs12_to_shadow(vmx);
8331 vmx->nested.sync_shadow_vmcs = false;
8332 }
8333
104f226b
AK		 8334 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8335 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8336 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8337 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8338
1e02ce4c 8339 cr4 = cr4_read_shadow();
d974baa3
AL		 8340 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8341 vmcs_writel(HOST_CR4, cr4);
8342 vmx->host_state.vmcs_host_cr4 = cr4;
8343 }
8344
104f226b
AK		 8345 /* When single-stepping over STI and MOV SS, we must clear the
8346 * corresponding interruptibility bits in the guest state. Otherwise
8347 * vmentry fails as it then expects bit 14 (BS) in pending debug
8348 * exceptions being set, but that's not correct for the guest debugging
8349 * case. */
8350 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8351 vmx_set_interrupt_shadow(vcpu, 0);
8352
d7cd9796 8353 atomic_switch_perf_msrs(vmx);
2a7921b7 8354 debugctlmsr = get_debugctlmsr();
d7cd9796 8355
d462b819 8356 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8357 asm(
6aa8b732 8358 /* Store host registers */
b188c81f
AK		 8359 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8360 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8361 "push %%" _ASM_CX " \n\t"
8362 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8363 "je 1f \n\t"
b188c81f 8364 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8365 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8366 "1: \n\t"
d3edefc0 8367 /* Reload cr2 if changed */
b188c81f
AK		 8368 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8369 "mov %%cr2, %%" _ASM_DX " \n\t"
8370 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8371 "je 2f \n\t"
b188c81f 8372 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8373 "2: \n\t"
6aa8b732 8374 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8375 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8376 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8377 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8378 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8379 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8380 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8381 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8382 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8383#ifdef CONFIG_X86_64
e08aa78a
AK		 8384 "mov %c[r8](%0), %%r8 \n\t"
8385 "mov %c[r9](%0), %%r9 \n\t"
8386 "mov %c[r10](%0), %%r10 \n\t"
8387 "mov %c[r11](%0), %%r11 \n\t"
8388 "mov %c[r12](%0), %%r12 \n\t"
8389 "mov %c[r13](%0), %%r13 \n\t"
8390 "mov %c[r14](%0), %%r14 \n\t"
8391 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8392#endif
b188c81f 8393 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8394
6aa8b732 8395 /* Enter guest mode */
83287ea4 8396 "jne 1f \n\t"
4ecac3fd 8397 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8398 "jmp 2f \n\t"
8399 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8400 "2: "
6aa8b732 8401 /* Save guest registers, load host registers, keep flags */
b188c81f 8402 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8403 "pop %0 \n\t"
b188c81f
AK		 8404 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8405 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8406 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8407 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8408 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8409 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8410 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8411#ifdef CONFIG_X86_64
e08aa78a
AK		 8412 "mov %%r8, %c[r8](%0) \n\t"
8413 "mov %%r9, %c[r9](%0) \n\t"
8414 "mov %%r10, %c[r10](%0) \n\t"
8415 "mov %%r11, %c[r11](%0) \n\t"
8416 "mov %%r12, %c[r12](%0) \n\t"
8417 "mov %%r13, %c[r13](%0) \n\t"
8418 "mov %%r14, %c[r14](%0) \n\t"
8419 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8420#endif
b188c81f
AK		 8421 "mov %%cr2, %%" _ASM_AX " \n\t"
8422 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8423
b188c81f 8424 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8425 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8426 ".pushsection .rodata \n\t"
8427 ".global vmx_return \n\t"
8428 "vmx_return: " _ASM_PTR " 2b \n\t"
8429 ".popsection"
e08aa78a 8430 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8431 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8432 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8433 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8434 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8435 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8436 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8437 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8438 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8439 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8440 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8441#ifdef CONFIG_X86_64
ad312c7c
ZX		 8442 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8443 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8444 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8445 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8446 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8447 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8448 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8449 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8450#endif
40712fae
AK		 8451 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8452 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8453 : "cc", "memory"
8454#ifdef CONFIG_X86_64
b188c81f 8455 , "rax", "rbx", "rdi", "rsi"
c2036300 8456 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8457#else
8458 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8459#endif
8460 );
6aa8b732 8461
2a7921b7
GN		 8462 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8463 if (debugctlmsr)
8464 update_debugctlmsr(debugctlmsr);
8465
aa67f609
AK		 8466#ifndef CONFIG_X86_64
8467 /*
8468 * The sysexit path does not restore ds/es, so we must set them to
8469 * a reasonable value ourselves.
8470 *
8471 * We can't defer this to vmx_load_host_state() since that function
8472 * may be executed in interrupt context, which saves and restore segments
8473 * around it, nullifying its effect.
8474 */
8475 loadsegment(ds, __USER_DS);
8476 loadsegment(es, __USER_DS);
8477#endif
8478
6de4f3ad 8479 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8480 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8481 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8482 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8483 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8484 vcpu->arch.regs_dirty = 0;
8485
1155f76a
AK		 8486 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8487
d462b819 8488 vmx->loaded_vmcs->launched = 1;
1b6269db 8489
51aa01d1 8490 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8491 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8492
e0b890d3
GN		 8493 /*
8494 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8495 * we did not inject a still-pending event to L1 now because of
8496 * nested_run_pending, we need to re-enable this bit.
8497 */
8498 if (vmx->nested.nested_run_pending)
8499 kvm_make_request(KVM_REQ_EVENT, vcpu);
8500
8501 vmx->nested.nested_run_pending = 0;
8502
51aa01d1
AK		 8503 vmx_complete_atomic_exit(vmx);
8504 vmx_recover_nmi_blocking(vmx);
cf393f75 8505 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8506}
8507
4fa7734c
PB		 8508static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8509{
8510 struct vcpu_vmx *vmx = to_vmx(vcpu);
8511 int cpu;
8512
8513 if (vmx->loaded_vmcs == &vmx->vmcs01)
8514 return;
8515
8516 cpu = get_cpu();
8517 vmx->loaded_vmcs = &vmx->vmcs01;
8518 vmx_vcpu_put(vcpu);
8519 vmx_vcpu_load(vcpu, cpu);
8520 vcpu->cpu = cpu;
8521 put_cpu();
8522}
8523
6aa8b732
AK		 8524static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8525{
fb3f0f51
RR		 8526 struct vcpu_vmx *vmx = to_vmx(vcpu);
8527
843e4330
KH		 8528 if (enable_pml)
8529 vmx_disable_pml(vmx);
cdbecfc3 8530 free_vpid(vmx);
4fa7734c
PB		 8531 leave_guest_mode(vcpu);
8532 vmx_load_vmcs01(vcpu);
26a865f4 8533 free_nested(vmx);
4fa7734c 8534 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8535 kfree(vmx->guest_msrs);
8536 kvm_vcpu_uninit(vcpu);
a4770347 8537 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8538}
8539
fb3f0f51 8540static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8541{
fb3f0f51 8542 int err;
c16f862d 8543 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8544 int cpu;
6aa8b732 8545
a2fa3e9f 8546 if (!vmx)
fb3f0f51
RR		 8547 return ERR_PTR(-ENOMEM);
8548
2384d2b3
SY		 8549 allocate_vpid(vmx);
8550
fb3f0f51
RR		 8551 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8552 if (err)
8553 goto free_vcpu;
965b58a5 8554
a2fa3e9f 8555 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8556 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8557 > PAGE_SIZE);
0123be42 8558
be6d05cf 8559 err = -ENOMEM;
fb3f0f51 8560 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8561 goto uninit_vcpu;
8562 }
965b58a5 8563
d462b819
NHE		 8564 vmx->loaded_vmcs = &vmx->vmcs01;
8565 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8566 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8567 goto free_msrs;
d462b819
NHE		 8568 if (!vmm_exclusive)
8569 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8570 loaded_vmcs_init(vmx->loaded_vmcs);
8571 if (!vmm_exclusive)
8572 kvm_cpu_vmxoff();
a2fa3e9f 8573
15ad7146
AK		 8574 cpu = get_cpu();
8575 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8576 vmx->vcpu.cpu = cpu;
8b9cf98c 8577 err = vmx_vcpu_setup(vmx);
fb3f0f51 8578 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8579 put_cpu();
fb3f0f51
RR		 8580 if (err)
8581 goto free_vmcs;
35754c98 8582 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK		 8583 err = alloc_apic_access_page(kvm);
8584 if (err)
5e4a0b3c 8585 goto free_vmcs;
a63cb560 8586 }
fb3f0f51 8587
b927a3ce
SY		 8588 if (enable_ept) {
8589 if (!kvm->arch.ept_identity_map_addr)
8590 kvm->arch.ept_identity_map_addr =
8591 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8592 err = init_rmode_identity_map(kvm);
8593 if (err)
93ea5388 8594 goto free_vmcs;
b927a3ce 8595 }
b7ebfb05 8596
b9c237bb
WV		 8597 if (nested)
8598 nested_vmx_setup_ctls_msrs(vmx);
8599
705699a1 8600 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE		 8601 vmx->nested.current_vmptr = -1ull;
8602 vmx->nested.current_vmcs12 = NULL;
8603
843e4330
KH		 8604 /*
8605 * If PML is turned on, failure on enabling PML just results in failure
8606 * of creating the vcpu, therefore we can simplify PML logic (by
8607 * avoiding dealing with cases, such as enabling PML partially on vcpus
8608 * for the guest, etc.
8609 */
8610 if (enable_pml) {
8611 err = vmx_enable_pml(vmx);
8612 if (err)
8613 goto free_vmcs;
8614 }
8615
fb3f0f51
RR		 8616 return &vmx->vcpu;
8617
8618free_vmcs:
5f3fbc34 8619 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8620free_msrs:
fb3f0f51
RR		 8621 kfree(vmx->guest_msrs);
8622uninit_vcpu:
8623 kvm_vcpu_uninit(&vmx->vcpu);
8624free_vcpu:
cdbecfc3 8625 free_vpid(vmx);
a4770347 8626 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8627 return ERR_PTR(err);
6aa8b732
AK		 8628}
8629
002c7f7c
YS		 8630static void __init vmx_check_processor_compat(void *rtn)
8631{
8632 struct vmcs_config vmcs_conf;
8633
8634 *(int *)rtn = 0;
8635 if (setup_vmcs_config(&vmcs_conf) < 0)
8636 *(int *)rtn = -EIO;
8637 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8638 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8639 smp_processor_id());
8640 *(int *)rtn = -EIO;
8641 }
8642}
8643
67253af5
SY		 8644static int get_ept_level(void)
8645{
8646 return VMX_EPT_DEFAULT_GAW + 1;
8647}
8648
4b12f0de 8649static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8650{
b18d5431
XG		 8651 u8 cache;
8652 u64 ipat = 0;
4b12f0de 8653
522c68c4 8654 /* For VT-d and EPT combination
606decd6 8655 * 1. MMIO: always map as UC
522c68c4
SY		 8656 * 2. EPT with VT-d:
8657 * a. VT-d without snooping control feature: can't guarantee the
606decd6 8658 * result, try to trust guest.
522c68c4
SY		 8659 * b. VT-d with snooping control feature: snooping control feature of
8660 * VT-d engine can guarantee the cache correctness. Just set it
8661 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8662 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8663 * consistent with host MTRR
8664 */
606decd6
PB		 8665 if (is_mmio) {
8666 cache = MTRR_TYPE_UNCACHABLE;
8667 goto exit;
8668 }
8669
8670 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG		 8671 ipat = VMX_EPT_IPAT_BIT;
8672 cache = MTRR_TYPE_WRBACK;
8673 goto exit;
8674 }
8675
8676 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8677 ipat = VMX_EPT_IPAT_BIT;
0da029ed 8678 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG		 8679 cache = MTRR_TYPE_WRBACK;
8680 else
8681 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG		 8682 goto exit;
8683 }
8684
ff53604b 8685 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG		 8686
8687exit:
8688 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY		 8689}
8690
17cc3935 8691static int vmx_get_lpage_level(void)
344f414f 8692{
878403b7
SY		 8693 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8694 return PT_DIRECTORY_LEVEL;
8695 else
8696 /* For shadow and EPT supported 1GB page */
8697 return PT_PDPE_LEVEL;
344f414f
JR		 8698}
8699
feda805f
XG		 8700static void vmcs_set_secondary_exec_control(u32 new_ctl)
8701{
8702 /*
8703 * These bits in the secondary execution controls field
8704 * are dynamic, the others are mostly based on the hypervisor
8705 * architecture and the guest's CPUID. Do not touch the
8706 * dynamic bits.
8707 */
8708 u32 mask =
8709 SECONDARY_EXEC_SHADOW_VMCS |
8710 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8711 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8712
8713 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8714
8715 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8716 (new_ctl & ~mask) | (cur_ctl & mask));
8717}
8718
0e851880
SY		 8719static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8720{
4e47c7a6
SY		 8721 struct kvm_cpuid_entry2 *best;
8722 struct vcpu_vmx *vmx = to_vmx(vcpu);
feda805f 8723 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
4e47c7a6 8724
4e47c7a6 8725 if (vmx_rdtscp_supported()) {
1cea0ce6
XG		 8726 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8727 if (!rdtscp_enabled)
feda805f 8728 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
f36201e5 8729
8b97265a 8730 if (nested) {
1cea0ce6 8731 if (rdtscp_enabled)
8b97265a
PB		 8732 vmx->nested.nested_vmx_secondary_ctls_high |=
8733 SECONDARY_EXEC_RDTSCP;
8734 else
8735 vmx->nested.nested_vmx_secondary_ctls_high &=
8736 ~SECONDARY_EXEC_RDTSCP;
8737 }
4e47c7a6 8738 }
ad756a16 8739
ad756a16
MJ		 8740 /* Exposing INVPCID only when PCID is exposed */
8741 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8742 if (vmx_invpcid_supported() &&
29541bb8
XG		 8743 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8744 !guest_cpuid_has_pcid(vcpu))) {
feda805f 8745 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
29541bb8 8746
ad756a16 8747 if (best)
4f977045 8748 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8749 }
8b3e34e4 8750
feda805f
XG		 8751 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8752
8b3e34e4
XG		 8753 if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8754 if (guest_cpuid_has_pcommit(vcpu))
8755 vmx->nested.nested_vmx_secondary_ctls_high |=
8756 SECONDARY_EXEC_PCOMMIT;
8757 else
8758 vmx->nested.nested_vmx_secondary_ctls_high &=
8759 ~SECONDARY_EXEC_PCOMMIT;
8760 }
0e851880
SY		 8761}
8762
d4330ef2
JR		 8763static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8764{
7b8050f5
NHE		 8765 if (func == 1 && nested)
8766 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8767}
8768
25d92081
YZ		 8769static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8770 struct x86_exception *fault)
8771{
533558bc
JK		 8772 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8773 u32 exit_reason;
25d92081
YZ		 8774
8775 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8776 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8777 else
533558bc
JK		 8778 exit_reason = EXIT_REASON_EPT_VIOLATION;
8779 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8780 vmcs12->guest_physical_address = fault->address;
8781}
8782
155a97a3
NHE		 8783/* Callbacks for nested_ept_init_mmu_context: */
8784
8785static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8786{
8787 /* return the page table to be shadowed - in our case, EPT12 */
8788 return get_vmcs12(vcpu)->ept_pointer;
8789}
8790
8a3c1a33 8791static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8792{
ad896af0
PB		 8793 WARN_ON(mmu_is_nested(vcpu));
8794 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8795 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8796 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8797 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8798 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8799 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8800
8801 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8802}
8803
8804static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8805{
8806 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8807}
8808
19d5f10b
EK		 8809static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8810 u16 error_code)
8811{
8812 bool inequality, bit;
8813
8814 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8815 inequality =
8816 (error_code & vmcs12->page_fault_error_code_mask) !=
8817 vmcs12->page_fault_error_code_match;
8818 return inequality ^ bit;
8819}
8820
feaf0c7d
GN		 8821static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8822 struct x86_exception *fault)
8823{
8824 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8825
8826 WARN_ON(!is_guest_mode(vcpu));
8827
19d5f10b 8828 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8829 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8830 vmcs_read32(VM_EXIT_INTR_INFO),
8831 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8832 else
8833 kvm_inject_page_fault(vcpu, fault);
8834}
8835
a2bcba50
WL		 8836static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8837 struct vmcs12 *vmcs12)
8838{
8839 struct vcpu_vmx *vmx = to_vmx(vcpu);
9090422f 8840 int maxphyaddr = cpuid_maxphyaddr(vcpu);
a2bcba50
WL		 8841
8842 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9090422f
EK		 8843 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8844 vmcs12->apic_access_addr >> maxphyaddr)
a2bcba50
WL		 8845 return false;
8846
8847 /*
8848 * Translate L1 physical address to host physical
8849 * address for vmcs02. Keep the page pinned, so this
8850 * physical address remains valid. We keep a reference
8851 * to it so we can release it later.
8852 */
8853 if (vmx->nested.apic_access_page) /* shouldn't happen */
8854 nested_release_page(vmx->nested.apic_access_page);
8855 vmx->nested.apic_access_page =
8856 nested_get_page(vcpu, vmcs12->apic_access_addr);
8857 }
a7c0b07d
WL		 8858
8859 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9090422f
EK		 8860 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8861 vmcs12->virtual_apic_page_addr >> maxphyaddr)
a7c0b07d
WL		 8862 return false;
8863
8864 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8865 nested_release_page(vmx->nested.virtual_apic_page);
8866 vmx->nested.virtual_apic_page =
8867 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8868
8869 /*
8870 * Failing the vm entry is _not_ what the processor does
8871 * but it's basically the only possibility we have.
8872 * We could still enter the guest if CR8 load exits are
8873 * enabled, CR8 store exits are enabled, and virtualize APIC
8874 * access is disabled; in this case the processor would never
8875 * use the TPR shadow and we could simply clear the bit from
8876 * the execution control. But such a configuration is useless,
8877 * so let's keep the code simple.
8878 */
8879 if (!vmx->nested.virtual_apic_page)
8880 return false;
8881 }
8882
705699a1 8883 if (nested_cpu_has_posted_intr(vmcs12)) {
9090422f
EK		 8884 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8885 vmcs12->posted_intr_desc_addr >> maxphyaddr)
705699a1
WV		 8886 return false;
8887
8888 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8889 kunmap(vmx->nested.pi_desc_page);
8890 nested_release_page(vmx->nested.pi_desc_page);
8891 }
8892 vmx->nested.pi_desc_page =
8893 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8894 if (!vmx->nested.pi_desc_page)
8895 return false;
8896
8897 vmx->nested.pi_desc =
8898 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8899 if (!vmx->nested.pi_desc) {
8900 nested_release_page_clean(vmx->nested.pi_desc_page);
8901 return false;
8902 }
8903 vmx->nested.pi_desc =
8904 (struct pi_desc *)((void *)vmx->nested.pi_desc +
8905 (unsigned long)(vmcs12->posted_intr_desc_addr &
8906 (PAGE_SIZE - 1)));
8907 }
8908
a2bcba50
WL		 8909 return true;
8910}
8911
f4124500
JK		 8912static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8913{
8914 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8915 struct vcpu_vmx *vmx = to_vmx(vcpu);
8916
8917 if (vcpu->arch.virtual_tsc_khz == 0)
8918 return;
8919
8920 /* Make sure short timeouts reliably trigger an immediate vmexit.
8921 * hrtimer_start does not guarantee this. */
8922 if (preemption_timeout <= 1) {
8923 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8924 return;
8925 }
8926
8927 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8928 preemption_timeout *= 1000000;
8929 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8930 hrtimer_start(&vmx->nested.preemption_timer,
8931 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8932}
8933
3af18d9c
WV		 8934static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8935 struct vmcs12 *vmcs12)
8936{
8937 int maxphyaddr;
8938 u64 addr;
8939
8940 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8941 return 0;
8942
8943 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8944 WARN_ON(1);
8945 return -EINVAL;
8946 }
8947 maxphyaddr = cpuid_maxphyaddr(vcpu);
8948
8949 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8950 ((addr + PAGE_SIZE) >> maxphyaddr))
8951 return -EINVAL;
8952
8953 return 0;
8954}
8955
8956/*
8957 * Merge L0's and L1's MSR bitmap, return false to indicate that
8958 * we do not use the hardware.
8959 */
8960static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8961 struct vmcs12 *vmcs12)
8962{
82f0dd4b 8963 int msr;
f2b93280
WV		 8964 struct page *page;
8965 unsigned long *msr_bitmap;
8966
8967 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8968 return false;
8969
8970 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8971 if (!page) {
8972 WARN_ON(1);
8973 return false;
8974 }
8975 msr_bitmap = (unsigned long *)kmap(page);
8976 if (!msr_bitmap) {
8977 nested_release_page_clean(page);
8978 WARN_ON(1);
8979 return false;
8980 }
8981
8982 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 8983 if (nested_cpu_has_apic_reg_virt(vmcs12))
8984 for (msr = 0x800; msr <= 0x8ff; msr++)
8985 nested_vmx_disable_intercept_for_msr(
8986 msr_bitmap,
8987 vmx_msr_bitmap_nested,
8988 msr, MSR_TYPE_R);
f2b93280
WV		 8989 /* TPR is allowed */
8990 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8991 vmx_msr_bitmap_nested,
8992 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8993 MSR_TYPE_R | MSR_TYPE_W);
608406e2
WV		 8994 if (nested_cpu_has_vid(vmcs12)) {
8995 /* EOI and self-IPI are allowed */
8996 nested_vmx_disable_intercept_for_msr(
8997 msr_bitmap,
8998 vmx_msr_bitmap_nested,
8999 APIC_BASE_MSR + (APIC_EOI >> 4),
9000 MSR_TYPE_W);
9001 nested_vmx_disable_intercept_for_msr(
9002 msr_bitmap,
9003 vmx_msr_bitmap_nested,
9004 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9005 MSR_TYPE_W);
9006 }
82f0dd4b
WV		 9007 } else {
9008 /*
9009 * Enable reading intercept of all the x2apic
9010 * MSRs. We should not rely on vmcs12 to do any
9011 * optimizations here, it may have been modified
9012 * by L1.
9013 */
9014 for (msr = 0x800; msr <= 0x8ff; msr++)
9015 __vmx_enable_intercept_for_msr(
9016 vmx_msr_bitmap_nested,
9017 msr,
9018 MSR_TYPE_R);
9019
f2b93280
WV		 9020 __vmx_enable_intercept_for_msr(
9021 vmx_msr_bitmap_nested,
9022 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
82f0dd4b 9023 MSR_TYPE_W);
608406e2
WV		 9024 __vmx_enable_intercept_for_msr(
9025 vmx_msr_bitmap_nested,
9026 APIC_BASE_MSR + (APIC_EOI >> 4),
9027 MSR_TYPE_W);
9028 __vmx_enable_intercept_for_msr(
9029 vmx_msr_bitmap_nested,
9030 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9031 MSR_TYPE_W);
82f0dd4b 9032 }
f2b93280
WV		 9033 kunmap(page);
9034 nested_release_page_clean(page);
9035
9036 return true;
9037}
9038
9039static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9040 struct vmcs12 *vmcs12)
9041{
82f0dd4b 9042 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 9043 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV		 9044 !nested_cpu_has_vid(vmcs12) &&
9045 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV		 9046 return 0;
9047
9048 /*
9049 * If virtualize x2apic mode is enabled,
9050 * virtualize apic access must be disabled.
9051 */
82f0dd4b
WV		 9052 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9053 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 9054 return -EINVAL;
9055
608406e2
WV		 9056 /*
9057 * If virtual interrupt delivery is enabled,
9058 * we must exit on external interrupts.
9059 */
9060 if (nested_cpu_has_vid(vmcs12) &&
9061 !nested_exit_on_intr(vcpu))
9062 return -EINVAL;
9063
705699a1
WV		 9064 /*
9065 * bits 15:8 should be zero in posted_intr_nv,
9066 * the descriptor address has been already checked
9067 * in nested_get_vmcs12_pages.
9068 */
9069 if (nested_cpu_has_posted_intr(vmcs12) &&
9070 (!nested_cpu_has_vid(vmcs12) ||
9071 !nested_exit_intr_ack_set(vcpu) ||
9072 vmcs12->posted_intr_nv & 0xff00))
9073 return -EINVAL;
9074
f2b93280
WV		 9075 /* tpr shadow is needed by all apicv features. */
9076 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9077 return -EINVAL;
9078
9079 return 0;
3af18d9c
WV		 9080}
9081
e9ac033e
EK		 9082static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9083 unsigned long count_field,
92d71bc6 9084 unsigned long addr_field)
ff651cb6 9085{
92d71bc6 9086 int maxphyaddr;
e9ac033e
EK		 9087 u64 count, addr;
9088
9089 if (vmcs12_read_any(vcpu, count_field, &count) ||
9090 vmcs12_read_any(vcpu, addr_field, &addr)) {
9091 WARN_ON(1);
9092 return -EINVAL;
9093 }
9094 if (count == 0)
9095 return 0;
92d71bc6 9096 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK		 9097 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9098 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9099 pr_warn_ratelimited(
9100 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9101 addr_field, maxphyaddr, count, addr);
9102 return -EINVAL;
9103 }
9104 return 0;
9105}
9106
9107static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9108 struct vmcs12 *vmcs12)
9109{
e9ac033e
EK		 9110 if (vmcs12->vm_exit_msr_load_count == 0 &&
9111 vmcs12->vm_exit_msr_store_count == 0 &&
9112 vmcs12->vm_entry_msr_load_count == 0)
9113 return 0; /* Fast path */
e9ac033e 9114 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9115 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9116 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9117 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9118 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9119 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK		 9120 return -EINVAL;
9121 return 0;
9122}
9123
9124static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9125 struct vmx_msr_entry *e)
9126{
9127 /* x2APIC MSR accesses are not allowed */
8a9781f7 9128 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK		 9129 return -EINVAL;
9130 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9131 e->index == MSR_IA32_UCODE_REV)
9132 return -EINVAL;
9133 if (e->reserved != 0)
ff651cb6
WV		 9134 return -EINVAL;
9135 return 0;
9136}
9137
e9ac033e
EK		 9138static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9139 struct vmx_msr_entry *e)
ff651cb6
WV		 9140{
9141 if (e->index == MSR_FS_BASE ||
9142 e->index == MSR_GS_BASE ||
e9ac033e
EK		 9143 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9144 nested_vmx_msr_check_common(vcpu, e))
9145 return -EINVAL;
9146 return 0;
9147}
9148
9149static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9150 struct vmx_msr_entry *e)
9151{
9152 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9153 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 9154 return -EINVAL;
9155 return 0;
9156}
9157
9158/*
9159 * Load guest's/host's msr at nested entry/exit.
9160 * return 0 for success, entry index for failure.
9161 */
9162static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9163{
9164 u32 i;
9165 struct vmx_msr_entry e;
9166 struct msr_data msr;
9167
9168 msr.host_initiated = false;
9169 for (i = 0; i < count; i++) {
54bf36aa
PB		 9170 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9171 &e, sizeof(e))) {
e9ac033e
EK		 9172 pr_warn_ratelimited(
9173 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9174 __func__, i, gpa + i * sizeof(e));
ff651cb6 9175 goto fail;
e9ac033e
EK		 9176 }
9177 if (nested_vmx_load_msr_check(vcpu, &e)) {
9178 pr_warn_ratelimited(
9179 "%s check failed (%u, 0x%x, 0x%x)\n",
9180 __func__, i, e.index, e.reserved);
9181 goto fail;
9182 }
ff651cb6
WV		 9183 msr.index = e.index;
9184 msr.data = e.value;
e9ac033e
EK		 9185 if (kvm_set_msr(vcpu, &msr)) {
9186 pr_warn_ratelimited(
9187 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9188 __func__, i, e.index, e.value);
ff651cb6 9189 goto fail;
e9ac033e 9190 }
ff651cb6
WV		 9191 }
9192 return 0;
9193fail:
9194 return i + 1;
9195}
9196
9197static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9198{
9199 u32 i;
9200 struct vmx_msr_entry e;
9201
9202 for (i = 0; i < count; i++) {
609e36d3 9203 struct msr_data msr_info;
54bf36aa
PB		 9204 if (kvm_vcpu_read_guest(vcpu,
9205 gpa + i * sizeof(e),
9206 &e, 2 * sizeof(u32))) {
e9ac033e
EK		 9207 pr_warn_ratelimited(
9208 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9209 __func__, i, gpa + i * sizeof(e));
ff651cb6 9210 return -EINVAL;
e9ac033e
EK		 9211 }
9212 if (nested_vmx_store_msr_check(vcpu, &e)) {
9213 pr_warn_ratelimited(
9214 "%s check failed (%u, 0x%x, 0x%x)\n",
9215 __func__, i, e.index, e.reserved);
ff651cb6 9216 return -EINVAL;
e9ac033e 9217 }
609e36d3
PB		 9218 msr_info.host_initiated = false;
9219 msr_info.index = e.index;
9220 if (kvm_get_msr(vcpu, &msr_info)) {
e9ac033e
EK		 9221 pr_warn_ratelimited(
9222 "%s cannot read MSR (%u, 0x%x)\n",
9223 __func__, i, e.index);
9224 return -EINVAL;
9225 }
54bf36aa
PB		 9226 if (kvm_vcpu_write_guest(vcpu,
9227 gpa + i * sizeof(e) +
9228 offsetof(struct vmx_msr_entry, value),
9229 &msr_info.data, sizeof(msr_info.data))) {
e9ac033e
EK		 9230 pr_warn_ratelimited(
9231 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9232 __func__, i, e.index, msr_info.data);
e9ac033e
EK		 9233 return -EINVAL;
9234 }
ff651cb6
WV		 9235 }
9236 return 0;
9237}
9238
fe3ef05c
NHE		 9239/*
9240 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9241 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9242 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 9243 * guest in a way that will both be appropriate to L1's requests, and our
9244 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9245 * function also has additional necessary side-effects, like setting various
9246 * vcpu->arch fields.
9247 */
9248static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9249{
9250 struct vcpu_vmx *vmx = to_vmx(vcpu);
9251 u32 exec_control;
9252
9253 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9254 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9255 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9256 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9257 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9258 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9259 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9260 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9261 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9262 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9263 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9264 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9265 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9266 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9267 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9268 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9269 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9270 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9271 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9272 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9273 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9274 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9275 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9276 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9277 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9278 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9279 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9280 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9281 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9282 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9283 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9284 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9285 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9286 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9287 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9288 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9289
2996fca0
JK		 9290 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9291 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9292 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9293 } else {
9294 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9295 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9296 }
fe3ef05c
NHE		 9297 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9298 vmcs12->vm_entry_intr_info_field);
9299 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9300 vmcs12->vm_entry_exception_error_code);
9301 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9302 vmcs12->vm_entry_instruction_len);
9303 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9304 vmcs12->guest_interruptibility_info);
fe3ef05c 9305 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9306 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 9307 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9308 vmcs12->guest_pending_dbg_exceptions);
9309 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9310 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9311
81dc01f7
WL		 9312 if (nested_cpu_has_xsaves(vmcs12))
9313 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 9314 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9315
f4124500
JK		 9316 exec_control = vmcs12->pin_based_vm_exec_control;
9317 exec_control |= vmcs_config.pin_based_exec_ctrl;
705699a1
WV		 9318 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9319
9320 if (nested_cpu_has_posted_intr(vmcs12)) {
9321 /*
9322 * Note that we use L0's vector here and in
9323 * vmx_deliver_nested_posted_interrupt.
9324 */
9325 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9326 vmx->nested.pi_pending = false;
9327 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9328 vmcs_write64(POSTED_INTR_DESC_ADDR,
9329 page_to_phys(vmx->nested.pi_desc_page) +
9330 (unsigned long)(vmcs12->posted_intr_desc_addr &
9331 (PAGE_SIZE - 1)));
9332 } else
9333 exec_control &= ~PIN_BASED_POSTED_INTR;
9334
f4124500 9335 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 9336
f4124500
JK		 9337 vmx->nested.preemption_timer_expired = false;
9338 if (nested_cpu_has_preemption_timer(vmcs12))
9339 vmx_start_preemption_timer(vcpu);
0238ea91 9340
fe3ef05c
NHE		 9341 /*
9342 * Whether page-faults are trapped is determined by a combination of
9343 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9344 * If enable_ept, L0 doesn't care about page faults and we should
9345 * set all of these to L1's desires. However, if !enable_ept, L0 does
9346 * care about (at least some) page faults, and because it is not easy
9347 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9348 * to exit on each and every L2 page fault. This is done by setting
9349 * MASK=MATCH=0 and (see below) EB.PF=1.
9350 * Note that below we don't need special code to set EB.PF beyond the
9351 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9352 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9353 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9354 *
9355 * A problem with this approach (when !enable_ept) is that L1 may be
9356 * injected with more page faults than it asked for. This could have
9357 * caused problems, but in practice existing hypervisors don't care.
9358 * To fix this, we will need to emulate the PFEC checking (on the L1
9359 * page tables), using walk_addr(), when injecting PFs to L1.
9360 */
9361 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9362 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9363 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9364 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9365
9366 if (cpu_has_secondary_exec_ctrls()) {
f4124500 9367 exec_control = vmx_secondary_exec_control(vmx);
e2821620 9368
fe3ef05c 9369 /* Take the following fields only from vmcs12 */
696dfd95 9370 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 9371 SECONDARY_EXEC_RDTSCP |
696dfd95 9372 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8b3e34e4
XG		 9373 SECONDARY_EXEC_APIC_REGISTER_VIRT |
9374 SECONDARY_EXEC_PCOMMIT);
fe3ef05c
NHE		 9375 if (nested_cpu_has(vmcs12,
9376 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9377 exec_control |= vmcs12->secondary_vm_exec_control;
9378
9379 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 9380 /*
9381 * If translation failed, no matter: This feature asks
9382 * to exit when accessing the given address, and if it
9383 * can never be accessed, this feature won't do
9384 * anything anyway.
9385 */
9386 if (!vmx->nested.apic_access_page)
9387 exec_control &=
9388 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9389 else
9390 vmcs_write64(APIC_ACCESS_ADDR,
9391 page_to_phys(vmx->nested.apic_access_page));
f2b93280 9392 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
35754c98 9393 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
ca3f257a
JK		 9394 exec_control |=
9395 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 9396 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 9397 }
9398
608406e2
WV		 9399 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9400 vmcs_write64(EOI_EXIT_BITMAP0,
9401 vmcs12->eoi_exit_bitmap0);
9402 vmcs_write64(EOI_EXIT_BITMAP1,
9403 vmcs12->eoi_exit_bitmap1);
9404 vmcs_write64(EOI_EXIT_BITMAP2,
9405 vmcs12->eoi_exit_bitmap2);
9406 vmcs_write64(EOI_EXIT_BITMAP3,
9407 vmcs12->eoi_exit_bitmap3);
9408 vmcs_write16(GUEST_INTR_STATUS,
9409 vmcs12->guest_intr_status);
9410 }
9411
fe3ef05c
NHE		 9412 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9413 }
9414
9415
9416 /*
9417 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9418 * Some constant fields are set here by vmx_set_constant_host_state().
9419 * Other fields are different per CPU, and will be set later when
9420 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9421 */
a547c6db 9422 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 9423
9424 /*
9425 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9426 * entry, but only if the current (host) sp changed from the value
9427 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9428 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9429 * here we just force the write to happen on entry.
9430 */
9431 vmx->host_rsp = 0;
9432
9433 exec_control = vmx_exec_control(vmx); /* L0's desires */
9434 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9435 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9436 exec_control &= ~CPU_BASED_TPR_SHADOW;
9437 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 9438
9439 if (exec_control & CPU_BASED_TPR_SHADOW) {
9440 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9441 page_to_phys(vmx->nested.virtual_apic_page));
9442 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9443 }
9444
3af18d9c 9445 if (cpu_has_vmx_msr_bitmap() &&
670125bd
WV		 9446 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9447 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9448 /* MSR_BITMAP will be set by following vmx_set_efer. */
3af18d9c
WV		 9449 } else
9450 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9451
fe3ef05c 9452 /*
3af18d9c 9453 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 9454 * Rather, exit every time.
9455 */
fe3ef05c
NHE		 9456 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9457 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9458
9459 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9460
9461 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9462 * bitwise-or of what L1 wants to trap for L2, and what we want to
9463 * trap. Note that CR0.TS also needs updating - we do this later.
9464 */
9465 update_exception_bitmap(vcpu);
9466 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9467 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9468
8049d651
NHE		 9469 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9470 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9471 * bits are further modified by vmx_set_efer() below.
9472 */
f4124500 9473 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9474
9475 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9476 * emulated by vmx_set_efer(), below.
9477 */
2961e876 9478 vm_entry_controls_init(vmx,
8049d651
NHE		 9479 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9480 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9481 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9482
44811c02 9483 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9484 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9485 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9486 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9487 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9488
9489
9490 set_cr4_guest_host_mask(vmx);
9491
36be0b9d
PB		 9492 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9493 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9494
27fc51b2
NHE		 9495 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9496 vmcs_write64(TSC_OFFSET,
9497 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9498 else
9499 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9500
9501 if (enable_vpid) {
9502 /*
9503 * Trivially support vpid by letting L2s share their parent
9504 * L1's vpid. TODO: move to a more elaborate solution, giving
9505 * each L2 its own vpid and exposing the vpid feature to L1.
9506 */
9507 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9508 vmx_flush_tlb(vcpu);
9509 }
9510
155a97a3
NHE		 9511 if (nested_cpu_has_ept(vmcs12)) {
9512 kvm_mmu_unload(vcpu);
9513 nested_ept_init_mmu_context(vcpu);
9514 }
9515
fe3ef05c
NHE		 9516 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9517 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9518 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9519 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9520 else
9521 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9522 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9523 vmx_set_efer(vcpu, vcpu->arch.efer);
9524
9525 /*
9526 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9527 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9528 * The CR0_READ_SHADOW is what L2 should have expected to read given
9529 * the specifications by L1; It's not enough to take
9530 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9531 * have more bits than L1 expected.
9532 */
9533 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9534 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9535
9536 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9537 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9538
9539 /* shadow page tables on either EPT or shadow page tables */
9540 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9541 kvm_mmu_reset_context(vcpu);
9542
feaf0c7d
GN		 9543 if (!enable_ept)
9544 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9545
3633cfc3
NHE		 9546 /*
9547 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9548 */
9549 if (enable_ept) {
9550 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9551 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9552 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9553 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9554 }
9555
fe3ef05c
NHE		 9556 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9557 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9558}
9559
cd232ad0
NHE		 9560/*
9561 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9562 * for running an L2 nested guest.
9563 */
9564static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9565{
9566 struct vmcs12 *vmcs12;
9567 struct vcpu_vmx *vmx = to_vmx(vcpu);
9568 int cpu;
9569 struct loaded_vmcs *vmcs02;
384bb783 9570 bool ia32e;
ff651cb6 9571 u32 msr_entry_idx;
cd232ad0
NHE		 9572
9573 if (!nested_vmx_check_permission(vcpu) ||
9574 !nested_vmx_check_vmcs12(vcpu))
9575 return 1;
9576
9577 skip_emulated_instruction(vcpu);
9578 vmcs12 = get_vmcs12(vcpu);
9579
012f83cb
AG		 9580 if (enable_shadow_vmcs)
9581 copy_shadow_to_vmcs12(vmx);
9582
7c177938
NHE		 9583 /*
9584 * The nested entry process starts with enforcing various prerequisites
9585 * on vmcs12 as required by the Intel SDM, and act appropriately when
9586 * they fail: As the SDM explains, some conditions should cause the
9587 * instruction to fail, while others will cause the instruction to seem
9588 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9589 * To speed up the normal (success) code path, we should avoid checking
9590 * for misconfigurations which will anyway be caught by the processor
9591 * when using the merged vmcs02.
9592 */
9593 if (vmcs12->launch_state == launch) {
9594 nested_vmx_failValid(vcpu,
9595 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9596 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9597 return 1;
9598 }
9599
6dfacadd
JK		 9600 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9601 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9602 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9603 return 1;
9604 }
9605
3af18d9c 9606 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9607 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9608 return 1;
9609 }
9610
3af18d9c 9611 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9612 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9613 return 1;
9614 }
9615
f2b93280
WV		 9616 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9617 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9618 return 1;
9619 }
9620
e9ac033e
EK		 9621 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9622 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9623 return 1;
9624 }
9625
7c177938 9626 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9627 vmx->nested.nested_vmx_true_procbased_ctls_low,
9628 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9629 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9630 vmx->nested.nested_vmx_secondary_ctls_low,
9631 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9632 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9633 vmx->nested.nested_vmx_pinbased_ctls_low,
9634 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9635 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9636 vmx->nested.nested_vmx_true_exit_ctls_low,
9637 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9638 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9639 vmx->nested.nested_vmx_true_entry_ctls_low,
9640 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9641 {
9642 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9643 return 1;
9644 }
9645
9646 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9647 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9648 nested_vmx_failValid(vcpu,
9649 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9650 return 1;
9651 }
9652
b9c237bb 9653 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9654 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9655 nested_vmx_entry_failure(vcpu, vmcs12,
9656 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9657 return 1;
9658 }
9659 if (vmcs12->vmcs_link_pointer != -1ull) {
9660 nested_vmx_entry_failure(vcpu, vmcs12,
9661 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9662 return 1;
9663 }
9664
384bb783 9665 /*
cb0c8cda 9666 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9667 * are performed on the field for the IA32_EFER MSR:
9668 * - Bits reserved in the IA32_EFER MSR must be 0.
9669 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9670 * the IA-32e mode guest VM-exit control. It must also be identical
9671 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9672 * CR0.PG) is 1.
9673 */
9674 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9675 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9676 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9677 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9678 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9679 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9680 nested_vmx_entry_failure(vcpu, vmcs12,
9681 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9682 return 1;
9683 }
9684 }
9685
9686 /*
9687 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9688 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9689 * the values of the LMA and LME bits in the field must each be that of
9690 * the host address-space size VM-exit control.
9691 */
9692 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9693 ia32e = (vmcs12->vm_exit_controls &
9694 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9695 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9696 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9697 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9698 nested_vmx_entry_failure(vcpu, vmcs12,
9699 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9700 return 1;
9701 }
9702 }
9703
7c177938
NHE		 9704 /*
9705 * We're finally done with prerequisite checking, and can start with
9706 * the nested entry.
9707 */
9708
cd232ad0
NHE		 9709 vmcs02 = nested_get_current_vmcs02(vmx);
9710 if (!vmcs02)
9711 return -ENOMEM;
9712
9713 enter_guest_mode(vcpu);
9714
9715 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9716
2996fca0
JK		 9717 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9718 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9719
cd232ad0
NHE		 9720 cpu = get_cpu();
9721 vmx->loaded_vmcs = vmcs02;
9722 vmx_vcpu_put(vcpu);
9723 vmx_vcpu_load(vcpu, cpu);
9724 vcpu->cpu = cpu;
9725 put_cpu();
9726
36c3cc42
JK		 9727 vmx_segment_cache_clear(vmx);
9728
cd232ad0
NHE		 9729 prepare_vmcs02(vcpu, vmcs12);
9730
ff651cb6
WV		 9731 msr_entry_idx = nested_vmx_load_msr(vcpu,
9732 vmcs12->vm_entry_msr_load_addr,
9733 vmcs12->vm_entry_msr_load_count);
9734 if (msr_entry_idx) {
9735 leave_guest_mode(vcpu);
9736 vmx_load_vmcs01(vcpu);
9737 nested_vmx_entry_failure(vcpu, vmcs12,
9738 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9739 return 1;
9740 }
9741
9742 vmcs12->launch_state = 1;
9743
6dfacadd 9744 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 9745 return kvm_vcpu_halt(vcpu);
6dfacadd 9746
7af40ad3
JK		 9747 vmx->nested.nested_run_pending = 1;
9748
cd232ad0
NHE		 9749 /*
9750 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9751 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9752 * returned as far as L1 is concerned. It will only return (and set
9753 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9754 */
9755 return 1;
9756}
9757
4704d0be
NHE		 9758/*
9759 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9760 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9761 * This function returns the new value we should put in vmcs12.guest_cr0.
9762 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9763 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9764 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9765 * didn't trap the bit, because if L1 did, so would L0).
9766 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9767 * been modified by L2, and L1 knows it. So just leave the old value of
9768 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9769 * isn't relevant, because if L0 traps this bit it can set it to anything.
9770 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9771 * changed these bits, and therefore they need to be updated, but L0
9772 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9773 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9774 */
9775static inline unsigned long
9776vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9777{
9778 return
9779 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9780 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9781 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9782 vcpu->arch.cr0_guest_owned_bits));
9783}
9784
9785static inline unsigned long
9786vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9787{
9788 return
9789 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9790 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9791 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9792 vcpu->arch.cr4_guest_owned_bits));
9793}
9794
5f3d5799
JK		 9795static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9796 struct vmcs12 *vmcs12)
9797{
9798 u32 idt_vectoring;
9799 unsigned int nr;
9800
851eb667 9801 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9802 nr = vcpu->arch.exception.nr;
9803 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9804
9805 if (kvm_exception_is_soft(nr)) {
9806 vmcs12->vm_exit_instruction_len =
9807 vcpu->arch.event_exit_inst_len;
9808 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9809 } else
9810 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9811
9812 if (vcpu->arch.exception.has_error_code) {
9813 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9814 vmcs12->idt_vectoring_error_code =
9815 vcpu->arch.exception.error_code;
9816 }
9817
9818 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9819 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9820 vmcs12->idt_vectoring_info_field =
9821 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9822 } else if (vcpu->arch.interrupt.pending) {
9823 nr = vcpu->arch.interrupt.nr;
9824 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9825
9826 if (vcpu->arch.interrupt.soft) {
9827 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9828 vmcs12->vm_entry_instruction_len =
9829 vcpu->arch.event_exit_inst_len;
9830 } else
9831 idt_vectoring |= INTR_TYPE_EXT_INTR;
9832
9833 vmcs12->idt_vectoring_info_field = idt_vectoring;
9834 }
9835}
9836
b6b8a145
JK		 9837static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9838{
9839 struct vcpu_vmx *vmx = to_vmx(vcpu);
9840
f4124500
JK		 9841 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9842 vmx->nested.preemption_timer_expired) {
9843 if (vmx->nested.nested_run_pending)
9844 return -EBUSY;
9845 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9846 return 0;
9847 }
9848
b6b8a145 9849 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9850 if (vmx->nested.nested_run_pending ||
9851 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9852 return -EBUSY;
9853 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9854 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9855 INTR_INFO_VALID_MASK, 0);
9856 /*
9857 * The NMI-triggered VM exit counts as injection:
9858 * clear this one and block further NMIs.
9859 */
9860 vcpu->arch.nmi_pending = 0;
9861 vmx_set_nmi_mask(vcpu, true);
9862 return 0;
9863 }
9864
9865 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9866 nested_exit_on_intr(vcpu)) {
9867 if (vmx->nested.nested_run_pending)
9868 return -EBUSY;
9869 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 9870 return 0;
b6b8a145
JK		 9871 }
9872
705699a1 9873 return vmx_complete_nested_posted_interrupt(vcpu);
b6b8a145
JK		 9874}
9875
f4124500
JK		 9876static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9877{
9878 ktime_t remaining =
9879 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9880 u64 value;
9881
9882 if (ktime_to_ns(remaining) <= 0)
9883 return 0;
9884
9885 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9886 do_div(value, 1000000);
9887 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9888}
9889
4704d0be
NHE		 9890/*
9891 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9892 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9893 * and this function updates it to reflect the changes to the guest state while
9894 * L2 was running (and perhaps made some exits which were handled directly by L0
9895 * without going back to L1), and to reflect the exit reason.
9896 * Note that we do not have to copy here all VMCS fields, just those that
9897 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9898 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9899 * which already writes to vmcs12 directly.
9900 */
533558bc
JK		 9901static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9902 u32 exit_reason, u32 exit_intr_info,
9903 unsigned long exit_qualification)
4704d0be
NHE		 9904{
9905 /* update guest state fields: */
9906 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9907 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9908
4704d0be
NHE		 9909 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9910 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9911 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9912
9913 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9914 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9915 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9916 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9917 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9918 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9919 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9920 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9921 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9922 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9923 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9924 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9925 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9926 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9927 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9928 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9929 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9930 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9931 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9932 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9933 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9934 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9935 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9936 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9937 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9938 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9939 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9940 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9941 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9942 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9943 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9944 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9945 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9946 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9947 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9948 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9949
4704d0be
NHE		 9950 vmcs12->guest_interruptibility_info =
9951 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9952 vmcs12->guest_pending_dbg_exceptions =
9953 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9954 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9955 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9956 else
9957 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9958
f4124500
JK		 9959 if (nested_cpu_has_preemption_timer(vmcs12)) {
9960 if (vmcs12->vm_exit_controls &
9961 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9962 vmcs12->vmx_preemption_timer_value =
9963 vmx_get_preemption_timer_value(vcpu);
9964 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9965 }
7854cbca 9966
3633cfc3
NHE		 9967 /*
9968 * In some cases (usually, nested EPT), L2 is allowed to change its
9969 * own CR3 without exiting. If it has changed it, we must keep it.
9970 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9971 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9972 *
9973 * Additionally, restore L2's PDPTR to vmcs12.
9974 */
9975 if (enable_ept) {
9976 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9977 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9978 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9979 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9980 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9981 }
9982
608406e2
WV		 9983 if (nested_cpu_has_vid(vmcs12))
9984 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9985
c18911a2
JK		 9986 vmcs12->vm_entry_controls =
9987 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9988 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9989
2996fca0
JK		 9990 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9991 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9992 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9993 }
9994
4704d0be
NHE		 9995 /* TODO: These cannot have changed unless we have MSR bitmaps and
9996 * the relevant bit asks not to trap the change */
b8c07d55 9997 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9998 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9999 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10000 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 10001 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10002 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10003 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 10004 if (vmx_mpx_supported())
10005 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 10006 if (nested_cpu_has_xsaves(vmcs12))
10007 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 10008
10009 /* update exit information fields: */
10010
533558bc
JK		 10011 vmcs12->vm_exit_reason = exit_reason;
10012 vmcs12->exit_qualification = exit_qualification;
4704d0be 10013
533558bc 10014 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 10015 if ((vmcs12->vm_exit_intr_info &
10016 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10017 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10018 vmcs12->vm_exit_intr_error_code =
10019 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 10020 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 10021 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10022 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10023
5f3d5799
JK		 10024 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10025 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10026 * instead of reading the real value. */
4704d0be 10027 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 10028
10029 /*
10030 * Transfer the event that L0 or L1 may wanted to inject into
10031 * L2 to IDT_VECTORING_INFO_FIELD.
10032 */
10033 vmcs12_save_pending_event(vcpu, vmcs12);
10034 }
10035
10036 /*
10037 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10038 * preserved above and would only end up incorrectly in L1.
10039 */
10040 vcpu->arch.nmi_injected = false;
10041 kvm_clear_exception_queue(vcpu);
10042 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 10043}
10044
10045/*
10046 * A part of what we need to when the nested L2 guest exits and we want to
10047 * run its L1 parent, is to reset L1's guest state to the host state specified
10048 * in vmcs12.
10049 * This function is to be called not only on normal nested exit, but also on
10050 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10051 * Failures During or After Loading Guest State").
10052 * This function should be called when the active VMCS is L1's (vmcs01).
10053 */
733568f9
JK		 10054static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10055 struct vmcs12 *vmcs12)
4704d0be 10056{
21feb4eb
ACL		 10057 struct kvm_segment seg;
10058
4704d0be
NHE		 10059 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10060 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10061 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 10062 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10063 else
10064 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10065 vmx_set_efer(vcpu, vcpu->arch.efer);
10066
10067 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10068 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10069 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 10070 /*
10071 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10072 * actually changed, because it depends on the current state of
10073 * fpu_active (which may have changed).
10074 * Note that vmx_set_cr0 refers to efer set above.
10075 */
9e3e4dbf 10076 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 10077 /*
10078 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10079 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10080 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10081 */
10082 update_exception_bitmap(vcpu);
10083 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10084 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10085
10086 /*
10087 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10088 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10089 */
10090 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10091 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10092
29bf08f1 10093 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10094
4704d0be
NHE		 10095 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10096 kvm_mmu_reset_context(vcpu);
10097
feaf0c7d
GN		 10098 if (!enable_ept)
10099 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10100
4704d0be
NHE		 10101 if (enable_vpid) {
10102 /*
10103 * Trivially support vpid by letting L2s share their parent
10104 * L1's vpid. TODO: move to a more elaborate solution, giving
10105 * each L2 its own vpid and exposing the vpid feature to L1.
10106 */
10107 vmx_flush_tlb(vcpu);
10108 }
10109
10110
10111 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10112 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10113 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10114 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10115 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10116
36be0b9d
PB		 10117 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10118 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10119 vmcs_write64(GUEST_BNDCFGS, 0);
10120
44811c02 10121 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10122 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 10123 vcpu->arch.pat = vmcs12->host_ia32_pat;
10124 }
4704d0be
NHE		 10125 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10126 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10127 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10128
21feb4eb
ACL		 10129 /* Set L1 segment info according to Intel SDM
10130 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10131 seg = (struct kvm_segment) {
10132 .base = 0,
10133 .limit = 0xFFFFFFFF,
10134 .selector = vmcs12->host_cs_selector,
10135 .type = 11,
10136 .present = 1,
10137 .s = 1,
10138 .g = 1
10139 };
10140 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10141 seg.l = 1;
10142 else
10143 seg.db = 1;
10144 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10145 seg = (struct kvm_segment) {
10146 .base = 0,
10147 .limit = 0xFFFFFFFF,
10148 .type = 3,
10149 .present = 1,
10150 .s = 1,
10151 .db = 1,
10152 .g = 1
10153 };
10154 seg.selector = vmcs12->host_ds_selector;
10155 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10156 seg.selector = vmcs12->host_es_selector;
10157 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10158 seg.selector = vmcs12->host_ss_selector;
10159 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10160 seg.selector = vmcs12->host_fs_selector;
10161 seg.base = vmcs12->host_fs_base;
10162 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10163 seg.selector = vmcs12->host_gs_selector;
10164 seg.base = vmcs12->host_gs_base;
10165 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10166 seg = (struct kvm_segment) {
205befd9 10167 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 10168 .limit = 0x67,
10169 .selector = vmcs12->host_tr_selector,
10170 .type = 11,
10171 .present = 1
10172 };
10173 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10174
503cd0c5
JK		 10175 kvm_set_dr(vcpu, 7, 0x400);
10176 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 10177
3af18d9c
WV		 10178 if (cpu_has_vmx_msr_bitmap())
10179 vmx_set_msr_bitmap(vcpu);
10180
ff651cb6
WV		 10181 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10182 vmcs12->vm_exit_msr_load_count))
10183 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 10184}
10185
10186/*
10187 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10188 * and modify vmcs12 to make it see what it would expect to see there if
10189 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10190 */
533558bc
JK		 10191static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10192 u32 exit_intr_info,
10193 unsigned long exit_qualification)
4704d0be
NHE		 10194{
10195 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 10196 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10197
5f3d5799
JK		 10198 /* trying to cancel vmlaunch/vmresume is a bug */
10199 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10200
4704d0be 10201 leave_guest_mode(vcpu);
533558bc
JK		 10202 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10203 exit_qualification);
4704d0be 10204
ff651cb6
WV		 10205 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10206 vmcs12->vm_exit_msr_store_count))
10207 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10208
f3380ca5
WL		 10209 vmx_load_vmcs01(vcpu);
10210
77b0f5d6
BD		 10211 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10212 && nested_exit_intr_ack_set(vcpu)) {
10213 int irq = kvm_cpu_get_interrupt(vcpu);
10214 WARN_ON(irq < 0);
10215 vmcs12->vm_exit_intr_info = irq |
10216 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10217 }
10218
542060ea
JK		 10219 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10220 vmcs12->exit_qualification,
10221 vmcs12->idt_vectoring_info_field,
10222 vmcs12->vm_exit_intr_info,
10223 vmcs12->vm_exit_intr_error_code,
10224 KVM_ISA_VMX);
4704d0be 10225
2961e876
GN		 10226 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10227 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 10228 vmx_segment_cache_clear(vmx);
10229
4704d0be
NHE		 10230 /* if no vmcs02 cache requested, remove the one we used */
10231 if (VMCS02_POOL_SIZE == 0)
10232 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10233
10234 load_vmcs12_host_state(vcpu, vmcs12);
10235
27fc51b2 10236 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 10237 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10238
10239 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10240 vmx->host_rsp = 0;
10241
10242 /* Unpin physical memory we referred to in vmcs02 */
10243 if (vmx->nested.apic_access_page) {
10244 nested_release_page(vmx->nested.apic_access_page);
48d89b92 10245 vmx->nested.apic_access_page = NULL;
4704d0be 10246 }
a7c0b07d
WL		 10247 if (vmx->nested.virtual_apic_page) {
10248 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 10249 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 10250 }
705699a1
WV		 10251 if (vmx->nested.pi_desc_page) {
10252 kunmap(vmx->nested.pi_desc_page);
10253 nested_release_page(vmx->nested.pi_desc_page);
10254 vmx->nested.pi_desc_page = NULL;
10255 vmx->nested.pi_desc = NULL;
10256 }
4704d0be 10257
38b99173
TC		 10258 /*
10259 * We are now running in L2, mmu_notifier will force to reload the
10260 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10261 */
10262 kvm_vcpu_reload_apic_access_page(vcpu);
10263
4704d0be
NHE		 10264 /*
10265 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10266 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10267 * success or failure flag accordingly.
10268 */
10269 if (unlikely(vmx->fail)) {
10270 vmx->fail = 0;
10271 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10272 } else
10273 nested_vmx_succeed(vcpu);
012f83cb
AG		 10274 if (enable_shadow_vmcs)
10275 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 10276
10277 /* in case we halted in L2 */
10278 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 10279}
10280
42124925
JK		 10281/*
10282 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10283 */
10284static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10285{
10286 if (is_guest_mode(vcpu))
533558bc 10287 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 10288 free_nested(to_vmx(vcpu));
10289}
10290
7c177938
NHE		 10291/*
10292 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10293 * 23.7 "VM-entry failures during or after loading guest state" (this also
10294 * lists the acceptable exit-reason and exit-qualification parameters).
10295 * It should only be called before L2 actually succeeded to run, and when
10296 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10297 */
10298static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10299 struct vmcs12 *vmcs12,
10300 u32 reason, unsigned long qualification)
10301{
10302 load_vmcs12_host_state(vcpu, vmcs12);
10303 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10304 vmcs12->exit_qualification = qualification;
10305 nested_vmx_succeed(vcpu);
012f83cb
AG		 10306 if (enable_shadow_vmcs)
10307 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 10308}
10309
8a76d7f2
JR		 10310static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10311 struct x86_instruction_info *info,
10312 enum x86_intercept_stage stage)
10313{
10314 return X86EMUL_CONTINUE;
10315}
10316
48d89b92 10317static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 10318{
b4a2d31d
RK		 10319 if (ple_gap)
10320 shrink_ple_window(vcpu);
ae97a3b8
RK		 10321}
10322
843e4330
KH		 10323static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10324 struct kvm_memory_slot *slot)
10325{
10326 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10327 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10328}
10329
10330static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10331 struct kvm_memory_slot *slot)
10332{
10333 kvm_mmu_slot_set_dirty(kvm, slot);
10334}
10335
10336static void vmx_flush_log_dirty(struct kvm *kvm)
10337{
10338 kvm_flush_pml_buffers(kvm);
10339}
10340
10341static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10342 struct kvm_memory_slot *memslot,
10343 gfn_t offset, unsigned long mask)
10344{
10345 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10346}
10347
cbdd1bea 10348static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 10349 .cpu_has_kvm_support = cpu_has_kvm_support,
10350 .disabled_by_bios = vmx_disabled_by_bios,
10351 .hardware_setup = hardware_setup,
10352 .hardware_unsetup = hardware_unsetup,
002c7f7c 10353 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 10354 .hardware_enable = hardware_enable,
10355 .hardware_disable = hardware_disable,
04547156 10356 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 10357 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK		 10358
10359 .vcpu_create = vmx_create_vcpu,
10360 .vcpu_free = vmx_free_vcpu,
04d2cc77 10361 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 10362
04d2cc77 10363 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 10364 .vcpu_load = vmx_vcpu_load,
10365 .vcpu_put = vmx_vcpu_put,
10366
c8639010 10367 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 10368 .get_msr = vmx_get_msr,
10369 .set_msr = vmx_set_msr,
10370 .get_segment_base = vmx_get_segment_base,
10371 .get_segment = vmx_get_segment,
10372 .set_segment = vmx_set_segment,
2e4d2653 10373 .get_cpl = vmx_get_cpl,
6aa8b732 10374 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 10375 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 10376 .decache_cr3 = vmx_decache_cr3,
25c4c276 10377 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 10378 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 10379 .set_cr3 = vmx_set_cr3,
10380 .set_cr4 = vmx_set_cr4,
6aa8b732 10381 .set_efer = vmx_set_efer,
6aa8b732
AK		 10382 .get_idt = vmx_get_idt,
10383 .set_idt = vmx_set_idt,
10384 .get_gdt = vmx_get_gdt,
10385 .set_gdt = vmx_set_gdt,
73aaf249
JK		 10386 .get_dr6 = vmx_get_dr6,
10387 .set_dr6 = vmx_set_dr6,
020df079 10388 .set_dr7 = vmx_set_dr7,
81908bf4 10389 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 10390 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 10391 .get_rflags = vmx_get_rflags,
10392 .set_rflags = vmx_set_rflags,
0fdd74f7 10393 .fpu_activate = vmx_fpu_activate,
02daab21 10394 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 10395
10396 .tlb_flush = vmx_flush_tlb,
6aa8b732 10397
6aa8b732 10398 .run = vmx_vcpu_run,
6062d012 10399 .handle_exit = vmx_handle_exit,
6aa8b732 10400 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 10401 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10402 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 10403 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 10404 .set_irq = vmx_inject_irq,
95ba8273 10405 .set_nmi = vmx_inject_nmi,
298101da 10406 .queue_exception = vmx_queue_exception,
b463a6f7 10407 .cancel_injection = vmx_cancel_injection,
78646121 10408 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 10409 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 10410 .get_nmi_mask = vmx_get_nmi_mask,
10411 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 10412 .enable_nmi_window = enable_nmi_window,
10413 .enable_irq_window = enable_irq_window,
10414 .update_cr8_intercept = update_cr8_intercept,
8d14695f 10415 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 10416 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d50ab6c1 10417 .cpu_uses_apicv = vmx_cpu_uses_apicv,
c7c9c56c
YZ		 10418 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10419 .hwapic_irr_update = vmx_hwapic_irr_update,
10420 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 10421 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10422 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 10423
cbc94022 10424 .set_tss_addr = vmx_set_tss_addr,
67253af5 10425 .get_tdp_level = get_ept_level,
4b12f0de 10426 .get_mt_mask = vmx_get_mt_mask,
229456fc 10427
586f9607 10428 .get_exit_info = vmx_get_exit_info,
586f9607 10429
17cc3935 10430 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 10431
10432 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 10433
10434 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 10435 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 10436
10437 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 10438
10439 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 10440
4051b188 10441 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 10442 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 10443 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 10444 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 10445 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 10446 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 10447
10448 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 10449
10450 .check_intercept = vmx_check_intercept,
a547c6db 10451 .handle_external_intr = vmx_handle_external_intr,
da8999d3 10452 .mpx_supported = vmx_mpx_supported,
55412b2e 10453 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 10454
10455 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 10456
10457 .sched_in = vmx_sched_in,
843e4330
KH		 10458
10459 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10460 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10461 .flush_log_dirty = vmx_flush_log_dirty,
10462 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
25462f7f
WH		 10463
10464 .pmu_ops = &intel_pmu_ops,
6aa8b732
AK		 10465};
10466
10467static int __init vmx_init(void)
10468{
34a1cd60
TC		 10469 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10470 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 10471 if (r)
34a1cd60 10472 return r;
25c5f225 10473
2965faa5 10474#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 10475 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10476 crash_vmclear_local_loaded_vmcss);
10477#endif
10478
fdef3ad1 10479 return 0;
6aa8b732
AK		 10480}
10481
10482static void __exit vmx_exit(void)
10483{
2965faa5 10484#ifdef CONFIG_KEXEC_CORE
3b63a43f 10485 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10486 synchronize_rcu();
10487#endif
10488
cb498ea2 10489 kvm_exit();
6aa8b732
AK		 10490}
10491
10492module_init(vmx_init)
10493module_exit(vmx_exit)
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