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KVM: Extend struct pi_desc for VT-d Posted-Interrupts
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
af658dca 31#include <linux/trace_events.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
952f07ec 43#include <asm/fpu/internal.h>
d7cd9796 44#include <asm/perf_event.h>
81908bf4 45#include <asm/debugreg.h>
8f536b76 46#include <asm/kexec.h>
dab2087d 47#include <asm/apic.h>
6aa8b732 48
229456fc 49#include "trace.h"
25462f7f 50#include "pmu.h"
229456fc 51
4ecac3fd 52#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 53#define __ex_clear(x, reg) \
54 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 55
6aa8b732
AK		 56MODULE_AUTHOR("Qumranet");
57MODULE_LICENSE("GPL");
58
e9bda3b3
JT		 59static const struct x86_cpu_id vmx_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_VMX),
61 {}
62};
63MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
64
476bc001 65static bool __read_mostly enable_vpid = 1;
736caefe 66module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 67
476bc001 68static bool __read_mostly flexpriority_enabled = 1;
736caefe 69module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 70
476bc001 71static bool __read_mostly enable_ept = 1;
736caefe 72module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 73
476bc001 74static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 75module_param_named(unrestricted_guest,
76 enable_unrestricted_guest, bool, S_IRUGO);
77
83c3a331
XH		 78static bool __read_mostly enable_ept_ad_bits = 1;
79module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
80
a27685c3 81static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 82module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 83
476bc001 84static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 85module_param(vmm_exclusive, bool, S_IRUGO);
86
476bc001 87static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 88module_param(fasteoi, bool, S_IRUGO);
89
5a71785d 90static bool __read_mostly enable_apicv = 1;
01e439be 91module_param(enable_apicv, bool, S_IRUGO);
83d4c286 92
abc4fc58
AG		 93static bool __read_mostly enable_shadow_vmcs = 1;
94module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 95/*
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
99 */
476bc001 100static bool __read_mostly nested = 0;
801d3424
NHE		 101module_param(nested, bool, S_IRUGO);
102
20300099
WL		 103static u64 __read_mostly host_xss;
104
843e4330
KH		 105static bool __read_mostly enable_pml = 1;
106module_param_named(pml, enable_pml, bool, S_IRUGO);
107
5037878e
GN		 108#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 110#define KVM_VM_CR0_ALWAYS_ON \
111 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 112#define KVM_CR4_GUEST_OWNED_BITS \
113 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 114 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 115
cdc0e244
AK		 116#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
118
78ac8b47
AK		 119#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
120
f4124500
JK		 121#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
122
4b8d54f9
ZE		 123/*
124 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125 * ple_gap: upper bound on the amount of time between two successive
126 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 127 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 128 * ple_window: upper bound on the amount of time a guest is allowed to execute
129 * in a PAUSE loop. Tests indicate that most spinlocks are held for
130 * less than 2^12 cycles
131 * Time is measured based on a counter that runs at the same rate as the TSC,
132 * refer SDM volume 3b section 21.6.13 & 22.1.3.
133 */
b4a2d31d
RK		 134#define KVM_VMX_DEFAULT_PLE_GAP 128
135#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
136#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
137#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
139 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
140
4b8d54f9
ZE		 141static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
142module_param(ple_gap, int, S_IRUGO);
143
144static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
145module_param(ple_window, int, S_IRUGO);
146
b4a2d31d
RK		 147/* Default doubles per-vcpu window every exit. */
148static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
149module_param(ple_window_grow, int, S_IRUGO);
150
151/* Default resets per-vcpu window every exit to ple_window. */
152static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
153module_param(ple_window_shrink, int, S_IRUGO);
154
155/* Default is to compute the maximum so we can never overflow. */
156static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
158module_param(ple_window_max, int, S_IRUGO);
159
83287ea4
AK		 160extern const ulong vmx_return;
161
8bf00a52 162#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 163#define VMCS02_POOL_SIZE 1
61d2ef2c 164
a2fa3e9f
GH		 165struct vmcs {
166 u32 revision_id;
167 u32 abort;
168 char data[0];
169};
170
d462b819
NHE		 171/*
172 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174 * loaded on this CPU (so we can clear them if the CPU goes down).
175 */
176struct loaded_vmcs {
177 struct vmcs *vmcs;
178 int cpu;
179 int launched;
180 struct list_head loaded_vmcss_on_cpu_link;
181};
182
26bb0981
AK		 183struct shared_msr_entry {
184 unsigned index;
185 u64 data;
d5696725 186 u64 mask;
26bb0981
AK		 187};
188
a9d30f33
NHE		 189/*
190 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195 * More than one of these structures may exist, if L1 runs multiple L2 guests.
196 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197 * underlying hardware which will be used to run L2.
198 * This structure is packed to ensure that its layout is identical across
199 * machines (necessary for live migration).
200 * If there are changes in this struct, VMCS12_REVISION must be changed.
201 */
22bd0358 202typedef u64 natural_width;
a9d30f33
NHE		 203struct __packed vmcs12 {
204 /* According to the Intel spec, a VMCS region must start with the
205 * following two fields. Then follow implementation-specific data.
206 */
207 u32 revision_id;
208 u32 abort;
22bd0358 209
27d6c865
NHE		 210 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211 u32 padding[7]; /* room for future expansion */
212
22bd0358
NHE		 213 u64 io_bitmap_a;
214 u64 io_bitmap_b;
215 u64 msr_bitmap;
216 u64 vm_exit_msr_store_addr;
217 u64 vm_exit_msr_load_addr;
218 u64 vm_entry_msr_load_addr;
219 u64 tsc_offset;
220 u64 virtual_apic_page_addr;
221 u64 apic_access_addr;
705699a1 222 u64 posted_intr_desc_addr;
22bd0358 223 u64 ept_pointer;
608406e2
WV		 224 u64 eoi_exit_bitmap0;
225 u64 eoi_exit_bitmap1;
226 u64 eoi_exit_bitmap2;
227 u64 eoi_exit_bitmap3;
81dc01f7 228 u64 xss_exit_bitmap;
22bd0358
NHE		 229 u64 guest_physical_address;
230 u64 vmcs_link_pointer;
231 u64 guest_ia32_debugctl;
232 u64 guest_ia32_pat;
233 u64 guest_ia32_efer;
234 u64 guest_ia32_perf_global_ctrl;
235 u64 guest_pdptr0;
236 u64 guest_pdptr1;
237 u64 guest_pdptr2;
238 u64 guest_pdptr3;
36be0b9d 239 u64 guest_bndcfgs;
22bd0358
NHE		 240 u64 host_ia32_pat;
241 u64 host_ia32_efer;
242 u64 host_ia32_perf_global_ctrl;
243 u64 padding64[8]; /* room for future expansion */
244 /*
245 * To allow migration of L1 (complete with its L2 guests) between
246 * machines of different natural widths (32 or 64 bit), we cannot have
247 * unsigned long fields with no explict size. We use u64 (aliased
248 * natural_width) instead. Luckily, x86 is little-endian.
249 */
250 natural_width cr0_guest_host_mask;
251 natural_width cr4_guest_host_mask;
252 natural_width cr0_read_shadow;
253 natural_width cr4_read_shadow;
254 natural_width cr3_target_value0;
255 natural_width cr3_target_value1;
256 natural_width cr3_target_value2;
257 natural_width cr3_target_value3;
258 natural_width exit_qualification;
259 natural_width guest_linear_address;
260 natural_width guest_cr0;
261 natural_width guest_cr3;
262 natural_width guest_cr4;
263 natural_width guest_es_base;
264 natural_width guest_cs_base;
265 natural_width guest_ss_base;
266 natural_width guest_ds_base;
267 natural_width guest_fs_base;
268 natural_width guest_gs_base;
269 natural_width guest_ldtr_base;
270 natural_width guest_tr_base;
271 natural_width guest_gdtr_base;
272 natural_width guest_idtr_base;
273 natural_width guest_dr7;
274 natural_width guest_rsp;
275 natural_width guest_rip;
276 natural_width guest_rflags;
277 natural_width guest_pending_dbg_exceptions;
278 natural_width guest_sysenter_esp;
279 natural_width guest_sysenter_eip;
280 natural_width host_cr0;
281 natural_width host_cr3;
282 natural_width host_cr4;
283 natural_width host_fs_base;
284 natural_width host_gs_base;
285 natural_width host_tr_base;
286 natural_width host_gdtr_base;
287 natural_width host_idtr_base;
288 natural_width host_ia32_sysenter_esp;
289 natural_width host_ia32_sysenter_eip;
290 natural_width host_rsp;
291 natural_width host_rip;
292 natural_width paddingl[8]; /* room for future expansion */
293 u32 pin_based_vm_exec_control;
294 u32 cpu_based_vm_exec_control;
295 u32 exception_bitmap;
296 u32 page_fault_error_code_mask;
297 u32 page_fault_error_code_match;
298 u32 cr3_target_count;
299 u32 vm_exit_controls;
300 u32 vm_exit_msr_store_count;
301 u32 vm_exit_msr_load_count;
302 u32 vm_entry_controls;
303 u32 vm_entry_msr_load_count;
304 u32 vm_entry_intr_info_field;
305 u32 vm_entry_exception_error_code;
306 u32 vm_entry_instruction_len;
307 u32 tpr_threshold;
308 u32 secondary_vm_exec_control;
309 u32 vm_instruction_error;
310 u32 vm_exit_reason;
311 u32 vm_exit_intr_info;
312 u32 vm_exit_intr_error_code;
313 u32 idt_vectoring_info_field;
314 u32 idt_vectoring_error_code;
315 u32 vm_exit_instruction_len;
316 u32 vmx_instruction_info;
317 u32 guest_es_limit;
318 u32 guest_cs_limit;
319 u32 guest_ss_limit;
320 u32 guest_ds_limit;
321 u32 guest_fs_limit;
322 u32 guest_gs_limit;
323 u32 guest_ldtr_limit;
324 u32 guest_tr_limit;
325 u32 guest_gdtr_limit;
326 u32 guest_idtr_limit;
327 u32 guest_es_ar_bytes;
328 u32 guest_cs_ar_bytes;
329 u32 guest_ss_ar_bytes;
330 u32 guest_ds_ar_bytes;
331 u32 guest_fs_ar_bytes;
332 u32 guest_gs_ar_bytes;
333 u32 guest_ldtr_ar_bytes;
334 u32 guest_tr_ar_bytes;
335 u32 guest_interruptibility_info;
336 u32 guest_activity_state;
337 u32 guest_sysenter_cs;
338 u32 host_ia32_sysenter_cs;
0238ea91
JK		 339 u32 vmx_preemption_timer_value;
340 u32 padding32[7]; /* room for future expansion */
22bd0358 341 u16 virtual_processor_id;
705699a1 342 u16 posted_intr_nv;
22bd0358
NHE		 343 u16 guest_es_selector;
344 u16 guest_cs_selector;
345 u16 guest_ss_selector;
346 u16 guest_ds_selector;
347 u16 guest_fs_selector;
348 u16 guest_gs_selector;
349 u16 guest_ldtr_selector;
350 u16 guest_tr_selector;
608406e2 351 u16 guest_intr_status;
22bd0358
NHE		 352 u16 host_es_selector;
353 u16 host_cs_selector;
354 u16 host_ss_selector;
355 u16 host_ds_selector;
356 u16 host_fs_selector;
357 u16 host_gs_selector;
358 u16 host_tr_selector;
a9d30f33
NHE		 359};
360
361/*
362 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
365 */
366#define VMCS12_REVISION 0x11e57ed0
367
368/*
369 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371 * current implementation, 4K are reserved to avoid future complications.
372 */
373#define VMCS12_SIZE 0x1000
374
ff2f6fe9
NHE		 375/* Used to remember the last vmcs02 used for some recently used vmcs12s */
376struct vmcs02_list {
377 struct list_head list;
378 gpa_t vmptr;
379 struct loaded_vmcs vmcs02;
380};
381
ec378aee
NHE		 382/*
383 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
385 */
386struct nested_vmx {
387 /* Has the level1 guest done vmxon? */
388 bool vmxon;
3573e22c 389 gpa_t vmxon_ptr;
a9d30f33
NHE		 390
391 /* The guest-physical address of the current VMCS L1 keeps for L2 */
392 gpa_t current_vmptr;
393 /* The host-usable pointer to the above */
394 struct page *current_vmcs12_page;
395 struct vmcs12 *current_vmcs12;
8de48833 396 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 397 /*
398 * Indicates if the shadow vmcs must be updated with the
399 * data hold by vmcs12
400 */
401 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 402
403 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404 struct list_head vmcs02_pool;
405 int vmcs02_num;
fe3ef05c 406 u64 vmcs01_tsc_offset;
644d711a
NHE		 407 /* L2 must run next, and mustn't decide to exit to L1. */
408 bool nested_run_pending;
fe3ef05c
NHE		 409 /*
410 * Guest pages referred to in vmcs02 with host-physical pointers, so
411 * we must keep them pinned while L2 runs.
412 */
413 struct page *apic_access_page;
a7c0b07d 414 struct page *virtual_apic_page;
705699a1
WV		 415 struct page *pi_desc_page;
416 struct pi_desc *pi_desc;
417 bool pi_pending;
418 u16 posted_intr_nv;
b3897a49 419 u64 msr_ia32_feature_control;
f4124500
JK		 420
421 struct hrtimer preemption_timer;
422 bool preemption_timer_expired;
2996fca0
JK		 423
424 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
425 u64 vmcs01_debugctl;
b9c237bb
WV		 426
427 u32 nested_vmx_procbased_ctls_low;
428 u32 nested_vmx_procbased_ctls_high;
429 u32 nested_vmx_true_procbased_ctls_low;
430 u32 nested_vmx_secondary_ctls_low;
431 u32 nested_vmx_secondary_ctls_high;
432 u32 nested_vmx_pinbased_ctls_low;
433 u32 nested_vmx_pinbased_ctls_high;
434 u32 nested_vmx_exit_ctls_low;
435 u32 nested_vmx_exit_ctls_high;
436 u32 nested_vmx_true_exit_ctls_low;
437 u32 nested_vmx_entry_ctls_low;
438 u32 nested_vmx_entry_ctls_high;
439 u32 nested_vmx_true_entry_ctls_low;
440 u32 nested_vmx_misc_low;
441 u32 nested_vmx_misc_high;
442 u32 nested_vmx_ept_caps;
ec378aee
NHE		 443};
444
01e439be
YZ		 445#define POSTED_INTR_ON 0
446/* Posted-Interrupt Descriptor */
447struct pi_desc {
448 u32 pir[8]; /* Posted interrupt requested */
6ef1522f
FW		 449 union {
450 struct {
451 /* bit 256 - Outstanding Notification */
452 u16 on : 1,
453 /* bit 257 - Suppress Notification */
454 sn : 1,
455 /* bit 271:258 - Reserved */
456 rsvd_1 : 14;
457 /* bit 279:272 - Notification Vector */
458 u8 nv;
459 /* bit 287:280 - Reserved */
460 u8 rsvd_2;
461 /* bit 319:288 - Notification Destination */
462 u32 ndst;
463 };
464 u64 control;
465 };
466 u32 rsvd[6];
01e439be
YZ		 467} __aligned(64);
468
a20ed54d
YZ		 469static bool pi_test_and_set_on(struct pi_desc *pi_desc)
470{
471 return test_and_set_bit(POSTED_INTR_ON,
472 (unsigned long *)&pi_desc->control);
473}
474
475static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
476{
477 return test_and_clear_bit(POSTED_INTR_ON,
478 (unsigned long *)&pi_desc->control);
479}
480
481static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
482{
483 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
484}
485
a2fa3e9f 486struct vcpu_vmx {
fb3f0f51 487 struct kvm_vcpu vcpu;
313dbd49 488 unsigned long host_rsp;
29bd8a78 489 u8 fail;
9d58b931 490 bool nmi_known_unmasked;
51aa01d1 491 u32 exit_intr_info;
1155f76a 492 u32 idt_vectoring_info;
6de12732 493 ulong rflags;
26bb0981 494 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 495 int nmsrs;
496 int save_nmsrs;
a547c6db 497 unsigned long host_idt_base;
a2fa3e9f 498#ifdef CONFIG_X86_64
44ea2b17
AK		 499 u64 msr_host_kernel_gs_base;
500 u64 msr_guest_kernel_gs_base;
a2fa3e9f 501#endif
2961e876
GN		 502 u32 vm_entry_controls_shadow;
503 u32 vm_exit_controls_shadow;
d462b819
NHE		 504 /*
505 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
506 * non-nested (L1) guest, it always points to vmcs01. For a nested
507 * guest (L2), it points to a different VMCS.
508 */
509 struct loaded_vmcs vmcs01;
510 struct loaded_vmcs *loaded_vmcs;
511 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 512 struct msr_autoload {
513 unsigned nr;
514 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
515 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
516 } msr_autoload;
a2fa3e9f
GH		 517 struct {
518 int loaded;
519 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 520#ifdef CONFIG_X86_64
521 u16 ds_sel, es_sel;
522#endif
152d3f2f
LV		 523 int gs_ldt_reload_needed;
524 int fs_reload_needed;
da8999d3 525 u64 msr_host_bndcfgs;
d974baa3 526 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 527 } host_state;
9c8cba37 528 struct {
7ffd92c5 529 int vm86_active;
78ac8b47 530 ulong save_rflags;
f5f7b2fe
AK		 531 struct kvm_segment segs[8];
532 } rmode;
533 struct {
534 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 535 struct kvm_save_segment {
536 u16 selector;
537 unsigned long base;
538 u32 limit;
539 u32 ar;
f5f7b2fe 540 } seg[8];
2fb92db1 541 } segment_cache;
2384d2b3 542 int vpid;
04fa4d32 543 bool emulation_required;
3b86cd99
JK		 544
545 /* Support for vnmi-less CPUs */
546 int soft_vnmi_blocked;
547 ktime_t entry_time;
548 s64 vnmi_blocked_time;
a0861c02 549 u32 exit_reason;
4e47c7a6 550
01e439be
YZ		 551 /* Posted interrupt descriptor */
552 struct pi_desc pi_desc;
553
ec378aee
NHE		 554 /* Support for a guest hypervisor (nested VMX) */
555 struct nested_vmx nested;
a7653ecd
RK		 556
557 /* Dynamic PLE window. */
558 int ple_window;
559 bool ple_window_dirty;
843e4330
KH		 560
561 /* Support for PML */
562#define PML_ENTITY_NUM 512
563 struct page *pml_pg;
a2fa3e9f
GH		 564};
565
2fb92db1
AK		 566enum segment_cache_field {
567 SEG_FIELD_SEL = 0,
568 SEG_FIELD_BASE = 1,
569 SEG_FIELD_LIMIT = 2,
570 SEG_FIELD_AR = 3,
571
572 SEG_FIELD_NR = 4
573};
574
a2fa3e9f
GH		 575static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
576{
fb3f0f51 577 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 578}
579
22bd0358
NHE		 580#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
581#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
582#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
583 [number##_HIGH] = VMCS12_OFFSET(name)+4
584
4607c2d7 585
fe2b201b 586static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 587 /*
588 * We do NOT shadow fields that are modified when L0
589 * traps and emulates any vmx instruction (e.g. VMPTRLD,
590 * VMXON...) executed by L1.
591 * For example, VM_INSTRUCTION_ERROR is read
592 * by L1 if a vmx instruction fails (part of the error path).
593 * Note the code assumes this logic. If for some reason
594 * we start shadowing these fields then we need to
595 * force a shadow sync when L0 emulates vmx instructions
596 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
597 * by nested_vmx_failValid)
598 */
599 VM_EXIT_REASON,
600 VM_EXIT_INTR_INFO,
601 VM_EXIT_INSTRUCTION_LEN,
602 IDT_VECTORING_INFO_FIELD,
603 IDT_VECTORING_ERROR_CODE,
604 VM_EXIT_INTR_ERROR_CODE,
605 EXIT_QUALIFICATION,
606 GUEST_LINEAR_ADDRESS,
607 GUEST_PHYSICAL_ADDRESS
608};
fe2b201b 609static int max_shadow_read_only_fields =
4607c2d7
AG		 610 ARRAY_SIZE(shadow_read_only_fields);
611
fe2b201b 612static unsigned long shadow_read_write_fields[] = {
a7c0b07d 613 TPR_THRESHOLD,
4607c2d7
AG		 614 GUEST_RIP,
615 GUEST_RSP,
616 GUEST_CR0,
617 GUEST_CR3,
618 GUEST_CR4,
619 GUEST_INTERRUPTIBILITY_INFO,
620 GUEST_RFLAGS,
621 GUEST_CS_SELECTOR,
622 GUEST_CS_AR_BYTES,
623 GUEST_CS_LIMIT,
624 GUEST_CS_BASE,
625 GUEST_ES_BASE,
36be0b9d 626 GUEST_BNDCFGS,
4607c2d7
AG		 627 CR0_GUEST_HOST_MASK,
628 CR0_READ_SHADOW,
629 CR4_READ_SHADOW,
630 TSC_OFFSET,
631 EXCEPTION_BITMAP,
632 CPU_BASED_VM_EXEC_CONTROL,
633 VM_ENTRY_EXCEPTION_ERROR_CODE,
634 VM_ENTRY_INTR_INFO_FIELD,
635 VM_ENTRY_INSTRUCTION_LEN,
636 VM_ENTRY_EXCEPTION_ERROR_CODE,
637 HOST_FS_BASE,
638 HOST_GS_BASE,
639 HOST_FS_SELECTOR,
640 HOST_GS_SELECTOR
641};
fe2b201b 642static int max_shadow_read_write_fields =
4607c2d7
AG		 643 ARRAY_SIZE(shadow_read_write_fields);
644
772e0318 645static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 646 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 647 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE		 648 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
649 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
650 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
651 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
652 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
653 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
654 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
655 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 656 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 657 FIELD(HOST_ES_SELECTOR, host_es_selector),
658 FIELD(HOST_CS_SELECTOR, host_cs_selector),
659 FIELD(HOST_SS_SELECTOR, host_ss_selector),
660 FIELD(HOST_DS_SELECTOR, host_ds_selector),
661 FIELD(HOST_FS_SELECTOR, host_fs_selector),
662 FIELD(HOST_GS_SELECTOR, host_gs_selector),
663 FIELD(HOST_TR_SELECTOR, host_tr_selector),
664 FIELD64(IO_BITMAP_A, io_bitmap_a),
665 FIELD64(IO_BITMAP_B, io_bitmap_b),
666 FIELD64(MSR_BITMAP, msr_bitmap),
667 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
668 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
669 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
670 FIELD64(TSC_OFFSET, tsc_offset),
671 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
672 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 673 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 674 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 675 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
676 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
677 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
678 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 679 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 680 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
681 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
682 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
683 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
684 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
685 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
686 FIELD64(GUEST_PDPTR0, guest_pdptr0),
687 FIELD64(GUEST_PDPTR1, guest_pdptr1),
688 FIELD64(GUEST_PDPTR2, guest_pdptr2),
689 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 690 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 691 FIELD64(HOST_IA32_PAT, host_ia32_pat),
692 FIELD64(HOST_IA32_EFER, host_ia32_efer),
693 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
694 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
695 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
696 FIELD(EXCEPTION_BITMAP, exception_bitmap),
697 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
698 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
699 FIELD(CR3_TARGET_COUNT, cr3_target_count),
700 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
701 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
702 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
703 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
704 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
705 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
706 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
707 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
708 FIELD(TPR_THRESHOLD, tpr_threshold),
709 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
710 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
711 FIELD(VM_EXIT_REASON, vm_exit_reason),
712 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
713 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
714 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
715 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
716 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
717 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
718 FIELD(GUEST_ES_LIMIT, guest_es_limit),
719 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
720 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
721 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
722 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
723 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
724 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
725 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
726 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
727 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
728 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
729 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
730 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
731 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
732 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
733 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
734 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
735 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
736 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
737 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
738 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
739 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 740 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 741 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
742 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
743 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
744 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
745 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
746 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
747 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
748 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
749 FIELD(EXIT_QUALIFICATION, exit_qualification),
750 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
751 FIELD(GUEST_CR0, guest_cr0),
752 FIELD(GUEST_CR3, guest_cr3),
753 FIELD(GUEST_CR4, guest_cr4),
754 FIELD(GUEST_ES_BASE, guest_es_base),
755 FIELD(GUEST_CS_BASE, guest_cs_base),
756 FIELD(GUEST_SS_BASE, guest_ss_base),
757 FIELD(GUEST_DS_BASE, guest_ds_base),
758 FIELD(GUEST_FS_BASE, guest_fs_base),
759 FIELD(GUEST_GS_BASE, guest_gs_base),
760 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
761 FIELD(GUEST_TR_BASE, guest_tr_base),
762 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
763 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
764 FIELD(GUEST_DR7, guest_dr7),
765 FIELD(GUEST_RSP, guest_rsp),
766 FIELD(GUEST_RIP, guest_rip),
767 FIELD(GUEST_RFLAGS, guest_rflags),
768 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
769 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
770 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
771 FIELD(HOST_CR0, host_cr0),
772 FIELD(HOST_CR3, host_cr3),
773 FIELD(HOST_CR4, host_cr4),
774 FIELD(HOST_FS_BASE, host_fs_base),
775 FIELD(HOST_GS_BASE, host_gs_base),
776 FIELD(HOST_TR_BASE, host_tr_base),
777 FIELD(HOST_GDTR_BASE, host_gdtr_base),
778 FIELD(HOST_IDTR_BASE, host_idtr_base),
779 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
780 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
781 FIELD(HOST_RSP, host_rsp),
782 FIELD(HOST_RIP, host_rip),
783};
22bd0358
NHE		 784
785static inline short vmcs_field_to_offset(unsigned long field)
786{
a2ae9df7
PB		 787 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
788
789 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
790 vmcs_field_to_offset_table[field] == 0)
791 return -ENOENT;
792
22bd0358
NHE		 793 return vmcs_field_to_offset_table[field];
794}
795
a9d30f33
NHE		 796static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
797{
798 return to_vmx(vcpu)->nested.current_vmcs12;
799}
800
801static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
802{
54bf36aa 803 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 804 if (is_error_page(page))
a9d30f33 805 return NULL;
32cad84f 806
a9d30f33
NHE		 807 return page;
808}
809
810static void nested_release_page(struct page *page)
811{
812 kvm_release_page_dirty(page);
813}
814
815static void nested_release_page_clean(struct page *page)
816{
817 kvm_release_page_clean(page);
818}
819
bfd0a56b 820static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 821static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 822static void kvm_cpu_vmxon(u64 addr);
823static void kvm_cpu_vmxoff(void);
93c4adc7 824static bool vmx_mpx_supported(void);
f53cd63c 825static bool vmx_xsaves_supported(void);
d50ab6c1 826static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
776e58ea 827static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 828static void vmx_set_segment(struct kvm_vcpu *vcpu,
829 struct kvm_segment *var, int seg);
830static void vmx_get_segment(struct kvm_vcpu *vcpu,
831 struct kvm_segment *var, int seg);
d99e4152
GN		 832static bool guest_state_valid(struct kvm_vcpu *vcpu);
833static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 834static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 835static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 836static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 837static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 838
6aa8b732
AK		 839static DEFINE_PER_CPU(struct vmcs *, vmxarea);
840static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 841/*
842 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
843 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
844 */
845static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 846static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 847
3e7c73e9
AK		 848static unsigned long *vmx_io_bitmap_a;
849static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 850static unsigned long *vmx_msr_bitmap_legacy;
851static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 852static unsigned long *vmx_msr_bitmap_legacy_x2apic;
853static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 854static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 855static unsigned long *vmx_vmread_bitmap;
856static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 857
110312c8 858static bool cpu_has_load_ia32_efer;
8bf00a52 859static bool cpu_has_load_perf_global_ctrl;
110312c8 860
2384d2b3
SY		 861static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
862static DEFINE_SPINLOCK(vmx_vpid_lock);
863
1c3d14fe 864static struct vmcs_config {
6aa8b732
AK		 865 int size;
866 int order;
867 u32 revision_id;
1c3d14fe
YS		 868 u32 pin_based_exec_ctrl;
869 u32 cpu_based_exec_ctrl;
f78e0e2e 870 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 871 u32 vmexit_ctrl;
872 u32 vmentry_ctrl;
873} vmcs_config;
6aa8b732 874
efff9e53 875static struct vmx_capability {
d56f546d
SY		 876 u32 ept;
877 u32 vpid;
878} vmx_capability;
879
6aa8b732
AK		 880#define VMX_SEGMENT_FIELD(seg) \
881 [VCPU_SREG_##seg] = { \
882 .selector = GUEST_##seg##_SELECTOR, \
883 .base = GUEST_##seg##_BASE, \
884 .limit = GUEST_##seg##_LIMIT, \
885 .ar_bytes = GUEST_##seg##_AR_BYTES, \
886 }
887
772e0318 888static const struct kvm_vmx_segment_field {
6aa8b732
AK		 889 unsigned selector;
890 unsigned base;
891 unsigned limit;
892 unsigned ar_bytes;
893} kvm_vmx_segment_fields[] = {
894 VMX_SEGMENT_FIELD(CS),
895 VMX_SEGMENT_FIELD(DS),
896 VMX_SEGMENT_FIELD(ES),
897 VMX_SEGMENT_FIELD(FS),
898 VMX_SEGMENT_FIELD(GS),
899 VMX_SEGMENT_FIELD(SS),
900 VMX_SEGMENT_FIELD(TR),
901 VMX_SEGMENT_FIELD(LDTR),
902};
903
26bb0981
AK		 904static u64 host_efer;
905
6de4f3ad
AK		 906static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
907
4d56c8a7 908/*
8c06585d 909 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 910 * away by decrementing the array size.
911 */
6aa8b732 912static const u32 vmx_msr_index[] = {
05b3e0c2 913#ifdef CONFIG_X86_64
44ea2b17 914 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 915#endif
8c06585d 916 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 917};
6aa8b732 918
31299944 919static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 920{
921 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
922 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 923 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 924}
925
31299944 926static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 927{
928 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
929 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 930 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 931}
932
31299944 933static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 934{
935 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
936 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 937 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 938}
939
31299944 940static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 941{
942 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
943 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
944}
945
31299944 946static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 947{
948 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
949 INTR_INFO_VALID_MASK)) ==
950 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
951}
952
31299944 953static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 954{
04547156 955 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 956}
957
31299944 958static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 959{
04547156 960 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 961}
962
35754c98 963static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 964{
35754c98 965 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS		 966}
967
31299944 968static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 969{
04547156
SY		 970 return vmcs_config.cpu_based_exec_ctrl &
971 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 972}
973
774ead3a 974static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 975{
04547156
SY		 976 return vmcs_config.cpu_based_2nd_exec_ctrl &
977 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
978}
979
8d14695f
YZ		 980static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
981{
982 return vmcs_config.cpu_based_2nd_exec_ctrl &
983 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
984}
985
83d4c286
YZ		 986static inline bool cpu_has_vmx_apic_register_virt(void)
987{
988 return vmcs_config.cpu_based_2nd_exec_ctrl &
989 SECONDARY_EXEC_APIC_REGISTER_VIRT;
990}
991
c7c9c56c
YZ		 992static inline bool cpu_has_vmx_virtual_intr_delivery(void)
993{
994 return vmcs_config.cpu_based_2nd_exec_ctrl &
995 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
996}
997
01e439be
YZ		 998static inline bool cpu_has_vmx_posted_intr(void)
999{
d6a858d1
PB		 1000 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1001 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ		 1002}
1003
1004static inline bool cpu_has_vmx_apicv(void)
1005{
1006 return cpu_has_vmx_apic_register_virt() &&
1007 cpu_has_vmx_virtual_intr_delivery() &&
1008 cpu_has_vmx_posted_intr();
1009}
1010
04547156
SY		 1011static inline bool cpu_has_vmx_flexpriority(void)
1012{
1013 return cpu_has_vmx_tpr_shadow() &&
1014 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 1015}
1016
e799794e
MT		 1017static inline bool cpu_has_vmx_ept_execute_only(void)
1018{
31299944 1019 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 1020}
1021
e799794e
MT		 1022static inline bool cpu_has_vmx_ept_2m_page(void)
1023{
31299944 1024 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1025}
1026
878403b7
SY		 1027static inline bool cpu_has_vmx_ept_1g_page(void)
1028{
31299944 1029 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1030}
1031
4bc9b982
SY		 1032static inline bool cpu_has_vmx_ept_4levels(void)
1033{
1034 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1035}
1036
83c3a331
XH		 1037static inline bool cpu_has_vmx_ept_ad_bits(void)
1038{
1039 return vmx_capability.ept & VMX_EPT_AD_BIT;
1040}
1041
31299944 1042static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1043{
31299944 1044 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1045}
1046
31299944 1047static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1048{
31299944 1049 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1050}
1051
518c8aee
GJ		 1052static inline bool cpu_has_vmx_invvpid_single(void)
1053{
1054 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1055}
1056
b9d762fa
GJ		 1057static inline bool cpu_has_vmx_invvpid_global(void)
1058{
1059 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1060}
1061
31299944 1062static inline bool cpu_has_vmx_ept(void)
d56f546d 1063{
04547156
SY		 1064 return vmcs_config.cpu_based_2nd_exec_ctrl &
1065 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1066}
1067
31299944 1068static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1069{
1070 return vmcs_config.cpu_based_2nd_exec_ctrl &
1071 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1072}
1073
31299944 1074static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1075{
1076 return vmcs_config.cpu_based_2nd_exec_ctrl &
1077 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1078}
1079
35754c98 1080static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1081{
35754c98 1082 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 1083}
1084
31299944 1085static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1086{
04547156
SY		 1087 return vmcs_config.cpu_based_2nd_exec_ctrl &
1088 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1089}
1090
31299944 1091static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1092{
1093 return vmcs_config.cpu_based_2nd_exec_ctrl &
1094 SECONDARY_EXEC_RDTSCP;
1095}
1096
ad756a16
MJ		 1097static inline bool cpu_has_vmx_invpcid(void)
1098{
1099 return vmcs_config.cpu_based_2nd_exec_ctrl &
1100 SECONDARY_EXEC_ENABLE_INVPCID;
1101}
1102
31299944 1103static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1104{
1105 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1106}
1107
f5f48ee1
SY		 1108static inline bool cpu_has_vmx_wbinvd_exit(void)
1109{
1110 return vmcs_config.cpu_based_2nd_exec_ctrl &
1111 SECONDARY_EXEC_WBINVD_EXITING;
1112}
1113
abc4fc58
AG		 1114static inline bool cpu_has_vmx_shadow_vmcs(void)
1115{
1116 u64 vmx_msr;
1117 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1118 /* check if the cpu supports writing r/o exit information fields */
1119 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1120 return false;
1121
1122 return vmcs_config.cpu_based_2nd_exec_ctrl &
1123 SECONDARY_EXEC_SHADOW_VMCS;
1124}
1125
843e4330
KH		 1126static inline bool cpu_has_vmx_pml(void)
1127{
1128 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1129}
1130
04547156
SY		 1131static inline bool report_flexpriority(void)
1132{
1133 return flexpriority_enabled;
1134}
1135
fe3ef05c
NHE		 1136static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1137{
1138 return vmcs12->cpu_based_vm_exec_control & bit;
1139}
1140
1141static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1142{
1143 return (vmcs12->cpu_based_vm_exec_control &
1144 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1145 (vmcs12->secondary_vm_exec_control & bit);
1146}
1147
f5c4368f 1148static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1149{
1150 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1151}
1152
f4124500
JK		 1153static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1154{
1155 return vmcs12->pin_based_vm_exec_control &
1156 PIN_BASED_VMX_PREEMPTION_TIMER;
1157}
1158
155a97a3
NHE		 1159static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1160{
1161 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1162}
1163
81dc01f7
WL		 1164static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1165{
1166 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1167 vmx_xsaves_supported();
1168}
1169
f2b93280
WV		 1170static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1171{
1172 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1173}
1174
82f0dd4b
WV		 1175static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1176{
1177 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1178}
1179
608406e2
WV		 1180static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1181{
1182 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1183}
1184
705699a1
WV		 1185static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1186{
1187 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1188}
1189
644d711a
NHE		 1190static inline bool is_exception(u32 intr_info)
1191{
1192 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1193 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1194}
1195
533558bc
JK		 1196static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1197 u32 exit_intr_info,
1198 unsigned long exit_qualification);
7c177938
NHE		 1199static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1200 struct vmcs12 *vmcs12,
1201 u32 reason, unsigned long qualification);
1202
8b9cf98c 1203static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1204{
1205 int i;
1206
a2fa3e9f 1207 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1208 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1209 return i;
1210 return -1;
1211}
1212
2384d2b3
SY		 1213static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1214{
1215 struct {
1216 u64 vpid : 16;
1217 u64 rsvd : 48;
1218 u64 gva;
1219 } operand = { vpid, 0, gva };
1220
4ecac3fd 1221 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1222 /* CF==1 or ZF==1 --> rc = -1 */
1223 "; ja 1f ; ud2 ; 1:"
1224 : : "a"(&operand), "c"(ext) : "cc", "memory");
1225}
1226
1439442c
SY		 1227static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1228{
1229 struct {
1230 u64 eptp, gpa;
1231 } operand = {eptp, gpa};
1232
4ecac3fd 1233 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1234 /* CF==1 or ZF==1 --> rc = -1 */
1235 "; ja 1f ; ud2 ; 1:\n"
1236 : : "a" (&operand), "c" (ext) : "cc", "memory");
1237}
1238
26bb0981 1239static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1240{
1241 int i;
1242
8b9cf98c 1243 i = __find_msr_index(vmx, msr);
a75beee6 1244 if (i >= 0)
a2fa3e9f 1245 return &vmx->guest_msrs[i];
8b6d44c7 1246 return NULL;
7725f0ba
AK		 1247}
1248
6aa8b732
AK		 1249static void vmcs_clear(struct vmcs *vmcs)
1250{
1251 u64 phys_addr = __pa(vmcs);
1252 u8 error;
1253
4ecac3fd 1254 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1255 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1256 : "cc", "memory");
1257 if (error)
1258 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1259 vmcs, phys_addr);
1260}
1261
d462b819
NHE		 1262static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1263{
1264 vmcs_clear(loaded_vmcs->vmcs);
1265 loaded_vmcs->cpu = -1;
1266 loaded_vmcs->launched = 0;
1267}
1268
7725b894
DX		 1269static void vmcs_load(struct vmcs *vmcs)
1270{
1271 u64 phys_addr = __pa(vmcs);
1272 u8 error;
1273
1274 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1275 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1276 : "cc", "memory");
1277 if (error)
2844d849 1278 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1279 vmcs, phys_addr);
1280}
1281
2965faa5 1282#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 1283/*
1284 * This bitmap is used to indicate whether the vmclear
1285 * operation is enabled on all cpus. All disabled by
1286 * default.
1287 */
1288static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1289
1290static inline void crash_enable_local_vmclear(int cpu)
1291{
1292 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1293}
1294
1295static inline void crash_disable_local_vmclear(int cpu)
1296{
1297 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1298}
1299
1300static inline int crash_local_vmclear_enabled(int cpu)
1301{
1302 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1303}
1304
1305static void crash_vmclear_local_loaded_vmcss(void)
1306{
1307 int cpu = raw_smp_processor_id();
1308 struct loaded_vmcs *v;
1309
1310 if (!crash_local_vmclear_enabled(cpu))
1311 return;
1312
1313 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1314 loaded_vmcss_on_cpu_link)
1315 vmcs_clear(v->vmcs);
1316}
1317#else
1318static inline void crash_enable_local_vmclear(int cpu) { }
1319static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1320#endif /* CONFIG_KEXEC_CORE */
8f536b76 1321
d462b819 1322static void __loaded_vmcs_clear(void *arg)
6aa8b732 1323{
d462b819 1324 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1325 int cpu = raw_smp_processor_id();
6aa8b732 1326
d462b819
NHE		 1327 if (loaded_vmcs->cpu != cpu)
1328 return; /* vcpu migration can race with cpu offline */
1329 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1330 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1331 crash_disable_local_vmclear(cpu);
d462b819 1332 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1333
1334 /*
1335 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1336 * is before setting loaded_vmcs->vcpu to -1 which is done in
1337 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1338 * then adds the vmcs into percpu list before it is deleted.
1339 */
1340 smp_wmb();
1341
d462b819 1342 loaded_vmcs_init(loaded_vmcs);
8f536b76 1343 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1344}
1345
d462b819 1346static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1347{
e6c7d321
XG		 1348 int cpu = loaded_vmcs->cpu;
1349
1350 if (cpu != -1)
1351 smp_call_function_single(cpu,
1352 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1353}
1354
1760dd49 1355static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1356{
1357 if (vmx->vpid == 0)
1358 return;
1359
518c8aee
GJ		 1360 if (cpu_has_vmx_invvpid_single())
1361 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1362}
1363
b9d762fa
GJ		 1364static inline void vpid_sync_vcpu_global(void)
1365{
1366 if (cpu_has_vmx_invvpid_global())
1367 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1368}
1369
1370static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1371{
1372 if (cpu_has_vmx_invvpid_single())
1760dd49 1373 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1374 else
1375 vpid_sync_vcpu_global();
1376}
1377
1439442c
SY		 1378static inline void ept_sync_global(void)
1379{
1380 if (cpu_has_vmx_invept_global())
1381 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1382}
1383
1384static inline void ept_sync_context(u64 eptp)
1385{
089d034e 1386 if (enable_ept) {
1439442c
SY		 1387 if (cpu_has_vmx_invept_context())
1388 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1389 else
1390 ept_sync_global();
1391 }
1392}
1393
96304217 1394static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1395{
5e520e62 1396 unsigned long value;
6aa8b732 1397
5e520e62
AK		 1398 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1399 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1400 return value;
1401}
1402
96304217 1403static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1404{
1405 return vmcs_readl(field);
1406}
1407
96304217 1408static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1409{
1410 return vmcs_readl(field);
1411}
1412
96304217 1413static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1414{
05b3e0c2 1415#ifdef CONFIG_X86_64
6aa8b732
AK		 1416 return vmcs_readl(field);
1417#else
1418 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1419#endif
1420}
1421
e52de1b8
AK		 1422static noinline void vmwrite_error(unsigned long field, unsigned long value)
1423{
1424 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1425 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1426 dump_stack();
1427}
1428
6aa8b732
AK		 1429static void vmcs_writel(unsigned long field, unsigned long value)
1430{
1431 u8 error;
1432
4ecac3fd 1433 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1434 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1435 if (unlikely(error))
1436 vmwrite_error(field, value);
6aa8b732
AK		 1437}
1438
1439static void vmcs_write16(unsigned long field, u16 value)
1440{
1441 vmcs_writel(field, value);
1442}
1443
1444static void vmcs_write32(unsigned long field, u32 value)
1445{
1446 vmcs_writel(field, value);
1447}
1448
1449static void vmcs_write64(unsigned long field, u64 value)
1450{
6aa8b732 1451 vmcs_writel(field, value);
7682f2d0 1452#ifndef CONFIG_X86_64
6aa8b732
AK		 1453 asm volatile ("");
1454 vmcs_writel(field+1, value >> 32);
1455#endif
1456}
1457
2ab455cc
AL		 1458static void vmcs_clear_bits(unsigned long field, u32 mask)
1459{
1460 vmcs_writel(field, vmcs_readl(field) & ~mask);
1461}
1462
1463static void vmcs_set_bits(unsigned long field, u32 mask)
1464{
1465 vmcs_writel(field, vmcs_readl(field) | mask);
1466}
1467
2961e876
GN		 1468static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1469{
1470 vmcs_write32(VM_ENTRY_CONTROLS, val);
1471 vmx->vm_entry_controls_shadow = val;
1472}
1473
1474static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1475{
1476 if (vmx->vm_entry_controls_shadow != val)
1477 vm_entry_controls_init(vmx, val);
1478}
1479
1480static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1481{
1482 return vmx->vm_entry_controls_shadow;
1483}
1484
1485
1486static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1487{
1488 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1489}
1490
1491static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1492{
1493 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1494}
1495
1496static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1497{
1498 vmcs_write32(VM_EXIT_CONTROLS, val);
1499 vmx->vm_exit_controls_shadow = val;
1500}
1501
1502static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1503{
1504 if (vmx->vm_exit_controls_shadow != val)
1505 vm_exit_controls_init(vmx, val);
1506}
1507
1508static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1509{
1510 return vmx->vm_exit_controls_shadow;
1511}
1512
1513
1514static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1515{
1516 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1517}
1518
1519static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1520{
1521 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1522}
1523
2fb92db1
AK		 1524static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1525{
1526 vmx->segment_cache.bitmask = 0;
1527}
1528
1529static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1530 unsigned field)
1531{
1532 bool ret;
1533 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1534
1535 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1536 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1537 vmx->segment_cache.bitmask = 0;
1538 }
1539 ret = vmx->segment_cache.bitmask & mask;
1540 vmx->segment_cache.bitmask |= mask;
1541 return ret;
1542}
1543
1544static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1545{
1546 u16 *p = &vmx->segment_cache.seg[seg].selector;
1547
1548 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1549 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1550 return *p;
1551}
1552
1553static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1554{
1555 ulong *p = &vmx->segment_cache.seg[seg].base;
1556
1557 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1558 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1559 return *p;
1560}
1561
1562static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1563{
1564 u32 *p = &vmx->segment_cache.seg[seg].limit;
1565
1566 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1567 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1568 return *p;
1569}
1570
1571static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1572{
1573 u32 *p = &vmx->segment_cache.seg[seg].ar;
1574
1575 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1576 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1577 return *p;
1578}
1579
abd3f2d6
AK		 1580static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1581{
1582 u32 eb;
1583
fd7373cc
JK		 1584 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1585 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1586 if ((vcpu->guest_debug &
1587 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1588 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1589 eb |= 1u << BP_VECTOR;
7ffd92c5 1590 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1591 eb = ~0;
089d034e 1592 if (enable_ept)
1439442c 1593 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1594 if (vcpu->fpu_active)
1595 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1596
1597 /* When we are running a nested L2 guest and L1 specified for it a
1598 * certain exception bitmap, we must trap the same exceptions and pass
1599 * them to L1. When running L2, we will only handle the exceptions
1600 * specified above if L1 did not want them.
1601 */
1602 if (is_guest_mode(vcpu))
1603 eb |= get_vmcs12(vcpu)->exception_bitmap;
1604
abd3f2d6
AK		 1605 vmcs_write32(EXCEPTION_BITMAP, eb);
1606}
1607
2961e876
GN		 1608static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1609 unsigned long entry, unsigned long exit)
8bf00a52 1610{
2961e876
GN		 1611 vm_entry_controls_clearbit(vmx, entry);
1612 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1613}
1614
61d2ef2c
AK		 1615static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1616{
1617 unsigned i;
1618 struct msr_autoload *m = &vmx->msr_autoload;
1619
8bf00a52
GN		 1620 switch (msr) {
1621 case MSR_EFER:
1622 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1623 clear_atomic_switch_msr_special(vmx,
1624 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1625 VM_EXIT_LOAD_IA32_EFER);
1626 return;
1627 }
1628 break;
1629 case MSR_CORE_PERF_GLOBAL_CTRL:
1630 if (cpu_has_load_perf_global_ctrl) {
2961e876 1631 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1632 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1633 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1634 return;
1635 }
1636 break;
110312c8
AK		 1637 }
1638
61d2ef2c
AK		 1639 for (i = 0; i < m->nr; ++i)
1640 if (m->guest[i].index == msr)
1641 break;
1642
1643 if (i == m->nr)
1644 return;
1645 --m->nr;
1646 m->guest[i] = m->guest[m->nr];
1647 m->host[i] = m->host[m->nr];
1648 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1649 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1650}
1651
2961e876
GN		 1652static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1653 unsigned long entry, unsigned long exit,
1654 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1655 u64 guest_val, u64 host_val)
8bf00a52
GN		 1656{
1657 vmcs_write64(guest_val_vmcs, guest_val);
1658 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1659 vm_entry_controls_setbit(vmx, entry);
1660 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1661}
1662
61d2ef2c
AK		 1663static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1664 u64 guest_val, u64 host_val)
1665{
1666 unsigned i;
1667 struct msr_autoload *m = &vmx->msr_autoload;
1668
8bf00a52
GN		 1669 switch (msr) {
1670 case MSR_EFER:
1671 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1672 add_atomic_switch_msr_special(vmx,
1673 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1674 VM_EXIT_LOAD_IA32_EFER,
1675 GUEST_IA32_EFER,
1676 HOST_IA32_EFER,
1677 guest_val, host_val);
1678 return;
1679 }
1680 break;
1681 case MSR_CORE_PERF_GLOBAL_CTRL:
1682 if (cpu_has_load_perf_global_ctrl) {
2961e876 1683 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1684 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1685 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1686 GUEST_IA32_PERF_GLOBAL_CTRL,
1687 HOST_IA32_PERF_GLOBAL_CTRL,
1688 guest_val, host_val);
1689 return;
1690 }
1691 break;
110312c8
AK		 1692 }
1693
61d2ef2c
AK		 1694 for (i = 0; i < m->nr; ++i)
1695 if (m->guest[i].index == msr)
1696 break;
1697
e7fc6f93 1698 if (i == NR_AUTOLOAD_MSRS) {
60266204 1699 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1700 "Can't add msr %x\n", msr);
1701 return;
1702 } else if (i == m->nr) {
61d2ef2c
AK		 1703 ++m->nr;
1704 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1705 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1706 }
1707
1708 m->guest[i].index = msr;
1709 m->guest[i].value = guest_val;
1710 m->host[i].index = msr;
1711 m->host[i].value = host_val;
1712}
1713
33ed6329
AK		 1714static void reload_tss(void)
1715{
33ed6329
AK		 1716 /*
1717 * VT restores TR but not its size. Useless.
1718 */
89cbc767 1719 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1720 struct desc_struct *descs;
33ed6329 1721
d359192f 1722 descs = (void *)gdt->address;
33ed6329
AK		 1723 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1724 load_TR_desc();
33ed6329
AK		 1725}
1726
92c0d900 1727static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1728{
3a34a881 1729 u64 guest_efer;
51c6cf66
AK		 1730 u64 ignore_bits;
1731
f6801dff 1732 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1733
51c6cf66 1734 /*
0fa06071 1735 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1736 * outside long mode
1737 */
1738 ignore_bits = EFER_NX | EFER_SCE;
1739#ifdef CONFIG_X86_64
1740 ignore_bits |= EFER_LMA | EFER_LME;
1741 /* SCE is meaningful only in long mode on Intel */
1742 if (guest_efer & EFER_LMA)
1743 ignore_bits &= ~(u64)EFER_SCE;
1744#endif
51c6cf66
AK		 1745 guest_efer &= ~ignore_bits;
1746 guest_efer |= host_efer & ignore_bits;
26bb0981 1747 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1748 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1749
1750 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1751
1752 /*
1753 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1754 * On CPUs that support "load IA32_EFER", always switch EFER
1755 * atomically, since it's faster than switching it manually.
1756 */
1757 if (cpu_has_load_ia32_efer ||
1758 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1759 guest_efer = vmx->vcpu.arch.efer;
1760 if (!(guest_efer & EFER_LMA))
1761 guest_efer &= ~EFER_LME;
54b98bff
AL		 1762 if (guest_efer != host_efer)
1763 add_atomic_switch_msr(vmx, MSR_EFER,
1764 guest_efer, host_efer);
84ad33ef
AK		 1765 return false;
1766 }
1767
26bb0981 1768 return true;
51c6cf66
AK		 1769}
1770
2d49ec72
GN		 1771static unsigned long segment_base(u16 selector)
1772{
89cbc767 1773 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1774 struct desc_struct *d;
1775 unsigned long table_base;
1776 unsigned long v;
1777
1778 if (!(selector & ~3))
1779 return 0;
1780
d359192f 1781 table_base = gdt->address;
2d49ec72
GN		 1782
1783 if (selector & 4) { /* from ldt */
1784 u16 ldt_selector = kvm_read_ldt();
1785
1786 if (!(ldt_selector & ~3))
1787 return 0;
1788
1789 table_base = segment_base(ldt_selector);
1790 }
1791 d = (struct desc_struct *)(table_base + (selector & ~7));
1792 v = get_desc_base(d);
1793#ifdef CONFIG_X86_64
1794 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1795 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1796#endif
1797 return v;
1798}
1799
1800static inline unsigned long kvm_read_tr_base(void)
1801{
1802 u16 tr;
1803 asm("str %0" : "=g"(tr));
1804 return segment_base(tr);
1805}
1806
04d2cc77 1807static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1808{
04d2cc77 1809 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1810 int i;
04d2cc77 1811
a2fa3e9f 1812 if (vmx->host_state.loaded)
33ed6329
AK		 1813 return;
1814
a2fa3e9f 1815 vmx->host_state.loaded = 1;
33ed6329
AK		 1816 /*
1817 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1818 * allow segment selectors with cpl > 0 or ti == 1.
1819 */
d6e88aec 1820 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1821 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1822 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1823 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1824 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1825 vmx->host_state.fs_reload_needed = 0;
1826 } else {
33ed6329 1827 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1828 vmx->host_state.fs_reload_needed = 1;
33ed6329 1829 }
9581d442 1830 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1831 if (!(vmx->host_state.gs_sel & 7))
1832 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1833 else {
1834 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1835 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1836 }
1837
b2da15ac
AK		 1838#ifdef CONFIG_X86_64
1839 savesegment(ds, vmx->host_state.ds_sel);
1840 savesegment(es, vmx->host_state.es_sel);
1841#endif
1842
33ed6329
AK		 1843#ifdef CONFIG_X86_64
1844 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1845 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1846#else
a2fa3e9f
GH		 1847 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1848 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1849#endif
707c0874
AK		 1850
1851#ifdef CONFIG_X86_64
c8770e7b
AK		 1852 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1853 if (is_long_mode(&vmx->vcpu))
44ea2b17 1854 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1855#endif
da8999d3
LJ		 1856 if (boot_cpu_has(X86_FEATURE_MPX))
1857 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1858 for (i = 0; i < vmx->save_nmsrs; ++i)
1859 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1860 vmx->guest_msrs[i].data,
1861 vmx->guest_msrs[i].mask);
33ed6329
AK		 1862}
1863
a9b21b62 1864static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1865{
a2fa3e9f 1866 if (!vmx->host_state.loaded)
33ed6329
AK		 1867 return;
1868
e1beb1d3 1869 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1870 vmx->host_state.loaded = 0;
c8770e7b
AK		 1871#ifdef CONFIG_X86_64
1872 if (is_long_mode(&vmx->vcpu))
1873 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1874#endif
152d3f2f 1875 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1876 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1877#ifdef CONFIG_X86_64
9581d442 1878 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1879#else
1880 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1881#endif
33ed6329 1882 }
0a77fe4c
AK		 1883 if (vmx->host_state.fs_reload_needed)
1884 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1885#ifdef CONFIG_X86_64
1886 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1887 loadsegment(ds, vmx->host_state.ds_sel);
1888 loadsegment(es, vmx->host_state.es_sel);
1889 }
b2da15ac 1890#endif
152d3f2f 1891 reload_tss();
44ea2b17 1892#ifdef CONFIG_X86_64
c8770e7b 1893 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1894#endif
da8999d3
LJ		 1895 if (vmx->host_state.msr_host_bndcfgs)
1896 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1897 /*
1898 * If the FPU is not active (through the host task or
1899 * the guest vcpu), then restore the cr0.TS bit.
1900 */
3c6dffa9 1901 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
b1a74bf8 1902 stts();
89cbc767 1903 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1904}
1905
a9b21b62
AK		 1906static void vmx_load_host_state(struct vcpu_vmx *vmx)
1907{
1908 preempt_disable();
1909 __vmx_load_host_state(vmx);
1910 preempt_enable();
1911}
1912
6aa8b732
AK		 1913/*
1914 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1915 * vcpu mutex is already taken.
1916 */
15ad7146 1917static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1918{
a2fa3e9f 1919 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1920 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1921
4610c9cc
DX		 1922 if (!vmm_exclusive)
1923 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1924 else if (vmx->loaded_vmcs->cpu != cpu)
1925 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1926
d462b819
NHE		 1927 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1928 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1929 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1930 }
1931
d462b819 1932 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1933 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1934 unsigned long sysenter_esp;
1935
a8eeb04a 1936 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1937 local_irq_disable();
8f536b76 1938 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1939
1940 /*
1941 * Read loaded_vmcs->cpu should be before fetching
1942 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1943 * See the comments in __loaded_vmcs_clear().
1944 */
1945 smp_rmb();
1946
d462b819
NHE		 1947 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1948 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1949 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1950 local_irq_enable();
1951
6aa8b732
AK		 1952 /*
1953 * Linux uses per-cpu TSS and GDT, so set these when switching
1954 * processors.
1955 */
d6e88aec 1956 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1957 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1958
1959 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1960 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1961 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1962 }
6aa8b732
AK		 1963}
1964
1965static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1966{
a9b21b62 1967 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1968 if (!vmm_exclusive) {
d462b819
NHE		 1969 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1970 vcpu->cpu = -1;
4610c9cc
DX		 1971 kvm_cpu_vmxoff();
1972 }
6aa8b732
AK		 1973}
1974
5fd86fcf
AK		 1975static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1976{
81231c69
AK		 1977 ulong cr0;
1978
5fd86fcf
AK		 1979 if (vcpu->fpu_active)
1980 return;
1981 vcpu->fpu_active = 1;
81231c69
AK		 1982 cr0 = vmcs_readl(GUEST_CR0);
1983 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1984 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1985 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1986 update_exception_bitmap(vcpu);
edcafe3c 1987 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1988 if (is_guest_mode(vcpu))
1989 vcpu->arch.cr0_guest_owned_bits &=
1990 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1991 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1992}
1993
edcafe3c
AK		 1994static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1995
fe3ef05c
NHE		 1996/*
1997 * Return the cr0 value that a nested guest would read. This is a combination
1998 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1999 * its hypervisor (cr0_read_shadow).
2000 */
2001static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2002{
2003 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2004 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2005}
2006static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2007{
2008 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2009 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2010}
2011
5fd86fcf
AK		 2012static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2013{
36cf24e0
NHE		 2014 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2015 * set this *before* calling this function.
2016 */
edcafe3c 2017 vmx_decache_cr0_guest_bits(vcpu);
81231c69 2018 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 2019 update_exception_bitmap(vcpu);
edcafe3c
AK		 2020 vcpu->arch.cr0_guest_owned_bits = 0;
2021 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 2022 if (is_guest_mode(vcpu)) {
2023 /*
2024 * L1's specified read shadow might not contain the TS bit,
2025 * so now that we turned on shadowing of this bit, we need to
2026 * set this bit of the shadow. Like in nested_vmx_run we need
2027 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2028 * up-to-date here because we just decached cr0.TS (and we'll
2029 * only update vmcs12->guest_cr0 on nested exit).
2030 */
2031 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2032 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2033 (vcpu->arch.cr0 & X86_CR0_TS);
2034 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2035 } else
2036 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2037}
2038
6aa8b732
AK		 2039static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2040{
78ac8b47 2041 unsigned long rflags, save_rflags;
345dcaa8 2042
6de12732
AK		 2043 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2044 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2045 rflags = vmcs_readl(GUEST_RFLAGS);
2046 if (to_vmx(vcpu)->rmode.vm86_active) {
2047 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2048 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2049 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2050 }
2051 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2052 }
6de12732 2053 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2054}
2055
2056static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2057{
6de12732
AK		 2058 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2059 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2060 if (to_vmx(vcpu)->rmode.vm86_active) {
2061 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2062 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2063 }
6aa8b732
AK		 2064 vmcs_writel(GUEST_RFLAGS, rflags);
2065}
2066
37ccdcbe 2067static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2068{
2069 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2070 int ret = 0;
2071
2072 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2073 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2074 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2075 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2076
37ccdcbe 2077 return ret;
2809f5d2
GC		 2078}
2079
2080static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2081{
2082 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2083 u32 interruptibility = interruptibility_old;
2084
2085 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2086
48005f64 2087 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2088 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2089 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2090 interruptibility |= GUEST_INTR_STATE_STI;
2091
2092 if ((interruptibility != interruptibility_old))
2093 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2094}
2095
6aa8b732
AK		 2096static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2097{
2098 unsigned long rip;
6aa8b732 2099
5fdbf976 2100 rip = kvm_rip_read(vcpu);
6aa8b732 2101 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2102 kvm_rip_write(vcpu, rip);
6aa8b732 2103
2809f5d2
GC		 2104 /* skipping an emulated instruction also counts */
2105 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2106}
2107
0b6ac343
NHE		 2108/*
2109 * KVM wants to inject page-faults which it got to the guest. This function
2110 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2111 */
e011c663 2112static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2113{
2114 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2115
e011c663 2116 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2117 return 0;
2118
533558bc
JK		 2119 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2120 vmcs_read32(VM_EXIT_INTR_INFO),
2121 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2122 return 1;
2123}
2124
298101da 2125static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2126 bool has_error_code, u32 error_code,
2127 bool reinject)
298101da 2128{
77ab6db0 2129 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2130 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2131
e011c663
GN		 2132 if (!reinject && is_guest_mode(vcpu) &&
2133 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2134 return;
2135
8ab2d2e2 2136 if (has_error_code) {
77ab6db0 2137 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2138 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2139 }
77ab6db0 2140
7ffd92c5 2141 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2142 int inc_eip = 0;
2143 if (kvm_exception_is_soft(nr))
2144 inc_eip = vcpu->arch.event_exit_inst_len;
2145 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2146 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2147 return;
2148 }
2149
66fd3f7f
GN		 2150 if (kvm_exception_is_soft(nr)) {
2151 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2152 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2153 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2154 } else
2155 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2156
2157 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2158}
2159
4e47c7a6
SY		 2160static bool vmx_rdtscp_supported(void)
2161{
2162 return cpu_has_vmx_rdtscp();
2163}
2164
ad756a16
MJ		 2165static bool vmx_invpcid_supported(void)
2166{
2167 return cpu_has_vmx_invpcid() && enable_ept;
2168}
2169
a75beee6
ED		 2170/*
2171 * Swap MSR entry in host/guest MSR entry array.
2172 */
8b9cf98c 2173static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2174{
26bb0981 2175 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2176
2177 tmp = vmx->guest_msrs[to];
2178 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2179 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2180}
2181
8d14695f
YZ		 2182static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2183{
2184 unsigned long *msr_bitmap;
2185
670125bd
WV		 2186 if (is_guest_mode(vcpu))
2187 msr_bitmap = vmx_msr_bitmap_nested;
8a9781f7 2188 else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
8d14695f
YZ		 2189 if (is_long_mode(vcpu))
2190 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2191 else
2192 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2193 } else {
2194 if (is_long_mode(vcpu))
2195 msr_bitmap = vmx_msr_bitmap_longmode;
2196 else
2197 msr_bitmap = vmx_msr_bitmap_legacy;
2198 }
2199
2200 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2201}
2202
e38aea3e
AK		 2203/*
2204 * Set up the vmcs to automatically save and restore system
2205 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2206 * mode, as fiddling with msrs is very expensive.
2207 */
8b9cf98c 2208static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2209{
26bb0981 2210 int save_nmsrs, index;
e38aea3e 2211
a75beee6
ED		 2212 save_nmsrs = 0;
2213#ifdef CONFIG_X86_64
8b9cf98c 2214 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2215 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2216 if (index >= 0)
8b9cf98c
RR		 2217 move_msr_up(vmx, index, save_nmsrs++);
2218 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2219 if (index >= 0)
8b9cf98c
RR		 2220 move_msr_up(vmx, index, save_nmsrs++);
2221 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2222 if (index >= 0)
8b9cf98c 2223 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6 2224 index = __find_msr_index(vmx, MSR_TSC_AUX);
1cea0ce6 2225 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
4e47c7a6 2226 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2227 /*
8c06585d 2228 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2229 * if efer.sce is enabled.
2230 */
8c06585d 2231 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2232 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2233 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2234 }
2235#endif
92c0d900
AK		 2236 index = __find_msr_index(vmx, MSR_EFER);
2237 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2238 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2239
26bb0981 2240 vmx->save_nmsrs = save_nmsrs;
5897297b 2241
8d14695f
YZ		 2242 if (cpu_has_vmx_msr_bitmap())
2243 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2244}
2245
6aa8b732
AK		 2246/*
2247 * reads and returns guest's timestamp counter "register"
2248 * guest_tsc = host_tsc + tsc_offset -- 21.3
2249 */
2250static u64 guest_read_tsc(void)
2251{
2252 u64 host_tsc, tsc_offset;
2253
4ea1636b 2254 host_tsc = rdtsc();
6aa8b732
AK		 2255 tsc_offset = vmcs_read64(TSC_OFFSET);
2256 return host_tsc + tsc_offset;
2257}
2258
d5c1785d
NHE		 2259/*
2260 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2261 * counter, even if a nested guest (L2) is currently running.
2262 */
48d89b92 2263static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2264{
886b470c 2265 u64 tsc_offset;
d5c1785d 2266
d5c1785d
NHE		 2267 tsc_offset = is_guest_mode(vcpu) ?
2268 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2269 vmcs_read64(TSC_OFFSET);
2270 return host_tsc + tsc_offset;
2271}
2272
4051b188 2273/*
cc578287
ZA		 2274 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2275 * software catchup for faster rates on slower CPUs.
4051b188 2276 */
cc578287 2277static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2278{
cc578287
ZA		 2279 if (!scale)
2280 return;
2281
2282 if (user_tsc_khz > tsc_khz) {
2283 vcpu->arch.tsc_catchup = 1;
2284 vcpu->arch.tsc_always_catchup = 1;
2285 } else
2286 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2287}
2288
ba904635
WA		 2289static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2290{
2291 return vmcs_read64(TSC_OFFSET);
2292}
2293
6aa8b732 2294/*
99e3e30a 2295 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2296 */
99e3e30a 2297static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2298{
27fc51b2 2299 if (is_guest_mode(vcpu)) {
7991825b 2300 /*
27fc51b2
NHE		 2301 * We're here if L1 chose not to trap WRMSR to TSC. According
2302 * to the spec, this should set L1's TSC; The offset that L1
2303 * set for L2 remains unchanged, and still needs to be added
2304 * to the newly set TSC to get L2's TSC.
7991825b 2305 */
27fc51b2
NHE		 2306 struct vmcs12 *vmcs12;
2307 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2308 /* recalculate vmcs02.TSC_OFFSET: */
2309 vmcs12 = get_vmcs12(vcpu);
2310 vmcs_write64(TSC_OFFSET, offset +
2311 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2312 vmcs12->tsc_offset : 0));
2313 } else {
489223ed
YY		 2314 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2315 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2316 vmcs_write64(TSC_OFFSET, offset);
2317 }
6aa8b732
AK		 2318}
2319
f1e2b260 2320static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2321{
2322 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2323
e48672fa 2324 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2325 if (is_guest_mode(vcpu)) {
2326 /* Even when running L2, the adjustment needs to apply to L1 */
2327 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2328 } else
2329 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2330 offset + adjustment);
e48672fa
ZA		 2331}
2332
857e4099
JR		 2333static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2334{
4ea1636b 2335 return target_tsc - rdtsc();
857e4099
JR		 2336}
2337
801d3424
NHE		 2338static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2339{
2340 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2341 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2342}
2343
2344/*
2345 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2346 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2347 * all guests if the "nested" module option is off, and can also be disabled
2348 * for a single guest by disabling its VMX cpuid bit.
2349 */
2350static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2351{
2352 return nested && guest_cpuid_has_vmx(vcpu);
2353}
2354
b87a51ae
NHE		 2355/*
2356 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2357 * returned for the various VMX controls MSRs when nested VMX is enabled.
2358 * The same values should also be used to verify that vmcs12 control fields are
2359 * valid during nested entry from L1 to L2.
2360 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2361 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2362 * bit in the high half is on if the corresponding bit in the control field
2363 * may be on. See also vmx_control_verify().
b87a51ae 2364 */
b9c237bb 2365static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2366{
2367 /*
2368 * Note that as a general rule, the high half of the MSRs (bits in
2369 * the control fields which may be 1) should be initialized by the
2370 * intersection of the underlying hardware's MSR (i.e., features which
2371 * can be supported) and the list of features we want to expose -
2372 * because they are known to be properly supported in our code.
2373 * Also, usually, the low half of the MSRs (bits which must be 1) can
2374 * be set to 0, meaning that L1 may turn off any of these bits. The
2375 * reason is that if one of these bits is necessary, it will appear
2376 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2377 * fields of vmcs01 and vmcs02, will turn these bits off - and
2378 * nested_vmx_exit_handled() will not pass related exits to L1.
2379 * These rules have exceptions below.
2380 */
2381
2382 /* pin-based controls */
eabeaacc 2383 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2384 vmx->nested.nested_vmx_pinbased_ctls_low,
2385 vmx->nested.nested_vmx_pinbased_ctls_high);
2386 vmx->nested.nested_vmx_pinbased_ctls_low |=
2387 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2388 vmx->nested.nested_vmx_pinbased_ctls_high &=
2389 PIN_BASED_EXT_INTR_MASK |
2390 PIN_BASED_NMI_EXITING |
2391 PIN_BASED_VIRTUAL_NMIS;
2392 vmx->nested.nested_vmx_pinbased_ctls_high |=
2393 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2394 PIN_BASED_VMX_PREEMPTION_TIMER;
35754c98 2395 if (vmx_cpu_uses_apicv(&vmx->vcpu))
705699a1
WV		 2396 vmx->nested.nested_vmx_pinbased_ctls_high |=
2397 PIN_BASED_POSTED_INTR;
b87a51ae 2398
3dbcd8da 2399 /* exit controls */
c0dfee58 2400 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2401 vmx->nested.nested_vmx_exit_ctls_low,
2402 vmx->nested.nested_vmx_exit_ctls_high);
2403 vmx->nested.nested_vmx_exit_ctls_low =
2404 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2405
b9c237bb 2406 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2407#ifdef CONFIG_X86_64
c0dfee58 2408 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2409#endif
f4124500 2410 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2411 vmx->nested.nested_vmx_exit_ctls_high |=
2412 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2413 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2414 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2415
36be0b9d 2416 if (vmx_mpx_supported())
b9c237bb 2417 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2418
2996fca0 2419 /* We support free control of debug control saving. */
b9c237bb
WV		 2420 vmx->nested.nested_vmx_true_exit_ctls_low =
2421 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2422 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2423
b87a51ae
NHE		 2424 /* entry controls */
2425 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2426 vmx->nested.nested_vmx_entry_ctls_low,
2427 vmx->nested.nested_vmx_entry_ctls_high);
2428 vmx->nested.nested_vmx_entry_ctls_low =
2429 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2430 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2431#ifdef CONFIG_X86_64
2432 VM_ENTRY_IA32E_MODE |
2433#endif
2434 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2435 vmx->nested.nested_vmx_entry_ctls_high |=
2436 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2437 if (vmx_mpx_supported())
b9c237bb 2438 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2439
2996fca0 2440 /* We support free control of debug control loading. */
b9c237bb
WV		 2441 vmx->nested.nested_vmx_true_entry_ctls_low =
2442 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2443 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2444
b87a51ae
NHE		 2445 /* cpu-based controls */
2446 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2447 vmx->nested.nested_vmx_procbased_ctls_low,
2448 vmx->nested.nested_vmx_procbased_ctls_high);
2449 vmx->nested.nested_vmx_procbased_ctls_low =
2450 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2451 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2452 CPU_BASED_VIRTUAL_INTR_PENDING |
2453 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2454 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2455 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2456 CPU_BASED_CR3_STORE_EXITING |
2457#ifdef CONFIG_X86_64
2458 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2459#endif
2460 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD		 2461 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2462 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2463 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2464 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE		 2465 /*
2466 * We can allow some features even when not supported by the
2467 * hardware. For example, L1 can specify an MSR bitmap - and we
2468 * can use it to avoid exits to L1 - even when L0 runs L2
2469 * without MSR bitmaps.
2470 */
b9c237bb
WV		 2471 vmx->nested.nested_vmx_procbased_ctls_high |=
2472 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2473 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2474
3dcdf3ec 2475 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2476 vmx->nested.nested_vmx_true_procbased_ctls_low =
2477 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2478 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2479
b87a51ae
NHE		 2480 /* secondary cpu-based controls */
2481 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2482 vmx->nested.nested_vmx_secondary_ctls_low,
2483 vmx->nested.nested_vmx_secondary_ctls_high);
2484 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2485 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2486 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2487 SECONDARY_EXEC_RDTSCP |
f2b93280 2488 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2489 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2490 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7 2491 SECONDARY_EXEC_WBINVD_EXITING |
8b3e34e4
XG		 2492 SECONDARY_EXEC_XSAVES |
2493 SECONDARY_EXEC_PCOMMIT;
c18911a2 2494
afa61f75
NHE		 2495 if (enable_ept) {
2496 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2497 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2498 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2499 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2500 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2501 VMX_EPT_INVEPT_BIT;
b9c237bb 2502 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2503 /*
4b855078
BD		 2504 * For nested guests, we don't do anything specific
2505 * for single context invalidation. Hence, only advertise
2506 * support for global context invalidation.
afa61f75 2507 */
b9c237bb 2508 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2509 } else
b9c237bb 2510 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2511
0790ec17
RK		 2512 if (enable_unrestricted_guest)
2513 vmx->nested.nested_vmx_secondary_ctls_high |=
2514 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2515
c18911a2 2516 /* miscellaneous data */
b9c237bb
WV		 2517 rdmsr(MSR_IA32_VMX_MISC,
2518 vmx->nested.nested_vmx_misc_low,
2519 vmx->nested.nested_vmx_misc_high);
2520 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2521 vmx->nested.nested_vmx_misc_low |=
2522 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2523 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2524 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2525}
2526
2527static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2528{
2529 /*
2530 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2531 */
2532 return ((control & high) | low) == control;
2533}
2534
2535static inline u64 vmx_control_msr(u32 low, u32 high)
2536{
2537 return low | ((u64)high << 32);
2538}
2539
cae50139 2540/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2541static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2542{
b9c237bb
WV		 2543 struct vcpu_vmx *vmx = to_vmx(vcpu);
2544
b87a51ae 2545 switch (msr_index) {
b87a51ae
NHE		 2546 case MSR_IA32_VMX_BASIC:
2547 /*
2548 * This MSR reports some information about VMX support. We
2549 * should return information about the VMX we emulate for the
2550 * guest, and the VMCS structure we give it - not about the
2551 * VMX support of the underlying hardware.
2552 */
3dbcd8da 2553 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2554 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2555 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2556 break;
2557 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2558 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2559 *pdata = vmx_control_msr(
2560 vmx->nested.nested_vmx_pinbased_ctls_low,
2561 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2562 break;
2563 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2564 *pdata = vmx_control_msr(
2565 vmx->nested.nested_vmx_true_procbased_ctls_low,
2566 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2567 break;
b87a51ae 2568 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2569 *pdata = vmx_control_msr(
2570 vmx->nested.nested_vmx_procbased_ctls_low,
2571 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2572 break;
2573 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2574 *pdata = vmx_control_msr(
2575 vmx->nested.nested_vmx_true_exit_ctls_low,
2576 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2577 break;
b87a51ae 2578 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2579 *pdata = vmx_control_msr(
2580 vmx->nested.nested_vmx_exit_ctls_low,
2581 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2582 break;
2583 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2584 *pdata = vmx_control_msr(
2585 vmx->nested.nested_vmx_true_entry_ctls_low,
2586 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2587 break;
b87a51ae 2588 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2589 *pdata = vmx_control_msr(
2590 vmx->nested.nested_vmx_entry_ctls_low,
2591 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2592 break;
2593 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2594 *pdata = vmx_control_msr(
2595 vmx->nested.nested_vmx_misc_low,
2596 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2597 break;
2598 /*
2599 * These MSRs specify bits which the guest must keep fixed (on or off)
2600 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2601 * We picked the standard core2 setting.
2602 */
2603#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2604#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2605 case MSR_IA32_VMX_CR0_FIXED0:
2606 *pdata = VMXON_CR0_ALWAYSON;
2607 break;
2608 case MSR_IA32_VMX_CR0_FIXED1:
2609 *pdata = -1ULL;
2610 break;
2611 case MSR_IA32_VMX_CR4_FIXED0:
2612 *pdata = VMXON_CR4_ALWAYSON;
2613 break;
2614 case MSR_IA32_VMX_CR4_FIXED1:
2615 *pdata = -1ULL;
2616 break;
2617 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2618 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2619 break;
2620 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2621 *pdata = vmx_control_msr(
2622 vmx->nested.nested_vmx_secondary_ctls_low,
2623 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2624 break;
2625 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2626 /* Currently, no nested vpid support */
b9c237bb 2627 *pdata = vmx->nested.nested_vmx_ept_caps;
b87a51ae
NHE		 2628 break;
2629 default:
b87a51ae 2630 return 1;
b3897a49
NHE		 2631 }
2632
b87a51ae
NHE		 2633 return 0;
2634}
2635
6aa8b732
AK		 2636/*
2637 * Reads an msr value (of 'msr_index') into 'pdata'.
2638 * Returns 0 on success, non-0 otherwise.
2639 * Assumes vcpu_load() was already called.
2640 */
609e36d3 2641static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2642{
26bb0981 2643 struct shared_msr_entry *msr;
6aa8b732 2644
609e36d3 2645 switch (msr_info->index) {
05b3e0c2 2646#ifdef CONFIG_X86_64
6aa8b732 2647 case MSR_FS_BASE:
609e36d3 2648 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK		 2649 break;
2650 case MSR_GS_BASE:
609e36d3 2651 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 2652 break;
44ea2b17
AK		 2653 case MSR_KERNEL_GS_BASE:
2654 vmx_load_host_state(to_vmx(vcpu));
609e36d3 2655 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 2656 break;
26bb0981 2657#endif
6aa8b732 2658 case MSR_EFER:
609e36d3 2659 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 2660 case MSR_IA32_TSC:
609e36d3 2661 msr_info->data = guest_read_tsc();
6aa8b732
AK		 2662 break;
2663 case MSR_IA32_SYSENTER_CS:
609e36d3 2664 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 2665 break;
2666 case MSR_IA32_SYSENTER_EIP:
609e36d3 2667 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2668 break;
2669 case MSR_IA32_SYSENTER_ESP:
609e36d3 2670 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2671 break;
0dd376e7 2672 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2673 if (!vmx_mpx_supported())
2674 return 1;
609e36d3 2675 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 2676 break;
cae50139
JK		 2677 case MSR_IA32_FEATURE_CONTROL:
2678 if (!nested_vmx_allowed(vcpu))
2679 return 1;
609e36d3 2680 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
cae50139
JK		 2681 break;
2682 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2683 if (!nested_vmx_allowed(vcpu))
2684 return 1;
609e36d3 2685 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL		 2686 case MSR_IA32_XSS:
2687 if (!vmx_xsaves_supported())
2688 return 1;
609e36d3 2689 msr_info->data = vcpu->arch.ia32_xss;
20300099 2690 break;
4e47c7a6 2691 case MSR_TSC_AUX:
1cea0ce6 2692 if (!guest_cpuid_has_rdtscp(vcpu))
4e47c7a6
SY		 2693 return 1;
2694 /* Otherwise falls through */
6aa8b732 2695 default:
609e36d3 2696 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 2697 if (msr) {
609e36d3 2698 msr_info->data = msr->data;
3bab1f5d 2699 break;
6aa8b732 2700 }
609e36d3 2701 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2702 }
2703
6aa8b732
AK		 2704 return 0;
2705}
2706
cae50139
JK		 2707static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2708
6aa8b732
AK		 2709/*
2710 * Writes msr value into into the appropriate "register".
2711 * Returns 0 on success, non-0 otherwise.
2712 * Assumes vcpu_load() was already called.
2713 */
8fe8ab46 2714static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2715{
a2fa3e9f 2716 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2717 struct shared_msr_entry *msr;
2cc51560 2718 int ret = 0;
8fe8ab46
WA		 2719 u32 msr_index = msr_info->index;
2720 u64 data = msr_info->data;
2cc51560 2721
6aa8b732 2722 switch (msr_index) {
3bab1f5d 2723 case MSR_EFER:
8fe8ab46 2724 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2725 break;
16175a79 2726#ifdef CONFIG_X86_64
6aa8b732 2727 case MSR_FS_BASE:
2fb92db1 2728 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2729 vmcs_writel(GUEST_FS_BASE, data);
2730 break;
2731 case MSR_GS_BASE:
2fb92db1 2732 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2733 vmcs_writel(GUEST_GS_BASE, data);
2734 break;
44ea2b17
AK		 2735 case MSR_KERNEL_GS_BASE:
2736 vmx_load_host_state(vmx);
2737 vmx->msr_guest_kernel_gs_base = data;
2738 break;
6aa8b732
AK		 2739#endif
2740 case MSR_IA32_SYSENTER_CS:
2741 vmcs_write32(GUEST_SYSENTER_CS, data);
2742 break;
2743 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2744 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2745 break;
2746 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2747 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2748 break;
0dd376e7 2749 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2750 if (!vmx_mpx_supported())
2751 return 1;
0dd376e7
LJ		 2752 vmcs_write64(GUEST_BNDCFGS, data);
2753 break;
af24a4e4 2754 case MSR_IA32_TSC:
8fe8ab46 2755 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2756 break;
468d472f
SY		 2757 case MSR_IA32_CR_PAT:
2758 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2759 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2760 return 1;
468d472f
SY		 2761 vmcs_write64(GUEST_IA32_PAT, data);
2762 vcpu->arch.pat = data;
2763 break;
2764 }
8fe8ab46 2765 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2766 break;
ba904635
WA		 2767 case MSR_IA32_TSC_ADJUST:
2768 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2769 break;
cae50139
JK		 2770 case MSR_IA32_FEATURE_CONTROL:
2771 if (!nested_vmx_allowed(vcpu) ||
2772 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2773 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2774 return 1;
2775 vmx->nested.msr_ia32_feature_control = data;
2776 if (msr_info->host_initiated && data == 0)
2777 vmx_leave_nested(vcpu);
2778 break;
2779 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2780 return 1; /* they are read-only */
20300099
WL		 2781 case MSR_IA32_XSS:
2782 if (!vmx_xsaves_supported())
2783 return 1;
2784 /*
2785 * The only supported bit as of Skylake is bit 8, but
2786 * it is not supported on KVM.
2787 */
2788 if (data != 0)
2789 return 1;
2790 vcpu->arch.ia32_xss = data;
2791 if (vcpu->arch.ia32_xss != host_xss)
2792 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2793 vcpu->arch.ia32_xss, host_xss);
2794 else
2795 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2796 break;
4e47c7a6 2797 case MSR_TSC_AUX:
1cea0ce6 2798 if (!guest_cpuid_has_rdtscp(vcpu))
4e47c7a6
SY		 2799 return 1;
2800 /* Check reserved bit, higher 32 bits should be zero */
2801 if ((data >> 32) != 0)
2802 return 1;
2803 /* Otherwise falls through */
6aa8b732 2804 default:
8b9cf98c 2805 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2806 if (msr) {
8b3c3104 2807 u64 old_msr_data = msr->data;
3bab1f5d 2808 msr->data = data;
2225fd56
AK		 2809 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2810 preempt_disable();
8b3c3104
AH		 2811 ret = kvm_set_shared_msr(msr->index, msr->data,
2812 msr->mask);
2225fd56 2813 preempt_enable();
8b3c3104
AH		 2814 if (ret)
2815 msr->data = old_msr_data;
2225fd56 2816 }
3bab1f5d 2817 break;
6aa8b732 2818 }
8fe8ab46 2819 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2820 }
2821
2cc51560 2822 return ret;
6aa8b732
AK		 2823}
2824
5fdbf976 2825static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2826{
5fdbf976
MT		 2827 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2828 switch (reg) {
2829 case VCPU_REGS_RSP:
2830 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2831 break;
2832 case VCPU_REGS_RIP:
2833 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2834 break;
6de4f3ad
AK		 2835 case VCPU_EXREG_PDPTR:
2836 if (enable_ept)
2837 ept_save_pdptrs(vcpu);
2838 break;
5fdbf976
MT		 2839 default:
2840 break;
2841 }
6aa8b732
AK		 2842}
2843
6aa8b732
AK		 2844static __init int cpu_has_kvm_support(void)
2845{
6210e37b 2846 return cpu_has_vmx();
6aa8b732
AK		 2847}
2848
2849static __init int vmx_disabled_by_bios(void)
2850{
2851 u64 msr;
2852
2853 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2854 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2855 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2856 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2857 && tboot_enabled())
2858 return 1;
23f3e991 2859 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2860 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2861 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2862 && !tboot_enabled()) {
2863 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2864 "activate TXT before enabling KVM\n");
cafd6659 2865 return 1;
f9335afe 2866 }
23f3e991
JC		 2867 /* launched w/o TXT and VMX disabled */
2868 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2869 && !tboot_enabled())
2870 return 1;
cafd6659
SW		 2871 }
2872
2873 return 0;
6aa8b732
AK		 2874}
2875
7725b894
DX		 2876static void kvm_cpu_vmxon(u64 addr)
2877{
2878 asm volatile (ASM_VMX_VMXON_RAX
2879 : : "a"(&addr), "m"(addr)
2880 : "memory", "cc");
2881}
2882
13a34e06 2883static int hardware_enable(void)
6aa8b732
AK		 2884{
2885 int cpu = raw_smp_processor_id();
2886 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2887 u64 old, test_bits;
6aa8b732 2888
1e02ce4c 2889 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2890 return -EBUSY;
2891
d462b819 2892 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2893
2894 /*
2895 * Now we can enable the vmclear operation in kdump
2896 * since the loaded_vmcss_on_cpu list on this cpu
2897 * has been initialized.
2898 *
2899 * Though the cpu is not in VMX operation now, there
2900 * is no problem to enable the vmclear operation
2901 * for the loaded_vmcss_on_cpu list is empty!
2902 */
2903 crash_enable_local_vmclear(cpu);
2904
6aa8b732 2905 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2906
2907 test_bits = FEATURE_CONTROL_LOCKED;
2908 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2909 if (tboot_enabled())
2910 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2911
2912 if ((old & test_bits) != test_bits) {
6aa8b732 2913 /* enable and lock */
cafd6659
SW		 2914 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2915 }
375074cc 2916 cr4_set_bits(X86_CR4_VMXE);
10474ae8 2917
4610c9cc
DX		 2918 if (vmm_exclusive) {
2919 kvm_cpu_vmxon(phys_addr);
2920 ept_sync_global();
2921 }
10474ae8 2922
89cbc767 2923 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2924
10474ae8 2925 return 0;
6aa8b732
AK		 2926}
2927
d462b819 2928static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2929{
2930 int cpu = raw_smp_processor_id();
d462b819 2931 struct loaded_vmcs *v, *n;
543e4243 2932
d462b819
NHE		 2933 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2934 loaded_vmcss_on_cpu_link)
2935 __loaded_vmcs_clear(v);
543e4243
AK		 2936}
2937
710ff4a8
EH		 2938
2939/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2940 * tricks.
2941 */
2942static void kvm_cpu_vmxoff(void)
6aa8b732 2943{
4ecac3fd 2944 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2945}
2946
13a34e06 2947static void hardware_disable(void)
710ff4a8 2948{
4610c9cc 2949 if (vmm_exclusive) {
d462b819 2950 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2951 kvm_cpu_vmxoff();
2952 }
375074cc 2953 cr4_clear_bits(X86_CR4_VMXE);
710ff4a8
EH		 2954}
2955
1c3d14fe 2956static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2957 u32 msr, u32 *result)
1c3d14fe
YS		 2958{
2959 u32 vmx_msr_low, vmx_msr_high;
2960 u32 ctl = ctl_min | ctl_opt;
2961
2962 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2963
2964 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2965 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2966
2967 /* Ensure minimum (required) set of control bits are supported. */
2968 if (ctl_min & ~ctl)
002c7f7c 2969 return -EIO;
1c3d14fe
YS		 2970
2971 *result = ctl;
2972 return 0;
2973}
2974
110312c8
AK		 2975static __init bool allow_1_setting(u32 msr, u32 ctl)
2976{
2977 u32 vmx_msr_low, vmx_msr_high;
2978
2979 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2980 return vmx_msr_high & ctl;
2981}
2982
002c7f7c 2983static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2984{
2985 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2986 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2987 u32 _pin_based_exec_control = 0;
2988 u32 _cpu_based_exec_control = 0;
f78e0e2e 2989 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2990 u32 _vmexit_control = 0;
2991 u32 _vmentry_control = 0;
2992
10166744 2993 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2994#ifdef CONFIG_X86_64
2995 CPU_BASED_CR8_LOAD_EXITING |
2996 CPU_BASED_CR8_STORE_EXITING |
2997#endif
d56f546d
SY		 2998 CPU_BASED_CR3_LOAD_EXITING |
2999 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 3000 CPU_BASED_USE_IO_BITMAPS |
3001 CPU_BASED_MOV_DR_EXITING |
a7052897 3002 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 3003 CPU_BASED_MWAIT_EXITING |
3004 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 3005 CPU_BASED_INVLPG_EXITING |
3006 CPU_BASED_RDPMC_EXITING;
443381a8 3007
f78e0e2e 3008 opt = CPU_BASED_TPR_SHADOW |
25c5f225 3009 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 3010 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 3011 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3012 &_cpu_based_exec_control) < 0)
002c7f7c 3013 return -EIO;
6e5d865c
YS		 3014#ifdef CONFIG_X86_64
3015 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3016 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3017 ~CPU_BASED_CR8_STORE_EXITING;
3018#endif
f78e0e2e 3019 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 3020 min2 = 0;
3021 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3022 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3023 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3024 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3025 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3026 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3027 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3028 SECONDARY_EXEC_RDTSCP |
83d4c286 3029 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3030 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3031 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3032 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 3033 SECONDARY_EXEC_XSAVES |
8b3e34e4
XG		 3034 SECONDARY_EXEC_ENABLE_PML |
3035 SECONDARY_EXEC_PCOMMIT;
d56f546d
SY		 3036 if (adjust_vmx_controls(min2, opt2,
3037 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3038 &_cpu_based_2nd_exec_control) < 0)
3039 return -EIO;
3040 }
3041#ifndef CONFIG_X86_64
3042 if (!(_cpu_based_2nd_exec_control &
3043 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3044 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3045#endif
83d4c286
YZ		 3046
3047 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3048 _cpu_based_2nd_exec_control &= ~(
8d14695f 3049 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3050 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3051 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3052
d56f546d 3053 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3054 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3055 enabled */
5fff7d27
GN		 3056 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3057 CPU_BASED_CR3_STORE_EXITING |
3058 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3059 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3060 vmx_capability.ept, vmx_capability.vpid);
3061 }
1c3d14fe 3062
81908bf4 3063 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3064#ifdef CONFIG_X86_64
3065 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3066#endif
a547c6db 3067 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3068 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3069 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3070 &_vmexit_control) < 0)
002c7f7c 3071 return -EIO;
1c3d14fe 3072
01e439be
YZ		 3073 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3074 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3075 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3076 &_pin_based_exec_control) < 0)
3077 return -EIO;
3078
3079 if (!(_cpu_based_2nd_exec_control &
3080 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3081 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3082 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3083
c845f9c6 3084 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3085 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3086 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3087 &_vmentry_control) < 0)
002c7f7c 3088 return -EIO;
6aa8b732 3089
c68876fd 3090 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3091
3092 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3093 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3094 return -EIO;
1c3d14fe
YS		 3095
3096#ifdef CONFIG_X86_64
3097 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3098 if (vmx_msr_high & (1u<<16))
002c7f7c 3099 return -EIO;
1c3d14fe
YS		 3100#endif
3101
3102 /* Require Write-Back (WB) memory type for VMCS accesses. */
3103 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3104 return -EIO;
1c3d14fe 3105
002c7f7c
YS		 3106 vmcs_conf->size = vmx_msr_high & 0x1fff;
3107 vmcs_conf->order = get_order(vmcs_config.size);
3108 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3109
002c7f7c
YS		 3110 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3111 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3112 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3113 vmcs_conf->vmexit_ctrl = _vmexit_control;
3114 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3115
110312c8
AK		 3116 cpu_has_load_ia32_efer =
3117 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3118 VM_ENTRY_LOAD_IA32_EFER)
3119 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3120 VM_EXIT_LOAD_IA32_EFER);
3121
8bf00a52
GN		 3122 cpu_has_load_perf_global_ctrl =
3123 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3124 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3125 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3126 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3127
3128 /*
3129 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3130 * but due to arrata below it can't be used. Workaround is to use
3131 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3132 *
3133 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3134 *
3135 * AAK155 (model 26)
3136 * AAP115 (model 30)
3137 * AAT100 (model 37)
3138 * BC86,AAY89,BD102 (model 44)
3139 * BA97 (model 46)
3140 *
3141 */
3142 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3143 switch (boot_cpu_data.x86_model) {
3144 case 26:
3145 case 30:
3146 case 37:
3147 case 44:
3148 case 46:
3149 cpu_has_load_perf_global_ctrl = false;
3150 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3151 "does not work properly. Using workaround\n");
3152 break;
3153 default:
3154 break;
3155 }
3156 }
3157
20300099
WL		 3158 if (cpu_has_xsaves)
3159 rdmsrl(MSR_IA32_XSS, host_xss);
3160
1c3d14fe 3161 return 0;
c68876fd 3162}
6aa8b732
AK		 3163
3164static struct vmcs *alloc_vmcs_cpu(int cpu)
3165{
3166 int node = cpu_to_node(cpu);
3167 struct page *pages;
3168 struct vmcs *vmcs;
3169
96db800f 3170 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3171 if (!pages)
3172 return NULL;
3173 vmcs = page_address(pages);
1c3d14fe
YS		 3174 memset(vmcs, 0, vmcs_config.size);
3175 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3176 return vmcs;
3177}
3178
3179static struct vmcs *alloc_vmcs(void)
3180{
d3b2c338 3181 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3182}
3183
3184static void free_vmcs(struct vmcs *vmcs)
3185{
1c3d14fe 3186 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3187}
3188
d462b819
NHE		 3189/*
3190 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3191 */
3192static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3193{
3194 if (!loaded_vmcs->vmcs)
3195 return;
3196 loaded_vmcs_clear(loaded_vmcs);
3197 free_vmcs(loaded_vmcs->vmcs);
3198 loaded_vmcs->vmcs = NULL;
3199}
3200
39959588 3201static void free_kvm_area(void)
6aa8b732
AK		 3202{
3203 int cpu;
3204
3230bb47 3205 for_each_possible_cpu(cpu) {
6aa8b732 3206 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3207 per_cpu(vmxarea, cpu) = NULL;
3208 }
6aa8b732
AK		 3209}
3210
fe2b201b
BD		 3211static void init_vmcs_shadow_fields(void)
3212{
3213 int i, j;
3214
3215 /* No checks for read only fields yet */
3216
3217 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3218 switch (shadow_read_write_fields[i]) {
3219 case GUEST_BNDCFGS:
3220 if (!vmx_mpx_supported())
3221 continue;
3222 break;
3223 default:
3224 break;
3225 }
3226
3227 if (j < i)
3228 shadow_read_write_fields[j] =
3229 shadow_read_write_fields[i];
3230 j++;
3231 }
3232 max_shadow_read_write_fields = j;
3233
3234 /* shadowed fields guest access without vmexit */
3235 for (i = 0; i < max_shadow_read_write_fields; i++) {
3236 clear_bit(shadow_read_write_fields[i],
3237 vmx_vmwrite_bitmap);
3238 clear_bit(shadow_read_write_fields[i],
3239 vmx_vmread_bitmap);
3240 }
3241 for (i = 0; i < max_shadow_read_only_fields; i++)
3242 clear_bit(shadow_read_only_fields[i],
3243 vmx_vmread_bitmap);
3244}
3245
6aa8b732
AK		 3246static __init int alloc_kvm_area(void)
3247{
3248 int cpu;
3249
3230bb47 3250 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3251 struct vmcs *vmcs;
3252
3253 vmcs = alloc_vmcs_cpu(cpu);
3254 if (!vmcs) {
3255 free_kvm_area();
3256 return -ENOMEM;
3257 }
3258
3259 per_cpu(vmxarea, cpu) = vmcs;
3260 }
3261 return 0;
3262}
3263
14168786
GN		 3264static bool emulation_required(struct kvm_vcpu *vcpu)
3265{
3266 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3267}
3268
91b0aa2c 3269static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3270 struct kvm_segment *save)
6aa8b732 3271{
d99e4152
GN		 3272 if (!emulate_invalid_guest_state) {
3273 /*
3274 * CS and SS RPL should be equal during guest entry according
3275 * to VMX spec, but in reality it is not always so. Since vcpu
3276 * is in the middle of the transition from real mode to
3277 * protected mode it is safe to assume that RPL 0 is a good
3278 * default value.
3279 */
3280 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 3281 save->selector &= ~SEGMENT_RPL_MASK;
3282 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3283 save->s = 1;
6aa8b732 3284 }
d99e4152 3285 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3286}
3287
3288static void enter_pmode(struct kvm_vcpu *vcpu)
3289{
3290 unsigned long flags;
a89a8fb9 3291 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3292
d99e4152
GN		 3293 /*
3294 * Update real mode segment cache. It may be not up-to-date if sement
3295 * register was written while vcpu was in a guest mode.
3296 */
3297 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3298 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3299 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3300 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3301 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3302 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3303
7ffd92c5 3304 vmx->rmode.vm86_active = 0;
6aa8b732 3305
2fb92db1
AK		 3306 vmx_segment_cache_clear(vmx);
3307
f5f7b2fe 3308 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3309
3310 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3311 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3312 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3313 vmcs_writel(GUEST_RFLAGS, flags);
3314
66aee91a
RR		 3315 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3316 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3317
3318 update_exception_bitmap(vcpu);
3319
91b0aa2c
GN		 3320 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3321 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3322 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3323 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3324 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3325 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3326}
3327
f5f7b2fe 3328static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3329{
772e0318 3330 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3331 struct kvm_segment var = *save;
3332
3333 var.dpl = 0x3;
3334 if (seg == VCPU_SREG_CS)
3335 var.type = 0x3;
3336
3337 if (!emulate_invalid_guest_state) {
3338 var.selector = var.base >> 4;
3339 var.base = var.base & 0xffff0;
3340 var.limit = 0xffff;
3341 var.g = 0;
3342 var.db = 0;
3343 var.present = 1;
3344 var.s = 1;
3345 var.l = 0;
3346 var.unusable = 0;
3347 var.type = 0x3;
3348 var.avl = 0;
3349 if (save->base & 0xf)
3350 printk_once(KERN_WARNING "kvm: segment base is not "
3351 "paragraph aligned when entering "
3352 "protected mode (seg=%d)", seg);
3353 }
6aa8b732 3354
d99e4152
GN		 3355 vmcs_write16(sf->selector, var.selector);
3356 vmcs_write32(sf->base, var.base);
3357 vmcs_write32(sf->limit, var.limit);
3358 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3359}
3360
3361static void enter_rmode(struct kvm_vcpu *vcpu)
3362{
3363 unsigned long flags;
a89a8fb9 3364 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3365
f5f7b2fe
AK		 3366 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3367 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3368 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3369 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3370 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3371 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3372 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3373
7ffd92c5 3374 vmx->rmode.vm86_active = 1;
6aa8b732 3375
776e58ea
GN		 3376 /*
3377 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3378 * vcpu. Warn the user that an update is overdue.
776e58ea 3379 */
4918c6ca 3380 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3381 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3382 "called before entering vcpu\n");
776e58ea 3383
2fb92db1
AK		 3384 vmx_segment_cache_clear(vmx);
3385
4918c6ca 3386 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3387 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3388 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3389
3390 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3391 vmx->rmode.save_rflags = flags;
6aa8b732 3392
053de044 3393 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3394
3395 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3396 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3397 update_exception_bitmap(vcpu);
3398
d99e4152
GN		 3399 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3400 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3401 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3402 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3403 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3404 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3405
8668a3c4 3406 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3407}
3408
401d10de
AS		 3409static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3410{
3411 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3412 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3413
3414 if (!msr)
3415 return;
401d10de 3416
44ea2b17
AK		 3417 /*
3418 * Force kernel_gs_base reloading before EFER changes, as control
3419 * of this msr depends on is_long_mode().
3420 */
3421 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3422 vcpu->arch.efer = efer;
401d10de 3423 if (efer & EFER_LMA) {
2961e876 3424 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3425 msr->data = efer;
3426 } else {
2961e876 3427 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3428
3429 msr->data = efer & ~EFER_LME;
3430 }
3431 setup_msrs(vmx);
3432}
3433
05b3e0c2 3434#ifdef CONFIG_X86_64
6aa8b732
AK		 3435
3436static void enter_lmode(struct kvm_vcpu *vcpu)
3437{
3438 u32 guest_tr_ar;
3439
2fb92db1
AK		 3440 vmx_segment_cache_clear(to_vmx(vcpu));
3441
6aa8b732 3442 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 3443 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3444 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3445 __func__);
6aa8b732 3446 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 3447 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3448 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 3449 }
da38f438 3450 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3451}
3452
3453static void exit_lmode(struct kvm_vcpu *vcpu)
3454{
2961e876 3455 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3456 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3457}
3458
3459#endif
3460
2384d2b3
SY		 3461static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3462{
b9d762fa 3463 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3464 if (enable_ept) {
3465 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3466 return;
4e1096d2 3467 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3468 }
2384d2b3
SY		 3469}
3470
e8467fda
AK		 3471static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3472{
3473 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3474
3475 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3476 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3477}
3478
aff48baa
AK		 3479static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3480{
3481 if (enable_ept && is_paging(vcpu))
3482 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3483 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3484}
3485
25c4c276 3486static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3487{
fc78f519
AK		 3488 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3489
3490 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3491 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3492}
3493
1439442c
SY		 3494static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3495{
d0d538b9
GN		 3496 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3497
6de4f3ad
AK		 3498 if (!test_bit(VCPU_EXREG_PDPTR,
3499 (unsigned long *)&vcpu->arch.regs_dirty))
3500 return;
3501
1439442c 3502 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3503 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3504 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3505 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3506 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3507 }
3508}
3509
8f5d549f
AK		 3510static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3511{
d0d538b9
GN		 3512 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3513
8f5d549f 3514 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3515 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3516 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3517 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3518 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3519 }
6de4f3ad
AK		 3520
3521 __set_bit(VCPU_EXREG_PDPTR,
3522 (unsigned long *)&vcpu->arch.regs_avail);
3523 __set_bit(VCPU_EXREG_PDPTR,
3524 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3525}
3526
5e1746d6 3527static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3528
3529static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3530 unsigned long cr0,
3531 struct kvm_vcpu *vcpu)
3532{
5233dd51
MT		 3533 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3534 vmx_decache_cr3(vcpu);
1439442c
SY		 3535 if (!(cr0 & X86_CR0_PG)) {
3536 /* From paging/starting to nonpaging */
3537 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3538 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3539 (CPU_BASED_CR3_LOAD_EXITING |
3540 CPU_BASED_CR3_STORE_EXITING));
3541 vcpu->arch.cr0 = cr0;
fc78f519 3542 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3543 } else if (!is_paging(vcpu)) {
3544 /* From nonpaging to paging */
3545 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3546 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3547 ~(CPU_BASED_CR3_LOAD_EXITING |
3548 CPU_BASED_CR3_STORE_EXITING));
3549 vcpu->arch.cr0 = cr0;
fc78f519 3550 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3551 }
95eb84a7
SY		 3552
3553 if (!(cr0 & X86_CR0_WP))
3554 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3555}
3556
6aa8b732
AK		 3557static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3558{
7ffd92c5 3559 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3560 unsigned long hw_cr0;
3561
5037878e 3562 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3563 if (enable_unrestricted_guest)
5037878e 3564 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3565 else {
5037878e 3566 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3567
218e763f
GN		 3568 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3569 enter_pmode(vcpu);
6aa8b732 3570
218e763f
GN		 3571 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3572 enter_rmode(vcpu);
3573 }
6aa8b732 3574
05b3e0c2 3575#ifdef CONFIG_X86_64
f6801dff 3576 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3577 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3578 enter_lmode(vcpu);
707d92fa 3579 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3580 exit_lmode(vcpu);
3581 }
3582#endif
3583
089d034e 3584 if (enable_ept)
1439442c
SY		 3585 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3586
02daab21 3587 if (!vcpu->fpu_active)
81231c69 3588 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3589
6aa8b732 3590 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3591 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3592 vcpu->arch.cr0 = cr0;
14168786
GN		 3593
3594 /* depends on vcpu->arch.cr0 to be set to a new value */
3595 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3596}
3597
1439442c
SY		 3598static u64 construct_eptp(unsigned long root_hpa)
3599{
3600 u64 eptp;
3601
3602 /* TODO write the value reading from MSR */
3603 eptp = VMX_EPT_DEFAULT_MT |
3604 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3605 if (enable_ept_ad_bits)
3606 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3607 eptp |= (root_hpa & PAGE_MASK);
3608
3609 return eptp;
3610}
3611
6aa8b732
AK		 3612static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3613{
1439442c
SY		 3614 unsigned long guest_cr3;
3615 u64 eptp;
3616
3617 guest_cr3 = cr3;
089d034e 3618 if (enable_ept) {
1439442c
SY		 3619 eptp = construct_eptp(cr3);
3620 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3621 if (is_paging(vcpu) || is_guest_mode(vcpu))
3622 guest_cr3 = kvm_read_cr3(vcpu);
3623 else
3624 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3625 ept_load_pdptrs(vcpu);
1439442c
SY		 3626 }
3627
2384d2b3 3628 vmx_flush_tlb(vcpu);
1439442c 3629 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3630}
3631
5e1746d6 3632static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3633{
085e68ee
BS		 3634 /*
3635 * Pass through host's Machine Check Enable value to hw_cr4, which
3636 * is in force while we are in guest mode. Do not let guests control
3637 * this bit, even if host CR4.MCE == 0.
3638 */
3639 unsigned long hw_cr4 =
3640 (cr4_read_shadow() & X86_CR4_MCE) |
3641 (cr4 & ~X86_CR4_MCE) |
3642 (to_vmx(vcpu)->rmode.vm86_active ?
3643 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 3644
5e1746d6
NHE		 3645 if (cr4 & X86_CR4_VMXE) {
3646 /*
3647 * To use VMXON (and later other VMX instructions), a guest
3648 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3649 * So basically the check on whether to allow nested VMX
3650 * is here.
3651 */
3652 if (!nested_vmx_allowed(vcpu))
3653 return 1;
1a0d74e6
JK		 3654 }
3655 if (to_vmx(vcpu)->nested.vmxon &&
3656 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3657 return 1;
3658
ad312c7c 3659 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3660 if (enable_ept) {
3661 if (!is_paging(vcpu)) {
3662 hw_cr4 &= ~X86_CR4_PAE;
3663 hw_cr4 |= X86_CR4_PSE;
c08800a5 3664 /*
e1e746b3
FW		 3665 * SMEP/SMAP is disabled if CPU is in non-paging mode
3666 * in hardware. However KVM always uses paging mode to
c08800a5 3667 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3668 * To emulate this behavior, SMEP/SMAP needs to be
3669 * manually disabled when guest switches to non-paging
3670 * mode.
c08800a5 3671 */
e1e746b3 3672 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3673 } else if (!(cr4 & X86_CR4_PAE)) {
3674 hw_cr4 &= ~X86_CR4_PAE;
3675 }
3676 }
1439442c
SY		 3677
3678 vmcs_writel(CR4_READ_SHADOW, cr4);
3679 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3680 return 0;
6aa8b732
AK		 3681}
3682
6aa8b732
AK		 3683static void vmx_get_segment(struct kvm_vcpu *vcpu,
3684 struct kvm_segment *var, int seg)
3685{
a9179499 3686 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3687 u32 ar;
3688
c6ad1153 3689 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3690 *var = vmx->rmode.segs[seg];
a9179499 3691 if (seg == VCPU_SREG_TR
2fb92db1 3692 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3693 return;
1390a28b
AK		 3694 var->base = vmx_read_guest_seg_base(vmx, seg);
3695 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3696 return;
a9179499 3697 }
2fb92db1
AK		 3698 var->base = vmx_read_guest_seg_base(vmx, seg);
3699 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3700 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3701 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3702 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3703 var->type = ar & 15;
3704 var->s = (ar >> 4) & 1;
3705 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3706 /*
3707 * Some userspaces do not preserve unusable property. Since usable
3708 * segment has to be present according to VMX spec we can use present
3709 * property to amend userspace bug by making unusable segment always
3710 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3711 * segment as unusable.
3712 */
3713 var->present = !var->unusable;
6aa8b732
AK		 3714 var->avl = (ar >> 12) & 1;
3715 var->l = (ar >> 13) & 1;
3716 var->db = (ar >> 14) & 1;
3717 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3718}
3719
a9179499
AK		 3720static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3721{
a9179499
AK		 3722 struct kvm_segment s;
3723
3724 if (to_vmx(vcpu)->rmode.vm86_active) {
3725 vmx_get_segment(vcpu, &s, seg);
3726 return s.base;
3727 }
2fb92db1 3728 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3729}
3730
b09408d0 3731static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3732{
b09408d0
MT		 3733 struct vcpu_vmx *vmx = to_vmx(vcpu);
3734
ae9fedc7 3735 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3736 return 0;
ae9fedc7
PB		 3737 else {
3738 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3739 return VMX_AR_DPL(ar);
69c73028 3740 }
69c73028
AK		 3741}
3742
653e3108 3743static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3744{
6aa8b732
AK		 3745 u32 ar;
3746
f0495f9b 3747 if (var->unusable || !var->present)
6aa8b732
AK		 3748 ar = 1 << 16;
3749 else {
3750 ar = var->type & 15;
3751 ar |= (var->s & 1) << 4;
3752 ar |= (var->dpl & 3) << 5;
3753 ar |= (var->present & 1) << 7;
3754 ar |= (var->avl & 1) << 12;
3755 ar |= (var->l & 1) << 13;
3756 ar |= (var->db & 1) << 14;
3757 ar |= (var->g & 1) << 15;
3758 }
653e3108
AK		 3759
3760 return ar;
3761}
3762
3763static void vmx_set_segment(struct kvm_vcpu *vcpu,
3764 struct kvm_segment *var, int seg)
3765{
7ffd92c5 3766 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3767 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3768
2fb92db1
AK		 3769 vmx_segment_cache_clear(vmx);
3770
1ecd50a9
GN		 3771 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3772 vmx->rmode.segs[seg] = *var;
3773 if (seg == VCPU_SREG_TR)
3774 vmcs_write16(sf->selector, var->selector);
3775 else if (var->s)
3776 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3777 goto out;
653e3108 3778 }
1ecd50a9 3779
653e3108
AK		 3780 vmcs_writel(sf->base, var->base);
3781 vmcs_write32(sf->limit, var->limit);
3782 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3783
3784 /*
3785 * Fix the "Accessed" bit in AR field of segment registers for older
3786 * qemu binaries.
3787 * IA32 arch specifies that at the time of processor reset the
3788 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3789 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3790 * state vmexit when "unrestricted guest" mode is turned on.
3791 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3792 * tree. Newer qemu binaries with that qemu fix would not need this
3793 * kvm hack.
3794 */
3795 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3796 var->type |= 0x1; /* Accessed */
3a624e29 3797
f924d66d 3798 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3799
3800out:
98eb2f8b 3801 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3802}
3803
6aa8b732
AK		 3804static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3805{
2fb92db1 3806 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3807
3808 *db = (ar >> 14) & 1;
3809 *l = (ar >> 13) & 1;
3810}
3811
89a27f4d 3812static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3813{
89a27f4d
GN		 3814 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3815 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3816}
3817
89a27f4d 3818static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3819{
89a27f4d
GN		 3820 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3821 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3822}
3823
89a27f4d 3824static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3825{
89a27f4d
GN		 3826 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3827 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3828}
3829
89a27f4d 3830static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3831{
89a27f4d
GN		 3832 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3833 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3834}
3835
648dfaa7
MG		 3836static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3837{
3838 struct kvm_segment var;
3839 u32 ar;
3840
3841 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3842 var.dpl = 0x3;
0647f4aa
GN		 3843 if (seg == VCPU_SREG_CS)
3844 var.type = 0x3;
648dfaa7
MG		 3845 ar = vmx_segment_access_rights(&var);
3846
3847 if (var.base != (var.selector << 4))
3848 return false;
89efbed0 3849 if (var.limit != 0xffff)
648dfaa7 3850 return false;
07f42f5f 3851 if (ar != 0xf3)
648dfaa7
MG		 3852 return false;
3853
3854 return true;
3855}
3856
3857static bool code_segment_valid(struct kvm_vcpu *vcpu)
3858{
3859 struct kvm_segment cs;
3860 unsigned int cs_rpl;
3861
3862 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3863 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3864
1872a3f4
AK		 3865 if (cs.unusable)
3866 return false;
4d283ec9 3867 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3868 return false;
3869 if (!cs.s)
3870 return false;
4d283ec9 3871 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3872 if (cs.dpl > cs_rpl)
3873 return false;
1872a3f4 3874 } else {
648dfaa7
MG		 3875 if (cs.dpl != cs_rpl)
3876 return false;
3877 }
3878 if (!cs.present)
3879 return false;
3880
3881 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3882 return true;
3883}
3884
3885static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3886{
3887 struct kvm_segment ss;
3888 unsigned int ss_rpl;
3889
3890 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3891 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3892
1872a3f4
AK		 3893 if (ss.unusable)
3894 return true;
3895 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3896 return false;
3897 if (!ss.s)
3898 return false;
3899 if (ss.dpl != ss_rpl) /* DPL != RPL */
3900 return false;
3901 if (!ss.present)
3902 return false;
3903
3904 return true;
3905}
3906
3907static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3908{
3909 struct kvm_segment var;
3910 unsigned int rpl;
3911
3912 vmx_get_segment(vcpu, &var, seg);
b32a9918 3913 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3914
1872a3f4
AK		 3915 if (var.unusable)
3916 return true;
648dfaa7
MG		 3917 if (!var.s)
3918 return false;
3919 if (!var.present)
3920 return false;
4d283ec9 3921 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3922 if (var.dpl < rpl) /* DPL < RPL */
3923 return false;
3924 }
3925
3926 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3927 * rights flags
3928 */
3929 return true;
3930}
3931
3932static bool tr_valid(struct kvm_vcpu *vcpu)
3933{
3934 struct kvm_segment tr;
3935
3936 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3937
1872a3f4
AK		 3938 if (tr.unusable)
3939 return false;
b32a9918 3940 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3941 return false;
1872a3f4 3942 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3943 return false;
3944 if (!tr.present)
3945 return false;
3946
3947 return true;
3948}
3949
3950static bool ldtr_valid(struct kvm_vcpu *vcpu)
3951{
3952 struct kvm_segment ldtr;
3953
3954 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3955
1872a3f4
AK		 3956 if (ldtr.unusable)
3957 return true;
b32a9918 3958 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3959 return false;
3960 if (ldtr.type != 2)
3961 return false;
3962 if (!ldtr.present)
3963 return false;
3964
3965 return true;
3966}
3967
3968static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3969{
3970 struct kvm_segment cs, ss;
3971
3972 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3973 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3974
b32a9918
NA		 3975 return ((cs.selector & SEGMENT_RPL_MASK) ==
3976 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3977}
3978
3979/*
3980 * Check if guest state is valid. Returns true if valid, false if
3981 * not.
3982 * We assume that registers are always usable
3983 */
3984static bool guest_state_valid(struct kvm_vcpu *vcpu)
3985{
c5e97c80
GN		 3986 if (enable_unrestricted_guest)
3987 return true;
3988
648dfaa7 3989 /* real mode guest state checks */
f13882d8 3990 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3991 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3992 return false;
3993 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3994 return false;
3995 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3996 return false;
3997 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3998 return false;
3999 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4000 return false;
4001 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4002 return false;
4003 } else {
4004 /* protected mode guest state checks */
4005 if (!cs_ss_rpl_check(vcpu))
4006 return false;
4007 if (!code_segment_valid(vcpu))
4008 return false;
4009 if (!stack_segment_valid(vcpu))
4010 return false;
4011 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4012 return false;
4013 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4014 return false;
4015 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4016 return false;
4017 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4018 return false;
4019 if (!tr_valid(vcpu))
4020 return false;
4021 if (!ldtr_valid(vcpu))
4022 return false;
4023 }
4024 /* TODO:
4025 * - Add checks on RIP
4026 * - Add checks on RFLAGS
4027 */
4028
4029 return true;
4030}
4031
d77c26fc 4032static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4033{
40dcaa9f 4034 gfn_t fn;
195aefde 4035 u16 data = 0;
1f755a82 4036 int idx, r;
6aa8b732 4037
40dcaa9f 4038 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4039 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 4040 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4041 if (r < 0)
10589a46 4042 goto out;
195aefde 4043 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4044 r = kvm_write_guest_page(kvm, fn++, &data,
4045 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4046 if (r < 0)
10589a46 4047 goto out;
195aefde
IE		 4048 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4049 if (r < 0)
10589a46 4050 goto out;
195aefde
IE		 4051 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4052 if (r < 0)
10589a46 4053 goto out;
195aefde 4054 data = ~0;
10589a46
MT		 4055 r = kvm_write_guest_page(kvm, fn, &data,
4056 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4057 sizeof(u8));
10589a46 4058out:
40dcaa9f 4059 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4060 return r;
6aa8b732
AK		 4061}
4062
b7ebfb05
SY		 4063static int init_rmode_identity_map(struct kvm *kvm)
4064{
f51770ed 4065 int i, idx, r = 0;
b7ebfb05
SY		 4066 pfn_t identity_map_pfn;
4067 u32 tmp;
4068
089d034e 4069 if (!enable_ept)
f51770ed 4070 return 0;
a255d479
TC		 4071
4072 /* Protect kvm->arch.ept_identity_pagetable_done. */
4073 mutex_lock(&kvm->slots_lock);
4074
f51770ed 4075 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4076 goto out2;
a255d479 4077
b927a3ce 4078 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4079
4080 r = alloc_identity_pagetable(kvm);
f51770ed 4081 if (r < 0)
a255d479
TC		 4082 goto out2;
4083
40dcaa9f 4084 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4085 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4086 if (r < 0)
4087 goto out;
4088 /* Set up identity-mapping pagetable for EPT in real mode */
4089 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4090 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4091 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4092 r = kvm_write_guest_page(kvm, identity_map_pfn,
4093 &tmp, i * sizeof(tmp), sizeof(tmp));
4094 if (r < 0)
4095 goto out;
4096 }
4097 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4098
b7ebfb05 4099out:
40dcaa9f 4100 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4101
4102out2:
4103 mutex_unlock(&kvm->slots_lock);
f51770ed 4104 return r;
b7ebfb05
SY		 4105}
4106
6aa8b732
AK		 4107static void seg_setup(int seg)
4108{
772e0318 4109 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4110 unsigned int ar;
6aa8b732
AK		 4111
4112 vmcs_write16(sf->selector, 0);
4113 vmcs_writel(sf->base, 0);
4114 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4115 ar = 0x93;
4116 if (seg == VCPU_SREG_CS)
4117 ar |= 0x08; /* code segment */
3a624e29
NK		 4118
4119 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4120}
4121
f78e0e2e
SY		 4122static int alloc_apic_access_page(struct kvm *kvm)
4123{
4484141a 4124 struct page *page;
f78e0e2e
SY		 4125 struct kvm_userspace_memory_region kvm_userspace_mem;
4126 int r = 0;
4127
79fac95e 4128 mutex_lock(&kvm->slots_lock);
c24ae0dc 4129 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4130 goto out;
4131 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4132 kvm_userspace_mem.flags = 0;
73a6d941 4133 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4134 kvm_userspace_mem.memory_size = PAGE_SIZE;
9da0e4d5 4135 r = __x86_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4136 if (r)
4137 goto out;
72dc67a6 4138
73a6d941 4139 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4140 if (is_error_page(page)) {
4141 r = -EFAULT;
4142 goto out;
4143 }
4144
c24ae0dc
TC		 4145 /*
4146 * Do not pin the page in memory, so that memory hot-unplug
4147 * is able to migrate it.
4148 */
4149 put_page(page);
4150 kvm->arch.apic_access_page_done = true;
f78e0e2e 4151out:
79fac95e 4152 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4153 return r;
4154}
4155
b7ebfb05
SY		 4156static int alloc_identity_pagetable(struct kvm *kvm)
4157{
a255d479
TC		 4158 /* Called with kvm->slots_lock held. */
4159
b7ebfb05
SY		 4160 struct kvm_userspace_memory_region kvm_userspace_mem;
4161 int r = 0;
4162
a255d479
TC		 4163 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4164
b7ebfb05
SY		 4165 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4166 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4167 kvm_userspace_mem.guest_phys_addr =
4168 kvm->arch.ept_identity_map_addr;
b7ebfb05 4169 kvm_userspace_mem.memory_size = PAGE_SIZE;
9da0e4d5 4170 r = __x86_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4171
b7ebfb05
SY		 4172 return r;
4173}
4174
2384d2b3
SY		 4175static void allocate_vpid(struct vcpu_vmx *vmx)
4176{
4177 int vpid;
4178
4179 vmx->vpid = 0;
919818ab 4180 if (!enable_vpid)
2384d2b3
SY		 4181 return;
4182 spin_lock(&vmx_vpid_lock);
4183 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4184 if (vpid < VMX_NR_VPIDS) {
4185 vmx->vpid = vpid;
4186 __set_bit(vpid, vmx_vpid_bitmap);
4187 }
4188 spin_unlock(&vmx_vpid_lock);
4189}
4190
cdbecfc3
LJ		 4191static void free_vpid(struct vcpu_vmx *vmx)
4192{
4193 if (!enable_vpid)
4194 return;
4195 spin_lock(&vmx_vpid_lock);
4196 if (vmx->vpid != 0)
4197 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4198 spin_unlock(&vmx_vpid_lock);
4199}
4200
8d14695f
YZ		 4201#define MSR_TYPE_R 1
4202#define MSR_TYPE_W 2
4203static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4204 u32 msr, int type)
25c5f225 4205{
3e7c73e9 4206 int f = sizeof(unsigned long);
25c5f225
SY		 4207
4208 if (!cpu_has_vmx_msr_bitmap())
4209 return;
4210
4211 /*
4212 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4213 * have the write-low and read-high bitmap offsets the wrong way round.
4214 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4215 */
25c5f225 4216 if (msr <= 0x1fff) {
8d14695f
YZ		 4217 if (type & MSR_TYPE_R)
4218 /* read-low */
4219 __clear_bit(msr, msr_bitmap + 0x000 / f);
4220
4221 if (type & MSR_TYPE_W)
4222 /* write-low */
4223 __clear_bit(msr, msr_bitmap + 0x800 / f);
4224
25c5f225
SY		 4225 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4226 msr &= 0x1fff;
8d14695f
YZ		 4227 if (type & MSR_TYPE_R)
4228 /* read-high */
4229 __clear_bit(msr, msr_bitmap + 0x400 / f);
4230
4231 if (type & MSR_TYPE_W)
4232 /* write-high */
4233 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4234
4235 }
4236}
4237
4238static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4239 u32 msr, int type)
4240{
4241 int f = sizeof(unsigned long);
4242
4243 if (!cpu_has_vmx_msr_bitmap())
4244 return;
4245
4246 /*
4247 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4248 * have the write-low and read-high bitmap offsets the wrong way round.
4249 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4250 */
4251 if (msr <= 0x1fff) {
4252 if (type & MSR_TYPE_R)
4253 /* read-low */
4254 __set_bit(msr, msr_bitmap + 0x000 / f);
4255
4256 if (type & MSR_TYPE_W)
4257 /* write-low */
4258 __set_bit(msr, msr_bitmap + 0x800 / f);
4259
4260 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4261 msr &= 0x1fff;
4262 if (type & MSR_TYPE_R)
4263 /* read-high */
4264 __set_bit(msr, msr_bitmap + 0x400 / f);
4265
4266 if (type & MSR_TYPE_W)
4267 /* write-high */
4268 __set_bit(msr, msr_bitmap + 0xc00 / f);
4269
25c5f225 4270 }
25c5f225
SY		 4271}
4272
f2b93280
WV		 4273/*
4274 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4275 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4276 */
4277static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4278 unsigned long *msr_bitmap_nested,
4279 u32 msr, int type)
4280{
4281 int f = sizeof(unsigned long);
4282
4283 if (!cpu_has_vmx_msr_bitmap()) {
4284 WARN_ON(1);
4285 return;
4286 }
4287
4288 /*
4289 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4290 * have the write-low and read-high bitmap offsets the wrong way round.
4291 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4292 */
4293 if (msr <= 0x1fff) {
4294 if (type & MSR_TYPE_R &&
4295 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4296 /* read-low */
4297 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4298
4299 if (type & MSR_TYPE_W &&
4300 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4301 /* write-low */
4302 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4303
4304 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4305 msr &= 0x1fff;
4306 if (type & MSR_TYPE_R &&
4307 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4308 /* read-high */
4309 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4310
4311 if (type & MSR_TYPE_W &&
4312 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4313 /* write-high */
4314 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4315
4316 }
4317}
4318
5897297b
AK		 4319static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4320{
4321 if (!longmode_only)
8d14695f
YZ		 4322 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4323 msr, MSR_TYPE_R | MSR_TYPE_W);
4324 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4325 msr, MSR_TYPE_R | MSR_TYPE_W);
4326}
4327
4328static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4329{
4330 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4331 msr, MSR_TYPE_R);
4332 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4333 msr, MSR_TYPE_R);
4334}
4335
4336static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4337{
4338 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4339 msr, MSR_TYPE_R);
4340 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4341 msr, MSR_TYPE_R);
4342}
4343
4344static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4345{
4346 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4347 msr, MSR_TYPE_W);
4348 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4349 msr, MSR_TYPE_W);
5897297b
AK		 4350}
4351
d50ab6c1
PB		 4352static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4353{
35754c98 4354 return enable_apicv && lapic_in_kernel(vcpu);
d50ab6c1
PB		 4355}
4356
705699a1
WV		 4357static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4358{
4359 struct vcpu_vmx *vmx = to_vmx(vcpu);
4360 int max_irr;
4361 void *vapic_page;
4362 u16 status;
4363
4364 if (vmx->nested.pi_desc &&
4365 vmx->nested.pi_pending) {
4366 vmx->nested.pi_pending = false;
4367 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4368 return 0;
4369
4370 max_irr = find_last_bit(
4371 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4372
4373 if (max_irr == 256)
4374 return 0;
4375
4376 vapic_page = kmap(vmx->nested.virtual_apic_page);
4377 if (!vapic_page) {
4378 WARN_ON(1);
4379 return -ENOMEM;
4380 }
4381 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4382 kunmap(vmx->nested.virtual_apic_page);
4383
4384 status = vmcs_read16(GUEST_INTR_STATUS);
4385 if ((u8)max_irr > ((u8)status & 0xff)) {
4386 status &= ~0xff;
4387 status |= (u8)max_irr;
4388 vmcs_write16(GUEST_INTR_STATUS, status);
4389 }
4390 }
4391 return 0;
4392}
4393
21bc8dc5
RK		 4394static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4395{
4396#ifdef CONFIG_SMP
4397 if (vcpu->mode == IN_GUEST_MODE) {
4398 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4399 POSTED_INTR_VECTOR);
4400 return true;
4401 }
4402#endif
4403 return false;
4404}
4405
705699a1
WV		 4406static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4407 int vector)
4408{
4409 struct vcpu_vmx *vmx = to_vmx(vcpu);
4410
4411 if (is_guest_mode(vcpu) &&
4412 vector == vmx->nested.posted_intr_nv) {
4413 /* the PIR and ON have been set by L1. */
21bc8dc5 4414 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV		 4415 /*
4416 * If a posted intr is not recognized by hardware,
4417 * we will accomplish it in the next vmentry.
4418 */
4419 vmx->nested.pi_pending = true;
4420 kvm_make_request(KVM_REQ_EVENT, vcpu);
4421 return 0;
4422 }
4423 return -1;
4424}
a20ed54d
YZ		 4425/*
4426 * Send interrupt to vcpu via posted interrupt way.
4427 * 1. If target vcpu is running(non-root mode), send posted interrupt
4428 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4429 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4430 * interrupt from PIR in next vmentry.
4431 */
4432static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4433{
4434 struct vcpu_vmx *vmx = to_vmx(vcpu);
4435 int r;
4436
705699a1
WV		 4437 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4438 if (!r)
4439 return;
4440
a20ed54d
YZ		 4441 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4442 return;
4443
4444 r = pi_test_and_set_on(&vmx->pi_desc);
4445 kvm_make_request(KVM_REQ_EVENT, vcpu);
21bc8dc5 4446 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ		 4447 kvm_vcpu_kick(vcpu);
4448}
4449
4450static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4451{
4452 struct vcpu_vmx *vmx = to_vmx(vcpu);
4453
4454 if (!pi_test_and_clear_on(&vmx->pi_desc))
4455 return;
4456
4457 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4458}
4459
4460static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4461{
4462 return;
4463}
4464
a3a8ff8e
NHE		 4465/*
4466 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4467 * will not change in the lifetime of the guest.
4468 * Note that host-state that does change is set elsewhere. E.g., host-state
4469 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4470 */
a547c6db 4471static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4472{
4473 u32 low32, high32;
4474 unsigned long tmpl;
4475 struct desc_ptr dt;
d974baa3 4476 unsigned long cr4;
a3a8ff8e 4477
b1a74bf8 4478 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4479 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4480
d974baa3 4481 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 4482 cr4 = cr4_read_shadow();
d974baa3
AL		 4483 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4484 vmx->host_state.vmcs_host_cr4 = cr4;
4485
a3a8ff8e 4486 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4487#ifdef CONFIG_X86_64
4488 /*
4489 * Load null selectors, so we can avoid reloading them in
4490 * __vmx_load_host_state(), in case userspace uses the null selectors
4491 * too (the expected case).
4492 */
4493 vmcs_write16(HOST_DS_SELECTOR, 0);
4494 vmcs_write16(HOST_ES_SELECTOR, 0);
4495#else
a3a8ff8e
NHE		 4496 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4497 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4498#endif
a3a8ff8e
NHE		 4499 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4500 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4501
4502 native_store_idt(&dt);
4503 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4504 vmx->host_idt_base = dt.address;
a3a8ff8e 4505
83287ea4 4506 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4507
4508 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4509 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4510 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4511 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4512
4513 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4514 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4515 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4516 }
4517}
4518
bf8179a0
NHE		 4519static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4520{
4521 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4522 if (enable_ept)
4523 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4524 if (is_guest_mode(&vmx->vcpu))
4525 vmx->vcpu.arch.cr4_guest_owned_bits &=
4526 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4527 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4528}
4529
01e439be
YZ		 4530static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4531{
4532 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4533
35754c98 4534 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
01e439be
YZ		 4535 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4536 return pin_based_exec_ctrl;
4537}
4538
bf8179a0
NHE		 4539static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4540{
4541 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4542
4543 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4544 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4545
35754c98 4546 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE		 4547 exec_control &= ~CPU_BASED_TPR_SHADOW;
4548#ifdef CONFIG_X86_64
4549 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4550 CPU_BASED_CR8_LOAD_EXITING;
4551#endif
4552 }
4553 if (!enable_ept)
4554 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4555 CPU_BASED_CR3_LOAD_EXITING |
4556 CPU_BASED_INVLPG_EXITING;
4557 return exec_control;
4558}
4559
4560static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4561{
4562 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 4563 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE		 4564 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4565 if (vmx->vpid == 0)
4566 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4567 if (!enable_ept) {
4568 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4569 enable_unrestricted_guest = 0;
ad756a16
MJ		 4570 /* Enable INVPCID for non-ept guests may cause performance regression. */
4571 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4572 }
4573 if (!enable_unrestricted_guest)
4574 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4575 if (!ple_gap)
4576 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
35754c98 4577 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
c7c9c56c
YZ		 4578 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4579 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4580 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4581 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4582 (handle_vmptrld).
4583 We can NOT enable shadow_vmcs here because we don't have yet
4584 a current VMCS12
4585 */
4586 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4587 /* PML is enabled/disabled in creating/destorying vcpu */
4588 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4589
8b3e34e4
XG		 4590 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4591 exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4592
bf8179a0
NHE		 4593 return exec_control;
4594}
4595
ce88decf
XG		 4596static void ept_set_mmio_spte_mask(void)
4597{
4598 /*
4599 * EPT Misconfigurations can be generated if the value of bits 2:0
4600 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4601 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4602 * spte.
4603 */
885032b9 4604 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4605}
4606
f53cd63c 4607#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4608/*
4609 * Sets up the vmcs for emulated real mode.
4610 */
8b9cf98c 4611static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4612{
2e4ce7f5 4613#ifdef CONFIG_X86_64
6aa8b732 4614 unsigned long a;
2e4ce7f5 4615#endif
6aa8b732 4616 int i;
6aa8b732 4617
6aa8b732 4618 /* I/O */
3e7c73e9
AK		 4619 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4620 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4621
4607c2d7
AG		 4622 if (enable_shadow_vmcs) {
4623 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4624 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4625 }
25c5f225 4626 if (cpu_has_vmx_msr_bitmap())
5897297b 4627 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4628
6aa8b732
AK		 4629 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4630
6aa8b732 4631 /* Control */
01e439be 4632 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4633
bf8179a0 4634 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4635
8b3e34e4 4636 if (cpu_has_secondary_exec_ctrls())
bf8179a0
NHE		 4637 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4638 vmx_secondary_exec_control(vmx));
f78e0e2e 4639
35754c98 4640 if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
c7c9c56c
YZ		 4641 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4642 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4643 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4644 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4645
4646 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4647
4648 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4649 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4650 }
4651
4b8d54f9
ZE		 4652 if (ple_gap) {
4653 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4654 vmx->ple_window = ple_window;
4655 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4656 }
4657
c3707958
XG		 4658 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4659 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4660 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4661
9581d442
AK		 4662 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4663 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4664 vmx_set_constant_host_state(vmx);
05b3e0c2 4665#ifdef CONFIG_X86_64
6aa8b732
AK		 4666 rdmsrl(MSR_FS_BASE, a);
4667 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4668 rdmsrl(MSR_GS_BASE, a);
4669 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4670#else
4671 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4672 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4673#endif
4674
2cc51560
ED		 4675 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4676 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4677 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4678 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4679 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4680
74545705
RK		 4681 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4682 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4683
03916db9 4684 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4685 u32 index = vmx_msr_index[i];
4686 u32 data_low, data_high;
a2fa3e9f 4687 int j = vmx->nmsrs;
6aa8b732
AK		 4688
4689 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4690 continue;
432bd6cb
AK		 4691 if (wrmsr_safe(index, data_low, data_high) < 0)
4692 continue;
26bb0981
AK		 4693 vmx->guest_msrs[j].index = i;
4694 vmx->guest_msrs[j].data = 0;
d5696725 4695 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4696 ++vmx->nmsrs;
6aa8b732 4697 }
6aa8b732 4698
2961e876
GN		 4699
4700 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4701
4702 /* 22.2.1, 20.8.1 */
2961e876 4703 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4704
e00c8cf2 4705 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4706 set_cr4_guest_host_mask(vmx);
e00c8cf2 4707
f53cd63c
WL		 4708 if (vmx_xsaves_supported())
4709 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4710
e00c8cf2
AK		 4711 return 0;
4712}
4713
d28bc9dd 4714static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4715{
4716 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4717 struct msr_data apic_base_msr;
d28bc9dd 4718 u64 cr0;
e00c8cf2 4719
7ffd92c5 4720 vmx->rmode.vm86_active = 0;
e00c8cf2 4721
3b86cd99
JK		 4722 vmx->soft_vnmi_blocked = 0;
4723
ad312c7c 4724 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 4725 kvm_set_cr8(vcpu, 0);
4726
4727 if (!init_event) {
4728 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4729 MSR_IA32_APICBASE_ENABLE;
4730 if (kvm_vcpu_is_reset_bsp(vcpu))
4731 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4732 apic_base_msr.host_initiated = true;
4733 kvm_set_apic_base(vcpu, &apic_base_msr);
4734 }
e00c8cf2 4735
2fb92db1
AK		 4736 vmx_segment_cache_clear(vmx);
4737
5706be0d 4738 seg_setup(VCPU_SREG_CS);
66450a21 4739 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4740 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4741
4742 seg_setup(VCPU_SREG_DS);
4743 seg_setup(VCPU_SREG_ES);
4744 seg_setup(VCPU_SREG_FS);
4745 seg_setup(VCPU_SREG_GS);
4746 seg_setup(VCPU_SREG_SS);
4747
4748 vmcs_write16(GUEST_TR_SELECTOR, 0);
4749 vmcs_writel(GUEST_TR_BASE, 0);
4750 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4751 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4752
4753 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4754 vmcs_writel(GUEST_LDTR_BASE, 0);
4755 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4756 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4757
d28bc9dd
NA		 4758 if (!init_event) {
4759 vmcs_write32(GUEST_SYSENTER_CS, 0);
4760 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4761 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4762 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4763 }
e00c8cf2
AK		 4764
4765 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4766 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4767
e00c8cf2
AK		 4768 vmcs_writel(GUEST_GDTR_BASE, 0);
4769 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4770
4771 vmcs_writel(GUEST_IDTR_BASE, 0);
4772 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4773
443381a8 4774 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4775 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4776 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4777
e00c8cf2
AK		 4778 setup_msrs(vmx);
4779
6aa8b732
AK		 4780 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4781
d28bc9dd 4782 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4783 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4784 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4785 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4786 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4787 vmcs_write32(TPR_THRESHOLD, 0);
4788 }
4789
a73896cb 4790 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4791
35754c98 4792 if (vmx_cpu_uses_apicv(vcpu))
01e439be
YZ		 4793 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4794
2384d2b3
SY		 4795 if (vmx->vpid != 0)
4796 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4797
d28bc9dd
NA		 4798 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4799 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4800 vmx->vcpu.arch.cr0 = cr0;
4801 vmx_set_cr4(vcpu, 0);
4802 if (!init_event)
4803 vmx_set_efer(vcpu, 0);
4804 vmx_fpu_activate(vcpu);
4805 update_exception_bitmap(vcpu);
6aa8b732 4806
b9d762fa 4807 vpid_sync_context(vmx);
6aa8b732
AK		 4808}
4809
b6f1250e
NHE		 4810/*
4811 * In nested virtualization, check if L1 asked to exit on external interrupts.
4812 * For most existing hypervisors, this will always return true.
4813 */
4814static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4815{
4816 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4817 PIN_BASED_EXT_INTR_MASK;
4818}
4819
77b0f5d6
BD		 4820/*
4821 * In nested virtualization, check if L1 has set
4822 * VM_EXIT_ACK_INTR_ON_EXIT
4823 */
4824static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4825{
4826 return get_vmcs12(vcpu)->vm_exit_controls &
4827 VM_EXIT_ACK_INTR_ON_EXIT;
4828}
4829
ea8ceb83
JK		 4830static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4831{
4832 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4833 PIN_BASED_NMI_EXITING;
4834}
4835
c9a7953f 4836static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4837{
4838 u32 cpu_based_vm_exec_control;
730dca42 4839
3b86cd99
JK		 4840 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4841 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4842 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4843}
4844
c9a7953f 4845static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4846{
4847 u32 cpu_based_vm_exec_control;
4848
c9a7953f
JK		 4849 if (!cpu_has_virtual_nmis() ||
4850 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4851 enable_irq_window(vcpu);
4852 return;
4853 }
3b86cd99
JK		 4854
4855 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4856 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4857 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4858}
4859
66fd3f7f 4860static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4861{
9c8cba37 4862 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4863 uint32_t intr;
4864 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4865
229456fc 4866 trace_kvm_inj_virq(irq);
2714d1d3 4867
fa89a817 4868 ++vcpu->stat.irq_injections;
7ffd92c5 4869 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4870 int inc_eip = 0;
4871 if (vcpu->arch.interrupt.soft)
4872 inc_eip = vcpu->arch.event_exit_inst_len;
4873 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4874 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4875 return;
4876 }
66fd3f7f
GN		 4877 intr = irq | INTR_INFO_VALID_MASK;
4878 if (vcpu->arch.interrupt.soft) {
4879 intr |= INTR_TYPE_SOFT_INTR;
4880 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4881 vmx->vcpu.arch.event_exit_inst_len);
4882 } else
4883 intr |= INTR_TYPE_EXT_INTR;
4884 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4885}
4886
f08864b4
SY		 4887static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4888{
66a5a347
JK		 4889 struct vcpu_vmx *vmx = to_vmx(vcpu);
4890
0b6ac343
NHE		 4891 if (is_guest_mode(vcpu))
4892 return;
4893
3b86cd99
JK		 4894 if (!cpu_has_virtual_nmis()) {
4895 /*
4896 * Tracking the NMI-blocked state in software is built upon
4897 * finding the next open IRQ window. This, in turn, depends on
4898 * well-behaving guests: They have to keep IRQs disabled at
4899 * least as long as the NMI handler runs. Otherwise we may
4900 * cause NMI nesting, maybe breaking the guest. But as this is
4901 * highly unlikely, we can live with the residual risk.
4902 */
4903 vmx->soft_vnmi_blocked = 1;
4904 vmx->vnmi_blocked_time = 0;
4905 }
4906
487b391d 4907 ++vcpu->stat.nmi_injections;
9d58b931 4908 vmx->nmi_known_unmasked = false;
7ffd92c5 4909 if (vmx->rmode.vm86_active) {
71f9833b 4910 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4911 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4912 return;
4913 }
f08864b4
SY		 4914 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4915 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4916}
4917
3cfc3092
JK		 4918static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4919{
4920 if (!cpu_has_virtual_nmis())
4921 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4922 if (to_vmx(vcpu)->nmi_known_unmasked)
4923 return false;
c332c83a 4924 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4925}
4926
4927static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4928{
4929 struct vcpu_vmx *vmx = to_vmx(vcpu);
4930
4931 if (!cpu_has_virtual_nmis()) {
4932 if (vmx->soft_vnmi_blocked != masked) {
4933 vmx->soft_vnmi_blocked = masked;
4934 vmx->vnmi_blocked_time = 0;
4935 }
4936 } else {
9d58b931 4937 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4938 if (masked)
4939 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4940 GUEST_INTR_STATE_NMI);
4941 else
4942 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4943 GUEST_INTR_STATE_NMI);
4944 }
4945}
4946
2505dc9f
JK		 4947static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4948{
b6b8a145
JK		 4949 if (to_vmx(vcpu)->nested.nested_run_pending)
4950 return 0;
ea8ceb83 4951
2505dc9f
JK		 4952 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4953 return 0;
4954
4955 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4956 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4957 | GUEST_INTR_STATE_NMI));
4958}
4959
78646121
GN		 4960static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4961{
b6b8a145
JK		 4962 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4963 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4964 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4965 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4966}
4967
cbc94022
IE		 4968static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4969{
4970 int ret;
4971 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4972 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4973 .guest_phys_addr = addr,
4974 .memory_size = PAGE_SIZE * 3,
4975 .flags = 0,
4976 };
4977
9da0e4d5 4978 ret = x86_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4979 if (ret)
4980 return ret;
bfc6d222 4981 kvm->arch.tss_addr = addr;
1f755a82 4982 return init_rmode_tss(kvm);
cbc94022
IE		 4983}
4984
0ca1b4f4 4985static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4986{
77ab6db0 4987 switch (vec) {
77ab6db0 4988 case BP_VECTOR:
c573cd22
JK		 4989 /*
4990 * Update instruction length as we may reinject the exception
4991 * from user space while in guest debugging mode.
4992 */
4993 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4994 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4995 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4996 return false;
4997 /* fall through */
4998 case DB_VECTOR:
4999 if (vcpu->guest_debug &
5000 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5001 return false;
d0bfb940
JK		 5002 /* fall through */
5003 case DE_VECTOR:
77ab6db0
JK		 5004 case OF_VECTOR:
5005 case BR_VECTOR:
5006 case UD_VECTOR:
5007 case DF_VECTOR:
5008 case SS_VECTOR:
5009 case GP_VECTOR:
5010 case MF_VECTOR:
0ca1b4f4
GN		 5011 return true;
5012 break;
77ab6db0 5013 }
0ca1b4f4
GN		 5014 return false;
5015}
5016
5017static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5018 int vec, u32 err_code)
5019{
5020 /*
5021 * Instruction with address size override prefix opcode 0x67
5022 * Cause the #SS fault with 0 error code in VM86 mode.
5023 */
5024 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5025 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5026 if (vcpu->arch.halt_request) {
5027 vcpu->arch.halt_request = 0;
5cb56059 5028 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 5029 }
5030 return 1;
5031 }
5032 return 0;
5033 }
5034
5035 /*
5036 * Forward all other exceptions that are valid in real mode.
5037 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5038 * the required debugging infrastructure rework.
5039 */
5040 kvm_queue_exception(vcpu, vec);
5041 return 1;
6aa8b732
AK		 5042}
5043
a0861c02
AK		 5044/*
5045 * Trigger machine check on the host. We assume all the MSRs are already set up
5046 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5047 * We pass a fake environment to the machine check handler because we want
5048 * the guest to be always treated like user space, no matter what context
5049 * it used internally.
5050 */
5051static void kvm_machine_check(void)
5052{
5053#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5054 struct pt_regs regs = {
5055 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5056 .flags = X86_EFLAGS_IF,
5057 };
5058
5059 do_machine_check(&regs, 0);
5060#endif
5061}
5062
851ba692 5063static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 5064{
5065 /* already handled by vcpu_run */
5066 return 1;
5067}
5068
851ba692 5069static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5070{
1155f76a 5071 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5072 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5073 u32 intr_info, ex_no, error_code;
42dbaa5a 5074 unsigned long cr2, rip, dr6;
6aa8b732
AK		 5075 u32 vect_info;
5076 enum emulation_result er;
5077
1155f76a 5078 vect_info = vmx->idt_vectoring_info;
88786475 5079 intr_info = vmx->exit_intr_info;
6aa8b732 5080
a0861c02 5081 if (is_machine_check(intr_info))
851ba692 5082 return handle_machine_check(vcpu);
a0861c02 5083
e4a41889 5084 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 5085 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 5086
5087 if (is_no_device(intr_info)) {
5fd86fcf 5088 vmx_fpu_activate(vcpu);
2ab455cc
AL		 5089 return 1;
5090 }
5091
7aa81cc0 5092 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK		 5093 if (is_guest_mode(vcpu)) {
5094 kvm_queue_exception(vcpu, UD_VECTOR);
5095 return 1;
5096 }
51d8b661 5097 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5098 if (er != EMULATE_DONE)
7ee5d940 5099 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 5100 return 1;
5101 }
5102
6aa8b732 5103 error_code = 0;
2e11384c 5104 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5105 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 5106
5107 /*
5108 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5109 * MMIO, it is better to report an internal error.
5110 * See the comments in vmx_handle_exit.
5111 */
5112 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5113 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5114 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5115 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5116 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 5117 vcpu->run->internal.data[0] = vect_info;
5118 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5119 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 5120 return 0;
5121 }
5122
6aa8b732 5123 if (is_page_fault(intr_info)) {
1439442c 5124 /* EPT won't cause page fault directly */
cf3ace79 5125 BUG_ON(enable_ept);
6aa8b732 5126 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5127 trace_kvm_page_fault(cr2, error_code);
5128
3298b75c 5129 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5130 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5131 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5132 }
5133
d0bfb940 5134 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5135
5136 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5137 return handle_rmode_exception(vcpu, ex_no, error_code);
5138
42dbaa5a
JK		 5139 switch (ex_no) {
5140 case DB_VECTOR:
5141 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5142 if (!(vcpu->guest_debug &
5143 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5144 vcpu->arch.dr6 &= ~15;
6f43ed01 5145 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5146 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5147 skip_emulated_instruction(vcpu);
5148
42dbaa5a
JK		 5149 kvm_queue_exception(vcpu, DB_VECTOR);
5150 return 1;
5151 }
5152 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5153 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5154 /* fall through */
5155 case BP_VECTOR:
c573cd22
JK		 5156 /*
5157 * Update instruction length as we may reinject #BP from
5158 * user space while in guest debugging mode. Reading it for
5159 * #DB as well causes no harm, it is not used in that case.
5160 */
5161 vmx->vcpu.arch.event_exit_inst_len =
5162 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5163 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5164 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5165 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5166 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5167 break;
5168 default:
d0bfb940
JK		 5169 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5170 kvm_run->ex.exception = ex_no;
5171 kvm_run->ex.error_code = error_code;
42dbaa5a 5172 break;
6aa8b732 5173 }
6aa8b732
AK		 5174 return 0;
5175}
5176
851ba692 5177static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5178{
1165f5fe 5179 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5180 return 1;
5181}
5182
851ba692 5183static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5184{
851ba692 5185 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5186 return 0;
5187}
6aa8b732 5188
851ba692 5189static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5190{
bfdaab09 5191 unsigned long exit_qualification;
34c33d16 5192 int size, in, string;
039576c0 5193 unsigned port;
6aa8b732 5194
bfdaab09 5195 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5196 string = (exit_qualification & 16) != 0;
cf8f70bf 5197 in = (exit_qualification & 8) != 0;
e70669ab 5198
cf8f70bf 5199 ++vcpu->stat.io_exits;
e70669ab 5200
cf8f70bf 5201 if (string || in)
51d8b661 5202 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5203
cf8f70bf
GN		 5204 port = exit_qualification >> 16;
5205 size = (exit_qualification & 7) + 1;
e93f36bc 5206 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5207
5208 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5209}
5210
102d8325
IM		 5211static void
5212vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5213{
5214 /*
5215 * Patch in the VMCALL instruction:
5216 */
5217 hypercall[0] = 0x0f;
5218 hypercall[1] = 0x01;
5219 hypercall[2] = 0xc1;
102d8325
IM		 5220}
5221
b9c237bb 5222static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5223{
5224 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5225 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5226
b9c237bb 5227 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5228 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5229 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5230 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5231 return (val & always_on) == always_on;
5232}
5233
0fa06071 5234/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5235static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5236{
eeadf9e7 5237 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5238 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5239 unsigned long orig_val = val;
5240
eeadf9e7
NHE		 5241 /*
5242 * We get here when L2 changed cr0 in a way that did not change
5243 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5244 * but did change L0 shadowed bits. So we first calculate the
5245 * effective cr0 value that L1 would like to write into the
5246 * hardware. It consists of the L2-owned bits from the new
5247 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5248 */
1a0d74e6
JK		 5249 val = (val & ~vmcs12->cr0_guest_host_mask) |
5250 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5251
b9c237bb 5252 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5253 return 1;
1a0d74e6
JK		 5254
5255 if (kvm_set_cr0(vcpu, val))
5256 return 1;
5257 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5258 return 0;
1a0d74e6
JK		 5259 } else {
5260 if (to_vmx(vcpu)->nested.vmxon &&
5261 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5262 return 1;
eeadf9e7 5263 return kvm_set_cr0(vcpu, val);
1a0d74e6 5264 }
eeadf9e7
NHE		 5265}
5266
5267static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5268{
5269 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5270 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5271 unsigned long orig_val = val;
5272
5273 /* analogously to handle_set_cr0 */
5274 val = (val & ~vmcs12->cr4_guest_host_mask) |
5275 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5276 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5277 return 1;
1a0d74e6 5278 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5279 return 0;
5280 } else
5281 return kvm_set_cr4(vcpu, val);
5282}
5283
5284/* called to set cr0 as approriate for clts instruction exit. */
5285static void handle_clts(struct kvm_vcpu *vcpu)
5286{
5287 if (is_guest_mode(vcpu)) {
5288 /*
5289 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5290 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5291 * just pretend it's off (also in arch.cr0 for fpu_activate).
5292 */
5293 vmcs_writel(CR0_READ_SHADOW,
5294 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5295 vcpu->arch.cr0 &= ~X86_CR0_TS;
5296 } else
5297 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5298}
5299
851ba692 5300static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5301{
229456fc 5302 unsigned long exit_qualification, val;
6aa8b732
AK		 5303 int cr;
5304 int reg;
49a9b07e 5305 int err;
6aa8b732 5306
bfdaab09 5307 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5308 cr = exit_qualification & 15;
5309 reg = (exit_qualification >> 8) & 15;
5310 switch ((exit_qualification >> 4) & 3) {
5311 case 0: /* mov to cr */
1e32c079 5312 val = kvm_register_readl(vcpu, reg);
229456fc 5313 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5314 switch (cr) {
5315 case 0:
eeadf9e7 5316 err = handle_set_cr0(vcpu, val);
db8fcefa 5317 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5318 return 1;
5319 case 3:
2390218b 5320 err = kvm_set_cr3(vcpu, val);
db8fcefa 5321 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5322 return 1;
5323 case 4:
eeadf9e7 5324 err = handle_set_cr4(vcpu, val);
db8fcefa 5325 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5326 return 1;
0a5fff19
GN		 5327 case 8: {
5328 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5329 u8 cr8 = (u8)val;
eea1cff9 5330 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5331 kvm_complete_insn_gp(vcpu, err);
35754c98 5332 if (lapic_in_kernel(vcpu))
0a5fff19
GN		 5333 return 1;
5334 if (cr8_prev <= cr8)
5335 return 1;
851ba692 5336 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5337 return 0;
5338 }
4b8073e4 5339 }
6aa8b732 5340 break;
25c4c276 5341 case 2: /* clts */
eeadf9e7 5342 handle_clts(vcpu);
4d4ec087 5343 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5344 skip_emulated_instruction(vcpu);
6b52d186 5345 vmx_fpu_activate(vcpu);
25c4c276 5346 return 1;
6aa8b732
AK		 5347 case 1: /*mov from cr*/
5348 switch (cr) {
5349 case 3:
9f8fe504
AK		 5350 val = kvm_read_cr3(vcpu);
5351 kvm_register_write(vcpu, reg, val);
5352 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5353 skip_emulated_instruction(vcpu);
5354 return 1;
5355 case 8:
229456fc
MT		 5356 val = kvm_get_cr8(vcpu);
5357 kvm_register_write(vcpu, reg, val);
5358 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5359 skip_emulated_instruction(vcpu);
5360 return 1;
5361 }
5362 break;
5363 case 3: /* lmsw */
a1f83a74 5364 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5365 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5366 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5367
5368 skip_emulated_instruction(vcpu);
5369 return 1;
5370 default:
5371 break;
5372 }
851ba692 5373 vcpu->run->exit_reason = 0;
a737f256 5374 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5375 (int)(exit_qualification >> 4) & 3, cr);
5376 return 0;
5377}
5378
851ba692 5379static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5380{
bfdaab09 5381 unsigned long exit_qualification;
16f8a6f9
NA		 5382 int dr, dr7, reg;
5383
5384 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5385 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5386
5387 /* First, if DR does not exist, trigger UD */
5388 if (!kvm_require_dr(vcpu, dr))
5389 return 1;
6aa8b732 5390
f2483415 5391 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5392 if (!kvm_require_cpl(vcpu, 0))
5393 return 1;
16f8a6f9
NA		 5394 dr7 = vmcs_readl(GUEST_DR7);
5395 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5396 /*
5397 * As the vm-exit takes precedence over the debug trap, we
5398 * need to emulate the latter, either for the host or the
5399 * guest debugging itself.
5400 */
5401 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5402 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5403 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5404 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5405 vcpu->run->debug.arch.exception = DB_VECTOR;
5406 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5407 return 0;
5408 } else {
7305eb5d 5409 vcpu->arch.dr6 &= ~15;
6f43ed01 5410 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5411 kvm_queue_exception(vcpu, DB_VECTOR);
5412 return 1;
5413 }
5414 }
5415
81908bf4
PB		 5416 if (vcpu->guest_debug == 0) {
5417 u32 cpu_based_vm_exec_control;
5418
5419 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5420 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5421 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5422
5423 /*
5424 * No more DR vmexits; force a reload of the debug registers
5425 * and reenter on this instruction. The next vmexit will
5426 * retrieve the full state of the debug registers.
5427 */
5428 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5429 return 1;
5430 }
5431
42dbaa5a
JK		 5432 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5433 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5434 unsigned long val;
4c4d563b
JK		 5435
5436 if (kvm_get_dr(vcpu, dr, &val))
5437 return 1;
5438 kvm_register_write(vcpu, reg, val);
020df079 5439 } else
5777392e 5440 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5441 return 1;
5442
6aa8b732
AK		 5443 skip_emulated_instruction(vcpu);
5444 return 1;
5445}
5446
73aaf249
JK		 5447static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5448{
5449 return vcpu->arch.dr6;
5450}
5451
5452static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5453{
5454}
5455
81908bf4
PB		 5456static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5457{
5458 u32 cpu_based_vm_exec_control;
5459
5460 get_debugreg(vcpu->arch.db[0], 0);
5461 get_debugreg(vcpu->arch.db[1], 1);
5462 get_debugreg(vcpu->arch.db[2], 2);
5463 get_debugreg(vcpu->arch.db[3], 3);
5464 get_debugreg(vcpu->arch.dr6, 6);
5465 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5466
5467 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5468
5469 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5470 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5471 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5472}
5473
020df079
GN		 5474static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5475{
5476 vmcs_writel(GUEST_DR7, val);
5477}
5478
851ba692 5479static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5480{
06465c5a
AK		 5481 kvm_emulate_cpuid(vcpu);
5482 return 1;
6aa8b732
AK		 5483}
5484
851ba692 5485static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5486{
ad312c7c 5487 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 5488 struct msr_data msr_info;
6aa8b732 5489
609e36d3
PB		 5490 msr_info.index = ecx;
5491 msr_info.host_initiated = false;
5492 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 5493 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5494 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5495 return 1;
5496 }
5497
609e36d3 5498 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 5499
6aa8b732 5500 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB		 5501 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5502 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6aa8b732
AK		 5503 skip_emulated_instruction(vcpu);
5504 return 1;
5505}
5506
851ba692 5507static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5508{
8fe8ab46 5509 struct msr_data msr;
ad312c7c
ZX		 5510 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5511 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5512 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5513
8fe8ab46
WA		 5514 msr.data = data;
5515 msr.index = ecx;
5516 msr.host_initiated = false;
854e8bb1 5517 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5518 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5519 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5520 return 1;
5521 }
5522
59200273 5523 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5524 skip_emulated_instruction(vcpu);
5525 return 1;
5526}
5527
851ba692 5528static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5529{
3842d135 5530 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5531 return 1;
5532}
5533
851ba692 5534static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5535{
85f455f7
ED		 5536 u32 cpu_based_vm_exec_control;
5537
5538 /* clear pending irq */
5539 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5540 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5541 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5542
3842d135
AK		 5543 kvm_make_request(KVM_REQ_EVENT, vcpu);
5544
a26bf12a 5545 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 5546 return 1;
5547}
5548
851ba692 5549static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 5550{
d3bef15f 5551 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5552}
5553
851ba692 5554static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5555{
7aa81cc0
AL		 5556 kvm_emulate_hypercall(vcpu);
5557 return 1;
c21415e8
IM		 5558}
5559
ec25d5e6
GN		 5560static int handle_invd(struct kvm_vcpu *vcpu)
5561{
51d8b661 5562 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5563}
5564
851ba692 5565static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5566{
f9c617f6 5567 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5568
5569 kvm_mmu_invlpg(vcpu, exit_qualification);
5570 skip_emulated_instruction(vcpu);
5571 return 1;
5572}
5573
fee84b07
AK		 5574static int handle_rdpmc(struct kvm_vcpu *vcpu)
5575{
5576 int err;
5577
5578 err = kvm_rdpmc(vcpu);
5579 kvm_complete_insn_gp(vcpu, err);
5580
5581 return 1;
5582}
5583
851ba692 5584static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5585{
f5f48ee1 5586 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5587 return 1;
5588}
5589
2acf923e
DC		 5590static int handle_xsetbv(struct kvm_vcpu *vcpu)
5591{
5592 u64 new_bv = kvm_read_edx_eax(vcpu);
5593 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5594
5595 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5596 skip_emulated_instruction(vcpu);
5597 return 1;
5598}
5599
f53cd63c
WL		 5600static int handle_xsaves(struct kvm_vcpu *vcpu)
5601{
5602 skip_emulated_instruction(vcpu);
5603 WARN(1, "this should never happen\n");
5604 return 1;
5605}
5606
5607static int handle_xrstors(struct kvm_vcpu *vcpu)
5608{
5609 skip_emulated_instruction(vcpu);
5610 WARN(1, "this should never happen\n");
5611 return 1;
5612}
5613
851ba692 5614static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5615{
58fbbf26
KT		 5616 if (likely(fasteoi)) {
5617 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5618 int access_type, offset;
5619
5620 access_type = exit_qualification & APIC_ACCESS_TYPE;
5621 offset = exit_qualification & APIC_ACCESS_OFFSET;
5622 /*
5623 * Sane guest uses MOV to write EOI, with written value
5624 * not cared. So make a short-circuit here by avoiding
5625 * heavy instruction emulation.
5626 */
5627 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5628 (offset == APIC_EOI)) {
5629 kvm_lapic_set_eoi(vcpu);
5630 skip_emulated_instruction(vcpu);
5631 return 1;
5632 }
5633 }
51d8b661 5634 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5635}
5636
c7c9c56c
YZ		 5637static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5638{
5639 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5640 int vector = exit_qualification & 0xff;
5641
5642 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5643 kvm_apic_set_eoi_accelerated(vcpu, vector);
5644 return 1;
5645}
5646
83d4c286
YZ		 5647static int handle_apic_write(struct kvm_vcpu *vcpu)
5648{
5649 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5650 u32 offset = exit_qualification & 0xfff;
5651
5652 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5653 kvm_apic_write_nodecode(vcpu, offset);
5654 return 1;
5655}
5656
851ba692 5657static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5658{
60637aac 5659 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5660 unsigned long exit_qualification;
e269fb21
JK		 5661 bool has_error_code = false;
5662 u32 error_code = 0;
37817f29 5663 u16 tss_selector;
7f3d35fd 5664 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5665
5666 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5667 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5668 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5669
5670 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5671
5672 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5673 if (reason == TASK_SWITCH_GATE && idt_v) {
5674 switch (type) {
5675 case INTR_TYPE_NMI_INTR:
5676 vcpu->arch.nmi_injected = false;
654f06fc 5677 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5678 break;
5679 case INTR_TYPE_EXT_INTR:
66fd3f7f 5680 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5681 kvm_clear_interrupt_queue(vcpu);
5682 break;
5683 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5684 if (vmx->idt_vectoring_info &
5685 VECTORING_INFO_DELIVER_CODE_MASK) {
5686 has_error_code = true;
5687 error_code =
5688 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5689 }
5690 /* fall through */
64a7ec06
GN		 5691 case INTR_TYPE_SOFT_EXCEPTION:
5692 kvm_clear_exception_queue(vcpu);
5693 break;
5694 default:
5695 break;
5696 }
60637aac 5697 }
37817f29
IE		 5698 tss_selector = exit_qualification;
5699
64a7ec06
GN		 5700 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5701 type != INTR_TYPE_EXT_INTR &&
5702 type != INTR_TYPE_NMI_INTR))
5703 skip_emulated_instruction(vcpu);
5704
7f3d35fd
KW		 5705 if (kvm_task_switch(vcpu, tss_selector,
5706 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5707 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5708 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5709 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5710 vcpu->run->internal.ndata = 0;
42dbaa5a 5711 return 0;
acb54517 5712 }
42dbaa5a 5713
42dbaa5a
JK		 5714 /*
5715 * TODO: What about debug traps on tss switch?
5716 * Are we supposed to inject them and update dr6?
5717 */
5718
5719 return 1;
37817f29
IE		 5720}
5721
851ba692 5722static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5723{
f9c617f6 5724 unsigned long exit_qualification;
1439442c 5725 gpa_t gpa;
4f5982a5 5726 u32 error_code;
1439442c 5727 int gla_validity;
1439442c 5728
f9c617f6 5729 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5730
1439442c
SY		 5731 gla_validity = (exit_qualification >> 7) & 0x3;
5732 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5733 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5734 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5735 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5736 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5737 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5738 (long unsigned int)exit_qualification);
851ba692
AK		 5739 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5740 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5741 return 0;
1439442c
SY		 5742 }
5743
0be9c7a8
GN		 5744 /*
5745 * EPT violation happened while executing iret from NMI,
5746 * "blocked by NMI" bit has to be set before next VM entry.
5747 * There are errata that may cause this bit to not be set:
5748 * AAK134, BY25.
5749 */
bcd1c294
GN		 5750 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5751 cpu_has_virtual_nmis() &&
5752 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5753 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5754
1439442c 5755 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5756 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5757
5758 /* It is a write fault? */
81ed33e4 5759 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5760 /* It is a fetch fault? */
81ed33e4 5761 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5762 /* ept page table is present? */
81ed33e4 5763 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5764
25d92081
YZ		 5765 vcpu->arch.exit_qualification = exit_qualification;
5766
4f5982a5 5767 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5768}
5769
851ba692 5770static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5771{
f735d4af 5772 int ret;
68f89400
MT		 5773 gpa_t gpa;
5774
5775 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 5776 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
68c3b4d1 5777 skip_emulated_instruction(vcpu);
931c33b1 5778 trace_kvm_fast_mmio(gpa);
68c3b4d1
MT		 5779 return 1;
5780 }
68f89400 5781
ce88decf 5782 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5783 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5784 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5785 EMULATE_DONE;
f8f55942
XG		 5786
5787 if (unlikely(ret == RET_MMIO_PF_INVALID))
5788 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5789
b37fbea6 5790 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5791 return 1;
5792
5793 /* It is the real ept misconfig */
f735d4af 5794 WARN_ON(1);
68f89400 5795
851ba692
AK		 5796 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5797 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5798
5799 return 0;
5800}
5801
851ba692 5802static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5803{
5804 u32 cpu_based_vm_exec_control;
5805
5806 /* clear pending NMI */
5807 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5808 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5809 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5810 ++vcpu->stat.nmi_window_exits;
3842d135 5811 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5812
5813 return 1;
5814}
5815
80ced186 5816static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5817{
8b3079a5
AK		 5818 struct vcpu_vmx *vmx = to_vmx(vcpu);
5819 enum emulation_result err = EMULATE_DONE;
80ced186 5820 int ret = 1;
49e9d557
AK		 5821 u32 cpu_exec_ctrl;
5822 bool intr_window_requested;
b8405c18 5823 unsigned count = 130;
49e9d557
AK		 5824
5825 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5826 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5827
98eb2f8b 5828 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5829 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5830 return handle_interrupt_window(&vmx->vcpu);
5831
de87dcdd
AK		 5832 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5833 return 1;
5834
991eebf9 5835 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5836
ac0a48c3 5837 if (err == EMULATE_USER_EXIT) {
94452b9e 5838 ++vcpu->stat.mmio_exits;
80ced186
MG		 5839 ret = 0;
5840 goto out;
5841 }
1d5a4d9b 5842
de5f70e0
AK		 5843 if (err != EMULATE_DONE) {
5844 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5845 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5846 vcpu->run->internal.ndata = 0;
6d77dbfc 5847 return 0;
de5f70e0 5848 }
ea953ef0 5849
8d76c49e
GN		 5850 if (vcpu->arch.halt_request) {
5851 vcpu->arch.halt_request = 0;
5cb56059 5852 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5853 goto out;
5854 }
5855
ea953ef0 5856 if (signal_pending(current))
80ced186 5857 goto out;
ea953ef0
MG		 5858 if (need_resched())
5859 schedule();
5860 }
5861
80ced186
MG		 5862out:
5863 return ret;
ea953ef0
MG		 5864}
5865
b4a2d31d
RK		 5866static int __grow_ple_window(int val)
5867{
5868 if (ple_window_grow < 1)
5869 return ple_window;
5870
5871 val = min(val, ple_window_actual_max);
5872
5873 if (ple_window_grow < ple_window)
5874 val *= ple_window_grow;
5875 else
5876 val += ple_window_grow;
5877
5878 return val;
5879}
5880
5881static int __shrink_ple_window(int val, int modifier, int minimum)
5882{
5883 if (modifier < 1)
5884 return ple_window;
5885
5886 if (modifier < ple_window)
5887 val /= modifier;
5888 else
5889 val -= modifier;
5890
5891 return max(val, minimum);
5892}
5893
5894static void grow_ple_window(struct kvm_vcpu *vcpu)
5895{
5896 struct vcpu_vmx *vmx = to_vmx(vcpu);
5897 int old = vmx->ple_window;
5898
5899 vmx->ple_window = __grow_ple_window(old);
5900
5901 if (vmx->ple_window != old)
5902 vmx->ple_window_dirty = true;
7b46268d
RK		 5903
5904 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5905}
5906
5907static void shrink_ple_window(struct kvm_vcpu *vcpu)
5908{
5909 struct vcpu_vmx *vmx = to_vmx(vcpu);
5910 int old = vmx->ple_window;
5911
5912 vmx->ple_window = __shrink_ple_window(old,
5913 ple_window_shrink, ple_window);
5914
5915 if (vmx->ple_window != old)
5916 vmx->ple_window_dirty = true;
7b46268d
RK		 5917
5918 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5919}
5920
5921/*
5922 * ple_window_actual_max is computed to be one grow_ple_window() below
5923 * ple_window_max. (See __grow_ple_window for the reason.)
5924 * This prevents overflows, because ple_window_max is int.
5925 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5926 * this process.
5927 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5928 */
5929static void update_ple_window_actual_max(void)
5930{
5931 ple_window_actual_max =
5932 __shrink_ple_window(max(ple_window_max, ple_window),
5933 ple_window_grow, INT_MIN);
5934}
5935
f2c7648d
TC		 5936static __init int hardware_setup(void)
5937{
34a1cd60
TC		 5938 int r = -ENOMEM, i, msr;
5939
5940 rdmsrl_safe(MSR_EFER, &host_efer);
5941
5942 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5943 kvm_define_shared_msr(i, vmx_msr_index[i]);
5944
5945 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5946 if (!vmx_io_bitmap_a)
5947 return r;
5948
5949 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5950 if (!vmx_io_bitmap_b)
5951 goto out;
5952
5953 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5954 if (!vmx_msr_bitmap_legacy)
5955 goto out1;
5956
5957 vmx_msr_bitmap_legacy_x2apic =
5958 (unsigned long *)__get_free_page(GFP_KERNEL);
5959 if (!vmx_msr_bitmap_legacy_x2apic)
5960 goto out2;
5961
5962 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5963 if (!vmx_msr_bitmap_longmode)
5964 goto out3;
5965
5966 vmx_msr_bitmap_longmode_x2apic =
5967 (unsigned long *)__get_free_page(GFP_KERNEL);
5968 if (!vmx_msr_bitmap_longmode_x2apic)
5969 goto out4;
3af18d9c
WV		 5970
5971 if (nested) {
5972 vmx_msr_bitmap_nested =
5973 (unsigned long *)__get_free_page(GFP_KERNEL);
5974 if (!vmx_msr_bitmap_nested)
5975 goto out5;
5976 }
5977
34a1cd60
TC		 5978 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5979 if (!vmx_vmread_bitmap)
3af18d9c 5980 goto out6;
34a1cd60
TC		 5981
5982 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5983 if (!vmx_vmwrite_bitmap)
3af18d9c 5984 goto out7;
34a1cd60
TC		 5985
5986 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5987 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5988
5989 /*
5990 * Allow direct access to the PC debug port (it is often used for I/O
5991 * delays, but the vmexits simply slow things down).
5992 */
5993 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5994 clear_bit(0x80, vmx_io_bitmap_a);
5995
5996 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5997
5998 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5999 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 6000 if (nested)
6001 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 6002
34a1cd60
TC		 6003 if (setup_vmcs_config(&vmcs_config) < 0) {
6004 r = -EIO;
3af18d9c 6005 goto out8;
baa03522 6006 }
f2c7648d
TC		 6007
6008 if (boot_cpu_has(X86_FEATURE_NX))
6009 kvm_enable_efer_bits(EFER_NX);
6010
6011 if (!cpu_has_vmx_vpid())
6012 enable_vpid = 0;
6013 if (!cpu_has_vmx_shadow_vmcs())
6014 enable_shadow_vmcs = 0;
6015 if (enable_shadow_vmcs)
6016 init_vmcs_shadow_fields();
6017
6018 if (!cpu_has_vmx_ept() ||
6019 !cpu_has_vmx_ept_4levels()) {
6020 enable_ept = 0;
6021 enable_unrestricted_guest = 0;
6022 enable_ept_ad_bits = 0;
6023 }
6024
6025 if (!cpu_has_vmx_ept_ad_bits())
6026 enable_ept_ad_bits = 0;
6027
6028 if (!cpu_has_vmx_unrestricted_guest())
6029 enable_unrestricted_guest = 0;
6030
ad15a296 6031 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6032 flexpriority_enabled = 0;
6033
ad15a296
PB		 6034 /*
6035 * set_apic_access_page_addr() is used to reload apic access
6036 * page upon invalidation. No need to do anything if not
6037 * using the APIC_ACCESS_ADDR VMCS field.
6038 */
6039 if (!flexpriority_enabled)
f2c7648d 6040 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6041
6042 if (!cpu_has_vmx_tpr_shadow())
6043 kvm_x86_ops->update_cr8_intercept = NULL;
6044
6045 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6046 kvm_disable_largepages();
6047
6048 if (!cpu_has_vmx_ple())
6049 ple_gap = 0;
6050
6051 if (!cpu_has_vmx_apicv())
6052 enable_apicv = 0;
6053
6054 if (enable_apicv)
6055 kvm_x86_ops->update_cr8_intercept = NULL;
6056 else {
6057 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6058 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6059 kvm_x86_ops->deliver_posted_interrupt = NULL;
6060 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6061 }
6062
baa03522
TC		 6063 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6064 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6065 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6066 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6067 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6068 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6069 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6070
6071 memcpy(vmx_msr_bitmap_legacy_x2apic,
6072 vmx_msr_bitmap_legacy, PAGE_SIZE);
6073 memcpy(vmx_msr_bitmap_longmode_x2apic,
6074 vmx_msr_bitmap_longmode, PAGE_SIZE);
6075
04bb92e4
WL		 6076 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6077
baa03522
TC		 6078 if (enable_apicv) {
6079 for (msr = 0x800; msr <= 0x8ff; msr++)
6080 vmx_disable_intercept_msr_read_x2apic(msr);
6081
6082 /* According SDM, in x2apic mode, the whole id reg is used.
6083 * But in KVM, it only use the highest eight bits. Need to
6084 * intercept it */
6085 vmx_enable_intercept_msr_read_x2apic(0x802);
6086 /* TMCCT */
6087 vmx_enable_intercept_msr_read_x2apic(0x839);
6088 /* TPR */
6089 vmx_disable_intercept_msr_write_x2apic(0x808);
6090 /* EOI */
6091 vmx_disable_intercept_msr_write_x2apic(0x80b);
6092 /* SELF-IPI */
6093 vmx_disable_intercept_msr_write_x2apic(0x83f);
6094 }
6095
6096 if (enable_ept) {
6097 kvm_mmu_set_mask_ptes(0ull,
6098 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6099 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6100 0ull, VMX_EPT_EXECUTABLE_MASK);
6101 ept_set_mmio_spte_mask();
6102 kvm_enable_tdp();
6103 } else
6104 kvm_disable_tdp();
6105
6106 update_ple_window_actual_max();
6107
843e4330
KH		 6108 /*
6109 * Only enable PML when hardware supports PML feature, and both EPT
6110 * and EPT A/D bit features are enabled -- PML depends on them to work.
6111 */
6112 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6113 enable_pml = 0;
6114
6115 if (!enable_pml) {
6116 kvm_x86_ops->slot_enable_log_dirty = NULL;
6117 kvm_x86_ops->slot_disable_log_dirty = NULL;
6118 kvm_x86_ops->flush_log_dirty = NULL;
6119 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6120 }
6121
f2c7648d 6122 return alloc_kvm_area();
34a1cd60 6123
3af18d9c 6124out8:
34a1cd60 6125 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6126out7:
34a1cd60 6127 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6128out6:
6129 if (nested)
6130 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6131out5:
6132 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6133out4:
6134 free_page((unsigned long)vmx_msr_bitmap_longmode);
6135out3:
6136 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6137out2:
6138 free_page((unsigned long)vmx_msr_bitmap_legacy);
6139out1:
6140 free_page((unsigned long)vmx_io_bitmap_b);
6141out:
6142 free_page((unsigned long)vmx_io_bitmap_a);
6143
6144 return r;
f2c7648d
TC		 6145}
6146
6147static __exit void hardware_unsetup(void)
6148{
34a1cd60
TC		 6149 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6150 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6151 free_page((unsigned long)vmx_msr_bitmap_legacy);
6152 free_page((unsigned long)vmx_msr_bitmap_longmode);
6153 free_page((unsigned long)vmx_io_bitmap_b);
6154 free_page((unsigned long)vmx_io_bitmap_a);
6155 free_page((unsigned long)vmx_vmwrite_bitmap);
6156 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6157 if (nested)
6158 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6159
f2c7648d
TC		 6160 free_kvm_area();
6161}
6162
4b8d54f9
ZE		 6163/*
6164 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6165 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6166 */
9fb41ba8 6167static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6168{
b4a2d31d
RK		 6169 if (ple_gap)
6170 grow_ple_window(vcpu);
6171
4b8d54f9
ZE		 6172 skip_emulated_instruction(vcpu);
6173 kvm_vcpu_on_spin(vcpu);
6174
6175 return 1;
6176}
6177
87c00572 6178static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6179{
87c00572 6180 skip_emulated_instruction(vcpu);
59708670
SY		 6181 return 1;
6182}
6183
87c00572
GS		 6184static int handle_mwait(struct kvm_vcpu *vcpu)
6185{
6186 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6187 return handle_nop(vcpu);
6188}
6189
5f3d45e7
MD		 6190static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6191{
6192 return 1;
6193}
6194
87c00572
GS		 6195static int handle_monitor(struct kvm_vcpu *vcpu)
6196{
6197 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6198 return handle_nop(vcpu);
6199}
6200
ff2f6fe9
NHE		 6201/*
6202 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6203 * We could reuse a single VMCS for all the L2 guests, but we also want the
6204 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6205 * allows keeping them loaded on the processor, and in the future will allow
6206 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6207 * every entry if they never change.
6208 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6209 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6210 *
6211 * The following functions allocate and free a vmcs02 in this pool.
6212 */
6213
6214/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6215static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6216{
6217 struct vmcs02_list *item;
6218 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6219 if (item->vmptr == vmx->nested.current_vmptr) {
6220 list_move(&item->list, &vmx->nested.vmcs02_pool);
6221 return &item->vmcs02;
6222 }
6223
6224 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6225 /* Recycle the least recently used VMCS. */
6226 item = list_entry(vmx->nested.vmcs02_pool.prev,
6227 struct vmcs02_list, list);
6228 item->vmptr = vmx->nested.current_vmptr;
6229 list_move(&item->list, &vmx->nested.vmcs02_pool);
6230 return &item->vmcs02;
6231 }
6232
6233 /* Create a new VMCS */
0fa24ce3 6234 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6235 if (!item)
6236 return NULL;
6237 item->vmcs02.vmcs = alloc_vmcs();
6238 if (!item->vmcs02.vmcs) {
6239 kfree(item);
6240 return NULL;
6241 }
6242 loaded_vmcs_init(&item->vmcs02);
6243 item->vmptr = vmx->nested.current_vmptr;
6244 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6245 vmx->nested.vmcs02_num++;
6246 return &item->vmcs02;
6247}
6248
6249/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6250static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6251{
6252 struct vmcs02_list *item;
6253 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6254 if (item->vmptr == vmptr) {
6255 free_loaded_vmcs(&item->vmcs02);
6256 list_del(&item->list);
6257 kfree(item);
6258 vmx->nested.vmcs02_num--;
6259 return;
6260 }
6261}
6262
6263/*
6264 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6265 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6266 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6267 */
6268static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6269{
6270 struct vmcs02_list *item, *n;
4fa7734c
PB		 6271
6272 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6273 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6274 /*
6275 * Something will leak if the above WARN triggers. Better than
6276 * a use-after-free.
6277 */
6278 if (vmx->loaded_vmcs == &item->vmcs02)
6279 continue;
6280
6281 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6282 list_del(&item->list);
6283 kfree(item);
4fa7734c 6284 vmx->nested.vmcs02_num--;
ff2f6fe9 6285 }
ff2f6fe9
NHE		 6286}
6287
0658fbaa
ACL		 6288/*
6289 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6290 * set the success or error code of an emulated VMX instruction, as specified
6291 * by Vol 2B, VMX Instruction Reference, "Conventions".
6292 */
6293static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6294{
6295 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6296 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6297 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6298}
6299
6300static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6301{
6302 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6303 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6304 X86_EFLAGS_SF | X86_EFLAGS_OF))
6305 | X86_EFLAGS_CF);
6306}
6307
145c28dd 6308static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6309 u32 vm_instruction_error)
6310{
6311 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6312 /*
6313 * failValid writes the error number to the current VMCS, which
6314 * can't be done there isn't a current VMCS.
6315 */
6316 nested_vmx_failInvalid(vcpu);
6317 return;
6318 }
6319 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6320 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6321 X86_EFLAGS_SF | X86_EFLAGS_OF))
6322 | X86_EFLAGS_ZF);
6323 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6324 /*
6325 * We don't need to force a shadow sync because
6326 * VM_INSTRUCTION_ERROR is not shadowed
6327 */
6328}
145c28dd 6329
ff651cb6
WV		 6330static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6331{
6332 /* TODO: not to reset guest simply here. */
6333 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6334 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6335}
6336
f4124500
JK		 6337static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6338{
6339 struct vcpu_vmx *vmx =
6340 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6341
6342 vmx->nested.preemption_timer_expired = true;
6343 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6344 kvm_vcpu_kick(&vmx->vcpu);
6345
6346 return HRTIMER_NORESTART;
6347}
6348
19677e32
BD		 6349/*
6350 * Decode the memory-address operand of a vmx instruction, as recorded on an
6351 * exit caused by such an instruction (run by a guest hypervisor).
6352 * On success, returns 0. When the operand is invalid, returns 1 and throws
6353 * #UD or #GP.
6354 */
6355static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6356 unsigned long exit_qualification,
f9eb4af6 6357 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6358{
f9eb4af6
EK		 6359 gva_t off;
6360 bool exn;
6361 struct kvm_segment s;
6362
19677e32
BD		 6363 /*
6364 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6365 * Execution", on an exit, vmx_instruction_info holds most of the
6366 * addressing components of the operand. Only the displacement part
6367 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6368 * For how an actual address is calculated from all these components,
6369 * refer to Vol. 1, "Operand Addressing".
6370 */
6371 int scaling = vmx_instruction_info & 3;
6372 int addr_size = (vmx_instruction_info >> 7) & 7;
6373 bool is_reg = vmx_instruction_info & (1u << 10);
6374 int seg_reg = (vmx_instruction_info >> 15) & 7;
6375 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6376 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6377 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6378 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6379
6380 if (is_reg) {
6381 kvm_queue_exception(vcpu, UD_VECTOR);
6382 return 1;
6383 }
6384
6385 /* Addr = segment_base + offset */
6386 /* offset = base + [index * scale] + displacement */
f9eb4af6 6387 off = exit_qualification; /* holds the displacement */
19677e32 6388 if (base_is_valid)
f9eb4af6 6389 off += kvm_register_read(vcpu, base_reg);
19677e32 6390 if (index_is_valid)
f9eb4af6
EK		 6391 off += kvm_register_read(vcpu, index_reg)<<scaling;
6392 vmx_get_segment(vcpu, &s, seg_reg);
6393 *ret = s.base + off;
19677e32
BD		 6394
6395 if (addr_size == 1) /* 32 bit */
6396 *ret &= 0xffffffff;
6397
f9eb4af6
EK		 6398 /* Checks for #GP/#SS exceptions. */
6399 exn = false;
6400 if (is_protmode(vcpu)) {
6401 /* Protected mode: apply checks for segment validity in the
6402 * following order:
6403 * - segment type check (#GP(0) may be thrown)
6404 * - usability check (#GP(0)/#SS(0))
6405 * - limit check (#GP(0)/#SS(0))
6406 */
6407 if (wr)
6408 /* #GP(0) if the destination operand is located in a
6409 * read-only data segment or any code segment.
6410 */
6411 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6412 else
6413 /* #GP(0) if the source operand is located in an
6414 * execute-only code segment
6415 */
6416 exn = ((s.type & 0xa) == 8);
6417 }
6418 if (exn) {
6419 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6420 return 1;
6421 }
6422 if (is_long_mode(vcpu)) {
6423 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6424 * non-canonical form. This is an only check for long mode.
6425 */
6426 exn = is_noncanonical_address(*ret);
6427 } else if (is_protmode(vcpu)) {
6428 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6429 */
6430 exn = (s.unusable != 0);
6431 /* Protected mode: #GP(0)/#SS(0) if the memory
6432 * operand is outside the segment limit.
6433 */
6434 exn = exn || (off + sizeof(u64) > s.limit);
6435 }
6436 if (exn) {
6437 kvm_queue_exception_e(vcpu,
6438 seg_reg == VCPU_SREG_SS ?
6439 SS_VECTOR : GP_VECTOR,
6440 0);
6441 return 1;
6442 }
6443
19677e32
BD		 6444 return 0;
6445}
6446
3573e22c
BD		 6447/*
6448 * This function performs the various checks including
6449 * - if it's 4KB aligned
6450 * - No bits beyond the physical address width are set
6451 * - Returns 0 on success or else 1
4291b588 6452 * (Intel SDM Section 30.3)
3573e22c 6453 */
4291b588
BD		 6454static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6455 gpa_t *vmpointer)
3573e22c
BD		 6456{
6457 gva_t gva;
6458 gpa_t vmptr;
6459 struct x86_exception e;
6460 struct page *page;
6461 struct vcpu_vmx *vmx = to_vmx(vcpu);
6462 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6463
6464 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 6465 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD		 6466 return 1;
6467
6468 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6469 sizeof(vmptr), &e)) {
6470 kvm_inject_page_fault(vcpu, &e);
6471 return 1;
6472 }
6473
6474 switch (exit_reason) {
6475 case EXIT_REASON_VMON:
6476 /*
6477 * SDM 3: 24.11.5
6478 * The first 4 bytes of VMXON region contain the supported
6479 * VMCS revision identifier
6480 *
6481 * Note - IA32_VMX_BASIC[48] will never be 1
6482 * for the nested case;
6483 * which replaces physical address width with 32
6484 *
6485 */
bc39c4db 6486 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6487 nested_vmx_failInvalid(vcpu);
6488 skip_emulated_instruction(vcpu);
6489 return 1;
6490 }
6491
6492 page = nested_get_page(vcpu, vmptr);
6493 if (page == NULL ||
6494 *(u32 *)kmap(page) != VMCS12_REVISION) {
6495 nested_vmx_failInvalid(vcpu);
6496 kunmap(page);
6497 skip_emulated_instruction(vcpu);
6498 return 1;
6499 }
6500 kunmap(page);
6501 vmx->nested.vmxon_ptr = vmptr;
6502 break;
4291b588 6503 case EXIT_REASON_VMCLEAR:
bc39c4db 6504 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6505 nested_vmx_failValid(vcpu,
6506 VMXERR_VMCLEAR_INVALID_ADDRESS);
6507 skip_emulated_instruction(vcpu);
6508 return 1;
6509 }
6510
6511 if (vmptr == vmx->nested.vmxon_ptr) {
6512 nested_vmx_failValid(vcpu,
6513 VMXERR_VMCLEAR_VMXON_POINTER);
6514 skip_emulated_instruction(vcpu);
6515 return 1;
6516 }
6517 break;
6518 case EXIT_REASON_VMPTRLD:
bc39c4db 6519 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6520 nested_vmx_failValid(vcpu,
6521 VMXERR_VMPTRLD_INVALID_ADDRESS);
6522 skip_emulated_instruction(vcpu);
6523 return 1;
6524 }
3573e22c 6525
4291b588
BD		 6526 if (vmptr == vmx->nested.vmxon_ptr) {
6527 nested_vmx_failValid(vcpu,
6528 VMXERR_VMCLEAR_VMXON_POINTER);
6529 skip_emulated_instruction(vcpu);
6530 return 1;
6531 }
6532 break;
3573e22c
BD		 6533 default:
6534 return 1; /* shouldn't happen */
6535 }
6536
4291b588
BD		 6537 if (vmpointer)
6538 *vmpointer = vmptr;
3573e22c
BD		 6539 return 0;
6540}
6541
ec378aee
NHE		 6542/*
6543 * Emulate the VMXON instruction.
6544 * Currently, we just remember that VMX is active, and do not save or even
6545 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6546 * do not currently need to store anything in that guest-allocated memory
6547 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6548 * argument is different from the VMXON pointer (which the spec says they do).
6549 */
6550static int handle_vmon(struct kvm_vcpu *vcpu)
6551{
6552 struct kvm_segment cs;
6553 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6554 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6555 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6556 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6557
6558 /* The Intel VMX Instruction Reference lists a bunch of bits that
6559 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6560 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6561 * Otherwise, we should fail with #UD. We test these now:
6562 */
6563 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6564 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6565 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6566 kvm_queue_exception(vcpu, UD_VECTOR);
6567 return 1;
6568 }
6569
6570 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6571 if (is_long_mode(vcpu) && !cs.l) {
6572 kvm_queue_exception(vcpu, UD_VECTOR);
6573 return 1;
6574 }
6575
6576 if (vmx_get_cpl(vcpu)) {
6577 kvm_inject_gp(vcpu, 0);
6578 return 1;
6579 }
3573e22c 6580
4291b588 6581 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6582 return 1;
6583
145c28dd
AG		 6584 if (vmx->nested.vmxon) {
6585 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6586 skip_emulated_instruction(vcpu);
6587 return 1;
6588 }
b3897a49
NHE		 6589
6590 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6591 != VMXON_NEEDED_FEATURES) {
6592 kvm_inject_gp(vcpu, 0);
6593 return 1;
6594 }
6595
8de48833
AG		 6596 if (enable_shadow_vmcs) {
6597 shadow_vmcs = alloc_vmcs();
6598 if (!shadow_vmcs)
6599 return -ENOMEM;
6600 /* mark vmcs as shadow */
6601 shadow_vmcs->revision_id |= (1u << 31);
6602 /* init shadow vmcs */
6603 vmcs_clear(shadow_vmcs);
6604 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6605 }
ec378aee 6606
ff2f6fe9
NHE		 6607 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6608 vmx->nested.vmcs02_num = 0;
6609
f4124500
JK		 6610 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6611 HRTIMER_MODE_REL);
6612 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6613
ec378aee
NHE		 6614 vmx->nested.vmxon = true;
6615
6616 skip_emulated_instruction(vcpu);
a25eb114 6617 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6618 return 1;
6619}
6620
6621/*
6622 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6623 * for running VMX instructions (except VMXON, whose prerequisites are
6624 * slightly different). It also specifies what exception to inject otherwise.
6625 */
6626static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6627{
6628 struct kvm_segment cs;
6629 struct vcpu_vmx *vmx = to_vmx(vcpu);
6630
6631 if (!vmx->nested.vmxon) {
6632 kvm_queue_exception(vcpu, UD_VECTOR);
6633 return 0;
6634 }
6635
6636 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6637 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6638 (is_long_mode(vcpu) && !cs.l)) {
6639 kvm_queue_exception(vcpu, UD_VECTOR);
6640 return 0;
6641 }
6642
6643 if (vmx_get_cpl(vcpu)) {
6644 kvm_inject_gp(vcpu, 0);
6645 return 0;
6646 }
6647
6648 return 1;
6649}
6650
e7953d7f
AG		 6651static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6652{
9a2a05b9
PB		 6653 if (vmx->nested.current_vmptr == -1ull)
6654 return;
6655
6656 /* current_vmptr and current_vmcs12 are always set/reset together */
6657 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6658 return;
6659
012f83cb 6660 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6661 /* copy to memory all shadowed fields in case
6662 they were modified */
6663 copy_shadow_to_vmcs12(vmx);
6664 vmx->nested.sync_shadow_vmcs = false;
7ec36296
XG		 6665 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6666 SECONDARY_EXEC_SHADOW_VMCS);
9a2a05b9 6667 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6668 }
705699a1 6669 vmx->nested.posted_intr_nv = -1;
e7953d7f
AG		 6670 kunmap(vmx->nested.current_vmcs12_page);
6671 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6672 vmx->nested.current_vmptr = -1ull;
6673 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6674}
6675
ec378aee
NHE		 6676/*
6677 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6678 * just stops using VMX.
6679 */
6680static void free_nested(struct vcpu_vmx *vmx)
6681{
6682 if (!vmx->nested.vmxon)
6683 return;
9a2a05b9 6684
ec378aee 6685 vmx->nested.vmxon = false;
9a2a05b9 6686 nested_release_vmcs12(vmx);
e7953d7f
AG		 6687 if (enable_shadow_vmcs)
6688 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6689 /* Unpin physical memory we referred to in current vmcs02 */
6690 if (vmx->nested.apic_access_page) {
6691 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6692 vmx->nested.apic_access_page = NULL;
fe3ef05c 6693 }
a7c0b07d
WL		 6694 if (vmx->nested.virtual_apic_page) {
6695 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6696 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6697 }
705699a1
WV		 6698 if (vmx->nested.pi_desc_page) {
6699 kunmap(vmx->nested.pi_desc_page);
6700 nested_release_page(vmx->nested.pi_desc_page);
6701 vmx->nested.pi_desc_page = NULL;
6702 vmx->nested.pi_desc = NULL;
6703 }
ff2f6fe9
NHE		 6704
6705 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6706}
6707
6708/* Emulate the VMXOFF instruction */
6709static int handle_vmoff(struct kvm_vcpu *vcpu)
6710{
6711 if (!nested_vmx_check_permission(vcpu))
6712 return 1;
6713 free_nested(to_vmx(vcpu));
6714 skip_emulated_instruction(vcpu);
a25eb114 6715 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6716 return 1;
6717}
6718
27d6c865
NHE		 6719/* Emulate the VMCLEAR instruction */
6720static int handle_vmclear(struct kvm_vcpu *vcpu)
6721{
6722 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6723 gpa_t vmptr;
6724 struct vmcs12 *vmcs12;
6725 struct page *page;
27d6c865
NHE		 6726
6727 if (!nested_vmx_check_permission(vcpu))
6728 return 1;
6729
4291b588 6730 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6731 return 1;
27d6c865 6732
9a2a05b9 6733 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6734 nested_release_vmcs12(vmx);
27d6c865
NHE		 6735
6736 page = nested_get_page(vcpu, vmptr);
6737 if (page == NULL) {
6738 /*
6739 * For accurate processor emulation, VMCLEAR beyond available
6740 * physical memory should do nothing at all. However, it is
6741 * possible that a nested vmx bug, not a guest hypervisor bug,
6742 * resulted in this case, so let's shut down before doing any
6743 * more damage:
6744 */
6745 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6746 return 1;
6747 }
6748 vmcs12 = kmap(page);
6749 vmcs12->launch_state = 0;
6750 kunmap(page);
6751 nested_release_page(page);
6752
6753 nested_free_vmcs02(vmx, vmptr);
6754
6755 skip_emulated_instruction(vcpu);
6756 nested_vmx_succeed(vcpu);
6757 return 1;
6758}
6759
cd232ad0
NHE		 6760static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6761
6762/* Emulate the VMLAUNCH instruction */
6763static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6764{
6765 return nested_vmx_run(vcpu, true);
6766}
6767
6768/* Emulate the VMRESUME instruction */
6769static int handle_vmresume(struct kvm_vcpu *vcpu)
6770{
6771
6772 return nested_vmx_run(vcpu, false);
6773}
6774
49f705c5
NHE		 6775enum vmcs_field_type {
6776 VMCS_FIELD_TYPE_U16 = 0,
6777 VMCS_FIELD_TYPE_U64 = 1,
6778 VMCS_FIELD_TYPE_U32 = 2,
6779 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6780};
6781
6782static inline int vmcs_field_type(unsigned long field)
6783{
6784 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6785 return VMCS_FIELD_TYPE_U32;
6786 return (field >> 13) & 0x3 ;
6787}
6788
6789static inline int vmcs_field_readonly(unsigned long field)
6790{
6791 return (((field >> 10) & 0x3) == 1);
6792}
6793
6794/*
6795 * Read a vmcs12 field. Since these can have varying lengths and we return
6796 * one type, we chose the biggest type (u64) and zero-extend the return value
6797 * to that size. Note that the caller, handle_vmread, might need to use only
6798 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6799 * 64-bit fields are to be returned).
6800 */
a2ae9df7
PB		 6801static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6802 unsigned long field, u64 *ret)
49f705c5
NHE		 6803{
6804 short offset = vmcs_field_to_offset(field);
6805 char *p;
6806
6807 if (offset < 0)
a2ae9df7 6808 return offset;
49f705c5
NHE		 6809
6810 p = ((char *)(get_vmcs12(vcpu))) + offset;
6811
6812 switch (vmcs_field_type(field)) {
6813 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6814 *ret = *((natural_width *)p);
a2ae9df7 6815 return 0;
49f705c5
NHE		 6816 case VMCS_FIELD_TYPE_U16:
6817 *ret = *((u16 *)p);
a2ae9df7 6818 return 0;
49f705c5
NHE		 6819 case VMCS_FIELD_TYPE_U32:
6820 *ret = *((u32 *)p);
a2ae9df7 6821 return 0;
49f705c5
NHE		 6822 case VMCS_FIELD_TYPE_U64:
6823 *ret = *((u64 *)p);
a2ae9df7 6824 return 0;
49f705c5 6825 default:
a2ae9df7
PB		 6826 WARN_ON(1);
6827 return -ENOENT;
49f705c5
NHE		 6828 }
6829}
6830
20b97fea 6831
a2ae9df7
PB		 6832static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6833 unsigned long field, u64 field_value){
20b97fea
AG		 6834 short offset = vmcs_field_to_offset(field);
6835 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6836 if (offset < 0)
a2ae9df7 6837 return offset;
20b97fea
AG		 6838
6839 switch (vmcs_field_type(field)) {
6840 case VMCS_FIELD_TYPE_U16:
6841 *(u16 *)p = field_value;
a2ae9df7 6842 return 0;
20b97fea
AG		 6843 case VMCS_FIELD_TYPE_U32:
6844 *(u32 *)p = field_value;
a2ae9df7 6845 return 0;
20b97fea
AG		 6846 case VMCS_FIELD_TYPE_U64:
6847 *(u64 *)p = field_value;
a2ae9df7 6848 return 0;
20b97fea
AG		 6849 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6850 *(natural_width *)p = field_value;
a2ae9df7 6851 return 0;
20b97fea 6852 default:
a2ae9df7
PB		 6853 WARN_ON(1);
6854 return -ENOENT;
20b97fea
AG		 6855 }
6856
6857}
6858
16f5b903
AG		 6859static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6860{
6861 int i;
6862 unsigned long field;
6863 u64 field_value;
6864 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6865 const unsigned long *fields = shadow_read_write_fields;
6866 const int num_fields = max_shadow_read_write_fields;
16f5b903 6867
282da870
JK		 6868 preempt_disable();
6869
16f5b903
AG		 6870 vmcs_load(shadow_vmcs);
6871
6872 for (i = 0; i < num_fields; i++) {
6873 field = fields[i];
6874 switch (vmcs_field_type(field)) {
6875 case VMCS_FIELD_TYPE_U16:
6876 field_value = vmcs_read16(field);
6877 break;
6878 case VMCS_FIELD_TYPE_U32:
6879 field_value = vmcs_read32(field);
6880 break;
6881 case VMCS_FIELD_TYPE_U64:
6882 field_value = vmcs_read64(field);
6883 break;
6884 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6885 field_value = vmcs_readl(field);
6886 break;
a2ae9df7
PB		 6887 default:
6888 WARN_ON(1);
6889 continue;
16f5b903
AG		 6890 }
6891 vmcs12_write_any(&vmx->vcpu, field, field_value);
6892 }
6893
6894 vmcs_clear(shadow_vmcs);
6895 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6896
6897 preempt_enable();
16f5b903
AG		 6898}
6899
c3114420
AG		 6900static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6901{
c2bae893
MK		 6902 const unsigned long *fields[] = {
6903 shadow_read_write_fields,
6904 shadow_read_only_fields
c3114420 6905 };
c2bae893 6906 const int max_fields[] = {
c3114420
AG		 6907 max_shadow_read_write_fields,
6908 max_shadow_read_only_fields
6909 };
6910 int i, q;
6911 unsigned long field;
6912 u64 field_value = 0;
6913 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6914
6915 vmcs_load(shadow_vmcs);
6916
c2bae893 6917 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6918 for (i = 0; i < max_fields[q]; i++) {
6919 field = fields[q][i];
6920 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6921
6922 switch (vmcs_field_type(field)) {
6923 case VMCS_FIELD_TYPE_U16:
6924 vmcs_write16(field, (u16)field_value);
6925 break;
6926 case VMCS_FIELD_TYPE_U32:
6927 vmcs_write32(field, (u32)field_value);
6928 break;
6929 case VMCS_FIELD_TYPE_U64:
6930 vmcs_write64(field, (u64)field_value);
6931 break;
6932 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6933 vmcs_writel(field, (long)field_value);
6934 break;
a2ae9df7
PB		 6935 default:
6936 WARN_ON(1);
6937 break;
c3114420
AG		 6938 }
6939 }
6940 }
6941
6942 vmcs_clear(shadow_vmcs);
6943 vmcs_load(vmx->loaded_vmcs->vmcs);
6944}
6945
49f705c5
NHE		 6946/*
6947 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6948 * used before) all generate the same failure when it is missing.
6949 */
6950static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6951{
6952 struct vcpu_vmx *vmx = to_vmx(vcpu);
6953 if (vmx->nested.current_vmptr == -1ull) {
6954 nested_vmx_failInvalid(vcpu);
6955 skip_emulated_instruction(vcpu);
6956 return 0;
6957 }
6958 return 1;
6959}
6960
6961static int handle_vmread(struct kvm_vcpu *vcpu)
6962{
6963 unsigned long field;
6964 u64 field_value;
6965 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6966 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6967 gva_t gva = 0;
6968
6969 if (!nested_vmx_check_permission(vcpu) ||
6970 !nested_vmx_check_vmcs12(vcpu))
6971 return 1;
6972
6973 /* Decode instruction info and find the field to read */
27e6fb5d 6974 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6975 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6976 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6977 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6978 skip_emulated_instruction(vcpu);
6979 return 1;
6980 }
6981 /*
6982 * Now copy part of this value to register or memory, as requested.
6983 * Note that the number of bits actually copied is 32 or 64 depending
6984 * on the guest's mode (32 or 64 bit), not on the given field's length.
6985 */
6986 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6987 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6988 field_value);
6989 } else {
6990 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 6991 vmx_instruction_info, true, &gva))
49f705c5
NHE		 6992 return 1;
6993 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6994 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6995 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6996 }
6997
6998 nested_vmx_succeed(vcpu);
6999 skip_emulated_instruction(vcpu);
7000 return 1;
7001}
7002
7003
7004static int handle_vmwrite(struct kvm_vcpu *vcpu)
7005{
7006 unsigned long field;
7007 gva_t gva;
7008 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7009 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 7010 /* The value to write might be 32 or 64 bits, depending on L1's long
7011 * mode, and eventually we need to write that into a field of several
7012 * possible lengths. The code below first zero-extends the value to 64
7013 * bit (field_value), and then copies only the approriate number of
7014 * bits into the vmcs12 field.
7015 */
7016 u64 field_value = 0;
7017 struct x86_exception e;
7018
7019 if (!nested_vmx_check_permission(vcpu) ||
7020 !nested_vmx_check_vmcs12(vcpu))
7021 return 1;
7022
7023 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7024 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 7025 (((vmx_instruction_info) >> 3) & 0xf));
7026 else {
7027 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7028 vmx_instruction_info, false, &gva))
49f705c5
NHE		 7029 return 1;
7030 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7031 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 7032 kvm_inject_page_fault(vcpu, &e);
7033 return 1;
7034 }
7035 }
7036
7037
27e6fb5d 7038 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 7039 if (vmcs_field_readonly(field)) {
7040 nested_vmx_failValid(vcpu,
7041 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7042 skip_emulated_instruction(vcpu);
7043 return 1;
7044 }
7045
a2ae9df7 7046 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 7047 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7048 skip_emulated_instruction(vcpu);
7049 return 1;
7050 }
7051
7052 nested_vmx_succeed(vcpu);
7053 skip_emulated_instruction(vcpu);
7054 return 1;
7055}
7056
63846663
NHE		 7057/* Emulate the VMPTRLD instruction */
7058static int handle_vmptrld(struct kvm_vcpu *vcpu)
7059{
7060 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7061 gpa_t vmptr;
63846663
NHE		 7062
7063 if (!nested_vmx_check_permission(vcpu))
7064 return 1;
7065
4291b588 7066 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 7067 return 1;
63846663
NHE		 7068
7069 if (vmx->nested.current_vmptr != vmptr) {
7070 struct vmcs12 *new_vmcs12;
7071 struct page *page;
7072 page = nested_get_page(vcpu, vmptr);
7073 if (page == NULL) {
7074 nested_vmx_failInvalid(vcpu);
7075 skip_emulated_instruction(vcpu);
7076 return 1;
7077 }
7078 new_vmcs12 = kmap(page);
7079 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7080 kunmap(page);
7081 nested_release_page_clean(page);
7082 nested_vmx_failValid(vcpu,
7083 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7084 skip_emulated_instruction(vcpu);
7085 return 1;
7086 }
63846663 7087
9a2a05b9 7088 nested_release_vmcs12(vmx);
63846663
NHE		 7089 vmx->nested.current_vmptr = vmptr;
7090 vmx->nested.current_vmcs12 = new_vmcs12;
7091 vmx->nested.current_vmcs12_page = page;
012f83cb 7092 if (enable_shadow_vmcs) {
7ec36296
XG		 7093 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7094 SECONDARY_EXEC_SHADOW_VMCS);
8a1b9dd0
AG		 7095 vmcs_write64(VMCS_LINK_POINTER,
7096 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 7097 vmx->nested.sync_shadow_vmcs = true;
7098 }
63846663
NHE		 7099 }
7100
7101 nested_vmx_succeed(vcpu);
7102 skip_emulated_instruction(vcpu);
7103 return 1;
7104}
7105
6a4d7550
NHE		 7106/* Emulate the VMPTRST instruction */
7107static int handle_vmptrst(struct kvm_vcpu *vcpu)
7108{
7109 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7110 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7111 gva_t vmcs_gva;
7112 struct x86_exception e;
7113
7114 if (!nested_vmx_check_permission(vcpu))
7115 return 1;
7116
7117 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7118 vmx_instruction_info, true, &vmcs_gva))
6a4d7550
NHE		 7119 return 1;
7120 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7121 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7122 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7123 sizeof(u64), &e)) {
7124 kvm_inject_page_fault(vcpu, &e);
7125 return 1;
7126 }
7127 nested_vmx_succeed(vcpu);
7128 skip_emulated_instruction(vcpu);
7129 return 1;
7130}
7131
bfd0a56b
NHE		 7132/* Emulate the INVEPT instruction */
7133static int handle_invept(struct kvm_vcpu *vcpu)
7134{
b9c237bb 7135 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7136 u32 vmx_instruction_info, types;
7137 unsigned long type;
7138 gva_t gva;
7139 struct x86_exception e;
7140 struct {
7141 u64 eptp, gpa;
7142 } operand;
bfd0a56b 7143
b9c237bb
WV		 7144 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7145 SECONDARY_EXEC_ENABLE_EPT) ||
7146 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7147 kvm_queue_exception(vcpu, UD_VECTOR);
7148 return 1;
7149 }
7150
7151 if (!nested_vmx_check_permission(vcpu))
7152 return 1;
7153
7154 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7155 kvm_queue_exception(vcpu, UD_VECTOR);
7156 return 1;
7157 }
7158
7159 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7160 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7161
b9c237bb 7162 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7163
7164 if (!(types & (1UL << type))) {
7165 nested_vmx_failValid(vcpu,
7166 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7167 return 1;
7168 }
7169
7170 /* According to the Intel VMX instruction reference, the memory
7171 * operand is read even if it isn't needed (e.g., for type==global)
7172 */
7173 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7174 vmx_instruction_info, false, &gva))
bfd0a56b
NHE		 7175 return 1;
7176 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7177 sizeof(operand), &e)) {
7178 kvm_inject_page_fault(vcpu, &e);
7179 return 1;
7180 }
7181
7182 switch (type) {
bfd0a56b
NHE		 7183 case VMX_EPT_EXTENT_GLOBAL:
7184 kvm_mmu_sync_roots(vcpu);
77c3913b 7185 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7186 nested_vmx_succeed(vcpu);
7187 break;
7188 default:
4b855078 7189 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7190 BUG_ON(1);
7191 break;
7192 }
7193
7194 skip_emulated_instruction(vcpu);
7195 return 1;
7196}
7197
a642fc30
PM		 7198static int handle_invvpid(struct kvm_vcpu *vcpu)
7199{
7200 kvm_queue_exception(vcpu, UD_VECTOR);
7201 return 1;
7202}
7203
843e4330
KH		 7204static int handle_pml_full(struct kvm_vcpu *vcpu)
7205{
7206 unsigned long exit_qualification;
7207
7208 trace_kvm_pml_full(vcpu->vcpu_id);
7209
7210 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7211
7212 /*
7213 * PML buffer FULL happened while executing iret from NMI,
7214 * "blocked by NMI" bit has to be set before next VM entry.
7215 */
7216 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7217 cpu_has_virtual_nmis() &&
7218 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7219 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7220 GUEST_INTR_STATE_NMI);
7221
7222 /*
7223 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7224 * here.., and there's no userspace involvement needed for PML.
7225 */
7226 return 1;
7227}
7228
8b3e34e4
XG		 7229static int handle_pcommit(struct kvm_vcpu *vcpu)
7230{
7231 /* we never catch pcommit instruct for L1 guest. */
7232 WARN_ON(1);
7233 return 1;
7234}
7235
6aa8b732
AK		 7236/*
7237 * The exit handlers return 1 if the exit was handled fully and guest execution
7238 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7239 * to be done to userspace and return 0.
7240 */
772e0318 7241static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7242 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7243 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7244 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7245 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7246 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7247 [EXIT_REASON_CR_ACCESS] = handle_cr,
7248 [EXIT_REASON_DR_ACCESS] = handle_dr,
7249 [EXIT_REASON_CPUID] = handle_cpuid,
7250 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7251 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7252 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7253 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7254 [EXIT_REASON_INVD] = handle_invd,
a7052897 7255 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7256 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7257 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7258 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7259 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7260 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7261 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7262 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7263 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7264 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7265 [EXIT_REASON_VMOFF] = handle_vmoff,
7266 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7267 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7268 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7269 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7270 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7271 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7272 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7273 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7274 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7275 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7276 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7277 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7278 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7279 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7280 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7281 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7282 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7283 [EXIT_REASON_XSAVES] = handle_xsaves,
7284 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7285 [EXIT_REASON_PML_FULL] = handle_pml_full,
8b3e34e4 7286 [EXIT_REASON_PCOMMIT] = handle_pcommit,
6aa8b732
AK		 7287};
7288
7289static const int kvm_vmx_max_exit_handlers =
50a3485c 7290 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7291
908a7bdd
JK		 7292static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7293 struct vmcs12 *vmcs12)
7294{
7295 unsigned long exit_qualification;
7296 gpa_t bitmap, last_bitmap;
7297 unsigned int port;
7298 int size;
7299 u8 b;
7300
908a7bdd 7301 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7302 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7303
7304 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7305
7306 port = exit_qualification >> 16;
7307 size = (exit_qualification & 7) + 1;
7308
7309 last_bitmap = (gpa_t)-1;
7310 b = -1;
7311
7312 while (size > 0) {
7313 if (port < 0x8000)
7314 bitmap = vmcs12->io_bitmap_a;
7315 else if (port < 0x10000)
7316 bitmap = vmcs12->io_bitmap_b;
7317 else
1d804d07 7318 return true;
908a7bdd
JK		 7319 bitmap += (port & 0x7fff) / 8;
7320
7321 if (last_bitmap != bitmap)
54bf36aa 7322 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7323 return true;
908a7bdd 7324 if (b & (1 << (port & 7)))
1d804d07 7325 return true;
908a7bdd
JK		 7326
7327 port++;
7328 size--;
7329 last_bitmap = bitmap;
7330 }
7331
1d804d07 7332 return false;
908a7bdd
JK		 7333}
7334
644d711a
NHE		 7335/*
7336 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7337 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7338 * disinterest in the current event (read or write a specific MSR) by using an
7339 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7340 */
7341static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7342 struct vmcs12 *vmcs12, u32 exit_reason)
7343{
7344 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7345 gpa_t bitmap;
7346
cbd29cb6 7347 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7348 return true;
644d711a
NHE		 7349
7350 /*
7351 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7352 * for the four combinations of read/write and low/high MSR numbers.
7353 * First we need to figure out which of the four to use:
7354 */
7355 bitmap = vmcs12->msr_bitmap;
7356 if (exit_reason == EXIT_REASON_MSR_WRITE)
7357 bitmap += 2048;
7358 if (msr_index >= 0xc0000000) {
7359 msr_index -= 0xc0000000;
7360 bitmap += 1024;
7361 }
7362
7363 /* Then read the msr_index'th bit from this bitmap: */
7364 if (msr_index < 1024*8) {
7365 unsigned char b;
54bf36aa 7366 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7367 return true;
644d711a
NHE		 7368 return 1 & (b >> (msr_index & 7));
7369 } else
1d804d07 7370 return true; /* let L1 handle the wrong parameter */
644d711a
NHE		 7371}
7372
7373/*
7374 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7375 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7376 * intercept (via guest_host_mask etc.) the current event.
7377 */
7378static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7379 struct vmcs12 *vmcs12)
7380{
7381 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7382 int cr = exit_qualification & 15;
7383 int reg = (exit_qualification >> 8) & 15;
1e32c079 7384 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7385
7386 switch ((exit_qualification >> 4) & 3) {
7387 case 0: /* mov to cr */
7388 switch (cr) {
7389 case 0:
7390 if (vmcs12->cr0_guest_host_mask &
7391 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7392 return true;
644d711a
NHE		 7393 break;
7394 case 3:
7395 if ((vmcs12->cr3_target_count >= 1 &&
7396 vmcs12->cr3_target_value0 == val) ||
7397 (vmcs12->cr3_target_count >= 2 &&
7398 vmcs12->cr3_target_value1 == val) ||
7399 (vmcs12->cr3_target_count >= 3 &&
7400 vmcs12->cr3_target_value2 == val) ||
7401 (vmcs12->cr3_target_count >= 4 &&
7402 vmcs12->cr3_target_value3 == val))
1d804d07 7403 return false;
644d711a 7404 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7405 return true;
644d711a
NHE		 7406 break;
7407 case 4:
7408 if (vmcs12->cr4_guest_host_mask &
7409 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7410 return true;
644d711a
NHE		 7411 break;
7412 case 8:
7413 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7414 return true;
644d711a
NHE		 7415 break;
7416 }
7417 break;
7418 case 2: /* clts */
7419 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7420 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7421 return true;
644d711a
NHE		 7422 break;
7423 case 1: /* mov from cr */
7424 switch (cr) {
7425 case 3:
7426 if (vmcs12->cpu_based_vm_exec_control &
7427 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7428 return true;
644d711a
NHE		 7429 break;
7430 case 8:
7431 if (vmcs12->cpu_based_vm_exec_control &
7432 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7433 return true;
644d711a
NHE		 7434 break;
7435 }
7436 break;
7437 case 3: /* lmsw */
7438 /*
7439 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7440 * cr0. Other attempted changes are ignored, with no exit.
7441 */
7442 if (vmcs12->cr0_guest_host_mask & 0xe &
7443 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7444 return true;
644d711a
NHE		 7445 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7446 !(vmcs12->cr0_read_shadow & 0x1) &&
7447 (val & 0x1))
1d804d07 7448 return true;
644d711a
NHE		 7449 break;
7450 }
1d804d07 7451 return false;
644d711a
NHE		 7452}
7453
7454/*
7455 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7456 * should handle it ourselves in L0 (and then continue L2). Only call this
7457 * when in is_guest_mode (L2).
7458 */
7459static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7460{
644d711a
NHE		 7461 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7462 struct vcpu_vmx *vmx = to_vmx(vcpu);
7463 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7464 u32 exit_reason = vmx->exit_reason;
644d711a 7465
542060ea
JK		 7466 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7467 vmcs_readl(EXIT_QUALIFICATION),
7468 vmx->idt_vectoring_info,
7469 intr_info,
7470 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7471 KVM_ISA_VMX);
7472
644d711a 7473 if (vmx->nested.nested_run_pending)
1d804d07 7474 return false;
644d711a
NHE		 7475
7476 if (unlikely(vmx->fail)) {
bd80158a
JK		 7477 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7478 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 7479 return true;
644d711a
NHE		 7480 }
7481
7482 switch (exit_reason) {
7483 case EXIT_REASON_EXCEPTION_NMI:
7484 if (!is_exception(intr_info))
1d804d07 7485 return false;
644d711a
NHE		 7486 else if (is_page_fault(intr_info))
7487 return enable_ept;
e504c909 7488 else if (is_no_device(intr_info) &&
ccf9844e 7489 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 7490 return false;
644d711a
NHE		 7491 return vmcs12->exception_bitmap &
7492 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7493 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 7494 return false;
644d711a 7495 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 7496 return true;
644d711a 7497 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7498 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7499 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7500 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 7501 case EXIT_REASON_TASK_SWITCH:
1d804d07 7502 return true;
644d711a 7503 case EXIT_REASON_CPUID:
bc613494 7504 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
1d804d07
JP		 7505 return false;
7506 return true;
644d711a
NHE		 7507 case EXIT_REASON_HLT:
7508 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7509 case EXIT_REASON_INVD:
1d804d07 7510 return true;
644d711a
NHE		 7511 case EXIT_REASON_INVLPG:
7512 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7513 case EXIT_REASON_RDPMC:
7514 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
b3a2a907 7515 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE		 7516 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7517 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7518 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7519 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7520 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7521 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7522 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7523 /*
7524 * VMX instructions trap unconditionally. This allows L1 to
7525 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7526 */
1d804d07 7527 return true;
644d711a
NHE		 7528 case EXIT_REASON_CR_ACCESS:
7529 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7530 case EXIT_REASON_DR_ACCESS:
7531 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7532 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7533 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7534 case EXIT_REASON_MSR_READ:
7535 case EXIT_REASON_MSR_WRITE:
7536 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7537 case EXIT_REASON_INVALID_STATE:
1d804d07 7538 return true;
644d711a
NHE		 7539 case EXIT_REASON_MWAIT_INSTRUCTION:
7540 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD		 7541 case EXIT_REASON_MONITOR_TRAP_FLAG:
7542 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE		 7543 case EXIT_REASON_MONITOR_INSTRUCTION:
7544 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7545 case EXIT_REASON_PAUSE_INSTRUCTION:
7546 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7547 nested_cpu_has2(vmcs12,
7548 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7549 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 7550 return false;
644d711a 7551 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7552 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7553 case EXIT_REASON_APIC_ACCESS:
7554 return nested_cpu_has2(vmcs12,
7555 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 7556 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 7557 case EXIT_REASON_EOI_INDUCED:
7558 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 7559 return true;
644d711a 7560 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7561 /*
7562 * L0 always deals with the EPT violation. If nested EPT is
7563 * used, and the nested mmu code discovers that the address is
7564 * missing in the guest EPT table (EPT12), the EPT violation
7565 * will be injected with nested_ept_inject_page_fault()
7566 */
1d804d07 7567 return false;
644d711a 7568 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7569 /*
7570 * L2 never uses directly L1's EPT, but rather L0's own EPT
7571 * table (shadow on EPT) or a merged EPT table that L0 built
7572 * (EPT on EPT). So any problems with the structure of the
7573 * table is L0's fault.
7574 */
1d804d07 7575 return false;
644d711a
NHE		 7576 case EXIT_REASON_WBINVD:
7577 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7578 case EXIT_REASON_XSETBV:
1d804d07 7579 return true;
81dc01f7
WL		 7580 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7581 /*
7582 * This should never happen, since it is not possible to
7583 * set XSS to a non-zero value---neither in L1 nor in L2.
7584 * If if it were, XSS would have to be checked against
7585 * the XSS exit bitmap in vmcs12.
7586 */
7587 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8b3e34e4
XG		 7588 case EXIT_REASON_PCOMMIT:
7589 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
644d711a 7590 default:
1d804d07 7591 return true;
644d711a
NHE		 7592 }
7593}
7594
586f9607
AK		 7595static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7596{
7597 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7598 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7599}
7600
843e4330
KH		 7601static int vmx_enable_pml(struct vcpu_vmx *vmx)
7602{
7603 struct page *pml_pg;
843e4330
KH		 7604
7605 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7606 if (!pml_pg)
7607 return -ENOMEM;
7608
7609 vmx->pml_pg = pml_pg;
7610
7611 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7612 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7613
7ec36296 7614 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_ENABLE_PML);
843e4330
KH		 7615
7616 return 0;
7617}
7618
7619static void vmx_disable_pml(struct vcpu_vmx *vmx)
7620{
843e4330
KH		 7621 ASSERT(vmx->pml_pg);
7622 __free_page(vmx->pml_pg);
7623 vmx->pml_pg = NULL;
7624
7ec36296 7625 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_ENABLE_PML);
843e4330
KH		 7626}
7627
54bf36aa 7628static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 7629{
54bf36aa 7630 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH		 7631 u64 *pml_buf;
7632 u16 pml_idx;
7633
7634 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7635
7636 /* Do nothing if PML buffer is empty */
7637 if (pml_idx == (PML_ENTITY_NUM - 1))
7638 return;
7639
7640 /* PML index always points to next available PML buffer entity */
7641 if (pml_idx >= PML_ENTITY_NUM)
7642 pml_idx = 0;
7643 else
7644 pml_idx++;
7645
7646 pml_buf = page_address(vmx->pml_pg);
7647 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7648 u64 gpa;
7649
7650 gpa = pml_buf[pml_idx];
7651 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 7652 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH		 7653 }
7654
7655 /* reset PML index */
7656 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7657}
7658
7659/*
7660 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7661 * Called before reporting dirty_bitmap to userspace.
7662 */
7663static void kvm_flush_pml_buffers(struct kvm *kvm)
7664{
7665 int i;
7666 struct kvm_vcpu *vcpu;
7667 /*
7668 * We only need to kick vcpu out of guest mode here, as PML buffer
7669 * is flushed at beginning of all VMEXITs, and it's obvious that only
7670 * vcpus running in guest are possible to have unflushed GPAs in PML
7671 * buffer.
7672 */
7673 kvm_for_each_vcpu(i, vcpu, kvm)
7674 kvm_vcpu_kick(vcpu);
7675}
7676
4eb64dce
PB		 7677static void vmx_dump_sel(char *name, uint32_t sel)
7678{
7679 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7680 name, vmcs_read32(sel),
7681 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7682 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7683 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7684}
7685
7686static void vmx_dump_dtsel(char *name, uint32_t limit)
7687{
7688 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7689 name, vmcs_read32(limit),
7690 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7691}
7692
7693static void dump_vmcs(void)
7694{
7695 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7696 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7697 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7698 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7699 u32 secondary_exec_control = 0;
7700 unsigned long cr4 = vmcs_readl(GUEST_CR4);
7701 u64 efer = vmcs_readl(GUEST_IA32_EFER);
7702 int i, n;
7703
7704 if (cpu_has_secondary_exec_ctrls())
7705 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7706
7707 pr_err("*** Guest State ***\n");
7708 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7709 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7710 vmcs_readl(CR0_GUEST_HOST_MASK));
7711 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7712 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7713 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7714 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7715 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7716 {
7717 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7718 vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7719 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7720 vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7721 }
7722 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7723 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7724 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7725 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7726 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7727 vmcs_readl(GUEST_SYSENTER_ESP),
7728 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7729 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
7730 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
7731 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
7732 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
7733 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
7734 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
7735 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7736 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7737 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7738 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
7739 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7740 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7741 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7742 efer, vmcs_readl(GUEST_IA32_PAT));
7743 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7744 vmcs_readl(GUEST_IA32_DEBUGCTL),
7745 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7746 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7747 pr_err("PerfGlobCtl = 0x%016lx\n",
7748 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7749 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7750 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7751 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7752 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7753 vmcs_read32(GUEST_ACTIVITY_STATE));
7754 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7755 pr_err("InterruptStatus = %04x\n",
7756 vmcs_read16(GUEST_INTR_STATUS));
7757
7758 pr_err("*** Host State ***\n");
7759 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7760 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7761 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7762 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7763 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7764 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7765 vmcs_read16(HOST_TR_SELECTOR));
7766 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7767 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7768 vmcs_readl(HOST_TR_BASE));
7769 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7770 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7771 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7772 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7773 vmcs_readl(HOST_CR4));
7774 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7775 vmcs_readl(HOST_IA32_SYSENTER_ESP),
7776 vmcs_read32(HOST_IA32_SYSENTER_CS),
7777 vmcs_readl(HOST_IA32_SYSENTER_EIP));
7778 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7779 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7780 vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7781 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7782 pr_err("PerfGlobCtl = 0x%016lx\n",
7783 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7784
7785 pr_err("*** Control State ***\n");
7786 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7787 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7788 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7789 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7790 vmcs_read32(EXCEPTION_BITMAP),
7791 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7792 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7793 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7794 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7795 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
7796 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
7797 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
7798 vmcs_read32(VM_EXIT_INTR_INFO),
7799 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7800 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
7801 pr_err(" reason=%08x qualification=%016lx\n",
7802 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
7803 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
7804 vmcs_read32(IDT_VECTORING_INFO_FIELD),
7805 vmcs_read32(IDT_VECTORING_ERROR_CODE));
7806 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
7807 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
7808 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
7809 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
7810 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
7811 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
7812 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
7813 n = vmcs_read32(CR3_TARGET_COUNT);
7814 for (i = 0; i + 1 < n; i += 4)
7815 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
7816 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
7817 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
7818 if (i < n)
7819 pr_err("CR3 target%u=%016lx\n",
7820 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
7821 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
7822 pr_err("PLE Gap=%08x Window=%08x\n",
7823 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
7824 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
7825 pr_err("Virtual processor ID = 0x%04x\n",
7826 vmcs_read16(VIRTUAL_PROCESSOR_ID));
7827}
7828
6aa8b732
AK		 7829/*
7830 * The guest has exited. See if we can fix it or if we need userspace
7831 * assistance.
7832 */
851ba692 7833static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7834{
29bd8a78 7835 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7836 u32 exit_reason = vmx->exit_reason;
1155f76a 7837 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7838
843e4330
KH		 7839 /*
7840 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7841 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7842 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7843 * mode as if vcpus is in root mode, the PML buffer must has been
7844 * flushed already.
7845 */
7846 if (enable_pml)
54bf36aa 7847 vmx_flush_pml_buffer(vcpu);
843e4330 7848
80ced186 7849 /* If guest state is invalid, start emulating */
14168786 7850 if (vmx->emulation_required)
80ced186 7851 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7852
644d711a 7853 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7854 nested_vmx_vmexit(vcpu, exit_reason,
7855 vmcs_read32(VM_EXIT_INTR_INFO),
7856 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7857 return 1;
7858 }
7859
5120702e 7860 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 7861 dump_vmcs();
5120702e
MG		 7862 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7863 vcpu->run->fail_entry.hardware_entry_failure_reason
7864 = exit_reason;
7865 return 0;
7866 }
7867
29bd8a78 7868 if (unlikely(vmx->fail)) {
851ba692
AK		 7869 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7870 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7871 = vmcs_read32(VM_INSTRUCTION_ERROR);
7872 return 0;
7873 }
6aa8b732 7874
b9bf6882
XG		 7875 /*
7876 * Note:
7877 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7878 * delivery event since it indicates guest is accessing MMIO.
7879 * The vm-exit can be triggered again after return to guest that
7880 * will cause infinite loop.
7881 */
d77c26fc 7882 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7883 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7884 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7885 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7886 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7887 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7888 vcpu->run->internal.ndata = 2;
7889 vcpu->run->internal.data[0] = vectoring_info;
7890 vcpu->run->internal.data[1] = exit_reason;
7891 return 0;
7892 }
3b86cd99 7893
644d711a
NHE		 7894 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7895 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7896 get_vmcs12(vcpu))))) {
c4282df9 7897 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7898 vmx->soft_vnmi_blocked = 0;
3b86cd99 7899 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7900 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7901 /*
7902 * This CPU don't support us in finding the end of an
7903 * NMI-blocked window if the guest runs with IRQs
7904 * disabled. So we pull the trigger after 1 s of
7905 * futile waiting, but inform the user about this.
7906 */
7907 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7908 "state on VCPU %d after 1 s timeout\n",
7909 __func__, vcpu->vcpu_id);
7910 vmx->soft_vnmi_blocked = 0;
3b86cd99 7911 }
3b86cd99
JK		 7912 }
7913
6aa8b732
AK		 7914 if (exit_reason < kvm_vmx_max_exit_handlers
7915 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7916 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7917 else {
2bc19dc3
MT		 7918 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7919 kvm_queue_exception(vcpu, UD_VECTOR);
7920 return 1;
6aa8b732 7921 }
6aa8b732
AK		 7922}
7923
95ba8273 7924static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7925{
a7c0b07d
WL		 7926 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7927
7928 if (is_guest_mode(vcpu) &&
7929 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7930 return;
7931
95ba8273 7932 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7933 vmcs_write32(TPR_THRESHOLD, 0);
7934 return;
7935 }
7936
95ba8273 7937 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7938}
7939
8d14695f
YZ		 7940static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7941{
7942 u32 sec_exec_control;
7943
7944 /*
7945 * There is not point to enable virtualize x2apic without enable
7946 * apicv
7947 */
c7c9c56c 7948 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
35754c98 7949 !vmx_cpu_uses_apicv(vcpu))
8d14695f
YZ		 7950 return;
7951
35754c98 7952 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ		 7953 return;
7954
7955 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7956
7957 if (set) {
7958 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7959 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7960 } else {
7961 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7962 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7963 }
7964 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7965
7966 vmx_set_msr_bitmap(vcpu);
7967}
7968
38b99173
TC		 7969static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7970{
7971 struct vcpu_vmx *vmx = to_vmx(vcpu);
7972
7973 /*
7974 * Currently we do not handle the nested case where L2 has an
7975 * APIC access page of its own; that page is still pinned.
7976 * Hence, we skip the case where the VCPU is in guest mode _and_
7977 * L1 prepared an APIC access page for L2.
7978 *
7979 * For the case where L1 and L2 share the same APIC access page
7980 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7981 * in the vmcs12), this function will only update either the vmcs01
7982 * or the vmcs02. If the former, the vmcs02 will be updated by
7983 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7984 * the next L2->L1 exit.
7985 */
7986 if (!is_guest_mode(vcpu) ||
7987 !nested_cpu_has2(vmx->nested.current_vmcs12,
7988 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7989 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7990}
7991
c7c9c56c
YZ		 7992static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7993{
7994 u16 status;
7995 u8 old;
7996
c7c9c56c
YZ		 7997 if (isr == -1)
7998 isr = 0;
7999
8000 status = vmcs_read16(GUEST_INTR_STATUS);
8001 old = status >> 8;
8002 if (isr != old) {
8003 status &= 0xff;
8004 status |= isr << 8;
8005 vmcs_write16(GUEST_INTR_STATUS, status);
8006 }
8007}
8008
8009static void vmx_set_rvi(int vector)
8010{
8011 u16 status;
8012 u8 old;
8013
4114c27d
WW		 8014 if (vector == -1)
8015 vector = 0;
8016
c7c9c56c
YZ		 8017 status = vmcs_read16(GUEST_INTR_STATUS);
8018 old = (u8)status & 0xff;
8019 if ((u8)vector != old) {
8020 status &= ~0xff;
8021 status |= (u8)vector;
8022 vmcs_write16(GUEST_INTR_STATUS, status);
8023 }
8024}
8025
8026static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8027{
4114c27d
WW		 8028 if (!is_guest_mode(vcpu)) {
8029 vmx_set_rvi(max_irr);
8030 return;
8031 }
8032
c7c9c56c
YZ		 8033 if (max_irr == -1)
8034 return;
8035
963fee16 8036 /*
4114c27d
WW		 8037 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8038 * handles it.
963fee16 8039 */
4114c27d 8040 if (nested_exit_on_intr(vcpu))
963fee16
WL		 8041 return;
8042
963fee16 8043 /*
4114c27d 8044 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 8045 * is run without virtual interrupt delivery.
8046 */
8047 if (!kvm_event_needs_reinjection(vcpu) &&
8048 vmx_interrupt_allowed(vcpu)) {
8049 kvm_queue_interrupt(vcpu, max_irr, false);
8050 vmx_inject_irq(vcpu);
8051 }
c7c9c56c
YZ		 8052}
8053
3bb345f3 8054static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
c7c9c56c 8055{
3bb345f3 8056 u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
35754c98 8057 if (!vmx_cpu_uses_apicv(vcpu))
3d81bc7e
YZ		 8058 return;
8059
c7c9c56c
YZ		 8060 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8061 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8062 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8063 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8064}
8065
51aa01d1 8066static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8067{
00eba012
AK		 8068 u32 exit_intr_info;
8069
8070 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8071 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8072 return;
8073
c5ca8e57 8074 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 8075 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 8076
8077 /* Handle machine checks before interrupts are enabled */
00eba012 8078 if (is_machine_check(exit_intr_info))
a0861c02
AK		 8079 kvm_machine_check();
8080
20f65983 8081 /* We need to handle NMIs before interrupts are enabled */
00eba012 8082 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 8083 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8084 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8085 asm("int $2");
ff9d07a0
ZY		 8086 kvm_after_handle_nmi(&vmx->vcpu);
8087 }
51aa01d1 8088}
20f65983 8089
a547c6db
YZ		 8090static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8091{
8092 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8093
8094 /*
8095 * If external interrupt exists, IF bit is set in rflags/eflags on the
8096 * interrupt stack frame, and interrupt will be enabled on a return
8097 * from interrupt handler.
8098 */
8099 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8100 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8101 unsigned int vector;
8102 unsigned long entry;
8103 gate_desc *desc;
8104 struct vcpu_vmx *vmx = to_vmx(vcpu);
8105#ifdef CONFIG_X86_64
8106 unsigned long tmp;
8107#endif
8108
8109 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8110 desc = (gate_desc *)vmx->host_idt_base + vector;
8111 entry = gate_offset(*desc);
8112 asm volatile(
8113#ifdef CONFIG_X86_64
8114 "mov %%" _ASM_SP ", %[sp]\n\t"
8115 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8116 "push $%c[ss]\n\t"
8117 "push %[sp]\n\t"
8118#endif
8119 "pushf\n\t"
8120 "orl $0x200, (%%" _ASM_SP ")\n\t"
8121 __ASM_SIZE(push) " $%c[cs]\n\t"
8122 "call *%[entry]\n\t"
8123 :
8124#ifdef CONFIG_X86_64
8125 [sp]"=&r"(tmp)
8126#endif
8127 :
8128 [entry]"r"(entry),
8129 [ss]"i"(__KERNEL_DS),
8130 [cs]"i"(__KERNEL_CS)
8131 );
8132 } else
8133 local_irq_enable();
8134}
8135
6d396b55
PB		 8136static bool vmx_has_high_real_mode_segbase(void)
8137{
8138 return enable_unrestricted_guest || emulate_invalid_guest_state;
8139}
8140
da8999d3
LJ		 8141static bool vmx_mpx_supported(void)
8142{
8143 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8144 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8145}
8146
55412b2e
WL		 8147static bool vmx_xsaves_supported(void)
8148{
8149 return vmcs_config.cpu_based_2nd_exec_ctrl &
8150 SECONDARY_EXEC_XSAVES;
8151}
8152
51aa01d1
AK		 8153static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8154{
c5ca8e57 8155 u32 exit_intr_info;
51aa01d1
AK		 8156 bool unblock_nmi;
8157 u8 vector;
8158 bool idtv_info_valid;
8159
8160 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8161
cf393f75 8162 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 8163 if (vmx->nmi_known_unmasked)
8164 return;
c5ca8e57
AK		 8165 /*
8166 * Can't use vmx->exit_intr_info since we're not sure what
8167 * the exit reason is.
8168 */
8169 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 8170 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8171 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8172 /*
7b4a25cb 8173 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 8174 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8175 * a guest IRET fault.
7b4a25cb
GN		 8176 * SDM 3: 23.2.2 (September 2008)
8177 * Bit 12 is undefined in any of the following cases:
8178 * If the VM exit sets the valid bit in the IDT-vectoring
8179 * information field.
8180 * If the VM exit is due to a double fault.
cf393f75 8181 */
7b4a25cb
GN		 8182 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8183 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 8184 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8185 GUEST_INTR_STATE_NMI);
9d58b931
AK		 8186 else
8187 vmx->nmi_known_unmasked =
8188 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8189 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 8190 } else if (unlikely(vmx->soft_vnmi_blocked))
8191 vmx->vnmi_blocked_time +=
8192 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 8193}
8194
3ab66e8a 8195static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 8196 u32 idt_vectoring_info,
8197 int instr_len_field,
8198 int error_code_field)
51aa01d1 8199{
51aa01d1
AK		 8200 u8 vector;
8201 int type;
8202 bool idtv_info_valid;
8203
8204 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8205
3ab66e8a
JK		 8206 vcpu->arch.nmi_injected = false;
8207 kvm_clear_exception_queue(vcpu);
8208 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 8209
8210 if (!idtv_info_valid)
8211 return;
8212
3ab66e8a 8213 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8214
668f612f
AK		 8215 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8216 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8217
64a7ec06 8218 switch (type) {
37b96e98 8219 case INTR_TYPE_NMI_INTR:
3ab66e8a 8220 vcpu->arch.nmi_injected = true;
668f612f 8221 /*
7b4a25cb 8222 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 8223 * Clear bit "block by NMI" before VM entry if a NMI
8224 * delivery faulted.
668f612f 8225 */
3ab66e8a 8226 vmx_set_nmi_mask(vcpu, false);
37b96e98 8227 break;
37b96e98 8228 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8229 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 8230 /* fall through */
8231 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8232 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8233 u32 err = vmcs_read32(error_code_field);
851eb667 8234 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8235 } else
851eb667 8236 kvm_requeue_exception(vcpu, vector);
37b96e98 8237 break;
66fd3f7f 8238 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8239 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8240 /* fall through */
37b96e98 8241 case INTR_TYPE_EXT_INTR:
3ab66e8a 8242 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 8243 break;
8244 default:
8245 break;
f7d9238f 8246 }
cf393f75
AK		 8247}
8248
83422e17
AK		 8249static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8250{
3ab66e8a 8251 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8252 VM_EXIT_INSTRUCTION_LEN,
8253 IDT_VECTORING_ERROR_CODE);
8254}
8255
b463a6f7
AK		 8256static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8257{
3ab66e8a 8258 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8259 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8260 VM_ENTRY_INSTRUCTION_LEN,
8261 VM_ENTRY_EXCEPTION_ERROR_CODE);
8262
8263 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8264}
8265
d7cd9796
GN		 8266static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8267{
8268 int i, nr_msrs;
8269 struct perf_guest_switch_msr *msrs;
8270
8271 msrs = perf_guest_get_msrs(&nr_msrs);
8272
8273 if (!msrs)
8274 return;
8275
8276 for (i = 0; i < nr_msrs; i++)
8277 if (msrs[i].host == msrs[i].guest)
8278 clear_atomic_switch_msr(vmx, msrs[i].msr);
8279 else
8280 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8281 msrs[i].host);
8282}
8283
a3b5ba49 8284static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8285{
a2fa3e9f 8286 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8287 unsigned long debugctlmsr, cr4;
104f226b
AK		 8288
8289 /* Record the guest's net vcpu time for enforced NMI injections. */
8290 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8291 vmx->entry_time = ktime_get();
8292
8293 /* Don't enter VMX if guest state is invalid, let the exit handler
8294 start emulation until we arrive back to a valid state */
14168786 8295 if (vmx->emulation_required)
104f226b
AK		 8296 return;
8297
a7653ecd
RK		 8298 if (vmx->ple_window_dirty) {
8299 vmx->ple_window_dirty = false;
8300 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8301 }
8302
012f83cb
AG		 8303 if (vmx->nested.sync_shadow_vmcs) {
8304 copy_vmcs12_to_shadow(vmx);
8305 vmx->nested.sync_shadow_vmcs = false;
8306 }
8307
104f226b
AK		 8308 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8309 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8310 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8311 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8312
1e02ce4c 8313 cr4 = cr4_read_shadow();
d974baa3
AL		 8314 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8315 vmcs_writel(HOST_CR4, cr4);
8316 vmx->host_state.vmcs_host_cr4 = cr4;
8317 }
8318
104f226b
AK		 8319 /* When single-stepping over STI and MOV SS, we must clear the
8320 * corresponding interruptibility bits in the guest state. Otherwise
8321 * vmentry fails as it then expects bit 14 (BS) in pending debug
8322 * exceptions being set, but that's not correct for the guest debugging
8323 * case. */
8324 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8325 vmx_set_interrupt_shadow(vcpu, 0);
8326
d7cd9796 8327 atomic_switch_perf_msrs(vmx);
2a7921b7 8328 debugctlmsr = get_debugctlmsr();
d7cd9796 8329
d462b819 8330 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8331 asm(
6aa8b732 8332 /* Store host registers */
b188c81f
AK		 8333 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8334 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8335 "push %%" _ASM_CX " \n\t"
8336 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8337 "je 1f \n\t"
b188c81f 8338 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8339 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8340 "1: \n\t"
d3edefc0 8341 /* Reload cr2 if changed */
b188c81f
AK		 8342 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8343 "mov %%cr2, %%" _ASM_DX " \n\t"
8344 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8345 "je 2f \n\t"
b188c81f 8346 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8347 "2: \n\t"
6aa8b732 8348 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8349 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8350 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8351 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8352 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8353 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8354 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8355 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8356 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8357#ifdef CONFIG_X86_64
e08aa78a
AK		 8358 "mov %c[r8](%0), %%r8 \n\t"
8359 "mov %c[r9](%0), %%r9 \n\t"
8360 "mov %c[r10](%0), %%r10 \n\t"
8361 "mov %c[r11](%0), %%r11 \n\t"
8362 "mov %c[r12](%0), %%r12 \n\t"
8363 "mov %c[r13](%0), %%r13 \n\t"
8364 "mov %c[r14](%0), %%r14 \n\t"
8365 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8366#endif
b188c81f 8367 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8368
6aa8b732 8369 /* Enter guest mode */
83287ea4 8370 "jne 1f \n\t"
4ecac3fd 8371 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8372 "jmp 2f \n\t"
8373 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8374 "2: "
6aa8b732 8375 /* Save guest registers, load host registers, keep flags */
b188c81f 8376 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8377 "pop %0 \n\t"
b188c81f
AK		 8378 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8379 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8380 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8381 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8382 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8383 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8384 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8385#ifdef CONFIG_X86_64
e08aa78a
AK		 8386 "mov %%r8, %c[r8](%0) \n\t"
8387 "mov %%r9, %c[r9](%0) \n\t"
8388 "mov %%r10, %c[r10](%0) \n\t"
8389 "mov %%r11, %c[r11](%0) \n\t"
8390 "mov %%r12, %c[r12](%0) \n\t"
8391 "mov %%r13, %c[r13](%0) \n\t"
8392 "mov %%r14, %c[r14](%0) \n\t"
8393 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8394#endif
b188c81f
AK		 8395 "mov %%cr2, %%" _ASM_AX " \n\t"
8396 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8397
b188c81f 8398 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8399 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8400 ".pushsection .rodata \n\t"
8401 ".global vmx_return \n\t"
8402 "vmx_return: " _ASM_PTR " 2b \n\t"
8403 ".popsection"
e08aa78a 8404 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8405 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8406 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8407 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8408 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8409 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8410 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8411 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8412 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8413 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8414 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8415#ifdef CONFIG_X86_64
ad312c7c
ZX		 8416 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8417 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8418 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8419 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8420 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8421 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8422 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8423 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8424#endif
40712fae
AK		 8425 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8426 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8427 : "cc", "memory"
8428#ifdef CONFIG_X86_64
b188c81f 8429 , "rax", "rbx", "rdi", "rsi"
c2036300 8430 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8431#else
8432 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8433#endif
8434 );
6aa8b732 8435
2a7921b7
GN		 8436 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8437 if (debugctlmsr)
8438 update_debugctlmsr(debugctlmsr);
8439
aa67f609
AK		 8440#ifndef CONFIG_X86_64
8441 /*
8442 * The sysexit path does not restore ds/es, so we must set them to
8443 * a reasonable value ourselves.
8444 *
8445 * We can't defer this to vmx_load_host_state() since that function
8446 * may be executed in interrupt context, which saves and restore segments
8447 * around it, nullifying its effect.
8448 */
8449 loadsegment(ds, __USER_DS);
8450 loadsegment(es, __USER_DS);
8451#endif
8452
6de4f3ad 8453 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8454 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8455 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8456 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8457 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8458 vcpu->arch.regs_dirty = 0;
8459
1155f76a
AK		 8460 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8461
d462b819 8462 vmx->loaded_vmcs->launched = 1;
1b6269db 8463
51aa01d1 8464 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8465 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8466
e0b890d3
GN		 8467 /*
8468 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8469 * we did not inject a still-pending event to L1 now because of
8470 * nested_run_pending, we need to re-enable this bit.
8471 */
8472 if (vmx->nested.nested_run_pending)
8473 kvm_make_request(KVM_REQ_EVENT, vcpu);
8474
8475 vmx->nested.nested_run_pending = 0;
8476
51aa01d1
AK		 8477 vmx_complete_atomic_exit(vmx);
8478 vmx_recover_nmi_blocking(vmx);
cf393f75 8479 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8480}
8481
4fa7734c
PB		 8482static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8483{
8484 struct vcpu_vmx *vmx = to_vmx(vcpu);
8485 int cpu;
8486
8487 if (vmx->loaded_vmcs == &vmx->vmcs01)
8488 return;
8489
8490 cpu = get_cpu();
8491 vmx->loaded_vmcs = &vmx->vmcs01;
8492 vmx_vcpu_put(vcpu);
8493 vmx_vcpu_load(vcpu, cpu);
8494 vcpu->cpu = cpu;
8495 put_cpu();
8496}
8497
6aa8b732
AK		 8498static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8499{
fb3f0f51
RR		 8500 struct vcpu_vmx *vmx = to_vmx(vcpu);
8501
843e4330
KH		 8502 if (enable_pml)
8503 vmx_disable_pml(vmx);
cdbecfc3 8504 free_vpid(vmx);
4fa7734c
PB		 8505 leave_guest_mode(vcpu);
8506 vmx_load_vmcs01(vcpu);
26a865f4 8507 free_nested(vmx);
4fa7734c 8508 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8509 kfree(vmx->guest_msrs);
8510 kvm_vcpu_uninit(vcpu);
a4770347 8511 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8512}
8513
fb3f0f51 8514static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8515{
fb3f0f51 8516 int err;
c16f862d 8517 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8518 int cpu;
6aa8b732 8519
a2fa3e9f 8520 if (!vmx)
fb3f0f51
RR		 8521 return ERR_PTR(-ENOMEM);
8522
2384d2b3
SY		 8523 allocate_vpid(vmx);
8524
fb3f0f51
RR		 8525 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8526 if (err)
8527 goto free_vcpu;
965b58a5 8528
a2fa3e9f 8529 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8530 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8531 > PAGE_SIZE);
0123be42 8532
be6d05cf 8533 err = -ENOMEM;
fb3f0f51 8534 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8535 goto uninit_vcpu;
8536 }
965b58a5 8537
d462b819
NHE		 8538 vmx->loaded_vmcs = &vmx->vmcs01;
8539 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8540 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8541 goto free_msrs;
d462b819
NHE		 8542 if (!vmm_exclusive)
8543 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8544 loaded_vmcs_init(vmx->loaded_vmcs);
8545 if (!vmm_exclusive)
8546 kvm_cpu_vmxoff();
a2fa3e9f 8547
15ad7146
AK		 8548 cpu = get_cpu();
8549 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8550 vmx->vcpu.cpu = cpu;
8b9cf98c 8551 err = vmx_vcpu_setup(vmx);
fb3f0f51 8552 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8553 put_cpu();
fb3f0f51
RR		 8554 if (err)
8555 goto free_vmcs;
35754c98 8556 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK		 8557 err = alloc_apic_access_page(kvm);
8558 if (err)
5e4a0b3c 8559 goto free_vmcs;
a63cb560 8560 }
fb3f0f51 8561
b927a3ce
SY		 8562 if (enable_ept) {
8563 if (!kvm->arch.ept_identity_map_addr)
8564 kvm->arch.ept_identity_map_addr =
8565 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8566 err = init_rmode_identity_map(kvm);
8567 if (err)
93ea5388 8568 goto free_vmcs;
b927a3ce 8569 }
b7ebfb05 8570
b9c237bb
WV		 8571 if (nested)
8572 nested_vmx_setup_ctls_msrs(vmx);
8573
705699a1 8574 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE		 8575 vmx->nested.current_vmptr = -1ull;
8576 vmx->nested.current_vmcs12 = NULL;
8577
843e4330
KH		 8578 /*
8579 * If PML is turned on, failure on enabling PML just results in failure
8580 * of creating the vcpu, therefore we can simplify PML logic (by
8581 * avoiding dealing with cases, such as enabling PML partially on vcpus
8582 * for the guest, etc.
8583 */
8584 if (enable_pml) {
8585 err = vmx_enable_pml(vmx);
8586 if (err)
8587 goto free_vmcs;
8588 }
8589
fb3f0f51
RR		 8590 return &vmx->vcpu;
8591
8592free_vmcs:
5f3fbc34 8593 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8594free_msrs:
fb3f0f51
RR		 8595 kfree(vmx->guest_msrs);
8596uninit_vcpu:
8597 kvm_vcpu_uninit(&vmx->vcpu);
8598free_vcpu:
cdbecfc3 8599 free_vpid(vmx);
a4770347 8600 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8601 return ERR_PTR(err);
6aa8b732
AK		 8602}
8603
002c7f7c
YS		 8604static void __init vmx_check_processor_compat(void *rtn)
8605{
8606 struct vmcs_config vmcs_conf;
8607
8608 *(int *)rtn = 0;
8609 if (setup_vmcs_config(&vmcs_conf) < 0)
8610 *(int *)rtn = -EIO;
8611 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8612 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8613 smp_processor_id());
8614 *(int *)rtn = -EIO;
8615 }
8616}
8617
67253af5
SY		 8618static int get_ept_level(void)
8619{
8620 return VMX_EPT_DEFAULT_GAW + 1;
8621}
8622
4b12f0de 8623static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8624{
b18d5431
XG		 8625 u8 cache;
8626 u64 ipat = 0;
4b12f0de 8627
522c68c4 8628 /* For VT-d and EPT combination
606decd6 8629 * 1. MMIO: always map as UC
522c68c4
SY		 8630 * 2. EPT with VT-d:
8631 * a. VT-d without snooping control feature: can't guarantee the
606decd6 8632 * result, try to trust guest.
522c68c4
SY		 8633 * b. VT-d with snooping control feature: snooping control feature of
8634 * VT-d engine can guarantee the cache correctness. Just set it
8635 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8636 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8637 * consistent with host MTRR
8638 */
606decd6
PB		 8639 if (is_mmio) {
8640 cache = MTRR_TYPE_UNCACHABLE;
8641 goto exit;
8642 }
8643
8644 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG		 8645 ipat = VMX_EPT_IPAT_BIT;
8646 cache = MTRR_TYPE_WRBACK;
8647 goto exit;
8648 }
8649
8650 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8651 ipat = VMX_EPT_IPAT_BIT;
0da029ed 8652 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG		 8653 cache = MTRR_TYPE_WRBACK;
8654 else
8655 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG		 8656 goto exit;
8657 }
8658
ff53604b 8659 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG		 8660
8661exit:
8662 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY		 8663}
8664
17cc3935 8665static int vmx_get_lpage_level(void)
344f414f 8666{
878403b7
SY		 8667 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8668 return PT_DIRECTORY_LEVEL;
8669 else
8670 /* For shadow and EPT supported 1GB page */
8671 return PT_PDPE_LEVEL;
344f414f
JR		 8672}
8673
feda805f
XG		 8674static void vmcs_set_secondary_exec_control(u32 new_ctl)
8675{
8676 /*
8677 * These bits in the secondary execution controls field
8678 * are dynamic, the others are mostly based on the hypervisor
8679 * architecture and the guest's CPUID. Do not touch the
8680 * dynamic bits.
8681 */
8682 u32 mask =
8683 SECONDARY_EXEC_SHADOW_VMCS |
8684 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8685 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8686
8687 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8688
8689 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8690 (new_ctl & ~mask) | (cur_ctl & mask));
8691}
8692
0e851880
SY		 8693static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8694{
4e47c7a6
SY		 8695 struct kvm_cpuid_entry2 *best;
8696 struct vcpu_vmx *vmx = to_vmx(vcpu);
feda805f 8697 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
4e47c7a6 8698
4e47c7a6 8699 if (vmx_rdtscp_supported()) {
1cea0ce6
XG		 8700 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8701 if (!rdtscp_enabled)
feda805f 8702 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
f36201e5 8703
8b97265a 8704 if (nested) {
1cea0ce6 8705 if (rdtscp_enabled)
8b97265a
PB		 8706 vmx->nested.nested_vmx_secondary_ctls_high |=
8707 SECONDARY_EXEC_RDTSCP;
8708 else
8709 vmx->nested.nested_vmx_secondary_ctls_high &=
8710 ~SECONDARY_EXEC_RDTSCP;
8711 }
4e47c7a6 8712 }
ad756a16 8713
ad756a16
MJ		 8714 /* Exposing INVPCID only when PCID is exposed */
8715 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8716 if (vmx_invpcid_supported() &&
29541bb8
XG		 8717 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8718 !guest_cpuid_has_pcid(vcpu))) {
feda805f 8719 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
29541bb8 8720
ad756a16 8721 if (best)
4f977045 8722 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8723 }
8b3e34e4 8724
feda805f
XG		 8725 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8726
8b3e34e4
XG		 8727 if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8728 if (guest_cpuid_has_pcommit(vcpu))
8729 vmx->nested.nested_vmx_secondary_ctls_high |=
8730 SECONDARY_EXEC_PCOMMIT;
8731 else
8732 vmx->nested.nested_vmx_secondary_ctls_high &=
8733 ~SECONDARY_EXEC_PCOMMIT;
8734 }
0e851880
SY		 8735}
8736
d4330ef2
JR		 8737static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8738{
7b8050f5
NHE		 8739 if (func == 1 && nested)
8740 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8741}
8742
25d92081
YZ		 8743static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8744 struct x86_exception *fault)
8745{
533558bc
JK		 8746 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8747 u32 exit_reason;
25d92081
YZ		 8748
8749 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8750 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8751 else
533558bc
JK		 8752 exit_reason = EXIT_REASON_EPT_VIOLATION;
8753 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8754 vmcs12->guest_physical_address = fault->address;
8755}
8756
155a97a3
NHE		 8757/* Callbacks for nested_ept_init_mmu_context: */
8758
8759static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8760{
8761 /* return the page table to be shadowed - in our case, EPT12 */
8762 return get_vmcs12(vcpu)->ept_pointer;
8763}
8764
8a3c1a33 8765static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8766{
ad896af0
PB		 8767 WARN_ON(mmu_is_nested(vcpu));
8768 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8769 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8770 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8771 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8772 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8773 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8774
8775 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8776}
8777
8778static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8779{
8780 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8781}
8782
19d5f10b
EK		 8783static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8784 u16 error_code)
8785{
8786 bool inequality, bit;
8787
8788 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8789 inequality =
8790 (error_code & vmcs12->page_fault_error_code_mask) !=
8791 vmcs12->page_fault_error_code_match;
8792 return inequality ^ bit;
8793}
8794
feaf0c7d
GN		 8795static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8796 struct x86_exception *fault)
8797{
8798 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8799
8800 WARN_ON(!is_guest_mode(vcpu));
8801
19d5f10b 8802 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8803 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8804 vmcs_read32(VM_EXIT_INTR_INFO),
8805 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8806 else
8807 kvm_inject_page_fault(vcpu, fault);
8808}
8809
a2bcba50
WL		 8810static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8811 struct vmcs12 *vmcs12)
8812{
8813 struct vcpu_vmx *vmx = to_vmx(vcpu);
9090422f 8814 int maxphyaddr = cpuid_maxphyaddr(vcpu);
a2bcba50
WL		 8815
8816 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9090422f
EK		 8817 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8818 vmcs12->apic_access_addr >> maxphyaddr)
a2bcba50
WL		 8819 return false;
8820
8821 /*
8822 * Translate L1 physical address to host physical
8823 * address for vmcs02. Keep the page pinned, so this
8824 * physical address remains valid. We keep a reference
8825 * to it so we can release it later.
8826 */
8827 if (vmx->nested.apic_access_page) /* shouldn't happen */
8828 nested_release_page(vmx->nested.apic_access_page);
8829 vmx->nested.apic_access_page =
8830 nested_get_page(vcpu, vmcs12->apic_access_addr);
8831 }
a7c0b07d
WL		 8832
8833 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9090422f
EK		 8834 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8835 vmcs12->virtual_apic_page_addr >> maxphyaddr)
a7c0b07d
WL		 8836 return false;
8837
8838 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8839 nested_release_page(vmx->nested.virtual_apic_page);
8840 vmx->nested.virtual_apic_page =
8841 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8842
8843 /*
8844 * Failing the vm entry is _not_ what the processor does
8845 * but it's basically the only possibility we have.
8846 * We could still enter the guest if CR8 load exits are
8847 * enabled, CR8 store exits are enabled, and virtualize APIC
8848 * access is disabled; in this case the processor would never
8849 * use the TPR shadow and we could simply clear the bit from
8850 * the execution control. But such a configuration is useless,
8851 * so let's keep the code simple.
8852 */
8853 if (!vmx->nested.virtual_apic_page)
8854 return false;
8855 }
8856
705699a1 8857 if (nested_cpu_has_posted_intr(vmcs12)) {
9090422f
EK		 8858 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8859 vmcs12->posted_intr_desc_addr >> maxphyaddr)
705699a1
WV		 8860 return false;
8861
8862 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8863 kunmap(vmx->nested.pi_desc_page);
8864 nested_release_page(vmx->nested.pi_desc_page);
8865 }
8866 vmx->nested.pi_desc_page =
8867 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8868 if (!vmx->nested.pi_desc_page)
8869 return false;
8870
8871 vmx->nested.pi_desc =
8872 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8873 if (!vmx->nested.pi_desc) {
8874 nested_release_page_clean(vmx->nested.pi_desc_page);
8875 return false;
8876 }
8877 vmx->nested.pi_desc =
8878 (struct pi_desc *)((void *)vmx->nested.pi_desc +
8879 (unsigned long)(vmcs12->posted_intr_desc_addr &
8880 (PAGE_SIZE - 1)));
8881 }
8882
a2bcba50
WL		 8883 return true;
8884}
8885
f4124500
JK		 8886static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8887{
8888 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8889 struct vcpu_vmx *vmx = to_vmx(vcpu);
8890
8891 if (vcpu->arch.virtual_tsc_khz == 0)
8892 return;
8893
8894 /* Make sure short timeouts reliably trigger an immediate vmexit.
8895 * hrtimer_start does not guarantee this. */
8896 if (preemption_timeout <= 1) {
8897 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8898 return;
8899 }
8900
8901 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8902 preemption_timeout *= 1000000;
8903 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8904 hrtimer_start(&vmx->nested.preemption_timer,
8905 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8906}
8907
3af18d9c
WV		 8908static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8909 struct vmcs12 *vmcs12)
8910{
8911 int maxphyaddr;
8912 u64 addr;
8913
8914 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8915 return 0;
8916
8917 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8918 WARN_ON(1);
8919 return -EINVAL;
8920 }
8921 maxphyaddr = cpuid_maxphyaddr(vcpu);
8922
8923 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8924 ((addr + PAGE_SIZE) >> maxphyaddr))
8925 return -EINVAL;
8926
8927 return 0;
8928}
8929
8930/*
8931 * Merge L0's and L1's MSR bitmap, return false to indicate that
8932 * we do not use the hardware.
8933 */
8934static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8935 struct vmcs12 *vmcs12)
8936{
82f0dd4b 8937 int msr;
f2b93280
WV		 8938 struct page *page;
8939 unsigned long *msr_bitmap;
8940
8941 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8942 return false;
8943
8944 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8945 if (!page) {
8946 WARN_ON(1);
8947 return false;
8948 }
8949 msr_bitmap = (unsigned long *)kmap(page);
8950 if (!msr_bitmap) {
8951 nested_release_page_clean(page);
8952 WARN_ON(1);
8953 return false;
8954 }
8955
8956 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 8957 if (nested_cpu_has_apic_reg_virt(vmcs12))
8958 for (msr = 0x800; msr <= 0x8ff; msr++)
8959 nested_vmx_disable_intercept_for_msr(
8960 msr_bitmap,
8961 vmx_msr_bitmap_nested,
8962 msr, MSR_TYPE_R);
f2b93280
WV		 8963 /* TPR is allowed */
8964 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8965 vmx_msr_bitmap_nested,
8966 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8967 MSR_TYPE_R | MSR_TYPE_W);
608406e2
WV		 8968 if (nested_cpu_has_vid(vmcs12)) {
8969 /* EOI and self-IPI are allowed */
8970 nested_vmx_disable_intercept_for_msr(
8971 msr_bitmap,
8972 vmx_msr_bitmap_nested,
8973 APIC_BASE_MSR + (APIC_EOI >> 4),
8974 MSR_TYPE_W);
8975 nested_vmx_disable_intercept_for_msr(
8976 msr_bitmap,
8977 vmx_msr_bitmap_nested,
8978 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8979 MSR_TYPE_W);
8980 }
82f0dd4b
WV		 8981 } else {
8982 /*
8983 * Enable reading intercept of all the x2apic
8984 * MSRs. We should not rely on vmcs12 to do any
8985 * optimizations here, it may have been modified
8986 * by L1.
8987 */
8988 for (msr = 0x800; msr <= 0x8ff; msr++)
8989 __vmx_enable_intercept_for_msr(
8990 vmx_msr_bitmap_nested,
8991 msr,
8992 MSR_TYPE_R);
8993
f2b93280
WV		 8994 __vmx_enable_intercept_for_msr(
8995 vmx_msr_bitmap_nested,
8996 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
82f0dd4b 8997 MSR_TYPE_W);
608406e2
WV		 8998 __vmx_enable_intercept_for_msr(
8999 vmx_msr_bitmap_nested,
9000 APIC_BASE_MSR + (APIC_EOI >> 4),
9001 MSR_TYPE_W);
9002 __vmx_enable_intercept_for_msr(
9003 vmx_msr_bitmap_nested,
9004 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9005 MSR_TYPE_W);
82f0dd4b 9006 }
f2b93280
WV		 9007 kunmap(page);
9008 nested_release_page_clean(page);
9009
9010 return true;
9011}
9012
9013static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9014 struct vmcs12 *vmcs12)
9015{
82f0dd4b 9016 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 9017 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV		 9018 !nested_cpu_has_vid(vmcs12) &&
9019 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV		 9020 return 0;
9021
9022 /*
9023 * If virtualize x2apic mode is enabled,
9024 * virtualize apic access must be disabled.
9025 */
82f0dd4b
WV		 9026 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9027 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 9028 return -EINVAL;
9029
608406e2
WV		 9030 /*
9031 * If virtual interrupt delivery is enabled,
9032 * we must exit on external interrupts.
9033 */
9034 if (nested_cpu_has_vid(vmcs12) &&
9035 !nested_exit_on_intr(vcpu))
9036 return -EINVAL;
9037
705699a1
WV		 9038 /*
9039 * bits 15:8 should be zero in posted_intr_nv,
9040 * the descriptor address has been already checked
9041 * in nested_get_vmcs12_pages.
9042 */
9043 if (nested_cpu_has_posted_intr(vmcs12) &&
9044 (!nested_cpu_has_vid(vmcs12) ||
9045 !nested_exit_intr_ack_set(vcpu) ||
9046 vmcs12->posted_intr_nv & 0xff00))
9047 return -EINVAL;
9048
f2b93280
WV		 9049 /* tpr shadow is needed by all apicv features. */
9050 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9051 return -EINVAL;
9052
9053 return 0;
3af18d9c
WV		 9054}
9055
e9ac033e
EK		 9056static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9057 unsigned long count_field,
92d71bc6 9058 unsigned long addr_field)
ff651cb6 9059{
92d71bc6 9060 int maxphyaddr;
e9ac033e
EK		 9061 u64 count, addr;
9062
9063 if (vmcs12_read_any(vcpu, count_field, &count) ||
9064 vmcs12_read_any(vcpu, addr_field, &addr)) {
9065 WARN_ON(1);
9066 return -EINVAL;
9067 }
9068 if (count == 0)
9069 return 0;
92d71bc6 9070 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK		 9071 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9072 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9073 pr_warn_ratelimited(
9074 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9075 addr_field, maxphyaddr, count, addr);
9076 return -EINVAL;
9077 }
9078 return 0;
9079}
9080
9081static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9082 struct vmcs12 *vmcs12)
9083{
e9ac033e
EK		 9084 if (vmcs12->vm_exit_msr_load_count == 0 &&
9085 vmcs12->vm_exit_msr_store_count == 0 &&
9086 vmcs12->vm_entry_msr_load_count == 0)
9087 return 0; /* Fast path */
e9ac033e 9088 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9089 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9090 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9091 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9092 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9093 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK		 9094 return -EINVAL;
9095 return 0;
9096}
9097
9098static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9099 struct vmx_msr_entry *e)
9100{
9101 /* x2APIC MSR accesses are not allowed */
8a9781f7 9102 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK		 9103 return -EINVAL;
9104 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9105 e->index == MSR_IA32_UCODE_REV)
9106 return -EINVAL;
9107 if (e->reserved != 0)
ff651cb6
WV		 9108 return -EINVAL;
9109 return 0;
9110}
9111
e9ac033e
EK		 9112static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9113 struct vmx_msr_entry *e)
ff651cb6
WV		 9114{
9115 if (e->index == MSR_FS_BASE ||
9116 e->index == MSR_GS_BASE ||
e9ac033e
EK		 9117 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9118 nested_vmx_msr_check_common(vcpu, e))
9119 return -EINVAL;
9120 return 0;
9121}
9122
9123static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9124 struct vmx_msr_entry *e)
9125{
9126 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9127 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 9128 return -EINVAL;
9129 return 0;
9130}
9131
9132/*
9133 * Load guest's/host's msr at nested entry/exit.
9134 * return 0 for success, entry index for failure.
9135 */
9136static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9137{
9138 u32 i;
9139 struct vmx_msr_entry e;
9140 struct msr_data msr;
9141
9142 msr.host_initiated = false;
9143 for (i = 0; i < count; i++) {
54bf36aa
PB		 9144 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9145 &e, sizeof(e))) {
e9ac033e
EK		 9146 pr_warn_ratelimited(
9147 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9148 __func__, i, gpa + i * sizeof(e));
ff651cb6 9149 goto fail;
e9ac033e
EK		 9150 }
9151 if (nested_vmx_load_msr_check(vcpu, &e)) {
9152 pr_warn_ratelimited(
9153 "%s check failed (%u, 0x%x, 0x%x)\n",
9154 __func__, i, e.index, e.reserved);
9155 goto fail;
9156 }
ff651cb6
WV		 9157 msr.index = e.index;
9158 msr.data = e.value;
e9ac033e
EK		 9159 if (kvm_set_msr(vcpu, &msr)) {
9160 pr_warn_ratelimited(
9161 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9162 __func__, i, e.index, e.value);
ff651cb6 9163 goto fail;
e9ac033e 9164 }
ff651cb6
WV		 9165 }
9166 return 0;
9167fail:
9168 return i + 1;
9169}
9170
9171static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9172{
9173 u32 i;
9174 struct vmx_msr_entry e;
9175
9176 for (i = 0; i < count; i++) {
609e36d3 9177 struct msr_data msr_info;
54bf36aa
PB		 9178 if (kvm_vcpu_read_guest(vcpu,
9179 gpa + i * sizeof(e),
9180 &e, 2 * sizeof(u32))) {
e9ac033e
EK		 9181 pr_warn_ratelimited(
9182 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9183 __func__, i, gpa + i * sizeof(e));
ff651cb6 9184 return -EINVAL;
e9ac033e
EK		 9185 }
9186 if (nested_vmx_store_msr_check(vcpu, &e)) {
9187 pr_warn_ratelimited(
9188 "%s check failed (%u, 0x%x, 0x%x)\n",
9189 __func__, i, e.index, e.reserved);
ff651cb6 9190 return -EINVAL;
e9ac033e 9191 }
609e36d3
PB		 9192 msr_info.host_initiated = false;
9193 msr_info.index = e.index;
9194 if (kvm_get_msr(vcpu, &msr_info)) {
e9ac033e
EK		 9195 pr_warn_ratelimited(
9196 "%s cannot read MSR (%u, 0x%x)\n",
9197 __func__, i, e.index);
9198 return -EINVAL;
9199 }
54bf36aa
PB		 9200 if (kvm_vcpu_write_guest(vcpu,
9201 gpa + i * sizeof(e) +
9202 offsetof(struct vmx_msr_entry, value),
9203 &msr_info.data, sizeof(msr_info.data))) {
e9ac033e
EK		 9204 pr_warn_ratelimited(
9205 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9206 __func__, i, e.index, msr_info.data);
e9ac033e
EK		 9207 return -EINVAL;
9208 }
ff651cb6
WV		 9209 }
9210 return 0;
9211}
9212
fe3ef05c
NHE		 9213/*
9214 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9215 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9216 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 9217 * guest in a way that will both be appropriate to L1's requests, and our
9218 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9219 * function also has additional necessary side-effects, like setting various
9220 * vcpu->arch fields.
9221 */
9222static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9223{
9224 struct vcpu_vmx *vmx = to_vmx(vcpu);
9225 u32 exec_control;
9226
9227 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9228 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9229 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9230 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9231 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9232 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9233 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9234 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9235 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9236 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9237 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9238 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9239 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9240 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9241 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9242 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9243 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9244 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9245 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9246 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9247 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9248 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9249 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9250 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9251 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9252 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9253 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9254 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9255 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9256 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9257 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9258 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9259 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9260 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9261 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9262 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9263
2996fca0
JK		 9264 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9265 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9266 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9267 } else {
9268 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9269 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9270 }
fe3ef05c
NHE		 9271 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9272 vmcs12->vm_entry_intr_info_field);
9273 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9274 vmcs12->vm_entry_exception_error_code);
9275 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9276 vmcs12->vm_entry_instruction_len);
9277 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9278 vmcs12->guest_interruptibility_info);
fe3ef05c 9279 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9280 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 9281 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9282 vmcs12->guest_pending_dbg_exceptions);
9283 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9284 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9285
81dc01f7
WL		 9286 if (nested_cpu_has_xsaves(vmcs12))
9287 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 9288 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9289
f4124500
JK		 9290 exec_control = vmcs12->pin_based_vm_exec_control;
9291 exec_control |= vmcs_config.pin_based_exec_ctrl;
705699a1
WV		 9292 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9293
9294 if (nested_cpu_has_posted_intr(vmcs12)) {
9295 /*
9296 * Note that we use L0's vector here and in
9297 * vmx_deliver_nested_posted_interrupt.
9298 */
9299 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9300 vmx->nested.pi_pending = false;
9301 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9302 vmcs_write64(POSTED_INTR_DESC_ADDR,
9303 page_to_phys(vmx->nested.pi_desc_page) +
9304 (unsigned long)(vmcs12->posted_intr_desc_addr &
9305 (PAGE_SIZE - 1)));
9306 } else
9307 exec_control &= ~PIN_BASED_POSTED_INTR;
9308
f4124500 9309 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 9310
f4124500
JK		 9311 vmx->nested.preemption_timer_expired = false;
9312 if (nested_cpu_has_preemption_timer(vmcs12))
9313 vmx_start_preemption_timer(vcpu);
0238ea91 9314
fe3ef05c
NHE		 9315 /*
9316 * Whether page-faults are trapped is determined by a combination of
9317 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9318 * If enable_ept, L0 doesn't care about page faults and we should
9319 * set all of these to L1's desires. However, if !enable_ept, L0 does
9320 * care about (at least some) page faults, and because it is not easy
9321 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9322 * to exit on each and every L2 page fault. This is done by setting
9323 * MASK=MATCH=0 and (see below) EB.PF=1.
9324 * Note that below we don't need special code to set EB.PF beyond the
9325 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9326 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9327 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9328 *
9329 * A problem with this approach (when !enable_ept) is that L1 may be
9330 * injected with more page faults than it asked for. This could have
9331 * caused problems, but in practice existing hypervisors don't care.
9332 * To fix this, we will need to emulate the PFEC checking (on the L1
9333 * page tables), using walk_addr(), when injecting PFs to L1.
9334 */
9335 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9336 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9337 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9338 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9339
9340 if (cpu_has_secondary_exec_ctrls()) {
f4124500 9341 exec_control = vmx_secondary_exec_control(vmx);
e2821620 9342
fe3ef05c 9343 /* Take the following fields only from vmcs12 */
696dfd95 9344 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 9345 SECONDARY_EXEC_RDTSCP |
696dfd95 9346 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8b3e34e4
XG		 9347 SECONDARY_EXEC_APIC_REGISTER_VIRT |
9348 SECONDARY_EXEC_PCOMMIT);
fe3ef05c
NHE		 9349 if (nested_cpu_has(vmcs12,
9350 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9351 exec_control |= vmcs12->secondary_vm_exec_control;
9352
9353 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 9354 /*
9355 * If translation failed, no matter: This feature asks
9356 * to exit when accessing the given address, and if it
9357 * can never be accessed, this feature won't do
9358 * anything anyway.
9359 */
9360 if (!vmx->nested.apic_access_page)
9361 exec_control &=
9362 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9363 else
9364 vmcs_write64(APIC_ACCESS_ADDR,
9365 page_to_phys(vmx->nested.apic_access_page));
f2b93280 9366 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
35754c98 9367 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
ca3f257a
JK		 9368 exec_control |=
9369 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 9370 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 9371 }
9372
608406e2
WV		 9373 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9374 vmcs_write64(EOI_EXIT_BITMAP0,
9375 vmcs12->eoi_exit_bitmap0);
9376 vmcs_write64(EOI_EXIT_BITMAP1,
9377 vmcs12->eoi_exit_bitmap1);
9378 vmcs_write64(EOI_EXIT_BITMAP2,
9379 vmcs12->eoi_exit_bitmap2);
9380 vmcs_write64(EOI_EXIT_BITMAP3,
9381 vmcs12->eoi_exit_bitmap3);
9382 vmcs_write16(GUEST_INTR_STATUS,
9383 vmcs12->guest_intr_status);
9384 }
9385
fe3ef05c
NHE		 9386 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9387 }
9388
9389
9390 /*
9391 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9392 * Some constant fields are set here by vmx_set_constant_host_state().
9393 * Other fields are different per CPU, and will be set later when
9394 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9395 */
a547c6db 9396 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 9397
9398 /*
9399 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9400 * entry, but only if the current (host) sp changed from the value
9401 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9402 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9403 * here we just force the write to happen on entry.
9404 */
9405 vmx->host_rsp = 0;
9406
9407 exec_control = vmx_exec_control(vmx); /* L0's desires */
9408 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9409 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9410 exec_control &= ~CPU_BASED_TPR_SHADOW;
9411 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 9412
9413 if (exec_control & CPU_BASED_TPR_SHADOW) {
9414 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9415 page_to_phys(vmx->nested.virtual_apic_page));
9416 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9417 }
9418
3af18d9c 9419 if (cpu_has_vmx_msr_bitmap() &&
670125bd
WV		 9420 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9421 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9422 /* MSR_BITMAP will be set by following vmx_set_efer. */
3af18d9c
WV		 9423 } else
9424 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9425
fe3ef05c 9426 /*
3af18d9c 9427 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 9428 * Rather, exit every time.
9429 */
fe3ef05c
NHE		 9430 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9431 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9432
9433 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9434
9435 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9436 * bitwise-or of what L1 wants to trap for L2, and what we want to
9437 * trap. Note that CR0.TS also needs updating - we do this later.
9438 */
9439 update_exception_bitmap(vcpu);
9440 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9441 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9442
8049d651
NHE		 9443 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9444 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9445 * bits are further modified by vmx_set_efer() below.
9446 */
f4124500 9447 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9448
9449 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9450 * emulated by vmx_set_efer(), below.
9451 */
2961e876 9452 vm_entry_controls_init(vmx,
8049d651
NHE		 9453 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9454 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9455 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9456
44811c02 9457 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9458 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9459 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9460 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9461 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9462
9463
9464 set_cr4_guest_host_mask(vmx);
9465
36be0b9d
PB		 9466 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9467 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9468
27fc51b2
NHE		 9469 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9470 vmcs_write64(TSC_OFFSET,
9471 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9472 else
9473 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9474
9475 if (enable_vpid) {
9476 /*
9477 * Trivially support vpid by letting L2s share their parent
9478 * L1's vpid. TODO: move to a more elaborate solution, giving
9479 * each L2 its own vpid and exposing the vpid feature to L1.
9480 */
9481 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9482 vmx_flush_tlb(vcpu);
9483 }
9484
155a97a3
NHE		 9485 if (nested_cpu_has_ept(vmcs12)) {
9486 kvm_mmu_unload(vcpu);
9487 nested_ept_init_mmu_context(vcpu);
9488 }
9489
fe3ef05c
NHE		 9490 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9491 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9492 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9493 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9494 else
9495 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9496 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9497 vmx_set_efer(vcpu, vcpu->arch.efer);
9498
9499 /*
9500 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9501 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9502 * The CR0_READ_SHADOW is what L2 should have expected to read given
9503 * the specifications by L1; It's not enough to take
9504 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9505 * have more bits than L1 expected.
9506 */
9507 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9508 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9509
9510 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9511 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9512
9513 /* shadow page tables on either EPT or shadow page tables */
9514 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9515 kvm_mmu_reset_context(vcpu);
9516
feaf0c7d
GN		 9517 if (!enable_ept)
9518 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9519
3633cfc3
NHE		 9520 /*
9521 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9522 */
9523 if (enable_ept) {
9524 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9525 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9526 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9527 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9528 }
9529
fe3ef05c
NHE		 9530 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9531 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9532}
9533
cd232ad0
NHE		 9534/*
9535 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9536 * for running an L2 nested guest.
9537 */
9538static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9539{
9540 struct vmcs12 *vmcs12;
9541 struct vcpu_vmx *vmx = to_vmx(vcpu);
9542 int cpu;
9543 struct loaded_vmcs *vmcs02;
384bb783 9544 bool ia32e;
ff651cb6 9545 u32 msr_entry_idx;
cd232ad0
NHE		 9546
9547 if (!nested_vmx_check_permission(vcpu) ||
9548 !nested_vmx_check_vmcs12(vcpu))
9549 return 1;
9550
9551 skip_emulated_instruction(vcpu);
9552 vmcs12 = get_vmcs12(vcpu);
9553
012f83cb
AG		 9554 if (enable_shadow_vmcs)
9555 copy_shadow_to_vmcs12(vmx);
9556
7c177938
NHE		 9557 /*
9558 * The nested entry process starts with enforcing various prerequisites
9559 * on vmcs12 as required by the Intel SDM, and act appropriately when
9560 * they fail: As the SDM explains, some conditions should cause the
9561 * instruction to fail, while others will cause the instruction to seem
9562 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9563 * To speed up the normal (success) code path, we should avoid checking
9564 * for misconfigurations which will anyway be caught by the processor
9565 * when using the merged vmcs02.
9566 */
9567 if (vmcs12->launch_state == launch) {
9568 nested_vmx_failValid(vcpu,
9569 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9570 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9571 return 1;
9572 }
9573
6dfacadd
JK		 9574 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9575 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9576 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9577 return 1;
9578 }
9579
3af18d9c 9580 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9581 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9582 return 1;
9583 }
9584
3af18d9c 9585 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9586 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9587 return 1;
9588 }
9589
f2b93280
WV		 9590 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9591 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9592 return 1;
9593 }
9594
e9ac033e
EK		 9595 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9596 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9597 return 1;
9598 }
9599
7c177938 9600 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9601 vmx->nested.nested_vmx_true_procbased_ctls_low,
9602 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9603 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9604 vmx->nested.nested_vmx_secondary_ctls_low,
9605 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9606 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9607 vmx->nested.nested_vmx_pinbased_ctls_low,
9608 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9609 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9610 vmx->nested.nested_vmx_true_exit_ctls_low,
9611 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9612 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9613 vmx->nested.nested_vmx_true_entry_ctls_low,
9614 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9615 {
9616 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9617 return 1;
9618 }
9619
9620 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9621 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9622 nested_vmx_failValid(vcpu,
9623 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9624 return 1;
9625 }
9626
b9c237bb 9627 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9628 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9629 nested_vmx_entry_failure(vcpu, vmcs12,
9630 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9631 return 1;
9632 }
9633 if (vmcs12->vmcs_link_pointer != -1ull) {
9634 nested_vmx_entry_failure(vcpu, vmcs12,
9635 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9636 return 1;
9637 }
9638
384bb783 9639 /*
cb0c8cda 9640 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9641 * are performed on the field for the IA32_EFER MSR:
9642 * - Bits reserved in the IA32_EFER MSR must be 0.
9643 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9644 * the IA-32e mode guest VM-exit control. It must also be identical
9645 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9646 * CR0.PG) is 1.
9647 */
9648 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9649 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9650 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9651 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9652 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9653 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9654 nested_vmx_entry_failure(vcpu, vmcs12,
9655 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9656 return 1;
9657 }
9658 }
9659
9660 /*
9661 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9662 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9663 * the values of the LMA and LME bits in the field must each be that of
9664 * the host address-space size VM-exit control.
9665 */
9666 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9667 ia32e = (vmcs12->vm_exit_controls &
9668 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9669 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9670 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9671 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9672 nested_vmx_entry_failure(vcpu, vmcs12,
9673 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9674 return 1;
9675 }
9676 }
9677
7c177938
NHE		 9678 /*
9679 * We're finally done with prerequisite checking, and can start with
9680 * the nested entry.
9681 */
9682
cd232ad0
NHE		 9683 vmcs02 = nested_get_current_vmcs02(vmx);
9684 if (!vmcs02)
9685 return -ENOMEM;
9686
9687 enter_guest_mode(vcpu);
9688
9689 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9690
2996fca0
JK		 9691 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9692 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9693
cd232ad0
NHE		 9694 cpu = get_cpu();
9695 vmx->loaded_vmcs = vmcs02;
9696 vmx_vcpu_put(vcpu);
9697 vmx_vcpu_load(vcpu, cpu);
9698 vcpu->cpu = cpu;
9699 put_cpu();
9700
36c3cc42
JK		 9701 vmx_segment_cache_clear(vmx);
9702
cd232ad0
NHE		 9703 prepare_vmcs02(vcpu, vmcs12);
9704
ff651cb6
WV		 9705 msr_entry_idx = nested_vmx_load_msr(vcpu,
9706 vmcs12->vm_entry_msr_load_addr,
9707 vmcs12->vm_entry_msr_load_count);
9708 if (msr_entry_idx) {
9709 leave_guest_mode(vcpu);
9710 vmx_load_vmcs01(vcpu);
9711 nested_vmx_entry_failure(vcpu, vmcs12,
9712 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9713 return 1;
9714 }
9715
9716 vmcs12->launch_state = 1;
9717
6dfacadd 9718 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 9719 return kvm_vcpu_halt(vcpu);
6dfacadd 9720
7af40ad3
JK		 9721 vmx->nested.nested_run_pending = 1;
9722
cd232ad0
NHE		 9723 /*
9724 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9725 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9726 * returned as far as L1 is concerned. It will only return (and set
9727 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9728 */
9729 return 1;
9730}
9731
4704d0be
NHE		 9732/*
9733 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9734 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9735 * This function returns the new value we should put in vmcs12.guest_cr0.
9736 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9737 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9738 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9739 * didn't trap the bit, because if L1 did, so would L0).
9740 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9741 * been modified by L2, and L1 knows it. So just leave the old value of
9742 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9743 * isn't relevant, because if L0 traps this bit it can set it to anything.
9744 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9745 * changed these bits, and therefore they need to be updated, but L0
9746 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9747 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9748 */
9749static inline unsigned long
9750vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9751{
9752 return
9753 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9754 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9755 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9756 vcpu->arch.cr0_guest_owned_bits));
9757}
9758
9759static inline unsigned long
9760vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9761{
9762 return
9763 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9764 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9765 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9766 vcpu->arch.cr4_guest_owned_bits));
9767}
9768
5f3d5799
JK		 9769static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9770 struct vmcs12 *vmcs12)
9771{
9772 u32 idt_vectoring;
9773 unsigned int nr;
9774
851eb667 9775 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9776 nr = vcpu->arch.exception.nr;
9777 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9778
9779 if (kvm_exception_is_soft(nr)) {
9780 vmcs12->vm_exit_instruction_len =
9781 vcpu->arch.event_exit_inst_len;
9782 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9783 } else
9784 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9785
9786 if (vcpu->arch.exception.has_error_code) {
9787 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9788 vmcs12->idt_vectoring_error_code =
9789 vcpu->arch.exception.error_code;
9790 }
9791
9792 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9793 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9794 vmcs12->idt_vectoring_info_field =
9795 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9796 } else if (vcpu->arch.interrupt.pending) {
9797 nr = vcpu->arch.interrupt.nr;
9798 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9799
9800 if (vcpu->arch.interrupt.soft) {
9801 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9802 vmcs12->vm_entry_instruction_len =
9803 vcpu->arch.event_exit_inst_len;
9804 } else
9805 idt_vectoring |= INTR_TYPE_EXT_INTR;
9806
9807 vmcs12->idt_vectoring_info_field = idt_vectoring;
9808 }
9809}
9810
b6b8a145
JK		 9811static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9812{
9813 struct vcpu_vmx *vmx = to_vmx(vcpu);
9814
f4124500
JK		 9815 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9816 vmx->nested.preemption_timer_expired) {
9817 if (vmx->nested.nested_run_pending)
9818 return -EBUSY;
9819 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9820 return 0;
9821 }
9822
b6b8a145 9823 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9824 if (vmx->nested.nested_run_pending ||
9825 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9826 return -EBUSY;
9827 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9828 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9829 INTR_INFO_VALID_MASK, 0);
9830 /*
9831 * The NMI-triggered VM exit counts as injection:
9832 * clear this one and block further NMIs.
9833 */
9834 vcpu->arch.nmi_pending = 0;
9835 vmx_set_nmi_mask(vcpu, true);
9836 return 0;
9837 }
9838
9839 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9840 nested_exit_on_intr(vcpu)) {
9841 if (vmx->nested.nested_run_pending)
9842 return -EBUSY;
9843 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 9844 return 0;
b6b8a145
JK		 9845 }
9846
705699a1 9847 return vmx_complete_nested_posted_interrupt(vcpu);
b6b8a145
JK		 9848}
9849
f4124500
JK		 9850static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9851{
9852 ktime_t remaining =
9853 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9854 u64 value;
9855
9856 if (ktime_to_ns(remaining) <= 0)
9857 return 0;
9858
9859 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9860 do_div(value, 1000000);
9861 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9862}
9863
4704d0be
NHE		 9864/*
9865 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9866 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9867 * and this function updates it to reflect the changes to the guest state while
9868 * L2 was running (and perhaps made some exits which were handled directly by L0
9869 * without going back to L1), and to reflect the exit reason.
9870 * Note that we do not have to copy here all VMCS fields, just those that
9871 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9872 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9873 * which already writes to vmcs12 directly.
9874 */
533558bc
JK		 9875static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9876 u32 exit_reason, u32 exit_intr_info,
9877 unsigned long exit_qualification)
4704d0be
NHE		 9878{
9879 /* update guest state fields: */
9880 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9881 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9882
4704d0be
NHE		 9883 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9884 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9885 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9886
9887 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9888 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9889 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9890 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9891 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9892 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9893 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9894 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9895 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9896 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9897 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9898 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9899 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9900 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9901 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9902 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9903 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9904 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9905 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9906 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9907 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9908 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9909 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9910 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9911 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9912 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9913 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9914 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9915 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9916 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9917 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9918 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9919 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9920 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9921 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9922 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9923
4704d0be
NHE		 9924 vmcs12->guest_interruptibility_info =
9925 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9926 vmcs12->guest_pending_dbg_exceptions =
9927 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9928 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9929 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9930 else
9931 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9932
f4124500
JK		 9933 if (nested_cpu_has_preemption_timer(vmcs12)) {
9934 if (vmcs12->vm_exit_controls &
9935 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9936 vmcs12->vmx_preemption_timer_value =
9937 vmx_get_preemption_timer_value(vcpu);
9938 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9939 }
7854cbca 9940
3633cfc3
NHE		 9941 /*
9942 * In some cases (usually, nested EPT), L2 is allowed to change its
9943 * own CR3 without exiting. If it has changed it, we must keep it.
9944 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9945 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9946 *
9947 * Additionally, restore L2's PDPTR to vmcs12.
9948 */
9949 if (enable_ept) {
9950 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9951 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9952 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9953 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9954 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9955 }
9956
608406e2
WV		 9957 if (nested_cpu_has_vid(vmcs12))
9958 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9959
c18911a2
JK		 9960 vmcs12->vm_entry_controls =
9961 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9962 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9963
2996fca0
JK		 9964 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9965 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9966 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9967 }
9968
4704d0be
NHE		 9969 /* TODO: These cannot have changed unless we have MSR bitmaps and
9970 * the relevant bit asks not to trap the change */
b8c07d55 9971 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9972 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9973 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9974 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 9975 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9976 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9977 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 9978 if (vmx_mpx_supported())
9979 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 9980 if (nested_cpu_has_xsaves(vmcs12))
9981 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 9982
9983 /* update exit information fields: */
9984
533558bc
JK		 9985 vmcs12->vm_exit_reason = exit_reason;
9986 vmcs12->exit_qualification = exit_qualification;
4704d0be 9987
533558bc 9988 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 9989 if ((vmcs12->vm_exit_intr_info &
9990 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9991 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9992 vmcs12->vm_exit_intr_error_code =
9993 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 9994 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 9995 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9996 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9997
5f3d5799
JK		 9998 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9999 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10000 * instead of reading the real value. */
4704d0be 10001 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 10002
10003 /*
10004 * Transfer the event that L0 or L1 may wanted to inject into
10005 * L2 to IDT_VECTORING_INFO_FIELD.
10006 */
10007 vmcs12_save_pending_event(vcpu, vmcs12);
10008 }
10009
10010 /*
10011 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10012 * preserved above and would only end up incorrectly in L1.
10013 */
10014 vcpu->arch.nmi_injected = false;
10015 kvm_clear_exception_queue(vcpu);
10016 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 10017}
10018
10019/*
10020 * A part of what we need to when the nested L2 guest exits and we want to
10021 * run its L1 parent, is to reset L1's guest state to the host state specified
10022 * in vmcs12.
10023 * This function is to be called not only on normal nested exit, but also on
10024 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10025 * Failures During or After Loading Guest State").
10026 * This function should be called when the active VMCS is L1's (vmcs01).
10027 */
733568f9
JK		 10028static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10029 struct vmcs12 *vmcs12)
4704d0be 10030{
21feb4eb
ACL		 10031 struct kvm_segment seg;
10032
4704d0be
NHE		 10033 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10034 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10035 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 10036 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10037 else
10038 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10039 vmx_set_efer(vcpu, vcpu->arch.efer);
10040
10041 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10042 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10043 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 10044 /*
10045 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10046 * actually changed, because it depends on the current state of
10047 * fpu_active (which may have changed).
10048 * Note that vmx_set_cr0 refers to efer set above.
10049 */
9e3e4dbf 10050 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 10051 /*
10052 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10053 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10054 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10055 */
10056 update_exception_bitmap(vcpu);
10057 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10058 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10059
10060 /*
10061 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10062 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10063 */
10064 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10065 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10066
29bf08f1 10067 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10068
4704d0be
NHE		 10069 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10070 kvm_mmu_reset_context(vcpu);
10071
feaf0c7d
GN		 10072 if (!enable_ept)
10073 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10074
4704d0be
NHE		 10075 if (enable_vpid) {
10076 /*
10077 * Trivially support vpid by letting L2s share their parent
10078 * L1's vpid. TODO: move to a more elaborate solution, giving
10079 * each L2 its own vpid and exposing the vpid feature to L1.
10080 */
10081 vmx_flush_tlb(vcpu);
10082 }
10083
10084
10085 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10086 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10087 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10088 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10089 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10090
36be0b9d
PB		 10091 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10092 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10093 vmcs_write64(GUEST_BNDCFGS, 0);
10094
44811c02 10095 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10096 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 10097 vcpu->arch.pat = vmcs12->host_ia32_pat;
10098 }
4704d0be
NHE		 10099 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10100 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10101 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10102
21feb4eb
ACL		 10103 /* Set L1 segment info according to Intel SDM
10104 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10105 seg = (struct kvm_segment) {
10106 .base = 0,
10107 .limit = 0xFFFFFFFF,
10108 .selector = vmcs12->host_cs_selector,
10109 .type = 11,
10110 .present = 1,
10111 .s = 1,
10112 .g = 1
10113 };
10114 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10115 seg.l = 1;
10116 else
10117 seg.db = 1;
10118 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10119 seg = (struct kvm_segment) {
10120 .base = 0,
10121 .limit = 0xFFFFFFFF,
10122 .type = 3,
10123 .present = 1,
10124 .s = 1,
10125 .db = 1,
10126 .g = 1
10127 };
10128 seg.selector = vmcs12->host_ds_selector;
10129 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10130 seg.selector = vmcs12->host_es_selector;
10131 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10132 seg.selector = vmcs12->host_ss_selector;
10133 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10134 seg.selector = vmcs12->host_fs_selector;
10135 seg.base = vmcs12->host_fs_base;
10136 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10137 seg.selector = vmcs12->host_gs_selector;
10138 seg.base = vmcs12->host_gs_base;
10139 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10140 seg = (struct kvm_segment) {
205befd9 10141 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 10142 .limit = 0x67,
10143 .selector = vmcs12->host_tr_selector,
10144 .type = 11,
10145 .present = 1
10146 };
10147 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10148
503cd0c5
JK		 10149 kvm_set_dr(vcpu, 7, 0x400);
10150 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 10151
3af18d9c
WV		 10152 if (cpu_has_vmx_msr_bitmap())
10153 vmx_set_msr_bitmap(vcpu);
10154
ff651cb6
WV		 10155 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10156 vmcs12->vm_exit_msr_load_count))
10157 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 10158}
10159
10160/*
10161 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10162 * and modify vmcs12 to make it see what it would expect to see there if
10163 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10164 */
533558bc
JK		 10165static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10166 u32 exit_intr_info,
10167 unsigned long exit_qualification)
4704d0be
NHE		 10168{
10169 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 10170 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10171
5f3d5799
JK		 10172 /* trying to cancel vmlaunch/vmresume is a bug */
10173 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10174
4704d0be 10175 leave_guest_mode(vcpu);
533558bc
JK		 10176 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10177 exit_qualification);
4704d0be 10178
ff651cb6
WV		 10179 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10180 vmcs12->vm_exit_msr_store_count))
10181 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10182
f3380ca5
WL		 10183 vmx_load_vmcs01(vcpu);
10184
77b0f5d6
BD		 10185 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10186 && nested_exit_intr_ack_set(vcpu)) {
10187 int irq = kvm_cpu_get_interrupt(vcpu);
10188 WARN_ON(irq < 0);
10189 vmcs12->vm_exit_intr_info = irq |
10190 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10191 }
10192
542060ea
JK		 10193 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10194 vmcs12->exit_qualification,
10195 vmcs12->idt_vectoring_info_field,
10196 vmcs12->vm_exit_intr_info,
10197 vmcs12->vm_exit_intr_error_code,
10198 KVM_ISA_VMX);
4704d0be 10199
2961e876
GN		 10200 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10201 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 10202 vmx_segment_cache_clear(vmx);
10203
4704d0be
NHE		 10204 /* if no vmcs02 cache requested, remove the one we used */
10205 if (VMCS02_POOL_SIZE == 0)
10206 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10207
10208 load_vmcs12_host_state(vcpu, vmcs12);
10209
27fc51b2 10210 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 10211 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10212
10213 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10214 vmx->host_rsp = 0;
10215
10216 /* Unpin physical memory we referred to in vmcs02 */
10217 if (vmx->nested.apic_access_page) {
10218 nested_release_page(vmx->nested.apic_access_page);
48d89b92 10219 vmx->nested.apic_access_page = NULL;
4704d0be 10220 }
a7c0b07d
WL		 10221 if (vmx->nested.virtual_apic_page) {
10222 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 10223 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 10224 }
705699a1
WV		 10225 if (vmx->nested.pi_desc_page) {
10226 kunmap(vmx->nested.pi_desc_page);
10227 nested_release_page(vmx->nested.pi_desc_page);
10228 vmx->nested.pi_desc_page = NULL;
10229 vmx->nested.pi_desc = NULL;
10230 }
4704d0be 10231
38b99173
TC		 10232 /*
10233 * We are now running in L2, mmu_notifier will force to reload the
10234 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10235 */
10236 kvm_vcpu_reload_apic_access_page(vcpu);
10237
4704d0be
NHE		 10238 /*
10239 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10240 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10241 * success or failure flag accordingly.
10242 */
10243 if (unlikely(vmx->fail)) {
10244 vmx->fail = 0;
10245 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10246 } else
10247 nested_vmx_succeed(vcpu);
012f83cb
AG		 10248 if (enable_shadow_vmcs)
10249 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 10250
10251 /* in case we halted in L2 */
10252 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 10253}
10254
42124925
JK		 10255/*
10256 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10257 */
10258static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10259{
10260 if (is_guest_mode(vcpu))
533558bc 10261 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 10262 free_nested(to_vmx(vcpu));
10263}
10264
7c177938
NHE		 10265/*
10266 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10267 * 23.7 "VM-entry failures during or after loading guest state" (this also
10268 * lists the acceptable exit-reason and exit-qualification parameters).
10269 * It should only be called before L2 actually succeeded to run, and when
10270 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10271 */
10272static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10273 struct vmcs12 *vmcs12,
10274 u32 reason, unsigned long qualification)
10275{
10276 load_vmcs12_host_state(vcpu, vmcs12);
10277 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10278 vmcs12->exit_qualification = qualification;
10279 nested_vmx_succeed(vcpu);
012f83cb
AG		 10280 if (enable_shadow_vmcs)
10281 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 10282}
10283
8a76d7f2
JR		 10284static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10285 struct x86_instruction_info *info,
10286 enum x86_intercept_stage stage)
10287{
10288 return X86EMUL_CONTINUE;
10289}
10290
48d89b92 10291static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 10292{
b4a2d31d
RK		 10293 if (ple_gap)
10294 shrink_ple_window(vcpu);
ae97a3b8
RK		 10295}
10296
843e4330
KH		 10297static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10298 struct kvm_memory_slot *slot)
10299{
10300 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10301 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10302}
10303
10304static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10305 struct kvm_memory_slot *slot)
10306{
10307 kvm_mmu_slot_set_dirty(kvm, slot);
10308}
10309
10310static void vmx_flush_log_dirty(struct kvm *kvm)
10311{
10312 kvm_flush_pml_buffers(kvm);
10313}
10314
10315static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10316 struct kvm_memory_slot *memslot,
10317 gfn_t offset, unsigned long mask)
10318{
10319 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10320}
10321
cbdd1bea 10322static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 10323 .cpu_has_kvm_support = cpu_has_kvm_support,
10324 .disabled_by_bios = vmx_disabled_by_bios,
10325 .hardware_setup = hardware_setup,
10326 .hardware_unsetup = hardware_unsetup,
002c7f7c 10327 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 10328 .hardware_enable = hardware_enable,
10329 .hardware_disable = hardware_disable,
04547156 10330 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 10331 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK		 10332
10333 .vcpu_create = vmx_create_vcpu,
10334 .vcpu_free = vmx_free_vcpu,
04d2cc77 10335 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 10336
04d2cc77 10337 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 10338 .vcpu_load = vmx_vcpu_load,
10339 .vcpu_put = vmx_vcpu_put,
10340
c8639010 10341 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 10342 .get_msr = vmx_get_msr,
10343 .set_msr = vmx_set_msr,
10344 .get_segment_base = vmx_get_segment_base,
10345 .get_segment = vmx_get_segment,
10346 .set_segment = vmx_set_segment,
2e4d2653 10347 .get_cpl = vmx_get_cpl,
6aa8b732 10348 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 10349 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 10350 .decache_cr3 = vmx_decache_cr3,
25c4c276 10351 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 10352 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 10353 .set_cr3 = vmx_set_cr3,
10354 .set_cr4 = vmx_set_cr4,
6aa8b732 10355 .set_efer = vmx_set_efer,
6aa8b732
AK		 10356 .get_idt = vmx_get_idt,
10357 .set_idt = vmx_set_idt,
10358 .get_gdt = vmx_get_gdt,
10359 .set_gdt = vmx_set_gdt,
73aaf249
JK		 10360 .get_dr6 = vmx_get_dr6,
10361 .set_dr6 = vmx_set_dr6,
020df079 10362 .set_dr7 = vmx_set_dr7,
81908bf4 10363 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 10364 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 10365 .get_rflags = vmx_get_rflags,
10366 .set_rflags = vmx_set_rflags,
0fdd74f7 10367 .fpu_activate = vmx_fpu_activate,
02daab21 10368 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 10369
10370 .tlb_flush = vmx_flush_tlb,
6aa8b732 10371
6aa8b732 10372 .run = vmx_vcpu_run,
6062d012 10373 .handle_exit = vmx_handle_exit,
6aa8b732 10374 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 10375 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10376 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 10377 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 10378 .set_irq = vmx_inject_irq,
95ba8273 10379 .set_nmi = vmx_inject_nmi,
298101da 10380 .queue_exception = vmx_queue_exception,
b463a6f7 10381 .cancel_injection = vmx_cancel_injection,
78646121 10382 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 10383 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 10384 .get_nmi_mask = vmx_get_nmi_mask,
10385 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 10386 .enable_nmi_window = enable_nmi_window,
10387 .enable_irq_window = enable_irq_window,
10388 .update_cr8_intercept = update_cr8_intercept,
8d14695f 10389 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 10390 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d50ab6c1 10391 .cpu_uses_apicv = vmx_cpu_uses_apicv,
c7c9c56c
YZ		 10392 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10393 .hwapic_irr_update = vmx_hwapic_irr_update,
10394 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 10395 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10396 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 10397
cbc94022 10398 .set_tss_addr = vmx_set_tss_addr,
67253af5 10399 .get_tdp_level = get_ept_level,
4b12f0de 10400 .get_mt_mask = vmx_get_mt_mask,
229456fc 10401
586f9607 10402 .get_exit_info = vmx_get_exit_info,
586f9607 10403
17cc3935 10404 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 10405
10406 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 10407
10408 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 10409 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 10410
10411 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 10412
10413 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 10414
4051b188 10415 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 10416 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 10417 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 10418 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 10419 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 10420 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 10421
10422 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 10423
10424 .check_intercept = vmx_check_intercept,
a547c6db 10425 .handle_external_intr = vmx_handle_external_intr,
da8999d3 10426 .mpx_supported = vmx_mpx_supported,
55412b2e 10427 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 10428
10429 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 10430
10431 .sched_in = vmx_sched_in,
843e4330
KH		 10432
10433 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10434 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10435 .flush_log_dirty = vmx_flush_log_dirty,
10436 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
25462f7f
WH		 10437
10438 .pmu_ops = &intel_pmu_ops,
6aa8b732
AK		 10439};
10440
10441static int __init vmx_init(void)
10442{
34a1cd60
TC		 10443 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10444 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 10445 if (r)
34a1cd60 10446 return r;
25c5f225 10447
2965faa5 10448#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 10449 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10450 crash_vmclear_local_loaded_vmcss);
10451#endif
10452
fdef3ad1 10453 return 0;
6aa8b732
AK		 10454}
10455
10456static void __exit vmx_exit(void)
10457{
2965faa5 10458#ifdef CONFIG_KEXEC_CORE
3b63a43f 10459 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10460 synchronize_rcu();
10461#endif
10462
cb498ea2 10463 kvm_exit();
6aa8b732
AK		 10464}
10465
10466module_init(vmx_init)
10467module_exit(vmx_exit)
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