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KVM: VMX: adjust interface to allocate/free_vpid
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
af658dca 31#include <linux/trace_events.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
28b835d6 38#include <asm/cpu.h>
6aa8b732 39#include <asm/io.h>
3b3be0d1 40#include <asm/desc.h>
13673a90 41#include <asm/vmx.h>
6210e37b 42#include <asm/virtext.h>
a0861c02 43#include <asm/mce.h>
952f07ec 44#include <asm/fpu/internal.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
dab2087d 48#include <asm/apic.h>
efc64404 49#include <asm/irq_remapping.h>
6aa8b732 50
229456fc 51#include "trace.h"
25462f7f 52#include "pmu.h"
229456fc 53
4ecac3fd 54#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 55#define __ex_clear(x, reg) \
56 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 57
6aa8b732
AK		 58MODULE_AUTHOR("Qumranet");
59MODULE_LICENSE("GPL");
60
e9bda3b3
JT		 61static const struct x86_cpu_id vmx_cpu_id[] = {
62 X86_FEATURE_MATCH(X86_FEATURE_VMX),
63 {}
64};
65MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
66
476bc001 67static bool __read_mostly enable_vpid = 1;
736caefe 68module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 69
476bc001 70static bool __read_mostly flexpriority_enabled = 1;
736caefe 71module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 72
476bc001 73static bool __read_mostly enable_ept = 1;
736caefe 74module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 75
476bc001 76static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 77module_param_named(unrestricted_guest,
78 enable_unrestricted_guest, bool, S_IRUGO);
79
83c3a331
XH		 80static bool __read_mostly enable_ept_ad_bits = 1;
81module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
82
a27685c3 83static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 84module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 85
476bc001 86static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 87module_param(vmm_exclusive, bool, S_IRUGO);
88
476bc001 89static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 90module_param(fasteoi, bool, S_IRUGO);
91
5a71785d 92static bool __read_mostly enable_apicv = 1;
01e439be 93module_param(enable_apicv, bool, S_IRUGO);
83d4c286 94
abc4fc58
AG		 95static bool __read_mostly enable_shadow_vmcs = 1;
96module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 97/*
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
101 */
476bc001 102static bool __read_mostly nested = 0;
801d3424
NHE		 103module_param(nested, bool, S_IRUGO);
104
20300099
WL		 105static u64 __read_mostly host_xss;
106
843e4330
KH		 107static bool __read_mostly enable_pml = 1;
108module_param_named(pml, enable_pml, bool, S_IRUGO);
109
5037878e
GN		 110#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
111#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 112#define KVM_VM_CR0_ALWAYS_ON \
113 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 114#define KVM_CR4_GUEST_OWNED_BITS \
115 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 116 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 117
cdc0e244
AK		 118#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
119#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
120
78ac8b47
AK		 121#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
122
f4124500
JK		 123#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
124
4b8d54f9
ZE		 125/*
126 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
127 * ple_gap: upper bound on the amount of time between two successive
128 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 129 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 130 * ple_window: upper bound on the amount of time a guest is allowed to execute
131 * in a PAUSE loop. Tests indicate that most spinlocks are held for
132 * less than 2^12 cycles
133 * Time is measured based on a counter that runs at the same rate as the TSC,
134 * refer SDM volume 3b section 21.6.13 & 22.1.3.
135 */
b4a2d31d
RK		 136#define KVM_VMX_DEFAULT_PLE_GAP 128
137#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
138#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
139#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
140#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
141 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
142
4b8d54f9
ZE		 143static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
144module_param(ple_gap, int, S_IRUGO);
145
146static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
147module_param(ple_window, int, S_IRUGO);
148
b4a2d31d
RK		 149/* Default doubles per-vcpu window every exit. */
150static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
151module_param(ple_window_grow, int, S_IRUGO);
152
153/* Default resets per-vcpu window every exit to ple_window. */
154static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
155module_param(ple_window_shrink, int, S_IRUGO);
156
157/* Default is to compute the maximum so we can never overflow. */
158static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
159static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
160module_param(ple_window_max, int, S_IRUGO);
161
83287ea4
AK		 162extern const ulong vmx_return;
163
8bf00a52 164#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 165#define VMCS02_POOL_SIZE 1
61d2ef2c 166
a2fa3e9f
GH		 167struct vmcs {
168 u32 revision_id;
169 u32 abort;
170 char data[0];
171};
172
d462b819
NHE		 173/*
174 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
175 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
176 * loaded on this CPU (so we can clear them if the CPU goes down).
177 */
178struct loaded_vmcs {
179 struct vmcs *vmcs;
180 int cpu;
181 int launched;
182 struct list_head loaded_vmcss_on_cpu_link;
183};
184
26bb0981
AK		 185struct shared_msr_entry {
186 unsigned index;
187 u64 data;
d5696725 188 u64 mask;
26bb0981
AK		 189};
190
a9d30f33
NHE		 191/*
192 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
193 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
194 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
195 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
196 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
197 * More than one of these structures may exist, if L1 runs multiple L2 guests.
198 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
199 * underlying hardware which will be used to run L2.
200 * This structure is packed to ensure that its layout is identical across
201 * machines (necessary for live migration).
202 * If there are changes in this struct, VMCS12_REVISION must be changed.
203 */
22bd0358 204typedef u64 natural_width;
a9d30f33
NHE		 205struct __packed vmcs12 {
206 /* According to the Intel spec, a VMCS region must start with the
207 * following two fields. Then follow implementation-specific data.
208 */
209 u32 revision_id;
210 u32 abort;
22bd0358 211
27d6c865
NHE		 212 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
213 u32 padding[7]; /* room for future expansion */
214
22bd0358
NHE		 215 u64 io_bitmap_a;
216 u64 io_bitmap_b;
217 u64 msr_bitmap;
218 u64 vm_exit_msr_store_addr;
219 u64 vm_exit_msr_load_addr;
220 u64 vm_entry_msr_load_addr;
221 u64 tsc_offset;
222 u64 virtual_apic_page_addr;
223 u64 apic_access_addr;
705699a1 224 u64 posted_intr_desc_addr;
22bd0358 225 u64 ept_pointer;
608406e2
WV		 226 u64 eoi_exit_bitmap0;
227 u64 eoi_exit_bitmap1;
228 u64 eoi_exit_bitmap2;
229 u64 eoi_exit_bitmap3;
81dc01f7 230 u64 xss_exit_bitmap;
22bd0358
NHE		 231 u64 guest_physical_address;
232 u64 vmcs_link_pointer;
233 u64 guest_ia32_debugctl;
234 u64 guest_ia32_pat;
235 u64 guest_ia32_efer;
236 u64 guest_ia32_perf_global_ctrl;
237 u64 guest_pdptr0;
238 u64 guest_pdptr1;
239 u64 guest_pdptr2;
240 u64 guest_pdptr3;
36be0b9d 241 u64 guest_bndcfgs;
22bd0358
NHE		 242 u64 host_ia32_pat;
243 u64 host_ia32_efer;
244 u64 host_ia32_perf_global_ctrl;
245 u64 padding64[8]; /* room for future expansion */
246 /*
247 * To allow migration of L1 (complete with its L2 guests) between
248 * machines of different natural widths (32 or 64 bit), we cannot have
249 * unsigned long fields with no explict size. We use u64 (aliased
250 * natural_width) instead. Luckily, x86 is little-endian.
251 */
252 natural_width cr0_guest_host_mask;
253 natural_width cr4_guest_host_mask;
254 natural_width cr0_read_shadow;
255 natural_width cr4_read_shadow;
256 natural_width cr3_target_value0;
257 natural_width cr3_target_value1;
258 natural_width cr3_target_value2;
259 natural_width cr3_target_value3;
260 natural_width exit_qualification;
261 natural_width guest_linear_address;
262 natural_width guest_cr0;
263 natural_width guest_cr3;
264 natural_width guest_cr4;
265 natural_width guest_es_base;
266 natural_width guest_cs_base;
267 natural_width guest_ss_base;
268 natural_width guest_ds_base;
269 natural_width guest_fs_base;
270 natural_width guest_gs_base;
271 natural_width guest_ldtr_base;
272 natural_width guest_tr_base;
273 natural_width guest_gdtr_base;
274 natural_width guest_idtr_base;
275 natural_width guest_dr7;
276 natural_width guest_rsp;
277 natural_width guest_rip;
278 natural_width guest_rflags;
279 natural_width guest_pending_dbg_exceptions;
280 natural_width guest_sysenter_esp;
281 natural_width guest_sysenter_eip;
282 natural_width host_cr0;
283 natural_width host_cr3;
284 natural_width host_cr4;
285 natural_width host_fs_base;
286 natural_width host_gs_base;
287 natural_width host_tr_base;
288 natural_width host_gdtr_base;
289 natural_width host_idtr_base;
290 natural_width host_ia32_sysenter_esp;
291 natural_width host_ia32_sysenter_eip;
292 natural_width host_rsp;
293 natural_width host_rip;
294 natural_width paddingl[8]; /* room for future expansion */
295 u32 pin_based_vm_exec_control;
296 u32 cpu_based_vm_exec_control;
297 u32 exception_bitmap;
298 u32 page_fault_error_code_mask;
299 u32 page_fault_error_code_match;
300 u32 cr3_target_count;
301 u32 vm_exit_controls;
302 u32 vm_exit_msr_store_count;
303 u32 vm_exit_msr_load_count;
304 u32 vm_entry_controls;
305 u32 vm_entry_msr_load_count;
306 u32 vm_entry_intr_info_field;
307 u32 vm_entry_exception_error_code;
308 u32 vm_entry_instruction_len;
309 u32 tpr_threshold;
310 u32 secondary_vm_exec_control;
311 u32 vm_instruction_error;
312 u32 vm_exit_reason;
313 u32 vm_exit_intr_info;
314 u32 vm_exit_intr_error_code;
315 u32 idt_vectoring_info_field;
316 u32 idt_vectoring_error_code;
317 u32 vm_exit_instruction_len;
318 u32 vmx_instruction_info;
319 u32 guest_es_limit;
320 u32 guest_cs_limit;
321 u32 guest_ss_limit;
322 u32 guest_ds_limit;
323 u32 guest_fs_limit;
324 u32 guest_gs_limit;
325 u32 guest_ldtr_limit;
326 u32 guest_tr_limit;
327 u32 guest_gdtr_limit;
328 u32 guest_idtr_limit;
329 u32 guest_es_ar_bytes;
330 u32 guest_cs_ar_bytes;
331 u32 guest_ss_ar_bytes;
332 u32 guest_ds_ar_bytes;
333 u32 guest_fs_ar_bytes;
334 u32 guest_gs_ar_bytes;
335 u32 guest_ldtr_ar_bytes;
336 u32 guest_tr_ar_bytes;
337 u32 guest_interruptibility_info;
338 u32 guest_activity_state;
339 u32 guest_sysenter_cs;
340 u32 host_ia32_sysenter_cs;
0238ea91
JK		 341 u32 vmx_preemption_timer_value;
342 u32 padding32[7]; /* room for future expansion */
22bd0358 343 u16 virtual_processor_id;
705699a1 344 u16 posted_intr_nv;
22bd0358
NHE		 345 u16 guest_es_selector;
346 u16 guest_cs_selector;
347 u16 guest_ss_selector;
348 u16 guest_ds_selector;
349 u16 guest_fs_selector;
350 u16 guest_gs_selector;
351 u16 guest_ldtr_selector;
352 u16 guest_tr_selector;
608406e2 353 u16 guest_intr_status;
22bd0358
NHE		 354 u16 host_es_selector;
355 u16 host_cs_selector;
356 u16 host_ss_selector;
357 u16 host_ds_selector;
358 u16 host_fs_selector;
359 u16 host_gs_selector;
360 u16 host_tr_selector;
a9d30f33
NHE		 361};
362
363/*
364 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
365 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
366 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
367 */
368#define VMCS12_REVISION 0x11e57ed0
369
370/*
371 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
372 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
373 * current implementation, 4K are reserved to avoid future complications.
374 */
375#define VMCS12_SIZE 0x1000
376
ff2f6fe9
NHE		 377/* Used to remember the last vmcs02 used for some recently used vmcs12s */
378struct vmcs02_list {
379 struct list_head list;
380 gpa_t vmptr;
381 struct loaded_vmcs vmcs02;
382};
383
ec378aee
NHE		 384/*
385 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
386 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
387 */
388struct nested_vmx {
389 /* Has the level1 guest done vmxon? */
390 bool vmxon;
3573e22c 391 gpa_t vmxon_ptr;
a9d30f33
NHE		 392
393 /* The guest-physical address of the current VMCS L1 keeps for L2 */
394 gpa_t current_vmptr;
395 /* The host-usable pointer to the above */
396 struct page *current_vmcs12_page;
397 struct vmcs12 *current_vmcs12;
8de48833 398 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 399 /*
400 * Indicates if the shadow vmcs must be updated with the
401 * data hold by vmcs12
402 */
403 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 404
405 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
406 struct list_head vmcs02_pool;
407 int vmcs02_num;
fe3ef05c 408 u64 vmcs01_tsc_offset;
644d711a
NHE		 409 /* L2 must run next, and mustn't decide to exit to L1. */
410 bool nested_run_pending;
fe3ef05c
NHE		 411 /*
412 * Guest pages referred to in vmcs02 with host-physical pointers, so
413 * we must keep them pinned while L2 runs.
414 */
415 struct page *apic_access_page;
a7c0b07d 416 struct page *virtual_apic_page;
705699a1
WV		 417 struct page *pi_desc_page;
418 struct pi_desc *pi_desc;
419 bool pi_pending;
420 u16 posted_intr_nv;
b3897a49 421 u64 msr_ia32_feature_control;
f4124500
JK		 422
423 struct hrtimer preemption_timer;
424 bool preemption_timer_expired;
2996fca0
JK		 425
426 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
427 u64 vmcs01_debugctl;
b9c237bb
WV		 428
429 u32 nested_vmx_procbased_ctls_low;
430 u32 nested_vmx_procbased_ctls_high;
431 u32 nested_vmx_true_procbased_ctls_low;
432 u32 nested_vmx_secondary_ctls_low;
433 u32 nested_vmx_secondary_ctls_high;
434 u32 nested_vmx_pinbased_ctls_low;
435 u32 nested_vmx_pinbased_ctls_high;
436 u32 nested_vmx_exit_ctls_low;
437 u32 nested_vmx_exit_ctls_high;
438 u32 nested_vmx_true_exit_ctls_low;
439 u32 nested_vmx_entry_ctls_low;
440 u32 nested_vmx_entry_ctls_high;
441 u32 nested_vmx_true_entry_ctls_low;
442 u32 nested_vmx_misc_low;
443 u32 nested_vmx_misc_high;
444 u32 nested_vmx_ept_caps;
ec378aee
NHE		 445};
446
01e439be 447#define POSTED_INTR_ON 0
ebbfc765
FW		 448#define POSTED_INTR_SN 1
449
01e439be
YZ		 450/* Posted-Interrupt Descriptor */
451struct pi_desc {
452 u32 pir[8]; /* Posted interrupt requested */
6ef1522f
FW		 453 union {
454 struct {
455 /* bit 256 - Outstanding Notification */
456 u16 on : 1,
457 /* bit 257 - Suppress Notification */
458 sn : 1,
459 /* bit 271:258 - Reserved */
460 rsvd_1 : 14;
461 /* bit 279:272 - Notification Vector */
462 u8 nv;
463 /* bit 287:280 - Reserved */
464 u8 rsvd_2;
465 /* bit 319:288 - Notification Destination */
466 u32 ndst;
467 };
468 u64 control;
469 };
470 u32 rsvd[6];
01e439be
YZ		 471} __aligned(64);
472
a20ed54d
YZ		 473static bool pi_test_and_set_on(struct pi_desc *pi_desc)
474{
475 return test_and_set_bit(POSTED_INTR_ON,
476 (unsigned long *)&pi_desc->control);
477}
478
479static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
480{
481 return test_and_clear_bit(POSTED_INTR_ON,
482 (unsigned long *)&pi_desc->control);
483}
484
485static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
486{
487 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
488}
489
ebbfc765
FW		 490static inline void pi_clear_sn(struct pi_desc *pi_desc)
491{
492 return clear_bit(POSTED_INTR_SN,
493 (unsigned long *)&pi_desc->control);
494}
495
496static inline void pi_set_sn(struct pi_desc *pi_desc)
497{
498 return set_bit(POSTED_INTR_SN,
499 (unsigned long *)&pi_desc->control);
500}
501
502static inline int pi_test_on(struct pi_desc *pi_desc)
503{
504 return test_bit(POSTED_INTR_ON,
505 (unsigned long *)&pi_desc->control);
506}
507
508static inline int pi_test_sn(struct pi_desc *pi_desc)
509{
510 return test_bit(POSTED_INTR_SN,
511 (unsigned long *)&pi_desc->control);
512}
513
a2fa3e9f 514struct vcpu_vmx {
fb3f0f51 515 struct kvm_vcpu vcpu;
313dbd49 516 unsigned long host_rsp;
29bd8a78 517 u8 fail;
9d58b931 518 bool nmi_known_unmasked;
51aa01d1 519 u32 exit_intr_info;
1155f76a 520 u32 idt_vectoring_info;
6de12732 521 ulong rflags;
26bb0981 522 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 523 int nmsrs;
524 int save_nmsrs;
a547c6db 525 unsigned long host_idt_base;
a2fa3e9f 526#ifdef CONFIG_X86_64
44ea2b17
AK		 527 u64 msr_host_kernel_gs_base;
528 u64 msr_guest_kernel_gs_base;
a2fa3e9f 529#endif
2961e876
GN		 530 u32 vm_entry_controls_shadow;
531 u32 vm_exit_controls_shadow;
d462b819
NHE		 532 /*
533 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
534 * non-nested (L1) guest, it always points to vmcs01. For a nested
535 * guest (L2), it points to a different VMCS.
536 */
537 struct loaded_vmcs vmcs01;
538 struct loaded_vmcs *loaded_vmcs;
539 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 540 struct msr_autoload {
541 unsigned nr;
542 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
543 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
544 } msr_autoload;
a2fa3e9f
GH		 545 struct {
546 int loaded;
547 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 548#ifdef CONFIG_X86_64
549 u16 ds_sel, es_sel;
550#endif
152d3f2f
LV		 551 int gs_ldt_reload_needed;
552 int fs_reload_needed;
da8999d3 553 u64 msr_host_bndcfgs;
d974baa3 554 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 555 } host_state;
9c8cba37 556 struct {
7ffd92c5 557 int vm86_active;
78ac8b47 558 ulong save_rflags;
f5f7b2fe
AK		 559 struct kvm_segment segs[8];
560 } rmode;
561 struct {
562 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 563 struct kvm_save_segment {
564 u16 selector;
565 unsigned long base;
566 u32 limit;
567 u32 ar;
f5f7b2fe 568 } seg[8];
2fb92db1 569 } segment_cache;
2384d2b3 570 int vpid;
04fa4d32 571 bool emulation_required;
3b86cd99
JK		 572
573 /* Support for vnmi-less CPUs */
574 int soft_vnmi_blocked;
575 ktime_t entry_time;
576 s64 vnmi_blocked_time;
a0861c02 577 u32 exit_reason;
4e47c7a6 578
01e439be
YZ		 579 /* Posted interrupt descriptor */
580 struct pi_desc pi_desc;
581
ec378aee
NHE		 582 /* Support for a guest hypervisor (nested VMX) */
583 struct nested_vmx nested;
a7653ecd
RK		 584
585 /* Dynamic PLE window. */
586 int ple_window;
587 bool ple_window_dirty;
843e4330
KH		 588
589 /* Support for PML */
590#define PML_ENTITY_NUM 512
591 struct page *pml_pg;
a2fa3e9f
GH		 592};
593
2fb92db1
AK		 594enum segment_cache_field {
595 SEG_FIELD_SEL = 0,
596 SEG_FIELD_BASE = 1,
597 SEG_FIELD_LIMIT = 2,
598 SEG_FIELD_AR = 3,
599
600 SEG_FIELD_NR = 4
601};
602
a2fa3e9f
GH		 603static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
604{
fb3f0f51 605 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 606}
607
efc64404
FW		 608static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
609{
610 return &(to_vmx(vcpu)->pi_desc);
611}
612
22bd0358
NHE		 613#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
614#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
615#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
616 [number##_HIGH] = VMCS12_OFFSET(name)+4
617
4607c2d7 618
fe2b201b 619static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 620 /*
621 * We do NOT shadow fields that are modified when L0
622 * traps and emulates any vmx instruction (e.g. VMPTRLD,
623 * VMXON...) executed by L1.
624 * For example, VM_INSTRUCTION_ERROR is read
625 * by L1 if a vmx instruction fails (part of the error path).
626 * Note the code assumes this logic. If for some reason
627 * we start shadowing these fields then we need to
628 * force a shadow sync when L0 emulates vmx instructions
629 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
630 * by nested_vmx_failValid)
631 */
632 VM_EXIT_REASON,
633 VM_EXIT_INTR_INFO,
634 VM_EXIT_INSTRUCTION_LEN,
635 IDT_VECTORING_INFO_FIELD,
636 IDT_VECTORING_ERROR_CODE,
637 VM_EXIT_INTR_ERROR_CODE,
638 EXIT_QUALIFICATION,
639 GUEST_LINEAR_ADDRESS,
640 GUEST_PHYSICAL_ADDRESS
641};
fe2b201b 642static int max_shadow_read_only_fields =
4607c2d7
AG		 643 ARRAY_SIZE(shadow_read_only_fields);
644
fe2b201b 645static unsigned long shadow_read_write_fields[] = {
a7c0b07d 646 TPR_THRESHOLD,
4607c2d7
AG		 647 GUEST_RIP,
648 GUEST_RSP,
649 GUEST_CR0,
650 GUEST_CR3,
651 GUEST_CR4,
652 GUEST_INTERRUPTIBILITY_INFO,
653 GUEST_RFLAGS,
654 GUEST_CS_SELECTOR,
655 GUEST_CS_AR_BYTES,
656 GUEST_CS_LIMIT,
657 GUEST_CS_BASE,
658 GUEST_ES_BASE,
36be0b9d 659 GUEST_BNDCFGS,
4607c2d7
AG		 660 CR0_GUEST_HOST_MASK,
661 CR0_READ_SHADOW,
662 CR4_READ_SHADOW,
663 TSC_OFFSET,
664 EXCEPTION_BITMAP,
665 CPU_BASED_VM_EXEC_CONTROL,
666 VM_ENTRY_EXCEPTION_ERROR_CODE,
667 VM_ENTRY_INTR_INFO_FIELD,
668 VM_ENTRY_INSTRUCTION_LEN,
669 VM_ENTRY_EXCEPTION_ERROR_CODE,
670 HOST_FS_BASE,
671 HOST_GS_BASE,
672 HOST_FS_SELECTOR,
673 HOST_GS_SELECTOR
674};
fe2b201b 675static int max_shadow_read_write_fields =
4607c2d7
AG		 676 ARRAY_SIZE(shadow_read_write_fields);
677
772e0318 678static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 679 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 680 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE		 681 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
682 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
683 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
684 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
685 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
686 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
687 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
688 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 689 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 690 FIELD(HOST_ES_SELECTOR, host_es_selector),
691 FIELD(HOST_CS_SELECTOR, host_cs_selector),
692 FIELD(HOST_SS_SELECTOR, host_ss_selector),
693 FIELD(HOST_DS_SELECTOR, host_ds_selector),
694 FIELD(HOST_FS_SELECTOR, host_fs_selector),
695 FIELD(HOST_GS_SELECTOR, host_gs_selector),
696 FIELD(HOST_TR_SELECTOR, host_tr_selector),
697 FIELD64(IO_BITMAP_A, io_bitmap_a),
698 FIELD64(IO_BITMAP_B, io_bitmap_b),
699 FIELD64(MSR_BITMAP, msr_bitmap),
700 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
701 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
702 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
703 FIELD64(TSC_OFFSET, tsc_offset),
704 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
705 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 706 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 707 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 708 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
709 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
710 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
711 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 712 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 713 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
714 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
715 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
716 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
717 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
718 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
719 FIELD64(GUEST_PDPTR0, guest_pdptr0),
720 FIELD64(GUEST_PDPTR1, guest_pdptr1),
721 FIELD64(GUEST_PDPTR2, guest_pdptr2),
722 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 723 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 724 FIELD64(HOST_IA32_PAT, host_ia32_pat),
725 FIELD64(HOST_IA32_EFER, host_ia32_efer),
726 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
727 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
728 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
729 FIELD(EXCEPTION_BITMAP, exception_bitmap),
730 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
731 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
732 FIELD(CR3_TARGET_COUNT, cr3_target_count),
733 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
734 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
735 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
736 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
737 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
738 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
739 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
740 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
741 FIELD(TPR_THRESHOLD, tpr_threshold),
742 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
743 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
744 FIELD(VM_EXIT_REASON, vm_exit_reason),
745 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
746 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
747 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
748 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
749 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
750 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
751 FIELD(GUEST_ES_LIMIT, guest_es_limit),
752 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
753 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
754 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
755 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
756 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
757 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
758 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
759 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
760 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
761 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
762 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
763 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
764 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
765 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
766 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
767 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
768 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
769 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
770 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
771 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
772 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 773 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 774 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
775 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
776 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
777 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
778 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
779 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
780 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
781 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
782 FIELD(EXIT_QUALIFICATION, exit_qualification),
783 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
784 FIELD(GUEST_CR0, guest_cr0),
785 FIELD(GUEST_CR3, guest_cr3),
786 FIELD(GUEST_CR4, guest_cr4),
787 FIELD(GUEST_ES_BASE, guest_es_base),
788 FIELD(GUEST_CS_BASE, guest_cs_base),
789 FIELD(GUEST_SS_BASE, guest_ss_base),
790 FIELD(GUEST_DS_BASE, guest_ds_base),
791 FIELD(GUEST_FS_BASE, guest_fs_base),
792 FIELD(GUEST_GS_BASE, guest_gs_base),
793 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
794 FIELD(GUEST_TR_BASE, guest_tr_base),
795 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
796 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
797 FIELD(GUEST_DR7, guest_dr7),
798 FIELD(GUEST_RSP, guest_rsp),
799 FIELD(GUEST_RIP, guest_rip),
800 FIELD(GUEST_RFLAGS, guest_rflags),
801 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
802 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
803 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
804 FIELD(HOST_CR0, host_cr0),
805 FIELD(HOST_CR3, host_cr3),
806 FIELD(HOST_CR4, host_cr4),
807 FIELD(HOST_FS_BASE, host_fs_base),
808 FIELD(HOST_GS_BASE, host_gs_base),
809 FIELD(HOST_TR_BASE, host_tr_base),
810 FIELD(HOST_GDTR_BASE, host_gdtr_base),
811 FIELD(HOST_IDTR_BASE, host_idtr_base),
812 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
813 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
814 FIELD(HOST_RSP, host_rsp),
815 FIELD(HOST_RIP, host_rip),
816};
22bd0358
NHE		 817
818static inline short vmcs_field_to_offset(unsigned long field)
819{
a2ae9df7
PB		 820 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
821
822 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
823 vmcs_field_to_offset_table[field] == 0)
824 return -ENOENT;
825
22bd0358
NHE		 826 return vmcs_field_to_offset_table[field];
827}
828
a9d30f33
NHE		 829static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
830{
831 return to_vmx(vcpu)->nested.current_vmcs12;
832}
833
834static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
835{
54bf36aa 836 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 837 if (is_error_page(page))
a9d30f33 838 return NULL;
32cad84f 839
a9d30f33
NHE		 840 return page;
841}
842
843static void nested_release_page(struct page *page)
844{
845 kvm_release_page_dirty(page);
846}
847
848static void nested_release_page_clean(struct page *page)
849{
850 kvm_release_page_clean(page);
851}
852
bfd0a56b 853static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 854static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 855static void kvm_cpu_vmxon(u64 addr);
856static void kvm_cpu_vmxoff(void);
93c4adc7 857static bool vmx_mpx_supported(void);
f53cd63c 858static bool vmx_xsaves_supported(void);
d50ab6c1 859static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
776e58ea 860static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 861static void vmx_set_segment(struct kvm_vcpu *vcpu,
862 struct kvm_segment *var, int seg);
863static void vmx_get_segment(struct kvm_vcpu *vcpu,
864 struct kvm_segment *var, int seg);
d99e4152
GN		 865static bool guest_state_valid(struct kvm_vcpu *vcpu);
866static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 867static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 868static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 869static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 870static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 871
6aa8b732
AK		 872static DEFINE_PER_CPU(struct vmcs *, vmxarea);
873static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 874/*
875 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
876 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
877 */
878static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 879static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 880
bf9f6ac8
FW		 881/*
882 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
883 * can find which vCPU should be waken up.
884 */
885static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
886static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
887
3e7c73e9
AK		 888static unsigned long *vmx_io_bitmap_a;
889static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 890static unsigned long *vmx_msr_bitmap_legacy;
891static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 892static unsigned long *vmx_msr_bitmap_legacy_x2apic;
893static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 894static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 895static unsigned long *vmx_vmread_bitmap;
896static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 897
110312c8 898static bool cpu_has_load_ia32_efer;
8bf00a52 899static bool cpu_has_load_perf_global_ctrl;
110312c8 900
2384d2b3
SY		 901static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
902static DEFINE_SPINLOCK(vmx_vpid_lock);
903
1c3d14fe 904static struct vmcs_config {
6aa8b732
AK		 905 int size;
906 int order;
907 u32 revision_id;
1c3d14fe
YS		 908 u32 pin_based_exec_ctrl;
909 u32 cpu_based_exec_ctrl;
f78e0e2e 910 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 911 u32 vmexit_ctrl;
912 u32 vmentry_ctrl;
913} vmcs_config;
6aa8b732 914
efff9e53 915static struct vmx_capability {
d56f546d
SY		 916 u32 ept;
917 u32 vpid;
918} vmx_capability;
919
6aa8b732
AK		 920#define VMX_SEGMENT_FIELD(seg) \
921 [VCPU_SREG_##seg] = { \
922 .selector = GUEST_##seg##_SELECTOR, \
923 .base = GUEST_##seg##_BASE, \
924 .limit = GUEST_##seg##_LIMIT, \
925 .ar_bytes = GUEST_##seg##_AR_BYTES, \
926 }
927
772e0318 928static const struct kvm_vmx_segment_field {
6aa8b732
AK		 929 unsigned selector;
930 unsigned base;
931 unsigned limit;
932 unsigned ar_bytes;
933} kvm_vmx_segment_fields[] = {
934 VMX_SEGMENT_FIELD(CS),
935 VMX_SEGMENT_FIELD(DS),
936 VMX_SEGMENT_FIELD(ES),
937 VMX_SEGMENT_FIELD(FS),
938 VMX_SEGMENT_FIELD(GS),
939 VMX_SEGMENT_FIELD(SS),
940 VMX_SEGMENT_FIELD(TR),
941 VMX_SEGMENT_FIELD(LDTR),
942};
943
26bb0981
AK		 944static u64 host_efer;
945
6de4f3ad
AK		 946static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
947
4d56c8a7 948/*
8c06585d 949 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 950 * away by decrementing the array size.
951 */
6aa8b732 952static const u32 vmx_msr_index[] = {
05b3e0c2 953#ifdef CONFIG_X86_64
44ea2b17 954 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 955#endif
8c06585d 956 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 957};
6aa8b732 958
31299944 959static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 960{
961 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
962 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 963 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 964}
965
31299944 966static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 967{
968 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
969 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 970 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 971}
972
31299944 973static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 974{
975 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
976 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 977 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 978}
979
31299944 980static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 981{
982 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
983 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
984}
985
31299944 986static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 987{
988 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
989 INTR_INFO_VALID_MASK)) ==
990 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
991}
992
31299944 993static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 994{
04547156 995 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 996}
997
31299944 998static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 999{
04547156 1000 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 1001}
1002
35754c98 1003static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 1004{
35754c98 1005 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS		 1006}
1007
31299944 1008static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 1009{
04547156
SY		 1010 return vmcs_config.cpu_based_exec_ctrl &
1011 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 1012}
1013
774ead3a 1014static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 1015{
04547156
SY		 1016 return vmcs_config.cpu_based_2nd_exec_ctrl &
1017 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1018}
1019
8d14695f
YZ		 1020static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1021{
1022 return vmcs_config.cpu_based_2nd_exec_ctrl &
1023 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1024}
1025
83d4c286
YZ		 1026static inline bool cpu_has_vmx_apic_register_virt(void)
1027{
1028 return vmcs_config.cpu_based_2nd_exec_ctrl &
1029 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1030}
1031
c7c9c56c
YZ		 1032static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1033{
1034 return vmcs_config.cpu_based_2nd_exec_ctrl &
1035 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1036}
1037
01e439be
YZ		 1038static inline bool cpu_has_vmx_posted_intr(void)
1039{
d6a858d1
PB		 1040 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1041 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ		 1042}
1043
1044static inline bool cpu_has_vmx_apicv(void)
1045{
1046 return cpu_has_vmx_apic_register_virt() &&
1047 cpu_has_vmx_virtual_intr_delivery() &&
1048 cpu_has_vmx_posted_intr();
1049}
1050
04547156
SY		 1051static inline bool cpu_has_vmx_flexpriority(void)
1052{
1053 return cpu_has_vmx_tpr_shadow() &&
1054 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 1055}
1056
e799794e
MT		 1057static inline bool cpu_has_vmx_ept_execute_only(void)
1058{
31299944 1059 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 1060}
1061
e799794e
MT		 1062static inline bool cpu_has_vmx_ept_2m_page(void)
1063{
31299944 1064 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1065}
1066
878403b7
SY		 1067static inline bool cpu_has_vmx_ept_1g_page(void)
1068{
31299944 1069 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1070}
1071
4bc9b982
SY		 1072static inline bool cpu_has_vmx_ept_4levels(void)
1073{
1074 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1075}
1076
83c3a331
XH		 1077static inline bool cpu_has_vmx_ept_ad_bits(void)
1078{
1079 return vmx_capability.ept & VMX_EPT_AD_BIT;
1080}
1081
31299944 1082static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1083{
31299944 1084 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1085}
1086
31299944 1087static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1088{
31299944 1089 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1090}
1091
518c8aee
GJ		 1092static inline bool cpu_has_vmx_invvpid_single(void)
1093{
1094 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1095}
1096
b9d762fa
GJ		 1097static inline bool cpu_has_vmx_invvpid_global(void)
1098{
1099 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1100}
1101
31299944 1102static inline bool cpu_has_vmx_ept(void)
d56f546d 1103{
04547156
SY		 1104 return vmcs_config.cpu_based_2nd_exec_ctrl &
1105 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1106}
1107
31299944 1108static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1109{
1110 return vmcs_config.cpu_based_2nd_exec_ctrl &
1111 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1112}
1113
31299944 1114static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1115{
1116 return vmcs_config.cpu_based_2nd_exec_ctrl &
1117 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1118}
1119
35754c98 1120static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1121{
35754c98 1122 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 1123}
1124
31299944 1125static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1126{
04547156
SY		 1127 return vmcs_config.cpu_based_2nd_exec_ctrl &
1128 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1129}
1130
31299944 1131static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1132{
1133 return vmcs_config.cpu_based_2nd_exec_ctrl &
1134 SECONDARY_EXEC_RDTSCP;
1135}
1136
ad756a16
MJ		 1137static inline bool cpu_has_vmx_invpcid(void)
1138{
1139 return vmcs_config.cpu_based_2nd_exec_ctrl &
1140 SECONDARY_EXEC_ENABLE_INVPCID;
1141}
1142
31299944 1143static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1144{
1145 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1146}
1147
f5f48ee1
SY		 1148static inline bool cpu_has_vmx_wbinvd_exit(void)
1149{
1150 return vmcs_config.cpu_based_2nd_exec_ctrl &
1151 SECONDARY_EXEC_WBINVD_EXITING;
1152}
1153
abc4fc58
AG		 1154static inline bool cpu_has_vmx_shadow_vmcs(void)
1155{
1156 u64 vmx_msr;
1157 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1158 /* check if the cpu supports writing r/o exit information fields */
1159 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1160 return false;
1161
1162 return vmcs_config.cpu_based_2nd_exec_ctrl &
1163 SECONDARY_EXEC_SHADOW_VMCS;
1164}
1165
843e4330
KH		 1166static inline bool cpu_has_vmx_pml(void)
1167{
1168 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1169}
1170
04547156
SY		 1171static inline bool report_flexpriority(void)
1172{
1173 return flexpriority_enabled;
1174}
1175
fe3ef05c
NHE		 1176static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1177{
1178 return vmcs12->cpu_based_vm_exec_control & bit;
1179}
1180
1181static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1182{
1183 return (vmcs12->cpu_based_vm_exec_control &
1184 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1185 (vmcs12->secondary_vm_exec_control & bit);
1186}
1187
f5c4368f 1188static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1189{
1190 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1191}
1192
f4124500
JK		 1193static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1194{
1195 return vmcs12->pin_based_vm_exec_control &
1196 PIN_BASED_VMX_PREEMPTION_TIMER;
1197}
1198
155a97a3
NHE		 1199static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1200{
1201 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1202}
1203
81dc01f7
WL		 1204static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1205{
1206 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1207 vmx_xsaves_supported();
1208}
1209
f2b93280
WV		 1210static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1211{
1212 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1213}
1214
82f0dd4b
WV		 1215static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1216{
1217 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1218}
1219
608406e2
WV		 1220static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1221{
1222 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1223}
1224
705699a1
WV		 1225static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1226{
1227 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1228}
1229
644d711a
NHE		 1230static inline bool is_exception(u32 intr_info)
1231{
1232 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1233 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1234}
1235
533558bc
JK		 1236static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1237 u32 exit_intr_info,
1238 unsigned long exit_qualification);
7c177938
NHE		 1239static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1240 struct vmcs12 *vmcs12,
1241 u32 reason, unsigned long qualification);
1242
8b9cf98c 1243static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1244{
1245 int i;
1246
a2fa3e9f 1247 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1248 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1249 return i;
1250 return -1;
1251}
1252
2384d2b3
SY		 1253static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1254{
1255 struct {
1256 u64 vpid : 16;
1257 u64 rsvd : 48;
1258 u64 gva;
1259 } operand = { vpid, 0, gva };
1260
4ecac3fd 1261 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1262 /* CF==1 or ZF==1 --> rc = -1 */
1263 "; ja 1f ; ud2 ; 1:"
1264 : : "a"(&operand), "c"(ext) : "cc", "memory");
1265}
1266
1439442c
SY		 1267static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1268{
1269 struct {
1270 u64 eptp, gpa;
1271 } operand = {eptp, gpa};
1272
4ecac3fd 1273 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1274 /* CF==1 or ZF==1 --> rc = -1 */
1275 "; ja 1f ; ud2 ; 1:\n"
1276 : : "a" (&operand), "c" (ext) : "cc", "memory");
1277}
1278
26bb0981 1279static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1280{
1281 int i;
1282
8b9cf98c 1283 i = __find_msr_index(vmx, msr);
a75beee6 1284 if (i >= 0)
a2fa3e9f 1285 return &vmx->guest_msrs[i];
8b6d44c7 1286 return NULL;
7725f0ba
AK		 1287}
1288
6aa8b732
AK		 1289static void vmcs_clear(struct vmcs *vmcs)
1290{
1291 u64 phys_addr = __pa(vmcs);
1292 u8 error;
1293
4ecac3fd 1294 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1295 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1296 : "cc", "memory");
1297 if (error)
1298 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1299 vmcs, phys_addr);
1300}
1301
d462b819
NHE		 1302static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1303{
1304 vmcs_clear(loaded_vmcs->vmcs);
1305 loaded_vmcs->cpu = -1;
1306 loaded_vmcs->launched = 0;
1307}
1308
7725b894
DX		 1309static void vmcs_load(struct vmcs *vmcs)
1310{
1311 u64 phys_addr = __pa(vmcs);
1312 u8 error;
1313
1314 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1315 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1316 : "cc", "memory");
1317 if (error)
2844d849 1318 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1319 vmcs, phys_addr);
1320}
1321
2965faa5 1322#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 1323/*
1324 * This bitmap is used to indicate whether the vmclear
1325 * operation is enabled on all cpus. All disabled by
1326 * default.
1327 */
1328static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1329
1330static inline void crash_enable_local_vmclear(int cpu)
1331{
1332 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1333}
1334
1335static inline void crash_disable_local_vmclear(int cpu)
1336{
1337 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1338}
1339
1340static inline int crash_local_vmclear_enabled(int cpu)
1341{
1342 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1343}
1344
1345static void crash_vmclear_local_loaded_vmcss(void)
1346{
1347 int cpu = raw_smp_processor_id();
1348 struct loaded_vmcs *v;
1349
1350 if (!crash_local_vmclear_enabled(cpu))
1351 return;
1352
1353 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1354 loaded_vmcss_on_cpu_link)
1355 vmcs_clear(v->vmcs);
1356}
1357#else
1358static inline void crash_enable_local_vmclear(int cpu) { }
1359static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1360#endif /* CONFIG_KEXEC_CORE */
8f536b76 1361
d462b819 1362static void __loaded_vmcs_clear(void *arg)
6aa8b732 1363{
d462b819 1364 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1365 int cpu = raw_smp_processor_id();
6aa8b732 1366
d462b819
NHE		 1367 if (loaded_vmcs->cpu != cpu)
1368 return; /* vcpu migration can race with cpu offline */
1369 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1370 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1371 crash_disable_local_vmclear(cpu);
d462b819 1372 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1373
1374 /*
1375 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1376 * is before setting loaded_vmcs->vcpu to -1 which is done in
1377 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1378 * then adds the vmcs into percpu list before it is deleted.
1379 */
1380 smp_wmb();
1381
d462b819 1382 loaded_vmcs_init(loaded_vmcs);
8f536b76 1383 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1384}
1385
d462b819 1386static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1387{
e6c7d321
XG		 1388 int cpu = loaded_vmcs->cpu;
1389
1390 if (cpu != -1)
1391 smp_call_function_single(cpu,
1392 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1393}
1394
1760dd49 1395static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1396{
1397 if (vmx->vpid == 0)
1398 return;
1399
518c8aee
GJ		 1400 if (cpu_has_vmx_invvpid_single())
1401 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1402}
1403
b9d762fa
GJ		 1404static inline void vpid_sync_vcpu_global(void)
1405{
1406 if (cpu_has_vmx_invvpid_global())
1407 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1408}
1409
1410static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1411{
1412 if (cpu_has_vmx_invvpid_single())
1760dd49 1413 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1414 else
1415 vpid_sync_vcpu_global();
1416}
1417
1439442c
SY		 1418static inline void ept_sync_global(void)
1419{
1420 if (cpu_has_vmx_invept_global())
1421 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1422}
1423
1424static inline void ept_sync_context(u64 eptp)
1425{
089d034e 1426 if (enable_ept) {
1439442c
SY		 1427 if (cpu_has_vmx_invept_context())
1428 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1429 else
1430 ept_sync_global();
1431 }
1432}
1433
96304217 1434static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1435{
5e520e62 1436 unsigned long value;
6aa8b732 1437
5e520e62
AK		 1438 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1439 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1440 return value;
1441}
1442
96304217 1443static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1444{
1445 return vmcs_readl(field);
1446}
1447
96304217 1448static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1449{
1450 return vmcs_readl(field);
1451}
1452
96304217 1453static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1454{
05b3e0c2 1455#ifdef CONFIG_X86_64
6aa8b732
AK		 1456 return vmcs_readl(field);
1457#else
1458 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1459#endif
1460}
1461
e52de1b8
AK		 1462static noinline void vmwrite_error(unsigned long field, unsigned long value)
1463{
1464 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1465 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1466 dump_stack();
1467}
1468
6aa8b732
AK		 1469static void vmcs_writel(unsigned long field, unsigned long value)
1470{
1471 u8 error;
1472
4ecac3fd 1473 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1474 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1475 if (unlikely(error))
1476 vmwrite_error(field, value);
6aa8b732
AK		 1477}
1478
1479static void vmcs_write16(unsigned long field, u16 value)
1480{
1481 vmcs_writel(field, value);
1482}
1483
1484static void vmcs_write32(unsigned long field, u32 value)
1485{
1486 vmcs_writel(field, value);
1487}
1488
1489static void vmcs_write64(unsigned long field, u64 value)
1490{
6aa8b732 1491 vmcs_writel(field, value);
7682f2d0 1492#ifndef CONFIG_X86_64
6aa8b732
AK		 1493 asm volatile ("");
1494 vmcs_writel(field+1, value >> 32);
1495#endif
1496}
1497
2ab455cc
AL		 1498static void vmcs_clear_bits(unsigned long field, u32 mask)
1499{
1500 vmcs_writel(field, vmcs_readl(field) & ~mask);
1501}
1502
1503static void vmcs_set_bits(unsigned long field, u32 mask)
1504{
1505 vmcs_writel(field, vmcs_readl(field) | mask);
1506}
1507
2961e876
GN		 1508static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1509{
1510 vmcs_write32(VM_ENTRY_CONTROLS, val);
1511 vmx->vm_entry_controls_shadow = val;
1512}
1513
1514static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1515{
1516 if (vmx->vm_entry_controls_shadow != val)
1517 vm_entry_controls_init(vmx, val);
1518}
1519
1520static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1521{
1522 return vmx->vm_entry_controls_shadow;
1523}
1524
1525
1526static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1527{
1528 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1529}
1530
1531static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1532{
1533 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1534}
1535
1536static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1537{
1538 vmcs_write32(VM_EXIT_CONTROLS, val);
1539 vmx->vm_exit_controls_shadow = val;
1540}
1541
1542static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1543{
1544 if (vmx->vm_exit_controls_shadow != val)
1545 vm_exit_controls_init(vmx, val);
1546}
1547
1548static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1549{
1550 return vmx->vm_exit_controls_shadow;
1551}
1552
1553
1554static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1555{
1556 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1557}
1558
1559static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1560{
1561 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1562}
1563
2fb92db1
AK		 1564static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1565{
1566 vmx->segment_cache.bitmask = 0;
1567}
1568
1569static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1570 unsigned field)
1571{
1572 bool ret;
1573 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1574
1575 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1576 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1577 vmx->segment_cache.bitmask = 0;
1578 }
1579 ret = vmx->segment_cache.bitmask & mask;
1580 vmx->segment_cache.bitmask |= mask;
1581 return ret;
1582}
1583
1584static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1585{
1586 u16 *p = &vmx->segment_cache.seg[seg].selector;
1587
1588 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1589 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1590 return *p;
1591}
1592
1593static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1594{
1595 ulong *p = &vmx->segment_cache.seg[seg].base;
1596
1597 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1598 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1599 return *p;
1600}
1601
1602static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1603{
1604 u32 *p = &vmx->segment_cache.seg[seg].limit;
1605
1606 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1607 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1608 return *p;
1609}
1610
1611static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1612{
1613 u32 *p = &vmx->segment_cache.seg[seg].ar;
1614
1615 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1616 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1617 return *p;
1618}
1619
abd3f2d6
AK		 1620static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1621{
1622 u32 eb;
1623
fd7373cc
JK		 1624 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1625 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1626 if ((vcpu->guest_debug &
1627 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1628 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1629 eb |= 1u << BP_VECTOR;
7ffd92c5 1630 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1631 eb = ~0;
089d034e 1632 if (enable_ept)
1439442c 1633 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1634 if (vcpu->fpu_active)
1635 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1636
1637 /* When we are running a nested L2 guest and L1 specified for it a
1638 * certain exception bitmap, we must trap the same exceptions and pass
1639 * them to L1. When running L2, we will only handle the exceptions
1640 * specified above if L1 did not want them.
1641 */
1642 if (is_guest_mode(vcpu))
1643 eb |= get_vmcs12(vcpu)->exception_bitmap;
1644
abd3f2d6
AK		 1645 vmcs_write32(EXCEPTION_BITMAP, eb);
1646}
1647
2961e876
GN		 1648static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1649 unsigned long entry, unsigned long exit)
8bf00a52 1650{
2961e876
GN		 1651 vm_entry_controls_clearbit(vmx, entry);
1652 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1653}
1654
61d2ef2c
AK		 1655static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1656{
1657 unsigned i;
1658 struct msr_autoload *m = &vmx->msr_autoload;
1659
8bf00a52
GN		 1660 switch (msr) {
1661 case MSR_EFER:
1662 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1663 clear_atomic_switch_msr_special(vmx,
1664 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1665 VM_EXIT_LOAD_IA32_EFER);
1666 return;
1667 }
1668 break;
1669 case MSR_CORE_PERF_GLOBAL_CTRL:
1670 if (cpu_has_load_perf_global_ctrl) {
2961e876 1671 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1672 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1673 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1674 return;
1675 }
1676 break;
110312c8
AK		 1677 }
1678
61d2ef2c
AK		 1679 for (i = 0; i < m->nr; ++i)
1680 if (m->guest[i].index == msr)
1681 break;
1682
1683 if (i == m->nr)
1684 return;
1685 --m->nr;
1686 m->guest[i] = m->guest[m->nr];
1687 m->host[i] = m->host[m->nr];
1688 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1689 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1690}
1691
2961e876
GN		 1692static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1693 unsigned long entry, unsigned long exit,
1694 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1695 u64 guest_val, u64 host_val)
8bf00a52
GN		 1696{
1697 vmcs_write64(guest_val_vmcs, guest_val);
1698 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1699 vm_entry_controls_setbit(vmx, entry);
1700 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1701}
1702
61d2ef2c
AK		 1703static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1704 u64 guest_val, u64 host_val)
1705{
1706 unsigned i;
1707 struct msr_autoload *m = &vmx->msr_autoload;
1708
8bf00a52
GN		 1709 switch (msr) {
1710 case MSR_EFER:
1711 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1712 add_atomic_switch_msr_special(vmx,
1713 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1714 VM_EXIT_LOAD_IA32_EFER,
1715 GUEST_IA32_EFER,
1716 HOST_IA32_EFER,
1717 guest_val, host_val);
1718 return;
1719 }
1720 break;
1721 case MSR_CORE_PERF_GLOBAL_CTRL:
1722 if (cpu_has_load_perf_global_ctrl) {
2961e876 1723 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1724 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1725 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1726 GUEST_IA32_PERF_GLOBAL_CTRL,
1727 HOST_IA32_PERF_GLOBAL_CTRL,
1728 guest_val, host_val);
1729 return;
1730 }
1731 break;
110312c8
AK		 1732 }
1733
61d2ef2c
AK		 1734 for (i = 0; i < m->nr; ++i)
1735 if (m->guest[i].index == msr)
1736 break;
1737
e7fc6f93 1738 if (i == NR_AUTOLOAD_MSRS) {
60266204 1739 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1740 "Can't add msr %x\n", msr);
1741 return;
1742 } else if (i == m->nr) {
61d2ef2c
AK		 1743 ++m->nr;
1744 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1745 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1746 }
1747
1748 m->guest[i].index = msr;
1749 m->guest[i].value = guest_val;
1750 m->host[i].index = msr;
1751 m->host[i].value = host_val;
1752}
1753
33ed6329
AK		 1754static void reload_tss(void)
1755{
33ed6329
AK		 1756 /*
1757 * VT restores TR but not its size. Useless.
1758 */
89cbc767 1759 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1760 struct desc_struct *descs;
33ed6329 1761
d359192f 1762 descs = (void *)gdt->address;
33ed6329
AK		 1763 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1764 load_TR_desc();
33ed6329
AK		 1765}
1766
92c0d900 1767static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1768{
3a34a881 1769 u64 guest_efer;
51c6cf66
AK		 1770 u64 ignore_bits;
1771
f6801dff 1772 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1773
51c6cf66 1774 /*
0fa06071 1775 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1776 * outside long mode
1777 */
1778 ignore_bits = EFER_NX | EFER_SCE;
1779#ifdef CONFIG_X86_64
1780 ignore_bits |= EFER_LMA | EFER_LME;
1781 /* SCE is meaningful only in long mode on Intel */
1782 if (guest_efer & EFER_LMA)
1783 ignore_bits &= ~(u64)EFER_SCE;
1784#endif
51c6cf66
AK		 1785 guest_efer &= ~ignore_bits;
1786 guest_efer |= host_efer & ignore_bits;
26bb0981 1787 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1788 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1789
1790 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1791
1792 /*
1793 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1794 * On CPUs that support "load IA32_EFER", always switch EFER
1795 * atomically, since it's faster than switching it manually.
1796 */
1797 if (cpu_has_load_ia32_efer ||
1798 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1799 guest_efer = vmx->vcpu.arch.efer;
1800 if (!(guest_efer & EFER_LMA))
1801 guest_efer &= ~EFER_LME;
54b98bff
AL		 1802 if (guest_efer != host_efer)
1803 add_atomic_switch_msr(vmx, MSR_EFER,
1804 guest_efer, host_efer);
84ad33ef
AK		 1805 return false;
1806 }
1807
26bb0981 1808 return true;
51c6cf66
AK		 1809}
1810
2d49ec72
GN		 1811static unsigned long segment_base(u16 selector)
1812{
89cbc767 1813 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1814 struct desc_struct *d;
1815 unsigned long table_base;
1816 unsigned long v;
1817
1818 if (!(selector & ~3))
1819 return 0;
1820
d359192f 1821 table_base = gdt->address;
2d49ec72
GN		 1822
1823 if (selector & 4) { /* from ldt */
1824 u16 ldt_selector = kvm_read_ldt();
1825
1826 if (!(ldt_selector & ~3))
1827 return 0;
1828
1829 table_base = segment_base(ldt_selector);
1830 }
1831 d = (struct desc_struct *)(table_base + (selector & ~7));
1832 v = get_desc_base(d);
1833#ifdef CONFIG_X86_64
1834 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1835 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1836#endif
1837 return v;
1838}
1839
1840static inline unsigned long kvm_read_tr_base(void)
1841{
1842 u16 tr;
1843 asm("str %0" : "=g"(tr));
1844 return segment_base(tr);
1845}
1846
04d2cc77 1847static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1848{
04d2cc77 1849 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1850 int i;
04d2cc77 1851
a2fa3e9f 1852 if (vmx->host_state.loaded)
33ed6329
AK		 1853 return;
1854
a2fa3e9f 1855 vmx->host_state.loaded = 1;
33ed6329
AK		 1856 /*
1857 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1858 * allow segment selectors with cpl > 0 or ti == 1.
1859 */
d6e88aec 1860 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1861 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1862 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1863 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1864 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1865 vmx->host_state.fs_reload_needed = 0;
1866 } else {
33ed6329 1867 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1868 vmx->host_state.fs_reload_needed = 1;
33ed6329 1869 }
9581d442 1870 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1871 if (!(vmx->host_state.gs_sel & 7))
1872 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1873 else {
1874 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1875 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1876 }
1877
b2da15ac
AK		 1878#ifdef CONFIG_X86_64
1879 savesegment(ds, vmx->host_state.ds_sel);
1880 savesegment(es, vmx->host_state.es_sel);
1881#endif
1882
33ed6329
AK		 1883#ifdef CONFIG_X86_64
1884 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1885 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1886#else
a2fa3e9f
GH		 1887 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1888 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1889#endif
707c0874
AK		 1890
1891#ifdef CONFIG_X86_64
c8770e7b
AK		 1892 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1893 if (is_long_mode(&vmx->vcpu))
44ea2b17 1894 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1895#endif
da8999d3
LJ		 1896 if (boot_cpu_has(X86_FEATURE_MPX))
1897 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1898 for (i = 0; i < vmx->save_nmsrs; ++i)
1899 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1900 vmx->guest_msrs[i].data,
1901 vmx->guest_msrs[i].mask);
33ed6329
AK		 1902}
1903
a9b21b62 1904static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1905{
a2fa3e9f 1906 if (!vmx->host_state.loaded)
33ed6329
AK		 1907 return;
1908
e1beb1d3 1909 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1910 vmx->host_state.loaded = 0;
c8770e7b
AK		 1911#ifdef CONFIG_X86_64
1912 if (is_long_mode(&vmx->vcpu))
1913 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1914#endif
152d3f2f 1915 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1916 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1917#ifdef CONFIG_X86_64
9581d442 1918 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1919#else
1920 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1921#endif
33ed6329 1922 }
0a77fe4c
AK		 1923 if (vmx->host_state.fs_reload_needed)
1924 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1925#ifdef CONFIG_X86_64
1926 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1927 loadsegment(ds, vmx->host_state.ds_sel);
1928 loadsegment(es, vmx->host_state.es_sel);
1929 }
b2da15ac 1930#endif
152d3f2f 1931 reload_tss();
44ea2b17 1932#ifdef CONFIG_X86_64
c8770e7b 1933 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1934#endif
da8999d3
LJ		 1935 if (vmx->host_state.msr_host_bndcfgs)
1936 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1937 /*
1938 * If the FPU is not active (through the host task or
1939 * the guest vcpu), then restore the cr0.TS bit.
1940 */
3c6dffa9 1941 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
b1a74bf8 1942 stts();
89cbc767 1943 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1944}
1945
a9b21b62
AK		 1946static void vmx_load_host_state(struct vcpu_vmx *vmx)
1947{
1948 preempt_disable();
1949 __vmx_load_host_state(vmx);
1950 preempt_enable();
1951}
1952
28b835d6
FW		 1953static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1954{
1955 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1956 struct pi_desc old, new;
1957 unsigned int dest;
1958
1959 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1960 !irq_remapping_cap(IRQ_POSTING_CAP))
1961 return;
1962
1963 do {
1964 old.control = new.control = pi_desc->control;
1965
1966 /*
1967 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
1968 * are two possible cases:
1969 * 1. After running 'pre_block', context switch
1970 * happened. For this case, 'sn' was set in
1971 * vmx_vcpu_put(), so we need to clear it here.
1972 * 2. After running 'pre_block', we were blocked,
1973 * and woken up by some other guy. For this case,
1974 * we don't need to do anything, 'pi_post_block'
1975 * will do everything for us. However, we cannot
1976 * check whether it is case #1 or case #2 here
1977 * (maybe, not needed), so we also clear sn here,
1978 * I think it is not a big deal.
1979 */
1980 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
1981 if (vcpu->cpu != cpu) {
1982 dest = cpu_physical_id(cpu);
1983
1984 if (x2apic_enabled())
1985 new.ndst = dest;
1986 else
1987 new.ndst = (dest << 8) & 0xFF00;
1988 }
1989
1990 /* set 'NV' to 'notification vector' */
1991 new.nv = POSTED_INTR_VECTOR;
1992 }
1993
1994 /* Allow posting non-urgent interrupts */
1995 new.sn = 0;
1996 } while (cmpxchg(&pi_desc->control, old.control,
1997 new.control) != old.control);
1998}
6aa8b732
AK		 1999/*
2000 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2001 * vcpu mutex is already taken.
2002 */
15ad7146 2003static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 2004{
a2fa3e9f 2005 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 2006 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 2007
4610c9cc
DX		 2008 if (!vmm_exclusive)
2009 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 2010 else if (vmx->loaded_vmcs->cpu != cpu)
2011 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 2012
d462b819
NHE		 2013 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2014 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2015 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 2016 }
2017
d462b819 2018 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 2019 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 2020 unsigned long sysenter_esp;
2021
a8eeb04a 2022 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 2023 local_irq_disable();
8f536b76 2024 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 2025
2026 /*
2027 * Read loaded_vmcs->cpu should be before fetching
2028 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2029 * See the comments in __loaded_vmcs_clear().
2030 */
2031 smp_rmb();
2032
d462b819
NHE		 2033 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2034 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 2035 crash_enable_local_vmclear(cpu);
92fe13be
DX		 2036 local_irq_enable();
2037
6aa8b732
AK		 2038 /*
2039 * Linux uses per-cpu TSS and GDT, so set these when switching
2040 * processors.
2041 */
d6e88aec 2042 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 2043 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 2044
2045 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2046 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 2047 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 2048 }
28b835d6
FW		 2049
2050 vmx_vcpu_pi_load(vcpu, cpu);
2051}
2052
2053static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2054{
2055 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2056
2057 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2058 !irq_remapping_cap(IRQ_POSTING_CAP))
2059 return;
2060
2061 /* Set SN when the vCPU is preempted */
2062 if (vcpu->preempted)
2063 pi_set_sn(pi_desc);
6aa8b732
AK		 2064}
2065
2066static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2067{
28b835d6
FW		 2068 vmx_vcpu_pi_put(vcpu);
2069
a9b21b62 2070 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 2071 if (!vmm_exclusive) {
d462b819
NHE		 2072 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2073 vcpu->cpu = -1;
4610c9cc
DX		 2074 kvm_cpu_vmxoff();
2075 }
6aa8b732
AK		 2076}
2077
5fd86fcf
AK		 2078static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2079{
81231c69
AK		 2080 ulong cr0;
2081
5fd86fcf
AK		 2082 if (vcpu->fpu_active)
2083 return;
2084 vcpu->fpu_active = 1;
81231c69
AK		 2085 cr0 = vmcs_readl(GUEST_CR0);
2086 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2087 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2088 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 2089 update_exception_bitmap(vcpu);
edcafe3c 2090 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 2091 if (is_guest_mode(vcpu))
2092 vcpu->arch.cr0_guest_owned_bits &=
2093 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 2094 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 2095}
2096
edcafe3c
AK		 2097static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2098
fe3ef05c
NHE		 2099/*
2100 * Return the cr0 value that a nested guest would read. This is a combination
2101 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2102 * its hypervisor (cr0_read_shadow).
2103 */
2104static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2105{
2106 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2107 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2108}
2109static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2110{
2111 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2112 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2113}
2114
5fd86fcf
AK		 2115static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2116{
36cf24e0
NHE		 2117 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2118 * set this *before* calling this function.
2119 */
edcafe3c 2120 vmx_decache_cr0_guest_bits(vcpu);
81231c69 2121 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 2122 update_exception_bitmap(vcpu);
edcafe3c
AK		 2123 vcpu->arch.cr0_guest_owned_bits = 0;
2124 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 2125 if (is_guest_mode(vcpu)) {
2126 /*
2127 * L1's specified read shadow might not contain the TS bit,
2128 * so now that we turned on shadowing of this bit, we need to
2129 * set this bit of the shadow. Like in nested_vmx_run we need
2130 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2131 * up-to-date here because we just decached cr0.TS (and we'll
2132 * only update vmcs12->guest_cr0 on nested exit).
2133 */
2134 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2135 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2136 (vcpu->arch.cr0 & X86_CR0_TS);
2137 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2138 } else
2139 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2140}
2141
6aa8b732
AK		 2142static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2143{
78ac8b47 2144 unsigned long rflags, save_rflags;
345dcaa8 2145
6de12732
AK		 2146 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2147 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2148 rflags = vmcs_readl(GUEST_RFLAGS);
2149 if (to_vmx(vcpu)->rmode.vm86_active) {
2150 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2151 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2152 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2153 }
2154 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2155 }
6de12732 2156 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2157}
2158
2159static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2160{
6de12732
AK		 2161 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2162 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2163 if (to_vmx(vcpu)->rmode.vm86_active) {
2164 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2165 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2166 }
6aa8b732
AK		 2167 vmcs_writel(GUEST_RFLAGS, rflags);
2168}
2169
37ccdcbe 2170static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2171{
2172 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2173 int ret = 0;
2174
2175 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2176 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2177 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2178 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2179
37ccdcbe 2180 return ret;
2809f5d2
GC		 2181}
2182
2183static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2184{
2185 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2186 u32 interruptibility = interruptibility_old;
2187
2188 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2189
48005f64 2190 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2191 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2192 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2193 interruptibility |= GUEST_INTR_STATE_STI;
2194
2195 if ((interruptibility != interruptibility_old))
2196 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2197}
2198
6aa8b732
AK		 2199static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2200{
2201 unsigned long rip;
6aa8b732 2202
5fdbf976 2203 rip = kvm_rip_read(vcpu);
6aa8b732 2204 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2205 kvm_rip_write(vcpu, rip);
6aa8b732 2206
2809f5d2
GC		 2207 /* skipping an emulated instruction also counts */
2208 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2209}
2210
0b6ac343
NHE		 2211/*
2212 * KVM wants to inject page-faults which it got to the guest. This function
2213 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2214 */
e011c663 2215static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2216{
2217 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2218
e011c663 2219 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2220 return 0;
2221
533558bc
JK		 2222 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2223 vmcs_read32(VM_EXIT_INTR_INFO),
2224 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2225 return 1;
2226}
2227
298101da 2228static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2229 bool has_error_code, u32 error_code,
2230 bool reinject)
298101da 2231{
77ab6db0 2232 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2233 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2234
e011c663
GN		 2235 if (!reinject && is_guest_mode(vcpu) &&
2236 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2237 return;
2238
8ab2d2e2 2239 if (has_error_code) {
77ab6db0 2240 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2241 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2242 }
77ab6db0 2243
7ffd92c5 2244 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2245 int inc_eip = 0;
2246 if (kvm_exception_is_soft(nr))
2247 inc_eip = vcpu->arch.event_exit_inst_len;
2248 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2249 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2250 return;
2251 }
2252
66fd3f7f
GN		 2253 if (kvm_exception_is_soft(nr)) {
2254 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2255 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2256 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2257 } else
2258 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2259
2260 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2261}
2262
4e47c7a6
SY		 2263static bool vmx_rdtscp_supported(void)
2264{
2265 return cpu_has_vmx_rdtscp();
2266}
2267
ad756a16
MJ		 2268static bool vmx_invpcid_supported(void)
2269{
2270 return cpu_has_vmx_invpcid() && enable_ept;
2271}
2272
a75beee6
ED		 2273/*
2274 * Swap MSR entry in host/guest MSR entry array.
2275 */
8b9cf98c 2276static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2277{
26bb0981 2278 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2279
2280 tmp = vmx->guest_msrs[to];
2281 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2282 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2283}
2284
8d14695f
YZ		 2285static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2286{
2287 unsigned long *msr_bitmap;
2288
670125bd
WV		 2289 if (is_guest_mode(vcpu))
2290 msr_bitmap = vmx_msr_bitmap_nested;
8a9781f7 2291 else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
8d14695f
YZ		 2292 if (is_long_mode(vcpu))
2293 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2294 else
2295 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2296 } else {
2297 if (is_long_mode(vcpu))
2298 msr_bitmap = vmx_msr_bitmap_longmode;
2299 else
2300 msr_bitmap = vmx_msr_bitmap_legacy;
2301 }
2302
2303 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2304}
2305
e38aea3e
AK		 2306/*
2307 * Set up the vmcs to automatically save and restore system
2308 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2309 * mode, as fiddling with msrs is very expensive.
2310 */
8b9cf98c 2311static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2312{
26bb0981 2313 int save_nmsrs, index;
e38aea3e 2314
a75beee6
ED		 2315 save_nmsrs = 0;
2316#ifdef CONFIG_X86_64
8b9cf98c 2317 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2318 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2319 if (index >= 0)
8b9cf98c
RR		 2320 move_msr_up(vmx, index, save_nmsrs++);
2321 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2322 if (index >= 0)
8b9cf98c
RR		 2323 move_msr_up(vmx, index, save_nmsrs++);
2324 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2325 if (index >= 0)
8b9cf98c 2326 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6 2327 index = __find_msr_index(vmx, MSR_TSC_AUX);
1cea0ce6 2328 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
4e47c7a6 2329 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2330 /*
8c06585d 2331 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2332 * if efer.sce is enabled.
2333 */
8c06585d 2334 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2335 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2336 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2337 }
2338#endif
92c0d900
AK		 2339 index = __find_msr_index(vmx, MSR_EFER);
2340 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2341 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2342
26bb0981 2343 vmx->save_nmsrs = save_nmsrs;
5897297b 2344
8d14695f
YZ		 2345 if (cpu_has_vmx_msr_bitmap())
2346 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2347}
2348
6aa8b732
AK		 2349/*
2350 * reads and returns guest's timestamp counter "register"
2351 * guest_tsc = host_tsc + tsc_offset -- 21.3
2352 */
2353static u64 guest_read_tsc(void)
2354{
2355 u64 host_tsc, tsc_offset;
2356
4ea1636b 2357 host_tsc = rdtsc();
6aa8b732
AK		 2358 tsc_offset = vmcs_read64(TSC_OFFSET);
2359 return host_tsc + tsc_offset;
2360}
2361
d5c1785d
NHE		 2362/*
2363 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2364 * counter, even if a nested guest (L2) is currently running.
2365 */
48d89b92 2366static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2367{
886b470c 2368 u64 tsc_offset;
d5c1785d 2369
d5c1785d
NHE		 2370 tsc_offset = is_guest_mode(vcpu) ?
2371 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2372 vmcs_read64(TSC_OFFSET);
2373 return host_tsc + tsc_offset;
2374}
2375
4051b188 2376/*
cc578287
ZA		 2377 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2378 * software catchup for faster rates on slower CPUs.
4051b188 2379 */
cc578287 2380static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2381{
cc578287
ZA		 2382 if (!scale)
2383 return;
2384
2385 if (user_tsc_khz > tsc_khz) {
2386 vcpu->arch.tsc_catchup = 1;
2387 vcpu->arch.tsc_always_catchup = 1;
2388 } else
2389 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2390}
2391
ba904635
WA		 2392static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2393{
2394 return vmcs_read64(TSC_OFFSET);
2395}
2396
6aa8b732 2397/*
99e3e30a 2398 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2399 */
99e3e30a 2400static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2401{
27fc51b2 2402 if (is_guest_mode(vcpu)) {
7991825b 2403 /*
27fc51b2
NHE		 2404 * We're here if L1 chose not to trap WRMSR to TSC. According
2405 * to the spec, this should set L1's TSC; The offset that L1
2406 * set for L2 remains unchanged, and still needs to be added
2407 * to the newly set TSC to get L2's TSC.
7991825b 2408 */
27fc51b2
NHE		 2409 struct vmcs12 *vmcs12;
2410 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2411 /* recalculate vmcs02.TSC_OFFSET: */
2412 vmcs12 = get_vmcs12(vcpu);
2413 vmcs_write64(TSC_OFFSET, offset +
2414 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2415 vmcs12->tsc_offset : 0));
2416 } else {
489223ed
YY		 2417 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2418 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2419 vmcs_write64(TSC_OFFSET, offset);
2420 }
6aa8b732
AK		 2421}
2422
f1e2b260 2423static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2424{
2425 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2426
e48672fa 2427 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2428 if (is_guest_mode(vcpu)) {
2429 /* Even when running L2, the adjustment needs to apply to L1 */
2430 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2431 } else
2432 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2433 offset + adjustment);
e48672fa
ZA		 2434}
2435
857e4099
JR		 2436static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2437{
4ea1636b 2438 return target_tsc - rdtsc();
857e4099
JR		 2439}
2440
801d3424
NHE		 2441static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2442{
2443 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2444 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2445}
2446
2447/*
2448 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2449 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2450 * all guests if the "nested" module option is off, and can also be disabled
2451 * for a single guest by disabling its VMX cpuid bit.
2452 */
2453static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2454{
2455 return nested && guest_cpuid_has_vmx(vcpu);
2456}
2457
b87a51ae
NHE		 2458/*
2459 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2460 * returned for the various VMX controls MSRs when nested VMX is enabled.
2461 * The same values should also be used to verify that vmcs12 control fields are
2462 * valid during nested entry from L1 to L2.
2463 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2464 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2465 * bit in the high half is on if the corresponding bit in the control field
2466 * may be on. See also vmx_control_verify().
b87a51ae 2467 */
b9c237bb 2468static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2469{
2470 /*
2471 * Note that as a general rule, the high half of the MSRs (bits in
2472 * the control fields which may be 1) should be initialized by the
2473 * intersection of the underlying hardware's MSR (i.e., features which
2474 * can be supported) and the list of features we want to expose -
2475 * because they are known to be properly supported in our code.
2476 * Also, usually, the low half of the MSRs (bits which must be 1) can
2477 * be set to 0, meaning that L1 may turn off any of these bits. The
2478 * reason is that if one of these bits is necessary, it will appear
2479 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2480 * fields of vmcs01 and vmcs02, will turn these bits off - and
2481 * nested_vmx_exit_handled() will not pass related exits to L1.
2482 * These rules have exceptions below.
2483 */
2484
2485 /* pin-based controls */
eabeaacc 2486 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2487 vmx->nested.nested_vmx_pinbased_ctls_low,
2488 vmx->nested.nested_vmx_pinbased_ctls_high);
2489 vmx->nested.nested_vmx_pinbased_ctls_low |=
2490 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2491 vmx->nested.nested_vmx_pinbased_ctls_high &=
2492 PIN_BASED_EXT_INTR_MASK |
2493 PIN_BASED_NMI_EXITING |
2494 PIN_BASED_VIRTUAL_NMIS;
2495 vmx->nested.nested_vmx_pinbased_ctls_high |=
2496 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2497 PIN_BASED_VMX_PREEMPTION_TIMER;
35754c98 2498 if (vmx_cpu_uses_apicv(&vmx->vcpu))
705699a1
WV		 2499 vmx->nested.nested_vmx_pinbased_ctls_high |=
2500 PIN_BASED_POSTED_INTR;
b87a51ae 2501
3dbcd8da 2502 /* exit controls */
c0dfee58 2503 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2504 vmx->nested.nested_vmx_exit_ctls_low,
2505 vmx->nested.nested_vmx_exit_ctls_high);
2506 vmx->nested.nested_vmx_exit_ctls_low =
2507 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2508
b9c237bb 2509 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2510#ifdef CONFIG_X86_64
c0dfee58 2511 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2512#endif
f4124500 2513 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2514 vmx->nested.nested_vmx_exit_ctls_high |=
2515 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2516 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2517 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2518
36be0b9d 2519 if (vmx_mpx_supported())
b9c237bb 2520 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2521
2996fca0 2522 /* We support free control of debug control saving. */
b9c237bb
WV		 2523 vmx->nested.nested_vmx_true_exit_ctls_low =
2524 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2525 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2526
b87a51ae
NHE		 2527 /* entry controls */
2528 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2529 vmx->nested.nested_vmx_entry_ctls_low,
2530 vmx->nested.nested_vmx_entry_ctls_high);
2531 vmx->nested.nested_vmx_entry_ctls_low =
2532 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2533 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2534#ifdef CONFIG_X86_64
2535 VM_ENTRY_IA32E_MODE |
2536#endif
2537 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2538 vmx->nested.nested_vmx_entry_ctls_high |=
2539 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2540 if (vmx_mpx_supported())
b9c237bb 2541 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2542
2996fca0 2543 /* We support free control of debug control loading. */
b9c237bb
WV		 2544 vmx->nested.nested_vmx_true_entry_ctls_low =
2545 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2546 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2547
b87a51ae
NHE		 2548 /* cpu-based controls */
2549 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2550 vmx->nested.nested_vmx_procbased_ctls_low,
2551 vmx->nested.nested_vmx_procbased_ctls_high);
2552 vmx->nested.nested_vmx_procbased_ctls_low =
2553 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2554 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2555 CPU_BASED_VIRTUAL_INTR_PENDING |
2556 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2557 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2558 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2559 CPU_BASED_CR3_STORE_EXITING |
2560#ifdef CONFIG_X86_64
2561 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2562#endif
2563 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD		 2564 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2565 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2566 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2567 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE		 2568 /*
2569 * We can allow some features even when not supported by the
2570 * hardware. For example, L1 can specify an MSR bitmap - and we
2571 * can use it to avoid exits to L1 - even when L0 runs L2
2572 * without MSR bitmaps.
2573 */
b9c237bb
WV		 2574 vmx->nested.nested_vmx_procbased_ctls_high |=
2575 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2576 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2577
3dcdf3ec 2578 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2579 vmx->nested.nested_vmx_true_procbased_ctls_low =
2580 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2581 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2582
b87a51ae
NHE		 2583 /* secondary cpu-based controls */
2584 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2585 vmx->nested.nested_vmx_secondary_ctls_low,
2586 vmx->nested.nested_vmx_secondary_ctls_high);
2587 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2588 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2589 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2590 SECONDARY_EXEC_RDTSCP |
f2b93280 2591 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2592 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2593 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7 2594 SECONDARY_EXEC_WBINVD_EXITING |
8b3e34e4
XG		 2595 SECONDARY_EXEC_XSAVES |
2596 SECONDARY_EXEC_PCOMMIT;
c18911a2 2597
afa61f75
NHE		 2598 if (enable_ept) {
2599 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2600 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2601 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2602 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2603 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2604 VMX_EPT_INVEPT_BIT;
b9c237bb 2605 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2606 /*
4b855078
BD		 2607 * For nested guests, we don't do anything specific
2608 * for single context invalidation. Hence, only advertise
2609 * support for global context invalidation.
afa61f75 2610 */
b9c237bb 2611 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2612 } else
b9c237bb 2613 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2614
0790ec17
RK		 2615 if (enable_unrestricted_guest)
2616 vmx->nested.nested_vmx_secondary_ctls_high |=
2617 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2618
c18911a2 2619 /* miscellaneous data */
b9c237bb
WV		 2620 rdmsr(MSR_IA32_VMX_MISC,
2621 vmx->nested.nested_vmx_misc_low,
2622 vmx->nested.nested_vmx_misc_high);
2623 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2624 vmx->nested.nested_vmx_misc_low |=
2625 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2626 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2627 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2628}
2629
2630static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2631{
2632 /*
2633 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2634 */
2635 return ((control & high) | low) == control;
2636}
2637
2638static inline u64 vmx_control_msr(u32 low, u32 high)
2639{
2640 return low | ((u64)high << 32);
2641}
2642
cae50139 2643/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2644static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2645{
b9c237bb
WV		 2646 struct vcpu_vmx *vmx = to_vmx(vcpu);
2647
b87a51ae 2648 switch (msr_index) {
b87a51ae
NHE		 2649 case MSR_IA32_VMX_BASIC:
2650 /*
2651 * This MSR reports some information about VMX support. We
2652 * should return information about the VMX we emulate for the
2653 * guest, and the VMCS structure we give it - not about the
2654 * VMX support of the underlying hardware.
2655 */
3dbcd8da 2656 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2657 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2658 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2659 break;
2660 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2661 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2662 *pdata = vmx_control_msr(
2663 vmx->nested.nested_vmx_pinbased_ctls_low,
2664 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2665 break;
2666 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2667 *pdata = vmx_control_msr(
2668 vmx->nested.nested_vmx_true_procbased_ctls_low,
2669 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2670 break;
b87a51ae 2671 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2672 *pdata = vmx_control_msr(
2673 vmx->nested.nested_vmx_procbased_ctls_low,
2674 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2675 break;
2676 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2677 *pdata = vmx_control_msr(
2678 vmx->nested.nested_vmx_true_exit_ctls_low,
2679 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2680 break;
b87a51ae 2681 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2682 *pdata = vmx_control_msr(
2683 vmx->nested.nested_vmx_exit_ctls_low,
2684 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2685 break;
2686 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2687 *pdata = vmx_control_msr(
2688 vmx->nested.nested_vmx_true_entry_ctls_low,
2689 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2690 break;
b87a51ae 2691 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2692 *pdata = vmx_control_msr(
2693 vmx->nested.nested_vmx_entry_ctls_low,
2694 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2695 break;
2696 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2697 *pdata = vmx_control_msr(
2698 vmx->nested.nested_vmx_misc_low,
2699 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2700 break;
2701 /*
2702 * These MSRs specify bits which the guest must keep fixed (on or off)
2703 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2704 * We picked the standard core2 setting.
2705 */
2706#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2707#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2708 case MSR_IA32_VMX_CR0_FIXED0:
2709 *pdata = VMXON_CR0_ALWAYSON;
2710 break;
2711 case MSR_IA32_VMX_CR0_FIXED1:
2712 *pdata = -1ULL;
2713 break;
2714 case MSR_IA32_VMX_CR4_FIXED0:
2715 *pdata = VMXON_CR4_ALWAYSON;
2716 break;
2717 case MSR_IA32_VMX_CR4_FIXED1:
2718 *pdata = -1ULL;
2719 break;
2720 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2721 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2722 break;
2723 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2724 *pdata = vmx_control_msr(
2725 vmx->nested.nested_vmx_secondary_ctls_low,
2726 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2727 break;
2728 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2729 /* Currently, no nested vpid support */
b9c237bb 2730 *pdata = vmx->nested.nested_vmx_ept_caps;
b87a51ae
NHE		 2731 break;
2732 default:
b87a51ae 2733 return 1;
b3897a49
NHE		 2734 }
2735
b87a51ae
NHE		 2736 return 0;
2737}
2738
6aa8b732
AK		 2739/*
2740 * Reads an msr value (of 'msr_index') into 'pdata'.
2741 * Returns 0 on success, non-0 otherwise.
2742 * Assumes vcpu_load() was already called.
2743 */
609e36d3 2744static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2745{
26bb0981 2746 struct shared_msr_entry *msr;
6aa8b732 2747
609e36d3 2748 switch (msr_info->index) {
05b3e0c2 2749#ifdef CONFIG_X86_64
6aa8b732 2750 case MSR_FS_BASE:
609e36d3 2751 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK		 2752 break;
2753 case MSR_GS_BASE:
609e36d3 2754 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 2755 break;
44ea2b17
AK		 2756 case MSR_KERNEL_GS_BASE:
2757 vmx_load_host_state(to_vmx(vcpu));
609e36d3 2758 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 2759 break;
26bb0981 2760#endif
6aa8b732 2761 case MSR_EFER:
609e36d3 2762 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 2763 case MSR_IA32_TSC:
609e36d3 2764 msr_info->data = guest_read_tsc();
6aa8b732
AK		 2765 break;
2766 case MSR_IA32_SYSENTER_CS:
609e36d3 2767 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 2768 break;
2769 case MSR_IA32_SYSENTER_EIP:
609e36d3 2770 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2771 break;
2772 case MSR_IA32_SYSENTER_ESP:
609e36d3 2773 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2774 break;
0dd376e7 2775 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2776 if (!vmx_mpx_supported())
2777 return 1;
609e36d3 2778 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 2779 break;
cae50139
JK		 2780 case MSR_IA32_FEATURE_CONTROL:
2781 if (!nested_vmx_allowed(vcpu))
2782 return 1;
609e36d3 2783 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
cae50139
JK		 2784 break;
2785 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2786 if (!nested_vmx_allowed(vcpu))
2787 return 1;
609e36d3 2788 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL		 2789 case MSR_IA32_XSS:
2790 if (!vmx_xsaves_supported())
2791 return 1;
609e36d3 2792 msr_info->data = vcpu->arch.ia32_xss;
20300099 2793 break;
4e47c7a6 2794 case MSR_TSC_AUX:
1cea0ce6 2795 if (!guest_cpuid_has_rdtscp(vcpu))
4e47c7a6
SY		 2796 return 1;
2797 /* Otherwise falls through */
6aa8b732 2798 default:
609e36d3 2799 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 2800 if (msr) {
609e36d3 2801 msr_info->data = msr->data;
3bab1f5d 2802 break;
6aa8b732 2803 }
609e36d3 2804 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2805 }
2806
6aa8b732
AK		 2807 return 0;
2808}
2809
cae50139
JK		 2810static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2811
6aa8b732
AK		 2812/*
2813 * Writes msr value into into the appropriate "register".
2814 * Returns 0 on success, non-0 otherwise.
2815 * Assumes vcpu_load() was already called.
2816 */
8fe8ab46 2817static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2818{
a2fa3e9f 2819 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2820 struct shared_msr_entry *msr;
2cc51560 2821 int ret = 0;
8fe8ab46
WA		 2822 u32 msr_index = msr_info->index;
2823 u64 data = msr_info->data;
2cc51560 2824
6aa8b732 2825 switch (msr_index) {
3bab1f5d 2826 case MSR_EFER:
8fe8ab46 2827 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2828 break;
16175a79 2829#ifdef CONFIG_X86_64
6aa8b732 2830 case MSR_FS_BASE:
2fb92db1 2831 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2832 vmcs_writel(GUEST_FS_BASE, data);
2833 break;
2834 case MSR_GS_BASE:
2fb92db1 2835 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2836 vmcs_writel(GUEST_GS_BASE, data);
2837 break;
44ea2b17
AK		 2838 case MSR_KERNEL_GS_BASE:
2839 vmx_load_host_state(vmx);
2840 vmx->msr_guest_kernel_gs_base = data;
2841 break;
6aa8b732
AK		 2842#endif
2843 case MSR_IA32_SYSENTER_CS:
2844 vmcs_write32(GUEST_SYSENTER_CS, data);
2845 break;
2846 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2847 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2848 break;
2849 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2850 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2851 break;
0dd376e7 2852 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2853 if (!vmx_mpx_supported())
2854 return 1;
0dd376e7
LJ		 2855 vmcs_write64(GUEST_BNDCFGS, data);
2856 break;
af24a4e4 2857 case MSR_IA32_TSC:
8fe8ab46 2858 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2859 break;
468d472f
SY		 2860 case MSR_IA32_CR_PAT:
2861 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2862 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2863 return 1;
468d472f
SY		 2864 vmcs_write64(GUEST_IA32_PAT, data);
2865 vcpu->arch.pat = data;
2866 break;
2867 }
8fe8ab46 2868 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2869 break;
ba904635
WA		 2870 case MSR_IA32_TSC_ADJUST:
2871 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2872 break;
cae50139
JK		 2873 case MSR_IA32_FEATURE_CONTROL:
2874 if (!nested_vmx_allowed(vcpu) ||
2875 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2876 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2877 return 1;
2878 vmx->nested.msr_ia32_feature_control = data;
2879 if (msr_info->host_initiated && data == 0)
2880 vmx_leave_nested(vcpu);
2881 break;
2882 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2883 return 1; /* they are read-only */
20300099
WL		 2884 case MSR_IA32_XSS:
2885 if (!vmx_xsaves_supported())
2886 return 1;
2887 /*
2888 * The only supported bit as of Skylake is bit 8, but
2889 * it is not supported on KVM.
2890 */
2891 if (data != 0)
2892 return 1;
2893 vcpu->arch.ia32_xss = data;
2894 if (vcpu->arch.ia32_xss != host_xss)
2895 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2896 vcpu->arch.ia32_xss, host_xss);
2897 else
2898 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2899 break;
4e47c7a6 2900 case MSR_TSC_AUX:
1cea0ce6 2901 if (!guest_cpuid_has_rdtscp(vcpu))
4e47c7a6
SY		 2902 return 1;
2903 /* Check reserved bit, higher 32 bits should be zero */
2904 if ((data >> 32) != 0)
2905 return 1;
2906 /* Otherwise falls through */
6aa8b732 2907 default:
8b9cf98c 2908 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2909 if (msr) {
8b3c3104 2910 u64 old_msr_data = msr->data;
3bab1f5d 2911 msr->data = data;
2225fd56
AK		 2912 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2913 preempt_disable();
8b3c3104
AH		 2914 ret = kvm_set_shared_msr(msr->index, msr->data,
2915 msr->mask);
2225fd56 2916 preempt_enable();
8b3c3104
AH		 2917 if (ret)
2918 msr->data = old_msr_data;
2225fd56 2919 }
3bab1f5d 2920 break;
6aa8b732 2921 }
8fe8ab46 2922 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2923 }
2924
2cc51560 2925 return ret;
6aa8b732
AK		 2926}
2927
5fdbf976 2928static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2929{
5fdbf976
MT		 2930 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2931 switch (reg) {
2932 case VCPU_REGS_RSP:
2933 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2934 break;
2935 case VCPU_REGS_RIP:
2936 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2937 break;
6de4f3ad
AK		 2938 case VCPU_EXREG_PDPTR:
2939 if (enable_ept)
2940 ept_save_pdptrs(vcpu);
2941 break;
5fdbf976
MT		 2942 default:
2943 break;
2944 }
6aa8b732
AK		 2945}
2946
6aa8b732
AK		 2947static __init int cpu_has_kvm_support(void)
2948{
6210e37b 2949 return cpu_has_vmx();
6aa8b732
AK		 2950}
2951
2952static __init int vmx_disabled_by_bios(void)
2953{
2954 u64 msr;
2955
2956 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2957 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2958 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2959 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2960 && tboot_enabled())
2961 return 1;
23f3e991 2962 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2963 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2964 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2965 && !tboot_enabled()) {
2966 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2967 "activate TXT before enabling KVM\n");
cafd6659 2968 return 1;
f9335afe 2969 }
23f3e991
JC		 2970 /* launched w/o TXT and VMX disabled */
2971 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2972 && !tboot_enabled())
2973 return 1;
cafd6659
SW		 2974 }
2975
2976 return 0;
6aa8b732
AK		 2977}
2978
7725b894
DX		 2979static void kvm_cpu_vmxon(u64 addr)
2980{
2981 asm volatile (ASM_VMX_VMXON_RAX
2982 : : "a"(&addr), "m"(addr)
2983 : "memory", "cc");
2984}
2985
13a34e06 2986static int hardware_enable(void)
6aa8b732
AK		 2987{
2988 int cpu = raw_smp_processor_id();
2989 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2990 u64 old, test_bits;
6aa8b732 2991
1e02ce4c 2992 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2993 return -EBUSY;
2994
d462b819 2995 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW		 2996 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2997 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY		 2998
2999 /*
3000 * Now we can enable the vmclear operation in kdump
3001 * since the loaded_vmcss_on_cpu list on this cpu
3002 * has been initialized.
3003 *
3004 * Though the cpu is not in VMX operation now, there
3005 * is no problem to enable the vmclear operation
3006 * for the loaded_vmcss_on_cpu list is empty!
3007 */
3008 crash_enable_local_vmclear(cpu);
3009
6aa8b732 3010 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 3011
3012 test_bits = FEATURE_CONTROL_LOCKED;
3013 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3014 if (tboot_enabled())
3015 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3016
3017 if ((old & test_bits) != test_bits) {
6aa8b732 3018 /* enable and lock */
cafd6659
SW		 3019 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3020 }
375074cc 3021 cr4_set_bits(X86_CR4_VMXE);
10474ae8 3022
4610c9cc
DX		 3023 if (vmm_exclusive) {
3024 kvm_cpu_vmxon(phys_addr);
3025 ept_sync_global();
3026 }
10474ae8 3027
89cbc767 3028 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 3029
10474ae8 3030 return 0;
6aa8b732
AK		 3031}
3032
d462b819 3033static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 3034{
3035 int cpu = raw_smp_processor_id();
d462b819 3036 struct loaded_vmcs *v, *n;
543e4243 3037
d462b819
NHE		 3038 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3039 loaded_vmcss_on_cpu_link)
3040 __loaded_vmcs_clear(v);
543e4243
AK		 3041}
3042
710ff4a8
EH		 3043
3044/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3045 * tricks.
3046 */
3047static void kvm_cpu_vmxoff(void)
6aa8b732 3048{
4ecac3fd 3049 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 3050}
3051
13a34e06 3052static void hardware_disable(void)
710ff4a8 3053{
4610c9cc 3054 if (vmm_exclusive) {
d462b819 3055 vmclear_local_loaded_vmcss();
4610c9cc
DX		 3056 kvm_cpu_vmxoff();
3057 }
375074cc 3058 cr4_clear_bits(X86_CR4_VMXE);
710ff4a8
EH		 3059}
3060
1c3d14fe 3061static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 3062 u32 msr, u32 *result)
1c3d14fe
YS		 3063{
3064 u32 vmx_msr_low, vmx_msr_high;
3065 u32 ctl = ctl_min | ctl_opt;
3066
3067 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3068
3069 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3070 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3071
3072 /* Ensure minimum (required) set of control bits are supported. */
3073 if (ctl_min & ~ctl)
002c7f7c 3074 return -EIO;
1c3d14fe
YS		 3075
3076 *result = ctl;
3077 return 0;
3078}
3079
110312c8
AK		 3080static __init bool allow_1_setting(u32 msr, u32 ctl)
3081{
3082 u32 vmx_msr_low, vmx_msr_high;
3083
3084 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3085 return vmx_msr_high & ctl;
3086}
3087
002c7f7c 3088static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 3089{
3090 u32 vmx_msr_low, vmx_msr_high;
d56f546d 3091 u32 min, opt, min2, opt2;
1c3d14fe
YS		 3092 u32 _pin_based_exec_control = 0;
3093 u32 _cpu_based_exec_control = 0;
f78e0e2e 3094 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 3095 u32 _vmexit_control = 0;
3096 u32 _vmentry_control = 0;
3097
10166744 3098 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 3099#ifdef CONFIG_X86_64
3100 CPU_BASED_CR8_LOAD_EXITING |
3101 CPU_BASED_CR8_STORE_EXITING |
3102#endif
d56f546d
SY		 3103 CPU_BASED_CR3_LOAD_EXITING |
3104 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 3105 CPU_BASED_USE_IO_BITMAPS |
3106 CPU_BASED_MOV_DR_EXITING |
a7052897 3107 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 3108 CPU_BASED_MWAIT_EXITING |
3109 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 3110 CPU_BASED_INVLPG_EXITING |
3111 CPU_BASED_RDPMC_EXITING;
443381a8 3112
f78e0e2e 3113 opt = CPU_BASED_TPR_SHADOW |
25c5f225 3114 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 3115 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 3116 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3117 &_cpu_based_exec_control) < 0)
002c7f7c 3118 return -EIO;
6e5d865c
YS		 3119#ifdef CONFIG_X86_64
3120 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3121 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3122 ~CPU_BASED_CR8_STORE_EXITING;
3123#endif
f78e0e2e 3124 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 3125 min2 = 0;
3126 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3127 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3128 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3129 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3130 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3131 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3132 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3133 SECONDARY_EXEC_RDTSCP |
83d4c286 3134 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3135 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3136 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3137 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 3138 SECONDARY_EXEC_XSAVES |
8b3e34e4
XG		 3139 SECONDARY_EXEC_ENABLE_PML |
3140 SECONDARY_EXEC_PCOMMIT;
d56f546d
SY		 3141 if (adjust_vmx_controls(min2, opt2,
3142 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3143 &_cpu_based_2nd_exec_control) < 0)
3144 return -EIO;
3145 }
3146#ifndef CONFIG_X86_64
3147 if (!(_cpu_based_2nd_exec_control &
3148 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3149 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3150#endif
83d4c286
YZ		 3151
3152 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3153 _cpu_based_2nd_exec_control &= ~(
8d14695f 3154 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3155 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3156 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3157
d56f546d 3158 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3159 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3160 enabled */
5fff7d27
GN		 3161 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3162 CPU_BASED_CR3_STORE_EXITING |
3163 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3164 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3165 vmx_capability.ept, vmx_capability.vpid);
3166 }
1c3d14fe 3167
81908bf4 3168 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3169#ifdef CONFIG_X86_64
3170 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3171#endif
a547c6db 3172 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3173 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3174 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3175 &_vmexit_control) < 0)
002c7f7c 3176 return -EIO;
1c3d14fe 3177
01e439be
YZ		 3178 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3179 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3180 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3181 &_pin_based_exec_control) < 0)
3182 return -EIO;
3183
3184 if (!(_cpu_based_2nd_exec_control &
3185 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3186 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3187 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3188
c845f9c6 3189 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3190 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3191 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3192 &_vmentry_control) < 0)
002c7f7c 3193 return -EIO;
6aa8b732 3194
c68876fd 3195 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3196
3197 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3198 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3199 return -EIO;
1c3d14fe
YS		 3200
3201#ifdef CONFIG_X86_64
3202 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3203 if (vmx_msr_high & (1u<<16))
002c7f7c 3204 return -EIO;
1c3d14fe
YS		 3205#endif
3206
3207 /* Require Write-Back (WB) memory type for VMCS accesses. */
3208 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3209 return -EIO;
1c3d14fe 3210
002c7f7c
YS		 3211 vmcs_conf->size = vmx_msr_high & 0x1fff;
3212 vmcs_conf->order = get_order(vmcs_config.size);
3213 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3214
002c7f7c
YS		 3215 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3216 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3217 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3218 vmcs_conf->vmexit_ctrl = _vmexit_control;
3219 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3220
110312c8
AK		 3221 cpu_has_load_ia32_efer =
3222 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3223 VM_ENTRY_LOAD_IA32_EFER)
3224 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3225 VM_EXIT_LOAD_IA32_EFER);
3226
8bf00a52
GN		 3227 cpu_has_load_perf_global_ctrl =
3228 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3229 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3230 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3231 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3232
3233 /*
3234 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3235 * but due to arrata below it can't be used. Workaround is to use
3236 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3237 *
3238 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3239 *
3240 * AAK155 (model 26)
3241 * AAP115 (model 30)
3242 * AAT100 (model 37)
3243 * BC86,AAY89,BD102 (model 44)
3244 * BA97 (model 46)
3245 *
3246 */
3247 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3248 switch (boot_cpu_data.x86_model) {
3249 case 26:
3250 case 30:
3251 case 37:
3252 case 44:
3253 case 46:
3254 cpu_has_load_perf_global_ctrl = false;
3255 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3256 "does not work properly. Using workaround\n");
3257 break;
3258 default:
3259 break;
3260 }
3261 }
3262
20300099
WL		 3263 if (cpu_has_xsaves)
3264 rdmsrl(MSR_IA32_XSS, host_xss);
3265
1c3d14fe 3266 return 0;
c68876fd 3267}
6aa8b732
AK		 3268
3269static struct vmcs *alloc_vmcs_cpu(int cpu)
3270{
3271 int node = cpu_to_node(cpu);
3272 struct page *pages;
3273 struct vmcs *vmcs;
3274
96db800f 3275 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3276 if (!pages)
3277 return NULL;
3278 vmcs = page_address(pages);
1c3d14fe
YS		 3279 memset(vmcs, 0, vmcs_config.size);
3280 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3281 return vmcs;
3282}
3283
3284static struct vmcs *alloc_vmcs(void)
3285{
d3b2c338 3286 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3287}
3288
3289static void free_vmcs(struct vmcs *vmcs)
3290{
1c3d14fe 3291 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3292}
3293
d462b819
NHE		 3294/*
3295 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3296 */
3297static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3298{
3299 if (!loaded_vmcs->vmcs)
3300 return;
3301 loaded_vmcs_clear(loaded_vmcs);
3302 free_vmcs(loaded_vmcs->vmcs);
3303 loaded_vmcs->vmcs = NULL;
3304}
3305
39959588 3306static void free_kvm_area(void)
6aa8b732
AK		 3307{
3308 int cpu;
3309
3230bb47 3310 for_each_possible_cpu(cpu) {
6aa8b732 3311 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3312 per_cpu(vmxarea, cpu) = NULL;
3313 }
6aa8b732
AK		 3314}
3315
fe2b201b
BD		 3316static void init_vmcs_shadow_fields(void)
3317{
3318 int i, j;
3319
3320 /* No checks for read only fields yet */
3321
3322 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3323 switch (shadow_read_write_fields[i]) {
3324 case GUEST_BNDCFGS:
3325 if (!vmx_mpx_supported())
3326 continue;
3327 break;
3328 default:
3329 break;
3330 }
3331
3332 if (j < i)
3333 shadow_read_write_fields[j] =
3334 shadow_read_write_fields[i];
3335 j++;
3336 }
3337 max_shadow_read_write_fields = j;
3338
3339 /* shadowed fields guest access without vmexit */
3340 for (i = 0; i < max_shadow_read_write_fields; i++) {
3341 clear_bit(shadow_read_write_fields[i],
3342 vmx_vmwrite_bitmap);
3343 clear_bit(shadow_read_write_fields[i],
3344 vmx_vmread_bitmap);
3345 }
3346 for (i = 0; i < max_shadow_read_only_fields; i++)
3347 clear_bit(shadow_read_only_fields[i],
3348 vmx_vmread_bitmap);
3349}
3350
6aa8b732
AK		 3351static __init int alloc_kvm_area(void)
3352{
3353 int cpu;
3354
3230bb47 3355 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3356 struct vmcs *vmcs;
3357
3358 vmcs = alloc_vmcs_cpu(cpu);
3359 if (!vmcs) {
3360 free_kvm_area();
3361 return -ENOMEM;
3362 }
3363
3364 per_cpu(vmxarea, cpu) = vmcs;
3365 }
3366 return 0;
3367}
3368
14168786
GN		 3369static bool emulation_required(struct kvm_vcpu *vcpu)
3370{
3371 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3372}
3373
91b0aa2c 3374static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3375 struct kvm_segment *save)
6aa8b732 3376{
d99e4152
GN		 3377 if (!emulate_invalid_guest_state) {
3378 /*
3379 * CS and SS RPL should be equal during guest entry according
3380 * to VMX spec, but in reality it is not always so. Since vcpu
3381 * is in the middle of the transition from real mode to
3382 * protected mode it is safe to assume that RPL 0 is a good
3383 * default value.
3384 */
3385 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 3386 save->selector &= ~SEGMENT_RPL_MASK;
3387 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3388 save->s = 1;
6aa8b732 3389 }
d99e4152 3390 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3391}
3392
3393static void enter_pmode(struct kvm_vcpu *vcpu)
3394{
3395 unsigned long flags;
a89a8fb9 3396 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3397
d99e4152
GN		 3398 /*
3399 * Update real mode segment cache. It may be not up-to-date if sement
3400 * register was written while vcpu was in a guest mode.
3401 */
3402 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3403 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3404 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3405 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3406 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3407 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3408
7ffd92c5 3409 vmx->rmode.vm86_active = 0;
6aa8b732 3410
2fb92db1
AK		 3411 vmx_segment_cache_clear(vmx);
3412
f5f7b2fe 3413 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3414
3415 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3416 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3417 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3418 vmcs_writel(GUEST_RFLAGS, flags);
3419
66aee91a
RR		 3420 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3421 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3422
3423 update_exception_bitmap(vcpu);
3424
91b0aa2c
GN		 3425 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3426 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3427 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3428 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3429 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3430 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3431}
3432
f5f7b2fe 3433static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3434{
772e0318 3435 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3436 struct kvm_segment var = *save;
3437
3438 var.dpl = 0x3;
3439 if (seg == VCPU_SREG_CS)
3440 var.type = 0x3;
3441
3442 if (!emulate_invalid_guest_state) {
3443 var.selector = var.base >> 4;
3444 var.base = var.base & 0xffff0;
3445 var.limit = 0xffff;
3446 var.g = 0;
3447 var.db = 0;
3448 var.present = 1;
3449 var.s = 1;
3450 var.l = 0;
3451 var.unusable = 0;
3452 var.type = 0x3;
3453 var.avl = 0;
3454 if (save->base & 0xf)
3455 printk_once(KERN_WARNING "kvm: segment base is not "
3456 "paragraph aligned when entering "
3457 "protected mode (seg=%d)", seg);
3458 }
6aa8b732 3459
d99e4152
GN		 3460 vmcs_write16(sf->selector, var.selector);
3461 vmcs_write32(sf->base, var.base);
3462 vmcs_write32(sf->limit, var.limit);
3463 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3464}
3465
3466static void enter_rmode(struct kvm_vcpu *vcpu)
3467{
3468 unsigned long flags;
a89a8fb9 3469 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3470
f5f7b2fe
AK		 3471 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3472 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3473 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3474 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3475 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3476 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3477 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3478
7ffd92c5 3479 vmx->rmode.vm86_active = 1;
6aa8b732 3480
776e58ea
GN		 3481 /*
3482 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3483 * vcpu. Warn the user that an update is overdue.
776e58ea 3484 */
4918c6ca 3485 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3486 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3487 "called before entering vcpu\n");
776e58ea 3488
2fb92db1
AK		 3489 vmx_segment_cache_clear(vmx);
3490
4918c6ca 3491 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3492 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3493 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3494
3495 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3496 vmx->rmode.save_rflags = flags;
6aa8b732 3497
053de044 3498 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3499
3500 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3501 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3502 update_exception_bitmap(vcpu);
3503
d99e4152
GN		 3504 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3505 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3506 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3507 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3508 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3509 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3510
8668a3c4 3511 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3512}
3513
401d10de
AS		 3514static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3515{
3516 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3517 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3518
3519 if (!msr)
3520 return;
401d10de 3521
44ea2b17
AK		 3522 /*
3523 * Force kernel_gs_base reloading before EFER changes, as control
3524 * of this msr depends on is_long_mode().
3525 */
3526 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3527 vcpu->arch.efer = efer;
401d10de 3528 if (efer & EFER_LMA) {
2961e876 3529 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3530 msr->data = efer;
3531 } else {
2961e876 3532 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3533
3534 msr->data = efer & ~EFER_LME;
3535 }
3536 setup_msrs(vmx);
3537}
3538
05b3e0c2 3539#ifdef CONFIG_X86_64
6aa8b732
AK		 3540
3541static void enter_lmode(struct kvm_vcpu *vcpu)
3542{
3543 u32 guest_tr_ar;
3544
2fb92db1
AK		 3545 vmx_segment_cache_clear(to_vmx(vcpu));
3546
6aa8b732 3547 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 3548 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3549 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3550 __func__);
6aa8b732 3551 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 3552 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3553 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 3554 }
da38f438 3555 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3556}
3557
3558static void exit_lmode(struct kvm_vcpu *vcpu)
3559{
2961e876 3560 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3561 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3562}
3563
3564#endif
3565
2384d2b3
SY		 3566static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3567{
b9d762fa 3568 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3569 if (enable_ept) {
3570 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3571 return;
4e1096d2 3572 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3573 }
2384d2b3
SY		 3574}
3575
e8467fda
AK		 3576static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3577{
3578 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3579
3580 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3581 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3582}
3583
aff48baa
AK		 3584static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3585{
3586 if (enable_ept && is_paging(vcpu))
3587 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3588 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3589}
3590
25c4c276 3591static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3592{
fc78f519
AK		 3593 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3594
3595 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3596 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3597}
3598
1439442c
SY		 3599static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3600{
d0d538b9
GN		 3601 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3602
6de4f3ad
AK		 3603 if (!test_bit(VCPU_EXREG_PDPTR,
3604 (unsigned long *)&vcpu->arch.regs_dirty))
3605 return;
3606
1439442c 3607 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3608 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3609 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3610 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3611 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3612 }
3613}
3614
8f5d549f
AK		 3615static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3616{
d0d538b9
GN		 3617 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3618
8f5d549f 3619 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3620 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3621 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3622 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3623 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3624 }
6de4f3ad
AK		 3625
3626 __set_bit(VCPU_EXREG_PDPTR,
3627 (unsigned long *)&vcpu->arch.regs_avail);
3628 __set_bit(VCPU_EXREG_PDPTR,
3629 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3630}
3631
5e1746d6 3632static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3633
3634static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3635 unsigned long cr0,
3636 struct kvm_vcpu *vcpu)
3637{
5233dd51
MT		 3638 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3639 vmx_decache_cr3(vcpu);
1439442c
SY		 3640 if (!(cr0 & X86_CR0_PG)) {
3641 /* From paging/starting to nonpaging */
3642 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3643 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3644 (CPU_BASED_CR3_LOAD_EXITING |
3645 CPU_BASED_CR3_STORE_EXITING));
3646 vcpu->arch.cr0 = cr0;
fc78f519 3647 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3648 } else if (!is_paging(vcpu)) {
3649 /* From nonpaging to paging */
3650 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3651 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3652 ~(CPU_BASED_CR3_LOAD_EXITING |
3653 CPU_BASED_CR3_STORE_EXITING));
3654 vcpu->arch.cr0 = cr0;
fc78f519 3655 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3656 }
95eb84a7
SY		 3657
3658 if (!(cr0 & X86_CR0_WP))
3659 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3660}
3661
6aa8b732
AK		 3662static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3663{
7ffd92c5 3664 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3665 unsigned long hw_cr0;
3666
5037878e 3667 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3668 if (enable_unrestricted_guest)
5037878e 3669 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3670 else {
5037878e 3671 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3672
218e763f
GN		 3673 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3674 enter_pmode(vcpu);
6aa8b732 3675
218e763f
GN		 3676 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3677 enter_rmode(vcpu);
3678 }
6aa8b732 3679
05b3e0c2 3680#ifdef CONFIG_X86_64
f6801dff 3681 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3682 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3683 enter_lmode(vcpu);
707d92fa 3684 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3685 exit_lmode(vcpu);
3686 }
3687#endif
3688
089d034e 3689 if (enable_ept)
1439442c
SY		 3690 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3691
02daab21 3692 if (!vcpu->fpu_active)
81231c69 3693 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3694
6aa8b732 3695 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3696 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3697 vcpu->arch.cr0 = cr0;
14168786
GN		 3698
3699 /* depends on vcpu->arch.cr0 to be set to a new value */
3700 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3701}
3702
1439442c
SY		 3703static u64 construct_eptp(unsigned long root_hpa)
3704{
3705 u64 eptp;
3706
3707 /* TODO write the value reading from MSR */
3708 eptp = VMX_EPT_DEFAULT_MT |
3709 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3710 if (enable_ept_ad_bits)
3711 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3712 eptp |= (root_hpa & PAGE_MASK);
3713
3714 return eptp;
3715}
3716
6aa8b732
AK		 3717static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3718{
1439442c
SY		 3719 unsigned long guest_cr3;
3720 u64 eptp;
3721
3722 guest_cr3 = cr3;
089d034e 3723 if (enable_ept) {
1439442c
SY		 3724 eptp = construct_eptp(cr3);
3725 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3726 if (is_paging(vcpu) || is_guest_mode(vcpu))
3727 guest_cr3 = kvm_read_cr3(vcpu);
3728 else
3729 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3730 ept_load_pdptrs(vcpu);
1439442c
SY		 3731 }
3732
2384d2b3 3733 vmx_flush_tlb(vcpu);
1439442c 3734 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3735}
3736
5e1746d6 3737static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3738{
085e68ee
BS		 3739 /*
3740 * Pass through host's Machine Check Enable value to hw_cr4, which
3741 * is in force while we are in guest mode. Do not let guests control
3742 * this bit, even if host CR4.MCE == 0.
3743 */
3744 unsigned long hw_cr4 =
3745 (cr4_read_shadow() & X86_CR4_MCE) |
3746 (cr4 & ~X86_CR4_MCE) |
3747 (to_vmx(vcpu)->rmode.vm86_active ?
3748 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 3749
5e1746d6
NHE		 3750 if (cr4 & X86_CR4_VMXE) {
3751 /*
3752 * To use VMXON (and later other VMX instructions), a guest
3753 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3754 * So basically the check on whether to allow nested VMX
3755 * is here.
3756 */
3757 if (!nested_vmx_allowed(vcpu))
3758 return 1;
1a0d74e6
JK		 3759 }
3760 if (to_vmx(vcpu)->nested.vmxon &&
3761 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3762 return 1;
3763
ad312c7c 3764 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3765 if (enable_ept) {
3766 if (!is_paging(vcpu)) {
3767 hw_cr4 &= ~X86_CR4_PAE;
3768 hw_cr4 |= X86_CR4_PSE;
c08800a5 3769 /*
e1e746b3
FW		 3770 * SMEP/SMAP is disabled if CPU is in non-paging mode
3771 * in hardware. However KVM always uses paging mode to
c08800a5 3772 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3773 * To emulate this behavior, SMEP/SMAP needs to be
3774 * manually disabled when guest switches to non-paging
3775 * mode.
c08800a5 3776 */
e1e746b3 3777 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3778 } else if (!(cr4 & X86_CR4_PAE)) {
3779 hw_cr4 &= ~X86_CR4_PAE;
3780 }
3781 }
1439442c
SY		 3782
3783 vmcs_writel(CR4_READ_SHADOW, cr4);
3784 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3785 return 0;
6aa8b732
AK		 3786}
3787
6aa8b732
AK		 3788static void vmx_get_segment(struct kvm_vcpu *vcpu,
3789 struct kvm_segment *var, int seg)
3790{
a9179499 3791 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3792 u32 ar;
3793
c6ad1153 3794 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3795 *var = vmx->rmode.segs[seg];
a9179499 3796 if (seg == VCPU_SREG_TR
2fb92db1 3797 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3798 return;
1390a28b
AK		 3799 var->base = vmx_read_guest_seg_base(vmx, seg);
3800 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3801 return;
a9179499 3802 }
2fb92db1
AK		 3803 var->base = vmx_read_guest_seg_base(vmx, seg);
3804 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3805 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3806 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3807 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3808 var->type = ar & 15;
3809 var->s = (ar >> 4) & 1;
3810 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3811 /*
3812 * Some userspaces do not preserve unusable property. Since usable
3813 * segment has to be present according to VMX spec we can use present
3814 * property to amend userspace bug by making unusable segment always
3815 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3816 * segment as unusable.
3817 */
3818 var->present = !var->unusable;
6aa8b732
AK		 3819 var->avl = (ar >> 12) & 1;
3820 var->l = (ar >> 13) & 1;
3821 var->db = (ar >> 14) & 1;
3822 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3823}
3824
a9179499
AK		 3825static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3826{
a9179499
AK		 3827 struct kvm_segment s;
3828
3829 if (to_vmx(vcpu)->rmode.vm86_active) {
3830 vmx_get_segment(vcpu, &s, seg);
3831 return s.base;
3832 }
2fb92db1 3833 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3834}
3835
b09408d0 3836static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3837{
b09408d0
MT		 3838 struct vcpu_vmx *vmx = to_vmx(vcpu);
3839
ae9fedc7 3840 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3841 return 0;
ae9fedc7
PB		 3842 else {
3843 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3844 return VMX_AR_DPL(ar);
69c73028 3845 }
69c73028
AK		 3846}
3847
653e3108 3848static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3849{
6aa8b732
AK		 3850 u32 ar;
3851
f0495f9b 3852 if (var->unusable || !var->present)
6aa8b732
AK		 3853 ar = 1 << 16;
3854 else {
3855 ar = var->type & 15;
3856 ar |= (var->s & 1) << 4;
3857 ar |= (var->dpl & 3) << 5;
3858 ar |= (var->present & 1) << 7;
3859 ar |= (var->avl & 1) << 12;
3860 ar |= (var->l & 1) << 13;
3861 ar |= (var->db & 1) << 14;
3862 ar |= (var->g & 1) << 15;
3863 }
653e3108
AK		 3864
3865 return ar;
3866}
3867
3868static void vmx_set_segment(struct kvm_vcpu *vcpu,
3869 struct kvm_segment *var, int seg)
3870{
7ffd92c5 3871 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3872 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3873
2fb92db1
AK		 3874 vmx_segment_cache_clear(vmx);
3875
1ecd50a9
GN		 3876 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3877 vmx->rmode.segs[seg] = *var;
3878 if (seg == VCPU_SREG_TR)
3879 vmcs_write16(sf->selector, var->selector);
3880 else if (var->s)
3881 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3882 goto out;
653e3108 3883 }
1ecd50a9 3884
653e3108
AK		 3885 vmcs_writel(sf->base, var->base);
3886 vmcs_write32(sf->limit, var->limit);
3887 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3888
3889 /*
3890 * Fix the "Accessed" bit in AR field of segment registers for older
3891 * qemu binaries.
3892 * IA32 arch specifies that at the time of processor reset the
3893 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3894 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3895 * state vmexit when "unrestricted guest" mode is turned on.
3896 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3897 * tree. Newer qemu binaries with that qemu fix would not need this
3898 * kvm hack.
3899 */
3900 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3901 var->type |= 0x1; /* Accessed */
3a624e29 3902
f924d66d 3903 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3904
3905out:
98eb2f8b 3906 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3907}
3908
6aa8b732
AK		 3909static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3910{
2fb92db1 3911 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3912
3913 *db = (ar >> 14) & 1;
3914 *l = (ar >> 13) & 1;
3915}
3916
89a27f4d 3917static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3918{
89a27f4d
GN		 3919 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3920 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3921}
3922
89a27f4d 3923static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3924{
89a27f4d
GN		 3925 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3926 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3927}
3928
89a27f4d 3929static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3930{
89a27f4d
GN		 3931 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3932 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3933}
3934
89a27f4d 3935static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3936{
89a27f4d
GN		 3937 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3938 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3939}
3940
648dfaa7
MG		 3941static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3942{
3943 struct kvm_segment var;
3944 u32 ar;
3945
3946 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3947 var.dpl = 0x3;
0647f4aa
GN		 3948 if (seg == VCPU_SREG_CS)
3949 var.type = 0x3;
648dfaa7
MG		 3950 ar = vmx_segment_access_rights(&var);
3951
3952 if (var.base != (var.selector << 4))
3953 return false;
89efbed0 3954 if (var.limit != 0xffff)
648dfaa7 3955 return false;
07f42f5f 3956 if (ar != 0xf3)
648dfaa7
MG		 3957 return false;
3958
3959 return true;
3960}
3961
3962static bool code_segment_valid(struct kvm_vcpu *vcpu)
3963{
3964 struct kvm_segment cs;
3965 unsigned int cs_rpl;
3966
3967 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3968 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3969
1872a3f4
AK		 3970 if (cs.unusable)
3971 return false;
4d283ec9 3972 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3973 return false;
3974 if (!cs.s)
3975 return false;
4d283ec9 3976 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3977 if (cs.dpl > cs_rpl)
3978 return false;
1872a3f4 3979 } else {
648dfaa7
MG		 3980 if (cs.dpl != cs_rpl)
3981 return false;
3982 }
3983 if (!cs.present)
3984 return false;
3985
3986 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3987 return true;
3988}
3989
3990static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3991{
3992 struct kvm_segment ss;
3993 unsigned int ss_rpl;
3994
3995 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3996 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3997
1872a3f4
AK		 3998 if (ss.unusable)
3999 return true;
4000 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 4001 return false;
4002 if (!ss.s)
4003 return false;
4004 if (ss.dpl != ss_rpl) /* DPL != RPL */
4005 return false;
4006 if (!ss.present)
4007 return false;
4008
4009 return true;
4010}
4011
4012static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4013{
4014 struct kvm_segment var;
4015 unsigned int rpl;
4016
4017 vmx_get_segment(vcpu, &var, seg);
b32a9918 4018 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 4019
1872a3f4
AK		 4020 if (var.unusable)
4021 return true;
648dfaa7
MG		 4022 if (!var.s)
4023 return false;
4024 if (!var.present)
4025 return false;
4d283ec9 4026 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 4027 if (var.dpl < rpl) /* DPL < RPL */
4028 return false;
4029 }
4030
4031 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4032 * rights flags
4033 */
4034 return true;
4035}
4036
4037static bool tr_valid(struct kvm_vcpu *vcpu)
4038{
4039 struct kvm_segment tr;
4040
4041 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4042
1872a3f4
AK		 4043 if (tr.unusable)
4044 return false;
b32a9918 4045 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 4046 return false;
1872a3f4 4047 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 4048 return false;
4049 if (!tr.present)
4050 return false;
4051
4052 return true;
4053}
4054
4055static bool ldtr_valid(struct kvm_vcpu *vcpu)
4056{
4057 struct kvm_segment ldtr;
4058
4059 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4060
1872a3f4
AK		 4061 if (ldtr.unusable)
4062 return true;
b32a9918 4063 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 4064 return false;
4065 if (ldtr.type != 2)
4066 return false;
4067 if (!ldtr.present)
4068 return false;
4069
4070 return true;
4071}
4072
4073static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4074{
4075 struct kvm_segment cs, ss;
4076
4077 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4078 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4079
b32a9918
NA		 4080 return ((cs.selector & SEGMENT_RPL_MASK) ==
4081 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 4082}
4083
4084/*
4085 * Check if guest state is valid. Returns true if valid, false if
4086 * not.
4087 * We assume that registers are always usable
4088 */
4089static bool guest_state_valid(struct kvm_vcpu *vcpu)
4090{
c5e97c80
GN		 4091 if (enable_unrestricted_guest)
4092 return true;
4093
648dfaa7 4094 /* real mode guest state checks */
f13882d8 4095 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 4096 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4097 return false;
4098 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4099 return false;
4100 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4101 return false;
4102 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4103 return false;
4104 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4105 return false;
4106 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4107 return false;
4108 } else {
4109 /* protected mode guest state checks */
4110 if (!cs_ss_rpl_check(vcpu))
4111 return false;
4112 if (!code_segment_valid(vcpu))
4113 return false;
4114 if (!stack_segment_valid(vcpu))
4115 return false;
4116 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4117 return false;
4118 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4119 return false;
4120 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4121 return false;
4122 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4123 return false;
4124 if (!tr_valid(vcpu))
4125 return false;
4126 if (!ldtr_valid(vcpu))
4127 return false;
4128 }
4129 /* TODO:
4130 * - Add checks on RIP
4131 * - Add checks on RFLAGS
4132 */
4133
4134 return true;
4135}
4136
d77c26fc 4137static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4138{
40dcaa9f 4139 gfn_t fn;
195aefde 4140 u16 data = 0;
1f755a82 4141 int idx, r;
6aa8b732 4142
40dcaa9f 4143 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4144 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 4145 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4146 if (r < 0)
10589a46 4147 goto out;
195aefde 4148 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4149 r = kvm_write_guest_page(kvm, fn++, &data,
4150 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4151 if (r < 0)
10589a46 4152 goto out;
195aefde
IE		 4153 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4154 if (r < 0)
10589a46 4155 goto out;
195aefde
IE		 4156 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4157 if (r < 0)
10589a46 4158 goto out;
195aefde 4159 data = ~0;
10589a46
MT		 4160 r = kvm_write_guest_page(kvm, fn, &data,
4161 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4162 sizeof(u8));
10589a46 4163out:
40dcaa9f 4164 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4165 return r;
6aa8b732
AK		 4166}
4167
b7ebfb05
SY		 4168static int init_rmode_identity_map(struct kvm *kvm)
4169{
f51770ed 4170 int i, idx, r = 0;
b7ebfb05
SY		 4171 pfn_t identity_map_pfn;
4172 u32 tmp;
4173
089d034e 4174 if (!enable_ept)
f51770ed 4175 return 0;
a255d479
TC		 4176
4177 /* Protect kvm->arch.ept_identity_pagetable_done. */
4178 mutex_lock(&kvm->slots_lock);
4179
f51770ed 4180 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4181 goto out2;
a255d479 4182
b927a3ce 4183 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4184
4185 r = alloc_identity_pagetable(kvm);
f51770ed 4186 if (r < 0)
a255d479
TC		 4187 goto out2;
4188
40dcaa9f 4189 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4190 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4191 if (r < 0)
4192 goto out;
4193 /* Set up identity-mapping pagetable for EPT in real mode */
4194 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4195 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4196 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4197 r = kvm_write_guest_page(kvm, identity_map_pfn,
4198 &tmp, i * sizeof(tmp), sizeof(tmp));
4199 if (r < 0)
4200 goto out;
4201 }
4202 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4203
b7ebfb05 4204out:
40dcaa9f 4205 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4206
4207out2:
4208 mutex_unlock(&kvm->slots_lock);
f51770ed 4209 return r;
b7ebfb05
SY		 4210}
4211
6aa8b732
AK		 4212static void seg_setup(int seg)
4213{
772e0318 4214 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4215 unsigned int ar;
6aa8b732
AK		 4216
4217 vmcs_write16(sf->selector, 0);
4218 vmcs_writel(sf->base, 0);
4219 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4220 ar = 0x93;
4221 if (seg == VCPU_SREG_CS)
4222 ar |= 0x08; /* code segment */
3a624e29
NK		 4223
4224 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4225}
4226
f78e0e2e
SY		 4227static int alloc_apic_access_page(struct kvm *kvm)
4228{
4484141a 4229 struct page *page;
f78e0e2e
SY		 4230 int r = 0;
4231
79fac95e 4232 mutex_lock(&kvm->slots_lock);
c24ae0dc 4233 if (kvm->arch.apic_access_page_done)
f78e0e2e 4234 goto out;
1d8007bd
PB		 4235 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4236 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY		 4237 if (r)
4238 goto out;
72dc67a6 4239
73a6d941 4240 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4241 if (is_error_page(page)) {
4242 r = -EFAULT;
4243 goto out;
4244 }
4245
c24ae0dc
TC		 4246 /*
4247 * Do not pin the page in memory, so that memory hot-unplug
4248 * is able to migrate it.
4249 */
4250 put_page(page);
4251 kvm->arch.apic_access_page_done = true;
f78e0e2e 4252out:
79fac95e 4253 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4254 return r;
4255}
4256
b7ebfb05
SY		 4257static int alloc_identity_pagetable(struct kvm *kvm)
4258{
a255d479
TC		 4259 /* Called with kvm->slots_lock held. */
4260
b7ebfb05
SY		 4261 int r = 0;
4262
a255d479
TC		 4263 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4264
1d8007bd
PB		 4265 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4266 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
b7ebfb05 4267
b7ebfb05
SY		 4268 return r;
4269}
4270
991e7a0e 4271static int allocate_vpid(void)
2384d2b3
SY		 4272{
4273 int vpid;
4274
919818ab 4275 if (!enable_vpid)
991e7a0e 4276 return 0;
2384d2b3
SY		 4277 spin_lock(&vmx_vpid_lock);
4278 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 4279 if (vpid < VMX_NR_VPIDS)
2384d2b3 4280 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL		 4281 else
4282 vpid = 0;
2384d2b3 4283 spin_unlock(&vmx_vpid_lock);
991e7a0e 4284 return vpid;
2384d2b3
SY		 4285}
4286
991e7a0e 4287static void free_vpid(int vpid)
cdbecfc3 4288{
991e7a0e 4289 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ		 4290 return;
4291 spin_lock(&vmx_vpid_lock);
991e7a0e 4292 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ		 4293 spin_unlock(&vmx_vpid_lock);
4294}
4295
8d14695f
YZ		 4296#define MSR_TYPE_R 1
4297#define MSR_TYPE_W 2
4298static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4299 u32 msr, int type)
25c5f225 4300{
3e7c73e9 4301 int f = sizeof(unsigned long);
25c5f225
SY		 4302
4303 if (!cpu_has_vmx_msr_bitmap())
4304 return;
4305
4306 /*
4307 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4308 * have the write-low and read-high bitmap offsets the wrong way round.
4309 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4310 */
25c5f225 4311 if (msr <= 0x1fff) {
8d14695f
YZ		 4312 if (type & MSR_TYPE_R)
4313 /* read-low */
4314 __clear_bit(msr, msr_bitmap + 0x000 / f);
4315
4316 if (type & MSR_TYPE_W)
4317 /* write-low */
4318 __clear_bit(msr, msr_bitmap + 0x800 / f);
4319
25c5f225
SY		 4320 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4321 msr &= 0x1fff;
8d14695f
YZ		 4322 if (type & MSR_TYPE_R)
4323 /* read-high */
4324 __clear_bit(msr, msr_bitmap + 0x400 / f);
4325
4326 if (type & MSR_TYPE_W)
4327 /* write-high */
4328 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4329
4330 }
4331}
4332
4333static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4334 u32 msr, int type)
4335{
4336 int f = sizeof(unsigned long);
4337
4338 if (!cpu_has_vmx_msr_bitmap())
4339 return;
4340
4341 /*
4342 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4343 * have the write-low and read-high bitmap offsets the wrong way round.
4344 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4345 */
4346 if (msr <= 0x1fff) {
4347 if (type & MSR_TYPE_R)
4348 /* read-low */
4349 __set_bit(msr, msr_bitmap + 0x000 / f);
4350
4351 if (type & MSR_TYPE_W)
4352 /* write-low */
4353 __set_bit(msr, msr_bitmap + 0x800 / f);
4354
4355 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4356 msr &= 0x1fff;
4357 if (type & MSR_TYPE_R)
4358 /* read-high */
4359 __set_bit(msr, msr_bitmap + 0x400 / f);
4360
4361 if (type & MSR_TYPE_W)
4362 /* write-high */
4363 __set_bit(msr, msr_bitmap + 0xc00 / f);
4364
25c5f225 4365 }
25c5f225
SY		 4366}
4367
f2b93280
WV		 4368/*
4369 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4370 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4371 */
4372static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4373 unsigned long *msr_bitmap_nested,
4374 u32 msr, int type)
4375{
4376 int f = sizeof(unsigned long);
4377
4378 if (!cpu_has_vmx_msr_bitmap()) {
4379 WARN_ON(1);
4380 return;
4381 }
4382
4383 /*
4384 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4385 * have the write-low and read-high bitmap offsets the wrong way round.
4386 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4387 */
4388 if (msr <= 0x1fff) {
4389 if (type & MSR_TYPE_R &&
4390 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4391 /* read-low */
4392 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4393
4394 if (type & MSR_TYPE_W &&
4395 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4396 /* write-low */
4397 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4398
4399 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4400 msr &= 0x1fff;
4401 if (type & MSR_TYPE_R &&
4402 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4403 /* read-high */
4404 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4405
4406 if (type & MSR_TYPE_W &&
4407 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4408 /* write-high */
4409 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4410
4411 }
4412}
4413
5897297b
AK		 4414static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4415{
4416 if (!longmode_only)
8d14695f
YZ		 4417 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4418 msr, MSR_TYPE_R | MSR_TYPE_W);
4419 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4420 msr, MSR_TYPE_R | MSR_TYPE_W);
4421}
4422
4423static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4424{
4425 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4426 msr, MSR_TYPE_R);
4427 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4428 msr, MSR_TYPE_R);
4429}
4430
4431static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4432{
4433 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4434 msr, MSR_TYPE_R);
4435 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4436 msr, MSR_TYPE_R);
4437}
4438
4439static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4440{
4441 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4442 msr, MSR_TYPE_W);
4443 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4444 msr, MSR_TYPE_W);
5897297b
AK		 4445}
4446
d50ab6c1
PB		 4447static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4448{
35754c98 4449 return enable_apicv && lapic_in_kernel(vcpu);
d50ab6c1
PB		 4450}
4451
705699a1
WV		 4452static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4453{
4454 struct vcpu_vmx *vmx = to_vmx(vcpu);
4455 int max_irr;
4456 void *vapic_page;
4457 u16 status;
4458
4459 if (vmx->nested.pi_desc &&
4460 vmx->nested.pi_pending) {
4461 vmx->nested.pi_pending = false;
4462 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4463 return 0;
4464
4465 max_irr = find_last_bit(
4466 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4467
4468 if (max_irr == 256)
4469 return 0;
4470
4471 vapic_page = kmap(vmx->nested.virtual_apic_page);
4472 if (!vapic_page) {
4473 WARN_ON(1);
4474 return -ENOMEM;
4475 }
4476 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4477 kunmap(vmx->nested.virtual_apic_page);
4478
4479 status = vmcs_read16(GUEST_INTR_STATUS);
4480 if ((u8)max_irr > ((u8)status & 0xff)) {
4481 status &= ~0xff;
4482 status |= (u8)max_irr;
4483 vmcs_write16(GUEST_INTR_STATUS, status);
4484 }
4485 }
4486 return 0;
4487}
4488
21bc8dc5
RK		 4489static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4490{
4491#ifdef CONFIG_SMP
4492 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6
FW		 4493 struct vcpu_vmx *vmx = to_vmx(vcpu);
4494
4495 /*
4496 * Currently, we don't support urgent interrupt,
4497 * all interrupts are recognized as non-urgent
4498 * interrupt, so we cannot post interrupts when
4499 * 'SN' is set.
4500 *
4501 * If the vcpu is in guest mode, it means it is
4502 * running instead of being scheduled out and
4503 * waiting in the run queue, and that's the only
4504 * case when 'SN' is set currently, warning if
4505 * 'SN' is set.
4506 */
4507 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4508
21bc8dc5
RK		 4509 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4510 POSTED_INTR_VECTOR);
4511 return true;
4512 }
4513#endif
4514 return false;
4515}
4516
705699a1
WV		 4517static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4518 int vector)
4519{
4520 struct vcpu_vmx *vmx = to_vmx(vcpu);
4521
4522 if (is_guest_mode(vcpu) &&
4523 vector == vmx->nested.posted_intr_nv) {
4524 /* the PIR and ON have been set by L1. */
21bc8dc5 4525 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV		 4526 /*
4527 * If a posted intr is not recognized by hardware,
4528 * we will accomplish it in the next vmentry.
4529 */
4530 vmx->nested.pi_pending = true;
4531 kvm_make_request(KVM_REQ_EVENT, vcpu);
4532 return 0;
4533 }
4534 return -1;
4535}
a20ed54d
YZ		 4536/*
4537 * Send interrupt to vcpu via posted interrupt way.
4538 * 1. If target vcpu is running(non-root mode), send posted interrupt
4539 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4540 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4541 * interrupt from PIR in next vmentry.
4542 */
4543static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4544{
4545 struct vcpu_vmx *vmx = to_vmx(vcpu);
4546 int r;
4547
705699a1
WV		 4548 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4549 if (!r)
4550 return;
4551
a20ed54d
YZ		 4552 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4553 return;
4554
4555 r = pi_test_and_set_on(&vmx->pi_desc);
4556 kvm_make_request(KVM_REQ_EVENT, vcpu);
21bc8dc5 4557 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ		 4558 kvm_vcpu_kick(vcpu);
4559}
4560
4561static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4562{
4563 struct vcpu_vmx *vmx = to_vmx(vcpu);
4564
4565 if (!pi_test_and_clear_on(&vmx->pi_desc))
4566 return;
4567
4568 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4569}
4570
4571static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4572{
4573 return;
4574}
4575
a3a8ff8e
NHE		 4576/*
4577 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4578 * will not change in the lifetime of the guest.
4579 * Note that host-state that does change is set elsewhere. E.g., host-state
4580 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4581 */
a547c6db 4582static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4583{
4584 u32 low32, high32;
4585 unsigned long tmpl;
4586 struct desc_ptr dt;
d974baa3 4587 unsigned long cr4;
a3a8ff8e 4588
b1a74bf8 4589 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4590 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4591
d974baa3 4592 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 4593 cr4 = cr4_read_shadow();
d974baa3
AL		 4594 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4595 vmx->host_state.vmcs_host_cr4 = cr4;
4596
a3a8ff8e 4597 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4598#ifdef CONFIG_X86_64
4599 /*
4600 * Load null selectors, so we can avoid reloading them in
4601 * __vmx_load_host_state(), in case userspace uses the null selectors
4602 * too (the expected case).
4603 */
4604 vmcs_write16(HOST_DS_SELECTOR, 0);
4605 vmcs_write16(HOST_ES_SELECTOR, 0);
4606#else
a3a8ff8e
NHE		 4607 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4608 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4609#endif
a3a8ff8e
NHE		 4610 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4611 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4612
4613 native_store_idt(&dt);
4614 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4615 vmx->host_idt_base = dt.address;
a3a8ff8e 4616
83287ea4 4617 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4618
4619 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4620 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4621 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4622 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4623
4624 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4625 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4626 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4627 }
4628}
4629
bf8179a0
NHE		 4630static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4631{
4632 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4633 if (enable_ept)
4634 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4635 if (is_guest_mode(&vmx->vcpu))
4636 vmx->vcpu.arch.cr4_guest_owned_bits &=
4637 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4638 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4639}
4640
01e439be
YZ		 4641static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4642{
4643 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4644
35754c98 4645 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
01e439be
YZ		 4646 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4647 return pin_based_exec_ctrl;
4648}
4649
bf8179a0
NHE		 4650static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4651{
4652 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4653
4654 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4655 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4656
35754c98 4657 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE		 4658 exec_control &= ~CPU_BASED_TPR_SHADOW;
4659#ifdef CONFIG_X86_64
4660 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4661 CPU_BASED_CR8_LOAD_EXITING;
4662#endif
4663 }
4664 if (!enable_ept)
4665 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4666 CPU_BASED_CR3_LOAD_EXITING |
4667 CPU_BASED_INVLPG_EXITING;
4668 return exec_control;
4669}
4670
4671static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4672{
4673 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 4674 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE		 4675 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4676 if (vmx->vpid == 0)
4677 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4678 if (!enable_ept) {
4679 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4680 enable_unrestricted_guest = 0;
ad756a16
MJ		 4681 /* Enable INVPCID for non-ept guests may cause performance regression. */
4682 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4683 }
4684 if (!enable_unrestricted_guest)
4685 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4686 if (!ple_gap)
4687 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
35754c98 4688 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
c7c9c56c
YZ		 4689 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4690 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4691 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4692 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4693 (handle_vmptrld).
4694 We can NOT enable shadow_vmcs here because we don't have yet
4695 a current VMCS12
4696 */
4697 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4698 /* PML is enabled/disabled in creating/destorying vcpu */
4699 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4700
8b3e34e4
XG		 4701 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4702 exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4703
bf8179a0
NHE		 4704 return exec_control;
4705}
4706
ce88decf
XG		 4707static void ept_set_mmio_spte_mask(void)
4708{
4709 /*
4710 * EPT Misconfigurations can be generated if the value of bits 2:0
4711 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4712 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4713 * spte.
4714 */
885032b9 4715 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4716}
4717
f53cd63c 4718#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4719/*
4720 * Sets up the vmcs for emulated real mode.
4721 */
8b9cf98c 4722static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4723{
2e4ce7f5 4724#ifdef CONFIG_X86_64
6aa8b732 4725 unsigned long a;
2e4ce7f5 4726#endif
6aa8b732 4727 int i;
6aa8b732 4728
6aa8b732 4729 /* I/O */
3e7c73e9
AK		 4730 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4731 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4732
4607c2d7
AG		 4733 if (enable_shadow_vmcs) {
4734 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4735 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4736 }
25c5f225 4737 if (cpu_has_vmx_msr_bitmap())
5897297b 4738 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4739
6aa8b732
AK		 4740 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4741
6aa8b732 4742 /* Control */
01e439be 4743 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4744
bf8179a0 4745 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4746
8b3e34e4 4747 if (cpu_has_secondary_exec_ctrls())
bf8179a0
NHE		 4748 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4749 vmx_secondary_exec_control(vmx));
f78e0e2e 4750
35754c98 4751 if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
c7c9c56c
YZ		 4752 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4753 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4754 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4755 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4756
4757 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4758
4759 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4760 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4761 }
4762
4b8d54f9
ZE		 4763 if (ple_gap) {
4764 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4765 vmx->ple_window = ple_window;
4766 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4767 }
4768
c3707958
XG		 4769 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4770 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4771 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4772
9581d442
AK		 4773 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4774 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4775 vmx_set_constant_host_state(vmx);
05b3e0c2 4776#ifdef CONFIG_X86_64
6aa8b732
AK		 4777 rdmsrl(MSR_FS_BASE, a);
4778 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4779 rdmsrl(MSR_GS_BASE, a);
4780 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4781#else
4782 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4783 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4784#endif
4785
2cc51560
ED		 4786 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4787 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4788 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4789 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4790 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4791
74545705
RK		 4792 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4793 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4794
03916db9 4795 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4796 u32 index = vmx_msr_index[i];
4797 u32 data_low, data_high;
a2fa3e9f 4798 int j = vmx->nmsrs;
6aa8b732
AK		 4799
4800 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4801 continue;
432bd6cb
AK		 4802 if (wrmsr_safe(index, data_low, data_high) < 0)
4803 continue;
26bb0981
AK		 4804 vmx->guest_msrs[j].index = i;
4805 vmx->guest_msrs[j].data = 0;
d5696725 4806 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4807 ++vmx->nmsrs;
6aa8b732 4808 }
6aa8b732 4809
2961e876
GN		 4810
4811 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4812
4813 /* 22.2.1, 20.8.1 */
2961e876 4814 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4815
e00c8cf2 4816 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4817 set_cr4_guest_host_mask(vmx);
e00c8cf2 4818
f53cd63c
WL		 4819 if (vmx_xsaves_supported())
4820 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4821
e00c8cf2
AK		 4822 return 0;
4823}
4824
d28bc9dd 4825static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4826{
4827 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4828 struct msr_data apic_base_msr;
d28bc9dd 4829 u64 cr0;
e00c8cf2 4830
7ffd92c5 4831 vmx->rmode.vm86_active = 0;
e00c8cf2 4832
3b86cd99
JK		 4833 vmx->soft_vnmi_blocked = 0;
4834
ad312c7c 4835 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 4836 kvm_set_cr8(vcpu, 0);
4837
4838 if (!init_event) {
4839 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4840 MSR_IA32_APICBASE_ENABLE;
4841 if (kvm_vcpu_is_reset_bsp(vcpu))
4842 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4843 apic_base_msr.host_initiated = true;
4844 kvm_set_apic_base(vcpu, &apic_base_msr);
4845 }
e00c8cf2 4846
2fb92db1
AK		 4847 vmx_segment_cache_clear(vmx);
4848
5706be0d 4849 seg_setup(VCPU_SREG_CS);
66450a21 4850 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4851 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4852
4853 seg_setup(VCPU_SREG_DS);
4854 seg_setup(VCPU_SREG_ES);
4855 seg_setup(VCPU_SREG_FS);
4856 seg_setup(VCPU_SREG_GS);
4857 seg_setup(VCPU_SREG_SS);
4858
4859 vmcs_write16(GUEST_TR_SELECTOR, 0);
4860 vmcs_writel(GUEST_TR_BASE, 0);
4861 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4862 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4863
4864 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4865 vmcs_writel(GUEST_LDTR_BASE, 0);
4866 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4867 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4868
d28bc9dd
NA		 4869 if (!init_event) {
4870 vmcs_write32(GUEST_SYSENTER_CS, 0);
4871 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4872 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4873 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4874 }
e00c8cf2
AK		 4875
4876 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4877 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4878
e00c8cf2
AK		 4879 vmcs_writel(GUEST_GDTR_BASE, 0);
4880 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4881
4882 vmcs_writel(GUEST_IDTR_BASE, 0);
4883 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4884
443381a8 4885 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4886 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4887 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4888
e00c8cf2
AK		 4889 setup_msrs(vmx);
4890
6aa8b732
AK		 4891 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4892
d28bc9dd 4893 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4894 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4895 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4896 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4897 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4898 vmcs_write32(TPR_THRESHOLD, 0);
4899 }
4900
a73896cb 4901 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4902
35754c98 4903 if (vmx_cpu_uses_apicv(vcpu))
01e439be
YZ		 4904 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4905
2384d2b3
SY		 4906 if (vmx->vpid != 0)
4907 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4908
d28bc9dd
NA		 4909 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4910 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4911 vmx->vcpu.arch.cr0 = cr0;
4912 vmx_set_cr4(vcpu, 0);
4913 if (!init_event)
4914 vmx_set_efer(vcpu, 0);
4915 vmx_fpu_activate(vcpu);
4916 update_exception_bitmap(vcpu);
6aa8b732 4917
b9d762fa 4918 vpid_sync_context(vmx);
6aa8b732
AK		 4919}
4920
b6f1250e
NHE		 4921/*
4922 * In nested virtualization, check if L1 asked to exit on external interrupts.
4923 * For most existing hypervisors, this will always return true.
4924 */
4925static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4926{
4927 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4928 PIN_BASED_EXT_INTR_MASK;
4929}
4930
77b0f5d6
BD		 4931/*
4932 * In nested virtualization, check if L1 has set
4933 * VM_EXIT_ACK_INTR_ON_EXIT
4934 */
4935static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4936{
4937 return get_vmcs12(vcpu)->vm_exit_controls &
4938 VM_EXIT_ACK_INTR_ON_EXIT;
4939}
4940
ea8ceb83
JK		 4941static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4942{
4943 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4944 PIN_BASED_NMI_EXITING;
4945}
4946
c9a7953f 4947static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4948{
4949 u32 cpu_based_vm_exec_control;
730dca42 4950
3b86cd99
JK		 4951 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4952 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4953 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4954}
4955
c9a7953f 4956static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4957{
4958 u32 cpu_based_vm_exec_control;
4959
c9a7953f
JK		 4960 if (!cpu_has_virtual_nmis() ||
4961 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4962 enable_irq_window(vcpu);
4963 return;
4964 }
3b86cd99
JK		 4965
4966 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4967 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4968 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4969}
4970
66fd3f7f 4971static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4972{
9c8cba37 4973 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4974 uint32_t intr;
4975 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4976
229456fc 4977 trace_kvm_inj_virq(irq);
2714d1d3 4978
fa89a817 4979 ++vcpu->stat.irq_injections;
7ffd92c5 4980 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4981 int inc_eip = 0;
4982 if (vcpu->arch.interrupt.soft)
4983 inc_eip = vcpu->arch.event_exit_inst_len;
4984 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4985 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4986 return;
4987 }
66fd3f7f
GN		 4988 intr = irq | INTR_INFO_VALID_MASK;
4989 if (vcpu->arch.interrupt.soft) {
4990 intr |= INTR_TYPE_SOFT_INTR;
4991 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4992 vmx->vcpu.arch.event_exit_inst_len);
4993 } else
4994 intr |= INTR_TYPE_EXT_INTR;
4995 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4996}
4997
f08864b4
SY		 4998static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4999{
66a5a347
JK		 5000 struct vcpu_vmx *vmx = to_vmx(vcpu);
5001
0b6ac343
NHE		 5002 if (is_guest_mode(vcpu))
5003 return;
5004
3b86cd99
JK		 5005 if (!cpu_has_virtual_nmis()) {
5006 /*
5007 * Tracking the NMI-blocked state in software is built upon
5008 * finding the next open IRQ window. This, in turn, depends on
5009 * well-behaving guests: They have to keep IRQs disabled at
5010 * least as long as the NMI handler runs. Otherwise we may
5011 * cause NMI nesting, maybe breaking the guest. But as this is
5012 * highly unlikely, we can live with the residual risk.
5013 */
5014 vmx->soft_vnmi_blocked = 1;
5015 vmx->vnmi_blocked_time = 0;
5016 }
5017
487b391d 5018 ++vcpu->stat.nmi_injections;
9d58b931 5019 vmx->nmi_known_unmasked = false;
7ffd92c5 5020 if (vmx->rmode.vm86_active) {
71f9833b 5021 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 5022 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 5023 return;
5024 }
f08864b4
SY		 5025 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5026 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 5027}
5028
3cfc3092
JK		 5029static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5030{
5031 if (!cpu_has_virtual_nmis())
5032 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 5033 if (to_vmx(vcpu)->nmi_known_unmasked)
5034 return false;
c332c83a 5035 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 5036}
5037
5038static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5039{
5040 struct vcpu_vmx *vmx = to_vmx(vcpu);
5041
5042 if (!cpu_has_virtual_nmis()) {
5043 if (vmx->soft_vnmi_blocked != masked) {
5044 vmx->soft_vnmi_blocked = masked;
5045 vmx->vnmi_blocked_time = 0;
5046 }
5047 } else {
9d58b931 5048 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 5049 if (masked)
5050 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5051 GUEST_INTR_STATE_NMI);
5052 else
5053 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5054 GUEST_INTR_STATE_NMI);
5055 }
5056}
5057
2505dc9f
JK		 5058static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5059{
b6b8a145
JK		 5060 if (to_vmx(vcpu)->nested.nested_run_pending)
5061 return 0;
ea8ceb83 5062
2505dc9f
JK		 5063 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5064 return 0;
5065
5066 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5067 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5068 | GUEST_INTR_STATE_NMI));
5069}
5070
78646121
GN		 5071static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5072{
b6b8a145
JK		 5073 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5074 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 5075 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5076 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 5077}
5078
cbc94022
IE		 5079static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5080{
5081 int ret;
cbc94022 5082
1d8007bd
PB		 5083 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5084 PAGE_SIZE * 3);
cbc94022
IE		 5085 if (ret)
5086 return ret;
bfc6d222 5087 kvm->arch.tss_addr = addr;
1f755a82 5088 return init_rmode_tss(kvm);
cbc94022
IE		 5089}
5090
0ca1b4f4 5091static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 5092{
77ab6db0 5093 switch (vec) {
77ab6db0 5094 case BP_VECTOR:
c573cd22
JK		 5095 /*
5096 * Update instruction length as we may reinject the exception
5097 * from user space while in guest debugging mode.
5098 */
5099 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5100 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 5101 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 5102 return false;
5103 /* fall through */
5104 case DB_VECTOR:
5105 if (vcpu->guest_debug &
5106 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5107 return false;
d0bfb940
JK		 5108 /* fall through */
5109 case DE_VECTOR:
77ab6db0
JK		 5110 case OF_VECTOR:
5111 case BR_VECTOR:
5112 case UD_VECTOR:
5113 case DF_VECTOR:
5114 case SS_VECTOR:
5115 case GP_VECTOR:
5116 case MF_VECTOR:
0ca1b4f4
GN		 5117 return true;
5118 break;
77ab6db0 5119 }
0ca1b4f4
GN		 5120 return false;
5121}
5122
5123static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5124 int vec, u32 err_code)
5125{
5126 /*
5127 * Instruction with address size override prefix opcode 0x67
5128 * Cause the #SS fault with 0 error code in VM86 mode.
5129 */
5130 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5131 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5132 if (vcpu->arch.halt_request) {
5133 vcpu->arch.halt_request = 0;
5cb56059 5134 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 5135 }
5136 return 1;
5137 }
5138 return 0;
5139 }
5140
5141 /*
5142 * Forward all other exceptions that are valid in real mode.
5143 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5144 * the required debugging infrastructure rework.
5145 */
5146 kvm_queue_exception(vcpu, vec);
5147 return 1;
6aa8b732
AK		 5148}
5149
a0861c02
AK		 5150/*
5151 * Trigger machine check on the host. We assume all the MSRs are already set up
5152 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5153 * We pass a fake environment to the machine check handler because we want
5154 * the guest to be always treated like user space, no matter what context
5155 * it used internally.
5156 */
5157static void kvm_machine_check(void)
5158{
5159#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5160 struct pt_regs regs = {
5161 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5162 .flags = X86_EFLAGS_IF,
5163 };
5164
5165 do_machine_check(&regs, 0);
5166#endif
5167}
5168
851ba692 5169static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 5170{
5171 /* already handled by vcpu_run */
5172 return 1;
5173}
5174
851ba692 5175static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5176{
1155f76a 5177 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5178 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5179 u32 intr_info, ex_no, error_code;
42dbaa5a 5180 unsigned long cr2, rip, dr6;
6aa8b732
AK		 5181 u32 vect_info;
5182 enum emulation_result er;
5183
1155f76a 5184 vect_info = vmx->idt_vectoring_info;
88786475 5185 intr_info = vmx->exit_intr_info;
6aa8b732 5186
a0861c02 5187 if (is_machine_check(intr_info))
851ba692 5188 return handle_machine_check(vcpu);
a0861c02 5189
e4a41889 5190 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 5191 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 5192
5193 if (is_no_device(intr_info)) {
5fd86fcf 5194 vmx_fpu_activate(vcpu);
2ab455cc
AL		 5195 return 1;
5196 }
5197
7aa81cc0 5198 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK		 5199 if (is_guest_mode(vcpu)) {
5200 kvm_queue_exception(vcpu, UD_VECTOR);
5201 return 1;
5202 }
51d8b661 5203 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5204 if (er != EMULATE_DONE)
7ee5d940 5205 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 5206 return 1;
5207 }
5208
6aa8b732 5209 error_code = 0;
2e11384c 5210 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5211 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 5212
5213 /*
5214 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5215 * MMIO, it is better to report an internal error.
5216 * See the comments in vmx_handle_exit.
5217 */
5218 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5219 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5220 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5221 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5222 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 5223 vcpu->run->internal.data[0] = vect_info;
5224 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5225 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 5226 return 0;
5227 }
5228
6aa8b732 5229 if (is_page_fault(intr_info)) {
1439442c 5230 /* EPT won't cause page fault directly */
cf3ace79 5231 BUG_ON(enable_ept);
6aa8b732 5232 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5233 trace_kvm_page_fault(cr2, error_code);
5234
3298b75c 5235 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5236 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5237 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5238 }
5239
d0bfb940 5240 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5241
5242 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5243 return handle_rmode_exception(vcpu, ex_no, error_code);
5244
42dbaa5a
JK		 5245 switch (ex_no) {
5246 case DB_VECTOR:
5247 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5248 if (!(vcpu->guest_debug &
5249 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5250 vcpu->arch.dr6 &= ~15;
6f43ed01 5251 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5252 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5253 skip_emulated_instruction(vcpu);
5254
42dbaa5a
JK		 5255 kvm_queue_exception(vcpu, DB_VECTOR);
5256 return 1;
5257 }
5258 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5259 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5260 /* fall through */
5261 case BP_VECTOR:
c573cd22
JK		 5262 /*
5263 * Update instruction length as we may reinject #BP from
5264 * user space while in guest debugging mode. Reading it for
5265 * #DB as well causes no harm, it is not used in that case.
5266 */
5267 vmx->vcpu.arch.event_exit_inst_len =
5268 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5269 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5270 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5271 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5272 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5273 break;
5274 default:
d0bfb940
JK		 5275 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5276 kvm_run->ex.exception = ex_no;
5277 kvm_run->ex.error_code = error_code;
42dbaa5a 5278 break;
6aa8b732 5279 }
6aa8b732
AK		 5280 return 0;
5281}
5282
851ba692 5283static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5284{
1165f5fe 5285 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5286 return 1;
5287}
5288
851ba692 5289static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5290{
851ba692 5291 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5292 return 0;
5293}
6aa8b732 5294
851ba692 5295static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5296{
bfdaab09 5297 unsigned long exit_qualification;
34c33d16 5298 int size, in, string;
039576c0 5299 unsigned port;
6aa8b732 5300
bfdaab09 5301 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5302 string = (exit_qualification & 16) != 0;
cf8f70bf 5303 in = (exit_qualification & 8) != 0;
e70669ab 5304
cf8f70bf 5305 ++vcpu->stat.io_exits;
e70669ab 5306
cf8f70bf 5307 if (string || in)
51d8b661 5308 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5309
cf8f70bf
GN		 5310 port = exit_qualification >> 16;
5311 size = (exit_qualification & 7) + 1;
e93f36bc 5312 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5313
5314 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5315}
5316
102d8325
IM		 5317static void
5318vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5319{
5320 /*
5321 * Patch in the VMCALL instruction:
5322 */
5323 hypercall[0] = 0x0f;
5324 hypercall[1] = 0x01;
5325 hypercall[2] = 0xc1;
102d8325
IM		 5326}
5327
b9c237bb 5328static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5329{
5330 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5331 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5332
b9c237bb 5333 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5334 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5335 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5336 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5337 return (val & always_on) == always_on;
5338}
5339
0fa06071 5340/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5341static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5342{
eeadf9e7 5343 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5344 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5345 unsigned long orig_val = val;
5346
eeadf9e7
NHE		 5347 /*
5348 * We get here when L2 changed cr0 in a way that did not change
5349 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5350 * but did change L0 shadowed bits. So we first calculate the
5351 * effective cr0 value that L1 would like to write into the
5352 * hardware. It consists of the L2-owned bits from the new
5353 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5354 */
1a0d74e6
JK		 5355 val = (val & ~vmcs12->cr0_guest_host_mask) |
5356 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5357
b9c237bb 5358 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5359 return 1;
1a0d74e6
JK		 5360
5361 if (kvm_set_cr0(vcpu, val))
5362 return 1;
5363 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5364 return 0;
1a0d74e6
JK		 5365 } else {
5366 if (to_vmx(vcpu)->nested.vmxon &&
5367 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5368 return 1;
eeadf9e7 5369 return kvm_set_cr0(vcpu, val);
1a0d74e6 5370 }
eeadf9e7
NHE		 5371}
5372
5373static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5374{
5375 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5376 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5377 unsigned long orig_val = val;
5378
5379 /* analogously to handle_set_cr0 */
5380 val = (val & ~vmcs12->cr4_guest_host_mask) |
5381 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5382 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5383 return 1;
1a0d74e6 5384 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5385 return 0;
5386 } else
5387 return kvm_set_cr4(vcpu, val);
5388}
5389
5390/* called to set cr0 as approriate for clts instruction exit. */
5391static void handle_clts(struct kvm_vcpu *vcpu)
5392{
5393 if (is_guest_mode(vcpu)) {
5394 /*
5395 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5396 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5397 * just pretend it's off (also in arch.cr0 for fpu_activate).
5398 */
5399 vmcs_writel(CR0_READ_SHADOW,
5400 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5401 vcpu->arch.cr0 &= ~X86_CR0_TS;
5402 } else
5403 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5404}
5405
851ba692 5406static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5407{
229456fc 5408 unsigned long exit_qualification, val;
6aa8b732
AK		 5409 int cr;
5410 int reg;
49a9b07e 5411 int err;
6aa8b732 5412
bfdaab09 5413 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5414 cr = exit_qualification & 15;
5415 reg = (exit_qualification >> 8) & 15;
5416 switch ((exit_qualification >> 4) & 3) {
5417 case 0: /* mov to cr */
1e32c079 5418 val = kvm_register_readl(vcpu, reg);
229456fc 5419 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5420 switch (cr) {
5421 case 0:
eeadf9e7 5422 err = handle_set_cr0(vcpu, val);
db8fcefa 5423 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5424 return 1;
5425 case 3:
2390218b 5426 err = kvm_set_cr3(vcpu, val);
db8fcefa 5427 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5428 return 1;
5429 case 4:
eeadf9e7 5430 err = handle_set_cr4(vcpu, val);
db8fcefa 5431 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5432 return 1;
0a5fff19
GN		 5433 case 8: {
5434 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5435 u8 cr8 = (u8)val;
eea1cff9 5436 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5437 kvm_complete_insn_gp(vcpu, err);
35754c98 5438 if (lapic_in_kernel(vcpu))
0a5fff19
GN		 5439 return 1;
5440 if (cr8_prev <= cr8)
5441 return 1;
851ba692 5442 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5443 return 0;
5444 }
4b8073e4 5445 }
6aa8b732 5446 break;
25c4c276 5447 case 2: /* clts */
eeadf9e7 5448 handle_clts(vcpu);
4d4ec087 5449 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5450 skip_emulated_instruction(vcpu);
6b52d186 5451 vmx_fpu_activate(vcpu);
25c4c276 5452 return 1;
6aa8b732
AK		 5453 case 1: /*mov from cr*/
5454 switch (cr) {
5455 case 3:
9f8fe504
AK		 5456 val = kvm_read_cr3(vcpu);
5457 kvm_register_write(vcpu, reg, val);
5458 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5459 skip_emulated_instruction(vcpu);
5460 return 1;
5461 case 8:
229456fc
MT		 5462 val = kvm_get_cr8(vcpu);
5463 kvm_register_write(vcpu, reg, val);
5464 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5465 skip_emulated_instruction(vcpu);
5466 return 1;
5467 }
5468 break;
5469 case 3: /* lmsw */
a1f83a74 5470 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5471 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5472 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5473
5474 skip_emulated_instruction(vcpu);
5475 return 1;
5476 default:
5477 break;
5478 }
851ba692 5479 vcpu->run->exit_reason = 0;
a737f256 5480 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5481 (int)(exit_qualification >> 4) & 3, cr);
5482 return 0;
5483}
5484
851ba692 5485static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5486{
bfdaab09 5487 unsigned long exit_qualification;
16f8a6f9
NA		 5488 int dr, dr7, reg;
5489
5490 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5491 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5492
5493 /* First, if DR does not exist, trigger UD */
5494 if (!kvm_require_dr(vcpu, dr))
5495 return 1;
6aa8b732 5496
f2483415 5497 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5498 if (!kvm_require_cpl(vcpu, 0))
5499 return 1;
16f8a6f9
NA		 5500 dr7 = vmcs_readl(GUEST_DR7);
5501 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5502 /*
5503 * As the vm-exit takes precedence over the debug trap, we
5504 * need to emulate the latter, either for the host or the
5505 * guest debugging itself.
5506 */
5507 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5508 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5509 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5510 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5511 vcpu->run->debug.arch.exception = DB_VECTOR;
5512 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5513 return 0;
5514 } else {
7305eb5d 5515 vcpu->arch.dr6 &= ~15;
6f43ed01 5516 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5517 kvm_queue_exception(vcpu, DB_VECTOR);
5518 return 1;
5519 }
5520 }
5521
81908bf4
PB		 5522 if (vcpu->guest_debug == 0) {
5523 u32 cpu_based_vm_exec_control;
5524
5525 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5526 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5527 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5528
5529 /*
5530 * No more DR vmexits; force a reload of the debug registers
5531 * and reenter on this instruction. The next vmexit will
5532 * retrieve the full state of the debug registers.
5533 */
5534 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5535 return 1;
5536 }
5537
42dbaa5a
JK		 5538 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5539 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5540 unsigned long val;
4c4d563b
JK		 5541
5542 if (kvm_get_dr(vcpu, dr, &val))
5543 return 1;
5544 kvm_register_write(vcpu, reg, val);
020df079 5545 } else
5777392e 5546 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5547 return 1;
5548
6aa8b732
AK		 5549 skip_emulated_instruction(vcpu);
5550 return 1;
5551}
5552
73aaf249
JK		 5553static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5554{
5555 return vcpu->arch.dr6;
5556}
5557
5558static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5559{
5560}
5561
81908bf4
PB		 5562static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5563{
5564 u32 cpu_based_vm_exec_control;
5565
5566 get_debugreg(vcpu->arch.db[0], 0);
5567 get_debugreg(vcpu->arch.db[1], 1);
5568 get_debugreg(vcpu->arch.db[2], 2);
5569 get_debugreg(vcpu->arch.db[3], 3);
5570 get_debugreg(vcpu->arch.dr6, 6);
5571 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5572
5573 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5574
5575 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5576 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5577 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5578}
5579
020df079
GN		 5580static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5581{
5582 vmcs_writel(GUEST_DR7, val);
5583}
5584
851ba692 5585static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5586{
06465c5a
AK		 5587 kvm_emulate_cpuid(vcpu);
5588 return 1;
6aa8b732
AK		 5589}
5590
851ba692 5591static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5592{
ad312c7c 5593 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 5594 struct msr_data msr_info;
6aa8b732 5595
609e36d3
PB		 5596 msr_info.index = ecx;
5597 msr_info.host_initiated = false;
5598 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 5599 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5600 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5601 return 1;
5602 }
5603
609e36d3 5604 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 5605
6aa8b732 5606 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB		 5607 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5608 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6aa8b732
AK		 5609 skip_emulated_instruction(vcpu);
5610 return 1;
5611}
5612
851ba692 5613static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5614{
8fe8ab46 5615 struct msr_data msr;
ad312c7c
ZX		 5616 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5617 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5618 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5619
8fe8ab46
WA		 5620 msr.data = data;
5621 msr.index = ecx;
5622 msr.host_initiated = false;
854e8bb1 5623 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5624 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5625 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5626 return 1;
5627 }
5628
59200273 5629 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5630 skip_emulated_instruction(vcpu);
5631 return 1;
5632}
5633
851ba692 5634static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5635{
3842d135 5636 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5637 return 1;
5638}
5639
851ba692 5640static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5641{
85f455f7
ED		 5642 u32 cpu_based_vm_exec_control;
5643
5644 /* clear pending irq */
5645 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5646 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5647 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5648
3842d135
AK		 5649 kvm_make_request(KVM_REQ_EVENT, vcpu);
5650
a26bf12a 5651 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 5652 return 1;
5653}
5654
851ba692 5655static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 5656{
d3bef15f 5657 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5658}
5659
851ba692 5660static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5661{
7aa81cc0
AL		 5662 kvm_emulate_hypercall(vcpu);
5663 return 1;
c21415e8
IM		 5664}
5665
ec25d5e6
GN		 5666static int handle_invd(struct kvm_vcpu *vcpu)
5667{
51d8b661 5668 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5669}
5670
851ba692 5671static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5672{
f9c617f6 5673 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5674
5675 kvm_mmu_invlpg(vcpu, exit_qualification);
5676 skip_emulated_instruction(vcpu);
5677 return 1;
5678}
5679
fee84b07
AK		 5680static int handle_rdpmc(struct kvm_vcpu *vcpu)
5681{
5682 int err;
5683
5684 err = kvm_rdpmc(vcpu);
5685 kvm_complete_insn_gp(vcpu, err);
5686
5687 return 1;
5688}
5689
851ba692 5690static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5691{
f5f48ee1 5692 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5693 return 1;
5694}
5695
2acf923e
DC		 5696static int handle_xsetbv(struct kvm_vcpu *vcpu)
5697{
5698 u64 new_bv = kvm_read_edx_eax(vcpu);
5699 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5700
5701 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5702 skip_emulated_instruction(vcpu);
5703 return 1;
5704}
5705
f53cd63c
WL		 5706static int handle_xsaves(struct kvm_vcpu *vcpu)
5707{
5708 skip_emulated_instruction(vcpu);
5709 WARN(1, "this should never happen\n");
5710 return 1;
5711}
5712
5713static int handle_xrstors(struct kvm_vcpu *vcpu)
5714{
5715 skip_emulated_instruction(vcpu);
5716 WARN(1, "this should never happen\n");
5717 return 1;
5718}
5719
851ba692 5720static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5721{
58fbbf26
KT		 5722 if (likely(fasteoi)) {
5723 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5724 int access_type, offset;
5725
5726 access_type = exit_qualification & APIC_ACCESS_TYPE;
5727 offset = exit_qualification & APIC_ACCESS_OFFSET;
5728 /*
5729 * Sane guest uses MOV to write EOI, with written value
5730 * not cared. So make a short-circuit here by avoiding
5731 * heavy instruction emulation.
5732 */
5733 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5734 (offset == APIC_EOI)) {
5735 kvm_lapic_set_eoi(vcpu);
5736 skip_emulated_instruction(vcpu);
5737 return 1;
5738 }
5739 }
51d8b661 5740 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5741}
5742
c7c9c56c
YZ		 5743static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5744{
5745 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5746 int vector = exit_qualification & 0xff;
5747
5748 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5749 kvm_apic_set_eoi_accelerated(vcpu, vector);
5750 return 1;
5751}
5752
83d4c286
YZ		 5753static int handle_apic_write(struct kvm_vcpu *vcpu)
5754{
5755 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5756 u32 offset = exit_qualification & 0xfff;
5757
5758 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5759 kvm_apic_write_nodecode(vcpu, offset);
5760 return 1;
5761}
5762
851ba692 5763static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5764{
60637aac 5765 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5766 unsigned long exit_qualification;
e269fb21
JK		 5767 bool has_error_code = false;
5768 u32 error_code = 0;
37817f29 5769 u16 tss_selector;
7f3d35fd 5770 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5771
5772 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5773 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5774 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5775
5776 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5777
5778 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5779 if (reason == TASK_SWITCH_GATE && idt_v) {
5780 switch (type) {
5781 case INTR_TYPE_NMI_INTR:
5782 vcpu->arch.nmi_injected = false;
654f06fc 5783 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5784 break;
5785 case INTR_TYPE_EXT_INTR:
66fd3f7f 5786 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5787 kvm_clear_interrupt_queue(vcpu);
5788 break;
5789 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5790 if (vmx->idt_vectoring_info &
5791 VECTORING_INFO_DELIVER_CODE_MASK) {
5792 has_error_code = true;
5793 error_code =
5794 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5795 }
5796 /* fall through */
64a7ec06
GN		 5797 case INTR_TYPE_SOFT_EXCEPTION:
5798 kvm_clear_exception_queue(vcpu);
5799 break;
5800 default:
5801 break;
5802 }
60637aac 5803 }
37817f29
IE		 5804 tss_selector = exit_qualification;
5805
64a7ec06
GN		 5806 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5807 type != INTR_TYPE_EXT_INTR &&
5808 type != INTR_TYPE_NMI_INTR))
5809 skip_emulated_instruction(vcpu);
5810
7f3d35fd
KW		 5811 if (kvm_task_switch(vcpu, tss_selector,
5812 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5813 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5814 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5815 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5816 vcpu->run->internal.ndata = 0;
42dbaa5a 5817 return 0;
acb54517 5818 }
42dbaa5a 5819
42dbaa5a
JK		 5820 /*
5821 * TODO: What about debug traps on tss switch?
5822 * Are we supposed to inject them and update dr6?
5823 */
5824
5825 return 1;
37817f29
IE		 5826}
5827
851ba692 5828static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5829{
f9c617f6 5830 unsigned long exit_qualification;
1439442c 5831 gpa_t gpa;
4f5982a5 5832 u32 error_code;
1439442c 5833 int gla_validity;
1439442c 5834
f9c617f6 5835 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5836
1439442c
SY		 5837 gla_validity = (exit_qualification >> 7) & 0x3;
5838 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5839 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5840 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5841 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5842 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5843 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5844 (long unsigned int)exit_qualification);
851ba692
AK		 5845 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5846 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5847 return 0;
1439442c
SY		 5848 }
5849
0be9c7a8
GN		 5850 /*
5851 * EPT violation happened while executing iret from NMI,
5852 * "blocked by NMI" bit has to be set before next VM entry.
5853 * There are errata that may cause this bit to not be set:
5854 * AAK134, BY25.
5855 */
bcd1c294
GN		 5856 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5857 cpu_has_virtual_nmis() &&
5858 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5859 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5860
1439442c 5861 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5862 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5863
5864 /* It is a write fault? */
81ed33e4 5865 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5866 /* It is a fetch fault? */
81ed33e4 5867 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5868 /* ept page table is present? */
81ed33e4 5869 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5870
25d92081
YZ		 5871 vcpu->arch.exit_qualification = exit_qualification;
5872
4f5982a5 5873 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5874}
5875
851ba692 5876static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5877{
f735d4af 5878 int ret;
68f89400
MT		 5879 gpa_t gpa;
5880
5881 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 5882 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
68c3b4d1 5883 skip_emulated_instruction(vcpu);
931c33b1 5884 trace_kvm_fast_mmio(gpa);
68c3b4d1
MT		 5885 return 1;
5886 }
68f89400 5887
ce88decf 5888 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5889 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5890 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5891 EMULATE_DONE;
f8f55942
XG		 5892
5893 if (unlikely(ret == RET_MMIO_PF_INVALID))
5894 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5895
b37fbea6 5896 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5897 return 1;
5898
5899 /* It is the real ept misconfig */
f735d4af 5900 WARN_ON(1);
68f89400 5901
851ba692
AK		 5902 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5903 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5904
5905 return 0;
5906}
5907
851ba692 5908static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5909{
5910 u32 cpu_based_vm_exec_control;
5911
5912 /* clear pending NMI */
5913 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5914 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5915 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5916 ++vcpu->stat.nmi_window_exits;
3842d135 5917 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5918
5919 return 1;
5920}
5921
80ced186 5922static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5923{
8b3079a5
AK		 5924 struct vcpu_vmx *vmx = to_vmx(vcpu);
5925 enum emulation_result err = EMULATE_DONE;
80ced186 5926 int ret = 1;
49e9d557
AK		 5927 u32 cpu_exec_ctrl;
5928 bool intr_window_requested;
b8405c18 5929 unsigned count = 130;
49e9d557
AK		 5930
5931 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5932 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5933
98eb2f8b 5934 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5935 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5936 return handle_interrupt_window(&vmx->vcpu);
5937
de87dcdd
AK		 5938 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5939 return 1;
5940
991eebf9 5941 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5942
ac0a48c3 5943 if (err == EMULATE_USER_EXIT) {
94452b9e 5944 ++vcpu->stat.mmio_exits;
80ced186
MG		 5945 ret = 0;
5946 goto out;
5947 }
1d5a4d9b 5948
de5f70e0
AK		 5949 if (err != EMULATE_DONE) {
5950 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5951 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5952 vcpu->run->internal.ndata = 0;
6d77dbfc 5953 return 0;
de5f70e0 5954 }
ea953ef0 5955
8d76c49e
GN		 5956 if (vcpu->arch.halt_request) {
5957 vcpu->arch.halt_request = 0;
5cb56059 5958 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5959 goto out;
5960 }
5961
ea953ef0 5962 if (signal_pending(current))
80ced186 5963 goto out;
ea953ef0
MG		 5964 if (need_resched())
5965 schedule();
5966 }
5967
80ced186
MG		 5968out:
5969 return ret;
ea953ef0
MG		 5970}
5971
b4a2d31d
RK		 5972static int __grow_ple_window(int val)
5973{
5974 if (ple_window_grow < 1)
5975 return ple_window;
5976
5977 val = min(val, ple_window_actual_max);
5978
5979 if (ple_window_grow < ple_window)
5980 val *= ple_window_grow;
5981 else
5982 val += ple_window_grow;
5983
5984 return val;
5985}
5986
5987static int __shrink_ple_window(int val, int modifier, int minimum)
5988{
5989 if (modifier < 1)
5990 return ple_window;
5991
5992 if (modifier < ple_window)
5993 val /= modifier;
5994 else
5995 val -= modifier;
5996
5997 return max(val, minimum);
5998}
5999
6000static void grow_ple_window(struct kvm_vcpu *vcpu)
6001{
6002 struct vcpu_vmx *vmx = to_vmx(vcpu);
6003 int old = vmx->ple_window;
6004
6005 vmx->ple_window = __grow_ple_window(old);
6006
6007 if (vmx->ple_window != old)
6008 vmx->ple_window_dirty = true;
7b46268d
RK		 6009
6010 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 6011}
6012
6013static void shrink_ple_window(struct kvm_vcpu *vcpu)
6014{
6015 struct vcpu_vmx *vmx = to_vmx(vcpu);
6016 int old = vmx->ple_window;
6017
6018 vmx->ple_window = __shrink_ple_window(old,
6019 ple_window_shrink, ple_window);
6020
6021 if (vmx->ple_window != old)
6022 vmx->ple_window_dirty = true;
7b46268d
RK		 6023
6024 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 6025}
6026
6027/*
6028 * ple_window_actual_max is computed to be one grow_ple_window() below
6029 * ple_window_max. (See __grow_ple_window for the reason.)
6030 * This prevents overflows, because ple_window_max is int.
6031 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6032 * this process.
6033 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6034 */
6035static void update_ple_window_actual_max(void)
6036{
6037 ple_window_actual_max =
6038 __shrink_ple_window(max(ple_window_max, ple_window),
6039 ple_window_grow, INT_MIN);
6040}
6041
bf9f6ac8
FW		 6042/*
6043 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6044 */
6045static void wakeup_handler(void)
6046{
6047 struct kvm_vcpu *vcpu;
6048 int cpu = smp_processor_id();
6049
6050 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6051 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6052 blocked_vcpu_list) {
6053 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6054
6055 if (pi_test_on(pi_desc) == 1)
6056 kvm_vcpu_kick(vcpu);
6057 }
6058 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6059}
6060
f2c7648d
TC		 6061static __init int hardware_setup(void)
6062{
34a1cd60
TC		 6063 int r = -ENOMEM, i, msr;
6064
6065 rdmsrl_safe(MSR_EFER, &host_efer);
6066
6067 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6068 kvm_define_shared_msr(i, vmx_msr_index[i]);
6069
6070 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6071 if (!vmx_io_bitmap_a)
6072 return r;
6073
6074 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6075 if (!vmx_io_bitmap_b)
6076 goto out;
6077
6078 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6079 if (!vmx_msr_bitmap_legacy)
6080 goto out1;
6081
6082 vmx_msr_bitmap_legacy_x2apic =
6083 (unsigned long *)__get_free_page(GFP_KERNEL);
6084 if (!vmx_msr_bitmap_legacy_x2apic)
6085 goto out2;
6086
6087 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6088 if (!vmx_msr_bitmap_longmode)
6089 goto out3;
6090
6091 vmx_msr_bitmap_longmode_x2apic =
6092 (unsigned long *)__get_free_page(GFP_KERNEL);
6093 if (!vmx_msr_bitmap_longmode_x2apic)
6094 goto out4;
3af18d9c
WV		 6095
6096 if (nested) {
6097 vmx_msr_bitmap_nested =
6098 (unsigned long *)__get_free_page(GFP_KERNEL);
6099 if (!vmx_msr_bitmap_nested)
6100 goto out5;
6101 }
6102
34a1cd60
TC		 6103 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6104 if (!vmx_vmread_bitmap)
3af18d9c 6105 goto out6;
34a1cd60
TC		 6106
6107 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6108 if (!vmx_vmwrite_bitmap)
3af18d9c 6109 goto out7;
34a1cd60
TC		 6110
6111 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6112 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6113
6114 /*
6115 * Allow direct access to the PC debug port (it is often used for I/O
6116 * delays, but the vmexits simply slow things down).
6117 */
6118 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6119 clear_bit(0x80, vmx_io_bitmap_a);
6120
6121 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6122
6123 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6124 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 6125 if (nested)
6126 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 6127
34a1cd60
TC		 6128 if (setup_vmcs_config(&vmcs_config) < 0) {
6129 r = -EIO;
3af18d9c 6130 goto out8;
baa03522 6131 }
f2c7648d
TC		 6132
6133 if (boot_cpu_has(X86_FEATURE_NX))
6134 kvm_enable_efer_bits(EFER_NX);
6135
6136 if (!cpu_has_vmx_vpid())
6137 enable_vpid = 0;
6138 if (!cpu_has_vmx_shadow_vmcs())
6139 enable_shadow_vmcs = 0;
6140 if (enable_shadow_vmcs)
6141 init_vmcs_shadow_fields();
6142
6143 if (!cpu_has_vmx_ept() ||
6144 !cpu_has_vmx_ept_4levels()) {
6145 enable_ept = 0;
6146 enable_unrestricted_guest = 0;
6147 enable_ept_ad_bits = 0;
6148 }
6149
6150 if (!cpu_has_vmx_ept_ad_bits())
6151 enable_ept_ad_bits = 0;
6152
6153 if (!cpu_has_vmx_unrestricted_guest())
6154 enable_unrestricted_guest = 0;
6155
ad15a296 6156 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6157 flexpriority_enabled = 0;
6158
ad15a296
PB		 6159 /*
6160 * set_apic_access_page_addr() is used to reload apic access
6161 * page upon invalidation. No need to do anything if not
6162 * using the APIC_ACCESS_ADDR VMCS field.
6163 */
6164 if (!flexpriority_enabled)
f2c7648d 6165 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6166
6167 if (!cpu_has_vmx_tpr_shadow())
6168 kvm_x86_ops->update_cr8_intercept = NULL;
6169
6170 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6171 kvm_disable_largepages();
6172
6173 if (!cpu_has_vmx_ple())
6174 ple_gap = 0;
6175
6176 if (!cpu_has_vmx_apicv())
6177 enable_apicv = 0;
6178
6179 if (enable_apicv)
6180 kvm_x86_ops->update_cr8_intercept = NULL;
6181 else {
6182 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6183 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6184 kvm_x86_ops->deliver_posted_interrupt = NULL;
6185 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6186 }
6187
baa03522
TC		 6188 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6189 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6190 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6191 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6192 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6193 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6194 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6195
6196 memcpy(vmx_msr_bitmap_legacy_x2apic,
6197 vmx_msr_bitmap_legacy, PAGE_SIZE);
6198 memcpy(vmx_msr_bitmap_longmode_x2apic,
6199 vmx_msr_bitmap_longmode, PAGE_SIZE);
6200
04bb92e4
WL		 6201 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6202
baa03522
TC		 6203 if (enable_apicv) {
6204 for (msr = 0x800; msr <= 0x8ff; msr++)
6205 vmx_disable_intercept_msr_read_x2apic(msr);
6206
6207 /* According SDM, in x2apic mode, the whole id reg is used.
6208 * But in KVM, it only use the highest eight bits. Need to
6209 * intercept it */
6210 vmx_enable_intercept_msr_read_x2apic(0x802);
6211 /* TMCCT */
6212 vmx_enable_intercept_msr_read_x2apic(0x839);
6213 /* TPR */
6214 vmx_disable_intercept_msr_write_x2apic(0x808);
6215 /* EOI */
6216 vmx_disable_intercept_msr_write_x2apic(0x80b);
6217 /* SELF-IPI */
6218 vmx_disable_intercept_msr_write_x2apic(0x83f);
6219 }
6220
6221 if (enable_ept) {
6222 kvm_mmu_set_mask_ptes(0ull,
6223 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6224 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6225 0ull, VMX_EPT_EXECUTABLE_MASK);
6226 ept_set_mmio_spte_mask();
6227 kvm_enable_tdp();
6228 } else
6229 kvm_disable_tdp();
6230
6231 update_ple_window_actual_max();
6232
843e4330
KH		 6233 /*
6234 * Only enable PML when hardware supports PML feature, and both EPT
6235 * and EPT A/D bit features are enabled -- PML depends on them to work.
6236 */
6237 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6238 enable_pml = 0;
6239
6240 if (!enable_pml) {
6241 kvm_x86_ops->slot_enable_log_dirty = NULL;
6242 kvm_x86_ops->slot_disable_log_dirty = NULL;
6243 kvm_x86_ops->flush_log_dirty = NULL;
6244 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6245 }
6246
bf9f6ac8
FW		 6247 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6248
f2c7648d 6249 return alloc_kvm_area();
34a1cd60 6250
3af18d9c 6251out8:
34a1cd60 6252 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6253out7:
34a1cd60 6254 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6255out6:
6256 if (nested)
6257 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6258out5:
6259 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6260out4:
6261 free_page((unsigned long)vmx_msr_bitmap_longmode);
6262out3:
6263 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6264out2:
6265 free_page((unsigned long)vmx_msr_bitmap_legacy);
6266out1:
6267 free_page((unsigned long)vmx_io_bitmap_b);
6268out:
6269 free_page((unsigned long)vmx_io_bitmap_a);
6270
6271 return r;
f2c7648d
TC		 6272}
6273
6274static __exit void hardware_unsetup(void)
6275{
34a1cd60
TC		 6276 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6277 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6278 free_page((unsigned long)vmx_msr_bitmap_legacy);
6279 free_page((unsigned long)vmx_msr_bitmap_longmode);
6280 free_page((unsigned long)vmx_io_bitmap_b);
6281 free_page((unsigned long)vmx_io_bitmap_a);
6282 free_page((unsigned long)vmx_vmwrite_bitmap);
6283 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6284 if (nested)
6285 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6286
f2c7648d
TC		 6287 free_kvm_area();
6288}
6289
4b8d54f9
ZE		 6290/*
6291 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6292 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6293 */
9fb41ba8 6294static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6295{
b4a2d31d
RK		 6296 if (ple_gap)
6297 grow_ple_window(vcpu);
6298
4b8d54f9
ZE		 6299 skip_emulated_instruction(vcpu);
6300 kvm_vcpu_on_spin(vcpu);
6301
6302 return 1;
6303}
6304
87c00572 6305static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6306{
87c00572 6307 skip_emulated_instruction(vcpu);
59708670
SY		 6308 return 1;
6309}
6310
87c00572
GS		 6311static int handle_mwait(struct kvm_vcpu *vcpu)
6312{
6313 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6314 return handle_nop(vcpu);
6315}
6316
5f3d45e7
MD		 6317static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6318{
6319 return 1;
6320}
6321
87c00572
GS		 6322static int handle_monitor(struct kvm_vcpu *vcpu)
6323{
6324 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6325 return handle_nop(vcpu);
6326}
6327
ff2f6fe9
NHE		 6328/*
6329 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6330 * We could reuse a single VMCS for all the L2 guests, but we also want the
6331 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6332 * allows keeping them loaded on the processor, and in the future will allow
6333 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6334 * every entry if they never change.
6335 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6336 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6337 *
6338 * The following functions allocate and free a vmcs02 in this pool.
6339 */
6340
6341/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6342static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6343{
6344 struct vmcs02_list *item;
6345 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6346 if (item->vmptr == vmx->nested.current_vmptr) {
6347 list_move(&item->list, &vmx->nested.vmcs02_pool);
6348 return &item->vmcs02;
6349 }
6350
6351 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6352 /* Recycle the least recently used VMCS. */
6353 item = list_entry(vmx->nested.vmcs02_pool.prev,
6354 struct vmcs02_list, list);
6355 item->vmptr = vmx->nested.current_vmptr;
6356 list_move(&item->list, &vmx->nested.vmcs02_pool);
6357 return &item->vmcs02;
6358 }
6359
6360 /* Create a new VMCS */
0fa24ce3 6361 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6362 if (!item)
6363 return NULL;
6364 item->vmcs02.vmcs = alloc_vmcs();
6365 if (!item->vmcs02.vmcs) {
6366 kfree(item);
6367 return NULL;
6368 }
6369 loaded_vmcs_init(&item->vmcs02);
6370 item->vmptr = vmx->nested.current_vmptr;
6371 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6372 vmx->nested.vmcs02_num++;
6373 return &item->vmcs02;
6374}
6375
6376/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6377static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6378{
6379 struct vmcs02_list *item;
6380 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6381 if (item->vmptr == vmptr) {
6382 free_loaded_vmcs(&item->vmcs02);
6383 list_del(&item->list);
6384 kfree(item);
6385 vmx->nested.vmcs02_num--;
6386 return;
6387 }
6388}
6389
6390/*
6391 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6392 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6393 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6394 */
6395static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6396{
6397 struct vmcs02_list *item, *n;
4fa7734c
PB		 6398
6399 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6400 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6401 /*
6402 * Something will leak if the above WARN triggers. Better than
6403 * a use-after-free.
6404 */
6405 if (vmx->loaded_vmcs == &item->vmcs02)
6406 continue;
6407
6408 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6409 list_del(&item->list);
6410 kfree(item);
4fa7734c 6411 vmx->nested.vmcs02_num--;
ff2f6fe9 6412 }
ff2f6fe9
NHE		 6413}
6414
0658fbaa
ACL		 6415/*
6416 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6417 * set the success or error code of an emulated VMX instruction, as specified
6418 * by Vol 2B, VMX Instruction Reference, "Conventions".
6419 */
6420static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6421{
6422 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6423 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6424 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6425}
6426
6427static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6428{
6429 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6430 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6431 X86_EFLAGS_SF | X86_EFLAGS_OF))
6432 | X86_EFLAGS_CF);
6433}
6434
145c28dd 6435static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6436 u32 vm_instruction_error)
6437{
6438 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6439 /*
6440 * failValid writes the error number to the current VMCS, which
6441 * can't be done there isn't a current VMCS.
6442 */
6443 nested_vmx_failInvalid(vcpu);
6444 return;
6445 }
6446 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6447 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6448 X86_EFLAGS_SF | X86_EFLAGS_OF))
6449 | X86_EFLAGS_ZF);
6450 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6451 /*
6452 * We don't need to force a shadow sync because
6453 * VM_INSTRUCTION_ERROR is not shadowed
6454 */
6455}
145c28dd 6456
ff651cb6
WV		 6457static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6458{
6459 /* TODO: not to reset guest simply here. */
6460 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6461 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6462}
6463
f4124500
JK		 6464static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6465{
6466 struct vcpu_vmx *vmx =
6467 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6468
6469 vmx->nested.preemption_timer_expired = true;
6470 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6471 kvm_vcpu_kick(&vmx->vcpu);
6472
6473 return HRTIMER_NORESTART;
6474}
6475
19677e32
BD		 6476/*
6477 * Decode the memory-address operand of a vmx instruction, as recorded on an
6478 * exit caused by such an instruction (run by a guest hypervisor).
6479 * On success, returns 0. When the operand is invalid, returns 1 and throws
6480 * #UD or #GP.
6481 */
6482static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6483 unsigned long exit_qualification,
f9eb4af6 6484 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6485{
f9eb4af6
EK		 6486 gva_t off;
6487 bool exn;
6488 struct kvm_segment s;
6489
19677e32
BD		 6490 /*
6491 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6492 * Execution", on an exit, vmx_instruction_info holds most of the
6493 * addressing components of the operand. Only the displacement part
6494 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6495 * For how an actual address is calculated from all these components,
6496 * refer to Vol. 1, "Operand Addressing".
6497 */
6498 int scaling = vmx_instruction_info & 3;
6499 int addr_size = (vmx_instruction_info >> 7) & 7;
6500 bool is_reg = vmx_instruction_info & (1u << 10);
6501 int seg_reg = (vmx_instruction_info >> 15) & 7;
6502 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6503 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6504 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6505 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6506
6507 if (is_reg) {
6508 kvm_queue_exception(vcpu, UD_VECTOR);
6509 return 1;
6510 }
6511
6512 /* Addr = segment_base + offset */
6513 /* offset = base + [index * scale] + displacement */
f9eb4af6 6514 off = exit_qualification; /* holds the displacement */
19677e32 6515 if (base_is_valid)
f9eb4af6 6516 off += kvm_register_read(vcpu, base_reg);
19677e32 6517 if (index_is_valid)
f9eb4af6
EK		 6518 off += kvm_register_read(vcpu, index_reg)<<scaling;
6519 vmx_get_segment(vcpu, &s, seg_reg);
6520 *ret = s.base + off;
19677e32
BD		 6521
6522 if (addr_size == 1) /* 32 bit */
6523 *ret &= 0xffffffff;
6524
f9eb4af6
EK		 6525 /* Checks for #GP/#SS exceptions. */
6526 exn = false;
6527 if (is_protmode(vcpu)) {
6528 /* Protected mode: apply checks for segment validity in the
6529 * following order:
6530 * - segment type check (#GP(0) may be thrown)
6531 * - usability check (#GP(0)/#SS(0))
6532 * - limit check (#GP(0)/#SS(0))
6533 */
6534 if (wr)
6535 /* #GP(0) if the destination operand is located in a
6536 * read-only data segment or any code segment.
6537 */
6538 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6539 else
6540 /* #GP(0) if the source operand is located in an
6541 * execute-only code segment
6542 */
6543 exn = ((s.type & 0xa) == 8);
6544 }
6545 if (exn) {
6546 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6547 return 1;
6548 }
6549 if (is_long_mode(vcpu)) {
6550 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6551 * non-canonical form. This is an only check for long mode.
6552 */
6553 exn = is_noncanonical_address(*ret);
6554 } else if (is_protmode(vcpu)) {
6555 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6556 */
6557 exn = (s.unusable != 0);
6558 /* Protected mode: #GP(0)/#SS(0) if the memory
6559 * operand is outside the segment limit.
6560 */
6561 exn = exn || (off + sizeof(u64) > s.limit);
6562 }
6563 if (exn) {
6564 kvm_queue_exception_e(vcpu,
6565 seg_reg == VCPU_SREG_SS ?
6566 SS_VECTOR : GP_VECTOR,
6567 0);
6568 return 1;
6569 }
6570
19677e32
BD		 6571 return 0;
6572}
6573
3573e22c
BD		 6574/*
6575 * This function performs the various checks including
6576 * - if it's 4KB aligned
6577 * - No bits beyond the physical address width are set
6578 * - Returns 0 on success or else 1
4291b588 6579 * (Intel SDM Section 30.3)
3573e22c 6580 */
4291b588
BD		 6581static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6582 gpa_t *vmpointer)
3573e22c
BD		 6583{
6584 gva_t gva;
6585 gpa_t vmptr;
6586 struct x86_exception e;
6587 struct page *page;
6588 struct vcpu_vmx *vmx = to_vmx(vcpu);
6589 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6590
6591 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 6592 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD		 6593 return 1;
6594
6595 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6596 sizeof(vmptr), &e)) {
6597 kvm_inject_page_fault(vcpu, &e);
6598 return 1;
6599 }
6600
6601 switch (exit_reason) {
6602 case EXIT_REASON_VMON:
6603 /*
6604 * SDM 3: 24.11.5
6605 * The first 4 bytes of VMXON region contain the supported
6606 * VMCS revision identifier
6607 *
6608 * Note - IA32_VMX_BASIC[48] will never be 1
6609 * for the nested case;
6610 * which replaces physical address width with 32
6611 *
6612 */
bc39c4db 6613 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6614 nested_vmx_failInvalid(vcpu);
6615 skip_emulated_instruction(vcpu);
6616 return 1;
6617 }
6618
6619 page = nested_get_page(vcpu, vmptr);
6620 if (page == NULL ||
6621 *(u32 *)kmap(page) != VMCS12_REVISION) {
6622 nested_vmx_failInvalid(vcpu);
6623 kunmap(page);
6624 skip_emulated_instruction(vcpu);
6625 return 1;
6626 }
6627 kunmap(page);
6628 vmx->nested.vmxon_ptr = vmptr;
6629 break;
4291b588 6630 case EXIT_REASON_VMCLEAR:
bc39c4db 6631 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6632 nested_vmx_failValid(vcpu,
6633 VMXERR_VMCLEAR_INVALID_ADDRESS);
6634 skip_emulated_instruction(vcpu);
6635 return 1;
6636 }
6637
6638 if (vmptr == vmx->nested.vmxon_ptr) {
6639 nested_vmx_failValid(vcpu,
6640 VMXERR_VMCLEAR_VMXON_POINTER);
6641 skip_emulated_instruction(vcpu);
6642 return 1;
6643 }
6644 break;
6645 case EXIT_REASON_VMPTRLD:
bc39c4db 6646 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6647 nested_vmx_failValid(vcpu,
6648 VMXERR_VMPTRLD_INVALID_ADDRESS);
6649 skip_emulated_instruction(vcpu);
6650 return 1;
6651 }
3573e22c 6652
4291b588
BD		 6653 if (vmptr == vmx->nested.vmxon_ptr) {
6654 nested_vmx_failValid(vcpu,
6655 VMXERR_VMCLEAR_VMXON_POINTER);
6656 skip_emulated_instruction(vcpu);
6657 return 1;
6658 }
6659 break;
3573e22c
BD		 6660 default:
6661 return 1; /* shouldn't happen */
6662 }
6663
4291b588
BD		 6664 if (vmpointer)
6665 *vmpointer = vmptr;
3573e22c
BD		 6666 return 0;
6667}
6668
ec378aee
NHE		 6669/*
6670 * Emulate the VMXON instruction.
6671 * Currently, we just remember that VMX is active, and do not save or even
6672 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6673 * do not currently need to store anything in that guest-allocated memory
6674 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6675 * argument is different from the VMXON pointer (which the spec says they do).
6676 */
6677static int handle_vmon(struct kvm_vcpu *vcpu)
6678{
6679 struct kvm_segment cs;
6680 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6681 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6682 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6683 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6684
6685 /* The Intel VMX Instruction Reference lists a bunch of bits that
6686 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6687 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6688 * Otherwise, we should fail with #UD. We test these now:
6689 */
6690 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6691 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6692 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6693 kvm_queue_exception(vcpu, UD_VECTOR);
6694 return 1;
6695 }
6696
6697 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6698 if (is_long_mode(vcpu) && !cs.l) {
6699 kvm_queue_exception(vcpu, UD_VECTOR);
6700 return 1;
6701 }
6702
6703 if (vmx_get_cpl(vcpu)) {
6704 kvm_inject_gp(vcpu, 0);
6705 return 1;
6706 }
3573e22c 6707
4291b588 6708 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6709 return 1;
6710
145c28dd
AG		 6711 if (vmx->nested.vmxon) {
6712 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6713 skip_emulated_instruction(vcpu);
6714 return 1;
6715 }
b3897a49
NHE		 6716
6717 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6718 != VMXON_NEEDED_FEATURES) {
6719 kvm_inject_gp(vcpu, 0);
6720 return 1;
6721 }
6722
8de48833
AG		 6723 if (enable_shadow_vmcs) {
6724 shadow_vmcs = alloc_vmcs();
6725 if (!shadow_vmcs)
6726 return -ENOMEM;
6727 /* mark vmcs as shadow */
6728 shadow_vmcs->revision_id |= (1u << 31);
6729 /* init shadow vmcs */
6730 vmcs_clear(shadow_vmcs);
6731 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6732 }
ec378aee 6733
ff2f6fe9
NHE		 6734 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6735 vmx->nested.vmcs02_num = 0;
6736
f4124500
JK		 6737 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6738 HRTIMER_MODE_REL);
6739 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6740
ec378aee
NHE		 6741 vmx->nested.vmxon = true;
6742
6743 skip_emulated_instruction(vcpu);
a25eb114 6744 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6745 return 1;
6746}
6747
6748/*
6749 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6750 * for running VMX instructions (except VMXON, whose prerequisites are
6751 * slightly different). It also specifies what exception to inject otherwise.
6752 */
6753static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6754{
6755 struct kvm_segment cs;
6756 struct vcpu_vmx *vmx = to_vmx(vcpu);
6757
6758 if (!vmx->nested.vmxon) {
6759 kvm_queue_exception(vcpu, UD_VECTOR);
6760 return 0;
6761 }
6762
6763 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6764 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6765 (is_long_mode(vcpu) && !cs.l)) {
6766 kvm_queue_exception(vcpu, UD_VECTOR);
6767 return 0;
6768 }
6769
6770 if (vmx_get_cpl(vcpu)) {
6771 kvm_inject_gp(vcpu, 0);
6772 return 0;
6773 }
6774
6775 return 1;
6776}
6777
e7953d7f
AG		 6778static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6779{
9a2a05b9
PB		 6780 if (vmx->nested.current_vmptr == -1ull)
6781 return;
6782
6783 /* current_vmptr and current_vmcs12 are always set/reset together */
6784 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6785 return;
6786
012f83cb 6787 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6788 /* copy to memory all shadowed fields in case
6789 they were modified */
6790 copy_shadow_to_vmcs12(vmx);
6791 vmx->nested.sync_shadow_vmcs = false;
7ec36296
XG		 6792 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6793 SECONDARY_EXEC_SHADOW_VMCS);
9a2a05b9 6794 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6795 }
705699a1 6796 vmx->nested.posted_intr_nv = -1;
e7953d7f
AG		 6797 kunmap(vmx->nested.current_vmcs12_page);
6798 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6799 vmx->nested.current_vmptr = -1ull;
6800 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6801}
6802
ec378aee
NHE		 6803/*
6804 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6805 * just stops using VMX.
6806 */
6807static void free_nested(struct vcpu_vmx *vmx)
6808{
6809 if (!vmx->nested.vmxon)
6810 return;
9a2a05b9 6811
ec378aee 6812 vmx->nested.vmxon = false;
9a2a05b9 6813 nested_release_vmcs12(vmx);
e7953d7f
AG		 6814 if (enable_shadow_vmcs)
6815 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6816 /* Unpin physical memory we referred to in current vmcs02 */
6817 if (vmx->nested.apic_access_page) {
6818 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6819 vmx->nested.apic_access_page = NULL;
fe3ef05c 6820 }
a7c0b07d
WL		 6821 if (vmx->nested.virtual_apic_page) {
6822 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6823 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6824 }
705699a1
WV		 6825 if (vmx->nested.pi_desc_page) {
6826 kunmap(vmx->nested.pi_desc_page);
6827 nested_release_page(vmx->nested.pi_desc_page);
6828 vmx->nested.pi_desc_page = NULL;
6829 vmx->nested.pi_desc = NULL;
6830 }
ff2f6fe9
NHE		 6831
6832 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6833}
6834
6835/* Emulate the VMXOFF instruction */
6836static int handle_vmoff(struct kvm_vcpu *vcpu)
6837{
6838 if (!nested_vmx_check_permission(vcpu))
6839 return 1;
6840 free_nested(to_vmx(vcpu));
6841 skip_emulated_instruction(vcpu);
a25eb114 6842 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6843 return 1;
6844}
6845
27d6c865
NHE		 6846/* Emulate the VMCLEAR instruction */
6847static int handle_vmclear(struct kvm_vcpu *vcpu)
6848{
6849 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6850 gpa_t vmptr;
6851 struct vmcs12 *vmcs12;
6852 struct page *page;
27d6c865
NHE		 6853
6854 if (!nested_vmx_check_permission(vcpu))
6855 return 1;
6856
4291b588 6857 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6858 return 1;
27d6c865 6859
9a2a05b9 6860 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6861 nested_release_vmcs12(vmx);
27d6c865
NHE		 6862
6863 page = nested_get_page(vcpu, vmptr);
6864 if (page == NULL) {
6865 /*
6866 * For accurate processor emulation, VMCLEAR beyond available
6867 * physical memory should do nothing at all. However, it is
6868 * possible that a nested vmx bug, not a guest hypervisor bug,
6869 * resulted in this case, so let's shut down before doing any
6870 * more damage:
6871 */
6872 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6873 return 1;
6874 }
6875 vmcs12 = kmap(page);
6876 vmcs12->launch_state = 0;
6877 kunmap(page);
6878 nested_release_page(page);
6879
6880 nested_free_vmcs02(vmx, vmptr);
6881
6882 skip_emulated_instruction(vcpu);
6883 nested_vmx_succeed(vcpu);
6884 return 1;
6885}
6886
cd232ad0
NHE		 6887static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6888
6889/* Emulate the VMLAUNCH instruction */
6890static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6891{
6892 return nested_vmx_run(vcpu, true);
6893}
6894
6895/* Emulate the VMRESUME instruction */
6896static int handle_vmresume(struct kvm_vcpu *vcpu)
6897{
6898
6899 return nested_vmx_run(vcpu, false);
6900}
6901
49f705c5
NHE		 6902enum vmcs_field_type {
6903 VMCS_FIELD_TYPE_U16 = 0,
6904 VMCS_FIELD_TYPE_U64 = 1,
6905 VMCS_FIELD_TYPE_U32 = 2,
6906 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6907};
6908
6909static inline int vmcs_field_type(unsigned long field)
6910{
6911 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6912 return VMCS_FIELD_TYPE_U32;
6913 return (field >> 13) & 0x3 ;
6914}
6915
6916static inline int vmcs_field_readonly(unsigned long field)
6917{
6918 return (((field >> 10) & 0x3) == 1);
6919}
6920
6921/*
6922 * Read a vmcs12 field. Since these can have varying lengths and we return
6923 * one type, we chose the biggest type (u64) and zero-extend the return value
6924 * to that size. Note that the caller, handle_vmread, might need to use only
6925 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6926 * 64-bit fields are to be returned).
6927 */
a2ae9df7
PB		 6928static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6929 unsigned long field, u64 *ret)
49f705c5
NHE		 6930{
6931 short offset = vmcs_field_to_offset(field);
6932 char *p;
6933
6934 if (offset < 0)
a2ae9df7 6935 return offset;
49f705c5
NHE		 6936
6937 p = ((char *)(get_vmcs12(vcpu))) + offset;
6938
6939 switch (vmcs_field_type(field)) {
6940 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6941 *ret = *((natural_width *)p);
a2ae9df7 6942 return 0;
49f705c5
NHE		 6943 case VMCS_FIELD_TYPE_U16:
6944 *ret = *((u16 *)p);
a2ae9df7 6945 return 0;
49f705c5
NHE		 6946 case VMCS_FIELD_TYPE_U32:
6947 *ret = *((u32 *)p);
a2ae9df7 6948 return 0;
49f705c5
NHE		 6949 case VMCS_FIELD_TYPE_U64:
6950 *ret = *((u64 *)p);
a2ae9df7 6951 return 0;
49f705c5 6952 default:
a2ae9df7
PB		 6953 WARN_ON(1);
6954 return -ENOENT;
49f705c5
NHE		 6955 }
6956}
6957
20b97fea 6958
a2ae9df7
PB		 6959static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6960 unsigned long field, u64 field_value){
20b97fea
AG		 6961 short offset = vmcs_field_to_offset(field);
6962 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6963 if (offset < 0)
a2ae9df7 6964 return offset;
20b97fea
AG		 6965
6966 switch (vmcs_field_type(field)) {
6967 case VMCS_FIELD_TYPE_U16:
6968 *(u16 *)p = field_value;
a2ae9df7 6969 return 0;
20b97fea
AG		 6970 case VMCS_FIELD_TYPE_U32:
6971 *(u32 *)p = field_value;
a2ae9df7 6972 return 0;
20b97fea
AG		 6973 case VMCS_FIELD_TYPE_U64:
6974 *(u64 *)p = field_value;
a2ae9df7 6975 return 0;
20b97fea
AG		 6976 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6977 *(natural_width *)p = field_value;
a2ae9df7 6978 return 0;
20b97fea 6979 default:
a2ae9df7
PB		 6980 WARN_ON(1);
6981 return -ENOENT;
20b97fea
AG		 6982 }
6983
6984}
6985
16f5b903
AG		 6986static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6987{
6988 int i;
6989 unsigned long field;
6990 u64 field_value;
6991 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6992 const unsigned long *fields = shadow_read_write_fields;
6993 const int num_fields = max_shadow_read_write_fields;
16f5b903 6994
282da870
JK		 6995 preempt_disable();
6996
16f5b903
AG		 6997 vmcs_load(shadow_vmcs);
6998
6999 for (i = 0; i < num_fields; i++) {
7000 field = fields[i];
7001 switch (vmcs_field_type(field)) {
7002 case VMCS_FIELD_TYPE_U16:
7003 field_value = vmcs_read16(field);
7004 break;
7005 case VMCS_FIELD_TYPE_U32:
7006 field_value = vmcs_read32(field);
7007 break;
7008 case VMCS_FIELD_TYPE_U64:
7009 field_value = vmcs_read64(field);
7010 break;
7011 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7012 field_value = vmcs_readl(field);
7013 break;
a2ae9df7
PB		 7014 default:
7015 WARN_ON(1);
7016 continue;
16f5b903
AG		 7017 }
7018 vmcs12_write_any(&vmx->vcpu, field, field_value);
7019 }
7020
7021 vmcs_clear(shadow_vmcs);
7022 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 7023
7024 preempt_enable();
16f5b903
AG		 7025}
7026
c3114420
AG		 7027static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7028{
c2bae893
MK		 7029 const unsigned long *fields[] = {
7030 shadow_read_write_fields,
7031 shadow_read_only_fields
c3114420 7032 };
c2bae893 7033 const int max_fields[] = {
c3114420
AG		 7034 max_shadow_read_write_fields,
7035 max_shadow_read_only_fields
7036 };
7037 int i, q;
7038 unsigned long field;
7039 u64 field_value = 0;
7040 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7041
7042 vmcs_load(shadow_vmcs);
7043
c2bae893 7044 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 7045 for (i = 0; i < max_fields[q]; i++) {
7046 field = fields[q][i];
7047 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7048
7049 switch (vmcs_field_type(field)) {
7050 case VMCS_FIELD_TYPE_U16:
7051 vmcs_write16(field, (u16)field_value);
7052 break;
7053 case VMCS_FIELD_TYPE_U32:
7054 vmcs_write32(field, (u32)field_value);
7055 break;
7056 case VMCS_FIELD_TYPE_U64:
7057 vmcs_write64(field, (u64)field_value);
7058 break;
7059 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7060 vmcs_writel(field, (long)field_value);
7061 break;
a2ae9df7
PB		 7062 default:
7063 WARN_ON(1);
7064 break;
c3114420
AG		 7065 }
7066 }
7067 }
7068
7069 vmcs_clear(shadow_vmcs);
7070 vmcs_load(vmx->loaded_vmcs->vmcs);
7071}
7072
49f705c5
NHE		 7073/*
7074 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7075 * used before) all generate the same failure when it is missing.
7076 */
7077static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7078{
7079 struct vcpu_vmx *vmx = to_vmx(vcpu);
7080 if (vmx->nested.current_vmptr == -1ull) {
7081 nested_vmx_failInvalid(vcpu);
7082 skip_emulated_instruction(vcpu);
7083 return 0;
7084 }
7085 return 1;
7086}
7087
7088static int handle_vmread(struct kvm_vcpu *vcpu)
7089{
7090 unsigned long field;
7091 u64 field_value;
7092 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7093 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7094 gva_t gva = 0;
7095
7096 if (!nested_vmx_check_permission(vcpu) ||
7097 !nested_vmx_check_vmcs12(vcpu))
7098 return 1;
7099
7100 /* Decode instruction info and find the field to read */
27e6fb5d 7101 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 7102 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 7103 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 7104 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7105 skip_emulated_instruction(vcpu);
7106 return 1;
7107 }
7108 /*
7109 * Now copy part of this value to register or memory, as requested.
7110 * Note that the number of bits actually copied is 32 or 64 depending
7111 * on the guest's mode (32 or 64 bit), not on the given field's length.
7112 */
7113 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 7114 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 7115 field_value);
7116 } else {
7117 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7118 vmx_instruction_info, true, &gva))
49f705c5
NHE		 7119 return 1;
7120 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7121 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7122 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7123 }
7124
7125 nested_vmx_succeed(vcpu);
7126 skip_emulated_instruction(vcpu);
7127 return 1;
7128}
7129
7130
7131static int handle_vmwrite(struct kvm_vcpu *vcpu)
7132{
7133 unsigned long field;
7134 gva_t gva;
7135 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7136 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 7137 /* The value to write might be 32 or 64 bits, depending on L1's long
7138 * mode, and eventually we need to write that into a field of several
7139 * possible lengths. The code below first zero-extends the value to 64
7140 * bit (field_value), and then copies only the approriate number of
7141 * bits into the vmcs12 field.
7142 */
7143 u64 field_value = 0;
7144 struct x86_exception e;
7145
7146 if (!nested_vmx_check_permission(vcpu) ||
7147 !nested_vmx_check_vmcs12(vcpu))
7148 return 1;
7149
7150 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7151 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 7152 (((vmx_instruction_info) >> 3) & 0xf));
7153 else {
7154 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7155 vmx_instruction_info, false, &gva))
49f705c5
NHE		 7156 return 1;
7157 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7158 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 7159 kvm_inject_page_fault(vcpu, &e);
7160 return 1;
7161 }
7162 }
7163
7164
27e6fb5d 7165 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 7166 if (vmcs_field_readonly(field)) {
7167 nested_vmx_failValid(vcpu,
7168 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7169 skip_emulated_instruction(vcpu);
7170 return 1;
7171 }
7172
a2ae9df7 7173 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 7174 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7175 skip_emulated_instruction(vcpu);
7176 return 1;
7177 }
7178
7179 nested_vmx_succeed(vcpu);
7180 skip_emulated_instruction(vcpu);
7181 return 1;
7182}
7183
63846663
NHE		 7184/* Emulate the VMPTRLD instruction */
7185static int handle_vmptrld(struct kvm_vcpu *vcpu)
7186{
7187 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7188 gpa_t vmptr;
63846663
NHE		 7189
7190 if (!nested_vmx_check_permission(vcpu))
7191 return 1;
7192
4291b588 7193 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 7194 return 1;
63846663
NHE		 7195
7196 if (vmx->nested.current_vmptr != vmptr) {
7197 struct vmcs12 *new_vmcs12;
7198 struct page *page;
7199 page = nested_get_page(vcpu, vmptr);
7200 if (page == NULL) {
7201 nested_vmx_failInvalid(vcpu);
7202 skip_emulated_instruction(vcpu);
7203 return 1;
7204 }
7205 new_vmcs12 = kmap(page);
7206 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7207 kunmap(page);
7208 nested_release_page_clean(page);
7209 nested_vmx_failValid(vcpu,
7210 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7211 skip_emulated_instruction(vcpu);
7212 return 1;
7213 }
63846663 7214
9a2a05b9 7215 nested_release_vmcs12(vmx);
63846663
NHE		 7216 vmx->nested.current_vmptr = vmptr;
7217 vmx->nested.current_vmcs12 = new_vmcs12;
7218 vmx->nested.current_vmcs12_page = page;
012f83cb 7219 if (enable_shadow_vmcs) {
7ec36296
XG		 7220 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7221 SECONDARY_EXEC_SHADOW_VMCS);
8a1b9dd0
AG		 7222 vmcs_write64(VMCS_LINK_POINTER,
7223 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 7224 vmx->nested.sync_shadow_vmcs = true;
7225 }
63846663
NHE		 7226 }
7227
7228 nested_vmx_succeed(vcpu);
7229 skip_emulated_instruction(vcpu);
7230 return 1;
7231}
7232
6a4d7550
NHE		 7233/* Emulate the VMPTRST instruction */
7234static int handle_vmptrst(struct kvm_vcpu *vcpu)
7235{
7236 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7237 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7238 gva_t vmcs_gva;
7239 struct x86_exception e;
7240
7241 if (!nested_vmx_check_permission(vcpu))
7242 return 1;
7243
7244 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7245 vmx_instruction_info, true, &vmcs_gva))
6a4d7550
NHE		 7246 return 1;
7247 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7248 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7249 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7250 sizeof(u64), &e)) {
7251 kvm_inject_page_fault(vcpu, &e);
7252 return 1;
7253 }
7254 nested_vmx_succeed(vcpu);
7255 skip_emulated_instruction(vcpu);
7256 return 1;
7257}
7258
bfd0a56b
NHE		 7259/* Emulate the INVEPT instruction */
7260static int handle_invept(struct kvm_vcpu *vcpu)
7261{
b9c237bb 7262 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7263 u32 vmx_instruction_info, types;
7264 unsigned long type;
7265 gva_t gva;
7266 struct x86_exception e;
7267 struct {
7268 u64 eptp, gpa;
7269 } operand;
bfd0a56b 7270
b9c237bb
WV		 7271 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7272 SECONDARY_EXEC_ENABLE_EPT) ||
7273 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7274 kvm_queue_exception(vcpu, UD_VECTOR);
7275 return 1;
7276 }
7277
7278 if (!nested_vmx_check_permission(vcpu))
7279 return 1;
7280
7281 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7282 kvm_queue_exception(vcpu, UD_VECTOR);
7283 return 1;
7284 }
7285
7286 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7287 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7288
b9c237bb 7289 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7290
7291 if (!(types & (1UL << type))) {
7292 nested_vmx_failValid(vcpu,
7293 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7294 return 1;
7295 }
7296
7297 /* According to the Intel VMX instruction reference, the memory
7298 * operand is read even if it isn't needed (e.g., for type==global)
7299 */
7300 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7301 vmx_instruction_info, false, &gva))
bfd0a56b
NHE		 7302 return 1;
7303 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7304 sizeof(operand), &e)) {
7305 kvm_inject_page_fault(vcpu, &e);
7306 return 1;
7307 }
7308
7309 switch (type) {
bfd0a56b
NHE		 7310 case VMX_EPT_EXTENT_GLOBAL:
7311 kvm_mmu_sync_roots(vcpu);
77c3913b 7312 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7313 nested_vmx_succeed(vcpu);
7314 break;
7315 default:
4b855078 7316 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7317 BUG_ON(1);
7318 break;
7319 }
7320
7321 skip_emulated_instruction(vcpu);
7322 return 1;
7323}
7324
a642fc30
PM		 7325static int handle_invvpid(struct kvm_vcpu *vcpu)
7326{
7327 kvm_queue_exception(vcpu, UD_VECTOR);
7328 return 1;
7329}
7330
843e4330
KH		 7331static int handle_pml_full(struct kvm_vcpu *vcpu)
7332{
7333 unsigned long exit_qualification;
7334
7335 trace_kvm_pml_full(vcpu->vcpu_id);
7336
7337 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7338
7339 /*
7340 * PML buffer FULL happened while executing iret from NMI,
7341 * "blocked by NMI" bit has to be set before next VM entry.
7342 */
7343 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7344 cpu_has_virtual_nmis() &&
7345 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7346 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7347 GUEST_INTR_STATE_NMI);
7348
7349 /*
7350 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7351 * here.., and there's no userspace involvement needed for PML.
7352 */
7353 return 1;
7354}
7355
8b3e34e4
XG		 7356static int handle_pcommit(struct kvm_vcpu *vcpu)
7357{
7358 /* we never catch pcommit instruct for L1 guest. */
7359 WARN_ON(1);
7360 return 1;
7361}
7362
6aa8b732
AK		 7363/*
7364 * The exit handlers return 1 if the exit was handled fully and guest execution
7365 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7366 * to be done to userspace and return 0.
7367 */
772e0318 7368static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7369 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7370 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7371 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7372 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7373 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7374 [EXIT_REASON_CR_ACCESS] = handle_cr,
7375 [EXIT_REASON_DR_ACCESS] = handle_dr,
7376 [EXIT_REASON_CPUID] = handle_cpuid,
7377 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7378 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7379 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7380 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7381 [EXIT_REASON_INVD] = handle_invd,
a7052897 7382 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7383 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7384 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7385 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7386 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7387 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7388 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7389 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7390 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7391 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7392 [EXIT_REASON_VMOFF] = handle_vmoff,
7393 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7394 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7395 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7396 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7397 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7398 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7399 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7400 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7401 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7402 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7403 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7404 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7405 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7406 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7407 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7408 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7409 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7410 [EXIT_REASON_XSAVES] = handle_xsaves,
7411 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7412 [EXIT_REASON_PML_FULL] = handle_pml_full,
8b3e34e4 7413 [EXIT_REASON_PCOMMIT] = handle_pcommit,
6aa8b732
AK		 7414};
7415
7416static const int kvm_vmx_max_exit_handlers =
50a3485c 7417 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7418
908a7bdd
JK		 7419static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7420 struct vmcs12 *vmcs12)
7421{
7422 unsigned long exit_qualification;
7423 gpa_t bitmap, last_bitmap;
7424 unsigned int port;
7425 int size;
7426 u8 b;
7427
908a7bdd 7428 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7429 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7430
7431 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7432
7433 port = exit_qualification >> 16;
7434 size = (exit_qualification & 7) + 1;
7435
7436 last_bitmap = (gpa_t)-1;
7437 b = -1;
7438
7439 while (size > 0) {
7440 if (port < 0x8000)
7441 bitmap = vmcs12->io_bitmap_a;
7442 else if (port < 0x10000)
7443 bitmap = vmcs12->io_bitmap_b;
7444 else
1d804d07 7445 return true;
908a7bdd
JK		 7446 bitmap += (port & 0x7fff) / 8;
7447
7448 if (last_bitmap != bitmap)
54bf36aa 7449 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7450 return true;
908a7bdd 7451 if (b & (1 << (port & 7)))
1d804d07 7452 return true;
908a7bdd
JK		 7453
7454 port++;
7455 size--;
7456 last_bitmap = bitmap;
7457 }
7458
1d804d07 7459 return false;
908a7bdd
JK		 7460}
7461
644d711a
NHE		 7462/*
7463 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7464 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7465 * disinterest in the current event (read or write a specific MSR) by using an
7466 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7467 */
7468static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7469 struct vmcs12 *vmcs12, u32 exit_reason)
7470{
7471 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7472 gpa_t bitmap;
7473
cbd29cb6 7474 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7475 return true;
644d711a
NHE		 7476
7477 /*
7478 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7479 * for the four combinations of read/write and low/high MSR numbers.
7480 * First we need to figure out which of the four to use:
7481 */
7482 bitmap = vmcs12->msr_bitmap;
7483 if (exit_reason == EXIT_REASON_MSR_WRITE)
7484 bitmap += 2048;
7485 if (msr_index >= 0xc0000000) {
7486 msr_index -= 0xc0000000;
7487 bitmap += 1024;
7488 }
7489
7490 /* Then read the msr_index'th bit from this bitmap: */
7491 if (msr_index < 1024*8) {
7492 unsigned char b;
54bf36aa 7493 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7494 return true;
644d711a
NHE		 7495 return 1 & (b >> (msr_index & 7));
7496 } else
1d804d07 7497 return true; /* let L1 handle the wrong parameter */
644d711a
NHE		 7498}
7499
7500/*
7501 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7502 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7503 * intercept (via guest_host_mask etc.) the current event.
7504 */
7505static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7506 struct vmcs12 *vmcs12)
7507{
7508 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7509 int cr = exit_qualification & 15;
7510 int reg = (exit_qualification >> 8) & 15;
1e32c079 7511 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7512
7513 switch ((exit_qualification >> 4) & 3) {
7514 case 0: /* mov to cr */
7515 switch (cr) {
7516 case 0:
7517 if (vmcs12->cr0_guest_host_mask &
7518 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7519 return true;
644d711a
NHE		 7520 break;
7521 case 3:
7522 if ((vmcs12->cr3_target_count >= 1 &&
7523 vmcs12->cr3_target_value0 == val) ||
7524 (vmcs12->cr3_target_count >= 2 &&
7525 vmcs12->cr3_target_value1 == val) ||
7526 (vmcs12->cr3_target_count >= 3 &&
7527 vmcs12->cr3_target_value2 == val) ||
7528 (vmcs12->cr3_target_count >= 4 &&
7529 vmcs12->cr3_target_value3 == val))
1d804d07 7530 return false;
644d711a 7531 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7532 return true;
644d711a
NHE		 7533 break;
7534 case 4:
7535 if (vmcs12->cr4_guest_host_mask &
7536 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7537 return true;
644d711a
NHE		 7538 break;
7539 case 8:
7540 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7541 return true;
644d711a
NHE		 7542 break;
7543 }
7544 break;
7545 case 2: /* clts */
7546 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7547 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7548 return true;
644d711a
NHE		 7549 break;
7550 case 1: /* mov from cr */
7551 switch (cr) {
7552 case 3:
7553 if (vmcs12->cpu_based_vm_exec_control &
7554 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7555 return true;
644d711a
NHE		 7556 break;
7557 case 8:
7558 if (vmcs12->cpu_based_vm_exec_control &
7559 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7560 return true;
644d711a
NHE		 7561 break;
7562 }
7563 break;
7564 case 3: /* lmsw */
7565 /*
7566 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7567 * cr0. Other attempted changes are ignored, with no exit.
7568 */
7569 if (vmcs12->cr0_guest_host_mask & 0xe &
7570 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7571 return true;
644d711a
NHE		 7572 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7573 !(vmcs12->cr0_read_shadow & 0x1) &&
7574 (val & 0x1))
1d804d07 7575 return true;
644d711a
NHE		 7576 break;
7577 }
1d804d07 7578 return false;
644d711a
NHE		 7579}
7580
7581/*
7582 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7583 * should handle it ourselves in L0 (and then continue L2). Only call this
7584 * when in is_guest_mode (L2).
7585 */
7586static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7587{
644d711a
NHE		 7588 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7589 struct vcpu_vmx *vmx = to_vmx(vcpu);
7590 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7591 u32 exit_reason = vmx->exit_reason;
644d711a 7592
542060ea
JK		 7593 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7594 vmcs_readl(EXIT_QUALIFICATION),
7595 vmx->idt_vectoring_info,
7596 intr_info,
7597 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7598 KVM_ISA_VMX);
7599
644d711a 7600 if (vmx->nested.nested_run_pending)
1d804d07 7601 return false;
644d711a
NHE		 7602
7603 if (unlikely(vmx->fail)) {
bd80158a
JK		 7604 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7605 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 7606 return true;
644d711a
NHE		 7607 }
7608
7609 switch (exit_reason) {
7610 case EXIT_REASON_EXCEPTION_NMI:
7611 if (!is_exception(intr_info))
1d804d07 7612 return false;
644d711a
NHE		 7613 else if (is_page_fault(intr_info))
7614 return enable_ept;
e504c909 7615 else if (is_no_device(intr_info) &&
ccf9844e 7616 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 7617 return false;
644d711a
NHE		 7618 return vmcs12->exception_bitmap &
7619 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7620 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 7621 return false;
644d711a 7622 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 7623 return true;
644d711a 7624 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7625 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7626 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7627 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 7628 case EXIT_REASON_TASK_SWITCH:
1d804d07 7629 return true;
644d711a 7630 case EXIT_REASON_CPUID:
bc613494 7631 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
1d804d07
JP		 7632 return false;
7633 return true;
644d711a
NHE		 7634 case EXIT_REASON_HLT:
7635 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7636 case EXIT_REASON_INVD:
1d804d07 7637 return true;
644d711a
NHE		 7638 case EXIT_REASON_INVLPG:
7639 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7640 case EXIT_REASON_RDPMC:
7641 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
b3a2a907 7642 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE		 7643 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7644 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7645 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7646 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7647 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7648 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7649 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7650 /*
7651 * VMX instructions trap unconditionally. This allows L1 to
7652 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7653 */
1d804d07 7654 return true;
644d711a
NHE		 7655 case EXIT_REASON_CR_ACCESS:
7656 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7657 case EXIT_REASON_DR_ACCESS:
7658 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7659 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7660 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7661 case EXIT_REASON_MSR_READ:
7662 case EXIT_REASON_MSR_WRITE:
7663 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7664 case EXIT_REASON_INVALID_STATE:
1d804d07 7665 return true;
644d711a
NHE		 7666 case EXIT_REASON_MWAIT_INSTRUCTION:
7667 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD		 7668 case EXIT_REASON_MONITOR_TRAP_FLAG:
7669 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE		 7670 case EXIT_REASON_MONITOR_INSTRUCTION:
7671 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7672 case EXIT_REASON_PAUSE_INSTRUCTION:
7673 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7674 nested_cpu_has2(vmcs12,
7675 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7676 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 7677 return false;
644d711a 7678 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7679 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7680 case EXIT_REASON_APIC_ACCESS:
7681 return nested_cpu_has2(vmcs12,
7682 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 7683 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 7684 case EXIT_REASON_EOI_INDUCED:
7685 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 7686 return true;
644d711a 7687 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7688 /*
7689 * L0 always deals with the EPT violation. If nested EPT is
7690 * used, and the nested mmu code discovers that the address is
7691 * missing in the guest EPT table (EPT12), the EPT violation
7692 * will be injected with nested_ept_inject_page_fault()
7693 */
1d804d07 7694 return false;
644d711a 7695 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7696 /*
7697 * L2 never uses directly L1's EPT, but rather L0's own EPT
7698 * table (shadow on EPT) or a merged EPT table that L0 built
7699 * (EPT on EPT). So any problems with the structure of the
7700 * table is L0's fault.
7701 */
1d804d07 7702 return false;
644d711a
NHE		 7703 case EXIT_REASON_WBINVD:
7704 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7705 case EXIT_REASON_XSETBV:
1d804d07 7706 return true;
81dc01f7
WL		 7707 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7708 /*
7709 * This should never happen, since it is not possible to
7710 * set XSS to a non-zero value---neither in L1 nor in L2.
7711 * If if it were, XSS would have to be checked against
7712 * the XSS exit bitmap in vmcs12.
7713 */
7714 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8b3e34e4
XG		 7715 case EXIT_REASON_PCOMMIT:
7716 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
644d711a 7717 default:
1d804d07 7718 return true;
644d711a
NHE		 7719 }
7720}
7721
586f9607
AK		 7722static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7723{
7724 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7725 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7726}
7727
843e4330
KH		 7728static int vmx_enable_pml(struct vcpu_vmx *vmx)
7729{
7730 struct page *pml_pg;
843e4330
KH		 7731
7732 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7733 if (!pml_pg)
7734 return -ENOMEM;
7735
7736 vmx->pml_pg = pml_pg;
7737
7738 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7739 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7740
7ec36296 7741 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_ENABLE_PML);
843e4330
KH		 7742
7743 return 0;
7744}
7745
7746static void vmx_disable_pml(struct vcpu_vmx *vmx)
7747{
843e4330
KH		 7748 ASSERT(vmx->pml_pg);
7749 __free_page(vmx->pml_pg);
7750 vmx->pml_pg = NULL;
7751
7ec36296 7752 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_ENABLE_PML);
843e4330
KH		 7753}
7754
54bf36aa 7755static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 7756{
54bf36aa 7757 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH		 7758 u64 *pml_buf;
7759 u16 pml_idx;
7760
7761 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7762
7763 /* Do nothing if PML buffer is empty */
7764 if (pml_idx == (PML_ENTITY_NUM - 1))
7765 return;
7766
7767 /* PML index always points to next available PML buffer entity */
7768 if (pml_idx >= PML_ENTITY_NUM)
7769 pml_idx = 0;
7770 else
7771 pml_idx++;
7772
7773 pml_buf = page_address(vmx->pml_pg);
7774 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7775 u64 gpa;
7776
7777 gpa = pml_buf[pml_idx];
7778 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 7779 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH		 7780 }
7781
7782 /* reset PML index */
7783 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7784}
7785
7786/*
7787 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7788 * Called before reporting dirty_bitmap to userspace.
7789 */
7790static void kvm_flush_pml_buffers(struct kvm *kvm)
7791{
7792 int i;
7793 struct kvm_vcpu *vcpu;
7794 /*
7795 * We only need to kick vcpu out of guest mode here, as PML buffer
7796 * is flushed at beginning of all VMEXITs, and it's obvious that only
7797 * vcpus running in guest are possible to have unflushed GPAs in PML
7798 * buffer.
7799 */
7800 kvm_for_each_vcpu(i, vcpu, kvm)
7801 kvm_vcpu_kick(vcpu);
7802}
7803
4eb64dce
PB		 7804static void vmx_dump_sel(char *name, uint32_t sel)
7805{
7806 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7807 name, vmcs_read32(sel),
7808 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7809 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7810 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7811}
7812
7813static void vmx_dump_dtsel(char *name, uint32_t limit)
7814{
7815 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7816 name, vmcs_read32(limit),
7817 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7818}
7819
7820static void dump_vmcs(void)
7821{
7822 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7823 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7824 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7825 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7826 u32 secondary_exec_control = 0;
7827 unsigned long cr4 = vmcs_readl(GUEST_CR4);
7828 u64 efer = vmcs_readl(GUEST_IA32_EFER);
7829 int i, n;
7830
7831 if (cpu_has_secondary_exec_ctrls())
7832 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7833
7834 pr_err("*** Guest State ***\n");
7835 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7836 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7837 vmcs_readl(CR0_GUEST_HOST_MASK));
7838 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7839 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7840 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7841 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7842 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7843 {
7844 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7845 vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7846 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7847 vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7848 }
7849 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7850 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7851 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7852 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7853 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7854 vmcs_readl(GUEST_SYSENTER_ESP),
7855 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7856 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
7857 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
7858 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
7859 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
7860 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
7861 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
7862 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7863 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7864 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7865 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
7866 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7867 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7868 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7869 efer, vmcs_readl(GUEST_IA32_PAT));
7870 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7871 vmcs_readl(GUEST_IA32_DEBUGCTL),
7872 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7873 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7874 pr_err("PerfGlobCtl = 0x%016lx\n",
7875 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7876 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7877 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7878 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7879 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7880 vmcs_read32(GUEST_ACTIVITY_STATE));
7881 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7882 pr_err("InterruptStatus = %04x\n",
7883 vmcs_read16(GUEST_INTR_STATUS));
7884
7885 pr_err("*** Host State ***\n");
7886 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7887 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7888 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7889 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7890 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7891 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7892 vmcs_read16(HOST_TR_SELECTOR));
7893 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7894 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7895 vmcs_readl(HOST_TR_BASE));
7896 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7897 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7898 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7899 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7900 vmcs_readl(HOST_CR4));
7901 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7902 vmcs_readl(HOST_IA32_SYSENTER_ESP),
7903 vmcs_read32(HOST_IA32_SYSENTER_CS),
7904 vmcs_readl(HOST_IA32_SYSENTER_EIP));
7905 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7906 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7907 vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7908 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7909 pr_err("PerfGlobCtl = 0x%016lx\n",
7910 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7911
7912 pr_err("*** Control State ***\n");
7913 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7914 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7915 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7916 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7917 vmcs_read32(EXCEPTION_BITMAP),
7918 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7919 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7920 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7921 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7922 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
7923 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
7924 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
7925 vmcs_read32(VM_EXIT_INTR_INFO),
7926 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7927 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
7928 pr_err(" reason=%08x qualification=%016lx\n",
7929 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
7930 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
7931 vmcs_read32(IDT_VECTORING_INFO_FIELD),
7932 vmcs_read32(IDT_VECTORING_ERROR_CODE));
7933 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
7934 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
7935 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
7936 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
7937 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
7938 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
7939 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
7940 n = vmcs_read32(CR3_TARGET_COUNT);
7941 for (i = 0; i + 1 < n; i += 4)
7942 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
7943 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
7944 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
7945 if (i < n)
7946 pr_err("CR3 target%u=%016lx\n",
7947 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
7948 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
7949 pr_err("PLE Gap=%08x Window=%08x\n",
7950 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
7951 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
7952 pr_err("Virtual processor ID = 0x%04x\n",
7953 vmcs_read16(VIRTUAL_PROCESSOR_ID));
7954}
7955
6aa8b732
AK		 7956/*
7957 * The guest has exited. See if we can fix it or if we need userspace
7958 * assistance.
7959 */
851ba692 7960static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7961{
29bd8a78 7962 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7963 u32 exit_reason = vmx->exit_reason;
1155f76a 7964 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7965
843e4330
KH		 7966 /*
7967 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7968 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7969 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7970 * mode as if vcpus is in root mode, the PML buffer must has been
7971 * flushed already.
7972 */
7973 if (enable_pml)
54bf36aa 7974 vmx_flush_pml_buffer(vcpu);
843e4330 7975
80ced186 7976 /* If guest state is invalid, start emulating */
14168786 7977 if (vmx->emulation_required)
80ced186 7978 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7979
644d711a 7980 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7981 nested_vmx_vmexit(vcpu, exit_reason,
7982 vmcs_read32(VM_EXIT_INTR_INFO),
7983 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7984 return 1;
7985 }
7986
5120702e 7987 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 7988 dump_vmcs();
5120702e
MG		 7989 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7990 vcpu->run->fail_entry.hardware_entry_failure_reason
7991 = exit_reason;
7992 return 0;
7993 }
7994
29bd8a78 7995 if (unlikely(vmx->fail)) {
851ba692
AK		 7996 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7997 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7998 = vmcs_read32(VM_INSTRUCTION_ERROR);
7999 return 0;
8000 }
6aa8b732 8001
b9bf6882
XG		 8002 /*
8003 * Note:
8004 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8005 * delivery event since it indicates guest is accessing MMIO.
8006 * The vm-exit can be triggered again after return to guest that
8007 * will cause infinite loop.
8008 */
d77c26fc 8009 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 8010 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 8011 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 8012 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8013 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8014 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8015 vcpu->run->internal.ndata = 2;
8016 vcpu->run->internal.data[0] = vectoring_info;
8017 vcpu->run->internal.data[1] = exit_reason;
8018 return 0;
8019 }
3b86cd99 8020
644d711a
NHE		 8021 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8022 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 8023 get_vmcs12(vcpu))))) {
c4282df9 8024 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 8025 vmx->soft_vnmi_blocked = 0;
3b86cd99 8026 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 8027 vcpu->arch.nmi_pending) {
3b86cd99
JK		 8028 /*
8029 * This CPU don't support us in finding the end of an
8030 * NMI-blocked window if the guest runs with IRQs
8031 * disabled. So we pull the trigger after 1 s of
8032 * futile waiting, but inform the user about this.
8033 */
8034 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8035 "state on VCPU %d after 1 s timeout\n",
8036 __func__, vcpu->vcpu_id);
8037 vmx->soft_vnmi_blocked = 0;
3b86cd99 8038 }
3b86cd99
JK		 8039 }
8040
6aa8b732
AK		 8041 if (exit_reason < kvm_vmx_max_exit_handlers
8042 && kvm_vmx_exit_handlers[exit_reason])
851ba692 8043 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 8044 else {
2bc19dc3
MT		 8045 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8046 kvm_queue_exception(vcpu, UD_VECTOR);
8047 return 1;
6aa8b732 8048 }
6aa8b732
AK		 8049}
8050
95ba8273 8051static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 8052{
a7c0b07d
WL		 8053 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8054
8055 if (is_guest_mode(vcpu) &&
8056 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8057 return;
8058
95ba8273 8059 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 8060 vmcs_write32(TPR_THRESHOLD, 0);
8061 return;
8062 }
8063
95ba8273 8064 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 8065}
8066
8d14695f
YZ		 8067static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8068{
8069 u32 sec_exec_control;
8070
8071 /*
8072 * There is not point to enable virtualize x2apic without enable
8073 * apicv
8074 */
c7c9c56c 8075 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
35754c98 8076 !vmx_cpu_uses_apicv(vcpu))
8d14695f
YZ		 8077 return;
8078
35754c98 8079 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ		 8080 return;
8081
8082 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8083
8084 if (set) {
8085 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8086 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8087 } else {
8088 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8089 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8090 }
8091 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8092
8093 vmx_set_msr_bitmap(vcpu);
8094}
8095
38b99173
TC		 8096static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8097{
8098 struct vcpu_vmx *vmx = to_vmx(vcpu);
8099
8100 /*
8101 * Currently we do not handle the nested case where L2 has an
8102 * APIC access page of its own; that page is still pinned.
8103 * Hence, we skip the case where the VCPU is in guest mode _and_
8104 * L1 prepared an APIC access page for L2.
8105 *
8106 * For the case where L1 and L2 share the same APIC access page
8107 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8108 * in the vmcs12), this function will only update either the vmcs01
8109 * or the vmcs02. If the former, the vmcs02 will be updated by
8110 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8111 * the next L2->L1 exit.
8112 */
8113 if (!is_guest_mode(vcpu) ||
8114 !nested_cpu_has2(vmx->nested.current_vmcs12,
8115 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8116 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8117}
8118
c7c9c56c
YZ		 8119static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8120{
8121 u16 status;
8122 u8 old;
8123
c7c9c56c
YZ		 8124 if (isr == -1)
8125 isr = 0;
8126
8127 status = vmcs_read16(GUEST_INTR_STATUS);
8128 old = status >> 8;
8129 if (isr != old) {
8130 status &= 0xff;
8131 status |= isr << 8;
8132 vmcs_write16(GUEST_INTR_STATUS, status);
8133 }
8134}
8135
8136static void vmx_set_rvi(int vector)
8137{
8138 u16 status;
8139 u8 old;
8140
4114c27d
WW		 8141 if (vector == -1)
8142 vector = 0;
8143
c7c9c56c
YZ		 8144 status = vmcs_read16(GUEST_INTR_STATUS);
8145 old = (u8)status & 0xff;
8146 if ((u8)vector != old) {
8147 status &= ~0xff;
8148 status |= (u8)vector;
8149 vmcs_write16(GUEST_INTR_STATUS, status);
8150 }
8151}
8152
8153static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8154{
4114c27d
WW		 8155 if (!is_guest_mode(vcpu)) {
8156 vmx_set_rvi(max_irr);
8157 return;
8158 }
8159
c7c9c56c
YZ		 8160 if (max_irr == -1)
8161 return;
8162
963fee16 8163 /*
4114c27d
WW		 8164 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8165 * handles it.
963fee16 8166 */
4114c27d 8167 if (nested_exit_on_intr(vcpu))
963fee16
WL		 8168 return;
8169
963fee16 8170 /*
4114c27d 8171 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 8172 * is run without virtual interrupt delivery.
8173 */
8174 if (!kvm_event_needs_reinjection(vcpu) &&
8175 vmx_interrupt_allowed(vcpu)) {
8176 kvm_queue_interrupt(vcpu, max_irr, false);
8177 vmx_inject_irq(vcpu);
8178 }
c7c9c56c
YZ		 8179}
8180
3bb345f3 8181static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
c7c9c56c 8182{
3bb345f3 8183 u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
35754c98 8184 if (!vmx_cpu_uses_apicv(vcpu))
3d81bc7e
YZ		 8185 return;
8186
c7c9c56c
YZ		 8187 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8188 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8189 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8190 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8191}
8192
51aa01d1 8193static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8194{
00eba012
AK		 8195 u32 exit_intr_info;
8196
8197 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8198 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8199 return;
8200
c5ca8e57 8201 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 8202 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 8203
8204 /* Handle machine checks before interrupts are enabled */
00eba012 8205 if (is_machine_check(exit_intr_info))
a0861c02
AK		 8206 kvm_machine_check();
8207
20f65983 8208 /* We need to handle NMIs before interrupts are enabled */
00eba012 8209 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 8210 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8211 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8212 asm("int $2");
ff9d07a0
ZY		 8213 kvm_after_handle_nmi(&vmx->vcpu);
8214 }
51aa01d1 8215}
20f65983 8216
a547c6db
YZ		 8217static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8218{
8219 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8220
8221 /*
8222 * If external interrupt exists, IF bit is set in rflags/eflags on the
8223 * interrupt stack frame, and interrupt will be enabled on a return
8224 * from interrupt handler.
8225 */
8226 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8227 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8228 unsigned int vector;
8229 unsigned long entry;
8230 gate_desc *desc;
8231 struct vcpu_vmx *vmx = to_vmx(vcpu);
8232#ifdef CONFIG_X86_64
8233 unsigned long tmp;
8234#endif
8235
8236 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8237 desc = (gate_desc *)vmx->host_idt_base + vector;
8238 entry = gate_offset(*desc);
8239 asm volatile(
8240#ifdef CONFIG_X86_64
8241 "mov %%" _ASM_SP ", %[sp]\n\t"
8242 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8243 "push $%c[ss]\n\t"
8244 "push %[sp]\n\t"
8245#endif
8246 "pushf\n\t"
8247 "orl $0x200, (%%" _ASM_SP ")\n\t"
8248 __ASM_SIZE(push) " $%c[cs]\n\t"
8249 "call *%[entry]\n\t"
8250 :
8251#ifdef CONFIG_X86_64
8252 [sp]"=&r"(tmp)
8253#endif
8254 :
8255 [entry]"r"(entry),
8256 [ss]"i"(__KERNEL_DS),
8257 [cs]"i"(__KERNEL_CS)
8258 );
8259 } else
8260 local_irq_enable();
8261}
8262
6d396b55
PB		 8263static bool vmx_has_high_real_mode_segbase(void)
8264{
8265 return enable_unrestricted_guest || emulate_invalid_guest_state;
8266}
8267
da8999d3
LJ		 8268static bool vmx_mpx_supported(void)
8269{
8270 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8271 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8272}
8273
55412b2e
WL		 8274static bool vmx_xsaves_supported(void)
8275{
8276 return vmcs_config.cpu_based_2nd_exec_ctrl &
8277 SECONDARY_EXEC_XSAVES;
8278}
8279
51aa01d1
AK		 8280static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8281{
c5ca8e57 8282 u32 exit_intr_info;
51aa01d1
AK		 8283 bool unblock_nmi;
8284 u8 vector;
8285 bool idtv_info_valid;
8286
8287 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8288
cf393f75 8289 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 8290 if (vmx->nmi_known_unmasked)
8291 return;
c5ca8e57
AK		 8292 /*
8293 * Can't use vmx->exit_intr_info since we're not sure what
8294 * the exit reason is.
8295 */
8296 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 8297 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8298 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8299 /*
7b4a25cb 8300 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 8301 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8302 * a guest IRET fault.
7b4a25cb
GN		 8303 * SDM 3: 23.2.2 (September 2008)
8304 * Bit 12 is undefined in any of the following cases:
8305 * If the VM exit sets the valid bit in the IDT-vectoring
8306 * information field.
8307 * If the VM exit is due to a double fault.
cf393f75 8308 */
7b4a25cb
GN		 8309 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8310 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 8311 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8312 GUEST_INTR_STATE_NMI);
9d58b931
AK		 8313 else
8314 vmx->nmi_known_unmasked =
8315 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8316 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 8317 } else if (unlikely(vmx->soft_vnmi_blocked))
8318 vmx->vnmi_blocked_time +=
8319 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 8320}
8321
3ab66e8a 8322static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 8323 u32 idt_vectoring_info,
8324 int instr_len_field,
8325 int error_code_field)
51aa01d1 8326{
51aa01d1
AK		 8327 u8 vector;
8328 int type;
8329 bool idtv_info_valid;
8330
8331 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8332
3ab66e8a
JK		 8333 vcpu->arch.nmi_injected = false;
8334 kvm_clear_exception_queue(vcpu);
8335 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 8336
8337 if (!idtv_info_valid)
8338 return;
8339
3ab66e8a 8340 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8341
668f612f
AK		 8342 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8343 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8344
64a7ec06 8345 switch (type) {
37b96e98 8346 case INTR_TYPE_NMI_INTR:
3ab66e8a 8347 vcpu->arch.nmi_injected = true;
668f612f 8348 /*
7b4a25cb 8349 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 8350 * Clear bit "block by NMI" before VM entry if a NMI
8351 * delivery faulted.
668f612f 8352 */
3ab66e8a 8353 vmx_set_nmi_mask(vcpu, false);
37b96e98 8354 break;
37b96e98 8355 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8356 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 8357 /* fall through */
8358 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8359 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8360 u32 err = vmcs_read32(error_code_field);
851eb667 8361 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8362 } else
851eb667 8363 kvm_requeue_exception(vcpu, vector);
37b96e98 8364 break;
66fd3f7f 8365 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8366 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8367 /* fall through */
37b96e98 8368 case INTR_TYPE_EXT_INTR:
3ab66e8a 8369 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 8370 break;
8371 default:
8372 break;
f7d9238f 8373 }
cf393f75
AK		 8374}
8375
83422e17
AK		 8376static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8377{
3ab66e8a 8378 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8379 VM_EXIT_INSTRUCTION_LEN,
8380 IDT_VECTORING_ERROR_CODE);
8381}
8382
b463a6f7
AK		 8383static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8384{
3ab66e8a 8385 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8386 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8387 VM_ENTRY_INSTRUCTION_LEN,
8388 VM_ENTRY_EXCEPTION_ERROR_CODE);
8389
8390 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8391}
8392
d7cd9796
GN		 8393static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8394{
8395 int i, nr_msrs;
8396 struct perf_guest_switch_msr *msrs;
8397
8398 msrs = perf_guest_get_msrs(&nr_msrs);
8399
8400 if (!msrs)
8401 return;
8402
8403 for (i = 0; i < nr_msrs; i++)
8404 if (msrs[i].host == msrs[i].guest)
8405 clear_atomic_switch_msr(vmx, msrs[i].msr);
8406 else
8407 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8408 msrs[i].host);
8409}
8410
a3b5ba49 8411static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8412{
a2fa3e9f 8413 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8414 unsigned long debugctlmsr, cr4;
104f226b
AK		 8415
8416 /* Record the guest's net vcpu time for enforced NMI injections. */
8417 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8418 vmx->entry_time = ktime_get();
8419
8420 /* Don't enter VMX if guest state is invalid, let the exit handler
8421 start emulation until we arrive back to a valid state */
14168786 8422 if (vmx->emulation_required)
104f226b
AK		 8423 return;
8424
a7653ecd
RK		 8425 if (vmx->ple_window_dirty) {
8426 vmx->ple_window_dirty = false;
8427 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8428 }
8429
012f83cb
AG		 8430 if (vmx->nested.sync_shadow_vmcs) {
8431 copy_vmcs12_to_shadow(vmx);
8432 vmx->nested.sync_shadow_vmcs = false;
8433 }
8434
104f226b
AK		 8435 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8436 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8437 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8438 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8439
1e02ce4c 8440 cr4 = cr4_read_shadow();
d974baa3
AL		 8441 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8442 vmcs_writel(HOST_CR4, cr4);
8443 vmx->host_state.vmcs_host_cr4 = cr4;
8444 }
8445
104f226b
AK		 8446 /* When single-stepping over STI and MOV SS, we must clear the
8447 * corresponding interruptibility bits in the guest state. Otherwise
8448 * vmentry fails as it then expects bit 14 (BS) in pending debug
8449 * exceptions being set, but that's not correct for the guest debugging
8450 * case. */
8451 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8452 vmx_set_interrupt_shadow(vcpu, 0);
8453
d7cd9796 8454 atomic_switch_perf_msrs(vmx);
2a7921b7 8455 debugctlmsr = get_debugctlmsr();
d7cd9796 8456
d462b819 8457 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8458 asm(
6aa8b732 8459 /* Store host registers */
b188c81f
AK		 8460 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8461 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8462 "push %%" _ASM_CX " \n\t"
8463 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8464 "je 1f \n\t"
b188c81f 8465 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8466 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8467 "1: \n\t"
d3edefc0 8468 /* Reload cr2 if changed */
b188c81f
AK		 8469 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8470 "mov %%cr2, %%" _ASM_DX " \n\t"
8471 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8472 "je 2f \n\t"
b188c81f 8473 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8474 "2: \n\t"
6aa8b732 8475 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8476 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8477 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8478 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8479 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8480 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8481 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8482 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8483 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8484#ifdef CONFIG_X86_64
e08aa78a
AK		 8485 "mov %c[r8](%0), %%r8 \n\t"
8486 "mov %c[r9](%0), %%r9 \n\t"
8487 "mov %c[r10](%0), %%r10 \n\t"
8488 "mov %c[r11](%0), %%r11 \n\t"
8489 "mov %c[r12](%0), %%r12 \n\t"
8490 "mov %c[r13](%0), %%r13 \n\t"
8491 "mov %c[r14](%0), %%r14 \n\t"
8492 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8493#endif
b188c81f 8494 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8495
6aa8b732 8496 /* Enter guest mode */
83287ea4 8497 "jne 1f \n\t"
4ecac3fd 8498 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8499 "jmp 2f \n\t"
8500 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8501 "2: "
6aa8b732 8502 /* Save guest registers, load host registers, keep flags */
b188c81f 8503 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8504 "pop %0 \n\t"
b188c81f
AK		 8505 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8506 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8507 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8508 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8509 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8510 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8511 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8512#ifdef CONFIG_X86_64
e08aa78a
AK		 8513 "mov %%r8, %c[r8](%0) \n\t"
8514 "mov %%r9, %c[r9](%0) \n\t"
8515 "mov %%r10, %c[r10](%0) \n\t"
8516 "mov %%r11, %c[r11](%0) \n\t"
8517 "mov %%r12, %c[r12](%0) \n\t"
8518 "mov %%r13, %c[r13](%0) \n\t"
8519 "mov %%r14, %c[r14](%0) \n\t"
8520 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8521#endif
b188c81f
AK		 8522 "mov %%cr2, %%" _ASM_AX " \n\t"
8523 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8524
b188c81f 8525 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8526 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8527 ".pushsection .rodata \n\t"
8528 ".global vmx_return \n\t"
8529 "vmx_return: " _ASM_PTR " 2b \n\t"
8530 ".popsection"
e08aa78a 8531 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8532 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8533 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8534 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8535 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8536 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8537 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8538 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8539 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8540 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8541 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8542#ifdef CONFIG_X86_64
ad312c7c
ZX		 8543 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8544 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8545 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8546 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8547 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8548 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8549 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8550 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8551#endif
40712fae
AK		 8552 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8553 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8554 : "cc", "memory"
8555#ifdef CONFIG_X86_64
b188c81f 8556 , "rax", "rbx", "rdi", "rsi"
c2036300 8557 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8558#else
8559 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8560#endif
8561 );
6aa8b732 8562
2a7921b7
GN		 8563 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8564 if (debugctlmsr)
8565 update_debugctlmsr(debugctlmsr);
8566
aa67f609
AK		 8567#ifndef CONFIG_X86_64
8568 /*
8569 * The sysexit path does not restore ds/es, so we must set them to
8570 * a reasonable value ourselves.
8571 *
8572 * We can't defer this to vmx_load_host_state() since that function
8573 * may be executed in interrupt context, which saves and restore segments
8574 * around it, nullifying its effect.
8575 */
8576 loadsegment(ds, __USER_DS);
8577 loadsegment(es, __USER_DS);
8578#endif
8579
6de4f3ad 8580 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8581 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8582 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8583 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8584 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8585 vcpu->arch.regs_dirty = 0;
8586
1155f76a
AK		 8587 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8588
d462b819 8589 vmx->loaded_vmcs->launched = 1;
1b6269db 8590
51aa01d1 8591 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8592 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8593
e0b890d3
GN		 8594 /*
8595 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8596 * we did not inject a still-pending event to L1 now because of
8597 * nested_run_pending, we need to re-enable this bit.
8598 */
8599 if (vmx->nested.nested_run_pending)
8600 kvm_make_request(KVM_REQ_EVENT, vcpu);
8601
8602 vmx->nested.nested_run_pending = 0;
8603
51aa01d1
AK		 8604 vmx_complete_atomic_exit(vmx);
8605 vmx_recover_nmi_blocking(vmx);
cf393f75 8606 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8607}
8608
4fa7734c
PB		 8609static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8610{
8611 struct vcpu_vmx *vmx = to_vmx(vcpu);
8612 int cpu;
8613
8614 if (vmx->loaded_vmcs == &vmx->vmcs01)
8615 return;
8616
8617 cpu = get_cpu();
8618 vmx->loaded_vmcs = &vmx->vmcs01;
8619 vmx_vcpu_put(vcpu);
8620 vmx_vcpu_load(vcpu, cpu);
8621 vcpu->cpu = cpu;
8622 put_cpu();
8623}
8624
6aa8b732
AK		 8625static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8626{
fb3f0f51
RR		 8627 struct vcpu_vmx *vmx = to_vmx(vcpu);
8628
843e4330
KH		 8629 if (enable_pml)
8630 vmx_disable_pml(vmx);
991e7a0e 8631 free_vpid(vmx->vpid);
4fa7734c
PB		 8632 leave_guest_mode(vcpu);
8633 vmx_load_vmcs01(vcpu);
26a865f4 8634 free_nested(vmx);
4fa7734c 8635 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8636 kfree(vmx->guest_msrs);
8637 kvm_vcpu_uninit(vcpu);
a4770347 8638 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8639}
8640
fb3f0f51 8641static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8642{
fb3f0f51 8643 int err;
c16f862d 8644 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8645 int cpu;
6aa8b732 8646
a2fa3e9f 8647 if (!vmx)
fb3f0f51
RR		 8648 return ERR_PTR(-ENOMEM);
8649
991e7a0e 8650 vmx->vpid = allocate_vpid();
2384d2b3 8651
fb3f0f51
RR		 8652 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8653 if (err)
8654 goto free_vcpu;
965b58a5 8655
a2fa3e9f 8656 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8657 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8658 > PAGE_SIZE);
0123be42 8659
be6d05cf 8660 err = -ENOMEM;
fb3f0f51 8661 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8662 goto uninit_vcpu;
8663 }
965b58a5 8664
d462b819
NHE		 8665 vmx->loaded_vmcs = &vmx->vmcs01;
8666 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8667 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8668 goto free_msrs;
d462b819
NHE		 8669 if (!vmm_exclusive)
8670 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8671 loaded_vmcs_init(vmx->loaded_vmcs);
8672 if (!vmm_exclusive)
8673 kvm_cpu_vmxoff();
a2fa3e9f 8674
15ad7146
AK		 8675 cpu = get_cpu();
8676 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8677 vmx->vcpu.cpu = cpu;
8b9cf98c 8678 err = vmx_vcpu_setup(vmx);
fb3f0f51 8679 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8680 put_cpu();
fb3f0f51
RR		 8681 if (err)
8682 goto free_vmcs;
35754c98 8683 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK		 8684 err = alloc_apic_access_page(kvm);
8685 if (err)
5e4a0b3c 8686 goto free_vmcs;
a63cb560 8687 }
fb3f0f51 8688
b927a3ce
SY		 8689 if (enable_ept) {
8690 if (!kvm->arch.ept_identity_map_addr)
8691 kvm->arch.ept_identity_map_addr =
8692 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8693 err = init_rmode_identity_map(kvm);
8694 if (err)
93ea5388 8695 goto free_vmcs;
b927a3ce 8696 }
b7ebfb05 8697
b9c237bb
WV		 8698 if (nested)
8699 nested_vmx_setup_ctls_msrs(vmx);
8700
705699a1 8701 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE		 8702 vmx->nested.current_vmptr = -1ull;
8703 vmx->nested.current_vmcs12 = NULL;
8704
843e4330
KH		 8705 /*
8706 * If PML is turned on, failure on enabling PML just results in failure
8707 * of creating the vcpu, therefore we can simplify PML logic (by
8708 * avoiding dealing with cases, such as enabling PML partially on vcpus
8709 * for the guest, etc.
8710 */
8711 if (enable_pml) {
8712 err = vmx_enable_pml(vmx);
8713 if (err)
8714 goto free_vmcs;
8715 }
8716
fb3f0f51
RR		 8717 return &vmx->vcpu;
8718
8719free_vmcs:
5f3fbc34 8720 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8721free_msrs:
fb3f0f51
RR		 8722 kfree(vmx->guest_msrs);
8723uninit_vcpu:
8724 kvm_vcpu_uninit(&vmx->vcpu);
8725free_vcpu:
991e7a0e 8726 free_vpid(vmx->vpid);
a4770347 8727 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8728 return ERR_PTR(err);
6aa8b732
AK		 8729}
8730
002c7f7c
YS		 8731static void __init vmx_check_processor_compat(void *rtn)
8732{
8733 struct vmcs_config vmcs_conf;
8734
8735 *(int *)rtn = 0;
8736 if (setup_vmcs_config(&vmcs_conf) < 0)
8737 *(int *)rtn = -EIO;
8738 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8739 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8740 smp_processor_id());
8741 *(int *)rtn = -EIO;
8742 }
8743}
8744
67253af5
SY		 8745static int get_ept_level(void)
8746{
8747 return VMX_EPT_DEFAULT_GAW + 1;
8748}
8749
4b12f0de 8750static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8751{
b18d5431
XG		 8752 u8 cache;
8753 u64 ipat = 0;
4b12f0de 8754
522c68c4 8755 /* For VT-d and EPT combination
606decd6 8756 * 1. MMIO: always map as UC
522c68c4
SY		 8757 * 2. EPT with VT-d:
8758 * a. VT-d without snooping control feature: can't guarantee the
606decd6 8759 * result, try to trust guest.
522c68c4
SY		 8760 * b. VT-d with snooping control feature: snooping control feature of
8761 * VT-d engine can guarantee the cache correctness. Just set it
8762 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8763 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8764 * consistent with host MTRR
8765 */
606decd6
PB		 8766 if (is_mmio) {
8767 cache = MTRR_TYPE_UNCACHABLE;
8768 goto exit;
8769 }
8770
8771 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG		 8772 ipat = VMX_EPT_IPAT_BIT;
8773 cache = MTRR_TYPE_WRBACK;
8774 goto exit;
8775 }
8776
8777 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8778 ipat = VMX_EPT_IPAT_BIT;
0da029ed 8779 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG		 8780 cache = MTRR_TYPE_WRBACK;
8781 else
8782 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG		 8783 goto exit;
8784 }
8785
ff53604b 8786 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG		 8787
8788exit:
8789 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY		 8790}
8791
17cc3935 8792static int vmx_get_lpage_level(void)
344f414f 8793{
878403b7
SY		 8794 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8795 return PT_DIRECTORY_LEVEL;
8796 else
8797 /* For shadow and EPT supported 1GB page */
8798 return PT_PDPE_LEVEL;
344f414f
JR		 8799}
8800
feda805f
XG		 8801static void vmcs_set_secondary_exec_control(u32 new_ctl)
8802{
8803 /*
8804 * These bits in the secondary execution controls field
8805 * are dynamic, the others are mostly based on the hypervisor
8806 * architecture and the guest's CPUID. Do not touch the
8807 * dynamic bits.
8808 */
8809 u32 mask =
8810 SECONDARY_EXEC_SHADOW_VMCS |
8811 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8812 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8813
8814 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8815
8816 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8817 (new_ctl & ~mask) | (cur_ctl & mask));
8818}
8819
0e851880
SY		 8820static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8821{
4e47c7a6
SY		 8822 struct kvm_cpuid_entry2 *best;
8823 struct vcpu_vmx *vmx = to_vmx(vcpu);
feda805f 8824 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
4e47c7a6 8825
4e47c7a6 8826 if (vmx_rdtscp_supported()) {
1cea0ce6
XG		 8827 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8828 if (!rdtscp_enabled)
feda805f 8829 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
f36201e5 8830
8b97265a 8831 if (nested) {
1cea0ce6 8832 if (rdtscp_enabled)
8b97265a
PB		 8833 vmx->nested.nested_vmx_secondary_ctls_high |=
8834 SECONDARY_EXEC_RDTSCP;
8835 else
8836 vmx->nested.nested_vmx_secondary_ctls_high &=
8837 ~SECONDARY_EXEC_RDTSCP;
8838 }
4e47c7a6 8839 }
ad756a16 8840
ad756a16
MJ		 8841 /* Exposing INVPCID only when PCID is exposed */
8842 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8843 if (vmx_invpcid_supported() &&
29541bb8
XG		 8844 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8845 !guest_cpuid_has_pcid(vcpu))) {
feda805f 8846 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
29541bb8 8847
ad756a16 8848 if (best)
4f977045 8849 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8850 }
8b3e34e4 8851
feda805f
XG		 8852 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8853
8b3e34e4
XG		 8854 if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8855 if (guest_cpuid_has_pcommit(vcpu))
8856 vmx->nested.nested_vmx_secondary_ctls_high |=
8857 SECONDARY_EXEC_PCOMMIT;
8858 else
8859 vmx->nested.nested_vmx_secondary_ctls_high &=
8860 ~SECONDARY_EXEC_PCOMMIT;
8861 }
0e851880
SY		 8862}
8863
d4330ef2
JR		 8864static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8865{
7b8050f5
NHE		 8866 if (func == 1 && nested)
8867 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8868}
8869
25d92081
YZ		 8870static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8871 struct x86_exception *fault)
8872{
533558bc
JK		 8873 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8874 u32 exit_reason;
25d92081
YZ		 8875
8876 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8877 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8878 else
533558bc
JK		 8879 exit_reason = EXIT_REASON_EPT_VIOLATION;
8880 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8881 vmcs12->guest_physical_address = fault->address;
8882}
8883
155a97a3
NHE		 8884/* Callbacks for nested_ept_init_mmu_context: */
8885
8886static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8887{
8888 /* return the page table to be shadowed - in our case, EPT12 */
8889 return get_vmcs12(vcpu)->ept_pointer;
8890}
8891
8a3c1a33 8892static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8893{
ad896af0
PB		 8894 WARN_ON(mmu_is_nested(vcpu));
8895 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8896 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8897 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8898 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8899 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8900 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8901
8902 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8903}
8904
8905static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8906{
8907 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8908}
8909
19d5f10b
EK		 8910static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8911 u16 error_code)
8912{
8913 bool inequality, bit;
8914
8915 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8916 inequality =
8917 (error_code & vmcs12->page_fault_error_code_mask) !=
8918 vmcs12->page_fault_error_code_match;
8919 return inequality ^ bit;
8920}
8921
feaf0c7d
GN		 8922static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8923 struct x86_exception *fault)
8924{
8925 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8926
8927 WARN_ON(!is_guest_mode(vcpu));
8928
19d5f10b 8929 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8930 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8931 vmcs_read32(VM_EXIT_INTR_INFO),
8932 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8933 else
8934 kvm_inject_page_fault(vcpu, fault);
8935}
8936
a2bcba50
WL		 8937static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8938 struct vmcs12 *vmcs12)
8939{
8940 struct vcpu_vmx *vmx = to_vmx(vcpu);
9090422f 8941 int maxphyaddr = cpuid_maxphyaddr(vcpu);
a2bcba50
WL		 8942
8943 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9090422f
EK		 8944 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8945 vmcs12->apic_access_addr >> maxphyaddr)
a2bcba50
WL		 8946 return false;
8947
8948 /*
8949 * Translate L1 physical address to host physical
8950 * address for vmcs02. Keep the page pinned, so this
8951 * physical address remains valid. We keep a reference
8952 * to it so we can release it later.
8953 */
8954 if (vmx->nested.apic_access_page) /* shouldn't happen */
8955 nested_release_page(vmx->nested.apic_access_page);
8956 vmx->nested.apic_access_page =
8957 nested_get_page(vcpu, vmcs12->apic_access_addr);
8958 }
a7c0b07d
WL		 8959
8960 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9090422f
EK		 8961 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8962 vmcs12->virtual_apic_page_addr >> maxphyaddr)
a7c0b07d
WL		 8963 return false;
8964
8965 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8966 nested_release_page(vmx->nested.virtual_apic_page);
8967 vmx->nested.virtual_apic_page =
8968 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8969
8970 /*
8971 * Failing the vm entry is _not_ what the processor does
8972 * but it's basically the only possibility we have.
8973 * We could still enter the guest if CR8 load exits are
8974 * enabled, CR8 store exits are enabled, and virtualize APIC
8975 * access is disabled; in this case the processor would never
8976 * use the TPR shadow and we could simply clear the bit from
8977 * the execution control. But such a configuration is useless,
8978 * so let's keep the code simple.
8979 */
8980 if (!vmx->nested.virtual_apic_page)
8981 return false;
8982 }
8983
705699a1 8984 if (nested_cpu_has_posted_intr(vmcs12)) {
9090422f
EK		 8985 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8986 vmcs12->posted_intr_desc_addr >> maxphyaddr)
705699a1
WV		 8987 return false;
8988
8989 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8990 kunmap(vmx->nested.pi_desc_page);
8991 nested_release_page(vmx->nested.pi_desc_page);
8992 }
8993 vmx->nested.pi_desc_page =
8994 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8995 if (!vmx->nested.pi_desc_page)
8996 return false;
8997
8998 vmx->nested.pi_desc =
8999 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9000 if (!vmx->nested.pi_desc) {
9001 nested_release_page_clean(vmx->nested.pi_desc_page);
9002 return false;
9003 }
9004 vmx->nested.pi_desc =
9005 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9006 (unsigned long)(vmcs12->posted_intr_desc_addr &
9007 (PAGE_SIZE - 1)));
9008 }
9009
a2bcba50
WL		 9010 return true;
9011}
9012
f4124500
JK		 9013static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9014{
9015 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9016 struct vcpu_vmx *vmx = to_vmx(vcpu);
9017
9018 if (vcpu->arch.virtual_tsc_khz == 0)
9019 return;
9020
9021 /* Make sure short timeouts reliably trigger an immediate vmexit.
9022 * hrtimer_start does not guarantee this. */
9023 if (preemption_timeout <= 1) {
9024 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9025 return;
9026 }
9027
9028 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9029 preemption_timeout *= 1000000;
9030 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9031 hrtimer_start(&vmx->nested.preemption_timer,
9032 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9033}
9034
3af18d9c
WV		 9035static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9036 struct vmcs12 *vmcs12)
9037{
9038 int maxphyaddr;
9039 u64 addr;
9040
9041 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9042 return 0;
9043
9044 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9045 WARN_ON(1);
9046 return -EINVAL;
9047 }
9048 maxphyaddr = cpuid_maxphyaddr(vcpu);
9049
9050 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9051 ((addr + PAGE_SIZE) >> maxphyaddr))
9052 return -EINVAL;
9053
9054 return 0;
9055}
9056
9057/*
9058 * Merge L0's and L1's MSR bitmap, return false to indicate that
9059 * we do not use the hardware.
9060 */
9061static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9062 struct vmcs12 *vmcs12)
9063{
82f0dd4b 9064 int msr;
f2b93280
WV		 9065 struct page *page;
9066 unsigned long *msr_bitmap;
9067
9068 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9069 return false;
9070
9071 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9072 if (!page) {
9073 WARN_ON(1);
9074 return false;
9075 }
9076 msr_bitmap = (unsigned long *)kmap(page);
9077 if (!msr_bitmap) {
9078 nested_release_page_clean(page);
9079 WARN_ON(1);
9080 return false;
9081 }
9082
9083 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 9084 if (nested_cpu_has_apic_reg_virt(vmcs12))
9085 for (msr = 0x800; msr <= 0x8ff; msr++)
9086 nested_vmx_disable_intercept_for_msr(
9087 msr_bitmap,
9088 vmx_msr_bitmap_nested,
9089 msr, MSR_TYPE_R);
f2b93280
WV		 9090 /* TPR is allowed */
9091 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9092 vmx_msr_bitmap_nested,
9093 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9094 MSR_TYPE_R | MSR_TYPE_W);
608406e2
WV		 9095 if (nested_cpu_has_vid(vmcs12)) {
9096 /* EOI and self-IPI are allowed */
9097 nested_vmx_disable_intercept_for_msr(
9098 msr_bitmap,
9099 vmx_msr_bitmap_nested,
9100 APIC_BASE_MSR + (APIC_EOI >> 4),
9101 MSR_TYPE_W);
9102 nested_vmx_disable_intercept_for_msr(
9103 msr_bitmap,
9104 vmx_msr_bitmap_nested,
9105 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9106 MSR_TYPE_W);
9107 }
82f0dd4b
WV		 9108 } else {
9109 /*
9110 * Enable reading intercept of all the x2apic
9111 * MSRs. We should not rely on vmcs12 to do any
9112 * optimizations here, it may have been modified
9113 * by L1.
9114 */
9115 for (msr = 0x800; msr <= 0x8ff; msr++)
9116 __vmx_enable_intercept_for_msr(
9117 vmx_msr_bitmap_nested,
9118 msr,
9119 MSR_TYPE_R);
9120
f2b93280
WV		 9121 __vmx_enable_intercept_for_msr(
9122 vmx_msr_bitmap_nested,
9123 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
82f0dd4b 9124 MSR_TYPE_W);
608406e2
WV		 9125 __vmx_enable_intercept_for_msr(
9126 vmx_msr_bitmap_nested,
9127 APIC_BASE_MSR + (APIC_EOI >> 4),
9128 MSR_TYPE_W);
9129 __vmx_enable_intercept_for_msr(
9130 vmx_msr_bitmap_nested,
9131 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9132 MSR_TYPE_W);
82f0dd4b 9133 }
f2b93280
WV		 9134 kunmap(page);
9135 nested_release_page_clean(page);
9136
9137 return true;
9138}
9139
9140static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9141 struct vmcs12 *vmcs12)
9142{
82f0dd4b 9143 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 9144 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV		 9145 !nested_cpu_has_vid(vmcs12) &&
9146 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV		 9147 return 0;
9148
9149 /*
9150 * If virtualize x2apic mode is enabled,
9151 * virtualize apic access must be disabled.
9152 */
82f0dd4b
WV		 9153 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9154 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 9155 return -EINVAL;
9156
608406e2
WV		 9157 /*
9158 * If virtual interrupt delivery is enabled,
9159 * we must exit on external interrupts.
9160 */
9161 if (nested_cpu_has_vid(vmcs12) &&
9162 !nested_exit_on_intr(vcpu))
9163 return -EINVAL;
9164
705699a1
WV		 9165 /*
9166 * bits 15:8 should be zero in posted_intr_nv,
9167 * the descriptor address has been already checked
9168 * in nested_get_vmcs12_pages.
9169 */
9170 if (nested_cpu_has_posted_intr(vmcs12) &&
9171 (!nested_cpu_has_vid(vmcs12) ||
9172 !nested_exit_intr_ack_set(vcpu) ||
9173 vmcs12->posted_intr_nv & 0xff00))
9174 return -EINVAL;
9175
f2b93280
WV		 9176 /* tpr shadow is needed by all apicv features. */
9177 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9178 return -EINVAL;
9179
9180 return 0;
3af18d9c
WV		 9181}
9182
e9ac033e
EK		 9183static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9184 unsigned long count_field,
92d71bc6 9185 unsigned long addr_field)
ff651cb6 9186{
92d71bc6 9187 int maxphyaddr;
e9ac033e
EK		 9188 u64 count, addr;
9189
9190 if (vmcs12_read_any(vcpu, count_field, &count) ||
9191 vmcs12_read_any(vcpu, addr_field, &addr)) {
9192 WARN_ON(1);
9193 return -EINVAL;
9194 }
9195 if (count == 0)
9196 return 0;
92d71bc6 9197 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK		 9198 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9199 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9200 pr_warn_ratelimited(
9201 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9202 addr_field, maxphyaddr, count, addr);
9203 return -EINVAL;
9204 }
9205 return 0;
9206}
9207
9208static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9209 struct vmcs12 *vmcs12)
9210{
e9ac033e
EK		 9211 if (vmcs12->vm_exit_msr_load_count == 0 &&
9212 vmcs12->vm_exit_msr_store_count == 0 &&
9213 vmcs12->vm_entry_msr_load_count == 0)
9214 return 0; /* Fast path */
e9ac033e 9215 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9216 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9217 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9218 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9219 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9220 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK		 9221 return -EINVAL;
9222 return 0;
9223}
9224
9225static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9226 struct vmx_msr_entry *e)
9227{
9228 /* x2APIC MSR accesses are not allowed */
8a9781f7 9229 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK		 9230 return -EINVAL;
9231 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9232 e->index == MSR_IA32_UCODE_REV)
9233 return -EINVAL;
9234 if (e->reserved != 0)
ff651cb6
WV		 9235 return -EINVAL;
9236 return 0;
9237}
9238
e9ac033e
EK		 9239static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9240 struct vmx_msr_entry *e)
ff651cb6
WV		 9241{
9242 if (e->index == MSR_FS_BASE ||
9243 e->index == MSR_GS_BASE ||
e9ac033e
EK		 9244 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9245 nested_vmx_msr_check_common(vcpu, e))
9246 return -EINVAL;
9247 return 0;
9248}
9249
9250static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9251 struct vmx_msr_entry *e)
9252{
9253 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9254 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 9255 return -EINVAL;
9256 return 0;
9257}
9258
9259/*
9260 * Load guest's/host's msr at nested entry/exit.
9261 * return 0 for success, entry index for failure.
9262 */
9263static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9264{
9265 u32 i;
9266 struct vmx_msr_entry e;
9267 struct msr_data msr;
9268
9269 msr.host_initiated = false;
9270 for (i = 0; i < count; i++) {
54bf36aa
PB		 9271 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9272 &e, sizeof(e))) {
e9ac033e
EK		 9273 pr_warn_ratelimited(
9274 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9275 __func__, i, gpa + i * sizeof(e));
ff651cb6 9276 goto fail;
e9ac033e
EK		 9277 }
9278 if (nested_vmx_load_msr_check(vcpu, &e)) {
9279 pr_warn_ratelimited(
9280 "%s check failed (%u, 0x%x, 0x%x)\n",
9281 __func__, i, e.index, e.reserved);
9282 goto fail;
9283 }
ff651cb6
WV		 9284 msr.index = e.index;
9285 msr.data = e.value;
e9ac033e
EK		 9286 if (kvm_set_msr(vcpu, &msr)) {
9287 pr_warn_ratelimited(
9288 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9289 __func__, i, e.index, e.value);
ff651cb6 9290 goto fail;
e9ac033e 9291 }
ff651cb6
WV		 9292 }
9293 return 0;
9294fail:
9295 return i + 1;
9296}
9297
9298static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9299{
9300 u32 i;
9301 struct vmx_msr_entry e;
9302
9303 for (i = 0; i < count; i++) {
609e36d3 9304 struct msr_data msr_info;
54bf36aa
PB		 9305 if (kvm_vcpu_read_guest(vcpu,
9306 gpa + i * sizeof(e),
9307 &e, 2 * sizeof(u32))) {
e9ac033e
EK		 9308 pr_warn_ratelimited(
9309 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9310 __func__, i, gpa + i * sizeof(e));
ff651cb6 9311 return -EINVAL;
e9ac033e
EK		 9312 }
9313 if (nested_vmx_store_msr_check(vcpu, &e)) {
9314 pr_warn_ratelimited(
9315 "%s check failed (%u, 0x%x, 0x%x)\n",
9316 __func__, i, e.index, e.reserved);
ff651cb6 9317 return -EINVAL;
e9ac033e 9318 }
609e36d3
PB		 9319 msr_info.host_initiated = false;
9320 msr_info.index = e.index;
9321 if (kvm_get_msr(vcpu, &msr_info)) {
e9ac033e
EK		 9322 pr_warn_ratelimited(
9323 "%s cannot read MSR (%u, 0x%x)\n",
9324 __func__, i, e.index);
9325 return -EINVAL;
9326 }
54bf36aa
PB		 9327 if (kvm_vcpu_write_guest(vcpu,
9328 gpa + i * sizeof(e) +
9329 offsetof(struct vmx_msr_entry, value),
9330 &msr_info.data, sizeof(msr_info.data))) {
e9ac033e
EK		 9331 pr_warn_ratelimited(
9332 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9333 __func__, i, e.index, msr_info.data);
e9ac033e
EK		 9334 return -EINVAL;
9335 }
ff651cb6
WV		 9336 }
9337 return 0;
9338}
9339
fe3ef05c
NHE		 9340/*
9341 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9342 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9343 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 9344 * guest in a way that will both be appropriate to L1's requests, and our
9345 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9346 * function also has additional necessary side-effects, like setting various
9347 * vcpu->arch fields.
9348 */
9349static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9350{
9351 struct vcpu_vmx *vmx = to_vmx(vcpu);
9352 u32 exec_control;
9353
9354 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9355 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9356 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9357 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9358 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9359 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9360 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9361 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9362 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9363 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9364 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9365 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9366 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9367 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9368 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9369 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9370 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9371 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9372 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9373 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9374 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9375 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9376 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9377 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9378 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9379 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9380 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9381 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9382 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9383 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9384 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9385 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9386 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9387 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9388 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9389 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9390
2996fca0
JK		 9391 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9392 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9393 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9394 } else {
9395 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9396 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9397 }
fe3ef05c
NHE		 9398 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9399 vmcs12->vm_entry_intr_info_field);
9400 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9401 vmcs12->vm_entry_exception_error_code);
9402 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9403 vmcs12->vm_entry_instruction_len);
9404 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9405 vmcs12->guest_interruptibility_info);
fe3ef05c 9406 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9407 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 9408 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9409 vmcs12->guest_pending_dbg_exceptions);
9410 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9411 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9412
81dc01f7
WL		 9413 if (nested_cpu_has_xsaves(vmcs12))
9414 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 9415 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9416
f4124500
JK		 9417 exec_control = vmcs12->pin_based_vm_exec_control;
9418 exec_control |= vmcs_config.pin_based_exec_ctrl;
705699a1
WV		 9419 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9420
9421 if (nested_cpu_has_posted_intr(vmcs12)) {
9422 /*
9423 * Note that we use L0's vector here and in
9424 * vmx_deliver_nested_posted_interrupt.
9425 */
9426 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9427 vmx->nested.pi_pending = false;
9428 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9429 vmcs_write64(POSTED_INTR_DESC_ADDR,
9430 page_to_phys(vmx->nested.pi_desc_page) +
9431 (unsigned long)(vmcs12->posted_intr_desc_addr &
9432 (PAGE_SIZE - 1)));
9433 } else
9434 exec_control &= ~PIN_BASED_POSTED_INTR;
9435
f4124500 9436 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 9437
f4124500
JK		 9438 vmx->nested.preemption_timer_expired = false;
9439 if (nested_cpu_has_preemption_timer(vmcs12))
9440 vmx_start_preemption_timer(vcpu);
0238ea91 9441
fe3ef05c
NHE		 9442 /*
9443 * Whether page-faults are trapped is determined by a combination of
9444 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9445 * If enable_ept, L0 doesn't care about page faults and we should
9446 * set all of these to L1's desires. However, if !enable_ept, L0 does
9447 * care about (at least some) page faults, and because it is not easy
9448 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9449 * to exit on each and every L2 page fault. This is done by setting
9450 * MASK=MATCH=0 and (see below) EB.PF=1.
9451 * Note that below we don't need special code to set EB.PF beyond the
9452 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9453 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9454 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9455 *
9456 * A problem with this approach (when !enable_ept) is that L1 may be
9457 * injected with more page faults than it asked for. This could have
9458 * caused problems, but in practice existing hypervisors don't care.
9459 * To fix this, we will need to emulate the PFEC checking (on the L1
9460 * page tables), using walk_addr(), when injecting PFs to L1.
9461 */
9462 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9463 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9464 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9465 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9466
9467 if (cpu_has_secondary_exec_ctrls()) {
f4124500 9468 exec_control = vmx_secondary_exec_control(vmx);
e2821620 9469
fe3ef05c 9470 /* Take the following fields only from vmcs12 */
696dfd95 9471 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 9472 SECONDARY_EXEC_RDTSCP |
696dfd95 9473 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8b3e34e4
XG		 9474 SECONDARY_EXEC_APIC_REGISTER_VIRT |
9475 SECONDARY_EXEC_PCOMMIT);
fe3ef05c
NHE		 9476 if (nested_cpu_has(vmcs12,
9477 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9478 exec_control |= vmcs12->secondary_vm_exec_control;
9479
9480 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 9481 /*
9482 * If translation failed, no matter: This feature asks
9483 * to exit when accessing the given address, and if it
9484 * can never be accessed, this feature won't do
9485 * anything anyway.
9486 */
9487 if (!vmx->nested.apic_access_page)
9488 exec_control &=
9489 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9490 else
9491 vmcs_write64(APIC_ACCESS_ADDR,
9492 page_to_phys(vmx->nested.apic_access_page));
f2b93280 9493 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
35754c98 9494 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
ca3f257a
JK		 9495 exec_control |=
9496 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 9497 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 9498 }
9499
608406e2
WV		 9500 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9501 vmcs_write64(EOI_EXIT_BITMAP0,
9502 vmcs12->eoi_exit_bitmap0);
9503 vmcs_write64(EOI_EXIT_BITMAP1,
9504 vmcs12->eoi_exit_bitmap1);
9505 vmcs_write64(EOI_EXIT_BITMAP2,
9506 vmcs12->eoi_exit_bitmap2);
9507 vmcs_write64(EOI_EXIT_BITMAP3,
9508 vmcs12->eoi_exit_bitmap3);
9509 vmcs_write16(GUEST_INTR_STATUS,
9510 vmcs12->guest_intr_status);
9511 }
9512
fe3ef05c
NHE		 9513 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9514 }
9515
9516
9517 /*
9518 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9519 * Some constant fields are set here by vmx_set_constant_host_state().
9520 * Other fields are different per CPU, and will be set later when
9521 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9522 */
a547c6db 9523 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 9524
9525 /*
9526 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9527 * entry, but only if the current (host) sp changed from the value
9528 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9529 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9530 * here we just force the write to happen on entry.
9531 */
9532 vmx->host_rsp = 0;
9533
9534 exec_control = vmx_exec_control(vmx); /* L0's desires */
9535 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9536 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9537 exec_control &= ~CPU_BASED_TPR_SHADOW;
9538 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 9539
9540 if (exec_control & CPU_BASED_TPR_SHADOW) {
9541 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9542 page_to_phys(vmx->nested.virtual_apic_page));
9543 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9544 }
9545
3af18d9c 9546 if (cpu_has_vmx_msr_bitmap() &&
670125bd
WV		 9547 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9548 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9549 /* MSR_BITMAP will be set by following vmx_set_efer. */
3af18d9c
WV		 9550 } else
9551 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9552
fe3ef05c 9553 /*
3af18d9c 9554 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 9555 * Rather, exit every time.
9556 */
fe3ef05c
NHE		 9557 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9558 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9559
9560 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9561
9562 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9563 * bitwise-or of what L1 wants to trap for L2, and what we want to
9564 * trap. Note that CR0.TS also needs updating - we do this later.
9565 */
9566 update_exception_bitmap(vcpu);
9567 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9568 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9569
8049d651
NHE		 9570 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9571 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9572 * bits are further modified by vmx_set_efer() below.
9573 */
f4124500 9574 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9575
9576 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9577 * emulated by vmx_set_efer(), below.
9578 */
2961e876 9579 vm_entry_controls_init(vmx,
8049d651
NHE		 9580 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9581 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9582 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9583
44811c02 9584 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9585 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9586 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9587 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9588 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9589
9590
9591 set_cr4_guest_host_mask(vmx);
9592
36be0b9d
PB		 9593 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9594 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9595
27fc51b2
NHE		 9596 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9597 vmcs_write64(TSC_OFFSET,
9598 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9599 else
9600 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9601
9602 if (enable_vpid) {
9603 /*
9604 * Trivially support vpid by letting L2s share their parent
9605 * L1's vpid. TODO: move to a more elaborate solution, giving
9606 * each L2 its own vpid and exposing the vpid feature to L1.
9607 */
9608 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9609 vmx_flush_tlb(vcpu);
9610 }
9611
155a97a3
NHE		 9612 if (nested_cpu_has_ept(vmcs12)) {
9613 kvm_mmu_unload(vcpu);
9614 nested_ept_init_mmu_context(vcpu);
9615 }
9616
fe3ef05c
NHE		 9617 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9618 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9619 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9620 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9621 else
9622 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9623 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9624 vmx_set_efer(vcpu, vcpu->arch.efer);
9625
9626 /*
9627 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9628 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9629 * The CR0_READ_SHADOW is what L2 should have expected to read given
9630 * the specifications by L1; It's not enough to take
9631 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9632 * have more bits than L1 expected.
9633 */
9634 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9635 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9636
9637 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9638 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9639
9640 /* shadow page tables on either EPT or shadow page tables */
9641 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9642 kvm_mmu_reset_context(vcpu);
9643
feaf0c7d
GN		 9644 if (!enable_ept)
9645 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9646
3633cfc3
NHE		 9647 /*
9648 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9649 */
9650 if (enable_ept) {
9651 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9652 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9653 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9654 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9655 }
9656
fe3ef05c
NHE		 9657 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9658 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9659}
9660
cd232ad0
NHE		 9661/*
9662 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9663 * for running an L2 nested guest.
9664 */
9665static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9666{
9667 struct vmcs12 *vmcs12;
9668 struct vcpu_vmx *vmx = to_vmx(vcpu);
9669 int cpu;
9670 struct loaded_vmcs *vmcs02;
384bb783 9671 bool ia32e;
ff651cb6 9672 u32 msr_entry_idx;
cd232ad0
NHE		 9673
9674 if (!nested_vmx_check_permission(vcpu) ||
9675 !nested_vmx_check_vmcs12(vcpu))
9676 return 1;
9677
9678 skip_emulated_instruction(vcpu);
9679 vmcs12 = get_vmcs12(vcpu);
9680
012f83cb
AG		 9681 if (enable_shadow_vmcs)
9682 copy_shadow_to_vmcs12(vmx);
9683
7c177938
NHE		 9684 /*
9685 * The nested entry process starts with enforcing various prerequisites
9686 * on vmcs12 as required by the Intel SDM, and act appropriately when
9687 * they fail: As the SDM explains, some conditions should cause the
9688 * instruction to fail, while others will cause the instruction to seem
9689 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9690 * To speed up the normal (success) code path, we should avoid checking
9691 * for misconfigurations which will anyway be caught by the processor
9692 * when using the merged vmcs02.
9693 */
9694 if (vmcs12->launch_state == launch) {
9695 nested_vmx_failValid(vcpu,
9696 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9697 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9698 return 1;
9699 }
9700
6dfacadd
JK		 9701 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9702 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9703 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9704 return 1;
9705 }
9706
3af18d9c 9707 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9708 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9709 return 1;
9710 }
9711
3af18d9c 9712 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9713 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9714 return 1;
9715 }
9716
f2b93280
WV		 9717 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9718 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9719 return 1;
9720 }
9721
e9ac033e
EK		 9722 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9723 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9724 return 1;
9725 }
9726
7c177938 9727 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9728 vmx->nested.nested_vmx_true_procbased_ctls_low,
9729 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9730 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9731 vmx->nested.nested_vmx_secondary_ctls_low,
9732 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9733 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9734 vmx->nested.nested_vmx_pinbased_ctls_low,
9735 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9736 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9737 vmx->nested.nested_vmx_true_exit_ctls_low,
9738 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9739 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9740 vmx->nested.nested_vmx_true_entry_ctls_low,
9741 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9742 {
9743 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9744 return 1;
9745 }
9746
9747 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9748 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9749 nested_vmx_failValid(vcpu,
9750 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9751 return 1;
9752 }
9753
b9c237bb 9754 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9755 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9756 nested_vmx_entry_failure(vcpu, vmcs12,
9757 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9758 return 1;
9759 }
9760 if (vmcs12->vmcs_link_pointer != -1ull) {
9761 nested_vmx_entry_failure(vcpu, vmcs12,
9762 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9763 return 1;
9764 }
9765
384bb783 9766 /*
cb0c8cda 9767 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9768 * are performed on the field for the IA32_EFER MSR:
9769 * - Bits reserved in the IA32_EFER MSR must be 0.
9770 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9771 * the IA-32e mode guest VM-exit control. It must also be identical
9772 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9773 * CR0.PG) is 1.
9774 */
9775 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9776 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9777 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9778 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9779 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9780 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9781 nested_vmx_entry_failure(vcpu, vmcs12,
9782 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9783 return 1;
9784 }
9785 }
9786
9787 /*
9788 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9789 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9790 * the values of the LMA and LME bits in the field must each be that of
9791 * the host address-space size VM-exit control.
9792 */
9793 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9794 ia32e = (vmcs12->vm_exit_controls &
9795 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9796 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9797 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9798 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9799 nested_vmx_entry_failure(vcpu, vmcs12,
9800 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9801 return 1;
9802 }
9803 }
9804
7c177938
NHE		 9805 /*
9806 * We're finally done with prerequisite checking, and can start with
9807 * the nested entry.
9808 */
9809
cd232ad0
NHE		 9810 vmcs02 = nested_get_current_vmcs02(vmx);
9811 if (!vmcs02)
9812 return -ENOMEM;
9813
9814 enter_guest_mode(vcpu);
9815
9816 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9817
2996fca0
JK		 9818 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9819 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9820
cd232ad0
NHE		 9821 cpu = get_cpu();
9822 vmx->loaded_vmcs = vmcs02;
9823 vmx_vcpu_put(vcpu);
9824 vmx_vcpu_load(vcpu, cpu);
9825 vcpu->cpu = cpu;
9826 put_cpu();
9827
36c3cc42
JK		 9828 vmx_segment_cache_clear(vmx);
9829
cd232ad0
NHE		 9830 prepare_vmcs02(vcpu, vmcs12);
9831
ff651cb6
WV		 9832 msr_entry_idx = nested_vmx_load_msr(vcpu,
9833 vmcs12->vm_entry_msr_load_addr,
9834 vmcs12->vm_entry_msr_load_count);
9835 if (msr_entry_idx) {
9836 leave_guest_mode(vcpu);
9837 vmx_load_vmcs01(vcpu);
9838 nested_vmx_entry_failure(vcpu, vmcs12,
9839 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9840 return 1;
9841 }
9842
9843 vmcs12->launch_state = 1;
9844
6dfacadd 9845 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 9846 return kvm_vcpu_halt(vcpu);
6dfacadd 9847
7af40ad3
JK		 9848 vmx->nested.nested_run_pending = 1;
9849
cd232ad0
NHE		 9850 /*
9851 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9852 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9853 * returned as far as L1 is concerned. It will only return (and set
9854 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9855 */
9856 return 1;
9857}
9858
4704d0be
NHE		 9859/*
9860 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9861 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9862 * This function returns the new value we should put in vmcs12.guest_cr0.
9863 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9864 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9865 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9866 * didn't trap the bit, because if L1 did, so would L0).
9867 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9868 * been modified by L2, and L1 knows it. So just leave the old value of
9869 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9870 * isn't relevant, because if L0 traps this bit it can set it to anything.
9871 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9872 * changed these bits, and therefore they need to be updated, but L0
9873 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9874 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9875 */
9876static inline unsigned long
9877vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9878{
9879 return
9880 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9881 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9882 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9883 vcpu->arch.cr0_guest_owned_bits));
9884}
9885
9886static inline unsigned long
9887vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9888{
9889 return
9890 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9891 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9892 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9893 vcpu->arch.cr4_guest_owned_bits));
9894}
9895
5f3d5799
JK		 9896static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9897 struct vmcs12 *vmcs12)
9898{
9899 u32 idt_vectoring;
9900 unsigned int nr;
9901
851eb667 9902 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9903 nr = vcpu->arch.exception.nr;
9904 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9905
9906 if (kvm_exception_is_soft(nr)) {
9907 vmcs12->vm_exit_instruction_len =
9908 vcpu->arch.event_exit_inst_len;
9909 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9910 } else
9911 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9912
9913 if (vcpu->arch.exception.has_error_code) {
9914 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9915 vmcs12->idt_vectoring_error_code =
9916 vcpu->arch.exception.error_code;
9917 }
9918
9919 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9920 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9921 vmcs12->idt_vectoring_info_field =
9922 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9923 } else if (vcpu->arch.interrupt.pending) {
9924 nr = vcpu->arch.interrupt.nr;
9925 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9926
9927 if (vcpu->arch.interrupt.soft) {
9928 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9929 vmcs12->vm_entry_instruction_len =
9930 vcpu->arch.event_exit_inst_len;
9931 } else
9932 idt_vectoring |= INTR_TYPE_EXT_INTR;
9933
9934 vmcs12->idt_vectoring_info_field = idt_vectoring;
9935 }
9936}
9937
b6b8a145
JK		 9938static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9939{
9940 struct vcpu_vmx *vmx = to_vmx(vcpu);
9941
f4124500
JK		 9942 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9943 vmx->nested.preemption_timer_expired) {
9944 if (vmx->nested.nested_run_pending)
9945 return -EBUSY;
9946 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9947 return 0;
9948 }
9949
b6b8a145 9950 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9951 if (vmx->nested.nested_run_pending ||
9952 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9953 return -EBUSY;
9954 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9955 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9956 INTR_INFO_VALID_MASK, 0);
9957 /*
9958 * The NMI-triggered VM exit counts as injection:
9959 * clear this one and block further NMIs.
9960 */
9961 vcpu->arch.nmi_pending = 0;
9962 vmx_set_nmi_mask(vcpu, true);
9963 return 0;
9964 }
9965
9966 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9967 nested_exit_on_intr(vcpu)) {
9968 if (vmx->nested.nested_run_pending)
9969 return -EBUSY;
9970 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 9971 return 0;
b6b8a145
JK		 9972 }
9973
705699a1 9974 return vmx_complete_nested_posted_interrupt(vcpu);
b6b8a145
JK		 9975}
9976
f4124500
JK		 9977static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9978{
9979 ktime_t remaining =
9980 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9981 u64 value;
9982
9983 if (ktime_to_ns(remaining) <= 0)
9984 return 0;
9985
9986 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9987 do_div(value, 1000000);
9988 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9989}
9990
4704d0be
NHE		 9991/*
9992 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9993 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9994 * and this function updates it to reflect the changes to the guest state while
9995 * L2 was running (and perhaps made some exits which were handled directly by L0
9996 * without going back to L1), and to reflect the exit reason.
9997 * Note that we do not have to copy here all VMCS fields, just those that
9998 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9999 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10000 * which already writes to vmcs12 directly.
10001 */
533558bc
JK		 10002static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10003 u32 exit_reason, u32 exit_intr_info,
10004 unsigned long exit_qualification)
4704d0be
NHE		 10005{
10006 /* update guest state fields: */
10007 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10008 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10009
4704d0be
NHE		 10010 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10011 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10012 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10013
10014 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10015 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10016 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10017 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10018 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10019 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10020 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10021 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10022 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10023 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10024 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10025 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10026 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10027 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10028 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10029 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10030 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10031 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10032 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10033 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10034 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10035 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10036 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10037 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10038 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10039 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10040 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10041 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10042 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10043 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10044 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10045 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10046 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10047 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10048 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10049 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10050
4704d0be
NHE		 10051 vmcs12->guest_interruptibility_info =
10052 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10053 vmcs12->guest_pending_dbg_exceptions =
10054 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 10055 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10056 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10057 else
10058 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 10059
f4124500
JK		 10060 if (nested_cpu_has_preemption_timer(vmcs12)) {
10061 if (vmcs12->vm_exit_controls &
10062 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10063 vmcs12->vmx_preemption_timer_value =
10064 vmx_get_preemption_timer_value(vcpu);
10065 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10066 }
7854cbca 10067
3633cfc3
NHE		 10068 /*
10069 * In some cases (usually, nested EPT), L2 is allowed to change its
10070 * own CR3 without exiting. If it has changed it, we must keep it.
10071 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10072 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10073 *
10074 * Additionally, restore L2's PDPTR to vmcs12.
10075 */
10076 if (enable_ept) {
10077 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10078 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10079 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10080 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10081 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10082 }
10083
608406e2
WV		 10084 if (nested_cpu_has_vid(vmcs12))
10085 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10086
c18911a2
JK		 10087 vmcs12->vm_entry_controls =
10088 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 10089 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 10090
2996fca0
JK		 10091 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10092 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10093 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10094 }
10095
4704d0be
NHE		 10096 /* TODO: These cannot have changed unless we have MSR bitmaps and
10097 * the relevant bit asks not to trap the change */
b8c07d55 10098 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 10099 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 10100 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10101 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 10102 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10103 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10104 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 10105 if (vmx_mpx_supported())
10106 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 10107 if (nested_cpu_has_xsaves(vmcs12))
10108 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 10109
10110 /* update exit information fields: */
10111
533558bc
JK		 10112 vmcs12->vm_exit_reason = exit_reason;
10113 vmcs12->exit_qualification = exit_qualification;
4704d0be 10114
533558bc 10115 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 10116 if ((vmcs12->vm_exit_intr_info &
10117 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10118 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10119 vmcs12->vm_exit_intr_error_code =
10120 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 10121 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 10122 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10123 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10124
5f3d5799
JK		 10125 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10126 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10127 * instead of reading the real value. */
4704d0be 10128 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 10129
10130 /*
10131 * Transfer the event that L0 or L1 may wanted to inject into
10132 * L2 to IDT_VECTORING_INFO_FIELD.
10133 */
10134 vmcs12_save_pending_event(vcpu, vmcs12);
10135 }
10136
10137 /*
10138 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10139 * preserved above and would only end up incorrectly in L1.
10140 */
10141 vcpu->arch.nmi_injected = false;
10142 kvm_clear_exception_queue(vcpu);
10143 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 10144}
10145
10146/*
10147 * A part of what we need to when the nested L2 guest exits and we want to
10148 * run its L1 parent, is to reset L1's guest state to the host state specified
10149 * in vmcs12.
10150 * This function is to be called not only on normal nested exit, but also on
10151 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10152 * Failures During or After Loading Guest State").
10153 * This function should be called when the active VMCS is L1's (vmcs01).
10154 */
733568f9
JK		 10155static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10156 struct vmcs12 *vmcs12)
4704d0be 10157{
21feb4eb
ACL		 10158 struct kvm_segment seg;
10159
4704d0be
NHE		 10160 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10161 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10162 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 10163 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10164 else
10165 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10166 vmx_set_efer(vcpu, vcpu->arch.efer);
10167
10168 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10169 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10170 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 10171 /*
10172 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10173 * actually changed, because it depends on the current state of
10174 * fpu_active (which may have changed).
10175 * Note that vmx_set_cr0 refers to efer set above.
10176 */
9e3e4dbf 10177 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 10178 /*
10179 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10180 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10181 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10182 */
10183 update_exception_bitmap(vcpu);
10184 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10185 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10186
10187 /*
10188 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10189 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10190 */
10191 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10192 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10193
29bf08f1 10194 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10195
4704d0be
NHE		 10196 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10197 kvm_mmu_reset_context(vcpu);
10198
feaf0c7d
GN		 10199 if (!enable_ept)
10200 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10201
4704d0be
NHE		 10202 if (enable_vpid) {
10203 /*
10204 * Trivially support vpid by letting L2s share their parent
10205 * L1's vpid. TODO: move to a more elaborate solution, giving
10206 * each L2 its own vpid and exposing the vpid feature to L1.
10207 */
10208 vmx_flush_tlb(vcpu);
10209 }
10210
10211
10212 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10213 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10214 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10215 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10216 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10217
36be0b9d
PB		 10218 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10219 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10220 vmcs_write64(GUEST_BNDCFGS, 0);
10221
44811c02 10222 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10223 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 10224 vcpu->arch.pat = vmcs12->host_ia32_pat;
10225 }
4704d0be
NHE		 10226 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10227 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10228 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10229
21feb4eb
ACL		 10230 /* Set L1 segment info according to Intel SDM
10231 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10232 seg = (struct kvm_segment) {
10233 .base = 0,
10234 .limit = 0xFFFFFFFF,
10235 .selector = vmcs12->host_cs_selector,
10236 .type = 11,
10237 .present = 1,
10238 .s = 1,
10239 .g = 1
10240 };
10241 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10242 seg.l = 1;
10243 else
10244 seg.db = 1;
10245 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10246 seg = (struct kvm_segment) {
10247 .base = 0,
10248 .limit = 0xFFFFFFFF,
10249 .type = 3,
10250 .present = 1,
10251 .s = 1,
10252 .db = 1,
10253 .g = 1
10254 };
10255 seg.selector = vmcs12->host_ds_selector;
10256 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10257 seg.selector = vmcs12->host_es_selector;
10258 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10259 seg.selector = vmcs12->host_ss_selector;
10260 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10261 seg.selector = vmcs12->host_fs_selector;
10262 seg.base = vmcs12->host_fs_base;
10263 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10264 seg.selector = vmcs12->host_gs_selector;
10265 seg.base = vmcs12->host_gs_base;
10266 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10267 seg = (struct kvm_segment) {
205befd9 10268 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 10269 .limit = 0x67,
10270 .selector = vmcs12->host_tr_selector,
10271 .type = 11,
10272 .present = 1
10273 };
10274 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10275
503cd0c5
JK		 10276 kvm_set_dr(vcpu, 7, 0x400);
10277 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 10278
3af18d9c
WV		 10279 if (cpu_has_vmx_msr_bitmap())
10280 vmx_set_msr_bitmap(vcpu);
10281
ff651cb6
WV		 10282 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10283 vmcs12->vm_exit_msr_load_count))
10284 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 10285}
10286
10287/*
10288 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10289 * and modify vmcs12 to make it see what it would expect to see there if
10290 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10291 */
533558bc
JK		 10292static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10293 u32 exit_intr_info,
10294 unsigned long exit_qualification)
4704d0be
NHE		 10295{
10296 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 10297 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10298
5f3d5799
JK		 10299 /* trying to cancel vmlaunch/vmresume is a bug */
10300 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10301
4704d0be 10302 leave_guest_mode(vcpu);
533558bc
JK		 10303 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10304 exit_qualification);
4704d0be 10305
ff651cb6
WV		 10306 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10307 vmcs12->vm_exit_msr_store_count))
10308 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10309
f3380ca5
WL		 10310 vmx_load_vmcs01(vcpu);
10311
77b0f5d6
BD		 10312 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10313 && nested_exit_intr_ack_set(vcpu)) {
10314 int irq = kvm_cpu_get_interrupt(vcpu);
10315 WARN_ON(irq < 0);
10316 vmcs12->vm_exit_intr_info = irq |
10317 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10318 }
10319
542060ea
JK		 10320 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10321 vmcs12->exit_qualification,
10322 vmcs12->idt_vectoring_info_field,
10323 vmcs12->vm_exit_intr_info,
10324 vmcs12->vm_exit_intr_error_code,
10325 KVM_ISA_VMX);
4704d0be 10326
2961e876
GN		 10327 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10328 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 10329 vmx_segment_cache_clear(vmx);
10330
4704d0be
NHE		 10331 /* if no vmcs02 cache requested, remove the one we used */
10332 if (VMCS02_POOL_SIZE == 0)
10333 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10334
10335 load_vmcs12_host_state(vcpu, vmcs12);
10336
27fc51b2 10337 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 10338 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10339
10340 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10341 vmx->host_rsp = 0;
10342
10343 /* Unpin physical memory we referred to in vmcs02 */
10344 if (vmx->nested.apic_access_page) {
10345 nested_release_page(vmx->nested.apic_access_page);
48d89b92 10346 vmx->nested.apic_access_page = NULL;
4704d0be 10347 }
a7c0b07d
WL		 10348 if (vmx->nested.virtual_apic_page) {
10349 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 10350 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 10351 }
705699a1
WV		 10352 if (vmx->nested.pi_desc_page) {
10353 kunmap(vmx->nested.pi_desc_page);
10354 nested_release_page(vmx->nested.pi_desc_page);
10355 vmx->nested.pi_desc_page = NULL;
10356 vmx->nested.pi_desc = NULL;
10357 }
4704d0be 10358
38b99173
TC		 10359 /*
10360 * We are now running in L2, mmu_notifier will force to reload the
10361 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10362 */
10363 kvm_vcpu_reload_apic_access_page(vcpu);
10364
4704d0be
NHE		 10365 /*
10366 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10367 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10368 * success or failure flag accordingly.
10369 */
10370 if (unlikely(vmx->fail)) {
10371 vmx->fail = 0;
10372 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10373 } else
10374 nested_vmx_succeed(vcpu);
012f83cb
AG		 10375 if (enable_shadow_vmcs)
10376 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 10377
10378 /* in case we halted in L2 */
10379 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 10380}
10381
42124925
JK		 10382/*
10383 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10384 */
10385static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10386{
10387 if (is_guest_mode(vcpu))
533558bc 10388 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 10389 free_nested(to_vmx(vcpu));
10390}
10391
7c177938
NHE		 10392/*
10393 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10394 * 23.7 "VM-entry failures during or after loading guest state" (this also
10395 * lists the acceptable exit-reason and exit-qualification parameters).
10396 * It should only be called before L2 actually succeeded to run, and when
10397 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10398 */
10399static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10400 struct vmcs12 *vmcs12,
10401 u32 reason, unsigned long qualification)
10402{
10403 load_vmcs12_host_state(vcpu, vmcs12);
10404 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10405 vmcs12->exit_qualification = qualification;
10406 nested_vmx_succeed(vcpu);
012f83cb
AG		 10407 if (enable_shadow_vmcs)
10408 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 10409}
10410
8a76d7f2
JR		 10411static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10412 struct x86_instruction_info *info,
10413 enum x86_intercept_stage stage)
10414{
10415 return X86EMUL_CONTINUE;
10416}
10417
48d89b92 10418static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 10419{
b4a2d31d
RK		 10420 if (ple_gap)
10421 shrink_ple_window(vcpu);
ae97a3b8
RK		 10422}
10423
843e4330
KH		 10424static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10425 struct kvm_memory_slot *slot)
10426{
10427 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10428 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10429}
10430
10431static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10432 struct kvm_memory_slot *slot)
10433{
10434 kvm_mmu_slot_set_dirty(kvm, slot);
10435}
10436
10437static void vmx_flush_log_dirty(struct kvm *kvm)
10438{
10439 kvm_flush_pml_buffers(kvm);
10440}
10441
10442static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10443 struct kvm_memory_slot *memslot,
10444 gfn_t offset, unsigned long mask)
10445{
10446 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10447}
10448
bf9f6ac8
FW		 10449/*
10450 * This routine does the following things for vCPU which is going
10451 * to be blocked if VT-d PI is enabled.
10452 * - Store the vCPU to the wakeup list, so when interrupts happen
10453 * we can find the right vCPU to wake up.
10454 * - Change the Posted-interrupt descriptor as below:
10455 * 'NDST' <-- vcpu->pre_pcpu
10456 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10457 * - If 'ON' is set during this process, which means at least one
10458 * interrupt is posted for this vCPU, we cannot block it, in
10459 * this case, return 1, otherwise, return 0.
10460 *
10461 */
10462static int vmx_pre_block(struct kvm_vcpu *vcpu)
10463{
10464 unsigned long flags;
10465 unsigned int dest;
10466 struct pi_desc old, new;
10467 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10468
10469 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10470 !irq_remapping_cap(IRQ_POSTING_CAP))
10471 return 0;
10472
10473 vcpu->pre_pcpu = vcpu->cpu;
10474 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10475 vcpu->pre_pcpu), flags);
10476 list_add_tail(&vcpu->blocked_vcpu_list,
10477 &per_cpu(blocked_vcpu_on_cpu,
10478 vcpu->pre_pcpu));
10479 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10480 vcpu->pre_pcpu), flags);
10481
10482 do {
10483 old.control = new.control = pi_desc->control;
10484
10485 /*
10486 * We should not block the vCPU if
10487 * an interrupt is posted for it.
10488 */
10489 if (pi_test_on(pi_desc) == 1) {
10490 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10491 vcpu->pre_pcpu), flags);
10492 list_del(&vcpu->blocked_vcpu_list);
10493 spin_unlock_irqrestore(
10494 &per_cpu(blocked_vcpu_on_cpu_lock,
10495 vcpu->pre_pcpu), flags);
10496 vcpu->pre_pcpu = -1;
10497
10498 return 1;
10499 }
10500
10501 WARN((pi_desc->sn == 1),
10502 "Warning: SN field of posted-interrupts "
10503 "is set before blocking\n");
10504
10505 /*
10506 * Since vCPU can be preempted during this process,
10507 * vcpu->cpu could be different with pre_pcpu, we
10508 * need to set pre_pcpu as the destination of wakeup
10509 * notification event, then we can find the right vCPU
10510 * to wakeup in wakeup handler if interrupts happen
10511 * when the vCPU is in blocked state.
10512 */
10513 dest = cpu_physical_id(vcpu->pre_pcpu);
10514
10515 if (x2apic_enabled())
10516 new.ndst = dest;
10517 else
10518 new.ndst = (dest << 8) & 0xFF00;
10519
10520 /* set 'NV' to 'wakeup vector' */
10521 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10522 } while (cmpxchg(&pi_desc->control, old.control,
10523 new.control) != old.control);
10524
10525 return 0;
10526}
10527
10528static void vmx_post_block(struct kvm_vcpu *vcpu)
10529{
10530 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10531 struct pi_desc old, new;
10532 unsigned int dest;
10533 unsigned long flags;
10534
10535 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10536 !irq_remapping_cap(IRQ_POSTING_CAP))
10537 return;
10538
10539 do {
10540 old.control = new.control = pi_desc->control;
10541
10542 dest = cpu_physical_id(vcpu->cpu);
10543
10544 if (x2apic_enabled())
10545 new.ndst = dest;
10546 else
10547 new.ndst = (dest << 8) & 0xFF00;
10548
10549 /* Allow posting non-urgent interrupts */
10550 new.sn = 0;
10551
10552 /* set 'NV' to 'notification vector' */
10553 new.nv = POSTED_INTR_VECTOR;
10554 } while (cmpxchg(&pi_desc->control, old.control,
10555 new.control) != old.control);
10556
10557 if(vcpu->pre_pcpu != -1) {
10558 spin_lock_irqsave(
10559 &per_cpu(blocked_vcpu_on_cpu_lock,
10560 vcpu->pre_pcpu), flags);
10561 list_del(&vcpu->blocked_vcpu_list);
10562 spin_unlock_irqrestore(
10563 &per_cpu(blocked_vcpu_on_cpu_lock,
10564 vcpu->pre_pcpu), flags);
10565 vcpu->pre_pcpu = -1;
10566 }
10567}
10568
efc64404
FW		 10569/*
10570 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10571 *
10572 * @kvm: kvm
10573 * @host_irq: host irq of the interrupt
10574 * @guest_irq: gsi of the interrupt
10575 * @set: set or unset PI
10576 * returns 0 on success, < 0 on failure
10577 */
10578static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10579 uint32_t guest_irq, bool set)
10580{
10581 struct kvm_kernel_irq_routing_entry *e;
10582 struct kvm_irq_routing_table *irq_rt;
10583 struct kvm_lapic_irq irq;
10584 struct kvm_vcpu *vcpu;
10585 struct vcpu_data vcpu_info;
10586 int idx, ret = -EINVAL;
10587
10588 if (!kvm_arch_has_assigned_device(kvm) ||
10589 !irq_remapping_cap(IRQ_POSTING_CAP))
10590 return 0;
10591
10592 idx = srcu_read_lock(&kvm->irq_srcu);
10593 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10594 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10595
10596 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10597 if (e->type != KVM_IRQ_ROUTING_MSI)
10598 continue;
10599 /*
10600 * VT-d PI cannot support posting multicast/broadcast
10601 * interrupts to a vCPU, we still use interrupt remapping
10602 * for these kind of interrupts.
10603 *
10604 * For lowest-priority interrupts, we only support
10605 * those with single CPU as the destination, e.g. user
10606 * configures the interrupts via /proc/irq or uses
10607 * irqbalance to make the interrupts single-CPU.
10608 *
10609 * We will support full lowest-priority interrupt later.
10610 */
10611
10612 kvm_set_msi_irq(e, &irq);
10613 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10614 continue;
10615
10616 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10617 vcpu_info.vector = irq.vector;
10618
10619 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10620 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10621
10622 if (set)
10623 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10624 else {
10625 /* suppress notification event before unposting */
10626 pi_set_sn(vcpu_to_pi_desc(vcpu));
10627 ret = irq_set_vcpu_affinity(host_irq, NULL);
10628 pi_clear_sn(vcpu_to_pi_desc(vcpu));
10629 }
10630
10631 if (ret < 0) {
10632 printk(KERN_INFO "%s: failed to update PI IRTE\n",
10633 __func__);
10634 goto out;
10635 }
10636 }
10637
10638 ret = 0;
10639out:
10640 srcu_read_unlock(&kvm->irq_srcu, idx);
10641 return ret;
10642}
10643
cbdd1bea 10644static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 10645 .cpu_has_kvm_support = cpu_has_kvm_support,
10646 .disabled_by_bios = vmx_disabled_by_bios,
10647 .hardware_setup = hardware_setup,
10648 .hardware_unsetup = hardware_unsetup,
002c7f7c 10649 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 10650 .hardware_enable = hardware_enable,
10651 .hardware_disable = hardware_disable,
04547156 10652 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 10653 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK		 10654
10655 .vcpu_create = vmx_create_vcpu,
10656 .vcpu_free = vmx_free_vcpu,
04d2cc77 10657 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 10658
04d2cc77 10659 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 10660 .vcpu_load = vmx_vcpu_load,
10661 .vcpu_put = vmx_vcpu_put,
10662
c8639010 10663 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 10664 .get_msr = vmx_get_msr,
10665 .set_msr = vmx_set_msr,
10666 .get_segment_base = vmx_get_segment_base,
10667 .get_segment = vmx_get_segment,
10668 .set_segment = vmx_set_segment,
2e4d2653 10669 .get_cpl = vmx_get_cpl,
6aa8b732 10670 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 10671 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 10672 .decache_cr3 = vmx_decache_cr3,
25c4c276 10673 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 10674 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 10675 .set_cr3 = vmx_set_cr3,
10676 .set_cr4 = vmx_set_cr4,
6aa8b732 10677 .set_efer = vmx_set_efer,
6aa8b732
AK		 10678 .get_idt = vmx_get_idt,
10679 .set_idt = vmx_set_idt,
10680 .get_gdt = vmx_get_gdt,
10681 .set_gdt = vmx_set_gdt,
73aaf249
JK		 10682 .get_dr6 = vmx_get_dr6,
10683 .set_dr6 = vmx_set_dr6,
020df079 10684 .set_dr7 = vmx_set_dr7,
81908bf4 10685 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 10686 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 10687 .get_rflags = vmx_get_rflags,
10688 .set_rflags = vmx_set_rflags,
0fdd74f7 10689 .fpu_activate = vmx_fpu_activate,
02daab21 10690 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 10691
10692 .tlb_flush = vmx_flush_tlb,
6aa8b732 10693
6aa8b732 10694 .run = vmx_vcpu_run,
6062d012 10695 .handle_exit = vmx_handle_exit,
6aa8b732 10696 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 10697 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10698 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 10699 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 10700 .set_irq = vmx_inject_irq,
95ba8273 10701 .set_nmi = vmx_inject_nmi,
298101da 10702 .queue_exception = vmx_queue_exception,
b463a6f7 10703 .cancel_injection = vmx_cancel_injection,
78646121 10704 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 10705 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 10706 .get_nmi_mask = vmx_get_nmi_mask,
10707 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 10708 .enable_nmi_window = enable_nmi_window,
10709 .enable_irq_window = enable_irq_window,
10710 .update_cr8_intercept = update_cr8_intercept,
8d14695f 10711 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 10712 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d50ab6c1 10713 .cpu_uses_apicv = vmx_cpu_uses_apicv,
c7c9c56c
YZ		 10714 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10715 .hwapic_irr_update = vmx_hwapic_irr_update,
10716 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 10717 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10718 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 10719
cbc94022 10720 .set_tss_addr = vmx_set_tss_addr,
67253af5 10721 .get_tdp_level = get_ept_level,
4b12f0de 10722 .get_mt_mask = vmx_get_mt_mask,
229456fc 10723
586f9607 10724 .get_exit_info = vmx_get_exit_info,
586f9607 10725
17cc3935 10726 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 10727
10728 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 10729
10730 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 10731 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 10732
10733 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 10734
10735 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 10736
4051b188 10737 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 10738 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 10739 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 10740 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 10741 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 10742 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 10743
10744 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 10745
10746 .check_intercept = vmx_check_intercept,
a547c6db 10747 .handle_external_intr = vmx_handle_external_intr,
da8999d3 10748 .mpx_supported = vmx_mpx_supported,
55412b2e 10749 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 10750
10751 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 10752
10753 .sched_in = vmx_sched_in,
843e4330
KH		 10754
10755 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10756 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10757 .flush_log_dirty = vmx_flush_log_dirty,
10758 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
25462f7f 10759
bf9f6ac8
FW		 10760 .pre_block = vmx_pre_block,
10761 .post_block = vmx_post_block,
10762
25462f7f 10763 .pmu_ops = &intel_pmu_ops,
efc64404
FW		 10764
10765 .update_pi_irte = vmx_update_pi_irte,
6aa8b732
AK		 10766};
10767
10768static int __init vmx_init(void)
10769{
34a1cd60
TC		 10770 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10771 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 10772 if (r)
34a1cd60 10773 return r;
25c5f225 10774
2965faa5 10775#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 10776 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10777 crash_vmclear_local_loaded_vmcss);
10778#endif
10779
fdef3ad1 10780 return 0;
6aa8b732
AK		 10781}
10782
10783static void __exit vmx_exit(void)
10784{
2965faa5 10785#ifdef CONFIG_KEXEC_CORE
3b63a43f 10786 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10787 synchronize_rcu();
10788#endif
10789
cb498ea2 10790 kvm_exit();
6aa8b732
AK		 10791}
10792
10793module_init(vmx_init)
10794module_exit(vmx_exit)
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