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KVM: VMX: drop rdtscp_enabled check in prepare_vmcs02()
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
af658dca 31#include <linux/trace_events.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
952f07ec 43#include <asm/fpu/internal.h>
d7cd9796 44#include <asm/perf_event.h>
81908bf4 45#include <asm/debugreg.h>
8f536b76 46#include <asm/kexec.h>
dab2087d 47#include <asm/apic.h>
6aa8b732 48
229456fc 49#include "trace.h"
25462f7f 50#include "pmu.h"
229456fc 51
4ecac3fd 52#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 53#define __ex_clear(x, reg) \
54 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 55
6aa8b732
AK		 56MODULE_AUTHOR("Qumranet");
57MODULE_LICENSE("GPL");
58
e9bda3b3
JT		 59static const struct x86_cpu_id vmx_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_VMX),
61 {}
62};
63MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
64
476bc001 65static bool __read_mostly enable_vpid = 1;
736caefe 66module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 67
476bc001 68static bool __read_mostly flexpriority_enabled = 1;
736caefe 69module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 70
476bc001 71static bool __read_mostly enable_ept = 1;
736caefe 72module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 73
476bc001 74static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 75module_param_named(unrestricted_guest,
76 enable_unrestricted_guest, bool, S_IRUGO);
77
83c3a331
XH		 78static bool __read_mostly enable_ept_ad_bits = 1;
79module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
80
a27685c3 81static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 82module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 83
476bc001 84static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 85module_param(vmm_exclusive, bool, S_IRUGO);
86
476bc001 87static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 88module_param(fasteoi, bool, S_IRUGO);
89
5a71785d 90static bool __read_mostly enable_apicv = 1;
01e439be 91module_param(enable_apicv, bool, S_IRUGO);
83d4c286 92
abc4fc58
AG		 93static bool __read_mostly enable_shadow_vmcs = 1;
94module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 95/*
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
99 */
476bc001 100static bool __read_mostly nested = 0;
801d3424
NHE		 101module_param(nested, bool, S_IRUGO);
102
20300099
WL		 103static u64 __read_mostly host_xss;
104
843e4330
KH		 105static bool __read_mostly enable_pml = 1;
106module_param_named(pml, enable_pml, bool, S_IRUGO);
107
5037878e
GN		 108#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 110#define KVM_VM_CR0_ALWAYS_ON \
111 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 112#define KVM_CR4_GUEST_OWNED_BITS \
113 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 114 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 115
cdc0e244
AK		 116#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
118
78ac8b47
AK		 119#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
120
f4124500
JK		 121#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
122
4b8d54f9
ZE		 123/*
124 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125 * ple_gap: upper bound on the amount of time between two successive
126 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 127 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 128 * ple_window: upper bound on the amount of time a guest is allowed to execute
129 * in a PAUSE loop. Tests indicate that most spinlocks are held for
130 * less than 2^12 cycles
131 * Time is measured based on a counter that runs at the same rate as the TSC,
132 * refer SDM volume 3b section 21.6.13 & 22.1.3.
133 */
b4a2d31d
RK		 134#define KVM_VMX_DEFAULT_PLE_GAP 128
135#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
136#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
137#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
139 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
140
4b8d54f9
ZE		 141static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
142module_param(ple_gap, int, S_IRUGO);
143
144static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
145module_param(ple_window, int, S_IRUGO);
146
b4a2d31d
RK		 147/* Default doubles per-vcpu window every exit. */
148static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
149module_param(ple_window_grow, int, S_IRUGO);
150
151/* Default resets per-vcpu window every exit to ple_window. */
152static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
153module_param(ple_window_shrink, int, S_IRUGO);
154
155/* Default is to compute the maximum so we can never overflow. */
156static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
158module_param(ple_window_max, int, S_IRUGO);
159
83287ea4
AK		 160extern const ulong vmx_return;
161
8bf00a52 162#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 163#define VMCS02_POOL_SIZE 1
61d2ef2c 164
a2fa3e9f
GH		 165struct vmcs {
166 u32 revision_id;
167 u32 abort;
168 char data[0];
169};
170
d462b819
NHE		 171/*
172 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174 * loaded on this CPU (so we can clear them if the CPU goes down).
175 */
176struct loaded_vmcs {
177 struct vmcs *vmcs;
178 int cpu;
179 int launched;
180 struct list_head loaded_vmcss_on_cpu_link;
181};
182
26bb0981
AK		 183struct shared_msr_entry {
184 unsigned index;
185 u64 data;
d5696725 186 u64 mask;
26bb0981
AK		 187};
188
a9d30f33
NHE		 189/*
190 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195 * More than one of these structures may exist, if L1 runs multiple L2 guests.
196 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197 * underlying hardware which will be used to run L2.
198 * This structure is packed to ensure that its layout is identical across
199 * machines (necessary for live migration).
200 * If there are changes in this struct, VMCS12_REVISION must be changed.
201 */
22bd0358 202typedef u64 natural_width;
a9d30f33
NHE		 203struct __packed vmcs12 {
204 /* According to the Intel spec, a VMCS region must start with the
205 * following two fields. Then follow implementation-specific data.
206 */
207 u32 revision_id;
208 u32 abort;
22bd0358 209
27d6c865
NHE		 210 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211 u32 padding[7]; /* room for future expansion */
212
22bd0358
NHE		 213 u64 io_bitmap_a;
214 u64 io_bitmap_b;
215 u64 msr_bitmap;
216 u64 vm_exit_msr_store_addr;
217 u64 vm_exit_msr_load_addr;
218 u64 vm_entry_msr_load_addr;
219 u64 tsc_offset;
220 u64 virtual_apic_page_addr;
221 u64 apic_access_addr;
705699a1 222 u64 posted_intr_desc_addr;
22bd0358 223 u64 ept_pointer;
608406e2
WV		 224 u64 eoi_exit_bitmap0;
225 u64 eoi_exit_bitmap1;
226 u64 eoi_exit_bitmap2;
227 u64 eoi_exit_bitmap3;
81dc01f7 228 u64 xss_exit_bitmap;
22bd0358
NHE		 229 u64 guest_physical_address;
230 u64 vmcs_link_pointer;
231 u64 guest_ia32_debugctl;
232 u64 guest_ia32_pat;
233 u64 guest_ia32_efer;
234 u64 guest_ia32_perf_global_ctrl;
235 u64 guest_pdptr0;
236 u64 guest_pdptr1;
237 u64 guest_pdptr2;
238 u64 guest_pdptr3;
36be0b9d 239 u64 guest_bndcfgs;
22bd0358
NHE		 240 u64 host_ia32_pat;
241 u64 host_ia32_efer;
242 u64 host_ia32_perf_global_ctrl;
243 u64 padding64[8]; /* room for future expansion */
244 /*
245 * To allow migration of L1 (complete with its L2 guests) between
246 * machines of different natural widths (32 or 64 bit), we cannot have
247 * unsigned long fields with no explict size. We use u64 (aliased
248 * natural_width) instead. Luckily, x86 is little-endian.
249 */
250 natural_width cr0_guest_host_mask;
251 natural_width cr4_guest_host_mask;
252 natural_width cr0_read_shadow;
253 natural_width cr4_read_shadow;
254 natural_width cr3_target_value0;
255 natural_width cr3_target_value1;
256 natural_width cr3_target_value2;
257 natural_width cr3_target_value3;
258 natural_width exit_qualification;
259 natural_width guest_linear_address;
260 natural_width guest_cr0;
261 natural_width guest_cr3;
262 natural_width guest_cr4;
263 natural_width guest_es_base;
264 natural_width guest_cs_base;
265 natural_width guest_ss_base;
266 natural_width guest_ds_base;
267 natural_width guest_fs_base;
268 natural_width guest_gs_base;
269 natural_width guest_ldtr_base;
270 natural_width guest_tr_base;
271 natural_width guest_gdtr_base;
272 natural_width guest_idtr_base;
273 natural_width guest_dr7;
274 natural_width guest_rsp;
275 natural_width guest_rip;
276 natural_width guest_rflags;
277 natural_width guest_pending_dbg_exceptions;
278 natural_width guest_sysenter_esp;
279 natural_width guest_sysenter_eip;
280 natural_width host_cr0;
281 natural_width host_cr3;
282 natural_width host_cr4;
283 natural_width host_fs_base;
284 natural_width host_gs_base;
285 natural_width host_tr_base;
286 natural_width host_gdtr_base;
287 natural_width host_idtr_base;
288 natural_width host_ia32_sysenter_esp;
289 natural_width host_ia32_sysenter_eip;
290 natural_width host_rsp;
291 natural_width host_rip;
292 natural_width paddingl[8]; /* room for future expansion */
293 u32 pin_based_vm_exec_control;
294 u32 cpu_based_vm_exec_control;
295 u32 exception_bitmap;
296 u32 page_fault_error_code_mask;
297 u32 page_fault_error_code_match;
298 u32 cr3_target_count;
299 u32 vm_exit_controls;
300 u32 vm_exit_msr_store_count;
301 u32 vm_exit_msr_load_count;
302 u32 vm_entry_controls;
303 u32 vm_entry_msr_load_count;
304 u32 vm_entry_intr_info_field;
305 u32 vm_entry_exception_error_code;
306 u32 vm_entry_instruction_len;
307 u32 tpr_threshold;
308 u32 secondary_vm_exec_control;
309 u32 vm_instruction_error;
310 u32 vm_exit_reason;
311 u32 vm_exit_intr_info;
312 u32 vm_exit_intr_error_code;
313 u32 idt_vectoring_info_field;
314 u32 idt_vectoring_error_code;
315 u32 vm_exit_instruction_len;
316 u32 vmx_instruction_info;
317 u32 guest_es_limit;
318 u32 guest_cs_limit;
319 u32 guest_ss_limit;
320 u32 guest_ds_limit;
321 u32 guest_fs_limit;
322 u32 guest_gs_limit;
323 u32 guest_ldtr_limit;
324 u32 guest_tr_limit;
325 u32 guest_gdtr_limit;
326 u32 guest_idtr_limit;
327 u32 guest_es_ar_bytes;
328 u32 guest_cs_ar_bytes;
329 u32 guest_ss_ar_bytes;
330 u32 guest_ds_ar_bytes;
331 u32 guest_fs_ar_bytes;
332 u32 guest_gs_ar_bytes;
333 u32 guest_ldtr_ar_bytes;
334 u32 guest_tr_ar_bytes;
335 u32 guest_interruptibility_info;
336 u32 guest_activity_state;
337 u32 guest_sysenter_cs;
338 u32 host_ia32_sysenter_cs;
0238ea91
JK		 339 u32 vmx_preemption_timer_value;
340 u32 padding32[7]; /* room for future expansion */
22bd0358 341 u16 virtual_processor_id;
705699a1 342 u16 posted_intr_nv;
22bd0358
NHE		 343 u16 guest_es_selector;
344 u16 guest_cs_selector;
345 u16 guest_ss_selector;
346 u16 guest_ds_selector;
347 u16 guest_fs_selector;
348 u16 guest_gs_selector;
349 u16 guest_ldtr_selector;
350 u16 guest_tr_selector;
608406e2 351 u16 guest_intr_status;
22bd0358
NHE		 352 u16 host_es_selector;
353 u16 host_cs_selector;
354 u16 host_ss_selector;
355 u16 host_ds_selector;
356 u16 host_fs_selector;
357 u16 host_gs_selector;
358 u16 host_tr_selector;
a9d30f33
NHE		 359};
360
361/*
362 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
365 */
366#define VMCS12_REVISION 0x11e57ed0
367
368/*
369 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371 * current implementation, 4K are reserved to avoid future complications.
372 */
373#define VMCS12_SIZE 0x1000
374
ff2f6fe9
NHE		 375/* Used to remember the last vmcs02 used for some recently used vmcs12s */
376struct vmcs02_list {
377 struct list_head list;
378 gpa_t vmptr;
379 struct loaded_vmcs vmcs02;
380};
381
ec378aee
NHE		 382/*
383 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
385 */
386struct nested_vmx {
387 /* Has the level1 guest done vmxon? */
388 bool vmxon;
3573e22c 389 gpa_t vmxon_ptr;
a9d30f33
NHE		 390
391 /* The guest-physical address of the current VMCS L1 keeps for L2 */
392 gpa_t current_vmptr;
393 /* The host-usable pointer to the above */
394 struct page *current_vmcs12_page;
395 struct vmcs12 *current_vmcs12;
8de48833 396 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 397 /*
398 * Indicates if the shadow vmcs must be updated with the
399 * data hold by vmcs12
400 */
401 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 402
403 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404 struct list_head vmcs02_pool;
405 int vmcs02_num;
fe3ef05c 406 u64 vmcs01_tsc_offset;
644d711a
NHE		 407 /* L2 must run next, and mustn't decide to exit to L1. */
408 bool nested_run_pending;
fe3ef05c
NHE		 409 /*
410 * Guest pages referred to in vmcs02 with host-physical pointers, so
411 * we must keep them pinned while L2 runs.
412 */
413 struct page *apic_access_page;
a7c0b07d 414 struct page *virtual_apic_page;
705699a1
WV		 415 struct page *pi_desc_page;
416 struct pi_desc *pi_desc;
417 bool pi_pending;
418 u16 posted_intr_nv;
b3897a49 419 u64 msr_ia32_feature_control;
f4124500
JK		 420
421 struct hrtimer preemption_timer;
422 bool preemption_timer_expired;
2996fca0
JK		 423
424 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
425 u64 vmcs01_debugctl;
b9c237bb
WV		 426
427 u32 nested_vmx_procbased_ctls_low;
428 u32 nested_vmx_procbased_ctls_high;
429 u32 nested_vmx_true_procbased_ctls_low;
430 u32 nested_vmx_secondary_ctls_low;
431 u32 nested_vmx_secondary_ctls_high;
432 u32 nested_vmx_pinbased_ctls_low;
433 u32 nested_vmx_pinbased_ctls_high;
434 u32 nested_vmx_exit_ctls_low;
435 u32 nested_vmx_exit_ctls_high;
436 u32 nested_vmx_true_exit_ctls_low;
437 u32 nested_vmx_entry_ctls_low;
438 u32 nested_vmx_entry_ctls_high;
439 u32 nested_vmx_true_entry_ctls_low;
440 u32 nested_vmx_misc_low;
441 u32 nested_vmx_misc_high;
442 u32 nested_vmx_ept_caps;
ec378aee
NHE		 443};
444
01e439be
YZ		 445#define POSTED_INTR_ON 0
446/* Posted-Interrupt Descriptor */
447struct pi_desc {
448 u32 pir[8]; /* Posted interrupt requested */
449 u32 control; /* bit 0 of control is outstanding notification bit */
450 u32 rsvd[7];
451} __aligned(64);
452
a20ed54d
YZ		 453static bool pi_test_and_set_on(struct pi_desc *pi_desc)
454{
455 return test_and_set_bit(POSTED_INTR_ON,
456 (unsigned long *)&pi_desc->control);
457}
458
459static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
460{
461 return test_and_clear_bit(POSTED_INTR_ON,
462 (unsigned long *)&pi_desc->control);
463}
464
465static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
466{
467 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
468}
469
a2fa3e9f 470struct vcpu_vmx {
fb3f0f51 471 struct kvm_vcpu vcpu;
313dbd49 472 unsigned long host_rsp;
29bd8a78 473 u8 fail;
9d58b931 474 bool nmi_known_unmasked;
51aa01d1 475 u32 exit_intr_info;
1155f76a 476 u32 idt_vectoring_info;
6de12732 477 ulong rflags;
26bb0981 478 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 479 int nmsrs;
480 int save_nmsrs;
a547c6db 481 unsigned long host_idt_base;
a2fa3e9f 482#ifdef CONFIG_X86_64
44ea2b17
AK		 483 u64 msr_host_kernel_gs_base;
484 u64 msr_guest_kernel_gs_base;
a2fa3e9f 485#endif
2961e876
GN		 486 u32 vm_entry_controls_shadow;
487 u32 vm_exit_controls_shadow;
d462b819
NHE		 488 /*
489 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
490 * non-nested (L1) guest, it always points to vmcs01. For a nested
491 * guest (L2), it points to a different VMCS.
492 */
493 struct loaded_vmcs vmcs01;
494 struct loaded_vmcs *loaded_vmcs;
495 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 496 struct msr_autoload {
497 unsigned nr;
498 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
499 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
500 } msr_autoload;
a2fa3e9f
GH		 501 struct {
502 int loaded;
503 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 504#ifdef CONFIG_X86_64
505 u16 ds_sel, es_sel;
506#endif
152d3f2f
LV		 507 int gs_ldt_reload_needed;
508 int fs_reload_needed;
da8999d3 509 u64 msr_host_bndcfgs;
d974baa3 510 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 511 } host_state;
9c8cba37 512 struct {
7ffd92c5 513 int vm86_active;
78ac8b47 514 ulong save_rflags;
f5f7b2fe
AK		 515 struct kvm_segment segs[8];
516 } rmode;
517 struct {
518 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 519 struct kvm_save_segment {
520 u16 selector;
521 unsigned long base;
522 u32 limit;
523 u32 ar;
f5f7b2fe 524 } seg[8];
2fb92db1 525 } segment_cache;
2384d2b3 526 int vpid;
04fa4d32 527 bool emulation_required;
3b86cd99
JK		 528
529 /* Support for vnmi-less CPUs */
530 int soft_vnmi_blocked;
531 ktime_t entry_time;
532 s64 vnmi_blocked_time;
a0861c02 533 u32 exit_reason;
4e47c7a6
SY		 534
535 bool rdtscp_enabled;
ec378aee 536
01e439be
YZ		 537 /* Posted interrupt descriptor */
538 struct pi_desc pi_desc;
539
ec378aee
NHE		 540 /* Support for a guest hypervisor (nested VMX) */
541 struct nested_vmx nested;
a7653ecd
RK		 542
543 /* Dynamic PLE window. */
544 int ple_window;
545 bool ple_window_dirty;
843e4330
KH		 546
547 /* Support for PML */
548#define PML_ENTITY_NUM 512
549 struct page *pml_pg;
a2fa3e9f
GH		 550};
551
2fb92db1
AK		 552enum segment_cache_field {
553 SEG_FIELD_SEL = 0,
554 SEG_FIELD_BASE = 1,
555 SEG_FIELD_LIMIT = 2,
556 SEG_FIELD_AR = 3,
557
558 SEG_FIELD_NR = 4
559};
560
a2fa3e9f
GH		 561static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
562{
fb3f0f51 563 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 564}
565
22bd0358
NHE		 566#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
567#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
568#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
569 [number##_HIGH] = VMCS12_OFFSET(name)+4
570
4607c2d7 571
fe2b201b 572static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 573 /*
574 * We do NOT shadow fields that are modified when L0
575 * traps and emulates any vmx instruction (e.g. VMPTRLD,
576 * VMXON...) executed by L1.
577 * For example, VM_INSTRUCTION_ERROR is read
578 * by L1 if a vmx instruction fails (part of the error path).
579 * Note the code assumes this logic. If for some reason
580 * we start shadowing these fields then we need to
581 * force a shadow sync when L0 emulates vmx instructions
582 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
583 * by nested_vmx_failValid)
584 */
585 VM_EXIT_REASON,
586 VM_EXIT_INTR_INFO,
587 VM_EXIT_INSTRUCTION_LEN,
588 IDT_VECTORING_INFO_FIELD,
589 IDT_VECTORING_ERROR_CODE,
590 VM_EXIT_INTR_ERROR_CODE,
591 EXIT_QUALIFICATION,
592 GUEST_LINEAR_ADDRESS,
593 GUEST_PHYSICAL_ADDRESS
594};
fe2b201b 595static int max_shadow_read_only_fields =
4607c2d7
AG		 596 ARRAY_SIZE(shadow_read_only_fields);
597
fe2b201b 598static unsigned long shadow_read_write_fields[] = {
a7c0b07d 599 TPR_THRESHOLD,
4607c2d7
AG		 600 GUEST_RIP,
601 GUEST_RSP,
602 GUEST_CR0,
603 GUEST_CR3,
604 GUEST_CR4,
605 GUEST_INTERRUPTIBILITY_INFO,
606 GUEST_RFLAGS,
607 GUEST_CS_SELECTOR,
608 GUEST_CS_AR_BYTES,
609 GUEST_CS_LIMIT,
610 GUEST_CS_BASE,
611 GUEST_ES_BASE,
36be0b9d 612 GUEST_BNDCFGS,
4607c2d7
AG		 613 CR0_GUEST_HOST_MASK,
614 CR0_READ_SHADOW,
615 CR4_READ_SHADOW,
616 TSC_OFFSET,
617 EXCEPTION_BITMAP,
618 CPU_BASED_VM_EXEC_CONTROL,
619 VM_ENTRY_EXCEPTION_ERROR_CODE,
620 VM_ENTRY_INTR_INFO_FIELD,
621 VM_ENTRY_INSTRUCTION_LEN,
622 VM_ENTRY_EXCEPTION_ERROR_CODE,
623 HOST_FS_BASE,
624 HOST_GS_BASE,
625 HOST_FS_SELECTOR,
626 HOST_GS_SELECTOR
627};
fe2b201b 628static int max_shadow_read_write_fields =
4607c2d7
AG		 629 ARRAY_SIZE(shadow_read_write_fields);
630
772e0318 631static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 632 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 633 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE		 634 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
635 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
636 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
637 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
638 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
639 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
640 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
641 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 642 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 643 FIELD(HOST_ES_SELECTOR, host_es_selector),
644 FIELD(HOST_CS_SELECTOR, host_cs_selector),
645 FIELD(HOST_SS_SELECTOR, host_ss_selector),
646 FIELD(HOST_DS_SELECTOR, host_ds_selector),
647 FIELD(HOST_FS_SELECTOR, host_fs_selector),
648 FIELD(HOST_GS_SELECTOR, host_gs_selector),
649 FIELD(HOST_TR_SELECTOR, host_tr_selector),
650 FIELD64(IO_BITMAP_A, io_bitmap_a),
651 FIELD64(IO_BITMAP_B, io_bitmap_b),
652 FIELD64(MSR_BITMAP, msr_bitmap),
653 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
654 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
655 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
656 FIELD64(TSC_OFFSET, tsc_offset),
657 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
658 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 659 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 660 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 661 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
662 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
663 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
664 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 665 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 666 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
667 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
668 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
669 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
670 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
671 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
672 FIELD64(GUEST_PDPTR0, guest_pdptr0),
673 FIELD64(GUEST_PDPTR1, guest_pdptr1),
674 FIELD64(GUEST_PDPTR2, guest_pdptr2),
675 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 676 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 677 FIELD64(HOST_IA32_PAT, host_ia32_pat),
678 FIELD64(HOST_IA32_EFER, host_ia32_efer),
679 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
680 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
681 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
682 FIELD(EXCEPTION_BITMAP, exception_bitmap),
683 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
684 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
685 FIELD(CR3_TARGET_COUNT, cr3_target_count),
686 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
687 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
688 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
689 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
690 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
691 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
692 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
693 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
694 FIELD(TPR_THRESHOLD, tpr_threshold),
695 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
696 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
697 FIELD(VM_EXIT_REASON, vm_exit_reason),
698 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
699 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
700 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
701 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
702 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
703 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
704 FIELD(GUEST_ES_LIMIT, guest_es_limit),
705 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
706 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
707 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
708 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
709 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
710 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
711 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
712 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
713 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
714 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
715 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
716 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
717 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
718 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
719 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
720 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
721 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
722 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
723 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
724 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
725 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 726 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 727 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
728 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
729 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
730 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
731 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
732 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
733 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
734 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
735 FIELD(EXIT_QUALIFICATION, exit_qualification),
736 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
737 FIELD(GUEST_CR0, guest_cr0),
738 FIELD(GUEST_CR3, guest_cr3),
739 FIELD(GUEST_CR4, guest_cr4),
740 FIELD(GUEST_ES_BASE, guest_es_base),
741 FIELD(GUEST_CS_BASE, guest_cs_base),
742 FIELD(GUEST_SS_BASE, guest_ss_base),
743 FIELD(GUEST_DS_BASE, guest_ds_base),
744 FIELD(GUEST_FS_BASE, guest_fs_base),
745 FIELD(GUEST_GS_BASE, guest_gs_base),
746 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
747 FIELD(GUEST_TR_BASE, guest_tr_base),
748 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
749 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
750 FIELD(GUEST_DR7, guest_dr7),
751 FIELD(GUEST_RSP, guest_rsp),
752 FIELD(GUEST_RIP, guest_rip),
753 FIELD(GUEST_RFLAGS, guest_rflags),
754 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
755 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
756 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
757 FIELD(HOST_CR0, host_cr0),
758 FIELD(HOST_CR3, host_cr3),
759 FIELD(HOST_CR4, host_cr4),
760 FIELD(HOST_FS_BASE, host_fs_base),
761 FIELD(HOST_GS_BASE, host_gs_base),
762 FIELD(HOST_TR_BASE, host_tr_base),
763 FIELD(HOST_GDTR_BASE, host_gdtr_base),
764 FIELD(HOST_IDTR_BASE, host_idtr_base),
765 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
766 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
767 FIELD(HOST_RSP, host_rsp),
768 FIELD(HOST_RIP, host_rip),
769};
22bd0358
NHE		 770
771static inline short vmcs_field_to_offset(unsigned long field)
772{
a2ae9df7
PB		 773 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
774
775 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
776 vmcs_field_to_offset_table[field] == 0)
777 return -ENOENT;
778
22bd0358
NHE		 779 return vmcs_field_to_offset_table[field];
780}
781
a9d30f33
NHE		 782static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
783{
784 return to_vmx(vcpu)->nested.current_vmcs12;
785}
786
787static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
788{
54bf36aa 789 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 790 if (is_error_page(page))
a9d30f33 791 return NULL;
32cad84f 792
a9d30f33
NHE		 793 return page;
794}
795
796static void nested_release_page(struct page *page)
797{
798 kvm_release_page_dirty(page);
799}
800
801static void nested_release_page_clean(struct page *page)
802{
803 kvm_release_page_clean(page);
804}
805
bfd0a56b 806static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 807static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 808static void kvm_cpu_vmxon(u64 addr);
809static void kvm_cpu_vmxoff(void);
93c4adc7 810static bool vmx_mpx_supported(void);
f53cd63c 811static bool vmx_xsaves_supported(void);
d50ab6c1 812static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
776e58ea 813static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 814static void vmx_set_segment(struct kvm_vcpu *vcpu,
815 struct kvm_segment *var, int seg);
816static void vmx_get_segment(struct kvm_vcpu *vcpu,
817 struct kvm_segment *var, int seg);
d99e4152
GN		 818static bool guest_state_valid(struct kvm_vcpu *vcpu);
819static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 820static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 821static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 822static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 823static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 824
6aa8b732
AK		 825static DEFINE_PER_CPU(struct vmcs *, vmxarea);
826static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 827/*
828 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
829 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
830 */
831static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 832static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 833
3e7c73e9
AK		 834static unsigned long *vmx_io_bitmap_a;
835static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 836static unsigned long *vmx_msr_bitmap_legacy;
837static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 838static unsigned long *vmx_msr_bitmap_legacy_x2apic;
839static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 840static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 841static unsigned long *vmx_vmread_bitmap;
842static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 843
110312c8 844static bool cpu_has_load_ia32_efer;
8bf00a52 845static bool cpu_has_load_perf_global_ctrl;
110312c8 846
2384d2b3
SY		 847static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
848static DEFINE_SPINLOCK(vmx_vpid_lock);
849
1c3d14fe 850static struct vmcs_config {
6aa8b732
AK		 851 int size;
852 int order;
853 u32 revision_id;
1c3d14fe
YS		 854 u32 pin_based_exec_ctrl;
855 u32 cpu_based_exec_ctrl;
f78e0e2e 856 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 857 u32 vmexit_ctrl;
858 u32 vmentry_ctrl;
859} vmcs_config;
6aa8b732 860
efff9e53 861static struct vmx_capability {
d56f546d
SY		 862 u32 ept;
863 u32 vpid;
864} vmx_capability;
865
6aa8b732
AK		 866#define VMX_SEGMENT_FIELD(seg) \
867 [VCPU_SREG_##seg] = { \
868 .selector = GUEST_##seg##_SELECTOR, \
869 .base = GUEST_##seg##_BASE, \
870 .limit = GUEST_##seg##_LIMIT, \
871 .ar_bytes = GUEST_##seg##_AR_BYTES, \
872 }
873
772e0318 874static const struct kvm_vmx_segment_field {
6aa8b732
AK		 875 unsigned selector;
876 unsigned base;
877 unsigned limit;
878 unsigned ar_bytes;
879} kvm_vmx_segment_fields[] = {
880 VMX_SEGMENT_FIELD(CS),
881 VMX_SEGMENT_FIELD(DS),
882 VMX_SEGMENT_FIELD(ES),
883 VMX_SEGMENT_FIELD(FS),
884 VMX_SEGMENT_FIELD(GS),
885 VMX_SEGMENT_FIELD(SS),
886 VMX_SEGMENT_FIELD(TR),
887 VMX_SEGMENT_FIELD(LDTR),
888};
889
26bb0981
AK		 890static u64 host_efer;
891
6de4f3ad
AK		 892static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
893
4d56c8a7 894/*
8c06585d 895 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 896 * away by decrementing the array size.
897 */
6aa8b732 898static const u32 vmx_msr_index[] = {
05b3e0c2 899#ifdef CONFIG_X86_64
44ea2b17 900 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 901#endif
8c06585d 902 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 903};
6aa8b732 904
31299944 905static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 906{
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
908 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 909 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 910}
911
31299944 912static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 913{
914 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
915 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 916 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 917}
918
31299944 919static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 920{
921 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
922 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 923 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 924}
925
31299944 926static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 927{
928 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
929 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
930}
931
31299944 932static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 933{
934 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
935 INTR_INFO_VALID_MASK)) ==
936 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
937}
938
31299944 939static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 940{
04547156 941 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 942}
943
31299944 944static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 945{
04547156 946 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 947}
948
35754c98 949static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 950{
35754c98 951 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS		 952}
953
31299944 954static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 955{
04547156
SY		 956 return vmcs_config.cpu_based_exec_ctrl &
957 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 958}
959
774ead3a 960static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 961{
04547156
SY		 962 return vmcs_config.cpu_based_2nd_exec_ctrl &
963 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
964}
965
8d14695f
YZ		 966static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
967{
968 return vmcs_config.cpu_based_2nd_exec_ctrl &
969 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
970}
971
83d4c286
YZ		 972static inline bool cpu_has_vmx_apic_register_virt(void)
973{
974 return vmcs_config.cpu_based_2nd_exec_ctrl &
975 SECONDARY_EXEC_APIC_REGISTER_VIRT;
976}
977
c7c9c56c
YZ		 978static inline bool cpu_has_vmx_virtual_intr_delivery(void)
979{
980 return vmcs_config.cpu_based_2nd_exec_ctrl &
981 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
982}
983
01e439be
YZ		 984static inline bool cpu_has_vmx_posted_intr(void)
985{
d6a858d1
PB		 986 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
987 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ		 988}
989
990static inline bool cpu_has_vmx_apicv(void)
991{
992 return cpu_has_vmx_apic_register_virt() &&
993 cpu_has_vmx_virtual_intr_delivery() &&
994 cpu_has_vmx_posted_intr();
995}
996
04547156
SY		 997static inline bool cpu_has_vmx_flexpriority(void)
998{
999 return cpu_has_vmx_tpr_shadow() &&
1000 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 1001}
1002
e799794e
MT		 1003static inline bool cpu_has_vmx_ept_execute_only(void)
1004{
31299944 1005 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 1006}
1007
e799794e
MT		 1008static inline bool cpu_has_vmx_ept_2m_page(void)
1009{
31299944 1010 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1011}
1012
878403b7
SY		 1013static inline bool cpu_has_vmx_ept_1g_page(void)
1014{
31299944 1015 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1016}
1017
4bc9b982
SY		 1018static inline bool cpu_has_vmx_ept_4levels(void)
1019{
1020 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1021}
1022
83c3a331
XH		 1023static inline bool cpu_has_vmx_ept_ad_bits(void)
1024{
1025 return vmx_capability.ept & VMX_EPT_AD_BIT;
1026}
1027
31299944 1028static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1029{
31299944 1030 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1031}
1032
31299944 1033static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1034{
31299944 1035 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1036}
1037
518c8aee
GJ		 1038static inline bool cpu_has_vmx_invvpid_single(void)
1039{
1040 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1041}
1042
b9d762fa
GJ		 1043static inline bool cpu_has_vmx_invvpid_global(void)
1044{
1045 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1046}
1047
31299944 1048static inline bool cpu_has_vmx_ept(void)
d56f546d 1049{
04547156
SY		 1050 return vmcs_config.cpu_based_2nd_exec_ctrl &
1051 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1052}
1053
31299944 1054static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1055{
1056 return vmcs_config.cpu_based_2nd_exec_ctrl &
1057 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1058}
1059
31299944 1060static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1061{
1062 return vmcs_config.cpu_based_2nd_exec_ctrl &
1063 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1064}
1065
35754c98 1066static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1067{
35754c98 1068 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 1069}
1070
31299944 1071static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1072{
04547156
SY		 1073 return vmcs_config.cpu_based_2nd_exec_ctrl &
1074 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1075}
1076
31299944 1077static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1078{
1079 return vmcs_config.cpu_based_2nd_exec_ctrl &
1080 SECONDARY_EXEC_RDTSCP;
1081}
1082
ad756a16
MJ		 1083static inline bool cpu_has_vmx_invpcid(void)
1084{
1085 return vmcs_config.cpu_based_2nd_exec_ctrl &
1086 SECONDARY_EXEC_ENABLE_INVPCID;
1087}
1088
31299944 1089static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1090{
1091 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1092}
1093
f5f48ee1
SY		 1094static inline bool cpu_has_vmx_wbinvd_exit(void)
1095{
1096 return vmcs_config.cpu_based_2nd_exec_ctrl &
1097 SECONDARY_EXEC_WBINVD_EXITING;
1098}
1099
abc4fc58
AG		 1100static inline bool cpu_has_vmx_shadow_vmcs(void)
1101{
1102 u64 vmx_msr;
1103 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1104 /* check if the cpu supports writing r/o exit information fields */
1105 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1106 return false;
1107
1108 return vmcs_config.cpu_based_2nd_exec_ctrl &
1109 SECONDARY_EXEC_SHADOW_VMCS;
1110}
1111
843e4330
KH		 1112static inline bool cpu_has_vmx_pml(void)
1113{
1114 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1115}
1116
04547156
SY		 1117static inline bool report_flexpriority(void)
1118{
1119 return flexpriority_enabled;
1120}
1121
fe3ef05c
NHE		 1122static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1123{
1124 return vmcs12->cpu_based_vm_exec_control & bit;
1125}
1126
1127static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1128{
1129 return (vmcs12->cpu_based_vm_exec_control &
1130 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1131 (vmcs12->secondary_vm_exec_control & bit);
1132}
1133
f5c4368f 1134static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1135{
1136 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1137}
1138
f4124500
JK		 1139static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1140{
1141 return vmcs12->pin_based_vm_exec_control &
1142 PIN_BASED_VMX_PREEMPTION_TIMER;
1143}
1144
155a97a3
NHE		 1145static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1146{
1147 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1148}
1149
81dc01f7
WL		 1150static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1151{
1152 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1153 vmx_xsaves_supported();
1154}
1155
f2b93280
WV		 1156static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1157{
1158 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1159}
1160
82f0dd4b
WV		 1161static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1162{
1163 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1164}
1165
608406e2
WV		 1166static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1167{
1168 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1169}
1170
705699a1
WV		 1171static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1172{
1173 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1174}
1175
644d711a
NHE		 1176static inline bool is_exception(u32 intr_info)
1177{
1178 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1179 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1180}
1181
533558bc
JK		 1182static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1183 u32 exit_intr_info,
1184 unsigned long exit_qualification);
7c177938
NHE		 1185static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1186 struct vmcs12 *vmcs12,
1187 u32 reason, unsigned long qualification);
1188
8b9cf98c 1189static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1190{
1191 int i;
1192
a2fa3e9f 1193 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1194 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1195 return i;
1196 return -1;
1197}
1198
2384d2b3
SY		 1199static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1200{
1201 struct {
1202 u64 vpid : 16;
1203 u64 rsvd : 48;
1204 u64 gva;
1205 } operand = { vpid, 0, gva };
1206
4ecac3fd 1207 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1208 /* CF==1 or ZF==1 --> rc = -1 */
1209 "; ja 1f ; ud2 ; 1:"
1210 : : "a"(&operand), "c"(ext) : "cc", "memory");
1211}
1212
1439442c
SY		 1213static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1214{
1215 struct {
1216 u64 eptp, gpa;
1217 } operand = {eptp, gpa};
1218
4ecac3fd 1219 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1220 /* CF==1 or ZF==1 --> rc = -1 */
1221 "; ja 1f ; ud2 ; 1:\n"
1222 : : "a" (&operand), "c" (ext) : "cc", "memory");
1223}
1224
26bb0981 1225static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1226{
1227 int i;
1228
8b9cf98c 1229 i = __find_msr_index(vmx, msr);
a75beee6 1230 if (i >= 0)
a2fa3e9f 1231 return &vmx->guest_msrs[i];
8b6d44c7 1232 return NULL;
7725f0ba
AK		 1233}
1234
6aa8b732
AK		 1235static void vmcs_clear(struct vmcs *vmcs)
1236{
1237 u64 phys_addr = __pa(vmcs);
1238 u8 error;
1239
4ecac3fd 1240 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1241 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1242 : "cc", "memory");
1243 if (error)
1244 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1245 vmcs, phys_addr);
1246}
1247
d462b819
NHE		 1248static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1249{
1250 vmcs_clear(loaded_vmcs->vmcs);
1251 loaded_vmcs->cpu = -1;
1252 loaded_vmcs->launched = 0;
1253}
1254
7725b894
DX		 1255static void vmcs_load(struct vmcs *vmcs)
1256{
1257 u64 phys_addr = __pa(vmcs);
1258 u8 error;
1259
1260 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1261 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1262 : "cc", "memory");
1263 if (error)
2844d849 1264 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1265 vmcs, phys_addr);
1266}
1267
2965faa5 1268#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 1269/*
1270 * This bitmap is used to indicate whether the vmclear
1271 * operation is enabled on all cpus. All disabled by
1272 * default.
1273 */
1274static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1275
1276static inline void crash_enable_local_vmclear(int cpu)
1277{
1278 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1279}
1280
1281static inline void crash_disable_local_vmclear(int cpu)
1282{
1283 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1284}
1285
1286static inline int crash_local_vmclear_enabled(int cpu)
1287{
1288 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1289}
1290
1291static void crash_vmclear_local_loaded_vmcss(void)
1292{
1293 int cpu = raw_smp_processor_id();
1294 struct loaded_vmcs *v;
1295
1296 if (!crash_local_vmclear_enabled(cpu))
1297 return;
1298
1299 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1300 loaded_vmcss_on_cpu_link)
1301 vmcs_clear(v->vmcs);
1302}
1303#else
1304static inline void crash_enable_local_vmclear(int cpu) { }
1305static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1306#endif /* CONFIG_KEXEC_CORE */
8f536b76 1307
d462b819 1308static void __loaded_vmcs_clear(void *arg)
6aa8b732 1309{
d462b819 1310 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1311 int cpu = raw_smp_processor_id();
6aa8b732 1312
d462b819
NHE		 1313 if (loaded_vmcs->cpu != cpu)
1314 return; /* vcpu migration can race with cpu offline */
1315 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1316 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1317 crash_disable_local_vmclear(cpu);
d462b819 1318 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1319
1320 /*
1321 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1322 * is before setting loaded_vmcs->vcpu to -1 which is done in
1323 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1324 * then adds the vmcs into percpu list before it is deleted.
1325 */
1326 smp_wmb();
1327
d462b819 1328 loaded_vmcs_init(loaded_vmcs);
8f536b76 1329 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1330}
1331
d462b819 1332static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1333{
e6c7d321
XG		 1334 int cpu = loaded_vmcs->cpu;
1335
1336 if (cpu != -1)
1337 smp_call_function_single(cpu,
1338 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1339}
1340
1760dd49 1341static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1342{
1343 if (vmx->vpid == 0)
1344 return;
1345
518c8aee
GJ		 1346 if (cpu_has_vmx_invvpid_single())
1347 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1348}
1349
b9d762fa
GJ		 1350static inline void vpid_sync_vcpu_global(void)
1351{
1352 if (cpu_has_vmx_invvpid_global())
1353 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1354}
1355
1356static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1357{
1358 if (cpu_has_vmx_invvpid_single())
1760dd49 1359 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1360 else
1361 vpid_sync_vcpu_global();
1362}
1363
1439442c
SY		 1364static inline void ept_sync_global(void)
1365{
1366 if (cpu_has_vmx_invept_global())
1367 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1368}
1369
1370static inline void ept_sync_context(u64 eptp)
1371{
089d034e 1372 if (enable_ept) {
1439442c
SY		 1373 if (cpu_has_vmx_invept_context())
1374 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1375 else
1376 ept_sync_global();
1377 }
1378}
1379
96304217 1380static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1381{
5e520e62 1382 unsigned long value;
6aa8b732 1383
5e520e62
AK		 1384 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1385 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1386 return value;
1387}
1388
96304217 1389static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1390{
1391 return vmcs_readl(field);
1392}
1393
96304217 1394static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1395{
1396 return vmcs_readl(field);
1397}
1398
96304217 1399static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1400{
05b3e0c2 1401#ifdef CONFIG_X86_64
6aa8b732
AK		 1402 return vmcs_readl(field);
1403#else
1404 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1405#endif
1406}
1407
e52de1b8
AK		 1408static noinline void vmwrite_error(unsigned long field, unsigned long value)
1409{
1410 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1411 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1412 dump_stack();
1413}
1414
6aa8b732
AK		 1415static void vmcs_writel(unsigned long field, unsigned long value)
1416{
1417 u8 error;
1418
4ecac3fd 1419 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1420 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1421 if (unlikely(error))
1422 vmwrite_error(field, value);
6aa8b732
AK		 1423}
1424
1425static void vmcs_write16(unsigned long field, u16 value)
1426{
1427 vmcs_writel(field, value);
1428}
1429
1430static void vmcs_write32(unsigned long field, u32 value)
1431{
1432 vmcs_writel(field, value);
1433}
1434
1435static void vmcs_write64(unsigned long field, u64 value)
1436{
6aa8b732 1437 vmcs_writel(field, value);
7682f2d0 1438#ifndef CONFIG_X86_64
6aa8b732
AK		 1439 asm volatile ("");
1440 vmcs_writel(field+1, value >> 32);
1441#endif
1442}
1443
2ab455cc
AL		 1444static void vmcs_clear_bits(unsigned long field, u32 mask)
1445{
1446 vmcs_writel(field, vmcs_readl(field) & ~mask);
1447}
1448
1449static void vmcs_set_bits(unsigned long field, u32 mask)
1450{
1451 vmcs_writel(field, vmcs_readl(field) | mask);
1452}
1453
2961e876
GN		 1454static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1455{
1456 vmcs_write32(VM_ENTRY_CONTROLS, val);
1457 vmx->vm_entry_controls_shadow = val;
1458}
1459
1460static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1461{
1462 if (vmx->vm_entry_controls_shadow != val)
1463 vm_entry_controls_init(vmx, val);
1464}
1465
1466static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1467{
1468 return vmx->vm_entry_controls_shadow;
1469}
1470
1471
1472static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1473{
1474 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1475}
1476
1477static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1478{
1479 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1480}
1481
1482static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1483{
1484 vmcs_write32(VM_EXIT_CONTROLS, val);
1485 vmx->vm_exit_controls_shadow = val;
1486}
1487
1488static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1489{
1490 if (vmx->vm_exit_controls_shadow != val)
1491 vm_exit_controls_init(vmx, val);
1492}
1493
1494static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1495{
1496 return vmx->vm_exit_controls_shadow;
1497}
1498
1499
1500static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1501{
1502 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1503}
1504
1505static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1506{
1507 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1508}
1509
2fb92db1
AK		 1510static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1511{
1512 vmx->segment_cache.bitmask = 0;
1513}
1514
1515static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1516 unsigned field)
1517{
1518 bool ret;
1519 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1520
1521 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1522 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1523 vmx->segment_cache.bitmask = 0;
1524 }
1525 ret = vmx->segment_cache.bitmask & mask;
1526 vmx->segment_cache.bitmask |= mask;
1527 return ret;
1528}
1529
1530static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1531{
1532 u16 *p = &vmx->segment_cache.seg[seg].selector;
1533
1534 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1535 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1536 return *p;
1537}
1538
1539static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1540{
1541 ulong *p = &vmx->segment_cache.seg[seg].base;
1542
1543 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1544 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1545 return *p;
1546}
1547
1548static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1549{
1550 u32 *p = &vmx->segment_cache.seg[seg].limit;
1551
1552 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1553 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1554 return *p;
1555}
1556
1557static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1558{
1559 u32 *p = &vmx->segment_cache.seg[seg].ar;
1560
1561 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1562 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1563 return *p;
1564}
1565
abd3f2d6
AK		 1566static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1567{
1568 u32 eb;
1569
fd7373cc
JK		 1570 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1571 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1572 if ((vcpu->guest_debug &
1573 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1574 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1575 eb |= 1u << BP_VECTOR;
7ffd92c5 1576 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1577 eb = ~0;
089d034e 1578 if (enable_ept)
1439442c 1579 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1580 if (vcpu->fpu_active)
1581 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1582
1583 /* When we are running a nested L2 guest and L1 specified for it a
1584 * certain exception bitmap, we must trap the same exceptions and pass
1585 * them to L1. When running L2, we will only handle the exceptions
1586 * specified above if L1 did not want them.
1587 */
1588 if (is_guest_mode(vcpu))
1589 eb |= get_vmcs12(vcpu)->exception_bitmap;
1590
abd3f2d6
AK		 1591 vmcs_write32(EXCEPTION_BITMAP, eb);
1592}
1593
2961e876
GN		 1594static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1595 unsigned long entry, unsigned long exit)
8bf00a52 1596{
2961e876
GN		 1597 vm_entry_controls_clearbit(vmx, entry);
1598 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1599}
1600
61d2ef2c
AK		 1601static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1602{
1603 unsigned i;
1604 struct msr_autoload *m = &vmx->msr_autoload;
1605
8bf00a52
GN		 1606 switch (msr) {
1607 case MSR_EFER:
1608 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1609 clear_atomic_switch_msr_special(vmx,
1610 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1611 VM_EXIT_LOAD_IA32_EFER);
1612 return;
1613 }
1614 break;
1615 case MSR_CORE_PERF_GLOBAL_CTRL:
1616 if (cpu_has_load_perf_global_ctrl) {
2961e876 1617 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1618 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1619 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1620 return;
1621 }
1622 break;
110312c8
AK		 1623 }
1624
61d2ef2c
AK		 1625 for (i = 0; i < m->nr; ++i)
1626 if (m->guest[i].index == msr)
1627 break;
1628
1629 if (i == m->nr)
1630 return;
1631 --m->nr;
1632 m->guest[i] = m->guest[m->nr];
1633 m->host[i] = m->host[m->nr];
1634 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1635 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1636}
1637
2961e876
GN		 1638static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1639 unsigned long entry, unsigned long exit,
1640 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1641 u64 guest_val, u64 host_val)
8bf00a52
GN		 1642{
1643 vmcs_write64(guest_val_vmcs, guest_val);
1644 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1645 vm_entry_controls_setbit(vmx, entry);
1646 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1647}
1648
61d2ef2c
AK		 1649static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1650 u64 guest_val, u64 host_val)
1651{
1652 unsigned i;
1653 struct msr_autoload *m = &vmx->msr_autoload;
1654
8bf00a52
GN		 1655 switch (msr) {
1656 case MSR_EFER:
1657 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1658 add_atomic_switch_msr_special(vmx,
1659 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1660 VM_EXIT_LOAD_IA32_EFER,
1661 GUEST_IA32_EFER,
1662 HOST_IA32_EFER,
1663 guest_val, host_val);
1664 return;
1665 }
1666 break;
1667 case MSR_CORE_PERF_GLOBAL_CTRL:
1668 if (cpu_has_load_perf_global_ctrl) {
2961e876 1669 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1670 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1671 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1672 GUEST_IA32_PERF_GLOBAL_CTRL,
1673 HOST_IA32_PERF_GLOBAL_CTRL,
1674 guest_val, host_val);
1675 return;
1676 }
1677 break;
110312c8
AK		 1678 }
1679
61d2ef2c
AK		 1680 for (i = 0; i < m->nr; ++i)
1681 if (m->guest[i].index == msr)
1682 break;
1683
e7fc6f93 1684 if (i == NR_AUTOLOAD_MSRS) {
60266204 1685 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1686 "Can't add msr %x\n", msr);
1687 return;
1688 } else if (i == m->nr) {
61d2ef2c
AK		 1689 ++m->nr;
1690 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1691 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1692 }
1693
1694 m->guest[i].index = msr;
1695 m->guest[i].value = guest_val;
1696 m->host[i].index = msr;
1697 m->host[i].value = host_val;
1698}
1699
33ed6329
AK		 1700static void reload_tss(void)
1701{
33ed6329
AK		 1702 /*
1703 * VT restores TR but not its size. Useless.
1704 */
89cbc767 1705 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1706 struct desc_struct *descs;
33ed6329 1707
d359192f 1708 descs = (void *)gdt->address;
33ed6329
AK		 1709 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1710 load_TR_desc();
33ed6329
AK		 1711}
1712
92c0d900 1713static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1714{
3a34a881 1715 u64 guest_efer;
51c6cf66
AK		 1716 u64 ignore_bits;
1717
f6801dff 1718 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1719
51c6cf66 1720 /*
0fa06071 1721 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1722 * outside long mode
1723 */
1724 ignore_bits = EFER_NX | EFER_SCE;
1725#ifdef CONFIG_X86_64
1726 ignore_bits |= EFER_LMA | EFER_LME;
1727 /* SCE is meaningful only in long mode on Intel */
1728 if (guest_efer & EFER_LMA)
1729 ignore_bits &= ~(u64)EFER_SCE;
1730#endif
51c6cf66
AK		 1731 guest_efer &= ~ignore_bits;
1732 guest_efer |= host_efer & ignore_bits;
26bb0981 1733 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1734 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1735
1736 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1737
1738 /*
1739 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1740 * On CPUs that support "load IA32_EFER", always switch EFER
1741 * atomically, since it's faster than switching it manually.
1742 */
1743 if (cpu_has_load_ia32_efer ||
1744 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1745 guest_efer = vmx->vcpu.arch.efer;
1746 if (!(guest_efer & EFER_LMA))
1747 guest_efer &= ~EFER_LME;
54b98bff
AL		 1748 if (guest_efer != host_efer)
1749 add_atomic_switch_msr(vmx, MSR_EFER,
1750 guest_efer, host_efer);
84ad33ef
AK		 1751 return false;
1752 }
1753
26bb0981 1754 return true;
51c6cf66
AK		 1755}
1756
2d49ec72
GN		 1757static unsigned long segment_base(u16 selector)
1758{
89cbc767 1759 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1760 struct desc_struct *d;
1761 unsigned long table_base;
1762 unsigned long v;
1763
1764 if (!(selector & ~3))
1765 return 0;
1766
d359192f 1767 table_base = gdt->address;
2d49ec72
GN		 1768
1769 if (selector & 4) { /* from ldt */
1770 u16 ldt_selector = kvm_read_ldt();
1771
1772 if (!(ldt_selector & ~3))
1773 return 0;
1774
1775 table_base = segment_base(ldt_selector);
1776 }
1777 d = (struct desc_struct *)(table_base + (selector & ~7));
1778 v = get_desc_base(d);
1779#ifdef CONFIG_X86_64
1780 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1781 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1782#endif
1783 return v;
1784}
1785
1786static inline unsigned long kvm_read_tr_base(void)
1787{
1788 u16 tr;
1789 asm("str %0" : "=g"(tr));
1790 return segment_base(tr);
1791}
1792
04d2cc77 1793static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1794{
04d2cc77 1795 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1796 int i;
04d2cc77 1797
a2fa3e9f 1798 if (vmx->host_state.loaded)
33ed6329
AK		 1799 return;
1800
a2fa3e9f 1801 vmx->host_state.loaded = 1;
33ed6329
AK		 1802 /*
1803 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1804 * allow segment selectors with cpl > 0 or ti == 1.
1805 */
d6e88aec 1806 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1807 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1808 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1809 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1810 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1811 vmx->host_state.fs_reload_needed = 0;
1812 } else {
33ed6329 1813 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1814 vmx->host_state.fs_reload_needed = 1;
33ed6329 1815 }
9581d442 1816 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1817 if (!(vmx->host_state.gs_sel & 7))
1818 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1819 else {
1820 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1821 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1822 }
1823
b2da15ac
AK		 1824#ifdef CONFIG_X86_64
1825 savesegment(ds, vmx->host_state.ds_sel);
1826 savesegment(es, vmx->host_state.es_sel);
1827#endif
1828
33ed6329
AK		 1829#ifdef CONFIG_X86_64
1830 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1831 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1832#else
a2fa3e9f
GH		 1833 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1834 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1835#endif
707c0874
AK		 1836
1837#ifdef CONFIG_X86_64
c8770e7b
AK		 1838 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1839 if (is_long_mode(&vmx->vcpu))
44ea2b17 1840 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1841#endif
da8999d3
LJ		 1842 if (boot_cpu_has(X86_FEATURE_MPX))
1843 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1844 for (i = 0; i < vmx->save_nmsrs; ++i)
1845 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1846 vmx->guest_msrs[i].data,
1847 vmx->guest_msrs[i].mask);
33ed6329
AK		 1848}
1849
a9b21b62 1850static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1851{
a2fa3e9f 1852 if (!vmx->host_state.loaded)
33ed6329
AK		 1853 return;
1854
e1beb1d3 1855 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1856 vmx->host_state.loaded = 0;
c8770e7b
AK		 1857#ifdef CONFIG_X86_64
1858 if (is_long_mode(&vmx->vcpu))
1859 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1860#endif
152d3f2f 1861 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1862 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1863#ifdef CONFIG_X86_64
9581d442 1864 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1865#else
1866 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1867#endif
33ed6329 1868 }
0a77fe4c
AK		 1869 if (vmx->host_state.fs_reload_needed)
1870 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1871#ifdef CONFIG_X86_64
1872 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1873 loadsegment(ds, vmx->host_state.ds_sel);
1874 loadsegment(es, vmx->host_state.es_sel);
1875 }
b2da15ac 1876#endif
152d3f2f 1877 reload_tss();
44ea2b17 1878#ifdef CONFIG_X86_64
c8770e7b 1879 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1880#endif
da8999d3
LJ		 1881 if (vmx->host_state.msr_host_bndcfgs)
1882 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1883 /*
1884 * If the FPU is not active (through the host task or
1885 * the guest vcpu), then restore the cr0.TS bit.
1886 */
3c6dffa9 1887 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
b1a74bf8 1888 stts();
89cbc767 1889 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1890}
1891
a9b21b62
AK		 1892static void vmx_load_host_state(struct vcpu_vmx *vmx)
1893{
1894 preempt_disable();
1895 __vmx_load_host_state(vmx);
1896 preempt_enable();
1897}
1898
6aa8b732
AK		 1899/*
1900 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1901 * vcpu mutex is already taken.
1902 */
15ad7146 1903static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1904{
a2fa3e9f 1905 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1906 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1907
4610c9cc
DX		 1908 if (!vmm_exclusive)
1909 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1910 else if (vmx->loaded_vmcs->cpu != cpu)
1911 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1912
d462b819
NHE		 1913 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1914 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1915 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1916 }
1917
d462b819 1918 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1919 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1920 unsigned long sysenter_esp;
1921
a8eeb04a 1922 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1923 local_irq_disable();
8f536b76 1924 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1925
1926 /*
1927 * Read loaded_vmcs->cpu should be before fetching
1928 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1929 * See the comments in __loaded_vmcs_clear().
1930 */
1931 smp_rmb();
1932
d462b819
NHE		 1933 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1934 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1935 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1936 local_irq_enable();
1937
6aa8b732
AK		 1938 /*
1939 * Linux uses per-cpu TSS and GDT, so set these when switching
1940 * processors.
1941 */
d6e88aec 1942 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1943 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1944
1945 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1946 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1947 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1948 }
6aa8b732
AK		 1949}
1950
1951static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1952{
a9b21b62 1953 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1954 if (!vmm_exclusive) {
d462b819
NHE		 1955 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1956 vcpu->cpu = -1;
4610c9cc
DX		 1957 kvm_cpu_vmxoff();
1958 }
6aa8b732
AK		 1959}
1960
5fd86fcf
AK		 1961static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1962{
81231c69
AK		 1963 ulong cr0;
1964
5fd86fcf
AK		 1965 if (vcpu->fpu_active)
1966 return;
1967 vcpu->fpu_active = 1;
81231c69
AK		 1968 cr0 = vmcs_readl(GUEST_CR0);
1969 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1970 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1971 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1972 update_exception_bitmap(vcpu);
edcafe3c 1973 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1974 if (is_guest_mode(vcpu))
1975 vcpu->arch.cr0_guest_owned_bits &=
1976 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1977 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1978}
1979
edcafe3c
AK		 1980static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1981
fe3ef05c
NHE		 1982/*
1983 * Return the cr0 value that a nested guest would read. This is a combination
1984 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1985 * its hypervisor (cr0_read_shadow).
1986 */
1987static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1988{
1989 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1990 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1991}
1992static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1993{
1994 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1995 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1996}
1997
5fd86fcf
AK		 1998static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1999{
36cf24e0
NHE		 2000 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2001 * set this *before* calling this function.
2002 */
edcafe3c 2003 vmx_decache_cr0_guest_bits(vcpu);
81231c69 2004 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 2005 update_exception_bitmap(vcpu);
edcafe3c
AK		 2006 vcpu->arch.cr0_guest_owned_bits = 0;
2007 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 2008 if (is_guest_mode(vcpu)) {
2009 /*
2010 * L1's specified read shadow might not contain the TS bit,
2011 * so now that we turned on shadowing of this bit, we need to
2012 * set this bit of the shadow. Like in nested_vmx_run we need
2013 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2014 * up-to-date here because we just decached cr0.TS (and we'll
2015 * only update vmcs12->guest_cr0 on nested exit).
2016 */
2017 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2018 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2019 (vcpu->arch.cr0 & X86_CR0_TS);
2020 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2021 } else
2022 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2023}
2024
6aa8b732
AK		 2025static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2026{
78ac8b47 2027 unsigned long rflags, save_rflags;
345dcaa8 2028
6de12732
AK		 2029 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2030 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2031 rflags = vmcs_readl(GUEST_RFLAGS);
2032 if (to_vmx(vcpu)->rmode.vm86_active) {
2033 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2034 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2035 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2036 }
2037 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2038 }
6de12732 2039 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2040}
2041
2042static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2043{
6de12732
AK		 2044 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2045 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2046 if (to_vmx(vcpu)->rmode.vm86_active) {
2047 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2048 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2049 }
6aa8b732
AK		 2050 vmcs_writel(GUEST_RFLAGS, rflags);
2051}
2052
37ccdcbe 2053static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2054{
2055 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2056 int ret = 0;
2057
2058 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2059 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2060 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2061 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2062
37ccdcbe 2063 return ret;
2809f5d2
GC		 2064}
2065
2066static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2067{
2068 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2069 u32 interruptibility = interruptibility_old;
2070
2071 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2072
48005f64 2073 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2074 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2075 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2076 interruptibility |= GUEST_INTR_STATE_STI;
2077
2078 if ((interruptibility != interruptibility_old))
2079 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2080}
2081
6aa8b732
AK		 2082static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2083{
2084 unsigned long rip;
6aa8b732 2085
5fdbf976 2086 rip = kvm_rip_read(vcpu);
6aa8b732 2087 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2088 kvm_rip_write(vcpu, rip);
6aa8b732 2089
2809f5d2
GC		 2090 /* skipping an emulated instruction also counts */
2091 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2092}
2093
0b6ac343
NHE		 2094/*
2095 * KVM wants to inject page-faults which it got to the guest. This function
2096 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2097 */
e011c663 2098static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2099{
2100 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2101
e011c663 2102 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2103 return 0;
2104
533558bc
JK		 2105 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2106 vmcs_read32(VM_EXIT_INTR_INFO),
2107 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2108 return 1;
2109}
2110
298101da 2111static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2112 bool has_error_code, u32 error_code,
2113 bool reinject)
298101da 2114{
77ab6db0 2115 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2116 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2117
e011c663
GN		 2118 if (!reinject && is_guest_mode(vcpu) &&
2119 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2120 return;
2121
8ab2d2e2 2122 if (has_error_code) {
77ab6db0 2123 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2124 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2125 }
77ab6db0 2126
7ffd92c5 2127 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2128 int inc_eip = 0;
2129 if (kvm_exception_is_soft(nr))
2130 inc_eip = vcpu->arch.event_exit_inst_len;
2131 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2132 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2133 return;
2134 }
2135
66fd3f7f
GN		 2136 if (kvm_exception_is_soft(nr)) {
2137 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2138 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2139 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2140 } else
2141 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2142
2143 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2144}
2145
4e47c7a6
SY		 2146static bool vmx_rdtscp_supported(void)
2147{
2148 return cpu_has_vmx_rdtscp();
2149}
2150
ad756a16
MJ		 2151static bool vmx_invpcid_supported(void)
2152{
2153 return cpu_has_vmx_invpcid() && enable_ept;
2154}
2155
a75beee6
ED		 2156/*
2157 * Swap MSR entry in host/guest MSR entry array.
2158 */
8b9cf98c 2159static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2160{
26bb0981 2161 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2162
2163 tmp = vmx->guest_msrs[to];
2164 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2165 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2166}
2167
8d14695f
YZ		 2168static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2169{
2170 unsigned long *msr_bitmap;
2171
670125bd
WV		 2172 if (is_guest_mode(vcpu))
2173 msr_bitmap = vmx_msr_bitmap_nested;
8a9781f7 2174 else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
8d14695f
YZ		 2175 if (is_long_mode(vcpu))
2176 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2177 else
2178 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2179 } else {
2180 if (is_long_mode(vcpu))
2181 msr_bitmap = vmx_msr_bitmap_longmode;
2182 else
2183 msr_bitmap = vmx_msr_bitmap_legacy;
2184 }
2185
2186 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2187}
2188
e38aea3e
AK		 2189/*
2190 * Set up the vmcs to automatically save and restore system
2191 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2192 * mode, as fiddling with msrs is very expensive.
2193 */
8b9cf98c 2194static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2195{
26bb0981 2196 int save_nmsrs, index;
e38aea3e 2197
a75beee6
ED		 2198 save_nmsrs = 0;
2199#ifdef CONFIG_X86_64
8b9cf98c 2200 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2201 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2202 if (index >= 0)
8b9cf98c
RR		 2203 move_msr_up(vmx, index, save_nmsrs++);
2204 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2205 if (index >= 0)
8b9cf98c
RR		 2206 move_msr_up(vmx, index, save_nmsrs++);
2207 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2208 if (index >= 0)
8b9cf98c 2209 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2210 index = __find_msr_index(vmx, MSR_TSC_AUX);
2211 if (index >= 0 && vmx->rdtscp_enabled)
2212 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2213 /*
8c06585d 2214 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2215 * if efer.sce is enabled.
2216 */
8c06585d 2217 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2218 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2219 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2220 }
2221#endif
92c0d900
AK		 2222 index = __find_msr_index(vmx, MSR_EFER);
2223 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2224 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2225
26bb0981 2226 vmx->save_nmsrs = save_nmsrs;
5897297b 2227
8d14695f
YZ		 2228 if (cpu_has_vmx_msr_bitmap())
2229 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2230}
2231
6aa8b732
AK		 2232/*
2233 * reads and returns guest's timestamp counter "register"
2234 * guest_tsc = host_tsc + tsc_offset -- 21.3
2235 */
2236static u64 guest_read_tsc(void)
2237{
2238 u64 host_tsc, tsc_offset;
2239
4ea1636b 2240 host_tsc = rdtsc();
6aa8b732
AK		 2241 tsc_offset = vmcs_read64(TSC_OFFSET);
2242 return host_tsc + tsc_offset;
2243}
2244
d5c1785d
NHE		 2245/*
2246 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2247 * counter, even if a nested guest (L2) is currently running.
2248 */
48d89b92 2249static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2250{
886b470c 2251 u64 tsc_offset;
d5c1785d 2252
d5c1785d
NHE		 2253 tsc_offset = is_guest_mode(vcpu) ?
2254 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2255 vmcs_read64(TSC_OFFSET);
2256 return host_tsc + tsc_offset;
2257}
2258
4051b188 2259/*
cc578287
ZA		 2260 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2261 * software catchup for faster rates on slower CPUs.
4051b188 2262 */
cc578287 2263static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2264{
cc578287
ZA		 2265 if (!scale)
2266 return;
2267
2268 if (user_tsc_khz > tsc_khz) {
2269 vcpu->arch.tsc_catchup = 1;
2270 vcpu->arch.tsc_always_catchup = 1;
2271 } else
2272 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2273}
2274
ba904635
WA		 2275static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2276{
2277 return vmcs_read64(TSC_OFFSET);
2278}
2279
6aa8b732 2280/*
99e3e30a 2281 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2282 */
99e3e30a 2283static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2284{
27fc51b2 2285 if (is_guest_mode(vcpu)) {
7991825b 2286 /*
27fc51b2
NHE		 2287 * We're here if L1 chose not to trap WRMSR to TSC. According
2288 * to the spec, this should set L1's TSC; The offset that L1
2289 * set for L2 remains unchanged, and still needs to be added
2290 * to the newly set TSC to get L2's TSC.
7991825b 2291 */
27fc51b2
NHE		 2292 struct vmcs12 *vmcs12;
2293 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2294 /* recalculate vmcs02.TSC_OFFSET: */
2295 vmcs12 = get_vmcs12(vcpu);
2296 vmcs_write64(TSC_OFFSET, offset +
2297 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2298 vmcs12->tsc_offset : 0));
2299 } else {
489223ed
YY		 2300 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2301 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2302 vmcs_write64(TSC_OFFSET, offset);
2303 }
6aa8b732
AK		 2304}
2305
f1e2b260 2306static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2307{
2308 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2309
e48672fa 2310 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2311 if (is_guest_mode(vcpu)) {
2312 /* Even when running L2, the adjustment needs to apply to L1 */
2313 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2314 } else
2315 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2316 offset + adjustment);
e48672fa
ZA		 2317}
2318
857e4099
JR		 2319static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2320{
4ea1636b 2321 return target_tsc - rdtsc();
857e4099
JR		 2322}
2323
801d3424
NHE		 2324static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2325{
2326 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2327 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2328}
2329
2330/*
2331 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2332 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2333 * all guests if the "nested" module option is off, and can also be disabled
2334 * for a single guest by disabling its VMX cpuid bit.
2335 */
2336static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2337{
2338 return nested && guest_cpuid_has_vmx(vcpu);
2339}
2340
b87a51ae
NHE		 2341/*
2342 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2343 * returned for the various VMX controls MSRs when nested VMX is enabled.
2344 * The same values should also be used to verify that vmcs12 control fields are
2345 * valid during nested entry from L1 to L2.
2346 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2347 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2348 * bit in the high half is on if the corresponding bit in the control field
2349 * may be on. See also vmx_control_verify().
b87a51ae 2350 */
b9c237bb 2351static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2352{
2353 /*
2354 * Note that as a general rule, the high half of the MSRs (bits in
2355 * the control fields which may be 1) should be initialized by the
2356 * intersection of the underlying hardware's MSR (i.e., features which
2357 * can be supported) and the list of features we want to expose -
2358 * because they are known to be properly supported in our code.
2359 * Also, usually, the low half of the MSRs (bits which must be 1) can
2360 * be set to 0, meaning that L1 may turn off any of these bits. The
2361 * reason is that if one of these bits is necessary, it will appear
2362 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2363 * fields of vmcs01 and vmcs02, will turn these bits off - and
2364 * nested_vmx_exit_handled() will not pass related exits to L1.
2365 * These rules have exceptions below.
2366 */
2367
2368 /* pin-based controls */
eabeaacc 2369 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2370 vmx->nested.nested_vmx_pinbased_ctls_low,
2371 vmx->nested.nested_vmx_pinbased_ctls_high);
2372 vmx->nested.nested_vmx_pinbased_ctls_low |=
2373 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2374 vmx->nested.nested_vmx_pinbased_ctls_high &=
2375 PIN_BASED_EXT_INTR_MASK |
2376 PIN_BASED_NMI_EXITING |
2377 PIN_BASED_VIRTUAL_NMIS;
2378 vmx->nested.nested_vmx_pinbased_ctls_high |=
2379 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2380 PIN_BASED_VMX_PREEMPTION_TIMER;
35754c98 2381 if (vmx_cpu_uses_apicv(&vmx->vcpu))
705699a1
WV		 2382 vmx->nested.nested_vmx_pinbased_ctls_high |=
2383 PIN_BASED_POSTED_INTR;
b87a51ae 2384
3dbcd8da 2385 /* exit controls */
c0dfee58 2386 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2387 vmx->nested.nested_vmx_exit_ctls_low,
2388 vmx->nested.nested_vmx_exit_ctls_high);
2389 vmx->nested.nested_vmx_exit_ctls_low =
2390 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2391
b9c237bb 2392 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2393#ifdef CONFIG_X86_64
c0dfee58 2394 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2395#endif
f4124500 2396 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2397 vmx->nested.nested_vmx_exit_ctls_high |=
2398 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2399 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2400 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2401
36be0b9d 2402 if (vmx_mpx_supported())
b9c237bb 2403 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2404
2996fca0 2405 /* We support free control of debug control saving. */
b9c237bb
WV		 2406 vmx->nested.nested_vmx_true_exit_ctls_low =
2407 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2408 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2409
b87a51ae
NHE		 2410 /* entry controls */
2411 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2412 vmx->nested.nested_vmx_entry_ctls_low,
2413 vmx->nested.nested_vmx_entry_ctls_high);
2414 vmx->nested.nested_vmx_entry_ctls_low =
2415 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2416 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2417#ifdef CONFIG_X86_64
2418 VM_ENTRY_IA32E_MODE |
2419#endif
2420 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2421 vmx->nested.nested_vmx_entry_ctls_high |=
2422 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2423 if (vmx_mpx_supported())
b9c237bb 2424 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2425
2996fca0 2426 /* We support free control of debug control loading. */
b9c237bb
WV		 2427 vmx->nested.nested_vmx_true_entry_ctls_low =
2428 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2429 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2430
b87a51ae
NHE		 2431 /* cpu-based controls */
2432 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2433 vmx->nested.nested_vmx_procbased_ctls_low,
2434 vmx->nested.nested_vmx_procbased_ctls_high);
2435 vmx->nested.nested_vmx_procbased_ctls_low =
2436 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2437 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2438 CPU_BASED_VIRTUAL_INTR_PENDING |
2439 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2440 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2441 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2442 CPU_BASED_CR3_STORE_EXITING |
2443#ifdef CONFIG_X86_64
2444 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2445#endif
2446 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD		 2447 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2448 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2449 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2450 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE		 2451 /*
2452 * We can allow some features even when not supported by the
2453 * hardware. For example, L1 can specify an MSR bitmap - and we
2454 * can use it to avoid exits to L1 - even when L0 runs L2
2455 * without MSR bitmaps.
2456 */
b9c237bb
WV		 2457 vmx->nested.nested_vmx_procbased_ctls_high |=
2458 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2459 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2460
3dcdf3ec 2461 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2462 vmx->nested.nested_vmx_true_procbased_ctls_low =
2463 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2464 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2465
b87a51ae
NHE		 2466 /* secondary cpu-based controls */
2467 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2468 vmx->nested.nested_vmx_secondary_ctls_low,
2469 vmx->nested.nested_vmx_secondary_ctls_high);
2470 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2471 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2472 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2473 SECONDARY_EXEC_RDTSCP |
f2b93280 2474 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2475 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2476 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7 2477 SECONDARY_EXEC_WBINVD_EXITING |
8b3e34e4
XG		 2478 SECONDARY_EXEC_XSAVES |
2479 SECONDARY_EXEC_PCOMMIT;
c18911a2 2480
afa61f75
NHE		 2481 if (enable_ept) {
2482 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2483 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2484 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2485 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2486 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2487 VMX_EPT_INVEPT_BIT;
b9c237bb 2488 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2489 /*
4b855078
BD		 2490 * For nested guests, we don't do anything specific
2491 * for single context invalidation. Hence, only advertise
2492 * support for global context invalidation.
afa61f75 2493 */
b9c237bb 2494 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2495 } else
b9c237bb 2496 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2497
0790ec17
RK		 2498 if (enable_unrestricted_guest)
2499 vmx->nested.nested_vmx_secondary_ctls_high |=
2500 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2501
c18911a2 2502 /* miscellaneous data */
b9c237bb
WV		 2503 rdmsr(MSR_IA32_VMX_MISC,
2504 vmx->nested.nested_vmx_misc_low,
2505 vmx->nested.nested_vmx_misc_high);
2506 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2507 vmx->nested.nested_vmx_misc_low |=
2508 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2509 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2510 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2511}
2512
2513static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2514{
2515 /*
2516 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2517 */
2518 return ((control & high) | low) == control;
2519}
2520
2521static inline u64 vmx_control_msr(u32 low, u32 high)
2522{
2523 return low | ((u64)high << 32);
2524}
2525
cae50139 2526/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2527static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2528{
b9c237bb
WV		 2529 struct vcpu_vmx *vmx = to_vmx(vcpu);
2530
b87a51ae 2531 switch (msr_index) {
b87a51ae
NHE		 2532 case MSR_IA32_VMX_BASIC:
2533 /*
2534 * This MSR reports some information about VMX support. We
2535 * should return information about the VMX we emulate for the
2536 * guest, and the VMCS structure we give it - not about the
2537 * VMX support of the underlying hardware.
2538 */
3dbcd8da 2539 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2540 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2541 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2542 break;
2543 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2544 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2545 *pdata = vmx_control_msr(
2546 vmx->nested.nested_vmx_pinbased_ctls_low,
2547 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2548 break;
2549 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2550 *pdata = vmx_control_msr(
2551 vmx->nested.nested_vmx_true_procbased_ctls_low,
2552 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2553 break;
b87a51ae 2554 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2555 *pdata = vmx_control_msr(
2556 vmx->nested.nested_vmx_procbased_ctls_low,
2557 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2558 break;
2559 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2560 *pdata = vmx_control_msr(
2561 vmx->nested.nested_vmx_true_exit_ctls_low,
2562 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2563 break;
b87a51ae 2564 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2565 *pdata = vmx_control_msr(
2566 vmx->nested.nested_vmx_exit_ctls_low,
2567 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2568 break;
2569 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2570 *pdata = vmx_control_msr(
2571 vmx->nested.nested_vmx_true_entry_ctls_low,
2572 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2573 break;
b87a51ae 2574 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2575 *pdata = vmx_control_msr(
2576 vmx->nested.nested_vmx_entry_ctls_low,
2577 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2578 break;
2579 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2580 *pdata = vmx_control_msr(
2581 vmx->nested.nested_vmx_misc_low,
2582 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2583 break;
2584 /*
2585 * These MSRs specify bits which the guest must keep fixed (on or off)
2586 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2587 * We picked the standard core2 setting.
2588 */
2589#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2590#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2591 case MSR_IA32_VMX_CR0_FIXED0:
2592 *pdata = VMXON_CR0_ALWAYSON;
2593 break;
2594 case MSR_IA32_VMX_CR0_FIXED1:
2595 *pdata = -1ULL;
2596 break;
2597 case MSR_IA32_VMX_CR4_FIXED0:
2598 *pdata = VMXON_CR4_ALWAYSON;
2599 break;
2600 case MSR_IA32_VMX_CR4_FIXED1:
2601 *pdata = -1ULL;
2602 break;
2603 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2604 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2605 break;
2606 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2607 *pdata = vmx_control_msr(
2608 vmx->nested.nested_vmx_secondary_ctls_low,
2609 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2610 break;
2611 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2612 /* Currently, no nested vpid support */
b9c237bb 2613 *pdata = vmx->nested.nested_vmx_ept_caps;
b87a51ae
NHE		 2614 break;
2615 default:
b87a51ae 2616 return 1;
b3897a49
NHE		 2617 }
2618
b87a51ae
NHE		 2619 return 0;
2620}
2621
6aa8b732
AK		 2622/*
2623 * Reads an msr value (of 'msr_index') into 'pdata'.
2624 * Returns 0 on success, non-0 otherwise.
2625 * Assumes vcpu_load() was already called.
2626 */
609e36d3 2627static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2628{
26bb0981 2629 struct shared_msr_entry *msr;
6aa8b732 2630
609e36d3 2631 switch (msr_info->index) {
05b3e0c2 2632#ifdef CONFIG_X86_64
6aa8b732 2633 case MSR_FS_BASE:
609e36d3 2634 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK		 2635 break;
2636 case MSR_GS_BASE:
609e36d3 2637 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 2638 break;
44ea2b17
AK		 2639 case MSR_KERNEL_GS_BASE:
2640 vmx_load_host_state(to_vmx(vcpu));
609e36d3 2641 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 2642 break;
26bb0981 2643#endif
6aa8b732 2644 case MSR_EFER:
609e36d3 2645 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 2646 case MSR_IA32_TSC:
609e36d3 2647 msr_info->data = guest_read_tsc();
6aa8b732
AK		 2648 break;
2649 case MSR_IA32_SYSENTER_CS:
609e36d3 2650 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 2651 break;
2652 case MSR_IA32_SYSENTER_EIP:
609e36d3 2653 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2654 break;
2655 case MSR_IA32_SYSENTER_ESP:
609e36d3 2656 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2657 break;
0dd376e7 2658 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2659 if (!vmx_mpx_supported())
2660 return 1;
609e36d3 2661 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 2662 break;
cae50139
JK		 2663 case MSR_IA32_FEATURE_CONTROL:
2664 if (!nested_vmx_allowed(vcpu))
2665 return 1;
609e36d3 2666 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
cae50139
JK		 2667 break;
2668 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2669 if (!nested_vmx_allowed(vcpu))
2670 return 1;
609e36d3 2671 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL		 2672 case MSR_IA32_XSS:
2673 if (!vmx_xsaves_supported())
2674 return 1;
609e36d3 2675 msr_info->data = vcpu->arch.ia32_xss;
20300099 2676 break;
4e47c7a6
SY		 2677 case MSR_TSC_AUX:
2678 if (!to_vmx(vcpu)->rdtscp_enabled)
2679 return 1;
2680 /* Otherwise falls through */
6aa8b732 2681 default:
609e36d3 2682 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 2683 if (msr) {
609e36d3 2684 msr_info->data = msr->data;
3bab1f5d 2685 break;
6aa8b732 2686 }
609e36d3 2687 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2688 }
2689
6aa8b732
AK		 2690 return 0;
2691}
2692
cae50139
JK		 2693static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2694
6aa8b732
AK		 2695/*
2696 * Writes msr value into into the appropriate "register".
2697 * Returns 0 on success, non-0 otherwise.
2698 * Assumes vcpu_load() was already called.
2699 */
8fe8ab46 2700static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2701{
a2fa3e9f 2702 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2703 struct shared_msr_entry *msr;
2cc51560 2704 int ret = 0;
8fe8ab46
WA		 2705 u32 msr_index = msr_info->index;
2706 u64 data = msr_info->data;
2cc51560 2707
6aa8b732 2708 switch (msr_index) {
3bab1f5d 2709 case MSR_EFER:
8fe8ab46 2710 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2711 break;
16175a79 2712#ifdef CONFIG_X86_64
6aa8b732 2713 case MSR_FS_BASE:
2fb92db1 2714 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2715 vmcs_writel(GUEST_FS_BASE, data);
2716 break;
2717 case MSR_GS_BASE:
2fb92db1 2718 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2719 vmcs_writel(GUEST_GS_BASE, data);
2720 break;
44ea2b17
AK		 2721 case MSR_KERNEL_GS_BASE:
2722 vmx_load_host_state(vmx);
2723 vmx->msr_guest_kernel_gs_base = data;
2724 break;
6aa8b732
AK		 2725#endif
2726 case MSR_IA32_SYSENTER_CS:
2727 vmcs_write32(GUEST_SYSENTER_CS, data);
2728 break;
2729 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2730 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2731 break;
2732 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2733 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2734 break;
0dd376e7 2735 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2736 if (!vmx_mpx_supported())
2737 return 1;
0dd376e7
LJ		 2738 vmcs_write64(GUEST_BNDCFGS, data);
2739 break;
af24a4e4 2740 case MSR_IA32_TSC:
8fe8ab46 2741 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2742 break;
468d472f
SY		 2743 case MSR_IA32_CR_PAT:
2744 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2745 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2746 return 1;
468d472f
SY		 2747 vmcs_write64(GUEST_IA32_PAT, data);
2748 vcpu->arch.pat = data;
2749 break;
2750 }
8fe8ab46 2751 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2752 break;
ba904635
WA		 2753 case MSR_IA32_TSC_ADJUST:
2754 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2755 break;
cae50139
JK		 2756 case MSR_IA32_FEATURE_CONTROL:
2757 if (!nested_vmx_allowed(vcpu) ||
2758 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2759 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2760 return 1;
2761 vmx->nested.msr_ia32_feature_control = data;
2762 if (msr_info->host_initiated && data == 0)
2763 vmx_leave_nested(vcpu);
2764 break;
2765 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2766 return 1; /* they are read-only */
20300099
WL		 2767 case MSR_IA32_XSS:
2768 if (!vmx_xsaves_supported())
2769 return 1;
2770 /*
2771 * The only supported bit as of Skylake is bit 8, but
2772 * it is not supported on KVM.
2773 */
2774 if (data != 0)
2775 return 1;
2776 vcpu->arch.ia32_xss = data;
2777 if (vcpu->arch.ia32_xss != host_xss)
2778 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2779 vcpu->arch.ia32_xss, host_xss);
2780 else
2781 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2782 break;
4e47c7a6
SY		 2783 case MSR_TSC_AUX:
2784 if (!vmx->rdtscp_enabled)
2785 return 1;
2786 /* Check reserved bit, higher 32 bits should be zero */
2787 if ((data >> 32) != 0)
2788 return 1;
2789 /* Otherwise falls through */
6aa8b732 2790 default:
8b9cf98c 2791 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2792 if (msr) {
8b3c3104 2793 u64 old_msr_data = msr->data;
3bab1f5d 2794 msr->data = data;
2225fd56
AK		 2795 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2796 preempt_disable();
8b3c3104
AH		 2797 ret = kvm_set_shared_msr(msr->index, msr->data,
2798 msr->mask);
2225fd56 2799 preempt_enable();
8b3c3104
AH		 2800 if (ret)
2801 msr->data = old_msr_data;
2225fd56 2802 }
3bab1f5d 2803 break;
6aa8b732 2804 }
8fe8ab46 2805 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2806 }
2807
2cc51560 2808 return ret;
6aa8b732
AK		 2809}
2810
5fdbf976 2811static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2812{
5fdbf976
MT		 2813 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2814 switch (reg) {
2815 case VCPU_REGS_RSP:
2816 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2817 break;
2818 case VCPU_REGS_RIP:
2819 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2820 break;
6de4f3ad
AK		 2821 case VCPU_EXREG_PDPTR:
2822 if (enable_ept)
2823 ept_save_pdptrs(vcpu);
2824 break;
5fdbf976
MT		 2825 default:
2826 break;
2827 }
6aa8b732
AK		 2828}
2829
6aa8b732
AK		 2830static __init int cpu_has_kvm_support(void)
2831{
6210e37b 2832 return cpu_has_vmx();
6aa8b732
AK		 2833}
2834
2835static __init int vmx_disabled_by_bios(void)
2836{
2837 u64 msr;
2838
2839 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2840 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2841 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2842 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2843 && tboot_enabled())
2844 return 1;
23f3e991 2845 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2846 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2847 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2848 && !tboot_enabled()) {
2849 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2850 "activate TXT before enabling KVM\n");
cafd6659 2851 return 1;
f9335afe 2852 }
23f3e991
JC		 2853 /* launched w/o TXT and VMX disabled */
2854 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2855 && !tboot_enabled())
2856 return 1;
cafd6659
SW		 2857 }
2858
2859 return 0;
6aa8b732
AK		 2860}
2861
7725b894
DX		 2862static void kvm_cpu_vmxon(u64 addr)
2863{
2864 asm volatile (ASM_VMX_VMXON_RAX
2865 : : "a"(&addr), "m"(addr)
2866 : "memory", "cc");
2867}
2868
13a34e06 2869static int hardware_enable(void)
6aa8b732
AK		 2870{
2871 int cpu = raw_smp_processor_id();
2872 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2873 u64 old, test_bits;
6aa8b732 2874
1e02ce4c 2875 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2876 return -EBUSY;
2877
d462b819 2878 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2879
2880 /*
2881 * Now we can enable the vmclear operation in kdump
2882 * since the loaded_vmcss_on_cpu list on this cpu
2883 * has been initialized.
2884 *
2885 * Though the cpu is not in VMX operation now, there
2886 * is no problem to enable the vmclear operation
2887 * for the loaded_vmcss_on_cpu list is empty!
2888 */
2889 crash_enable_local_vmclear(cpu);
2890
6aa8b732 2891 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2892
2893 test_bits = FEATURE_CONTROL_LOCKED;
2894 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2895 if (tboot_enabled())
2896 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2897
2898 if ((old & test_bits) != test_bits) {
6aa8b732 2899 /* enable and lock */
cafd6659
SW		 2900 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2901 }
375074cc 2902 cr4_set_bits(X86_CR4_VMXE);
10474ae8 2903
4610c9cc
DX		 2904 if (vmm_exclusive) {
2905 kvm_cpu_vmxon(phys_addr);
2906 ept_sync_global();
2907 }
10474ae8 2908
89cbc767 2909 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2910
10474ae8 2911 return 0;
6aa8b732
AK		 2912}
2913
d462b819 2914static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2915{
2916 int cpu = raw_smp_processor_id();
d462b819 2917 struct loaded_vmcs *v, *n;
543e4243 2918
d462b819
NHE		 2919 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2920 loaded_vmcss_on_cpu_link)
2921 __loaded_vmcs_clear(v);
543e4243
AK		 2922}
2923
710ff4a8
EH		 2924
2925/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2926 * tricks.
2927 */
2928static void kvm_cpu_vmxoff(void)
6aa8b732 2929{
4ecac3fd 2930 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2931}
2932
13a34e06 2933static void hardware_disable(void)
710ff4a8 2934{
4610c9cc 2935 if (vmm_exclusive) {
d462b819 2936 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2937 kvm_cpu_vmxoff();
2938 }
375074cc 2939 cr4_clear_bits(X86_CR4_VMXE);
710ff4a8
EH		 2940}
2941
1c3d14fe 2942static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2943 u32 msr, u32 *result)
1c3d14fe
YS		 2944{
2945 u32 vmx_msr_low, vmx_msr_high;
2946 u32 ctl = ctl_min | ctl_opt;
2947
2948 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2949
2950 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2951 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2952
2953 /* Ensure minimum (required) set of control bits are supported. */
2954 if (ctl_min & ~ctl)
002c7f7c 2955 return -EIO;
1c3d14fe
YS		 2956
2957 *result = ctl;
2958 return 0;
2959}
2960
110312c8
AK		 2961static __init bool allow_1_setting(u32 msr, u32 ctl)
2962{
2963 u32 vmx_msr_low, vmx_msr_high;
2964
2965 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2966 return vmx_msr_high & ctl;
2967}
2968
002c7f7c 2969static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2970{
2971 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2972 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2973 u32 _pin_based_exec_control = 0;
2974 u32 _cpu_based_exec_control = 0;
f78e0e2e 2975 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2976 u32 _vmexit_control = 0;
2977 u32 _vmentry_control = 0;
2978
10166744 2979 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2980#ifdef CONFIG_X86_64
2981 CPU_BASED_CR8_LOAD_EXITING |
2982 CPU_BASED_CR8_STORE_EXITING |
2983#endif
d56f546d
SY		 2984 CPU_BASED_CR3_LOAD_EXITING |
2985 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2986 CPU_BASED_USE_IO_BITMAPS |
2987 CPU_BASED_MOV_DR_EXITING |
a7052897 2988 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2989 CPU_BASED_MWAIT_EXITING |
2990 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2991 CPU_BASED_INVLPG_EXITING |
2992 CPU_BASED_RDPMC_EXITING;
443381a8 2993
f78e0e2e 2994 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2995 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2996 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2997 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2998 &_cpu_based_exec_control) < 0)
002c7f7c 2999 return -EIO;
6e5d865c
YS		 3000#ifdef CONFIG_X86_64
3001 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3002 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3003 ~CPU_BASED_CR8_STORE_EXITING;
3004#endif
f78e0e2e 3005 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 3006 min2 = 0;
3007 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3008 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3009 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3010 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3011 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3012 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3013 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3014 SECONDARY_EXEC_RDTSCP |
83d4c286 3015 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3016 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3017 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3018 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 3019 SECONDARY_EXEC_XSAVES |
8b3e34e4
XG		 3020 SECONDARY_EXEC_ENABLE_PML |
3021 SECONDARY_EXEC_PCOMMIT;
d56f546d
SY		 3022 if (adjust_vmx_controls(min2, opt2,
3023 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3024 &_cpu_based_2nd_exec_control) < 0)
3025 return -EIO;
3026 }
3027#ifndef CONFIG_X86_64
3028 if (!(_cpu_based_2nd_exec_control &
3029 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3030 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3031#endif
83d4c286
YZ		 3032
3033 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3034 _cpu_based_2nd_exec_control &= ~(
8d14695f 3035 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3036 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3037 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3038
d56f546d 3039 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3040 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3041 enabled */
5fff7d27
GN		 3042 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3043 CPU_BASED_CR3_STORE_EXITING |
3044 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3045 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3046 vmx_capability.ept, vmx_capability.vpid);
3047 }
1c3d14fe 3048
81908bf4 3049 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3050#ifdef CONFIG_X86_64
3051 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3052#endif
a547c6db 3053 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3054 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3055 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3056 &_vmexit_control) < 0)
002c7f7c 3057 return -EIO;
1c3d14fe 3058
01e439be
YZ		 3059 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3060 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3061 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3062 &_pin_based_exec_control) < 0)
3063 return -EIO;
3064
3065 if (!(_cpu_based_2nd_exec_control &
3066 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3067 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3068 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3069
c845f9c6 3070 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3071 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3072 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3073 &_vmentry_control) < 0)
002c7f7c 3074 return -EIO;
6aa8b732 3075
c68876fd 3076 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3077
3078 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3079 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3080 return -EIO;
1c3d14fe
YS		 3081
3082#ifdef CONFIG_X86_64
3083 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3084 if (vmx_msr_high & (1u<<16))
002c7f7c 3085 return -EIO;
1c3d14fe
YS		 3086#endif
3087
3088 /* Require Write-Back (WB) memory type for VMCS accesses. */
3089 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3090 return -EIO;
1c3d14fe 3091
002c7f7c
YS		 3092 vmcs_conf->size = vmx_msr_high & 0x1fff;
3093 vmcs_conf->order = get_order(vmcs_config.size);
3094 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3095
002c7f7c
YS		 3096 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3097 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3098 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3099 vmcs_conf->vmexit_ctrl = _vmexit_control;
3100 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3101
110312c8
AK		 3102 cpu_has_load_ia32_efer =
3103 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3104 VM_ENTRY_LOAD_IA32_EFER)
3105 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3106 VM_EXIT_LOAD_IA32_EFER);
3107
8bf00a52
GN		 3108 cpu_has_load_perf_global_ctrl =
3109 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3110 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3111 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3112 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3113
3114 /*
3115 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3116 * but due to arrata below it can't be used. Workaround is to use
3117 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3118 *
3119 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3120 *
3121 * AAK155 (model 26)
3122 * AAP115 (model 30)
3123 * AAT100 (model 37)
3124 * BC86,AAY89,BD102 (model 44)
3125 * BA97 (model 46)
3126 *
3127 */
3128 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3129 switch (boot_cpu_data.x86_model) {
3130 case 26:
3131 case 30:
3132 case 37:
3133 case 44:
3134 case 46:
3135 cpu_has_load_perf_global_ctrl = false;
3136 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3137 "does not work properly. Using workaround\n");
3138 break;
3139 default:
3140 break;
3141 }
3142 }
3143
20300099
WL		 3144 if (cpu_has_xsaves)
3145 rdmsrl(MSR_IA32_XSS, host_xss);
3146
1c3d14fe 3147 return 0;
c68876fd 3148}
6aa8b732
AK		 3149
3150static struct vmcs *alloc_vmcs_cpu(int cpu)
3151{
3152 int node = cpu_to_node(cpu);
3153 struct page *pages;
3154 struct vmcs *vmcs;
3155
96db800f 3156 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3157 if (!pages)
3158 return NULL;
3159 vmcs = page_address(pages);
1c3d14fe
YS		 3160 memset(vmcs, 0, vmcs_config.size);
3161 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3162 return vmcs;
3163}
3164
3165static struct vmcs *alloc_vmcs(void)
3166{
d3b2c338 3167 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3168}
3169
3170static void free_vmcs(struct vmcs *vmcs)
3171{
1c3d14fe 3172 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3173}
3174
d462b819
NHE		 3175/*
3176 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3177 */
3178static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3179{
3180 if (!loaded_vmcs->vmcs)
3181 return;
3182 loaded_vmcs_clear(loaded_vmcs);
3183 free_vmcs(loaded_vmcs->vmcs);
3184 loaded_vmcs->vmcs = NULL;
3185}
3186
39959588 3187static void free_kvm_area(void)
6aa8b732
AK		 3188{
3189 int cpu;
3190
3230bb47 3191 for_each_possible_cpu(cpu) {
6aa8b732 3192 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3193 per_cpu(vmxarea, cpu) = NULL;
3194 }
6aa8b732
AK		 3195}
3196
fe2b201b
BD		 3197static void init_vmcs_shadow_fields(void)
3198{
3199 int i, j;
3200
3201 /* No checks for read only fields yet */
3202
3203 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3204 switch (shadow_read_write_fields[i]) {
3205 case GUEST_BNDCFGS:
3206 if (!vmx_mpx_supported())
3207 continue;
3208 break;
3209 default:
3210 break;
3211 }
3212
3213 if (j < i)
3214 shadow_read_write_fields[j] =
3215 shadow_read_write_fields[i];
3216 j++;
3217 }
3218 max_shadow_read_write_fields = j;
3219
3220 /* shadowed fields guest access without vmexit */
3221 for (i = 0; i < max_shadow_read_write_fields; i++) {
3222 clear_bit(shadow_read_write_fields[i],
3223 vmx_vmwrite_bitmap);
3224 clear_bit(shadow_read_write_fields[i],
3225 vmx_vmread_bitmap);
3226 }
3227 for (i = 0; i < max_shadow_read_only_fields; i++)
3228 clear_bit(shadow_read_only_fields[i],
3229 vmx_vmread_bitmap);
3230}
3231
6aa8b732
AK		 3232static __init int alloc_kvm_area(void)
3233{
3234 int cpu;
3235
3230bb47 3236 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3237 struct vmcs *vmcs;
3238
3239 vmcs = alloc_vmcs_cpu(cpu);
3240 if (!vmcs) {
3241 free_kvm_area();
3242 return -ENOMEM;
3243 }
3244
3245 per_cpu(vmxarea, cpu) = vmcs;
3246 }
3247 return 0;
3248}
3249
14168786
GN		 3250static bool emulation_required(struct kvm_vcpu *vcpu)
3251{
3252 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3253}
3254
91b0aa2c 3255static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3256 struct kvm_segment *save)
6aa8b732 3257{
d99e4152
GN		 3258 if (!emulate_invalid_guest_state) {
3259 /*
3260 * CS and SS RPL should be equal during guest entry according
3261 * to VMX spec, but in reality it is not always so. Since vcpu
3262 * is in the middle of the transition from real mode to
3263 * protected mode it is safe to assume that RPL 0 is a good
3264 * default value.
3265 */
3266 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 3267 save->selector &= ~SEGMENT_RPL_MASK;
3268 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3269 save->s = 1;
6aa8b732 3270 }
d99e4152 3271 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3272}
3273
3274static void enter_pmode(struct kvm_vcpu *vcpu)
3275{
3276 unsigned long flags;
a89a8fb9 3277 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3278
d99e4152
GN		 3279 /*
3280 * Update real mode segment cache. It may be not up-to-date if sement
3281 * register was written while vcpu was in a guest mode.
3282 */
3283 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3284 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3285 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3286 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3287 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3288 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3289
7ffd92c5 3290 vmx->rmode.vm86_active = 0;
6aa8b732 3291
2fb92db1
AK		 3292 vmx_segment_cache_clear(vmx);
3293
f5f7b2fe 3294 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3295
3296 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3297 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3298 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3299 vmcs_writel(GUEST_RFLAGS, flags);
3300
66aee91a
RR		 3301 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3302 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3303
3304 update_exception_bitmap(vcpu);
3305
91b0aa2c
GN		 3306 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3307 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3308 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3309 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3310 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3311 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3312}
3313
f5f7b2fe 3314static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3315{
772e0318 3316 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3317 struct kvm_segment var = *save;
3318
3319 var.dpl = 0x3;
3320 if (seg == VCPU_SREG_CS)
3321 var.type = 0x3;
3322
3323 if (!emulate_invalid_guest_state) {
3324 var.selector = var.base >> 4;
3325 var.base = var.base & 0xffff0;
3326 var.limit = 0xffff;
3327 var.g = 0;
3328 var.db = 0;
3329 var.present = 1;
3330 var.s = 1;
3331 var.l = 0;
3332 var.unusable = 0;
3333 var.type = 0x3;
3334 var.avl = 0;
3335 if (save->base & 0xf)
3336 printk_once(KERN_WARNING "kvm: segment base is not "
3337 "paragraph aligned when entering "
3338 "protected mode (seg=%d)", seg);
3339 }
6aa8b732 3340
d99e4152
GN		 3341 vmcs_write16(sf->selector, var.selector);
3342 vmcs_write32(sf->base, var.base);
3343 vmcs_write32(sf->limit, var.limit);
3344 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3345}
3346
3347static void enter_rmode(struct kvm_vcpu *vcpu)
3348{
3349 unsigned long flags;
a89a8fb9 3350 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3351
f5f7b2fe
AK		 3352 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3353 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3354 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3355 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3356 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3357 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3358 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3359
7ffd92c5 3360 vmx->rmode.vm86_active = 1;
6aa8b732 3361
776e58ea
GN		 3362 /*
3363 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3364 * vcpu. Warn the user that an update is overdue.
776e58ea 3365 */
4918c6ca 3366 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3367 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3368 "called before entering vcpu\n");
776e58ea 3369
2fb92db1
AK		 3370 vmx_segment_cache_clear(vmx);
3371
4918c6ca 3372 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3373 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3374 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3375
3376 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3377 vmx->rmode.save_rflags = flags;
6aa8b732 3378
053de044 3379 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3380
3381 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3382 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3383 update_exception_bitmap(vcpu);
3384
d99e4152
GN		 3385 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3386 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3387 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3388 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3389 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3390 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3391
8668a3c4 3392 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3393}
3394
401d10de
AS		 3395static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3396{
3397 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3398 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3399
3400 if (!msr)
3401 return;
401d10de 3402
44ea2b17
AK		 3403 /*
3404 * Force kernel_gs_base reloading before EFER changes, as control
3405 * of this msr depends on is_long_mode().
3406 */
3407 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3408 vcpu->arch.efer = efer;
401d10de 3409 if (efer & EFER_LMA) {
2961e876 3410 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3411 msr->data = efer;
3412 } else {
2961e876 3413 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3414
3415 msr->data = efer & ~EFER_LME;
3416 }
3417 setup_msrs(vmx);
3418}
3419
05b3e0c2 3420#ifdef CONFIG_X86_64
6aa8b732
AK		 3421
3422static void enter_lmode(struct kvm_vcpu *vcpu)
3423{
3424 u32 guest_tr_ar;
3425
2fb92db1
AK		 3426 vmx_segment_cache_clear(to_vmx(vcpu));
3427
6aa8b732 3428 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 3429 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3430 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3431 __func__);
6aa8b732 3432 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 3433 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3434 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 3435 }
da38f438 3436 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3437}
3438
3439static void exit_lmode(struct kvm_vcpu *vcpu)
3440{
2961e876 3441 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3442 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3443}
3444
3445#endif
3446
2384d2b3
SY		 3447static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3448{
b9d762fa 3449 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3450 if (enable_ept) {
3451 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3452 return;
4e1096d2 3453 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3454 }
2384d2b3
SY		 3455}
3456
e8467fda
AK		 3457static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3458{
3459 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3460
3461 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3462 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3463}
3464
aff48baa
AK		 3465static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3466{
3467 if (enable_ept && is_paging(vcpu))
3468 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3469 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3470}
3471
25c4c276 3472static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3473{
fc78f519
AK		 3474 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3475
3476 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3477 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3478}
3479
1439442c
SY		 3480static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3481{
d0d538b9
GN		 3482 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3483
6de4f3ad
AK		 3484 if (!test_bit(VCPU_EXREG_PDPTR,
3485 (unsigned long *)&vcpu->arch.regs_dirty))
3486 return;
3487
1439442c 3488 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3489 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3490 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3491 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3492 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3493 }
3494}
3495
8f5d549f
AK		 3496static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3497{
d0d538b9
GN		 3498 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3499
8f5d549f 3500 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3501 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3502 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3503 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3504 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3505 }
6de4f3ad
AK		 3506
3507 __set_bit(VCPU_EXREG_PDPTR,
3508 (unsigned long *)&vcpu->arch.regs_avail);
3509 __set_bit(VCPU_EXREG_PDPTR,
3510 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3511}
3512
5e1746d6 3513static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3514
3515static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3516 unsigned long cr0,
3517 struct kvm_vcpu *vcpu)
3518{
5233dd51
MT		 3519 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3520 vmx_decache_cr3(vcpu);
1439442c
SY		 3521 if (!(cr0 & X86_CR0_PG)) {
3522 /* From paging/starting to nonpaging */
3523 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3524 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3525 (CPU_BASED_CR3_LOAD_EXITING |
3526 CPU_BASED_CR3_STORE_EXITING));
3527 vcpu->arch.cr0 = cr0;
fc78f519 3528 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3529 } else if (!is_paging(vcpu)) {
3530 /* From nonpaging to paging */
3531 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3532 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3533 ~(CPU_BASED_CR3_LOAD_EXITING |
3534 CPU_BASED_CR3_STORE_EXITING));
3535 vcpu->arch.cr0 = cr0;
fc78f519 3536 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3537 }
95eb84a7
SY		 3538
3539 if (!(cr0 & X86_CR0_WP))
3540 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3541}
3542
6aa8b732
AK		 3543static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3544{
7ffd92c5 3545 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3546 unsigned long hw_cr0;
3547
5037878e 3548 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3549 if (enable_unrestricted_guest)
5037878e 3550 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3551 else {
5037878e 3552 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3553
218e763f
GN		 3554 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3555 enter_pmode(vcpu);
6aa8b732 3556
218e763f
GN		 3557 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3558 enter_rmode(vcpu);
3559 }
6aa8b732 3560
05b3e0c2 3561#ifdef CONFIG_X86_64
f6801dff 3562 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3563 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3564 enter_lmode(vcpu);
707d92fa 3565 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3566 exit_lmode(vcpu);
3567 }
3568#endif
3569
089d034e 3570 if (enable_ept)
1439442c
SY		 3571 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3572
02daab21 3573 if (!vcpu->fpu_active)
81231c69 3574 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3575
6aa8b732 3576 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3577 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3578 vcpu->arch.cr0 = cr0;
14168786
GN		 3579
3580 /* depends on vcpu->arch.cr0 to be set to a new value */
3581 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3582}
3583
1439442c
SY		 3584static u64 construct_eptp(unsigned long root_hpa)
3585{
3586 u64 eptp;
3587
3588 /* TODO write the value reading from MSR */
3589 eptp = VMX_EPT_DEFAULT_MT |
3590 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3591 if (enable_ept_ad_bits)
3592 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3593 eptp |= (root_hpa & PAGE_MASK);
3594
3595 return eptp;
3596}
3597
6aa8b732
AK		 3598static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3599{
1439442c
SY		 3600 unsigned long guest_cr3;
3601 u64 eptp;
3602
3603 guest_cr3 = cr3;
089d034e 3604 if (enable_ept) {
1439442c
SY		 3605 eptp = construct_eptp(cr3);
3606 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3607 if (is_paging(vcpu) || is_guest_mode(vcpu))
3608 guest_cr3 = kvm_read_cr3(vcpu);
3609 else
3610 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3611 ept_load_pdptrs(vcpu);
1439442c
SY		 3612 }
3613
2384d2b3 3614 vmx_flush_tlb(vcpu);
1439442c 3615 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3616}
3617
5e1746d6 3618static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3619{
085e68ee
BS		 3620 /*
3621 * Pass through host's Machine Check Enable value to hw_cr4, which
3622 * is in force while we are in guest mode. Do not let guests control
3623 * this bit, even if host CR4.MCE == 0.
3624 */
3625 unsigned long hw_cr4 =
3626 (cr4_read_shadow() & X86_CR4_MCE) |
3627 (cr4 & ~X86_CR4_MCE) |
3628 (to_vmx(vcpu)->rmode.vm86_active ?
3629 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 3630
5e1746d6
NHE		 3631 if (cr4 & X86_CR4_VMXE) {
3632 /*
3633 * To use VMXON (and later other VMX instructions), a guest
3634 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3635 * So basically the check on whether to allow nested VMX
3636 * is here.
3637 */
3638 if (!nested_vmx_allowed(vcpu))
3639 return 1;
1a0d74e6
JK		 3640 }
3641 if (to_vmx(vcpu)->nested.vmxon &&
3642 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3643 return 1;
3644
ad312c7c 3645 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3646 if (enable_ept) {
3647 if (!is_paging(vcpu)) {
3648 hw_cr4 &= ~X86_CR4_PAE;
3649 hw_cr4 |= X86_CR4_PSE;
c08800a5 3650 /*
e1e746b3
FW		 3651 * SMEP/SMAP is disabled if CPU is in non-paging mode
3652 * in hardware. However KVM always uses paging mode to
c08800a5 3653 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3654 * To emulate this behavior, SMEP/SMAP needs to be
3655 * manually disabled when guest switches to non-paging
3656 * mode.
c08800a5 3657 */
e1e746b3 3658 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3659 } else if (!(cr4 & X86_CR4_PAE)) {
3660 hw_cr4 &= ~X86_CR4_PAE;
3661 }
3662 }
1439442c
SY		 3663
3664 vmcs_writel(CR4_READ_SHADOW, cr4);
3665 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3666 return 0;
6aa8b732
AK		 3667}
3668
6aa8b732
AK		 3669static void vmx_get_segment(struct kvm_vcpu *vcpu,
3670 struct kvm_segment *var, int seg)
3671{
a9179499 3672 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3673 u32 ar;
3674
c6ad1153 3675 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3676 *var = vmx->rmode.segs[seg];
a9179499 3677 if (seg == VCPU_SREG_TR
2fb92db1 3678 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3679 return;
1390a28b
AK		 3680 var->base = vmx_read_guest_seg_base(vmx, seg);
3681 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3682 return;
a9179499 3683 }
2fb92db1
AK		 3684 var->base = vmx_read_guest_seg_base(vmx, seg);
3685 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3686 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3687 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3688 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3689 var->type = ar & 15;
3690 var->s = (ar >> 4) & 1;
3691 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3692 /*
3693 * Some userspaces do not preserve unusable property. Since usable
3694 * segment has to be present according to VMX spec we can use present
3695 * property to amend userspace bug by making unusable segment always
3696 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3697 * segment as unusable.
3698 */
3699 var->present = !var->unusable;
6aa8b732
AK		 3700 var->avl = (ar >> 12) & 1;
3701 var->l = (ar >> 13) & 1;
3702 var->db = (ar >> 14) & 1;
3703 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3704}
3705
a9179499
AK		 3706static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3707{
a9179499
AK		 3708 struct kvm_segment s;
3709
3710 if (to_vmx(vcpu)->rmode.vm86_active) {
3711 vmx_get_segment(vcpu, &s, seg);
3712 return s.base;
3713 }
2fb92db1 3714 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3715}
3716
b09408d0 3717static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3718{
b09408d0
MT		 3719 struct vcpu_vmx *vmx = to_vmx(vcpu);
3720
ae9fedc7 3721 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3722 return 0;
ae9fedc7
PB		 3723 else {
3724 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3725 return VMX_AR_DPL(ar);
69c73028 3726 }
69c73028
AK		 3727}
3728
653e3108 3729static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3730{
6aa8b732
AK		 3731 u32 ar;
3732
f0495f9b 3733 if (var->unusable || !var->present)
6aa8b732
AK		 3734 ar = 1 << 16;
3735 else {
3736 ar = var->type & 15;
3737 ar |= (var->s & 1) << 4;
3738 ar |= (var->dpl & 3) << 5;
3739 ar |= (var->present & 1) << 7;
3740 ar |= (var->avl & 1) << 12;
3741 ar |= (var->l & 1) << 13;
3742 ar |= (var->db & 1) << 14;
3743 ar |= (var->g & 1) << 15;
3744 }
653e3108
AK		 3745
3746 return ar;
3747}
3748
3749static void vmx_set_segment(struct kvm_vcpu *vcpu,
3750 struct kvm_segment *var, int seg)
3751{
7ffd92c5 3752 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3753 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3754
2fb92db1
AK		 3755 vmx_segment_cache_clear(vmx);
3756
1ecd50a9
GN		 3757 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3758 vmx->rmode.segs[seg] = *var;
3759 if (seg == VCPU_SREG_TR)
3760 vmcs_write16(sf->selector, var->selector);
3761 else if (var->s)
3762 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3763 goto out;
653e3108 3764 }
1ecd50a9 3765
653e3108
AK		 3766 vmcs_writel(sf->base, var->base);
3767 vmcs_write32(sf->limit, var->limit);
3768 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3769
3770 /*
3771 * Fix the "Accessed" bit in AR field of segment registers for older
3772 * qemu binaries.
3773 * IA32 arch specifies that at the time of processor reset the
3774 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3775 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3776 * state vmexit when "unrestricted guest" mode is turned on.
3777 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3778 * tree. Newer qemu binaries with that qemu fix would not need this
3779 * kvm hack.
3780 */
3781 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3782 var->type |= 0x1; /* Accessed */
3a624e29 3783
f924d66d 3784 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3785
3786out:
98eb2f8b 3787 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3788}
3789
6aa8b732
AK		 3790static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3791{
2fb92db1 3792 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3793
3794 *db = (ar >> 14) & 1;
3795 *l = (ar >> 13) & 1;
3796}
3797
89a27f4d 3798static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3799{
89a27f4d
GN		 3800 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3801 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3802}
3803
89a27f4d 3804static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3805{
89a27f4d
GN		 3806 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3807 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3808}
3809
89a27f4d 3810static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3811{
89a27f4d
GN		 3812 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3813 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3814}
3815
89a27f4d 3816static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3817{
89a27f4d
GN		 3818 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3819 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3820}
3821
648dfaa7
MG		 3822static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3823{
3824 struct kvm_segment var;
3825 u32 ar;
3826
3827 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3828 var.dpl = 0x3;
0647f4aa
GN		 3829 if (seg == VCPU_SREG_CS)
3830 var.type = 0x3;
648dfaa7
MG		 3831 ar = vmx_segment_access_rights(&var);
3832
3833 if (var.base != (var.selector << 4))
3834 return false;
89efbed0 3835 if (var.limit != 0xffff)
648dfaa7 3836 return false;
07f42f5f 3837 if (ar != 0xf3)
648dfaa7
MG		 3838 return false;
3839
3840 return true;
3841}
3842
3843static bool code_segment_valid(struct kvm_vcpu *vcpu)
3844{
3845 struct kvm_segment cs;
3846 unsigned int cs_rpl;
3847
3848 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3849 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3850
1872a3f4
AK		 3851 if (cs.unusable)
3852 return false;
4d283ec9 3853 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3854 return false;
3855 if (!cs.s)
3856 return false;
4d283ec9 3857 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3858 if (cs.dpl > cs_rpl)
3859 return false;
1872a3f4 3860 } else {
648dfaa7
MG		 3861 if (cs.dpl != cs_rpl)
3862 return false;
3863 }
3864 if (!cs.present)
3865 return false;
3866
3867 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3868 return true;
3869}
3870
3871static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3872{
3873 struct kvm_segment ss;
3874 unsigned int ss_rpl;
3875
3876 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3877 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3878
1872a3f4
AK		 3879 if (ss.unusable)
3880 return true;
3881 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3882 return false;
3883 if (!ss.s)
3884 return false;
3885 if (ss.dpl != ss_rpl) /* DPL != RPL */
3886 return false;
3887 if (!ss.present)
3888 return false;
3889
3890 return true;
3891}
3892
3893static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3894{
3895 struct kvm_segment var;
3896 unsigned int rpl;
3897
3898 vmx_get_segment(vcpu, &var, seg);
b32a9918 3899 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3900
1872a3f4
AK		 3901 if (var.unusable)
3902 return true;
648dfaa7
MG		 3903 if (!var.s)
3904 return false;
3905 if (!var.present)
3906 return false;
4d283ec9 3907 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3908 if (var.dpl < rpl) /* DPL < RPL */
3909 return false;
3910 }
3911
3912 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3913 * rights flags
3914 */
3915 return true;
3916}
3917
3918static bool tr_valid(struct kvm_vcpu *vcpu)
3919{
3920 struct kvm_segment tr;
3921
3922 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3923
1872a3f4
AK		 3924 if (tr.unusable)
3925 return false;
b32a9918 3926 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3927 return false;
1872a3f4 3928 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3929 return false;
3930 if (!tr.present)
3931 return false;
3932
3933 return true;
3934}
3935
3936static bool ldtr_valid(struct kvm_vcpu *vcpu)
3937{
3938 struct kvm_segment ldtr;
3939
3940 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3941
1872a3f4
AK		 3942 if (ldtr.unusable)
3943 return true;
b32a9918 3944 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3945 return false;
3946 if (ldtr.type != 2)
3947 return false;
3948 if (!ldtr.present)
3949 return false;
3950
3951 return true;
3952}
3953
3954static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3955{
3956 struct kvm_segment cs, ss;
3957
3958 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3959 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3960
b32a9918
NA		 3961 return ((cs.selector & SEGMENT_RPL_MASK) ==
3962 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3963}
3964
3965/*
3966 * Check if guest state is valid. Returns true if valid, false if
3967 * not.
3968 * We assume that registers are always usable
3969 */
3970static bool guest_state_valid(struct kvm_vcpu *vcpu)
3971{
c5e97c80
GN		 3972 if (enable_unrestricted_guest)
3973 return true;
3974
648dfaa7 3975 /* real mode guest state checks */
f13882d8 3976 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3977 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3978 return false;
3979 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3980 return false;
3981 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3982 return false;
3983 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3984 return false;
3985 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3986 return false;
3987 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3988 return false;
3989 } else {
3990 /* protected mode guest state checks */
3991 if (!cs_ss_rpl_check(vcpu))
3992 return false;
3993 if (!code_segment_valid(vcpu))
3994 return false;
3995 if (!stack_segment_valid(vcpu))
3996 return false;
3997 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3998 return false;
3999 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4000 return false;
4001 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4002 return false;
4003 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4004 return false;
4005 if (!tr_valid(vcpu))
4006 return false;
4007 if (!ldtr_valid(vcpu))
4008 return false;
4009 }
4010 /* TODO:
4011 * - Add checks on RIP
4012 * - Add checks on RFLAGS
4013 */
4014
4015 return true;
4016}
4017
d77c26fc 4018static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4019{
40dcaa9f 4020 gfn_t fn;
195aefde 4021 u16 data = 0;
1f755a82 4022 int idx, r;
6aa8b732 4023
40dcaa9f 4024 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4025 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 4026 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4027 if (r < 0)
10589a46 4028 goto out;
195aefde 4029 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4030 r = kvm_write_guest_page(kvm, fn++, &data,
4031 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4032 if (r < 0)
10589a46 4033 goto out;
195aefde
IE		 4034 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4035 if (r < 0)
10589a46 4036 goto out;
195aefde
IE		 4037 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4038 if (r < 0)
10589a46 4039 goto out;
195aefde 4040 data = ~0;
10589a46
MT		 4041 r = kvm_write_guest_page(kvm, fn, &data,
4042 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4043 sizeof(u8));
10589a46 4044out:
40dcaa9f 4045 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4046 return r;
6aa8b732
AK		 4047}
4048
b7ebfb05
SY		 4049static int init_rmode_identity_map(struct kvm *kvm)
4050{
f51770ed 4051 int i, idx, r = 0;
b7ebfb05
SY		 4052 pfn_t identity_map_pfn;
4053 u32 tmp;
4054
089d034e 4055 if (!enable_ept)
f51770ed 4056 return 0;
a255d479
TC		 4057
4058 /* Protect kvm->arch.ept_identity_pagetable_done. */
4059 mutex_lock(&kvm->slots_lock);
4060
f51770ed 4061 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4062 goto out2;
a255d479 4063
b927a3ce 4064 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4065
4066 r = alloc_identity_pagetable(kvm);
f51770ed 4067 if (r < 0)
a255d479
TC		 4068 goto out2;
4069
40dcaa9f 4070 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4071 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4072 if (r < 0)
4073 goto out;
4074 /* Set up identity-mapping pagetable for EPT in real mode */
4075 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4076 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4077 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4078 r = kvm_write_guest_page(kvm, identity_map_pfn,
4079 &tmp, i * sizeof(tmp), sizeof(tmp));
4080 if (r < 0)
4081 goto out;
4082 }
4083 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4084
b7ebfb05 4085out:
40dcaa9f 4086 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4087
4088out2:
4089 mutex_unlock(&kvm->slots_lock);
f51770ed 4090 return r;
b7ebfb05
SY		 4091}
4092
6aa8b732
AK		 4093static void seg_setup(int seg)
4094{
772e0318 4095 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4096 unsigned int ar;
6aa8b732
AK		 4097
4098 vmcs_write16(sf->selector, 0);
4099 vmcs_writel(sf->base, 0);
4100 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4101 ar = 0x93;
4102 if (seg == VCPU_SREG_CS)
4103 ar |= 0x08; /* code segment */
3a624e29
NK		 4104
4105 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4106}
4107
f78e0e2e
SY		 4108static int alloc_apic_access_page(struct kvm *kvm)
4109{
4484141a 4110 struct page *page;
f78e0e2e
SY		 4111 struct kvm_userspace_memory_region kvm_userspace_mem;
4112 int r = 0;
4113
79fac95e 4114 mutex_lock(&kvm->slots_lock);
c24ae0dc 4115 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4116 goto out;
4117 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4118 kvm_userspace_mem.flags = 0;
73a6d941 4119 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4120 kvm_userspace_mem.memory_size = PAGE_SIZE;
9da0e4d5 4121 r = __x86_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4122 if (r)
4123 goto out;
72dc67a6 4124
73a6d941 4125 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4126 if (is_error_page(page)) {
4127 r = -EFAULT;
4128 goto out;
4129 }
4130
c24ae0dc
TC		 4131 /*
4132 * Do not pin the page in memory, so that memory hot-unplug
4133 * is able to migrate it.
4134 */
4135 put_page(page);
4136 kvm->arch.apic_access_page_done = true;
f78e0e2e 4137out:
79fac95e 4138 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4139 return r;
4140}
4141
b7ebfb05
SY		 4142static int alloc_identity_pagetable(struct kvm *kvm)
4143{
a255d479
TC		 4144 /* Called with kvm->slots_lock held. */
4145
b7ebfb05
SY		 4146 struct kvm_userspace_memory_region kvm_userspace_mem;
4147 int r = 0;
4148
a255d479
TC		 4149 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4150
b7ebfb05
SY		 4151 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4152 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4153 kvm_userspace_mem.guest_phys_addr =
4154 kvm->arch.ept_identity_map_addr;
b7ebfb05 4155 kvm_userspace_mem.memory_size = PAGE_SIZE;
9da0e4d5 4156 r = __x86_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4157
b7ebfb05
SY		 4158 return r;
4159}
4160
2384d2b3
SY		 4161static void allocate_vpid(struct vcpu_vmx *vmx)
4162{
4163 int vpid;
4164
4165 vmx->vpid = 0;
919818ab 4166 if (!enable_vpid)
2384d2b3
SY		 4167 return;
4168 spin_lock(&vmx_vpid_lock);
4169 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4170 if (vpid < VMX_NR_VPIDS) {
4171 vmx->vpid = vpid;
4172 __set_bit(vpid, vmx_vpid_bitmap);
4173 }
4174 spin_unlock(&vmx_vpid_lock);
4175}
4176
cdbecfc3
LJ		 4177static void free_vpid(struct vcpu_vmx *vmx)
4178{
4179 if (!enable_vpid)
4180 return;
4181 spin_lock(&vmx_vpid_lock);
4182 if (vmx->vpid != 0)
4183 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4184 spin_unlock(&vmx_vpid_lock);
4185}
4186
8d14695f
YZ		 4187#define MSR_TYPE_R 1
4188#define MSR_TYPE_W 2
4189static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4190 u32 msr, int type)
25c5f225 4191{
3e7c73e9 4192 int f = sizeof(unsigned long);
25c5f225
SY		 4193
4194 if (!cpu_has_vmx_msr_bitmap())
4195 return;
4196
4197 /*
4198 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4199 * have the write-low and read-high bitmap offsets the wrong way round.
4200 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4201 */
25c5f225 4202 if (msr <= 0x1fff) {
8d14695f
YZ		 4203 if (type & MSR_TYPE_R)
4204 /* read-low */
4205 __clear_bit(msr, msr_bitmap + 0x000 / f);
4206
4207 if (type & MSR_TYPE_W)
4208 /* write-low */
4209 __clear_bit(msr, msr_bitmap + 0x800 / f);
4210
25c5f225
SY		 4211 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4212 msr &= 0x1fff;
8d14695f
YZ		 4213 if (type & MSR_TYPE_R)
4214 /* read-high */
4215 __clear_bit(msr, msr_bitmap + 0x400 / f);
4216
4217 if (type & MSR_TYPE_W)
4218 /* write-high */
4219 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4220
4221 }
4222}
4223
4224static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4225 u32 msr, int type)
4226{
4227 int f = sizeof(unsigned long);
4228
4229 if (!cpu_has_vmx_msr_bitmap())
4230 return;
4231
4232 /*
4233 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4234 * have the write-low and read-high bitmap offsets the wrong way round.
4235 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4236 */
4237 if (msr <= 0x1fff) {
4238 if (type & MSR_TYPE_R)
4239 /* read-low */
4240 __set_bit(msr, msr_bitmap + 0x000 / f);
4241
4242 if (type & MSR_TYPE_W)
4243 /* write-low */
4244 __set_bit(msr, msr_bitmap + 0x800 / f);
4245
4246 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4247 msr &= 0x1fff;
4248 if (type & MSR_TYPE_R)
4249 /* read-high */
4250 __set_bit(msr, msr_bitmap + 0x400 / f);
4251
4252 if (type & MSR_TYPE_W)
4253 /* write-high */
4254 __set_bit(msr, msr_bitmap + 0xc00 / f);
4255
25c5f225 4256 }
25c5f225
SY		 4257}
4258
f2b93280
WV		 4259/*
4260 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4261 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4262 */
4263static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4264 unsigned long *msr_bitmap_nested,
4265 u32 msr, int type)
4266{
4267 int f = sizeof(unsigned long);
4268
4269 if (!cpu_has_vmx_msr_bitmap()) {
4270 WARN_ON(1);
4271 return;
4272 }
4273
4274 /*
4275 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4276 * have the write-low and read-high bitmap offsets the wrong way round.
4277 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4278 */
4279 if (msr <= 0x1fff) {
4280 if (type & MSR_TYPE_R &&
4281 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4282 /* read-low */
4283 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4284
4285 if (type & MSR_TYPE_W &&
4286 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4287 /* write-low */
4288 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4289
4290 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4291 msr &= 0x1fff;
4292 if (type & MSR_TYPE_R &&
4293 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4294 /* read-high */
4295 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4296
4297 if (type & MSR_TYPE_W &&
4298 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4299 /* write-high */
4300 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4301
4302 }
4303}
4304
5897297b
AK		 4305static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4306{
4307 if (!longmode_only)
8d14695f
YZ		 4308 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4309 msr, MSR_TYPE_R | MSR_TYPE_W);
4310 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4311 msr, MSR_TYPE_R | MSR_TYPE_W);
4312}
4313
4314static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4315{
4316 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4317 msr, MSR_TYPE_R);
4318 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4319 msr, MSR_TYPE_R);
4320}
4321
4322static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4323{
4324 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4325 msr, MSR_TYPE_R);
4326 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4327 msr, MSR_TYPE_R);
4328}
4329
4330static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4331{
4332 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4333 msr, MSR_TYPE_W);
4334 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4335 msr, MSR_TYPE_W);
5897297b
AK		 4336}
4337
d50ab6c1
PB		 4338static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4339{
35754c98 4340 return enable_apicv && lapic_in_kernel(vcpu);
d50ab6c1
PB		 4341}
4342
705699a1
WV		 4343static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4344{
4345 struct vcpu_vmx *vmx = to_vmx(vcpu);
4346 int max_irr;
4347 void *vapic_page;
4348 u16 status;
4349
4350 if (vmx->nested.pi_desc &&
4351 vmx->nested.pi_pending) {
4352 vmx->nested.pi_pending = false;
4353 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4354 return 0;
4355
4356 max_irr = find_last_bit(
4357 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4358
4359 if (max_irr == 256)
4360 return 0;
4361
4362 vapic_page = kmap(vmx->nested.virtual_apic_page);
4363 if (!vapic_page) {
4364 WARN_ON(1);
4365 return -ENOMEM;
4366 }
4367 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4368 kunmap(vmx->nested.virtual_apic_page);
4369
4370 status = vmcs_read16(GUEST_INTR_STATUS);
4371 if ((u8)max_irr > ((u8)status & 0xff)) {
4372 status &= ~0xff;
4373 status |= (u8)max_irr;
4374 vmcs_write16(GUEST_INTR_STATUS, status);
4375 }
4376 }
4377 return 0;
4378}
4379
21bc8dc5
RK		 4380static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4381{
4382#ifdef CONFIG_SMP
4383 if (vcpu->mode == IN_GUEST_MODE) {
4384 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4385 POSTED_INTR_VECTOR);
4386 return true;
4387 }
4388#endif
4389 return false;
4390}
4391
705699a1
WV		 4392static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4393 int vector)
4394{
4395 struct vcpu_vmx *vmx = to_vmx(vcpu);
4396
4397 if (is_guest_mode(vcpu) &&
4398 vector == vmx->nested.posted_intr_nv) {
4399 /* the PIR and ON have been set by L1. */
21bc8dc5 4400 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV		 4401 /*
4402 * If a posted intr is not recognized by hardware,
4403 * we will accomplish it in the next vmentry.
4404 */
4405 vmx->nested.pi_pending = true;
4406 kvm_make_request(KVM_REQ_EVENT, vcpu);
4407 return 0;
4408 }
4409 return -1;
4410}
a20ed54d
YZ		 4411/*
4412 * Send interrupt to vcpu via posted interrupt way.
4413 * 1. If target vcpu is running(non-root mode), send posted interrupt
4414 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4415 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4416 * interrupt from PIR in next vmentry.
4417 */
4418static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4419{
4420 struct vcpu_vmx *vmx = to_vmx(vcpu);
4421 int r;
4422
705699a1
WV		 4423 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4424 if (!r)
4425 return;
4426
a20ed54d
YZ		 4427 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4428 return;
4429
4430 r = pi_test_and_set_on(&vmx->pi_desc);
4431 kvm_make_request(KVM_REQ_EVENT, vcpu);
21bc8dc5 4432 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ		 4433 kvm_vcpu_kick(vcpu);
4434}
4435
4436static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4437{
4438 struct vcpu_vmx *vmx = to_vmx(vcpu);
4439
4440 if (!pi_test_and_clear_on(&vmx->pi_desc))
4441 return;
4442
4443 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4444}
4445
4446static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4447{
4448 return;
4449}
4450
a3a8ff8e
NHE		 4451/*
4452 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4453 * will not change in the lifetime of the guest.
4454 * Note that host-state that does change is set elsewhere. E.g., host-state
4455 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4456 */
a547c6db 4457static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4458{
4459 u32 low32, high32;
4460 unsigned long tmpl;
4461 struct desc_ptr dt;
d974baa3 4462 unsigned long cr4;
a3a8ff8e 4463
b1a74bf8 4464 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4465 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4466
d974baa3 4467 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 4468 cr4 = cr4_read_shadow();
d974baa3
AL		 4469 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4470 vmx->host_state.vmcs_host_cr4 = cr4;
4471
a3a8ff8e 4472 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4473#ifdef CONFIG_X86_64
4474 /*
4475 * Load null selectors, so we can avoid reloading them in
4476 * __vmx_load_host_state(), in case userspace uses the null selectors
4477 * too (the expected case).
4478 */
4479 vmcs_write16(HOST_DS_SELECTOR, 0);
4480 vmcs_write16(HOST_ES_SELECTOR, 0);
4481#else
a3a8ff8e
NHE		 4482 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4483 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4484#endif
a3a8ff8e
NHE		 4485 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4486 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4487
4488 native_store_idt(&dt);
4489 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4490 vmx->host_idt_base = dt.address;
a3a8ff8e 4491
83287ea4 4492 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4493
4494 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4495 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4496 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4497 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4498
4499 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4500 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4501 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4502 }
4503}
4504
bf8179a0
NHE		 4505static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4506{
4507 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4508 if (enable_ept)
4509 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4510 if (is_guest_mode(&vmx->vcpu))
4511 vmx->vcpu.arch.cr4_guest_owned_bits &=
4512 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4513 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4514}
4515
01e439be
YZ		 4516static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4517{
4518 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4519
35754c98 4520 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
01e439be
YZ		 4521 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4522 return pin_based_exec_ctrl;
4523}
4524
bf8179a0
NHE		 4525static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4526{
4527 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4528
4529 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4530 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4531
35754c98 4532 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE		 4533 exec_control &= ~CPU_BASED_TPR_SHADOW;
4534#ifdef CONFIG_X86_64
4535 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4536 CPU_BASED_CR8_LOAD_EXITING;
4537#endif
4538 }
4539 if (!enable_ept)
4540 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4541 CPU_BASED_CR3_LOAD_EXITING |
4542 CPU_BASED_INVLPG_EXITING;
4543 return exec_control;
4544}
4545
4546static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4547{
4548 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 4549 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE		 4550 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4551 if (vmx->vpid == 0)
4552 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4553 if (!enable_ept) {
4554 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4555 enable_unrestricted_guest = 0;
ad756a16
MJ		 4556 /* Enable INVPCID for non-ept guests may cause performance regression. */
4557 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4558 }
4559 if (!enable_unrestricted_guest)
4560 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4561 if (!ple_gap)
4562 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
35754c98 4563 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
c7c9c56c
YZ		 4564 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4565 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4566 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4567 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4568 (handle_vmptrld).
4569 We can NOT enable shadow_vmcs here because we don't have yet
4570 a current VMCS12
4571 */
4572 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4573 /* PML is enabled/disabled in creating/destorying vcpu */
4574 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4575
8b3e34e4
XG		 4576 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4577 exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4578
bf8179a0
NHE		 4579 return exec_control;
4580}
4581
ce88decf
XG		 4582static void ept_set_mmio_spte_mask(void)
4583{
4584 /*
4585 * EPT Misconfigurations can be generated if the value of bits 2:0
4586 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4587 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4588 * spte.
4589 */
885032b9 4590 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4591}
4592
f53cd63c 4593#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4594/*
4595 * Sets up the vmcs for emulated real mode.
4596 */
8b9cf98c 4597static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4598{
2e4ce7f5 4599#ifdef CONFIG_X86_64
6aa8b732 4600 unsigned long a;
2e4ce7f5 4601#endif
6aa8b732 4602 int i;
6aa8b732 4603
6aa8b732 4604 /* I/O */
3e7c73e9
AK		 4605 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4606 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4607
4607c2d7
AG		 4608 if (enable_shadow_vmcs) {
4609 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4610 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4611 }
25c5f225 4612 if (cpu_has_vmx_msr_bitmap())
5897297b 4613 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4614
6aa8b732
AK		 4615 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4616
6aa8b732 4617 /* Control */
01e439be 4618 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4619
bf8179a0 4620 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4621
8b3e34e4 4622 if (cpu_has_secondary_exec_ctrls())
bf8179a0
NHE		 4623 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4624 vmx_secondary_exec_control(vmx));
f78e0e2e 4625
35754c98 4626 if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
c7c9c56c
YZ		 4627 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4628 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4629 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4630 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4631
4632 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4633
4634 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4635 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4636 }
4637
4b8d54f9
ZE		 4638 if (ple_gap) {
4639 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4640 vmx->ple_window = ple_window;
4641 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4642 }
4643
c3707958
XG		 4644 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4645 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4646 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4647
9581d442
AK		 4648 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4649 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4650 vmx_set_constant_host_state(vmx);
05b3e0c2 4651#ifdef CONFIG_X86_64
6aa8b732
AK		 4652 rdmsrl(MSR_FS_BASE, a);
4653 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4654 rdmsrl(MSR_GS_BASE, a);
4655 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4656#else
4657 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4658 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4659#endif
4660
2cc51560
ED		 4661 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4662 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4663 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4664 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4665 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4666
74545705
RK		 4667 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4668 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4669
03916db9 4670 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4671 u32 index = vmx_msr_index[i];
4672 u32 data_low, data_high;
a2fa3e9f 4673 int j = vmx->nmsrs;
6aa8b732
AK		 4674
4675 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4676 continue;
432bd6cb
AK		 4677 if (wrmsr_safe(index, data_low, data_high) < 0)
4678 continue;
26bb0981
AK		 4679 vmx->guest_msrs[j].index = i;
4680 vmx->guest_msrs[j].data = 0;
d5696725 4681 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4682 ++vmx->nmsrs;
6aa8b732 4683 }
6aa8b732 4684
2961e876
GN		 4685
4686 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4687
4688 /* 22.2.1, 20.8.1 */
2961e876 4689 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4690
e00c8cf2 4691 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4692 set_cr4_guest_host_mask(vmx);
e00c8cf2 4693
f53cd63c
WL		 4694 if (vmx_xsaves_supported())
4695 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4696
e00c8cf2
AK		 4697 return 0;
4698}
4699
d28bc9dd 4700static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4701{
4702 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4703 struct msr_data apic_base_msr;
d28bc9dd 4704 u64 cr0;
e00c8cf2 4705
7ffd92c5 4706 vmx->rmode.vm86_active = 0;
e00c8cf2 4707
3b86cd99
JK		 4708 vmx->soft_vnmi_blocked = 0;
4709
ad312c7c 4710 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 4711 kvm_set_cr8(vcpu, 0);
4712
4713 if (!init_event) {
4714 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4715 MSR_IA32_APICBASE_ENABLE;
4716 if (kvm_vcpu_is_reset_bsp(vcpu))
4717 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4718 apic_base_msr.host_initiated = true;
4719 kvm_set_apic_base(vcpu, &apic_base_msr);
4720 }
e00c8cf2 4721
2fb92db1
AK		 4722 vmx_segment_cache_clear(vmx);
4723
5706be0d 4724 seg_setup(VCPU_SREG_CS);
66450a21 4725 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4726 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4727
4728 seg_setup(VCPU_SREG_DS);
4729 seg_setup(VCPU_SREG_ES);
4730 seg_setup(VCPU_SREG_FS);
4731 seg_setup(VCPU_SREG_GS);
4732 seg_setup(VCPU_SREG_SS);
4733
4734 vmcs_write16(GUEST_TR_SELECTOR, 0);
4735 vmcs_writel(GUEST_TR_BASE, 0);
4736 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4737 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4738
4739 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4740 vmcs_writel(GUEST_LDTR_BASE, 0);
4741 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4742 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4743
d28bc9dd
NA		 4744 if (!init_event) {
4745 vmcs_write32(GUEST_SYSENTER_CS, 0);
4746 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4747 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4748 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4749 }
e00c8cf2
AK		 4750
4751 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4752 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4753
e00c8cf2
AK		 4754 vmcs_writel(GUEST_GDTR_BASE, 0);
4755 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4756
4757 vmcs_writel(GUEST_IDTR_BASE, 0);
4758 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4759
443381a8 4760 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4761 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4762 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4763
e00c8cf2
AK		 4764 setup_msrs(vmx);
4765
6aa8b732
AK		 4766 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4767
d28bc9dd 4768 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4769 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4770 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4771 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4772 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4773 vmcs_write32(TPR_THRESHOLD, 0);
4774 }
4775
a73896cb 4776 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4777
35754c98 4778 if (vmx_cpu_uses_apicv(vcpu))
01e439be
YZ		 4779 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4780
2384d2b3
SY		 4781 if (vmx->vpid != 0)
4782 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4783
d28bc9dd
NA		 4784 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4785 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4786 vmx->vcpu.arch.cr0 = cr0;
4787 vmx_set_cr4(vcpu, 0);
4788 if (!init_event)
4789 vmx_set_efer(vcpu, 0);
4790 vmx_fpu_activate(vcpu);
4791 update_exception_bitmap(vcpu);
6aa8b732 4792
b9d762fa 4793 vpid_sync_context(vmx);
6aa8b732
AK		 4794}
4795
b6f1250e
NHE		 4796/*
4797 * In nested virtualization, check if L1 asked to exit on external interrupts.
4798 * For most existing hypervisors, this will always return true.
4799 */
4800static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4801{
4802 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4803 PIN_BASED_EXT_INTR_MASK;
4804}
4805
77b0f5d6
BD		 4806/*
4807 * In nested virtualization, check if L1 has set
4808 * VM_EXIT_ACK_INTR_ON_EXIT
4809 */
4810static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4811{
4812 return get_vmcs12(vcpu)->vm_exit_controls &
4813 VM_EXIT_ACK_INTR_ON_EXIT;
4814}
4815
ea8ceb83
JK		 4816static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4817{
4818 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4819 PIN_BASED_NMI_EXITING;
4820}
4821
c9a7953f 4822static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4823{
4824 u32 cpu_based_vm_exec_control;
730dca42 4825
3b86cd99
JK		 4826 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4827 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4828 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4829}
4830
c9a7953f 4831static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4832{
4833 u32 cpu_based_vm_exec_control;
4834
c9a7953f
JK		 4835 if (!cpu_has_virtual_nmis() ||
4836 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4837 enable_irq_window(vcpu);
4838 return;
4839 }
3b86cd99
JK		 4840
4841 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4842 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4843 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4844}
4845
66fd3f7f 4846static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4847{
9c8cba37 4848 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4849 uint32_t intr;
4850 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4851
229456fc 4852 trace_kvm_inj_virq(irq);
2714d1d3 4853
fa89a817 4854 ++vcpu->stat.irq_injections;
7ffd92c5 4855 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4856 int inc_eip = 0;
4857 if (vcpu->arch.interrupt.soft)
4858 inc_eip = vcpu->arch.event_exit_inst_len;
4859 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4860 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4861 return;
4862 }
66fd3f7f
GN		 4863 intr = irq | INTR_INFO_VALID_MASK;
4864 if (vcpu->arch.interrupt.soft) {
4865 intr |= INTR_TYPE_SOFT_INTR;
4866 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4867 vmx->vcpu.arch.event_exit_inst_len);
4868 } else
4869 intr |= INTR_TYPE_EXT_INTR;
4870 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4871}
4872
f08864b4
SY		 4873static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4874{
66a5a347
JK		 4875 struct vcpu_vmx *vmx = to_vmx(vcpu);
4876
0b6ac343
NHE		 4877 if (is_guest_mode(vcpu))
4878 return;
4879
3b86cd99
JK		 4880 if (!cpu_has_virtual_nmis()) {
4881 /*
4882 * Tracking the NMI-blocked state in software is built upon
4883 * finding the next open IRQ window. This, in turn, depends on
4884 * well-behaving guests: They have to keep IRQs disabled at
4885 * least as long as the NMI handler runs. Otherwise we may
4886 * cause NMI nesting, maybe breaking the guest. But as this is
4887 * highly unlikely, we can live with the residual risk.
4888 */
4889 vmx->soft_vnmi_blocked = 1;
4890 vmx->vnmi_blocked_time = 0;
4891 }
4892
487b391d 4893 ++vcpu->stat.nmi_injections;
9d58b931 4894 vmx->nmi_known_unmasked = false;
7ffd92c5 4895 if (vmx->rmode.vm86_active) {
71f9833b 4896 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4897 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4898 return;
4899 }
f08864b4
SY		 4900 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4901 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4902}
4903
3cfc3092
JK		 4904static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4905{
4906 if (!cpu_has_virtual_nmis())
4907 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4908 if (to_vmx(vcpu)->nmi_known_unmasked)
4909 return false;
c332c83a 4910 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4911}
4912
4913static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4914{
4915 struct vcpu_vmx *vmx = to_vmx(vcpu);
4916
4917 if (!cpu_has_virtual_nmis()) {
4918 if (vmx->soft_vnmi_blocked != masked) {
4919 vmx->soft_vnmi_blocked = masked;
4920 vmx->vnmi_blocked_time = 0;
4921 }
4922 } else {
9d58b931 4923 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4924 if (masked)
4925 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4926 GUEST_INTR_STATE_NMI);
4927 else
4928 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4929 GUEST_INTR_STATE_NMI);
4930 }
4931}
4932
2505dc9f
JK		 4933static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4934{
b6b8a145
JK		 4935 if (to_vmx(vcpu)->nested.nested_run_pending)
4936 return 0;
ea8ceb83 4937
2505dc9f
JK		 4938 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4939 return 0;
4940
4941 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4942 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4943 | GUEST_INTR_STATE_NMI));
4944}
4945
78646121
GN		 4946static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4947{
b6b8a145
JK		 4948 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4949 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4950 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4951 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4952}
4953
cbc94022
IE		 4954static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4955{
4956 int ret;
4957 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4958 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4959 .guest_phys_addr = addr,
4960 .memory_size = PAGE_SIZE * 3,
4961 .flags = 0,
4962 };
4963
9da0e4d5 4964 ret = x86_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4965 if (ret)
4966 return ret;
bfc6d222 4967 kvm->arch.tss_addr = addr;
1f755a82 4968 return init_rmode_tss(kvm);
cbc94022
IE		 4969}
4970
0ca1b4f4 4971static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4972{
77ab6db0 4973 switch (vec) {
77ab6db0 4974 case BP_VECTOR:
c573cd22
JK		 4975 /*
4976 * Update instruction length as we may reinject the exception
4977 * from user space while in guest debugging mode.
4978 */
4979 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4980 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4981 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4982 return false;
4983 /* fall through */
4984 case DB_VECTOR:
4985 if (vcpu->guest_debug &
4986 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4987 return false;
d0bfb940
JK		 4988 /* fall through */
4989 case DE_VECTOR:
77ab6db0
JK		 4990 case OF_VECTOR:
4991 case BR_VECTOR:
4992 case UD_VECTOR:
4993 case DF_VECTOR:
4994 case SS_VECTOR:
4995 case GP_VECTOR:
4996 case MF_VECTOR:
0ca1b4f4
GN		 4997 return true;
4998 break;
77ab6db0 4999 }
0ca1b4f4
GN		 5000 return false;
5001}
5002
5003static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5004 int vec, u32 err_code)
5005{
5006 /*
5007 * Instruction with address size override prefix opcode 0x67
5008 * Cause the #SS fault with 0 error code in VM86 mode.
5009 */
5010 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5011 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5012 if (vcpu->arch.halt_request) {
5013 vcpu->arch.halt_request = 0;
5cb56059 5014 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 5015 }
5016 return 1;
5017 }
5018 return 0;
5019 }
5020
5021 /*
5022 * Forward all other exceptions that are valid in real mode.
5023 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5024 * the required debugging infrastructure rework.
5025 */
5026 kvm_queue_exception(vcpu, vec);
5027 return 1;
6aa8b732
AK		 5028}
5029
a0861c02
AK		 5030/*
5031 * Trigger machine check on the host. We assume all the MSRs are already set up
5032 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5033 * We pass a fake environment to the machine check handler because we want
5034 * the guest to be always treated like user space, no matter what context
5035 * it used internally.
5036 */
5037static void kvm_machine_check(void)
5038{
5039#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5040 struct pt_regs regs = {
5041 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5042 .flags = X86_EFLAGS_IF,
5043 };
5044
5045 do_machine_check(&regs, 0);
5046#endif
5047}
5048
851ba692 5049static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 5050{
5051 /* already handled by vcpu_run */
5052 return 1;
5053}
5054
851ba692 5055static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5056{
1155f76a 5057 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5058 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5059 u32 intr_info, ex_no, error_code;
42dbaa5a 5060 unsigned long cr2, rip, dr6;
6aa8b732
AK		 5061 u32 vect_info;
5062 enum emulation_result er;
5063
1155f76a 5064 vect_info = vmx->idt_vectoring_info;
88786475 5065 intr_info = vmx->exit_intr_info;
6aa8b732 5066
a0861c02 5067 if (is_machine_check(intr_info))
851ba692 5068 return handle_machine_check(vcpu);
a0861c02 5069
e4a41889 5070 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 5071 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 5072
5073 if (is_no_device(intr_info)) {
5fd86fcf 5074 vmx_fpu_activate(vcpu);
2ab455cc
AL		 5075 return 1;
5076 }
5077
7aa81cc0 5078 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK		 5079 if (is_guest_mode(vcpu)) {
5080 kvm_queue_exception(vcpu, UD_VECTOR);
5081 return 1;
5082 }
51d8b661 5083 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5084 if (er != EMULATE_DONE)
7ee5d940 5085 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 5086 return 1;
5087 }
5088
6aa8b732 5089 error_code = 0;
2e11384c 5090 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5091 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 5092
5093 /*
5094 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5095 * MMIO, it is better to report an internal error.
5096 * See the comments in vmx_handle_exit.
5097 */
5098 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5099 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5100 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5101 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5102 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 5103 vcpu->run->internal.data[0] = vect_info;
5104 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5105 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 5106 return 0;
5107 }
5108
6aa8b732 5109 if (is_page_fault(intr_info)) {
1439442c 5110 /* EPT won't cause page fault directly */
cf3ace79 5111 BUG_ON(enable_ept);
6aa8b732 5112 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5113 trace_kvm_page_fault(cr2, error_code);
5114
3298b75c 5115 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5116 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5117 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5118 }
5119
d0bfb940 5120 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5121
5122 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5123 return handle_rmode_exception(vcpu, ex_no, error_code);
5124
42dbaa5a
JK		 5125 switch (ex_no) {
5126 case DB_VECTOR:
5127 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5128 if (!(vcpu->guest_debug &
5129 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5130 vcpu->arch.dr6 &= ~15;
6f43ed01 5131 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5132 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5133 skip_emulated_instruction(vcpu);
5134
42dbaa5a
JK		 5135 kvm_queue_exception(vcpu, DB_VECTOR);
5136 return 1;
5137 }
5138 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5139 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5140 /* fall through */
5141 case BP_VECTOR:
c573cd22
JK		 5142 /*
5143 * Update instruction length as we may reinject #BP from
5144 * user space while in guest debugging mode. Reading it for
5145 * #DB as well causes no harm, it is not used in that case.
5146 */
5147 vmx->vcpu.arch.event_exit_inst_len =
5148 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5149 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5150 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5151 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5152 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5153 break;
5154 default:
d0bfb940
JK		 5155 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5156 kvm_run->ex.exception = ex_no;
5157 kvm_run->ex.error_code = error_code;
42dbaa5a 5158 break;
6aa8b732 5159 }
6aa8b732
AK		 5160 return 0;
5161}
5162
851ba692 5163static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5164{
1165f5fe 5165 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5166 return 1;
5167}
5168
851ba692 5169static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5170{
851ba692 5171 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5172 return 0;
5173}
6aa8b732 5174
851ba692 5175static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5176{
bfdaab09 5177 unsigned long exit_qualification;
34c33d16 5178 int size, in, string;
039576c0 5179 unsigned port;
6aa8b732 5180
bfdaab09 5181 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5182 string = (exit_qualification & 16) != 0;
cf8f70bf 5183 in = (exit_qualification & 8) != 0;
e70669ab 5184
cf8f70bf 5185 ++vcpu->stat.io_exits;
e70669ab 5186
cf8f70bf 5187 if (string || in)
51d8b661 5188 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5189
cf8f70bf
GN		 5190 port = exit_qualification >> 16;
5191 size = (exit_qualification & 7) + 1;
e93f36bc 5192 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5193
5194 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5195}
5196
102d8325
IM		 5197static void
5198vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5199{
5200 /*
5201 * Patch in the VMCALL instruction:
5202 */
5203 hypercall[0] = 0x0f;
5204 hypercall[1] = 0x01;
5205 hypercall[2] = 0xc1;
102d8325
IM		 5206}
5207
b9c237bb 5208static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5209{
5210 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5211 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5212
b9c237bb 5213 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5214 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5215 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5216 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5217 return (val & always_on) == always_on;
5218}
5219
0fa06071 5220/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5221static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5222{
eeadf9e7 5223 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5224 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5225 unsigned long orig_val = val;
5226
eeadf9e7
NHE		 5227 /*
5228 * We get here when L2 changed cr0 in a way that did not change
5229 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5230 * but did change L0 shadowed bits. So we first calculate the
5231 * effective cr0 value that L1 would like to write into the
5232 * hardware. It consists of the L2-owned bits from the new
5233 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5234 */
1a0d74e6
JK		 5235 val = (val & ~vmcs12->cr0_guest_host_mask) |
5236 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5237
b9c237bb 5238 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5239 return 1;
1a0d74e6
JK		 5240
5241 if (kvm_set_cr0(vcpu, val))
5242 return 1;
5243 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5244 return 0;
1a0d74e6
JK		 5245 } else {
5246 if (to_vmx(vcpu)->nested.vmxon &&
5247 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5248 return 1;
eeadf9e7 5249 return kvm_set_cr0(vcpu, val);
1a0d74e6 5250 }
eeadf9e7
NHE		 5251}
5252
5253static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5254{
5255 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5256 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5257 unsigned long orig_val = val;
5258
5259 /* analogously to handle_set_cr0 */
5260 val = (val & ~vmcs12->cr4_guest_host_mask) |
5261 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5262 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5263 return 1;
1a0d74e6 5264 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5265 return 0;
5266 } else
5267 return kvm_set_cr4(vcpu, val);
5268}
5269
5270/* called to set cr0 as approriate for clts instruction exit. */
5271static void handle_clts(struct kvm_vcpu *vcpu)
5272{
5273 if (is_guest_mode(vcpu)) {
5274 /*
5275 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5276 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5277 * just pretend it's off (also in arch.cr0 for fpu_activate).
5278 */
5279 vmcs_writel(CR0_READ_SHADOW,
5280 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5281 vcpu->arch.cr0 &= ~X86_CR0_TS;
5282 } else
5283 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5284}
5285
851ba692 5286static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5287{
229456fc 5288 unsigned long exit_qualification, val;
6aa8b732
AK		 5289 int cr;
5290 int reg;
49a9b07e 5291 int err;
6aa8b732 5292
bfdaab09 5293 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5294 cr = exit_qualification & 15;
5295 reg = (exit_qualification >> 8) & 15;
5296 switch ((exit_qualification >> 4) & 3) {
5297 case 0: /* mov to cr */
1e32c079 5298 val = kvm_register_readl(vcpu, reg);
229456fc 5299 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5300 switch (cr) {
5301 case 0:
eeadf9e7 5302 err = handle_set_cr0(vcpu, val);
db8fcefa 5303 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5304 return 1;
5305 case 3:
2390218b 5306 err = kvm_set_cr3(vcpu, val);
db8fcefa 5307 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5308 return 1;
5309 case 4:
eeadf9e7 5310 err = handle_set_cr4(vcpu, val);
db8fcefa 5311 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5312 return 1;
0a5fff19
GN		 5313 case 8: {
5314 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5315 u8 cr8 = (u8)val;
eea1cff9 5316 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5317 kvm_complete_insn_gp(vcpu, err);
35754c98 5318 if (lapic_in_kernel(vcpu))
0a5fff19
GN		 5319 return 1;
5320 if (cr8_prev <= cr8)
5321 return 1;
851ba692 5322 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5323 return 0;
5324 }
4b8073e4 5325 }
6aa8b732 5326 break;
25c4c276 5327 case 2: /* clts */
eeadf9e7 5328 handle_clts(vcpu);
4d4ec087 5329 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5330 skip_emulated_instruction(vcpu);
6b52d186 5331 vmx_fpu_activate(vcpu);
25c4c276 5332 return 1;
6aa8b732
AK		 5333 case 1: /*mov from cr*/
5334 switch (cr) {
5335 case 3:
9f8fe504
AK		 5336 val = kvm_read_cr3(vcpu);
5337 kvm_register_write(vcpu, reg, val);
5338 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5339 skip_emulated_instruction(vcpu);
5340 return 1;
5341 case 8:
229456fc
MT		 5342 val = kvm_get_cr8(vcpu);
5343 kvm_register_write(vcpu, reg, val);
5344 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5345 skip_emulated_instruction(vcpu);
5346 return 1;
5347 }
5348 break;
5349 case 3: /* lmsw */
a1f83a74 5350 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5351 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5352 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5353
5354 skip_emulated_instruction(vcpu);
5355 return 1;
5356 default:
5357 break;
5358 }
851ba692 5359 vcpu->run->exit_reason = 0;
a737f256 5360 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5361 (int)(exit_qualification >> 4) & 3, cr);
5362 return 0;
5363}
5364
851ba692 5365static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5366{
bfdaab09 5367 unsigned long exit_qualification;
16f8a6f9
NA		 5368 int dr, dr7, reg;
5369
5370 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5371 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5372
5373 /* First, if DR does not exist, trigger UD */
5374 if (!kvm_require_dr(vcpu, dr))
5375 return 1;
6aa8b732 5376
f2483415 5377 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5378 if (!kvm_require_cpl(vcpu, 0))
5379 return 1;
16f8a6f9
NA		 5380 dr7 = vmcs_readl(GUEST_DR7);
5381 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5382 /*
5383 * As the vm-exit takes precedence over the debug trap, we
5384 * need to emulate the latter, either for the host or the
5385 * guest debugging itself.
5386 */
5387 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5388 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5389 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5390 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5391 vcpu->run->debug.arch.exception = DB_VECTOR;
5392 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5393 return 0;
5394 } else {
7305eb5d 5395 vcpu->arch.dr6 &= ~15;
6f43ed01 5396 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5397 kvm_queue_exception(vcpu, DB_VECTOR);
5398 return 1;
5399 }
5400 }
5401
81908bf4
PB		 5402 if (vcpu->guest_debug == 0) {
5403 u32 cpu_based_vm_exec_control;
5404
5405 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5406 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5407 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5408
5409 /*
5410 * No more DR vmexits; force a reload of the debug registers
5411 * and reenter on this instruction. The next vmexit will
5412 * retrieve the full state of the debug registers.
5413 */
5414 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5415 return 1;
5416 }
5417
42dbaa5a
JK		 5418 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5419 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5420 unsigned long val;
4c4d563b
JK		 5421
5422 if (kvm_get_dr(vcpu, dr, &val))
5423 return 1;
5424 kvm_register_write(vcpu, reg, val);
020df079 5425 } else
5777392e 5426 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5427 return 1;
5428
6aa8b732
AK		 5429 skip_emulated_instruction(vcpu);
5430 return 1;
5431}
5432
73aaf249
JK		 5433static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5434{
5435 return vcpu->arch.dr6;
5436}
5437
5438static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5439{
5440}
5441
81908bf4
PB		 5442static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5443{
5444 u32 cpu_based_vm_exec_control;
5445
5446 get_debugreg(vcpu->arch.db[0], 0);
5447 get_debugreg(vcpu->arch.db[1], 1);
5448 get_debugreg(vcpu->arch.db[2], 2);
5449 get_debugreg(vcpu->arch.db[3], 3);
5450 get_debugreg(vcpu->arch.dr6, 6);
5451 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5452
5453 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5454
5455 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5456 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5457 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5458}
5459
020df079
GN		 5460static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5461{
5462 vmcs_writel(GUEST_DR7, val);
5463}
5464
851ba692 5465static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5466{
06465c5a
AK		 5467 kvm_emulate_cpuid(vcpu);
5468 return 1;
6aa8b732
AK		 5469}
5470
851ba692 5471static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5472{
ad312c7c 5473 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 5474 struct msr_data msr_info;
6aa8b732 5475
609e36d3
PB		 5476 msr_info.index = ecx;
5477 msr_info.host_initiated = false;
5478 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 5479 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5480 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5481 return 1;
5482 }
5483
609e36d3 5484 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 5485
6aa8b732 5486 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB		 5487 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5488 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6aa8b732
AK		 5489 skip_emulated_instruction(vcpu);
5490 return 1;
5491}
5492
851ba692 5493static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5494{
8fe8ab46 5495 struct msr_data msr;
ad312c7c
ZX		 5496 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5497 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5498 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5499
8fe8ab46
WA		 5500 msr.data = data;
5501 msr.index = ecx;
5502 msr.host_initiated = false;
854e8bb1 5503 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5504 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5505 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5506 return 1;
5507 }
5508
59200273 5509 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5510 skip_emulated_instruction(vcpu);
5511 return 1;
5512}
5513
851ba692 5514static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5515{
3842d135 5516 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5517 return 1;
5518}
5519
851ba692 5520static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5521{
85f455f7
ED		 5522 u32 cpu_based_vm_exec_control;
5523
5524 /* clear pending irq */
5525 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5526 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5527 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5528
3842d135
AK		 5529 kvm_make_request(KVM_REQ_EVENT, vcpu);
5530
a26bf12a 5531 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 5532 return 1;
5533}
5534
851ba692 5535static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 5536{
d3bef15f 5537 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5538}
5539
851ba692 5540static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5541{
7aa81cc0
AL		 5542 kvm_emulate_hypercall(vcpu);
5543 return 1;
c21415e8
IM		 5544}
5545
ec25d5e6
GN		 5546static int handle_invd(struct kvm_vcpu *vcpu)
5547{
51d8b661 5548 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5549}
5550
851ba692 5551static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5552{
f9c617f6 5553 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5554
5555 kvm_mmu_invlpg(vcpu, exit_qualification);
5556 skip_emulated_instruction(vcpu);
5557 return 1;
5558}
5559
fee84b07
AK		 5560static int handle_rdpmc(struct kvm_vcpu *vcpu)
5561{
5562 int err;
5563
5564 err = kvm_rdpmc(vcpu);
5565 kvm_complete_insn_gp(vcpu, err);
5566
5567 return 1;
5568}
5569
851ba692 5570static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5571{
f5f48ee1 5572 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5573 return 1;
5574}
5575
2acf923e
DC		 5576static int handle_xsetbv(struct kvm_vcpu *vcpu)
5577{
5578 u64 new_bv = kvm_read_edx_eax(vcpu);
5579 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5580
5581 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5582 skip_emulated_instruction(vcpu);
5583 return 1;
5584}
5585
f53cd63c
WL		 5586static int handle_xsaves(struct kvm_vcpu *vcpu)
5587{
5588 skip_emulated_instruction(vcpu);
5589 WARN(1, "this should never happen\n");
5590 return 1;
5591}
5592
5593static int handle_xrstors(struct kvm_vcpu *vcpu)
5594{
5595 skip_emulated_instruction(vcpu);
5596 WARN(1, "this should never happen\n");
5597 return 1;
5598}
5599
851ba692 5600static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5601{
58fbbf26
KT		 5602 if (likely(fasteoi)) {
5603 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5604 int access_type, offset;
5605
5606 access_type = exit_qualification & APIC_ACCESS_TYPE;
5607 offset = exit_qualification & APIC_ACCESS_OFFSET;
5608 /*
5609 * Sane guest uses MOV to write EOI, with written value
5610 * not cared. So make a short-circuit here by avoiding
5611 * heavy instruction emulation.
5612 */
5613 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5614 (offset == APIC_EOI)) {
5615 kvm_lapic_set_eoi(vcpu);
5616 skip_emulated_instruction(vcpu);
5617 return 1;
5618 }
5619 }
51d8b661 5620 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5621}
5622
c7c9c56c
YZ		 5623static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5624{
5625 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5626 int vector = exit_qualification & 0xff;
5627
5628 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5629 kvm_apic_set_eoi_accelerated(vcpu, vector);
5630 return 1;
5631}
5632
83d4c286
YZ		 5633static int handle_apic_write(struct kvm_vcpu *vcpu)
5634{
5635 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5636 u32 offset = exit_qualification & 0xfff;
5637
5638 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5639 kvm_apic_write_nodecode(vcpu, offset);
5640 return 1;
5641}
5642
851ba692 5643static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5644{
60637aac 5645 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5646 unsigned long exit_qualification;
e269fb21
JK		 5647 bool has_error_code = false;
5648 u32 error_code = 0;
37817f29 5649 u16 tss_selector;
7f3d35fd 5650 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5651
5652 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5653 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5654 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5655
5656 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5657
5658 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5659 if (reason == TASK_SWITCH_GATE && idt_v) {
5660 switch (type) {
5661 case INTR_TYPE_NMI_INTR:
5662 vcpu->arch.nmi_injected = false;
654f06fc 5663 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5664 break;
5665 case INTR_TYPE_EXT_INTR:
66fd3f7f 5666 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5667 kvm_clear_interrupt_queue(vcpu);
5668 break;
5669 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5670 if (vmx->idt_vectoring_info &
5671 VECTORING_INFO_DELIVER_CODE_MASK) {
5672 has_error_code = true;
5673 error_code =
5674 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5675 }
5676 /* fall through */
64a7ec06
GN		 5677 case INTR_TYPE_SOFT_EXCEPTION:
5678 kvm_clear_exception_queue(vcpu);
5679 break;
5680 default:
5681 break;
5682 }
60637aac 5683 }
37817f29
IE		 5684 tss_selector = exit_qualification;
5685
64a7ec06
GN		 5686 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5687 type != INTR_TYPE_EXT_INTR &&
5688 type != INTR_TYPE_NMI_INTR))
5689 skip_emulated_instruction(vcpu);
5690
7f3d35fd
KW		 5691 if (kvm_task_switch(vcpu, tss_selector,
5692 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5693 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5694 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5695 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5696 vcpu->run->internal.ndata = 0;
42dbaa5a 5697 return 0;
acb54517 5698 }
42dbaa5a 5699
42dbaa5a
JK		 5700 /*
5701 * TODO: What about debug traps on tss switch?
5702 * Are we supposed to inject them and update dr6?
5703 */
5704
5705 return 1;
37817f29
IE		 5706}
5707
851ba692 5708static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5709{
f9c617f6 5710 unsigned long exit_qualification;
1439442c 5711 gpa_t gpa;
4f5982a5 5712 u32 error_code;
1439442c 5713 int gla_validity;
1439442c 5714
f9c617f6 5715 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5716
1439442c
SY		 5717 gla_validity = (exit_qualification >> 7) & 0x3;
5718 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5719 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5720 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5721 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5722 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5723 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5724 (long unsigned int)exit_qualification);
851ba692
AK		 5725 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5726 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5727 return 0;
1439442c
SY		 5728 }
5729
0be9c7a8
GN		 5730 /*
5731 * EPT violation happened while executing iret from NMI,
5732 * "blocked by NMI" bit has to be set before next VM entry.
5733 * There are errata that may cause this bit to not be set:
5734 * AAK134, BY25.
5735 */
bcd1c294
GN		 5736 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5737 cpu_has_virtual_nmis() &&
5738 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5739 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5740
1439442c 5741 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5742 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5743
5744 /* It is a write fault? */
81ed33e4 5745 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5746 /* It is a fetch fault? */
81ed33e4 5747 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5748 /* ept page table is present? */
81ed33e4 5749 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5750
25d92081
YZ		 5751 vcpu->arch.exit_qualification = exit_qualification;
5752
4f5982a5 5753 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5754}
5755
851ba692 5756static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5757{
f735d4af 5758 int ret;
68f89400
MT		 5759 gpa_t gpa;
5760
5761 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 5762 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
68c3b4d1 5763 skip_emulated_instruction(vcpu);
931c33b1 5764 trace_kvm_fast_mmio(gpa);
68c3b4d1
MT		 5765 return 1;
5766 }
68f89400 5767
ce88decf 5768 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5769 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5770 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5771 EMULATE_DONE;
f8f55942
XG		 5772
5773 if (unlikely(ret == RET_MMIO_PF_INVALID))
5774 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5775
b37fbea6 5776 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5777 return 1;
5778
5779 /* It is the real ept misconfig */
f735d4af 5780 WARN_ON(1);
68f89400 5781
851ba692
AK		 5782 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5783 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5784
5785 return 0;
5786}
5787
851ba692 5788static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5789{
5790 u32 cpu_based_vm_exec_control;
5791
5792 /* clear pending NMI */
5793 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5794 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5795 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5796 ++vcpu->stat.nmi_window_exits;
3842d135 5797 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5798
5799 return 1;
5800}
5801
80ced186 5802static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5803{
8b3079a5
AK		 5804 struct vcpu_vmx *vmx = to_vmx(vcpu);
5805 enum emulation_result err = EMULATE_DONE;
80ced186 5806 int ret = 1;
49e9d557
AK		 5807 u32 cpu_exec_ctrl;
5808 bool intr_window_requested;
b8405c18 5809 unsigned count = 130;
49e9d557
AK		 5810
5811 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5812 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5813
98eb2f8b 5814 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5815 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5816 return handle_interrupt_window(&vmx->vcpu);
5817
de87dcdd
AK		 5818 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5819 return 1;
5820
991eebf9 5821 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5822
ac0a48c3 5823 if (err == EMULATE_USER_EXIT) {
94452b9e 5824 ++vcpu->stat.mmio_exits;
80ced186
MG		 5825 ret = 0;
5826 goto out;
5827 }
1d5a4d9b 5828
de5f70e0
AK		 5829 if (err != EMULATE_DONE) {
5830 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5831 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5832 vcpu->run->internal.ndata = 0;
6d77dbfc 5833 return 0;
de5f70e0 5834 }
ea953ef0 5835
8d76c49e
GN		 5836 if (vcpu->arch.halt_request) {
5837 vcpu->arch.halt_request = 0;
5cb56059 5838 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5839 goto out;
5840 }
5841
ea953ef0 5842 if (signal_pending(current))
80ced186 5843 goto out;
ea953ef0
MG		 5844 if (need_resched())
5845 schedule();
5846 }
5847
80ced186
MG		 5848out:
5849 return ret;
ea953ef0
MG		 5850}
5851
b4a2d31d
RK		 5852static int __grow_ple_window(int val)
5853{
5854 if (ple_window_grow < 1)
5855 return ple_window;
5856
5857 val = min(val, ple_window_actual_max);
5858
5859 if (ple_window_grow < ple_window)
5860 val *= ple_window_grow;
5861 else
5862 val += ple_window_grow;
5863
5864 return val;
5865}
5866
5867static int __shrink_ple_window(int val, int modifier, int minimum)
5868{
5869 if (modifier < 1)
5870 return ple_window;
5871
5872 if (modifier < ple_window)
5873 val /= modifier;
5874 else
5875 val -= modifier;
5876
5877 return max(val, minimum);
5878}
5879
5880static void grow_ple_window(struct kvm_vcpu *vcpu)
5881{
5882 struct vcpu_vmx *vmx = to_vmx(vcpu);
5883 int old = vmx->ple_window;
5884
5885 vmx->ple_window = __grow_ple_window(old);
5886
5887 if (vmx->ple_window != old)
5888 vmx->ple_window_dirty = true;
7b46268d
RK		 5889
5890 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5891}
5892
5893static void shrink_ple_window(struct kvm_vcpu *vcpu)
5894{
5895 struct vcpu_vmx *vmx = to_vmx(vcpu);
5896 int old = vmx->ple_window;
5897
5898 vmx->ple_window = __shrink_ple_window(old,
5899 ple_window_shrink, ple_window);
5900
5901 if (vmx->ple_window != old)
5902 vmx->ple_window_dirty = true;
7b46268d
RK		 5903
5904 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5905}
5906
5907/*
5908 * ple_window_actual_max is computed to be one grow_ple_window() below
5909 * ple_window_max. (See __grow_ple_window for the reason.)
5910 * This prevents overflows, because ple_window_max is int.
5911 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5912 * this process.
5913 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5914 */
5915static void update_ple_window_actual_max(void)
5916{
5917 ple_window_actual_max =
5918 __shrink_ple_window(max(ple_window_max, ple_window),
5919 ple_window_grow, INT_MIN);
5920}
5921
f2c7648d
TC		 5922static __init int hardware_setup(void)
5923{
34a1cd60
TC		 5924 int r = -ENOMEM, i, msr;
5925
5926 rdmsrl_safe(MSR_EFER, &host_efer);
5927
5928 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5929 kvm_define_shared_msr(i, vmx_msr_index[i]);
5930
5931 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5932 if (!vmx_io_bitmap_a)
5933 return r;
5934
5935 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5936 if (!vmx_io_bitmap_b)
5937 goto out;
5938
5939 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5940 if (!vmx_msr_bitmap_legacy)
5941 goto out1;
5942
5943 vmx_msr_bitmap_legacy_x2apic =
5944 (unsigned long *)__get_free_page(GFP_KERNEL);
5945 if (!vmx_msr_bitmap_legacy_x2apic)
5946 goto out2;
5947
5948 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5949 if (!vmx_msr_bitmap_longmode)
5950 goto out3;
5951
5952 vmx_msr_bitmap_longmode_x2apic =
5953 (unsigned long *)__get_free_page(GFP_KERNEL);
5954 if (!vmx_msr_bitmap_longmode_x2apic)
5955 goto out4;
3af18d9c
WV		 5956
5957 if (nested) {
5958 vmx_msr_bitmap_nested =
5959 (unsigned long *)__get_free_page(GFP_KERNEL);
5960 if (!vmx_msr_bitmap_nested)
5961 goto out5;
5962 }
5963
34a1cd60
TC		 5964 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5965 if (!vmx_vmread_bitmap)
3af18d9c 5966 goto out6;
34a1cd60
TC		 5967
5968 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5969 if (!vmx_vmwrite_bitmap)
3af18d9c 5970 goto out7;
34a1cd60
TC		 5971
5972 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5973 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5974
5975 /*
5976 * Allow direct access to the PC debug port (it is often used for I/O
5977 * delays, but the vmexits simply slow things down).
5978 */
5979 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5980 clear_bit(0x80, vmx_io_bitmap_a);
5981
5982 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5983
5984 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5985 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 5986 if (nested)
5987 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 5988
34a1cd60
TC		 5989 if (setup_vmcs_config(&vmcs_config) < 0) {
5990 r = -EIO;
3af18d9c 5991 goto out8;
baa03522 5992 }
f2c7648d
TC		 5993
5994 if (boot_cpu_has(X86_FEATURE_NX))
5995 kvm_enable_efer_bits(EFER_NX);
5996
5997 if (!cpu_has_vmx_vpid())
5998 enable_vpid = 0;
5999 if (!cpu_has_vmx_shadow_vmcs())
6000 enable_shadow_vmcs = 0;
6001 if (enable_shadow_vmcs)
6002 init_vmcs_shadow_fields();
6003
6004 if (!cpu_has_vmx_ept() ||
6005 !cpu_has_vmx_ept_4levels()) {
6006 enable_ept = 0;
6007 enable_unrestricted_guest = 0;
6008 enable_ept_ad_bits = 0;
6009 }
6010
6011 if (!cpu_has_vmx_ept_ad_bits())
6012 enable_ept_ad_bits = 0;
6013
6014 if (!cpu_has_vmx_unrestricted_guest())
6015 enable_unrestricted_guest = 0;
6016
ad15a296 6017 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6018 flexpriority_enabled = 0;
6019
ad15a296
PB		 6020 /*
6021 * set_apic_access_page_addr() is used to reload apic access
6022 * page upon invalidation. No need to do anything if not
6023 * using the APIC_ACCESS_ADDR VMCS field.
6024 */
6025 if (!flexpriority_enabled)
f2c7648d 6026 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6027
6028 if (!cpu_has_vmx_tpr_shadow())
6029 kvm_x86_ops->update_cr8_intercept = NULL;
6030
6031 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6032 kvm_disable_largepages();
6033
6034 if (!cpu_has_vmx_ple())
6035 ple_gap = 0;
6036
6037 if (!cpu_has_vmx_apicv())
6038 enable_apicv = 0;
6039
6040 if (enable_apicv)
6041 kvm_x86_ops->update_cr8_intercept = NULL;
6042 else {
6043 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6044 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6045 kvm_x86_ops->deliver_posted_interrupt = NULL;
6046 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6047 }
6048
baa03522
TC		 6049 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6050 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6051 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6052 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6053 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6054 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6055 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6056
6057 memcpy(vmx_msr_bitmap_legacy_x2apic,
6058 vmx_msr_bitmap_legacy, PAGE_SIZE);
6059 memcpy(vmx_msr_bitmap_longmode_x2apic,
6060 vmx_msr_bitmap_longmode, PAGE_SIZE);
6061
04bb92e4
WL		 6062 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6063
baa03522
TC		 6064 if (enable_apicv) {
6065 for (msr = 0x800; msr <= 0x8ff; msr++)
6066 vmx_disable_intercept_msr_read_x2apic(msr);
6067
6068 /* According SDM, in x2apic mode, the whole id reg is used.
6069 * But in KVM, it only use the highest eight bits. Need to
6070 * intercept it */
6071 vmx_enable_intercept_msr_read_x2apic(0x802);
6072 /* TMCCT */
6073 vmx_enable_intercept_msr_read_x2apic(0x839);
6074 /* TPR */
6075 vmx_disable_intercept_msr_write_x2apic(0x808);
6076 /* EOI */
6077 vmx_disable_intercept_msr_write_x2apic(0x80b);
6078 /* SELF-IPI */
6079 vmx_disable_intercept_msr_write_x2apic(0x83f);
6080 }
6081
6082 if (enable_ept) {
6083 kvm_mmu_set_mask_ptes(0ull,
6084 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6085 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6086 0ull, VMX_EPT_EXECUTABLE_MASK);
6087 ept_set_mmio_spte_mask();
6088 kvm_enable_tdp();
6089 } else
6090 kvm_disable_tdp();
6091
6092 update_ple_window_actual_max();
6093
843e4330
KH		 6094 /*
6095 * Only enable PML when hardware supports PML feature, and both EPT
6096 * and EPT A/D bit features are enabled -- PML depends on them to work.
6097 */
6098 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6099 enable_pml = 0;
6100
6101 if (!enable_pml) {
6102 kvm_x86_ops->slot_enable_log_dirty = NULL;
6103 kvm_x86_ops->slot_disable_log_dirty = NULL;
6104 kvm_x86_ops->flush_log_dirty = NULL;
6105 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6106 }
6107
f2c7648d 6108 return alloc_kvm_area();
34a1cd60 6109
3af18d9c 6110out8:
34a1cd60 6111 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6112out7:
34a1cd60 6113 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6114out6:
6115 if (nested)
6116 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6117out5:
6118 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6119out4:
6120 free_page((unsigned long)vmx_msr_bitmap_longmode);
6121out3:
6122 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6123out2:
6124 free_page((unsigned long)vmx_msr_bitmap_legacy);
6125out1:
6126 free_page((unsigned long)vmx_io_bitmap_b);
6127out:
6128 free_page((unsigned long)vmx_io_bitmap_a);
6129
6130 return r;
f2c7648d
TC		 6131}
6132
6133static __exit void hardware_unsetup(void)
6134{
34a1cd60
TC		 6135 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6136 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6137 free_page((unsigned long)vmx_msr_bitmap_legacy);
6138 free_page((unsigned long)vmx_msr_bitmap_longmode);
6139 free_page((unsigned long)vmx_io_bitmap_b);
6140 free_page((unsigned long)vmx_io_bitmap_a);
6141 free_page((unsigned long)vmx_vmwrite_bitmap);
6142 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6143 if (nested)
6144 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6145
f2c7648d
TC		 6146 free_kvm_area();
6147}
6148
4b8d54f9
ZE		 6149/*
6150 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6151 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6152 */
9fb41ba8 6153static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6154{
b4a2d31d
RK		 6155 if (ple_gap)
6156 grow_ple_window(vcpu);
6157
4b8d54f9
ZE		 6158 skip_emulated_instruction(vcpu);
6159 kvm_vcpu_on_spin(vcpu);
6160
6161 return 1;
6162}
6163
87c00572 6164static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6165{
87c00572 6166 skip_emulated_instruction(vcpu);
59708670
SY		 6167 return 1;
6168}
6169
87c00572
GS		 6170static int handle_mwait(struct kvm_vcpu *vcpu)
6171{
6172 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6173 return handle_nop(vcpu);
6174}
6175
5f3d45e7
MD		 6176static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6177{
6178 return 1;
6179}
6180
87c00572
GS		 6181static int handle_monitor(struct kvm_vcpu *vcpu)
6182{
6183 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6184 return handle_nop(vcpu);
6185}
6186
ff2f6fe9
NHE		 6187/*
6188 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6189 * We could reuse a single VMCS for all the L2 guests, but we also want the
6190 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6191 * allows keeping them loaded on the processor, and in the future will allow
6192 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6193 * every entry if they never change.
6194 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6195 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6196 *
6197 * The following functions allocate and free a vmcs02 in this pool.
6198 */
6199
6200/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6201static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6202{
6203 struct vmcs02_list *item;
6204 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6205 if (item->vmptr == vmx->nested.current_vmptr) {
6206 list_move(&item->list, &vmx->nested.vmcs02_pool);
6207 return &item->vmcs02;
6208 }
6209
6210 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6211 /* Recycle the least recently used VMCS. */
6212 item = list_entry(vmx->nested.vmcs02_pool.prev,
6213 struct vmcs02_list, list);
6214 item->vmptr = vmx->nested.current_vmptr;
6215 list_move(&item->list, &vmx->nested.vmcs02_pool);
6216 return &item->vmcs02;
6217 }
6218
6219 /* Create a new VMCS */
0fa24ce3 6220 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6221 if (!item)
6222 return NULL;
6223 item->vmcs02.vmcs = alloc_vmcs();
6224 if (!item->vmcs02.vmcs) {
6225 kfree(item);
6226 return NULL;
6227 }
6228 loaded_vmcs_init(&item->vmcs02);
6229 item->vmptr = vmx->nested.current_vmptr;
6230 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6231 vmx->nested.vmcs02_num++;
6232 return &item->vmcs02;
6233}
6234
6235/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6236static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6237{
6238 struct vmcs02_list *item;
6239 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6240 if (item->vmptr == vmptr) {
6241 free_loaded_vmcs(&item->vmcs02);
6242 list_del(&item->list);
6243 kfree(item);
6244 vmx->nested.vmcs02_num--;
6245 return;
6246 }
6247}
6248
6249/*
6250 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6251 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6252 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6253 */
6254static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6255{
6256 struct vmcs02_list *item, *n;
4fa7734c
PB		 6257
6258 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6259 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6260 /*
6261 * Something will leak if the above WARN triggers. Better than
6262 * a use-after-free.
6263 */
6264 if (vmx->loaded_vmcs == &item->vmcs02)
6265 continue;
6266
6267 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6268 list_del(&item->list);
6269 kfree(item);
4fa7734c 6270 vmx->nested.vmcs02_num--;
ff2f6fe9 6271 }
ff2f6fe9
NHE		 6272}
6273
0658fbaa
ACL		 6274/*
6275 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6276 * set the success or error code of an emulated VMX instruction, as specified
6277 * by Vol 2B, VMX Instruction Reference, "Conventions".
6278 */
6279static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6280{
6281 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6282 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6283 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6284}
6285
6286static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6287{
6288 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6289 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6290 X86_EFLAGS_SF | X86_EFLAGS_OF))
6291 | X86_EFLAGS_CF);
6292}
6293
145c28dd 6294static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6295 u32 vm_instruction_error)
6296{
6297 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6298 /*
6299 * failValid writes the error number to the current VMCS, which
6300 * can't be done there isn't a current VMCS.
6301 */
6302 nested_vmx_failInvalid(vcpu);
6303 return;
6304 }
6305 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6306 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6307 X86_EFLAGS_SF | X86_EFLAGS_OF))
6308 | X86_EFLAGS_ZF);
6309 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6310 /*
6311 * We don't need to force a shadow sync because
6312 * VM_INSTRUCTION_ERROR is not shadowed
6313 */
6314}
145c28dd 6315
ff651cb6
WV		 6316static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6317{
6318 /* TODO: not to reset guest simply here. */
6319 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6320 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6321}
6322
f4124500
JK		 6323static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6324{
6325 struct vcpu_vmx *vmx =
6326 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6327
6328 vmx->nested.preemption_timer_expired = true;
6329 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6330 kvm_vcpu_kick(&vmx->vcpu);
6331
6332 return HRTIMER_NORESTART;
6333}
6334
19677e32
BD		 6335/*
6336 * Decode the memory-address operand of a vmx instruction, as recorded on an
6337 * exit caused by such an instruction (run by a guest hypervisor).
6338 * On success, returns 0. When the operand is invalid, returns 1 and throws
6339 * #UD or #GP.
6340 */
6341static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6342 unsigned long exit_qualification,
f9eb4af6 6343 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6344{
f9eb4af6
EK		 6345 gva_t off;
6346 bool exn;
6347 struct kvm_segment s;
6348
19677e32
BD		 6349 /*
6350 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6351 * Execution", on an exit, vmx_instruction_info holds most of the
6352 * addressing components of the operand. Only the displacement part
6353 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6354 * For how an actual address is calculated from all these components,
6355 * refer to Vol. 1, "Operand Addressing".
6356 */
6357 int scaling = vmx_instruction_info & 3;
6358 int addr_size = (vmx_instruction_info >> 7) & 7;
6359 bool is_reg = vmx_instruction_info & (1u << 10);
6360 int seg_reg = (vmx_instruction_info >> 15) & 7;
6361 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6362 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6363 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6364 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6365
6366 if (is_reg) {
6367 kvm_queue_exception(vcpu, UD_VECTOR);
6368 return 1;
6369 }
6370
6371 /* Addr = segment_base + offset */
6372 /* offset = base + [index * scale] + displacement */
f9eb4af6 6373 off = exit_qualification; /* holds the displacement */
19677e32 6374 if (base_is_valid)
f9eb4af6 6375 off += kvm_register_read(vcpu, base_reg);
19677e32 6376 if (index_is_valid)
f9eb4af6
EK		 6377 off += kvm_register_read(vcpu, index_reg)<<scaling;
6378 vmx_get_segment(vcpu, &s, seg_reg);
6379 *ret = s.base + off;
19677e32
BD		 6380
6381 if (addr_size == 1) /* 32 bit */
6382 *ret &= 0xffffffff;
6383
f9eb4af6
EK		 6384 /* Checks for #GP/#SS exceptions. */
6385 exn = false;
6386 if (is_protmode(vcpu)) {
6387 /* Protected mode: apply checks for segment validity in the
6388 * following order:
6389 * - segment type check (#GP(0) may be thrown)
6390 * - usability check (#GP(0)/#SS(0))
6391 * - limit check (#GP(0)/#SS(0))
6392 */
6393 if (wr)
6394 /* #GP(0) if the destination operand is located in a
6395 * read-only data segment or any code segment.
6396 */
6397 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6398 else
6399 /* #GP(0) if the source operand is located in an
6400 * execute-only code segment
6401 */
6402 exn = ((s.type & 0xa) == 8);
6403 }
6404 if (exn) {
6405 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6406 return 1;
6407 }
6408 if (is_long_mode(vcpu)) {
6409 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6410 * non-canonical form. This is an only check for long mode.
6411 */
6412 exn = is_noncanonical_address(*ret);
6413 } else if (is_protmode(vcpu)) {
6414 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6415 */
6416 exn = (s.unusable != 0);
6417 /* Protected mode: #GP(0)/#SS(0) if the memory
6418 * operand is outside the segment limit.
6419 */
6420 exn = exn || (off + sizeof(u64) > s.limit);
6421 }
6422 if (exn) {
6423 kvm_queue_exception_e(vcpu,
6424 seg_reg == VCPU_SREG_SS ?
6425 SS_VECTOR : GP_VECTOR,
6426 0);
6427 return 1;
6428 }
6429
19677e32
BD		 6430 return 0;
6431}
6432
3573e22c
BD		 6433/*
6434 * This function performs the various checks including
6435 * - if it's 4KB aligned
6436 * - No bits beyond the physical address width are set
6437 * - Returns 0 on success or else 1
4291b588 6438 * (Intel SDM Section 30.3)
3573e22c 6439 */
4291b588
BD		 6440static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6441 gpa_t *vmpointer)
3573e22c
BD		 6442{
6443 gva_t gva;
6444 gpa_t vmptr;
6445 struct x86_exception e;
6446 struct page *page;
6447 struct vcpu_vmx *vmx = to_vmx(vcpu);
6448 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6449
6450 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 6451 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD		 6452 return 1;
6453
6454 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6455 sizeof(vmptr), &e)) {
6456 kvm_inject_page_fault(vcpu, &e);
6457 return 1;
6458 }
6459
6460 switch (exit_reason) {
6461 case EXIT_REASON_VMON:
6462 /*
6463 * SDM 3: 24.11.5
6464 * The first 4 bytes of VMXON region contain the supported
6465 * VMCS revision identifier
6466 *
6467 * Note - IA32_VMX_BASIC[48] will never be 1
6468 * for the nested case;
6469 * which replaces physical address width with 32
6470 *
6471 */
bc39c4db 6472 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6473 nested_vmx_failInvalid(vcpu);
6474 skip_emulated_instruction(vcpu);
6475 return 1;
6476 }
6477
6478 page = nested_get_page(vcpu, vmptr);
6479 if (page == NULL ||
6480 *(u32 *)kmap(page) != VMCS12_REVISION) {
6481 nested_vmx_failInvalid(vcpu);
6482 kunmap(page);
6483 skip_emulated_instruction(vcpu);
6484 return 1;
6485 }
6486 kunmap(page);
6487 vmx->nested.vmxon_ptr = vmptr;
6488 break;
4291b588 6489 case EXIT_REASON_VMCLEAR:
bc39c4db 6490 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6491 nested_vmx_failValid(vcpu,
6492 VMXERR_VMCLEAR_INVALID_ADDRESS);
6493 skip_emulated_instruction(vcpu);
6494 return 1;
6495 }
6496
6497 if (vmptr == vmx->nested.vmxon_ptr) {
6498 nested_vmx_failValid(vcpu,
6499 VMXERR_VMCLEAR_VMXON_POINTER);
6500 skip_emulated_instruction(vcpu);
6501 return 1;
6502 }
6503 break;
6504 case EXIT_REASON_VMPTRLD:
bc39c4db 6505 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6506 nested_vmx_failValid(vcpu,
6507 VMXERR_VMPTRLD_INVALID_ADDRESS);
6508 skip_emulated_instruction(vcpu);
6509 return 1;
6510 }
3573e22c 6511
4291b588
BD		 6512 if (vmptr == vmx->nested.vmxon_ptr) {
6513 nested_vmx_failValid(vcpu,
6514 VMXERR_VMCLEAR_VMXON_POINTER);
6515 skip_emulated_instruction(vcpu);
6516 return 1;
6517 }
6518 break;
3573e22c
BD		 6519 default:
6520 return 1; /* shouldn't happen */
6521 }
6522
4291b588
BD		 6523 if (vmpointer)
6524 *vmpointer = vmptr;
3573e22c
BD		 6525 return 0;
6526}
6527
ec378aee
NHE		 6528/*
6529 * Emulate the VMXON instruction.
6530 * Currently, we just remember that VMX is active, and do not save or even
6531 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6532 * do not currently need to store anything in that guest-allocated memory
6533 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6534 * argument is different from the VMXON pointer (which the spec says they do).
6535 */
6536static int handle_vmon(struct kvm_vcpu *vcpu)
6537{
6538 struct kvm_segment cs;
6539 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6540 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6541 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6542 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6543
6544 /* The Intel VMX Instruction Reference lists a bunch of bits that
6545 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6546 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6547 * Otherwise, we should fail with #UD. We test these now:
6548 */
6549 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6550 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6551 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6552 kvm_queue_exception(vcpu, UD_VECTOR);
6553 return 1;
6554 }
6555
6556 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6557 if (is_long_mode(vcpu) && !cs.l) {
6558 kvm_queue_exception(vcpu, UD_VECTOR);
6559 return 1;
6560 }
6561
6562 if (vmx_get_cpl(vcpu)) {
6563 kvm_inject_gp(vcpu, 0);
6564 return 1;
6565 }
3573e22c 6566
4291b588 6567 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6568 return 1;
6569
145c28dd
AG		 6570 if (vmx->nested.vmxon) {
6571 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6572 skip_emulated_instruction(vcpu);
6573 return 1;
6574 }
b3897a49
NHE		 6575
6576 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6577 != VMXON_NEEDED_FEATURES) {
6578 kvm_inject_gp(vcpu, 0);
6579 return 1;
6580 }
6581
8de48833
AG		 6582 if (enable_shadow_vmcs) {
6583 shadow_vmcs = alloc_vmcs();
6584 if (!shadow_vmcs)
6585 return -ENOMEM;
6586 /* mark vmcs as shadow */
6587 shadow_vmcs->revision_id |= (1u << 31);
6588 /* init shadow vmcs */
6589 vmcs_clear(shadow_vmcs);
6590 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6591 }
ec378aee 6592
ff2f6fe9
NHE		 6593 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6594 vmx->nested.vmcs02_num = 0;
6595
f4124500
JK		 6596 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6597 HRTIMER_MODE_REL);
6598 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6599
ec378aee
NHE		 6600 vmx->nested.vmxon = true;
6601
6602 skip_emulated_instruction(vcpu);
a25eb114 6603 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6604 return 1;
6605}
6606
6607/*
6608 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6609 * for running VMX instructions (except VMXON, whose prerequisites are
6610 * slightly different). It also specifies what exception to inject otherwise.
6611 */
6612static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6613{
6614 struct kvm_segment cs;
6615 struct vcpu_vmx *vmx = to_vmx(vcpu);
6616
6617 if (!vmx->nested.vmxon) {
6618 kvm_queue_exception(vcpu, UD_VECTOR);
6619 return 0;
6620 }
6621
6622 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6623 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6624 (is_long_mode(vcpu) && !cs.l)) {
6625 kvm_queue_exception(vcpu, UD_VECTOR);
6626 return 0;
6627 }
6628
6629 if (vmx_get_cpl(vcpu)) {
6630 kvm_inject_gp(vcpu, 0);
6631 return 0;
6632 }
6633
6634 return 1;
6635}
6636
e7953d7f
AG		 6637static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6638{
8a1b9dd0 6639 u32 exec_control;
9a2a05b9
PB		 6640 if (vmx->nested.current_vmptr == -1ull)
6641 return;
6642
6643 /* current_vmptr and current_vmcs12 are always set/reset together */
6644 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6645 return;
6646
012f83cb 6647 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6648 /* copy to memory all shadowed fields in case
6649 they were modified */
6650 copy_shadow_to_vmcs12(vmx);
6651 vmx->nested.sync_shadow_vmcs = false;
6652 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6653 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6654 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6655 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6656 }
705699a1 6657 vmx->nested.posted_intr_nv = -1;
e7953d7f
AG		 6658 kunmap(vmx->nested.current_vmcs12_page);
6659 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6660 vmx->nested.current_vmptr = -1ull;
6661 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6662}
6663
ec378aee
NHE		 6664/*
6665 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6666 * just stops using VMX.
6667 */
6668static void free_nested(struct vcpu_vmx *vmx)
6669{
6670 if (!vmx->nested.vmxon)
6671 return;
9a2a05b9 6672
ec378aee 6673 vmx->nested.vmxon = false;
9a2a05b9 6674 nested_release_vmcs12(vmx);
e7953d7f
AG		 6675 if (enable_shadow_vmcs)
6676 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6677 /* Unpin physical memory we referred to in current vmcs02 */
6678 if (vmx->nested.apic_access_page) {
6679 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6680 vmx->nested.apic_access_page = NULL;
fe3ef05c 6681 }
a7c0b07d
WL		 6682 if (vmx->nested.virtual_apic_page) {
6683 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6684 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6685 }
705699a1
WV		 6686 if (vmx->nested.pi_desc_page) {
6687 kunmap(vmx->nested.pi_desc_page);
6688 nested_release_page(vmx->nested.pi_desc_page);
6689 vmx->nested.pi_desc_page = NULL;
6690 vmx->nested.pi_desc = NULL;
6691 }
ff2f6fe9
NHE		 6692
6693 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6694}
6695
6696/* Emulate the VMXOFF instruction */
6697static int handle_vmoff(struct kvm_vcpu *vcpu)
6698{
6699 if (!nested_vmx_check_permission(vcpu))
6700 return 1;
6701 free_nested(to_vmx(vcpu));
6702 skip_emulated_instruction(vcpu);
a25eb114 6703 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6704 return 1;
6705}
6706
27d6c865
NHE		 6707/* Emulate the VMCLEAR instruction */
6708static int handle_vmclear(struct kvm_vcpu *vcpu)
6709{
6710 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6711 gpa_t vmptr;
6712 struct vmcs12 *vmcs12;
6713 struct page *page;
27d6c865
NHE		 6714
6715 if (!nested_vmx_check_permission(vcpu))
6716 return 1;
6717
4291b588 6718 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6719 return 1;
27d6c865 6720
9a2a05b9 6721 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6722 nested_release_vmcs12(vmx);
27d6c865
NHE		 6723
6724 page = nested_get_page(vcpu, vmptr);
6725 if (page == NULL) {
6726 /*
6727 * For accurate processor emulation, VMCLEAR beyond available
6728 * physical memory should do nothing at all. However, it is
6729 * possible that a nested vmx bug, not a guest hypervisor bug,
6730 * resulted in this case, so let's shut down before doing any
6731 * more damage:
6732 */
6733 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6734 return 1;
6735 }
6736 vmcs12 = kmap(page);
6737 vmcs12->launch_state = 0;
6738 kunmap(page);
6739 nested_release_page(page);
6740
6741 nested_free_vmcs02(vmx, vmptr);
6742
6743 skip_emulated_instruction(vcpu);
6744 nested_vmx_succeed(vcpu);
6745 return 1;
6746}
6747
cd232ad0
NHE		 6748static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6749
6750/* Emulate the VMLAUNCH instruction */
6751static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6752{
6753 return nested_vmx_run(vcpu, true);
6754}
6755
6756/* Emulate the VMRESUME instruction */
6757static int handle_vmresume(struct kvm_vcpu *vcpu)
6758{
6759
6760 return nested_vmx_run(vcpu, false);
6761}
6762
49f705c5
NHE		 6763enum vmcs_field_type {
6764 VMCS_FIELD_TYPE_U16 = 0,
6765 VMCS_FIELD_TYPE_U64 = 1,
6766 VMCS_FIELD_TYPE_U32 = 2,
6767 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6768};
6769
6770static inline int vmcs_field_type(unsigned long field)
6771{
6772 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6773 return VMCS_FIELD_TYPE_U32;
6774 return (field >> 13) & 0x3 ;
6775}
6776
6777static inline int vmcs_field_readonly(unsigned long field)
6778{
6779 return (((field >> 10) & 0x3) == 1);
6780}
6781
6782/*
6783 * Read a vmcs12 field. Since these can have varying lengths and we return
6784 * one type, we chose the biggest type (u64) and zero-extend the return value
6785 * to that size. Note that the caller, handle_vmread, might need to use only
6786 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6787 * 64-bit fields are to be returned).
6788 */
a2ae9df7
PB		 6789static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6790 unsigned long field, u64 *ret)
49f705c5
NHE		 6791{
6792 short offset = vmcs_field_to_offset(field);
6793 char *p;
6794
6795 if (offset < 0)
a2ae9df7 6796 return offset;
49f705c5
NHE		 6797
6798 p = ((char *)(get_vmcs12(vcpu))) + offset;
6799
6800 switch (vmcs_field_type(field)) {
6801 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6802 *ret = *((natural_width *)p);
a2ae9df7 6803 return 0;
49f705c5
NHE		 6804 case VMCS_FIELD_TYPE_U16:
6805 *ret = *((u16 *)p);
a2ae9df7 6806 return 0;
49f705c5
NHE		 6807 case VMCS_FIELD_TYPE_U32:
6808 *ret = *((u32 *)p);
a2ae9df7 6809 return 0;
49f705c5
NHE		 6810 case VMCS_FIELD_TYPE_U64:
6811 *ret = *((u64 *)p);
a2ae9df7 6812 return 0;
49f705c5 6813 default:
a2ae9df7
PB		 6814 WARN_ON(1);
6815 return -ENOENT;
49f705c5
NHE		 6816 }
6817}
6818
20b97fea 6819
a2ae9df7
PB		 6820static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6821 unsigned long field, u64 field_value){
20b97fea
AG		 6822 short offset = vmcs_field_to_offset(field);
6823 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6824 if (offset < 0)
a2ae9df7 6825 return offset;
20b97fea
AG		 6826
6827 switch (vmcs_field_type(field)) {
6828 case VMCS_FIELD_TYPE_U16:
6829 *(u16 *)p = field_value;
a2ae9df7 6830 return 0;
20b97fea
AG		 6831 case VMCS_FIELD_TYPE_U32:
6832 *(u32 *)p = field_value;
a2ae9df7 6833 return 0;
20b97fea
AG		 6834 case VMCS_FIELD_TYPE_U64:
6835 *(u64 *)p = field_value;
a2ae9df7 6836 return 0;
20b97fea
AG		 6837 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6838 *(natural_width *)p = field_value;
a2ae9df7 6839 return 0;
20b97fea 6840 default:
a2ae9df7
PB		 6841 WARN_ON(1);
6842 return -ENOENT;
20b97fea
AG		 6843 }
6844
6845}
6846
16f5b903
AG		 6847static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6848{
6849 int i;
6850 unsigned long field;
6851 u64 field_value;
6852 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6853 const unsigned long *fields = shadow_read_write_fields;
6854 const int num_fields = max_shadow_read_write_fields;
16f5b903 6855
282da870
JK		 6856 preempt_disable();
6857
16f5b903
AG		 6858 vmcs_load(shadow_vmcs);
6859
6860 for (i = 0; i < num_fields; i++) {
6861 field = fields[i];
6862 switch (vmcs_field_type(field)) {
6863 case VMCS_FIELD_TYPE_U16:
6864 field_value = vmcs_read16(field);
6865 break;
6866 case VMCS_FIELD_TYPE_U32:
6867 field_value = vmcs_read32(field);
6868 break;
6869 case VMCS_FIELD_TYPE_U64:
6870 field_value = vmcs_read64(field);
6871 break;
6872 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6873 field_value = vmcs_readl(field);
6874 break;
a2ae9df7
PB		 6875 default:
6876 WARN_ON(1);
6877 continue;
16f5b903
AG		 6878 }
6879 vmcs12_write_any(&vmx->vcpu, field, field_value);
6880 }
6881
6882 vmcs_clear(shadow_vmcs);
6883 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6884
6885 preempt_enable();
16f5b903
AG		 6886}
6887
c3114420
AG		 6888static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6889{
c2bae893
MK		 6890 const unsigned long *fields[] = {
6891 shadow_read_write_fields,
6892 shadow_read_only_fields
c3114420 6893 };
c2bae893 6894 const int max_fields[] = {
c3114420
AG		 6895 max_shadow_read_write_fields,
6896 max_shadow_read_only_fields
6897 };
6898 int i, q;
6899 unsigned long field;
6900 u64 field_value = 0;
6901 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6902
6903 vmcs_load(shadow_vmcs);
6904
c2bae893 6905 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6906 for (i = 0; i < max_fields[q]; i++) {
6907 field = fields[q][i];
6908 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6909
6910 switch (vmcs_field_type(field)) {
6911 case VMCS_FIELD_TYPE_U16:
6912 vmcs_write16(field, (u16)field_value);
6913 break;
6914 case VMCS_FIELD_TYPE_U32:
6915 vmcs_write32(field, (u32)field_value);
6916 break;
6917 case VMCS_FIELD_TYPE_U64:
6918 vmcs_write64(field, (u64)field_value);
6919 break;
6920 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6921 vmcs_writel(field, (long)field_value);
6922 break;
a2ae9df7
PB		 6923 default:
6924 WARN_ON(1);
6925 break;
c3114420
AG		 6926 }
6927 }
6928 }
6929
6930 vmcs_clear(shadow_vmcs);
6931 vmcs_load(vmx->loaded_vmcs->vmcs);
6932}
6933
49f705c5
NHE		 6934/*
6935 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6936 * used before) all generate the same failure when it is missing.
6937 */
6938static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6939{
6940 struct vcpu_vmx *vmx = to_vmx(vcpu);
6941 if (vmx->nested.current_vmptr == -1ull) {
6942 nested_vmx_failInvalid(vcpu);
6943 skip_emulated_instruction(vcpu);
6944 return 0;
6945 }
6946 return 1;
6947}
6948
6949static int handle_vmread(struct kvm_vcpu *vcpu)
6950{
6951 unsigned long field;
6952 u64 field_value;
6953 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6954 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6955 gva_t gva = 0;
6956
6957 if (!nested_vmx_check_permission(vcpu) ||
6958 !nested_vmx_check_vmcs12(vcpu))
6959 return 1;
6960
6961 /* Decode instruction info and find the field to read */
27e6fb5d 6962 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6963 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6964 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6965 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6966 skip_emulated_instruction(vcpu);
6967 return 1;
6968 }
6969 /*
6970 * Now copy part of this value to register or memory, as requested.
6971 * Note that the number of bits actually copied is 32 or 64 depending
6972 * on the guest's mode (32 or 64 bit), not on the given field's length.
6973 */
6974 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6975 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6976 field_value);
6977 } else {
6978 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 6979 vmx_instruction_info, true, &gva))
49f705c5
NHE		 6980 return 1;
6981 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6982 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6983 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6984 }
6985
6986 nested_vmx_succeed(vcpu);
6987 skip_emulated_instruction(vcpu);
6988 return 1;
6989}
6990
6991
6992static int handle_vmwrite(struct kvm_vcpu *vcpu)
6993{
6994 unsigned long field;
6995 gva_t gva;
6996 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6997 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6998 /* The value to write might be 32 or 64 bits, depending on L1's long
6999 * mode, and eventually we need to write that into a field of several
7000 * possible lengths. The code below first zero-extends the value to 64
7001 * bit (field_value), and then copies only the approriate number of
7002 * bits into the vmcs12 field.
7003 */
7004 u64 field_value = 0;
7005 struct x86_exception e;
7006
7007 if (!nested_vmx_check_permission(vcpu) ||
7008 !nested_vmx_check_vmcs12(vcpu))
7009 return 1;
7010
7011 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7012 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 7013 (((vmx_instruction_info) >> 3) & 0xf));
7014 else {
7015 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7016 vmx_instruction_info, false, &gva))
49f705c5
NHE		 7017 return 1;
7018 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7019 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 7020 kvm_inject_page_fault(vcpu, &e);
7021 return 1;
7022 }
7023 }
7024
7025
27e6fb5d 7026 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 7027 if (vmcs_field_readonly(field)) {
7028 nested_vmx_failValid(vcpu,
7029 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7030 skip_emulated_instruction(vcpu);
7031 return 1;
7032 }
7033
a2ae9df7 7034 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 7035 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7036 skip_emulated_instruction(vcpu);
7037 return 1;
7038 }
7039
7040 nested_vmx_succeed(vcpu);
7041 skip_emulated_instruction(vcpu);
7042 return 1;
7043}
7044
63846663
NHE		 7045/* Emulate the VMPTRLD instruction */
7046static int handle_vmptrld(struct kvm_vcpu *vcpu)
7047{
7048 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7049 gpa_t vmptr;
8a1b9dd0 7050 u32 exec_control;
63846663
NHE		 7051
7052 if (!nested_vmx_check_permission(vcpu))
7053 return 1;
7054
4291b588 7055 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 7056 return 1;
63846663
NHE		 7057
7058 if (vmx->nested.current_vmptr != vmptr) {
7059 struct vmcs12 *new_vmcs12;
7060 struct page *page;
7061 page = nested_get_page(vcpu, vmptr);
7062 if (page == NULL) {
7063 nested_vmx_failInvalid(vcpu);
7064 skip_emulated_instruction(vcpu);
7065 return 1;
7066 }
7067 new_vmcs12 = kmap(page);
7068 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7069 kunmap(page);
7070 nested_release_page_clean(page);
7071 nested_vmx_failValid(vcpu,
7072 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7073 skip_emulated_instruction(vcpu);
7074 return 1;
7075 }
63846663 7076
9a2a05b9 7077 nested_release_vmcs12(vmx);
63846663
NHE		 7078 vmx->nested.current_vmptr = vmptr;
7079 vmx->nested.current_vmcs12 = new_vmcs12;
7080 vmx->nested.current_vmcs12_page = page;
012f83cb 7081 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 7082 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7083 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7084 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7085 vmcs_write64(VMCS_LINK_POINTER,
7086 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 7087 vmx->nested.sync_shadow_vmcs = true;
7088 }
63846663
NHE		 7089 }
7090
7091 nested_vmx_succeed(vcpu);
7092 skip_emulated_instruction(vcpu);
7093 return 1;
7094}
7095
6a4d7550
NHE		 7096/* Emulate the VMPTRST instruction */
7097static int handle_vmptrst(struct kvm_vcpu *vcpu)
7098{
7099 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7100 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7101 gva_t vmcs_gva;
7102 struct x86_exception e;
7103
7104 if (!nested_vmx_check_permission(vcpu))
7105 return 1;
7106
7107 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7108 vmx_instruction_info, true, &vmcs_gva))
6a4d7550
NHE		 7109 return 1;
7110 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7111 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7112 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7113 sizeof(u64), &e)) {
7114 kvm_inject_page_fault(vcpu, &e);
7115 return 1;
7116 }
7117 nested_vmx_succeed(vcpu);
7118 skip_emulated_instruction(vcpu);
7119 return 1;
7120}
7121
bfd0a56b
NHE		 7122/* Emulate the INVEPT instruction */
7123static int handle_invept(struct kvm_vcpu *vcpu)
7124{
b9c237bb 7125 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7126 u32 vmx_instruction_info, types;
7127 unsigned long type;
7128 gva_t gva;
7129 struct x86_exception e;
7130 struct {
7131 u64 eptp, gpa;
7132 } operand;
bfd0a56b 7133
b9c237bb
WV		 7134 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7135 SECONDARY_EXEC_ENABLE_EPT) ||
7136 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7137 kvm_queue_exception(vcpu, UD_VECTOR);
7138 return 1;
7139 }
7140
7141 if (!nested_vmx_check_permission(vcpu))
7142 return 1;
7143
7144 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7145 kvm_queue_exception(vcpu, UD_VECTOR);
7146 return 1;
7147 }
7148
7149 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7150 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7151
b9c237bb 7152 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7153
7154 if (!(types & (1UL << type))) {
7155 nested_vmx_failValid(vcpu,
7156 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7157 return 1;
7158 }
7159
7160 /* According to the Intel VMX instruction reference, the memory
7161 * operand is read even if it isn't needed (e.g., for type==global)
7162 */
7163 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7164 vmx_instruction_info, false, &gva))
bfd0a56b
NHE		 7165 return 1;
7166 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7167 sizeof(operand), &e)) {
7168 kvm_inject_page_fault(vcpu, &e);
7169 return 1;
7170 }
7171
7172 switch (type) {
bfd0a56b
NHE		 7173 case VMX_EPT_EXTENT_GLOBAL:
7174 kvm_mmu_sync_roots(vcpu);
77c3913b 7175 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7176 nested_vmx_succeed(vcpu);
7177 break;
7178 default:
4b855078 7179 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7180 BUG_ON(1);
7181 break;
7182 }
7183
7184 skip_emulated_instruction(vcpu);
7185 return 1;
7186}
7187
a642fc30
PM		 7188static int handle_invvpid(struct kvm_vcpu *vcpu)
7189{
7190 kvm_queue_exception(vcpu, UD_VECTOR);
7191 return 1;
7192}
7193
843e4330
KH		 7194static int handle_pml_full(struct kvm_vcpu *vcpu)
7195{
7196 unsigned long exit_qualification;
7197
7198 trace_kvm_pml_full(vcpu->vcpu_id);
7199
7200 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7201
7202 /*
7203 * PML buffer FULL happened while executing iret from NMI,
7204 * "blocked by NMI" bit has to be set before next VM entry.
7205 */
7206 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7207 cpu_has_virtual_nmis() &&
7208 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7209 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7210 GUEST_INTR_STATE_NMI);
7211
7212 /*
7213 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7214 * here.., and there's no userspace involvement needed for PML.
7215 */
7216 return 1;
7217}
7218
8b3e34e4
XG		 7219static int handle_pcommit(struct kvm_vcpu *vcpu)
7220{
7221 /* we never catch pcommit instruct for L1 guest. */
7222 WARN_ON(1);
7223 return 1;
7224}
7225
6aa8b732
AK		 7226/*
7227 * The exit handlers return 1 if the exit was handled fully and guest execution
7228 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7229 * to be done to userspace and return 0.
7230 */
772e0318 7231static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7232 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7233 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7234 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7235 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7236 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7237 [EXIT_REASON_CR_ACCESS] = handle_cr,
7238 [EXIT_REASON_DR_ACCESS] = handle_dr,
7239 [EXIT_REASON_CPUID] = handle_cpuid,
7240 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7241 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7242 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7243 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7244 [EXIT_REASON_INVD] = handle_invd,
a7052897 7245 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7246 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7247 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7248 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7249 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7250 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7251 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7252 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7253 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7254 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7255 [EXIT_REASON_VMOFF] = handle_vmoff,
7256 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7257 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7258 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7259 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7260 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7261 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7262 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7263 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7264 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7265 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7266 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7267 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7268 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7269 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7270 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7271 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7272 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7273 [EXIT_REASON_XSAVES] = handle_xsaves,
7274 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7275 [EXIT_REASON_PML_FULL] = handle_pml_full,
8b3e34e4 7276 [EXIT_REASON_PCOMMIT] = handle_pcommit,
6aa8b732
AK		 7277};
7278
7279static const int kvm_vmx_max_exit_handlers =
50a3485c 7280 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7281
908a7bdd
JK		 7282static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7283 struct vmcs12 *vmcs12)
7284{
7285 unsigned long exit_qualification;
7286 gpa_t bitmap, last_bitmap;
7287 unsigned int port;
7288 int size;
7289 u8 b;
7290
908a7bdd 7291 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7292 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7293
7294 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7295
7296 port = exit_qualification >> 16;
7297 size = (exit_qualification & 7) + 1;
7298
7299 last_bitmap = (gpa_t)-1;
7300 b = -1;
7301
7302 while (size > 0) {
7303 if (port < 0x8000)
7304 bitmap = vmcs12->io_bitmap_a;
7305 else if (port < 0x10000)
7306 bitmap = vmcs12->io_bitmap_b;
7307 else
1d804d07 7308 return true;
908a7bdd
JK		 7309 bitmap += (port & 0x7fff) / 8;
7310
7311 if (last_bitmap != bitmap)
54bf36aa 7312 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7313 return true;
908a7bdd 7314 if (b & (1 << (port & 7)))
1d804d07 7315 return true;
908a7bdd
JK		 7316
7317 port++;
7318 size--;
7319 last_bitmap = bitmap;
7320 }
7321
1d804d07 7322 return false;
908a7bdd
JK		 7323}
7324
644d711a
NHE		 7325/*
7326 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7327 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7328 * disinterest in the current event (read or write a specific MSR) by using an
7329 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7330 */
7331static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7332 struct vmcs12 *vmcs12, u32 exit_reason)
7333{
7334 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7335 gpa_t bitmap;
7336
cbd29cb6 7337 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7338 return true;
644d711a
NHE		 7339
7340 /*
7341 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7342 * for the four combinations of read/write and low/high MSR numbers.
7343 * First we need to figure out which of the four to use:
7344 */
7345 bitmap = vmcs12->msr_bitmap;
7346 if (exit_reason == EXIT_REASON_MSR_WRITE)
7347 bitmap += 2048;
7348 if (msr_index >= 0xc0000000) {
7349 msr_index -= 0xc0000000;
7350 bitmap += 1024;
7351 }
7352
7353 /* Then read the msr_index'th bit from this bitmap: */
7354 if (msr_index < 1024*8) {
7355 unsigned char b;
54bf36aa 7356 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7357 return true;
644d711a
NHE		 7358 return 1 & (b >> (msr_index & 7));
7359 } else
1d804d07 7360 return true; /* let L1 handle the wrong parameter */
644d711a
NHE		 7361}
7362
7363/*
7364 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7365 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7366 * intercept (via guest_host_mask etc.) the current event.
7367 */
7368static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7369 struct vmcs12 *vmcs12)
7370{
7371 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7372 int cr = exit_qualification & 15;
7373 int reg = (exit_qualification >> 8) & 15;
1e32c079 7374 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7375
7376 switch ((exit_qualification >> 4) & 3) {
7377 case 0: /* mov to cr */
7378 switch (cr) {
7379 case 0:
7380 if (vmcs12->cr0_guest_host_mask &
7381 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7382 return true;
644d711a
NHE		 7383 break;
7384 case 3:
7385 if ((vmcs12->cr3_target_count >= 1 &&
7386 vmcs12->cr3_target_value0 == val) ||
7387 (vmcs12->cr3_target_count >= 2 &&
7388 vmcs12->cr3_target_value1 == val) ||
7389 (vmcs12->cr3_target_count >= 3 &&
7390 vmcs12->cr3_target_value2 == val) ||
7391 (vmcs12->cr3_target_count >= 4 &&
7392 vmcs12->cr3_target_value3 == val))
1d804d07 7393 return false;
644d711a 7394 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7395 return true;
644d711a
NHE		 7396 break;
7397 case 4:
7398 if (vmcs12->cr4_guest_host_mask &
7399 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7400 return true;
644d711a
NHE		 7401 break;
7402 case 8:
7403 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7404 return true;
644d711a
NHE		 7405 break;
7406 }
7407 break;
7408 case 2: /* clts */
7409 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7410 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7411 return true;
644d711a
NHE		 7412 break;
7413 case 1: /* mov from cr */
7414 switch (cr) {
7415 case 3:
7416 if (vmcs12->cpu_based_vm_exec_control &
7417 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7418 return true;
644d711a
NHE		 7419 break;
7420 case 8:
7421 if (vmcs12->cpu_based_vm_exec_control &
7422 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7423 return true;
644d711a
NHE		 7424 break;
7425 }
7426 break;
7427 case 3: /* lmsw */
7428 /*
7429 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7430 * cr0. Other attempted changes are ignored, with no exit.
7431 */
7432 if (vmcs12->cr0_guest_host_mask & 0xe &
7433 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7434 return true;
644d711a
NHE		 7435 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7436 !(vmcs12->cr0_read_shadow & 0x1) &&
7437 (val & 0x1))
1d804d07 7438 return true;
644d711a
NHE		 7439 break;
7440 }
1d804d07 7441 return false;
644d711a
NHE		 7442}
7443
7444/*
7445 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7446 * should handle it ourselves in L0 (and then continue L2). Only call this
7447 * when in is_guest_mode (L2).
7448 */
7449static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7450{
644d711a
NHE		 7451 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7452 struct vcpu_vmx *vmx = to_vmx(vcpu);
7453 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7454 u32 exit_reason = vmx->exit_reason;
644d711a 7455
542060ea
JK		 7456 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7457 vmcs_readl(EXIT_QUALIFICATION),
7458 vmx->idt_vectoring_info,
7459 intr_info,
7460 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7461 KVM_ISA_VMX);
7462
644d711a 7463 if (vmx->nested.nested_run_pending)
1d804d07 7464 return false;
644d711a
NHE		 7465
7466 if (unlikely(vmx->fail)) {
bd80158a
JK		 7467 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7468 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 7469 return true;
644d711a
NHE		 7470 }
7471
7472 switch (exit_reason) {
7473 case EXIT_REASON_EXCEPTION_NMI:
7474 if (!is_exception(intr_info))
1d804d07 7475 return false;
644d711a
NHE		 7476 else if (is_page_fault(intr_info))
7477 return enable_ept;
e504c909 7478 else if (is_no_device(intr_info) &&
ccf9844e 7479 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 7480 return false;
644d711a
NHE		 7481 return vmcs12->exception_bitmap &
7482 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7483 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 7484 return false;
644d711a 7485 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 7486 return true;
644d711a 7487 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7488 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7489 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7490 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 7491 case EXIT_REASON_TASK_SWITCH:
1d804d07 7492 return true;
644d711a 7493 case EXIT_REASON_CPUID:
bc613494 7494 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
1d804d07
JP		 7495 return false;
7496 return true;
644d711a
NHE		 7497 case EXIT_REASON_HLT:
7498 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7499 case EXIT_REASON_INVD:
1d804d07 7500 return true;
644d711a
NHE		 7501 case EXIT_REASON_INVLPG:
7502 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7503 case EXIT_REASON_RDPMC:
7504 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
b3a2a907 7505 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE		 7506 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7507 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7508 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7509 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7510 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7511 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7512 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7513 /*
7514 * VMX instructions trap unconditionally. This allows L1 to
7515 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7516 */
1d804d07 7517 return true;
644d711a
NHE		 7518 case EXIT_REASON_CR_ACCESS:
7519 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7520 case EXIT_REASON_DR_ACCESS:
7521 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7522 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7523 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7524 case EXIT_REASON_MSR_READ:
7525 case EXIT_REASON_MSR_WRITE:
7526 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7527 case EXIT_REASON_INVALID_STATE:
1d804d07 7528 return true;
644d711a
NHE		 7529 case EXIT_REASON_MWAIT_INSTRUCTION:
7530 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD		 7531 case EXIT_REASON_MONITOR_TRAP_FLAG:
7532 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE		 7533 case EXIT_REASON_MONITOR_INSTRUCTION:
7534 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7535 case EXIT_REASON_PAUSE_INSTRUCTION:
7536 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7537 nested_cpu_has2(vmcs12,
7538 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7539 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 7540 return false;
644d711a 7541 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7542 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7543 case EXIT_REASON_APIC_ACCESS:
7544 return nested_cpu_has2(vmcs12,
7545 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 7546 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 7547 case EXIT_REASON_EOI_INDUCED:
7548 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 7549 return true;
644d711a 7550 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7551 /*
7552 * L0 always deals with the EPT violation. If nested EPT is
7553 * used, and the nested mmu code discovers that the address is
7554 * missing in the guest EPT table (EPT12), the EPT violation
7555 * will be injected with nested_ept_inject_page_fault()
7556 */
1d804d07 7557 return false;
644d711a 7558 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7559 /*
7560 * L2 never uses directly L1's EPT, but rather L0's own EPT
7561 * table (shadow on EPT) or a merged EPT table that L0 built
7562 * (EPT on EPT). So any problems with the structure of the
7563 * table is L0's fault.
7564 */
1d804d07 7565 return false;
644d711a
NHE		 7566 case EXIT_REASON_WBINVD:
7567 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7568 case EXIT_REASON_XSETBV:
1d804d07 7569 return true;
81dc01f7
WL		 7570 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7571 /*
7572 * This should never happen, since it is not possible to
7573 * set XSS to a non-zero value---neither in L1 nor in L2.
7574 * If if it were, XSS would have to be checked against
7575 * the XSS exit bitmap in vmcs12.
7576 */
7577 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8b3e34e4
XG		 7578 case EXIT_REASON_PCOMMIT:
7579 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
644d711a 7580 default:
1d804d07 7581 return true;
644d711a
NHE		 7582 }
7583}
7584
586f9607
AK		 7585static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7586{
7587 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7588 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7589}
7590
843e4330
KH		 7591static int vmx_enable_pml(struct vcpu_vmx *vmx)
7592{
7593 struct page *pml_pg;
7594 u32 exec_control;
7595
7596 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7597 if (!pml_pg)
7598 return -ENOMEM;
7599
7600 vmx->pml_pg = pml_pg;
7601
7602 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7603 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7604
7605 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7606 exec_control |= SECONDARY_EXEC_ENABLE_PML;
7607 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7608
7609 return 0;
7610}
7611
7612static void vmx_disable_pml(struct vcpu_vmx *vmx)
7613{
7614 u32 exec_control;
7615
7616 ASSERT(vmx->pml_pg);
7617 __free_page(vmx->pml_pg);
7618 vmx->pml_pg = NULL;
7619
7620 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7621 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7622 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7623}
7624
54bf36aa 7625static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 7626{
54bf36aa 7627 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH		 7628 u64 *pml_buf;
7629 u16 pml_idx;
7630
7631 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7632
7633 /* Do nothing if PML buffer is empty */
7634 if (pml_idx == (PML_ENTITY_NUM - 1))
7635 return;
7636
7637 /* PML index always points to next available PML buffer entity */
7638 if (pml_idx >= PML_ENTITY_NUM)
7639 pml_idx = 0;
7640 else
7641 pml_idx++;
7642
7643 pml_buf = page_address(vmx->pml_pg);
7644 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7645 u64 gpa;
7646
7647 gpa = pml_buf[pml_idx];
7648 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 7649 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH		 7650 }
7651
7652 /* reset PML index */
7653 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7654}
7655
7656/*
7657 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7658 * Called before reporting dirty_bitmap to userspace.
7659 */
7660static void kvm_flush_pml_buffers(struct kvm *kvm)
7661{
7662 int i;
7663 struct kvm_vcpu *vcpu;
7664 /*
7665 * We only need to kick vcpu out of guest mode here, as PML buffer
7666 * is flushed at beginning of all VMEXITs, and it's obvious that only
7667 * vcpus running in guest are possible to have unflushed GPAs in PML
7668 * buffer.
7669 */
7670 kvm_for_each_vcpu(i, vcpu, kvm)
7671 kvm_vcpu_kick(vcpu);
7672}
7673
4eb64dce
PB		 7674static void vmx_dump_sel(char *name, uint32_t sel)
7675{
7676 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7677 name, vmcs_read32(sel),
7678 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7679 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7680 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7681}
7682
7683static void vmx_dump_dtsel(char *name, uint32_t limit)
7684{
7685 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7686 name, vmcs_read32(limit),
7687 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7688}
7689
7690static void dump_vmcs(void)
7691{
7692 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7693 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7694 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7695 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7696 u32 secondary_exec_control = 0;
7697 unsigned long cr4 = vmcs_readl(GUEST_CR4);
7698 u64 efer = vmcs_readl(GUEST_IA32_EFER);
7699 int i, n;
7700
7701 if (cpu_has_secondary_exec_ctrls())
7702 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7703
7704 pr_err("*** Guest State ***\n");
7705 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7706 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7707 vmcs_readl(CR0_GUEST_HOST_MASK));
7708 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7709 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7710 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7711 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7712 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7713 {
7714 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7715 vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7716 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7717 vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7718 }
7719 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7720 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7721 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7722 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7723 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7724 vmcs_readl(GUEST_SYSENTER_ESP),
7725 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7726 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
7727 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
7728 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
7729 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
7730 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
7731 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
7732 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7733 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7734 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7735 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
7736 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7737 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7738 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7739 efer, vmcs_readl(GUEST_IA32_PAT));
7740 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7741 vmcs_readl(GUEST_IA32_DEBUGCTL),
7742 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7743 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7744 pr_err("PerfGlobCtl = 0x%016lx\n",
7745 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7746 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7747 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7748 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7749 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7750 vmcs_read32(GUEST_ACTIVITY_STATE));
7751 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7752 pr_err("InterruptStatus = %04x\n",
7753 vmcs_read16(GUEST_INTR_STATUS));
7754
7755 pr_err("*** Host State ***\n");
7756 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7757 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7758 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7759 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7760 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7761 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7762 vmcs_read16(HOST_TR_SELECTOR));
7763 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7764 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7765 vmcs_readl(HOST_TR_BASE));
7766 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7767 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7768 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7769 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7770 vmcs_readl(HOST_CR4));
7771 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7772 vmcs_readl(HOST_IA32_SYSENTER_ESP),
7773 vmcs_read32(HOST_IA32_SYSENTER_CS),
7774 vmcs_readl(HOST_IA32_SYSENTER_EIP));
7775 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7776 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7777 vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7778 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7779 pr_err("PerfGlobCtl = 0x%016lx\n",
7780 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7781
7782 pr_err("*** Control State ***\n");
7783 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7784 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7785 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7786 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7787 vmcs_read32(EXCEPTION_BITMAP),
7788 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7789 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7790 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7791 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7792 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
7793 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
7794 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
7795 vmcs_read32(VM_EXIT_INTR_INFO),
7796 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7797 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
7798 pr_err(" reason=%08x qualification=%016lx\n",
7799 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
7800 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
7801 vmcs_read32(IDT_VECTORING_INFO_FIELD),
7802 vmcs_read32(IDT_VECTORING_ERROR_CODE));
7803 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
7804 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
7805 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
7806 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
7807 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
7808 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
7809 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
7810 n = vmcs_read32(CR3_TARGET_COUNT);
7811 for (i = 0; i + 1 < n; i += 4)
7812 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
7813 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
7814 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
7815 if (i < n)
7816 pr_err("CR3 target%u=%016lx\n",
7817 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
7818 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
7819 pr_err("PLE Gap=%08x Window=%08x\n",
7820 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
7821 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
7822 pr_err("Virtual processor ID = 0x%04x\n",
7823 vmcs_read16(VIRTUAL_PROCESSOR_ID));
7824}
7825
6aa8b732
AK		 7826/*
7827 * The guest has exited. See if we can fix it or if we need userspace
7828 * assistance.
7829 */
851ba692 7830static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7831{
29bd8a78 7832 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7833 u32 exit_reason = vmx->exit_reason;
1155f76a 7834 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7835
843e4330
KH		 7836 /*
7837 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7838 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7839 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7840 * mode as if vcpus is in root mode, the PML buffer must has been
7841 * flushed already.
7842 */
7843 if (enable_pml)
54bf36aa 7844 vmx_flush_pml_buffer(vcpu);
843e4330 7845
80ced186 7846 /* If guest state is invalid, start emulating */
14168786 7847 if (vmx->emulation_required)
80ced186 7848 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7849
644d711a 7850 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7851 nested_vmx_vmexit(vcpu, exit_reason,
7852 vmcs_read32(VM_EXIT_INTR_INFO),
7853 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7854 return 1;
7855 }
7856
5120702e 7857 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 7858 dump_vmcs();
5120702e
MG		 7859 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7860 vcpu->run->fail_entry.hardware_entry_failure_reason
7861 = exit_reason;
7862 return 0;
7863 }
7864
29bd8a78 7865 if (unlikely(vmx->fail)) {
851ba692
AK		 7866 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7867 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7868 = vmcs_read32(VM_INSTRUCTION_ERROR);
7869 return 0;
7870 }
6aa8b732 7871
b9bf6882
XG		 7872 /*
7873 * Note:
7874 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7875 * delivery event since it indicates guest is accessing MMIO.
7876 * The vm-exit can be triggered again after return to guest that
7877 * will cause infinite loop.
7878 */
d77c26fc 7879 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7880 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7881 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7882 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7883 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7884 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7885 vcpu->run->internal.ndata = 2;
7886 vcpu->run->internal.data[0] = vectoring_info;
7887 vcpu->run->internal.data[1] = exit_reason;
7888 return 0;
7889 }
3b86cd99 7890
644d711a
NHE		 7891 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7892 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7893 get_vmcs12(vcpu))))) {
c4282df9 7894 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7895 vmx->soft_vnmi_blocked = 0;
3b86cd99 7896 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7897 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7898 /*
7899 * This CPU don't support us in finding the end of an
7900 * NMI-blocked window if the guest runs with IRQs
7901 * disabled. So we pull the trigger after 1 s of
7902 * futile waiting, but inform the user about this.
7903 */
7904 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7905 "state on VCPU %d after 1 s timeout\n",
7906 __func__, vcpu->vcpu_id);
7907 vmx->soft_vnmi_blocked = 0;
3b86cd99 7908 }
3b86cd99
JK		 7909 }
7910
6aa8b732
AK		 7911 if (exit_reason < kvm_vmx_max_exit_handlers
7912 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7913 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7914 else {
2bc19dc3
MT		 7915 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7916 kvm_queue_exception(vcpu, UD_VECTOR);
7917 return 1;
6aa8b732 7918 }
6aa8b732
AK		 7919}
7920
95ba8273 7921static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7922{
a7c0b07d
WL		 7923 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7924
7925 if (is_guest_mode(vcpu) &&
7926 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7927 return;
7928
95ba8273 7929 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7930 vmcs_write32(TPR_THRESHOLD, 0);
7931 return;
7932 }
7933
95ba8273 7934 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7935}
7936
8d14695f
YZ		 7937static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7938{
7939 u32 sec_exec_control;
7940
7941 /*
7942 * There is not point to enable virtualize x2apic without enable
7943 * apicv
7944 */
c7c9c56c 7945 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
35754c98 7946 !vmx_cpu_uses_apicv(vcpu))
8d14695f
YZ		 7947 return;
7948
35754c98 7949 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ		 7950 return;
7951
7952 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7953
7954 if (set) {
7955 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7956 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7957 } else {
7958 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7959 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7960 }
7961 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7962
7963 vmx_set_msr_bitmap(vcpu);
7964}
7965
38b99173
TC		 7966static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7967{
7968 struct vcpu_vmx *vmx = to_vmx(vcpu);
7969
7970 /*
7971 * Currently we do not handle the nested case where L2 has an
7972 * APIC access page of its own; that page is still pinned.
7973 * Hence, we skip the case where the VCPU is in guest mode _and_
7974 * L1 prepared an APIC access page for L2.
7975 *
7976 * For the case where L1 and L2 share the same APIC access page
7977 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7978 * in the vmcs12), this function will only update either the vmcs01
7979 * or the vmcs02. If the former, the vmcs02 will be updated by
7980 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7981 * the next L2->L1 exit.
7982 */
7983 if (!is_guest_mode(vcpu) ||
7984 !nested_cpu_has2(vmx->nested.current_vmcs12,
7985 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7986 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7987}
7988
c7c9c56c
YZ		 7989static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7990{
7991 u16 status;
7992 u8 old;
7993
c7c9c56c
YZ		 7994 if (isr == -1)
7995 isr = 0;
7996
7997 status = vmcs_read16(GUEST_INTR_STATUS);
7998 old = status >> 8;
7999 if (isr != old) {
8000 status &= 0xff;
8001 status |= isr << 8;
8002 vmcs_write16(GUEST_INTR_STATUS, status);
8003 }
8004}
8005
8006static void vmx_set_rvi(int vector)
8007{
8008 u16 status;
8009 u8 old;
8010
4114c27d
WW		 8011 if (vector == -1)
8012 vector = 0;
8013
c7c9c56c
YZ		 8014 status = vmcs_read16(GUEST_INTR_STATUS);
8015 old = (u8)status & 0xff;
8016 if ((u8)vector != old) {
8017 status &= ~0xff;
8018 status |= (u8)vector;
8019 vmcs_write16(GUEST_INTR_STATUS, status);
8020 }
8021}
8022
8023static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8024{
4114c27d
WW		 8025 if (!is_guest_mode(vcpu)) {
8026 vmx_set_rvi(max_irr);
8027 return;
8028 }
8029
c7c9c56c
YZ		 8030 if (max_irr == -1)
8031 return;
8032
963fee16 8033 /*
4114c27d
WW		 8034 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8035 * handles it.
963fee16 8036 */
4114c27d 8037 if (nested_exit_on_intr(vcpu))
963fee16
WL		 8038 return;
8039
963fee16 8040 /*
4114c27d 8041 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 8042 * is run without virtual interrupt delivery.
8043 */
8044 if (!kvm_event_needs_reinjection(vcpu) &&
8045 vmx_interrupt_allowed(vcpu)) {
8046 kvm_queue_interrupt(vcpu, max_irr, false);
8047 vmx_inject_irq(vcpu);
8048 }
c7c9c56c
YZ		 8049}
8050
3bb345f3 8051static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
c7c9c56c 8052{
3bb345f3 8053 u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
35754c98 8054 if (!vmx_cpu_uses_apicv(vcpu))
3d81bc7e
YZ		 8055 return;
8056
c7c9c56c
YZ		 8057 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8058 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8059 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8060 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8061}
8062
51aa01d1 8063static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8064{
00eba012
AK		 8065 u32 exit_intr_info;
8066
8067 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8068 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8069 return;
8070
c5ca8e57 8071 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 8072 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 8073
8074 /* Handle machine checks before interrupts are enabled */
00eba012 8075 if (is_machine_check(exit_intr_info))
a0861c02
AK		 8076 kvm_machine_check();
8077
20f65983 8078 /* We need to handle NMIs before interrupts are enabled */
00eba012 8079 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 8080 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8081 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8082 asm("int $2");
ff9d07a0
ZY		 8083 kvm_after_handle_nmi(&vmx->vcpu);
8084 }
51aa01d1 8085}
20f65983 8086
a547c6db
YZ		 8087static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8088{
8089 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8090
8091 /*
8092 * If external interrupt exists, IF bit is set in rflags/eflags on the
8093 * interrupt stack frame, and interrupt will be enabled on a return
8094 * from interrupt handler.
8095 */
8096 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8097 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8098 unsigned int vector;
8099 unsigned long entry;
8100 gate_desc *desc;
8101 struct vcpu_vmx *vmx = to_vmx(vcpu);
8102#ifdef CONFIG_X86_64
8103 unsigned long tmp;
8104#endif
8105
8106 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8107 desc = (gate_desc *)vmx->host_idt_base + vector;
8108 entry = gate_offset(*desc);
8109 asm volatile(
8110#ifdef CONFIG_X86_64
8111 "mov %%" _ASM_SP ", %[sp]\n\t"
8112 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8113 "push $%c[ss]\n\t"
8114 "push %[sp]\n\t"
8115#endif
8116 "pushf\n\t"
8117 "orl $0x200, (%%" _ASM_SP ")\n\t"
8118 __ASM_SIZE(push) " $%c[cs]\n\t"
8119 "call *%[entry]\n\t"
8120 :
8121#ifdef CONFIG_X86_64
8122 [sp]"=&r"(tmp)
8123#endif
8124 :
8125 [entry]"r"(entry),
8126 [ss]"i"(__KERNEL_DS),
8127 [cs]"i"(__KERNEL_CS)
8128 );
8129 } else
8130 local_irq_enable();
8131}
8132
6d396b55
PB		 8133static bool vmx_has_high_real_mode_segbase(void)
8134{
8135 return enable_unrestricted_guest || emulate_invalid_guest_state;
8136}
8137
da8999d3
LJ		 8138static bool vmx_mpx_supported(void)
8139{
8140 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8141 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8142}
8143
55412b2e
WL		 8144static bool vmx_xsaves_supported(void)
8145{
8146 return vmcs_config.cpu_based_2nd_exec_ctrl &
8147 SECONDARY_EXEC_XSAVES;
8148}
8149
51aa01d1
AK		 8150static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8151{
c5ca8e57 8152 u32 exit_intr_info;
51aa01d1
AK		 8153 bool unblock_nmi;
8154 u8 vector;
8155 bool idtv_info_valid;
8156
8157 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8158
cf393f75 8159 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 8160 if (vmx->nmi_known_unmasked)
8161 return;
c5ca8e57
AK		 8162 /*
8163 * Can't use vmx->exit_intr_info since we're not sure what
8164 * the exit reason is.
8165 */
8166 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 8167 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8168 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8169 /*
7b4a25cb 8170 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 8171 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8172 * a guest IRET fault.
7b4a25cb
GN		 8173 * SDM 3: 23.2.2 (September 2008)
8174 * Bit 12 is undefined in any of the following cases:
8175 * If the VM exit sets the valid bit in the IDT-vectoring
8176 * information field.
8177 * If the VM exit is due to a double fault.
cf393f75 8178 */
7b4a25cb
GN		 8179 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8180 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 8181 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8182 GUEST_INTR_STATE_NMI);
9d58b931
AK		 8183 else
8184 vmx->nmi_known_unmasked =
8185 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8186 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 8187 } else if (unlikely(vmx->soft_vnmi_blocked))
8188 vmx->vnmi_blocked_time +=
8189 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 8190}
8191
3ab66e8a 8192static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 8193 u32 idt_vectoring_info,
8194 int instr_len_field,
8195 int error_code_field)
51aa01d1 8196{
51aa01d1
AK		 8197 u8 vector;
8198 int type;
8199 bool idtv_info_valid;
8200
8201 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8202
3ab66e8a
JK		 8203 vcpu->arch.nmi_injected = false;
8204 kvm_clear_exception_queue(vcpu);
8205 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 8206
8207 if (!idtv_info_valid)
8208 return;
8209
3ab66e8a 8210 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8211
668f612f
AK		 8212 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8213 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8214
64a7ec06 8215 switch (type) {
37b96e98 8216 case INTR_TYPE_NMI_INTR:
3ab66e8a 8217 vcpu->arch.nmi_injected = true;
668f612f 8218 /*
7b4a25cb 8219 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 8220 * Clear bit "block by NMI" before VM entry if a NMI
8221 * delivery faulted.
668f612f 8222 */
3ab66e8a 8223 vmx_set_nmi_mask(vcpu, false);
37b96e98 8224 break;
37b96e98 8225 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8226 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 8227 /* fall through */
8228 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8229 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8230 u32 err = vmcs_read32(error_code_field);
851eb667 8231 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8232 } else
851eb667 8233 kvm_requeue_exception(vcpu, vector);
37b96e98 8234 break;
66fd3f7f 8235 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8236 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8237 /* fall through */
37b96e98 8238 case INTR_TYPE_EXT_INTR:
3ab66e8a 8239 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 8240 break;
8241 default:
8242 break;
f7d9238f 8243 }
cf393f75
AK		 8244}
8245
83422e17
AK		 8246static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8247{
3ab66e8a 8248 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8249 VM_EXIT_INSTRUCTION_LEN,
8250 IDT_VECTORING_ERROR_CODE);
8251}
8252
b463a6f7
AK		 8253static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8254{
3ab66e8a 8255 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8256 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8257 VM_ENTRY_INSTRUCTION_LEN,
8258 VM_ENTRY_EXCEPTION_ERROR_CODE);
8259
8260 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8261}
8262
d7cd9796
GN		 8263static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8264{
8265 int i, nr_msrs;
8266 struct perf_guest_switch_msr *msrs;
8267
8268 msrs = perf_guest_get_msrs(&nr_msrs);
8269
8270 if (!msrs)
8271 return;
8272
8273 for (i = 0; i < nr_msrs; i++)
8274 if (msrs[i].host == msrs[i].guest)
8275 clear_atomic_switch_msr(vmx, msrs[i].msr);
8276 else
8277 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8278 msrs[i].host);
8279}
8280
a3b5ba49 8281static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8282{
a2fa3e9f 8283 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8284 unsigned long debugctlmsr, cr4;
104f226b
AK		 8285
8286 /* Record the guest's net vcpu time for enforced NMI injections. */
8287 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8288 vmx->entry_time = ktime_get();
8289
8290 /* Don't enter VMX if guest state is invalid, let the exit handler
8291 start emulation until we arrive back to a valid state */
14168786 8292 if (vmx->emulation_required)
104f226b
AK		 8293 return;
8294
a7653ecd
RK		 8295 if (vmx->ple_window_dirty) {
8296 vmx->ple_window_dirty = false;
8297 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8298 }
8299
012f83cb
AG		 8300 if (vmx->nested.sync_shadow_vmcs) {
8301 copy_vmcs12_to_shadow(vmx);
8302 vmx->nested.sync_shadow_vmcs = false;
8303 }
8304
104f226b
AK		 8305 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8306 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8307 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8308 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8309
1e02ce4c 8310 cr4 = cr4_read_shadow();
d974baa3
AL		 8311 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8312 vmcs_writel(HOST_CR4, cr4);
8313 vmx->host_state.vmcs_host_cr4 = cr4;
8314 }
8315
104f226b
AK		 8316 /* When single-stepping over STI and MOV SS, we must clear the
8317 * corresponding interruptibility bits in the guest state. Otherwise
8318 * vmentry fails as it then expects bit 14 (BS) in pending debug
8319 * exceptions being set, but that's not correct for the guest debugging
8320 * case. */
8321 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8322 vmx_set_interrupt_shadow(vcpu, 0);
8323
d7cd9796 8324 atomic_switch_perf_msrs(vmx);
2a7921b7 8325 debugctlmsr = get_debugctlmsr();
d7cd9796 8326
d462b819 8327 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8328 asm(
6aa8b732 8329 /* Store host registers */
b188c81f
AK		 8330 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8331 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8332 "push %%" _ASM_CX " \n\t"
8333 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8334 "je 1f \n\t"
b188c81f 8335 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8336 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8337 "1: \n\t"
d3edefc0 8338 /* Reload cr2 if changed */
b188c81f
AK		 8339 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8340 "mov %%cr2, %%" _ASM_DX " \n\t"
8341 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8342 "je 2f \n\t"
b188c81f 8343 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8344 "2: \n\t"
6aa8b732 8345 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8346 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8347 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8348 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8349 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8350 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8351 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8352 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8353 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8354#ifdef CONFIG_X86_64
e08aa78a
AK		 8355 "mov %c[r8](%0), %%r8 \n\t"
8356 "mov %c[r9](%0), %%r9 \n\t"
8357 "mov %c[r10](%0), %%r10 \n\t"
8358 "mov %c[r11](%0), %%r11 \n\t"
8359 "mov %c[r12](%0), %%r12 \n\t"
8360 "mov %c[r13](%0), %%r13 \n\t"
8361 "mov %c[r14](%0), %%r14 \n\t"
8362 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8363#endif
b188c81f 8364 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8365
6aa8b732 8366 /* Enter guest mode */
83287ea4 8367 "jne 1f \n\t"
4ecac3fd 8368 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8369 "jmp 2f \n\t"
8370 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8371 "2: "
6aa8b732 8372 /* Save guest registers, load host registers, keep flags */
b188c81f 8373 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8374 "pop %0 \n\t"
b188c81f
AK		 8375 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8376 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8377 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8378 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8379 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8380 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8381 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8382#ifdef CONFIG_X86_64
e08aa78a
AK		 8383 "mov %%r8, %c[r8](%0) \n\t"
8384 "mov %%r9, %c[r9](%0) \n\t"
8385 "mov %%r10, %c[r10](%0) \n\t"
8386 "mov %%r11, %c[r11](%0) \n\t"
8387 "mov %%r12, %c[r12](%0) \n\t"
8388 "mov %%r13, %c[r13](%0) \n\t"
8389 "mov %%r14, %c[r14](%0) \n\t"
8390 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8391#endif
b188c81f
AK		 8392 "mov %%cr2, %%" _ASM_AX " \n\t"
8393 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8394
b188c81f 8395 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8396 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8397 ".pushsection .rodata \n\t"
8398 ".global vmx_return \n\t"
8399 "vmx_return: " _ASM_PTR " 2b \n\t"
8400 ".popsection"
e08aa78a 8401 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8402 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8403 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8404 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8405 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8406 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8407 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8408 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8409 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8410 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8411 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8412#ifdef CONFIG_X86_64
ad312c7c
ZX		 8413 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8414 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8415 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8416 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8417 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8418 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8419 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8420 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8421#endif
40712fae
AK		 8422 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8423 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8424 : "cc", "memory"
8425#ifdef CONFIG_X86_64
b188c81f 8426 , "rax", "rbx", "rdi", "rsi"
c2036300 8427 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8428#else
8429 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8430#endif
8431 );
6aa8b732 8432
2a7921b7
GN		 8433 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8434 if (debugctlmsr)
8435 update_debugctlmsr(debugctlmsr);
8436
aa67f609
AK		 8437#ifndef CONFIG_X86_64
8438 /*
8439 * The sysexit path does not restore ds/es, so we must set them to
8440 * a reasonable value ourselves.
8441 *
8442 * We can't defer this to vmx_load_host_state() since that function
8443 * may be executed in interrupt context, which saves and restore segments
8444 * around it, nullifying its effect.
8445 */
8446 loadsegment(ds, __USER_DS);
8447 loadsegment(es, __USER_DS);
8448#endif
8449
6de4f3ad 8450 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8451 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8452 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8453 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8454 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8455 vcpu->arch.regs_dirty = 0;
8456
1155f76a
AK		 8457 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8458
d462b819 8459 vmx->loaded_vmcs->launched = 1;
1b6269db 8460
51aa01d1 8461 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8462 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8463
e0b890d3
GN		 8464 /*
8465 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8466 * we did not inject a still-pending event to L1 now because of
8467 * nested_run_pending, we need to re-enable this bit.
8468 */
8469 if (vmx->nested.nested_run_pending)
8470 kvm_make_request(KVM_REQ_EVENT, vcpu);
8471
8472 vmx->nested.nested_run_pending = 0;
8473
51aa01d1
AK		 8474 vmx_complete_atomic_exit(vmx);
8475 vmx_recover_nmi_blocking(vmx);
cf393f75 8476 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8477}
8478
4fa7734c
PB		 8479static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8480{
8481 struct vcpu_vmx *vmx = to_vmx(vcpu);
8482 int cpu;
8483
8484 if (vmx->loaded_vmcs == &vmx->vmcs01)
8485 return;
8486
8487 cpu = get_cpu();
8488 vmx->loaded_vmcs = &vmx->vmcs01;
8489 vmx_vcpu_put(vcpu);
8490 vmx_vcpu_load(vcpu, cpu);
8491 vcpu->cpu = cpu;
8492 put_cpu();
8493}
8494
6aa8b732
AK		 8495static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8496{
fb3f0f51
RR		 8497 struct vcpu_vmx *vmx = to_vmx(vcpu);
8498
843e4330
KH		 8499 if (enable_pml)
8500 vmx_disable_pml(vmx);
cdbecfc3 8501 free_vpid(vmx);
4fa7734c
PB		 8502 leave_guest_mode(vcpu);
8503 vmx_load_vmcs01(vcpu);
26a865f4 8504 free_nested(vmx);
4fa7734c 8505 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8506 kfree(vmx->guest_msrs);
8507 kvm_vcpu_uninit(vcpu);
a4770347 8508 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8509}
8510
fb3f0f51 8511static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8512{
fb3f0f51 8513 int err;
c16f862d 8514 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8515 int cpu;
6aa8b732 8516
a2fa3e9f 8517 if (!vmx)
fb3f0f51
RR		 8518 return ERR_PTR(-ENOMEM);
8519
2384d2b3
SY		 8520 allocate_vpid(vmx);
8521
fb3f0f51
RR		 8522 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8523 if (err)
8524 goto free_vcpu;
965b58a5 8525
a2fa3e9f 8526 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8527 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8528 > PAGE_SIZE);
0123be42 8529
be6d05cf 8530 err = -ENOMEM;
fb3f0f51 8531 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8532 goto uninit_vcpu;
8533 }
965b58a5 8534
d462b819
NHE		 8535 vmx->loaded_vmcs = &vmx->vmcs01;
8536 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8537 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8538 goto free_msrs;
d462b819
NHE		 8539 if (!vmm_exclusive)
8540 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8541 loaded_vmcs_init(vmx->loaded_vmcs);
8542 if (!vmm_exclusive)
8543 kvm_cpu_vmxoff();
a2fa3e9f 8544
15ad7146
AK		 8545 cpu = get_cpu();
8546 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8547 vmx->vcpu.cpu = cpu;
8b9cf98c 8548 err = vmx_vcpu_setup(vmx);
fb3f0f51 8549 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8550 put_cpu();
fb3f0f51
RR		 8551 if (err)
8552 goto free_vmcs;
35754c98 8553 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK		 8554 err = alloc_apic_access_page(kvm);
8555 if (err)
5e4a0b3c 8556 goto free_vmcs;
a63cb560 8557 }
fb3f0f51 8558
b927a3ce
SY		 8559 if (enable_ept) {
8560 if (!kvm->arch.ept_identity_map_addr)
8561 kvm->arch.ept_identity_map_addr =
8562 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8563 err = init_rmode_identity_map(kvm);
8564 if (err)
93ea5388 8565 goto free_vmcs;
b927a3ce 8566 }
b7ebfb05 8567
b9c237bb
WV		 8568 if (nested)
8569 nested_vmx_setup_ctls_msrs(vmx);
8570
705699a1 8571 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE		 8572 vmx->nested.current_vmptr = -1ull;
8573 vmx->nested.current_vmcs12 = NULL;
8574
843e4330
KH		 8575 /*
8576 * If PML is turned on, failure on enabling PML just results in failure
8577 * of creating the vcpu, therefore we can simplify PML logic (by
8578 * avoiding dealing with cases, such as enabling PML partially on vcpus
8579 * for the guest, etc.
8580 */
8581 if (enable_pml) {
8582 err = vmx_enable_pml(vmx);
8583 if (err)
8584 goto free_vmcs;
8585 }
8586
fb3f0f51
RR		 8587 return &vmx->vcpu;
8588
8589free_vmcs:
5f3fbc34 8590 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8591free_msrs:
fb3f0f51
RR		 8592 kfree(vmx->guest_msrs);
8593uninit_vcpu:
8594 kvm_vcpu_uninit(&vmx->vcpu);
8595free_vcpu:
cdbecfc3 8596 free_vpid(vmx);
a4770347 8597 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8598 return ERR_PTR(err);
6aa8b732
AK		 8599}
8600
002c7f7c
YS		 8601static void __init vmx_check_processor_compat(void *rtn)
8602{
8603 struct vmcs_config vmcs_conf;
8604
8605 *(int *)rtn = 0;
8606 if (setup_vmcs_config(&vmcs_conf) < 0)
8607 *(int *)rtn = -EIO;
8608 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8609 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8610 smp_processor_id());
8611 *(int *)rtn = -EIO;
8612 }
8613}
8614
67253af5
SY		 8615static int get_ept_level(void)
8616{
8617 return VMX_EPT_DEFAULT_GAW + 1;
8618}
8619
4b12f0de 8620static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8621{
b18d5431
XG		 8622 u8 cache;
8623 u64 ipat = 0;
4b12f0de 8624
522c68c4 8625 /* For VT-d and EPT combination
606decd6 8626 * 1. MMIO: always map as UC
522c68c4
SY		 8627 * 2. EPT with VT-d:
8628 * a. VT-d without snooping control feature: can't guarantee the
606decd6 8629 * result, try to trust guest.
522c68c4
SY		 8630 * b. VT-d with snooping control feature: snooping control feature of
8631 * VT-d engine can guarantee the cache correctness. Just set it
8632 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8633 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8634 * consistent with host MTRR
8635 */
606decd6
PB		 8636 if (is_mmio) {
8637 cache = MTRR_TYPE_UNCACHABLE;
8638 goto exit;
8639 }
8640
8641 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG		 8642 ipat = VMX_EPT_IPAT_BIT;
8643 cache = MTRR_TYPE_WRBACK;
8644 goto exit;
8645 }
8646
8647 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8648 ipat = VMX_EPT_IPAT_BIT;
0da029ed 8649 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG		 8650 cache = MTRR_TYPE_WRBACK;
8651 else
8652 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG		 8653 goto exit;
8654 }
8655
ff53604b 8656 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG		 8657
8658exit:
8659 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY		 8660}
8661
17cc3935 8662static int vmx_get_lpage_level(void)
344f414f 8663{
878403b7
SY		 8664 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8665 return PT_DIRECTORY_LEVEL;
8666 else
8667 /* For shadow and EPT supported 1GB page */
8668 return PT_PDPE_LEVEL;
344f414f
JR		 8669}
8670
0e851880
SY		 8671static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8672{
4e47c7a6
SY		 8673 struct kvm_cpuid_entry2 *best;
8674 struct vcpu_vmx *vmx = to_vmx(vcpu);
8675 u32 exec_control;
8676
8677 vmx->rdtscp_enabled = false;
8678 if (vmx_rdtscp_supported()) {
8679 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8680 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8681 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8682 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8683 vmx->rdtscp_enabled = true;
8684 else {
8685 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8686 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8687 exec_control);
8688 }
8689 }
b3a2a907
JK		 8690 if (nested && !vmx->rdtscp_enabled)
8691 vmx->nested.nested_vmx_secondary_ctls_high &=
8692 ~SECONDARY_EXEC_RDTSCP;
4e47c7a6 8693 }
ad756a16 8694
ad756a16
MJ		 8695 /* Exposing INVPCID only when PCID is exposed */
8696 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8697 if (vmx_invpcid_supported() &&
4f977045 8698 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8699 guest_cpuid_has_pcid(vcpu)) {
29282fde 8700 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8701 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8702 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8703 exec_control);
8704 } else {
29282fde
TI		 8705 if (cpu_has_secondary_exec_ctrls()) {
8706 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8707 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8708 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8709 exec_control);
8710 }
ad756a16 8711 if (best)
4f977045 8712 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8713 }
8b3e34e4
XG		 8714
8715 if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8716 if (guest_cpuid_has_pcommit(vcpu))
8717 vmx->nested.nested_vmx_secondary_ctls_high |=
8718 SECONDARY_EXEC_PCOMMIT;
8719 else
8720 vmx->nested.nested_vmx_secondary_ctls_high &=
8721 ~SECONDARY_EXEC_PCOMMIT;
8722 }
0e851880
SY		 8723}
8724
d4330ef2
JR		 8725static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8726{
7b8050f5
NHE		 8727 if (func == 1 && nested)
8728 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8729}
8730
25d92081
YZ		 8731static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8732 struct x86_exception *fault)
8733{
533558bc
JK		 8734 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8735 u32 exit_reason;
25d92081
YZ		 8736
8737 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8738 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8739 else
533558bc
JK		 8740 exit_reason = EXIT_REASON_EPT_VIOLATION;
8741 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8742 vmcs12->guest_physical_address = fault->address;
8743}
8744
155a97a3
NHE		 8745/* Callbacks for nested_ept_init_mmu_context: */
8746
8747static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8748{
8749 /* return the page table to be shadowed - in our case, EPT12 */
8750 return get_vmcs12(vcpu)->ept_pointer;
8751}
8752
8a3c1a33 8753static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8754{
ad896af0
PB		 8755 WARN_ON(mmu_is_nested(vcpu));
8756 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8757 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8758 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8759 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8760 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8761 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8762
8763 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8764}
8765
8766static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8767{
8768 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8769}
8770
19d5f10b
EK		 8771static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8772 u16 error_code)
8773{
8774 bool inequality, bit;
8775
8776 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8777 inequality =
8778 (error_code & vmcs12->page_fault_error_code_mask) !=
8779 vmcs12->page_fault_error_code_match;
8780 return inequality ^ bit;
8781}
8782
feaf0c7d
GN		 8783static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8784 struct x86_exception *fault)
8785{
8786 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8787
8788 WARN_ON(!is_guest_mode(vcpu));
8789
19d5f10b 8790 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8791 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8792 vmcs_read32(VM_EXIT_INTR_INFO),
8793 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8794 else
8795 kvm_inject_page_fault(vcpu, fault);
8796}
8797
a2bcba50
WL		 8798static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8799 struct vmcs12 *vmcs12)
8800{
8801 struct vcpu_vmx *vmx = to_vmx(vcpu);
9090422f 8802 int maxphyaddr = cpuid_maxphyaddr(vcpu);
a2bcba50
WL		 8803
8804 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9090422f
EK		 8805 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8806 vmcs12->apic_access_addr >> maxphyaddr)
a2bcba50
WL		 8807 return false;
8808
8809 /*
8810 * Translate L1 physical address to host physical
8811 * address for vmcs02. Keep the page pinned, so this
8812 * physical address remains valid. We keep a reference
8813 * to it so we can release it later.
8814 */
8815 if (vmx->nested.apic_access_page) /* shouldn't happen */
8816 nested_release_page(vmx->nested.apic_access_page);
8817 vmx->nested.apic_access_page =
8818 nested_get_page(vcpu, vmcs12->apic_access_addr);
8819 }
a7c0b07d
WL		 8820
8821 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9090422f
EK		 8822 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8823 vmcs12->virtual_apic_page_addr >> maxphyaddr)
a7c0b07d
WL		 8824 return false;
8825
8826 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8827 nested_release_page(vmx->nested.virtual_apic_page);
8828 vmx->nested.virtual_apic_page =
8829 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8830
8831 /*
8832 * Failing the vm entry is _not_ what the processor does
8833 * but it's basically the only possibility we have.
8834 * We could still enter the guest if CR8 load exits are
8835 * enabled, CR8 store exits are enabled, and virtualize APIC
8836 * access is disabled; in this case the processor would never
8837 * use the TPR shadow and we could simply clear the bit from
8838 * the execution control. But such a configuration is useless,
8839 * so let's keep the code simple.
8840 */
8841 if (!vmx->nested.virtual_apic_page)
8842 return false;
8843 }
8844
705699a1 8845 if (nested_cpu_has_posted_intr(vmcs12)) {
9090422f
EK		 8846 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8847 vmcs12->posted_intr_desc_addr >> maxphyaddr)
705699a1
WV		 8848 return false;
8849
8850 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8851 kunmap(vmx->nested.pi_desc_page);
8852 nested_release_page(vmx->nested.pi_desc_page);
8853 }
8854 vmx->nested.pi_desc_page =
8855 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8856 if (!vmx->nested.pi_desc_page)
8857 return false;
8858
8859 vmx->nested.pi_desc =
8860 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8861 if (!vmx->nested.pi_desc) {
8862 nested_release_page_clean(vmx->nested.pi_desc_page);
8863 return false;
8864 }
8865 vmx->nested.pi_desc =
8866 (struct pi_desc *)((void *)vmx->nested.pi_desc +
8867 (unsigned long)(vmcs12->posted_intr_desc_addr &
8868 (PAGE_SIZE - 1)));
8869 }
8870
a2bcba50
WL		 8871 return true;
8872}
8873
f4124500
JK		 8874static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8875{
8876 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8877 struct vcpu_vmx *vmx = to_vmx(vcpu);
8878
8879 if (vcpu->arch.virtual_tsc_khz == 0)
8880 return;
8881
8882 /* Make sure short timeouts reliably trigger an immediate vmexit.
8883 * hrtimer_start does not guarantee this. */
8884 if (preemption_timeout <= 1) {
8885 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8886 return;
8887 }
8888
8889 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8890 preemption_timeout *= 1000000;
8891 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8892 hrtimer_start(&vmx->nested.preemption_timer,
8893 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8894}
8895
3af18d9c
WV		 8896static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8897 struct vmcs12 *vmcs12)
8898{
8899 int maxphyaddr;
8900 u64 addr;
8901
8902 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8903 return 0;
8904
8905 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8906 WARN_ON(1);
8907 return -EINVAL;
8908 }
8909 maxphyaddr = cpuid_maxphyaddr(vcpu);
8910
8911 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8912 ((addr + PAGE_SIZE) >> maxphyaddr))
8913 return -EINVAL;
8914
8915 return 0;
8916}
8917
8918/*
8919 * Merge L0's and L1's MSR bitmap, return false to indicate that
8920 * we do not use the hardware.
8921 */
8922static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8923 struct vmcs12 *vmcs12)
8924{
82f0dd4b 8925 int msr;
f2b93280
WV		 8926 struct page *page;
8927 unsigned long *msr_bitmap;
8928
8929 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8930 return false;
8931
8932 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8933 if (!page) {
8934 WARN_ON(1);
8935 return false;
8936 }
8937 msr_bitmap = (unsigned long *)kmap(page);
8938 if (!msr_bitmap) {
8939 nested_release_page_clean(page);
8940 WARN_ON(1);
8941 return false;
8942 }
8943
8944 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 8945 if (nested_cpu_has_apic_reg_virt(vmcs12))
8946 for (msr = 0x800; msr <= 0x8ff; msr++)
8947 nested_vmx_disable_intercept_for_msr(
8948 msr_bitmap,
8949 vmx_msr_bitmap_nested,
8950 msr, MSR_TYPE_R);
f2b93280
WV		 8951 /* TPR is allowed */
8952 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8953 vmx_msr_bitmap_nested,
8954 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8955 MSR_TYPE_R | MSR_TYPE_W);
608406e2
WV		 8956 if (nested_cpu_has_vid(vmcs12)) {
8957 /* EOI and self-IPI are allowed */
8958 nested_vmx_disable_intercept_for_msr(
8959 msr_bitmap,
8960 vmx_msr_bitmap_nested,
8961 APIC_BASE_MSR + (APIC_EOI >> 4),
8962 MSR_TYPE_W);
8963 nested_vmx_disable_intercept_for_msr(
8964 msr_bitmap,
8965 vmx_msr_bitmap_nested,
8966 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8967 MSR_TYPE_W);
8968 }
82f0dd4b
WV		 8969 } else {
8970 /*
8971 * Enable reading intercept of all the x2apic
8972 * MSRs. We should not rely on vmcs12 to do any
8973 * optimizations here, it may have been modified
8974 * by L1.
8975 */
8976 for (msr = 0x800; msr <= 0x8ff; msr++)
8977 __vmx_enable_intercept_for_msr(
8978 vmx_msr_bitmap_nested,
8979 msr,
8980 MSR_TYPE_R);
8981
f2b93280
WV		 8982 __vmx_enable_intercept_for_msr(
8983 vmx_msr_bitmap_nested,
8984 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
82f0dd4b 8985 MSR_TYPE_W);
608406e2
WV		 8986 __vmx_enable_intercept_for_msr(
8987 vmx_msr_bitmap_nested,
8988 APIC_BASE_MSR + (APIC_EOI >> 4),
8989 MSR_TYPE_W);
8990 __vmx_enable_intercept_for_msr(
8991 vmx_msr_bitmap_nested,
8992 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8993 MSR_TYPE_W);
82f0dd4b 8994 }
f2b93280
WV		 8995 kunmap(page);
8996 nested_release_page_clean(page);
8997
8998 return true;
8999}
9000
9001static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9002 struct vmcs12 *vmcs12)
9003{
82f0dd4b 9004 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 9005 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV		 9006 !nested_cpu_has_vid(vmcs12) &&
9007 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV		 9008 return 0;
9009
9010 /*
9011 * If virtualize x2apic mode is enabled,
9012 * virtualize apic access must be disabled.
9013 */
82f0dd4b
WV		 9014 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9015 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 9016 return -EINVAL;
9017
608406e2
WV		 9018 /*
9019 * If virtual interrupt delivery is enabled,
9020 * we must exit on external interrupts.
9021 */
9022 if (nested_cpu_has_vid(vmcs12) &&
9023 !nested_exit_on_intr(vcpu))
9024 return -EINVAL;
9025
705699a1
WV		 9026 /*
9027 * bits 15:8 should be zero in posted_intr_nv,
9028 * the descriptor address has been already checked
9029 * in nested_get_vmcs12_pages.
9030 */
9031 if (nested_cpu_has_posted_intr(vmcs12) &&
9032 (!nested_cpu_has_vid(vmcs12) ||
9033 !nested_exit_intr_ack_set(vcpu) ||
9034 vmcs12->posted_intr_nv & 0xff00))
9035 return -EINVAL;
9036
f2b93280
WV		 9037 /* tpr shadow is needed by all apicv features. */
9038 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9039 return -EINVAL;
9040
9041 return 0;
3af18d9c
WV		 9042}
9043
e9ac033e
EK		 9044static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9045 unsigned long count_field,
92d71bc6 9046 unsigned long addr_field)
ff651cb6 9047{
92d71bc6 9048 int maxphyaddr;
e9ac033e
EK		 9049 u64 count, addr;
9050
9051 if (vmcs12_read_any(vcpu, count_field, &count) ||
9052 vmcs12_read_any(vcpu, addr_field, &addr)) {
9053 WARN_ON(1);
9054 return -EINVAL;
9055 }
9056 if (count == 0)
9057 return 0;
92d71bc6 9058 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK		 9059 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9060 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9061 pr_warn_ratelimited(
9062 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9063 addr_field, maxphyaddr, count, addr);
9064 return -EINVAL;
9065 }
9066 return 0;
9067}
9068
9069static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9070 struct vmcs12 *vmcs12)
9071{
e9ac033e
EK		 9072 if (vmcs12->vm_exit_msr_load_count == 0 &&
9073 vmcs12->vm_exit_msr_store_count == 0 &&
9074 vmcs12->vm_entry_msr_load_count == 0)
9075 return 0; /* Fast path */
e9ac033e 9076 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9077 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9078 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9079 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9080 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9081 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK		 9082 return -EINVAL;
9083 return 0;
9084}
9085
9086static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9087 struct vmx_msr_entry *e)
9088{
9089 /* x2APIC MSR accesses are not allowed */
8a9781f7 9090 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK		 9091 return -EINVAL;
9092 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9093 e->index == MSR_IA32_UCODE_REV)
9094 return -EINVAL;
9095 if (e->reserved != 0)
ff651cb6
WV		 9096 return -EINVAL;
9097 return 0;
9098}
9099
e9ac033e
EK		 9100static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9101 struct vmx_msr_entry *e)
ff651cb6
WV		 9102{
9103 if (e->index == MSR_FS_BASE ||
9104 e->index == MSR_GS_BASE ||
e9ac033e
EK		 9105 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9106 nested_vmx_msr_check_common(vcpu, e))
9107 return -EINVAL;
9108 return 0;
9109}
9110
9111static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9112 struct vmx_msr_entry *e)
9113{
9114 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9115 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 9116 return -EINVAL;
9117 return 0;
9118}
9119
9120/*
9121 * Load guest's/host's msr at nested entry/exit.
9122 * return 0 for success, entry index for failure.
9123 */
9124static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9125{
9126 u32 i;
9127 struct vmx_msr_entry e;
9128 struct msr_data msr;
9129
9130 msr.host_initiated = false;
9131 for (i = 0; i < count; i++) {
54bf36aa
PB		 9132 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9133 &e, sizeof(e))) {
e9ac033e
EK		 9134 pr_warn_ratelimited(
9135 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9136 __func__, i, gpa + i * sizeof(e));
ff651cb6 9137 goto fail;
e9ac033e
EK		 9138 }
9139 if (nested_vmx_load_msr_check(vcpu, &e)) {
9140 pr_warn_ratelimited(
9141 "%s check failed (%u, 0x%x, 0x%x)\n",
9142 __func__, i, e.index, e.reserved);
9143 goto fail;
9144 }
ff651cb6
WV		 9145 msr.index = e.index;
9146 msr.data = e.value;
e9ac033e
EK		 9147 if (kvm_set_msr(vcpu, &msr)) {
9148 pr_warn_ratelimited(
9149 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9150 __func__, i, e.index, e.value);
ff651cb6 9151 goto fail;
e9ac033e 9152 }
ff651cb6
WV		 9153 }
9154 return 0;
9155fail:
9156 return i + 1;
9157}
9158
9159static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9160{
9161 u32 i;
9162 struct vmx_msr_entry e;
9163
9164 for (i = 0; i < count; i++) {
609e36d3 9165 struct msr_data msr_info;
54bf36aa
PB		 9166 if (kvm_vcpu_read_guest(vcpu,
9167 gpa + i * sizeof(e),
9168 &e, 2 * sizeof(u32))) {
e9ac033e
EK		 9169 pr_warn_ratelimited(
9170 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9171 __func__, i, gpa + i * sizeof(e));
ff651cb6 9172 return -EINVAL;
e9ac033e
EK		 9173 }
9174 if (nested_vmx_store_msr_check(vcpu, &e)) {
9175 pr_warn_ratelimited(
9176 "%s check failed (%u, 0x%x, 0x%x)\n",
9177 __func__, i, e.index, e.reserved);
ff651cb6 9178 return -EINVAL;
e9ac033e 9179 }
609e36d3
PB		 9180 msr_info.host_initiated = false;
9181 msr_info.index = e.index;
9182 if (kvm_get_msr(vcpu, &msr_info)) {
e9ac033e
EK		 9183 pr_warn_ratelimited(
9184 "%s cannot read MSR (%u, 0x%x)\n",
9185 __func__, i, e.index);
9186 return -EINVAL;
9187 }
54bf36aa
PB		 9188 if (kvm_vcpu_write_guest(vcpu,
9189 gpa + i * sizeof(e) +
9190 offsetof(struct vmx_msr_entry, value),
9191 &msr_info.data, sizeof(msr_info.data))) {
e9ac033e
EK		 9192 pr_warn_ratelimited(
9193 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9194 __func__, i, e.index, msr_info.data);
e9ac033e
EK		 9195 return -EINVAL;
9196 }
ff651cb6
WV		 9197 }
9198 return 0;
9199}
9200
fe3ef05c
NHE		 9201/*
9202 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9203 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9204 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 9205 * guest in a way that will both be appropriate to L1's requests, and our
9206 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9207 * function also has additional necessary side-effects, like setting various
9208 * vcpu->arch fields.
9209 */
9210static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9211{
9212 struct vcpu_vmx *vmx = to_vmx(vcpu);
9213 u32 exec_control;
9214
9215 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9216 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9217 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9218 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9219 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9220 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9221 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9222 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9223 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9224 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9225 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9226 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9227 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9228 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9229 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9230 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9231 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9232 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9233 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9234 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9235 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9236 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9237 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9238 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9239 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9240 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9241 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9242 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9243 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9244 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9245 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9246 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9247 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9248 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9249 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9250 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9251
2996fca0
JK		 9252 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9253 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9254 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9255 } else {
9256 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9257 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9258 }
fe3ef05c
NHE		 9259 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9260 vmcs12->vm_entry_intr_info_field);
9261 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9262 vmcs12->vm_entry_exception_error_code);
9263 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9264 vmcs12->vm_entry_instruction_len);
9265 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9266 vmcs12->guest_interruptibility_info);
fe3ef05c 9267 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9268 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 9269 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9270 vmcs12->guest_pending_dbg_exceptions);
9271 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9272 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9273
81dc01f7
WL		 9274 if (nested_cpu_has_xsaves(vmcs12))
9275 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 9276 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9277
f4124500
JK		 9278 exec_control = vmcs12->pin_based_vm_exec_control;
9279 exec_control |= vmcs_config.pin_based_exec_ctrl;
705699a1
WV		 9280 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9281
9282 if (nested_cpu_has_posted_intr(vmcs12)) {
9283 /*
9284 * Note that we use L0's vector here and in
9285 * vmx_deliver_nested_posted_interrupt.
9286 */
9287 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9288 vmx->nested.pi_pending = false;
9289 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9290 vmcs_write64(POSTED_INTR_DESC_ADDR,
9291 page_to_phys(vmx->nested.pi_desc_page) +
9292 (unsigned long)(vmcs12->posted_intr_desc_addr &
9293 (PAGE_SIZE - 1)));
9294 } else
9295 exec_control &= ~PIN_BASED_POSTED_INTR;
9296
f4124500 9297 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 9298
f4124500
JK		 9299 vmx->nested.preemption_timer_expired = false;
9300 if (nested_cpu_has_preemption_timer(vmcs12))
9301 vmx_start_preemption_timer(vcpu);
0238ea91 9302
fe3ef05c
NHE		 9303 /*
9304 * Whether page-faults are trapped is determined by a combination of
9305 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9306 * If enable_ept, L0 doesn't care about page faults and we should
9307 * set all of these to L1's desires. However, if !enable_ept, L0 does
9308 * care about (at least some) page faults, and because it is not easy
9309 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9310 * to exit on each and every L2 page fault. This is done by setting
9311 * MASK=MATCH=0 and (see below) EB.PF=1.
9312 * Note that below we don't need special code to set EB.PF beyond the
9313 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9314 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9315 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9316 *
9317 * A problem with this approach (when !enable_ept) is that L1 may be
9318 * injected with more page faults than it asked for. This could have
9319 * caused problems, but in practice existing hypervisors don't care.
9320 * To fix this, we will need to emulate the PFEC checking (on the L1
9321 * page tables), using walk_addr(), when injecting PFs to L1.
9322 */
9323 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9324 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9325 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9326 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9327
9328 if (cpu_has_secondary_exec_ctrls()) {
f4124500 9329 exec_control = vmx_secondary_exec_control(vmx);
e2821620 9330
fe3ef05c 9331 /* Take the following fields only from vmcs12 */
696dfd95 9332 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 9333 SECONDARY_EXEC_RDTSCP |
696dfd95 9334 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8b3e34e4
XG		 9335 SECONDARY_EXEC_APIC_REGISTER_VIRT |
9336 SECONDARY_EXEC_PCOMMIT);
fe3ef05c
NHE		 9337 if (nested_cpu_has(vmcs12,
9338 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9339 exec_control |= vmcs12->secondary_vm_exec_control;
9340
9341 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 9342 /*
9343 * If translation failed, no matter: This feature asks
9344 * to exit when accessing the given address, and if it
9345 * can never be accessed, this feature won't do
9346 * anything anyway.
9347 */
9348 if (!vmx->nested.apic_access_page)
9349 exec_control &=
9350 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9351 else
9352 vmcs_write64(APIC_ACCESS_ADDR,
9353 page_to_phys(vmx->nested.apic_access_page));
f2b93280 9354 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
35754c98 9355 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
ca3f257a
JK		 9356 exec_control |=
9357 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 9358 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 9359 }
9360
608406e2
WV		 9361 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9362 vmcs_write64(EOI_EXIT_BITMAP0,
9363 vmcs12->eoi_exit_bitmap0);
9364 vmcs_write64(EOI_EXIT_BITMAP1,
9365 vmcs12->eoi_exit_bitmap1);
9366 vmcs_write64(EOI_EXIT_BITMAP2,
9367 vmcs12->eoi_exit_bitmap2);
9368 vmcs_write64(EOI_EXIT_BITMAP3,
9369 vmcs12->eoi_exit_bitmap3);
9370 vmcs_write16(GUEST_INTR_STATUS,
9371 vmcs12->guest_intr_status);
9372 }
9373
fe3ef05c
NHE		 9374 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9375 }
9376
9377
9378 /*
9379 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9380 * Some constant fields are set here by vmx_set_constant_host_state().
9381 * Other fields are different per CPU, and will be set later when
9382 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9383 */
a547c6db 9384 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 9385
9386 /*
9387 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9388 * entry, but only if the current (host) sp changed from the value
9389 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9390 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9391 * here we just force the write to happen on entry.
9392 */
9393 vmx->host_rsp = 0;
9394
9395 exec_control = vmx_exec_control(vmx); /* L0's desires */
9396 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9397 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9398 exec_control &= ~CPU_BASED_TPR_SHADOW;
9399 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 9400
9401 if (exec_control & CPU_BASED_TPR_SHADOW) {
9402 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9403 page_to_phys(vmx->nested.virtual_apic_page));
9404 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9405 }
9406
3af18d9c 9407 if (cpu_has_vmx_msr_bitmap() &&
670125bd
WV		 9408 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9409 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9410 /* MSR_BITMAP will be set by following vmx_set_efer. */
3af18d9c
WV		 9411 } else
9412 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9413
fe3ef05c 9414 /*
3af18d9c 9415 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 9416 * Rather, exit every time.
9417 */
fe3ef05c
NHE		 9418 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9419 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9420
9421 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9422
9423 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9424 * bitwise-or of what L1 wants to trap for L2, and what we want to
9425 * trap. Note that CR0.TS also needs updating - we do this later.
9426 */
9427 update_exception_bitmap(vcpu);
9428 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9429 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9430
8049d651
NHE		 9431 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9432 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9433 * bits are further modified by vmx_set_efer() below.
9434 */
f4124500 9435 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9436
9437 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9438 * emulated by vmx_set_efer(), below.
9439 */
2961e876 9440 vm_entry_controls_init(vmx,
8049d651
NHE		 9441 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9442 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9443 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9444
44811c02 9445 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9446 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9447 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9448 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9449 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9450
9451
9452 set_cr4_guest_host_mask(vmx);
9453
36be0b9d
PB		 9454 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9455 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9456
27fc51b2
NHE		 9457 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9458 vmcs_write64(TSC_OFFSET,
9459 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9460 else
9461 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9462
9463 if (enable_vpid) {
9464 /*
9465 * Trivially support vpid by letting L2s share their parent
9466 * L1's vpid. TODO: move to a more elaborate solution, giving
9467 * each L2 its own vpid and exposing the vpid feature to L1.
9468 */
9469 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9470 vmx_flush_tlb(vcpu);
9471 }
9472
155a97a3
NHE		 9473 if (nested_cpu_has_ept(vmcs12)) {
9474 kvm_mmu_unload(vcpu);
9475 nested_ept_init_mmu_context(vcpu);
9476 }
9477
fe3ef05c
NHE		 9478 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9479 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9480 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9481 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9482 else
9483 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9484 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9485 vmx_set_efer(vcpu, vcpu->arch.efer);
9486
9487 /*
9488 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9489 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9490 * The CR0_READ_SHADOW is what L2 should have expected to read given
9491 * the specifications by L1; It's not enough to take
9492 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9493 * have more bits than L1 expected.
9494 */
9495 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9496 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9497
9498 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9499 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9500
9501 /* shadow page tables on either EPT or shadow page tables */
9502 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9503 kvm_mmu_reset_context(vcpu);
9504
feaf0c7d
GN		 9505 if (!enable_ept)
9506 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9507
3633cfc3
NHE		 9508 /*
9509 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9510 */
9511 if (enable_ept) {
9512 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9513 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9514 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9515 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9516 }
9517
fe3ef05c
NHE		 9518 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9519 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9520}
9521
cd232ad0
NHE		 9522/*
9523 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9524 * for running an L2 nested guest.
9525 */
9526static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9527{
9528 struct vmcs12 *vmcs12;
9529 struct vcpu_vmx *vmx = to_vmx(vcpu);
9530 int cpu;
9531 struct loaded_vmcs *vmcs02;
384bb783 9532 bool ia32e;
ff651cb6 9533 u32 msr_entry_idx;
cd232ad0
NHE		 9534
9535 if (!nested_vmx_check_permission(vcpu) ||
9536 !nested_vmx_check_vmcs12(vcpu))
9537 return 1;
9538
9539 skip_emulated_instruction(vcpu);
9540 vmcs12 = get_vmcs12(vcpu);
9541
012f83cb
AG		 9542 if (enable_shadow_vmcs)
9543 copy_shadow_to_vmcs12(vmx);
9544
7c177938
NHE		 9545 /*
9546 * The nested entry process starts with enforcing various prerequisites
9547 * on vmcs12 as required by the Intel SDM, and act appropriately when
9548 * they fail: As the SDM explains, some conditions should cause the
9549 * instruction to fail, while others will cause the instruction to seem
9550 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9551 * To speed up the normal (success) code path, we should avoid checking
9552 * for misconfigurations which will anyway be caught by the processor
9553 * when using the merged vmcs02.
9554 */
9555 if (vmcs12->launch_state == launch) {
9556 nested_vmx_failValid(vcpu,
9557 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9558 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9559 return 1;
9560 }
9561
6dfacadd
JK		 9562 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9563 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9564 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9565 return 1;
9566 }
9567
3af18d9c 9568 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9569 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9570 return 1;
9571 }
9572
3af18d9c 9573 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9574 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9575 return 1;
9576 }
9577
f2b93280
WV		 9578 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9579 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9580 return 1;
9581 }
9582
e9ac033e
EK		 9583 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9584 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9585 return 1;
9586 }
9587
7c177938 9588 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9589 vmx->nested.nested_vmx_true_procbased_ctls_low,
9590 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9591 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9592 vmx->nested.nested_vmx_secondary_ctls_low,
9593 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9594 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9595 vmx->nested.nested_vmx_pinbased_ctls_low,
9596 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9597 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9598 vmx->nested.nested_vmx_true_exit_ctls_low,
9599 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9600 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9601 vmx->nested.nested_vmx_true_entry_ctls_low,
9602 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9603 {
9604 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9605 return 1;
9606 }
9607
9608 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9609 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9610 nested_vmx_failValid(vcpu,
9611 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9612 return 1;
9613 }
9614
b9c237bb 9615 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9616 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9617 nested_vmx_entry_failure(vcpu, vmcs12,
9618 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9619 return 1;
9620 }
9621 if (vmcs12->vmcs_link_pointer != -1ull) {
9622 nested_vmx_entry_failure(vcpu, vmcs12,
9623 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9624 return 1;
9625 }
9626
384bb783 9627 /*
cb0c8cda 9628 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9629 * are performed on the field for the IA32_EFER MSR:
9630 * - Bits reserved in the IA32_EFER MSR must be 0.
9631 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9632 * the IA-32e mode guest VM-exit control. It must also be identical
9633 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9634 * CR0.PG) is 1.
9635 */
9636 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9637 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9638 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9639 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9640 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9641 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9642 nested_vmx_entry_failure(vcpu, vmcs12,
9643 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9644 return 1;
9645 }
9646 }
9647
9648 /*
9649 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9650 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9651 * the values of the LMA and LME bits in the field must each be that of
9652 * the host address-space size VM-exit control.
9653 */
9654 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9655 ia32e = (vmcs12->vm_exit_controls &
9656 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9657 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9658 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9659 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9660 nested_vmx_entry_failure(vcpu, vmcs12,
9661 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9662 return 1;
9663 }
9664 }
9665
7c177938
NHE		 9666 /*
9667 * We're finally done with prerequisite checking, and can start with
9668 * the nested entry.
9669 */
9670
cd232ad0
NHE		 9671 vmcs02 = nested_get_current_vmcs02(vmx);
9672 if (!vmcs02)
9673 return -ENOMEM;
9674
9675 enter_guest_mode(vcpu);
9676
9677 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9678
2996fca0
JK		 9679 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9680 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9681
cd232ad0
NHE		 9682 cpu = get_cpu();
9683 vmx->loaded_vmcs = vmcs02;
9684 vmx_vcpu_put(vcpu);
9685 vmx_vcpu_load(vcpu, cpu);
9686 vcpu->cpu = cpu;
9687 put_cpu();
9688
36c3cc42
JK		 9689 vmx_segment_cache_clear(vmx);
9690
cd232ad0
NHE		 9691 prepare_vmcs02(vcpu, vmcs12);
9692
ff651cb6
WV		 9693 msr_entry_idx = nested_vmx_load_msr(vcpu,
9694 vmcs12->vm_entry_msr_load_addr,
9695 vmcs12->vm_entry_msr_load_count);
9696 if (msr_entry_idx) {
9697 leave_guest_mode(vcpu);
9698 vmx_load_vmcs01(vcpu);
9699 nested_vmx_entry_failure(vcpu, vmcs12,
9700 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9701 return 1;
9702 }
9703
9704 vmcs12->launch_state = 1;
9705
6dfacadd 9706 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 9707 return kvm_vcpu_halt(vcpu);
6dfacadd 9708
7af40ad3
JK		 9709 vmx->nested.nested_run_pending = 1;
9710
cd232ad0
NHE		 9711 /*
9712 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9713 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9714 * returned as far as L1 is concerned. It will only return (and set
9715 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9716 */
9717 return 1;
9718}
9719
4704d0be
NHE		 9720/*
9721 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9722 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9723 * This function returns the new value we should put in vmcs12.guest_cr0.
9724 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9725 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9726 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9727 * didn't trap the bit, because if L1 did, so would L0).
9728 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9729 * been modified by L2, and L1 knows it. So just leave the old value of
9730 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9731 * isn't relevant, because if L0 traps this bit it can set it to anything.
9732 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9733 * changed these bits, and therefore they need to be updated, but L0
9734 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9735 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9736 */
9737static inline unsigned long
9738vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9739{
9740 return
9741 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9742 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9743 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9744 vcpu->arch.cr0_guest_owned_bits));
9745}
9746
9747static inline unsigned long
9748vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9749{
9750 return
9751 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9752 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9753 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9754 vcpu->arch.cr4_guest_owned_bits));
9755}
9756
5f3d5799
JK		 9757static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9758 struct vmcs12 *vmcs12)
9759{
9760 u32 idt_vectoring;
9761 unsigned int nr;
9762
851eb667 9763 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9764 nr = vcpu->arch.exception.nr;
9765 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9766
9767 if (kvm_exception_is_soft(nr)) {
9768 vmcs12->vm_exit_instruction_len =
9769 vcpu->arch.event_exit_inst_len;
9770 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9771 } else
9772 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9773
9774 if (vcpu->arch.exception.has_error_code) {
9775 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9776 vmcs12->idt_vectoring_error_code =
9777 vcpu->arch.exception.error_code;
9778 }
9779
9780 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9781 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9782 vmcs12->idt_vectoring_info_field =
9783 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9784 } else if (vcpu->arch.interrupt.pending) {
9785 nr = vcpu->arch.interrupt.nr;
9786 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9787
9788 if (vcpu->arch.interrupt.soft) {
9789 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9790 vmcs12->vm_entry_instruction_len =
9791 vcpu->arch.event_exit_inst_len;
9792 } else
9793 idt_vectoring |= INTR_TYPE_EXT_INTR;
9794
9795 vmcs12->idt_vectoring_info_field = idt_vectoring;
9796 }
9797}
9798
b6b8a145
JK		 9799static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9800{
9801 struct vcpu_vmx *vmx = to_vmx(vcpu);
9802
f4124500
JK		 9803 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9804 vmx->nested.preemption_timer_expired) {
9805 if (vmx->nested.nested_run_pending)
9806 return -EBUSY;
9807 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9808 return 0;
9809 }
9810
b6b8a145 9811 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9812 if (vmx->nested.nested_run_pending ||
9813 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9814 return -EBUSY;
9815 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9816 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9817 INTR_INFO_VALID_MASK, 0);
9818 /*
9819 * The NMI-triggered VM exit counts as injection:
9820 * clear this one and block further NMIs.
9821 */
9822 vcpu->arch.nmi_pending = 0;
9823 vmx_set_nmi_mask(vcpu, true);
9824 return 0;
9825 }
9826
9827 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9828 nested_exit_on_intr(vcpu)) {
9829 if (vmx->nested.nested_run_pending)
9830 return -EBUSY;
9831 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 9832 return 0;
b6b8a145
JK		 9833 }
9834
705699a1 9835 return vmx_complete_nested_posted_interrupt(vcpu);
b6b8a145
JK		 9836}
9837
f4124500
JK		 9838static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9839{
9840 ktime_t remaining =
9841 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9842 u64 value;
9843
9844 if (ktime_to_ns(remaining) <= 0)
9845 return 0;
9846
9847 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9848 do_div(value, 1000000);
9849 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9850}
9851
4704d0be
NHE		 9852/*
9853 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9854 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9855 * and this function updates it to reflect the changes to the guest state while
9856 * L2 was running (and perhaps made some exits which were handled directly by L0
9857 * without going back to L1), and to reflect the exit reason.
9858 * Note that we do not have to copy here all VMCS fields, just those that
9859 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9860 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9861 * which already writes to vmcs12 directly.
9862 */
533558bc
JK		 9863static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9864 u32 exit_reason, u32 exit_intr_info,
9865 unsigned long exit_qualification)
4704d0be
NHE		 9866{
9867 /* update guest state fields: */
9868 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9869 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9870
4704d0be
NHE		 9871 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9872 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9873 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9874
9875 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9876 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9877 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9878 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9879 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9880 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9881 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9882 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9883 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9884 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9885 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9886 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9887 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9888 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9889 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9890 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9891 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9892 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9893 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9894 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9895 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9896 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9897 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9898 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9899 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9900 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9901 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9902 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9903 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9904 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9905 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9906 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9907 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9908 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9909 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9910 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9911
4704d0be
NHE		 9912 vmcs12->guest_interruptibility_info =
9913 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9914 vmcs12->guest_pending_dbg_exceptions =
9915 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9916 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9917 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9918 else
9919 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9920
f4124500
JK		 9921 if (nested_cpu_has_preemption_timer(vmcs12)) {
9922 if (vmcs12->vm_exit_controls &
9923 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9924 vmcs12->vmx_preemption_timer_value =
9925 vmx_get_preemption_timer_value(vcpu);
9926 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9927 }
7854cbca 9928
3633cfc3
NHE		 9929 /*
9930 * In some cases (usually, nested EPT), L2 is allowed to change its
9931 * own CR3 without exiting. If it has changed it, we must keep it.
9932 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9933 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9934 *
9935 * Additionally, restore L2's PDPTR to vmcs12.
9936 */
9937 if (enable_ept) {
9938 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9939 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9940 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9941 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9942 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9943 }
9944
608406e2
WV		 9945 if (nested_cpu_has_vid(vmcs12))
9946 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9947
c18911a2
JK		 9948 vmcs12->vm_entry_controls =
9949 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9950 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9951
2996fca0
JK		 9952 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9953 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9954 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9955 }
9956
4704d0be
NHE		 9957 /* TODO: These cannot have changed unless we have MSR bitmaps and
9958 * the relevant bit asks not to trap the change */
b8c07d55 9959 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9960 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9961 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9962 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 9963 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9964 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9965 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 9966 if (vmx_mpx_supported())
9967 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 9968 if (nested_cpu_has_xsaves(vmcs12))
9969 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 9970
9971 /* update exit information fields: */
9972
533558bc
JK		 9973 vmcs12->vm_exit_reason = exit_reason;
9974 vmcs12->exit_qualification = exit_qualification;
4704d0be 9975
533558bc 9976 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 9977 if ((vmcs12->vm_exit_intr_info &
9978 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9979 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9980 vmcs12->vm_exit_intr_error_code =
9981 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 9982 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 9983 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9984 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9985
5f3d5799
JK		 9986 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9987 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9988 * instead of reading the real value. */
4704d0be 9989 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 9990
9991 /*
9992 * Transfer the event that L0 or L1 may wanted to inject into
9993 * L2 to IDT_VECTORING_INFO_FIELD.
9994 */
9995 vmcs12_save_pending_event(vcpu, vmcs12);
9996 }
9997
9998 /*
9999 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10000 * preserved above and would only end up incorrectly in L1.
10001 */
10002 vcpu->arch.nmi_injected = false;
10003 kvm_clear_exception_queue(vcpu);
10004 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 10005}
10006
10007/*
10008 * A part of what we need to when the nested L2 guest exits and we want to
10009 * run its L1 parent, is to reset L1's guest state to the host state specified
10010 * in vmcs12.
10011 * This function is to be called not only on normal nested exit, but also on
10012 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10013 * Failures During or After Loading Guest State").
10014 * This function should be called when the active VMCS is L1's (vmcs01).
10015 */
733568f9
JK		 10016static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10017 struct vmcs12 *vmcs12)
4704d0be 10018{
21feb4eb
ACL		 10019 struct kvm_segment seg;
10020
4704d0be
NHE		 10021 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10022 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10023 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 10024 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10025 else
10026 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10027 vmx_set_efer(vcpu, vcpu->arch.efer);
10028
10029 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10030 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10031 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 10032 /*
10033 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10034 * actually changed, because it depends on the current state of
10035 * fpu_active (which may have changed).
10036 * Note that vmx_set_cr0 refers to efer set above.
10037 */
9e3e4dbf 10038 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 10039 /*
10040 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10041 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10042 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10043 */
10044 update_exception_bitmap(vcpu);
10045 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10046 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10047
10048 /*
10049 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10050 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10051 */
10052 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10053 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10054
29bf08f1 10055 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10056
4704d0be
NHE		 10057 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10058 kvm_mmu_reset_context(vcpu);
10059
feaf0c7d
GN		 10060 if (!enable_ept)
10061 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10062
4704d0be
NHE		 10063 if (enable_vpid) {
10064 /*
10065 * Trivially support vpid by letting L2s share their parent
10066 * L1's vpid. TODO: move to a more elaborate solution, giving
10067 * each L2 its own vpid and exposing the vpid feature to L1.
10068 */
10069 vmx_flush_tlb(vcpu);
10070 }
10071
10072
10073 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10074 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10075 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10076 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10077 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10078
36be0b9d
PB		 10079 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10080 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10081 vmcs_write64(GUEST_BNDCFGS, 0);
10082
44811c02 10083 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10084 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 10085 vcpu->arch.pat = vmcs12->host_ia32_pat;
10086 }
4704d0be
NHE		 10087 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10088 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10089 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10090
21feb4eb
ACL		 10091 /* Set L1 segment info according to Intel SDM
10092 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10093 seg = (struct kvm_segment) {
10094 .base = 0,
10095 .limit = 0xFFFFFFFF,
10096 .selector = vmcs12->host_cs_selector,
10097 .type = 11,
10098 .present = 1,
10099 .s = 1,
10100 .g = 1
10101 };
10102 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10103 seg.l = 1;
10104 else
10105 seg.db = 1;
10106 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10107 seg = (struct kvm_segment) {
10108 .base = 0,
10109 .limit = 0xFFFFFFFF,
10110 .type = 3,
10111 .present = 1,
10112 .s = 1,
10113 .db = 1,
10114 .g = 1
10115 };
10116 seg.selector = vmcs12->host_ds_selector;
10117 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10118 seg.selector = vmcs12->host_es_selector;
10119 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10120 seg.selector = vmcs12->host_ss_selector;
10121 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10122 seg.selector = vmcs12->host_fs_selector;
10123 seg.base = vmcs12->host_fs_base;
10124 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10125 seg.selector = vmcs12->host_gs_selector;
10126 seg.base = vmcs12->host_gs_base;
10127 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10128 seg = (struct kvm_segment) {
205befd9 10129 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 10130 .limit = 0x67,
10131 .selector = vmcs12->host_tr_selector,
10132 .type = 11,
10133 .present = 1
10134 };
10135 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10136
503cd0c5
JK		 10137 kvm_set_dr(vcpu, 7, 0x400);
10138 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 10139
3af18d9c
WV		 10140 if (cpu_has_vmx_msr_bitmap())
10141 vmx_set_msr_bitmap(vcpu);
10142
ff651cb6
WV		 10143 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10144 vmcs12->vm_exit_msr_load_count))
10145 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 10146}
10147
10148/*
10149 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10150 * and modify vmcs12 to make it see what it would expect to see there if
10151 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10152 */
533558bc
JK		 10153static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10154 u32 exit_intr_info,
10155 unsigned long exit_qualification)
4704d0be
NHE		 10156{
10157 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 10158 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10159
5f3d5799
JK		 10160 /* trying to cancel vmlaunch/vmresume is a bug */
10161 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10162
4704d0be 10163 leave_guest_mode(vcpu);
533558bc
JK		 10164 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10165 exit_qualification);
4704d0be 10166
ff651cb6
WV		 10167 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10168 vmcs12->vm_exit_msr_store_count))
10169 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10170
f3380ca5
WL		 10171 vmx_load_vmcs01(vcpu);
10172
77b0f5d6
BD		 10173 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10174 && nested_exit_intr_ack_set(vcpu)) {
10175 int irq = kvm_cpu_get_interrupt(vcpu);
10176 WARN_ON(irq < 0);
10177 vmcs12->vm_exit_intr_info = irq |
10178 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10179 }
10180
542060ea
JK		 10181 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10182 vmcs12->exit_qualification,
10183 vmcs12->idt_vectoring_info_field,
10184 vmcs12->vm_exit_intr_info,
10185 vmcs12->vm_exit_intr_error_code,
10186 KVM_ISA_VMX);
4704d0be 10187
2961e876
GN		 10188 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10189 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 10190 vmx_segment_cache_clear(vmx);
10191
4704d0be
NHE		 10192 /* if no vmcs02 cache requested, remove the one we used */
10193 if (VMCS02_POOL_SIZE == 0)
10194 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10195
10196 load_vmcs12_host_state(vcpu, vmcs12);
10197
27fc51b2 10198 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 10199 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10200
10201 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10202 vmx->host_rsp = 0;
10203
10204 /* Unpin physical memory we referred to in vmcs02 */
10205 if (vmx->nested.apic_access_page) {
10206 nested_release_page(vmx->nested.apic_access_page);
48d89b92 10207 vmx->nested.apic_access_page = NULL;
4704d0be 10208 }
a7c0b07d
WL		 10209 if (vmx->nested.virtual_apic_page) {
10210 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 10211 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 10212 }
705699a1
WV		 10213 if (vmx->nested.pi_desc_page) {
10214 kunmap(vmx->nested.pi_desc_page);
10215 nested_release_page(vmx->nested.pi_desc_page);
10216 vmx->nested.pi_desc_page = NULL;
10217 vmx->nested.pi_desc = NULL;
10218 }
4704d0be 10219
38b99173
TC		 10220 /*
10221 * We are now running in L2, mmu_notifier will force to reload the
10222 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10223 */
10224 kvm_vcpu_reload_apic_access_page(vcpu);
10225
4704d0be
NHE		 10226 /*
10227 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10228 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10229 * success or failure flag accordingly.
10230 */
10231 if (unlikely(vmx->fail)) {
10232 vmx->fail = 0;
10233 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10234 } else
10235 nested_vmx_succeed(vcpu);
012f83cb
AG		 10236 if (enable_shadow_vmcs)
10237 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 10238
10239 /* in case we halted in L2 */
10240 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 10241}
10242
42124925
JK		 10243/*
10244 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10245 */
10246static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10247{
10248 if (is_guest_mode(vcpu))
533558bc 10249 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 10250 free_nested(to_vmx(vcpu));
10251}
10252
7c177938
NHE		 10253/*
10254 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10255 * 23.7 "VM-entry failures during or after loading guest state" (this also
10256 * lists the acceptable exit-reason and exit-qualification parameters).
10257 * It should only be called before L2 actually succeeded to run, and when
10258 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10259 */
10260static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10261 struct vmcs12 *vmcs12,
10262 u32 reason, unsigned long qualification)
10263{
10264 load_vmcs12_host_state(vcpu, vmcs12);
10265 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10266 vmcs12->exit_qualification = qualification;
10267 nested_vmx_succeed(vcpu);
012f83cb
AG		 10268 if (enable_shadow_vmcs)
10269 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 10270}
10271
8a76d7f2
JR		 10272static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10273 struct x86_instruction_info *info,
10274 enum x86_intercept_stage stage)
10275{
10276 return X86EMUL_CONTINUE;
10277}
10278
48d89b92 10279static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 10280{
b4a2d31d
RK		 10281 if (ple_gap)
10282 shrink_ple_window(vcpu);
ae97a3b8
RK		 10283}
10284
843e4330
KH		 10285static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10286 struct kvm_memory_slot *slot)
10287{
10288 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10289 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10290}
10291
10292static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10293 struct kvm_memory_slot *slot)
10294{
10295 kvm_mmu_slot_set_dirty(kvm, slot);
10296}
10297
10298static void vmx_flush_log_dirty(struct kvm *kvm)
10299{
10300 kvm_flush_pml_buffers(kvm);
10301}
10302
10303static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10304 struct kvm_memory_slot *memslot,
10305 gfn_t offset, unsigned long mask)
10306{
10307 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10308}
10309
cbdd1bea 10310static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 10311 .cpu_has_kvm_support = cpu_has_kvm_support,
10312 .disabled_by_bios = vmx_disabled_by_bios,
10313 .hardware_setup = hardware_setup,
10314 .hardware_unsetup = hardware_unsetup,
002c7f7c 10315 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 10316 .hardware_enable = hardware_enable,
10317 .hardware_disable = hardware_disable,
04547156 10318 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 10319 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK		 10320
10321 .vcpu_create = vmx_create_vcpu,
10322 .vcpu_free = vmx_free_vcpu,
04d2cc77 10323 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 10324
04d2cc77 10325 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 10326 .vcpu_load = vmx_vcpu_load,
10327 .vcpu_put = vmx_vcpu_put,
10328
c8639010 10329 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 10330 .get_msr = vmx_get_msr,
10331 .set_msr = vmx_set_msr,
10332 .get_segment_base = vmx_get_segment_base,
10333 .get_segment = vmx_get_segment,
10334 .set_segment = vmx_set_segment,
2e4d2653 10335 .get_cpl = vmx_get_cpl,
6aa8b732 10336 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 10337 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 10338 .decache_cr3 = vmx_decache_cr3,
25c4c276 10339 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 10340 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 10341 .set_cr3 = vmx_set_cr3,
10342 .set_cr4 = vmx_set_cr4,
6aa8b732 10343 .set_efer = vmx_set_efer,
6aa8b732
AK		 10344 .get_idt = vmx_get_idt,
10345 .set_idt = vmx_set_idt,
10346 .get_gdt = vmx_get_gdt,
10347 .set_gdt = vmx_set_gdt,
73aaf249
JK		 10348 .get_dr6 = vmx_get_dr6,
10349 .set_dr6 = vmx_set_dr6,
020df079 10350 .set_dr7 = vmx_set_dr7,
81908bf4 10351 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 10352 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 10353 .get_rflags = vmx_get_rflags,
10354 .set_rflags = vmx_set_rflags,
0fdd74f7 10355 .fpu_activate = vmx_fpu_activate,
02daab21 10356 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 10357
10358 .tlb_flush = vmx_flush_tlb,
6aa8b732 10359
6aa8b732 10360 .run = vmx_vcpu_run,
6062d012 10361 .handle_exit = vmx_handle_exit,
6aa8b732 10362 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 10363 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10364 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 10365 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 10366 .set_irq = vmx_inject_irq,
95ba8273 10367 .set_nmi = vmx_inject_nmi,
298101da 10368 .queue_exception = vmx_queue_exception,
b463a6f7 10369 .cancel_injection = vmx_cancel_injection,
78646121 10370 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 10371 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 10372 .get_nmi_mask = vmx_get_nmi_mask,
10373 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 10374 .enable_nmi_window = enable_nmi_window,
10375 .enable_irq_window = enable_irq_window,
10376 .update_cr8_intercept = update_cr8_intercept,
8d14695f 10377 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 10378 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d50ab6c1 10379 .cpu_uses_apicv = vmx_cpu_uses_apicv,
c7c9c56c
YZ		 10380 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10381 .hwapic_irr_update = vmx_hwapic_irr_update,
10382 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 10383 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10384 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 10385
cbc94022 10386 .set_tss_addr = vmx_set_tss_addr,
67253af5 10387 .get_tdp_level = get_ept_level,
4b12f0de 10388 .get_mt_mask = vmx_get_mt_mask,
229456fc 10389
586f9607 10390 .get_exit_info = vmx_get_exit_info,
586f9607 10391
17cc3935 10392 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 10393
10394 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 10395
10396 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 10397 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 10398
10399 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 10400
10401 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 10402
4051b188 10403 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 10404 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 10405 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 10406 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 10407 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 10408 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 10409
10410 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 10411
10412 .check_intercept = vmx_check_intercept,
a547c6db 10413 .handle_external_intr = vmx_handle_external_intr,
da8999d3 10414 .mpx_supported = vmx_mpx_supported,
55412b2e 10415 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 10416
10417 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 10418
10419 .sched_in = vmx_sched_in,
843e4330
KH		 10420
10421 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10422 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10423 .flush_log_dirty = vmx_flush_log_dirty,
10424 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
25462f7f
WH		 10425
10426 .pmu_ops = &intel_pmu_ops,
6aa8b732
AK		 10427};
10428
10429static int __init vmx_init(void)
10430{
34a1cd60
TC		 10431 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10432 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 10433 if (r)
34a1cd60 10434 return r;
25c5f225 10435
2965faa5 10436#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 10437 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10438 crash_vmclear_local_loaded_vmcss);
10439#endif
10440
fdef3ad1 10441 return 0;
6aa8b732
AK		 10442}
10443
10444static void __exit vmx_exit(void)
10445{
2965faa5 10446#ifdef CONFIG_KEXEC_CORE
3b63a43f 10447 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10448 synchronize_rcu();
10449#endif
10450
cb498ea2 10451 kvm_exit();
6aa8b732
AK		 10452}
10453
10454module_init(vmx_init)
10455module_exit(vmx_exit)
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