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context_tracking: avoid irq_save/irq_restore on guest entry and exit
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
af658dca 31#include <linux/trace_events.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
28b835d6 38#include <asm/cpu.h>
6aa8b732 39#include <asm/io.h>
3b3be0d1 40#include <asm/desc.h>
13673a90 41#include <asm/vmx.h>
6210e37b 42#include <asm/virtext.h>
a0861c02 43#include <asm/mce.h>
952f07ec 44#include <asm/fpu/internal.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
dab2087d 48#include <asm/apic.h>
efc64404 49#include <asm/irq_remapping.h>
6aa8b732 50
229456fc 51#include "trace.h"
25462f7f 52#include "pmu.h"
229456fc 53
4ecac3fd 54#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 55#define __ex_clear(x, reg) \
56 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 57
6aa8b732
AK		 58MODULE_AUTHOR("Qumranet");
59MODULE_LICENSE("GPL");
60
e9bda3b3
JT		 61static const struct x86_cpu_id vmx_cpu_id[] = {
62 X86_FEATURE_MATCH(X86_FEATURE_VMX),
63 {}
64};
65MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
66
476bc001 67static bool __read_mostly enable_vpid = 1;
736caefe 68module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 69
476bc001 70static bool __read_mostly flexpriority_enabled = 1;
736caefe 71module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 72
476bc001 73static bool __read_mostly enable_ept = 1;
736caefe 74module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 75
476bc001 76static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 77module_param_named(unrestricted_guest,
78 enable_unrestricted_guest, bool, S_IRUGO);
79
83c3a331
XH		 80static bool __read_mostly enable_ept_ad_bits = 1;
81module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
82
a27685c3 83static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 84module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 85
476bc001 86static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 87module_param(vmm_exclusive, bool, S_IRUGO);
88
476bc001 89static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 90module_param(fasteoi, bool, S_IRUGO);
91
5a71785d 92static bool __read_mostly enable_apicv = 1;
01e439be 93module_param(enable_apicv, bool, S_IRUGO);
83d4c286 94
abc4fc58
AG		 95static bool __read_mostly enable_shadow_vmcs = 1;
96module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 97/*
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
101 */
476bc001 102static bool __read_mostly nested = 0;
801d3424
NHE		 103module_param(nested, bool, S_IRUGO);
104
20300099
WL		 105static u64 __read_mostly host_xss;
106
843e4330
KH		 107static bool __read_mostly enable_pml = 1;
108module_param_named(pml, enable_pml, bool, S_IRUGO);
109
64903d61
HZ		 110#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
111
5037878e
GN		 112#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
113#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 114#define KVM_VM_CR0_ALWAYS_ON \
115 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 116#define KVM_CR4_GUEST_OWNED_BITS \
117 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 118 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 119
cdc0e244
AK		 120#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
121#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
122
78ac8b47
AK		 123#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
124
f4124500
JK		 125#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
126
4b8d54f9
ZE		 127/*
128 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
129 * ple_gap: upper bound on the amount of time between two successive
130 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 131 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 132 * ple_window: upper bound on the amount of time a guest is allowed to execute
133 * in a PAUSE loop. Tests indicate that most spinlocks are held for
134 * less than 2^12 cycles
135 * Time is measured based on a counter that runs at the same rate as the TSC,
136 * refer SDM volume 3b section 21.6.13 & 22.1.3.
137 */
b4a2d31d
RK		 138#define KVM_VMX_DEFAULT_PLE_GAP 128
139#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
140#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
141#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
142#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
143 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
144
4b8d54f9
ZE		 145static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
146module_param(ple_gap, int, S_IRUGO);
147
148static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
149module_param(ple_window, int, S_IRUGO);
150
b4a2d31d
RK		 151/* Default doubles per-vcpu window every exit. */
152static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
153module_param(ple_window_grow, int, S_IRUGO);
154
155/* Default resets per-vcpu window every exit to ple_window. */
156static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
157module_param(ple_window_shrink, int, S_IRUGO);
158
159/* Default is to compute the maximum so we can never overflow. */
160static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
161static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
162module_param(ple_window_max, int, S_IRUGO);
163
83287ea4
AK		 164extern const ulong vmx_return;
165
8bf00a52 166#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 167#define VMCS02_POOL_SIZE 1
61d2ef2c 168
a2fa3e9f
GH		 169struct vmcs {
170 u32 revision_id;
171 u32 abort;
172 char data[0];
173};
174
d462b819
NHE		 175/*
176 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
177 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
178 * loaded on this CPU (so we can clear them if the CPU goes down).
179 */
180struct loaded_vmcs {
181 struct vmcs *vmcs;
182 int cpu;
183 int launched;
184 struct list_head loaded_vmcss_on_cpu_link;
185};
186
26bb0981
AK		 187struct shared_msr_entry {
188 unsigned index;
189 u64 data;
d5696725 190 u64 mask;
26bb0981
AK		 191};
192
a9d30f33
NHE		 193/*
194 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
195 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
196 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
197 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
198 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
199 * More than one of these structures may exist, if L1 runs multiple L2 guests.
200 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
201 * underlying hardware which will be used to run L2.
202 * This structure is packed to ensure that its layout is identical across
203 * machines (necessary for live migration).
204 * If there are changes in this struct, VMCS12_REVISION must be changed.
205 */
22bd0358 206typedef u64 natural_width;
a9d30f33
NHE		 207struct __packed vmcs12 {
208 /* According to the Intel spec, a VMCS region must start with the
209 * following two fields. Then follow implementation-specific data.
210 */
211 u32 revision_id;
212 u32 abort;
22bd0358 213
27d6c865
NHE		 214 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
215 u32 padding[7]; /* room for future expansion */
216
22bd0358
NHE		 217 u64 io_bitmap_a;
218 u64 io_bitmap_b;
219 u64 msr_bitmap;
220 u64 vm_exit_msr_store_addr;
221 u64 vm_exit_msr_load_addr;
222 u64 vm_entry_msr_load_addr;
223 u64 tsc_offset;
224 u64 virtual_apic_page_addr;
225 u64 apic_access_addr;
705699a1 226 u64 posted_intr_desc_addr;
22bd0358 227 u64 ept_pointer;
608406e2
WV		 228 u64 eoi_exit_bitmap0;
229 u64 eoi_exit_bitmap1;
230 u64 eoi_exit_bitmap2;
231 u64 eoi_exit_bitmap3;
81dc01f7 232 u64 xss_exit_bitmap;
22bd0358
NHE		 233 u64 guest_physical_address;
234 u64 vmcs_link_pointer;
235 u64 guest_ia32_debugctl;
236 u64 guest_ia32_pat;
237 u64 guest_ia32_efer;
238 u64 guest_ia32_perf_global_ctrl;
239 u64 guest_pdptr0;
240 u64 guest_pdptr1;
241 u64 guest_pdptr2;
242 u64 guest_pdptr3;
36be0b9d 243 u64 guest_bndcfgs;
22bd0358
NHE		 244 u64 host_ia32_pat;
245 u64 host_ia32_efer;
246 u64 host_ia32_perf_global_ctrl;
247 u64 padding64[8]; /* room for future expansion */
248 /*
249 * To allow migration of L1 (complete with its L2 guests) between
250 * machines of different natural widths (32 or 64 bit), we cannot have
251 * unsigned long fields with no explict size. We use u64 (aliased
252 * natural_width) instead. Luckily, x86 is little-endian.
253 */
254 natural_width cr0_guest_host_mask;
255 natural_width cr4_guest_host_mask;
256 natural_width cr0_read_shadow;
257 natural_width cr4_read_shadow;
258 natural_width cr3_target_value0;
259 natural_width cr3_target_value1;
260 natural_width cr3_target_value2;
261 natural_width cr3_target_value3;
262 natural_width exit_qualification;
263 natural_width guest_linear_address;
264 natural_width guest_cr0;
265 natural_width guest_cr3;
266 natural_width guest_cr4;
267 natural_width guest_es_base;
268 natural_width guest_cs_base;
269 natural_width guest_ss_base;
270 natural_width guest_ds_base;
271 natural_width guest_fs_base;
272 natural_width guest_gs_base;
273 natural_width guest_ldtr_base;
274 natural_width guest_tr_base;
275 natural_width guest_gdtr_base;
276 natural_width guest_idtr_base;
277 natural_width guest_dr7;
278 natural_width guest_rsp;
279 natural_width guest_rip;
280 natural_width guest_rflags;
281 natural_width guest_pending_dbg_exceptions;
282 natural_width guest_sysenter_esp;
283 natural_width guest_sysenter_eip;
284 natural_width host_cr0;
285 natural_width host_cr3;
286 natural_width host_cr4;
287 natural_width host_fs_base;
288 natural_width host_gs_base;
289 natural_width host_tr_base;
290 natural_width host_gdtr_base;
291 natural_width host_idtr_base;
292 natural_width host_ia32_sysenter_esp;
293 natural_width host_ia32_sysenter_eip;
294 natural_width host_rsp;
295 natural_width host_rip;
296 natural_width paddingl[8]; /* room for future expansion */
297 u32 pin_based_vm_exec_control;
298 u32 cpu_based_vm_exec_control;
299 u32 exception_bitmap;
300 u32 page_fault_error_code_mask;
301 u32 page_fault_error_code_match;
302 u32 cr3_target_count;
303 u32 vm_exit_controls;
304 u32 vm_exit_msr_store_count;
305 u32 vm_exit_msr_load_count;
306 u32 vm_entry_controls;
307 u32 vm_entry_msr_load_count;
308 u32 vm_entry_intr_info_field;
309 u32 vm_entry_exception_error_code;
310 u32 vm_entry_instruction_len;
311 u32 tpr_threshold;
312 u32 secondary_vm_exec_control;
313 u32 vm_instruction_error;
314 u32 vm_exit_reason;
315 u32 vm_exit_intr_info;
316 u32 vm_exit_intr_error_code;
317 u32 idt_vectoring_info_field;
318 u32 idt_vectoring_error_code;
319 u32 vm_exit_instruction_len;
320 u32 vmx_instruction_info;
321 u32 guest_es_limit;
322 u32 guest_cs_limit;
323 u32 guest_ss_limit;
324 u32 guest_ds_limit;
325 u32 guest_fs_limit;
326 u32 guest_gs_limit;
327 u32 guest_ldtr_limit;
328 u32 guest_tr_limit;
329 u32 guest_gdtr_limit;
330 u32 guest_idtr_limit;
331 u32 guest_es_ar_bytes;
332 u32 guest_cs_ar_bytes;
333 u32 guest_ss_ar_bytes;
334 u32 guest_ds_ar_bytes;
335 u32 guest_fs_ar_bytes;
336 u32 guest_gs_ar_bytes;
337 u32 guest_ldtr_ar_bytes;
338 u32 guest_tr_ar_bytes;
339 u32 guest_interruptibility_info;
340 u32 guest_activity_state;
341 u32 guest_sysenter_cs;
342 u32 host_ia32_sysenter_cs;
0238ea91
JK		 343 u32 vmx_preemption_timer_value;
344 u32 padding32[7]; /* room for future expansion */
22bd0358 345 u16 virtual_processor_id;
705699a1 346 u16 posted_intr_nv;
22bd0358
NHE		 347 u16 guest_es_selector;
348 u16 guest_cs_selector;
349 u16 guest_ss_selector;
350 u16 guest_ds_selector;
351 u16 guest_fs_selector;
352 u16 guest_gs_selector;
353 u16 guest_ldtr_selector;
354 u16 guest_tr_selector;
608406e2 355 u16 guest_intr_status;
22bd0358
NHE		 356 u16 host_es_selector;
357 u16 host_cs_selector;
358 u16 host_ss_selector;
359 u16 host_ds_selector;
360 u16 host_fs_selector;
361 u16 host_gs_selector;
362 u16 host_tr_selector;
a9d30f33
NHE		 363};
364
365/*
366 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
367 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
368 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
369 */
370#define VMCS12_REVISION 0x11e57ed0
371
372/*
373 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
374 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
375 * current implementation, 4K are reserved to avoid future complications.
376 */
377#define VMCS12_SIZE 0x1000
378
ff2f6fe9
NHE		 379/* Used to remember the last vmcs02 used for some recently used vmcs12s */
380struct vmcs02_list {
381 struct list_head list;
382 gpa_t vmptr;
383 struct loaded_vmcs vmcs02;
384};
385
ec378aee
NHE		 386/*
387 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
388 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
389 */
390struct nested_vmx {
391 /* Has the level1 guest done vmxon? */
392 bool vmxon;
3573e22c 393 gpa_t vmxon_ptr;
a9d30f33
NHE		 394
395 /* The guest-physical address of the current VMCS L1 keeps for L2 */
396 gpa_t current_vmptr;
397 /* The host-usable pointer to the above */
398 struct page *current_vmcs12_page;
399 struct vmcs12 *current_vmcs12;
8de48833 400 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 401 /*
402 * Indicates if the shadow vmcs must be updated with the
403 * data hold by vmcs12
404 */
405 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 406
407 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
408 struct list_head vmcs02_pool;
409 int vmcs02_num;
fe3ef05c 410 u64 vmcs01_tsc_offset;
644d711a
NHE		 411 /* L2 must run next, and mustn't decide to exit to L1. */
412 bool nested_run_pending;
fe3ef05c
NHE		 413 /*
414 * Guest pages referred to in vmcs02 with host-physical pointers, so
415 * we must keep them pinned while L2 runs.
416 */
417 struct page *apic_access_page;
a7c0b07d 418 struct page *virtual_apic_page;
705699a1
WV		 419 struct page *pi_desc_page;
420 struct pi_desc *pi_desc;
421 bool pi_pending;
422 u16 posted_intr_nv;
b3897a49 423 u64 msr_ia32_feature_control;
f4124500
JK		 424
425 struct hrtimer preemption_timer;
426 bool preemption_timer_expired;
2996fca0
JK		 427
428 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
429 u64 vmcs01_debugctl;
b9c237bb 430
5c614b35
WL		 431 u16 vpid02;
432 u16 last_vpid;
433
b9c237bb
WV		 434 u32 nested_vmx_procbased_ctls_low;
435 u32 nested_vmx_procbased_ctls_high;
436 u32 nested_vmx_true_procbased_ctls_low;
437 u32 nested_vmx_secondary_ctls_low;
438 u32 nested_vmx_secondary_ctls_high;
439 u32 nested_vmx_pinbased_ctls_low;
440 u32 nested_vmx_pinbased_ctls_high;
441 u32 nested_vmx_exit_ctls_low;
442 u32 nested_vmx_exit_ctls_high;
443 u32 nested_vmx_true_exit_ctls_low;
444 u32 nested_vmx_entry_ctls_low;
445 u32 nested_vmx_entry_ctls_high;
446 u32 nested_vmx_true_entry_ctls_low;
447 u32 nested_vmx_misc_low;
448 u32 nested_vmx_misc_high;
449 u32 nested_vmx_ept_caps;
99b83ac8 450 u32 nested_vmx_vpid_caps;
ec378aee
NHE		 451};
452
01e439be 453#define POSTED_INTR_ON 0
ebbfc765
FW		 454#define POSTED_INTR_SN 1
455
01e439be
YZ		 456/* Posted-Interrupt Descriptor */
457struct pi_desc {
458 u32 pir[8]; /* Posted interrupt requested */
6ef1522f
FW		 459 union {
460 struct {
461 /* bit 256 - Outstanding Notification */
462 u16 on : 1,
463 /* bit 257 - Suppress Notification */
464 sn : 1,
465 /* bit 271:258 - Reserved */
466 rsvd_1 : 14;
467 /* bit 279:272 - Notification Vector */
468 u8 nv;
469 /* bit 287:280 - Reserved */
470 u8 rsvd_2;
471 /* bit 319:288 - Notification Destination */
472 u32 ndst;
473 };
474 u64 control;
475 };
476 u32 rsvd[6];
01e439be
YZ		 477} __aligned(64);
478
a20ed54d
YZ		 479static bool pi_test_and_set_on(struct pi_desc *pi_desc)
480{
481 return test_and_set_bit(POSTED_INTR_ON,
482 (unsigned long *)&pi_desc->control);
483}
484
485static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
486{
487 return test_and_clear_bit(POSTED_INTR_ON,
488 (unsigned long *)&pi_desc->control);
489}
490
491static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
492{
493 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
494}
495
ebbfc765
FW		 496static inline void pi_clear_sn(struct pi_desc *pi_desc)
497{
498 return clear_bit(POSTED_INTR_SN,
499 (unsigned long *)&pi_desc->control);
500}
501
502static inline void pi_set_sn(struct pi_desc *pi_desc)
503{
504 return set_bit(POSTED_INTR_SN,
505 (unsigned long *)&pi_desc->control);
506}
507
508static inline int pi_test_on(struct pi_desc *pi_desc)
509{
510 return test_bit(POSTED_INTR_ON,
511 (unsigned long *)&pi_desc->control);
512}
513
514static inline int pi_test_sn(struct pi_desc *pi_desc)
515{
516 return test_bit(POSTED_INTR_SN,
517 (unsigned long *)&pi_desc->control);
518}
519
a2fa3e9f 520struct vcpu_vmx {
fb3f0f51 521 struct kvm_vcpu vcpu;
313dbd49 522 unsigned long host_rsp;
29bd8a78 523 u8 fail;
9d58b931 524 bool nmi_known_unmasked;
51aa01d1 525 u32 exit_intr_info;
1155f76a 526 u32 idt_vectoring_info;
6de12732 527 ulong rflags;
26bb0981 528 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 529 int nmsrs;
530 int save_nmsrs;
a547c6db 531 unsigned long host_idt_base;
a2fa3e9f 532#ifdef CONFIG_X86_64
44ea2b17
AK		 533 u64 msr_host_kernel_gs_base;
534 u64 msr_guest_kernel_gs_base;
a2fa3e9f 535#endif
2961e876
GN		 536 u32 vm_entry_controls_shadow;
537 u32 vm_exit_controls_shadow;
d462b819
NHE		 538 /*
539 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
540 * non-nested (L1) guest, it always points to vmcs01. For a nested
541 * guest (L2), it points to a different VMCS.
542 */
543 struct loaded_vmcs vmcs01;
544 struct loaded_vmcs *loaded_vmcs;
545 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 546 struct msr_autoload {
547 unsigned nr;
548 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
549 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
550 } msr_autoload;
a2fa3e9f
GH		 551 struct {
552 int loaded;
553 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 554#ifdef CONFIG_X86_64
555 u16 ds_sel, es_sel;
556#endif
152d3f2f
LV		 557 int gs_ldt_reload_needed;
558 int fs_reload_needed;
da8999d3 559 u64 msr_host_bndcfgs;
d974baa3 560 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 561 } host_state;
9c8cba37 562 struct {
7ffd92c5 563 int vm86_active;
78ac8b47 564 ulong save_rflags;
f5f7b2fe
AK		 565 struct kvm_segment segs[8];
566 } rmode;
567 struct {
568 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 569 struct kvm_save_segment {
570 u16 selector;
571 unsigned long base;
572 u32 limit;
573 u32 ar;
f5f7b2fe 574 } seg[8];
2fb92db1 575 } segment_cache;
2384d2b3 576 int vpid;
04fa4d32 577 bool emulation_required;
3b86cd99
JK		 578
579 /* Support for vnmi-less CPUs */
580 int soft_vnmi_blocked;
581 ktime_t entry_time;
582 s64 vnmi_blocked_time;
a0861c02 583 u32 exit_reason;
4e47c7a6 584
01e439be
YZ		 585 /* Posted interrupt descriptor */
586 struct pi_desc pi_desc;
587
ec378aee
NHE		 588 /* Support for a guest hypervisor (nested VMX) */
589 struct nested_vmx nested;
a7653ecd
RK		 590
591 /* Dynamic PLE window. */
592 int ple_window;
593 bool ple_window_dirty;
843e4330
KH		 594
595 /* Support for PML */
596#define PML_ENTITY_NUM 512
597 struct page *pml_pg;
a2fa3e9f
GH		 598};
599
2fb92db1
AK		 600enum segment_cache_field {
601 SEG_FIELD_SEL = 0,
602 SEG_FIELD_BASE = 1,
603 SEG_FIELD_LIMIT = 2,
604 SEG_FIELD_AR = 3,
605
606 SEG_FIELD_NR = 4
607};
608
a2fa3e9f
GH		 609static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
610{
fb3f0f51 611 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 612}
613
efc64404
FW		 614static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
615{
616 return &(to_vmx(vcpu)->pi_desc);
617}
618
22bd0358
NHE		 619#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
620#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
621#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
622 [number##_HIGH] = VMCS12_OFFSET(name)+4
623
4607c2d7 624
fe2b201b 625static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 626 /*
627 * We do NOT shadow fields that are modified when L0
628 * traps and emulates any vmx instruction (e.g. VMPTRLD,
629 * VMXON...) executed by L1.
630 * For example, VM_INSTRUCTION_ERROR is read
631 * by L1 if a vmx instruction fails (part of the error path).
632 * Note the code assumes this logic. If for some reason
633 * we start shadowing these fields then we need to
634 * force a shadow sync when L0 emulates vmx instructions
635 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
636 * by nested_vmx_failValid)
637 */
638 VM_EXIT_REASON,
639 VM_EXIT_INTR_INFO,
640 VM_EXIT_INSTRUCTION_LEN,
641 IDT_VECTORING_INFO_FIELD,
642 IDT_VECTORING_ERROR_CODE,
643 VM_EXIT_INTR_ERROR_CODE,
644 EXIT_QUALIFICATION,
645 GUEST_LINEAR_ADDRESS,
646 GUEST_PHYSICAL_ADDRESS
647};
fe2b201b 648static int max_shadow_read_only_fields =
4607c2d7
AG		 649 ARRAY_SIZE(shadow_read_only_fields);
650
fe2b201b 651static unsigned long shadow_read_write_fields[] = {
a7c0b07d 652 TPR_THRESHOLD,
4607c2d7
AG		 653 GUEST_RIP,
654 GUEST_RSP,
655 GUEST_CR0,
656 GUEST_CR3,
657 GUEST_CR4,
658 GUEST_INTERRUPTIBILITY_INFO,
659 GUEST_RFLAGS,
660 GUEST_CS_SELECTOR,
661 GUEST_CS_AR_BYTES,
662 GUEST_CS_LIMIT,
663 GUEST_CS_BASE,
664 GUEST_ES_BASE,
36be0b9d 665 GUEST_BNDCFGS,
4607c2d7
AG		 666 CR0_GUEST_HOST_MASK,
667 CR0_READ_SHADOW,
668 CR4_READ_SHADOW,
669 TSC_OFFSET,
670 EXCEPTION_BITMAP,
671 CPU_BASED_VM_EXEC_CONTROL,
672 VM_ENTRY_EXCEPTION_ERROR_CODE,
673 VM_ENTRY_INTR_INFO_FIELD,
674 VM_ENTRY_INSTRUCTION_LEN,
675 VM_ENTRY_EXCEPTION_ERROR_CODE,
676 HOST_FS_BASE,
677 HOST_GS_BASE,
678 HOST_FS_SELECTOR,
679 HOST_GS_SELECTOR
680};
fe2b201b 681static int max_shadow_read_write_fields =
4607c2d7
AG		 682 ARRAY_SIZE(shadow_read_write_fields);
683
772e0318 684static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 685 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 686 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE		 687 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
688 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
689 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
690 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
691 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
692 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
693 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
694 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 695 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 696 FIELD(HOST_ES_SELECTOR, host_es_selector),
697 FIELD(HOST_CS_SELECTOR, host_cs_selector),
698 FIELD(HOST_SS_SELECTOR, host_ss_selector),
699 FIELD(HOST_DS_SELECTOR, host_ds_selector),
700 FIELD(HOST_FS_SELECTOR, host_fs_selector),
701 FIELD(HOST_GS_SELECTOR, host_gs_selector),
702 FIELD(HOST_TR_SELECTOR, host_tr_selector),
703 FIELD64(IO_BITMAP_A, io_bitmap_a),
704 FIELD64(IO_BITMAP_B, io_bitmap_b),
705 FIELD64(MSR_BITMAP, msr_bitmap),
706 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
707 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
708 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
709 FIELD64(TSC_OFFSET, tsc_offset),
710 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
711 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 712 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 713 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 714 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
715 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
716 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
717 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 718 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 719 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
720 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
721 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
722 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
723 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
724 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
725 FIELD64(GUEST_PDPTR0, guest_pdptr0),
726 FIELD64(GUEST_PDPTR1, guest_pdptr1),
727 FIELD64(GUEST_PDPTR2, guest_pdptr2),
728 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 729 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 730 FIELD64(HOST_IA32_PAT, host_ia32_pat),
731 FIELD64(HOST_IA32_EFER, host_ia32_efer),
732 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
733 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
734 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
735 FIELD(EXCEPTION_BITMAP, exception_bitmap),
736 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
737 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
738 FIELD(CR3_TARGET_COUNT, cr3_target_count),
739 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
740 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
741 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
742 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
743 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
744 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
745 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
746 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
747 FIELD(TPR_THRESHOLD, tpr_threshold),
748 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
749 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
750 FIELD(VM_EXIT_REASON, vm_exit_reason),
751 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
752 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
753 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
754 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
755 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
756 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
757 FIELD(GUEST_ES_LIMIT, guest_es_limit),
758 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
759 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
760 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
761 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
762 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
763 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
764 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
765 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
766 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
767 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
768 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
769 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
770 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
771 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
772 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
773 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
774 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
775 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
776 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
777 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
778 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 779 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 780 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
781 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
782 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
783 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
784 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
785 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
786 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
787 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
788 FIELD(EXIT_QUALIFICATION, exit_qualification),
789 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
790 FIELD(GUEST_CR0, guest_cr0),
791 FIELD(GUEST_CR3, guest_cr3),
792 FIELD(GUEST_CR4, guest_cr4),
793 FIELD(GUEST_ES_BASE, guest_es_base),
794 FIELD(GUEST_CS_BASE, guest_cs_base),
795 FIELD(GUEST_SS_BASE, guest_ss_base),
796 FIELD(GUEST_DS_BASE, guest_ds_base),
797 FIELD(GUEST_FS_BASE, guest_fs_base),
798 FIELD(GUEST_GS_BASE, guest_gs_base),
799 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
800 FIELD(GUEST_TR_BASE, guest_tr_base),
801 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
802 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
803 FIELD(GUEST_DR7, guest_dr7),
804 FIELD(GUEST_RSP, guest_rsp),
805 FIELD(GUEST_RIP, guest_rip),
806 FIELD(GUEST_RFLAGS, guest_rflags),
807 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
808 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
809 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
810 FIELD(HOST_CR0, host_cr0),
811 FIELD(HOST_CR3, host_cr3),
812 FIELD(HOST_CR4, host_cr4),
813 FIELD(HOST_FS_BASE, host_fs_base),
814 FIELD(HOST_GS_BASE, host_gs_base),
815 FIELD(HOST_TR_BASE, host_tr_base),
816 FIELD(HOST_GDTR_BASE, host_gdtr_base),
817 FIELD(HOST_IDTR_BASE, host_idtr_base),
818 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
819 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
820 FIELD(HOST_RSP, host_rsp),
821 FIELD(HOST_RIP, host_rip),
822};
22bd0358
NHE		 823
824static inline short vmcs_field_to_offset(unsigned long field)
825{
a2ae9df7
PB		 826 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
827
828 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
829 vmcs_field_to_offset_table[field] == 0)
830 return -ENOENT;
831
22bd0358
NHE		 832 return vmcs_field_to_offset_table[field];
833}
834
a9d30f33
NHE		 835static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
836{
837 return to_vmx(vcpu)->nested.current_vmcs12;
838}
839
840static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
841{
54bf36aa 842 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 843 if (is_error_page(page))
a9d30f33 844 return NULL;
32cad84f 845
a9d30f33
NHE		 846 return page;
847}
848
849static void nested_release_page(struct page *page)
850{
851 kvm_release_page_dirty(page);
852}
853
854static void nested_release_page_clean(struct page *page)
855{
856 kvm_release_page_clean(page);
857}
858
bfd0a56b 859static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 860static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 861static void kvm_cpu_vmxon(u64 addr);
862static void kvm_cpu_vmxoff(void);
93c4adc7 863static bool vmx_mpx_supported(void);
f53cd63c 864static bool vmx_xsaves_supported(void);
d50ab6c1 865static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
776e58ea 866static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 867static void vmx_set_segment(struct kvm_vcpu *vcpu,
868 struct kvm_segment *var, int seg);
869static void vmx_get_segment(struct kvm_vcpu *vcpu,
870 struct kvm_segment *var, int seg);
d99e4152
GN		 871static bool guest_state_valid(struct kvm_vcpu *vcpu);
872static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 873static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 874static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 875static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 876static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 877
6aa8b732
AK		 878static DEFINE_PER_CPU(struct vmcs *, vmxarea);
879static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 880/*
881 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
882 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
883 */
884static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 885static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 886
bf9f6ac8
FW		 887/*
888 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
889 * can find which vCPU should be waken up.
890 */
891static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
892static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
893
3e7c73e9
AK		 894static unsigned long *vmx_io_bitmap_a;
895static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 896static unsigned long *vmx_msr_bitmap_legacy;
897static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 898static unsigned long *vmx_msr_bitmap_legacy_x2apic;
899static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 900static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 901static unsigned long *vmx_vmread_bitmap;
902static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 903
110312c8 904static bool cpu_has_load_ia32_efer;
8bf00a52 905static bool cpu_has_load_perf_global_ctrl;
110312c8 906
2384d2b3
SY		 907static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
908static DEFINE_SPINLOCK(vmx_vpid_lock);
909
1c3d14fe 910static struct vmcs_config {
6aa8b732
AK		 911 int size;
912 int order;
913 u32 revision_id;
1c3d14fe
YS		 914 u32 pin_based_exec_ctrl;
915 u32 cpu_based_exec_ctrl;
f78e0e2e 916 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 917 u32 vmexit_ctrl;
918 u32 vmentry_ctrl;
919} vmcs_config;
6aa8b732 920
efff9e53 921static struct vmx_capability {
d56f546d
SY		 922 u32 ept;
923 u32 vpid;
924} vmx_capability;
925
6aa8b732
AK		 926#define VMX_SEGMENT_FIELD(seg) \
927 [VCPU_SREG_##seg] = { \
928 .selector = GUEST_##seg##_SELECTOR, \
929 .base = GUEST_##seg##_BASE, \
930 .limit = GUEST_##seg##_LIMIT, \
931 .ar_bytes = GUEST_##seg##_AR_BYTES, \
932 }
933
772e0318 934static const struct kvm_vmx_segment_field {
6aa8b732
AK		 935 unsigned selector;
936 unsigned base;
937 unsigned limit;
938 unsigned ar_bytes;
939} kvm_vmx_segment_fields[] = {
940 VMX_SEGMENT_FIELD(CS),
941 VMX_SEGMENT_FIELD(DS),
942 VMX_SEGMENT_FIELD(ES),
943 VMX_SEGMENT_FIELD(FS),
944 VMX_SEGMENT_FIELD(GS),
945 VMX_SEGMENT_FIELD(SS),
946 VMX_SEGMENT_FIELD(TR),
947 VMX_SEGMENT_FIELD(LDTR),
948};
949
26bb0981
AK		 950static u64 host_efer;
951
6de4f3ad
AK		 952static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
953
4d56c8a7 954/*
8c06585d 955 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 956 * away by decrementing the array size.
957 */
6aa8b732 958static const u32 vmx_msr_index[] = {
05b3e0c2 959#ifdef CONFIG_X86_64
44ea2b17 960 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 961#endif
8c06585d 962 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 963};
6aa8b732 964
31299944 965static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 966{
967 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
968 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 969 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 970}
971
31299944 972static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 973{
974 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
975 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 976 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 977}
978
31299944 979static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 980{
981 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
982 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 983 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 984}
985
31299944 986static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 987{
988 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
989 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
990}
991
31299944 992static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 993{
994 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
995 INTR_INFO_VALID_MASK)) ==
996 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
997}
998
31299944 999static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 1000{
04547156 1001 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 1002}
1003
31299944 1004static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 1005{
04547156 1006 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 1007}
1008
35754c98 1009static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 1010{
35754c98 1011 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS		 1012}
1013
31299944 1014static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 1015{
04547156
SY		 1016 return vmcs_config.cpu_based_exec_ctrl &
1017 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 1018}
1019
774ead3a 1020static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 1021{
04547156
SY		 1022 return vmcs_config.cpu_based_2nd_exec_ctrl &
1023 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1024}
1025
8d14695f
YZ		 1026static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1027{
1028 return vmcs_config.cpu_based_2nd_exec_ctrl &
1029 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1030}
1031
83d4c286
YZ		 1032static inline bool cpu_has_vmx_apic_register_virt(void)
1033{
1034 return vmcs_config.cpu_based_2nd_exec_ctrl &
1035 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1036}
1037
c7c9c56c
YZ		 1038static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1039{
1040 return vmcs_config.cpu_based_2nd_exec_ctrl &
1041 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1042}
1043
01e439be
YZ		 1044static inline bool cpu_has_vmx_posted_intr(void)
1045{
d6a858d1
PB		 1046 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1047 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ		 1048}
1049
1050static inline bool cpu_has_vmx_apicv(void)
1051{
1052 return cpu_has_vmx_apic_register_virt() &&
1053 cpu_has_vmx_virtual_intr_delivery() &&
1054 cpu_has_vmx_posted_intr();
1055}
1056
04547156
SY		 1057static inline bool cpu_has_vmx_flexpriority(void)
1058{
1059 return cpu_has_vmx_tpr_shadow() &&
1060 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 1061}
1062
e799794e
MT		 1063static inline bool cpu_has_vmx_ept_execute_only(void)
1064{
31299944 1065 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 1066}
1067
e799794e
MT		 1068static inline bool cpu_has_vmx_ept_2m_page(void)
1069{
31299944 1070 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1071}
1072
878403b7
SY		 1073static inline bool cpu_has_vmx_ept_1g_page(void)
1074{
31299944 1075 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1076}
1077
4bc9b982
SY		 1078static inline bool cpu_has_vmx_ept_4levels(void)
1079{
1080 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1081}
1082
83c3a331
XH		 1083static inline bool cpu_has_vmx_ept_ad_bits(void)
1084{
1085 return vmx_capability.ept & VMX_EPT_AD_BIT;
1086}
1087
31299944 1088static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1089{
31299944 1090 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1091}
1092
31299944 1093static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1094{
31299944 1095 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1096}
1097
518c8aee
GJ		 1098static inline bool cpu_has_vmx_invvpid_single(void)
1099{
1100 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1101}
1102
b9d762fa
GJ		 1103static inline bool cpu_has_vmx_invvpid_global(void)
1104{
1105 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1106}
1107
31299944 1108static inline bool cpu_has_vmx_ept(void)
d56f546d 1109{
04547156
SY		 1110 return vmcs_config.cpu_based_2nd_exec_ctrl &
1111 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1112}
1113
31299944 1114static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1115{
1116 return vmcs_config.cpu_based_2nd_exec_ctrl &
1117 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1118}
1119
31299944 1120static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1121{
1122 return vmcs_config.cpu_based_2nd_exec_ctrl &
1123 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1124}
1125
35754c98 1126static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1127{
35754c98 1128 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 1129}
1130
31299944 1131static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1132{
04547156
SY		 1133 return vmcs_config.cpu_based_2nd_exec_ctrl &
1134 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1135}
1136
31299944 1137static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1138{
1139 return vmcs_config.cpu_based_2nd_exec_ctrl &
1140 SECONDARY_EXEC_RDTSCP;
1141}
1142
ad756a16
MJ		 1143static inline bool cpu_has_vmx_invpcid(void)
1144{
1145 return vmcs_config.cpu_based_2nd_exec_ctrl &
1146 SECONDARY_EXEC_ENABLE_INVPCID;
1147}
1148
31299944 1149static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1150{
1151 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1152}
1153
f5f48ee1
SY		 1154static inline bool cpu_has_vmx_wbinvd_exit(void)
1155{
1156 return vmcs_config.cpu_based_2nd_exec_ctrl &
1157 SECONDARY_EXEC_WBINVD_EXITING;
1158}
1159
abc4fc58
AG		 1160static inline bool cpu_has_vmx_shadow_vmcs(void)
1161{
1162 u64 vmx_msr;
1163 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1164 /* check if the cpu supports writing r/o exit information fields */
1165 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1166 return false;
1167
1168 return vmcs_config.cpu_based_2nd_exec_ctrl &
1169 SECONDARY_EXEC_SHADOW_VMCS;
1170}
1171
843e4330
KH		 1172static inline bool cpu_has_vmx_pml(void)
1173{
1174 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1175}
1176
64903d61
HZ		 1177static inline bool cpu_has_vmx_tsc_scaling(void)
1178{
1179 return vmcs_config.cpu_based_2nd_exec_ctrl &
1180 SECONDARY_EXEC_TSC_SCALING;
1181}
1182
04547156
SY		 1183static inline bool report_flexpriority(void)
1184{
1185 return flexpriority_enabled;
1186}
1187
fe3ef05c
NHE		 1188static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1189{
1190 return vmcs12->cpu_based_vm_exec_control & bit;
1191}
1192
1193static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1194{
1195 return (vmcs12->cpu_based_vm_exec_control &
1196 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1197 (vmcs12->secondary_vm_exec_control & bit);
1198}
1199
f5c4368f 1200static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1201{
1202 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1203}
1204
f4124500
JK		 1205static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1206{
1207 return vmcs12->pin_based_vm_exec_control &
1208 PIN_BASED_VMX_PREEMPTION_TIMER;
1209}
1210
155a97a3
NHE		 1211static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1212{
1213 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1214}
1215
81dc01f7
WL		 1216static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1217{
1218 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1219 vmx_xsaves_supported();
1220}
1221
f2b93280
WV		 1222static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1223{
1224 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1225}
1226
5c614b35
WL		 1227static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1228{
1229 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1230}
1231
82f0dd4b
WV		 1232static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1233{
1234 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1235}
1236
608406e2
WV		 1237static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1238{
1239 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1240}
1241
705699a1
WV		 1242static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1243{
1244 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1245}
1246
644d711a
NHE		 1247static inline bool is_exception(u32 intr_info)
1248{
1249 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1250 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1251}
1252
533558bc
JK		 1253static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1254 u32 exit_intr_info,
1255 unsigned long exit_qualification);
7c177938
NHE		 1256static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1257 struct vmcs12 *vmcs12,
1258 u32 reason, unsigned long qualification);
1259
8b9cf98c 1260static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1261{
1262 int i;
1263
a2fa3e9f 1264 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1265 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1266 return i;
1267 return -1;
1268}
1269
2384d2b3
SY		 1270static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1271{
1272 struct {
1273 u64 vpid : 16;
1274 u64 rsvd : 48;
1275 u64 gva;
1276 } operand = { vpid, 0, gva };
1277
4ecac3fd 1278 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1279 /* CF==1 or ZF==1 --> rc = -1 */
1280 "; ja 1f ; ud2 ; 1:"
1281 : : "a"(&operand), "c"(ext) : "cc", "memory");
1282}
1283
1439442c
SY		 1284static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1285{
1286 struct {
1287 u64 eptp, gpa;
1288 } operand = {eptp, gpa};
1289
4ecac3fd 1290 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1291 /* CF==1 or ZF==1 --> rc = -1 */
1292 "; ja 1f ; ud2 ; 1:\n"
1293 : : "a" (&operand), "c" (ext) : "cc", "memory");
1294}
1295
26bb0981 1296static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1297{
1298 int i;
1299
8b9cf98c 1300 i = __find_msr_index(vmx, msr);
a75beee6 1301 if (i >= 0)
a2fa3e9f 1302 return &vmx->guest_msrs[i];
8b6d44c7 1303 return NULL;
7725f0ba
AK		 1304}
1305
6aa8b732
AK		 1306static void vmcs_clear(struct vmcs *vmcs)
1307{
1308 u64 phys_addr = __pa(vmcs);
1309 u8 error;
1310
4ecac3fd 1311 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1312 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1313 : "cc", "memory");
1314 if (error)
1315 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1316 vmcs, phys_addr);
1317}
1318
d462b819
NHE		 1319static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1320{
1321 vmcs_clear(loaded_vmcs->vmcs);
1322 loaded_vmcs->cpu = -1;
1323 loaded_vmcs->launched = 0;
1324}
1325
7725b894
DX		 1326static void vmcs_load(struct vmcs *vmcs)
1327{
1328 u64 phys_addr = __pa(vmcs);
1329 u8 error;
1330
1331 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1332 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1333 : "cc", "memory");
1334 if (error)
2844d849 1335 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1336 vmcs, phys_addr);
1337}
1338
2965faa5 1339#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 1340/*
1341 * This bitmap is used to indicate whether the vmclear
1342 * operation is enabled on all cpus. All disabled by
1343 * default.
1344 */
1345static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1346
1347static inline void crash_enable_local_vmclear(int cpu)
1348{
1349 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1350}
1351
1352static inline void crash_disable_local_vmclear(int cpu)
1353{
1354 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1355}
1356
1357static inline int crash_local_vmclear_enabled(int cpu)
1358{
1359 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1360}
1361
1362static void crash_vmclear_local_loaded_vmcss(void)
1363{
1364 int cpu = raw_smp_processor_id();
1365 struct loaded_vmcs *v;
1366
1367 if (!crash_local_vmclear_enabled(cpu))
1368 return;
1369
1370 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1371 loaded_vmcss_on_cpu_link)
1372 vmcs_clear(v->vmcs);
1373}
1374#else
1375static inline void crash_enable_local_vmclear(int cpu) { }
1376static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1377#endif /* CONFIG_KEXEC_CORE */
8f536b76 1378
d462b819 1379static void __loaded_vmcs_clear(void *arg)
6aa8b732 1380{
d462b819 1381 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1382 int cpu = raw_smp_processor_id();
6aa8b732 1383
d462b819
NHE		 1384 if (loaded_vmcs->cpu != cpu)
1385 return; /* vcpu migration can race with cpu offline */
1386 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1387 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1388 crash_disable_local_vmclear(cpu);
d462b819 1389 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1390
1391 /*
1392 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1393 * is before setting loaded_vmcs->vcpu to -1 which is done in
1394 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1395 * then adds the vmcs into percpu list before it is deleted.
1396 */
1397 smp_wmb();
1398
d462b819 1399 loaded_vmcs_init(loaded_vmcs);
8f536b76 1400 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1401}
1402
d462b819 1403static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1404{
e6c7d321
XG		 1405 int cpu = loaded_vmcs->cpu;
1406
1407 if (cpu != -1)
1408 smp_call_function_single(cpu,
1409 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1410}
1411
dd5f5341 1412static inline void vpid_sync_vcpu_single(int vpid)
2384d2b3 1413{
dd5f5341 1414 if (vpid == 0)
2384d2b3
SY		 1415 return;
1416
518c8aee 1417 if (cpu_has_vmx_invvpid_single())
dd5f5341 1418 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
2384d2b3
SY		 1419}
1420
b9d762fa
GJ		 1421static inline void vpid_sync_vcpu_global(void)
1422{
1423 if (cpu_has_vmx_invvpid_global())
1424 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1425}
1426
dd5f5341 1427static inline void vpid_sync_context(int vpid)
b9d762fa
GJ		 1428{
1429 if (cpu_has_vmx_invvpid_single())
dd5f5341 1430 vpid_sync_vcpu_single(vpid);
b9d762fa
GJ		 1431 else
1432 vpid_sync_vcpu_global();
1433}
1434
1439442c
SY		 1435static inline void ept_sync_global(void)
1436{
1437 if (cpu_has_vmx_invept_global())
1438 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1439}
1440
1441static inline void ept_sync_context(u64 eptp)
1442{
089d034e 1443 if (enable_ept) {
1439442c
SY		 1444 if (cpu_has_vmx_invept_context())
1445 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1446 else
1447 ept_sync_global();
1448 }
1449}
1450
96304217 1451static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1452{
5e520e62 1453 unsigned long value;
6aa8b732 1454
5e520e62
AK		 1455 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1456 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1457 return value;
1458}
1459
96304217 1460static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1461{
1462 return vmcs_readl(field);
1463}
1464
96304217 1465static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1466{
1467 return vmcs_readl(field);
1468}
1469
96304217 1470static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1471{
05b3e0c2 1472#ifdef CONFIG_X86_64
6aa8b732
AK		 1473 return vmcs_readl(field);
1474#else
1475 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1476#endif
1477}
1478
e52de1b8
AK		 1479static noinline void vmwrite_error(unsigned long field, unsigned long value)
1480{
1481 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1482 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1483 dump_stack();
1484}
1485
6aa8b732
AK		 1486static void vmcs_writel(unsigned long field, unsigned long value)
1487{
1488 u8 error;
1489
4ecac3fd 1490 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1491 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1492 if (unlikely(error))
1493 vmwrite_error(field, value);
6aa8b732
AK		 1494}
1495
1496static void vmcs_write16(unsigned long field, u16 value)
1497{
1498 vmcs_writel(field, value);
1499}
1500
1501static void vmcs_write32(unsigned long field, u32 value)
1502{
1503 vmcs_writel(field, value);
1504}
1505
1506static void vmcs_write64(unsigned long field, u64 value)
1507{
6aa8b732 1508 vmcs_writel(field, value);
7682f2d0 1509#ifndef CONFIG_X86_64
6aa8b732
AK		 1510 asm volatile ("");
1511 vmcs_writel(field+1, value >> 32);
1512#endif
1513}
1514
2ab455cc
AL		 1515static void vmcs_clear_bits(unsigned long field, u32 mask)
1516{
1517 vmcs_writel(field, vmcs_readl(field) & ~mask);
1518}
1519
1520static void vmcs_set_bits(unsigned long field, u32 mask)
1521{
1522 vmcs_writel(field, vmcs_readl(field) | mask);
1523}
1524
2961e876
GN		 1525static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1526{
1527 vmcs_write32(VM_ENTRY_CONTROLS, val);
1528 vmx->vm_entry_controls_shadow = val;
1529}
1530
1531static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1532{
1533 if (vmx->vm_entry_controls_shadow != val)
1534 vm_entry_controls_init(vmx, val);
1535}
1536
1537static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1538{
1539 return vmx->vm_entry_controls_shadow;
1540}
1541
1542
1543static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1544{
1545 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1546}
1547
1548static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1549{
1550 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1551}
1552
1553static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1554{
1555 vmcs_write32(VM_EXIT_CONTROLS, val);
1556 vmx->vm_exit_controls_shadow = val;
1557}
1558
1559static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1560{
1561 if (vmx->vm_exit_controls_shadow != val)
1562 vm_exit_controls_init(vmx, val);
1563}
1564
1565static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1566{
1567 return vmx->vm_exit_controls_shadow;
1568}
1569
1570
1571static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1572{
1573 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1574}
1575
1576static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1577{
1578 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1579}
1580
2fb92db1
AK		 1581static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1582{
1583 vmx->segment_cache.bitmask = 0;
1584}
1585
1586static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1587 unsigned field)
1588{
1589 bool ret;
1590 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1591
1592 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1593 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1594 vmx->segment_cache.bitmask = 0;
1595 }
1596 ret = vmx->segment_cache.bitmask & mask;
1597 vmx->segment_cache.bitmask |= mask;
1598 return ret;
1599}
1600
1601static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1602{
1603 u16 *p = &vmx->segment_cache.seg[seg].selector;
1604
1605 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1606 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1607 return *p;
1608}
1609
1610static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1611{
1612 ulong *p = &vmx->segment_cache.seg[seg].base;
1613
1614 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1615 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1616 return *p;
1617}
1618
1619static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1620{
1621 u32 *p = &vmx->segment_cache.seg[seg].limit;
1622
1623 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1624 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1625 return *p;
1626}
1627
1628static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1629{
1630 u32 *p = &vmx->segment_cache.seg[seg].ar;
1631
1632 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1633 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1634 return *p;
1635}
1636
abd3f2d6
AK		 1637static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1638{
1639 u32 eb;
1640
fd7373cc
JK		 1641 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1642 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1643 if ((vcpu->guest_debug &
1644 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1645 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1646 eb |= 1u << BP_VECTOR;
7ffd92c5 1647 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1648 eb = ~0;
089d034e 1649 if (enable_ept)
1439442c 1650 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1651 if (vcpu->fpu_active)
1652 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1653
1654 /* When we are running a nested L2 guest and L1 specified for it a
1655 * certain exception bitmap, we must trap the same exceptions and pass
1656 * them to L1. When running L2, we will only handle the exceptions
1657 * specified above if L1 did not want them.
1658 */
1659 if (is_guest_mode(vcpu))
1660 eb |= get_vmcs12(vcpu)->exception_bitmap;
1661
abd3f2d6
AK		 1662 vmcs_write32(EXCEPTION_BITMAP, eb);
1663}
1664
2961e876
GN		 1665static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1666 unsigned long entry, unsigned long exit)
8bf00a52 1667{
2961e876
GN		 1668 vm_entry_controls_clearbit(vmx, entry);
1669 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1670}
1671
61d2ef2c
AK		 1672static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1673{
1674 unsigned i;
1675 struct msr_autoload *m = &vmx->msr_autoload;
1676
8bf00a52
GN		 1677 switch (msr) {
1678 case MSR_EFER:
1679 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1680 clear_atomic_switch_msr_special(vmx,
1681 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1682 VM_EXIT_LOAD_IA32_EFER);
1683 return;
1684 }
1685 break;
1686 case MSR_CORE_PERF_GLOBAL_CTRL:
1687 if (cpu_has_load_perf_global_ctrl) {
2961e876 1688 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1689 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1690 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1691 return;
1692 }
1693 break;
110312c8
AK		 1694 }
1695
61d2ef2c
AK		 1696 for (i = 0; i < m->nr; ++i)
1697 if (m->guest[i].index == msr)
1698 break;
1699
1700 if (i == m->nr)
1701 return;
1702 --m->nr;
1703 m->guest[i] = m->guest[m->nr];
1704 m->host[i] = m->host[m->nr];
1705 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1706 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1707}
1708
2961e876
GN		 1709static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1710 unsigned long entry, unsigned long exit,
1711 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1712 u64 guest_val, u64 host_val)
8bf00a52
GN		 1713{
1714 vmcs_write64(guest_val_vmcs, guest_val);
1715 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1716 vm_entry_controls_setbit(vmx, entry);
1717 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1718}
1719
61d2ef2c
AK		 1720static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1721 u64 guest_val, u64 host_val)
1722{
1723 unsigned i;
1724 struct msr_autoload *m = &vmx->msr_autoload;
1725
8bf00a52
GN		 1726 switch (msr) {
1727 case MSR_EFER:
1728 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1729 add_atomic_switch_msr_special(vmx,
1730 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1731 VM_EXIT_LOAD_IA32_EFER,
1732 GUEST_IA32_EFER,
1733 HOST_IA32_EFER,
1734 guest_val, host_val);
1735 return;
1736 }
1737 break;
1738 case MSR_CORE_PERF_GLOBAL_CTRL:
1739 if (cpu_has_load_perf_global_ctrl) {
2961e876 1740 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1741 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1742 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1743 GUEST_IA32_PERF_GLOBAL_CTRL,
1744 HOST_IA32_PERF_GLOBAL_CTRL,
1745 guest_val, host_val);
1746 return;
1747 }
1748 break;
110312c8
AK		 1749 }
1750
61d2ef2c
AK		 1751 for (i = 0; i < m->nr; ++i)
1752 if (m->guest[i].index == msr)
1753 break;
1754
e7fc6f93 1755 if (i == NR_AUTOLOAD_MSRS) {
60266204 1756 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1757 "Can't add msr %x\n", msr);
1758 return;
1759 } else if (i == m->nr) {
61d2ef2c
AK		 1760 ++m->nr;
1761 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1762 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1763 }
1764
1765 m->guest[i].index = msr;
1766 m->guest[i].value = guest_val;
1767 m->host[i].index = msr;
1768 m->host[i].value = host_val;
1769}
1770
33ed6329
AK		 1771static void reload_tss(void)
1772{
33ed6329
AK		 1773 /*
1774 * VT restores TR but not its size. Useless.
1775 */
89cbc767 1776 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1777 struct desc_struct *descs;
33ed6329 1778
d359192f 1779 descs = (void *)gdt->address;
33ed6329
AK		 1780 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1781 load_TR_desc();
33ed6329
AK		 1782}
1783
92c0d900 1784static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1785{
3a34a881 1786 u64 guest_efer;
51c6cf66
AK		 1787 u64 ignore_bits;
1788
f6801dff 1789 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1790
51c6cf66 1791 /*
0fa06071 1792 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1793 * outside long mode
1794 */
1795 ignore_bits = EFER_NX | EFER_SCE;
1796#ifdef CONFIG_X86_64
1797 ignore_bits |= EFER_LMA | EFER_LME;
1798 /* SCE is meaningful only in long mode on Intel */
1799 if (guest_efer & EFER_LMA)
1800 ignore_bits &= ~(u64)EFER_SCE;
1801#endif
51c6cf66
AK		 1802 guest_efer &= ~ignore_bits;
1803 guest_efer |= host_efer & ignore_bits;
26bb0981 1804 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1805 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1806
1807 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1808
1809 /*
1810 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1811 * On CPUs that support "load IA32_EFER", always switch EFER
1812 * atomically, since it's faster than switching it manually.
1813 */
1814 if (cpu_has_load_ia32_efer ||
1815 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1816 guest_efer = vmx->vcpu.arch.efer;
1817 if (!(guest_efer & EFER_LMA))
1818 guest_efer &= ~EFER_LME;
54b98bff
AL		 1819 if (guest_efer != host_efer)
1820 add_atomic_switch_msr(vmx, MSR_EFER,
1821 guest_efer, host_efer);
84ad33ef
AK		 1822 return false;
1823 }
1824
26bb0981 1825 return true;
51c6cf66
AK		 1826}
1827
2d49ec72
GN		 1828static unsigned long segment_base(u16 selector)
1829{
89cbc767 1830 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1831 struct desc_struct *d;
1832 unsigned long table_base;
1833 unsigned long v;
1834
1835 if (!(selector & ~3))
1836 return 0;
1837
d359192f 1838 table_base = gdt->address;
2d49ec72
GN		 1839
1840 if (selector & 4) { /* from ldt */
1841 u16 ldt_selector = kvm_read_ldt();
1842
1843 if (!(ldt_selector & ~3))
1844 return 0;
1845
1846 table_base = segment_base(ldt_selector);
1847 }
1848 d = (struct desc_struct *)(table_base + (selector & ~7));
1849 v = get_desc_base(d);
1850#ifdef CONFIG_X86_64
1851 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1852 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1853#endif
1854 return v;
1855}
1856
1857static inline unsigned long kvm_read_tr_base(void)
1858{
1859 u16 tr;
1860 asm("str %0" : "=g"(tr));
1861 return segment_base(tr);
1862}
1863
04d2cc77 1864static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1865{
04d2cc77 1866 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1867 int i;
04d2cc77 1868
a2fa3e9f 1869 if (vmx->host_state.loaded)
33ed6329
AK		 1870 return;
1871
a2fa3e9f 1872 vmx->host_state.loaded = 1;
33ed6329
AK		 1873 /*
1874 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1875 * allow segment selectors with cpl > 0 or ti == 1.
1876 */
d6e88aec 1877 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1878 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1879 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1880 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1881 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1882 vmx->host_state.fs_reload_needed = 0;
1883 } else {
33ed6329 1884 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1885 vmx->host_state.fs_reload_needed = 1;
33ed6329 1886 }
9581d442 1887 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1888 if (!(vmx->host_state.gs_sel & 7))
1889 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1890 else {
1891 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1892 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1893 }
1894
b2da15ac
AK		 1895#ifdef CONFIG_X86_64
1896 savesegment(ds, vmx->host_state.ds_sel);
1897 savesegment(es, vmx->host_state.es_sel);
1898#endif
1899
33ed6329
AK		 1900#ifdef CONFIG_X86_64
1901 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1902 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1903#else
a2fa3e9f
GH		 1904 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1905 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1906#endif
707c0874
AK		 1907
1908#ifdef CONFIG_X86_64
c8770e7b
AK		 1909 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1910 if (is_long_mode(&vmx->vcpu))
44ea2b17 1911 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1912#endif
da8999d3
LJ		 1913 if (boot_cpu_has(X86_FEATURE_MPX))
1914 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1915 for (i = 0; i < vmx->save_nmsrs; ++i)
1916 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1917 vmx->guest_msrs[i].data,
1918 vmx->guest_msrs[i].mask);
33ed6329
AK		 1919}
1920
a9b21b62 1921static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1922{
a2fa3e9f 1923 if (!vmx->host_state.loaded)
33ed6329
AK		 1924 return;
1925
e1beb1d3 1926 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1927 vmx->host_state.loaded = 0;
c8770e7b
AK		 1928#ifdef CONFIG_X86_64
1929 if (is_long_mode(&vmx->vcpu))
1930 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1931#endif
152d3f2f 1932 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1933 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1934#ifdef CONFIG_X86_64
9581d442 1935 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1936#else
1937 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1938#endif
33ed6329 1939 }
0a77fe4c
AK		 1940 if (vmx->host_state.fs_reload_needed)
1941 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1942#ifdef CONFIG_X86_64
1943 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1944 loadsegment(ds, vmx->host_state.ds_sel);
1945 loadsegment(es, vmx->host_state.es_sel);
1946 }
b2da15ac 1947#endif
152d3f2f 1948 reload_tss();
44ea2b17 1949#ifdef CONFIG_X86_64
c8770e7b 1950 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1951#endif
da8999d3
LJ		 1952 if (vmx->host_state.msr_host_bndcfgs)
1953 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1954 /*
1955 * If the FPU is not active (through the host task or
1956 * the guest vcpu), then restore the cr0.TS bit.
1957 */
3c6dffa9 1958 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
b1a74bf8 1959 stts();
89cbc767 1960 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1961}
1962
a9b21b62
AK		 1963static void vmx_load_host_state(struct vcpu_vmx *vmx)
1964{
1965 preempt_disable();
1966 __vmx_load_host_state(vmx);
1967 preempt_enable();
1968}
1969
28b835d6
FW		 1970static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1971{
1972 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1973 struct pi_desc old, new;
1974 unsigned int dest;
1975
1976 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1977 !irq_remapping_cap(IRQ_POSTING_CAP))
1978 return;
1979
1980 do {
1981 old.control = new.control = pi_desc->control;
1982
1983 /*
1984 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
1985 * are two possible cases:
1986 * 1. After running 'pre_block', context switch
1987 * happened. For this case, 'sn' was set in
1988 * vmx_vcpu_put(), so we need to clear it here.
1989 * 2. After running 'pre_block', we were blocked,
1990 * and woken up by some other guy. For this case,
1991 * we don't need to do anything, 'pi_post_block'
1992 * will do everything for us. However, we cannot
1993 * check whether it is case #1 or case #2 here
1994 * (maybe, not needed), so we also clear sn here,
1995 * I think it is not a big deal.
1996 */
1997 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
1998 if (vcpu->cpu != cpu) {
1999 dest = cpu_physical_id(cpu);
2000
2001 if (x2apic_enabled())
2002 new.ndst = dest;
2003 else
2004 new.ndst = (dest << 8) & 0xFF00;
2005 }
2006
2007 /* set 'NV' to 'notification vector' */
2008 new.nv = POSTED_INTR_VECTOR;
2009 }
2010
2011 /* Allow posting non-urgent interrupts */
2012 new.sn = 0;
2013 } while (cmpxchg(&pi_desc->control, old.control,
2014 new.control) != old.control);
2015}
6aa8b732
AK		 2016/*
2017 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2018 * vcpu mutex is already taken.
2019 */
15ad7146 2020static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 2021{
a2fa3e9f 2022 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 2023 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 2024
4610c9cc
DX		 2025 if (!vmm_exclusive)
2026 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 2027 else if (vmx->loaded_vmcs->cpu != cpu)
2028 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 2029
d462b819
NHE		 2030 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2031 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2032 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 2033 }
2034
d462b819 2035 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 2036 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 2037 unsigned long sysenter_esp;
2038
a8eeb04a 2039 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 2040 local_irq_disable();
8f536b76 2041 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 2042
2043 /*
2044 * Read loaded_vmcs->cpu should be before fetching
2045 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2046 * See the comments in __loaded_vmcs_clear().
2047 */
2048 smp_rmb();
2049
d462b819
NHE		 2050 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2051 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 2052 crash_enable_local_vmclear(cpu);
92fe13be
DX		 2053 local_irq_enable();
2054
6aa8b732
AK		 2055 /*
2056 * Linux uses per-cpu TSS and GDT, so set these when switching
2057 * processors.
2058 */
d6e88aec 2059 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 2060 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 2061
2062 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2063 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18
HZ		 2064
2065 /* Setup TSC multiplier */
2066 if (cpu_has_vmx_tsc_scaling())
2067 vmcs_write64(TSC_MULTIPLIER,
2068 vcpu->arch.tsc_scaling_ratio);
2069
d462b819 2070 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 2071 }
28b835d6
FW		 2072
2073 vmx_vcpu_pi_load(vcpu, cpu);
2074}
2075
2076static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2077{
2078 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2079
2080 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2081 !irq_remapping_cap(IRQ_POSTING_CAP))
2082 return;
2083
2084 /* Set SN when the vCPU is preempted */
2085 if (vcpu->preempted)
2086 pi_set_sn(pi_desc);
6aa8b732
AK		 2087}
2088
2089static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2090{
28b835d6
FW		 2091 vmx_vcpu_pi_put(vcpu);
2092
a9b21b62 2093 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 2094 if (!vmm_exclusive) {
d462b819
NHE		 2095 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2096 vcpu->cpu = -1;
4610c9cc
DX		 2097 kvm_cpu_vmxoff();
2098 }
6aa8b732
AK		 2099}
2100
5fd86fcf
AK		 2101static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2102{
81231c69
AK		 2103 ulong cr0;
2104
5fd86fcf
AK		 2105 if (vcpu->fpu_active)
2106 return;
2107 vcpu->fpu_active = 1;
81231c69
AK		 2108 cr0 = vmcs_readl(GUEST_CR0);
2109 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2110 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2111 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 2112 update_exception_bitmap(vcpu);
edcafe3c 2113 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 2114 if (is_guest_mode(vcpu))
2115 vcpu->arch.cr0_guest_owned_bits &=
2116 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 2117 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 2118}
2119
edcafe3c
AK		 2120static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2121
fe3ef05c
NHE		 2122/*
2123 * Return the cr0 value that a nested guest would read. This is a combination
2124 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2125 * its hypervisor (cr0_read_shadow).
2126 */
2127static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2128{
2129 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2130 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2131}
2132static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2133{
2134 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2135 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2136}
2137
5fd86fcf
AK		 2138static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2139{
36cf24e0
NHE		 2140 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2141 * set this *before* calling this function.
2142 */
edcafe3c 2143 vmx_decache_cr0_guest_bits(vcpu);
81231c69 2144 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 2145 update_exception_bitmap(vcpu);
edcafe3c
AK		 2146 vcpu->arch.cr0_guest_owned_bits = 0;
2147 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 2148 if (is_guest_mode(vcpu)) {
2149 /*
2150 * L1's specified read shadow might not contain the TS bit,
2151 * so now that we turned on shadowing of this bit, we need to
2152 * set this bit of the shadow. Like in nested_vmx_run we need
2153 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2154 * up-to-date here because we just decached cr0.TS (and we'll
2155 * only update vmcs12->guest_cr0 on nested exit).
2156 */
2157 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2158 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2159 (vcpu->arch.cr0 & X86_CR0_TS);
2160 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2161 } else
2162 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2163}
2164
6aa8b732
AK		 2165static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2166{
78ac8b47 2167 unsigned long rflags, save_rflags;
345dcaa8 2168
6de12732
AK		 2169 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2170 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2171 rflags = vmcs_readl(GUEST_RFLAGS);
2172 if (to_vmx(vcpu)->rmode.vm86_active) {
2173 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2174 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2175 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2176 }
2177 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2178 }
6de12732 2179 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2180}
2181
2182static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2183{
6de12732
AK		 2184 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2185 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2186 if (to_vmx(vcpu)->rmode.vm86_active) {
2187 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2188 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2189 }
6aa8b732
AK		 2190 vmcs_writel(GUEST_RFLAGS, rflags);
2191}
2192
37ccdcbe 2193static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2194{
2195 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2196 int ret = 0;
2197
2198 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2199 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2200 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2201 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2202
37ccdcbe 2203 return ret;
2809f5d2
GC		 2204}
2205
2206static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2207{
2208 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2209 u32 interruptibility = interruptibility_old;
2210
2211 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2212
48005f64 2213 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2214 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2215 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2216 interruptibility |= GUEST_INTR_STATE_STI;
2217
2218 if ((interruptibility != interruptibility_old))
2219 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2220}
2221
6aa8b732
AK		 2222static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2223{
2224 unsigned long rip;
6aa8b732 2225
5fdbf976 2226 rip = kvm_rip_read(vcpu);
6aa8b732 2227 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2228 kvm_rip_write(vcpu, rip);
6aa8b732 2229
2809f5d2
GC		 2230 /* skipping an emulated instruction also counts */
2231 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2232}
2233
0b6ac343
NHE		 2234/*
2235 * KVM wants to inject page-faults which it got to the guest. This function
2236 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2237 */
e011c663 2238static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2239{
2240 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2241
e011c663 2242 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2243 return 0;
2244
533558bc
JK		 2245 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2246 vmcs_read32(VM_EXIT_INTR_INFO),
2247 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2248 return 1;
2249}
2250
298101da 2251static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2252 bool has_error_code, u32 error_code,
2253 bool reinject)
298101da 2254{
77ab6db0 2255 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2256 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2257
e011c663
GN		 2258 if (!reinject && is_guest_mode(vcpu) &&
2259 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2260 return;
2261
8ab2d2e2 2262 if (has_error_code) {
77ab6db0 2263 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2264 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2265 }
77ab6db0 2266
7ffd92c5 2267 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2268 int inc_eip = 0;
2269 if (kvm_exception_is_soft(nr))
2270 inc_eip = vcpu->arch.event_exit_inst_len;
2271 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2272 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2273 return;
2274 }
2275
66fd3f7f
GN		 2276 if (kvm_exception_is_soft(nr)) {
2277 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2278 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2279 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2280 } else
2281 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2282
2283 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2284}
2285
4e47c7a6
SY		 2286static bool vmx_rdtscp_supported(void)
2287{
2288 return cpu_has_vmx_rdtscp();
2289}
2290
ad756a16
MJ		 2291static bool vmx_invpcid_supported(void)
2292{
2293 return cpu_has_vmx_invpcid() && enable_ept;
2294}
2295
a75beee6
ED		 2296/*
2297 * Swap MSR entry in host/guest MSR entry array.
2298 */
8b9cf98c 2299static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2300{
26bb0981 2301 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2302
2303 tmp = vmx->guest_msrs[to];
2304 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2305 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2306}
2307
8d14695f
YZ		 2308static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2309{
2310 unsigned long *msr_bitmap;
2311
670125bd
WV		 2312 if (is_guest_mode(vcpu))
2313 msr_bitmap = vmx_msr_bitmap_nested;
8a9781f7 2314 else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
8d14695f
YZ		 2315 if (is_long_mode(vcpu))
2316 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2317 else
2318 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2319 } else {
2320 if (is_long_mode(vcpu))
2321 msr_bitmap = vmx_msr_bitmap_longmode;
2322 else
2323 msr_bitmap = vmx_msr_bitmap_legacy;
2324 }
2325
2326 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2327}
2328
e38aea3e
AK		 2329/*
2330 * Set up the vmcs to automatically save and restore system
2331 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2332 * mode, as fiddling with msrs is very expensive.
2333 */
8b9cf98c 2334static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2335{
26bb0981 2336 int save_nmsrs, index;
e38aea3e 2337
a75beee6
ED		 2338 save_nmsrs = 0;
2339#ifdef CONFIG_X86_64
8b9cf98c 2340 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2341 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2342 if (index >= 0)
8b9cf98c
RR		 2343 move_msr_up(vmx, index, save_nmsrs++);
2344 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2345 if (index >= 0)
8b9cf98c
RR		 2346 move_msr_up(vmx, index, save_nmsrs++);
2347 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2348 if (index >= 0)
8b9cf98c 2349 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6 2350 index = __find_msr_index(vmx, MSR_TSC_AUX);
1cea0ce6 2351 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
4e47c7a6 2352 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2353 /*
8c06585d 2354 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2355 * if efer.sce is enabled.
2356 */
8c06585d 2357 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2358 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2359 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2360 }
2361#endif
92c0d900
AK		 2362 index = __find_msr_index(vmx, MSR_EFER);
2363 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2364 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2365
26bb0981 2366 vmx->save_nmsrs = save_nmsrs;
5897297b 2367
8d14695f
YZ		 2368 if (cpu_has_vmx_msr_bitmap())
2369 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2370}
2371
6aa8b732
AK		 2372/*
2373 * reads and returns guest's timestamp counter "register"
be7b263e
HZ		 2374 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2375 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
6aa8b732 2376 */
be7b263e 2377static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
6aa8b732
AK		 2378{
2379 u64 host_tsc, tsc_offset;
2380
4ea1636b 2381 host_tsc = rdtsc();
6aa8b732 2382 tsc_offset = vmcs_read64(TSC_OFFSET);
be7b263e 2383 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
6aa8b732
AK		 2384}
2385
d5c1785d
NHE		 2386/*
2387 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2388 * counter, even if a nested guest (L2) is currently running.
2389 */
48d89b92 2390static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2391{
886b470c 2392 u64 tsc_offset;
d5c1785d 2393
d5c1785d
NHE		 2394 tsc_offset = is_guest_mode(vcpu) ?
2395 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2396 vmcs_read64(TSC_OFFSET);
2397 return host_tsc + tsc_offset;
2398}
2399
ba904635
WA		 2400static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2401{
2402 return vmcs_read64(TSC_OFFSET);
2403}
2404
6aa8b732 2405/*
99e3e30a 2406 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2407 */
99e3e30a 2408static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2409{
27fc51b2 2410 if (is_guest_mode(vcpu)) {
7991825b 2411 /*
27fc51b2
NHE		 2412 * We're here if L1 chose not to trap WRMSR to TSC. According
2413 * to the spec, this should set L1's TSC; The offset that L1
2414 * set for L2 remains unchanged, and still needs to be added
2415 * to the newly set TSC to get L2's TSC.
7991825b 2416 */
27fc51b2
NHE		 2417 struct vmcs12 *vmcs12;
2418 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2419 /* recalculate vmcs02.TSC_OFFSET: */
2420 vmcs12 = get_vmcs12(vcpu);
2421 vmcs_write64(TSC_OFFSET, offset +
2422 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2423 vmcs12->tsc_offset : 0));
2424 } else {
489223ed
YY		 2425 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2426 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2427 vmcs_write64(TSC_OFFSET, offset);
2428 }
6aa8b732
AK		 2429}
2430
58ea6767 2431static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
e48672fa
ZA		 2432{
2433 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2434
e48672fa 2435 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2436 if (is_guest_mode(vcpu)) {
2437 /* Even when running L2, the adjustment needs to apply to L1 */
2438 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2439 } else
2440 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2441 offset + adjustment);
e48672fa
ZA		 2442}
2443
801d3424
NHE		 2444static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2445{
2446 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2447 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2448}
2449
2450/*
2451 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2452 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2453 * all guests if the "nested" module option is off, and can also be disabled
2454 * for a single guest by disabling its VMX cpuid bit.
2455 */
2456static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2457{
2458 return nested && guest_cpuid_has_vmx(vcpu);
2459}
2460
b87a51ae
NHE		 2461/*
2462 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2463 * returned for the various VMX controls MSRs when nested VMX is enabled.
2464 * The same values should also be used to verify that vmcs12 control fields are
2465 * valid during nested entry from L1 to L2.
2466 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2467 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2468 * bit in the high half is on if the corresponding bit in the control field
2469 * may be on. See also vmx_control_verify().
b87a51ae 2470 */
b9c237bb 2471static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2472{
2473 /*
2474 * Note that as a general rule, the high half of the MSRs (bits in
2475 * the control fields which may be 1) should be initialized by the
2476 * intersection of the underlying hardware's MSR (i.e., features which
2477 * can be supported) and the list of features we want to expose -
2478 * because they are known to be properly supported in our code.
2479 * Also, usually, the low half of the MSRs (bits which must be 1) can
2480 * be set to 0, meaning that L1 may turn off any of these bits. The
2481 * reason is that if one of these bits is necessary, it will appear
2482 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2483 * fields of vmcs01 and vmcs02, will turn these bits off - and
2484 * nested_vmx_exit_handled() will not pass related exits to L1.
2485 * These rules have exceptions below.
2486 */
2487
2488 /* pin-based controls */
eabeaacc 2489 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2490 vmx->nested.nested_vmx_pinbased_ctls_low,
2491 vmx->nested.nested_vmx_pinbased_ctls_high);
2492 vmx->nested.nested_vmx_pinbased_ctls_low |=
2493 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2494 vmx->nested.nested_vmx_pinbased_ctls_high &=
2495 PIN_BASED_EXT_INTR_MASK |
2496 PIN_BASED_NMI_EXITING |
2497 PIN_BASED_VIRTUAL_NMIS;
2498 vmx->nested.nested_vmx_pinbased_ctls_high |=
2499 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2500 PIN_BASED_VMX_PREEMPTION_TIMER;
35754c98 2501 if (vmx_cpu_uses_apicv(&vmx->vcpu))
705699a1
WV		 2502 vmx->nested.nested_vmx_pinbased_ctls_high |=
2503 PIN_BASED_POSTED_INTR;
b87a51ae 2504
3dbcd8da 2505 /* exit controls */
c0dfee58 2506 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2507 vmx->nested.nested_vmx_exit_ctls_low,
2508 vmx->nested.nested_vmx_exit_ctls_high);
2509 vmx->nested.nested_vmx_exit_ctls_low =
2510 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2511
b9c237bb 2512 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2513#ifdef CONFIG_X86_64
c0dfee58 2514 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2515#endif
f4124500 2516 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2517 vmx->nested.nested_vmx_exit_ctls_high |=
2518 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2519 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2520 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2521
36be0b9d 2522 if (vmx_mpx_supported())
b9c237bb 2523 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2524
2996fca0 2525 /* We support free control of debug control saving. */
b9c237bb
WV		 2526 vmx->nested.nested_vmx_true_exit_ctls_low =
2527 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2528 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2529
b87a51ae
NHE		 2530 /* entry controls */
2531 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2532 vmx->nested.nested_vmx_entry_ctls_low,
2533 vmx->nested.nested_vmx_entry_ctls_high);
2534 vmx->nested.nested_vmx_entry_ctls_low =
2535 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2536 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2537#ifdef CONFIG_X86_64
2538 VM_ENTRY_IA32E_MODE |
2539#endif
2540 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2541 vmx->nested.nested_vmx_entry_ctls_high |=
2542 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2543 if (vmx_mpx_supported())
b9c237bb 2544 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2545
2996fca0 2546 /* We support free control of debug control loading. */
b9c237bb
WV		 2547 vmx->nested.nested_vmx_true_entry_ctls_low =
2548 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2549 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2550
b87a51ae
NHE		 2551 /* cpu-based controls */
2552 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2553 vmx->nested.nested_vmx_procbased_ctls_low,
2554 vmx->nested.nested_vmx_procbased_ctls_high);
2555 vmx->nested.nested_vmx_procbased_ctls_low =
2556 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2557 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2558 CPU_BASED_VIRTUAL_INTR_PENDING |
2559 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2560 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2561 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2562 CPU_BASED_CR3_STORE_EXITING |
2563#ifdef CONFIG_X86_64
2564 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2565#endif
2566 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD		 2567 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2568 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2569 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2570 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE		 2571 /*
2572 * We can allow some features even when not supported by the
2573 * hardware. For example, L1 can specify an MSR bitmap - and we
2574 * can use it to avoid exits to L1 - even when L0 runs L2
2575 * without MSR bitmaps.
2576 */
b9c237bb
WV		 2577 vmx->nested.nested_vmx_procbased_ctls_high |=
2578 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2579 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2580
3dcdf3ec 2581 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2582 vmx->nested.nested_vmx_true_procbased_ctls_low =
2583 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2584 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2585
b87a51ae
NHE		 2586 /* secondary cpu-based controls */
2587 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2588 vmx->nested.nested_vmx_secondary_ctls_low,
2589 vmx->nested.nested_vmx_secondary_ctls_high);
2590 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2591 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2592 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2593 SECONDARY_EXEC_RDTSCP |
f2b93280 2594 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
5c614b35 2595 SECONDARY_EXEC_ENABLE_VPID |
82f0dd4b 2596 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2597 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7 2598 SECONDARY_EXEC_WBINVD_EXITING |
8b3e34e4
XG		 2599 SECONDARY_EXEC_XSAVES |
2600 SECONDARY_EXEC_PCOMMIT;
c18911a2 2601
afa61f75
NHE		 2602 if (enable_ept) {
2603 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2604 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2605 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2606 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2607 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2608 VMX_EPT_INVEPT_BIT;
b9c237bb 2609 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2610 /*
4b855078
BD		 2611 * For nested guests, we don't do anything specific
2612 * for single context invalidation. Hence, only advertise
2613 * support for global context invalidation.
afa61f75 2614 */
b9c237bb 2615 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2616 } else
b9c237bb 2617 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2618
089d7b6e
WL		 2619 if (enable_vpid)
2620 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2621 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2622 else
2623 vmx->nested.nested_vmx_vpid_caps = 0;
99b83ac8 2624
0790ec17
RK		 2625 if (enable_unrestricted_guest)
2626 vmx->nested.nested_vmx_secondary_ctls_high |=
2627 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2628
c18911a2 2629 /* miscellaneous data */
b9c237bb
WV		 2630 rdmsr(MSR_IA32_VMX_MISC,
2631 vmx->nested.nested_vmx_misc_low,
2632 vmx->nested.nested_vmx_misc_high);
2633 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2634 vmx->nested.nested_vmx_misc_low |=
2635 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2636 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2637 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2638}
2639
2640static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2641{
2642 /*
2643 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2644 */
2645 return ((control & high) | low) == control;
2646}
2647
2648static inline u64 vmx_control_msr(u32 low, u32 high)
2649{
2650 return low | ((u64)high << 32);
2651}
2652
cae50139 2653/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2654static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2655{
b9c237bb
WV		 2656 struct vcpu_vmx *vmx = to_vmx(vcpu);
2657
b87a51ae 2658 switch (msr_index) {
b87a51ae
NHE		 2659 case MSR_IA32_VMX_BASIC:
2660 /*
2661 * This MSR reports some information about VMX support. We
2662 * should return information about the VMX we emulate for the
2663 * guest, and the VMCS structure we give it - not about the
2664 * VMX support of the underlying hardware.
2665 */
3dbcd8da 2666 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2667 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2668 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2669 break;
2670 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2671 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2672 *pdata = vmx_control_msr(
2673 vmx->nested.nested_vmx_pinbased_ctls_low,
2674 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2675 break;
2676 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2677 *pdata = vmx_control_msr(
2678 vmx->nested.nested_vmx_true_procbased_ctls_low,
2679 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2680 break;
b87a51ae 2681 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2682 *pdata = vmx_control_msr(
2683 vmx->nested.nested_vmx_procbased_ctls_low,
2684 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2685 break;
2686 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2687 *pdata = vmx_control_msr(
2688 vmx->nested.nested_vmx_true_exit_ctls_low,
2689 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2690 break;
b87a51ae 2691 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2692 *pdata = vmx_control_msr(
2693 vmx->nested.nested_vmx_exit_ctls_low,
2694 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2695 break;
2696 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2697 *pdata = vmx_control_msr(
2698 vmx->nested.nested_vmx_true_entry_ctls_low,
2699 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2700 break;
b87a51ae 2701 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2702 *pdata = vmx_control_msr(
2703 vmx->nested.nested_vmx_entry_ctls_low,
2704 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2705 break;
2706 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2707 *pdata = vmx_control_msr(
2708 vmx->nested.nested_vmx_misc_low,
2709 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2710 break;
2711 /*
2712 * These MSRs specify bits which the guest must keep fixed (on or off)
2713 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2714 * We picked the standard core2 setting.
2715 */
2716#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2717#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2718 case MSR_IA32_VMX_CR0_FIXED0:
2719 *pdata = VMXON_CR0_ALWAYSON;
2720 break;
2721 case MSR_IA32_VMX_CR0_FIXED1:
2722 *pdata = -1ULL;
2723 break;
2724 case MSR_IA32_VMX_CR4_FIXED0:
2725 *pdata = VMXON_CR4_ALWAYSON;
2726 break;
2727 case MSR_IA32_VMX_CR4_FIXED1:
2728 *pdata = -1ULL;
2729 break;
2730 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2731 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2732 break;
2733 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2734 *pdata = vmx_control_msr(
2735 vmx->nested.nested_vmx_secondary_ctls_low,
2736 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2737 break;
2738 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2739 /* Currently, no nested vpid support */
089d7b6e
WL		 2740 *pdata = vmx->nested.nested_vmx_ept_caps |
2741 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
b87a51ae
NHE		 2742 break;
2743 default:
b87a51ae 2744 return 1;
b3897a49
NHE		 2745 }
2746
b87a51ae
NHE		 2747 return 0;
2748}
2749
6aa8b732
AK		 2750/*
2751 * Reads an msr value (of 'msr_index') into 'pdata'.
2752 * Returns 0 on success, non-0 otherwise.
2753 * Assumes vcpu_load() was already called.
2754 */
609e36d3 2755static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2756{
26bb0981 2757 struct shared_msr_entry *msr;
6aa8b732 2758
609e36d3 2759 switch (msr_info->index) {
05b3e0c2 2760#ifdef CONFIG_X86_64
6aa8b732 2761 case MSR_FS_BASE:
609e36d3 2762 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK		 2763 break;
2764 case MSR_GS_BASE:
609e36d3 2765 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 2766 break;
44ea2b17
AK		 2767 case MSR_KERNEL_GS_BASE:
2768 vmx_load_host_state(to_vmx(vcpu));
609e36d3 2769 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 2770 break;
26bb0981 2771#endif
6aa8b732 2772 case MSR_EFER:
609e36d3 2773 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 2774 case MSR_IA32_TSC:
be7b263e 2775 msr_info->data = guest_read_tsc(vcpu);
6aa8b732
AK		 2776 break;
2777 case MSR_IA32_SYSENTER_CS:
609e36d3 2778 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 2779 break;
2780 case MSR_IA32_SYSENTER_EIP:
609e36d3 2781 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2782 break;
2783 case MSR_IA32_SYSENTER_ESP:
609e36d3 2784 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2785 break;
0dd376e7 2786 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2787 if (!vmx_mpx_supported())
2788 return 1;
609e36d3 2789 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 2790 break;
cae50139
JK		 2791 case MSR_IA32_FEATURE_CONTROL:
2792 if (!nested_vmx_allowed(vcpu))
2793 return 1;
609e36d3 2794 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
cae50139
JK		 2795 break;
2796 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2797 if (!nested_vmx_allowed(vcpu))
2798 return 1;
609e36d3 2799 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL		 2800 case MSR_IA32_XSS:
2801 if (!vmx_xsaves_supported())
2802 return 1;
609e36d3 2803 msr_info->data = vcpu->arch.ia32_xss;
20300099 2804 break;
4e47c7a6 2805 case MSR_TSC_AUX:
1cea0ce6 2806 if (!guest_cpuid_has_rdtscp(vcpu))
4e47c7a6
SY		 2807 return 1;
2808 /* Otherwise falls through */
6aa8b732 2809 default:
609e36d3 2810 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 2811 if (msr) {
609e36d3 2812 msr_info->data = msr->data;
3bab1f5d 2813 break;
6aa8b732 2814 }
609e36d3 2815 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2816 }
2817
6aa8b732
AK		 2818 return 0;
2819}
2820
cae50139
JK		 2821static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2822
6aa8b732
AK		 2823/*
2824 * Writes msr value into into the appropriate "register".
2825 * Returns 0 on success, non-0 otherwise.
2826 * Assumes vcpu_load() was already called.
2827 */
8fe8ab46 2828static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2829{
a2fa3e9f 2830 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2831 struct shared_msr_entry *msr;
2cc51560 2832 int ret = 0;
8fe8ab46
WA		 2833 u32 msr_index = msr_info->index;
2834 u64 data = msr_info->data;
2cc51560 2835
6aa8b732 2836 switch (msr_index) {
3bab1f5d 2837 case MSR_EFER:
8fe8ab46 2838 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2839 break;
16175a79 2840#ifdef CONFIG_X86_64
6aa8b732 2841 case MSR_FS_BASE:
2fb92db1 2842 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2843 vmcs_writel(GUEST_FS_BASE, data);
2844 break;
2845 case MSR_GS_BASE:
2fb92db1 2846 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2847 vmcs_writel(GUEST_GS_BASE, data);
2848 break;
44ea2b17
AK		 2849 case MSR_KERNEL_GS_BASE:
2850 vmx_load_host_state(vmx);
2851 vmx->msr_guest_kernel_gs_base = data;
2852 break;
6aa8b732
AK		 2853#endif
2854 case MSR_IA32_SYSENTER_CS:
2855 vmcs_write32(GUEST_SYSENTER_CS, data);
2856 break;
2857 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2858 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2859 break;
2860 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2861 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2862 break;
0dd376e7 2863 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2864 if (!vmx_mpx_supported())
2865 return 1;
0dd376e7
LJ		 2866 vmcs_write64(GUEST_BNDCFGS, data);
2867 break;
af24a4e4 2868 case MSR_IA32_TSC:
8fe8ab46 2869 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2870 break;
468d472f
SY		 2871 case MSR_IA32_CR_PAT:
2872 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2873 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2874 return 1;
468d472f
SY		 2875 vmcs_write64(GUEST_IA32_PAT, data);
2876 vcpu->arch.pat = data;
2877 break;
2878 }
8fe8ab46 2879 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2880 break;
ba904635
WA		 2881 case MSR_IA32_TSC_ADJUST:
2882 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2883 break;
cae50139
JK		 2884 case MSR_IA32_FEATURE_CONTROL:
2885 if (!nested_vmx_allowed(vcpu) ||
2886 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2887 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2888 return 1;
2889 vmx->nested.msr_ia32_feature_control = data;
2890 if (msr_info->host_initiated && data == 0)
2891 vmx_leave_nested(vcpu);
2892 break;
2893 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2894 return 1; /* they are read-only */
20300099
WL		 2895 case MSR_IA32_XSS:
2896 if (!vmx_xsaves_supported())
2897 return 1;
2898 /*
2899 * The only supported bit as of Skylake is bit 8, but
2900 * it is not supported on KVM.
2901 */
2902 if (data != 0)
2903 return 1;
2904 vcpu->arch.ia32_xss = data;
2905 if (vcpu->arch.ia32_xss != host_xss)
2906 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2907 vcpu->arch.ia32_xss, host_xss);
2908 else
2909 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2910 break;
4e47c7a6 2911 case MSR_TSC_AUX:
1cea0ce6 2912 if (!guest_cpuid_has_rdtscp(vcpu))
4e47c7a6
SY		 2913 return 1;
2914 /* Check reserved bit, higher 32 bits should be zero */
2915 if ((data >> 32) != 0)
2916 return 1;
2917 /* Otherwise falls through */
6aa8b732 2918 default:
8b9cf98c 2919 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2920 if (msr) {
8b3c3104 2921 u64 old_msr_data = msr->data;
3bab1f5d 2922 msr->data = data;
2225fd56
AK		 2923 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2924 preempt_disable();
8b3c3104
AH		 2925 ret = kvm_set_shared_msr(msr->index, msr->data,
2926 msr->mask);
2225fd56 2927 preempt_enable();
8b3c3104
AH		 2928 if (ret)
2929 msr->data = old_msr_data;
2225fd56 2930 }
3bab1f5d 2931 break;
6aa8b732 2932 }
8fe8ab46 2933 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2934 }
2935
2cc51560 2936 return ret;
6aa8b732
AK		 2937}
2938
5fdbf976 2939static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2940{
5fdbf976
MT		 2941 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2942 switch (reg) {
2943 case VCPU_REGS_RSP:
2944 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2945 break;
2946 case VCPU_REGS_RIP:
2947 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2948 break;
6de4f3ad
AK		 2949 case VCPU_EXREG_PDPTR:
2950 if (enable_ept)
2951 ept_save_pdptrs(vcpu);
2952 break;
5fdbf976
MT		 2953 default:
2954 break;
2955 }
6aa8b732
AK		 2956}
2957
6aa8b732
AK		 2958static __init int cpu_has_kvm_support(void)
2959{
6210e37b 2960 return cpu_has_vmx();
6aa8b732
AK		 2961}
2962
2963static __init int vmx_disabled_by_bios(void)
2964{
2965 u64 msr;
2966
2967 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2968 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2969 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2970 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2971 && tboot_enabled())
2972 return 1;
23f3e991 2973 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2974 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2975 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2976 && !tboot_enabled()) {
2977 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2978 "activate TXT before enabling KVM\n");
cafd6659 2979 return 1;
f9335afe 2980 }
23f3e991
JC		 2981 /* launched w/o TXT and VMX disabled */
2982 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2983 && !tboot_enabled())
2984 return 1;
cafd6659
SW		 2985 }
2986
2987 return 0;
6aa8b732
AK		 2988}
2989
7725b894
DX		 2990static void kvm_cpu_vmxon(u64 addr)
2991{
2992 asm volatile (ASM_VMX_VMXON_RAX
2993 : : "a"(&addr), "m"(addr)
2994 : "memory", "cc");
2995}
2996
13a34e06 2997static int hardware_enable(void)
6aa8b732
AK		 2998{
2999 int cpu = raw_smp_processor_id();
3000 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 3001 u64 old, test_bits;
6aa8b732 3002
1e02ce4c 3003 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 3004 return -EBUSY;
3005
d462b819 3006 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW		 3007 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3008 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY		 3009
3010 /*
3011 * Now we can enable the vmclear operation in kdump
3012 * since the loaded_vmcss_on_cpu list on this cpu
3013 * has been initialized.
3014 *
3015 * Though the cpu is not in VMX operation now, there
3016 * is no problem to enable the vmclear operation
3017 * for the loaded_vmcss_on_cpu list is empty!
3018 */
3019 crash_enable_local_vmclear(cpu);
3020
6aa8b732 3021 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 3022
3023 test_bits = FEATURE_CONTROL_LOCKED;
3024 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3025 if (tboot_enabled())
3026 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3027
3028 if ((old & test_bits) != test_bits) {
6aa8b732 3029 /* enable and lock */
cafd6659
SW		 3030 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3031 }
375074cc 3032 cr4_set_bits(X86_CR4_VMXE);
10474ae8 3033
4610c9cc
DX		 3034 if (vmm_exclusive) {
3035 kvm_cpu_vmxon(phys_addr);
3036 ept_sync_global();
3037 }
10474ae8 3038
89cbc767 3039 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 3040
10474ae8 3041 return 0;
6aa8b732
AK		 3042}
3043
d462b819 3044static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 3045{
3046 int cpu = raw_smp_processor_id();
d462b819 3047 struct loaded_vmcs *v, *n;
543e4243 3048
d462b819
NHE		 3049 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3050 loaded_vmcss_on_cpu_link)
3051 __loaded_vmcs_clear(v);
543e4243
AK		 3052}
3053
710ff4a8
EH		 3054
3055/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3056 * tricks.
3057 */
3058static void kvm_cpu_vmxoff(void)
6aa8b732 3059{
4ecac3fd 3060 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 3061}
3062
13a34e06 3063static void hardware_disable(void)
710ff4a8 3064{
4610c9cc 3065 if (vmm_exclusive) {
d462b819 3066 vmclear_local_loaded_vmcss();
4610c9cc
DX		 3067 kvm_cpu_vmxoff();
3068 }
375074cc 3069 cr4_clear_bits(X86_CR4_VMXE);
710ff4a8
EH		 3070}
3071
1c3d14fe 3072static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 3073 u32 msr, u32 *result)
1c3d14fe
YS		 3074{
3075 u32 vmx_msr_low, vmx_msr_high;
3076 u32 ctl = ctl_min | ctl_opt;
3077
3078 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3079
3080 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3081 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3082
3083 /* Ensure minimum (required) set of control bits are supported. */
3084 if (ctl_min & ~ctl)
002c7f7c 3085 return -EIO;
1c3d14fe
YS		 3086
3087 *result = ctl;
3088 return 0;
3089}
3090
110312c8
AK		 3091static __init bool allow_1_setting(u32 msr, u32 ctl)
3092{
3093 u32 vmx_msr_low, vmx_msr_high;
3094
3095 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3096 return vmx_msr_high & ctl;
3097}
3098
002c7f7c 3099static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 3100{
3101 u32 vmx_msr_low, vmx_msr_high;
d56f546d 3102 u32 min, opt, min2, opt2;
1c3d14fe
YS		 3103 u32 _pin_based_exec_control = 0;
3104 u32 _cpu_based_exec_control = 0;
f78e0e2e 3105 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 3106 u32 _vmexit_control = 0;
3107 u32 _vmentry_control = 0;
3108
10166744 3109 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 3110#ifdef CONFIG_X86_64
3111 CPU_BASED_CR8_LOAD_EXITING |
3112 CPU_BASED_CR8_STORE_EXITING |
3113#endif
d56f546d
SY		 3114 CPU_BASED_CR3_LOAD_EXITING |
3115 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 3116 CPU_BASED_USE_IO_BITMAPS |
3117 CPU_BASED_MOV_DR_EXITING |
a7052897 3118 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 3119 CPU_BASED_MWAIT_EXITING |
3120 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 3121 CPU_BASED_INVLPG_EXITING |
3122 CPU_BASED_RDPMC_EXITING;
443381a8 3123
f78e0e2e 3124 opt = CPU_BASED_TPR_SHADOW |
25c5f225 3125 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 3126 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 3127 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3128 &_cpu_based_exec_control) < 0)
002c7f7c 3129 return -EIO;
6e5d865c
YS		 3130#ifdef CONFIG_X86_64
3131 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3132 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3133 ~CPU_BASED_CR8_STORE_EXITING;
3134#endif
f78e0e2e 3135 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 3136 min2 = 0;
3137 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3138 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3139 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3140 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3141 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3142 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3143 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3144 SECONDARY_EXEC_RDTSCP |
83d4c286 3145 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3146 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3147 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3148 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 3149 SECONDARY_EXEC_XSAVES |
8b3e34e4 3150 SECONDARY_EXEC_ENABLE_PML |
64903d61
HZ		 3151 SECONDARY_EXEC_PCOMMIT |
3152 SECONDARY_EXEC_TSC_SCALING;
d56f546d
SY		 3153 if (adjust_vmx_controls(min2, opt2,
3154 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3155 &_cpu_based_2nd_exec_control) < 0)
3156 return -EIO;
3157 }
3158#ifndef CONFIG_X86_64
3159 if (!(_cpu_based_2nd_exec_control &
3160 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3161 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3162#endif
83d4c286
YZ		 3163
3164 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3165 _cpu_based_2nd_exec_control &= ~(
8d14695f 3166 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3167 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3168 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3169
d56f546d 3170 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3171 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3172 enabled */
5fff7d27
GN		 3173 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3174 CPU_BASED_CR3_STORE_EXITING |
3175 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3176 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3177 vmx_capability.ept, vmx_capability.vpid);
3178 }
1c3d14fe 3179
81908bf4 3180 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3181#ifdef CONFIG_X86_64
3182 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3183#endif
a547c6db 3184 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3185 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3186 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3187 &_vmexit_control) < 0)
002c7f7c 3188 return -EIO;
1c3d14fe 3189
01e439be
YZ		 3190 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3191 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3192 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3193 &_pin_based_exec_control) < 0)
3194 return -EIO;
3195
3196 if (!(_cpu_based_2nd_exec_control &
3197 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3198 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3199 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3200
c845f9c6 3201 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3202 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3203 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3204 &_vmentry_control) < 0)
002c7f7c 3205 return -EIO;
6aa8b732 3206
c68876fd 3207 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3208
3209 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3210 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3211 return -EIO;
1c3d14fe
YS		 3212
3213#ifdef CONFIG_X86_64
3214 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3215 if (vmx_msr_high & (1u<<16))
002c7f7c 3216 return -EIO;
1c3d14fe
YS		 3217#endif
3218
3219 /* Require Write-Back (WB) memory type for VMCS accesses. */
3220 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3221 return -EIO;
1c3d14fe 3222
002c7f7c
YS		 3223 vmcs_conf->size = vmx_msr_high & 0x1fff;
3224 vmcs_conf->order = get_order(vmcs_config.size);
3225 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3226
002c7f7c
YS		 3227 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3228 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3229 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3230 vmcs_conf->vmexit_ctrl = _vmexit_control;
3231 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3232
110312c8
AK		 3233 cpu_has_load_ia32_efer =
3234 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3235 VM_ENTRY_LOAD_IA32_EFER)
3236 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3237 VM_EXIT_LOAD_IA32_EFER);
3238
8bf00a52
GN		 3239 cpu_has_load_perf_global_ctrl =
3240 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3241 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3242 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3243 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3244
3245 /*
3246 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3247 * but due to arrata below it can't be used. Workaround is to use
3248 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3249 *
3250 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3251 *
3252 * AAK155 (model 26)
3253 * AAP115 (model 30)
3254 * AAT100 (model 37)
3255 * BC86,AAY89,BD102 (model 44)
3256 * BA97 (model 46)
3257 *
3258 */
3259 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3260 switch (boot_cpu_data.x86_model) {
3261 case 26:
3262 case 30:
3263 case 37:
3264 case 44:
3265 case 46:
3266 cpu_has_load_perf_global_ctrl = false;
3267 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3268 "does not work properly. Using workaround\n");
3269 break;
3270 default:
3271 break;
3272 }
3273 }
3274
20300099
WL		 3275 if (cpu_has_xsaves)
3276 rdmsrl(MSR_IA32_XSS, host_xss);
3277
1c3d14fe 3278 return 0;
c68876fd 3279}
6aa8b732
AK		 3280
3281static struct vmcs *alloc_vmcs_cpu(int cpu)
3282{
3283 int node = cpu_to_node(cpu);
3284 struct page *pages;
3285 struct vmcs *vmcs;
3286
96db800f 3287 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3288 if (!pages)
3289 return NULL;
3290 vmcs = page_address(pages);
1c3d14fe
YS		 3291 memset(vmcs, 0, vmcs_config.size);
3292 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3293 return vmcs;
3294}
3295
3296static struct vmcs *alloc_vmcs(void)
3297{
d3b2c338 3298 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3299}
3300
3301static void free_vmcs(struct vmcs *vmcs)
3302{
1c3d14fe 3303 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3304}
3305
d462b819
NHE		 3306/*
3307 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3308 */
3309static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3310{
3311 if (!loaded_vmcs->vmcs)
3312 return;
3313 loaded_vmcs_clear(loaded_vmcs);
3314 free_vmcs(loaded_vmcs->vmcs);
3315 loaded_vmcs->vmcs = NULL;
3316}
3317
39959588 3318static void free_kvm_area(void)
6aa8b732
AK		 3319{
3320 int cpu;
3321
3230bb47 3322 for_each_possible_cpu(cpu) {
6aa8b732 3323 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3324 per_cpu(vmxarea, cpu) = NULL;
3325 }
6aa8b732
AK		 3326}
3327
fe2b201b
BD		 3328static void init_vmcs_shadow_fields(void)
3329{
3330 int i, j;
3331
3332 /* No checks for read only fields yet */
3333
3334 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3335 switch (shadow_read_write_fields[i]) {
3336 case GUEST_BNDCFGS:
3337 if (!vmx_mpx_supported())
3338 continue;
3339 break;
3340 default:
3341 break;
3342 }
3343
3344 if (j < i)
3345 shadow_read_write_fields[j] =
3346 shadow_read_write_fields[i];
3347 j++;
3348 }
3349 max_shadow_read_write_fields = j;
3350
3351 /* shadowed fields guest access without vmexit */
3352 for (i = 0; i < max_shadow_read_write_fields; i++) {
3353 clear_bit(shadow_read_write_fields[i],
3354 vmx_vmwrite_bitmap);
3355 clear_bit(shadow_read_write_fields[i],
3356 vmx_vmread_bitmap);
3357 }
3358 for (i = 0; i < max_shadow_read_only_fields; i++)
3359 clear_bit(shadow_read_only_fields[i],
3360 vmx_vmread_bitmap);
3361}
3362
6aa8b732
AK		 3363static __init int alloc_kvm_area(void)
3364{
3365 int cpu;
3366
3230bb47 3367 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3368 struct vmcs *vmcs;
3369
3370 vmcs = alloc_vmcs_cpu(cpu);
3371 if (!vmcs) {
3372 free_kvm_area();
3373 return -ENOMEM;
3374 }
3375
3376 per_cpu(vmxarea, cpu) = vmcs;
3377 }
3378 return 0;
3379}
3380
14168786
GN		 3381static bool emulation_required(struct kvm_vcpu *vcpu)
3382{
3383 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3384}
3385
91b0aa2c 3386static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3387 struct kvm_segment *save)
6aa8b732 3388{
d99e4152
GN		 3389 if (!emulate_invalid_guest_state) {
3390 /*
3391 * CS and SS RPL should be equal during guest entry according
3392 * to VMX spec, but in reality it is not always so. Since vcpu
3393 * is in the middle of the transition from real mode to
3394 * protected mode it is safe to assume that RPL 0 is a good
3395 * default value.
3396 */
3397 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 3398 save->selector &= ~SEGMENT_RPL_MASK;
3399 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3400 save->s = 1;
6aa8b732 3401 }
d99e4152 3402 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3403}
3404
3405static void enter_pmode(struct kvm_vcpu *vcpu)
3406{
3407 unsigned long flags;
a89a8fb9 3408 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3409
d99e4152
GN		 3410 /*
3411 * Update real mode segment cache. It may be not up-to-date if sement
3412 * register was written while vcpu was in a guest mode.
3413 */
3414 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3415 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3416 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3417 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3418 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3419 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3420
7ffd92c5 3421 vmx->rmode.vm86_active = 0;
6aa8b732 3422
2fb92db1
AK		 3423 vmx_segment_cache_clear(vmx);
3424
f5f7b2fe 3425 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3426
3427 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3428 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3429 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3430 vmcs_writel(GUEST_RFLAGS, flags);
3431
66aee91a
RR		 3432 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3433 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3434
3435 update_exception_bitmap(vcpu);
3436
91b0aa2c
GN		 3437 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3438 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3439 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3440 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3441 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3442 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3443}
3444
f5f7b2fe 3445static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3446{
772e0318 3447 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3448 struct kvm_segment var = *save;
3449
3450 var.dpl = 0x3;
3451 if (seg == VCPU_SREG_CS)
3452 var.type = 0x3;
3453
3454 if (!emulate_invalid_guest_state) {
3455 var.selector = var.base >> 4;
3456 var.base = var.base & 0xffff0;
3457 var.limit = 0xffff;
3458 var.g = 0;
3459 var.db = 0;
3460 var.present = 1;
3461 var.s = 1;
3462 var.l = 0;
3463 var.unusable = 0;
3464 var.type = 0x3;
3465 var.avl = 0;
3466 if (save->base & 0xf)
3467 printk_once(KERN_WARNING "kvm: segment base is not "
3468 "paragraph aligned when entering "
3469 "protected mode (seg=%d)", seg);
3470 }
6aa8b732 3471
d99e4152
GN		 3472 vmcs_write16(sf->selector, var.selector);
3473 vmcs_write32(sf->base, var.base);
3474 vmcs_write32(sf->limit, var.limit);
3475 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3476}
3477
3478static void enter_rmode(struct kvm_vcpu *vcpu)
3479{
3480 unsigned long flags;
a89a8fb9 3481 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3482
f5f7b2fe
AK		 3483 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3484 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3485 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3486 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3487 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3488 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3489 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3490
7ffd92c5 3491 vmx->rmode.vm86_active = 1;
6aa8b732 3492
776e58ea
GN		 3493 /*
3494 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3495 * vcpu. Warn the user that an update is overdue.
776e58ea 3496 */
4918c6ca 3497 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3498 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3499 "called before entering vcpu\n");
776e58ea 3500
2fb92db1
AK		 3501 vmx_segment_cache_clear(vmx);
3502
4918c6ca 3503 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3504 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3505 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3506
3507 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3508 vmx->rmode.save_rflags = flags;
6aa8b732 3509
053de044 3510 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3511
3512 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3513 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3514 update_exception_bitmap(vcpu);
3515
d99e4152
GN		 3516 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3517 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3518 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3519 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3520 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3521 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3522
8668a3c4 3523 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3524}
3525
401d10de
AS		 3526static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3527{
3528 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3529 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3530
3531 if (!msr)
3532 return;
401d10de 3533
44ea2b17
AK		 3534 /*
3535 * Force kernel_gs_base reloading before EFER changes, as control
3536 * of this msr depends on is_long_mode().
3537 */
3538 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3539 vcpu->arch.efer = efer;
401d10de 3540 if (efer & EFER_LMA) {
2961e876 3541 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3542 msr->data = efer;
3543 } else {
2961e876 3544 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3545
3546 msr->data = efer & ~EFER_LME;
3547 }
3548 setup_msrs(vmx);
3549}
3550
05b3e0c2 3551#ifdef CONFIG_X86_64
6aa8b732
AK		 3552
3553static void enter_lmode(struct kvm_vcpu *vcpu)
3554{
3555 u32 guest_tr_ar;
3556
2fb92db1
AK		 3557 vmx_segment_cache_clear(to_vmx(vcpu));
3558
6aa8b732 3559 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 3560 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3561 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3562 __func__);
6aa8b732 3563 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 3564 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3565 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 3566 }
da38f438 3567 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3568}
3569
3570static void exit_lmode(struct kvm_vcpu *vcpu)
3571{
2961e876 3572 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3573 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3574}
3575
3576#endif
3577
dd5f5341 3578static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
2384d2b3 3579{
dd5f5341 3580 vpid_sync_context(vpid);
dd180b3e
XG		 3581 if (enable_ept) {
3582 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3583 return;
4e1096d2 3584 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3585 }
2384d2b3
SY		 3586}
3587
dd5f5341
WL		 3588static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3589{
3590 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3591}
3592
e8467fda
AK		 3593static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3594{
3595 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3596
3597 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3598 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3599}
3600
aff48baa
AK		 3601static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3602{
3603 if (enable_ept && is_paging(vcpu))
3604 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3605 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3606}
3607
25c4c276 3608static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3609{
fc78f519
AK		 3610 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3611
3612 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3613 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3614}
3615
1439442c
SY		 3616static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3617{
d0d538b9
GN		 3618 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3619
6de4f3ad
AK		 3620 if (!test_bit(VCPU_EXREG_PDPTR,
3621 (unsigned long *)&vcpu->arch.regs_dirty))
3622 return;
3623
1439442c 3624 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3625 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3626 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3627 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3628 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3629 }
3630}
3631
8f5d549f
AK		 3632static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3633{
d0d538b9
GN		 3634 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3635
8f5d549f 3636 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3637 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3638 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3639 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3640 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3641 }
6de4f3ad
AK		 3642
3643 __set_bit(VCPU_EXREG_PDPTR,
3644 (unsigned long *)&vcpu->arch.regs_avail);
3645 __set_bit(VCPU_EXREG_PDPTR,
3646 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3647}
3648
5e1746d6 3649static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3650
3651static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3652 unsigned long cr0,
3653 struct kvm_vcpu *vcpu)
3654{
5233dd51
MT		 3655 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3656 vmx_decache_cr3(vcpu);
1439442c
SY		 3657 if (!(cr0 & X86_CR0_PG)) {
3658 /* From paging/starting to nonpaging */
3659 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3660 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3661 (CPU_BASED_CR3_LOAD_EXITING |
3662 CPU_BASED_CR3_STORE_EXITING));
3663 vcpu->arch.cr0 = cr0;
fc78f519 3664 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3665 } else if (!is_paging(vcpu)) {
3666 /* From nonpaging to paging */
3667 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3668 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3669 ~(CPU_BASED_CR3_LOAD_EXITING |
3670 CPU_BASED_CR3_STORE_EXITING));
3671 vcpu->arch.cr0 = cr0;
fc78f519 3672 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3673 }
95eb84a7
SY		 3674
3675 if (!(cr0 & X86_CR0_WP))
3676 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3677}
3678
6aa8b732
AK		 3679static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3680{
7ffd92c5 3681 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3682 unsigned long hw_cr0;
3683
5037878e 3684 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3685 if (enable_unrestricted_guest)
5037878e 3686 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3687 else {
5037878e 3688 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3689
218e763f
GN		 3690 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3691 enter_pmode(vcpu);
6aa8b732 3692
218e763f
GN		 3693 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3694 enter_rmode(vcpu);
3695 }
6aa8b732 3696
05b3e0c2 3697#ifdef CONFIG_X86_64
f6801dff 3698 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3699 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3700 enter_lmode(vcpu);
707d92fa 3701 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3702 exit_lmode(vcpu);
3703 }
3704#endif
3705
089d034e 3706 if (enable_ept)
1439442c
SY		 3707 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3708
02daab21 3709 if (!vcpu->fpu_active)
81231c69 3710 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3711
6aa8b732 3712 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3713 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3714 vcpu->arch.cr0 = cr0;
14168786
GN		 3715
3716 /* depends on vcpu->arch.cr0 to be set to a new value */
3717 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3718}
3719
1439442c
SY		 3720static u64 construct_eptp(unsigned long root_hpa)
3721{
3722 u64 eptp;
3723
3724 /* TODO write the value reading from MSR */
3725 eptp = VMX_EPT_DEFAULT_MT |
3726 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3727 if (enable_ept_ad_bits)
3728 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3729 eptp |= (root_hpa & PAGE_MASK);
3730
3731 return eptp;
3732}
3733
6aa8b732
AK		 3734static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3735{
1439442c
SY		 3736 unsigned long guest_cr3;
3737 u64 eptp;
3738
3739 guest_cr3 = cr3;
089d034e 3740 if (enable_ept) {
1439442c
SY		 3741 eptp = construct_eptp(cr3);
3742 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3743 if (is_paging(vcpu) || is_guest_mode(vcpu))
3744 guest_cr3 = kvm_read_cr3(vcpu);
3745 else
3746 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3747 ept_load_pdptrs(vcpu);
1439442c
SY		 3748 }
3749
2384d2b3 3750 vmx_flush_tlb(vcpu);
1439442c 3751 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3752}
3753
5e1746d6 3754static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3755{
085e68ee
BS		 3756 /*
3757 * Pass through host's Machine Check Enable value to hw_cr4, which
3758 * is in force while we are in guest mode. Do not let guests control
3759 * this bit, even if host CR4.MCE == 0.
3760 */
3761 unsigned long hw_cr4 =
3762 (cr4_read_shadow() & X86_CR4_MCE) |
3763 (cr4 & ~X86_CR4_MCE) |
3764 (to_vmx(vcpu)->rmode.vm86_active ?
3765 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 3766
5e1746d6
NHE		 3767 if (cr4 & X86_CR4_VMXE) {
3768 /*
3769 * To use VMXON (and later other VMX instructions), a guest
3770 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3771 * So basically the check on whether to allow nested VMX
3772 * is here.
3773 */
3774 if (!nested_vmx_allowed(vcpu))
3775 return 1;
1a0d74e6
JK		 3776 }
3777 if (to_vmx(vcpu)->nested.vmxon &&
3778 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3779 return 1;
3780
ad312c7c 3781 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3782 if (enable_ept) {
3783 if (!is_paging(vcpu)) {
3784 hw_cr4 &= ~X86_CR4_PAE;
3785 hw_cr4 |= X86_CR4_PSE;
3786 } else if (!(cr4 & X86_CR4_PAE)) {
3787 hw_cr4 &= ~X86_CR4_PAE;
3788 }
3789 }
1439442c 3790
656ec4a4
RK		 3791 if (!enable_unrestricted_guest && !is_paging(vcpu))
3792 /*
3793 * SMEP/SMAP is disabled if CPU is in non-paging mode in
3794 * hardware. However KVM always uses paging mode without
3795 * unrestricted guest.
3796 * To emulate this behavior, SMEP/SMAP needs to be manually
3797 * disabled when guest switches to non-paging mode.
3798 */
3799 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3800
1439442c
SY		 3801 vmcs_writel(CR4_READ_SHADOW, cr4);
3802 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3803 return 0;
6aa8b732
AK		 3804}
3805
6aa8b732
AK		 3806static void vmx_get_segment(struct kvm_vcpu *vcpu,
3807 struct kvm_segment *var, int seg)
3808{
a9179499 3809 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3810 u32 ar;
3811
c6ad1153 3812 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3813 *var = vmx->rmode.segs[seg];
a9179499 3814 if (seg == VCPU_SREG_TR
2fb92db1 3815 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3816 return;
1390a28b
AK		 3817 var->base = vmx_read_guest_seg_base(vmx, seg);
3818 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3819 return;
a9179499 3820 }
2fb92db1
AK		 3821 var->base = vmx_read_guest_seg_base(vmx, seg);
3822 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3823 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3824 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3825 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3826 var->type = ar & 15;
3827 var->s = (ar >> 4) & 1;
3828 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3829 /*
3830 * Some userspaces do not preserve unusable property. Since usable
3831 * segment has to be present according to VMX spec we can use present
3832 * property to amend userspace bug by making unusable segment always
3833 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3834 * segment as unusable.
3835 */
3836 var->present = !var->unusable;
6aa8b732
AK		 3837 var->avl = (ar >> 12) & 1;
3838 var->l = (ar >> 13) & 1;
3839 var->db = (ar >> 14) & 1;
3840 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3841}
3842
a9179499
AK		 3843static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3844{
a9179499
AK		 3845 struct kvm_segment s;
3846
3847 if (to_vmx(vcpu)->rmode.vm86_active) {
3848 vmx_get_segment(vcpu, &s, seg);
3849 return s.base;
3850 }
2fb92db1 3851 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3852}
3853
b09408d0 3854static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3855{
b09408d0
MT		 3856 struct vcpu_vmx *vmx = to_vmx(vcpu);
3857
ae9fedc7 3858 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3859 return 0;
ae9fedc7
PB		 3860 else {
3861 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3862 return VMX_AR_DPL(ar);
69c73028 3863 }
69c73028
AK		 3864}
3865
653e3108 3866static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3867{
6aa8b732
AK		 3868 u32 ar;
3869
f0495f9b 3870 if (var->unusable || !var->present)
6aa8b732
AK		 3871 ar = 1 << 16;
3872 else {
3873 ar = var->type & 15;
3874 ar |= (var->s & 1) << 4;
3875 ar |= (var->dpl & 3) << 5;
3876 ar |= (var->present & 1) << 7;
3877 ar |= (var->avl & 1) << 12;
3878 ar |= (var->l & 1) << 13;
3879 ar |= (var->db & 1) << 14;
3880 ar |= (var->g & 1) << 15;
3881 }
653e3108
AK		 3882
3883 return ar;
3884}
3885
3886static void vmx_set_segment(struct kvm_vcpu *vcpu,
3887 struct kvm_segment *var, int seg)
3888{
7ffd92c5 3889 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3890 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3891
2fb92db1
AK		 3892 vmx_segment_cache_clear(vmx);
3893
1ecd50a9
GN		 3894 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3895 vmx->rmode.segs[seg] = *var;
3896 if (seg == VCPU_SREG_TR)
3897 vmcs_write16(sf->selector, var->selector);
3898 else if (var->s)
3899 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3900 goto out;
653e3108 3901 }
1ecd50a9 3902
653e3108
AK		 3903 vmcs_writel(sf->base, var->base);
3904 vmcs_write32(sf->limit, var->limit);
3905 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3906
3907 /*
3908 * Fix the "Accessed" bit in AR field of segment registers for older
3909 * qemu binaries.
3910 * IA32 arch specifies that at the time of processor reset the
3911 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3912 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3913 * state vmexit when "unrestricted guest" mode is turned on.
3914 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3915 * tree. Newer qemu binaries with that qemu fix would not need this
3916 * kvm hack.
3917 */
3918 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3919 var->type |= 0x1; /* Accessed */
3a624e29 3920
f924d66d 3921 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3922
3923out:
98eb2f8b 3924 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3925}
3926
6aa8b732
AK		 3927static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3928{
2fb92db1 3929 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3930
3931 *db = (ar >> 14) & 1;
3932 *l = (ar >> 13) & 1;
3933}
3934
89a27f4d 3935static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3936{
89a27f4d
GN		 3937 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3938 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3939}
3940
89a27f4d 3941static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3942{
89a27f4d
GN		 3943 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3944 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3945}
3946
89a27f4d 3947static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3948{
89a27f4d
GN		 3949 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3950 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3951}
3952
89a27f4d 3953static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3954{
89a27f4d
GN		 3955 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3956 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3957}
3958
648dfaa7
MG		 3959static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3960{
3961 struct kvm_segment var;
3962 u32 ar;
3963
3964 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3965 var.dpl = 0x3;
0647f4aa
GN		 3966 if (seg == VCPU_SREG_CS)
3967 var.type = 0x3;
648dfaa7
MG		 3968 ar = vmx_segment_access_rights(&var);
3969
3970 if (var.base != (var.selector << 4))
3971 return false;
89efbed0 3972 if (var.limit != 0xffff)
648dfaa7 3973 return false;
07f42f5f 3974 if (ar != 0xf3)
648dfaa7
MG		 3975 return false;
3976
3977 return true;
3978}
3979
3980static bool code_segment_valid(struct kvm_vcpu *vcpu)
3981{
3982 struct kvm_segment cs;
3983 unsigned int cs_rpl;
3984
3985 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3986 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3987
1872a3f4
AK		 3988 if (cs.unusable)
3989 return false;
4d283ec9 3990 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3991 return false;
3992 if (!cs.s)
3993 return false;
4d283ec9 3994 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3995 if (cs.dpl > cs_rpl)
3996 return false;
1872a3f4 3997 } else {
648dfaa7
MG		 3998 if (cs.dpl != cs_rpl)
3999 return false;
4000 }
4001 if (!cs.present)
4002 return false;
4003
4004 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4005 return true;
4006}
4007
4008static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4009{
4010 struct kvm_segment ss;
4011 unsigned int ss_rpl;
4012
4013 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 4014 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 4015
1872a3f4
AK		 4016 if (ss.unusable)
4017 return true;
4018 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 4019 return false;
4020 if (!ss.s)
4021 return false;
4022 if (ss.dpl != ss_rpl) /* DPL != RPL */
4023 return false;
4024 if (!ss.present)
4025 return false;
4026
4027 return true;
4028}
4029
4030static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4031{
4032 struct kvm_segment var;
4033 unsigned int rpl;
4034
4035 vmx_get_segment(vcpu, &var, seg);
b32a9918 4036 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 4037
1872a3f4
AK		 4038 if (var.unusable)
4039 return true;
648dfaa7
MG		 4040 if (!var.s)
4041 return false;
4042 if (!var.present)
4043 return false;
4d283ec9 4044 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 4045 if (var.dpl < rpl) /* DPL < RPL */
4046 return false;
4047 }
4048
4049 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4050 * rights flags
4051 */
4052 return true;
4053}
4054
4055static bool tr_valid(struct kvm_vcpu *vcpu)
4056{
4057 struct kvm_segment tr;
4058
4059 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4060
1872a3f4
AK		 4061 if (tr.unusable)
4062 return false;
b32a9918 4063 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 4064 return false;
1872a3f4 4065 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 4066 return false;
4067 if (!tr.present)
4068 return false;
4069
4070 return true;
4071}
4072
4073static bool ldtr_valid(struct kvm_vcpu *vcpu)
4074{
4075 struct kvm_segment ldtr;
4076
4077 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4078
1872a3f4
AK		 4079 if (ldtr.unusable)
4080 return true;
b32a9918 4081 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 4082 return false;
4083 if (ldtr.type != 2)
4084 return false;
4085 if (!ldtr.present)
4086 return false;
4087
4088 return true;
4089}
4090
4091static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4092{
4093 struct kvm_segment cs, ss;
4094
4095 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4096 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4097
b32a9918
NA		 4098 return ((cs.selector & SEGMENT_RPL_MASK) ==
4099 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 4100}
4101
4102/*
4103 * Check if guest state is valid. Returns true if valid, false if
4104 * not.
4105 * We assume that registers are always usable
4106 */
4107static bool guest_state_valid(struct kvm_vcpu *vcpu)
4108{
c5e97c80
GN		 4109 if (enable_unrestricted_guest)
4110 return true;
4111
648dfaa7 4112 /* real mode guest state checks */
f13882d8 4113 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 4114 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4115 return false;
4116 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4117 return false;
4118 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4119 return false;
4120 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4121 return false;
4122 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4123 return false;
4124 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4125 return false;
4126 } else {
4127 /* protected mode guest state checks */
4128 if (!cs_ss_rpl_check(vcpu))
4129 return false;
4130 if (!code_segment_valid(vcpu))
4131 return false;
4132 if (!stack_segment_valid(vcpu))
4133 return false;
4134 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4135 return false;
4136 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4137 return false;
4138 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4139 return false;
4140 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4141 return false;
4142 if (!tr_valid(vcpu))
4143 return false;
4144 if (!ldtr_valid(vcpu))
4145 return false;
4146 }
4147 /* TODO:
4148 * - Add checks on RIP
4149 * - Add checks on RFLAGS
4150 */
4151
4152 return true;
4153}
4154
d77c26fc 4155static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4156{
40dcaa9f 4157 gfn_t fn;
195aefde 4158 u16 data = 0;
1f755a82 4159 int idx, r;
6aa8b732 4160
40dcaa9f 4161 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4162 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 4163 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4164 if (r < 0)
10589a46 4165 goto out;
195aefde 4166 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4167 r = kvm_write_guest_page(kvm, fn++, &data,
4168 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4169 if (r < 0)
10589a46 4170 goto out;
195aefde
IE		 4171 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4172 if (r < 0)
10589a46 4173 goto out;
195aefde
IE		 4174 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4175 if (r < 0)
10589a46 4176 goto out;
195aefde 4177 data = ~0;
10589a46
MT		 4178 r = kvm_write_guest_page(kvm, fn, &data,
4179 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4180 sizeof(u8));
10589a46 4181out:
40dcaa9f 4182 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4183 return r;
6aa8b732
AK		 4184}
4185
b7ebfb05
SY		 4186static int init_rmode_identity_map(struct kvm *kvm)
4187{
f51770ed 4188 int i, idx, r = 0;
b7ebfb05
SY		 4189 pfn_t identity_map_pfn;
4190 u32 tmp;
4191
089d034e 4192 if (!enable_ept)
f51770ed 4193 return 0;
a255d479
TC		 4194
4195 /* Protect kvm->arch.ept_identity_pagetable_done. */
4196 mutex_lock(&kvm->slots_lock);
4197
f51770ed 4198 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4199 goto out2;
a255d479 4200
b927a3ce 4201 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4202
4203 r = alloc_identity_pagetable(kvm);
f51770ed 4204 if (r < 0)
a255d479
TC		 4205 goto out2;
4206
40dcaa9f 4207 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4208 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4209 if (r < 0)
4210 goto out;
4211 /* Set up identity-mapping pagetable for EPT in real mode */
4212 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4213 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4214 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4215 r = kvm_write_guest_page(kvm, identity_map_pfn,
4216 &tmp, i * sizeof(tmp), sizeof(tmp));
4217 if (r < 0)
4218 goto out;
4219 }
4220 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4221
b7ebfb05 4222out:
40dcaa9f 4223 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4224
4225out2:
4226 mutex_unlock(&kvm->slots_lock);
f51770ed 4227 return r;
b7ebfb05
SY		 4228}
4229
6aa8b732
AK		 4230static void seg_setup(int seg)
4231{
772e0318 4232 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4233 unsigned int ar;
6aa8b732
AK		 4234
4235 vmcs_write16(sf->selector, 0);
4236 vmcs_writel(sf->base, 0);
4237 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4238 ar = 0x93;
4239 if (seg == VCPU_SREG_CS)
4240 ar |= 0x08; /* code segment */
3a624e29
NK		 4241
4242 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4243}
4244
f78e0e2e
SY		 4245static int alloc_apic_access_page(struct kvm *kvm)
4246{
4484141a 4247 struct page *page;
f78e0e2e
SY		 4248 int r = 0;
4249
79fac95e 4250 mutex_lock(&kvm->slots_lock);
c24ae0dc 4251 if (kvm->arch.apic_access_page_done)
f78e0e2e 4252 goto out;
1d8007bd
PB		 4253 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4254 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY		 4255 if (r)
4256 goto out;
72dc67a6 4257
73a6d941 4258 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4259 if (is_error_page(page)) {
4260 r = -EFAULT;
4261 goto out;
4262 }
4263
c24ae0dc
TC		 4264 /*
4265 * Do not pin the page in memory, so that memory hot-unplug
4266 * is able to migrate it.
4267 */
4268 put_page(page);
4269 kvm->arch.apic_access_page_done = true;
f78e0e2e 4270out:
79fac95e 4271 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4272 return r;
4273}
4274
b7ebfb05
SY		 4275static int alloc_identity_pagetable(struct kvm *kvm)
4276{
a255d479
TC		 4277 /* Called with kvm->slots_lock held. */
4278
b7ebfb05
SY		 4279 int r = 0;
4280
a255d479
TC		 4281 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4282
1d8007bd
PB		 4283 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4284 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
b7ebfb05 4285
b7ebfb05
SY		 4286 return r;
4287}
4288
991e7a0e 4289static int allocate_vpid(void)
2384d2b3
SY		 4290{
4291 int vpid;
4292
919818ab 4293 if (!enable_vpid)
991e7a0e 4294 return 0;
2384d2b3
SY		 4295 spin_lock(&vmx_vpid_lock);
4296 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 4297 if (vpid < VMX_NR_VPIDS)
2384d2b3 4298 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL		 4299 else
4300 vpid = 0;
2384d2b3 4301 spin_unlock(&vmx_vpid_lock);
991e7a0e 4302 return vpid;
2384d2b3
SY		 4303}
4304
991e7a0e 4305static void free_vpid(int vpid)
cdbecfc3 4306{
991e7a0e 4307 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ		 4308 return;
4309 spin_lock(&vmx_vpid_lock);
991e7a0e 4310 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ		 4311 spin_unlock(&vmx_vpid_lock);
4312}
4313
8d14695f
YZ		 4314#define MSR_TYPE_R 1
4315#define MSR_TYPE_W 2
4316static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4317 u32 msr, int type)
25c5f225 4318{
3e7c73e9 4319 int f = sizeof(unsigned long);
25c5f225
SY		 4320
4321 if (!cpu_has_vmx_msr_bitmap())
4322 return;
4323
4324 /*
4325 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4326 * have the write-low and read-high bitmap offsets the wrong way round.
4327 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4328 */
25c5f225 4329 if (msr <= 0x1fff) {
8d14695f
YZ		 4330 if (type & MSR_TYPE_R)
4331 /* read-low */
4332 __clear_bit(msr, msr_bitmap + 0x000 / f);
4333
4334 if (type & MSR_TYPE_W)
4335 /* write-low */
4336 __clear_bit(msr, msr_bitmap + 0x800 / f);
4337
25c5f225
SY		 4338 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4339 msr &= 0x1fff;
8d14695f
YZ		 4340 if (type & MSR_TYPE_R)
4341 /* read-high */
4342 __clear_bit(msr, msr_bitmap + 0x400 / f);
4343
4344 if (type & MSR_TYPE_W)
4345 /* write-high */
4346 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4347
4348 }
4349}
4350
4351static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4352 u32 msr, int type)
4353{
4354 int f = sizeof(unsigned long);
4355
4356 if (!cpu_has_vmx_msr_bitmap())
4357 return;
4358
4359 /*
4360 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4361 * have the write-low and read-high bitmap offsets the wrong way round.
4362 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4363 */
4364 if (msr <= 0x1fff) {
4365 if (type & MSR_TYPE_R)
4366 /* read-low */
4367 __set_bit(msr, msr_bitmap + 0x000 / f);
4368
4369 if (type & MSR_TYPE_W)
4370 /* write-low */
4371 __set_bit(msr, msr_bitmap + 0x800 / f);
4372
4373 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4374 msr &= 0x1fff;
4375 if (type & MSR_TYPE_R)
4376 /* read-high */
4377 __set_bit(msr, msr_bitmap + 0x400 / f);
4378
4379 if (type & MSR_TYPE_W)
4380 /* write-high */
4381 __set_bit(msr, msr_bitmap + 0xc00 / f);
4382
25c5f225 4383 }
25c5f225
SY		 4384}
4385
f2b93280
WV		 4386/*
4387 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4388 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4389 */
4390static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4391 unsigned long *msr_bitmap_nested,
4392 u32 msr, int type)
4393{
4394 int f = sizeof(unsigned long);
4395
4396 if (!cpu_has_vmx_msr_bitmap()) {
4397 WARN_ON(1);
4398 return;
4399 }
4400
4401 /*
4402 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4403 * have the write-low and read-high bitmap offsets the wrong way round.
4404 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4405 */
4406 if (msr <= 0x1fff) {
4407 if (type & MSR_TYPE_R &&
4408 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4409 /* read-low */
4410 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4411
4412 if (type & MSR_TYPE_W &&
4413 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4414 /* write-low */
4415 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4416
4417 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4418 msr &= 0x1fff;
4419 if (type & MSR_TYPE_R &&
4420 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4421 /* read-high */
4422 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4423
4424 if (type & MSR_TYPE_W &&
4425 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4426 /* write-high */
4427 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4428
4429 }
4430}
4431
5897297b
AK		 4432static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4433{
4434 if (!longmode_only)
8d14695f
YZ		 4435 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4436 msr, MSR_TYPE_R | MSR_TYPE_W);
4437 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4438 msr, MSR_TYPE_R | MSR_TYPE_W);
4439}
4440
4441static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4442{
4443 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4444 msr, MSR_TYPE_R);
4445 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4446 msr, MSR_TYPE_R);
4447}
4448
4449static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4450{
4451 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4452 msr, MSR_TYPE_R);
4453 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4454 msr, MSR_TYPE_R);
4455}
4456
4457static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4458{
4459 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4460 msr, MSR_TYPE_W);
4461 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4462 msr, MSR_TYPE_W);
5897297b
AK		 4463}
4464
d50ab6c1
PB		 4465static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4466{
35754c98 4467 return enable_apicv && lapic_in_kernel(vcpu);
d50ab6c1
PB		 4468}
4469
705699a1
WV		 4470static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4471{
4472 struct vcpu_vmx *vmx = to_vmx(vcpu);
4473 int max_irr;
4474 void *vapic_page;
4475 u16 status;
4476
4477 if (vmx->nested.pi_desc &&
4478 vmx->nested.pi_pending) {
4479 vmx->nested.pi_pending = false;
4480 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4481 return 0;
4482
4483 max_irr = find_last_bit(
4484 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4485
4486 if (max_irr == 256)
4487 return 0;
4488
4489 vapic_page = kmap(vmx->nested.virtual_apic_page);
4490 if (!vapic_page) {
4491 WARN_ON(1);
4492 return -ENOMEM;
4493 }
4494 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4495 kunmap(vmx->nested.virtual_apic_page);
4496
4497 status = vmcs_read16(GUEST_INTR_STATUS);
4498 if ((u8)max_irr > ((u8)status & 0xff)) {
4499 status &= ~0xff;
4500 status |= (u8)max_irr;
4501 vmcs_write16(GUEST_INTR_STATUS, status);
4502 }
4503 }
4504 return 0;
4505}
4506
21bc8dc5
RK		 4507static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4508{
4509#ifdef CONFIG_SMP
4510 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6
FW		 4511 struct vcpu_vmx *vmx = to_vmx(vcpu);
4512
4513 /*
4514 * Currently, we don't support urgent interrupt,
4515 * all interrupts are recognized as non-urgent
4516 * interrupt, so we cannot post interrupts when
4517 * 'SN' is set.
4518 *
4519 * If the vcpu is in guest mode, it means it is
4520 * running instead of being scheduled out and
4521 * waiting in the run queue, and that's the only
4522 * case when 'SN' is set currently, warning if
4523 * 'SN' is set.
4524 */
4525 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4526
21bc8dc5
RK		 4527 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4528 POSTED_INTR_VECTOR);
4529 return true;
4530 }
4531#endif
4532 return false;
4533}
4534
705699a1
WV		 4535static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4536 int vector)
4537{
4538 struct vcpu_vmx *vmx = to_vmx(vcpu);
4539
4540 if (is_guest_mode(vcpu) &&
4541 vector == vmx->nested.posted_intr_nv) {
4542 /* the PIR and ON have been set by L1. */
21bc8dc5 4543 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV		 4544 /*
4545 * If a posted intr is not recognized by hardware,
4546 * we will accomplish it in the next vmentry.
4547 */
4548 vmx->nested.pi_pending = true;
4549 kvm_make_request(KVM_REQ_EVENT, vcpu);
4550 return 0;
4551 }
4552 return -1;
4553}
a20ed54d
YZ		 4554/*
4555 * Send interrupt to vcpu via posted interrupt way.
4556 * 1. If target vcpu is running(non-root mode), send posted interrupt
4557 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4558 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4559 * interrupt from PIR in next vmentry.
4560 */
4561static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4562{
4563 struct vcpu_vmx *vmx = to_vmx(vcpu);
4564 int r;
4565
705699a1
WV		 4566 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4567 if (!r)
4568 return;
4569
a20ed54d
YZ		 4570 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4571 return;
4572
4573 r = pi_test_and_set_on(&vmx->pi_desc);
4574 kvm_make_request(KVM_REQ_EVENT, vcpu);
21bc8dc5 4575 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ		 4576 kvm_vcpu_kick(vcpu);
4577}
4578
4579static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4580{
4581 struct vcpu_vmx *vmx = to_vmx(vcpu);
4582
4583 if (!pi_test_and_clear_on(&vmx->pi_desc))
4584 return;
4585
4586 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4587}
4588
4589static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4590{
4591 return;
4592}
4593
a3a8ff8e
NHE		 4594/*
4595 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4596 * will not change in the lifetime of the guest.
4597 * Note that host-state that does change is set elsewhere. E.g., host-state
4598 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4599 */
a547c6db 4600static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4601{
4602 u32 low32, high32;
4603 unsigned long tmpl;
4604 struct desc_ptr dt;
d974baa3 4605 unsigned long cr4;
a3a8ff8e 4606
b1a74bf8 4607 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4608 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4609
d974baa3 4610 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 4611 cr4 = cr4_read_shadow();
d974baa3
AL		 4612 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4613 vmx->host_state.vmcs_host_cr4 = cr4;
4614
a3a8ff8e 4615 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4616#ifdef CONFIG_X86_64
4617 /*
4618 * Load null selectors, so we can avoid reloading them in
4619 * __vmx_load_host_state(), in case userspace uses the null selectors
4620 * too (the expected case).
4621 */
4622 vmcs_write16(HOST_DS_SELECTOR, 0);
4623 vmcs_write16(HOST_ES_SELECTOR, 0);
4624#else
a3a8ff8e
NHE		 4625 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4626 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4627#endif
a3a8ff8e
NHE		 4628 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4629 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4630
4631 native_store_idt(&dt);
4632 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4633 vmx->host_idt_base = dt.address;
a3a8ff8e 4634
83287ea4 4635 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4636
4637 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4638 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4639 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4640 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4641
4642 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4643 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4644 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4645 }
4646}
4647
bf8179a0
NHE		 4648static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4649{
4650 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4651 if (enable_ept)
4652 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4653 if (is_guest_mode(&vmx->vcpu))
4654 vmx->vcpu.arch.cr4_guest_owned_bits &=
4655 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4656 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4657}
4658
01e439be
YZ		 4659static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4660{
4661 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4662
35754c98 4663 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
01e439be
YZ		 4664 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4665 return pin_based_exec_ctrl;
4666}
4667
bf8179a0
NHE		 4668static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4669{
4670 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4671
4672 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4673 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4674
35754c98 4675 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE		 4676 exec_control &= ~CPU_BASED_TPR_SHADOW;
4677#ifdef CONFIG_X86_64
4678 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4679 CPU_BASED_CR8_LOAD_EXITING;
4680#endif
4681 }
4682 if (!enable_ept)
4683 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4684 CPU_BASED_CR3_LOAD_EXITING |
4685 CPU_BASED_INVLPG_EXITING;
4686 return exec_control;
4687}
4688
4689static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4690{
4691 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 4692 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE		 4693 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4694 if (vmx->vpid == 0)
4695 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4696 if (!enable_ept) {
4697 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4698 enable_unrestricted_guest = 0;
ad756a16
MJ		 4699 /* Enable INVPCID for non-ept guests may cause performance regression. */
4700 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4701 }
4702 if (!enable_unrestricted_guest)
4703 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4704 if (!ple_gap)
4705 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
35754c98 4706 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
c7c9c56c
YZ		 4707 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4708 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4709 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4710 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4711 (handle_vmptrld).
4712 We can NOT enable shadow_vmcs here because we don't have yet
4713 a current VMCS12
4714 */
4715 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH		 4716
4717 if (!enable_pml)
4718 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 4719
8b3e34e4
XG		 4720 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4721 exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4722
bf8179a0
NHE		 4723 return exec_control;
4724}
4725
ce88decf
XG		 4726static void ept_set_mmio_spte_mask(void)
4727{
4728 /*
4729 * EPT Misconfigurations can be generated if the value of bits 2:0
4730 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4731 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4732 * spte.
4733 */
885032b9 4734 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4735}
4736
f53cd63c 4737#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4738/*
4739 * Sets up the vmcs for emulated real mode.
4740 */
8b9cf98c 4741static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4742{
2e4ce7f5 4743#ifdef CONFIG_X86_64
6aa8b732 4744 unsigned long a;
2e4ce7f5 4745#endif
6aa8b732 4746 int i;
6aa8b732 4747
6aa8b732 4748 /* I/O */
3e7c73e9
AK		 4749 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4750 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4751
4607c2d7
AG		 4752 if (enable_shadow_vmcs) {
4753 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4754 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4755 }
25c5f225 4756 if (cpu_has_vmx_msr_bitmap())
5897297b 4757 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4758
6aa8b732
AK		 4759 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4760
6aa8b732 4761 /* Control */
01e439be 4762 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4763
bf8179a0 4764 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4765
8b3e34e4 4766 if (cpu_has_secondary_exec_ctrls())
bf8179a0
NHE		 4767 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4768 vmx_secondary_exec_control(vmx));
f78e0e2e 4769
35754c98 4770 if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
c7c9c56c
YZ		 4771 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4772 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4773 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4774 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4775
4776 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4777
4778 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4779 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4780 }
4781
4b8d54f9
ZE		 4782 if (ple_gap) {
4783 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4784 vmx->ple_window = ple_window;
4785 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4786 }
4787
c3707958
XG		 4788 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4789 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4790 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4791
9581d442
AK		 4792 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4793 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4794 vmx_set_constant_host_state(vmx);
05b3e0c2 4795#ifdef CONFIG_X86_64
6aa8b732
AK		 4796 rdmsrl(MSR_FS_BASE, a);
4797 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4798 rdmsrl(MSR_GS_BASE, a);
4799 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4800#else
4801 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4802 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4803#endif
4804
2cc51560
ED		 4805 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4806 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4807 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4808 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4809 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4810
74545705
RK		 4811 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4812 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4813
03916db9 4814 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4815 u32 index = vmx_msr_index[i];
4816 u32 data_low, data_high;
a2fa3e9f 4817 int j = vmx->nmsrs;
6aa8b732
AK		 4818
4819 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4820 continue;
432bd6cb
AK		 4821 if (wrmsr_safe(index, data_low, data_high) < 0)
4822 continue;
26bb0981
AK		 4823 vmx->guest_msrs[j].index = i;
4824 vmx->guest_msrs[j].data = 0;
d5696725 4825 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4826 ++vmx->nmsrs;
6aa8b732 4827 }
6aa8b732 4828
2961e876
GN		 4829
4830 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4831
4832 /* 22.2.1, 20.8.1 */
2961e876 4833 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4834
e00c8cf2 4835 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4836 set_cr4_guest_host_mask(vmx);
e00c8cf2 4837
f53cd63c
WL		 4838 if (vmx_xsaves_supported())
4839 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4840
e00c8cf2
AK		 4841 return 0;
4842}
4843
d28bc9dd 4844static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4845{
4846 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4847 struct msr_data apic_base_msr;
d28bc9dd 4848 u64 cr0;
e00c8cf2 4849
7ffd92c5 4850 vmx->rmode.vm86_active = 0;
e00c8cf2 4851
3b86cd99
JK		 4852 vmx->soft_vnmi_blocked = 0;
4853
ad312c7c 4854 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 4855 kvm_set_cr8(vcpu, 0);
4856
4857 if (!init_event) {
4858 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4859 MSR_IA32_APICBASE_ENABLE;
4860 if (kvm_vcpu_is_reset_bsp(vcpu))
4861 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4862 apic_base_msr.host_initiated = true;
4863 kvm_set_apic_base(vcpu, &apic_base_msr);
4864 }
e00c8cf2 4865
2fb92db1
AK		 4866 vmx_segment_cache_clear(vmx);
4867
5706be0d 4868 seg_setup(VCPU_SREG_CS);
66450a21 4869 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4870 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4871
4872 seg_setup(VCPU_SREG_DS);
4873 seg_setup(VCPU_SREG_ES);
4874 seg_setup(VCPU_SREG_FS);
4875 seg_setup(VCPU_SREG_GS);
4876 seg_setup(VCPU_SREG_SS);
4877
4878 vmcs_write16(GUEST_TR_SELECTOR, 0);
4879 vmcs_writel(GUEST_TR_BASE, 0);
4880 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4881 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4882
4883 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4884 vmcs_writel(GUEST_LDTR_BASE, 0);
4885 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4886 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4887
d28bc9dd
NA		 4888 if (!init_event) {
4889 vmcs_write32(GUEST_SYSENTER_CS, 0);
4890 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4891 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4892 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4893 }
e00c8cf2
AK		 4894
4895 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4896 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4897
e00c8cf2
AK		 4898 vmcs_writel(GUEST_GDTR_BASE, 0);
4899 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4900
4901 vmcs_writel(GUEST_IDTR_BASE, 0);
4902 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4903
443381a8 4904 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4905 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4906 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4907
e00c8cf2
AK		 4908 setup_msrs(vmx);
4909
6aa8b732
AK		 4910 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4911
d28bc9dd 4912 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4913 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4914 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4915 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4916 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4917 vmcs_write32(TPR_THRESHOLD, 0);
4918 }
4919
a73896cb 4920 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4921
35754c98 4922 if (vmx_cpu_uses_apicv(vcpu))
01e439be
YZ		 4923 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4924
2384d2b3
SY		 4925 if (vmx->vpid != 0)
4926 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4927
d28bc9dd
NA		 4928 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4929 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4930 vmx->vcpu.arch.cr0 = cr0;
4931 vmx_set_cr4(vcpu, 0);
5690891b 4932 vmx_set_efer(vcpu, 0);
d28bc9dd
NA		 4933 vmx_fpu_activate(vcpu);
4934 update_exception_bitmap(vcpu);
6aa8b732 4935
dd5f5341 4936 vpid_sync_context(vmx->vpid);
6aa8b732
AK		 4937}
4938
b6f1250e
NHE		 4939/*
4940 * In nested virtualization, check if L1 asked to exit on external interrupts.
4941 * For most existing hypervisors, this will always return true.
4942 */
4943static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4944{
4945 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4946 PIN_BASED_EXT_INTR_MASK;
4947}
4948
77b0f5d6
BD		 4949/*
4950 * In nested virtualization, check if L1 has set
4951 * VM_EXIT_ACK_INTR_ON_EXIT
4952 */
4953static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4954{
4955 return get_vmcs12(vcpu)->vm_exit_controls &
4956 VM_EXIT_ACK_INTR_ON_EXIT;
4957}
4958
ea8ceb83
JK		 4959static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4960{
4961 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4962 PIN_BASED_NMI_EXITING;
4963}
4964
c9a7953f 4965static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4966{
4967 u32 cpu_based_vm_exec_control;
730dca42 4968
3b86cd99
JK		 4969 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4970 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4971 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4972}
4973
c9a7953f 4974static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4975{
4976 u32 cpu_based_vm_exec_control;
4977
c9a7953f
JK		 4978 if (!cpu_has_virtual_nmis() ||
4979 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4980 enable_irq_window(vcpu);
4981 return;
4982 }
3b86cd99
JK		 4983
4984 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4985 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4986 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4987}
4988
66fd3f7f 4989static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4990{
9c8cba37 4991 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4992 uint32_t intr;
4993 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4994
229456fc 4995 trace_kvm_inj_virq(irq);
2714d1d3 4996
fa89a817 4997 ++vcpu->stat.irq_injections;
7ffd92c5 4998 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4999 int inc_eip = 0;
5000 if (vcpu->arch.interrupt.soft)
5001 inc_eip = vcpu->arch.event_exit_inst_len;
5002 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 5003 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 5004 return;
5005 }
66fd3f7f
GN		 5006 intr = irq | INTR_INFO_VALID_MASK;
5007 if (vcpu->arch.interrupt.soft) {
5008 intr |= INTR_TYPE_SOFT_INTR;
5009 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5010 vmx->vcpu.arch.event_exit_inst_len);
5011 } else
5012 intr |= INTR_TYPE_EXT_INTR;
5013 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 5014}
5015
f08864b4
SY		 5016static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5017{
66a5a347
JK		 5018 struct vcpu_vmx *vmx = to_vmx(vcpu);
5019
0b6ac343
NHE		 5020 if (is_guest_mode(vcpu))
5021 return;
5022
3b86cd99
JK		 5023 if (!cpu_has_virtual_nmis()) {
5024 /*
5025 * Tracking the NMI-blocked state in software is built upon
5026 * finding the next open IRQ window. This, in turn, depends on
5027 * well-behaving guests: They have to keep IRQs disabled at
5028 * least as long as the NMI handler runs. Otherwise we may
5029 * cause NMI nesting, maybe breaking the guest. But as this is
5030 * highly unlikely, we can live with the residual risk.
5031 */
5032 vmx->soft_vnmi_blocked = 1;
5033 vmx->vnmi_blocked_time = 0;
5034 }
5035
487b391d 5036 ++vcpu->stat.nmi_injections;
9d58b931 5037 vmx->nmi_known_unmasked = false;
7ffd92c5 5038 if (vmx->rmode.vm86_active) {
71f9833b 5039 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 5040 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 5041 return;
5042 }
f08864b4
SY		 5043 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5044 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 5045}
5046
3cfc3092
JK		 5047static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5048{
5049 if (!cpu_has_virtual_nmis())
5050 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 5051 if (to_vmx(vcpu)->nmi_known_unmasked)
5052 return false;
c332c83a 5053 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 5054}
5055
5056static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5057{
5058 struct vcpu_vmx *vmx = to_vmx(vcpu);
5059
5060 if (!cpu_has_virtual_nmis()) {
5061 if (vmx->soft_vnmi_blocked != masked) {
5062 vmx->soft_vnmi_blocked = masked;
5063 vmx->vnmi_blocked_time = 0;
5064 }
5065 } else {
9d58b931 5066 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 5067 if (masked)
5068 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5069 GUEST_INTR_STATE_NMI);
5070 else
5071 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5072 GUEST_INTR_STATE_NMI);
5073 }
5074}
5075
2505dc9f
JK		 5076static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5077{
b6b8a145
JK		 5078 if (to_vmx(vcpu)->nested.nested_run_pending)
5079 return 0;
ea8ceb83 5080
2505dc9f
JK		 5081 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5082 return 0;
5083
5084 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5085 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5086 | GUEST_INTR_STATE_NMI));
5087}
5088
78646121
GN		 5089static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5090{
b6b8a145
JK		 5091 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5092 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 5093 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5094 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 5095}
5096
cbc94022
IE		 5097static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5098{
5099 int ret;
cbc94022 5100
1d8007bd
PB		 5101 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5102 PAGE_SIZE * 3);
cbc94022
IE		 5103 if (ret)
5104 return ret;
bfc6d222 5105 kvm->arch.tss_addr = addr;
1f755a82 5106 return init_rmode_tss(kvm);
cbc94022
IE		 5107}
5108
0ca1b4f4 5109static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 5110{
77ab6db0 5111 switch (vec) {
77ab6db0 5112 case BP_VECTOR:
c573cd22
JK		 5113 /*
5114 * Update instruction length as we may reinject the exception
5115 * from user space while in guest debugging mode.
5116 */
5117 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5118 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 5119 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 5120 return false;
5121 /* fall through */
5122 case DB_VECTOR:
5123 if (vcpu->guest_debug &
5124 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5125 return false;
d0bfb940
JK		 5126 /* fall through */
5127 case DE_VECTOR:
77ab6db0
JK		 5128 case OF_VECTOR:
5129 case BR_VECTOR:
5130 case UD_VECTOR:
5131 case DF_VECTOR:
5132 case SS_VECTOR:
5133 case GP_VECTOR:
5134 case MF_VECTOR:
0ca1b4f4
GN		 5135 return true;
5136 break;
77ab6db0 5137 }
0ca1b4f4
GN		 5138 return false;
5139}
5140
5141static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5142 int vec, u32 err_code)
5143{
5144 /*
5145 * Instruction with address size override prefix opcode 0x67
5146 * Cause the #SS fault with 0 error code in VM86 mode.
5147 */
5148 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5149 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5150 if (vcpu->arch.halt_request) {
5151 vcpu->arch.halt_request = 0;
5cb56059 5152 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 5153 }
5154 return 1;
5155 }
5156 return 0;
5157 }
5158
5159 /*
5160 * Forward all other exceptions that are valid in real mode.
5161 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5162 * the required debugging infrastructure rework.
5163 */
5164 kvm_queue_exception(vcpu, vec);
5165 return 1;
6aa8b732
AK		 5166}
5167
a0861c02
AK		 5168/*
5169 * Trigger machine check on the host. We assume all the MSRs are already set up
5170 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5171 * We pass a fake environment to the machine check handler because we want
5172 * the guest to be always treated like user space, no matter what context
5173 * it used internally.
5174 */
5175static void kvm_machine_check(void)
5176{
5177#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5178 struct pt_regs regs = {
5179 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5180 .flags = X86_EFLAGS_IF,
5181 };
5182
5183 do_machine_check(&regs, 0);
5184#endif
5185}
5186
851ba692 5187static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 5188{
5189 /* already handled by vcpu_run */
5190 return 1;
5191}
5192
851ba692 5193static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5194{
1155f76a 5195 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5196 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5197 u32 intr_info, ex_no, error_code;
42dbaa5a 5198 unsigned long cr2, rip, dr6;
6aa8b732
AK		 5199 u32 vect_info;
5200 enum emulation_result er;
5201
1155f76a 5202 vect_info = vmx->idt_vectoring_info;
88786475 5203 intr_info = vmx->exit_intr_info;
6aa8b732 5204
a0861c02 5205 if (is_machine_check(intr_info))
851ba692 5206 return handle_machine_check(vcpu);
a0861c02 5207
e4a41889 5208 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 5209 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 5210
5211 if (is_no_device(intr_info)) {
5fd86fcf 5212 vmx_fpu_activate(vcpu);
2ab455cc
AL		 5213 return 1;
5214 }
5215
7aa81cc0 5216 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK		 5217 if (is_guest_mode(vcpu)) {
5218 kvm_queue_exception(vcpu, UD_VECTOR);
5219 return 1;
5220 }
51d8b661 5221 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5222 if (er != EMULATE_DONE)
7ee5d940 5223 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 5224 return 1;
5225 }
5226
6aa8b732 5227 error_code = 0;
2e11384c 5228 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5229 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 5230
5231 /*
5232 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5233 * MMIO, it is better to report an internal error.
5234 * See the comments in vmx_handle_exit.
5235 */
5236 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5237 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5238 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5239 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5240 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 5241 vcpu->run->internal.data[0] = vect_info;
5242 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5243 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 5244 return 0;
5245 }
5246
6aa8b732 5247 if (is_page_fault(intr_info)) {
1439442c 5248 /* EPT won't cause page fault directly */
cf3ace79 5249 BUG_ON(enable_ept);
6aa8b732 5250 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5251 trace_kvm_page_fault(cr2, error_code);
5252
3298b75c 5253 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5254 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5255 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5256 }
5257
d0bfb940 5258 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5259
5260 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5261 return handle_rmode_exception(vcpu, ex_no, error_code);
5262
42dbaa5a
JK		 5263 switch (ex_no) {
5264 case DB_VECTOR:
5265 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5266 if (!(vcpu->guest_debug &
5267 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5268 vcpu->arch.dr6 &= ~15;
6f43ed01 5269 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5270 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5271 skip_emulated_instruction(vcpu);
5272
42dbaa5a
JK		 5273 kvm_queue_exception(vcpu, DB_VECTOR);
5274 return 1;
5275 }
5276 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5277 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5278 /* fall through */
5279 case BP_VECTOR:
c573cd22
JK		 5280 /*
5281 * Update instruction length as we may reinject #BP from
5282 * user space while in guest debugging mode. Reading it for
5283 * #DB as well causes no harm, it is not used in that case.
5284 */
5285 vmx->vcpu.arch.event_exit_inst_len =
5286 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5287 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5288 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5289 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5290 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5291 break;
5292 default:
d0bfb940
JK		 5293 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5294 kvm_run->ex.exception = ex_no;
5295 kvm_run->ex.error_code = error_code;
42dbaa5a 5296 break;
6aa8b732 5297 }
6aa8b732
AK		 5298 return 0;
5299}
5300
851ba692 5301static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5302{
1165f5fe 5303 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5304 return 1;
5305}
5306
851ba692 5307static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5308{
851ba692 5309 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5310 return 0;
5311}
6aa8b732 5312
851ba692 5313static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5314{
bfdaab09 5315 unsigned long exit_qualification;
34c33d16 5316 int size, in, string;
039576c0 5317 unsigned port;
6aa8b732 5318
bfdaab09 5319 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5320 string = (exit_qualification & 16) != 0;
cf8f70bf 5321 in = (exit_qualification & 8) != 0;
e70669ab 5322
cf8f70bf 5323 ++vcpu->stat.io_exits;
e70669ab 5324
cf8f70bf 5325 if (string || in)
51d8b661 5326 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5327
cf8f70bf
GN		 5328 port = exit_qualification >> 16;
5329 size = (exit_qualification & 7) + 1;
e93f36bc 5330 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5331
5332 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5333}
5334
102d8325
IM		 5335static void
5336vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5337{
5338 /*
5339 * Patch in the VMCALL instruction:
5340 */
5341 hypercall[0] = 0x0f;
5342 hypercall[1] = 0x01;
5343 hypercall[2] = 0xc1;
102d8325
IM		 5344}
5345
b9c237bb 5346static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5347{
5348 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5349 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5350
b9c237bb 5351 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5352 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5353 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5354 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5355 return (val & always_on) == always_on;
5356}
5357
0fa06071 5358/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5359static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5360{
eeadf9e7 5361 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5362 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5363 unsigned long orig_val = val;
5364
eeadf9e7
NHE		 5365 /*
5366 * We get here when L2 changed cr0 in a way that did not change
5367 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5368 * but did change L0 shadowed bits. So we first calculate the
5369 * effective cr0 value that L1 would like to write into the
5370 * hardware. It consists of the L2-owned bits from the new
5371 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5372 */
1a0d74e6
JK		 5373 val = (val & ~vmcs12->cr0_guest_host_mask) |
5374 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5375
b9c237bb 5376 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5377 return 1;
1a0d74e6
JK		 5378
5379 if (kvm_set_cr0(vcpu, val))
5380 return 1;
5381 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5382 return 0;
1a0d74e6
JK		 5383 } else {
5384 if (to_vmx(vcpu)->nested.vmxon &&
5385 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5386 return 1;
eeadf9e7 5387 return kvm_set_cr0(vcpu, val);
1a0d74e6 5388 }
eeadf9e7
NHE		 5389}
5390
5391static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5392{
5393 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5394 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5395 unsigned long orig_val = val;
5396
5397 /* analogously to handle_set_cr0 */
5398 val = (val & ~vmcs12->cr4_guest_host_mask) |
5399 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5400 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5401 return 1;
1a0d74e6 5402 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5403 return 0;
5404 } else
5405 return kvm_set_cr4(vcpu, val);
5406}
5407
5408/* called to set cr0 as approriate for clts instruction exit. */
5409static void handle_clts(struct kvm_vcpu *vcpu)
5410{
5411 if (is_guest_mode(vcpu)) {
5412 /*
5413 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5414 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5415 * just pretend it's off (also in arch.cr0 for fpu_activate).
5416 */
5417 vmcs_writel(CR0_READ_SHADOW,
5418 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5419 vcpu->arch.cr0 &= ~X86_CR0_TS;
5420 } else
5421 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5422}
5423
851ba692 5424static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5425{
229456fc 5426 unsigned long exit_qualification, val;
6aa8b732
AK		 5427 int cr;
5428 int reg;
49a9b07e 5429 int err;
6aa8b732 5430
bfdaab09 5431 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5432 cr = exit_qualification & 15;
5433 reg = (exit_qualification >> 8) & 15;
5434 switch ((exit_qualification >> 4) & 3) {
5435 case 0: /* mov to cr */
1e32c079 5436 val = kvm_register_readl(vcpu, reg);
229456fc 5437 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5438 switch (cr) {
5439 case 0:
eeadf9e7 5440 err = handle_set_cr0(vcpu, val);
db8fcefa 5441 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5442 return 1;
5443 case 3:
2390218b 5444 err = kvm_set_cr3(vcpu, val);
db8fcefa 5445 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5446 return 1;
5447 case 4:
eeadf9e7 5448 err = handle_set_cr4(vcpu, val);
db8fcefa 5449 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5450 return 1;
0a5fff19
GN		 5451 case 8: {
5452 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5453 u8 cr8 = (u8)val;
eea1cff9 5454 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5455 kvm_complete_insn_gp(vcpu, err);
35754c98 5456 if (lapic_in_kernel(vcpu))
0a5fff19
GN		 5457 return 1;
5458 if (cr8_prev <= cr8)
5459 return 1;
851ba692 5460 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5461 return 0;
5462 }
4b8073e4 5463 }
6aa8b732 5464 break;
25c4c276 5465 case 2: /* clts */
eeadf9e7 5466 handle_clts(vcpu);
4d4ec087 5467 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5468 skip_emulated_instruction(vcpu);
6b52d186 5469 vmx_fpu_activate(vcpu);
25c4c276 5470 return 1;
6aa8b732
AK		 5471 case 1: /*mov from cr*/
5472 switch (cr) {
5473 case 3:
9f8fe504
AK		 5474 val = kvm_read_cr3(vcpu);
5475 kvm_register_write(vcpu, reg, val);
5476 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5477 skip_emulated_instruction(vcpu);
5478 return 1;
5479 case 8:
229456fc
MT		 5480 val = kvm_get_cr8(vcpu);
5481 kvm_register_write(vcpu, reg, val);
5482 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5483 skip_emulated_instruction(vcpu);
5484 return 1;
5485 }
5486 break;
5487 case 3: /* lmsw */
a1f83a74 5488 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5489 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5490 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5491
5492 skip_emulated_instruction(vcpu);
5493 return 1;
5494 default:
5495 break;
5496 }
851ba692 5497 vcpu->run->exit_reason = 0;
a737f256 5498 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5499 (int)(exit_qualification >> 4) & 3, cr);
5500 return 0;
5501}
5502
851ba692 5503static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5504{
bfdaab09 5505 unsigned long exit_qualification;
16f8a6f9
NA		 5506 int dr, dr7, reg;
5507
5508 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5509 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5510
5511 /* First, if DR does not exist, trigger UD */
5512 if (!kvm_require_dr(vcpu, dr))
5513 return 1;
6aa8b732 5514
f2483415 5515 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5516 if (!kvm_require_cpl(vcpu, 0))
5517 return 1;
16f8a6f9
NA		 5518 dr7 = vmcs_readl(GUEST_DR7);
5519 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5520 /*
5521 * As the vm-exit takes precedence over the debug trap, we
5522 * need to emulate the latter, either for the host or the
5523 * guest debugging itself.
5524 */
5525 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5526 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5527 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5528 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5529 vcpu->run->debug.arch.exception = DB_VECTOR;
5530 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5531 return 0;
5532 } else {
7305eb5d 5533 vcpu->arch.dr6 &= ~15;
6f43ed01 5534 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5535 kvm_queue_exception(vcpu, DB_VECTOR);
5536 return 1;
5537 }
5538 }
5539
81908bf4
PB		 5540 if (vcpu->guest_debug == 0) {
5541 u32 cpu_based_vm_exec_control;
5542
5543 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5544 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5545 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5546
5547 /*
5548 * No more DR vmexits; force a reload of the debug registers
5549 * and reenter on this instruction. The next vmexit will
5550 * retrieve the full state of the debug registers.
5551 */
5552 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5553 return 1;
5554 }
5555
42dbaa5a
JK		 5556 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5557 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5558 unsigned long val;
4c4d563b
JK		 5559
5560 if (kvm_get_dr(vcpu, dr, &val))
5561 return 1;
5562 kvm_register_write(vcpu, reg, val);
020df079 5563 } else
5777392e 5564 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5565 return 1;
5566
6aa8b732
AK		 5567 skip_emulated_instruction(vcpu);
5568 return 1;
5569}
5570
73aaf249
JK		 5571static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5572{
5573 return vcpu->arch.dr6;
5574}
5575
5576static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5577{
5578}
5579
81908bf4
PB		 5580static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5581{
5582 u32 cpu_based_vm_exec_control;
5583
5584 get_debugreg(vcpu->arch.db[0], 0);
5585 get_debugreg(vcpu->arch.db[1], 1);
5586 get_debugreg(vcpu->arch.db[2], 2);
5587 get_debugreg(vcpu->arch.db[3], 3);
5588 get_debugreg(vcpu->arch.dr6, 6);
5589 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5590
5591 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5592
5593 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5594 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5595 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5596}
5597
020df079
GN		 5598static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5599{
5600 vmcs_writel(GUEST_DR7, val);
5601}
5602
851ba692 5603static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5604{
06465c5a
AK		 5605 kvm_emulate_cpuid(vcpu);
5606 return 1;
6aa8b732
AK		 5607}
5608
851ba692 5609static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5610{
ad312c7c 5611 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 5612 struct msr_data msr_info;
6aa8b732 5613
609e36d3
PB		 5614 msr_info.index = ecx;
5615 msr_info.host_initiated = false;
5616 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 5617 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5618 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5619 return 1;
5620 }
5621
609e36d3 5622 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 5623
6aa8b732 5624 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB		 5625 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5626 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6aa8b732
AK		 5627 skip_emulated_instruction(vcpu);
5628 return 1;
5629}
5630
851ba692 5631static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5632{
8fe8ab46 5633 struct msr_data msr;
ad312c7c
ZX		 5634 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5635 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5636 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5637
8fe8ab46
WA		 5638 msr.data = data;
5639 msr.index = ecx;
5640 msr.host_initiated = false;
854e8bb1 5641 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5642 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5643 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5644 return 1;
5645 }
5646
59200273 5647 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5648 skip_emulated_instruction(vcpu);
5649 return 1;
5650}
5651
851ba692 5652static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5653{
3842d135 5654 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5655 return 1;
5656}
5657
851ba692 5658static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5659{
85f455f7
ED		 5660 u32 cpu_based_vm_exec_control;
5661
5662 /* clear pending irq */
5663 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5664 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5665 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5666
3842d135
AK		 5667 kvm_make_request(KVM_REQ_EVENT, vcpu);
5668
a26bf12a 5669 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 5670 return 1;
5671}
5672
851ba692 5673static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 5674{
d3bef15f 5675 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5676}
5677
851ba692 5678static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5679{
7aa81cc0
AL		 5680 kvm_emulate_hypercall(vcpu);
5681 return 1;
c21415e8
IM		 5682}
5683
ec25d5e6
GN		 5684static int handle_invd(struct kvm_vcpu *vcpu)
5685{
51d8b661 5686 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5687}
5688
851ba692 5689static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5690{
f9c617f6 5691 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5692
5693 kvm_mmu_invlpg(vcpu, exit_qualification);
5694 skip_emulated_instruction(vcpu);
5695 return 1;
5696}
5697
fee84b07
AK		 5698static int handle_rdpmc(struct kvm_vcpu *vcpu)
5699{
5700 int err;
5701
5702 err = kvm_rdpmc(vcpu);
5703 kvm_complete_insn_gp(vcpu, err);
5704
5705 return 1;
5706}
5707
851ba692 5708static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5709{
f5f48ee1 5710 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5711 return 1;
5712}
5713
2acf923e
DC		 5714static int handle_xsetbv(struct kvm_vcpu *vcpu)
5715{
5716 u64 new_bv = kvm_read_edx_eax(vcpu);
5717 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5718
5719 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5720 skip_emulated_instruction(vcpu);
5721 return 1;
5722}
5723
f53cd63c
WL		 5724static int handle_xsaves(struct kvm_vcpu *vcpu)
5725{
5726 skip_emulated_instruction(vcpu);
5727 WARN(1, "this should never happen\n");
5728 return 1;
5729}
5730
5731static int handle_xrstors(struct kvm_vcpu *vcpu)
5732{
5733 skip_emulated_instruction(vcpu);
5734 WARN(1, "this should never happen\n");
5735 return 1;
5736}
5737
851ba692 5738static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5739{
58fbbf26
KT		 5740 if (likely(fasteoi)) {
5741 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5742 int access_type, offset;
5743
5744 access_type = exit_qualification & APIC_ACCESS_TYPE;
5745 offset = exit_qualification & APIC_ACCESS_OFFSET;
5746 /*
5747 * Sane guest uses MOV to write EOI, with written value
5748 * not cared. So make a short-circuit here by avoiding
5749 * heavy instruction emulation.
5750 */
5751 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5752 (offset == APIC_EOI)) {
5753 kvm_lapic_set_eoi(vcpu);
5754 skip_emulated_instruction(vcpu);
5755 return 1;
5756 }
5757 }
51d8b661 5758 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5759}
5760
c7c9c56c
YZ		 5761static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5762{
5763 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5764 int vector = exit_qualification & 0xff;
5765
5766 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5767 kvm_apic_set_eoi_accelerated(vcpu, vector);
5768 return 1;
5769}
5770
83d4c286
YZ		 5771static int handle_apic_write(struct kvm_vcpu *vcpu)
5772{
5773 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5774 u32 offset = exit_qualification & 0xfff;
5775
5776 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5777 kvm_apic_write_nodecode(vcpu, offset);
5778 return 1;
5779}
5780
851ba692 5781static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5782{
60637aac 5783 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5784 unsigned long exit_qualification;
e269fb21
JK		 5785 bool has_error_code = false;
5786 u32 error_code = 0;
37817f29 5787 u16 tss_selector;
7f3d35fd 5788 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5789
5790 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5791 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5792 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5793
5794 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5795
5796 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5797 if (reason == TASK_SWITCH_GATE && idt_v) {
5798 switch (type) {
5799 case INTR_TYPE_NMI_INTR:
5800 vcpu->arch.nmi_injected = false;
654f06fc 5801 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5802 break;
5803 case INTR_TYPE_EXT_INTR:
66fd3f7f 5804 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5805 kvm_clear_interrupt_queue(vcpu);
5806 break;
5807 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5808 if (vmx->idt_vectoring_info &
5809 VECTORING_INFO_DELIVER_CODE_MASK) {
5810 has_error_code = true;
5811 error_code =
5812 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5813 }
5814 /* fall through */
64a7ec06
GN		 5815 case INTR_TYPE_SOFT_EXCEPTION:
5816 kvm_clear_exception_queue(vcpu);
5817 break;
5818 default:
5819 break;
5820 }
60637aac 5821 }
37817f29
IE		 5822 tss_selector = exit_qualification;
5823
64a7ec06
GN		 5824 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5825 type != INTR_TYPE_EXT_INTR &&
5826 type != INTR_TYPE_NMI_INTR))
5827 skip_emulated_instruction(vcpu);
5828
7f3d35fd
KW		 5829 if (kvm_task_switch(vcpu, tss_selector,
5830 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5831 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5832 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5833 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5834 vcpu->run->internal.ndata = 0;
42dbaa5a 5835 return 0;
acb54517 5836 }
42dbaa5a 5837
42dbaa5a
JK		 5838 /*
5839 * TODO: What about debug traps on tss switch?
5840 * Are we supposed to inject them and update dr6?
5841 */
5842
5843 return 1;
37817f29
IE		 5844}
5845
851ba692 5846static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5847{
f9c617f6 5848 unsigned long exit_qualification;
1439442c 5849 gpa_t gpa;
4f5982a5 5850 u32 error_code;
1439442c 5851 int gla_validity;
1439442c 5852
f9c617f6 5853 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5854
1439442c
SY		 5855 gla_validity = (exit_qualification >> 7) & 0x3;
5856 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5857 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5858 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5859 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5860 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5861 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5862 (long unsigned int)exit_qualification);
851ba692
AK		 5863 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5864 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5865 return 0;
1439442c
SY		 5866 }
5867
0be9c7a8
GN		 5868 /*
5869 * EPT violation happened while executing iret from NMI,
5870 * "blocked by NMI" bit has to be set before next VM entry.
5871 * There are errata that may cause this bit to not be set:
5872 * AAK134, BY25.
5873 */
bcd1c294
GN		 5874 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5875 cpu_has_virtual_nmis() &&
5876 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5877 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5878
1439442c 5879 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5880 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5881
5882 /* It is a write fault? */
81ed33e4 5883 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5884 /* It is a fetch fault? */
81ed33e4 5885 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5886 /* ept page table is present? */
81ed33e4 5887 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5888
25d92081
YZ		 5889 vcpu->arch.exit_qualification = exit_qualification;
5890
4f5982a5 5891 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5892}
5893
851ba692 5894static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5895{
f735d4af 5896 int ret;
68f89400
MT		 5897 gpa_t gpa;
5898
5899 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 5900 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
68c3b4d1 5901 skip_emulated_instruction(vcpu);
931c33b1 5902 trace_kvm_fast_mmio(gpa);
68c3b4d1
MT		 5903 return 1;
5904 }
68f89400 5905
450869d6 5906 ret = handle_mmio_page_fault(vcpu, gpa, true);
b37fbea6 5907 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5908 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5909 EMULATE_DONE;
f8f55942
XG		 5910
5911 if (unlikely(ret == RET_MMIO_PF_INVALID))
5912 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5913
b37fbea6 5914 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5915 return 1;
5916
5917 /* It is the real ept misconfig */
f735d4af 5918 WARN_ON(1);
68f89400 5919
851ba692
AK		 5920 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5921 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5922
5923 return 0;
5924}
5925
851ba692 5926static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5927{
5928 u32 cpu_based_vm_exec_control;
5929
5930 /* clear pending NMI */
5931 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5932 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5933 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5934 ++vcpu->stat.nmi_window_exits;
3842d135 5935 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5936
5937 return 1;
5938}
5939
80ced186 5940static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5941{
8b3079a5
AK		 5942 struct vcpu_vmx *vmx = to_vmx(vcpu);
5943 enum emulation_result err = EMULATE_DONE;
80ced186 5944 int ret = 1;
49e9d557
AK		 5945 u32 cpu_exec_ctrl;
5946 bool intr_window_requested;
b8405c18 5947 unsigned count = 130;
49e9d557
AK		 5948
5949 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5950 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5951
98eb2f8b 5952 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5953 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5954 return handle_interrupt_window(&vmx->vcpu);
5955
de87dcdd
AK		 5956 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5957 return 1;
5958
991eebf9 5959 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5960
ac0a48c3 5961 if (err == EMULATE_USER_EXIT) {
94452b9e 5962 ++vcpu->stat.mmio_exits;
80ced186
MG		 5963 ret = 0;
5964 goto out;
5965 }
1d5a4d9b 5966
de5f70e0
AK		 5967 if (err != EMULATE_DONE) {
5968 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5969 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5970 vcpu->run->internal.ndata = 0;
6d77dbfc 5971 return 0;
de5f70e0 5972 }
ea953ef0 5973
8d76c49e
GN		 5974 if (vcpu->arch.halt_request) {
5975 vcpu->arch.halt_request = 0;
5cb56059 5976 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5977 goto out;
5978 }
5979
ea953ef0 5980 if (signal_pending(current))
80ced186 5981 goto out;
ea953ef0
MG		 5982 if (need_resched())
5983 schedule();
5984 }
5985
80ced186
MG		 5986out:
5987 return ret;
ea953ef0
MG		 5988}
5989
b4a2d31d
RK		 5990static int __grow_ple_window(int val)
5991{
5992 if (ple_window_grow < 1)
5993 return ple_window;
5994
5995 val = min(val, ple_window_actual_max);
5996
5997 if (ple_window_grow < ple_window)
5998 val *= ple_window_grow;
5999 else
6000 val += ple_window_grow;
6001
6002 return val;
6003}
6004
6005static int __shrink_ple_window(int val, int modifier, int minimum)
6006{
6007 if (modifier < 1)
6008 return ple_window;
6009
6010 if (modifier < ple_window)
6011 val /= modifier;
6012 else
6013 val -= modifier;
6014
6015 return max(val, minimum);
6016}
6017
6018static void grow_ple_window(struct kvm_vcpu *vcpu)
6019{
6020 struct vcpu_vmx *vmx = to_vmx(vcpu);
6021 int old = vmx->ple_window;
6022
6023 vmx->ple_window = __grow_ple_window(old);
6024
6025 if (vmx->ple_window != old)
6026 vmx->ple_window_dirty = true;
7b46268d
RK		 6027
6028 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 6029}
6030
6031static void shrink_ple_window(struct kvm_vcpu *vcpu)
6032{
6033 struct vcpu_vmx *vmx = to_vmx(vcpu);
6034 int old = vmx->ple_window;
6035
6036 vmx->ple_window = __shrink_ple_window(old,
6037 ple_window_shrink, ple_window);
6038
6039 if (vmx->ple_window != old)
6040 vmx->ple_window_dirty = true;
7b46268d
RK		 6041
6042 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 6043}
6044
6045/*
6046 * ple_window_actual_max is computed to be one grow_ple_window() below
6047 * ple_window_max. (See __grow_ple_window for the reason.)
6048 * This prevents overflows, because ple_window_max is int.
6049 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6050 * this process.
6051 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6052 */
6053static void update_ple_window_actual_max(void)
6054{
6055 ple_window_actual_max =
6056 __shrink_ple_window(max(ple_window_max, ple_window),
6057 ple_window_grow, INT_MIN);
6058}
6059
bf9f6ac8
FW		 6060/*
6061 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6062 */
6063static void wakeup_handler(void)
6064{
6065 struct kvm_vcpu *vcpu;
6066 int cpu = smp_processor_id();
6067
6068 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6069 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6070 blocked_vcpu_list) {
6071 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6072
6073 if (pi_test_on(pi_desc) == 1)
6074 kvm_vcpu_kick(vcpu);
6075 }
6076 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6077}
6078
f2c7648d
TC		 6079static __init int hardware_setup(void)
6080{
34a1cd60
TC		 6081 int r = -ENOMEM, i, msr;
6082
6083 rdmsrl_safe(MSR_EFER, &host_efer);
6084
6085 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6086 kvm_define_shared_msr(i, vmx_msr_index[i]);
6087
6088 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6089 if (!vmx_io_bitmap_a)
6090 return r;
6091
6092 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6093 if (!vmx_io_bitmap_b)
6094 goto out;
6095
6096 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6097 if (!vmx_msr_bitmap_legacy)
6098 goto out1;
6099
6100 vmx_msr_bitmap_legacy_x2apic =
6101 (unsigned long *)__get_free_page(GFP_KERNEL);
6102 if (!vmx_msr_bitmap_legacy_x2apic)
6103 goto out2;
6104
6105 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6106 if (!vmx_msr_bitmap_longmode)
6107 goto out3;
6108
6109 vmx_msr_bitmap_longmode_x2apic =
6110 (unsigned long *)__get_free_page(GFP_KERNEL);
6111 if (!vmx_msr_bitmap_longmode_x2apic)
6112 goto out4;
3af18d9c
WV		 6113
6114 if (nested) {
6115 vmx_msr_bitmap_nested =
6116 (unsigned long *)__get_free_page(GFP_KERNEL);
6117 if (!vmx_msr_bitmap_nested)
6118 goto out5;
6119 }
6120
34a1cd60
TC		 6121 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6122 if (!vmx_vmread_bitmap)
3af18d9c 6123 goto out6;
34a1cd60
TC		 6124
6125 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6126 if (!vmx_vmwrite_bitmap)
3af18d9c 6127 goto out7;
34a1cd60
TC		 6128
6129 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6130 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6131
6132 /*
6133 * Allow direct access to the PC debug port (it is often used for I/O
6134 * delays, but the vmexits simply slow things down).
6135 */
6136 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6137 clear_bit(0x80, vmx_io_bitmap_a);
6138
6139 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6140
6141 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6142 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 6143 if (nested)
6144 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 6145
34a1cd60
TC		 6146 if (setup_vmcs_config(&vmcs_config) < 0) {
6147 r = -EIO;
3af18d9c 6148 goto out8;
baa03522 6149 }
f2c7648d
TC		 6150
6151 if (boot_cpu_has(X86_FEATURE_NX))
6152 kvm_enable_efer_bits(EFER_NX);
6153
6154 if (!cpu_has_vmx_vpid())
6155 enable_vpid = 0;
6156 if (!cpu_has_vmx_shadow_vmcs())
6157 enable_shadow_vmcs = 0;
6158 if (enable_shadow_vmcs)
6159 init_vmcs_shadow_fields();
6160
6161 if (!cpu_has_vmx_ept() ||
6162 !cpu_has_vmx_ept_4levels()) {
6163 enable_ept = 0;
6164 enable_unrestricted_guest = 0;
6165 enable_ept_ad_bits = 0;
6166 }
6167
6168 if (!cpu_has_vmx_ept_ad_bits())
6169 enable_ept_ad_bits = 0;
6170
6171 if (!cpu_has_vmx_unrestricted_guest())
6172 enable_unrestricted_guest = 0;
6173
ad15a296 6174 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6175 flexpriority_enabled = 0;
6176
ad15a296
PB		 6177 /*
6178 * set_apic_access_page_addr() is used to reload apic access
6179 * page upon invalidation. No need to do anything if not
6180 * using the APIC_ACCESS_ADDR VMCS field.
6181 */
6182 if (!flexpriority_enabled)
f2c7648d 6183 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6184
6185 if (!cpu_has_vmx_tpr_shadow())
6186 kvm_x86_ops->update_cr8_intercept = NULL;
6187
6188 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6189 kvm_disable_largepages();
6190
6191 if (!cpu_has_vmx_ple())
6192 ple_gap = 0;
6193
6194 if (!cpu_has_vmx_apicv())
6195 enable_apicv = 0;
6196
64903d61
HZ		 6197 if (cpu_has_vmx_tsc_scaling()) {
6198 kvm_has_tsc_control = true;
6199 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6200 kvm_tsc_scaling_ratio_frac_bits = 48;
6201 }
6202
f2c7648d
TC		 6203 if (enable_apicv)
6204 kvm_x86_ops->update_cr8_intercept = NULL;
6205 else {
6206 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6207 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6208 kvm_x86_ops->deliver_posted_interrupt = NULL;
6209 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6210 }
6211
baa03522
TC		 6212 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6213 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6214 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6215 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6216 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6217 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6218 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6219
6220 memcpy(vmx_msr_bitmap_legacy_x2apic,
6221 vmx_msr_bitmap_legacy, PAGE_SIZE);
6222 memcpy(vmx_msr_bitmap_longmode_x2apic,
6223 vmx_msr_bitmap_longmode, PAGE_SIZE);
6224
04bb92e4
WL		 6225 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6226
baa03522
TC		 6227 if (enable_apicv) {
6228 for (msr = 0x800; msr <= 0x8ff; msr++)
6229 vmx_disable_intercept_msr_read_x2apic(msr);
6230
6231 /* According SDM, in x2apic mode, the whole id reg is used.
6232 * But in KVM, it only use the highest eight bits. Need to
6233 * intercept it */
6234 vmx_enable_intercept_msr_read_x2apic(0x802);
6235 /* TMCCT */
6236 vmx_enable_intercept_msr_read_x2apic(0x839);
6237 /* TPR */
6238 vmx_disable_intercept_msr_write_x2apic(0x808);
6239 /* EOI */
6240 vmx_disable_intercept_msr_write_x2apic(0x80b);
6241 /* SELF-IPI */
6242 vmx_disable_intercept_msr_write_x2apic(0x83f);
6243 }
6244
6245 if (enable_ept) {
6246 kvm_mmu_set_mask_ptes(0ull,
6247 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6248 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6249 0ull, VMX_EPT_EXECUTABLE_MASK);
6250 ept_set_mmio_spte_mask();
6251 kvm_enable_tdp();
6252 } else
6253 kvm_disable_tdp();
6254
6255 update_ple_window_actual_max();
6256
843e4330
KH		 6257 /*
6258 * Only enable PML when hardware supports PML feature, and both EPT
6259 * and EPT A/D bit features are enabled -- PML depends on them to work.
6260 */
6261 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6262 enable_pml = 0;
6263
6264 if (!enable_pml) {
6265 kvm_x86_ops->slot_enable_log_dirty = NULL;
6266 kvm_x86_ops->slot_disable_log_dirty = NULL;
6267 kvm_x86_ops->flush_log_dirty = NULL;
6268 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6269 }
6270
bf9f6ac8
FW		 6271 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6272
f2c7648d 6273 return alloc_kvm_area();
34a1cd60 6274
3af18d9c 6275out8:
34a1cd60 6276 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6277out7:
34a1cd60 6278 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6279out6:
6280 if (nested)
6281 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6282out5:
6283 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6284out4:
6285 free_page((unsigned long)vmx_msr_bitmap_longmode);
6286out3:
6287 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6288out2:
6289 free_page((unsigned long)vmx_msr_bitmap_legacy);
6290out1:
6291 free_page((unsigned long)vmx_io_bitmap_b);
6292out:
6293 free_page((unsigned long)vmx_io_bitmap_a);
6294
6295 return r;
f2c7648d
TC		 6296}
6297
6298static __exit void hardware_unsetup(void)
6299{
34a1cd60
TC		 6300 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6301 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6302 free_page((unsigned long)vmx_msr_bitmap_legacy);
6303 free_page((unsigned long)vmx_msr_bitmap_longmode);
6304 free_page((unsigned long)vmx_io_bitmap_b);
6305 free_page((unsigned long)vmx_io_bitmap_a);
6306 free_page((unsigned long)vmx_vmwrite_bitmap);
6307 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6308 if (nested)
6309 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6310
f2c7648d
TC		 6311 free_kvm_area();
6312}
6313
4b8d54f9
ZE		 6314/*
6315 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6316 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6317 */
9fb41ba8 6318static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6319{
b4a2d31d
RK		 6320 if (ple_gap)
6321 grow_ple_window(vcpu);
6322
4b8d54f9
ZE		 6323 skip_emulated_instruction(vcpu);
6324 kvm_vcpu_on_spin(vcpu);
6325
6326 return 1;
6327}
6328
87c00572 6329static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6330{
87c00572 6331 skip_emulated_instruction(vcpu);
59708670
SY		 6332 return 1;
6333}
6334
87c00572
GS		 6335static int handle_mwait(struct kvm_vcpu *vcpu)
6336{
6337 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6338 return handle_nop(vcpu);
6339}
6340
5f3d45e7
MD		 6341static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6342{
6343 return 1;
6344}
6345
87c00572
GS		 6346static int handle_monitor(struct kvm_vcpu *vcpu)
6347{
6348 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6349 return handle_nop(vcpu);
6350}
6351
ff2f6fe9
NHE		 6352/*
6353 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6354 * We could reuse a single VMCS for all the L2 guests, but we also want the
6355 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6356 * allows keeping them loaded on the processor, and in the future will allow
6357 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6358 * every entry if they never change.
6359 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6360 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6361 *
6362 * The following functions allocate and free a vmcs02 in this pool.
6363 */
6364
6365/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6366static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6367{
6368 struct vmcs02_list *item;
6369 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6370 if (item->vmptr == vmx->nested.current_vmptr) {
6371 list_move(&item->list, &vmx->nested.vmcs02_pool);
6372 return &item->vmcs02;
6373 }
6374
6375 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6376 /* Recycle the least recently used VMCS. */
6377 item = list_entry(vmx->nested.vmcs02_pool.prev,
6378 struct vmcs02_list, list);
6379 item->vmptr = vmx->nested.current_vmptr;
6380 list_move(&item->list, &vmx->nested.vmcs02_pool);
6381 return &item->vmcs02;
6382 }
6383
6384 /* Create a new VMCS */
0fa24ce3 6385 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6386 if (!item)
6387 return NULL;
6388 item->vmcs02.vmcs = alloc_vmcs();
6389 if (!item->vmcs02.vmcs) {
6390 kfree(item);
6391 return NULL;
6392 }
6393 loaded_vmcs_init(&item->vmcs02);
6394 item->vmptr = vmx->nested.current_vmptr;
6395 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6396 vmx->nested.vmcs02_num++;
6397 return &item->vmcs02;
6398}
6399
6400/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6401static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6402{
6403 struct vmcs02_list *item;
6404 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6405 if (item->vmptr == vmptr) {
6406 free_loaded_vmcs(&item->vmcs02);
6407 list_del(&item->list);
6408 kfree(item);
6409 vmx->nested.vmcs02_num--;
6410 return;
6411 }
6412}
6413
6414/*
6415 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6416 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6417 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6418 */
6419static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6420{
6421 struct vmcs02_list *item, *n;
4fa7734c
PB		 6422
6423 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6424 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6425 /*
6426 * Something will leak if the above WARN triggers. Better than
6427 * a use-after-free.
6428 */
6429 if (vmx->loaded_vmcs == &item->vmcs02)
6430 continue;
6431
6432 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6433 list_del(&item->list);
6434 kfree(item);
4fa7734c 6435 vmx->nested.vmcs02_num--;
ff2f6fe9 6436 }
ff2f6fe9
NHE		 6437}
6438
0658fbaa
ACL		 6439/*
6440 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6441 * set the success or error code of an emulated VMX instruction, as specified
6442 * by Vol 2B, VMX Instruction Reference, "Conventions".
6443 */
6444static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6445{
6446 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6447 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6448 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6449}
6450
6451static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6452{
6453 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6454 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6455 X86_EFLAGS_SF | X86_EFLAGS_OF))
6456 | X86_EFLAGS_CF);
6457}
6458
145c28dd 6459static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6460 u32 vm_instruction_error)
6461{
6462 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6463 /*
6464 * failValid writes the error number to the current VMCS, which
6465 * can't be done there isn't a current VMCS.
6466 */
6467 nested_vmx_failInvalid(vcpu);
6468 return;
6469 }
6470 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6471 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6472 X86_EFLAGS_SF | X86_EFLAGS_OF))
6473 | X86_EFLAGS_ZF);
6474 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6475 /*
6476 * We don't need to force a shadow sync because
6477 * VM_INSTRUCTION_ERROR is not shadowed
6478 */
6479}
145c28dd 6480
ff651cb6
WV		 6481static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6482{
6483 /* TODO: not to reset guest simply here. */
6484 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6485 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6486}
6487
f4124500
JK		 6488static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6489{
6490 struct vcpu_vmx *vmx =
6491 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6492
6493 vmx->nested.preemption_timer_expired = true;
6494 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6495 kvm_vcpu_kick(&vmx->vcpu);
6496
6497 return HRTIMER_NORESTART;
6498}
6499
19677e32
BD		 6500/*
6501 * Decode the memory-address operand of a vmx instruction, as recorded on an
6502 * exit caused by such an instruction (run by a guest hypervisor).
6503 * On success, returns 0. When the operand is invalid, returns 1 and throws
6504 * #UD or #GP.
6505 */
6506static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6507 unsigned long exit_qualification,
f9eb4af6 6508 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6509{
f9eb4af6
EK		 6510 gva_t off;
6511 bool exn;
6512 struct kvm_segment s;
6513
19677e32
BD		 6514 /*
6515 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6516 * Execution", on an exit, vmx_instruction_info holds most of the
6517 * addressing components of the operand. Only the displacement part
6518 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6519 * For how an actual address is calculated from all these components,
6520 * refer to Vol. 1, "Operand Addressing".
6521 */
6522 int scaling = vmx_instruction_info & 3;
6523 int addr_size = (vmx_instruction_info >> 7) & 7;
6524 bool is_reg = vmx_instruction_info & (1u << 10);
6525 int seg_reg = (vmx_instruction_info >> 15) & 7;
6526 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6527 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6528 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6529 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6530
6531 if (is_reg) {
6532 kvm_queue_exception(vcpu, UD_VECTOR);
6533 return 1;
6534 }
6535
6536 /* Addr = segment_base + offset */
6537 /* offset = base + [index * scale] + displacement */
f9eb4af6 6538 off = exit_qualification; /* holds the displacement */
19677e32 6539 if (base_is_valid)
f9eb4af6 6540 off += kvm_register_read(vcpu, base_reg);
19677e32 6541 if (index_is_valid)
f9eb4af6
EK		 6542 off += kvm_register_read(vcpu, index_reg)<<scaling;
6543 vmx_get_segment(vcpu, &s, seg_reg);
6544 *ret = s.base + off;
19677e32
BD		 6545
6546 if (addr_size == 1) /* 32 bit */
6547 *ret &= 0xffffffff;
6548
f9eb4af6
EK		 6549 /* Checks for #GP/#SS exceptions. */
6550 exn = false;
6551 if (is_protmode(vcpu)) {
6552 /* Protected mode: apply checks for segment validity in the
6553 * following order:
6554 * - segment type check (#GP(0) may be thrown)
6555 * - usability check (#GP(0)/#SS(0))
6556 * - limit check (#GP(0)/#SS(0))
6557 */
6558 if (wr)
6559 /* #GP(0) if the destination operand is located in a
6560 * read-only data segment or any code segment.
6561 */
6562 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6563 else
6564 /* #GP(0) if the source operand is located in an
6565 * execute-only code segment
6566 */
6567 exn = ((s.type & 0xa) == 8);
6568 }
6569 if (exn) {
6570 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6571 return 1;
6572 }
6573 if (is_long_mode(vcpu)) {
6574 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6575 * non-canonical form. This is an only check for long mode.
6576 */
6577 exn = is_noncanonical_address(*ret);
6578 } else if (is_protmode(vcpu)) {
6579 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6580 */
6581 exn = (s.unusable != 0);
6582 /* Protected mode: #GP(0)/#SS(0) if the memory
6583 * operand is outside the segment limit.
6584 */
6585 exn = exn || (off + sizeof(u64) > s.limit);
6586 }
6587 if (exn) {
6588 kvm_queue_exception_e(vcpu,
6589 seg_reg == VCPU_SREG_SS ?
6590 SS_VECTOR : GP_VECTOR,
6591 0);
6592 return 1;
6593 }
6594
19677e32
BD		 6595 return 0;
6596}
6597
3573e22c
BD		 6598/*
6599 * This function performs the various checks including
6600 * - if it's 4KB aligned
6601 * - No bits beyond the physical address width are set
6602 * - Returns 0 on success or else 1
4291b588 6603 * (Intel SDM Section 30.3)
3573e22c 6604 */
4291b588
BD		 6605static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6606 gpa_t *vmpointer)
3573e22c
BD		 6607{
6608 gva_t gva;
6609 gpa_t vmptr;
6610 struct x86_exception e;
6611 struct page *page;
6612 struct vcpu_vmx *vmx = to_vmx(vcpu);
6613 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6614
6615 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 6616 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD		 6617 return 1;
6618
6619 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6620 sizeof(vmptr), &e)) {
6621 kvm_inject_page_fault(vcpu, &e);
6622 return 1;
6623 }
6624
6625 switch (exit_reason) {
6626 case EXIT_REASON_VMON:
6627 /*
6628 * SDM 3: 24.11.5
6629 * The first 4 bytes of VMXON region contain the supported
6630 * VMCS revision identifier
6631 *
6632 * Note - IA32_VMX_BASIC[48] will never be 1
6633 * for the nested case;
6634 * which replaces physical address width with 32
6635 *
6636 */
bc39c4db 6637 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6638 nested_vmx_failInvalid(vcpu);
6639 skip_emulated_instruction(vcpu);
6640 return 1;
6641 }
6642
6643 page = nested_get_page(vcpu, vmptr);
6644 if (page == NULL ||
6645 *(u32 *)kmap(page) != VMCS12_REVISION) {
6646 nested_vmx_failInvalid(vcpu);
6647 kunmap(page);
6648 skip_emulated_instruction(vcpu);
6649 return 1;
6650 }
6651 kunmap(page);
6652 vmx->nested.vmxon_ptr = vmptr;
6653 break;
4291b588 6654 case EXIT_REASON_VMCLEAR:
bc39c4db 6655 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6656 nested_vmx_failValid(vcpu,
6657 VMXERR_VMCLEAR_INVALID_ADDRESS);
6658 skip_emulated_instruction(vcpu);
6659 return 1;
6660 }
6661
6662 if (vmptr == vmx->nested.vmxon_ptr) {
6663 nested_vmx_failValid(vcpu,
6664 VMXERR_VMCLEAR_VMXON_POINTER);
6665 skip_emulated_instruction(vcpu);
6666 return 1;
6667 }
6668 break;
6669 case EXIT_REASON_VMPTRLD:
bc39c4db 6670 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6671 nested_vmx_failValid(vcpu,
6672 VMXERR_VMPTRLD_INVALID_ADDRESS);
6673 skip_emulated_instruction(vcpu);
6674 return 1;
6675 }
3573e22c 6676
4291b588
BD		 6677 if (vmptr == vmx->nested.vmxon_ptr) {
6678 nested_vmx_failValid(vcpu,
6679 VMXERR_VMCLEAR_VMXON_POINTER);
6680 skip_emulated_instruction(vcpu);
6681 return 1;
6682 }
6683 break;
3573e22c
BD		 6684 default:
6685 return 1; /* shouldn't happen */
6686 }
6687
4291b588
BD		 6688 if (vmpointer)
6689 *vmpointer = vmptr;
3573e22c
BD		 6690 return 0;
6691}
6692
ec378aee
NHE		 6693/*
6694 * Emulate the VMXON instruction.
6695 * Currently, we just remember that VMX is active, and do not save or even
6696 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6697 * do not currently need to store anything in that guest-allocated memory
6698 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6699 * argument is different from the VMXON pointer (which the spec says they do).
6700 */
6701static int handle_vmon(struct kvm_vcpu *vcpu)
6702{
6703 struct kvm_segment cs;
6704 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6705 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6706 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6707 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6708
6709 /* The Intel VMX Instruction Reference lists a bunch of bits that
6710 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6711 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6712 * Otherwise, we should fail with #UD. We test these now:
6713 */
6714 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6715 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6716 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6717 kvm_queue_exception(vcpu, UD_VECTOR);
6718 return 1;
6719 }
6720
6721 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6722 if (is_long_mode(vcpu) && !cs.l) {
6723 kvm_queue_exception(vcpu, UD_VECTOR);
6724 return 1;
6725 }
6726
6727 if (vmx_get_cpl(vcpu)) {
6728 kvm_inject_gp(vcpu, 0);
6729 return 1;
6730 }
3573e22c 6731
4291b588 6732 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6733 return 1;
6734
145c28dd
AG		 6735 if (vmx->nested.vmxon) {
6736 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6737 skip_emulated_instruction(vcpu);
6738 return 1;
6739 }
b3897a49
NHE		 6740
6741 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6742 != VMXON_NEEDED_FEATURES) {
6743 kvm_inject_gp(vcpu, 0);
6744 return 1;
6745 }
6746
8de48833
AG		 6747 if (enable_shadow_vmcs) {
6748 shadow_vmcs = alloc_vmcs();
6749 if (!shadow_vmcs)
6750 return -ENOMEM;
6751 /* mark vmcs as shadow */
6752 shadow_vmcs->revision_id |= (1u << 31);
6753 /* init shadow vmcs */
6754 vmcs_clear(shadow_vmcs);
6755 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6756 }
ec378aee 6757
ff2f6fe9
NHE		 6758 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6759 vmx->nested.vmcs02_num = 0;
6760
f4124500
JK		 6761 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6762 HRTIMER_MODE_REL);
6763 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6764
ec378aee
NHE		 6765 vmx->nested.vmxon = true;
6766
6767 skip_emulated_instruction(vcpu);
a25eb114 6768 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6769 return 1;
6770}
6771
6772/*
6773 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6774 * for running VMX instructions (except VMXON, whose prerequisites are
6775 * slightly different). It also specifies what exception to inject otherwise.
6776 */
6777static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6778{
6779 struct kvm_segment cs;
6780 struct vcpu_vmx *vmx = to_vmx(vcpu);
6781
6782 if (!vmx->nested.vmxon) {
6783 kvm_queue_exception(vcpu, UD_VECTOR);
6784 return 0;
6785 }
6786
6787 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6788 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6789 (is_long_mode(vcpu) && !cs.l)) {
6790 kvm_queue_exception(vcpu, UD_VECTOR);
6791 return 0;
6792 }
6793
6794 if (vmx_get_cpl(vcpu)) {
6795 kvm_inject_gp(vcpu, 0);
6796 return 0;
6797 }
6798
6799 return 1;
6800}
6801
e7953d7f
AG		 6802static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6803{
9a2a05b9
PB		 6804 if (vmx->nested.current_vmptr == -1ull)
6805 return;
6806
6807 /* current_vmptr and current_vmcs12 are always set/reset together */
6808 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6809 return;
6810
012f83cb 6811 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6812 /* copy to memory all shadowed fields in case
6813 they were modified */
6814 copy_shadow_to_vmcs12(vmx);
6815 vmx->nested.sync_shadow_vmcs = false;
7ec36296
XG		 6816 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6817 SECONDARY_EXEC_SHADOW_VMCS);
9a2a05b9 6818 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6819 }
705699a1 6820 vmx->nested.posted_intr_nv = -1;
e7953d7f
AG		 6821 kunmap(vmx->nested.current_vmcs12_page);
6822 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6823 vmx->nested.current_vmptr = -1ull;
6824 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6825}
6826
ec378aee
NHE		 6827/*
6828 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6829 * just stops using VMX.
6830 */
6831static void free_nested(struct vcpu_vmx *vmx)
6832{
6833 if (!vmx->nested.vmxon)
6834 return;
9a2a05b9 6835
ec378aee 6836 vmx->nested.vmxon = false;
5c614b35 6837 free_vpid(vmx->nested.vpid02);
9a2a05b9 6838 nested_release_vmcs12(vmx);
e7953d7f
AG		 6839 if (enable_shadow_vmcs)
6840 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6841 /* Unpin physical memory we referred to in current vmcs02 */
6842 if (vmx->nested.apic_access_page) {
6843 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6844 vmx->nested.apic_access_page = NULL;
fe3ef05c 6845 }
a7c0b07d
WL		 6846 if (vmx->nested.virtual_apic_page) {
6847 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6848 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6849 }
705699a1
WV		 6850 if (vmx->nested.pi_desc_page) {
6851 kunmap(vmx->nested.pi_desc_page);
6852 nested_release_page(vmx->nested.pi_desc_page);
6853 vmx->nested.pi_desc_page = NULL;
6854 vmx->nested.pi_desc = NULL;
6855 }
ff2f6fe9
NHE		 6856
6857 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6858}
6859
6860/* Emulate the VMXOFF instruction */
6861static int handle_vmoff(struct kvm_vcpu *vcpu)
6862{
6863 if (!nested_vmx_check_permission(vcpu))
6864 return 1;
6865 free_nested(to_vmx(vcpu));
6866 skip_emulated_instruction(vcpu);
a25eb114 6867 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6868 return 1;
6869}
6870
27d6c865
NHE		 6871/* Emulate the VMCLEAR instruction */
6872static int handle_vmclear(struct kvm_vcpu *vcpu)
6873{
6874 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6875 gpa_t vmptr;
6876 struct vmcs12 *vmcs12;
6877 struct page *page;
27d6c865
NHE		 6878
6879 if (!nested_vmx_check_permission(vcpu))
6880 return 1;
6881
4291b588 6882 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6883 return 1;
27d6c865 6884
9a2a05b9 6885 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6886 nested_release_vmcs12(vmx);
27d6c865
NHE		 6887
6888 page = nested_get_page(vcpu, vmptr);
6889 if (page == NULL) {
6890 /*
6891 * For accurate processor emulation, VMCLEAR beyond available
6892 * physical memory should do nothing at all. However, it is
6893 * possible that a nested vmx bug, not a guest hypervisor bug,
6894 * resulted in this case, so let's shut down before doing any
6895 * more damage:
6896 */
6897 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6898 return 1;
6899 }
6900 vmcs12 = kmap(page);
6901 vmcs12->launch_state = 0;
6902 kunmap(page);
6903 nested_release_page(page);
6904
6905 nested_free_vmcs02(vmx, vmptr);
6906
6907 skip_emulated_instruction(vcpu);
6908 nested_vmx_succeed(vcpu);
6909 return 1;
6910}
6911
cd232ad0
NHE		 6912static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6913
6914/* Emulate the VMLAUNCH instruction */
6915static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6916{
6917 return nested_vmx_run(vcpu, true);
6918}
6919
6920/* Emulate the VMRESUME instruction */
6921static int handle_vmresume(struct kvm_vcpu *vcpu)
6922{
6923
6924 return nested_vmx_run(vcpu, false);
6925}
6926
49f705c5
NHE		 6927enum vmcs_field_type {
6928 VMCS_FIELD_TYPE_U16 = 0,
6929 VMCS_FIELD_TYPE_U64 = 1,
6930 VMCS_FIELD_TYPE_U32 = 2,
6931 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6932};
6933
6934static inline int vmcs_field_type(unsigned long field)
6935{
6936 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6937 return VMCS_FIELD_TYPE_U32;
6938 return (field >> 13) & 0x3 ;
6939}
6940
6941static inline int vmcs_field_readonly(unsigned long field)
6942{
6943 return (((field >> 10) & 0x3) == 1);
6944}
6945
6946/*
6947 * Read a vmcs12 field. Since these can have varying lengths and we return
6948 * one type, we chose the biggest type (u64) and zero-extend the return value
6949 * to that size. Note that the caller, handle_vmread, might need to use only
6950 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6951 * 64-bit fields are to be returned).
6952 */
a2ae9df7
PB		 6953static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6954 unsigned long field, u64 *ret)
49f705c5
NHE		 6955{
6956 short offset = vmcs_field_to_offset(field);
6957 char *p;
6958
6959 if (offset < 0)
a2ae9df7 6960 return offset;
49f705c5
NHE		 6961
6962 p = ((char *)(get_vmcs12(vcpu))) + offset;
6963
6964 switch (vmcs_field_type(field)) {
6965 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6966 *ret = *((natural_width *)p);
a2ae9df7 6967 return 0;
49f705c5
NHE		 6968 case VMCS_FIELD_TYPE_U16:
6969 *ret = *((u16 *)p);
a2ae9df7 6970 return 0;
49f705c5
NHE		 6971 case VMCS_FIELD_TYPE_U32:
6972 *ret = *((u32 *)p);
a2ae9df7 6973 return 0;
49f705c5
NHE		 6974 case VMCS_FIELD_TYPE_U64:
6975 *ret = *((u64 *)p);
a2ae9df7 6976 return 0;
49f705c5 6977 default:
a2ae9df7
PB		 6978 WARN_ON(1);
6979 return -ENOENT;
49f705c5
NHE		 6980 }
6981}
6982
20b97fea 6983
a2ae9df7
PB		 6984static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6985 unsigned long field, u64 field_value){
20b97fea
AG		 6986 short offset = vmcs_field_to_offset(field);
6987 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6988 if (offset < 0)
a2ae9df7 6989 return offset;
20b97fea
AG		 6990
6991 switch (vmcs_field_type(field)) {
6992 case VMCS_FIELD_TYPE_U16:
6993 *(u16 *)p = field_value;
a2ae9df7 6994 return 0;
20b97fea
AG		 6995 case VMCS_FIELD_TYPE_U32:
6996 *(u32 *)p = field_value;
a2ae9df7 6997 return 0;
20b97fea
AG		 6998 case VMCS_FIELD_TYPE_U64:
6999 *(u64 *)p = field_value;
a2ae9df7 7000 return 0;
20b97fea
AG		 7001 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7002 *(natural_width *)p = field_value;
a2ae9df7 7003 return 0;
20b97fea 7004 default:
a2ae9df7
PB		 7005 WARN_ON(1);
7006 return -ENOENT;
20b97fea
AG		 7007 }
7008
7009}
7010
16f5b903
AG		 7011static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7012{
7013 int i;
7014 unsigned long field;
7015 u64 field_value;
7016 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 7017 const unsigned long *fields = shadow_read_write_fields;
7018 const int num_fields = max_shadow_read_write_fields;
16f5b903 7019
282da870
JK		 7020 preempt_disable();
7021
16f5b903
AG		 7022 vmcs_load(shadow_vmcs);
7023
7024 for (i = 0; i < num_fields; i++) {
7025 field = fields[i];
7026 switch (vmcs_field_type(field)) {
7027 case VMCS_FIELD_TYPE_U16:
7028 field_value = vmcs_read16(field);
7029 break;
7030 case VMCS_FIELD_TYPE_U32:
7031 field_value = vmcs_read32(field);
7032 break;
7033 case VMCS_FIELD_TYPE_U64:
7034 field_value = vmcs_read64(field);
7035 break;
7036 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7037 field_value = vmcs_readl(field);
7038 break;
a2ae9df7
PB		 7039 default:
7040 WARN_ON(1);
7041 continue;
16f5b903
AG		 7042 }
7043 vmcs12_write_any(&vmx->vcpu, field, field_value);
7044 }
7045
7046 vmcs_clear(shadow_vmcs);
7047 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 7048
7049 preempt_enable();
16f5b903
AG		 7050}
7051
c3114420
AG		 7052static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7053{
c2bae893
MK		 7054 const unsigned long *fields[] = {
7055 shadow_read_write_fields,
7056 shadow_read_only_fields
c3114420 7057 };
c2bae893 7058 const int max_fields[] = {
c3114420
AG		 7059 max_shadow_read_write_fields,
7060 max_shadow_read_only_fields
7061 };
7062 int i, q;
7063 unsigned long field;
7064 u64 field_value = 0;
7065 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7066
7067 vmcs_load(shadow_vmcs);
7068
c2bae893 7069 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 7070 for (i = 0; i < max_fields[q]; i++) {
7071 field = fields[q][i];
7072 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7073
7074 switch (vmcs_field_type(field)) {
7075 case VMCS_FIELD_TYPE_U16:
7076 vmcs_write16(field, (u16)field_value);
7077 break;
7078 case VMCS_FIELD_TYPE_U32:
7079 vmcs_write32(field, (u32)field_value);
7080 break;
7081 case VMCS_FIELD_TYPE_U64:
7082 vmcs_write64(field, (u64)field_value);
7083 break;
7084 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7085 vmcs_writel(field, (long)field_value);
7086 break;
a2ae9df7
PB		 7087 default:
7088 WARN_ON(1);
7089 break;
c3114420
AG		 7090 }
7091 }
7092 }
7093
7094 vmcs_clear(shadow_vmcs);
7095 vmcs_load(vmx->loaded_vmcs->vmcs);
7096}
7097
49f705c5
NHE		 7098/*
7099 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7100 * used before) all generate the same failure when it is missing.
7101 */
7102static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7103{
7104 struct vcpu_vmx *vmx = to_vmx(vcpu);
7105 if (vmx->nested.current_vmptr == -1ull) {
7106 nested_vmx_failInvalid(vcpu);
7107 skip_emulated_instruction(vcpu);
7108 return 0;
7109 }
7110 return 1;
7111}
7112
7113static int handle_vmread(struct kvm_vcpu *vcpu)
7114{
7115 unsigned long field;
7116 u64 field_value;
7117 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7118 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7119 gva_t gva = 0;
7120
7121 if (!nested_vmx_check_permission(vcpu) ||
7122 !nested_vmx_check_vmcs12(vcpu))
7123 return 1;
7124
7125 /* Decode instruction info and find the field to read */
27e6fb5d 7126 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 7127 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 7128 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 7129 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7130 skip_emulated_instruction(vcpu);
7131 return 1;
7132 }
7133 /*
7134 * Now copy part of this value to register or memory, as requested.
7135 * Note that the number of bits actually copied is 32 or 64 depending
7136 * on the guest's mode (32 or 64 bit), not on the given field's length.
7137 */
7138 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 7139 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 7140 field_value);
7141 } else {
7142 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7143 vmx_instruction_info, true, &gva))
49f705c5
NHE		 7144 return 1;
7145 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7146 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7147 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7148 }
7149
7150 nested_vmx_succeed(vcpu);
7151 skip_emulated_instruction(vcpu);
7152 return 1;
7153}
7154
7155
7156static int handle_vmwrite(struct kvm_vcpu *vcpu)
7157{
7158 unsigned long field;
7159 gva_t gva;
7160 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7161 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 7162 /* The value to write might be 32 or 64 bits, depending on L1's long
7163 * mode, and eventually we need to write that into a field of several
7164 * possible lengths. The code below first zero-extends the value to 64
7165 * bit (field_value), and then copies only the approriate number of
7166 * bits into the vmcs12 field.
7167 */
7168 u64 field_value = 0;
7169 struct x86_exception e;
7170
7171 if (!nested_vmx_check_permission(vcpu) ||
7172 !nested_vmx_check_vmcs12(vcpu))
7173 return 1;
7174
7175 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7176 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 7177 (((vmx_instruction_info) >> 3) & 0xf));
7178 else {
7179 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7180 vmx_instruction_info, false, &gva))
49f705c5
NHE		 7181 return 1;
7182 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7183 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 7184 kvm_inject_page_fault(vcpu, &e);
7185 return 1;
7186 }
7187 }
7188
7189
27e6fb5d 7190 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 7191 if (vmcs_field_readonly(field)) {
7192 nested_vmx_failValid(vcpu,
7193 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7194 skip_emulated_instruction(vcpu);
7195 return 1;
7196 }
7197
a2ae9df7 7198 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 7199 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7200 skip_emulated_instruction(vcpu);
7201 return 1;
7202 }
7203
7204 nested_vmx_succeed(vcpu);
7205 skip_emulated_instruction(vcpu);
7206 return 1;
7207}
7208
63846663
NHE		 7209/* Emulate the VMPTRLD instruction */
7210static int handle_vmptrld(struct kvm_vcpu *vcpu)
7211{
7212 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7213 gpa_t vmptr;
63846663
NHE		 7214
7215 if (!nested_vmx_check_permission(vcpu))
7216 return 1;
7217
4291b588 7218 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 7219 return 1;
63846663
NHE		 7220
7221 if (vmx->nested.current_vmptr != vmptr) {
7222 struct vmcs12 *new_vmcs12;
7223 struct page *page;
7224 page = nested_get_page(vcpu, vmptr);
7225 if (page == NULL) {
7226 nested_vmx_failInvalid(vcpu);
7227 skip_emulated_instruction(vcpu);
7228 return 1;
7229 }
7230 new_vmcs12 = kmap(page);
7231 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7232 kunmap(page);
7233 nested_release_page_clean(page);
7234 nested_vmx_failValid(vcpu,
7235 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7236 skip_emulated_instruction(vcpu);
7237 return 1;
7238 }
63846663 7239
9a2a05b9 7240 nested_release_vmcs12(vmx);
63846663
NHE		 7241 vmx->nested.current_vmptr = vmptr;
7242 vmx->nested.current_vmcs12 = new_vmcs12;
7243 vmx->nested.current_vmcs12_page = page;
012f83cb 7244 if (enable_shadow_vmcs) {
7ec36296
XG		 7245 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7246 SECONDARY_EXEC_SHADOW_VMCS);
8a1b9dd0
AG		 7247 vmcs_write64(VMCS_LINK_POINTER,
7248 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 7249 vmx->nested.sync_shadow_vmcs = true;
7250 }
63846663
NHE		 7251 }
7252
7253 nested_vmx_succeed(vcpu);
7254 skip_emulated_instruction(vcpu);
7255 return 1;
7256}
7257
6a4d7550
NHE		 7258/* Emulate the VMPTRST instruction */
7259static int handle_vmptrst(struct kvm_vcpu *vcpu)
7260{
7261 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7262 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7263 gva_t vmcs_gva;
7264 struct x86_exception e;
7265
7266 if (!nested_vmx_check_permission(vcpu))
7267 return 1;
7268
7269 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7270 vmx_instruction_info, true, &vmcs_gva))
6a4d7550
NHE		 7271 return 1;
7272 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7273 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7274 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7275 sizeof(u64), &e)) {
7276 kvm_inject_page_fault(vcpu, &e);
7277 return 1;
7278 }
7279 nested_vmx_succeed(vcpu);
7280 skip_emulated_instruction(vcpu);
7281 return 1;
7282}
7283
bfd0a56b
NHE		 7284/* Emulate the INVEPT instruction */
7285static int handle_invept(struct kvm_vcpu *vcpu)
7286{
b9c237bb 7287 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7288 u32 vmx_instruction_info, types;
7289 unsigned long type;
7290 gva_t gva;
7291 struct x86_exception e;
7292 struct {
7293 u64 eptp, gpa;
7294 } operand;
bfd0a56b 7295
b9c237bb
WV		 7296 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7297 SECONDARY_EXEC_ENABLE_EPT) ||
7298 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7299 kvm_queue_exception(vcpu, UD_VECTOR);
7300 return 1;
7301 }
7302
7303 if (!nested_vmx_check_permission(vcpu))
7304 return 1;
7305
7306 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7307 kvm_queue_exception(vcpu, UD_VECTOR);
7308 return 1;
7309 }
7310
7311 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7312 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7313
b9c237bb 7314 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7315
7316 if (!(types & (1UL << type))) {
7317 nested_vmx_failValid(vcpu,
7318 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7319 return 1;
7320 }
7321
7322 /* According to the Intel VMX instruction reference, the memory
7323 * operand is read even if it isn't needed (e.g., for type==global)
7324 */
7325 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7326 vmx_instruction_info, false, &gva))
bfd0a56b
NHE		 7327 return 1;
7328 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7329 sizeof(operand), &e)) {
7330 kvm_inject_page_fault(vcpu, &e);
7331 return 1;
7332 }
7333
7334 switch (type) {
bfd0a56b
NHE		 7335 case VMX_EPT_EXTENT_GLOBAL:
7336 kvm_mmu_sync_roots(vcpu);
77c3913b 7337 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7338 nested_vmx_succeed(vcpu);
7339 break;
7340 default:
4b855078 7341 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7342 BUG_ON(1);
7343 break;
7344 }
7345
7346 skip_emulated_instruction(vcpu);
7347 return 1;
7348}
7349
a642fc30
PM		 7350static int handle_invvpid(struct kvm_vcpu *vcpu)
7351{
99b83ac8
WL		 7352 struct vcpu_vmx *vmx = to_vmx(vcpu);
7353 u32 vmx_instruction_info;
7354 unsigned long type, types;
7355 gva_t gva;
7356 struct x86_exception e;
7357 int vpid;
7358
7359 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7360 SECONDARY_EXEC_ENABLE_VPID) ||
7361 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7362 kvm_queue_exception(vcpu, UD_VECTOR);
7363 return 1;
7364 }
7365
7366 if (!nested_vmx_check_permission(vcpu))
7367 return 1;
7368
7369 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7370 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7371
7372 types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7373
7374 if (!(types & (1UL << type))) {
7375 nested_vmx_failValid(vcpu,
7376 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7377 return 1;
7378 }
7379
7380 /* according to the intel vmx instruction reference, the memory
7381 * operand is read even if it isn't needed (e.g., for type==global)
7382 */
7383 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7384 vmx_instruction_info, false, &gva))
7385 return 1;
7386 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7387 sizeof(u32), &e)) {
7388 kvm_inject_page_fault(vcpu, &e);
7389 return 1;
7390 }
7391
7392 switch (type) {
7393 case VMX_VPID_EXTENT_ALL_CONTEXT:
7394 if (get_vmcs12(vcpu)->virtual_processor_id == 0) {
7395 nested_vmx_failValid(vcpu,
7396 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7397 return 1;
7398 }
5c614b35 7399 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
99b83ac8
WL		 7400 nested_vmx_succeed(vcpu);
7401 break;
7402 default:
7403 /* Trap single context invalidation invvpid calls */
7404 BUG_ON(1);
7405 break;
7406 }
7407
7408 skip_emulated_instruction(vcpu);
a642fc30
PM		 7409 return 1;
7410}
7411
843e4330
KH		 7412static int handle_pml_full(struct kvm_vcpu *vcpu)
7413{
7414 unsigned long exit_qualification;
7415
7416 trace_kvm_pml_full(vcpu->vcpu_id);
7417
7418 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7419
7420 /*
7421 * PML buffer FULL happened while executing iret from NMI,
7422 * "blocked by NMI" bit has to be set before next VM entry.
7423 */
7424 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7425 cpu_has_virtual_nmis() &&
7426 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7427 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7428 GUEST_INTR_STATE_NMI);
7429
7430 /*
7431 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7432 * here.., and there's no userspace involvement needed for PML.
7433 */
7434 return 1;
7435}
7436
8b3e34e4
XG		 7437static int handle_pcommit(struct kvm_vcpu *vcpu)
7438{
7439 /* we never catch pcommit instruct for L1 guest. */
7440 WARN_ON(1);
7441 return 1;
7442}
7443
6aa8b732
AK		 7444/*
7445 * The exit handlers return 1 if the exit was handled fully and guest execution
7446 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7447 * to be done to userspace and return 0.
7448 */
772e0318 7449static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7450 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7451 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7452 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7453 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7454 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7455 [EXIT_REASON_CR_ACCESS] = handle_cr,
7456 [EXIT_REASON_DR_ACCESS] = handle_dr,
7457 [EXIT_REASON_CPUID] = handle_cpuid,
7458 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7459 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7460 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7461 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7462 [EXIT_REASON_INVD] = handle_invd,
a7052897 7463 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7464 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7465 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7466 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7467 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7468 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7469 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7470 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7471 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7472 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7473 [EXIT_REASON_VMOFF] = handle_vmoff,
7474 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7475 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7476 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7477 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7478 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7479 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7480 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7481 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7482 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7483 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7484 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7485 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7486 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7487 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7488 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7489 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7490 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7491 [EXIT_REASON_XSAVES] = handle_xsaves,
7492 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7493 [EXIT_REASON_PML_FULL] = handle_pml_full,
8b3e34e4 7494 [EXIT_REASON_PCOMMIT] = handle_pcommit,
6aa8b732
AK		 7495};
7496
7497static const int kvm_vmx_max_exit_handlers =
50a3485c 7498 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7499
908a7bdd
JK		 7500static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7501 struct vmcs12 *vmcs12)
7502{
7503 unsigned long exit_qualification;
7504 gpa_t bitmap, last_bitmap;
7505 unsigned int port;
7506 int size;
7507 u8 b;
7508
908a7bdd 7509 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7510 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7511
7512 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7513
7514 port = exit_qualification >> 16;
7515 size = (exit_qualification & 7) + 1;
7516
7517 last_bitmap = (gpa_t)-1;
7518 b = -1;
7519
7520 while (size > 0) {
7521 if (port < 0x8000)
7522 bitmap = vmcs12->io_bitmap_a;
7523 else if (port < 0x10000)
7524 bitmap = vmcs12->io_bitmap_b;
7525 else
1d804d07 7526 return true;
908a7bdd
JK		 7527 bitmap += (port & 0x7fff) / 8;
7528
7529 if (last_bitmap != bitmap)
54bf36aa 7530 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7531 return true;
908a7bdd 7532 if (b & (1 << (port & 7)))
1d804d07 7533 return true;
908a7bdd
JK		 7534
7535 port++;
7536 size--;
7537 last_bitmap = bitmap;
7538 }
7539
1d804d07 7540 return false;
908a7bdd
JK		 7541}
7542
644d711a
NHE		 7543/*
7544 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7545 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7546 * disinterest in the current event (read or write a specific MSR) by using an
7547 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7548 */
7549static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7550 struct vmcs12 *vmcs12, u32 exit_reason)
7551{
7552 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7553 gpa_t bitmap;
7554
cbd29cb6 7555 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7556 return true;
644d711a
NHE		 7557
7558 /*
7559 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7560 * for the four combinations of read/write and low/high MSR numbers.
7561 * First we need to figure out which of the four to use:
7562 */
7563 bitmap = vmcs12->msr_bitmap;
7564 if (exit_reason == EXIT_REASON_MSR_WRITE)
7565 bitmap += 2048;
7566 if (msr_index >= 0xc0000000) {
7567 msr_index -= 0xc0000000;
7568 bitmap += 1024;
7569 }
7570
7571 /* Then read the msr_index'th bit from this bitmap: */
7572 if (msr_index < 1024*8) {
7573 unsigned char b;
54bf36aa 7574 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7575 return true;
644d711a
NHE		 7576 return 1 & (b >> (msr_index & 7));
7577 } else
1d804d07 7578 return true; /* let L1 handle the wrong parameter */
644d711a
NHE		 7579}
7580
7581/*
7582 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7583 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7584 * intercept (via guest_host_mask etc.) the current event.
7585 */
7586static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7587 struct vmcs12 *vmcs12)
7588{
7589 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7590 int cr = exit_qualification & 15;
7591 int reg = (exit_qualification >> 8) & 15;
1e32c079 7592 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7593
7594 switch ((exit_qualification >> 4) & 3) {
7595 case 0: /* mov to cr */
7596 switch (cr) {
7597 case 0:
7598 if (vmcs12->cr0_guest_host_mask &
7599 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7600 return true;
644d711a
NHE		 7601 break;
7602 case 3:
7603 if ((vmcs12->cr3_target_count >= 1 &&
7604 vmcs12->cr3_target_value0 == val) ||
7605 (vmcs12->cr3_target_count >= 2 &&
7606 vmcs12->cr3_target_value1 == val) ||
7607 (vmcs12->cr3_target_count >= 3 &&
7608 vmcs12->cr3_target_value2 == val) ||
7609 (vmcs12->cr3_target_count >= 4 &&
7610 vmcs12->cr3_target_value3 == val))
1d804d07 7611 return false;
644d711a 7612 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7613 return true;
644d711a
NHE		 7614 break;
7615 case 4:
7616 if (vmcs12->cr4_guest_host_mask &
7617 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7618 return true;
644d711a
NHE		 7619 break;
7620 case 8:
7621 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7622 return true;
644d711a
NHE		 7623 break;
7624 }
7625 break;
7626 case 2: /* clts */
7627 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7628 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7629 return true;
644d711a
NHE		 7630 break;
7631 case 1: /* mov from cr */
7632 switch (cr) {
7633 case 3:
7634 if (vmcs12->cpu_based_vm_exec_control &
7635 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7636 return true;
644d711a
NHE		 7637 break;
7638 case 8:
7639 if (vmcs12->cpu_based_vm_exec_control &
7640 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7641 return true;
644d711a
NHE		 7642 break;
7643 }
7644 break;
7645 case 3: /* lmsw */
7646 /*
7647 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7648 * cr0. Other attempted changes are ignored, with no exit.
7649 */
7650 if (vmcs12->cr0_guest_host_mask & 0xe &
7651 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7652 return true;
644d711a
NHE		 7653 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7654 !(vmcs12->cr0_read_shadow & 0x1) &&
7655 (val & 0x1))
1d804d07 7656 return true;
644d711a
NHE		 7657 break;
7658 }
1d804d07 7659 return false;
644d711a
NHE		 7660}
7661
7662/*
7663 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7664 * should handle it ourselves in L0 (and then continue L2). Only call this
7665 * when in is_guest_mode (L2).
7666 */
7667static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7668{
644d711a
NHE		 7669 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7670 struct vcpu_vmx *vmx = to_vmx(vcpu);
7671 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7672 u32 exit_reason = vmx->exit_reason;
644d711a 7673
542060ea
JK		 7674 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7675 vmcs_readl(EXIT_QUALIFICATION),
7676 vmx->idt_vectoring_info,
7677 intr_info,
7678 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7679 KVM_ISA_VMX);
7680
644d711a 7681 if (vmx->nested.nested_run_pending)
1d804d07 7682 return false;
644d711a
NHE		 7683
7684 if (unlikely(vmx->fail)) {
bd80158a
JK		 7685 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7686 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 7687 return true;
644d711a
NHE		 7688 }
7689
7690 switch (exit_reason) {
7691 case EXIT_REASON_EXCEPTION_NMI:
7692 if (!is_exception(intr_info))
1d804d07 7693 return false;
644d711a
NHE		 7694 else if (is_page_fault(intr_info))
7695 return enable_ept;
e504c909 7696 else if (is_no_device(intr_info) &&
ccf9844e 7697 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 7698 return false;
644d711a
NHE		 7699 return vmcs12->exception_bitmap &
7700 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7701 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 7702 return false;
644d711a 7703 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 7704 return true;
644d711a 7705 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7706 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7707 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7708 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 7709 case EXIT_REASON_TASK_SWITCH:
1d804d07 7710 return true;
644d711a 7711 case EXIT_REASON_CPUID:
bc613494 7712 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
1d804d07
JP		 7713 return false;
7714 return true;
644d711a
NHE		 7715 case EXIT_REASON_HLT:
7716 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7717 case EXIT_REASON_INVD:
1d804d07 7718 return true;
644d711a
NHE		 7719 case EXIT_REASON_INVLPG:
7720 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7721 case EXIT_REASON_RDPMC:
7722 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
b3a2a907 7723 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE		 7724 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7725 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7726 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7727 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7728 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7729 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7730 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7731 /*
7732 * VMX instructions trap unconditionally. This allows L1 to
7733 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7734 */
1d804d07 7735 return true;
644d711a
NHE		 7736 case EXIT_REASON_CR_ACCESS:
7737 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7738 case EXIT_REASON_DR_ACCESS:
7739 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7740 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7741 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7742 case EXIT_REASON_MSR_READ:
7743 case EXIT_REASON_MSR_WRITE:
7744 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7745 case EXIT_REASON_INVALID_STATE:
1d804d07 7746 return true;
644d711a
NHE		 7747 case EXIT_REASON_MWAIT_INSTRUCTION:
7748 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD		 7749 case EXIT_REASON_MONITOR_TRAP_FLAG:
7750 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE		 7751 case EXIT_REASON_MONITOR_INSTRUCTION:
7752 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7753 case EXIT_REASON_PAUSE_INSTRUCTION:
7754 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7755 nested_cpu_has2(vmcs12,
7756 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7757 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 7758 return false;
644d711a 7759 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7760 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7761 case EXIT_REASON_APIC_ACCESS:
7762 return nested_cpu_has2(vmcs12,
7763 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 7764 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 7765 case EXIT_REASON_EOI_INDUCED:
7766 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 7767 return true;
644d711a 7768 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7769 /*
7770 * L0 always deals with the EPT violation. If nested EPT is
7771 * used, and the nested mmu code discovers that the address is
7772 * missing in the guest EPT table (EPT12), the EPT violation
7773 * will be injected with nested_ept_inject_page_fault()
7774 */
1d804d07 7775 return false;
644d711a 7776 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7777 /*
7778 * L2 never uses directly L1's EPT, but rather L0's own EPT
7779 * table (shadow on EPT) or a merged EPT table that L0 built
7780 * (EPT on EPT). So any problems with the structure of the
7781 * table is L0's fault.
7782 */
1d804d07 7783 return false;
644d711a
NHE		 7784 case EXIT_REASON_WBINVD:
7785 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7786 case EXIT_REASON_XSETBV:
1d804d07 7787 return true;
81dc01f7
WL		 7788 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7789 /*
7790 * This should never happen, since it is not possible to
7791 * set XSS to a non-zero value---neither in L1 nor in L2.
7792 * If if it were, XSS would have to be checked against
7793 * the XSS exit bitmap in vmcs12.
7794 */
7795 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8b3e34e4
XG		 7796 case EXIT_REASON_PCOMMIT:
7797 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
644d711a 7798 default:
1d804d07 7799 return true;
644d711a
NHE		 7800 }
7801}
7802
586f9607
AK		 7803static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7804{
7805 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7806 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7807}
7808
a3eaa864 7809static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
843e4330
KH		 7810{
7811 struct page *pml_pg;
843e4330
KH		 7812
7813 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7814 if (!pml_pg)
7815 return -ENOMEM;
7816
7817 vmx->pml_pg = pml_pg;
7818
7819 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7820 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7821
843e4330
KH		 7822 return 0;
7823}
7824
a3eaa864 7825static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
843e4330 7826{
a3eaa864
KH		 7827 if (vmx->pml_pg) {
7828 __free_page(vmx->pml_pg);
7829 vmx->pml_pg = NULL;
7830 }
843e4330
KH		 7831}
7832
54bf36aa 7833static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 7834{
54bf36aa 7835 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH		 7836 u64 *pml_buf;
7837 u16 pml_idx;
7838
7839 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7840
7841 /* Do nothing if PML buffer is empty */
7842 if (pml_idx == (PML_ENTITY_NUM - 1))
7843 return;
7844
7845 /* PML index always points to next available PML buffer entity */
7846 if (pml_idx >= PML_ENTITY_NUM)
7847 pml_idx = 0;
7848 else
7849 pml_idx++;
7850
7851 pml_buf = page_address(vmx->pml_pg);
7852 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7853 u64 gpa;
7854
7855 gpa = pml_buf[pml_idx];
7856 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 7857 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH		 7858 }
7859
7860 /* reset PML index */
7861 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7862}
7863
7864/*
7865 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7866 * Called before reporting dirty_bitmap to userspace.
7867 */
7868static void kvm_flush_pml_buffers(struct kvm *kvm)
7869{
7870 int i;
7871 struct kvm_vcpu *vcpu;
7872 /*
7873 * We only need to kick vcpu out of guest mode here, as PML buffer
7874 * is flushed at beginning of all VMEXITs, and it's obvious that only
7875 * vcpus running in guest are possible to have unflushed GPAs in PML
7876 * buffer.
7877 */
7878 kvm_for_each_vcpu(i, vcpu, kvm)
7879 kvm_vcpu_kick(vcpu);
7880}
7881
4eb64dce
PB		 7882static void vmx_dump_sel(char *name, uint32_t sel)
7883{
7884 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7885 name, vmcs_read32(sel),
7886 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7887 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7888 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7889}
7890
7891static void vmx_dump_dtsel(char *name, uint32_t limit)
7892{
7893 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7894 name, vmcs_read32(limit),
7895 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7896}
7897
7898static void dump_vmcs(void)
7899{
7900 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7901 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7902 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7903 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7904 u32 secondary_exec_control = 0;
7905 unsigned long cr4 = vmcs_readl(GUEST_CR4);
7906 u64 efer = vmcs_readl(GUEST_IA32_EFER);
7907 int i, n;
7908
7909 if (cpu_has_secondary_exec_ctrls())
7910 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7911
7912 pr_err("*** Guest State ***\n");
7913 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7914 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7915 vmcs_readl(CR0_GUEST_HOST_MASK));
7916 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7917 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7918 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7919 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7920 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7921 {
7922 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7923 vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7924 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7925 vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7926 }
7927 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7928 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7929 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7930 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7931 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7932 vmcs_readl(GUEST_SYSENTER_ESP),
7933 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7934 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
7935 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
7936 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
7937 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
7938 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
7939 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
7940 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7941 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7942 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7943 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
7944 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7945 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7946 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7947 efer, vmcs_readl(GUEST_IA32_PAT));
7948 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7949 vmcs_readl(GUEST_IA32_DEBUGCTL),
7950 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7951 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7952 pr_err("PerfGlobCtl = 0x%016lx\n",
7953 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7954 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7955 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7956 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7957 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7958 vmcs_read32(GUEST_ACTIVITY_STATE));
7959 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7960 pr_err("InterruptStatus = %04x\n",
7961 vmcs_read16(GUEST_INTR_STATUS));
7962
7963 pr_err("*** Host State ***\n");
7964 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7965 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7966 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7967 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7968 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7969 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7970 vmcs_read16(HOST_TR_SELECTOR));
7971 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7972 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7973 vmcs_readl(HOST_TR_BASE));
7974 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7975 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7976 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7977 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7978 vmcs_readl(HOST_CR4));
7979 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7980 vmcs_readl(HOST_IA32_SYSENTER_ESP),
7981 vmcs_read32(HOST_IA32_SYSENTER_CS),
7982 vmcs_readl(HOST_IA32_SYSENTER_EIP));
7983 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7984 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7985 vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7986 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7987 pr_err("PerfGlobCtl = 0x%016lx\n",
7988 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7989
7990 pr_err("*** Control State ***\n");
7991 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7992 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7993 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7994 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7995 vmcs_read32(EXCEPTION_BITMAP),
7996 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7997 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7998 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7999 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8000 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8001 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8002 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8003 vmcs_read32(VM_EXIT_INTR_INFO),
8004 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8005 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8006 pr_err(" reason=%08x qualification=%016lx\n",
8007 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8008 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8009 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8010 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8011 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
8cfe9866
HZ		 8012 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8013 pr_err("TSC Multiplier = 0x%016lx\n",
8014 vmcs_readl(TSC_MULTIPLIER));
4eb64dce
PB		 8015 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8016 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8017 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8018 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8019 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8020 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
8021 n = vmcs_read32(CR3_TARGET_COUNT);
8022 for (i = 0; i + 1 < n; i += 4)
8023 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8024 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8025 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8026 if (i < n)
8027 pr_err("CR3 target%u=%016lx\n",
8028 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8029 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8030 pr_err("PLE Gap=%08x Window=%08x\n",
8031 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8032 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8033 pr_err("Virtual processor ID = 0x%04x\n",
8034 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8035}
8036
6aa8b732
AK		 8037/*
8038 * The guest has exited. See if we can fix it or if we need userspace
8039 * assistance.
8040 */
851ba692 8041static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 8042{
29bd8a78 8043 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 8044 u32 exit_reason = vmx->exit_reason;
1155f76a 8045 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 8046
843e4330
KH		 8047 /*
8048 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8049 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8050 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8051 * mode as if vcpus is in root mode, the PML buffer must has been
8052 * flushed already.
8053 */
8054 if (enable_pml)
54bf36aa 8055 vmx_flush_pml_buffer(vcpu);
843e4330 8056
80ced186 8057 /* If guest state is invalid, start emulating */
14168786 8058 if (vmx->emulation_required)
80ced186 8059 return handle_invalid_guest_state(vcpu);
1d5a4d9b 8060
644d711a 8061 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 8062 nested_vmx_vmexit(vcpu, exit_reason,
8063 vmcs_read32(VM_EXIT_INTR_INFO),
8064 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 8065 return 1;
8066 }
8067
5120702e 8068 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 8069 dump_vmcs();
5120702e
MG		 8070 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8071 vcpu->run->fail_entry.hardware_entry_failure_reason
8072 = exit_reason;
8073 return 0;
8074 }
8075
29bd8a78 8076 if (unlikely(vmx->fail)) {
851ba692
AK		 8077 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8078 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 8079 = vmcs_read32(VM_INSTRUCTION_ERROR);
8080 return 0;
8081 }
6aa8b732 8082
b9bf6882
XG		 8083 /*
8084 * Note:
8085 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8086 * delivery event since it indicates guest is accessing MMIO.
8087 * The vm-exit can be triggered again after return to guest that
8088 * will cause infinite loop.
8089 */
d77c26fc 8090 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 8091 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 8092 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 8093 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8094 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8095 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8096 vcpu->run->internal.ndata = 2;
8097 vcpu->run->internal.data[0] = vectoring_info;
8098 vcpu->run->internal.data[1] = exit_reason;
8099 return 0;
8100 }
3b86cd99 8101
644d711a
NHE		 8102 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8103 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 8104 get_vmcs12(vcpu))))) {
c4282df9 8105 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 8106 vmx->soft_vnmi_blocked = 0;
3b86cd99 8107 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 8108 vcpu->arch.nmi_pending) {
3b86cd99
JK		 8109 /*
8110 * This CPU don't support us in finding the end of an
8111 * NMI-blocked window if the guest runs with IRQs
8112 * disabled. So we pull the trigger after 1 s of
8113 * futile waiting, but inform the user about this.
8114 */
8115 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8116 "state on VCPU %d after 1 s timeout\n",
8117 __func__, vcpu->vcpu_id);
8118 vmx->soft_vnmi_blocked = 0;
3b86cd99 8119 }
3b86cd99
JK		 8120 }
8121
6aa8b732
AK		 8122 if (exit_reason < kvm_vmx_max_exit_handlers
8123 && kvm_vmx_exit_handlers[exit_reason])
851ba692 8124 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 8125 else {
2bc19dc3
MT		 8126 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8127 kvm_queue_exception(vcpu, UD_VECTOR);
8128 return 1;
6aa8b732 8129 }
6aa8b732
AK		 8130}
8131
95ba8273 8132static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 8133{
a7c0b07d
WL		 8134 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8135
8136 if (is_guest_mode(vcpu) &&
8137 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8138 return;
8139
95ba8273 8140 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 8141 vmcs_write32(TPR_THRESHOLD, 0);
8142 return;
8143 }
8144
95ba8273 8145 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 8146}
8147
8d14695f
YZ		 8148static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8149{
8150 u32 sec_exec_control;
8151
8152 /*
8153 * There is not point to enable virtualize x2apic without enable
8154 * apicv
8155 */
c7c9c56c 8156 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
35754c98 8157 !vmx_cpu_uses_apicv(vcpu))
8d14695f
YZ		 8158 return;
8159
35754c98 8160 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ		 8161 return;
8162
8163 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8164
8165 if (set) {
8166 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8167 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8168 } else {
8169 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8170 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8171 }
8172 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8173
8174 vmx_set_msr_bitmap(vcpu);
8175}
8176
38b99173
TC		 8177static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8178{
8179 struct vcpu_vmx *vmx = to_vmx(vcpu);
8180
8181 /*
8182 * Currently we do not handle the nested case where L2 has an
8183 * APIC access page of its own; that page is still pinned.
8184 * Hence, we skip the case where the VCPU is in guest mode _and_
8185 * L1 prepared an APIC access page for L2.
8186 *
8187 * For the case where L1 and L2 share the same APIC access page
8188 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8189 * in the vmcs12), this function will only update either the vmcs01
8190 * or the vmcs02. If the former, the vmcs02 will be updated by
8191 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8192 * the next L2->L1 exit.
8193 */
8194 if (!is_guest_mode(vcpu) ||
8195 !nested_cpu_has2(vmx->nested.current_vmcs12,
8196 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8197 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8198}
8199
c7c9c56c
YZ		 8200static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8201{
8202 u16 status;
8203 u8 old;
8204
c7c9c56c
YZ		 8205 if (isr == -1)
8206 isr = 0;
8207
8208 status = vmcs_read16(GUEST_INTR_STATUS);
8209 old = status >> 8;
8210 if (isr != old) {
8211 status &= 0xff;
8212 status |= isr << 8;
8213 vmcs_write16(GUEST_INTR_STATUS, status);
8214 }
8215}
8216
8217static void vmx_set_rvi(int vector)
8218{
8219 u16 status;
8220 u8 old;
8221
4114c27d
WW		 8222 if (vector == -1)
8223 vector = 0;
8224
c7c9c56c
YZ		 8225 status = vmcs_read16(GUEST_INTR_STATUS);
8226 old = (u8)status & 0xff;
8227 if ((u8)vector != old) {
8228 status &= ~0xff;
8229 status |= (u8)vector;
8230 vmcs_write16(GUEST_INTR_STATUS, status);
8231 }
8232}
8233
8234static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8235{
4114c27d
WW		 8236 if (!is_guest_mode(vcpu)) {
8237 vmx_set_rvi(max_irr);
8238 return;
8239 }
8240
c7c9c56c
YZ		 8241 if (max_irr == -1)
8242 return;
8243
963fee16 8244 /*
4114c27d
WW		 8245 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8246 * handles it.
963fee16 8247 */
4114c27d 8248 if (nested_exit_on_intr(vcpu))
963fee16
WL		 8249 return;
8250
963fee16 8251 /*
4114c27d 8252 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 8253 * is run without virtual interrupt delivery.
8254 */
8255 if (!kvm_event_needs_reinjection(vcpu) &&
8256 vmx_interrupt_allowed(vcpu)) {
8257 kvm_queue_interrupt(vcpu, max_irr, false);
8258 vmx_inject_irq(vcpu);
8259 }
c7c9c56c
YZ		 8260}
8261
3bb345f3 8262static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
c7c9c56c 8263{
3bb345f3 8264 u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
35754c98 8265 if (!vmx_cpu_uses_apicv(vcpu))
3d81bc7e
YZ		 8266 return;
8267
c7c9c56c
YZ		 8268 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8269 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8270 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8271 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8272}
8273
51aa01d1 8274static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8275{
00eba012
AK		 8276 u32 exit_intr_info;
8277
8278 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8279 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8280 return;
8281
c5ca8e57 8282 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 8283 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 8284
8285 /* Handle machine checks before interrupts are enabled */
00eba012 8286 if (is_machine_check(exit_intr_info))
a0861c02
AK		 8287 kvm_machine_check();
8288
20f65983 8289 /* We need to handle NMIs before interrupts are enabled */
00eba012 8290 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 8291 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8292 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8293 asm("int $2");
ff9d07a0
ZY		 8294 kvm_after_handle_nmi(&vmx->vcpu);
8295 }
51aa01d1 8296}
20f65983 8297
a547c6db
YZ		 8298static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8299{
8300 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8301
8302 /*
8303 * If external interrupt exists, IF bit is set in rflags/eflags on the
8304 * interrupt stack frame, and interrupt will be enabled on a return
8305 * from interrupt handler.
8306 */
8307 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8308 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8309 unsigned int vector;
8310 unsigned long entry;
8311 gate_desc *desc;
8312 struct vcpu_vmx *vmx = to_vmx(vcpu);
8313#ifdef CONFIG_X86_64
8314 unsigned long tmp;
8315#endif
8316
8317 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8318 desc = (gate_desc *)vmx->host_idt_base + vector;
8319 entry = gate_offset(*desc);
8320 asm volatile(
8321#ifdef CONFIG_X86_64
8322 "mov %%" _ASM_SP ", %[sp]\n\t"
8323 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8324 "push $%c[ss]\n\t"
8325 "push %[sp]\n\t"
8326#endif
8327 "pushf\n\t"
8328 "orl $0x200, (%%" _ASM_SP ")\n\t"
8329 __ASM_SIZE(push) " $%c[cs]\n\t"
8330 "call *%[entry]\n\t"
8331 :
8332#ifdef CONFIG_X86_64
8333 [sp]"=&r"(tmp)
8334#endif
8335 :
8336 [entry]"r"(entry),
8337 [ss]"i"(__KERNEL_DS),
8338 [cs]"i"(__KERNEL_CS)
8339 );
8340 } else
8341 local_irq_enable();
8342}
8343
6d396b55
PB		 8344static bool vmx_has_high_real_mode_segbase(void)
8345{
8346 return enable_unrestricted_guest || emulate_invalid_guest_state;
8347}
8348
da8999d3
LJ		 8349static bool vmx_mpx_supported(void)
8350{
8351 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8352 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8353}
8354
55412b2e
WL		 8355static bool vmx_xsaves_supported(void)
8356{
8357 return vmcs_config.cpu_based_2nd_exec_ctrl &
8358 SECONDARY_EXEC_XSAVES;
8359}
8360
51aa01d1
AK		 8361static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8362{
c5ca8e57 8363 u32 exit_intr_info;
51aa01d1
AK		 8364 bool unblock_nmi;
8365 u8 vector;
8366 bool idtv_info_valid;
8367
8368 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8369
cf393f75 8370 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 8371 if (vmx->nmi_known_unmasked)
8372 return;
c5ca8e57
AK		 8373 /*
8374 * Can't use vmx->exit_intr_info since we're not sure what
8375 * the exit reason is.
8376 */
8377 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 8378 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8379 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8380 /*
7b4a25cb 8381 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 8382 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8383 * a guest IRET fault.
7b4a25cb
GN		 8384 * SDM 3: 23.2.2 (September 2008)
8385 * Bit 12 is undefined in any of the following cases:
8386 * If the VM exit sets the valid bit in the IDT-vectoring
8387 * information field.
8388 * If the VM exit is due to a double fault.
cf393f75 8389 */
7b4a25cb
GN		 8390 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8391 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 8392 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8393 GUEST_INTR_STATE_NMI);
9d58b931
AK		 8394 else
8395 vmx->nmi_known_unmasked =
8396 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8397 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 8398 } else if (unlikely(vmx->soft_vnmi_blocked))
8399 vmx->vnmi_blocked_time +=
8400 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 8401}
8402
3ab66e8a 8403static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 8404 u32 idt_vectoring_info,
8405 int instr_len_field,
8406 int error_code_field)
51aa01d1 8407{
51aa01d1
AK		 8408 u8 vector;
8409 int type;
8410 bool idtv_info_valid;
8411
8412 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8413
3ab66e8a
JK		 8414 vcpu->arch.nmi_injected = false;
8415 kvm_clear_exception_queue(vcpu);
8416 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 8417
8418 if (!idtv_info_valid)
8419 return;
8420
3ab66e8a 8421 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8422
668f612f
AK		 8423 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8424 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8425
64a7ec06 8426 switch (type) {
37b96e98 8427 case INTR_TYPE_NMI_INTR:
3ab66e8a 8428 vcpu->arch.nmi_injected = true;
668f612f 8429 /*
7b4a25cb 8430 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 8431 * Clear bit "block by NMI" before VM entry if a NMI
8432 * delivery faulted.
668f612f 8433 */
3ab66e8a 8434 vmx_set_nmi_mask(vcpu, false);
37b96e98 8435 break;
37b96e98 8436 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8437 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 8438 /* fall through */
8439 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8440 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8441 u32 err = vmcs_read32(error_code_field);
851eb667 8442 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8443 } else
851eb667 8444 kvm_requeue_exception(vcpu, vector);
37b96e98 8445 break;
66fd3f7f 8446 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8447 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8448 /* fall through */
37b96e98 8449 case INTR_TYPE_EXT_INTR:
3ab66e8a 8450 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 8451 break;
8452 default:
8453 break;
f7d9238f 8454 }
cf393f75
AK		 8455}
8456
83422e17
AK		 8457static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8458{
3ab66e8a 8459 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8460 VM_EXIT_INSTRUCTION_LEN,
8461 IDT_VECTORING_ERROR_CODE);
8462}
8463
b463a6f7
AK		 8464static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8465{
3ab66e8a 8466 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8467 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8468 VM_ENTRY_INSTRUCTION_LEN,
8469 VM_ENTRY_EXCEPTION_ERROR_CODE);
8470
8471 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8472}
8473
d7cd9796
GN		 8474static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8475{
8476 int i, nr_msrs;
8477 struct perf_guest_switch_msr *msrs;
8478
8479 msrs = perf_guest_get_msrs(&nr_msrs);
8480
8481 if (!msrs)
8482 return;
8483
8484 for (i = 0; i < nr_msrs; i++)
8485 if (msrs[i].host == msrs[i].guest)
8486 clear_atomic_switch_msr(vmx, msrs[i].msr);
8487 else
8488 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8489 msrs[i].host);
8490}
8491
a3b5ba49 8492static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8493{
a2fa3e9f 8494 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8495 unsigned long debugctlmsr, cr4;
104f226b
AK		 8496
8497 /* Record the guest's net vcpu time for enforced NMI injections. */
8498 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8499 vmx->entry_time = ktime_get();
8500
8501 /* Don't enter VMX if guest state is invalid, let the exit handler
8502 start emulation until we arrive back to a valid state */
14168786 8503 if (vmx->emulation_required)
104f226b
AK		 8504 return;
8505
a7653ecd
RK		 8506 if (vmx->ple_window_dirty) {
8507 vmx->ple_window_dirty = false;
8508 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8509 }
8510
012f83cb
AG		 8511 if (vmx->nested.sync_shadow_vmcs) {
8512 copy_vmcs12_to_shadow(vmx);
8513 vmx->nested.sync_shadow_vmcs = false;
8514 }
8515
104f226b
AK		 8516 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8517 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8518 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8519 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8520
1e02ce4c 8521 cr4 = cr4_read_shadow();
d974baa3
AL		 8522 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8523 vmcs_writel(HOST_CR4, cr4);
8524 vmx->host_state.vmcs_host_cr4 = cr4;
8525 }
8526
104f226b
AK		 8527 /* When single-stepping over STI and MOV SS, we must clear the
8528 * corresponding interruptibility bits in the guest state. Otherwise
8529 * vmentry fails as it then expects bit 14 (BS) in pending debug
8530 * exceptions being set, but that's not correct for the guest debugging
8531 * case. */
8532 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8533 vmx_set_interrupt_shadow(vcpu, 0);
8534
d7cd9796 8535 atomic_switch_perf_msrs(vmx);
2a7921b7 8536 debugctlmsr = get_debugctlmsr();
d7cd9796 8537
d462b819 8538 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8539 asm(
6aa8b732 8540 /* Store host registers */
b188c81f
AK		 8541 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8542 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8543 "push %%" _ASM_CX " \n\t"
8544 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8545 "je 1f \n\t"
b188c81f 8546 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8547 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8548 "1: \n\t"
d3edefc0 8549 /* Reload cr2 if changed */
b188c81f
AK		 8550 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8551 "mov %%cr2, %%" _ASM_DX " \n\t"
8552 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8553 "je 2f \n\t"
b188c81f 8554 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8555 "2: \n\t"
6aa8b732 8556 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8557 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8558 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8559 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8560 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8561 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8562 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8563 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8564 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8565#ifdef CONFIG_X86_64
e08aa78a
AK		 8566 "mov %c[r8](%0), %%r8 \n\t"
8567 "mov %c[r9](%0), %%r9 \n\t"
8568 "mov %c[r10](%0), %%r10 \n\t"
8569 "mov %c[r11](%0), %%r11 \n\t"
8570 "mov %c[r12](%0), %%r12 \n\t"
8571 "mov %c[r13](%0), %%r13 \n\t"
8572 "mov %c[r14](%0), %%r14 \n\t"
8573 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8574#endif
b188c81f 8575 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8576
6aa8b732 8577 /* Enter guest mode */
83287ea4 8578 "jne 1f \n\t"
4ecac3fd 8579 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8580 "jmp 2f \n\t"
8581 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8582 "2: "
6aa8b732 8583 /* Save guest registers, load host registers, keep flags */
b188c81f 8584 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8585 "pop %0 \n\t"
b188c81f
AK		 8586 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8587 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8588 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8589 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8590 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8591 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8592 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8593#ifdef CONFIG_X86_64
e08aa78a
AK		 8594 "mov %%r8, %c[r8](%0) \n\t"
8595 "mov %%r9, %c[r9](%0) \n\t"
8596 "mov %%r10, %c[r10](%0) \n\t"
8597 "mov %%r11, %c[r11](%0) \n\t"
8598 "mov %%r12, %c[r12](%0) \n\t"
8599 "mov %%r13, %c[r13](%0) \n\t"
8600 "mov %%r14, %c[r14](%0) \n\t"
8601 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8602#endif
b188c81f
AK		 8603 "mov %%cr2, %%" _ASM_AX " \n\t"
8604 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8605
b188c81f 8606 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8607 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8608 ".pushsection .rodata \n\t"
8609 ".global vmx_return \n\t"
8610 "vmx_return: " _ASM_PTR " 2b \n\t"
8611 ".popsection"
e08aa78a 8612 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8613 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8614 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8615 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8616 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8617 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8618 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8619 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8620 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8621 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8622 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8623#ifdef CONFIG_X86_64
ad312c7c
ZX		 8624 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8625 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8626 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8627 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8628 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8629 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8630 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8631 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8632#endif
40712fae
AK		 8633 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8634 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8635 : "cc", "memory"
8636#ifdef CONFIG_X86_64
b188c81f 8637 , "rax", "rbx", "rdi", "rsi"
c2036300 8638 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8639#else
8640 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8641#endif
8642 );
6aa8b732 8643
2a7921b7
GN		 8644 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8645 if (debugctlmsr)
8646 update_debugctlmsr(debugctlmsr);
8647
aa67f609
AK		 8648#ifndef CONFIG_X86_64
8649 /*
8650 * The sysexit path does not restore ds/es, so we must set them to
8651 * a reasonable value ourselves.
8652 *
8653 * We can't defer this to vmx_load_host_state() since that function
8654 * may be executed in interrupt context, which saves and restore segments
8655 * around it, nullifying its effect.
8656 */
8657 loadsegment(ds, __USER_DS);
8658 loadsegment(es, __USER_DS);
8659#endif
8660
6de4f3ad 8661 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8662 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8663 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8664 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8665 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8666 vcpu->arch.regs_dirty = 0;
8667
1155f76a
AK		 8668 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8669
d462b819 8670 vmx->loaded_vmcs->launched = 1;
1b6269db 8671
51aa01d1 8672 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8673 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8674
e0b890d3
GN		 8675 /*
8676 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8677 * we did not inject a still-pending event to L1 now because of
8678 * nested_run_pending, we need to re-enable this bit.
8679 */
8680 if (vmx->nested.nested_run_pending)
8681 kvm_make_request(KVM_REQ_EVENT, vcpu);
8682
8683 vmx->nested.nested_run_pending = 0;
8684
51aa01d1
AK		 8685 vmx_complete_atomic_exit(vmx);
8686 vmx_recover_nmi_blocking(vmx);
cf393f75 8687 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8688}
8689
4fa7734c
PB		 8690static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8691{
8692 struct vcpu_vmx *vmx = to_vmx(vcpu);
8693 int cpu;
8694
8695 if (vmx->loaded_vmcs == &vmx->vmcs01)
8696 return;
8697
8698 cpu = get_cpu();
8699 vmx->loaded_vmcs = &vmx->vmcs01;
8700 vmx_vcpu_put(vcpu);
8701 vmx_vcpu_load(vcpu, cpu);
8702 vcpu->cpu = cpu;
8703 put_cpu();
8704}
8705
6aa8b732
AK		 8706static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8707{
fb3f0f51
RR		 8708 struct vcpu_vmx *vmx = to_vmx(vcpu);
8709
843e4330 8710 if (enable_pml)
a3eaa864 8711 vmx_destroy_pml_buffer(vmx);
991e7a0e 8712 free_vpid(vmx->vpid);
4fa7734c
PB		 8713 leave_guest_mode(vcpu);
8714 vmx_load_vmcs01(vcpu);
26a865f4 8715 free_nested(vmx);
4fa7734c 8716 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8717 kfree(vmx->guest_msrs);
8718 kvm_vcpu_uninit(vcpu);
a4770347 8719 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8720}
8721
fb3f0f51 8722static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8723{
fb3f0f51 8724 int err;
c16f862d 8725 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8726 int cpu;
6aa8b732 8727
a2fa3e9f 8728 if (!vmx)
fb3f0f51
RR		 8729 return ERR_PTR(-ENOMEM);
8730
991e7a0e 8731 vmx->vpid = allocate_vpid();
2384d2b3 8732
fb3f0f51
RR		 8733 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8734 if (err)
8735 goto free_vcpu;
965b58a5 8736
a2fa3e9f 8737 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8738 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8739 > PAGE_SIZE);
0123be42 8740
be6d05cf 8741 err = -ENOMEM;
fb3f0f51 8742 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8743 goto uninit_vcpu;
8744 }
965b58a5 8745
d462b819
NHE		 8746 vmx->loaded_vmcs = &vmx->vmcs01;
8747 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8748 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8749 goto free_msrs;
d462b819
NHE		 8750 if (!vmm_exclusive)
8751 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8752 loaded_vmcs_init(vmx->loaded_vmcs);
8753 if (!vmm_exclusive)
8754 kvm_cpu_vmxoff();
a2fa3e9f 8755
15ad7146
AK		 8756 cpu = get_cpu();
8757 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8758 vmx->vcpu.cpu = cpu;
8b9cf98c 8759 err = vmx_vcpu_setup(vmx);
fb3f0f51 8760 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8761 put_cpu();
fb3f0f51
RR		 8762 if (err)
8763 goto free_vmcs;
35754c98 8764 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK		 8765 err = alloc_apic_access_page(kvm);
8766 if (err)
5e4a0b3c 8767 goto free_vmcs;
a63cb560 8768 }
fb3f0f51 8769
b927a3ce
SY		 8770 if (enable_ept) {
8771 if (!kvm->arch.ept_identity_map_addr)
8772 kvm->arch.ept_identity_map_addr =
8773 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8774 err = init_rmode_identity_map(kvm);
8775 if (err)
93ea5388 8776 goto free_vmcs;
b927a3ce 8777 }
b7ebfb05 8778
5c614b35 8779 if (nested) {
b9c237bb 8780 nested_vmx_setup_ctls_msrs(vmx);
5c614b35
WL		 8781 vmx->nested.vpid02 = allocate_vpid();
8782 }
b9c237bb 8783
705699a1 8784 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE		 8785 vmx->nested.current_vmptr = -1ull;
8786 vmx->nested.current_vmcs12 = NULL;
8787
843e4330
KH		 8788 /*
8789 * If PML is turned on, failure on enabling PML just results in failure
8790 * of creating the vcpu, therefore we can simplify PML logic (by
8791 * avoiding dealing with cases, such as enabling PML partially on vcpus
8792 * for the guest, etc.
8793 */
8794 if (enable_pml) {
a3eaa864 8795 err = vmx_create_pml_buffer(vmx);
843e4330
KH		 8796 if (err)
8797 goto free_vmcs;
8798 }
8799
fb3f0f51
RR		 8800 return &vmx->vcpu;
8801
8802free_vmcs:
5c614b35 8803 free_vpid(vmx->nested.vpid02);
5f3fbc34 8804 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8805free_msrs:
fb3f0f51
RR		 8806 kfree(vmx->guest_msrs);
8807uninit_vcpu:
8808 kvm_vcpu_uninit(&vmx->vcpu);
8809free_vcpu:
991e7a0e 8810 free_vpid(vmx->vpid);
a4770347 8811 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8812 return ERR_PTR(err);
6aa8b732
AK		 8813}
8814
002c7f7c
YS		 8815static void __init vmx_check_processor_compat(void *rtn)
8816{
8817 struct vmcs_config vmcs_conf;
8818
8819 *(int *)rtn = 0;
8820 if (setup_vmcs_config(&vmcs_conf) < 0)
8821 *(int *)rtn = -EIO;
8822 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8823 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8824 smp_processor_id());
8825 *(int *)rtn = -EIO;
8826 }
8827}
8828
67253af5
SY		 8829static int get_ept_level(void)
8830{
8831 return VMX_EPT_DEFAULT_GAW + 1;
8832}
8833
4b12f0de 8834static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8835{
b18d5431
XG		 8836 u8 cache;
8837 u64 ipat = 0;
4b12f0de 8838
522c68c4 8839 /* For VT-d and EPT combination
606decd6 8840 * 1. MMIO: always map as UC
522c68c4
SY		 8841 * 2. EPT with VT-d:
8842 * a. VT-d without snooping control feature: can't guarantee the
606decd6 8843 * result, try to trust guest.
522c68c4
SY		 8844 * b. VT-d with snooping control feature: snooping control feature of
8845 * VT-d engine can guarantee the cache correctness. Just set it
8846 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8847 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8848 * consistent with host MTRR
8849 */
606decd6
PB		 8850 if (is_mmio) {
8851 cache = MTRR_TYPE_UNCACHABLE;
8852 goto exit;
8853 }
8854
8855 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG		 8856 ipat = VMX_EPT_IPAT_BIT;
8857 cache = MTRR_TYPE_WRBACK;
8858 goto exit;
8859 }
8860
8861 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8862 ipat = VMX_EPT_IPAT_BIT;
0da029ed 8863 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG		 8864 cache = MTRR_TYPE_WRBACK;
8865 else
8866 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG		 8867 goto exit;
8868 }
8869
ff53604b 8870 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG		 8871
8872exit:
8873 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY		 8874}
8875
17cc3935 8876static int vmx_get_lpage_level(void)
344f414f 8877{
878403b7
SY		 8878 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8879 return PT_DIRECTORY_LEVEL;
8880 else
8881 /* For shadow and EPT supported 1GB page */
8882 return PT_PDPE_LEVEL;
344f414f
JR		 8883}
8884
feda805f
XG		 8885static void vmcs_set_secondary_exec_control(u32 new_ctl)
8886{
8887 /*
8888 * These bits in the secondary execution controls field
8889 * are dynamic, the others are mostly based on the hypervisor
8890 * architecture and the guest's CPUID. Do not touch the
8891 * dynamic bits.
8892 */
8893 u32 mask =
8894 SECONDARY_EXEC_SHADOW_VMCS |
8895 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8896 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8897
8898 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8899
8900 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8901 (new_ctl & ~mask) | (cur_ctl & mask));
8902}
8903
0e851880
SY		 8904static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8905{
4e47c7a6
SY		 8906 struct kvm_cpuid_entry2 *best;
8907 struct vcpu_vmx *vmx = to_vmx(vcpu);
feda805f 8908 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
4e47c7a6 8909
4e47c7a6 8910 if (vmx_rdtscp_supported()) {
1cea0ce6
XG		 8911 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8912 if (!rdtscp_enabled)
feda805f 8913 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
f36201e5 8914
8b97265a 8915 if (nested) {
1cea0ce6 8916 if (rdtscp_enabled)
8b97265a
PB		 8917 vmx->nested.nested_vmx_secondary_ctls_high |=
8918 SECONDARY_EXEC_RDTSCP;
8919 else
8920 vmx->nested.nested_vmx_secondary_ctls_high &=
8921 ~SECONDARY_EXEC_RDTSCP;
8922 }
4e47c7a6 8923 }
ad756a16 8924
ad756a16
MJ		 8925 /* Exposing INVPCID only when PCID is exposed */
8926 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8927 if (vmx_invpcid_supported() &&
29541bb8
XG		 8928 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8929 !guest_cpuid_has_pcid(vcpu))) {
feda805f 8930 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
29541bb8 8931
ad756a16 8932 if (best)
4f977045 8933 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8934 }
8b3e34e4 8935
feda805f
XG		 8936 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8937
8b3e34e4
XG		 8938 if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8939 if (guest_cpuid_has_pcommit(vcpu))
8940 vmx->nested.nested_vmx_secondary_ctls_high |=
8941 SECONDARY_EXEC_PCOMMIT;
8942 else
8943 vmx->nested.nested_vmx_secondary_ctls_high &=
8944 ~SECONDARY_EXEC_PCOMMIT;
8945 }
0e851880
SY		 8946}
8947
d4330ef2
JR		 8948static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8949{
7b8050f5
NHE		 8950 if (func == 1 && nested)
8951 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8952}
8953
25d92081
YZ		 8954static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8955 struct x86_exception *fault)
8956{
533558bc
JK		 8957 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8958 u32 exit_reason;
25d92081
YZ		 8959
8960 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8961 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8962 else
533558bc
JK		 8963 exit_reason = EXIT_REASON_EPT_VIOLATION;
8964 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8965 vmcs12->guest_physical_address = fault->address;
8966}
8967
155a97a3
NHE		 8968/* Callbacks for nested_ept_init_mmu_context: */
8969
8970static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8971{
8972 /* return the page table to be shadowed - in our case, EPT12 */
8973 return get_vmcs12(vcpu)->ept_pointer;
8974}
8975
8a3c1a33 8976static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8977{
ad896af0
PB		 8978 WARN_ON(mmu_is_nested(vcpu));
8979 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8980 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8981 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8982 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8983 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8984 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8985
8986 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8987}
8988
8989static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8990{
8991 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8992}
8993
19d5f10b
EK		 8994static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8995 u16 error_code)
8996{
8997 bool inequality, bit;
8998
8999 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9000 inequality =
9001 (error_code & vmcs12->page_fault_error_code_mask) !=
9002 vmcs12->page_fault_error_code_match;
9003 return inequality ^ bit;
9004}
9005
feaf0c7d
GN		 9006static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9007 struct x86_exception *fault)
9008{
9009 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9010
9011 WARN_ON(!is_guest_mode(vcpu));
9012
19d5f10b 9013 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 9014 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9015 vmcs_read32(VM_EXIT_INTR_INFO),
9016 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 9017 else
9018 kvm_inject_page_fault(vcpu, fault);
9019}
9020
a2bcba50
WL		 9021static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9022 struct vmcs12 *vmcs12)
9023{
9024 struct vcpu_vmx *vmx = to_vmx(vcpu);
9090422f 9025 int maxphyaddr = cpuid_maxphyaddr(vcpu);
a2bcba50
WL		 9026
9027 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9090422f
EK		 9028 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9029 vmcs12->apic_access_addr >> maxphyaddr)
a2bcba50
WL		 9030 return false;
9031
9032 /*
9033 * Translate L1 physical address to host physical
9034 * address for vmcs02. Keep the page pinned, so this
9035 * physical address remains valid. We keep a reference
9036 * to it so we can release it later.
9037 */
9038 if (vmx->nested.apic_access_page) /* shouldn't happen */
9039 nested_release_page(vmx->nested.apic_access_page);
9040 vmx->nested.apic_access_page =
9041 nested_get_page(vcpu, vmcs12->apic_access_addr);
9042 }
a7c0b07d
WL		 9043
9044 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9090422f
EK		 9045 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9046 vmcs12->virtual_apic_page_addr >> maxphyaddr)
a7c0b07d
WL		 9047 return false;
9048
9049 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9050 nested_release_page(vmx->nested.virtual_apic_page);
9051 vmx->nested.virtual_apic_page =
9052 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9053
9054 /*
9055 * Failing the vm entry is _not_ what the processor does
9056 * but it's basically the only possibility we have.
9057 * We could still enter the guest if CR8 load exits are
9058 * enabled, CR8 store exits are enabled, and virtualize APIC
9059 * access is disabled; in this case the processor would never
9060 * use the TPR shadow and we could simply clear the bit from
9061 * the execution control. But such a configuration is useless,
9062 * so let's keep the code simple.
9063 */
9064 if (!vmx->nested.virtual_apic_page)
9065 return false;
9066 }
9067
705699a1 9068 if (nested_cpu_has_posted_intr(vmcs12)) {
9090422f
EK		 9069 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9070 vmcs12->posted_intr_desc_addr >> maxphyaddr)
705699a1
WV		 9071 return false;
9072
9073 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9074 kunmap(vmx->nested.pi_desc_page);
9075 nested_release_page(vmx->nested.pi_desc_page);
9076 }
9077 vmx->nested.pi_desc_page =
9078 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9079 if (!vmx->nested.pi_desc_page)
9080 return false;
9081
9082 vmx->nested.pi_desc =
9083 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9084 if (!vmx->nested.pi_desc) {
9085 nested_release_page_clean(vmx->nested.pi_desc_page);
9086 return false;
9087 }
9088 vmx->nested.pi_desc =
9089 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9090 (unsigned long)(vmcs12->posted_intr_desc_addr &
9091 (PAGE_SIZE - 1)));
9092 }
9093
a2bcba50
WL		 9094 return true;
9095}
9096
f4124500
JK		 9097static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9098{
9099 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9100 struct vcpu_vmx *vmx = to_vmx(vcpu);
9101
9102 if (vcpu->arch.virtual_tsc_khz == 0)
9103 return;
9104
9105 /* Make sure short timeouts reliably trigger an immediate vmexit.
9106 * hrtimer_start does not guarantee this. */
9107 if (preemption_timeout <= 1) {
9108 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9109 return;
9110 }
9111
9112 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9113 preemption_timeout *= 1000000;
9114 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9115 hrtimer_start(&vmx->nested.preemption_timer,
9116 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9117}
9118
3af18d9c
WV		 9119static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9120 struct vmcs12 *vmcs12)
9121{
9122 int maxphyaddr;
9123 u64 addr;
9124
9125 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9126 return 0;
9127
9128 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9129 WARN_ON(1);
9130 return -EINVAL;
9131 }
9132 maxphyaddr = cpuid_maxphyaddr(vcpu);
9133
9134 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9135 ((addr + PAGE_SIZE) >> maxphyaddr))
9136 return -EINVAL;
9137
9138 return 0;
9139}
9140
9141/*
9142 * Merge L0's and L1's MSR bitmap, return false to indicate that
9143 * we do not use the hardware.
9144 */
9145static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9146 struct vmcs12 *vmcs12)
9147{
82f0dd4b 9148 int msr;
f2b93280
WV		 9149 struct page *page;
9150 unsigned long *msr_bitmap;
9151
9152 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9153 return false;
9154
9155 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9156 if (!page) {
9157 WARN_ON(1);
9158 return false;
9159 }
9160 msr_bitmap = (unsigned long *)kmap(page);
9161 if (!msr_bitmap) {
9162 nested_release_page_clean(page);
9163 WARN_ON(1);
9164 return false;
9165 }
9166
9167 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 9168 if (nested_cpu_has_apic_reg_virt(vmcs12))
9169 for (msr = 0x800; msr <= 0x8ff; msr++)
9170 nested_vmx_disable_intercept_for_msr(
9171 msr_bitmap,
9172 vmx_msr_bitmap_nested,
9173 msr, MSR_TYPE_R);
f2b93280
WV		 9174 /* TPR is allowed */
9175 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9176 vmx_msr_bitmap_nested,
9177 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9178 MSR_TYPE_R | MSR_TYPE_W);
608406e2
WV		 9179 if (nested_cpu_has_vid(vmcs12)) {
9180 /* EOI and self-IPI are allowed */
9181 nested_vmx_disable_intercept_for_msr(
9182 msr_bitmap,
9183 vmx_msr_bitmap_nested,
9184 APIC_BASE_MSR + (APIC_EOI >> 4),
9185 MSR_TYPE_W);
9186 nested_vmx_disable_intercept_for_msr(
9187 msr_bitmap,
9188 vmx_msr_bitmap_nested,
9189 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9190 MSR_TYPE_W);
9191 }
82f0dd4b
WV		 9192 } else {
9193 /*
9194 * Enable reading intercept of all the x2apic
9195 * MSRs. We should not rely on vmcs12 to do any
9196 * optimizations here, it may have been modified
9197 * by L1.
9198 */
9199 for (msr = 0x800; msr <= 0x8ff; msr++)
9200 __vmx_enable_intercept_for_msr(
9201 vmx_msr_bitmap_nested,
9202 msr,
9203 MSR_TYPE_R);
9204
f2b93280
WV		 9205 __vmx_enable_intercept_for_msr(
9206 vmx_msr_bitmap_nested,
9207 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
82f0dd4b 9208 MSR_TYPE_W);
608406e2
WV		 9209 __vmx_enable_intercept_for_msr(
9210 vmx_msr_bitmap_nested,
9211 APIC_BASE_MSR + (APIC_EOI >> 4),
9212 MSR_TYPE_W);
9213 __vmx_enable_intercept_for_msr(
9214 vmx_msr_bitmap_nested,
9215 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9216 MSR_TYPE_W);
82f0dd4b 9217 }
f2b93280
WV		 9218 kunmap(page);
9219 nested_release_page_clean(page);
9220
9221 return true;
9222}
9223
9224static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9225 struct vmcs12 *vmcs12)
9226{
82f0dd4b 9227 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 9228 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV		 9229 !nested_cpu_has_vid(vmcs12) &&
9230 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV		 9231 return 0;
9232
9233 /*
9234 * If virtualize x2apic mode is enabled,
9235 * virtualize apic access must be disabled.
9236 */
82f0dd4b
WV		 9237 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9238 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 9239 return -EINVAL;
9240
608406e2
WV		 9241 /*
9242 * If virtual interrupt delivery is enabled,
9243 * we must exit on external interrupts.
9244 */
9245 if (nested_cpu_has_vid(vmcs12) &&
9246 !nested_exit_on_intr(vcpu))
9247 return -EINVAL;
9248
705699a1
WV		 9249 /*
9250 * bits 15:8 should be zero in posted_intr_nv,
9251 * the descriptor address has been already checked
9252 * in nested_get_vmcs12_pages.
9253 */
9254 if (nested_cpu_has_posted_intr(vmcs12) &&
9255 (!nested_cpu_has_vid(vmcs12) ||
9256 !nested_exit_intr_ack_set(vcpu) ||
9257 vmcs12->posted_intr_nv & 0xff00))
9258 return -EINVAL;
9259
f2b93280
WV		 9260 /* tpr shadow is needed by all apicv features. */
9261 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9262 return -EINVAL;
9263
9264 return 0;
3af18d9c
WV		 9265}
9266
e9ac033e
EK		 9267static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9268 unsigned long count_field,
92d71bc6 9269 unsigned long addr_field)
ff651cb6 9270{
92d71bc6 9271 int maxphyaddr;
e9ac033e
EK		 9272 u64 count, addr;
9273
9274 if (vmcs12_read_any(vcpu, count_field, &count) ||
9275 vmcs12_read_any(vcpu, addr_field, &addr)) {
9276 WARN_ON(1);
9277 return -EINVAL;
9278 }
9279 if (count == 0)
9280 return 0;
92d71bc6 9281 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK		 9282 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9283 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9284 pr_warn_ratelimited(
9285 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9286 addr_field, maxphyaddr, count, addr);
9287 return -EINVAL;
9288 }
9289 return 0;
9290}
9291
9292static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9293 struct vmcs12 *vmcs12)
9294{
e9ac033e
EK		 9295 if (vmcs12->vm_exit_msr_load_count == 0 &&
9296 vmcs12->vm_exit_msr_store_count == 0 &&
9297 vmcs12->vm_entry_msr_load_count == 0)
9298 return 0; /* Fast path */
e9ac033e 9299 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9300 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9301 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9302 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9303 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9304 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK		 9305 return -EINVAL;
9306 return 0;
9307}
9308
9309static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9310 struct vmx_msr_entry *e)
9311{
9312 /* x2APIC MSR accesses are not allowed */
8a9781f7 9313 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK		 9314 return -EINVAL;
9315 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9316 e->index == MSR_IA32_UCODE_REV)
9317 return -EINVAL;
9318 if (e->reserved != 0)
ff651cb6
WV		 9319 return -EINVAL;
9320 return 0;
9321}
9322
e9ac033e
EK		 9323static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9324 struct vmx_msr_entry *e)
ff651cb6
WV		 9325{
9326 if (e->index == MSR_FS_BASE ||
9327 e->index == MSR_GS_BASE ||
e9ac033e
EK		 9328 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9329 nested_vmx_msr_check_common(vcpu, e))
9330 return -EINVAL;
9331 return 0;
9332}
9333
9334static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9335 struct vmx_msr_entry *e)
9336{
9337 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9338 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 9339 return -EINVAL;
9340 return 0;
9341}
9342
9343/*
9344 * Load guest's/host's msr at nested entry/exit.
9345 * return 0 for success, entry index for failure.
9346 */
9347static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9348{
9349 u32 i;
9350 struct vmx_msr_entry e;
9351 struct msr_data msr;
9352
9353 msr.host_initiated = false;
9354 for (i = 0; i < count; i++) {
54bf36aa
PB		 9355 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9356 &e, sizeof(e))) {
e9ac033e
EK		 9357 pr_warn_ratelimited(
9358 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9359 __func__, i, gpa + i * sizeof(e));
ff651cb6 9360 goto fail;
e9ac033e
EK		 9361 }
9362 if (nested_vmx_load_msr_check(vcpu, &e)) {
9363 pr_warn_ratelimited(
9364 "%s check failed (%u, 0x%x, 0x%x)\n",
9365 __func__, i, e.index, e.reserved);
9366 goto fail;
9367 }
ff651cb6
WV		 9368 msr.index = e.index;
9369 msr.data = e.value;
e9ac033e
EK		 9370 if (kvm_set_msr(vcpu, &msr)) {
9371 pr_warn_ratelimited(
9372 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9373 __func__, i, e.index, e.value);
ff651cb6 9374 goto fail;
e9ac033e 9375 }
ff651cb6
WV		 9376 }
9377 return 0;
9378fail:
9379 return i + 1;
9380}
9381
9382static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9383{
9384 u32 i;
9385 struct vmx_msr_entry e;
9386
9387 for (i = 0; i < count; i++) {
609e36d3 9388 struct msr_data msr_info;
54bf36aa
PB		 9389 if (kvm_vcpu_read_guest(vcpu,
9390 gpa + i * sizeof(e),
9391 &e, 2 * sizeof(u32))) {
e9ac033e
EK		 9392 pr_warn_ratelimited(
9393 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9394 __func__, i, gpa + i * sizeof(e));
ff651cb6 9395 return -EINVAL;
e9ac033e
EK		 9396 }
9397 if (nested_vmx_store_msr_check(vcpu, &e)) {
9398 pr_warn_ratelimited(
9399 "%s check failed (%u, 0x%x, 0x%x)\n",
9400 __func__, i, e.index, e.reserved);
ff651cb6 9401 return -EINVAL;
e9ac033e 9402 }
609e36d3
PB		 9403 msr_info.host_initiated = false;
9404 msr_info.index = e.index;
9405 if (kvm_get_msr(vcpu, &msr_info)) {
e9ac033e
EK		 9406 pr_warn_ratelimited(
9407 "%s cannot read MSR (%u, 0x%x)\n",
9408 __func__, i, e.index);
9409 return -EINVAL;
9410 }
54bf36aa
PB		 9411 if (kvm_vcpu_write_guest(vcpu,
9412 gpa + i * sizeof(e) +
9413 offsetof(struct vmx_msr_entry, value),
9414 &msr_info.data, sizeof(msr_info.data))) {
e9ac033e
EK		 9415 pr_warn_ratelimited(
9416 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9417 __func__, i, e.index, msr_info.data);
e9ac033e
EK		 9418 return -EINVAL;
9419 }
ff651cb6
WV		 9420 }
9421 return 0;
9422}
9423
fe3ef05c
NHE		 9424/*
9425 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9426 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9427 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 9428 * guest in a way that will both be appropriate to L1's requests, and our
9429 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9430 * function also has additional necessary side-effects, like setting various
9431 * vcpu->arch fields.
9432 */
9433static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9434{
9435 struct vcpu_vmx *vmx = to_vmx(vcpu);
9436 u32 exec_control;
9437
9438 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9439 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9440 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9441 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9442 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9443 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9444 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9445 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9446 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9447 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9448 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9449 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9450 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9451 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9452 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9453 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9454 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9455 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9456 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9457 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9458 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9459 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9460 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9461 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9462 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9463 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9464 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9465 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9466 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9467 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9468 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9469 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9470 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9471 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9472 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9473 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9474
2996fca0
JK		 9475 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9476 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9477 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9478 } else {
9479 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9480 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9481 }
fe3ef05c
NHE		 9482 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9483 vmcs12->vm_entry_intr_info_field);
9484 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9485 vmcs12->vm_entry_exception_error_code);
9486 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9487 vmcs12->vm_entry_instruction_len);
9488 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9489 vmcs12->guest_interruptibility_info);
fe3ef05c 9490 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9491 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 9492 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9493 vmcs12->guest_pending_dbg_exceptions);
9494 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9495 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9496
81dc01f7
WL		 9497 if (nested_cpu_has_xsaves(vmcs12))
9498 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 9499 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9500
f4124500
JK		 9501 exec_control = vmcs12->pin_based_vm_exec_control;
9502 exec_control |= vmcs_config.pin_based_exec_ctrl;
705699a1
WV		 9503 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9504
9505 if (nested_cpu_has_posted_intr(vmcs12)) {
9506 /*
9507 * Note that we use L0's vector here and in
9508 * vmx_deliver_nested_posted_interrupt.
9509 */
9510 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9511 vmx->nested.pi_pending = false;
9512 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9513 vmcs_write64(POSTED_INTR_DESC_ADDR,
9514 page_to_phys(vmx->nested.pi_desc_page) +
9515 (unsigned long)(vmcs12->posted_intr_desc_addr &
9516 (PAGE_SIZE - 1)));
9517 } else
9518 exec_control &= ~PIN_BASED_POSTED_INTR;
9519
f4124500 9520 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 9521
f4124500
JK		 9522 vmx->nested.preemption_timer_expired = false;
9523 if (nested_cpu_has_preemption_timer(vmcs12))
9524 vmx_start_preemption_timer(vcpu);
0238ea91 9525
fe3ef05c
NHE		 9526 /*
9527 * Whether page-faults are trapped is determined by a combination of
9528 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9529 * If enable_ept, L0 doesn't care about page faults and we should
9530 * set all of these to L1's desires. However, if !enable_ept, L0 does
9531 * care about (at least some) page faults, and because it is not easy
9532 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9533 * to exit on each and every L2 page fault. This is done by setting
9534 * MASK=MATCH=0 and (see below) EB.PF=1.
9535 * Note that below we don't need special code to set EB.PF beyond the
9536 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9537 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9538 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9539 *
9540 * A problem with this approach (when !enable_ept) is that L1 may be
9541 * injected with more page faults than it asked for. This could have
9542 * caused problems, but in practice existing hypervisors don't care.
9543 * To fix this, we will need to emulate the PFEC checking (on the L1
9544 * page tables), using walk_addr(), when injecting PFs to L1.
9545 */
9546 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9547 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9548 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9549 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9550
9551 if (cpu_has_secondary_exec_ctrls()) {
f4124500 9552 exec_control = vmx_secondary_exec_control(vmx);
e2821620 9553
fe3ef05c 9554 /* Take the following fields only from vmcs12 */
696dfd95 9555 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 9556 SECONDARY_EXEC_RDTSCP |
696dfd95 9557 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8b3e34e4
XG		 9558 SECONDARY_EXEC_APIC_REGISTER_VIRT |
9559 SECONDARY_EXEC_PCOMMIT);
fe3ef05c
NHE		 9560 if (nested_cpu_has(vmcs12,
9561 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9562 exec_control |= vmcs12->secondary_vm_exec_control;
9563
9564 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 9565 /*
9566 * If translation failed, no matter: This feature asks
9567 * to exit when accessing the given address, and if it
9568 * can never be accessed, this feature won't do
9569 * anything anyway.
9570 */
9571 if (!vmx->nested.apic_access_page)
9572 exec_control &=
9573 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9574 else
9575 vmcs_write64(APIC_ACCESS_ADDR,
9576 page_to_phys(vmx->nested.apic_access_page));
f2b93280 9577 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
35754c98 9578 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
ca3f257a
JK		 9579 exec_control |=
9580 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 9581 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 9582 }
9583
608406e2
WV		 9584 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9585 vmcs_write64(EOI_EXIT_BITMAP0,
9586 vmcs12->eoi_exit_bitmap0);
9587 vmcs_write64(EOI_EXIT_BITMAP1,
9588 vmcs12->eoi_exit_bitmap1);
9589 vmcs_write64(EOI_EXIT_BITMAP2,
9590 vmcs12->eoi_exit_bitmap2);
9591 vmcs_write64(EOI_EXIT_BITMAP3,
9592 vmcs12->eoi_exit_bitmap3);
9593 vmcs_write16(GUEST_INTR_STATUS,
9594 vmcs12->guest_intr_status);
9595 }
9596
fe3ef05c
NHE		 9597 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9598 }
9599
9600
9601 /*
9602 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9603 * Some constant fields are set here by vmx_set_constant_host_state().
9604 * Other fields are different per CPU, and will be set later when
9605 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9606 */
a547c6db 9607 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 9608
9609 /*
9610 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9611 * entry, but only if the current (host) sp changed from the value
9612 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9613 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9614 * here we just force the write to happen on entry.
9615 */
9616 vmx->host_rsp = 0;
9617
9618 exec_control = vmx_exec_control(vmx); /* L0's desires */
9619 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9620 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9621 exec_control &= ~CPU_BASED_TPR_SHADOW;
9622 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 9623
9624 if (exec_control & CPU_BASED_TPR_SHADOW) {
9625 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9626 page_to_phys(vmx->nested.virtual_apic_page));
9627 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9628 }
9629
3af18d9c 9630 if (cpu_has_vmx_msr_bitmap() &&
670125bd
WV		 9631 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9632 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9633 /* MSR_BITMAP will be set by following vmx_set_efer. */
3af18d9c
WV		 9634 } else
9635 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9636
fe3ef05c 9637 /*
3af18d9c 9638 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 9639 * Rather, exit every time.
9640 */
fe3ef05c
NHE		 9641 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9642 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9643
9644 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9645
9646 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9647 * bitwise-or of what L1 wants to trap for L2, and what we want to
9648 * trap. Note that CR0.TS also needs updating - we do this later.
9649 */
9650 update_exception_bitmap(vcpu);
9651 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9652 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9653
8049d651
NHE		 9654 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9655 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9656 * bits are further modified by vmx_set_efer() below.
9657 */
f4124500 9658 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9659
9660 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9661 * emulated by vmx_set_efer(), below.
9662 */
2961e876 9663 vm_entry_controls_init(vmx,
8049d651
NHE		 9664 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9665 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9666 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9667
44811c02 9668 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9669 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9670 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9671 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9672 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9673
9674
9675 set_cr4_guest_host_mask(vmx);
9676
36be0b9d
PB		 9677 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9678 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9679
27fc51b2
NHE		 9680 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9681 vmcs_write64(TSC_OFFSET,
9682 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9683 else
9684 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9685
9686 if (enable_vpid) {
9687 /*
5c614b35
WL		 9688 * There is no direct mapping between vpid02 and vpid12, the
9689 * vpid02 is per-vCPU for L0 and reused while the value of
9690 * vpid12 is changed w/ one invvpid during nested vmentry.
9691 * The vpid12 is allocated by L1 for L2, so it will not
9692 * influence global bitmap(for vpid01 and vpid02 allocation)
9693 * even if spawn a lot of nested vCPUs.
fe3ef05c 9694 */
5c614b35
WL		 9695 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9696 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9697 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9698 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9699 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9700 }
9701 } else {
9702 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9703 vmx_flush_tlb(vcpu);
9704 }
9705
fe3ef05c
NHE		 9706 }
9707
155a97a3
NHE		 9708 if (nested_cpu_has_ept(vmcs12)) {
9709 kvm_mmu_unload(vcpu);
9710 nested_ept_init_mmu_context(vcpu);
9711 }
9712
fe3ef05c
NHE		 9713 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9714 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9715 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9716 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9717 else
9718 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9719 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9720 vmx_set_efer(vcpu, vcpu->arch.efer);
9721
9722 /*
9723 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9724 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9725 * The CR0_READ_SHADOW is what L2 should have expected to read given
9726 * the specifications by L1; It's not enough to take
9727 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9728 * have more bits than L1 expected.
9729 */
9730 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9731 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9732
9733 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9734 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9735
9736 /* shadow page tables on either EPT or shadow page tables */
9737 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9738 kvm_mmu_reset_context(vcpu);
9739
feaf0c7d
GN		 9740 if (!enable_ept)
9741 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9742
3633cfc3
NHE		 9743 /*
9744 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9745 */
9746 if (enable_ept) {
9747 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9748 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9749 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9750 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9751 }
9752
fe3ef05c
NHE		 9753 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9754 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9755}
9756
cd232ad0
NHE		 9757/*
9758 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9759 * for running an L2 nested guest.
9760 */
9761static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9762{
9763 struct vmcs12 *vmcs12;
9764 struct vcpu_vmx *vmx = to_vmx(vcpu);
9765 int cpu;
9766 struct loaded_vmcs *vmcs02;
384bb783 9767 bool ia32e;
ff651cb6 9768 u32 msr_entry_idx;
cd232ad0
NHE		 9769
9770 if (!nested_vmx_check_permission(vcpu) ||
9771 !nested_vmx_check_vmcs12(vcpu))
9772 return 1;
9773
9774 skip_emulated_instruction(vcpu);
9775 vmcs12 = get_vmcs12(vcpu);
9776
012f83cb
AG		 9777 if (enable_shadow_vmcs)
9778 copy_shadow_to_vmcs12(vmx);
9779
7c177938
NHE		 9780 /*
9781 * The nested entry process starts with enforcing various prerequisites
9782 * on vmcs12 as required by the Intel SDM, and act appropriately when
9783 * they fail: As the SDM explains, some conditions should cause the
9784 * instruction to fail, while others will cause the instruction to seem
9785 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9786 * To speed up the normal (success) code path, we should avoid checking
9787 * for misconfigurations which will anyway be caught by the processor
9788 * when using the merged vmcs02.
9789 */
9790 if (vmcs12->launch_state == launch) {
9791 nested_vmx_failValid(vcpu,
9792 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9793 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9794 return 1;
9795 }
9796
6dfacadd
JK		 9797 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9798 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9799 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9800 return 1;
9801 }
9802
3af18d9c 9803 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9804 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9805 return 1;
9806 }
9807
3af18d9c 9808 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9809 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9810 return 1;
9811 }
9812
f2b93280
WV		 9813 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9814 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9815 return 1;
9816 }
9817
e9ac033e
EK		 9818 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9819 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9820 return 1;
9821 }
9822
7c177938 9823 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9824 vmx->nested.nested_vmx_true_procbased_ctls_low,
9825 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9826 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9827 vmx->nested.nested_vmx_secondary_ctls_low,
9828 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9829 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9830 vmx->nested.nested_vmx_pinbased_ctls_low,
9831 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9832 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9833 vmx->nested.nested_vmx_true_exit_ctls_low,
9834 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9835 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9836 vmx->nested.nested_vmx_true_entry_ctls_low,
9837 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9838 {
9839 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9840 return 1;
9841 }
9842
9843 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9844 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9845 nested_vmx_failValid(vcpu,
9846 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9847 return 1;
9848 }
9849
b9c237bb 9850 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9851 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9852 nested_vmx_entry_failure(vcpu, vmcs12,
9853 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9854 return 1;
9855 }
9856 if (vmcs12->vmcs_link_pointer != -1ull) {
9857 nested_vmx_entry_failure(vcpu, vmcs12,
9858 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9859 return 1;
9860 }
9861
384bb783 9862 /*
cb0c8cda 9863 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9864 * are performed on the field for the IA32_EFER MSR:
9865 * - Bits reserved in the IA32_EFER MSR must be 0.
9866 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9867 * the IA-32e mode guest VM-exit control. It must also be identical
9868 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9869 * CR0.PG) is 1.
9870 */
9871 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9872 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9873 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9874 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9875 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9876 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9877 nested_vmx_entry_failure(vcpu, vmcs12,
9878 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9879 return 1;
9880 }
9881 }
9882
9883 /*
9884 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9885 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9886 * the values of the LMA and LME bits in the field must each be that of
9887 * the host address-space size VM-exit control.
9888 */
9889 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9890 ia32e = (vmcs12->vm_exit_controls &
9891 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9892 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9893 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9894 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9895 nested_vmx_entry_failure(vcpu, vmcs12,
9896 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9897 return 1;
9898 }
9899 }
9900
7c177938
NHE		 9901 /*
9902 * We're finally done with prerequisite checking, and can start with
9903 * the nested entry.
9904 */
9905
cd232ad0
NHE		 9906 vmcs02 = nested_get_current_vmcs02(vmx);
9907 if (!vmcs02)
9908 return -ENOMEM;
9909
9910 enter_guest_mode(vcpu);
9911
9912 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9913
2996fca0
JK		 9914 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9915 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9916
cd232ad0
NHE		 9917 cpu = get_cpu();
9918 vmx->loaded_vmcs = vmcs02;
9919 vmx_vcpu_put(vcpu);
9920 vmx_vcpu_load(vcpu, cpu);
9921 vcpu->cpu = cpu;
9922 put_cpu();
9923
36c3cc42
JK		 9924 vmx_segment_cache_clear(vmx);
9925
cd232ad0
NHE		 9926 prepare_vmcs02(vcpu, vmcs12);
9927
ff651cb6
WV		 9928 msr_entry_idx = nested_vmx_load_msr(vcpu,
9929 vmcs12->vm_entry_msr_load_addr,
9930 vmcs12->vm_entry_msr_load_count);
9931 if (msr_entry_idx) {
9932 leave_guest_mode(vcpu);
9933 vmx_load_vmcs01(vcpu);
9934 nested_vmx_entry_failure(vcpu, vmcs12,
9935 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9936 return 1;
9937 }
9938
9939 vmcs12->launch_state = 1;
9940
6dfacadd 9941 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 9942 return kvm_vcpu_halt(vcpu);
6dfacadd 9943
7af40ad3
JK		 9944 vmx->nested.nested_run_pending = 1;
9945
cd232ad0
NHE		 9946 /*
9947 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9948 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9949 * returned as far as L1 is concerned. It will only return (and set
9950 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9951 */
9952 return 1;
9953}
9954
4704d0be
NHE		 9955/*
9956 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9957 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9958 * This function returns the new value we should put in vmcs12.guest_cr0.
9959 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9960 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9961 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9962 * didn't trap the bit, because if L1 did, so would L0).
9963 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9964 * been modified by L2, and L1 knows it. So just leave the old value of
9965 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9966 * isn't relevant, because if L0 traps this bit it can set it to anything.
9967 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9968 * changed these bits, and therefore they need to be updated, but L0
9969 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9970 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9971 */
9972static inline unsigned long
9973vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9974{
9975 return
9976 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9977 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9978 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9979 vcpu->arch.cr0_guest_owned_bits));
9980}
9981
9982static inline unsigned long
9983vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9984{
9985 return
9986 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9987 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9988 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9989 vcpu->arch.cr4_guest_owned_bits));
9990}
9991
5f3d5799
JK		 9992static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9993 struct vmcs12 *vmcs12)
9994{
9995 u32 idt_vectoring;
9996 unsigned int nr;
9997
851eb667 9998 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9999 nr = vcpu->arch.exception.nr;
10000 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10001
10002 if (kvm_exception_is_soft(nr)) {
10003 vmcs12->vm_exit_instruction_len =
10004 vcpu->arch.event_exit_inst_len;
10005 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10006 } else
10007 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10008
10009 if (vcpu->arch.exception.has_error_code) {
10010 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10011 vmcs12->idt_vectoring_error_code =
10012 vcpu->arch.exception.error_code;
10013 }
10014
10015 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 10016 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 10017 vmcs12->idt_vectoring_info_field =
10018 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10019 } else if (vcpu->arch.interrupt.pending) {
10020 nr = vcpu->arch.interrupt.nr;
10021 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10022
10023 if (vcpu->arch.interrupt.soft) {
10024 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10025 vmcs12->vm_entry_instruction_len =
10026 vcpu->arch.event_exit_inst_len;
10027 } else
10028 idt_vectoring |= INTR_TYPE_EXT_INTR;
10029
10030 vmcs12->idt_vectoring_info_field = idt_vectoring;
10031 }
10032}
10033
b6b8a145
JK		 10034static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10035{
10036 struct vcpu_vmx *vmx = to_vmx(vcpu);
10037
f4124500
JK		 10038 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10039 vmx->nested.preemption_timer_expired) {
10040 if (vmx->nested.nested_run_pending)
10041 return -EBUSY;
10042 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10043 return 0;
10044 }
10045
b6b8a145 10046 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 10047 if (vmx->nested.nested_run_pending ||
10048 vcpu->arch.interrupt.pending)
b6b8a145
JK		 10049 return -EBUSY;
10050 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10051 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10052 INTR_INFO_VALID_MASK, 0);
10053 /*
10054 * The NMI-triggered VM exit counts as injection:
10055 * clear this one and block further NMIs.
10056 */
10057 vcpu->arch.nmi_pending = 0;
10058 vmx_set_nmi_mask(vcpu, true);
10059 return 0;
10060 }
10061
10062 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10063 nested_exit_on_intr(vcpu)) {
10064 if (vmx->nested.nested_run_pending)
10065 return -EBUSY;
10066 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 10067 return 0;
b6b8a145
JK		 10068 }
10069
705699a1 10070 return vmx_complete_nested_posted_interrupt(vcpu);
b6b8a145
JK		 10071}
10072
f4124500
JK		 10073static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10074{
10075 ktime_t remaining =
10076 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10077 u64 value;
10078
10079 if (ktime_to_ns(remaining) <= 0)
10080 return 0;
10081
10082 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10083 do_div(value, 1000000);
10084 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10085}
10086
4704d0be
NHE		 10087/*
10088 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10089 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10090 * and this function updates it to reflect the changes to the guest state while
10091 * L2 was running (and perhaps made some exits which were handled directly by L0
10092 * without going back to L1), and to reflect the exit reason.
10093 * Note that we do not have to copy here all VMCS fields, just those that
10094 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10095 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10096 * which already writes to vmcs12 directly.
10097 */
533558bc
JK		 10098static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10099 u32 exit_reason, u32 exit_intr_info,
10100 unsigned long exit_qualification)
4704d0be
NHE		 10101{
10102 /* update guest state fields: */
10103 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10104 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10105
4704d0be
NHE		 10106 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10107 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10108 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10109
10110 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10111 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10112 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10113 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10114 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10115 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10116 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10117 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10118 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10119 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10120 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10121 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10122 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10123 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10124 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10125 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10126 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10127 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10128 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10129 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10130 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10131 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10132 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10133 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10134 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10135 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10136 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10137 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10138 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10139 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10140 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10141 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10142 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10143 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10144 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10145 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10146
4704d0be
NHE		 10147 vmcs12->guest_interruptibility_info =
10148 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10149 vmcs12->guest_pending_dbg_exceptions =
10150 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 10151 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10152 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10153 else
10154 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 10155
f4124500
JK		 10156 if (nested_cpu_has_preemption_timer(vmcs12)) {
10157 if (vmcs12->vm_exit_controls &
10158 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10159 vmcs12->vmx_preemption_timer_value =
10160 vmx_get_preemption_timer_value(vcpu);
10161 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10162 }
7854cbca 10163
3633cfc3
NHE		 10164 /*
10165 * In some cases (usually, nested EPT), L2 is allowed to change its
10166 * own CR3 without exiting. If it has changed it, we must keep it.
10167 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10168 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10169 *
10170 * Additionally, restore L2's PDPTR to vmcs12.
10171 */
10172 if (enable_ept) {
10173 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10174 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10175 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10176 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10177 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10178 }
10179
608406e2
WV		 10180 if (nested_cpu_has_vid(vmcs12))
10181 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10182
c18911a2
JK		 10183 vmcs12->vm_entry_controls =
10184 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 10185 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 10186
2996fca0
JK		 10187 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10188 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10189 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10190 }
10191
4704d0be
NHE		 10192 /* TODO: These cannot have changed unless we have MSR bitmaps and
10193 * the relevant bit asks not to trap the change */
b8c07d55 10194 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 10195 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 10196 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10197 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 10198 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10199 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10200 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 10201 if (vmx_mpx_supported())
10202 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 10203 if (nested_cpu_has_xsaves(vmcs12))
10204 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 10205
10206 /* update exit information fields: */
10207
533558bc
JK		 10208 vmcs12->vm_exit_reason = exit_reason;
10209 vmcs12->exit_qualification = exit_qualification;
4704d0be 10210
533558bc 10211 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 10212 if ((vmcs12->vm_exit_intr_info &
10213 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10214 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10215 vmcs12->vm_exit_intr_error_code =
10216 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 10217 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 10218 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10219 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10220
5f3d5799
JK		 10221 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10222 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10223 * instead of reading the real value. */
4704d0be 10224 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 10225
10226 /*
10227 * Transfer the event that L0 or L1 may wanted to inject into
10228 * L2 to IDT_VECTORING_INFO_FIELD.
10229 */
10230 vmcs12_save_pending_event(vcpu, vmcs12);
10231 }
10232
10233 /*
10234 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10235 * preserved above and would only end up incorrectly in L1.
10236 */
10237 vcpu->arch.nmi_injected = false;
10238 kvm_clear_exception_queue(vcpu);
10239 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 10240}
10241
10242/*
10243 * A part of what we need to when the nested L2 guest exits and we want to
10244 * run its L1 parent, is to reset L1's guest state to the host state specified
10245 * in vmcs12.
10246 * This function is to be called not only on normal nested exit, but also on
10247 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10248 * Failures During or After Loading Guest State").
10249 * This function should be called when the active VMCS is L1's (vmcs01).
10250 */
733568f9
JK		 10251static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10252 struct vmcs12 *vmcs12)
4704d0be 10253{
21feb4eb
ACL		 10254 struct kvm_segment seg;
10255
4704d0be
NHE		 10256 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10257 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10258 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 10259 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10260 else
10261 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10262 vmx_set_efer(vcpu, vcpu->arch.efer);
10263
10264 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10265 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10266 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 10267 /*
10268 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10269 * actually changed, because it depends on the current state of
10270 * fpu_active (which may have changed).
10271 * Note that vmx_set_cr0 refers to efer set above.
10272 */
9e3e4dbf 10273 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 10274 /*
10275 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10276 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10277 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10278 */
10279 update_exception_bitmap(vcpu);
10280 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10281 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10282
10283 /*
10284 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10285 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10286 */
10287 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10288 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10289
29bf08f1 10290 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10291
4704d0be
NHE		 10292 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10293 kvm_mmu_reset_context(vcpu);
10294
feaf0c7d
GN		 10295 if (!enable_ept)
10296 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10297
4704d0be
NHE		 10298 if (enable_vpid) {
10299 /*
10300 * Trivially support vpid by letting L2s share their parent
10301 * L1's vpid. TODO: move to a more elaborate solution, giving
10302 * each L2 its own vpid and exposing the vpid feature to L1.
10303 */
10304 vmx_flush_tlb(vcpu);
10305 }
10306
10307
10308 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10309 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10310 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10311 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10312 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10313
36be0b9d
PB		 10314 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10315 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10316 vmcs_write64(GUEST_BNDCFGS, 0);
10317
44811c02 10318 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10319 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 10320 vcpu->arch.pat = vmcs12->host_ia32_pat;
10321 }
4704d0be
NHE		 10322 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10323 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10324 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10325
21feb4eb
ACL		 10326 /* Set L1 segment info according to Intel SDM
10327 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10328 seg = (struct kvm_segment) {
10329 .base = 0,
10330 .limit = 0xFFFFFFFF,
10331 .selector = vmcs12->host_cs_selector,
10332 .type = 11,
10333 .present = 1,
10334 .s = 1,
10335 .g = 1
10336 };
10337 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10338 seg.l = 1;
10339 else
10340 seg.db = 1;
10341 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10342 seg = (struct kvm_segment) {
10343 .base = 0,
10344 .limit = 0xFFFFFFFF,
10345 .type = 3,
10346 .present = 1,
10347 .s = 1,
10348 .db = 1,
10349 .g = 1
10350 };
10351 seg.selector = vmcs12->host_ds_selector;
10352 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10353 seg.selector = vmcs12->host_es_selector;
10354 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10355 seg.selector = vmcs12->host_ss_selector;
10356 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10357 seg.selector = vmcs12->host_fs_selector;
10358 seg.base = vmcs12->host_fs_base;
10359 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10360 seg.selector = vmcs12->host_gs_selector;
10361 seg.base = vmcs12->host_gs_base;
10362 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10363 seg = (struct kvm_segment) {
205befd9 10364 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 10365 .limit = 0x67,
10366 .selector = vmcs12->host_tr_selector,
10367 .type = 11,
10368 .present = 1
10369 };
10370 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10371
503cd0c5
JK		 10372 kvm_set_dr(vcpu, 7, 0x400);
10373 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 10374
3af18d9c
WV		 10375 if (cpu_has_vmx_msr_bitmap())
10376 vmx_set_msr_bitmap(vcpu);
10377
ff651cb6
WV		 10378 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10379 vmcs12->vm_exit_msr_load_count))
10380 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 10381}
10382
10383/*
10384 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10385 * and modify vmcs12 to make it see what it would expect to see there if
10386 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10387 */
533558bc
JK		 10388static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10389 u32 exit_intr_info,
10390 unsigned long exit_qualification)
4704d0be
NHE		 10391{
10392 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 10393 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10394
5f3d5799
JK		 10395 /* trying to cancel vmlaunch/vmresume is a bug */
10396 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10397
4704d0be 10398 leave_guest_mode(vcpu);
533558bc
JK		 10399 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10400 exit_qualification);
4704d0be 10401
ff651cb6
WV		 10402 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10403 vmcs12->vm_exit_msr_store_count))
10404 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10405
f3380ca5
WL		 10406 vmx_load_vmcs01(vcpu);
10407
77b0f5d6
BD		 10408 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10409 && nested_exit_intr_ack_set(vcpu)) {
10410 int irq = kvm_cpu_get_interrupt(vcpu);
10411 WARN_ON(irq < 0);
10412 vmcs12->vm_exit_intr_info = irq |
10413 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10414 }
10415
542060ea
JK		 10416 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10417 vmcs12->exit_qualification,
10418 vmcs12->idt_vectoring_info_field,
10419 vmcs12->vm_exit_intr_info,
10420 vmcs12->vm_exit_intr_error_code,
10421 KVM_ISA_VMX);
4704d0be 10422
2961e876
GN		 10423 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10424 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 10425 vmx_segment_cache_clear(vmx);
10426
4704d0be
NHE		 10427 /* if no vmcs02 cache requested, remove the one we used */
10428 if (VMCS02_POOL_SIZE == 0)
10429 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10430
10431 load_vmcs12_host_state(vcpu, vmcs12);
10432
27fc51b2 10433 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 10434 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10435
10436 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10437 vmx->host_rsp = 0;
10438
10439 /* Unpin physical memory we referred to in vmcs02 */
10440 if (vmx->nested.apic_access_page) {
10441 nested_release_page(vmx->nested.apic_access_page);
48d89b92 10442 vmx->nested.apic_access_page = NULL;
4704d0be 10443 }
a7c0b07d
WL		 10444 if (vmx->nested.virtual_apic_page) {
10445 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 10446 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 10447 }
705699a1
WV		 10448 if (vmx->nested.pi_desc_page) {
10449 kunmap(vmx->nested.pi_desc_page);
10450 nested_release_page(vmx->nested.pi_desc_page);
10451 vmx->nested.pi_desc_page = NULL;
10452 vmx->nested.pi_desc = NULL;
10453 }
4704d0be 10454
38b99173
TC		 10455 /*
10456 * We are now running in L2, mmu_notifier will force to reload the
10457 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10458 */
10459 kvm_vcpu_reload_apic_access_page(vcpu);
10460
4704d0be
NHE		 10461 /*
10462 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10463 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10464 * success or failure flag accordingly.
10465 */
10466 if (unlikely(vmx->fail)) {
10467 vmx->fail = 0;
10468 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10469 } else
10470 nested_vmx_succeed(vcpu);
012f83cb
AG		 10471 if (enable_shadow_vmcs)
10472 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 10473
10474 /* in case we halted in L2 */
10475 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 10476}
10477
42124925
JK		 10478/*
10479 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10480 */
10481static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10482{
10483 if (is_guest_mode(vcpu))
533558bc 10484 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 10485 free_nested(to_vmx(vcpu));
10486}
10487
7c177938
NHE		 10488/*
10489 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10490 * 23.7 "VM-entry failures during or after loading guest state" (this also
10491 * lists the acceptable exit-reason and exit-qualification parameters).
10492 * It should only be called before L2 actually succeeded to run, and when
10493 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10494 */
10495static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10496 struct vmcs12 *vmcs12,
10497 u32 reason, unsigned long qualification)
10498{
10499 load_vmcs12_host_state(vcpu, vmcs12);
10500 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10501 vmcs12->exit_qualification = qualification;
10502 nested_vmx_succeed(vcpu);
012f83cb
AG		 10503 if (enable_shadow_vmcs)
10504 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 10505}
10506
8a76d7f2
JR		 10507static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10508 struct x86_instruction_info *info,
10509 enum x86_intercept_stage stage)
10510{
10511 return X86EMUL_CONTINUE;
10512}
10513
48d89b92 10514static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 10515{
b4a2d31d
RK		 10516 if (ple_gap)
10517 shrink_ple_window(vcpu);
ae97a3b8
RK		 10518}
10519
843e4330
KH		 10520static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10521 struct kvm_memory_slot *slot)
10522{
10523 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10524 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10525}
10526
10527static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10528 struct kvm_memory_slot *slot)
10529{
10530 kvm_mmu_slot_set_dirty(kvm, slot);
10531}
10532
10533static void vmx_flush_log_dirty(struct kvm *kvm)
10534{
10535 kvm_flush_pml_buffers(kvm);
10536}
10537
10538static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10539 struct kvm_memory_slot *memslot,
10540 gfn_t offset, unsigned long mask)
10541{
10542 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10543}
10544
bf9f6ac8
FW		 10545/*
10546 * This routine does the following things for vCPU which is going
10547 * to be blocked if VT-d PI is enabled.
10548 * - Store the vCPU to the wakeup list, so when interrupts happen
10549 * we can find the right vCPU to wake up.
10550 * - Change the Posted-interrupt descriptor as below:
10551 * 'NDST' <-- vcpu->pre_pcpu
10552 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10553 * - If 'ON' is set during this process, which means at least one
10554 * interrupt is posted for this vCPU, we cannot block it, in
10555 * this case, return 1, otherwise, return 0.
10556 *
10557 */
10558static int vmx_pre_block(struct kvm_vcpu *vcpu)
10559{
10560 unsigned long flags;
10561 unsigned int dest;
10562 struct pi_desc old, new;
10563 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10564
10565 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10566 !irq_remapping_cap(IRQ_POSTING_CAP))
10567 return 0;
10568
10569 vcpu->pre_pcpu = vcpu->cpu;
10570 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10571 vcpu->pre_pcpu), flags);
10572 list_add_tail(&vcpu->blocked_vcpu_list,
10573 &per_cpu(blocked_vcpu_on_cpu,
10574 vcpu->pre_pcpu));
10575 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10576 vcpu->pre_pcpu), flags);
10577
10578 do {
10579 old.control = new.control = pi_desc->control;
10580
10581 /*
10582 * We should not block the vCPU if
10583 * an interrupt is posted for it.
10584 */
10585 if (pi_test_on(pi_desc) == 1) {
10586 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10587 vcpu->pre_pcpu), flags);
10588 list_del(&vcpu->blocked_vcpu_list);
10589 spin_unlock_irqrestore(
10590 &per_cpu(blocked_vcpu_on_cpu_lock,
10591 vcpu->pre_pcpu), flags);
10592 vcpu->pre_pcpu = -1;
10593
10594 return 1;
10595 }
10596
10597 WARN((pi_desc->sn == 1),
10598 "Warning: SN field of posted-interrupts "
10599 "is set before blocking\n");
10600
10601 /*
10602 * Since vCPU can be preempted during this process,
10603 * vcpu->cpu could be different with pre_pcpu, we
10604 * need to set pre_pcpu as the destination of wakeup
10605 * notification event, then we can find the right vCPU
10606 * to wakeup in wakeup handler if interrupts happen
10607 * when the vCPU is in blocked state.
10608 */
10609 dest = cpu_physical_id(vcpu->pre_pcpu);
10610
10611 if (x2apic_enabled())
10612 new.ndst = dest;
10613 else
10614 new.ndst = (dest << 8) & 0xFF00;
10615
10616 /* set 'NV' to 'wakeup vector' */
10617 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10618 } while (cmpxchg(&pi_desc->control, old.control,
10619 new.control) != old.control);
10620
10621 return 0;
10622}
10623
10624static void vmx_post_block(struct kvm_vcpu *vcpu)
10625{
10626 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10627 struct pi_desc old, new;
10628 unsigned int dest;
10629 unsigned long flags;
10630
10631 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10632 !irq_remapping_cap(IRQ_POSTING_CAP))
10633 return;
10634
10635 do {
10636 old.control = new.control = pi_desc->control;
10637
10638 dest = cpu_physical_id(vcpu->cpu);
10639
10640 if (x2apic_enabled())
10641 new.ndst = dest;
10642 else
10643 new.ndst = (dest << 8) & 0xFF00;
10644
10645 /* Allow posting non-urgent interrupts */
10646 new.sn = 0;
10647
10648 /* set 'NV' to 'notification vector' */
10649 new.nv = POSTED_INTR_VECTOR;
10650 } while (cmpxchg(&pi_desc->control, old.control,
10651 new.control) != old.control);
10652
10653 if(vcpu->pre_pcpu != -1) {
10654 spin_lock_irqsave(
10655 &per_cpu(blocked_vcpu_on_cpu_lock,
10656 vcpu->pre_pcpu), flags);
10657 list_del(&vcpu->blocked_vcpu_list);
10658 spin_unlock_irqrestore(
10659 &per_cpu(blocked_vcpu_on_cpu_lock,
10660 vcpu->pre_pcpu), flags);
10661 vcpu->pre_pcpu = -1;
10662 }
10663}
10664
efc64404
FW		 10665/*
10666 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10667 *
10668 * @kvm: kvm
10669 * @host_irq: host irq of the interrupt
10670 * @guest_irq: gsi of the interrupt
10671 * @set: set or unset PI
10672 * returns 0 on success, < 0 on failure
10673 */
10674static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10675 uint32_t guest_irq, bool set)
10676{
10677 struct kvm_kernel_irq_routing_entry *e;
10678 struct kvm_irq_routing_table *irq_rt;
10679 struct kvm_lapic_irq irq;
10680 struct kvm_vcpu *vcpu;
10681 struct vcpu_data vcpu_info;
10682 int idx, ret = -EINVAL;
10683
10684 if (!kvm_arch_has_assigned_device(kvm) ||
10685 !irq_remapping_cap(IRQ_POSTING_CAP))
10686 return 0;
10687
10688 idx = srcu_read_lock(&kvm->irq_srcu);
10689 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10690 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10691
10692 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10693 if (e->type != KVM_IRQ_ROUTING_MSI)
10694 continue;
10695 /*
10696 * VT-d PI cannot support posting multicast/broadcast
10697 * interrupts to a vCPU, we still use interrupt remapping
10698 * for these kind of interrupts.
10699 *
10700 * For lowest-priority interrupts, we only support
10701 * those with single CPU as the destination, e.g. user
10702 * configures the interrupts via /proc/irq or uses
10703 * irqbalance to make the interrupts single-CPU.
10704 *
10705 * We will support full lowest-priority interrupt later.
10706 */
10707
10708 kvm_set_msi_irq(e, &irq);
10709 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10710 continue;
10711
10712 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10713 vcpu_info.vector = irq.vector;
10714
10715 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10716 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10717
10718 if (set)
10719 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10720 else {
10721 /* suppress notification event before unposting */
10722 pi_set_sn(vcpu_to_pi_desc(vcpu));
10723 ret = irq_set_vcpu_affinity(host_irq, NULL);
10724 pi_clear_sn(vcpu_to_pi_desc(vcpu));
10725 }
10726
10727 if (ret < 0) {
10728 printk(KERN_INFO "%s: failed to update PI IRTE\n",
10729 __func__);
10730 goto out;
10731 }
10732 }
10733
10734 ret = 0;
10735out:
10736 srcu_read_unlock(&kvm->irq_srcu, idx);
10737 return ret;
10738}
10739
cbdd1bea 10740static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 10741 .cpu_has_kvm_support = cpu_has_kvm_support,
10742 .disabled_by_bios = vmx_disabled_by_bios,
10743 .hardware_setup = hardware_setup,
10744 .hardware_unsetup = hardware_unsetup,
002c7f7c 10745 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 10746 .hardware_enable = hardware_enable,
10747 .hardware_disable = hardware_disable,
04547156 10748 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 10749 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK		 10750
10751 .vcpu_create = vmx_create_vcpu,
10752 .vcpu_free = vmx_free_vcpu,
04d2cc77 10753 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 10754
04d2cc77 10755 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 10756 .vcpu_load = vmx_vcpu_load,
10757 .vcpu_put = vmx_vcpu_put,
10758
c8639010 10759 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 10760 .get_msr = vmx_get_msr,
10761 .set_msr = vmx_set_msr,
10762 .get_segment_base = vmx_get_segment_base,
10763 .get_segment = vmx_get_segment,
10764 .set_segment = vmx_set_segment,
2e4d2653 10765 .get_cpl = vmx_get_cpl,
6aa8b732 10766 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 10767 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 10768 .decache_cr3 = vmx_decache_cr3,
25c4c276 10769 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 10770 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 10771 .set_cr3 = vmx_set_cr3,
10772 .set_cr4 = vmx_set_cr4,
6aa8b732 10773 .set_efer = vmx_set_efer,
6aa8b732
AK		 10774 .get_idt = vmx_get_idt,
10775 .set_idt = vmx_set_idt,
10776 .get_gdt = vmx_get_gdt,
10777 .set_gdt = vmx_set_gdt,
73aaf249
JK		 10778 .get_dr6 = vmx_get_dr6,
10779 .set_dr6 = vmx_set_dr6,
020df079 10780 .set_dr7 = vmx_set_dr7,
81908bf4 10781 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 10782 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 10783 .get_rflags = vmx_get_rflags,
10784 .set_rflags = vmx_set_rflags,
0fdd74f7 10785 .fpu_activate = vmx_fpu_activate,
02daab21 10786 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 10787
10788 .tlb_flush = vmx_flush_tlb,
6aa8b732 10789
6aa8b732 10790 .run = vmx_vcpu_run,
6062d012 10791 .handle_exit = vmx_handle_exit,
6aa8b732 10792 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 10793 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10794 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 10795 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 10796 .set_irq = vmx_inject_irq,
95ba8273 10797 .set_nmi = vmx_inject_nmi,
298101da 10798 .queue_exception = vmx_queue_exception,
b463a6f7 10799 .cancel_injection = vmx_cancel_injection,
78646121 10800 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 10801 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 10802 .get_nmi_mask = vmx_get_nmi_mask,
10803 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 10804 .enable_nmi_window = enable_nmi_window,
10805 .enable_irq_window = enable_irq_window,
10806 .update_cr8_intercept = update_cr8_intercept,
8d14695f 10807 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 10808 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d50ab6c1 10809 .cpu_uses_apicv = vmx_cpu_uses_apicv,
c7c9c56c
YZ		 10810 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10811 .hwapic_irr_update = vmx_hwapic_irr_update,
10812 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 10813 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10814 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 10815
cbc94022 10816 .set_tss_addr = vmx_set_tss_addr,
67253af5 10817 .get_tdp_level = get_ept_level,
4b12f0de 10818 .get_mt_mask = vmx_get_mt_mask,
229456fc 10819
586f9607 10820 .get_exit_info = vmx_get_exit_info,
586f9607 10821
17cc3935 10822 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 10823
10824 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 10825
10826 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 10827 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 10828
10829 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 10830
10831 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 10832
ba904635 10833 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 10834 .write_tsc_offset = vmx_write_tsc_offset,
58ea6767 10835 .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
d5c1785d 10836 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 10837
10838 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 10839
10840 .check_intercept = vmx_check_intercept,
a547c6db 10841 .handle_external_intr = vmx_handle_external_intr,
da8999d3 10842 .mpx_supported = vmx_mpx_supported,
55412b2e 10843 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 10844
10845 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 10846
10847 .sched_in = vmx_sched_in,
843e4330
KH		 10848
10849 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10850 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10851 .flush_log_dirty = vmx_flush_log_dirty,
10852 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
25462f7f 10853
bf9f6ac8
FW		 10854 .pre_block = vmx_pre_block,
10855 .post_block = vmx_post_block,
10856
25462f7f 10857 .pmu_ops = &intel_pmu_ops,
efc64404
FW		 10858
10859 .update_pi_irte = vmx_update_pi_irte,
6aa8b732
AK		 10860};
10861
10862static int __init vmx_init(void)
10863{
34a1cd60
TC		 10864 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10865 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 10866 if (r)
34a1cd60 10867 return r;
25c5f225 10868
2965faa5 10869#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 10870 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10871 crash_vmclear_local_loaded_vmcss);
10872#endif
10873
fdef3ad1 10874 return 0;
6aa8b732
AK		 10875}
10876
10877static void __exit vmx_exit(void)
10878{
2965faa5 10879#ifdef CONFIG_KEXEC_CORE
3b63a43f 10880 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10881 synchronize_rcu();
10882#endif
10883
cb498ea2 10884 kvm_exit();
6aa8b732
AK		 10885}
10886
10887module_init(vmx_init)
10888module_exit(vmx_exit)
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