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c6dc6f63 AP |
1 | /* |
2 | * i386 CPUID helper functions | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
1ef26b1f | 19 | #include "qemu/osdep.h" |
f348b6d1 | 20 | #include "qemu/cutils.h" |
c6dc6f63 AP |
21 | |
22 | #include "cpu.h" | |
63c91552 | 23 | #include "exec/exec-all.h" |
9c17d615 | 24 | #include "sysemu/kvm.h" |
8932cfdf | 25 | #include "sysemu/cpus.h" |
50a2c6e5 | 26 | #include "kvm_i386.h" |
c6dc6f63 | 27 | |
d49b6836 | 28 | #include "qemu/error-report.h" |
1de7afc9 PB |
29 | #include "qemu/option.h" |
30 | #include "qemu/config-file.h" | |
7b1b5d19 | 31 | #include "qapi/qmp/qerror.h" |
c6dc6f63 | 32 | |
8e8aba50 EH |
33 | #include "qapi-types.h" |
34 | #include "qapi-visit.h" | |
7b1b5d19 | 35 | #include "qapi/visitor.h" |
9c17d615 | 36 | #include "sysemu/arch_init.h" |
71ad61d3 | 37 | |
b834b508 | 38 | #if defined(CONFIG_KVM) |
ef8621b1 | 39 | #include <linux/kvm_para.h> |
b834b508 | 40 | #endif |
65dee380 | 41 | |
9c17d615 | 42 | #include "sysemu/sysemu.h" |
53a89e26 | 43 | #include "hw/qdev-properties.h" |
5232d00a | 44 | #include "hw/i386/topology.h" |
bdeec802 | 45 | #ifndef CONFIG_USER_ONLY |
2001d0cd | 46 | #include "exec/address-spaces.h" |
741da0d3 | 47 | #include "hw/hw.h" |
0d09e41a | 48 | #include "hw/xen/xen.h" |
0d09e41a | 49 | #include "hw/i386/apic_internal.h" |
bdeec802 IM |
50 | #endif |
51 | ||
5e891bf8 EH |
52 | |
53 | /* Cache topology CPUID constants: */ | |
54 | ||
55 | /* CPUID Leaf 2 Descriptors */ | |
56 | ||
57 | #define CPUID_2_L1D_32KB_8WAY_64B 0x2c | |
58 | #define CPUID_2_L1I_32KB_8WAY_64B 0x30 | |
59 | #define CPUID_2_L2_2MB_8WAY_64B 0x7d | |
14c985cf | 60 | #define CPUID_2_L3_16MB_16WAY_64B 0x4d |
5e891bf8 EH |
61 | |
62 | ||
63 | /* CPUID Leaf 4 constants: */ | |
64 | ||
65 | /* EAX: */ | |
66 | #define CPUID_4_TYPE_DCACHE 1 | |
67 | #define CPUID_4_TYPE_ICACHE 2 | |
68 | #define CPUID_4_TYPE_UNIFIED 3 | |
69 | ||
70 | #define CPUID_4_LEVEL(l) ((l) << 5) | |
71 | ||
72 | #define CPUID_4_SELF_INIT_LEVEL (1 << 8) | |
73 | #define CPUID_4_FULLY_ASSOC (1 << 9) | |
74 | ||
75 | /* EDX: */ | |
76 | #define CPUID_4_NO_INVD_SHARING (1 << 0) | |
77 | #define CPUID_4_INCLUSIVE (1 << 1) | |
78 | #define CPUID_4_COMPLEX_IDX (1 << 2) | |
79 | ||
80 | #define ASSOC_FULL 0xFF | |
81 | ||
82 | /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ | |
83 | #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ | |
84 | a == 2 ? 0x2 : \ | |
85 | a == 4 ? 0x4 : \ | |
86 | a == 8 ? 0x6 : \ | |
87 | a == 16 ? 0x8 : \ | |
88 | a == 32 ? 0xA : \ | |
89 | a == 48 ? 0xB : \ | |
90 | a == 64 ? 0xC : \ | |
91 | a == 96 ? 0xD : \ | |
92 | a == 128 ? 0xE : \ | |
93 | a == ASSOC_FULL ? 0xF : \ | |
94 | 0 /* invalid value */) | |
95 | ||
96 | ||
97 | /* Definitions of the hardcoded cache entries we expose: */ | |
98 | ||
99 | /* L1 data cache: */ | |
100 | #define L1D_LINE_SIZE 64 | |
101 | #define L1D_ASSOCIATIVITY 8 | |
102 | #define L1D_SETS 64 | |
103 | #define L1D_PARTITIONS 1 | |
104 | /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */ | |
105 | #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B | |
106 | /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ | |
107 | #define L1D_LINES_PER_TAG 1 | |
108 | #define L1D_SIZE_KB_AMD 64 | |
109 | #define L1D_ASSOCIATIVITY_AMD 2 | |
110 | ||
111 | /* L1 instruction cache: */ | |
112 | #define L1I_LINE_SIZE 64 | |
113 | #define L1I_ASSOCIATIVITY 8 | |
114 | #define L1I_SETS 64 | |
115 | #define L1I_PARTITIONS 1 | |
116 | /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */ | |
117 | #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B | |
118 | /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ | |
119 | #define L1I_LINES_PER_TAG 1 | |
120 | #define L1I_SIZE_KB_AMD 64 | |
121 | #define L1I_ASSOCIATIVITY_AMD 2 | |
122 | ||
123 | /* Level 2 unified cache: */ | |
124 | #define L2_LINE_SIZE 64 | |
125 | #define L2_ASSOCIATIVITY 16 | |
126 | #define L2_SETS 4096 | |
127 | #define L2_PARTITIONS 1 | |
128 | /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */ | |
129 | /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ | |
130 | #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B | |
131 | /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ | |
132 | #define L2_LINES_PER_TAG 1 | |
133 | #define L2_SIZE_KB_AMD 512 | |
134 | ||
14c985cf | 135 | /* Level 3 unified cache: */ |
5e891bf8 EH |
136 | #define L3_SIZE_KB 0 /* disabled */ |
137 | #define L3_ASSOCIATIVITY 0 /* disabled */ | |
138 | #define L3_LINES_PER_TAG 0 /* disabled */ | |
139 | #define L3_LINE_SIZE 0 /* disabled */ | |
14c985cf LM |
140 | #define L3_N_LINE_SIZE 64 |
141 | #define L3_N_ASSOCIATIVITY 16 | |
142 | #define L3_N_SETS 16384 | |
143 | #define L3_N_PARTITIONS 1 | |
144 | #define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B | |
145 | #define L3_N_LINES_PER_TAG 1 | |
146 | #define L3_N_SIZE_KB_AMD 16384 | |
5e891bf8 EH |
147 | |
148 | /* TLB definitions: */ | |
149 | ||
150 | #define L1_DTLB_2M_ASSOC 1 | |
151 | #define L1_DTLB_2M_ENTRIES 255 | |
152 | #define L1_DTLB_4K_ASSOC 1 | |
153 | #define L1_DTLB_4K_ENTRIES 255 | |
154 | ||
155 | #define L1_ITLB_2M_ASSOC 1 | |
156 | #define L1_ITLB_2M_ENTRIES 255 | |
157 | #define L1_ITLB_4K_ASSOC 1 | |
158 | #define L1_ITLB_4K_ENTRIES 255 | |
159 | ||
160 | #define L2_DTLB_2M_ASSOC 0 /* disabled */ | |
161 | #define L2_DTLB_2M_ENTRIES 0 /* disabled */ | |
162 | #define L2_DTLB_4K_ASSOC 4 | |
163 | #define L2_DTLB_4K_ENTRIES 512 | |
164 | ||
165 | #define L2_ITLB_2M_ASSOC 0 /* disabled */ | |
166 | #define L2_ITLB_2M_ENTRIES 0 /* disabled */ | |
167 | #define L2_ITLB_4K_ASSOC 4 | |
168 | #define L2_ITLB_4K_ENTRIES 512 | |
169 | ||
170 | ||
171 | ||
99b88a17 IM |
172 | static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, |
173 | uint32_t vendor2, uint32_t vendor3) | |
174 | { | |
175 | int i; | |
176 | for (i = 0; i < 4; i++) { | |
177 | dst[i] = vendor1 >> (8 * i); | |
178 | dst[i + 4] = vendor2 >> (8 * i); | |
179 | dst[i + 8] = vendor3 >> (8 * i); | |
180 | } | |
181 | dst[CPUID_VENDOR_SZ] = '\0'; | |
182 | } | |
183 | ||
621626ce EH |
184 | #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) |
185 | #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ | |
186 | CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) | |
187 | #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ | |
188 | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ | |
189 | CPUID_PSE36 | CPUID_FXSR) | |
190 | #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) | |
191 | #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ | |
192 | CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ | |
193 | CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ | |
194 | CPUID_PAE | CPUID_SEP | CPUID_APIC) | |
195 | ||
196 | #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ | |
197 | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ | |
198 | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ | |
199 | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ | |
b6c5a6f0 | 200 | CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) |
621626ce EH |
201 | /* partly implemented: |
202 | CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ | |
203 | /* missing: | |
204 | CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ | |
205 | #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ | |
206 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ | |
207 | CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ | |
19dc85db | 208 | CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ |
621626ce EH |
209 | CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR) |
210 | /* missing: | |
211 | CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, | |
212 | CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA, | |
213 | CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, | |
19dc85db RH |
214 | CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX, |
215 | CPUID_EXT_F16C, CPUID_EXT_RDRAND */ | |
621626ce EH |
216 | |
217 | #ifdef TARGET_X86_64 | |
218 | #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM) | |
219 | #else | |
220 | #define TCG_EXT2_X86_64_FEATURES 0 | |
221 | #endif | |
222 | ||
223 | #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ | |
224 | CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ | |
225 | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ | |
226 | TCG_EXT2_X86_64_FEATURES) | |
227 | #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ | |
228 | CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) | |
229 | #define TCG_EXT4_FEATURES 0 | |
230 | #define TCG_SVM_FEATURES 0 | |
231 | #define TCG_KVM_FEATURES 0 | |
232 | #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ | |
0c47242b XG |
233 | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ |
234 | CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ | |
7eb24386 PB |
235 | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ |
236 | CPUID_7_0_EBX_ERMS) | |
621626ce | 237 | /* missing: |
07929f2a | 238 | CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, |
7eb24386 | 239 | CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, |
621626ce | 240 | CPUID_7_0_EBX_RDSEED */ |
0f70ed47 | 241 | #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE) |
303752a9 | 242 | #define TCG_APM_FEATURES 0 |
28b8e4d0 | 243 | #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT |
c9cfe8f9 RH |
244 | #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) |
245 | /* missing: | |
246 | CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ | |
621626ce | 247 | |
5ef57876 | 248 | typedef struct FeatureWordInfo { |
2d5312da EH |
249 | /* feature flags names are taken from "Intel Processor Identification and |
250 | * the CPUID Instruction" and AMD's "CPUID Specification". | |
251 | * In cases of disagreement between feature naming conventions, | |
252 | * aliases may be added. | |
253 | */ | |
254 | const char *feat_names[32]; | |
04d104b6 EH |
255 | uint32_t cpuid_eax; /* Input EAX for CPUID */ |
256 | bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */ | |
257 | uint32_t cpuid_ecx; /* Input ECX value for CPUID */ | |
258 | int cpuid_reg; /* output register (R_* constant) */ | |
37ce3522 | 259 | uint32_t tcg_features; /* Feature flags supported by TCG */ |
84f1b92f | 260 | uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */ |
5ef57876 EH |
261 | } FeatureWordInfo; |
262 | ||
263 | static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { | |
bffd67b0 | 264 | [FEAT_1_EDX] = { |
2d5312da EH |
265 | .feat_names = { |
266 | "fpu", "vme", "de", "pse", | |
267 | "tsc", "msr", "pae", "mce", | |
268 | "cx8", "apic", NULL, "sep", | |
269 | "mtrr", "pge", "mca", "cmov", | |
270 | "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, | |
271 | NULL, "ds" /* Intel dts */, "acpi", "mmx", | |
272 | "fxsr", "sse", "sse2", "ss", | |
273 | "ht" /* Intel htt */, "tm", "ia64", "pbe", | |
274 | }, | |
bffd67b0 | 275 | .cpuid_eax = 1, .cpuid_reg = R_EDX, |
37ce3522 | 276 | .tcg_features = TCG_FEATURES, |
bffd67b0 EH |
277 | }, |
278 | [FEAT_1_ECX] = { | |
2d5312da EH |
279 | .feat_names = { |
280 | "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor", | |
281 | "ds_cpl", "vmx", "smx", "est", | |
282 | "tm2", "ssse3", "cid", NULL, | |
283 | "fma", "cx16", "xtpr", "pdcm", | |
284 | NULL, "pcid", "dca", "sse4.1|sse4_1", | |
285 | "sse4.2|sse4_2", "x2apic", "movbe", "popcnt", | |
286 | "tsc-deadline", "aes", "xsave", "osxsave", | |
287 | "avx", "f16c", "rdrand", "hypervisor", | |
288 | }, | |
bffd67b0 | 289 | .cpuid_eax = 1, .cpuid_reg = R_ECX, |
37ce3522 | 290 | .tcg_features = TCG_EXT_FEATURES, |
bffd67b0 | 291 | }, |
2d5312da EH |
292 | /* Feature names that are already defined on feature_name[] but |
293 | * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their | |
294 | * names on feat_names below. They are copied automatically | |
295 | * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. | |
296 | */ | |
bffd67b0 | 297 | [FEAT_8000_0001_EDX] = { |
2d5312da EH |
298 | .feat_names = { |
299 | NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, | |
300 | NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, | |
301 | NULL /* cx8 */, NULL /* apic */, NULL, "syscall", | |
302 | NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, | |
303 | NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, | |
304 | "nx|xd", NULL, "mmxext", NULL /* mmx */, | |
305 | NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb", "rdtscp", | |
306 | NULL, "lm|i64", "3dnowext", "3dnow", | |
307 | }, | |
bffd67b0 | 308 | .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX, |
37ce3522 | 309 | .tcg_features = TCG_EXT2_FEATURES, |
bffd67b0 EH |
310 | }, |
311 | [FEAT_8000_0001_ECX] = { | |
2d5312da EH |
312 | .feat_names = { |
313 | "lahf_lm", "cmp_legacy", "svm", "extapic", | |
314 | "cr8legacy", "abm", "sse4a", "misalignsse", | |
315 | "3dnowprefetch", "osvw", "ibs", "xop", | |
316 | "skinit", "wdt", NULL, "lwp", | |
317 | "fma4", "tce", NULL, "nodeid_msr", | |
318 | NULL, "tbm", "topoext", "perfctr_core", | |
319 | "perfctr_nb", NULL, NULL, NULL, | |
320 | NULL, NULL, NULL, NULL, | |
321 | }, | |
bffd67b0 | 322 | .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX, |
37ce3522 | 323 | .tcg_features = TCG_EXT3_FEATURES, |
bffd67b0 | 324 | }, |
89e49c8b | 325 | [FEAT_C000_0001_EDX] = { |
2d5312da EH |
326 | .feat_names = { |
327 | NULL, NULL, "xstore", "xstore-en", | |
328 | NULL, NULL, "xcrypt", "xcrypt-en", | |
329 | "ace2", "ace2-en", "phe", "phe-en", | |
330 | "pmm", "pmm-en", NULL, NULL, | |
331 | NULL, NULL, NULL, NULL, | |
332 | NULL, NULL, NULL, NULL, | |
333 | NULL, NULL, NULL, NULL, | |
334 | NULL, NULL, NULL, NULL, | |
335 | }, | |
89e49c8b | 336 | .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX, |
37ce3522 | 337 | .tcg_features = TCG_EXT4_FEATURES, |
89e49c8b | 338 | }, |
bffd67b0 | 339 | [FEAT_KVM] = { |
2d5312da EH |
340 | .feat_names = { |
341 | "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", | |
342 | "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt", | |
343 | NULL, NULL, NULL, NULL, | |
344 | NULL, NULL, NULL, NULL, | |
345 | NULL, NULL, NULL, NULL, | |
346 | NULL, NULL, NULL, NULL, | |
347 | "kvmclock-stable-bit", NULL, NULL, NULL, | |
348 | NULL, NULL, NULL, NULL, | |
349 | }, | |
bffd67b0 | 350 | .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX, |
37ce3522 | 351 | .tcg_features = TCG_KVM_FEATURES, |
bffd67b0 | 352 | }, |
c35bd19a | 353 | [FEAT_HYPERV_EAX] = { |
2d5312da EH |
354 | .feat_names = { |
355 | NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */, | |
356 | NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */, | |
357 | NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */, | |
358 | NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */, | |
359 | NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */, | |
360 | NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */, | |
361 | NULL, NULL, NULL, NULL, | |
362 | NULL, NULL, NULL, NULL, | |
363 | NULL, NULL, NULL, NULL, | |
364 | NULL, NULL, NULL, NULL, | |
365 | NULL, NULL, NULL, NULL, | |
366 | }, | |
c35bd19a EY |
367 | .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX, |
368 | }, | |
369 | [FEAT_HYPERV_EBX] = { | |
2d5312da EH |
370 | .feat_names = { |
371 | NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */, | |
372 | NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */, | |
373 | NULL /* hv_post_messages */, NULL /* hv_signal_events */, | |
374 | NULL /* hv_create_port */, NULL /* hv_connect_port */, | |
375 | NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */, | |
376 | NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */, | |
377 | NULL, NULL, | |
378 | NULL, NULL, NULL, NULL, | |
379 | NULL, NULL, NULL, NULL, | |
380 | NULL, NULL, NULL, NULL, | |
381 | NULL, NULL, NULL, NULL, | |
382 | }, | |
c35bd19a EY |
383 | .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX, |
384 | }, | |
385 | [FEAT_HYPERV_EDX] = { | |
2d5312da EH |
386 | .feat_names = { |
387 | NULL /* hv_mwait */, NULL /* hv_guest_debugging */, | |
388 | NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */, | |
389 | NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */, | |
390 | NULL, NULL, | |
391 | NULL, NULL, NULL /* hv_guest_crash_msr */, NULL, | |
392 | NULL, NULL, NULL, NULL, | |
393 | NULL, NULL, NULL, NULL, | |
394 | NULL, NULL, NULL, NULL, | |
395 | NULL, NULL, NULL, NULL, | |
396 | NULL, NULL, NULL, NULL, | |
397 | }, | |
c35bd19a EY |
398 | .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX, |
399 | }, | |
bffd67b0 | 400 | [FEAT_SVM] = { |
2d5312da EH |
401 | .feat_names = { |
402 | "npt", "lbrv", "svm_lock", "nrip_save", | |
403 | "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists", | |
404 | NULL, NULL, "pause_filter", NULL, | |
405 | "pfthreshold", NULL, NULL, NULL, | |
406 | NULL, NULL, NULL, NULL, | |
407 | NULL, NULL, NULL, NULL, | |
408 | NULL, NULL, NULL, NULL, | |
409 | NULL, NULL, NULL, NULL, | |
410 | }, | |
bffd67b0 | 411 | .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX, |
37ce3522 | 412 | .tcg_features = TCG_SVM_FEATURES, |
bffd67b0 EH |
413 | }, |
414 | [FEAT_7_0_EBX] = { | |
2d5312da EH |
415 | .feat_names = { |
416 | "fsgsbase", "tsc_adjust", NULL, "bmi1", | |
417 | "hle", "avx2", NULL, "smep", | |
418 | "bmi2", "erms", "invpcid", "rtm", | |
419 | NULL, NULL, "mpx", NULL, | |
420 | "avx512f", "avx512dq", "rdseed", "adx", | |
421 | "smap", "avx512ifma", "pcommit", "clflushopt", | |
422 | "clwb", NULL, "avx512pf", "avx512er", | |
423 | "avx512cd", NULL, "avx512bw", "avx512vl", | |
424 | }, | |
04d104b6 EH |
425 | .cpuid_eax = 7, |
426 | .cpuid_needs_ecx = true, .cpuid_ecx = 0, | |
427 | .cpuid_reg = R_EBX, | |
37ce3522 | 428 | .tcg_features = TCG_7_0_EBX_FEATURES, |
bffd67b0 | 429 | }, |
f74eefe0 | 430 | [FEAT_7_0_ECX] = { |
2d5312da EH |
431 | .feat_names = { |
432 | NULL, "avx512vbmi", "umip", "pku", | |
433 | "ospke", NULL, NULL, NULL, | |
434 | NULL, NULL, NULL, NULL, | |
435 | NULL, NULL, NULL, NULL, | |
436 | NULL, NULL, NULL, NULL, | |
437 | NULL, NULL, "rdpid", NULL, | |
438 | NULL, NULL, NULL, NULL, | |
439 | NULL, NULL, NULL, NULL, | |
440 | }, | |
f74eefe0 HH |
441 | .cpuid_eax = 7, |
442 | .cpuid_needs_ecx = true, .cpuid_ecx = 0, | |
443 | .cpuid_reg = R_ECX, | |
444 | .tcg_features = TCG_7_0_ECX_FEATURES, | |
445 | }, | |
303752a9 | 446 | [FEAT_8000_0007_EDX] = { |
2d5312da EH |
447 | .feat_names = { |
448 | NULL, NULL, NULL, NULL, | |
449 | NULL, NULL, NULL, NULL, | |
450 | "invtsc", NULL, NULL, NULL, | |
451 | NULL, NULL, NULL, NULL, | |
452 | NULL, NULL, NULL, NULL, | |
453 | NULL, NULL, NULL, NULL, | |
454 | NULL, NULL, NULL, NULL, | |
455 | NULL, NULL, NULL, NULL, | |
456 | }, | |
303752a9 MT |
457 | .cpuid_eax = 0x80000007, |
458 | .cpuid_reg = R_EDX, | |
459 | .tcg_features = TCG_APM_FEATURES, | |
460 | .unmigratable_flags = CPUID_APM_INVTSC, | |
461 | }, | |
0bb0b2d2 | 462 | [FEAT_XSAVE] = { |
2d5312da EH |
463 | .feat_names = { |
464 | "xsaveopt", "xsavec", "xgetbv1", "xsaves", | |
465 | NULL, NULL, NULL, NULL, | |
466 | NULL, NULL, NULL, NULL, | |
467 | NULL, NULL, NULL, NULL, | |
468 | NULL, NULL, NULL, NULL, | |
469 | NULL, NULL, NULL, NULL, | |
470 | NULL, NULL, NULL, NULL, | |
471 | NULL, NULL, NULL, NULL, | |
472 | }, | |
0bb0b2d2 PB |
473 | .cpuid_eax = 0xd, |
474 | .cpuid_needs_ecx = true, .cpuid_ecx = 1, | |
475 | .cpuid_reg = R_EAX, | |
c9cfe8f9 | 476 | .tcg_features = TCG_XSAVE_FEATURES, |
0bb0b2d2 | 477 | }, |
28b8e4d0 | 478 | [FEAT_6_EAX] = { |
2d5312da EH |
479 | .feat_names = { |
480 | NULL, NULL, "arat", NULL, | |
481 | NULL, NULL, NULL, NULL, | |
482 | NULL, NULL, NULL, NULL, | |
483 | NULL, NULL, NULL, NULL, | |
484 | NULL, NULL, NULL, NULL, | |
485 | NULL, NULL, NULL, NULL, | |
486 | NULL, NULL, NULL, NULL, | |
487 | NULL, NULL, NULL, NULL, | |
488 | }, | |
28b8e4d0 JK |
489 | .cpuid_eax = 6, .cpuid_reg = R_EAX, |
490 | .tcg_features = TCG_6_EAX_FEATURES, | |
491 | }, | |
5ef57876 EH |
492 | }; |
493 | ||
8e8aba50 EH |
494 | typedef struct X86RegisterInfo32 { |
495 | /* Name of register */ | |
496 | const char *name; | |
497 | /* QAPI enum value register */ | |
498 | X86CPURegister32 qapi_enum; | |
499 | } X86RegisterInfo32; | |
500 | ||
501 | #define REGISTER(reg) \ | |
5d371f41 | 502 | [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } |
a443bc34 | 503 | static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { |
8e8aba50 EH |
504 | REGISTER(EAX), |
505 | REGISTER(ECX), | |
506 | REGISTER(EDX), | |
507 | REGISTER(EBX), | |
508 | REGISTER(ESP), | |
509 | REGISTER(EBP), | |
510 | REGISTER(ESI), | |
511 | REGISTER(EDI), | |
512 | }; | |
513 | #undef REGISTER | |
514 | ||
3f32bd21 RH |
515 | typedef struct ExtSaveArea { |
516 | uint32_t feature, bits; | |
517 | uint32_t offset, size; | |
518 | } ExtSaveArea; | |
519 | ||
520 | static const ExtSaveArea x86_ext_save_areas[] = { | |
cfc3b074 PB |
521 | [XSTATE_YMM_BIT] = |
522 | { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, | |
ee1b09f6 EH |
523 | .offset = offsetof(X86XSaveArea, avx_state), |
524 | .size = sizeof(XSaveAVX) }, | |
cfc3b074 PB |
525 | [XSTATE_BNDREGS_BIT] = |
526 | { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, | |
ee1b09f6 EH |
527 | .offset = offsetof(X86XSaveArea, bndreg_state), |
528 | .size = sizeof(XSaveBNDREG) }, | |
cfc3b074 PB |
529 | [XSTATE_BNDCSR_BIT] = |
530 | { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, | |
ee1b09f6 EH |
531 | .offset = offsetof(X86XSaveArea, bndcsr_state), |
532 | .size = sizeof(XSaveBNDCSR) }, | |
cfc3b074 PB |
533 | [XSTATE_OPMASK_BIT] = |
534 | { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, | |
ee1b09f6 EH |
535 | .offset = offsetof(X86XSaveArea, opmask_state), |
536 | .size = sizeof(XSaveOpmask) }, | |
cfc3b074 PB |
537 | [XSTATE_ZMM_Hi256_BIT] = |
538 | { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, | |
ee1b09f6 EH |
539 | .offset = offsetof(X86XSaveArea, zmm_hi256_state), |
540 | .size = sizeof(XSaveZMM_Hi256) }, | |
cfc3b074 PB |
541 | [XSTATE_Hi16_ZMM_BIT] = |
542 | { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, | |
ee1b09f6 EH |
543 | .offset = offsetof(X86XSaveArea, hi16_zmm_state), |
544 | .size = sizeof(XSaveHi16_ZMM) }, | |
cfc3b074 PB |
545 | [XSTATE_PKRU_BIT] = |
546 | { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, | |
ee1b09f6 EH |
547 | .offset = offsetof(X86XSaveArea, pkru_state), |
548 | .size = sizeof(XSavePKRU) }, | |
2560f19f | 549 | }; |
8e8aba50 | 550 | |
8b4beddc EH |
551 | const char *get_register_name_32(unsigned int reg) |
552 | { | |
31ccdde2 | 553 | if (reg >= CPU_NB_REGS32) { |
8b4beddc EH |
554 | return NULL; |
555 | } | |
8e8aba50 | 556 | return x86_reg_info_32[reg].name; |
8b4beddc EH |
557 | } |
558 | ||
84f1b92f EH |
559 | /* |
560 | * Returns the set of feature flags that are supported and migratable by | |
561 | * QEMU, for a given FeatureWord. | |
562 | */ | |
563 | static uint32_t x86_cpu_get_migratable_flags(FeatureWord w) | |
564 | { | |
565 | FeatureWordInfo *wi = &feature_word_info[w]; | |
566 | uint32_t r = 0; | |
567 | int i; | |
568 | ||
569 | for (i = 0; i < 32; i++) { | |
570 | uint32_t f = 1U << i; | |
571 | /* If the feature name is unknown, it is not supported by QEMU yet */ | |
572 | if (!wi->feat_names[i]) { | |
573 | continue; | |
574 | } | |
575 | /* Skip features known to QEMU, but explicitly marked as unmigratable */ | |
576 | if (wi->unmigratable_flags & f) { | |
577 | continue; | |
578 | } | |
579 | r |= f; | |
580 | } | |
581 | return r; | |
582 | } | |
583 | ||
bb44e0d1 JK |
584 | void host_cpuid(uint32_t function, uint32_t count, |
585 | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) | |
bdde476a | 586 | { |
a1fd24af AL |
587 | uint32_t vec[4]; |
588 | ||
589 | #ifdef __x86_64__ | |
590 | asm volatile("cpuid" | |
591 | : "=a"(vec[0]), "=b"(vec[1]), | |
592 | "=c"(vec[2]), "=d"(vec[3]) | |
593 | : "0"(function), "c"(count) : "cc"); | |
c1f41226 | 594 | #elif defined(__i386__) |
a1fd24af AL |
595 | asm volatile("pusha \n\t" |
596 | "cpuid \n\t" | |
597 | "mov %%eax, 0(%2) \n\t" | |
598 | "mov %%ebx, 4(%2) \n\t" | |
599 | "mov %%ecx, 8(%2) \n\t" | |
600 | "mov %%edx, 12(%2) \n\t" | |
601 | "popa" | |
602 | : : "a"(function), "c"(count), "S"(vec) | |
603 | : "memory", "cc"); | |
c1f41226 EH |
604 | #else |
605 | abort(); | |
a1fd24af AL |
606 | #endif |
607 | ||
bdde476a | 608 | if (eax) |
a1fd24af | 609 | *eax = vec[0]; |
bdde476a | 610 | if (ebx) |
a1fd24af | 611 | *ebx = vec[1]; |
bdde476a | 612 | if (ecx) |
a1fd24af | 613 | *ecx = vec[2]; |
bdde476a | 614 | if (edx) |
a1fd24af | 615 | *edx = vec[3]; |
bdde476a | 616 | } |
c6dc6f63 AP |
617 | |
618 | #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c))) | |
619 | ||
620 | /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of | |
621 | * a substring. ex if !NULL points to the first char after a substring, | |
622 | * otherwise the string is assumed to sized by a terminating nul. | |
623 | * Return lexical ordering of *s1:*s2. | |
624 | */ | |
8f9d989c CF |
625 | static int sstrcmp(const char *s1, const char *e1, |
626 | const char *s2, const char *e2) | |
c6dc6f63 AP |
627 | { |
628 | for (;;) { | |
629 | if (!*s1 || !*s2 || *s1 != *s2) | |
630 | return (*s1 - *s2); | |
631 | ++s1, ++s2; | |
632 | if (s1 == e1 && s2 == e2) | |
633 | return (0); | |
634 | else if (s1 == e1) | |
635 | return (*s2); | |
636 | else if (s2 == e2) | |
637 | return (*s1); | |
638 | } | |
639 | } | |
640 | ||
641 | /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple | |
642 | * '|' delimited (possibly empty) strings in which case search for a match | |
643 | * within the alternatives proceeds left to right. Return 0 for success, | |
644 | * non-zero otherwise. | |
645 | */ | |
646 | static int altcmp(const char *s, const char *e, const char *altstr) | |
647 | { | |
648 | const char *p, *q; | |
649 | ||
650 | for (q = p = altstr; ; ) { | |
651 | while (*p && *p != '|') | |
652 | ++p; | |
653 | if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p))) | |
654 | return (0); | |
655 | if (!*p) | |
656 | return (1); | |
657 | else | |
658 | q = ++p; | |
659 | } | |
660 | } | |
661 | ||
662 | /* search featureset for flag *[s..e), if found set corresponding bit in | |
e41e0fc6 | 663 | * *pval and return true, otherwise return false |
c6dc6f63 | 664 | */ |
e41e0fc6 JK |
665 | static bool lookup_feature(uint32_t *pval, const char *s, const char *e, |
666 | const char **featureset) | |
c6dc6f63 AP |
667 | { |
668 | uint32_t mask; | |
669 | const char **ppc; | |
e41e0fc6 | 670 | bool found = false; |
c6dc6f63 | 671 | |
e41e0fc6 | 672 | for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) { |
c6dc6f63 AP |
673 | if (*ppc && !altcmp(s, e, *ppc)) { |
674 | *pval |= mask; | |
e41e0fc6 | 675 | found = true; |
c6dc6f63 | 676 | } |
e41e0fc6 JK |
677 | } |
678 | return found; | |
c6dc6f63 AP |
679 | } |
680 | ||
5ef57876 | 681 | static void add_flagname_to_bitmaps(const char *flagname, |
c00c94ab EH |
682 | FeatureWordArray words, |
683 | Error **errp) | |
c6dc6f63 | 684 | { |
5ef57876 EH |
685 | FeatureWord w; |
686 | for (w = 0; w < FEATURE_WORDS; w++) { | |
687 | FeatureWordInfo *wi = &feature_word_info[w]; | |
2d5312da | 688 | if (lookup_feature(&words[w], flagname, NULL, wi->feat_names)) { |
5ef57876 EH |
689 | break; |
690 | } | |
691 | } | |
692 | if (w == FEATURE_WORDS) { | |
c00c94ab | 693 | error_setg(errp, "CPU feature %s not found", flagname); |
5ef57876 | 694 | } |
c6dc6f63 AP |
695 | } |
696 | ||
d940ee9b EH |
697 | /* CPU class name definitions: */ |
698 | ||
699 | #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU | |
700 | #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) | |
701 | ||
702 | /* Return type name for a given CPU model name | |
703 | * Caller is responsible for freeing the returned string. | |
704 | */ | |
705 | static char *x86_cpu_type_name(const char *model_name) | |
706 | { | |
707 | return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); | |
708 | } | |
709 | ||
500050d1 AF |
710 | static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) |
711 | { | |
d940ee9b EH |
712 | ObjectClass *oc; |
713 | char *typename; | |
714 | ||
500050d1 AF |
715 | if (cpu_model == NULL) { |
716 | return NULL; | |
717 | } | |
718 | ||
d940ee9b EH |
719 | typename = x86_cpu_type_name(cpu_model); |
720 | oc = object_class_by_name(typename); | |
721 | g_free(typename); | |
722 | return oc; | |
500050d1 AF |
723 | } |
724 | ||
104494ea IM |
725 | static char *x86_cpu_class_get_model_name(X86CPUClass *cc) |
726 | { | |
727 | const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); | |
728 | assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); | |
729 | return g_strndup(class_name, | |
730 | strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); | |
731 | } | |
732 | ||
d940ee9b | 733 | struct X86CPUDefinition { |
c6dc6f63 AP |
734 | const char *name; |
735 | uint32_t level; | |
90e4b0c3 | 736 | uint32_t xlevel; |
99b88a17 IM |
737 | /* vendor is zero-terminated, 12 character ASCII string */ |
738 | char vendor[CPUID_VENDOR_SZ + 1]; | |
c6dc6f63 AP |
739 | int family; |
740 | int model; | |
741 | int stepping; | |
0514ef2f | 742 | FeatureWordArray features; |
c6dc6f63 | 743 | char model_id[48]; |
d940ee9b | 744 | }; |
c6dc6f63 | 745 | |
9576de75 | 746 | static X86CPUDefinition builtin_x86_defs[] = { |
c6dc6f63 AP |
747 | { |
748 | .name = "qemu64", | |
3046bb5d | 749 | .level = 0xd, |
99b88a17 | 750 | .vendor = CPUID_VENDOR_AMD, |
c6dc6f63 | 751 | .family = 6, |
f8e6a11a | 752 | .model = 6, |
c6dc6f63 | 753 | .stepping = 3, |
0514ef2f | 754 | .features[FEAT_1_EDX] = |
27861ecc | 755 | PPRO_FEATURES | |
c6dc6f63 | 756 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
c6dc6f63 | 757 | CPUID_PSE36, |
0514ef2f | 758 | .features[FEAT_1_ECX] = |
6aa91e4a | 759 | CPUID_EXT_SSE3 | CPUID_EXT_CX16, |
0514ef2f | 760 | .features[FEAT_8000_0001_EDX] = |
c6dc6f63 | 761 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
0514ef2f | 762 | .features[FEAT_8000_0001_ECX] = |
71195672 | 763 | CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, |
c6dc6f63 | 764 | .xlevel = 0x8000000A, |
9cf2cc3d | 765 | .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, |
c6dc6f63 AP |
766 | }, |
767 | { | |
768 | .name = "phenom", | |
769 | .level = 5, | |
99b88a17 | 770 | .vendor = CPUID_VENDOR_AMD, |
c6dc6f63 AP |
771 | .family = 16, |
772 | .model = 2, | |
773 | .stepping = 3, | |
b9fc20bc | 774 | /* Missing: CPUID_HT */ |
0514ef2f | 775 | .features[FEAT_1_EDX] = |
27861ecc | 776 | PPRO_FEATURES | |
c6dc6f63 | 777 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
b9fc20bc | 778 | CPUID_PSE36 | CPUID_VME, |
0514ef2f | 779 | .features[FEAT_1_ECX] = |
27861ecc | 780 | CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | |
c6dc6f63 | 781 | CPUID_EXT_POPCNT, |
0514ef2f | 782 | .features[FEAT_8000_0001_EDX] = |
c6dc6f63 AP |
783 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | |
784 | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | | |
8560efed | 785 | CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, |
c6dc6f63 AP |
786 | /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, |
787 | CPUID_EXT3_CR8LEG, | |
788 | CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, | |
789 | CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ | |
0514ef2f | 790 | .features[FEAT_8000_0001_ECX] = |
27861ecc | 791 | CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | |
c6dc6f63 | 792 | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, |
b9fc20bc | 793 | /* Missing: CPUID_SVM_LBRV */ |
0514ef2f | 794 | .features[FEAT_SVM] = |
b9fc20bc | 795 | CPUID_SVM_NPT, |
c6dc6f63 AP |
796 | .xlevel = 0x8000001A, |
797 | .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" | |
798 | }, | |
799 | { | |
800 | .name = "core2duo", | |
801 | .level = 10, | |
99b88a17 | 802 | .vendor = CPUID_VENDOR_INTEL, |
c6dc6f63 AP |
803 | .family = 6, |
804 | .model = 15, | |
805 | .stepping = 11, | |
b9fc20bc | 806 | /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ |
0514ef2f | 807 | .features[FEAT_1_EDX] = |
27861ecc | 808 | PPRO_FEATURES | |
c6dc6f63 | 809 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
b9fc20bc EH |
810 | CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, |
811 | /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, | |
e93abc14 | 812 | * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ |
0514ef2f | 813 | .features[FEAT_1_ECX] = |
27861ecc | 814 | CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | |
e93abc14 | 815 | CPUID_EXT_CX16, |
0514ef2f | 816 | .features[FEAT_8000_0001_EDX] = |
27861ecc | 817 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
0514ef2f | 818 | .features[FEAT_8000_0001_ECX] = |
27861ecc | 819 | CPUID_EXT3_LAHF_LM, |
c6dc6f63 AP |
820 | .xlevel = 0x80000008, |
821 | .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", | |
822 | }, | |
823 | { | |
824 | .name = "kvm64", | |
3046bb5d | 825 | .level = 0xd, |
99b88a17 | 826 | .vendor = CPUID_VENDOR_INTEL, |
c6dc6f63 AP |
827 | .family = 15, |
828 | .model = 6, | |
829 | .stepping = 1, | |
b3a4f0b1 | 830 | /* Missing: CPUID_HT */ |
0514ef2f | 831 | .features[FEAT_1_EDX] = |
b3a4f0b1 | 832 | PPRO_FEATURES | CPUID_VME | |
c6dc6f63 AP |
833 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
834 | CPUID_PSE36, | |
835 | /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ | |
0514ef2f | 836 | .features[FEAT_1_ECX] = |
27861ecc | 837 | CPUID_EXT_SSE3 | CPUID_EXT_CX16, |
c6dc6f63 | 838 | /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ |
0514ef2f | 839 | .features[FEAT_8000_0001_EDX] = |
c6dc6f63 AP |
840 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
841 | /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, | |
842 | CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, | |
843 | CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, | |
844 | CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ | |
0514ef2f | 845 | .features[FEAT_8000_0001_ECX] = |
27861ecc | 846 | 0, |
c6dc6f63 AP |
847 | .xlevel = 0x80000008, |
848 | .model_id = "Common KVM processor" | |
849 | }, | |
c6dc6f63 AP |
850 | { |
851 | .name = "qemu32", | |
852 | .level = 4, | |
99b88a17 | 853 | .vendor = CPUID_VENDOR_INTEL, |
c6dc6f63 | 854 | .family = 6, |
f8e6a11a | 855 | .model = 6, |
c6dc6f63 | 856 | .stepping = 3, |
0514ef2f | 857 | .features[FEAT_1_EDX] = |
27861ecc | 858 | PPRO_FEATURES, |
0514ef2f | 859 | .features[FEAT_1_ECX] = |
6aa91e4a | 860 | CPUID_EXT_SSE3, |
58012d66 | 861 | .xlevel = 0x80000004, |
9cf2cc3d | 862 | .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, |
c6dc6f63 | 863 | }, |
eafaf1e5 AP |
864 | { |
865 | .name = "kvm32", | |
866 | .level = 5, | |
99b88a17 | 867 | .vendor = CPUID_VENDOR_INTEL, |
eafaf1e5 AP |
868 | .family = 15, |
869 | .model = 6, | |
870 | .stepping = 1, | |
0514ef2f | 871 | .features[FEAT_1_EDX] = |
b3a4f0b1 | 872 | PPRO_FEATURES | CPUID_VME | |
eafaf1e5 | 873 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, |
0514ef2f | 874 | .features[FEAT_1_ECX] = |
27861ecc | 875 | CPUID_EXT_SSE3, |
0514ef2f | 876 | .features[FEAT_8000_0001_ECX] = |
27861ecc | 877 | 0, |
eafaf1e5 AP |
878 | .xlevel = 0x80000008, |
879 | .model_id = "Common 32-bit KVM processor" | |
880 | }, | |
c6dc6f63 AP |
881 | { |
882 | .name = "coreduo", | |
883 | .level = 10, | |
99b88a17 | 884 | .vendor = CPUID_VENDOR_INTEL, |
c6dc6f63 AP |
885 | .family = 6, |
886 | .model = 14, | |
887 | .stepping = 8, | |
b9fc20bc | 888 | /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ |
0514ef2f | 889 | .features[FEAT_1_EDX] = |
27861ecc | 890 | PPRO_FEATURES | CPUID_VME | |
b9fc20bc EH |
891 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | |
892 | CPUID_SS, | |
893 | /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, | |
e93abc14 | 894 | * CPUID_EXT_PDCM, CPUID_EXT_VMX */ |
0514ef2f | 895 | .features[FEAT_1_ECX] = |
e93abc14 | 896 | CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, |
0514ef2f | 897 | .features[FEAT_8000_0001_EDX] = |
27861ecc | 898 | CPUID_EXT2_NX, |
c6dc6f63 AP |
899 | .xlevel = 0x80000008, |
900 | .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", | |
901 | }, | |
902 | { | |
903 | .name = "486", | |
58012d66 | 904 | .level = 1, |
99b88a17 | 905 | .vendor = CPUID_VENDOR_INTEL, |
c6dc6f63 | 906 | .family = 4, |
b2a856d9 | 907 | .model = 8, |
c6dc6f63 | 908 | .stepping = 0, |
0514ef2f | 909 | .features[FEAT_1_EDX] = |
27861ecc | 910 | I486_FEATURES, |
c6dc6f63 AP |
911 | .xlevel = 0, |
912 | }, | |
913 | { | |
914 | .name = "pentium", | |
915 | .level = 1, | |
99b88a17 | 916 | .vendor = CPUID_VENDOR_INTEL, |
c6dc6f63 AP |
917 | .family = 5, |
918 | .model = 4, | |
919 | .stepping = 3, | |
0514ef2f | 920 | .features[FEAT_1_EDX] = |
27861ecc | 921 | PENTIUM_FEATURES, |
c6dc6f63 AP |
922 | .xlevel = 0, |
923 | }, | |
924 | { | |
925 | .name = "pentium2", | |
926 | .level = 2, | |
99b88a17 | 927 | .vendor = CPUID_VENDOR_INTEL, |
c6dc6f63 AP |
928 | .family = 6, |
929 | .model = 5, | |
930 | .stepping = 2, | |
0514ef2f | 931 | .features[FEAT_1_EDX] = |
27861ecc | 932 | PENTIUM2_FEATURES, |
c6dc6f63 AP |
933 | .xlevel = 0, |
934 | }, | |
935 | { | |
936 | .name = "pentium3", | |
3046bb5d | 937 | .level = 3, |
99b88a17 | 938 | .vendor = CPUID_VENDOR_INTEL, |
c6dc6f63 AP |
939 | .family = 6, |
940 | .model = 7, | |
941 | .stepping = 3, | |
0514ef2f | 942 | .features[FEAT_1_EDX] = |
27861ecc | 943 | PENTIUM3_FEATURES, |
c6dc6f63 AP |
944 | .xlevel = 0, |
945 | }, | |
946 | { | |
947 | .name = "athlon", | |
948 | .level = 2, | |
99b88a17 | 949 | .vendor = CPUID_VENDOR_AMD, |
c6dc6f63 AP |
950 | .family = 6, |
951 | .model = 2, | |
952 | .stepping = 3, | |
0514ef2f | 953 | .features[FEAT_1_EDX] = |
27861ecc | 954 | PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | |
60032ac0 | 955 | CPUID_MCA, |
0514ef2f | 956 | .features[FEAT_8000_0001_EDX] = |
60032ac0 | 957 | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, |
c6dc6f63 | 958 | .xlevel = 0x80000008, |
9cf2cc3d | 959 | .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, |
c6dc6f63 AP |
960 | }, |
961 | { | |
962 | .name = "n270", | |
3046bb5d | 963 | .level = 10, |
99b88a17 | 964 | .vendor = CPUID_VENDOR_INTEL, |
c6dc6f63 AP |
965 | .family = 6, |
966 | .model = 28, | |
967 | .stepping = 2, | |
b9fc20bc | 968 | /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ |
0514ef2f | 969 | .features[FEAT_1_EDX] = |
27861ecc | 970 | PPRO_FEATURES | |
b9fc20bc EH |
971 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | |
972 | CPUID_ACPI | CPUID_SS, | |
c6dc6f63 | 973 | /* Some CPUs got no CPUID_SEP */ |
b9fc20bc EH |
974 | /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, |
975 | * CPUID_EXT_XTPR */ | |
0514ef2f | 976 | .features[FEAT_1_ECX] = |
27861ecc | 977 | CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | |
4458c236 | 978 | CPUID_EXT_MOVBE, |
0514ef2f | 979 | .features[FEAT_8000_0001_EDX] = |
60032ac0 | 980 | CPUID_EXT2_NX, |
0514ef2f | 981 | .features[FEAT_8000_0001_ECX] = |
27861ecc | 982 | CPUID_EXT3_LAHF_LM, |
3046bb5d | 983 | .xlevel = 0x80000008, |
c6dc6f63 AP |
984 | .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", |
985 | }, | |
3eca4642 EH |
986 | { |
987 | .name = "Conroe", | |
3046bb5d | 988 | .level = 10, |
99b88a17 | 989 | .vendor = CPUID_VENDOR_INTEL, |
3eca4642 | 990 | .family = 6, |
ffce9ebb | 991 | .model = 15, |
3eca4642 | 992 | .stepping = 3, |
0514ef2f | 993 | .features[FEAT_1_EDX] = |
b3a4f0b1 | 994 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | |
b3fb3a20 EH |
995 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | |
996 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
997 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
998 | CPUID_DE | CPUID_FP87, | |
0514ef2f | 999 | .features[FEAT_1_ECX] = |
27861ecc | 1000 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, |
0514ef2f | 1001 | .features[FEAT_8000_0001_EDX] = |
27861ecc | 1002 | CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, |
0514ef2f | 1003 | .features[FEAT_8000_0001_ECX] = |
27861ecc | 1004 | CPUID_EXT3_LAHF_LM, |
3046bb5d | 1005 | .xlevel = 0x80000008, |
3eca4642 EH |
1006 | .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", |
1007 | }, | |
1008 | { | |
1009 | .name = "Penryn", | |
3046bb5d | 1010 | .level = 10, |
99b88a17 | 1011 | .vendor = CPUID_VENDOR_INTEL, |
3eca4642 | 1012 | .family = 6, |
ffce9ebb | 1013 | .model = 23, |
3eca4642 | 1014 | .stepping = 3, |
0514ef2f | 1015 | .features[FEAT_1_EDX] = |
b3a4f0b1 | 1016 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | |
b3fb3a20 EH |
1017 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | |
1018 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1019 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1020 | CPUID_DE | CPUID_FP87, | |
0514ef2f | 1021 | .features[FEAT_1_ECX] = |
27861ecc | 1022 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | |
b3fb3a20 | 1023 | CPUID_EXT_SSE3, |
0514ef2f | 1024 | .features[FEAT_8000_0001_EDX] = |
27861ecc | 1025 | CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, |
0514ef2f | 1026 | .features[FEAT_8000_0001_ECX] = |
27861ecc | 1027 | CPUID_EXT3_LAHF_LM, |
3046bb5d | 1028 | .xlevel = 0x80000008, |
3eca4642 EH |
1029 | .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", |
1030 | }, | |
1031 | { | |
1032 | .name = "Nehalem", | |
3046bb5d | 1033 | .level = 11, |
99b88a17 | 1034 | .vendor = CPUID_VENDOR_INTEL, |
3eca4642 | 1035 | .family = 6, |
ffce9ebb | 1036 | .model = 26, |
3eca4642 | 1037 | .stepping = 3, |
0514ef2f | 1038 | .features[FEAT_1_EDX] = |
b3a4f0b1 | 1039 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | |
b3fb3a20 EH |
1040 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | |
1041 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1042 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1043 | CPUID_DE | CPUID_FP87, | |
0514ef2f | 1044 | .features[FEAT_1_ECX] = |
27861ecc | 1045 | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | |
b3fb3a20 | 1046 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, |
0514ef2f | 1047 | .features[FEAT_8000_0001_EDX] = |
27861ecc | 1048 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
0514ef2f | 1049 | .features[FEAT_8000_0001_ECX] = |
27861ecc | 1050 | CPUID_EXT3_LAHF_LM, |
3046bb5d | 1051 | .xlevel = 0x80000008, |
3eca4642 EH |
1052 | .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", |
1053 | }, | |
1054 | { | |
1055 | .name = "Westmere", | |
1056 | .level = 11, | |
99b88a17 | 1057 | .vendor = CPUID_VENDOR_INTEL, |
3eca4642 EH |
1058 | .family = 6, |
1059 | .model = 44, | |
1060 | .stepping = 1, | |
0514ef2f | 1061 | .features[FEAT_1_EDX] = |
b3a4f0b1 | 1062 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | |
b3fb3a20 EH |
1063 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | |
1064 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1065 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1066 | CPUID_DE | CPUID_FP87, | |
0514ef2f | 1067 | .features[FEAT_1_ECX] = |
27861ecc | 1068 | CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | |
b3fb3a20 EH |
1069 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | |
1070 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, | |
0514ef2f | 1071 | .features[FEAT_8000_0001_EDX] = |
27861ecc | 1072 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
0514ef2f | 1073 | .features[FEAT_8000_0001_ECX] = |
27861ecc | 1074 | CPUID_EXT3_LAHF_LM, |
28b8e4d0 JK |
1075 | .features[FEAT_6_EAX] = |
1076 | CPUID_6_EAX_ARAT, | |
3046bb5d | 1077 | .xlevel = 0x80000008, |
3eca4642 EH |
1078 | .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", |
1079 | }, | |
1080 | { | |
1081 | .name = "SandyBridge", | |
1082 | .level = 0xd, | |
99b88a17 | 1083 | .vendor = CPUID_VENDOR_INTEL, |
3eca4642 EH |
1084 | .family = 6, |
1085 | .model = 42, | |
1086 | .stepping = 1, | |
0514ef2f | 1087 | .features[FEAT_1_EDX] = |
b3a4f0b1 | 1088 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | |
b3fb3a20 EH |
1089 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | |
1090 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1091 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1092 | CPUID_DE | CPUID_FP87, | |
0514ef2f | 1093 | .features[FEAT_1_ECX] = |
27861ecc | 1094 | CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | |
b3fb3a20 EH |
1095 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | |
1096 | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | | |
1097 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | | |
1098 | CPUID_EXT_SSE3, | |
0514ef2f | 1099 | .features[FEAT_8000_0001_EDX] = |
27861ecc | 1100 | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | |
b3fb3a20 | 1101 | CPUID_EXT2_SYSCALL, |
0514ef2f | 1102 | .features[FEAT_8000_0001_ECX] = |
27861ecc | 1103 | CPUID_EXT3_LAHF_LM, |
0bb0b2d2 PB |
1104 | .features[FEAT_XSAVE] = |
1105 | CPUID_XSAVE_XSAVEOPT, | |
28b8e4d0 JK |
1106 | .features[FEAT_6_EAX] = |
1107 | CPUID_6_EAX_ARAT, | |
3046bb5d | 1108 | .xlevel = 0x80000008, |
3eca4642 EH |
1109 | .model_id = "Intel Xeon E312xx (Sandy Bridge)", |
1110 | }, | |
2f9ac42a PB |
1111 | { |
1112 | .name = "IvyBridge", | |
1113 | .level = 0xd, | |
1114 | .vendor = CPUID_VENDOR_INTEL, | |
1115 | .family = 6, | |
1116 | .model = 58, | |
1117 | .stepping = 9, | |
1118 | .features[FEAT_1_EDX] = | |
1119 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
1120 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
1121 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1122 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1123 | CPUID_DE | CPUID_FP87, | |
1124 | .features[FEAT_1_ECX] = | |
1125 | CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | | |
1126 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | | |
1127 | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | | |
1128 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | | |
1129 | CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, | |
1130 | .features[FEAT_7_0_EBX] = | |
1131 | CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | | |
1132 | CPUID_7_0_EBX_ERMS, | |
1133 | .features[FEAT_8000_0001_EDX] = | |
1134 | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | | |
1135 | CPUID_EXT2_SYSCALL, | |
1136 | .features[FEAT_8000_0001_ECX] = | |
1137 | CPUID_EXT3_LAHF_LM, | |
1138 | .features[FEAT_XSAVE] = | |
1139 | CPUID_XSAVE_XSAVEOPT, | |
28b8e4d0 JK |
1140 | .features[FEAT_6_EAX] = |
1141 | CPUID_6_EAX_ARAT, | |
3046bb5d | 1142 | .xlevel = 0x80000008, |
2f9ac42a PB |
1143 | .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", |
1144 | }, | |
37507094 | 1145 | { |
a356850b EH |
1146 | .name = "Haswell-noTSX", |
1147 | .level = 0xd, | |
1148 | .vendor = CPUID_VENDOR_INTEL, | |
1149 | .family = 6, | |
1150 | .model = 60, | |
1151 | .stepping = 1, | |
1152 | .features[FEAT_1_EDX] = | |
1153 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
1154 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
1155 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1156 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1157 | CPUID_DE | CPUID_FP87, | |
1158 | .features[FEAT_1_ECX] = | |
1159 | CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | | |
1160 | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | | |
1161 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | | |
1162 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | | |
1163 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | | |
1164 | CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, | |
1165 | .features[FEAT_8000_0001_EDX] = | |
1166 | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | | |
1167 | CPUID_EXT2_SYSCALL, | |
1168 | .features[FEAT_8000_0001_ECX] = | |
becb6667 | 1169 | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, |
a356850b EH |
1170 | .features[FEAT_7_0_EBX] = |
1171 | CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | | |
1172 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | | |
1173 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID, | |
1174 | .features[FEAT_XSAVE] = | |
1175 | CPUID_XSAVE_XSAVEOPT, | |
28b8e4d0 JK |
1176 | .features[FEAT_6_EAX] = |
1177 | CPUID_6_EAX_ARAT, | |
3046bb5d | 1178 | .xlevel = 0x80000008, |
a356850b EH |
1179 | .model_id = "Intel Core Processor (Haswell, no TSX)", |
1180 | }, { | |
37507094 EH |
1181 | .name = "Haswell", |
1182 | .level = 0xd, | |
99b88a17 | 1183 | .vendor = CPUID_VENDOR_INTEL, |
37507094 EH |
1184 | .family = 6, |
1185 | .model = 60, | |
1186 | .stepping = 1, | |
0514ef2f | 1187 | .features[FEAT_1_EDX] = |
b3a4f0b1 | 1188 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | |
b3fb3a20 EH |
1189 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | |
1190 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1191 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1192 | CPUID_DE | CPUID_FP87, | |
0514ef2f | 1193 | .features[FEAT_1_ECX] = |
27861ecc | 1194 | CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | |
b3fb3a20 EH |
1195 | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | |
1196 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | | |
1197 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | | |
1198 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | | |
78a611f1 | 1199 | CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, |
0514ef2f | 1200 | .features[FEAT_8000_0001_EDX] = |
27861ecc | 1201 | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | |
b3fb3a20 | 1202 | CPUID_EXT2_SYSCALL, |
0514ef2f | 1203 | .features[FEAT_8000_0001_ECX] = |
becb6667 | 1204 | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, |
0514ef2f | 1205 | .features[FEAT_7_0_EBX] = |
27861ecc | 1206 | CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | |
1ee91598 EH |
1207 | CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | |
1208 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | | |
1209 | CPUID_7_0_EBX_RTM, | |
0bb0b2d2 PB |
1210 | .features[FEAT_XSAVE] = |
1211 | CPUID_XSAVE_XSAVEOPT, | |
28b8e4d0 JK |
1212 | .features[FEAT_6_EAX] = |
1213 | CPUID_6_EAX_ARAT, | |
3046bb5d | 1214 | .xlevel = 0x80000008, |
37507094 EH |
1215 | .model_id = "Intel Core Processor (Haswell)", |
1216 | }, | |
a356850b EH |
1217 | { |
1218 | .name = "Broadwell-noTSX", | |
1219 | .level = 0xd, | |
1220 | .vendor = CPUID_VENDOR_INTEL, | |
1221 | .family = 6, | |
1222 | .model = 61, | |
1223 | .stepping = 2, | |
1224 | .features[FEAT_1_EDX] = | |
1225 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
1226 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
1227 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1228 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1229 | CPUID_DE | CPUID_FP87, | |
1230 | .features[FEAT_1_ECX] = | |
1231 | CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | | |
1232 | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | | |
1233 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | | |
1234 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | | |
1235 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | | |
1236 | CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, | |
1237 | .features[FEAT_8000_0001_EDX] = | |
1238 | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | | |
1239 | CPUID_EXT2_SYSCALL, | |
1240 | .features[FEAT_8000_0001_ECX] = | |
becb6667 | 1241 | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, |
a356850b EH |
1242 | .features[FEAT_7_0_EBX] = |
1243 | CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | | |
1244 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | | |
1245 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | | |
1246 | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | | |
1247 | CPUID_7_0_EBX_SMAP, | |
1248 | .features[FEAT_XSAVE] = | |
1249 | CPUID_XSAVE_XSAVEOPT, | |
28b8e4d0 JK |
1250 | .features[FEAT_6_EAX] = |
1251 | CPUID_6_EAX_ARAT, | |
3046bb5d | 1252 | .xlevel = 0x80000008, |
a356850b EH |
1253 | .model_id = "Intel Core Processor (Broadwell, no TSX)", |
1254 | }, | |
ece01354 EH |
1255 | { |
1256 | .name = "Broadwell", | |
1257 | .level = 0xd, | |
1258 | .vendor = CPUID_VENDOR_INTEL, | |
1259 | .family = 6, | |
1260 | .model = 61, | |
1261 | .stepping = 2, | |
1262 | .features[FEAT_1_EDX] = | |
b3a4f0b1 | 1263 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | |
ece01354 EH |
1264 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | |
1265 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1266 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1267 | CPUID_DE | CPUID_FP87, | |
1268 | .features[FEAT_1_ECX] = | |
1269 | CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | | |
1270 | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | | |
1271 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | | |
1272 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | | |
1273 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | | |
78a611f1 | 1274 | CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, |
ece01354 EH |
1275 | .features[FEAT_8000_0001_EDX] = |
1276 | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | | |
1277 | CPUID_EXT2_SYSCALL, | |
1278 | .features[FEAT_8000_0001_ECX] = | |
becb6667 | 1279 | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, |
ece01354 EH |
1280 | .features[FEAT_7_0_EBX] = |
1281 | CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | | |
1ee91598 | 1282 | CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | |
ece01354 | 1283 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | |
1ee91598 | 1284 | CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | |
ece01354 | 1285 | CPUID_7_0_EBX_SMAP, |
0bb0b2d2 PB |
1286 | .features[FEAT_XSAVE] = |
1287 | CPUID_XSAVE_XSAVEOPT, | |
28b8e4d0 JK |
1288 | .features[FEAT_6_EAX] = |
1289 | CPUID_6_EAX_ARAT, | |
3046bb5d | 1290 | .xlevel = 0x80000008, |
ece01354 EH |
1291 | .model_id = "Intel Core Processor (Broadwell)", |
1292 | }, | |
f6f949e9 EH |
1293 | { |
1294 | .name = "Skylake-Client", | |
1295 | .level = 0xd, | |
1296 | .vendor = CPUID_VENDOR_INTEL, | |
1297 | .family = 6, | |
1298 | .model = 94, | |
1299 | .stepping = 3, | |
1300 | .features[FEAT_1_EDX] = | |
1301 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
1302 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
1303 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1304 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1305 | CPUID_DE | CPUID_FP87, | |
1306 | .features[FEAT_1_ECX] = | |
1307 | CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | | |
1308 | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | | |
1309 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | | |
1310 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | | |
1311 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | | |
1312 | CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, | |
1313 | .features[FEAT_8000_0001_EDX] = | |
1314 | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | | |
1315 | CPUID_EXT2_SYSCALL, | |
1316 | .features[FEAT_8000_0001_ECX] = | |
1317 | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, | |
1318 | .features[FEAT_7_0_EBX] = | |
1319 | CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | | |
1320 | CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | | |
1321 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | | |
1322 | CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | | |
1323 | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX, | |
1324 | /* Missing: XSAVES (not supported by some Linux versions, | |
1325 | * including v4.1 to v4.6). | |
1326 | * KVM doesn't yet expose any XSAVES state save component, | |
1327 | * and the only one defined in Skylake (processor tracing) | |
1328 | * probably will block migration anyway. | |
1329 | */ | |
1330 | .features[FEAT_XSAVE] = | |
1331 | CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | | |
1332 | CPUID_XSAVE_XGETBV1, | |
1333 | .features[FEAT_6_EAX] = | |
1334 | CPUID_6_EAX_ARAT, | |
1335 | .xlevel = 0x80000008, | |
1336 | .model_id = "Intel Core Processor (Skylake)", | |
1337 | }, | |
3eca4642 EH |
1338 | { |
1339 | .name = "Opteron_G1", | |
1340 | .level = 5, | |
99b88a17 | 1341 | .vendor = CPUID_VENDOR_AMD, |
3eca4642 EH |
1342 | .family = 15, |
1343 | .model = 6, | |
1344 | .stepping = 1, | |
0514ef2f | 1345 | .features[FEAT_1_EDX] = |
b3a4f0b1 | 1346 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | |
b3fb3a20 EH |
1347 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | |
1348 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1349 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1350 | CPUID_DE | CPUID_FP87, | |
0514ef2f | 1351 | .features[FEAT_1_ECX] = |
27861ecc | 1352 | CPUID_EXT_SSE3, |
0514ef2f | 1353 | .features[FEAT_8000_0001_EDX] = |
27861ecc | 1354 | CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | |
b3fb3a20 EH |
1355 | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | |
1356 | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | | |
1357 | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | | |
1358 | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | | |
1359 | CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, | |
3eca4642 EH |
1360 | .xlevel = 0x80000008, |
1361 | .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", | |
1362 | }, | |
1363 | { | |
1364 | .name = "Opteron_G2", | |
1365 | .level = 5, | |
99b88a17 | 1366 | .vendor = CPUID_VENDOR_AMD, |
3eca4642 EH |
1367 | .family = 15, |
1368 | .model = 6, | |
1369 | .stepping = 1, | |
0514ef2f | 1370 | .features[FEAT_1_EDX] = |
b3a4f0b1 | 1371 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | |
b3fb3a20 EH |
1372 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | |
1373 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1374 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1375 | CPUID_DE | CPUID_FP87, | |
0514ef2f | 1376 | .features[FEAT_1_ECX] = |
27861ecc | 1377 | CPUID_EXT_CX16 | CPUID_EXT_SSE3, |
33b5e8c0 | 1378 | /* Missing: CPUID_EXT2_RDTSCP */ |
0514ef2f | 1379 | .features[FEAT_8000_0001_EDX] = |
33b5e8c0 | 1380 | CPUID_EXT2_LM | CPUID_EXT2_FXSR | |
b3fb3a20 EH |
1381 | CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | |
1382 | CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | | |
1383 | CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | | |
1384 | CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | | |
1385 | CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE | | |
1386 | CPUID_EXT2_DE | CPUID_EXT2_FPU, | |
0514ef2f | 1387 | .features[FEAT_8000_0001_ECX] = |
27861ecc | 1388 | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, |
3eca4642 EH |
1389 | .xlevel = 0x80000008, |
1390 | .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", | |
1391 | }, | |
1392 | { | |
1393 | .name = "Opteron_G3", | |
1394 | .level = 5, | |
99b88a17 | 1395 | .vendor = CPUID_VENDOR_AMD, |
3eca4642 EH |
1396 | .family = 15, |
1397 | .model = 6, | |
1398 | .stepping = 1, | |
0514ef2f | 1399 | .features[FEAT_1_EDX] = |
b3a4f0b1 | 1400 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | |
b3fb3a20 EH |
1401 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | |
1402 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1403 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1404 | CPUID_DE | CPUID_FP87, | |
0514ef2f | 1405 | .features[FEAT_1_ECX] = |
27861ecc | 1406 | CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | |
b3fb3a20 | 1407 | CPUID_EXT_SSE3, |
33b5e8c0 | 1408 | /* Missing: CPUID_EXT2_RDTSCP */ |
0514ef2f | 1409 | .features[FEAT_8000_0001_EDX] = |
33b5e8c0 | 1410 | CPUID_EXT2_LM | CPUID_EXT2_FXSR | |
b3fb3a20 EH |
1411 | CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | |
1412 | CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | | |
1413 | CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | | |
1414 | CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | | |
1415 | CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE | | |
1416 | CPUID_EXT2_DE | CPUID_EXT2_FPU, | |
0514ef2f | 1417 | .features[FEAT_8000_0001_ECX] = |
27861ecc | 1418 | CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | |
b3fb3a20 | 1419 | CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, |
3eca4642 EH |
1420 | .xlevel = 0x80000008, |
1421 | .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", | |
1422 | }, | |
1423 | { | |
1424 | .name = "Opteron_G4", | |
1425 | .level = 0xd, | |
99b88a17 | 1426 | .vendor = CPUID_VENDOR_AMD, |
3eca4642 EH |
1427 | .family = 21, |
1428 | .model = 1, | |
1429 | .stepping = 2, | |
0514ef2f | 1430 | .features[FEAT_1_EDX] = |
b3a4f0b1 | 1431 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | |
b3fb3a20 EH |
1432 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | |
1433 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1434 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1435 | CPUID_DE | CPUID_FP87, | |
0514ef2f | 1436 | .features[FEAT_1_ECX] = |
27861ecc | 1437 | CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | |
b3fb3a20 EH |
1438 | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | |
1439 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | | |
1440 | CPUID_EXT_SSE3, | |
33b5e8c0 | 1441 | /* Missing: CPUID_EXT2_RDTSCP */ |
0514ef2f | 1442 | .features[FEAT_8000_0001_EDX] = |
33b5e8c0 | 1443 | CPUID_EXT2_LM | |
b3fb3a20 EH |
1444 | CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | |
1445 | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | | |
1446 | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | | |
1447 | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | | |
1448 | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | | |
1449 | CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, | |
0514ef2f | 1450 | .features[FEAT_8000_0001_ECX] = |
27861ecc | 1451 | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | |
b3fb3a20 EH |
1452 | CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | |
1453 | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | | |
1454 | CPUID_EXT3_LAHF_LM, | |
0bb0b2d2 | 1455 | /* no xsaveopt! */ |
3eca4642 EH |
1456 | .xlevel = 0x8000001A, |
1457 | .model_id = "AMD Opteron 62xx class CPU", | |
1458 | }, | |
021941b9 AP |
1459 | { |
1460 | .name = "Opteron_G5", | |
1461 | .level = 0xd, | |
99b88a17 | 1462 | .vendor = CPUID_VENDOR_AMD, |
021941b9 AP |
1463 | .family = 21, |
1464 | .model = 2, | |
1465 | .stepping = 0, | |
0514ef2f | 1466 | .features[FEAT_1_EDX] = |
b3a4f0b1 | 1467 | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | |
b3fb3a20 EH |
1468 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | |
1469 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1470 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1471 | CPUID_DE | CPUID_FP87, | |
0514ef2f | 1472 | .features[FEAT_1_ECX] = |
27861ecc | 1473 | CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | |
b3fb3a20 EH |
1474 | CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | |
1475 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | | |
1476 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, | |
33b5e8c0 | 1477 | /* Missing: CPUID_EXT2_RDTSCP */ |
0514ef2f | 1478 | .features[FEAT_8000_0001_EDX] = |
33b5e8c0 | 1479 | CPUID_EXT2_LM | |
b3fb3a20 EH |
1480 | CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | |
1481 | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | | |
1482 | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | | |
1483 | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | | |
1484 | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | | |
1485 | CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, | |
0514ef2f | 1486 | .features[FEAT_8000_0001_ECX] = |
27861ecc | 1487 | CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | |
b3fb3a20 EH |
1488 | CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | |
1489 | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | | |
1490 | CPUID_EXT3_LAHF_LM, | |
0bb0b2d2 | 1491 | /* no xsaveopt! */ |
021941b9 AP |
1492 | .xlevel = 0x8000001A, |
1493 | .model_id = "AMD Opteron 63xx class CPU", | |
1494 | }, | |
c6dc6f63 AP |
1495 | }; |
1496 | ||
5114e842 EH |
1497 | typedef struct PropValue { |
1498 | const char *prop, *value; | |
1499 | } PropValue; | |
1500 | ||
1501 | /* KVM-specific features that are automatically added/removed | |
1502 | * from all CPU models when KVM is enabled. | |
1503 | */ | |
1504 | static PropValue kvm_default_props[] = { | |
1505 | { "kvmclock", "on" }, | |
1506 | { "kvm-nopiodelay", "on" }, | |
1507 | { "kvm-asyncpf", "on" }, | |
1508 | { "kvm-steal-time", "on" }, | |
1509 | { "kvm-pv-eoi", "on" }, | |
1510 | { "kvmclock-stable-bit", "on" }, | |
1511 | { "x2apic", "on" }, | |
1512 | { "acpi", "off" }, | |
1513 | { "monitor", "off" }, | |
1514 | { "svm", "off" }, | |
1515 | { NULL, NULL }, | |
1516 | }; | |
1517 | ||
1518 | void x86_cpu_change_kvm_default(const char *prop, const char *value) | |
1519 | { | |
1520 | PropValue *pv; | |
1521 | for (pv = kvm_default_props; pv->prop; pv++) { | |
1522 | if (!strcmp(pv->prop, prop)) { | |
1523 | pv->value = value; | |
1524 | break; | |
1525 | } | |
1526 | } | |
1527 | ||
1528 | /* It is valid to call this function only for properties that | |
1529 | * are already present in the kvm_default_props table. | |
1530 | */ | |
1531 | assert(pv->prop); | |
1532 | } | |
1533 | ||
4d1b279b EH |
1534 | static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w, |
1535 | bool migratable_only); | |
1536 | ||
d940ee9b EH |
1537 | #ifdef CONFIG_KVM |
1538 | ||
40bfe48f HZ |
1539 | static bool lmce_supported(void) |
1540 | { | |
1541 | uint64_t mce_cap; | |
1542 | ||
1543 | if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) { | |
1544 | return false; | |
1545 | } | |
1546 | ||
1547 | return !!(mce_cap & MCG_LMCE_P); | |
1548 | } | |
1549 | ||
c6dc6f63 AP |
1550 | static int cpu_x86_fill_model_id(char *str) |
1551 | { | |
1552 | uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; | |
1553 | int i; | |
1554 | ||
1555 | for (i = 0; i < 3; i++) { | |
1556 | host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); | |
1557 | memcpy(str + i * 16 + 0, &eax, 4); | |
1558 | memcpy(str + i * 16 + 4, &ebx, 4); | |
1559 | memcpy(str + i * 16 + 8, &ecx, 4); | |
1560 | memcpy(str + i * 16 + 12, &edx, 4); | |
1561 | } | |
1562 | return 0; | |
1563 | } | |
1564 | ||
d940ee9b EH |
1565 | static X86CPUDefinition host_cpudef; |
1566 | ||
84f1b92f | 1567 | static Property host_x86_cpu_properties[] = { |
120eee7d | 1568 | DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), |
e265e3e4 | 1569 | DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), |
84f1b92f EH |
1570 | DEFINE_PROP_END_OF_LIST() |
1571 | }; | |
1572 | ||
d940ee9b | 1573 | /* class_init for the "host" CPU model |
6e746f30 | 1574 | * |
d940ee9b | 1575 | * This function may be called before KVM is initialized. |
6e746f30 | 1576 | */ |
d940ee9b | 1577 | static void host_x86_cpu_class_init(ObjectClass *oc, void *data) |
c6dc6f63 | 1578 | { |
84f1b92f | 1579 | DeviceClass *dc = DEVICE_CLASS(oc); |
d940ee9b | 1580 | X86CPUClass *xcc = X86_CPU_CLASS(oc); |
c6dc6f63 AP |
1581 | uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; |
1582 | ||
d940ee9b | 1583 | xcc->kvm_required = true; |
6e746f30 | 1584 | |
c6dc6f63 | 1585 | host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); |
d940ee9b | 1586 | x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx); |
c6dc6f63 AP |
1587 | |
1588 | host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); | |
d940ee9b EH |
1589 | host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); |
1590 | host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); | |
1591 | host_cpudef.stepping = eax & 0x0F; | |
c6dc6f63 | 1592 | |
d940ee9b | 1593 | cpu_x86_fill_model_id(host_cpudef.model_id); |
2a573259 | 1594 | |
d940ee9b | 1595 | xcc->cpu_def = &host_cpudef; |
d940ee9b EH |
1596 | |
1597 | /* level, xlevel, xlevel2, and the feature words are initialized on | |
1598 | * instance_init, because they require KVM to be initialized. | |
1599 | */ | |
84f1b92f EH |
1600 | |
1601 | dc->props = host_x86_cpu_properties; | |
4c315c27 MA |
1602 | /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */ |
1603 | dc->cannot_destroy_with_object_finalize_yet = true; | |
d940ee9b EH |
1604 | } |
1605 | ||
1606 | static void host_x86_cpu_initfn(Object *obj) | |
1607 | { | |
1608 | X86CPU *cpu = X86_CPU(obj); | |
1609 | CPUX86State *env = &cpu->env; | |
1610 | KVMState *s = kvm_state; | |
d940ee9b | 1611 | |
4d1b279b EH |
1612 | /* We can't fill the features array here because we don't know yet if |
1613 | * "migratable" is true or false. | |
1614 | */ | |
1615 | cpu->host_features = true; | |
1616 | ||
104494ea | 1617 | /* If KVM is disabled, x86_cpu_realizefn() will report an error later */ |
e4356010 | 1618 | if (kvm_enabled()) { |
c39c0edf EH |
1619 | env->cpuid_min_level = |
1620 | kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); | |
1621 | env->cpuid_min_xlevel = | |
1622 | kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); | |
1623 | env->cpuid_min_xlevel2 = | |
1624 | kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); | |
40bfe48f HZ |
1625 | |
1626 | if (lmce_supported()) { | |
1627 | object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort); | |
1628 | } | |
e4356010 | 1629 | } |
2a573259 | 1630 | |
d940ee9b | 1631 | object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort); |
c6dc6f63 AP |
1632 | } |
1633 | ||
d940ee9b EH |
1634 | static const TypeInfo host_x86_cpu_type_info = { |
1635 | .name = X86_CPU_TYPE_NAME("host"), | |
1636 | .parent = TYPE_X86_CPU, | |
1637 | .instance_init = host_x86_cpu_initfn, | |
1638 | .class_init = host_x86_cpu_class_init, | |
1639 | }; | |
1640 | ||
1641 | #endif | |
1642 | ||
8459e396 | 1643 | static void report_unavailable_features(FeatureWord w, uint32_t mask) |
c6dc6f63 | 1644 | { |
8459e396 | 1645 | FeatureWordInfo *f = &feature_word_info[w]; |
c6dc6f63 AP |
1646 | int i; |
1647 | ||
857aee33 | 1648 | for (i = 0; i < 32; ++i) { |
72370dc1 | 1649 | if ((1UL << i) & mask) { |
bffd67b0 | 1650 | const char *reg = get_register_name_32(f->cpuid_reg); |
8b4beddc | 1651 | assert(reg); |
fefb41bf | 1652 | fprintf(stderr, "warning: %s doesn't support requested feature: " |
8b4beddc | 1653 | "CPUID.%02XH:%s%s%s [bit %d]\n", |
fefb41bf | 1654 | kvm_enabled() ? "host" : "TCG", |
bffd67b0 EH |
1655 | f->cpuid_eax, reg, |
1656 | f->feat_names[i] ? "." : "", | |
1657 | f->feat_names[i] ? f->feat_names[i] : "", i); | |
c6dc6f63 | 1658 | } |
857aee33 | 1659 | } |
c6dc6f63 AP |
1660 | } |
1661 | ||
d7bce999 EB |
1662 | static void x86_cpuid_version_get_family(Object *obj, Visitor *v, |
1663 | const char *name, void *opaque, | |
1664 | Error **errp) | |
95b8519d AF |
1665 | { |
1666 | X86CPU *cpu = X86_CPU(obj); | |
1667 | CPUX86State *env = &cpu->env; | |
1668 | int64_t value; | |
1669 | ||
1670 | value = (env->cpuid_version >> 8) & 0xf; | |
1671 | if (value == 0xf) { | |
1672 | value += (env->cpuid_version >> 20) & 0xff; | |
1673 | } | |
51e72bc1 | 1674 | visit_type_int(v, name, &value, errp); |
95b8519d AF |
1675 | } |
1676 | ||
d7bce999 EB |
1677 | static void x86_cpuid_version_set_family(Object *obj, Visitor *v, |
1678 | const char *name, void *opaque, | |
1679 | Error **errp) | |
ed5e1ec3 | 1680 | { |
71ad61d3 AF |
1681 | X86CPU *cpu = X86_CPU(obj); |
1682 | CPUX86State *env = &cpu->env; | |
1683 | const int64_t min = 0; | |
1684 | const int64_t max = 0xff + 0xf; | |
65cd9064 | 1685 | Error *local_err = NULL; |
71ad61d3 AF |
1686 | int64_t value; |
1687 | ||
51e72bc1 | 1688 | visit_type_int(v, name, &value, &local_err); |
65cd9064 MA |
1689 | if (local_err) { |
1690 | error_propagate(errp, local_err); | |
71ad61d3 AF |
1691 | return; |
1692 | } | |
1693 | if (value < min || value > max) { | |
c6bd8c70 MA |
1694 | error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", |
1695 | name ? name : "null", value, min, max); | |
71ad61d3 AF |
1696 | return; |
1697 | } | |
1698 | ||
ed5e1ec3 | 1699 | env->cpuid_version &= ~0xff00f00; |
71ad61d3 AF |
1700 | if (value > 0x0f) { |
1701 | env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); | |
ed5e1ec3 | 1702 | } else { |
71ad61d3 | 1703 | env->cpuid_version |= value << 8; |
ed5e1ec3 AF |
1704 | } |
1705 | } | |
1706 | ||
d7bce999 EB |
1707 | static void x86_cpuid_version_get_model(Object *obj, Visitor *v, |
1708 | const char *name, void *opaque, | |
1709 | Error **errp) | |
67e30c83 AF |
1710 | { |
1711 | X86CPU *cpu = X86_CPU(obj); | |
1712 | CPUX86State *env = &cpu->env; | |
1713 | int64_t value; | |
1714 | ||
1715 | value = (env->cpuid_version >> 4) & 0xf; | |
1716 | value |= ((env->cpuid_version >> 16) & 0xf) << 4; | |
51e72bc1 | 1717 | visit_type_int(v, name, &value, errp); |
67e30c83 AF |
1718 | } |
1719 | ||
d7bce999 EB |
1720 | static void x86_cpuid_version_set_model(Object *obj, Visitor *v, |
1721 | const char *name, void *opaque, | |
1722 | Error **errp) | |
b0704cbd | 1723 | { |
c5291a4f AF |
1724 | X86CPU *cpu = X86_CPU(obj); |
1725 | CPUX86State *env = &cpu->env; | |
1726 | const int64_t min = 0; | |
1727 | const int64_t max = 0xff; | |
65cd9064 | 1728 | Error *local_err = NULL; |
c5291a4f AF |
1729 | int64_t value; |
1730 | ||
51e72bc1 | 1731 | visit_type_int(v, name, &value, &local_err); |
65cd9064 MA |
1732 | if (local_err) { |
1733 | error_propagate(errp, local_err); | |
c5291a4f AF |
1734 | return; |
1735 | } | |
1736 | if (value < min || value > max) { | |
c6bd8c70 MA |
1737 | error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", |
1738 | name ? name : "null", value, min, max); | |
c5291a4f AF |
1739 | return; |
1740 | } | |
1741 | ||
b0704cbd | 1742 | env->cpuid_version &= ~0xf00f0; |
c5291a4f | 1743 | env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); |
b0704cbd AF |
1744 | } |
1745 | ||
35112e41 | 1746 | static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, |
d7bce999 | 1747 | const char *name, void *opaque, |
35112e41 AF |
1748 | Error **errp) |
1749 | { | |
1750 | X86CPU *cpu = X86_CPU(obj); | |
1751 | CPUX86State *env = &cpu->env; | |
1752 | int64_t value; | |
1753 | ||
1754 | value = env->cpuid_version & 0xf; | |
51e72bc1 | 1755 | visit_type_int(v, name, &value, errp); |
35112e41 AF |
1756 | } |
1757 | ||
036e2222 | 1758 | static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, |
d7bce999 | 1759 | const char *name, void *opaque, |
036e2222 | 1760 | Error **errp) |
38c3dc46 | 1761 | { |
036e2222 AF |
1762 | X86CPU *cpu = X86_CPU(obj); |
1763 | CPUX86State *env = &cpu->env; | |
1764 | const int64_t min = 0; | |
1765 | const int64_t max = 0xf; | |
65cd9064 | 1766 | Error *local_err = NULL; |
036e2222 AF |
1767 | int64_t value; |
1768 | ||
51e72bc1 | 1769 | visit_type_int(v, name, &value, &local_err); |
65cd9064 MA |
1770 | if (local_err) { |
1771 | error_propagate(errp, local_err); | |
036e2222 AF |
1772 | return; |
1773 | } | |
1774 | if (value < min || value > max) { | |
c6bd8c70 MA |
1775 | error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", |
1776 | name ? name : "null", value, min, max); | |
036e2222 AF |
1777 | return; |
1778 | } | |
1779 | ||
38c3dc46 | 1780 | env->cpuid_version &= ~0xf; |
036e2222 | 1781 | env->cpuid_version |= value & 0xf; |
38c3dc46 AF |
1782 | } |
1783 | ||
d480e1af AF |
1784 | static char *x86_cpuid_get_vendor(Object *obj, Error **errp) |
1785 | { | |
1786 | X86CPU *cpu = X86_CPU(obj); | |
1787 | CPUX86State *env = &cpu->env; | |
1788 | char *value; | |
d480e1af | 1789 | |
e42a92ae | 1790 | value = g_malloc(CPUID_VENDOR_SZ + 1); |
99b88a17 IM |
1791 | x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, |
1792 | env->cpuid_vendor3); | |
d480e1af AF |
1793 | return value; |
1794 | } | |
1795 | ||
1796 | static void x86_cpuid_set_vendor(Object *obj, const char *value, | |
1797 | Error **errp) | |
1798 | { | |
1799 | X86CPU *cpu = X86_CPU(obj); | |
1800 | CPUX86State *env = &cpu->env; | |
1801 | int i; | |
1802 | ||
9df694ee | 1803 | if (strlen(value) != CPUID_VENDOR_SZ) { |
c6bd8c70 | 1804 | error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value); |
d480e1af AF |
1805 | return; |
1806 | } | |
1807 | ||
1808 | env->cpuid_vendor1 = 0; | |
1809 | env->cpuid_vendor2 = 0; | |
1810 | env->cpuid_vendor3 = 0; | |
1811 | for (i = 0; i < 4; i++) { | |
1812 | env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); | |
1813 | env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); | |
1814 | env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); | |
1815 | } | |
d480e1af AF |
1816 | } |
1817 | ||
63e886eb AF |
1818 | static char *x86_cpuid_get_model_id(Object *obj, Error **errp) |
1819 | { | |
1820 | X86CPU *cpu = X86_CPU(obj); | |
1821 | CPUX86State *env = &cpu->env; | |
1822 | char *value; | |
1823 | int i; | |
1824 | ||
1825 | value = g_malloc(48 + 1); | |
1826 | for (i = 0; i < 48; i++) { | |
1827 | value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); | |
1828 | } | |
1829 | value[48] = '\0'; | |
1830 | return value; | |
1831 | } | |
1832 | ||
938d4c25 AF |
1833 | static void x86_cpuid_set_model_id(Object *obj, const char *model_id, |
1834 | Error **errp) | |
dcce6675 | 1835 | { |
938d4c25 AF |
1836 | X86CPU *cpu = X86_CPU(obj); |
1837 | CPUX86State *env = &cpu->env; | |
dcce6675 AF |
1838 | int c, len, i; |
1839 | ||
1840 | if (model_id == NULL) { | |
1841 | model_id = ""; | |
1842 | } | |
1843 | len = strlen(model_id); | |
d0a6acf4 | 1844 | memset(env->cpuid_model, 0, 48); |
dcce6675 AF |
1845 | for (i = 0; i < 48; i++) { |
1846 | if (i >= len) { | |
1847 | c = '\0'; | |
1848 | } else { | |
1849 | c = (uint8_t)model_id[i]; | |
1850 | } | |
1851 | env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); | |
1852 | } | |
1853 | } | |
1854 | ||
d7bce999 EB |
1855 | static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, |
1856 | void *opaque, Error **errp) | |
89e48965 AF |
1857 | { |
1858 | X86CPU *cpu = X86_CPU(obj); | |
1859 | int64_t value; | |
1860 | ||
1861 | value = cpu->env.tsc_khz * 1000; | |
51e72bc1 | 1862 | visit_type_int(v, name, &value, errp); |
89e48965 AF |
1863 | } |
1864 | ||
d7bce999 EB |
1865 | static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, |
1866 | void *opaque, Error **errp) | |
89e48965 AF |
1867 | { |
1868 | X86CPU *cpu = X86_CPU(obj); | |
1869 | const int64_t min = 0; | |
2e84849a | 1870 | const int64_t max = INT64_MAX; |
65cd9064 | 1871 | Error *local_err = NULL; |
89e48965 AF |
1872 | int64_t value; |
1873 | ||
51e72bc1 | 1874 | visit_type_int(v, name, &value, &local_err); |
65cd9064 MA |
1875 | if (local_err) { |
1876 | error_propagate(errp, local_err); | |
89e48965 AF |
1877 | return; |
1878 | } | |
1879 | if (value < min || value > max) { | |
c6bd8c70 MA |
1880 | error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", |
1881 | name ? name : "null", value, min, max); | |
89e48965 AF |
1882 | return; |
1883 | } | |
1884 | ||
36f96c4b | 1885 | cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; |
89e48965 AF |
1886 | } |
1887 | ||
7e5292b5 | 1888 | /* Generic getter for "feature-words" and "filtered-features" properties */ |
d7bce999 EB |
1889 | static void x86_cpu_get_feature_words(Object *obj, Visitor *v, |
1890 | const char *name, void *opaque, | |
1891 | Error **errp) | |
8e8aba50 | 1892 | { |
7e5292b5 | 1893 | uint32_t *array = (uint32_t *)opaque; |
8e8aba50 | 1894 | FeatureWord w; |
8e8aba50 EH |
1895 | X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; |
1896 | X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; | |
1897 | X86CPUFeatureWordInfoList *list = NULL; | |
1898 | ||
1899 | for (w = 0; w < FEATURE_WORDS; w++) { | |
1900 | FeatureWordInfo *wi = &feature_word_info[w]; | |
1901 | X86CPUFeatureWordInfo *qwi = &word_infos[w]; | |
1902 | qwi->cpuid_input_eax = wi->cpuid_eax; | |
1903 | qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx; | |
1904 | qwi->cpuid_input_ecx = wi->cpuid_ecx; | |
1905 | qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum; | |
7e5292b5 | 1906 | qwi->features = array[w]; |
8e8aba50 EH |
1907 | |
1908 | /* List will be in reverse order, but order shouldn't matter */ | |
1909 | list_entries[w].next = list; | |
1910 | list_entries[w].value = &word_infos[w]; | |
1911 | list = &list_entries[w]; | |
1912 | } | |
1913 | ||
6b62d961 | 1914 | visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); |
8e8aba50 EH |
1915 | } |
1916 | ||
d7bce999 EB |
1917 | static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name, |
1918 | void *opaque, Error **errp) | |
c8f0f88e IM |
1919 | { |
1920 | X86CPU *cpu = X86_CPU(obj); | |
1921 | int64_t value = cpu->hyperv_spinlock_attempts; | |
1922 | ||
51e72bc1 | 1923 | visit_type_int(v, name, &value, errp); |
c8f0f88e IM |
1924 | } |
1925 | ||
d7bce999 EB |
1926 | static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name, |
1927 | void *opaque, Error **errp) | |
c8f0f88e IM |
1928 | { |
1929 | const int64_t min = 0xFFF; | |
1930 | const int64_t max = UINT_MAX; | |
1931 | X86CPU *cpu = X86_CPU(obj); | |
1932 | Error *err = NULL; | |
1933 | int64_t value; | |
1934 | ||
51e72bc1 | 1935 | visit_type_int(v, name, &value, &err); |
c8f0f88e IM |
1936 | if (err) { |
1937 | error_propagate(errp, err); | |
1938 | return; | |
1939 | } | |
1940 | ||
1941 | if (value < min || value > max) { | |
1942 | error_setg(errp, "Property %s.%s doesn't take value %" PRId64 | |
5bb4c35d | 1943 | " (minimum: %" PRId64 ", maximum: %" PRId64 ")", |
1944 | object_get_typename(obj), name ? name : "null", | |
1945 | value, min, max); | |
c8f0f88e IM |
1946 | return; |
1947 | } | |
1948 | cpu->hyperv_spinlock_attempts = value; | |
1949 | } | |
1950 | ||
1951 | static PropertyInfo qdev_prop_spinlocks = { | |
1952 | .name = "int", | |
1953 | .get = x86_get_hv_spinlocks, | |
1954 | .set = x86_set_hv_spinlocks, | |
1955 | }; | |
1956 | ||
72ac2e87 IM |
1957 | /* Convert all '_' in a feature string option name to '-', to make feature |
1958 | * name conform to QOM property naming rule, which uses '-' instead of '_'. | |
1959 | */ | |
1960 | static inline void feat2prop(char *s) | |
1961 | { | |
1962 | while ((s = strchr(s, '_'))) { | |
1963 | *s = '-'; | |
1964 | } | |
1965 | } | |
1966 | ||
dc15c051 IM |
1967 | /* Compatibily hack to maintain legacy +-feat semantic, |
1968 | * where +-feat overwrites any feature set by | |
1969 | * feat=on|feat even if the later is parsed after +-feat | |
1970 | * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) | |
1971 | */ | |
1972 | static FeatureWordArray plus_features = { 0 }; | |
1973 | static FeatureWordArray minus_features = { 0 }; | |
1974 | ||
8f961357 EH |
1975 | /* Parse "+feature,-feature,feature=foo" CPU feature string |
1976 | */ | |
62a48a2a | 1977 | static void x86_cpu_parse_featurestr(const char *typename, char *features, |
94a444b2 | 1978 | Error **errp) |
8f961357 | 1979 | { |
8f961357 | 1980 | char *featurestr; /* Single 'key=value" string being parsed */ |
94a444b2 | 1981 | Error *local_err = NULL; |
62a48a2a IM |
1982 | static bool cpu_globals_initialized; |
1983 | ||
1984 | if (cpu_globals_initialized) { | |
1985 | return; | |
1986 | } | |
1987 | cpu_globals_initialized = true; | |
8f961357 | 1988 | |
f6750e95 EH |
1989 | if (!features) { |
1990 | return; | |
1991 | } | |
1992 | ||
1993 | for (featurestr = strtok(features, ","); | |
1994 | featurestr && !local_err; | |
1995 | featurestr = strtok(NULL, ",")) { | |
1996 | const char *name; | |
1997 | const char *val = NULL; | |
1998 | char *eq = NULL; | |
cf2887c9 | 1999 | char num[32]; |
62a48a2a | 2000 | GlobalProperty *prop; |
c6dc6f63 | 2001 | |
f6750e95 | 2002 | /* Compatibility syntax: */ |
c6dc6f63 | 2003 | if (featurestr[0] == '+') { |
c00c94ab | 2004 | add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err); |
f6750e95 | 2005 | continue; |
c6dc6f63 | 2006 | } else if (featurestr[0] == '-') { |
c00c94ab | 2007 | add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err); |
f6750e95 EH |
2008 | continue; |
2009 | } | |
2010 | ||
2011 | eq = strchr(featurestr, '='); | |
2012 | if (eq) { | |
2013 | *eq++ = 0; | |
2014 | val = eq; | |
c6dc6f63 | 2015 | } else { |
f6750e95 | 2016 | val = "on"; |
a91987c2 | 2017 | } |
f6750e95 EH |
2018 | |
2019 | feat2prop(featurestr); | |
2020 | name = featurestr; | |
2021 | ||
2022 | /* Special case: */ | |
2023 | if (!strcmp(name, "tsc-freq")) { | |
2024 | int64_t tsc_freq; | |
2025 | char *err; | |
f6750e95 EH |
2026 | |
2027 | tsc_freq = qemu_strtosz_suffix_unit(val, &err, | |
2028 | QEMU_STRTOSZ_DEFSUFFIX_B, 1000); | |
2029 | if (tsc_freq < 0 || *err) { | |
2030 | error_setg(errp, "bad numerical value %s", val); | |
2031 | return; | |
2032 | } | |
2033 | snprintf(num, sizeof(num), "%" PRId64, tsc_freq); | |
2034 | val = num; | |
2035 | name = "tsc-frequency"; | |
c6dc6f63 | 2036 | } |
f6750e95 | 2037 | |
62a48a2a IM |
2038 | prop = g_new0(typeof(*prop), 1); |
2039 | prop->driver = typename; | |
2040 | prop->property = g_strdup(name); | |
2041 | prop->value = g_strdup(val); | |
2042 | prop->errp = &error_fatal; | |
2043 | qdev_prop_register_global(prop); | |
f6750e95 EH |
2044 | } |
2045 | ||
2046 | if (local_err) { | |
2047 | error_propagate(errp, local_err); | |
c6dc6f63 | 2048 | } |
c6dc6f63 AP |
2049 | } |
2050 | ||
8c3329e5 | 2051 | /* Print all cpuid feature names in featureset |
c6dc6f63 | 2052 | */ |
8c3329e5 | 2053 | static void listflags(FILE *f, fprintf_function print, const char **featureset) |
0856579c | 2054 | { |
8c3329e5 EH |
2055 | int bit; |
2056 | bool first = true; | |
2057 | ||
2058 | for (bit = 0; bit < 32; bit++) { | |
2059 | if (featureset[bit]) { | |
2060 | print(f, "%s%s", first ? "" : " ", featureset[bit]); | |
2061 | first = false; | |
c6dc6f63 | 2062 | } |
8c3329e5 | 2063 | } |
c6dc6f63 AP |
2064 | } |
2065 | ||
e916cbf8 PM |
2066 | /* generate CPU information. */ |
2067 | void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
c6dc6f63 | 2068 | { |
9576de75 | 2069 | X86CPUDefinition *def; |
c6dc6f63 | 2070 | char buf[256]; |
7fc9b714 | 2071 | int i; |
c6dc6f63 | 2072 | |
7fc9b714 AF |
2073 | for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { |
2074 | def = &builtin_x86_defs[i]; | |
c04321b3 | 2075 | snprintf(buf, sizeof(buf), "%s", def->name); |
6cdf8854 | 2076 | (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id); |
c6dc6f63 | 2077 | } |
21ad7789 JK |
2078 | #ifdef CONFIG_KVM |
2079 | (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host", | |
2080 | "KVM processor with all supported host features " | |
2081 | "(only available in KVM mode)"); | |
2082 | #endif | |
2083 | ||
6cdf8854 | 2084 | (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n"); |
3af60be2 JK |
2085 | for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { |
2086 | FeatureWordInfo *fw = &feature_word_info[i]; | |
2087 | ||
8c3329e5 EH |
2088 | (*cpu_fprintf)(f, " "); |
2089 | listflags(f, cpu_fprintf, fw->feat_names); | |
2090 | (*cpu_fprintf)(f, "\n"); | |
3af60be2 | 2091 | } |
c6dc6f63 AP |
2092 | } |
2093 | ||
76b64a7a | 2094 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) |
e3966126 AL |
2095 | { |
2096 | CpuDefinitionInfoList *cpu_list = NULL; | |
9576de75 | 2097 | X86CPUDefinition *def; |
7fc9b714 | 2098 | int i; |
e3966126 | 2099 | |
7fc9b714 | 2100 | for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { |
e3966126 AL |
2101 | CpuDefinitionInfoList *entry; |
2102 | CpuDefinitionInfo *info; | |
2103 | ||
7fc9b714 | 2104 | def = &builtin_x86_defs[i]; |
e3966126 AL |
2105 | info = g_malloc0(sizeof(*info)); |
2106 | info->name = g_strdup(def->name); | |
2107 | ||
2108 | entry = g_malloc0(sizeof(*entry)); | |
2109 | entry->value = info; | |
2110 | entry->next = cpu_list; | |
2111 | cpu_list = entry; | |
2112 | } | |
2113 | ||
2114 | return cpu_list; | |
2115 | } | |
2116 | ||
84f1b92f EH |
2117 | static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w, |
2118 | bool migratable_only) | |
27418adf EH |
2119 | { |
2120 | FeatureWordInfo *wi = &feature_word_info[w]; | |
84f1b92f | 2121 | uint32_t r; |
27418adf | 2122 | |
fefb41bf | 2123 | if (kvm_enabled()) { |
84f1b92f EH |
2124 | r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax, |
2125 | wi->cpuid_ecx, | |
2126 | wi->cpuid_reg); | |
fefb41bf | 2127 | } else if (tcg_enabled()) { |
84f1b92f | 2128 | r = wi->tcg_features; |
fefb41bf EH |
2129 | } else { |
2130 | return ~0; | |
2131 | } | |
84f1b92f EH |
2132 | if (migratable_only) { |
2133 | r &= x86_cpu_get_migratable_flags(w); | |
2134 | } | |
2135 | return r; | |
27418adf EH |
2136 | } |
2137 | ||
51f63aed EH |
2138 | /* |
2139 | * Filters CPU feature words based on host availability of each feature. | |
2140 | * | |
51f63aed EH |
2141 | * Returns: 0 if all flags are supported by the host, non-zero otherwise. |
2142 | */ | |
27418adf | 2143 | static int x86_cpu_filter_features(X86CPU *cpu) |
bc74b7db EH |
2144 | { |
2145 | CPUX86State *env = &cpu->env; | |
bd87d2a2 | 2146 | FeatureWord w; |
51f63aed EH |
2147 | int rv = 0; |
2148 | ||
bd87d2a2 | 2149 | for (w = 0; w < FEATURE_WORDS; w++) { |
84f1b92f EH |
2150 | uint32_t host_feat = |
2151 | x86_cpu_get_supported_feature_word(w, cpu->migratable); | |
034acf4a EH |
2152 | uint32_t requested_features = env->features[w]; |
2153 | env->features[w] &= host_feat; | |
2154 | cpu->filtered_features[w] = requested_features & ~env->features[w]; | |
51f63aed EH |
2155 | if (cpu->filtered_features[w]) { |
2156 | if (cpu->check_cpuid || cpu->enforce_cpuid) { | |
8459e396 | 2157 | report_unavailable_features(w, cpu->filtered_features[w]); |
51f63aed EH |
2158 | } |
2159 | rv = 1; | |
2160 | } | |
bd87d2a2 | 2161 | } |
51f63aed EH |
2162 | |
2163 | return rv; | |
bc74b7db | 2164 | } |
bc74b7db | 2165 | |
5114e842 EH |
2166 | static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) |
2167 | { | |
2168 | PropValue *pv; | |
2169 | for (pv = props; pv->prop; pv++) { | |
2170 | if (!pv->value) { | |
2171 | continue; | |
2172 | } | |
2173 | object_property_parse(OBJECT(cpu), pv->value, pv->prop, | |
2174 | &error_abort); | |
2175 | } | |
2176 | } | |
2177 | ||
d940ee9b | 2178 | /* Load data from X86CPUDefinition |
c080e30e | 2179 | */ |
d940ee9b | 2180 | static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp) |
c6dc6f63 | 2181 | { |
61dcd775 | 2182 | CPUX86State *env = &cpu->env; |
74f54bc4 EH |
2183 | const char *vendor; |
2184 | char host_vendor[CPUID_VENDOR_SZ + 1]; | |
e1c224b4 | 2185 | FeatureWord w; |
c6dc6f63 | 2186 | |
c39c0edf EH |
2187 | /* CPU models only set _minimum_ values for level/xlevel: */ |
2188 | object_property_set_int(OBJECT(cpu), def->level, "min-level", errp); | |
2189 | object_property_set_int(OBJECT(cpu), def->xlevel, "min-xlevel", errp); | |
2190 | ||
2d64255b AF |
2191 | object_property_set_int(OBJECT(cpu), def->family, "family", errp); |
2192 | object_property_set_int(OBJECT(cpu), def->model, "model", errp); | |
2193 | object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp); | |
2d64255b | 2194 | object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp); |
e1c224b4 EH |
2195 | for (w = 0; w < FEATURE_WORDS; w++) { |
2196 | env->features[w] = def->features[w]; | |
2197 | } | |
82beb536 | 2198 | |
9576de75 | 2199 | /* Special cases not set in the X86CPUDefinition structs: */ |
82beb536 | 2200 | if (kvm_enabled()) { |
492a4c94 LT |
2201 | if (!kvm_irqchip_in_kernel()) { |
2202 | x86_cpu_change_kvm_default("x2apic", "off"); | |
2203 | } | |
2204 | ||
5114e842 | 2205 | x86_cpu_apply_props(cpu, kvm_default_props); |
82beb536 | 2206 | } |
5fcca9ff | 2207 | |
82beb536 | 2208 | env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; |
7c08db30 EH |
2209 | |
2210 | /* sysenter isn't supported in compatibility mode on AMD, | |
2211 | * syscall isn't supported in compatibility mode on Intel. | |
2212 | * Normally we advertise the actual CPU vendor, but you can | |
2213 | * override this using the 'vendor' property if you want to use | |
2214 | * KVM's sysenter/syscall emulation in compatibility mode and | |
2215 | * when doing cross vendor migration | |
2216 | */ | |
74f54bc4 | 2217 | vendor = def->vendor; |
7c08db30 EH |
2218 | if (kvm_enabled()) { |
2219 | uint32_t ebx = 0, ecx = 0, edx = 0; | |
2220 | host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); | |
2221 | x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx); | |
2222 | vendor = host_vendor; | |
2223 | } | |
2224 | ||
2225 | object_property_set_str(OBJECT(cpu), vendor, "vendor", errp); | |
2226 | ||
c6dc6f63 AP |
2227 | } |
2228 | ||
0856579c | 2229 | X86CPU *cpu_x86_init(const char *cpu_model) |
7f833247 | 2230 | { |
a57d0163 | 2231 | return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model)); |
5c3c6a68 AF |
2232 | } |
2233 | ||
d940ee9b EH |
2234 | static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) |
2235 | { | |
2236 | X86CPUDefinition *cpudef = data; | |
2237 | X86CPUClass *xcc = X86_CPU_CLASS(oc); | |
2238 | ||
2239 | xcc->cpu_def = cpudef; | |
2240 | } | |
2241 | ||
2242 | static void x86_register_cpudef_type(X86CPUDefinition *def) | |
2243 | { | |
2244 | char *typename = x86_cpu_type_name(def->name); | |
2245 | TypeInfo ti = { | |
2246 | .name = typename, | |
2247 | .parent = TYPE_X86_CPU, | |
2248 | .class_init = x86_cpu_cpudef_class_init, | |
2249 | .class_data = def, | |
2250 | }; | |
2251 | ||
2252 | type_register(&ti); | |
2253 | g_free(typename); | |
2254 | } | |
2255 | ||
c6dc6f63 | 2256 | #if !defined(CONFIG_USER_ONLY) |
c6dc6f63 | 2257 | |
0e26b7b8 BS |
2258 | void cpu_clear_apic_feature(CPUX86State *env) |
2259 | { | |
0514ef2f | 2260 | env->features[FEAT_1_EDX] &= ~CPUID_APIC; |
0e26b7b8 BS |
2261 | } |
2262 | ||
c6dc6f63 AP |
2263 | #endif /* !CONFIG_USER_ONLY */ |
2264 | ||
c6dc6f63 AP |
2265 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, |
2266 | uint32_t *eax, uint32_t *ebx, | |
2267 | uint32_t *ecx, uint32_t *edx) | |
2268 | { | |
a60f24b5 AF |
2269 | X86CPU *cpu = x86_env_get_cpu(env); |
2270 | CPUState *cs = CPU(cpu); | |
14c985cf | 2271 | uint32_t pkg_offset; |
a60f24b5 | 2272 | |
c6dc6f63 AP |
2273 | /* test if maximum index reached */ |
2274 | if (index & 0x80000000) { | |
b3baa152 BW |
2275 | if (index > env->cpuid_xlevel) { |
2276 | if (env->cpuid_xlevel2 > 0) { | |
2277 | /* Handle the Centaur's CPUID instruction. */ | |
2278 | if (index > env->cpuid_xlevel2) { | |
2279 | index = env->cpuid_xlevel2; | |
2280 | } else if (index < 0xC0000000) { | |
2281 | index = env->cpuid_xlevel; | |
2282 | } | |
2283 | } else { | |
57f26ae7 EH |
2284 | /* Intel documentation states that invalid EAX input will |
2285 | * return the same information as EAX=cpuid_level | |
2286 | * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) | |
2287 | */ | |
2288 | index = env->cpuid_level; | |
b3baa152 BW |
2289 | } |
2290 | } | |
c6dc6f63 AP |
2291 | } else { |
2292 | if (index > env->cpuid_level) | |
2293 | index = env->cpuid_level; | |
2294 | } | |
2295 | ||
2296 | switch(index) { | |
2297 | case 0: | |
2298 | *eax = env->cpuid_level; | |
5eb2f7a4 EH |
2299 | *ebx = env->cpuid_vendor1; |
2300 | *edx = env->cpuid_vendor2; | |
2301 | *ecx = env->cpuid_vendor3; | |
c6dc6f63 AP |
2302 | break; |
2303 | case 1: | |
2304 | *eax = env->cpuid_version; | |
7e72a45c EH |
2305 | *ebx = (cpu->apic_id << 24) | |
2306 | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ | |
0514ef2f | 2307 | *ecx = env->features[FEAT_1_ECX]; |
19dc85db RH |
2308 | if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { |
2309 | *ecx |= CPUID_EXT_OSXSAVE; | |
2310 | } | |
0514ef2f | 2311 | *edx = env->features[FEAT_1_EDX]; |
ce3960eb AF |
2312 | if (cs->nr_cores * cs->nr_threads > 1) { |
2313 | *ebx |= (cs->nr_cores * cs->nr_threads) << 16; | |
19dc85db | 2314 | *edx |= CPUID_HT; |
c6dc6f63 AP |
2315 | } |
2316 | break; | |
2317 | case 2: | |
2318 | /* cache info: needed for Pentium Pro compatibility */ | |
787aaf57 BC |
2319 | if (cpu->cache_info_passthrough) { |
2320 | host_cpuid(index, 0, eax, ebx, ecx, edx); | |
2321 | break; | |
2322 | } | |
5e891bf8 | 2323 | *eax = 1; /* Number of CPUID[EAX=2] calls required */ |
c6dc6f63 | 2324 | *ebx = 0; |
14c985cf LM |
2325 | if (!cpu->enable_l3_cache) { |
2326 | *ecx = 0; | |
2327 | } else { | |
2328 | *ecx = L3_N_DESCRIPTOR; | |
2329 | } | |
5e891bf8 EH |
2330 | *edx = (L1D_DESCRIPTOR << 16) | \ |
2331 | (L1I_DESCRIPTOR << 8) | \ | |
2332 | (L2_DESCRIPTOR); | |
c6dc6f63 AP |
2333 | break; |
2334 | case 4: | |
2335 | /* cache info: needed for Core compatibility */ | |
787aaf57 BC |
2336 | if (cpu->cache_info_passthrough) { |
2337 | host_cpuid(index, count, eax, ebx, ecx, edx); | |
76c2975a | 2338 | *eax &= ~0xFC000000; |
c6dc6f63 | 2339 | } else { |
2f7a21c4 | 2340 | *eax = 0; |
76c2975a | 2341 | switch (count) { |
c6dc6f63 | 2342 | case 0: /* L1 dcache info */ |
5e891bf8 EH |
2343 | *eax |= CPUID_4_TYPE_DCACHE | \ |
2344 | CPUID_4_LEVEL(1) | \ | |
2345 | CPUID_4_SELF_INIT_LEVEL; | |
2346 | *ebx = (L1D_LINE_SIZE - 1) | \ | |
2347 | ((L1D_PARTITIONS - 1) << 12) | \ | |
2348 | ((L1D_ASSOCIATIVITY - 1) << 22); | |
2349 | *ecx = L1D_SETS - 1; | |
2350 | *edx = CPUID_4_NO_INVD_SHARING; | |
c6dc6f63 AP |
2351 | break; |
2352 | case 1: /* L1 icache info */ | |
5e891bf8 EH |
2353 | *eax |= CPUID_4_TYPE_ICACHE | \ |
2354 | CPUID_4_LEVEL(1) | \ | |
2355 | CPUID_4_SELF_INIT_LEVEL; | |
2356 | *ebx = (L1I_LINE_SIZE - 1) | \ | |
2357 | ((L1I_PARTITIONS - 1) << 12) | \ | |
2358 | ((L1I_ASSOCIATIVITY - 1) << 22); | |
2359 | *ecx = L1I_SETS - 1; | |
2360 | *edx = CPUID_4_NO_INVD_SHARING; | |
c6dc6f63 AP |
2361 | break; |
2362 | case 2: /* L2 cache info */ | |
5e891bf8 EH |
2363 | *eax |= CPUID_4_TYPE_UNIFIED | \ |
2364 | CPUID_4_LEVEL(2) | \ | |
2365 | CPUID_4_SELF_INIT_LEVEL; | |
ce3960eb AF |
2366 | if (cs->nr_threads > 1) { |
2367 | *eax |= (cs->nr_threads - 1) << 14; | |
c6dc6f63 | 2368 | } |
5e891bf8 EH |
2369 | *ebx = (L2_LINE_SIZE - 1) | \ |
2370 | ((L2_PARTITIONS - 1) << 12) | \ | |
2371 | ((L2_ASSOCIATIVITY - 1) << 22); | |
2372 | *ecx = L2_SETS - 1; | |
2373 | *edx = CPUID_4_NO_INVD_SHARING; | |
c6dc6f63 | 2374 | break; |
14c985cf LM |
2375 | case 3: /* L3 cache info */ |
2376 | if (!cpu->enable_l3_cache) { | |
2377 | *eax = 0; | |
2378 | *ebx = 0; | |
2379 | *ecx = 0; | |
2380 | *edx = 0; | |
2381 | break; | |
2382 | } | |
2383 | *eax |= CPUID_4_TYPE_UNIFIED | \ | |
2384 | CPUID_4_LEVEL(3) | \ | |
2385 | CPUID_4_SELF_INIT_LEVEL; | |
2386 | pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads); | |
2387 | *eax |= ((1 << pkg_offset) - 1) << 14; | |
2388 | *ebx = (L3_N_LINE_SIZE - 1) | \ | |
2389 | ((L3_N_PARTITIONS - 1) << 12) | \ | |
2390 | ((L3_N_ASSOCIATIVITY - 1) << 22); | |
2391 | *ecx = L3_N_SETS - 1; | |
2392 | *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX; | |
2393 | break; | |
c6dc6f63 AP |
2394 | default: /* end of info */ |
2395 | *eax = 0; | |
2396 | *ebx = 0; | |
2397 | *ecx = 0; | |
2398 | *edx = 0; | |
2399 | break; | |
76c2975a PB |
2400 | } |
2401 | } | |
2402 | ||
2403 | /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */ | |
2404 | if ((*eax & 31) && cs->nr_cores > 1) { | |
2405 | *eax |= (cs->nr_cores - 1) << 26; | |
c6dc6f63 AP |
2406 | } |
2407 | break; | |
2408 | case 5: | |
2409 | /* mwait info: needed for Core compatibility */ | |
2410 | *eax = 0; /* Smallest monitor-line size in bytes */ | |
2411 | *ebx = 0; /* Largest monitor-line size in bytes */ | |
2412 | *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; | |
2413 | *edx = 0; | |
2414 | break; | |
2415 | case 6: | |
2416 | /* Thermal and Power Leaf */ | |
28b8e4d0 | 2417 | *eax = env->features[FEAT_6_EAX]; |
c6dc6f63 AP |
2418 | *ebx = 0; |
2419 | *ecx = 0; | |
2420 | *edx = 0; | |
2421 | break; | |
f7911686 | 2422 | case 7: |
13526728 EH |
2423 | /* Structured Extended Feature Flags Enumeration Leaf */ |
2424 | if (count == 0) { | |
2425 | *eax = 0; /* Maximum ECX value for sub-leaves */ | |
0514ef2f | 2426 | *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ |
f74eefe0 | 2427 | *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ |
0f70ed47 PB |
2428 | if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { |
2429 | *ecx |= CPUID_7_0_ECX_OSPKE; | |
2430 | } | |
13526728 | 2431 | *edx = 0; /* Reserved */ |
f7911686 YW |
2432 | } else { |
2433 | *eax = 0; | |
2434 | *ebx = 0; | |
2435 | *ecx = 0; | |
2436 | *edx = 0; | |
2437 | } | |
2438 | break; | |
c6dc6f63 AP |
2439 | case 9: |
2440 | /* Direct Cache Access Information Leaf */ | |
2441 | *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ | |
2442 | *ebx = 0; | |
2443 | *ecx = 0; | |
2444 | *edx = 0; | |
2445 | break; | |
2446 | case 0xA: | |
2447 | /* Architectural Performance Monitoring Leaf */ | |
9337e3b6 | 2448 | if (kvm_enabled() && cpu->enable_pmu) { |
a60f24b5 | 2449 | KVMState *s = cs->kvm_state; |
a0fa8208 GN |
2450 | |
2451 | *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX); | |
2452 | *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX); | |
2453 | *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX); | |
2454 | *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX); | |
2455 | } else { | |
2456 | *eax = 0; | |
2457 | *ebx = 0; | |
2458 | *ecx = 0; | |
2459 | *edx = 0; | |
2460 | } | |
c6dc6f63 | 2461 | break; |
5232d00a RK |
2462 | case 0xB: |
2463 | /* Extended Topology Enumeration Leaf */ | |
2464 | if (!cpu->enable_cpuid_0xb) { | |
2465 | *eax = *ebx = *ecx = *edx = 0; | |
2466 | break; | |
2467 | } | |
2468 | ||
2469 | *ecx = count & 0xff; | |
2470 | *edx = cpu->apic_id; | |
2471 | ||
2472 | switch (count) { | |
2473 | case 0: | |
eab60fb9 MAL |
2474 | *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads); |
2475 | *ebx = cs->nr_threads; | |
5232d00a RK |
2476 | *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; |
2477 | break; | |
2478 | case 1: | |
eab60fb9 MAL |
2479 | *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads); |
2480 | *ebx = cs->nr_cores * cs->nr_threads; | |
5232d00a RK |
2481 | *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; |
2482 | break; | |
2483 | default: | |
2484 | *eax = 0; | |
2485 | *ebx = 0; | |
2486 | *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; | |
2487 | } | |
2488 | ||
2489 | assert(!(*eax & ~0x1f)); | |
2490 | *ebx &= 0xffff; /* The count doesn't need to be reliable. */ | |
2491 | break; | |
2560f19f PB |
2492 | case 0xD: { |
2493 | KVMState *s = cs->kvm_state; | |
19dc85db | 2494 | uint64_t ena_mask; |
2560f19f PB |
2495 | int i; |
2496 | ||
51e49430 | 2497 | /* Processor Extended State */ |
2560f19f PB |
2498 | *eax = 0; |
2499 | *ebx = 0; | |
2500 | *ecx = 0; | |
2501 | *edx = 0; | |
19dc85db | 2502 | if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { |
51e49430 SY |
2503 | break; |
2504 | } | |
19dc85db RH |
2505 | if (kvm_enabled()) { |
2506 | ena_mask = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX); | |
2507 | ena_mask <<= 32; | |
2508 | ena_mask |= kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX); | |
2509 | } else { | |
2510 | ena_mask = -1; | |
2511 | } | |
ba9bc59e | 2512 | |
2560f19f PB |
2513 | if (count == 0) { |
2514 | *ecx = 0x240; | |
f4f1110e RH |
2515 | for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { |
2516 | const ExtSaveArea *esa = &x86_ext_save_areas[i]; | |
9646f492 | 2517 | if ((env->features[esa->feature] & esa->bits) |
19dc85db | 2518 | && ((ena_mask >> i) & 1) != 0) { |
2560f19f | 2519 | if (i < 32) { |
19dc85db | 2520 | *eax |= 1u << i; |
2560f19f | 2521 | } else { |
19dc85db | 2522 | *edx |= 1u << (i - 32); |
2560f19f PB |
2523 | } |
2524 | *ecx = MAX(*ecx, esa->offset + esa->size); | |
2525 | } | |
2526 | } | |
cfc3b074 | 2527 | *eax |= ena_mask & (XSTATE_FP_MASK | XSTATE_SSE_MASK); |
2560f19f PB |
2528 | *ebx = *ecx; |
2529 | } else if (count == 1) { | |
0bb0b2d2 | 2530 | *eax = env->features[FEAT_XSAVE]; |
f4f1110e RH |
2531 | } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { |
2532 | const ExtSaveArea *esa = &x86_ext_save_areas[count]; | |
9646f492 | 2533 | if ((env->features[esa->feature] & esa->bits) |
19dc85db | 2534 | && ((ena_mask >> count) & 1) != 0) { |
33f373d7 LJ |
2535 | *eax = esa->size; |
2536 | *ebx = esa->offset; | |
2560f19f | 2537 | } |
51e49430 SY |
2538 | } |
2539 | break; | |
2560f19f | 2540 | } |
c6dc6f63 AP |
2541 | case 0x80000000: |
2542 | *eax = env->cpuid_xlevel; | |
2543 | *ebx = env->cpuid_vendor1; | |
2544 | *edx = env->cpuid_vendor2; | |
2545 | *ecx = env->cpuid_vendor3; | |
2546 | break; | |
2547 | case 0x80000001: | |
2548 | *eax = env->cpuid_version; | |
2549 | *ebx = 0; | |
0514ef2f EH |
2550 | *ecx = env->features[FEAT_8000_0001_ECX]; |
2551 | *edx = env->features[FEAT_8000_0001_EDX]; | |
c6dc6f63 AP |
2552 | |
2553 | /* The Linux kernel checks for the CMPLegacy bit and | |
2554 | * discards multiple thread information if it is set. | |
cb8d4c8f | 2555 | * So don't set it here for Intel to make Linux guests happy. |
c6dc6f63 | 2556 | */ |
ce3960eb | 2557 | if (cs->nr_cores * cs->nr_threads > 1) { |
5eb2f7a4 EH |
2558 | if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || |
2559 | env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || | |
2560 | env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { | |
c6dc6f63 AP |
2561 | *ecx |= 1 << 1; /* CmpLegacy bit */ |
2562 | } | |
2563 | } | |
c6dc6f63 AP |
2564 | break; |
2565 | case 0x80000002: | |
2566 | case 0x80000003: | |
2567 | case 0x80000004: | |
2568 | *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; | |
2569 | *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; | |
2570 | *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; | |
2571 | *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; | |
2572 | break; | |
2573 | case 0x80000005: | |
2574 | /* cache info (L1 cache) */ | |
787aaf57 BC |
2575 | if (cpu->cache_info_passthrough) { |
2576 | host_cpuid(index, 0, eax, ebx, ecx, edx); | |
2577 | break; | |
2578 | } | |
5e891bf8 EH |
2579 | *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \ |
2580 | (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); | |
2581 | *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \ | |
2582 | (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); | |
2583 | *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \ | |
2584 | (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE); | |
2585 | *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \ | |
2586 | (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE); | |
c6dc6f63 AP |
2587 | break; |
2588 | case 0x80000006: | |
2589 | /* cache info (L2 cache) */ | |
787aaf57 BC |
2590 | if (cpu->cache_info_passthrough) { |
2591 | host_cpuid(index, 0, eax, ebx, ecx, edx); | |
2592 | break; | |
2593 | } | |
5e891bf8 EH |
2594 | *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \ |
2595 | (L2_DTLB_2M_ENTRIES << 16) | \ | |
2596 | (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \ | |
2597 | (L2_ITLB_2M_ENTRIES); | |
2598 | *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \ | |
2599 | (L2_DTLB_4K_ENTRIES << 16) | \ | |
2600 | (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \ | |
2601 | (L2_ITLB_4K_ENTRIES); | |
2602 | *ecx = (L2_SIZE_KB_AMD << 16) | \ | |
2603 | (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \ | |
2604 | (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE); | |
14c985cf LM |
2605 | if (!cpu->enable_l3_cache) { |
2606 | *edx = ((L3_SIZE_KB / 512) << 18) | \ | |
2607 | (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \ | |
2608 | (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE); | |
2609 | } else { | |
2610 | *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \ | |
2611 | (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \ | |
2612 | (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE); | |
2613 | } | |
c6dc6f63 | 2614 | break; |
303752a9 MT |
2615 | case 0x80000007: |
2616 | *eax = 0; | |
2617 | *ebx = 0; | |
2618 | *ecx = 0; | |
2619 | *edx = env->features[FEAT_8000_0007_EDX]; | |
2620 | break; | |
c6dc6f63 AP |
2621 | case 0x80000008: |
2622 | /* virtual & phys address size in low 2 bytes. */ | |
0514ef2f | 2623 | if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { |
af45907a DDAG |
2624 | /* 64 bit processor, 48 bits virtual, configurable |
2625 | * physical bits. | |
2626 | */ | |
2627 | *eax = 0x00003000 + cpu->phys_bits; | |
c6dc6f63 | 2628 | } else { |
af45907a | 2629 | *eax = cpu->phys_bits; |
c6dc6f63 AP |
2630 | } |
2631 | *ebx = 0; | |
2632 | *ecx = 0; | |
2633 | *edx = 0; | |
ce3960eb AF |
2634 | if (cs->nr_cores * cs->nr_threads > 1) { |
2635 | *ecx |= (cs->nr_cores * cs->nr_threads) - 1; | |
c6dc6f63 AP |
2636 | } |
2637 | break; | |
2638 | case 0x8000000A: | |
0514ef2f | 2639 | if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { |
9f3fb565 EH |
2640 | *eax = 0x00000001; /* SVM Revision */ |
2641 | *ebx = 0x00000010; /* nr of ASIDs */ | |
2642 | *ecx = 0; | |
0514ef2f | 2643 | *edx = env->features[FEAT_SVM]; /* optional features */ |
9f3fb565 EH |
2644 | } else { |
2645 | *eax = 0; | |
2646 | *ebx = 0; | |
2647 | *ecx = 0; | |
2648 | *edx = 0; | |
2649 | } | |
c6dc6f63 | 2650 | break; |
b3baa152 BW |
2651 | case 0xC0000000: |
2652 | *eax = env->cpuid_xlevel2; | |
2653 | *ebx = 0; | |
2654 | *ecx = 0; | |
2655 | *edx = 0; | |
2656 | break; | |
2657 | case 0xC0000001: | |
2658 | /* Support for VIA CPU's CPUID instruction */ | |
2659 | *eax = env->cpuid_version; | |
2660 | *ebx = 0; | |
2661 | *ecx = 0; | |
0514ef2f | 2662 | *edx = env->features[FEAT_C000_0001_EDX]; |
b3baa152 BW |
2663 | break; |
2664 | case 0xC0000002: | |
2665 | case 0xC0000003: | |
2666 | case 0xC0000004: | |
2667 | /* Reserved for the future, and now filled with zero */ | |
2668 | *eax = 0; | |
2669 | *ebx = 0; | |
2670 | *ecx = 0; | |
2671 | *edx = 0; | |
2672 | break; | |
c6dc6f63 AP |
2673 | default: |
2674 | /* reserved values: zero */ | |
2675 | *eax = 0; | |
2676 | *ebx = 0; | |
2677 | *ecx = 0; | |
2678 | *edx = 0; | |
2679 | break; | |
2680 | } | |
2681 | } | |
5fd2087a AF |
2682 | |
2683 | /* CPUClass::reset() */ | |
2684 | static void x86_cpu_reset(CPUState *s) | |
2685 | { | |
2686 | X86CPU *cpu = X86_CPU(s); | |
2687 | X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); | |
2688 | CPUX86State *env = &cpu->env; | |
a114d25d RH |
2689 | target_ulong cr4; |
2690 | uint64_t xcr0; | |
c1958aea AF |
2691 | int i; |
2692 | ||
5fd2087a AF |
2693 | xcc->parent_reset(s); |
2694 | ||
5e992a8e | 2695 | memset(env, 0, offsetof(CPUX86State, end_reset_fields)); |
c1958aea | 2696 | |
00c8cb0a | 2697 | tlb_flush(s, 1); |
c1958aea AF |
2698 | |
2699 | env->old_exception = -1; | |
2700 | ||
2701 | /* init to reset state */ | |
2702 | ||
c1958aea AF |
2703 | env->hflags2 |= HF2_GIF_MASK; |
2704 | ||
2705 | cpu_x86_update_cr0(env, 0x60000010); | |
2706 | env->a20_mask = ~0x0; | |
2707 | env->smbase = 0x30000; | |
2708 | ||
2709 | env->idt.limit = 0xffff; | |
2710 | env->gdt.limit = 0xffff; | |
2711 | env->ldt.limit = 0xffff; | |
2712 | env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); | |
2713 | env->tr.limit = 0xffff; | |
2714 | env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); | |
2715 | ||
2716 | cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, | |
2717 | DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | | |
2718 | DESC_R_MASK | DESC_A_MASK); | |
2719 | cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, | |
2720 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
2721 | DESC_A_MASK); | |
2722 | cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, | |
2723 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
2724 | DESC_A_MASK); | |
2725 | cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, | |
2726 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
2727 | DESC_A_MASK); | |
2728 | cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, | |
2729 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
2730 | DESC_A_MASK); | |
2731 | cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, | |
2732 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
2733 | DESC_A_MASK); | |
2734 | ||
2735 | env->eip = 0xfff0; | |
2736 | env->regs[R_EDX] = env->cpuid_version; | |
2737 | ||
2738 | env->eflags = 0x2; | |
2739 | ||
2740 | /* FPU init */ | |
2741 | for (i = 0; i < 8; i++) { | |
2742 | env->fptags[i] = 1; | |
2743 | } | |
5bde1407 | 2744 | cpu_set_fpuc(env, 0x37f); |
c1958aea AF |
2745 | |
2746 | env->mxcsr = 0x1f80; | |
a114d25d RH |
2747 | /* All units are in INIT state. */ |
2748 | env->xstate_bv = 0; | |
c1958aea AF |
2749 | |
2750 | env->pat = 0x0007040600070406ULL; | |
2751 | env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; | |
2752 | ||
2753 | memset(env->dr, 0, sizeof(env->dr)); | |
2754 | env->dr[6] = DR6_FIXED_1; | |
2755 | env->dr[7] = DR7_FIXED_1; | |
b3310ab3 | 2756 | cpu_breakpoint_remove_all(s, BP_CPU); |
75a34036 | 2757 | cpu_watchpoint_remove_all(s, BP_CPU); |
dd673288 | 2758 | |
a114d25d | 2759 | cr4 = 0; |
cfc3b074 | 2760 | xcr0 = XSTATE_FP_MASK; |
a114d25d RH |
2761 | |
2762 | #ifdef CONFIG_USER_ONLY | |
2763 | /* Enable all the features for user-mode. */ | |
2764 | if (env->features[FEAT_1_EDX] & CPUID_SSE) { | |
cfc3b074 | 2765 | xcr0 |= XSTATE_SSE_MASK; |
a114d25d | 2766 | } |
0f70ed47 PB |
2767 | for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { |
2768 | const ExtSaveArea *esa = &x86_ext_save_areas[i]; | |
9646f492 | 2769 | if (env->features[esa->feature] & esa->bits) { |
0f70ed47 PB |
2770 | xcr0 |= 1ull << i; |
2771 | } | |
a114d25d | 2772 | } |
0f70ed47 | 2773 | |
a114d25d RH |
2774 | if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { |
2775 | cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; | |
2776 | } | |
07929f2a RH |
2777 | if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { |
2778 | cr4 |= CR4_FSGSBASE_MASK; | |
2779 | } | |
a114d25d RH |
2780 | #endif |
2781 | ||
2782 | env->xcr0 = xcr0; | |
2783 | cpu_x86_update_cr4(env, cr4); | |
0522604b | 2784 | |
9db2efd9 AW |
2785 | /* |
2786 | * SDM 11.11.5 requires: | |
2787 | * - IA32_MTRR_DEF_TYPE MSR.E = 0 | |
2788 | * - IA32_MTRR_PHYSMASKn.V = 0 | |
2789 | * All other bits are undefined. For simplification, zero it all. | |
2790 | */ | |
2791 | env->mtrr_deftype = 0; | |
2792 | memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); | |
2793 | memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); | |
2794 | ||
dd673288 IM |
2795 | #if !defined(CONFIG_USER_ONLY) |
2796 | /* We hard-wire the BSP to the first CPU. */ | |
9cb11fd7 | 2797 | apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); |
dd673288 | 2798 | |
259186a7 | 2799 | s->halted = !cpu_is_bsp(cpu); |
50a2c6e5 PB |
2800 | |
2801 | if (kvm_enabled()) { | |
2802 | kvm_arch_reset_vcpu(cpu); | |
2803 | } | |
dd673288 | 2804 | #endif |
5fd2087a AF |
2805 | } |
2806 | ||
dd673288 IM |
2807 | #ifndef CONFIG_USER_ONLY |
2808 | bool cpu_is_bsp(X86CPU *cpu) | |
2809 | { | |
02e51483 | 2810 | return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP; |
dd673288 | 2811 | } |
65dee380 IM |
2812 | |
2813 | /* TODO: remove me, when reset over QOM tree is implemented */ | |
2814 | static void x86_cpu_machine_reset_cb(void *opaque) | |
2815 | { | |
2816 | X86CPU *cpu = opaque; | |
2817 | cpu_reset(CPU(cpu)); | |
2818 | } | |
dd673288 IM |
2819 | #endif |
2820 | ||
de024815 AF |
2821 | static void mce_init(X86CPU *cpu) |
2822 | { | |
2823 | CPUX86State *cenv = &cpu->env; | |
2824 | unsigned int bank; | |
2825 | ||
2826 | if (((cenv->cpuid_version >> 8) & 0xf) >= 6 | |
0514ef2f | 2827 | && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == |
de024815 | 2828 | (CPUID_MCE | CPUID_MCA)) { |
87f8b626 AR |
2829 | cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | |
2830 | (cpu->enable_lmce ? MCG_LMCE_P : 0); | |
de024815 AF |
2831 | cenv->mcg_ctl = ~(uint64_t)0; |
2832 | for (bank = 0; bank < MCE_BANKS_DEF; bank++) { | |
2833 | cenv->mce_banks[bank * 4] = ~(uint64_t)0; | |
2834 | } | |
2835 | } | |
2836 | } | |
2837 | ||
bdeec802 | 2838 | #ifndef CONFIG_USER_ONLY |
d3c64d6a | 2839 | static void x86_cpu_apic_create(X86CPU *cpu, Error **errp) |
bdeec802 | 2840 | { |
449994eb | 2841 | APICCommonState *apic; |
bdeec802 IM |
2842 | const char *apic_type = "apic"; |
2843 | ||
15eafc2e | 2844 | if (kvm_apic_in_kernel()) { |
bdeec802 IM |
2845 | apic_type = "kvm-apic"; |
2846 | } else if (xen_enabled()) { | |
2847 | apic_type = "xen-apic"; | |
2848 | } | |
2849 | ||
46232aaa | 2850 | cpu->apic_state = DEVICE(object_new(apic_type)); |
bdeec802 | 2851 | |
6816b1b3 IM |
2852 | object_property_add_child(OBJECT(cpu), "lapic", |
2853 | OBJECT(cpu->apic_state), &error_abort); | |
67e55caa | 2854 | object_unref(OBJECT(cpu->apic_state)); |
6816b1b3 | 2855 | |
7e72a45c | 2856 | qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id); |
bdeec802 | 2857 | /* TODO: convert to link<> */ |
02e51483 | 2858 | apic = APIC_COMMON(cpu->apic_state); |
60671e58 | 2859 | apic->cpu = cpu; |
8d42d2d3 | 2860 | apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; |
d3c64d6a IM |
2861 | } |
2862 | ||
2863 | static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) | |
2864 | { | |
8d42d2d3 CF |
2865 | APICCommonState *apic; |
2866 | static bool apic_mmio_map_once; | |
2867 | ||
02e51483 | 2868 | if (cpu->apic_state == NULL) { |
d3c64d6a IM |
2869 | return; |
2870 | } | |
6e8e2651 MA |
2871 | object_property_set_bool(OBJECT(cpu->apic_state), true, "realized", |
2872 | errp); | |
8d42d2d3 CF |
2873 | |
2874 | /* Map APIC MMIO area */ | |
2875 | apic = APIC_COMMON(cpu->apic_state); | |
2876 | if (!apic_mmio_map_once) { | |
2877 | memory_region_add_subregion_overlap(get_system_memory(), | |
2878 | apic->apicbase & | |
2879 | MSR_IA32_APICBASE_BASE, | |
2880 | &apic->io_memory, | |
2881 | 0x1000); | |
2882 | apic_mmio_map_once = true; | |
2883 | } | |
bdeec802 | 2884 | } |
f809c605 PB |
2885 | |
2886 | static void x86_cpu_machine_done(Notifier *n, void *unused) | |
2887 | { | |
2888 | X86CPU *cpu = container_of(n, X86CPU, machine_done); | |
2889 | MemoryRegion *smram = | |
2890 | (MemoryRegion *) object_resolve_path("/machine/smram", NULL); | |
2891 | ||
2892 | if (smram) { | |
2893 | cpu->smram = g_new(MemoryRegion, 1); | |
2894 | memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram", | |
2895 | smram, 0, 1ull << 32); | |
2896 | memory_region_set_enabled(cpu->smram, false); | |
2897 | memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1); | |
2898 | } | |
2899 | } | |
d3c64d6a IM |
2900 | #else |
2901 | static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) | |
2902 | { | |
2903 | } | |
bdeec802 IM |
2904 | #endif |
2905 | ||
11f6fee5 DDAG |
2906 | /* Note: Only safe for use on x86(-64) hosts */ |
2907 | static uint32_t x86_host_phys_bits(void) | |
2908 | { | |
2909 | uint32_t eax; | |
2910 | uint32_t host_phys_bits; | |
2911 | ||
2912 | host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); | |
2913 | if (eax >= 0x80000008) { | |
2914 | host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); | |
2915 | /* Note: According to AMD doc 25481 rev 2.34 they have a field | |
2916 | * at 23:16 that can specify a maximum physical address bits for | |
2917 | * the guest that can override this value; but I've not seen | |
2918 | * anything with that set. | |
2919 | */ | |
2920 | host_phys_bits = eax & 0xff; | |
2921 | } else { | |
2922 | /* It's an odd 64 bit machine that doesn't have the leaf for | |
2923 | * physical address bits; fall back to 36 that's most older | |
2924 | * Intel. | |
2925 | */ | |
2926 | host_phys_bits = 36; | |
2927 | } | |
2928 | ||
2929 | return host_phys_bits; | |
2930 | } | |
e48638fd | 2931 | |
c39c0edf EH |
2932 | static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) |
2933 | { | |
2934 | if (*min < value) { | |
2935 | *min = value; | |
2936 | } | |
2937 | } | |
2938 | ||
2939 | /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ | |
2940 | static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) | |
2941 | { | |
2942 | CPUX86State *env = &cpu->env; | |
2943 | FeatureWordInfo *fi = &feature_word_info[w]; | |
2944 | uint32_t eax = fi->cpuid_eax; | |
2945 | uint32_t region = eax & 0xF0000000; | |
2946 | ||
2947 | if (!env->features[w]) { | |
2948 | return; | |
2949 | } | |
2950 | ||
2951 | switch (region) { | |
2952 | case 0x00000000: | |
2953 | x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); | |
2954 | break; | |
2955 | case 0x80000000: | |
2956 | x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); | |
2957 | break; | |
2958 | case 0xC0000000: | |
2959 | x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); | |
2960 | break; | |
2961 | } | |
2962 | } | |
2963 | ||
e48638fd WH |
2964 | #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ |
2965 | (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ | |
2966 | (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) | |
2967 | #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ | |
2968 | (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ | |
2969 | (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) | |
2b6f294c | 2970 | static void x86_cpu_realizefn(DeviceState *dev, Error **errp) |
7a059953 | 2971 | { |
14a10fc3 | 2972 | CPUState *cs = CPU(dev); |
2b6f294c AF |
2973 | X86CPU *cpu = X86_CPU(dev); |
2974 | X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); | |
b34d12d1 | 2975 | CPUX86State *env = &cpu->env; |
2b6f294c | 2976 | Error *local_err = NULL; |
e48638fd | 2977 | static bool ht_warned; |
dc15c051 | 2978 | FeatureWord w; |
b34d12d1 | 2979 | |
104494ea IM |
2980 | if (xcc->kvm_required && !kvm_enabled()) { |
2981 | char *name = x86_cpu_class_get_model_name(xcc); | |
2982 | error_setg(&local_err, "CPU model '%s' requires KVM", name); | |
2983 | g_free(name); | |
2984 | goto out; | |
2985 | } | |
2986 | ||
d9c84f19 | 2987 | if (cpu->apic_id == UNASSIGNED_APIC_ID) { |
9886e834 EH |
2988 | error_setg(errp, "apic-id property was not initialized properly"); |
2989 | return; | |
2990 | } | |
2991 | ||
dc15c051 IM |
2992 | /*TODO: cpu->host_features incorrectly overwrites features |
2993 | * set using "feat=on|off". Once we fix this, we can convert | |
2994 | * plus_features & minus_features to global properties | |
2995 | * inside x86_cpu_parse_featurestr() too. | |
2996 | */ | |
2997 | if (cpu->host_features) { | |
2998 | for (w = 0; w < FEATURE_WORDS; w++) { | |
2999 | env->features[w] = | |
3000 | x86_cpu_get_supported_feature_word(w, cpu->migratable); | |
3001 | } | |
3002 | } | |
3003 | ||
3004 | for (w = 0; w < FEATURE_WORDS; w++) { | |
3005 | cpu->env.features[w] |= plus_features[w]; | |
3006 | cpu->env.features[w] &= ~minus_features[w]; | |
3007 | } | |
3008 | ||
c39c0edf EH |
3009 | |
3010 | /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ | |
3011 | x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); | |
3012 | if (cpu->full_cpuid_auto_level) { | |
3013 | x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); | |
3014 | x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); | |
3015 | x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); | |
3016 | x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); | |
3017 | x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); | |
3018 | x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); | |
3019 | x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); | |
3020 | x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); | |
3021 | x86_cpu_adjust_feat_level(cpu, FEAT_SVM); | |
3022 | x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); | |
0c3d7c00 EH |
3023 | /* SVM requires CPUID[0x8000000A] */ |
3024 | if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { | |
3025 | x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); | |
3026 | } | |
c39c0edf EH |
3027 | } |
3028 | ||
3029 | /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ | |
3030 | if (env->cpuid_level == UINT32_MAX) { | |
3031 | env->cpuid_level = env->cpuid_min_level; | |
3032 | } | |
3033 | if (env->cpuid_xlevel == UINT32_MAX) { | |
3034 | env->cpuid_xlevel = env->cpuid_min_xlevel; | |
3035 | } | |
3036 | if (env->cpuid_xlevel2 == UINT32_MAX) { | |
3037 | env->cpuid_xlevel2 = env->cpuid_min_xlevel2; | |
b34d12d1 | 3038 | } |
7a059953 | 3039 | |
9997cf7b EH |
3040 | if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) { |
3041 | error_setg(&local_err, | |
3042 | kvm_enabled() ? | |
3043 | "Host doesn't support requested features" : | |
3044 | "TCG doesn't support requested features"); | |
3045 | goto out; | |
3046 | } | |
3047 | ||
9b15cd9e IM |
3048 | /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on |
3049 | * CPUID[1].EDX. | |
3050 | */ | |
e48638fd | 3051 | if (IS_AMD_CPU(env)) { |
0514ef2f EH |
3052 | env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; |
3053 | env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] | |
9b15cd9e IM |
3054 | & CPUID_EXT2_AMD_ALIASES); |
3055 | } | |
3056 | ||
11f6fee5 DDAG |
3057 | /* For 64bit systems think about the number of physical bits to present. |
3058 | * ideally this should be the same as the host; anything other than matching | |
3059 | * the host can cause incorrect guest behaviour. | |
3060 | * QEMU used to pick the magic value of 40 bits that corresponds to | |
3061 | * consumer AMD devices but nothing else. | |
3062 | */ | |
af45907a | 3063 | if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { |
af45907a | 3064 | if (kvm_enabled()) { |
11f6fee5 DDAG |
3065 | uint32_t host_phys_bits = x86_host_phys_bits(); |
3066 | static bool warned; | |
3067 | ||
3068 | if (cpu->host_phys_bits) { | |
3069 | /* The user asked for us to use the host physical bits */ | |
3070 | cpu->phys_bits = host_phys_bits; | |
3071 | } | |
3072 | ||
3073 | /* Print a warning if the user set it to a value that's not the | |
3074 | * host value. | |
3075 | */ | |
3076 | if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 && | |
3077 | !warned) { | |
3078 | error_report("Warning: Host physical bits (%u)" | |
3079 | " does not match phys-bits property (%u)", | |
3080 | host_phys_bits, cpu->phys_bits); | |
3081 | warned = true; | |
3082 | } | |
3083 | ||
3084 | if (cpu->phys_bits && | |
3085 | (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || | |
3086 | cpu->phys_bits < 32)) { | |
af45907a DDAG |
3087 | error_setg(errp, "phys-bits should be between 32 and %u " |
3088 | " (but is %u)", | |
3089 | TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); | |
3090 | return; | |
3091 | } | |
3092 | } else { | |
11f6fee5 | 3093 | if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) { |
af45907a DDAG |
3094 | error_setg(errp, "TCG only supports phys-bits=%u", |
3095 | TCG_PHYS_ADDR_BITS); | |
3096 | return; | |
3097 | } | |
3098 | } | |
11f6fee5 DDAG |
3099 | /* 0 means it was not explicitly set by the user (or by machine |
3100 | * compat_props or by the host code above). In this case, the default | |
3101 | * is the value used by TCG (40). | |
3102 | */ | |
3103 | if (cpu->phys_bits == 0) { | |
3104 | cpu->phys_bits = TCG_PHYS_ADDR_BITS; | |
3105 | } | |
af45907a DDAG |
3106 | } else { |
3107 | /* For 32 bit systems don't use the user set value, but keep | |
3108 | * phys_bits consistent with what we tell the guest. | |
3109 | */ | |
3110 | if (cpu->phys_bits != 0) { | |
3111 | error_setg(errp, "phys-bits is not user-configurable in 32 bit"); | |
3112 | return; | |
3113 | } | |
fefb41bf | 3114 | |
af45907a DDAG |
3115 | if (env->features[FEAT_1_EDX] & CPUID_PSE36) { |
3116 | cpu->phys_bits = 36; | |
3117 | } else { | |
3118 | cpu->phys_bits = 32; | |
3119 | } | |
3120 | } | |
42ecabaa EH |
3121 | cpu_exec_init(cs, &error_abort); |
3122 | ||
57f2453a EH |
3123 | if (tcg_enabled()) { |
3124 | tcg_x86_init(); | |
3125 | } | |
3126 | ||
65dee380 IM |
3127 | #ifndef CONFIG_USER_ONLY |
3128 | qemu_register_reset(x86_cpu_machine_reset_cb, cpu); | |
bdeec802 | 3129 | |
0514ef2f | 3130 | if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) { |
d3c64d6a | 3131 | x86_cpu_apic_create(cpu, &local_err); |
2b6f294c | 3132 | if (local_err != NULL) { |
4dc1f449 | 3133 | goto out; |
bdeec802 IM |
3134 | } |
3135 | } | |
65dee380 IM |
3136 | #endif |
3137 | ||
7a059953 | 3138 | mce_init(cpu); |
2001d0cd PB |
3139 | |
3140 | #ifndef CONFIG_USER_ONLY | |
3141 | if (tcg_enabled()) { | |
56943e8c PM |
3142 | AddressSpace *newas = g_new(AddressSpace, 1); |
3143 | ||
f809c605 | 3144 | cpu->cpu_as_mem = g_new(MemoryRegion, 1); |
2001d0cd | 3145 | cpu->cpu_as_root = g_new(MemoryRegion, 1); |
f809c605 PB |
3146 | |
3147 | /* Outer container... */ | |
3148 | memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull); | |
2001d0cd | 3149 | memory_region_set_enabled(cpu->cpu_as_root, true); |
f809c605 PB |
3150 | |
3151 | /* ... with two regions inside: normal system memory with low | |
3152 | * priority, and... | |
3153 | */ | |
3154 | memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory", | |
3155 | get_system_memory(), 0, ~0ull); | |
3156 | memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0); | |
3157 | memory_region_set_enabled(cpu->cpu_as_mem, true); | |
56943e8c | 3158 | address_space_init(newas, cpu->cpu_as_root, "CPU"); |
12ebc9a7 | 3159 | cs->num_ases = 1; |
56943e8c | 3160 | cpu_address_space_init(cs, newas, 0); |
f809c605 PB |
3161 | |
3162 | /* ... SMRAM with higher priority, linked from /machine/smram. */ | |
3163 | cpu->machine_done.notify = x86_cpu_machine_done; | |
3164 | qemu_add_machine_init_done_notifier(&cpu->machine_done); | |
2001d0cd PB |
3165 | } |
3166 | #endif | |
3167 | ||
14a10fc3 | 3168 | qemu_init_vcpu(cs); |
d3c64d6a | 3169 | |
e48638fd WH |
3170 | /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this |
3171 | * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX | |
3172 | * based on inputs (sockets,cores,threads), it is still better to gives | |
3173 | * users a warning. | |
3174 | * | |
3175 | * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise | |
3176 | * cs->nr_threads hasn't be populated yet and the checking is incorrect. | |
3177 | */ | |
3178 | if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) { | |
3179 | error_report("AMD CPU doesn't support hyperthreading. Please configure" | |
3180 | " -smp options properly."); | |
3181 | ht_warned = true; | |
3182 | } | |
3183 | ||
d3c64d6a IM |
3184 | x86_cpu_apic_realize(cpu, &local_err); |
3185 | if (local_err != NULL) { | |
3186 | goto out; | |
3187 | } | |
14a10fc3 | 3188 | cpu_reset(cs); |
2b6f294c | 3189 | |
4dc1f449 | 3190 | xcc->parent_realize(dev, &local_err); |
2001d0cd | 3191 | |
4dc1f449 IM |
3192 | out: |
3193 | if (local_err != NULL) { | |
3194 | error_propagate(errp, local_err); | |
3195 | return; | |
3196 | } | |
7a059953 AF |
3197 | } |
3198 | ||
c884776e IM |
3199 | static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp) |
3200 | { | |
3201 | X86CPU *cpu = X86_CPU(dev); | |
3202 | ||
3203 | #ifndef CONFIG_USER_ONLY | |
3204 | cpu_remove_sync(CPU(dev)); | |
3205 | qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); | |
3206 | #endif | |
3207 | ||
3208 | if (cpu->apic_state) { | |
3209 | object_unparent(OBJECT(cpu->apic_state)); | |
3210 | cpu->apic_state = NULL; | |
3211 | } | |
3212 | } | |
3213 | ||
38e5c119 EH |
3214 | typedef struct BitProperty { |
3215 | uint32_t *ptr; | |
3216 | uint32_t mask; | |
3217 | } BitProperty; | |
3218 | ||
d7bce999 EB |
3219 | static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, |
3220 | void *opaque, Error **errp) | |
38e5c119 EH |
3221 | { |
3222 | BitProperty *fp = opaque; | |
3223 | bool value = (*fp->ptr & fp->mask) == fp->mask; | |
51e72bc1 | 3224 | visit_type_bool(v, name, &value, errp); |
38e5c119 EH |
3225 | } |
3226 | ||
d7bce999 EB |
3227 | static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, |
3228 | void *opaque, Error **errp) | |
38e5c119 EH |
3229 | { |
3230 | DeviceState *dev = DEVICE(obj); | |
3231 | BitProperty *fp = opaque; | |
3232 | Error *local_err = NULL; | |
3233 | bool value; | |
3234 | ||
3235 | if (dev->realized) { | |
3236 | qdev_prop_set_after_realize(dev, name, errp); | |
3237 | return; | |
3238 | } | |
3239 | ||
51e72bc1 | 3240 | visit_type_bool(v, name, &value, &local_err); |
38e5c119 EH |
3241 | if (local_err) { |
3242 | error_propagate(errp, local_err); | |
3243 | return; | |
3244 | } | |
3245 | ||
3246 | if (value) { | |
3247 | *fp->ptr |= fp->mask; | |
3248 | } else { | |
3249 | *fp->ptr &= ~fp->mask; | |
3250 | } | |
3251 | } | |
3252 | ||
3253 | static void x86_cpu_release_bit_prop(Object *obj, const char *name, | |
3254 | void *opaque) | |
3255 | { | |
3256 | BitProperty *prop = opaque; | |
3257 | g_free(prop); | |
3258 | } | |
3259 | ||
3260 | /* Register a boolean property to get/set a single bit in a uint32_t field. | |
3261 | * | |
3262 | * The same property name can be registered multiple times to make it affect | |
3263 | * multiple bits in the same FeatureWord. In that case, the getter will return | |
3264 | * true only if all bits are set. | |
3265 | */ | |
3266 | static void x86_cpu_register_bit_prop(X86CPU *cpu, | |
3267 | const char *prop_name, | |
3268 | uint32_t *field, | |
3269 | int bitnr) | |
3270 | { | |
3271 | BitProperty *fp; | |
3272 | ObjectProperty *op; | |
3273 | uint32_t mask = (1UL << bitnr); | |
3274 | ||
3275 | op = object_property_find(OBJECT(cpu), prop_name, NULL); | |
3276 | if (op) { | |
3277 | fp = op->opaque; | |
3278 | assert(fp->ptr == field); | |
3279 | fp->mask |= mask; | |
3280 | } else { | |
3281 | fp = g_new0(BitProperty, 1); | |
3282 | fp->ptr = field; | |
3283 | fp->mask = mask; | |
3284 | object_property_add(OBJECT(cpu), prop_name, "bool", | |
3285 | x86_cpu_get_bit_prop, | |
3286 | x86_cpu_set_bit_prop, | |
3287 | x86_cpu_release_bit_prop, fp, &error_abort); | |
3288 | } | |
3289 | } | |
3290 | ||
3291 | static void x86_cpu_register_feature_bit_props(X86CPU *cpu, | |
3292 | FeatureWord w, | |
3293 | int bitnr) | |
3294 | { | |
3295 | Object *obj = OBJECT(cpu); | |
3296 | int i; | |
3297 | char **names; | |
3298 | FeatureWordInfo *fi = &feature_word_info[w]; | |
3299 | ||
38e5c119 EH |
3300 | if (!fi->feat_names[bitnr]) { |
3301 | return; | |
3302 | } | |
3303 | ||
3304 | names = g_strsplit(fi->feat_names[bitnr], "|", 0); | |
3305 | ||
3306 | feat2prop(names[0]); | |
3307 | x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr); | |
3308 | ||
3309 | for (i = 1; names[i]; i++) { | |
3310 | feat2prop(names[i]); | |
d461a44c | 3311 | object_property_add_alias(obj, names[i], obj, names[0], |
38e5c119 EH |
3312 | &error_abort); |
3313 | } | |
3314 | ||
3315 | g_strfreev(names); | |
3316 | } | |
3317 | ||
de024815 AF |
3318 | static void x86_cpu_initfn(Object *obj) |
3319 | { | |
55e5c285 | 3320 | CPUState *cs = CPU(obj); |
de024815 | 3321 | X86CPU *cpu = X86_CPU(obj); |
d940ee9b | 3322 | X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); |
de024815 | 3323 | CPUX86State *env = &cpu->env; |
38e5c119 | 3324 | FeatureWord w; |
de024815 | 3325 | |
c05efcb1 | 3326 | cs->env_ptr = env; |
71ad61d3 AF |
3327 | |
3328 | object_property_add(obj, "family", "int", | |
95b8519d | 3329 | x86_cpuid_version_get_family, |
71ad61d3 | 3330 | x86_cpuid_version_set_family, NULL, NULL, NULL); |
c5291a4f | 3331 | object_property_add(obj, "model", "int", |
67e30c83 | 3332 | x86_cpuid_version_get_model, |
c5291a4f | 3333 | x86_cpuid_version_set_model, NULL, NULL, NULL); |
036e2222 | 3334 | object_property_add(obj, "stepping", "int", |
35112e41 | 3335 | x86_cpuid_version_get_stepping, |
036e2222 | 3336 | x86_cpuid_version_set_stepping, NULL, NULL, NULL); |
d480e1af AF |
3337 | object_property_add_str(obj, "vendor", |
3338 | x86_cpuid_get_vendor, | |
3339 | x86_cpuid_set_vendor, NULL); | |
938d4c25 | 3340 | object_property_add_str(obj, "model-id", |
63e886eb | 3341 | x86_cpuid_get_model_id, |
938d4c25 | 3342 | x86_cpuid_set_model_id, NULL); |
89e48965 AF |
3343 | object_property_add(obj, "tsc-frequency", "int", |
3344 | x86_cpuid_get_tsc_freq, | |
3345 | x86_cpuid_set_tsc_freq, NULL, NULL, NULL); | |
8e8aba50 EH |
3346 | object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", |
3347 | x86_cpu_get_feature_words, | |
7e5292b5 EH |
3348 | NULL, NULL, (void *)env->features, NULL); |
3349 | object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", | |
3350 | x86_cpu_get_feature_words, | |
3351 | NULL, NULL, (void *)cpu->filtered_features, NULL); | |
71ad61d3 | 3352 | |
92067bf4 | 3353 | cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY; |
d65e9815 | 3354 | |
38e5c119 EH |
3355 | for (w = 0; w < FEATURE_WORDS; w++) { |
3356 | int bitnr; | |
3357 | ||
3358 | for (bitnr = 0; bitnr < 32; bitnr++) { | |
3359 | x86_cpu_register_feature_bit_props(cpu, w, bitnr); | |
3360 | } | |
3361 | } | |
3362 | ||
d940ee9b | 3363 | x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort); |
de024815 AF |
3364 | } |
3365 | ||
997395d3 IM |
3366 | static int64_t x86_cpu_get_arch_id(CPUState *cs) |
3367 | { | |
3368 | X86CPU *cpu = X86_CPU(cs); | |
997395d3 | 3369 | |
7e72a45c | 3370 | return cpu->apic_id; |
997395d3 IM |
3371 | } |
3372 | ||
444d5590 AF |
3373 | static bool x86_cpu_get_paging_enabled(const CPUState *cs) |
3374 | { | |
3375 | X86CPU *cpu = X86_CPU(cs); | |
3376 | ||
3377 | return cpu->env.cr[0] & CR0_PG_MASK; | |
3378 | } | |
3379 | ||
f45748f1 AF |
3380 | static void x86_cpu_set_pc(CPUState *cs, vaddr value) |
3381 | { | |
3382 | X86CPU *cpu = X86_CPU(cs); | |
3383 | ||
3384 | cpu->env.eip = value; | |
3385 | } | |
3386 | ||
bdf7ae5b AF |
3387 | static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) |
3388 | { | |
3389 | X86CPU *cpu = X86_CPU(cs); | |
3390 | ||
3391 | cpu->env.eip = tb->pc - tb->cs_base; | |
3392 | } | |
3393 | ||
8c2e1b00 AF |
3394 | static bool x86_cpu_has_work(CPUState *cs) |
3395 | { | |
3396 | X86CPU *cpu = X86_CPU(cs); | |
3397 | CPUX86State *env = &cpu->env; | |
3398 | ||
6220e900 PD |
3399 | return ((cs->interrupt_request & (CPU_INTERRUPT_HARD | |
3400 | CPU_INTERRUPT_POLL)) && | |
8c2e1b00 AF |
3401 | (env->eflags & IF_MASK)) || |
3402 | (cs->interrupt_request & (CPU_INTERRUPT_NMI | | |
3403 | CPU_INTERRUPT_INIT | | |
3404 | CPU_INTERRUPT_SIPI | | |
a9bad65d PB |
3405 | CPU_INTERRUPT_MCE)) || |
3406 | ((cs->interrupt_request & CPU_INTERRUPT_SMI) && | |
3407 | !(env->hflags & HF_SMM_MASK)); | |
8c2e1b00 AF |
3408 | } |
3409 | ||
9337e3b6 | 3410 | static Property x86_cpu_properties[] = { |
2da00e31 IM |
3411 | #ifdef CONFIG_USER_ONLY |
3412 | /* apic_id = 0 by default for *-user, see commit 9886e834 */ | |
3413 | DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), | |
d89c2b8b IM |
3414 | DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), |
3415 | DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), | |
3416 | DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), | |
2da00e31 IM |
3417 | #else |
3418 | DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), | |
d89c2b8b IM |
3419 | DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), |
3420 | DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), | |
3421 | DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), | |
2da00e31 | 3422 | #endif |
9337e3b6 | 3423 | DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), |
c8f0f88e | 3424 | { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks }, |
89314504 | 3425 | DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false), |
0f46685d | 3426 | DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false), |
48a5f3bc | 3427 | DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false), |
f2a53c9e | 3428 | DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false), |
744b8a94 | 3429 | DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false), |
8c145d7c | 3430 | DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false), |
46eb8f98 | 3431 | DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false), |
866eea9a | 3432 | DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false), |
ff99aa64 | 3433 | DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false), |
15e41345 | 3434 | DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), |
912ffc47 | 3435 | DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), |
f522d2ac | 3436 | DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), |
af45907a | 3437 | DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), |
11f6fee5 | 3438 | DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), |
fcc35e7c | 3439 | DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), |
c39c0edf EH |
3440 | DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), |
3441 | DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), | |
3442 | DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), | |
3443 | DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), | |
3444 | DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), | |
3445 | DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), | |
3446 | DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), | |
1c4a55db | 3447 | DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), |
5232d00a | 3448 | DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), |
87f8b626 | 3449 | DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), |
14c985cf | 3450 | DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), |
9337e3b6 EH |
3451 | DEFINE_PROP_END_OF_LIST() |
3452 | }; | |
3453 | ||
5fd2087a AF |
3454 | static void x86_cpu_common_class_init(ObjectClass *oc, void *data) |
3455 | { | |
3456 | X86CPUClass *xcc = X86_CPU_CLASS(oc); | |
3457 | CPUClass *cc = CPU_CLASS(oc); | |
2b6f294c AF |
3458 | DeviceClass *dc = DEVICE_CLASS(oc); |
3459 | ||
3460 | xcc->parent_realize = dc->realize; | |
3461 | dc->realize = x86_cpu_realizefn; | |
c884776e | 3462 | dc->unrealize = x86_cpu_unrealizefn; |
9337e3b6 | 3463 | dc->props = x86_cpu_properties; |
5fd2087a AF |
3464 | |
3465 | xcc->parent_reset = cc->reset; | |
3466 | cc->reset = x86_cpu_reset; | |
91b1df8c | 3467 | cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; |
f56e3a14 | 3468 | |
500050d1 | 3469 | cc->class_by_name = x86_cpu_class_by_name; |
94a444b2 | 3470 | cc->parse_features = x86_cpu_parse_featurestr; |
8c2e1b00 | 3471 | cc->has_work = x86_cpu_has_work; |
97a8ea5a | 3472 | cc->do_interrupt = x86_cpu_do_interrupt; |
42f53fea | 3473 | cc->cpu_exec_interrupt = x86_cpu_exec_interrupt; |
878096ee | 3474 | cc->dump_state = x86_cpu_dump_state; |
f45748f1 | 3475 | cc->set_pc = x86_cpu_set_pc; |
bdf7ae5b | 3476 | cc->synchronize_from_tb = x86_cpu_synchronize_from_tb; |
5b50e790 AF |
3477 | cc->gdb_read_register = x86_cpu_gdb_read_register; |
3478 | cc->gdb_write_register = x86_cpu_gdb_write_register; | |
444d5590 AF |
3479 | cc->get_arch_id = x86_cpu_get_arch_id; |
3480 | cc->get_paging_enabled = x86_cpu_get_paging_enabled; | |
7510454e AF |
3481 | #ifdef CONFIG_USER_ONLY |
3482 | cc->handle_mmu_fault = x86_cpu_handle_mmu_fault; | |
3483 | #else | |
a23bbfda | 3484 | cc->get_memory_mapping = x86_cpu_get_memory_mapping; |
00b941e5 | 3485 | cc->get_phys_page_debug = x86_cpu_get_phys_page_debug; |
c72bf468 JF |
3486 | cc->write_elf64_note = x86_cpu_write_elf64_note; |
3487 | cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote; | |
3488 | cc->write_elf32_note = x86_cpu_write_elf32_note; | |
3489 | cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote; | |
00b941e5 | 3490 | cc->vmsd = &vmstate_x86_cpu; |
c72bf468 | 3491 | #endif |
a0e372f0 | 3492 | cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25; |
86025ee4 PM |
3493 | #ifndef CONFIG_USER_ONLY |
3494 | cc->debug_excp_handler = breakpoint_handler; | |
3495 | #endif | |
374e0cd4 RH |
3496 | cc->cpu_exec_enter = x86_cpu_exec_enter; |
3497 | cc->cpu_exec_exit = x86_cpu_exec_exit; | |
4c315c27 | 3498 | |
edd12111 | 3499 | dc->cannot_instantiate_with_device_add_yet = false; |
4c315c27 MA |
3500 | /* |
3501 | * Reason: x86_cpu_initfn() calls cpu_exec_init(), which saves the | |
3502 | * object in cpus -> dangling pointer after final object_unref(). | |
3503 | */ | |
3504 | dc->cannot_destroy_with_object_finalize_yet = true; | |
5fd2087a AF |
3505 | } |
3506 | ||
3507 | static const TypeInfo x86_cpu_type_info = { | |
3508 | .name = TYPE_X86_CPU, | |
3509 | .parent = TYPE_CPU, | |
3510 | .instance_size = sizeof(X86CPU), | |
de024815 | 3511 | .instance_init = x86_cpu_initfn, |
d940ee9b | 3512 | .abstract = true, |
5fd2087a AF |
3513 | .class_size = sizeof(X86CPUClass), |
3514 | .class_init = x86_cpu_common_class_init, | |
3515 | }; | |
3516 | ||
3517 | static void x86_cpu_register_types(void) | |
3518 | { | |
d940ee9b EH |
3519 | int i; |
3520 | ||
5fd2087a | 3521 | type_register_static(&x86_cpu_type_info); |
d940ee9b EH |
3522 | for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { |
3523 | x86_register_cpudef_type(&builtin_x86_defs[i]); | |
3524 | } | |
3525 | #ifdef CONFIG_KVM | |
3526 | type_register_static(&host_x86_cpu_type_info); | |
3527 | #endif | |
5fd2087a AF |
3528 | } |
3529 | ||
3530 | type_init(x86_cpu_register_types) |