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Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20160927' into staging
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
b834b508 38#if defined(CONFIG_KVM)
ef8621b1 39#include <linux/kvm_para.h>
b834b508 40#endif
65dee380 41
9c17d615 42#include "sysemu/sysemu.h"
53a89e26 43#include "hw/qdev-properties.h"
5232d00a 44#include "hw/i386/topology.h"
bdeec802 45#ifndef CONFIG_USER_ONLY
2001d0cd 46#include "exec/address-spaces.h"
741da0d3 47#include "hw/hw.h"
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
14c985cf 60#define CPUID_2_L3_16MB_16WAY_64B 0x4d
5e891bf8
EH		 61
62
63/* CPUID Leaf 4 constants: */
64
65/* EAX: */
66#define CPUID_4_TYPE_DCACHE 1
67#define CPUID_4_TYPE_ICACHE 2
68#define CPUID_4_TYPE_UNIFIED 3
69
70#define CPUID_4_LEVEL(l) ((l) << 5)
71
72#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73#define CPUID_4_FULLY_ASSOC (1 << 9)
74
75/* EDX: */
76#define CPUID_4_NO_INVD_SHARING (1 << 0)
77#define CPUID_4_INCLUSIVE (1 << 1)
78#define CPUID_4_COMPLEX_IDX (1 << 2)
79
80#define ASSOC_FULL 0xFF
81
82/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
84 a == 2 ? 0x2 : \
85 a == 4 ? 0x4 : \
86 a == 8 ? 0x6 : \
87 a == 16 ? 0x8 : \
88 a == 32 ? 0xA : \
89 a == 48 ? 0xB : \
90 a == 64 ? 0xC : \
91 a == 96 ? 0xD : \
92 a == 128 ? 0xE : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
95
96
97/* Definitions of the hardcoded cache entries we expose: */
98
99/* L1 data cache: */
100#define L1D_LINE_SIZE 64
101#define L1D_ASSOCIATIVITY 8
102#define L1D_SETS 64
103#define L1D_PARTITIONS 1
104/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107#define L1D_LINES_PER_TAG 1
108#define L1D_SIZE_KB_AMD 64
109#define L1D_ASSOCIATIVITY_AMD 2
110
111/* L1 instruction cache: */
112#define L1I_LINE_SIZE 64
113#define L1I_ASSOCIATIVITY 8
114#define L1I_SETS 64
115#define L1I_PARTITIONS 1
116/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119#define L1I_LINES_PER_TAG 1
120#define L1I_SIZE_KB_AMD 64
121#define L1I_ASSOCIATIVITY_AMD 2
122
123/* Level 2 unified cache: */
124#define L2_LINE_SIZE 64
125#define L2_ASSOCIATIVITY 16
126#define L2_SETS 4096
127#define L2_PARTITIONS 1
128/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132#define L2_LINES_PER_TAG 1
133#define L2_SIZE_KB_AMD 512
134
14c985cf 135/* Level 3 unified cache: */
5e891bf8
EH		 136#define L3_SIZE_KB 0 /* disabled */
137#define L3_ASSOCIATIVITY 0 /* disabled */
138#define L3_LINES_PER_TAG 0 /* disabled */
139#define L3_LINE_SIZE 0 /* disabled */
14c985cf
LM		 140#define L3_N_LINE_SIZE 64
141#define L3_N_ASSOCIATIVITY 16
142#define L3_N_SETS 16384
143#define L3_N_PARTITIONS 1
144#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
145#define L3_N_LINES_PER_TAG 1
146#define L3_N_SIZE_KB_AMD 16384
5e891bf8
EH		 147
148/* TLB definitions: */
149
150#define L1_DTLB_2M_ASSOC 1
151#define L1_DTLB_2M_ENTRIES 255
152#define L1_DTLB_4K_ASSOC 1
153#define L1_DTLB_4K_ENTRIES 255
154
155#define L1_ITLB_2M_ASSOC 1
156#define L1_ITLB_2M_ENTRIES 255
157#define L1_ITLB_4K_ASSOC 1
158#define L1_ITLB_4K_ENTRIES 255
159
160#define L2_DTLB_2M_ASSOC 0 /* disabled */
161#define L2_DTLB_2M_ENTRIES 0 /* disabled */
162#define L2_DTLB_4K_ASSOC 4
163#define L2_DTLB_4K_ENTRIES 512
164
165#define L2_ITLB_2M_ASSOC 0 /* disabled */
166#define L2_ITLB_2M_ENTRIES 0 /* disabled */
167#define L2_ITLB_4K_ASSOC 4
168#define L2_ITLB_4K_ENTRIES 512
169
170
171
99b88a17
IM		 172static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
173 uint32_t vendor2, uint32_t vendor3)
174{
175 int i;
176 for (i = 0; i < 4; i++) {
177 dst[i] = vendor1 >> (8 * i);
178 dst[i + 4] = vendor2 >> (8 * i);
179 dst[i + 8] = vendor3 >> (8 * i);
180 }
181 dst[CPUID_VENDOR_SZ] = '\0';
182}
183
621626ce
EH		 184#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
185#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
186 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
187#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
188 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
189 CPUID_PSE36 | CPUID_FXSR)
190#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
191#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
192 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
193 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
194 CPUID_PAE | CPUID_SEP | CPUID_APIC)
195
196#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
197 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
198 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
199 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 200 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 201 /* partly implemented:
202 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
203 /* missing:
204 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
205#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
206 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
207 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 208 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 209 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
210 /* missing:
211 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
212 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
213 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 214 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
215 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 216
217#ifdef TARGET_X86_64
218#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
219#else
220#define TCG_EXT2_X86_64_FEATURES 0
221#endif
222
223#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
224 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
225 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
226 TCG_EXT2_X86_64_FEATURES)
227#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
228 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
229#define TCG_EXT4_FEATURES 0
230#define TCG_SVM_FEATURES 0
231#define TCG_KVM_FEATURES 0
232#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 233 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
234 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 235 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
236 CPUID_7_0_EBX_ERMS)
621626ce 237 /* missing:
07929f2a 238 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 239 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 240 CPUID_7_0_EBX_RDSEED */
0f70ed47 241#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
303752a9 242#define TCG_APM_FEATURES 0
28b8e4d0 243#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 244#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
245 /* missing:
246 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 247
5ef57876 248typedef struct FeatureWordInfo {
2d5312da
EH		 249 /* feature flags names are taken from "Intel Processor Identification and
250 * the CPUID Instruction" and AMD's "CPUID Specification".
251 * In cases of disagreement between feature naming conventions,
252 * aliases may be added.
253 */
254 const char *feat_names[32];
04d104b6
EH		 255 uint32_t cpuid_eax; /* Input EAX for CPUID */
256 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
257 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
258 int cpuid_reg; /* output register (R_* constant) */
37ce3522 259 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 260 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 261} FeatureWordInfo;
262
263static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 264 [FEAT_1_EDX] = {
2d5312da
EH		 265 .feat_names = {
266 "fpu", "vme", "de", "pse",
267 "tsc", "msr", "pae", "mce",
268 "cx8", "apic", NULL, "sep",
269 "mtrr", "pge", "mca", "cmov",
270 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
271 NULL, "ds" /* Intel dts */, "acpi", "mmx",
272 "fxsr", "sse", "sse2", "ss",
273 "ht" /* Intel htt */, "tm", "ia64", "pbe",
274 },
bffd67b0 275 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 276 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 277 },
278 [FEAT_1_ECX] = {
2d5312da
EH		 279 .feat_names = {
280 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
281 "ds_cpl", "vmx", "smx", "est",
282 "tm2", "ssse3", "cid", NULL,
283 "fma", "cx16", "xtpr", "pdcm",
284 NULL, "pcid", "dca", "sse4.1|sse4_1",
285 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
286 "tsc-deadline", "aes", "xsave", "osxsave",
287 "avx", "f16c", "rdrand", "hypervisor",
288 },
bffd67b0 289 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 290 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 291 },
2d5312da
EH		 292 /* Feature names that are already defined on feature_name[] but
293 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
294 * names on feat_names below. They are copied automatically
295 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
296 */
bffd67b0 297 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 298 .feat_names = {
299 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
300 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
301 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
302 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
303 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
304 "nx|xd", NULL, "mmxext", NULL /* mmx */,
305 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb", "rdtscp",
306 NULL, "lm|i64", "3dnowext", "3dnow",
307 },
bffd67b0 308 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 309 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 310 },
311 [FEAT_8000_0001_ECX] = {
2d5312da
EH		 312 .feat_names = {
313 "lahf_lm", "cmp_legacy", "svm", "extapic",
314 "cr8legacy", "abm", "sse4a", "misalignsse",
315 "3dnowprefetch", "osvw", "ibs", "xop",
316 "skinit", "wdt", NULL, "lwp",
317 "fma4", "tce", NULL, "nodeid_msr",
318 NULL, "tbm", "topoext", "perfctr_core",
319 "perfctr_nb", NULL, NULL, NULL,
320 NULL, NULL, NULL, NULL,
321 },
bffd67b0 322 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 323 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 324 },
89e49c8b 325 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 326 .feat_names = {
327 NULL, NULL, "xstore", "xstore-en",
328 NULL, NULL, "xcrypt", "xcrypt-en",
329 "ace2", "ace2-en", "phe", "phe-en",
330 "pmm", "pmm-en", NULL, NULL,
331 NULL, NULL, NULL, NULL,
332 NULL, NULL, NULL, NULL,
333 NULL, NULL, NULL, NULL,
334 NULL, NULL, NULL, NULL,
335 },
89e49c8b 336 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 337 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 338 },
bffd67b0 339 [FEAT_KVM] = {
2d5312da
EH		 340 .feat_names = {
341 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
342 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
343 NULL, NULL, NULL, NULL,
344 NULL, NULL, NULL, NULL,
345 NULL, NULL, NULL, NULL,
346 NULL, NULL, NULL, NULL,
347 "kvmclock-stable-bit", NULL, NULL, NULL,
348 NULL, NULL, NULL, NULL,
349 },
bffd67b0 350 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 351 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 352 },
c35bd19a 353 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 354 .feat_names = {
355 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
356 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
357 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
358 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
359 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
360 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
361 NULL, NULL, NULL, NULL,
362 NULL, NULL, NULL, NULL,
363 NULL, NULL, NULL, NULL,
364 NULL, NULL, NULL, NULL,
365 NULL, NULL, NULL, NULL,
366 },
c35bd19a
EY		 367 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
368 },
369 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 370 .feat_names = {
371 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
372 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
373 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
374 NULL /* hv_create_port */, NULL /* hv_connect_port */,
375 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
376 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
377 NULL, NULL,
378 NULL, NULL, NULL, NULL,
379 NULL, NULL, NULL, NULL,
380 NULL, NULL, NULL, NULL,
381 NULL, NULL, NULL, NULL,
382 },
c35bd19a
EY		 383 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
384 },
385 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 386 .feat_names = {
387 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
388 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
389 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
390 NULL, NULL,
391 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
392 NULL, NULL, NULL, NULL,
393 NULL, NULL, NULL, NULL,
394 NULL, NULL, NULL, NULL,
395 NULL, NULL, NULL, NULL,
396 NULL, NULL, NULL, NULL,
397 },
c35bd19a
EY		 398 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
399 },
bffd67b0 400 [FEAT_SVM] = {
2d5312da
EH		 401 .feat_names = {
402 "npt", "lbrv", "svm_lock", "nrip_save",
403 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
404 NULL, NULL, "pause_filter", NULL,
405 "pfthreshold", NULL, NULL, NULL,
406 NULL, NULL, NULL, NULL,
407 NULL, NULL, NULL, NULL,
408 NULL, NULL, NULL, NULL,
409 NULL, NULL, NULL, NULL,
410 },
bffd67b0 411 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 412 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 413 },
414 [FEAT_7_0_EBX] = {
2d5312da
EH		 415 .feat_names = {
416 "fsgsbase", "tsc_adjust", NULL, "bmi1",
417 "hle", "avx2", NULL, "smep",
418 "bmi2", "erms", "invpcid", "rtm",
419 NULL, NULL, "mpx", NULL,
420 "avx512f", "avx512dq", "rdseed", "adx",
421 "smap", "avx512ifma", "pcommit", "clflushopt",
422 "clwb", NULL, "avx512pf", "avx512er",
423 "avx512cd", NULL, "avx512bw", "avx512vl",
424 },
04d104b6
EH		 425 .cpuid_eax = 7,
426 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
427 .cpuid_reg = R_EBX,
37ce3522 428 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 429 },
f74eefe0 430 [FEAT_7_0_ECX] = {
2d5312da
EH		 431 .feat_names = {
432 NULL, "avx512vbmi", "umip", "pku",
433 "ospke", NULL, NULL, NULL,
434 NULL, NULL, NULL, NULL,
435 NULL, NULL, NULL, NULL,
436 NULL, NULL, NULL, NULL,
437 NULL, NULL, "rdpid", NULL,
438 NULL, NULL, NULL, NULL,
439 NULL, NULL, NULL, NULL,
440 },
f74eefe0
HH		 441 .cpuid_eax = 7,
442 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
443 .cpuid_reg = R_ECX,
444 .tcg_features = TCG_7_0_ECX_FEATURES,
445 },
303752a9 446 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 447 .feat_names = {
448 NULL, NULL, NULL, NULL,
449 NULL, NULL, NULL, NULL,
450 "invtsc", NULL, NULL, NULL,
451 NULL, NULL, NULL, NULL,
452 NULL, NULL, NULL, NULL,
453 NULL, NULL, NULL, NULL,
454 NULL, NULL, NULL, NULL,
455 NULL, NULL, NULL, NULL,
456 },
303752a9
MT		 457 .cpuid_eax = 0x80000007,
458 .cpuid_reg = R_EDX,
459 .tcg_features = TCG_APM_FEATURES,
460 .unmigratable_flags = CPUID_APM_INVTSC,
461 },
0bb0b2d2 462 [FEAT_XSAVE] = {
2d5312da
EH		 463 .feat_names = {
464 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
465 NULL, NULL, NULL, NULL,
466 NULL, NULL, NULL, NULL,
467 NULL, NULL, NULL, NULL,
468 NULL, NULL, NULL, NULL,
469 NULL, NULL, NULL, NULL,
470 NULL, NULL, NULL, NULL,
471 NULL, NULL, NULL, NULL,
472 },
0bb0b2d2
PB		 473 .cpuid_eax = 0xd,
474 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
475 .cpuid_reg = R_EAX,
c9cfe8f9 476 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 477 },
28b8e4d0 478 [FEAT_6_EAX] = {
2d5312da
EH		 479 .feat_names = {
480 NULL, NULL, "arat", NULL,
481 NULL, NULL, NULL, NULL,
482 NULL, NULL, NULL, NULL,
483 NULL, NULL, NULL, NULL,
484 NULL, NULL, NULL, NULL,
485 NULL, NULL, NULL, NULL,
486 NULL, NULL, NULL, NULL,
487 NULL, NULL, NULL, NULL,
488 },
28b8e4d0
JK		 489 .cpuid_eax = 6, .cpuid_reg = R_EAX,
490 .tcg_features = TCG_6_EAX_FEATURES,
491 },
96193c22
EH		 492 [FEAT_XSAVE_COMP_LO] = {
493 .cpuid_eax = 0xD,
494 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
495 .cpuid_reg = R_EAX,
496 .tcg_features = ~0U,
497 },
498 [FEAT_XSAVE_COMP_HI] = {
499 .cpuid_eax = 0xD,
500 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
501 .cpuid_reg = R_EDX,
502 .tcg_features = ~0U,
503 },
5ef57876
EH		 504};
505
8e8aba50
EH		 506typedef struct X86RegisterInfo32 {
507 /* Name of register */
508 const char *name;
509 /* QAPI enum value register */
510 X86CPURegister32 qapi_enum;
511} X86RegisterInfo32;
512
513#define REGISTER(reg) \
5d371f41 514 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 515static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 516 REGISTER(EAX),
517 REGISTER(ECX),
518 REGISTER(EDX),
519 REGISTER(EBX),
520 REGISTER(ESP),
521 REGISTER(EBP),
522 REGISTER(ESI),
523 REGISTER(EDI),
524};
525#undef REGISTER
526
3f32bd21
RH		 527typedef struct ExtSaveArea {
528 uint32_t feature, bits;
529 uint32_t offset, size;
530} ExtSaveArea;
531
532static const ExtSaveArea x86_ext_save_areas[] = {
cfc3b074
PB		 533 [XSTATE_YMM_BIT] =
534 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 535 .offset = offsetof(X86XSaveArea, avx_state),
536 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 537 [XSTATE_BNDREGS_BIT] =
538 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 539 .offset = offsetof(X86XSaveArea, bndreg_state),
540 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 541 [XSTATE_BNDCSR_BIT] =
542 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 543 .offset = offsetof(X86XSaveArea, bndcsr_state),
544 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 545 [XSTATE_OPMASK_BIT] =
546 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 547 .offset = offsetof(X86XSaveArea, opmask_state),
548 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 549 [XSTATE_ZMM_Hi256_BIT] =
550 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 551 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
552 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 553 [XSTATE_Hi16_ZMM_BIT] =
554 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 555 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
556 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 557 [XSTATE_PKRU_BIT] =
558 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 559 .offset = offsetof(X86XSaveArea, pkru_state),
560 .size = sizeof(XSavePKRU) },
2560f19f 561};
8e8aba50 562
1fda6198
EH		 563static uint32_t xsave_area_size(uint64_t mask)
564{
565 int i;
566 uint64_t ret = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader);
567
568 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
569 const ExtSaveArea *esa = &x86_ext_save_areas[i];
570 if ((mask >> i) & 1) {
571 ret = MAX(ret, esa->offset + esa->size);
572 }
573 }
574 return ret;
575}
576
96193c22
EH		 577static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
578{
579 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
580 cpu->env.features[FEAT_XSAVE_COMP_LO];
581}
582
8b4beddc
EH		 583const char *get_register_name_32(unsigned int reg)
584{
31ccdde2 585 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 586 return NULL;
587 }
8e8aba50 588 return x86_reg_info_32[reg].name;
8b4beddc
EH		 589}
590
84f1b92f
EH		 591/*
592 * Returns the set of feature flags that are supported and migratable by
593 * QEMU, for a given FeatureWord.
594 */
595static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
596{
597 FeatureWordInfo *wi = &feature_word_info[w];
598 uint32_t r = 0;
599 int i;
600
601 for (i = 0; i < 32; i++) {
602 uint32_t f = 1U << i;
603 /* If the feature name is unknown, it is not supported by QEMU yet */
604 if (!wi->feat_names[i]) {
605 continue;
606 }
607 /* Skip features known to QEMU, but explicitly marked as unmigratable */
608 if (wi->unmigratable_flags & f) {
609 continue;
610 }
611 r |= f;
612 }
613 return r;
614}
615
bb44e0d1
JK		 616void host_cpuid(uint32_t function, uint32_t count,
617 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 618{
a1fd24af
AL		 619 uint32_t vec[4];
620
621#ifdef __x86_64__
622 asm volatile("cpuid"
623 : "=a"(vec[0]), "=b"(vec[1]),
624 "=c"(vec[2]), "=d"(vec[3])
625 : "0"(function), "c"(count) : "cc");
c1f41226 626#elif defined(__i386__)
a1fd24af
AL		 627 asm volatile("pusha \n\t"
628 "cpuid \n\t"
629 "mov %%eax, 0(%2) \n\t"
630 "mov %%ebx, 4(%2) \n\t"
631 "mov %%ecx, 8(%2) \n\t"
632 "mov %%edx, 12(%2) \n\t"
633 "popa"
634 : : "a"(function), "c"(count), "S"(vec)
635 : "memory", "cc");
c1f41226
EH		 636#else
637 abort();
a1fd24af
AL		 638#endif
639
bdde476a 640 if (eax)
a1fd24af 641 *eax = vec[0];
bdde476a 642 if (ebx)
a1fd24af 643 *ebx = vec[1];
bdde476a 644 if (ecx)
a1fd24af 645 *ecx = vec[2];
bdde476a 646 if (edx)
a1fd24af 647 *edx = vec[3];
bdde476a 648}
c6dc6f63
AP		 649
650#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
651
652/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
653 * a substring. ex if !NULL points to the first char after a substring,
654 * otherwise the string is assumed to sized by a terminating nul.
655 * Return lexical ordering of *s1:*s2.
656 */
8f9d989c
CF		 657static int sstrcmp(const char *s1, const char *e1,
658 const char *s2, const char *e2)
c6dc6f63
AP		 659{
660 for (;;) {
661 if (!*s1 || !*s2 || *s1 != *s2)
662 return (*s1 - *s2);
663 ++s1, ++s2;
664 if (s1 == e1 && s2 == e2)
665 return (0);
666 else if (s1 == e1)
667 return (*s2);
668 else if (s2 == e2)
669 return (*s1);
670 }
671}
672
673/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
674 * '|' delimited (possibly empty) strings in which case search for a match
675 * within the alternatives proceeds left to right. Return 0 for success,
676 * non-zero otherwise.
677 */
678static int altcmp(const char *s, const char *e, const char *altstr)
679{
680 const char *p, *q;
681
682 for (q = p = altstr; ; ) {
683 while (*p && *p != '|')
684 ++p;
685 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
686 return (0);
687 if (!*p)
688 return (1);
689 else
690 q = ++p;
691 }
692}
693
694/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 695 * *pval and return true, otherwise return false
c6dc6f63 696 */
e41e0fc6
JK		 697static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
698 const char **featureset)
c6dc6f63
AP		 699{
700 uint32_t mask;
701 const char **ppc;
e41e0fc6 702 bool found = false;
c6dc6f63 703
e41e0fc6 704 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 705 if (*ppc && !altcmp(s, e, *ppc)) {
706 *pval |= mask;
e41e0fc6 707 found = true;
c6dc6f63 708 }
e41e0fc6
JK		 709 }
710 return found;
c6dc6f63
AP		 711}
712
5ef57876 713static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 714 FeatureWordArray words,
715 Error **errp)
c6dc6f63 716{
5ef57876
EH		 717 FeatureWord w;
718 for (w = 0; w < FEATURE_WORDS; w++) {
719 FeatureWordInfo *wi = &feature_word_info[w];
2d5312da 720 if (lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
5ef57876
EH		 721 break;
722 }
723 }
724 if (w == FEATURE_WORDS) {
c00c94ab 725 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 726 }
c6dc6f63
AP		 727}
728
d940ee9b
EH		 729/* CPU class name definitions: */
730
731#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
732#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
733
734/* Return type name for a given CPU model name
735 * Caller is responsible for freeing the returned string.
736 */
737static char *x86_cpu_type_name(const char *model_name)
738{
739 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
740}
741
500050d1
AF		 742static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
743{
d940ee9b
EH		 744 ObjectClass *oc;
745 char *typename;
746
500050d1
AF		 747 if (cpu_model == NULL) {
748 return NULL;
749 }
750
d940ee9b
EH		 751 typename = x86_cpu_type_name(cpu_model);
752 oc = object_class_by_name(typename);
753 g_free(typename);
754 return oc;
500050d1
AF		 755}
756
104494ea
IM		 757static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
758{
759 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
760 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
761 return g_strndup(class_name,
762 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
763}
764
d940ee9b 765struct X86CPUDefinition {
c6dc6f63
AP		 766 const char *name;
767 uint32_t level;
90e4b0c3 768 uint32_t xlevel;
99b88a17
IM		 769 /* vendor is zero-terminated, 12 character ASCII string */
770 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 771 int family;
772 int model;
773 int stepping;
0514ef2f 774 FeatureWordArray features;
c6dc6f63 775 char model_id[48];
d940ee9b 776};
c6dc6f63 777
9576de75 778static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 779 {
780 .name = "qemu64",
3046bb5d 781 .level = 0xd,
99b88a17 782 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 783 .family = 6,
f8e6a11a 784 .model = 6,
c6dc6f63 785 .stepping = 3,
0514ef2f 786 .features[FEAT_1_EDX] =
27861ecc 787 PPRO_FEATURES |
c6dc6f63 788 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 789 CPUID_PSE36,
0514ef2f 790 .features[FEAT_1_ECX] =
6aa91e4a 791 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 792 .features[FEAT_8000_0001_EDX] =
c6dc6f63 793 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 794 .features[FEAT_8000_0001_ECX] =
71195672 795 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 796 .xlevel = 0x8000000A,
9cf2cc3d 797 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 798 },
799 {
800 .name = "phenom",
801 .level = 5,
99b88a17 802 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 803 .family = 16,
804 .model = 2,
805 .stepping = 3,
b9fc20bc 806 /* Missing: CPUID_HT */
0514ef2f 807 .features[FEAT_1_EDX] =
27861ecc 808 PPRO_FEATURES |
c6dc6f63 809 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 810 CPUID_PSE36 | CPUID_VME,
0514ef2f 811 .features[FEAT_1_ECX] =
27861ecc 812 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 813 CPUID_EXT_POPCNT,
0514ef2f 814 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 815 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
816 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 817 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 818 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
819 CPUID_EXT3_CR8LEG,
820 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
821 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 822 .features[FEAT_8000_0001_ECX] =
27861ecc 823 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 824 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 825 /* Missing: CPUID_SVM_LBRV */
0514ef2f 826 .features[FEAT_SVM] =
b9fc20bc 827 CPUID_SVM_NPT,
c6dc6f63
AP		 828 .xlevel = 0x8000001A,
829 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
830 },
831 {
832 .name = "core2duo",
833 .level = 10,
99b88a17 834 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 835 .family = 6,
836 .model = 15,
837 .stepping = 11,
b9fc20bc 838 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 839 .features[FEAT_1_EDX] =
27861ecc 840 PPRO_FEATURES |
c6dc6f63 841 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 842 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
843 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 844 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 845 .features[FEAT_1_ECX] =
27861ecc 846 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 847 CPUID_EXT_CX16,
0514ef2f 848 .features[FEAT_8000_0001_EDX] =
27861ecc 849 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 850 .features[FEAT_8000_0001_ECX] =
27861ecc 851 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 852 .xlevel = 0x80000008,
853 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
854 },
855 {
856 .name = "kvm64",
3046bb5d 857 .level = 0xd,
99b88a17 858 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 859 .family = 15,
860 .model = 6,
861 .stepping = 1,
b3a4f0b1 862 /* Missing: CPUID_HT */
0514ef2f 863 .features[FEAT_1_EDX] =
b3a4f0b1 864 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 865 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
866 CPUID_PSE36,
867 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 868 .features[FEAT_1_ECX] =
27861ecc 869 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 870 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 871 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 872 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
873 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
874 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
875 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
876 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 877 .features[FEAT_8000_0001_ECX] =
27861ecc 878 0,
c6dc6f63
AP		 879 .xlevel = 0x80000008,
880 .model_id = "Common KVM processor"
881 },
c6dc6f63
AP		 882 {
883 .name = "qemu32",
884 .level = 4,
99b88a17 885 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 886 .family = 6,
f8e6a11a 887 .model = 6,
c6dc6f63 888 .stepping = 3,
0514ef2f 889 .features[FEAT_1_EDX] =
27861ecc 890 PPRO_FEATURES,
0514ef2f 891 .features[FEAT_1_ECX] =
6aa91e4a 892 CPUID_EXT_SSE3,
58012d66 893 .xlevel = 0x80000004,
9cf2cc3d 894 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 895 },
eafaf1e5
AP		 896 {
897 .name = "kvm32",
898 .level = 5,
99b88a17 899 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 900 .family = 15,
901 .model = 6,
902 .stepping = 1,
0514ef2f 903 .features[FEAT_1_EDX] =
b3a4f0b1 904 PPRO_FEATURES | CPUID_VME |
eafaf1e5 905 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 906 .features[FEAT_1_ECX] =
27861ecc 907 CPUID_EXT_SSE3,
0514ef2f 908 .features[FEAT_8000_0001_ECX] =
27861ecc 909 0,
eafaf1e5
AP		 910 .xlevel = 0x80000008,
911 .model_id = "Common 32-bit KVM processor"
912 },
c6dc6f63
AP		 913 {
914 .name = "coreduo",
915 .level = 10,
99b88a17 916 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 917 .family = 6,
918 .model = 14,
919 .stepping = 8,
b9fc20bc 920 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 921 .features[FEAT_1_EDX] =
27861ecc 922 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 923 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
924 CPUID_SS,
925 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 926 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 927 .features[FEAT_1_ECX] =
e93abc14 928 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 929 .features[FEAT_8000_0001_EDX] =
27861ecc 930 CPUID_EXT2_NX,
c6dc6f63
AP		 931 .xlevel = 0x80000008,
932 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
933 },
934 {
935 .name = "486",
58012d66 936 .level = 1,
99b88a17 937 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 938 .family = 4,
b2a856d9 939 .model = 8,
c6dc6f63 940 .stepping = 0,
0514ef2f 941 .features[FEAT_1_EDX] =
27861ecc 942 I486_FEATURES,
c6dc6f63
AP		 943 .xlevel = 0,
944 },
945 {
946 .name = "pentium",
947 .level = 1,
99b88a17 948 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 949 .family = 5,
950 .model = 4,
951 .stepping = 3,
0514ef2f 952 .features[FEAT_1_EDX] =
27861ecc 953 PENTIUM_FEATURES,
c6dc6f63
AP		 954 .xlevel = 0,
955 },
956 {
957 .name = "pentium2",
958 .level = 2,
99b88a17 959 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 960 .family = 6,
961 .model = 5,
962 .stepping = 2,
0514ef2f 963 .features[FEAT_1_EDX] =
27861ecc 964 PENTIUM2_FEATURES,
c6dc6f63
AP		 965 .xlevel = 0,
966 },
967 {
968 .name = "pentium3",
3046bb5d 969 .level = 3,
99b88a17 970 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 971 .family = 6,
972 .model = 7,
973 .stepping = 3,
0514ef2f 974 .features[FEAT_1_EDX] =
27861ecc 975 PENTIUM3_FEATURES,
c6dc6f63
AP		 976 .xlevel = 0,
977 },
978 {
979 .name = "athlon",
980 .level = 2,
99b88a17 981 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 982 .family = 6,
983 .model = 2,
984 .stepping = 3,
0514ef2f 985 .features[FEAT_1_EDX] =
27861ecc 986 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 987 CPUID_MCA,
0514ef2f 988 .features[FEAT_8000_0001_EDX] =
60032ac0 989 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 990 .xlevel = 0x80000008,
9cf2cc3d 991 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 992 },
993 {
994 .name = "n270",
3046bb5d 995 .level = 10,
99b88a17 996 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 997 .family = 6,
998 .model = 28,
999 .stepping = 2,
b9fc20bc 1000 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1001 .features[FEAT_1_EDX] =
27861ecc 1002 PPRO_FEATURES |
b9fc20bc
EH		 1003 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1004 CPUID_ACPI | CPUID_SS,
c6dc6f63 1005 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1006 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1007 * CPUID_EXT_XTPR */
0514ef2f 1008 .features[FEAT_1_ECX] =
27861ecc 1009 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1010 CPUID_EXT_MOVBE,
0514ef2f 1011 .features[FEAT_8000_0001_EDX] =
60032ac0 1012 CPUID_EXT2_NX,
0514ef2f 1013 .features[FEAT_8000_0001_ECX] =
27861ecc 1014 CPUID_EXT3_LAHF_LM,
3046bb5d 1015 .xlevel = 0x80000008,
c6dc6f63
AP		 1016 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1017 },
3eca4642
EH		 1018 {
1019 .name = "Conroe",
3046bb5d 1020 .level = 10,
99b88a17 1021 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1022 .family = 6,
ffce9ebb 1023 .model = 15,
3eca4642 1024 .stepping = 3,
0514ef2f 1025 .features[FEAT_1_EDX] =
b3a4f0b1 1026 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1027 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1028 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1029 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1030 CPUID_DE | CPUID_FP87,
0514ef2f 1031 .features[FEAT_1_ECX] =
27861ecc 1032 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1033 .features[FEAT_8000_0001_EDX] =
27861ecc 1034 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1035 .features[FEAT_8000_0001_ECX] =
27861ecc 1036 CPUID_EXT3_LAHF_LM,
3046bb5d 1037 .xlevel = 0x80000008,
3eca4642
EH		 1038 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1039 },
1040 {
1041 .name = "Penryn",
3046bb5d 1042 .level = 10,
99b88a17 1043 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1044 .family = 6,
ffce9ebb 1045 .model = 23,
3eca4642 1046 .stepping = 3,
0514ef2f 1047 .features[FEAT_1_EDX] =
b3a4f0b1 1048 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1049 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1050 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1051 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1052 CPUID_DE | CPUID_FP87,
0514ef2f 1053 .features[FEAT_1_ECX] =
27861ecc 1054 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1055 CPUID_EXT_SSE3,
0514ef2f 1056 .features[FEAT_8000_0001_EDX] =
27861ecc 1057 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1058 .features[FEAT_8000_0001_ECX] =
27861ecc 1059 CPUID_EXT3_LAHF_LM,
3046bb5d 1060 .xlevel = 0x80000008,
3eca4642
EH		 1061 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1062 },
1063 {
1064 .name = "Nehalem",
3046bb5d 1065 .level = 11,
99b88a17 1066 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1067 .family = 6,
ffce9ebb 1068 .model = 26,
3eca4642 1069 .stepping = 3,
0514ef2f 1070 .features[FEAT_1_EDX] =
b3a4f0b1 1071 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1072 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1073 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1074 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1075 CPUID_DE | CPUID_FP87,
0514ef2f 1076 .features[FEAT_1_ECX] =
27861ecc 1077 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1078 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1079 .features[FEAT_8000_0001_EDX] =
27861ecc 1080 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1081 .features[FEAT_8000_0001_ECX] =
27861ecc 1082 CPUID_EXT3_LAHF_LM,
3046bb5d 1083 .xlevel = 0x80000008,
3eca4642
EH		 1084 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1085 },
1086 {
1087 .name = "Westmere",
1088 .level = 11,
99b88a17 1089 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1090 .family = 6,
1091 .model = 44,
1092 .stepping = 1,
0514ef2f 1093 .features[FEAT_1_EDX] =
b3a4f0b1 1094 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1095 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1096 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1097 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1098 CPUID_DE | CPUID_FP87,
0514ef2f 1099 .features[FEAT_1_ECX] =
27861ecc 1100 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1101 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1102 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1103 .features[FEAT_8000_0001_EDX] =
27861ecc 1104 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1105 .features[FEAT_8000_0001_ECX] =
27861ecc 1106 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1107 .features[FEAT_6_EAX] =
1108 CPUID_6_EAX_ARAT,
3046bb5d 1109 .xlevel = 0x80000008,
3eca4642
EH		 1110 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1111 },
1112 {
1113 .name = "SandyBridge",
1114 .level = 0xd,
99b88a17 1115 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1116 .family = 6,
1117 .model = 42,
1118 .stepping = 1,
0514ef2f 1119 .features[FEAT_1_EDX] =
b3a4f0b1 1120 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1121 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1122 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1123 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1124 CPUID_DE | CPUID_FP87,
0514ef2f 1125 .features[FEAT_1_ECX] =
27861ecc 1126 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1127 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1128 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1129 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1130 CPUID_EXT_SSE3,
0514ef2f 1131 .features[FEAT_8000_0001_EDX] =
27861ecc 1132 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1133 CPUID_EXT2_SYSCALL,
0514ef2f 1134 .features[FEAT_8000_0001_ECX] =
27861ecc 1135 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1136 .features[FEAT_XSAVE] =
1137 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1138 .features[FEAT_6_EAX] =
1139 CPUID_6_EAX_ARAT,
3046bb5d 1140 .xlevel = 0x80000008,
3eca4642
EH		 1141 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1142 },
2f9ac42a
PB		 1143 {
1144 .name = "IvyBridge",
1145 .level = 0xd,
1146 .vendor = CPUID_VENDOR_INTEL,
1147 .family = 6,
1148 .model = 58,
1149 .stepping = 9,
1150 .features[FEAT_1_EDX] =
1151 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1152 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1153 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1154 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1155 CPUID_DE | CPUID_FP87,
1156 .features[FEAT_1_ECX] =
1157 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1158 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1159 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1160 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1161 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1162 .features[FEAT_7_0_EBX] =
1163 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1164 CPUID_7_0_EBX_ERMS,
1165 .features[FEAT_8000_0001_EDX] =
1166 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1167 CPUID_EXT2_SYSCALL,
1168 .features[FEAT_8000_0001_ECX] =
1169 CPUID_EXT3_LAHF_LM,
1170 .features[FEAT_XSAVE] =
1171 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1172 .features[FEAT_6_EAX] =
1173 CPUID_6_EAX_ARAT,
3046bb5d 1174 .xlevel = 0x80000008,
2f9ac42a
PB		 1175 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1176 },
37507094 1177 {
a356850b
EH		 1178 .name = "Haswell-noTSX",
1179 .level = 0xd,
1180 .vendor = CPUID_VENDOR_INTEL,
1181 .family = 6,
1182 .model = 60,
1183 .stepping = 1,
1184 .features[FEAT_1_EDX] =
1185 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1186 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1187 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1188 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1189 CPUID_DE | CPUID_FP87,
1190 .features[FEAT_1_ECX] =
1191 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1192 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1193 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1194 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1195 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1196 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1197 .features[FEAT_8000_0001_EDX] =
1198 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1199 CPUID_EXT2_SYSCALL,
1200 .features[FEAT_8000_0001_ECX] =
becb6667 1201 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1202 .features[FEAT_7_0_EBX] =
1203 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1204 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1205 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1206 .features[FEAT_XSAVE] =
1207 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1208 .features[FEAT_6_EAX] =
1209 CPUID_6_EAX_ARAT,
3046bb5d 1210 .xlevel = 0x80000008,
a356850b
EH		 1211 .model_id = "Intel Core Processor (Haswell, no TSX)",
1212 }, {
37507094
EH		 1213 .name = "Haswell",
1214 .level = 0xd,
99b88a17 1215 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1216 .family = 6,
1217 .model = 60,
1218 .stepping = 1,
0514ef2f 1219 .features[FEAT_1_EDX] =
b3a4f0b1 1220 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1221 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1222 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1223 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1224 CPUID_DE | CPUID_FP87,
0514ef2f 1225 .features[FEAT_1_ECX] =
27861ecc 1226 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1227 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1228 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1229 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1230 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1231 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1232 .features[FEAT_8000_0001_EDX] =
27861ecc 1233 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1234 CPUID_EXT2_SYSCALL,
0514ef2f 1235 .features[FEAT_8000_0001_ECX] =
becb6667 1236 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1237 .features[FEAT_7_0_EBX] =
27861ecc 1238 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1239 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1240 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1241 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1242 .features[FEAT_XSAVE] =
1243 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1244 .features[FEAT_6_EAX] =
1245 CPUID_6_EAX_ARAT,
3046bb5d 1246 .xlevel = 0x80000008,
37507094
EH		 1247 .model_id = "Intel Core Processor (Haswell)",
1248 },
a356850b
EH		 1249 {
1250 .name = "Broadwell-noTSX",
1251 .level = 0xd,
1252 .vendor = CPUID_VENDOR_INTEL,
1253 .family = 6,
1254 .model = 61,
1255 .stepping = 2,
1256 .features[FEAT_1_EDX] =
1257 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1258 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1259 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1260 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1261 CPUID_DE | CPUID_FP87,
1262 .features[FEAT_1_ECX] =
1263 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1264 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1265 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1266 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1267 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1268 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1269 .features[FEAT_8000_0001_EDX] =
1270 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1271 CPUID_EXT2_SYSCALL,
1272 .features[FEAT_8000_0001_ECX] =
becb6667 1273 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1274 .features[FEAT_7_0_EBX] =
1275 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1276 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1277 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1278 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1279 CPUID_7_0_EBX_SMAP,
1280 .features[FEAT_XSAVE] =
1281 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1282 .features[FEAT_6_EAX] =
1283 CPUID_6_EAX_ARAT,
3046bb5d 1284 .xlevel = 0x80000008,
a356850b
EH		 1285 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1286 },
ece01354
EH		 1287 {
1288 .name = "Broadwell",
1289 .level = 0xd,
1290 .vendor = CPUID_VENDOR_INTEL,
1291 .family = 6,
1292 .model = 61,
1293 .stepping = 2,
1294 .features[FEAT_1_EDX] =
b3a4f0b1 1295 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1296 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1297 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1298 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1299 CPUID_DE | CPUID_FP87,
1300 .features[FEAT_1_ECX] =
1301 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1302 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1303 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1304 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1305 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1306 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1307 .features[FEAT_8000_0001_EDX] =
1308 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1309 CPUID_EXT2_SYSCALL,
1310 .features[FEAT_8000_0001_ECX] =
becb6667 1311 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1312 .features[FEAT_7_0_EBX] =
1313 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1314 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1315 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1316 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1317 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1318 .features[FEAT_XSAVE] =
1319 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1320 .features[FEAT_6_EAX] =
1321 CPUID_6_EAX_ARAT,
3046bb5d 1322 .xlevel = 0x80000008,
ece01354
EH		 1323 .model_id = "Intel Core Processor (Broadwell)",
1324 },
f6f949e9
EH		 1325 {
1326 .name = "Skylake-Client",
1327 .level = 0xd,
1328 .vendor = CPUID_VENDOR_INTEL,
1329 .family = 6,
1330 .model = 94,
1331 .stepping = 3,
1332 .features[FEAT_1_EDX] =
1333 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1334 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1335 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1336 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1337 CPUID_DE | CPUID_FP87,
1338 .features[FEAT_1_ECX] =
1339 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1340 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1341 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1342 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1343 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1344 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1345 .features[FEAT_8000_0001_EDX] =
1346 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1347 CPUID_EXT2_SYSCALL,
1348 .features[FEAT_8000_0001_ECX] =
1349 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1350 .features[FEAT_7_0_EBX] =
1351 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1352 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1353 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1354 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1355 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1356 /* Missing: XSAVES (not supported by some Linux versions,
1357 * including v4.1 to v4.6).
1358 * KVM doesn't yet expose any XSAVES state save component,
1359 * and the only one defined in Skylake (processor tracing)
1360 * probably will block migration anyway.
1361 */
1362 .features[FEAT_XSAVE] =
1363 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1364 CPUID_XSAVE_XGETBV1,
1365 .features[FEAT_6_EAX] =
1366 CPUID_6_EAX_ARAT,
1367 .xlevel = 0x80000008,
1368 .model_id = "Intel Core Processor (Skylake)",
1369 },
3eca4642
EH		 1370 {
1371 .name = "Opteron_G1",
1372 .level = 5,
99b88a17 1373 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1374 .family = 15,
1375 .model = 6,
1376 .stepping = 1,
0514ef2f 1377 .features[FEAT_1_EDX] =
b3a4f0b1 1378 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1379 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1380 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1381 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1382 CPUID_DE | CPUID_FP87,
0514ef2f 1383 .features[FEAT_1_ECX] =
27861ecc 1384 CPUID_EXT_SSE3,
0514ef2f 1385 .features[FEAT_8000_0001_EDX] =
27861ecc 1386 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1387 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1388 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1389 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1390 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1391 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1392 .xlevel = 0x80000008,
1393 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1394 },
1395 {
1396 .name = "Opteron_G2",
1397 .level = 5,
99b88a17 1398 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1399 .family = 15,
1400 .model = 6,
1401 .stepping = 1,
0514ef2f 1402 .features[FEAT_1_EDX] =
b3a4f0b1 1403 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1404 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1405 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1406 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1407 CPUID_DE | CPUID_FP87,
0514ef2f 1408 .features[FEAT_1_ECX] =
27861ecc 1409 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1410 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1411 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1412 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1413 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1414 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1415 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1416 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1417 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1418 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1419 .features[FEAT_8000_0001_ECX] =
27861ecc 1420 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1421 .xlevel = 0x80000008,
1422 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1423 },
1424 {
1425 .name = "Opteron_G3",
1426 .level = 5,
99b88a17 1427 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1428 .family = 15,
1429 .model = 6,
1430 .stepping = 1,
0514ef2f 1431 .features[FEAT_1_EDX] =
b3a4f0b1 1432 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1433 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1434 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1435 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1436 CPUID_DE | CPUID_FP87,
0514ef2f 1437 .features[FEAT_1_ECX] =
27861ecc 1438 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1439 CPUID_EXT_SSE3,
33b5e8c0 1440 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1441 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1442 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1443 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1444 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1445 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1446 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1447 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1448 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1449 .features[FEAT_8000_0001_ECX] =
27861ecc 1450 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1451 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1452 .xlevel = 0x80000008,
1453 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1454 },
1455 {
1456 .name = "Opteron_G4",
1457 .level = 0xd,
99b88a17 1458 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1459 .family = 21,
1460 .model = 1,
1461 .stepping = 2,
0514ef2f 1462 .features[FEAT_1_EDX] =
b3a4f0b1 1463 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1464 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1465 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1466 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1467 CPUID_DE | CPUID_FP87,
0514ef2f 1468 .features[FEAT_1_ECX] =
27861ecc 1469 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1470 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1471 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1472 CPUID_EXT_SSE3,
33b5e8c0 1473 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1474 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1475 CPUID_EXT2_LM |
b3fb3a20
EH		 1476 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1477 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1478 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1479 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1480 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1481 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1482 .features[FEAT_8000_0001_ECX] =
27861ecc 1483 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1484 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1485 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1486 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1487 /* no xsaveopt! */
3eca4642
EH		 1488 .xlevel = 0x8000001A,
1489 .model_id = "AMD Opteron 62xx class CPU",
1490 },
021941b9
AP		 1491 {
1492 .name = "Opteron_G5",
1493 .level = 0xd,
99b88a17 1494 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1495 .family = 21,
1496 .model = 2,
1497 .stepping = 0,
0514ef2f 1498 .features[FEAT_1_EDX] =
b3a4f0b1 1499 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1500 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1501 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1502 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1503 CPUID_DE | CPUID_FP87,
0514ef2f 1504 .features[FEAT_1_ECX] =
27861ecc 1505 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1506 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1507 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1508 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1509 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1510 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1511 CPUID_EXT2_LM |
b3fb3a20
EH		 1512 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1513 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1514 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1515 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1516 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1517 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1518 .features[FEAT_8000_0001_ECX] =
27861ecc 1519 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1520 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1521 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1522 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1523 /* no xsaveopt! */
021941b9
AP		 1524 .xlevel = 0x8000001A,
1525 .model_id = "AMD Opteron 63xx class CPU",
1526 },
c6dc6f63
AP		 1527};
1528
5114e842
EH		 1529typedef struct PropValue {
1530 const char *prop, *value;
1531} PropValue;
1532
1533/* KVM-specific features that are automatically added/removed
1534 * from all CPU models when KVM is enabled.
1535 */
1536static PropValue kvm_default_props[] = {
1537 { "kvmclock", "on" },
1538 { "kvm-nopiodelay", "on" },
1539 { "kvm-asyncpf", "on" },
1540 { "kvm-steal-time", "on" },
1541 { "kvm-pv-eoi", "on" },
1542 { "kvmclock-stable-bit", "on" },
1543 { "x2apic", "on" },
1544 { "acpi", "off" },
1545 { "monitor", "off" },
1546 { "svm", "off" },
1547 { NULL, NULL },
1548};
1549
1550void x86_cpu_change_kvm_default(const char *prop, const char *value)
1551{
1552 PropValue *pv;
1553 for (pv = kvm_default_props; pv->prop; pv++) {
1554 if (!strcmp(pv->prop, prop)) {
1555 pv->value = value;
1556 break;
1557 }
1558 }
1559
1560 /* It is valid to call this function only for properties that
1561 * are already present in the kvm_default_props table.
1562 */
1563 assert(pv->prop);
1564}
1565
4d1b279b
EH		 1566static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1567 bool migratable_only);
1568
d940ee9b
EH		 1569#ifdef CONFIG_KVM
1570
40bfe48f
HZ		 1571static bool lmce_supported(void)
1572{
1573 uint64_t mce_cap;
1574
1575 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1576 return false;
1577 }
1578
1579 return !!(mce_cap & MCG_LMCE_P);
1580}
1581
c6dc6f63
AP		 1582static int cpu_x86_fill_model_id(char *str)
1583{
1584 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1585 int i;
1586
1587 for (i = 0; i < 3; i++) {
1588 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1589 memcpy(str + i * 16 + 0, &eax, 4);
1590 memcpy(str + i * 16 + 4, &ebx, 4);
1591 memcpy(str + i * 16 + 8, &ecx, 4);
1592 memcpy(str + i * 16 + 12, &edx, 4);
1593 }
1594 return 0;
1595}
1596
d940ee9b
EH		 1597static X86CPUDefinition host_cpudef;
1598
84f1b92f 1599static Property host_x86_cpu_properties[] = {
120eee7d 1600 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1601 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1602 DEFINE_PROP_END_OF_LIST()
1603};
1604
d940ee9b 1605/* class_init for the "host" CPU model
6e746f30 1606 *
d940ee9b 1607 * This function may be called before KVM is initialized.
6e746f30 1608 */
d940ee9b 1609static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1610{
84f1b92f 1611 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1612 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1613 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1614
d940ee9b 1615 xcc->kvm_required = true;
6e746f30 1616
c6dc6f63 1617 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1618 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1619
1620 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1621 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1622 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1623 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1624
d940ee9b 1625 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1626
d940ee9b 1627 xcc->cpu_def = &host_cpudef;
d940ee9b
EH		 1628
1629 /* level, xlevel, xlevel2, and the feature words are initialized on
1630 * instance_init, because they require KVM to be initialized.
1631 */
84f1b92f
EH		 1632
1633 dc->props = host_x86_cpu_properties;
4c315c27
MA		 1634 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1635 dc->cannot_destroy_with_object_finalize_yet = true;
d940ee9b
EH		 1636}
1637
1638static void host_x86_cpu_initfn(Object *obj)
1639{
1640 X86CPU *cpu = X86_CPU(obj);
1641 CPUX86State *env = &cpu->env;
1642 KVMState *s = kvm_state;
d940ee9b 1643
4d1b279b
EH		 1644 /* We can't fill the features array here because we don't know yet if
1645 * "migratable" is true or false.
1646 */
1647 cpu->host_features = true;
1648
104494ea 1649 /* If KVM is disabled, x86_cpu_realizefn() will report an error later */
e4356010 1650 if (kvm_enabled()) {
c39c0edf
EH		 1651 env->cpuid_min_level =
1652 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1653 env->cpuid_min_xlevel =
1654 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1655 env->cpuid_min_xlevel2 =
1656 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
40bfe48f
HZ		 1657
1658 if (lmce_supported()) {
1659 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1660 }
e4356010 1661 }
2a573259 1662
d940ee9b 1663 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1664}
1665
d940ee9b
EH		 1666static const TypeInfo host_x86_cpu_type_info = {
1667 .name = X86_CPU_TYPE_NAME("host"),
1668 .parent = TYPE_X86_CPU,
1669 .instance_init = host_x86_cpu_initfn,
1670 .class_init = host_x86_cpu_class_init,
1671};
1672
1673#endif
1674
8459e396 1675static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1676{
8459e396 1677 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1678 int i;
1679
857aee33 1680 for (i = 0; i < 32; ++i) {
72370dc1 1681 if ((1UL << i) & mask) {
bffd67b0 1682 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1683 assert(reg);
fefb41bf 1684 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1685 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1686 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1687 f->cpuid_eax, reg,
1688 f->feat_names[i] ? "." : "",
1689 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1690 }
857aee33 1691 }
c6dc6f63
AP		 1692}
1693
d7bce999
EB		 1694static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1695 const char *name, void *opaque,
1696 Error **errp)
95b8519d
AF		 1697{
1698 X86CPU *cpu = X86_CPU(obj);
1699 CPUX86State *env = &cpu->env;
1700 int64_t value;
1701
1702 value = (env->cpuid_version >> 8) & 0xf;
1703 if (value == 0xf) {
1704 value += (env->cpuid_version >> 20) & 0xff;
1705 }
51e72bc1 1706 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1707}
1708
d7bce999
EB		 1709static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1710 const char *name, void *opaque,
1711 Error **errp)
ed5e1ec3 1712{
71ad61d3
AF		 1713 X86CPU *cpu = X86_CPU(obj);
1714 CPUX86State *env = &cpu->env;
1715 const int64_t min = 0;
1716 const int64_t max = 0xff + 0xf;
65cd9064 1717 Error *local_err = NULL;
71ad61d3
AF		 1718 int64_t value;
1719
51e72bc1 1720 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1721 if (local_err) {
1722 error_propagate(errp, local_err);
71ad61d3
AF		 1723 return;
1724 }
1725 if (value < min || value > max) {
c6bd8c70
MA		 1726 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1727 name ? name : "null", value, min, max);
71ad61d3
AF		 1728 return;
1729 }
1730
ed5e1ec3 1731 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1732 if (value > 0x0f) {
1733 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1734 } else {
71ad61d3 1735 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1736 }
1737}
1738
d7bce999
EB		 1739static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1740 const char *name, void *opaque,
1741 Error **errp)
67e30c83
AF		 1742{
1743 X86CPU *cpu = X86_CPU(obj);
1744 CPUX86State *env = &cpu->env;
1745 int64_t value;
1746
1747 value = (env->cpuid_version >> 4) & 0xf;
1748 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1749 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1750}
1751
d7bce999
EB		 1752static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1753 const char *name, void *opaque,
1754 Error **errp)
b0704cbd 1755{
c5291a4f
AF		 1756 X86CPU *cpu = X86_CPU(obj);
1757 CPUX86State *env = &cpu->env;
1758 const int64_t min = 0;
1759 const int64_t max = 0xff;
65cd9064 1760 Error *local_err = NULL;
c5291a4f
AF		 1761 int64_t value;
1762
51e72bc1 1763 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1764 if (local_err) {
1765 error_propagate(errp, local_err);
c5291a4f
AF		 1766 return;
1767 }
1768 if (value < min || value > max) {
c6bd8c70
MA		 1769 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1770 name ? name : "null", value, min, max);
c5291a4f
AF		 1771 return;
1772 }
1773
b0704cbd 1774 env->cpuid_version &= ~0xf00f0;
c5291a4f 1775 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1776}
1777
35112e41 1778static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1779 const char *name, void *opaque,
35112e41
AF		 1780 Error **errp)
1781{
1782 X86CPU *cpu = X86_CPU(obj);
1783 CPUX86State *env = &cpu->env;
1784 int64_t value;
1785
1786 value = env->cpuid_version & 0xf;
51e72bc1 1787 visit_type_int(v, name, &value, errp);
35112e41
AF		 1788}
1789
036e2222 1790static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1791 const char *name, void *opaque,
036e2222 1792 Error **errp)
38c3dc46 1793{
036e2222
AF		 1794 X86CPU *cpu = X86_CPU(obj);
1795 CPUX86State *env = &cpu->env;
1796 const int64_t min = 0;
1797 const int64_t max = 0xf;
65cd9064 1798 Error *local_err = NULL;
036e2222
AF		 1799 int64_t value;
1800
51e72bc1 1801 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1802 if (local_err) {
1803 error_propagate(errp, local_err);
036e2222
AF		 1804 return;
1805 }
1806 if (value < min || value > max) {
c6bd8c70
MA		 1807 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1808 name ? name : "null", value, min, max);
036e2222
AF		 1809 return;
1810 }
1811
38c3dc46 1812 env->cpuid_version &= ~0xf;
036e2222 1813 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1814}
1815
d480e1af
AF		 1816static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1817{
1818 X86CPU *cpu = X86_CPU(obj);
1819 CPUX86State *env = &cpu->env;
1820 char *value;
d480e1af 1821
e42a92ae 1822 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1823 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1824 env->cpuid_vendor3);
d480e1af
AF		 1825 return value;
1826}
1827
1828static void x86_cpuid_set_vendor(Object *obj, const char *value,
1829 Error **errp)
1830{
1831 X86CPU *cpu = X86_CPU(obj);
1832 CPUX86State *env = &cpu->env;
1833 int i;
1834
9df694ee 1835 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1836 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1837 return;
1838 }
1839
1840 env->cpuid_vendor1 = 0;
1841 env->cpuid_vendor2 = 0;
1842 env->cpuid_vendor3 = 0;
1843 for (i = 0; i < 4; i++) {
1844 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1845 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1846 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1847 }
d480e1af
AF		 1848}
1849
63e886eb
AF		 1850static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1851{
1852 X86CPU *cpu = X86_CPU(obj);
1853 CPUX86State *env = &cpu->env;
1854 char *value;
1855 int i;
1856
1857 value = g_malloc(48 + 1);
1858 for (i = 0; i < 48; i++) {
1859 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1860 }
1861 value[48] = '\0';
1862 return value;
1863}
1864
938d4c25
AF		 1865static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1866 Error **errp)
dcce6675 1867{
938d4c25
AF		 1868 X86CPU *cpu = X86_CPU(obj);
1869 CPUX86State *env = &cpu->env;
dcce6675
AF		 1870 int c, len, i;
1871
1872 if (model_id == NULL) {
1873 model_id = "";
1874 }
1875 len = strlen(model_id);
d0a6acf4 1876 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1877 for (i = 0; i < 48; i++) {
1878 if (i >= len) {
1879 c = '\0';
1880 } else {
1881 c = (uint8_t)model_id[i];
1882 }
1883 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1884 }
1885}
1886
d7bce999
EB		 1887static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1888 void *opaque, Error **errp)
89e48965
AF		 1889{
1890 X86CPU *cpu = X86_CPU(obj);
1891 int64_t value;
1892
1893 value = cpu->env.tsc_khz * 1000;
51e72bc1 1894 visit_type_int(v, name, &value, errp);
89e48965
AF		 1895}
1896
d7bce999
EB		 1897static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1898 void *opaque, Error **errp)
89e48965
AF		 1899{
1900 X86CPU *cpu = X86_CPU(obj);
1901 const int64_t min = 0;
2e84849a 1902 const int64_t max = INT64_MAX;
65cd9064 1903 Error *local_err = NULL;
89e48965
AF		 1904 int64_t value;
1905
51e72bc1 1906 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1907 if (local_err) {
1908 error_propagate(errp, local_err);
89e48965
AF		 1909 return;
1910 }
1911 if (value < min || value > max) {
c6bd8c70
MA		 1912 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1913 name ? name : "null", value, min, max);
89e48965
AF		 1914 return;
1915 }
1916
36f96c4b 1917 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1918}
1919
7e5292b5 1920/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1921static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1922 const char *name, void *opaque,
1923 Error **errp)
8e8aba50 1924{
7e5292b5 1925 uint32_t *array = (uint32_t *)opaque;
8e8aba50 1926 FeatureWord w;
8e8aba50
EH		 1927 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1928 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1929 X86CPUFeatureWordInfoList *list = NULL;
1930
1931 for (w = 0; w < FEATURE_WORDS; w++) {
1932 FeatureWordInfo *wi = &feature_word_info[w];
1933 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1934 qwi->cpuid_input_eax = wi->cpuid_eax;
1935 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1936 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1937 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1938 qwi->features = array[w];
8e8aba50
EH		 1939
1940 /* List will be in reverse order, but order shouldn't matter */
1941 list_entries[w].next = list;
1942 list_entries[w].value = &word_infos[w];
1943 list = &list_entries[w];
1944 }
1945
6b62d961 1946 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 1947}
1948
d7bce999
EB		 1949static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1950 void *opaque, Error **errp)
c8f0f88e
IM		 1951{
1952 X86CPU *cpu = X86_CPU(obj);
1953 int64_t value = cpu->hyperv_spinlock_attempts;
1954
51e72bc1 1955 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1956}
1957
d7bce999
EB		 1958static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1959 void *opaque, Error **errp)
c8f0f88e
IM		 1960{
1961 const int64_t min = 0xFFF;
1962 const int64_t max = UINT_MAX;
1963 X86CPU *cpu = X86_CPU(obj);
1964 Error *err = NULL;
1965 int64_t value;
1966
51e72bc1 1967 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1968 if (err) {
1969 error_propagate(errp, err);
1970 return;
1971 }
1972
1973 if (value < min || value > max) {
1974 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1975 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1976 object_get_typename(obj), name ? name : "null",
1977 value, min, max);
c8f0f88e
IM		 1978 return;
1979 }
1980 cpu->hyperv_spinlock_attempts = value;
1981}
1982
1983static PropertyInfo qdev_prop_spinlocks = {
1984 .name = "int",
1985 .get = x86_get_hv_spinlocks,
1986 .set = x86_set_hv_spinlocks,
1987};
1988
72ac2e87
IM		 1989/* Convert all '_' in a feature string option name to '-', to make feature
1990 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1991 */
1992static inline void feat2prop(char *s)
1993{
1994 while ((s = strchr(s, '_'))) {
1995 *s = '-';
1996 }
1997}
1998
dc15c051
IM		 1999/* Compatibily hack to maintain legacy +-feat semantic,
2000 * where +-feat overwrites any feature set by
2001 * feat=on|feat even if the later is parsed after +-feat
2002 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2003 */
2004static FeatureWordArray plus_features = { 0 };
2005static FeatureWordArray minus_features = { 0 };
2006
8f961357
EH		 2007/* Parse "+feature,-feature,feature=foo" CPU feature string
2008 */
62a48a2a 2009static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 2010 Error **errp)
8f961357 2011{
8f961357 2012 char *featurestr; /* Single 'key=value" string being parsed */
94a444b2 2013 Error *local_err = NULL;
62a48a2a
IM		 2014 static bool cpu_globals_initialized;
2015
2016 if (cpu_globals_initialized) {
2017 return;
2018 }
2019 cpu_globals_initialized = true;
8f961357 2020
f6750e95
EH		 2021 if (!features) {
2022 return;
2023 }
2024
2025 for (featurestr = strtok(features, ",");
2026 featurestr && !local_err;
2027 featurestr = strtok(NULL, ",")) {
2028 const char *name;
2029 const char *val = NULL;
2030 char *eq = NULL;
cf2887c9 2031 char num[32];
62a48a2a 2032 GlobalProperty *prop;
c6dc6f63 2033
f6750e95 2034 /* Compatibility syntax: */
c6dc6f63 2035 if (featurestr[0] == '+') {
c00c94ab 2036 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
f6750e95 2037 continue;
c6dc6f63 2038 } else if (featurestr[0] == '-') {
c00c94ab 2039 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
f6750e95
EH		 2040 continue;
2041 }
2042
2043 eq = strchr(featurestr, '=');
2044 if (eq) {
2045 *eq++ = 0;
2046 val = eq;
c6dc6f63 2047 } else {
f6750e95 2048 val = "on";
a91987c2 2049 }
f6750e95
EH		 2050
2051 feat2prop(featurestr);
2052 name = featurestr;
2053
2054 /* Special case: */
2055 if (!strcmp(name, "tsc-freq")) {
2056 int64_t tsc_freq;
2057 char *err;
f6750e95
EH		 2058
2059 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
2060 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
2061 if (tsc_freq < 0 || *err) {
2062 error_setg(errp, "bad numerical value %s", val);
2063 return;
2064 }
2065 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2066 val = num;
2067 name = "tsc-frequency";
c6dc6f63 2068 }
f6750e95 2069
62a48a2a
IM		 2070 prop = g_new0(typeof(*prop), 1);
2071 prop->driver = typename;
2072 prop->property = g_strdup(name);
2073 prop->value = g_strdup(val);
2074 prop->errp = &error_fatal;
2075 qdev_prop_register_global(prop);
f6750e95
EH		 2076 }
2077
2078 if (local_err) {
2079 error_propagate(errp, local_err);
c6dc6f63 2080 }
c6dc6f63
AP		 2081}
2082
8c3329e5 2083/* Print all cpuid feature names in featureset
c6dc6f63 2084 */
8c3329e5 2085static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2086{
8c3329e5
EH		 2087 int bit;
2088 bool first = true;
2089
2090 for (bit = 0; bit < 32; bit++) {
2091 if (featureset[bit]) {
2092 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2093 first = false;
c6dc6f63 2094 }
8c3329e5 2095 }
c6dc6f63
AP		 2096}
2097
e916cbf8
PM		 2098/* generate CPU information. */
2099void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2100{
9576de75 2101 X86CPUDefinition *def;
c6dc6f63 2102 char buf[256];
7fc9b714 2103 int i;
c6dc6f63 2104
7fc9b714
AF		 2105 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2106 def = &builtin_x86_defs[i];
c04321b3 2107 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 2108 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 2109 }
21ad7789
JK		 2110#ifdef CONFIG_KVM
2111 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
2112 "KVM processor with all supported host features "
2113 "(only available in KVM mode)");
2114#endif
2115
6cdf8854 2116 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2117 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2118 FeatureWordInfo *fw = &feature_word_info[i];
2119
8c3329e5
EH		 2120 (*cpu_fprintf)(f, " ");
2121 listflags(f, cpu_fprintf, fw->feat_names);
2122 (*cpu_fprintf)(f, "\n");
3af60be2 2123 }
c6dc6f63
AP		 2124}
2125
76b64a7a 2126CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2127{
2128 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 2129 X86CPUDefinition *def;
7fc9b714 2130 int i;
e3966126 2131
7fc9b714 2132 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 2133 CpuDefinitionInfoList *entry;
2134 CpuDefinitionInfo *info;
2135
7fc9b714 2136 def = &builtin_x86_defs[i];
e3966126
AL		 2137 info = g_malloc0(sizeof(*info));
2138 info->name = g_strdup(def->name);
2139
2140 entry = g_malloc0(sizeof(*entry));
2141 entry->value = info;
2142 entry->next = cpu_list;
2143 cpu_list = entry;
2144 }
2145
2146 return cpu_list;
2147}
2148
84f1b92f
EH		 2149static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2150 bool migratable_only)
27418adf
EH		 2151{
2152 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2153 uint32_t r;
27418adf 2154
fefb41bf 2155 if (kvm_enabled()) {
84f1b92f
EH		 2156 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2157 wi->cpuid_ecx,
2158 wi->cpuid_reg);
fefb41bf 2159 } else if (tcg_enabled()) {
84f1b92f 2160 r = wi->tcg_features;
fefb41bf
EH		 2161 } else {
2162 return ~0;
2163 }
84f1b92f
EH		 2164 if (migratable_only) {
2165 r &= x86_cpu_get_migratable_flags(w);
2166 }
2167 return r;
27418adf
EH		 2168}
2169
51f63aed
EH		 2170/*
2171 * Filters CPU feature words based on host availability of each feature.
2172 *
51f63aed
EH		 2173 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2174 */
27418adf 2175static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2176{
2177 CPUX86State *env = &cpu->env;
bd87d2a2 2178 FeatureWord w;
51f63aed
EH		 2179 int rv = 0;
2180
bd87d2a2 2181 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2182 uint32_t host_feat =
2183 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2184 uint32_t requested_features = env->features[w];
2185 env->features[w] &= host_feat;
2186 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2187 if (cpu->filtered_features[w]) {
2188 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2189 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2190 }
2191 rv = 1;
2192 }
bd87d2a2 2193 }
51f63aed
EH		 2194
2195 return rv;
bc74b7db 2196}
bc74b7db 2197
5114e842
EH		 2198static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2199{
2200 PropValue *pv;
2201 for (pv = props; pv->prop; pv++) {
2202 if (!pv->value) {
2203 continue;
2204 }
2205 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2206 &error_abort);
2207 }
2208}
2209
d940ee9b 2210/* Load data from X86CPUDefinition
c080e30e 2211 */
d940ee9b 2212static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2213{
61dcd775 2214 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2215 const char *vendor;
2216 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2217 FeatureWord w;
c6dc6f63 2218
c39c0edf
EH		 2219 /* CPU models only set _minimum_ values for level/xlevel: */
2220 object_property_set_int(OBJECT(cpu), def->level, "min-level", errp);
2221 object_property_set_int(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
2222
2d64255b
AF		 2223 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2224 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2225 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2226 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2227 for (w = 0; w < FEATURE_WORDS; w++) {
2228 env->features[w] = def->features[w];
2229 }
82beb536 2230
9576de75 2231 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2232 if (kvm_enabled()) {
492a4c94
LT		 2233 if (!kvm_irqchip_in_kernel()) {
2234 x86_cpu_change_kvm_default("x2apic", "off");
2235 }
2236
5114e842 2237 x86_cpu_apply_props(cpu, kvm_default_props);
82beb536 2238 }
5fcca9ff 2239
82beb536 2240 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2241
2242 /* sysenter isn't supported in compatibility mode on AMD,
2243 * syscall isn't supported in compatibility mode on Intel.
2244 * Normally we advertise the actual CPU vendor, but you can
2245 * override this using the 'vendor' property if you want to use
2246 * KVM's sysenter/syscall emulation in compatibility mode and
2247 * when doing cross vendor migration
2248 */
74f54bc4 2249 vendor = def->vendor;
7c08db30
EH		 2250 if (kvm_enabled()) {
2251 uint32_t ebx = 0, ecx = 0, edx = 0;
2252 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2253 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2254 vendor = host_vendor;
2255 }
2256
2257 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2258
c6dc6f63
AP		 2259}
2260
0856579c 2261X86CPU *cpu_x86_init(const char *cpu_model)
7f833247 2262{
a57d0163 2263 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
5c3c6a68
AF		 2264}
2265
d940ee9b
EH		 2266static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2267{
2268 X86CPUDefinition *cpudef = data;
2269 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2270
2271 xcc->cpu_def = cpudef;
2272}
2273
2274static void x86_register_cpudef_type(X86CPUDefinition *def)
2275{
2276 char *typename = x86_cpu_type_name(def->name);
2277 TypeInfo ti = {
2278 .name = typename,
2279 .parent = TYPE_X86_CPU,
2280 .class_init = x86_cpu_cpudef_class_init,
2281 .class_data = def,
2282 };
2283
2284 type_register(&ti);
2285 g_free(typename);
2286}
2287
c6dc6f63 2288#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2289
0e26b7b8
BS		 2290void cpu_clear_apic_feature(CPUX86State *env)
2291{
0514ef2f 2292 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2293}
2294
c6dc6f63
AP		 2295#endif /* !CONFIG_USER_ONLY */
2296
c6dc6f63
AP		 2297void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2298 uint32_t *eax, uint32_t *ebx,
2299 uint32_t *ecx, uint32_t *edx)
2300{
a60f24b5
AF		 2301 X86CPU *cpu = x86_env_get_cpu(env);
2302 CPUState *cs = CPU(cpu);
14c985cf 2303 uint32_t pkg_offset;
a60f24b5 2304
c6dc6f63
AP		 2305 /* test if maximum index reached */
2306 if (index & 0x80000000) {
b3baa152
BW		 2307 if (index > env->cpuid_xlevel) {
2308 if (env->cpuid_xlevel2 > 0) {
2309 /* Handle the Centaur's CPUID instruction. */
2310 if (index > env->cpuid_xlevel2) {
2311 index = env->cpuid_xlevel2;
2312 } else if (index < 0xC0000000) {
2313 index = env->cpuid_xlevel;
2314 }
2315 } else {
57f26ae7
EH		 2316 /* Intel documentation states that invalid EAX input will
2317 * return the same information as EAX=cpuid_level
2318 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2319 */
2320 index = env->cpuid_level;
b3baa152
BW		 2321 }
2322 }
c6dc6f63
AP		 2323 } else {
2324 if (index > env->cpuid_level)
2325 index = env->cpuid_level;
2326 }
2327
2328 switch(index) {
2329 case 0:
2330 *eax = env->cpuid_level;
5eb2f7a4
EH		 2331 *ebx = env->cpuid_vendor1;
2332 *edx = env->cpuid_vendor2;
2333 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2334 break;
2335 case 1:
2336 *eax = env->cpuid_version;
7e72a45c
EH		 2337 *ebx = (cpu->apic_id << 24) |
2338 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2339 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2340 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2341 *ecx |= CPUID_EXT_OSXSAVE;
2342 }
0514ef2f 2343 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2344 if (cs->nr_cores * cs->nr_threads > 1) {
2345 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2346 *edx |= CPUID_HT;
c6dc6f63
AP		 2347 }
2348 break;
2349 case 2:
2350 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2351 if (cpu->cache_info_passthrough) {
2352 host_cpuid(index, 0, eax, ebx, ecx, edx);
2353 break;
2354 }
5e891bf8 2355 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 2356 *ebx = 0;
14c985cf
LM		 2357 if (!cpu->enable_l3_cache) {
2358 *ecx = 0;
2359 } else {
2360 *ecx = L3_N_DESCRIPTOR;
2361 }
5e891bf8
EH		 2362 *edx = (L1D_DESCRIPTOR << 16) | \
2363 (L1I_DESCRIPTOR << 8) | \
2364 (L2_DESCRIPTOR);
c6dc6f63
AP		 2365 break;
2366 case 4:
2367 /* cache info: needed for Core compatibility */
787aaf57
BC		 2368 if (cpu->cache_info_passthrough) {
2369 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2370 *eax &= ~0xFC000000;
c6dc6f63 2371 } else {
2f7a21c4 2372 *eax = 0;
76c2975a 2373 switch (count) {
c6dc6f63 2374 case 0: /* L1 dcache info */
5e891bf8
EH		 2375 *eax |= CPUID_4_TYPE_DCACHE | \
2376 CPUID_4_LEVEL(1) | \
2377 CPUID_4_SELF_INIT_LEVEL;
2378 *ebx = (L1D_LINE_SIZE - 1) | \
2379 ((L1D_PARTITIONS - 1) << 12) | \
2380 ((L1D_ASSOCIATIVITY - 1) << 22);
2381 *ecx = L1D_SETS - 1;
2382 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2383 break;
2384 case 1: /* L1 icache info */
5e891bf8
EH		 2385 *eax |= CPUID_4_TYPE_ICACHE | \
2386 CPUID_4_LEVEL(1) | \
2387 CPUID_4_SELF_INIT_LEVEL;
2388 *ebx = (L1I_LINE_SIZE - 1) | \
2389 ((L1I_PARTITIONS - 1) << 12) | \
2390 ((L1I_ASSOCIATIVITY - 1) << 22);
2391 *ecx = L1I_SETS - 1;
2392 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2393 break;
2394 case 2: /* L2 cache info */
5e891bf8
EH		 2395 *eax |= CPUID_4_TYPE_UNIFIED | \
2396 CPUID_4_LEVEL(2) | \
2397 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2398 if (cs->nr_threads > 1) {
2399 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2400 }
5e891bf8
EH		 2401 *ebx = (L2_LINE_SIZE - 1) | \
2402 ((L2_PARTITIONS - 1) << 12) | \
2403 ((L2_ASSOCIATIVITY - 1) << 22);
2404 *ecx = L2_SETS - 1;
2405 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63 2406 break;
14c985cf
LM		 2407 case 3: /* L3 cache info */
2408 if (!cpu->enable_l3_cache) {
2409 *eax = 0;
2410 *ebx = 0;
2411 *ecx = 0;
2412 *edx = 0;
2413 break;
2414 }
2415 *eax |= CPUID_4_TYPE_UNIFIED | \
2416 CPUID_4_LEVEL(3) | \
2417 CPUID_4_SELF_INIT_LEVEL;
2418 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2419 *eax |= ((1 << pkg_offset) - 1) << 14;
2420 *ebx = (L3_N_LINE_SIZE - 1) | \
2421 ((L3_N_PARTITIONS - 1) << 12) | \
2422 ((L3_N_ASSOCIATIVITY - 1) << 22);
2423 *ecx = L3_N_SETS - 1;
2424 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2425 break;
c6dc6f63
AP		 2426 default: /* end of info */
2427 *eax = 0;
2428 *ebx = 0;
2429 *ecx = 0;
2430 *edx = 0;
2431 break;
76c2975a
PB		 2432 }
2433 }
2434
2435 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2436 if ((*eax & 31) && cs->nr_cores > 1) {
2437 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2438 }
2439 break;
2440 case 5:
2441 /* mwait info: needed for Core compatibility */
2442 *eax = 0; /* Smallest monitor-line size in bytes */
2443 *ebx = 0; /* Largest monitor-line size in bytes */
2444 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2445 *edx = 0;
2446 break;
2447 case 6:
2448 /* Thermal and Power Leaf */
28b8e4d0 2449 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2450 *ebx = 0;
2451 *ecx = 0;
2452 *edx = 0;
2453 break;
f7911686 2454 case 7:
13526728
EH		 2455 /* Structured Extended Feature Flags Enumeration Leaf */
2456 if (count == 0) {
2457 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2458 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2459 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2460 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2461 *ecx |= CPUID_7_0_ECX_OSPKE;
2462 }
13526728 2463 *edx = 0; /* Reserved */
f7911686
YW		 2464 } else {
2465 *eax = 0;
2466 *ebx = 0;
2467 *ecx = 0;
2468 *edx = 0;
2469 }
2470 break;
c6dc6f63
AP		 2471 case 9:
2472 /* Direct Cache Access Information Leaf */
2473 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2474 *ebx = 0;
2475 *ecx = 0;
2476 *edx = 0;
2477 break;
2478 case 0xA:
2479 /* Architectural Performance Monitoring Leaf */
9337e3b6 2480 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2481 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2482
2483 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2484 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2485 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2486 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2487 } else {
2488 *eax = 0;
2489 *ebx = 0;
2490 *ecx = 0;
2491 *edx = 0;
2492 }
c6dc6f63 2493 break;
5232d00a
RK		 2494 case 0xB:
2495 /* Extended Topology Enumeration Leaf */
2496 if (!cpu->enable_cpuid_0xb) {
2497 *eax = *ebx = *ecx = *edx = 0;
2498 break;
2499 }
2500
2501 *ecx = count & 0xff;
2502 *edx = cpu->apic_id;
2503
2504 switch (count) {
2505 case 0:
eab60fb9
MAL		 2506 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
2507 *ebx = cs->nr_threads;
5232d00a
RK		 2508 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2509 break;
2510 case 1:
eab60fb9
MAL		 2511 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2512 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 2513 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2514 break;
2515 default:
2516 *eax = 0;
2517 *ebx = 0;
2518 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2519 }
2520
2521 assert(!(*eax & ~0x1f));
2522 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2523 break;
2560f19f 2524 case 0xD: {
51e49430 2525 /* Processor Extended State */
2560f19f
PB		 2526 *eax = 0;
2527 *ebx = 0;
2528 *ecx = 0;
2529 *edx = 0;
19dc85db 2530 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2531 break;
2532 }
4928cd6d 2533
2560f19f 2534 if (count == 0) {
96193c22
EH		 2535 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
2536 *eax = env->features[FEAT_XSAVE_COMP_LO];
2537 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 2538 *ebx = *ecx;
2539 } else if (count == 1) {
0bb0b2d2 2540 *eax = env->features[FEAT_XSAVE];
f4f1110e 2541 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 2542 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
2543 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 2544 *eax = esa->size;
2545 *ebx = esa->offset;
2560f19f 2546 }
51e49430
SY		 2547 }
2548 break;
2560f19f 2549 }
c6dc6f63
AP		 2550 case 0x80000000:
2551 *eax = env->cpuid_xlevel;
2552 *ebx = env->cpuid_vendor1;
2553 *edx = env->cpuid_vendor2;
2554 *ecx = env->cpuid_vendor3;
2555 break;
2556 case 0x80000001:
2557 *eax = env->cpuid_version;
2558 *ebx = 0;
0514ef2f
EH		 2559 *ecx = env->features[FEAT_8000_0001_ECX];
2560 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2561
2562 /* The Linux kernel checks for the CMPLegacy bit and
2563 * discards multiple thread information if it is set.
cb8d4c8f 2564 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2565 */
ce3960eb 2566 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2567 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2568 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2569 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2570 *ecx |= 1 << 1; /* CmpLegacy bit */
2571 }
2572 }
c6dc6f63
AP		 2573 break;
2574 case 0x80000002:
2575 case 0x80000003:
2576 case 0x80000004:
2577 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2578 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2579 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2580 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2581 break;
2582 case 0x80000005:
2583 /* cache info (L1 cache) */
787aaf57
BC		 2584 if (cpu->cache_info_passthrough) {
2585 host_cpuid(index, 0, eax, ebx, ecx, edx);
2586 break;
2587 }
5e891bf8
EH		 2588 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2589 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2590 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2591 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2592 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2593 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2594 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2595 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2596 break;
2597 case 0x80000006:
2598 /* cache info (L2 cache) */
787aaf57
BC		 2599 if (cpu->cache_info_passthrough) {
2600 host_cpuid(index, 0, eax, ebx, ecx, edx);
2601 break;
2602 }
5e891bf8
EH		 2603 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2604 (L2_DTLB_2M_ENTRIES << 16) | \
2605 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2606 (L2_ITLB_2M_ENTRIES);
2607 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2608 (L2_DTLB_4K_ENTRIES << 16) | \
2609 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2610 (L2_ITLB_4K_ENTRIES);
2611 *ecx = (L2_SIZE_KB_AMD << 16) | \
2612 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2613 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
14c985cf
LM		 2614 if (!cpu->enable_l3_cache) {
2615 *edx = ((L3_SIZE_KB / 512) << 18) | \
2616 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2617 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2618 } else {
2619 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
2620 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
2621 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
2622 }
c6dc6f63 2623 break;
303752a9
MT		 2624 case 0x80000007:
2625 *eax = 0;
2626 *ebx = 0;
2627 *ecx = 0;
2628 *edx = env->features[FEAT_8000_0007_EDX];
2629 break;
c6dc6f63
AP		 2630 case 0x80000008:
2631 /* virtual & phys address size in low 2 bytes. */
0514ef2f 2632 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a
DDAG		 2633 /* 64 bit processor, 48 bits virtual, configurable
2634 * physical bits.
2635 */
2636 *eax = 0x00003000 + cpu->phys_bits;
c6dc6f63 2637 } else {
af45907a 2638 *eax = cpu->phys_bits;
c6dc6f63
AP		 2639 }
2640 *ebx = 0;
2641 *ecx = 0;
2642 *edx = 0;
ce3960eb
AF		 2643 if (cs->nr_cores * cs->nr_threads > 1) {
2644 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2645 }
2646 break;
2647 case 0x8000000A:
0514ef2f 2648 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2649 *eax = 0x00000001; /* SVM Revision */
2650 *ebx = 0x00000010; /* nr of ASIDs */
2651 *ecx = 0;
0514ef2f 2652 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2653 } else {
2654 *eax = 0;
2655 *ebx = 0;
2656 *ecx = 0;
2657 *edx = 0;
2658 }
c6dc6f63 2659 break;
b3baa152
BW		 2660 case 0xC0000000:
2661 *eax = env->cpuid_xlevel2;
2662 *ebx = 0;
2663 *ecx = 0;
2664 *edx = 0;
2665 break;
2666 case 0xC0000001:
2667 /* Support for VIA CPU's CPUID instruction */
2668 *eax = env->cpuid_version;
2669 *ebx = 0;
2670 *ecx = 0;
0514ef2f 2671 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2672 break;
2673 case 0xC0000002:
2674 case 0xC0000003:
2675 case 0xC0000004:
2676 /* Reserved for the future, and now filled with zero */
2677 *eax = 0;
2678 *ebx = 0;
2679 *ecx = 0;
2680 *edx = 0;
2681 break;
c6dc6f63
AP		 2682 default:
2683 /* reserved values: zero */
2684 *eax = 0;
2685 *ebx = 0;
2686 *ecx = 0;
2687 *edx = 0;
2688 break;
2689 }
2690}
5fd2087a
AF		 2691
2692/* CPUClass::reset() */
2693static void x86_cpu_reset(CPUState *s)
2694{
2695 X86CPU *cpu = X86_CPU(s);
2696 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2697 CPUX86State *env = &cpu->env;
a114d25d
RH		 2698 target_ulong cr4;
2699 uint64_t xcr0;
c1958aea
AF		 2700 int i;
2701
5fd2087a
AF		 2702 xcc->parent_reset(s);
2703
5e992a8e 2704 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 2705
00c8cb0a 2706 tlb_flush(s, 1);
c1958aea
AF		 2707
2708 env->old_exception = -1;
2709
2710 /* init to reset state */
2711
c1958aea
AF		 2712 env->hflags2 |= HF2_GIF_MASK;
2713
2714 cpu_x86_update_cr0(env, 0x60000010);
2715 env->a20_mask = ~0x0;
2716 env->smbase = 0x30000;
2717
2718 env->idt.limit = 0xffff;
2719 env->gdt.limit = 0xffff;
2720 env->ldt.limit = 0xffff;
2721 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2722 env->tr.limit = 0xffff;
2723 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2724
2725 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2726 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2727 DESC_R_MASK | DESC_A_MASK);
2728 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2729 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2730 DESC_A_MASK);
2731 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2732 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2733 DESC_A_MASK);
2734 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2735 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2736 DESC_A_MASK);
2737 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2738 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2739 DESC_A_MASK);
2740 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2741 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2742 DESC_A_MASK);
2743
2744 env->eip = 0xfff0;
2745 env->regs[R_EDX] = env->cpuid_version;
2746
2747 env->eflags = 0x2;
2748
2749 /* FPU init */
2750 for (i = 0; i < 8; i++) {
2751 env->fptags[i] = 1;
2752 }
5bde1407 2753 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2754
2755 env->mxcsr = 0x1f80;
a114d25d
RH		 2756 /* All units are in INIT state. */
2757 env->xstate_bv = 0;
c1958aea
AF		 2758
2759 env->pat = 0x0007040600070406ULL;
2760 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2761
2762 memset(env->dr, 0, sizeof(env->dr));
2763 env->dr[6] = DR6_FIXED_1;
2764 env->dr[7] = DR7_FIXED_1;
b3310ab3 2765 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2766 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2767
a114d25d 2768 cr4 = 0;
cfc3b074 2769 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 2770
2771#ifdef CONFIG_USER_ONLY
2772 /* Enable all the features for user-mode. */
2773 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 2774 xcr0 |= XSTATE_SSE_MASK;
a114d25d 2775 }
0f70ed47
PB		 2776 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2777 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 2778 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 2779 xcr0 |= 1ull << i;
2780 }
a114d25d 2781 }
0f70ed47 2782
a114d25d
RH		 2783 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2784 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2785 }
07929f2a
RH		 2786 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2787 cr4 |= CR4_FSGSBASE_MASK;
2788 }
a114d25d
RH		 2789#endif
2790
2791 env->xcr0 = xcr0;
2792 cpu_x86_update_cr4(env, cr4);
0522604b 2793
9db2efd9
AW		 2794 /*
2795 * SDM 11.11.5 requires:
2796 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2797 * - IA32_MTRR_PHYSMASKn.V = 0
2798 * All other bits are undefined. For simplification, zero it all.
2799 */
2800 env->mtrr_deftype = 0;
2801 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2802 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2803
dd673288
IM		 2804#if !defined(CONFIG_USER_ONLY)
2805 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2806 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2807
259186a7 2808 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2809
2810 if (kvm_enabled()) {
2811 kvm_arch_reset_vcpu(cpu);
2812 }
dd673288 2813#endif
5fd2087a
AF		 2814}
2815
dd673288
IM		 2816#ifndef CONFIG_USER_ONLY
2817bool cpu_is_bsp(X86CPU *cpu)
2818{
02e51483 2819 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2820}
65dee380
IM		 2821
2822/* TODO: remove me, when reset over QOM tree is implemented */
2823static void x86_cpu_machine_reset_cb(void *opaque)
2824{
2825 X86CPU *cpu = opaque;
2826 cpu_reset(CPU(cpu));
2827}
dd673288
IM		 2828#endif
2829
de024815
AF		 2830static void mce_init(X86CPU *cpu)
2831{
2832 CPUX86State *cenv = &cpu->env;
2833 unsigned int bank;
2834
2835 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2836 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 2837 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 2838 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
2839 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 2840 cenv->mcg_ctl = ~(uint64_t)0;
2841 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2842 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2843 }
2844 }
2845}
2846
bdeec802 2847#ifndef CONFIG_USER_ONLY
d3c64d6a 2848static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2849{
449994eb 2850 APICCommonState *apic;
bdeec802
IM		 2851 const char *apic_type = "apic";
2852
15eafc2e 2853 if (kvm_apic_in_kernel()) {
bdeec802
IM		 2854 apic_type = "kvm-apic";
2855 } else if (xen_enabled()) {
2856 apic_type = "xen-apic";
2857 }
2858
46232aaa 2859 cpu->apic_state = DEVICE(object_new(apic_type));
bdeec802 2860
6816b1b3
IM		 2861 object_property_add_child(OBJECT(cpu), "lapic",
2862 OBJECT(cpu->apic_state), &error_abort);
67e55caa 2863 object_unref(OBJECT(cpu->apic_state));
6816b1b3 2864
7e72a45c 2865 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2866 /* TODO: convert to link<> */
02e51483 2867 apic = APIC_COMMON(cpu->apic_state);
60671e58 2868 apic->cpu = cpu;
8d42d2d3 2869 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 2870}
2871
2872static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2873{
8d42d2d3
CF		 2874 APICCommonState *apic;
2875 static bool apic_mmio_map_once;
2876
02e51483 2877 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2878 return;
2879 }
6e8e2651
MA		 2880 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2881 errp);
8d42d2d3
CF		 2882
2883 /* Map APIC MMIO area */
2884 apic = APIC_COMMON(cpu->apic_state);
2885 if (!apic_mmio_map_once) {
2886 memory_region_add_subregion_overlap(get_system_memory(),
2887 apic->apicbase &
2888 MSR_IA32_APICBASE_BASE,
2889 &apic->io_memory,
2890 0x1000);
2891 apic_mmio_map_once = true;
2892 }
bdeec802 2893}
f809c605
PB		 2894
2895static void x86_cpu_machine_done(Notifier *n, void *unused)
2896{
2897 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2898 MemoryRegion *smram =
2899 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2900
2901 if (smram) {
2902 cpu->smram = g_new(MemoryRegion, 1);
2903 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2904 smram, 0, 1ull << 32);
2905 memory_region_set_enabled(cpu->smram, false);
2906 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2907 }
2908}
d3c64d6a
IM		 2909#else
2910static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2911{
2912}
bdeec802
IM		 2913#endif
2914
11f6fee5
DDAG		 2915/* Note: Only safe for use on x86(-64) hosts */
2916static uint32_t x86_host_phys_bits(void)
2917{
2918 uint32_t eax;
2919 uint32_t host_phys_bits;
2920
2921 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
2922 if (eax >= 0x80000008) {
2923 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
2924 /* Note: According to AMD doc 25481 rev 2.34 they have a field
2925 * at 23:16 that can specify a maximum physical address bits for
2926 * the guest that can override this value; but I've not seen
2927 * anything with that set.
2928 */
2929 host_phys_bits = eax & 0xff;
2930 } else {
2931 /* It's an odd 64 bit machine that doesn't have the leaf for
2932 * physical address bits; fall back to 36 that's most older
2933 * Intel.
2934 */
2935 host_phys_bits = 36;
2936 }
2937
2938 return host_phys_bits;
2939}
e48638fd 2940
c39c0edf
EH		 2941static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
2942{
2943 if (*min < value) {
2944 *min = value;
2945 }
2946}
2947
2948/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
2949static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
2950{
2951 CPUX86State *env = &cpu->env;
2952 FeatureWordInfo *fi = &feature_word_info[w];
2953 uint32_t eax = fi->cpuid_eax;
2954 uint32_t region = eax & 0xF0000000;
2955
2956 if (!env->features[w]) {
2957 return;
2958 }
2959
2960 switch (region) {
2961 case 0x00000000:
2962 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
2963 break;
2964 case 0x80000000:
2965 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
2966 break;
2967 case 0xC0000000:
2968 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
2969 break;
2970 }
2971}
2972
2ca8a8be
EH		 2973/* Calculate XSAVE components based on the configured CPU feature flags */
2974static void x86_cpu_enable_xsave_components(X86CPU *cpu)
2975{
2976 CPUX86State *env = &cpu->env;
2977 int i;
96193c22 2978 uint64_t mask;
2ca8a8be
EH		 2979
2980 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
2981 return;
2982 }
2983
96193c22 2984 mask = (XSTATE_FP_MASK | XSTATE_SSE_MASK);
2ca8a8be
EH		 2985 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2986 const ExtSaveArea *esa = &x86_ext_save_areas[i];
2987 if (env->features[esa->feature] & esa->bits) {
96193c22 2988 mask |= (1ULL << i);
2ca8a8be
EH		 2989 }
2990 }
2991
96193c22
EH		 2992 env->features[FEAT_XSAVE_COMP_LO] = mask;
2993 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 2994}
2995
e48638fd
WH		 2996#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2997 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2998 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2999#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3000 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3001 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 3002static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 3003{
14a10fc3 3004 CPUState *cs = CPU(dev);
2b6f294c
AF		 3005 X86CPU *cpu = X86_CPU(dev);
3006 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 3007 CPUX86State *env = &cpu->env;
2b6f294c 3008 Error *local_err = NULL;
e48638fd 3009 static bool ht_warned;
dc15c051 3010 FeatureWord w;
b34d12d1 3011
104494ea
IM		 3012 if (xcc->kvm_required && !kvm_enabled()) {
3013 char *name = x86_cpu_class_get_model_name(xcc);
3014 error_setg(&local_err, "CPU model '%s' requires KVM", name);
3015 g_free(name);
3016 goto out;
3017 }
3018
d9c84f19 3019 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
9886e834
EH		 3020 error_setg(errp, "apic-id property was not initialized properly");
3021 return;
3022 }
3023
dc15c051
IM		 3024 /*TODO: cpu->host_features incorrectly overwrites features
3025 * set using "feat=on|off". Once we fix this, we can convert
3026 * plus_features & minus_features to global properties
3027 * inside x86_cpu_parse_featurestr() too.
3028 */
3029 if (cpu->host_features) {
3030 for (w = 0; w < FEATURE_WORDS; w++) {
3031 env->features[w] =
3032 x86_cpu_get_supported_feature_word(w, cpu->migratable);
3033 }
3034 }
3035
3036 for (w = 0; w < FEATURE_WORDS; w++) {
3037 cpu->env.features[w] |= plus_features[w];
3038 cpu->env.features[w] &= ~minus_features[w];
3039 }
3040
aec661de
EH		 3041 if (!kvm_enabled() || !cpu->expose_kvm) {
3042 env->features[FEAT_KVM] = 0;
3043 }
3044
2ca8a8be 3045 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 3046
3047 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3048 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
3049 if (cpu->full_cpuid_auto_level) {
3050 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
3051 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
3052 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
3053 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
3054 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
3055 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
3056 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
3057 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
3058 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
3059 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 3060 /* SVM requires CPUID[0x8000000A] */
3061 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
3062 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
3063 }
c39c0edf
EH		 3064 }
3065
3066 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3067 if (env->cpuid_level == UINT32_MAX) {
3068 env->cpuid_level = env->cpuid_min_level;
3069 }
3070 if (env->cpuid_xlevel == UINT32_MAX) {
3071 env->cpuid_xlevel = env->cpuid_min_xlevel;
3072 }
3073 if (env->cpuid_xlevel2 == UINT32_MAX) {
3074 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 3075 }
7a059953 3076
9997cf7b
EH		 3077 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
3078 error_setg(&local_err,
3079 kvm_enabled() ?
3080 "Host doesn't support requested features" :
3081 "TCG doesn't support requested features");
3082 goto out;
3083 }
3084
9b15cd9e
IM		 3085 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3086 * CPUID[1].EDX.
3087 */
e48638fd 3088 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 3089 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3090 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 3091 & CPUID_EXT2_AMD_ALIASES);
3092 }
3093
11f6fee5
DDAG		 3094 /* For 64bit systems think about the number of physical bits to present.
3095 * ideally this should be the same as the host; anything other than matching
3096 * the host can cause incorrect guest behaviour.
3097 * QEMU used to pick the magic value of 40 bits that corresponds to
3098 * consumer AMD devices but nothing else.
3099 */
af45907a 3100 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a 3101 if (kvm_enabled()) {
11f6fee5
DDAG		 3102 uint32_t host_phys_bits = x86_host_phys_bits();
3103 static bool warned;
3104
3105 if (cpu->host_phys_bits) {
3106 /* The user asked for us to use the host physical bits */
3107 cpu->phys_bits = host_phys_bits;
3108 }
3109
3110 /* Print a warning if the user set it to a value that's not the
3111 * host value.
3112 */
3113 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3114 !warned) {
3115 error_report("Warning: Host physical bits (%u)"
3116 " does not match phys-bits property (%u)",
3117 host_phys_bits, cpu->phys_bits);
3118 warned = true;
3119 }
3120
3121 if (cpu->phys_bits &&
3122 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3123 cpu->phys_bits < 32)) {
af45907a
DDAG		 3124 error_setg(errp, "phys-bits should be between 32 and %u "
3125 " (but is %u)",
3126 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3127 return;
3128 }
3129 } else {
11f6fee5 3130 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 3131 error_setg(errp, "TCG only supports phys-bits=%u",
3132 TCG_PHYS_ADDR_BITS);
3133 return;
3134 }
3135 }
11f6fee5
DDAG		 3136 /* 0 means it was not explicitly set by the user (or by machine
3137 * compat_props or by the host code above). In this case, the default
3138 * is the value used by TCG (40).
3139 */
3140 if (cpu->phys_bits == 0) {
3141 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3142 }
af45907a
DDAG		 3143 } else {
3144 /* For 32 bit systems don't use the user set value, but keep
3145 * phys_bits consistent with what we tell the guest.
3146 */
3147 if (cpu->phys_bits != 0) {
3148 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3149 return;
3150 }
fefb41bf 3151
af45907a
DDAG		 3152 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3153 cpu->phys_bits = 36;
3154 } else {
3155 cpu->phys_bits = 32;
3156 }
3157 }
42ecabaa
EH		 3158 cpu_exec_init(cs, &error_abort);
3159
57f2453a
EH		 3160 if (tcg_enabled()) {
3161 tcg_x86_init();
3162 }
3163
65dee380
IM		 3164#ifndef CONFIG_USER_ONLY
3165 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 3166
0514ef2f 3167 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 3168 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 3169 if (local_err != NULL) {
4dc1f449 3170 goto out;
bdeec802
IM		 3171 }
3172 }
65dee380
IM		 3173#endif
3174
7a059953 3175 mce_init(cpu);
2001d0cd
PB		 3176
3177#ifndef CONFIG_USER_ONLY
3178 if (tcg_enabled()) {
56943e8c
PM		 3179 AddressSpace *newas = g_new(AddressSpace, 1);
3180
f809c605 3181 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 3182 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 3183
3184 /* Outer container... */
3185 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 3186 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 3187
3188 /* ... with two regions inside: normal system memory with low
3189 * priority, and...
3190 */
3191 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3192 get_system_memory(), 0, ~0ull);
3193 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3194 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 3195 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 3196 cs->num_ases = 1;
56943e8c 3197 cpu_address_space_init(cs, newas, 0);
f809c605
PB		 3198
3199 /* ... SMRAM with higher priority, linked from /machine/smram. */
3200 cpu->machine_done.notify = x86_cpu_machine_done;
3201 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 3202 }
3203#endif
3204
14a10fc3 3205 qemu_init_vcpu(cs);
d3c64d6a 3206
e48638fd
WH		 3207 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3208 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3209 * based on inputs (sockets,cores,threads), it is still better to gives
3210 * users a warning.
3211 *
3212 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3213 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3214 */
3215 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3216 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3217 " -smp options properly.");
3218 ht_warned = true;
3219 }
3220
d3c64d6a
IM		 3221 x86_cpu_apic_realize(cpu, &local_err);
3222 if (local_err != NULL) {
3223 goto out;
3224 }
14a10fc3 3225 cpu_reset(cs);
2b6f294c 3226
4dc1f449 3227 xcc->parent_realize(dev, &local_err);
2001d0cd 3228
4dc1f449
IM		 3229out:
3230 if (local_err != NULL) {
3231 error_propagate(errp, local_err);
3232 return;
3233 }
7a059953
AF		 3234}
3235
c884776e
IM		 3236static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3237{
3238 X86CPU *cpu = X86_CPU(dev);
3239
3240#ifndef CONFIG_USER_ONLY
3241 cpu_remove_sync(CPU(dev));
3242 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3243#endif
3244
3245 if (cpu->apic_state) {
3246 object_unparent(OBJECT(cpu->apic_state));
3247 cpu->apic_state = NULL;
3248 }
3249}
3250
38e5c119
EH		 3251typedef struct BitProperty {
3252 uint32_t *ptr;
3253 uint32_t mask;
3254} BitProperty;
3255
d7bce999
EB		 3256static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3257 void *opaque, Error **errp)
38e5c119
EH		 3258{
3259 BitProperty *fp = opaque;
3260 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 3261 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3262}
3263
d7bce999
EB		 3264static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3265 void *opaque, Error **errp)
38e5c119
EH		 3266{
3267 DeviceState *dev = DEVICE(obj);
3268 BitProperty *fp = opaque;
3269 Error *local_err = NULL;
3270 bool value;
3271
3272 if (dev->realized) {
3273 qdev_prop_set_after_realize(dev, name, errp);
3274 return;
3275 }
3276
51e72bc1 3277 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3278 if (local_err) {
3279 error_propagate(errp, local_err);
3280 return;
3281 }
3282
3283 if (value) {
3284 *fp->ptr |= fp->mask;
3285 } else {
3286 *fp->ptr &= ~fp->mask;
3287 }
3288}
3289
3290static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3291 void *opaque)
3292{
3293 BitProperty *prop = opaque;
3294 g_free(prop);
3295}
3296
3297/* Register a boolean property to get/set a single bit in a uint32_t field.
3298 *
3299 * The same property name can be registered multiple times to make it affect
3300 * multiple bits in the same FeatureWord. In that case, the getter will return
3301 * true only if all bits are set.
3302 */
3303static void x86_cpu_register_bit_prop(X86CPU *cpu,
3304 const char *prop_name,
3305 uint32_t *field,
3306 int bitnr)
3307{
3308 BitProperty *fp;
3309 ObjectProperty *op;
3310 uint32_t mask = (1UL << bitnr);
3311
3312 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3313 if (op) {
3314 fp = op->opaque;
3315 assert(fp->ptr == field);
3316 fp->mask |= mask;
3317 } else {
3318 fp = g_new0(BitProperty, 1);
3319 fp->ptr = field;
3320 fp->mask = mask;
3321 object_property_add(OBJECT(cpu), prop_name, "bool",
3322 x86_cpu_get_bit_prop,
3323 x86_cpu_set_bit_prop,
3324 x86_cpu_release_bit_prop, fp, &error_abort);
3325 }
3326}
3327
3328static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3329 FeatureWord w,
3330 int bitnr)
3331{
3332 Object *obj = OBJECT(cpu);
3333 int i;
3334 char **names;
3335 FeatureWordInfo *fi = &feature_word_info[w];
3336
38e5c119
EH		 3337 if (!fi->feat_names[bitnr]) {
3338 return;
3339 }
3340
3341 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
3342
3343 feat2prop(names[0]);
3344 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
3345
3346 for (i = 1; names[i]; i++) {
3347 feat2prop(names[i]);
d461a44c 3348 object_property_add_alias(obj, names[i], obj, names[0],
38e5c119
EH		 3349 &error_abort);
3350 }
3351
3352 g_strfreev(names);
3353}
3354
de024815
AF		 3355static void x86_cpu_initfn(Object *obj)
3356{
55e5c285 3357 CPUState *cs = CPU(obj);
de024815 3358 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3359 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3360 CPUX86State *env = &cpu->env;
38e5c119 3361 FeatureWord w;
de024815 3362
c05efcb1 3363 cs->env_ptr = env;
71ad61d3
AF		 3364
3365 object_property_add(obj, "family", "int",
95b8519d 3366 x86_cpuid_version_get_family,
71ad61d3 3367 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3368 object_property_add(obj, "model", "int",
67e30c83 3369 x86_cpuid_version_get_model,
c5291a4f 3370 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3371 object_property_add(obj, "stepping", "int",
35112e41 3372 x86_cpuid_version_get_stepping,
036e2222 3373 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3374 object_property_add_str(obj, "vendor",
3375 x86_cpuid_get_vendor,
3376 x86_cpuid_set_vendor, NULL);
938d4c25 3377 object_property_add_str(obj, "model-id",
63e886eb 3378 x86_cpuid_get_model_id,
938d4c25 3379 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3380 object_property_add(obj, "tsc-frequency", "int",
3381 x86_cpuid_get_tsc_freq,
3382 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 3383 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3384 x86_cpu_get_feature_words,
7e5292b5
EH		 3385 NULL, NULL, (void *)env->features, NULL);
3386 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3387 x86_cpu_get_feature_words,
3388 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3389
92067bf4 3390 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3391
38e5c119
EH		 3392 for (w = 0; w < FEATURE_WORDS; w++) {
3393 int bitnr;
3394
3395 for (bitnr = 0; bitnr < 32; bitnr++) {
3396 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3397 }
3398 }
3399
d940ee9b 3400 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
de024815
AF		 3401}
3402
997395d3
IM		 3403static int64_t x86_cpu_get_arch_id(CPUState *cs)
3404{
3405 X86CPU *cpu = X86_CPU(cs);
997395d3 3406
7e72a45c 3407 return cpu->apic_id;
997395d3
IM		 3408}
3409
444d5590
AF		 3410static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3411{
3412 X86CPU *cpu = X86_CPU(cs);
3413
3414 return cpu->env.cr[0] & CR0_PG_MASK;
3415}
3416
f45748f1
AF		 3417static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3418{
3419 X86CPU *cpu = X86_CPU(cs);
3420
3421 cpu->env.eip = value;
3422}
3423
bdf7ae5b
AF		 3424static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3425{
3426 X86CPU *cpu = X86_CPU(cs);
3427
3428 cpu->env.eip = tb->pc - tb->cs_base;
3429}
3430
8c2e1b00
AF		 3431static bool x86_cpu_has_work(CPUState *cs)
3432{
3433 X86CPU *cpu = X86_CPU(cs);
3434 CPUX86State *env = &cpu->env;
3435
6220e900
PD		 3436 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3437 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3438 (env->eflags & IF_MASK)) ||
3439 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3440 CPU_INTERRUPT_INIT |
3441 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3442 CPU_INTERRUPT_MCE)) ||
3443 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3444 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3445}
3446
9337e3b6 3447static Property x86_cpu_properties[] = {
2da00e31
IM		 3448#ifdef CONFIG_USER_ONLY
3449 /* apic_id = 0 by default for *-user, see commit 9886e834 */
3450 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 3451 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
3452 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
3453 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 3454#else
3455 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 3456 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
3457 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
3458 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 3459#endif
9337e3b6 3460 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3461 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3462 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3463 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3464 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3465 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3466 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3467 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3468 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3469 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3470 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3471 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3472 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3473 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 3474 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 3475 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 3476 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 3477 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
3478 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
3479 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
3480 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
3481 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
3482 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
3483 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 3484 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 3485 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 3486 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 3487 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
9337e3b6
EH		 3488 DEFINE_PROP_END_OF_LIST()
3489};
3490
5fd2087a
AF		 3491static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3492{
3493 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3494 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3495 DeviceClass *dc = DEVICE_CLASS(oc);
3496
3497 xcc->parent_realize = dc->realize;
3498 dc->realize = x86_cpu_realizefn;
c884776e 3499 dc->unrealize = x86_cpu_unrealizefn;
9337e3b6 3500 dc->props = x86_cpu_properties;
5fd2087a
AF		 3501
3502 xcc->parent_reset = cc->reset;
3503 cc->reset = x86_cpu_reset;
91b1df8c 3504 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3505
500050d1 3506 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3507 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3508 cc->has_work = x86_cpu_has_work;
97a8ea5a 3509 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3510 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3511 cc->dump_state = x86_cpu_dump_state;
f45748f1 3512 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3513 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3514 cc->gdb_read_register = x86_cpu_gdb_read_register;
3515 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3516 cc->get_arch_id = x86_cpu_get_arch_id;
3517 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3518#ifdef CONFIG_USER_ONLY
3519 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3520#else
a23bbfda 3521 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3522 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3523 cc->write_elf64_note = x86_cpu_write_elf64_note;
3524 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3525 cc->write_elf32_note = x86_cpu_write_elf32_note;
3526 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3527 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3528#endif
a0e372f0 3529 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3530#ifndef CONFIG_USER_ONLY
3531 cc->debug_excp_handler = breakpoint_handler;
3532#endif
374e0cd4
RH		 3533 cc->cpu_exec_enter = x86_cpu_exec_enter;
3534 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27 3535
edd12111 3536 dc->cannot_instantiate_with_device_add_yet = false;
4c315c27
MA		 3537 /*
3538 * Reason: x86_cpu_initfn() calls cpu_exec_init(), which saves the
3539 * object in cpus -> dangling pointer after final object_unref().
3540 */
3541 dc->cannot_destroy_with_object_finalize_yet = true;
5fd2087a
AF		 3542}
3543
3544static const TypeInfo x86_cpu_type_info = {
3545 .name = TYPE_X86_CPU,
3546 .parent = TYPE_CPU,
3547 .instance_size = sizeof(X86CPU),
de024815 3548 .instance_init = x86_cpu_initfn,
d940ee9b 3549 .abstract = true,
5fd2087a
AF		 3550 .class_size = sizeof(X86CPUClass),
3551 .class_init = x86_cpu_common_class_init,
3552};
3553
3554static void x86_cpu_register_types(void)
3555{
d940ee9b
EH		 3556 int i;
3557
5fd2087a 3558 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3559 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3560 x86_register_cpudef_type(&builtin_x86_defs[i]);
3561 }
3562#ifdef CONFIG_KVM
3563 type_register_static(&host_x86_cpu_type_info);
3564#endif
5fd2087a
AF		 3565}
3566
3567type_init(x86_cpu_register_types)
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