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target-i386: List CPU models using subclass list
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
b834b508 38#if defined(CONFIG_KVM)
ef8621b1 39#include <linux/kvm_para.h>
b834b508 40#endif
65dee380 41
9c17d615 42#include "sysemu/sysemu.h"
53a89e26 43#include "hw/qdev-properties.h"
5232d00a 44#include "hw/i386/topology.h"
bdeec802 45#ifndef CONFIG_USER_ONLY
2001d0cd 46#include "exec/address-spaces.h"
741da0d3 47#include "hw/hw.h"
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
14c985cf 60#define CPUID_2_L3_16MB_16WAY_64B 0x4d
5e891bf8
EH		 61
62
63/* CPUID Leaf 4 constants: */
64
65/* EAX: */
66#define CPUID_4_TYPE_DCACHE 1
67#define CPUID_4_TYPE_ICACHE 2
68#define CPUID_4_TYPE_UNIFIED 3
69
70#define CPUID_4_LEVEL(l) ((l) << 5)
71
72#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73#define CPUID_4_FULLY_ASSOC (1 << 9)
74
75/* EDX: */
76#define CPUID_4_NO_INVD_SHARING (1 << 0)
77#define CPUID_4_INCLUSIVE (1 << 1)
78#define CPUID_4_COMPLEX_IDX (1 << 2)
79
80#define ASSOC_FULL 0xFF
81
82/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
84 a == 2 ? 0x2 : \
85 a == 4 ? 0x4 : \
86 a == 8 ? 0x6 : \
87 a == 16 ? 0x8 : \
88 a == 32 ? 0xA : \
89 a == 48 ? 0xB : \
90 a == 64 ? 0xC : \
91 a == 96 ? 0xD : \
92 a == 128 ? 0xE : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
95
96
97/* Definitions of the hardcoded cache entries we expose: */
98
99/* L1 data cache: */
100#define L1D_LINE_SIZE 64
101#define L1D_ASSOCIATIVITY 8
102#define L1D_SETS 64
103#define L1D_PARTITIONS 1
104/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107#define L1D_LINES_PER_TAG 1
108#define L1D_SIZE_KB_AMD 64
109#define L1D_ASSOCIATIVITY_AMD 2
110
111/* L1 instruction cache: */
112#define L1I_LINE_SIZE 64
113#define L1I_ASSOCIATIVITY 8
114#define L1I_SETS 64
115#define L1I_PARTITIONS 1
116/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119#define L1I_LINES_PER_TAG 1
120#define L1I_SIZE_KB_AMD 64
121#define L1I_ASSOCIATIVITY_AMD 2
122
123/* Level 2 unified cache: */
124#define L2_LINE_SIZE 64
125#define L2_ASSOCIATIVITY 16
126#define L2_SETS 4096
127#define L2_PARTITIONS 1
128/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132#define L2_LINES_PER_TAG 1
133#define L2_SIZE_KB_AMD 512
134
14c985cf 135/* Level 3 unified cache: */
5e891bf8
EH		 136#define L3_SIZE_KB 0 /* disabled */
137#define L3_ASSOCIATIVITY 0 /* disabled */
138#define L3_LINES_PER_TAG 0 /* disabled */
139#define L3_LINE_SIZE 0 /* disabled */
14c985cf
LM		 140#define L3_N_LINE_SIZE 64
141#define L3_N_ASSOCIATIVITY 16
142#define L3_N_SETS 16384
143#define L3_N_PARTITIONS 1
144#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
145#define L3_N_LINES_PER_TAG 1
146#define L3_N_SIZE_KB_AMD 16384
5e891bf8
EH		 147
148/* TLB definitions: */
149
150#define L1_DTLB_2M_ASSOC 1
151#define L1_DTLB_2M_ENTRIES 255
152#define L1_DTLB_4K_ASSOC 1
153#define L1_DTLB_4K_ENTRIES 255
154
155#define L1_ITLB_2M_ASSOC 1
156#define L1_ITLB_2M_ENTRIES 255
157#define L1_ITLB_4K_ASSOC 1
158#define L1_ITLB_4K_ENTRIES 255
159
160#define L2_DTLB_2M_ASSOC 0 /* disabled */
161#define L2_DTLB_2M_ENTRIES 0 /* disabled */
162#define L2_DTLB_4K_ASSOC 4
163#define L2_DTLB_4K_ENTRIES 512
164
165#define L2_ITLB_2M_ASSOC 0 /* disabled */
166#define L2_ITLB_2M_ENTRIES 0 /* disabled */
167#define L2_ITLB_4K_ASSOC 4
168#define L2_ITLB_4K_ENTRIES 512
169
170
171
99b88a17
IM		 172static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
173 uint32_t vendor2, uint32_t vendor3)
174{
175 int i;
176 for (i = 0; i < 4; i++) {
177 dst[i] = vendor1 >> (8 * i);
178 dst[i + 4] = vendor2 >> (8 * i);
179 dst[i + 8] = vendor3 >> (8 * i);
180 }
181 dst[CPUID_VENDOR_SZ] = '\0';
182}
183
621626ce
EH		 184#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
185#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
186 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
187#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
188 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
189 CPUID_PSE36 | CPUID_FXSR)
190#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
191#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
192 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
193 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
194 CPUID_PAE | CPUID_SEP | CPUID_APIC)
195
196#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
197 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
198 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
199 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 200 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 201 /* partly implemented:
202 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
203 /* missing:
204 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
205#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
206 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
207 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 208 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 209 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
210 /* missing:
211 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
212 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
213 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 214 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
215 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 216
217#ifdef TARGET_X86_64
218#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
219#else
220#define TCG_EXT2_X86_64_FEATURES 0
221#endif
222
223#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
224 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
225 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
226 TCG_EXT2_X86_64_FEATURES)
227#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
228 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
229#define TCG_EXT4_FEATURES 0
230#define TCG_SVM_FEATURES 0
231#define TCG_KVM_FEATURES 0
232#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 233 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
234 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 235 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
236 CPUID_7_0_EBX_ERMS)
621626ce 237 /* missing:
07929f2a 238 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 239 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 240 CPUID_7_0_EBX_RDSEED */
0f70ed47 241#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
303752a9 242#define TCG_APM_FEATURES 0
28b8e4d0 243#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 244#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
245 /* missing:
246 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 247
5ef57876 248typedef struct FeatureWordInfo {
2d5312da
EH		 249 /* feature flags names are taken from "Intel Processor Identification and
250 * the CPUID Instruction" and AMD's "CPUID Specification".
251 * In cases of disagreement between feature naming conventions,
252 * aliases may be added.
253 */
254 const char *feat_names[32];
04d104b6
EH		 255 uint32_t cpuid_eax; /* Input EAX for CPUID */
256 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
257 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
258 int cpuid_reg; /* output register (R_* constant) */
37ce3522 259 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 260 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 261 uint32_t migratable_flags; /* Feature flags known to be migratable */
5ef57876
EH		 262} FeatureWordInfo;
263
264static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 265 [FEAT_1_EDX] = {
2d5312da
EH		 266 .feat_names = {
267 "fpu", "vme", "de", "pse",
268 "tsc", "msr", "pae", "mce",
269 "cx8", "apic", NULL, "sep",
270 "mtrr", "pge", "mca", "cmov",
271 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
272 NULL, "ds" /* Intel dts */, "acpi", "mmx",
273 "fxsr", "sse", "sse2", "ss",
274 "ht" /* Intel htt */, "tm", "ia64", "pbe",
275 },
bffd67b0 276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 277 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 278 },
279 [FEAT_1_ECX] = {
2d5312da
EH		 280 .feat_names = {
281 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
282 "ds_cpl", "vmx", "smx", "est",
283 "tm2", "ssse3", "cid", NULL,
284 "fma", "cx16", "xtpr", "pdcm",
285 NULL, "pcid", "dca", "sse4.1|sse4_1",
286 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
287 "tsc-deadline", "aes", "xsave", "osxsave",
288 "avx", "f16c", "rdrand", "hypervisor",
289 },
bffd67b0 290 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 291 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 292 },
2d5312da
EH		 293 /* Feature names that are already defined on feature_name[] but
294 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
295 * names on feat_names below. They are copied automatically
296 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
297 */
bffd67b0 298 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 299 .feat_names = {
300 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
301 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
302 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
303 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
304 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
305 "nx|xd", NULL, "mmxext", NULL /* mmx */,
306 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb", "rdtscp",
307 NULL, "lm|i64", "3dnowext", "3dnow",
308 },
bffd67b0 309 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 310 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 311 },
312 [FEAT_8000_0001_ECX] = {
2d5312da
EH		 313 .feat_names = {
314 "lahf_lm", "cmp_legacy", "svm", "extapic",
315 "cr8legacy", "abm", "sse4a", "misalignsse",
316 "3dnowprefetch", "osvw", "ibs", "xop",
317 "skinit", "wdt", NULL, "lwp",
318 "fma4", "tce", NULL, "nodeid_msr",
319 NULL, "tbm", "topoext", "perfctr_core",
320 "perfctr_nb", NULL, NULL, NULL,
321 NULL, NULL, NULL, NULL,
322 },
bffd67b0 323 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 324 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 325 },
89e49c8b 326 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 327 .feat_names = {
328 NULL, NULL, "xstore", "xstore-en",
329 NULL, NULL, "xcrypt", "xcrypt-en",
330 "ace2", "ace2-en", "phe", "phe-en",
331 "pmm", "pmm-en", NULL, NULL,
332 NULL, NULL, NULL, NULL,
333 NULL, NULL, NULL, NULL,
334 NULL, NULL, NULL, NULL,
335 NULL, NULL, NULL, NULL,
336 },
89e49c8b 337 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 338 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 339 },
bffd67b0 340 [FEAT_KVM] = {
2d5312da
EH		 341 .feat_names = {
342 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
343 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
344 NULL, NULL, NULL, NULL,
345 NULL, NULL, NULL, NULL,
346 NULL, NULL, NULL, NULL,
347 NULL, NULL, NULL, NULL,
348 "kvmclock-stable-bit", NULL, NULL, NULL,
349 NULL, NULL, NULL, NULL,
350 },
bffd67b0 351 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 352 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 353 },
c35bd19a 354 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 355 .feat_names = {
356 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
357 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
358 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
359 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
360 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
361 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
362 NULL, NULL, NULL, NULL,
363 NULL, NULL, NULL, NULL,
364 NULL, NULL, NULL, NULL,
365 NULL, NULL, NULL, NULL,
366 NULL, NULL, NULL, NULL,
367 },
c35bd19a
EY		 368 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
369 },
370 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 371 .feat_names = {
372 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
373 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
374 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
375 NULL /* hv_create_port */, NULL /* hv_connect_port */,
376 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
377 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
378 NULL, NULL,
379 NULL, NULL, NULL, NULL,
380 NULL, NULL, NULL, NULL,
381 NULL, NULL, NULL, NULL,
382 NULL, NULL, NULL, NULL,
383 },
c35bd19a
EY		 384 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
385 },
386 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 387 .feat_names = {
388 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
389 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
390 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
391 NULL, NULL,
392 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
393 NULL, NULL, NULL, NULL,
394 NULL, NULL, NULL, NULL,
395 NULL, NULL, NULL, NULL,
396 NULL, NULL, NULL, NULL,
397 NULL, NULL, NULL, NULL,
398 },
c35bd19a
EY		 399 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
400 },
bffd67b0 401 [FEAT_SVM] = {
2d5312da
EH		 402 .feat_names = {
403 "npt", "lbrv", "svm_lock", "nrip_save",
404 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
405 NULL, NULL, "pause_filter", NULL,
406 "pfthreshold", NULL, NULL, NULL,
407 NULL, NULL, NULL, NULL,
408 NULL, NULL, NULL, NULL,
409 NULL, NULL, NULL, NULL,
410 NULL, NULL, NULL, NULL,
411 },
bffd67b0 412 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 413 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 414 },
415 [FEAT_7_0_EBX] = {
2d5312da
EH		 416 .feat_names = {
417 "fsgsbase", "tsc_adjust", NULL, "bmi1",
418 "hle", "avx2", NULL, "smep",
419 "bmi2", "erms", "invpcid", "rtm",
420 NULL, NULL, "mpx", NULL,
421 "avx512f", "avx512dq", "rdseed", "adx",
422 "smap", "avx512ifma", "pcommit", "clflushopt",
423 "clwb", NULL, "avx512pf", "avx512er",
424 "avx512cd", NULL, "avx512bw", "avx512vl",
425 },
04d104b6
EH		 426 .cpuid_eax = 7,
427 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
428 .cpuid_reg = R_EBX,
37ce3522 429 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 430 },
f74eefe0 431 [FEAT_7_0_ECX] = {
2d5312da
EH		 432 .feat_names = {
433 NULL, "avx512vbmi", "umip", "pku",
434 "ospke", NULL, NULL, NULL,
435 NULL, NULL, NULL, NULL,
436 NULL, NULL, NULL, NULL,
437 NULL, NULL, NULL, NULL,
438 NULL, NULL, "rdpid", NULL,
439 NULL, NULL, NULL, NULL,
440 NULL, NULL, NULL, NULL,
441 },
f74eefe0
HH		 442 .cpuid_eax = 7,
443 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
444 .cpuid_reg = R_ECX,
445 .tcg_features = TCG_7_0_ECX_FEATURES,
446 },
303752a9 447 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 448 .feat_names = {
449 NULL, NULL, NULL, NULL,
450 NULL, NULL, NULL, NULL,
451 "invtsc", NULL, NULL, NULL,
452 NULL, NULL, NULL, NULL,
453 NULL, NULL, NULL, NULL,
454 NULL, NULL, NULL, NULL,
455 NULL, NULL, NULL, NULL,
456 NULL, NULL, NULL, NULL,
457 },
303752a9
MT		 458 .cpuid_eax = 0x80000007,
459 .cpuid_reg = R_EDX,
460 .tcg_features = TCG_APM_FEATURES,
461 .unmigratable_flags = CPUID_APM_INVTSC,
462 },
0bb0b2d2 463 [FEAT_XSAVE] = {
2d5312da
EH		 464 .feat_names = {
465 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
466 NULL, NULL, NULL, NULL,
467 NULL, NULL, NULL, NULL,
468 NULL, NULL, NULL, NULL,
469 NULL, NULL, NULL, NULL,
470 NULL, NULL, NULL, NULL,
471 NULL, NULL, NULL, NULL,
472 NULL, NULL, NULL, NULL,
473 },
0bb0b2d2
PB		 474 .cpuid_eax = 0xd,
475 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
476 .cpuid_reg = R_EAX,
c9cfe8f9 477 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 478 },
28b8e4d0 479 [FEAT_6_EAX] = {
2d5312da
EH		 480 .feat_names = {
481 NULL, NULL, "arat", NULL,
482 NULL, NULL, NULL, NULL,
483 NULL, NULL, NULL, NULL,
484 NULL, NULL, NULL, NULL,
485 NULL, NULL, NULL, NULL,
486 NULL, NULL, NULL, NULL,
487 NULL, NULL, NULL, NULL,
488 NULL, NULL, NULL, NULL,
489 },
28b8e4d0
JK		 490 .cpuid_eax = 6, .cpuid_reg = R_EAX,
491 .tcg_features = TCG_6_EAX_FEATURES,
492 },
96193c22
EH		 493 [FEAT_XSAVE_COMP_LO] = {
494 .cpuid_eax = 0xD,
495 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
496 .cpuid_reg = R_EAX,
497 .tcg_features = ~0U,
6fb2fff7
EH		 498 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
499 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
500 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
501 XSTATE_PKRU_MASK,
96193c22
EH		 502 },
503 [FEAT_XSAVE_COMP_HI] = {
504 .cpuid_eax = 0xD,
505 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
506 .cpuid_reg = R_EDX,
507 .tcg_features = ~0U,
508 },
5ef57876
EH		 509};
510
8e8aba50
EH		 511typedef struct X86RegisterInfo32 {
512 /* Name of register */
513 const char *name;
514 /* QAPI enum value register */
515 X86CPURegister32 qapi_enum;
516} X86RegisterInfo32;
517
518#define REGISTER(reg) \
5d371f41 519 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 520static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 521 REGISTER(EAX),
522 REGISTER(ECX),
523 REGISTER(EDX),
524 REGISTER(EBX),
525 REGISTER(ESP),
526 REGISTER(EBP),
527 REGISTER(ESI),
528 REGISTER(EDI),
529};
530#undef REGISTER
531
3f32bd21
RH		 532typedef struct ExtSaveArea {
533 uint32_t feature, bits;
534 uint32_t offset, size;
535} ExtSaveArea;
536
537static const ExtSaveArea x86_ext_save_areas[] = {
cfc3b074
PB		 538 [XSTATE_YMM_BIT] =
539 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 540 .offset = offsetof(X86XSaveArea, avx_state),
541 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 542 [XSTATE_BNDREGS_BIT] =
543 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 544 .offset = offsetof(X86XSaveArea, bndreg_state),
545 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 546 [XSTATE_BNDCSR_BIT] =
547 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 548 .offset = offsetof(X86XSaveArea, bndcsr_state),
549 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 550 [XSTATE_OPMASK_BIT] =
551 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 552 .offset = offsetof(X86XSaveArea, opmask_state),
553 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 554 [XSTATE_ZMM_Hi256_BIT] =
555 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 556 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
557 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 558 [XSTATE_Hi16_ZMM_BIT] =
559 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 560 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
561 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 562 [XSTATE_PKRU_BIT] =
563 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 564 .offset = offsetof(X86XSaveArea, pkru_state),
565 .size = sizeof(XSavePKRU) },
2560f19f 566};
8e8aba50 567
1fda6198
EH		 568static uint32_t xsave_area_size(uint64_t mask)
569{
570 int i;
571 uint64_t ret = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader);
572
573 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
574 const ExtSaveArea *esa = &x86_ext_save_areas[i];
575 if ((mask >> i) & 1) {
576 ret = MAX(ret, esa->offset + esa->size);
577 }
578 }
579 return ret;
580}
581
96193c22
EH		 582static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
583{
584 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
585 cpu->env.features[FEAT_XSAVE_COMP_LO];
586}
587
8b4beddc
EH		 588const char *get_register_name_32(unsigned int reg)
589{
31ccdde2 590 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 591 return NULL;
592 }
8e8aba50 593 return x86_reg_info_32[reg].name;
8b4beddc
EH		 594}
595
84f1b92f
EH		 596/*
597 * Returns the set of feature flags that are supported and migratable by
598 * QEMU, for a given FeatureWord.
599 */
600static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
601{
602 FeatureWordInfo *wi = &feature_word_info[w];
603 uint32_t r = 0;
604 int i;
605
606 for (i = 0; i < 32; i++) {
607 uint32_t f = 1U << i;
6fb2fff7
EH		 608
609 /* If the feature name is known, it is implicitly considered migratable,
610 * unless it is explicitly set in unmigratable_flags */
611 if ((wi->migratable_flags & f) ||
612 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
613 r |= f;
84f1b92f 614 }
84f1b92f
EH		 615 }
616 return r;
617}
618
bb44e0d1
JK		 619void host_cpuid(uint32_t function, uint32_t count,
620 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 621{
a1fd24af
AL		 622 uint32_t vec[4];
623
624#ifdef __x86_64__
625 asm volatile("cpuid"
626 : "=a"(vec[0]), "=b"(vec[1]),
627 "=c"(vec[2]), "=d"(vec[3])
628 : "0"(function), "c"(count) : "cc");
c1f41226 629#elif defined(__i386__)
a1fd24af
AL		 630 asm volatile("pusha \n\t"
631 "cpuid \n\t"
632 "mov %%eax, 0(%2) \n\t"
633 "mov %%ebx, 4(%2) \n\t"
634 "mov %%ecx, 8(%2) \n\t"
635 "mov %%edx, 12(%2) \n\t"
636 "popa"
637 : : "a"(function), "c"(count), "S"(vec)
638 : "memory", "cc");
c1f41226
EH		 639#else
640 abort();
a1fd24af
AL		 641#endif
642
bdde476a 643 if (eax)
a1fd24af 644 *eax = vec[0];
bdde476a 645 if (ebx)
a1fd24af 646 *ebx = vec[1];
bdde476a 647 if (ecx)
a1fd24af 648 *ecx = vec[2];
bdde476a 649 if (edx)
a1fd24af 650 *edx = vec[3];
bdde476a 651}
c6dc6f63
AP		 652
653#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
654
655/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
656 * a substring. ex if !NULL points to the first char after a substring,
657 * otherwise the string is assumed to sized by a terminating nul.
658 * Return lexical ordering of *s1:*s2.
659 */
8f9d989c
CF		 660static int sstrcmp(const char *s1, const char *e1,
661 const char *s2, const char *e2)
c6dc6f63
AP		 662{
663 for (;;) {
664 if (!*s1 || !*s2 || *s1 != *s2)
665 return (*s1 - *s2);
666 ++s1, ++s2;
667 if (s1 == e1 && s2 == e2)
668 return (0);
669 else if (s1 == e1)
670 return (*s2);
671 else if (s2 == e2)
672 return (*s1);
673 }
674}
675
676/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
677 * '|' delimited (possibly empty) strings in which case search for a match
678 * within the alternatives proceeds left to right. Return 0 for success,
679 * non-zero otherwise.
680 */
681static int altcmp(const char *s, const char *e, const char *altstr)
682{
683 const char *p, *q;
684
685 for (q = p = altstr; ; ) {
686 while (*p && *p != '|')
687 ++p;
688 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
689 return (0);
690 if (!*p)
691 return (1);
692 else
693 q = ++p;
694 }
695}
696
697/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 698 * *pval and return true, otherwise return false
c6dc6f63 699 */
e41e0fc6
JK		 700static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
701 const char **featureset)
c6dc6f63
AP		 702{
703 uint32_t mask;
704 const char **ppc;
e41e0fc6 705 bool found = false;
c6dc6f63 706
e41e0fc6 707 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 708 if (*ppc && !altcmp(s, e, *ppc)) {
709 *pval |= mask;
e41e0fc6 710 found = true;
c6dc6f63 711 }
e41e0fc6
JK		 712 }
713 return found;
c6dc6f63
AP		 714}
715
5ef57876 716static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 717 FeatureWordArray words,
718 Error **errp)
c6dc6f63 719{
5ef57876
EH		 720 FeatureWord w;
721 for (w = 0; w < FEATURE_WORDS; w++) {
722 FeatureWordInfo *wi = &feature_word_info[w];
2d5312da 723 if (lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
5ef57876
EH		 724 break;
725 }
726 }
727 if (w == FEATURE_WORDS) {
c00c94ab 728 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 729 }
c6dc6f63
AP		 730}
731
d940ee9b
EH		 732/* CPU class name definitions: */
733
734#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
735#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
736
737/* Return type name for a given CPU model name
738 * Caller is responsible for freeing the returned string.
739 */
740static char *x86_cpu_type_name(const char *model_name)
741{
742 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
743}
744
500050d1
AF		 745static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
746{
d940ee9b
EH		 747 ObjectClass *oc;
748 char *typename;
749
500050d1
AF		 750 if (cpu_model == NULL) {
751 return NULL;
752 }
753
d940ee9b
EH		 754 typename = x86_cpu_type_name(cpu_model);
755 oc = object_class_by_name(typename);
756 g_free(typename);
757 return oc;
500050d1
AF		 758}
759
104494ea
IM		 760static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
761{
762 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
763 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
764 return g_strndup(class_name,
765 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
766}
767
d940ee9b 768struct X86CPUDefinition {
c6dc6f63
AP		 769 const char *name;
770 uint32_t level;
90e4b0c3 771 uint32_t xlevel;
99b88a17
IM		 772 /* vendor is zero-terminated, 12 character ASCII string */
773 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 774 int family;
775 int model;
776 int stepping;
0514ef2f 777 FeatureWordArray features;
c6dc6f63 778 char model_id[48];
d940ee9b 779};
c6dc6f63 780
9576de75 781static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 782 {
783 .name = "qemu64",
3046bb5d 784 .level = 0xd,
99b88a17 785 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 786 .family = 6,
f8e6a11a 787 .model = 6,
c6dc6f63 788 .stepping = 3,
0514ef2f 789 .features[FEAT_1_EDX] =
27861ecc 790 PPRO_FEATURES |
c6dc6f63 791 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 792 CPUID_PSE36,
0514ef2f 793 .features[FEAT_1_ECX] =
6aa91e4a 794 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 795 .features[FEAT_8000_0001_EDX] =
c6dc6f63 796 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 797 .features[FEAT_8000_0001_ECX] =
71195672 798 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 799 .xlevel = 0x8000000A,
9cf2cc3d 800 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 801 },
802 {
803 .name = "phenom",
804 .level = 5,
99b88a17 805 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 806 .family = 16,
807 .model = 2,
808 .stepping = 3,
b9fc20bc 809 /* Missing: CPUID_HT */
0514ef2f 810 .features[FEAT_1_EDX] =
27861ecc 811 PPRO_FEATURES |
c6dc6f63 812 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 813 CPUID_PSE36 | CPUID_VME,
0514ef2f 814 .features[FEAT_1_ECX] =
27861ecc 815 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 816 CPUID_EXT_POPCNT,
0514ef2f 817 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 818 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
819 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 820 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 821 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
822 CPUID_EXT3_CR8LEG,
823 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
824 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 825 .features[FEAT_8000_0001_ECX] =
27861ecc 826 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 827 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 828 /* Missing: CPUID_SVM_LBRV */
0514ef2f 829 .features[FEAT_SVM] =
b9fc20bc 830 CPUID_SVM_NPT,
c6dc6f63
AP		 831 .xlevel = 0x8000001A,
832 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
833 },
834 {
835 .name = "core2duo",
836 .level = 10,
99b88a17 837 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 838 .family = 6,
839 .model = 15,
840 .stepping = 11,
b9fc20bc 841 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 842 .features[FEAT_1_EDX] =
27861ecc 843 PPRO_FEATURES |
c6dc6f63 844 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 845 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
846 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 847 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 848 .features[FEAT_1_ECX] =
27861ecc 849 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 850 CPUID_EXT_CX16,
0514ef2f 851 .features[FEAT_8000_0001_EDX] =
27861ecc 852 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 853 .features[FEAT_8000_0001_ECX] =
27861ecc 854 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 855 .xlevel = 0x80000008,
856 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
857 },
858 {
859 .name = "kvm64",
3046bb5d 860 .level = 0xd,
99b88a17 861 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 862 .family = 15,
863 .model = 6,
864 .stepping = 1,
b3a4f0b1 865 /* Missing: CPUID_HT */
0514ef2f 866 .features[FEAT_1_EDX] =
b3a4f0b1 867 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 868 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
869 CPUID_PSE36,
870 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 871 .features[FEAT_1_ECX] =
27861ecc 872 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 873 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 874 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 875 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
876 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
877 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
878 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
879 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 880 .features[FEAT_8000_0001_ECX] =
27861ecc 881 0,
c6dc6f63
AP		 882 .xlevel = 0x80000008,
883 .model_id = "Common KVM processor"
884 },
c6dc6f63
AP		 885 {
886 .name = "qemu32",
887 .level = 4,
99b88a17 888 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 889 .family = 6,
f8e6a11a 890 .model = 6,
c6dc6f63 891 .stepping = 3,
0514ef2f 892 .features[FEAT_1_EDX] =
27861ecc 893 PPRO_FEATURES,
0514ef2f 894 .features[FEAT_1_ECX] =
6aa91e4a 895 CPUID_EXT_SSE3,
58012d66 896 .xlevel = 0x80000004,
9cf2cc3d 897 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 898 },
eafaf1e5
AP		 899 {
900 .name = "kvm32",
901 .level = 5,
99b88a17 902 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 903 .family = 15,
904 .model = 6,
905 .stepping = 1,
0514ef2f 906 .features[FEAT_1_EDX] =
b3a4f0b1 907 PPRO_FEATURES | CPUID_VME |
eafaf1e5 908 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 909 .features[FEAT_1_ECX] =
27861ecc 910 CPUID_EXT_SSE3,
0514ef2f 911 .features[FEAT_8000_0001_ECX] =
27861ecc 912 0,
eafaf1e5
AP		 913 .xlevel = 0x80000008,
914 .model_id = "Common 32-bit KVM processor"
915 },
c6dc6f63
AP		 916 {
917 .name = "coreduo",
918 .level = 10,
99b88a17 919 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 920 .family = 6,
921 .model = 14,
922 .stepping = 8,
b9fc20bc 923 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 924 .features[FEAT_1_EDX] =
27861ecc 925 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 926 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
927 CPUID_SS,
928 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 929 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 930 .features[FEAT_1_ECX] =
e93abc14 931 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 932 .features[FEAT_8000_0001_EDX] =
27861ecc 933 CPUID_EXT2_NX,
c6dc6f63
AP		 934 .xlevel = 0x80000008,
935 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
936 },
937 {
938 .name = "486",
58012d66 939 .level = 1,
99b88a17 940 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 941 .family = 4,
b2a856d9 942 .model = 8,
c6dc6f63 943 .stepping = 0,
0514ef2f 944 .features[FEAT_1_EDX] =
27861ecc 945 I486_FEATURES,
c6dc6f63
AP		 946 .xlevel = 0,
947 },
948 {
949 .name = "pentium",
950 .level = 1,
99b88a17 951 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 952 .family = 5,
953 .model = 4,
954 .stepping = 3,
0514ef2f 955 .features[FEAT_1_EDX] =
27861ecc 956 PENTIUM_FEATURES,
c6dc6f63
AP		 957 .xlevel = 0,
958 },
959 {
960 .name = "pentium2",
961 .level = 2,
99b88a17 962 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 963 .family = 6,
964 .model = 5,
965 .stepping = 2,
0514ef2f 966 .features[FEAT_1_EDX] =
27861ecc 967 PENTIUM2_FEATURES,
c6dc6f63
AP		 968 .xlevel = 0,
969 },
970 {
971 .name = "pentium3",
3046bb5d 972 .level = 3,
99b88a17 973 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 974 .family = 6,
975 .model = 7,
976 .stepping = 3,
0514ef2f 977 .features[FEAT_1_EDX] =
27861ecc 978 PENTIUM3_FEATURES,
c6dc6f63
AP		 979 .xlevel = 0,
980 },
981 {
982 .name = "athlon",
983 .level = 2,
99b88a17 984 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 985 .family = 6,
986 .model = 2,
987 .stepping = 3,
0514ef2f 988 .features[FEAT_1_EDX] =
27861ecc 989 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 990 CPUID_MCA,
0514ef2f 991 .features[FEAT_8000_0001_EDX] =
60032ac0 992 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 993 .xlevel = 0x80000008,
9cf2cc3d 994 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 995 },
996 {
997 .name = "n270",
3046bb5d 998 .level = 10,
99b88a17 999 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1000 .family = 6,
1001 .model = 28,
1002 .stepping = 2,
b9fc20bc 1003 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1004 .features[FEAT_1_EDX] =
27861ecc 1005 PPRO_FEATURES |
b9fc20bc
EH		 1006 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1007 CPUID_ACPI | CPUID_SS,
c6dc6f63 1008 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1009 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1010 * CPUID_EXT_XTPR */
0514ef2f 1011 .features[FEAT_1_ECX] =
27861ecc 1012 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1013 CPUID_EXT_MOVBE,
0514ef2f 1014 .features[FEAT_8000_0001_EDX] =
60032ac0 1015 CPUID_EXT2_NX,
0514ef2f 1016 .features[FEAT_8000_0001_ECX] =
27861ecc 1017 CPUID_EXT3_LAHF_LM,
3046bb5d 1018 .xlevel = 0x80000008,
c6dc6f63
AP		 1019 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1020 },
3eca4642
EH		 1021 {
1022 .name = "Conroe",
3046bb5d 1023 .level = 10,
99b88a17 1024 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1025 .family = 6,
ffce9ebb 1026 .model = 15,
3eca4642 1027 .stepping = 3,
0514ef2f 1028 .features[FEAT_1_EDX] =
b3a4f0b1 1029 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1030 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1031 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1032 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1033 CPUID_DE | CPUID_FP87,
0514ef2f 1034 .features[FEAT_1_ECX] =
27861ecc 1035 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1036 .features[FEAT_8000_0001_EDX] =
27861ecc 1037 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1038 .features[FEAT_8000_0001_ECX] =
27861ecc 1039 CPUID_EXT3_LAHF_LM,
3046bb5d 1040 .xlevel = 0x80000008,
3eca4642
EH		 1041 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1042 },
1043 {
1044 .name = "Penryn",
3046bb5d 1045 .level = 10,
99b88a17 1046 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1047 .family = 6,
ffce9ebb 1048 .model = 23,
3eca4642 1049 .stepping = 3,
0514ef2f 1050 .features[FEAT_1_EDX] =
b3a4f0b1 1051 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1052 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1053 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1054 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1055 CPUID_DE | CPUID_FP87,
0514ef2f 1056 .features[FEAT_1_ECX] =
27861ecc 1057 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1058 CPUID_EXT_SSE3,
0514ef2f 1059 .features[FEAT_8000_0001_EDX] =
27861ecc 1060 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1061 .features[FEAT_8000_0001_ECX] =
27861ecc 1062 CPUID_EXT3_LAHF_LM,
3046bb5d 1063 .xlevel = 0x80000008,
3eca4642
EH		 1064 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1065 },
1066 {
1067 .name = "Nehalem",
3046bb5d 1068 .level = 11,
99b88a17 1069 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1070 .family = 6,
ffce9ebb 1071 .model = 26,
3eca4642 1072 .stepping = 3,
0514ef2f 1073 .features[FEAT_1_EDX] =
b3a4f0b1 1074 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1075 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1076 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1077 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1078 CPUID_DE | CPUID_FP87,
0514ef2f 1079 .features[FEAT_1_ECX] =
27861ecc 1080 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1081 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1082 .features[FEAT_8000_0001_EDX] =
27861ecc 1083 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1084 .features[FEAT_8000_0001_ECX] =
27861ecc 1085 CPUID_EXT3_LAHF_LM,
3046bb5d 1086 .xlevel = 0x80000008,
3eca4642
EH		 1087 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1088 },
1089 {
1090 .name = "Westmere",
1091 .level = 11,
99b88a17 1092 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1093 .family = 6,
1094 .model = 44,
1095 .stepping = 1,
0514ef2f 1096 .features[FEAT_1_EDX] =
b3a4f0b1 1097 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1098 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1099 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1100 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1101 CPUID_DE | CPUID_FP87,
0514ef2f 1102 .features[FEAT_1_ECX] =
27861ecc 1103 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1104 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1105 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1106 .features[FEAT_8000_0001_EDX] =
27861ecc 1107 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1108 .features[FEAT_8000_0001_ECX] =
27861ecc 1109 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1110 .features[FEAT_6_EAX] =
1111 CPUID_6_EAX_ARAT,
3046bb5d 1112 .xlevel = 0x80000008,
3eca4642
EH		 1113 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1114 },
1115 {
1116 .name = "SandyBridge",
1117 .level = 0xd,
99b88a17 1118 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1119 .family = 6,
1120 .model = 42,
1121 .stepping = 1,
0514ef2f 1122 .features[FEAT_1_EDX] =
b3a4f0b1 1123 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1124 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1125 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1126 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1127 CPUID_DE | CPUID_FP87,
0514ef2f 1128 .features[FEAT_1_ECX] =
27861ecc 1129 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1130 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1131 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1132 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1133 CPUID_EXT_SSE3,
0514ef2f 1134 .features[FEAT_8000_0001_EDX] =
27861ecc 1135 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1136 CPUID_EXT2_SYSCALL,
0514ef2f 1137 .features[FEAT_8000_0001_ECX] =
27861ecc 1138 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1139 .features[FEAT_XSAVE] =
1140 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1141 .features[FEAT_6_EAX] =
1142 CPUID_6_EAX_ARAT,
3046bb5d 1143 .xlevel = 0x80000008,
3eca4642
EH		 1144 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1145 },
2f9ac42a
PB		 1146 {
1147 .name = "IvyBridge",
1148 .level = 0xd,
1149 .vendor = CPUID_VENDOR_INTEL,
1150 .family = 6,
1151 .model = 58,
1152 .stepping = 9,
1153 .features[FEAT_1_EDX] =
1154 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1155 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1156 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1157 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1158 CPUID_DE | CPUID_FP87,
1159 .features[FEAT_1_ECX] =
1160 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1161 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1162 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1163 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1164 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1165 .features[FEAT_7_0_EBX] =
1166 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1167 CPUID_7_0_EBX_ERMS,
1168 .features[FEAT_8000_0001_EDX] =
1169 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1170 CPUID_EXT2_SYSCALL,
1171 .features[FEAT_8000_0001_ECX] =
1172 CPUID_EXT3_LAHF_LM,
1173 .features[FEAT_XSAVE] =
1174 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1175 .features[FEAT_6_EAX] =
1176 CPUID_6_EAX_ARAT,
3046bb5d 1177 .xlevel = 0x80000008,
2f9ac42a
PB		 1178 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1179 },
37507094 1180 {
a356850b
EH		 1181 .name = "Haswell-noTSX",
1182 .level = 0xd,
1183 .vendor = CPUID_VENDOR_INTEL,
1184 .family = 6,
1185 .model = 60,
1186 .stepping = 1,
1187 .features[FEAT_1_EDX] =
1188 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1189 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1190 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1191 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1192 CPUID_DE | CPUID_FP87,
1193 .features[FEAT_1_ECX] =
1194 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1195 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1196 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1197 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1198 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1199 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1200 .features[FEAT_8000_0001_EDX] =
1201 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1202 CPUID_EXT2_SYSCALL,
1203 .features[FEAT_8000_0001_ECX] =
becb6667 1204 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1205 .features[FEAT_7_0_EBX] =
1206 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1207 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1208 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1209 .features[FEAT_XSAVE] =
1210 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1211 .features[FEAT_6_EAX] =
1212 CPUID_6_EAX_ARAT,
3046bb5d 1213 .xlevel = 0x80000008,
a356850b
EH		 1214 .model_id = "Intel Core Processor (Haswell, no TSX)",
1215 }, {
37507094
EH		 1216 .name = "Haswell",
1217 .level = 0xd,
99b88a17 1218 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1219 .family = 6,
1220 .model = 60,
1221 .stepping = 1,
0514ef2f 1222 .features[FEAT_1_EDX] =
b3a4f0b1 1223 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1224 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1225 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1226 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1227 CPUID_DE | CPUID_FP87,
0514ef2f 1228 .features[FEAT_1_ECX] =
27861ecc 1229 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1230 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1231 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1232 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1233 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1234 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1235 .features[FEAT_8000_0001_EDX] =
27861ecc 1236 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1237 CPUID_EXT2_SYSCALL,
0514ef2f 1238 .features[FEAT_8000_0001_ECX] =
becb6667 1239 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1240 .features[FEAT_7_0_EBX] =
27861ecc 1241 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1242 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1243 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1244 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1245 .features[FEAT_XSAVE] =
1246 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1247 .features[FEAT_6_EAX] =
1248 CPUID_6_EAX_ARAT,
3046bb5d 1249 .xlevel = 0x80000008,
37507094
EH		 1250 .model_id = "Intel Core Processor (Haswell)",
1251 },
a356850b
EH		 1252 {
1253 .name = "Broadwell-noTSX",
1254 .level = 0xd,
1255 .vendor = CPUID_VENDOR_INTEL,
1256 .family = 6,
1257 .model = 61,
1258 .stepping = 2,
1259 .features[FEAT_1_EDX] =
1260 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1261 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1262 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1263 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1264 CPUID_DE | CPUID_FP87,
1265 .features[FEAT_1_ECX] =
1266 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1267 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1268 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1269 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1270 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1271 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1272 .features[FEAT_8000_0001_EDX] =
1273 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1274 CPUID_EXT2_SYSCALL,
1275 .features[FEAT_8000_0001_ECX] =
becb6667 1276 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1277 .features[FEAT_7_0_EBX] =
1278 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1279 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1280 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1281 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1282 CPUID_7_0_EBX_SMAP,
1283 .features[FEAT_XSAVE] =
1284 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1285 .features[FEAT_6_EAX] =
1286 CPUID_6_EAX_ARAT,
3046bb5d 1287 .xlevel = 0x80000008,
a356850b
EH		 1288 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1289 },
ece01354
EH		 1290 {
1291 .name = "Broadwell",
1292 .level = 0xd,
1293 .vendor = CPUID_VENDOR_INTEL,
1294 .family = 6,
1295 .model = 61,
1296 .stepping = 2,
1297 .features[FEAT_1_EDX] =
b3a4f0b1 1298 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1299 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1300 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1301 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1302 CPUID_DE | CPUID_FP87,
1303 .features[FEAT_1_ECX] =
1304 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1305 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1306 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1307 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1308 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1309 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1310 .features[FEAT_8000_0001_EDX] =
1311 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1312 CPUID_EXT2_SYSCALL,
1313 .features[FEAT_8000_0001_ECX] =
becb6667 1314 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1315 .features[FEAT_7_0_EBX] =
1316 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1317 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1318 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1319 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1320 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1321 .features[FEAT_XSAVE] =
1322 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1323 .features[FEAT_6_EAX] =
1324 CPUID_6_EAX_ARAT,
3046bb5d 1325 .xlevel = 0x80000008,
ece01354
EH		 1326 .model_id = "Intel Core Processor (Broadwell)",
1327 },
f6f949e9
EH		 1328 {
1329 .name = "Skylake-Client",
1330 .level = 0xd,
1331 .vendor = CPUID_VENDOR_INTEL,
1332 .family = 6,
1333 .model = 94,
1334 .stepping = 3,
1335 .features[FEAT_1_EDX] =
1336 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1337 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1338 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1339 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1340 CPUID_DE | CPUID_FP87,
1341 .features[FEAT_1_ECX] =
1342 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1343 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1344 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1345 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1346 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1347 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1348 .features[FEAT_8000_0001_EDX] =
1349 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1350 CPUID_EXT2_SYSCALL,
1351 .features[FEAT_8000_0001_ECX] =
1352 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1353 .features[FEAT_7_0_EBX] =
1354 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1355 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1356 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1357 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1358 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1359 /* Missing: XSAVES (not supported by some Linux versions,
1360 * including v4.1 to v4.6).
1361 * KVM doesn't yet expose any XSAVES state save component,
1362 * and the only one defined in Skylake (processor tracing)
1363 * probably will block migration anyway.
1364 */
1365 .features[FEAT_XSAVE] =
1366 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1367 CPUID_XSAVE_XGETBV1,
1368 .features[FEAT_6_EAX] =
1369 CPUID_6_EAX_ARAT,
1370 .xlevel = 0x80000008,
1371 .model_id = "Intel Core Processor (Skylake)",
1372 },
3eca4642
EH		 1373 {
1374 .name = "Opteron_G1",
1375 .level = 5,
99b88a17 1376 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1377 .family = 15,
1378 .model = 6,
1379 .stepping = 1,
0514ef2f 1380 .features[FEAT_1_EDX] =
b3a4f0b1 1381 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1382 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1383 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1384 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1385 CPUID_DE | CPUID_FP87,
0514ef2f 1386 .features[FEAT_1_ECX] =
27861ecc 1387 CPUID_EXT_SSE3,
0514ef2f 1388 .features[FEAT_8000_0001_EDX] =
27861ecc 1389 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1390 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1391 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1392 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1393 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1394 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1395 .xlevel = 0x80000008,
1396 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1397 },
1398 {
1399 .name = "Opteron_G2",
1400 .level = 5,
99b88a17 1401 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1402 .family = 15,
1403 .model = 6,
1404 .stepping = 1,
0514ef2f 1405 .features[FEAT_1_EDX] =
b3a4f0b1 1406 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1407 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1408 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1409 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1410 CPUID_DE | CPUID_FP87,
0514ef2f 1411 .features[FEAT_1_ECX] =
27861ecc 1412 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1413 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1414 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1415 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1416 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1417 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1418 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1419 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1420 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1421 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1422 .features[FEAT_8000_0001_ECX] =
27861ecc 1423 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1424 .xlevel = 0x80000008,
1425 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1426 },
1427 {
1428 .name = "Opteron_G3",
1429 .level = 5,
99b88a17 1430 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 1431 .family = 16,
1432 .model = 2,
1433 .stepping = 3,
0514ef2f 1434 .features[FEAT_1_EDX] =
b3a4f0b1 1435 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1436 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1437 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1438 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1439 CPUID_DE | CPUID_FP87,
0514ef2f 1440 .features[FEAT_1_ECX] =
27861ecc 1441 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1442 CPUID_EXT_SSE3,
33b5e8c0 1443 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1444 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1445 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1446 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1447 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1448 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1449 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1450 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1451 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1452 .features[FEAT_8000_0001_ECX] =
27861ecc 1453 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1454 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1455 .xlevel = 0x80000008,
1456 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1457 },
1458 {
1459 .name = "Opteron_G4",
1460 .level = 0xd,
99b88a17 1461 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1462 .family = 21,
1463 .model = 1,
1464 .stepping = 2,
0514ef2f 1465 .features[FEAT_1_EDX] =
b3a4f0b1 1466 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1467 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1468 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1469 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1470 CPUID_DE | CPUID_FP87,
0514ef2f 1471 .features[FEAT_1_ECX] =
27861ecc 1472 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1473 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1474 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1475 CPUID_EXT_SSE3,
33b5e8c0 1476 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1477 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1478 CPUID_EXT2_LM |
b3fb3a20
EH		 1479 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1480 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1481 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1482 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1483 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1484 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1485 .features[FEAT_8000_0001_ECX] =
27861ecc 1486 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1487 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1488 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1489 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1490 /* no xsaveopt! */
3eca4642
EH		 1491 .xlevel = 0x8000001A,
1492 .model_id = "AMD Opteron 62xx class CPU",
1493 },
021941b9
AP		 1494 {
1495 .name = "Opteron_G5",
1496 .level = 0xd,
99b88a17 1497 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1498 .family = 21,
1499 .model = 2,
1500 .stepping = 0,
0514ef2f 1501 .features[FEAT_1_EDX] =
b3a4f0b1 1502 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1503 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1504 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1505 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1506 CPUID_DE | CPUID_FP87,
0514ef2f 1507 .features[FEAT_1_ECX] =
27861ecc 1508 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1509 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1510 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1511 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1512 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1513 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1514 CPUID_EXT2_LM |
b3fb3a20
EH		 1515 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1516 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1517 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1518 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1519 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1520 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1521 .features[FEAT_8000_0001_ECX] =
27861ecc 1522 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1523 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1524 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1525 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1526 /* no xsaveopt! */
021941b9
AP		 1527 .xlevel = 0x8000001A,
1528 .model_id = "AMD Opteron 63xx class CPU",
1529 },
c6dc6f63
AP		 1530};
1531
5114e842
EH		 1532typedef struct PropValue {
1533 const char *prop, *value;
1534} PropValue;
1535
1536/* KVM-specific features that are automatically added/removed
1537 * from all CPU models when KVM is enabled.
1538 */
1539static PropValue kvm_default_props[] = {
1540 { "kvmclock", "on" },
1541 { "kvm-nopiodelay", "on" },
1542 { "kvm-asyncpf", "on" },
1543 { "kvm-steal-time", "on" },
1544 { "kvm-pv-eoi", "on" },
1545 { "kvmclock-stable-bit", "on" },
1546 { "x2apic", "on" },
1547 { "acpi", "off" },
1548 { "monitor", "off" },
1549 { "svm", "off" },
1550 { NULL, NULL },
1551};
1552
1553void x86_cpu_change_kvm_default(const char *prop, const char *value)
1554{
1555 PropValue *pv;
1556 for (pv = kvm_default_props; pv->prop; pv++) {
1557 if (!strcmp(pv->prop, prop)) {
1558 pv->value = value;
1559 break;
1560 }
1561 }
1562
1563 /* It is valid to call this function only for properties that
1564 * are already present in the kvm_default_props table.
1565 */
1566 assert(pv->prop);
1567}
1568
4d1b279b
EH		 1569static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1570 bool migratable_only);
1571
d940ee9b
EH		 1572#ifdef CONFIG_KVM
1573
40bfe48f
HZ		 1574static bool lmce_supported(void)
1575{
1576 uint64_t mce_cap;
1577
1578 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1579 return false;
1580 }
1581
1582 return !!(mce_cap & MCG_LMCE_P);
1583}
1584
c6dc6f63
AP		 1585static int cpu_x86_fill_model_id(char *str)
1586{
1587 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1588 int i;
1589
1590 for (i = 0; i < 3; i++) {
1591 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1592 memcpy(str + i * 16 + 0, &eax, 4);
1593 memcpy(str + i * 16 + 4, &ebx, 4);
1594 memcpy(str + i * 16 + 8, &ecx, 4);
1595 memcpy(str + i * 16 + 12, &edx, 4);
1596 }
1597 return 0;
1598}
1599
d940ee9b
EH		 1600static X86CPUDefinition host_cpudef;
1601
84f1b92f 1602static Property host_x86_cpu_properties[] = {
120eee7d 1603 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1604 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1605 DEFINE_PROP_END_OF_LIST()
1606};
1607
d940ee9b 1608/* class_init for the "host" CPU model
6e746f30 1609 *
d940ee9b 1610 * This function may be called before KVM is initialized.
6e746f30 1611 */
d940ee9b 1612static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1613{
84f1b92f 1614 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1615 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1616 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1617
d940ee9b 1618 xcc->kvm_required = true;
6e746f30 1619
c6dc6f63 1620 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1621 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1622
1623 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1624 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1625 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1626 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1627
d940ee9b 1628 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1629
d940ee9b 1630 xcc->cpu_def = &host_cpudef;
ee465a3e
EH		 1631 xcc->model_description =
1632 "KVM processor with all supported host features "
1633 "(only available in KVM mode)";
d940ee9b
EH		 1634
1635 /* level, xlevel, xlevel2, and the feature words are initialized on
1636 * instance_init, because they require KVM to be initialized.
1637 */
84f1b92f
EH		 1638
1639 dc->props = host_x86_cpu_properties;
4c315c27
MA		 1640 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1641 dc->cannot_destroy_with_object_finalize_yet = true;
d940ee9b
EH		 1642}
1643
1644static void host_x86_cpu_initfn(Object *obj)
1645{
1646 X86CPU *cpu = X86_CPU(obj);
1647 CPUX86State *env = &cpu->env;
1648 KVMState *s = kvm_state;
d940ee9b 1649
4d1b279b
EH		 1650 /* We can't fill the features array here because we don't know yet if
1651 * "migratable" is true or false.
1652 */
1653 cpu->host_features = true;
1654
104494ea 1655 /* If KVM is disabled, x86_cpu_realizefn() will report an error later */
e4356010 1656 if (kvm_enabled()) {
c39c0edf
EH		 1657 env->cpuid_min_level =
1658 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1659 env->cpuid_min_xlevel =
1660 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1661 env->cpuid_min_xlevel2 =
1662 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
40bfe48f
HZ		 1663
1664 if (lmce_supported()) {
1665 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1666 }
e4356010 1667 }
2a573259 1668
d940ee9b 1669 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1670}
1671
d940ee9b
EH		 1672static const TypeInfo host_x86_cpu_type_info = {
1673 .name = X86_CPU_TYPE_NAME("host"),
1674 .parent = TYPE_X86_CPU,
1675 .instance_init = host_x86_cpu_initfn,
1676 .class_init = host_x86_cpu_class_init,
1677};
1678
1679#endif
1680
8459e396 1681static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1682{
8459e396 1683 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1684 int i;
1685
857aee33 1686 for (i = 0; i < 32; ++i) {
72370dc1 1687 if ((1UL << i) & mask) {
bffd67b0 1688 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1689 assert(reg);
fefb41bf 1690 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1691 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1692 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1693 f->cpuid_eax, reg,
1694 f->feat_names[i] ? "." : "",
1695 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1696 }
857aee33 1697 }
c6dc6f63
AP		 1698}
1699
d7bce999
EB		 1700static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1701 const char *name, void *opaque,
1702 Error **errp)
95b8519d
AF		 1703{
1704 X86CPU *cpu = X86_CPU(obj);
1705 CPUX86State *env = &cpu->env;
1706 int64_t value;
1707
1708 value = (env->cpuid_version >> 8) & 0xf;
1709 if (value == 0xf) {
1710 value += (env->cpuid_version >> 20) & 0xff;
1711 }
51e72bc1 1712 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1713}
1714
d7bce999
EB		 1715static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1716 const char *name, void *opaque,
1717 Error **errp)
ed5e1ec3 1718{
71ad61d3
AF		 1719 X86CPU *cpu = X86_CPU(obj);
1720 CPUX86State *env = &cpu->env;
1721 const int64_t min = 0;
1722 const int64_t max = 0xff + 0xf;
65cd9064 1723 Error *local_err = NULL;
71ad61d3
AF		 1724 int64_t value;
1725
51e72bc1 1726 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1727 if (local_err) {
1728 error_propagate(errp, local_err);
71ad61d3
AF		 1729 return;
1730 }
1731 if (value < min || value > max) {
c6bd8c70
MA		 1732 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1733 name ? name : "null", value, min, max);
71ad61d3
AF		 1734 return;
1735 }
1736
ed5e1ec3 1737 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1738 if (value > 0x0f) {
1739 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1740 } else {
71ad61d3 1741 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1742 }
1743}
1744
d7bce999
EB		 1745static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1746 const char *name, void *opaque,
1747 Error **errp)
67e30c83
AF		 1748{
1749 X86CPU *cpu = X86_CPU(obj);
1750 CPUX86State *env = &cpu->env;
1751 int64_t value;
1752
1753 value = (env->cpuid_version >> 4) & 0xf;
1754 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1755 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1756}
1757
d7bce999
EB		 1758static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1759 const char *name, void *opaque,
1760 Error **errp)
b0704cbd 1761{
c5291a4f
AF		 1762 X86CPU *cpu = X86_CPU(obj);
1763 CPUX86State *env = &cpu->env;
1764 const int64_t min = 0;
1765 const int64_t max = 0xff;
65cd9064 1766 Error *local_err = NULL;
c5291a4f
AF		 1767 int64_t value;
1768
51e72bc1 1769 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1770 if (local_err) {
1771 error_propagate(errp, local_err);
c5291a4f
AF		 1772 return;
1773 }
1774 if (value < min || value > max) {
c6bd8c70
MA		 1775 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1776 name ? name : "null", value, min, max);
c5291a4f
AF		 1777 return;
1778 }
1779
b0704cbd 1780 env->cpuid_version &= ~0xf00f0;
c5291a4f 1781 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1782}
1783
35112e41 1784static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1785 const char *name, void *opaque,
35112e41
AF		 1786 Error **errp)
1787{
1788 X86CPU *cpu = X86_CPU(obj);
1789 CPUX86State *env = &cpu->env;
1790 int64_t value;
1791
1792 value = env->cpuid_version & 0xf;
51e72bc1 1793 visit_type_int(v, name, &value, errp);
35112e41
AF		 1794}
1795
036e2222 1796static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1797 const char *name, void *opaque,
036e2222 1798 Error **errp)
38c3dc46 1799{
036e2222
AF		 1800 X86CPU *cpu = X86_CPU(obj);
1801 CPUX86State *env = &cpu->env;
1802 const int64_t min = 0;
1803 const int64_t max = 0xf;
65cd9064 1804 Error *local_err = NULL;
036e2222
AF		 1805 int64_t value;
1806
51e72bc1 1807 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1808 if (local_err) {
1809 error_propagate(errp, local_err);
036e2222
AF		 1810 return;
1811 }
1812 if (value < min || value > max) {
c6bd8c70
MA		 1813 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1814 name ? name : "null", value, min, max);
036e2222
AF		 1815 return;
1816 }
1817
38c3dc46 1818 env->cpuid_version &= ~0xf;
036e2222 1819 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1820}
1821
d480e1af
AF		 1822static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1823{
1824 X86CPU *cpu = X86_CPU(obj);
1825 CPUX86State *env = &cpu->env;
1826 char *value;
d480e1af 1827
e42a92ae 1828 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1829 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1830 env->cpuid_vendor3);
d480e1af
AF		 1831 return value;
1832}
1833
1834static void x86_cpuid_set_vendor(Object *obj, const char *value,
1835 Error **errp)
1836{
1837 X86CPU *cpu = X86_CPU(obj);
1838 CPUX86State *env = &cpu->env;
1839 int i;
1840
9df694ee 1841 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1842 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1843 return;
1844 }
1845
1846 env->cpuid_vendor1 = 0;
1847 env->cpuid_vendor2 = 0;
1848 env->cpuid_vendor3 = 0;
1849 for (i = 0; i < 4; i++) {
1850 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1851 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1852 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1853 }
d480e1af
AF		 1854}
1855
63e886eb
AF		 1856static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1857{
1858 X86CPU *cpu = X86_CPU(obj);
1859 CPUX86State *env = &cpu->env;
1860 char *value;
1861 int i;
1862
1863 value = g_malloc(48 + 1);
1864 for (i = 0; i < 48; i++) {
1865 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1866 }
1867 value[48] = '\0';
1868 return value;
1869}
1870
938d4c25
AF		 1871static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1872 Error **errp)
dcce6675 1873{
938d4c25
AF		 1874 X86CPU *cpu = X86_CPU(obj);
1875 CPUX86State *env = &cpu->env;
dcce6675
AF		 1876 int c, len, i;
1877
1878 if (model_id == NULL) {
1879 model_id = "";
1880 }
1881 len = strlen(model_id);
d0a6acf4 1882 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1883 for (i = 0; i < 48; i++) {
1884 if (i >= len) {
1885 c = '\0';
1886 } else {
1887 c = (uint8_t)model_id[i];
1888 }
1889 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1890 }
1891}
1892
d7bce999
EB		 1893static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1894 void *opaque, Error **errp)
89e48965
AF		 1895{
1896 X86CPU *cpu = X86_CPU(obj);
1897 int64_t value;
1898
1899 value = cpu->env.tsc_khz * 1000;
51e72bc1 1900 visit_type_int(v, name, &value, errp);
89e48965
AF		 1901}
1902
d7bce999
EB		 1903static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1904 void *opaque, Error **errp)
89e48965
AF		 1905{
1906 X86CPU *cpu = X86_CPU(obj);
1907 const int64_t min = 0;
2e84849a 1908 const int64_t max = INT64_MAX;
65cd9064 1909 Error *local_err = NULL;
89e48965
AF		 1910 int64_t value;
1911
51e72bc1 1912 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1913 if (local_err) {
1914 error_propagate(errp, local_err);
89e48965
AF		 1915 return;
1916 }
1917 if (value < min || value > max) {
c6bd8c70
MA		 1918 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1919 name ? name : "null", value, min, max);
89e48965
AF		 1920 return;
1921 }
1922
36f96c4b 1923 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1924}
1925
7e5292b5 1926/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1927static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1928 const char *name, void *opaque,
1929 Error **errp)
8e8aba50 1930{
7e5292b5 1931 uint32_t *array = (uint32_t *)opaque;
8e8aba50 1932 FeatureWord w;
8e8aba50
EH		 1933 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1934 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1935 X86CPUFeatureWordInfoList *list = NULL;
1936
1937 for (w = 0; w < FEATURE_WORDS; w++) {
1938 FeatureWordInfo *wi = &feature_word_info[w];
1939 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1940 qwi->cpuid_input_eax = wi->cpuid_eax;
1941 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1942 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1943 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1944 qwi->features = array[w];
8e8aba50
EH		 1945
1946 /* List will be in reverse order, but order shouldn't matter */
1947 list_entries[w].next = list;
1948 list_entries[w].value = &word_infos[w];
1949 list = &list_entries[w];
1950 }
1951
6b62d961 1952 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 1953}
1954
d7bce999
EB		 1955static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1956 void *opaque, Error **errp)
c8f0f88e
IM		 1957{
1958 X86CPU *cpu = X86_CPU(obj);
1959 int64_t value = cpu->hyperv_spinlock_attempts;
1960
51e72bc1 1961 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1962}
1963
d7bce999
EB		 1964static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1965 void *opaque, Error **errp)
c8f0f88e
IM		 1966{
1967 const int64_t min = 0xFFF;
1968 const int64_t max = UINT_MAX;
1969 X86CPU *cpu = X86_CPU(obj);
1970 Error *err = NULL;
1971 int64_t value;
1972
51e72bc1 1973 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1974 if (err) {
1975 error_propagate(errp, err);
1976 return;
1977 }
1978
1979 if (value < min || value > max) {
1980 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1981 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1982 object_get_typename(obj), name ? name : "null",
1983 value, min, max);
c8f0f88e
IM		 1984 return;
1985 }
1986 cpu->hyperv_spinlock_attempts = value;
1987}
1988
1989static PropertyInfo qdev_prop_spinlocks = {
1990 .name = "int",
1991 .get = x86_get_hv_spinlocks,
1992 .set = x86_set_hv_spinlocks,
1993};
1994
72ac2e87
IM		 1995/* Convert all '_' in a feature string option name to '-', to make feature
1996 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1997 */
1998static inline void feat2prop(char *s)
1999{
2000 while ((s = strchr(s, '_'))) {
2001 *s = '-';
2002 }
2003}
2004
dc15c051
IM		 2005/* Compatibily hack to maintain legacy +-feat semantic,
2006 * where +-feat overwrites any feature set by
2007 * feat=on|feat even if the later is parsed after +-feat
2008 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2009 */
2010static FeatureWordArray plus_features = { 0 };
2011static FeatureWordArray minus_features = { 0 };
2012
8f961357
EH		 2013/* Parse "+feature,-feature,feature=foo" CPU feature string
2014 */
62a48a2a 2015static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 2016 Error **errp)
8f961357 2017{
8f961357 2018 char *featurestr; /* Single 'key=value" string being parsed */
94a444b2 2019 Error *local_err = NULL;
62a48a2a
IM		 2020 static bool cpu_globals_initialized;
2021
2022 if (cpu_globals_initialized) {
2023 return;
2024 }
2025 cpu_globals_initialized = true;
8f961357 2026
f6750e95
EH		 2027 if (!features) {
2028 return;
2029 }
2030
2031 for (featurestr = strtok(features, ",");
2032 featurestr && !local_err;
2033 featurestr = strtok(NULL, ",")) {
2034 const char *name;
2035 const char *val = NULL;
2036 char *eq = NULL;
cf2887c9 2037 char num[32];
62a48a2a 2038 GlobalProperty *prop;
c6dc6f63 2039
f6750e95 2040 /* Compatibility syntax: */
c6dc6f63 2041 if (featurestr[0] == '+') {
c00c94ab 2042 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
f6750e95 2043 continue;
c6dc6f63 2044 } else if (featurestr[0] == '-') {
c00c94ab 2045 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
f6750e95
EH		 2046 continue;
2047 }
2048
2049 eq = strchr(featurestr, '=');
2050 if (eq) {
2051 *eq++ = 0;
2052 val = eq;
c6dc6f63 2053 } else {
f6750e95 2054 val = "on";
a91987c2 2055 }
f6750e95
EH		 2056
2057 feat2prop(featurestr);
2058 name = featurestr;
2059
2060 /* Special case: */
2061 if (!strcmp(name, "tsc-freq")) {
2062 int64_t tsc_freq;
2063 char *err;
f6750e95
EH		 2064
2065 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
2066 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
2067 if (tsc_freq < 0 || *err) {
2068 error_setg(errp, "bad numerical value %s", val);
2069 return;
2070 }
2071 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2072 val = num;
2073 name = "tsc-frequency";
c6dc6f63 2074 }
f6750e95 2075
62a48a2a
IM		 2076 prop = g_new0(typeof(*prop), 1);
2077 prop->driver = typename;
2078 prop->property = g_strdup(name);
2079 prop->value = g_strdup(val);
2080 prop->errp = &error_fatal;
2081 qdev_prop_register_global(prop);
f6750e95
EH		 2082 }
2083
2084 if (local_err) {
2085 error_propagate(errp, local_err);
c6dc6f63 2086 }
c6dc6f63
AP		 2087}
2088
8c3329e5 2089/* Print all cpuid feature names in featureset
c6dc6f63 2090 */
8c3329e5 2091static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2092{
8c3329e5
EH		 2093 int bit;
2094 bool first = true;
2095
2096 for (bit = 0; bit < 32; bit++) {
2097 if (featureset[bit]) {
2098 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2099 first = false;
c6dc6f63 2100 }
8c3329e5 2101 }
c6dc6f63
AP		 2102}
2103
ee465a3e
EH		 2104/* Sort alphabetically by type name, listing kvm_required models last. */
2105static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
2106{
2107 ObjectClass *class_a = (ObjectClass *)a;
2108 ObjectClass *class_b = (ObjectClass *)b;
2109 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
2110 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
2111 const char *name_a, *name_b;
2112
2113 if (cc_a->kvm_required != cc_b->kvm_required) {
2114 /* kvm_required items go last */
2115 return cc_a->kvm_required ? 1 : -1;
2116 } else {
2117 name_a = object_class_get_name(class_a);
2118 name_b = object_class_get_name(class_b);
2119 return strcmp(name_a, name_b);
2120 }
2121}
2122
2123static GSList *get_sorted_cpu_model_list(void)
2124{
2125 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
2126 list = g_slist_sort(list, x86_cpu_list_compare);
2127 return list;
2128}
2129
2130static void x86_cpu_list_entry(gpointer data, gpointer user_data)
2131{
2132 ObjectClass *oc = data;
2133 X86CPUClass *cc = X86_CPU_CLASS(oc);
2134 CPUListState *s = user_data;
2135 char *name = x86_cpu_class_get_model_name(cc);
2136 const char *desc = cc->model_description;
2137 if (!desc) {
2138 desc = cc->cpu_def->model_id;
2139 }
2140
2141 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
2142 name, desc);
2143 g_free(name);
2144}
2145
2146/* list available CPU models and flags */
e916cbf8 2147void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2148{
7fc9b714 2149 int i;
ee465a3e
EH		 2150 CPUListState s = {
2151 .file = f,
2152 .cpu_fprintf = cpu_fprintf,
2153 };
2154 GSList *list;
c6dc6f63 2155
ee465a3e
EH		 2156 (*cpu_fprintf)(f, "Available CPUs:\n");
2157 list = get_sorted_cpu_model_list();
2158 g_slist_foreach(list, x86_cpu_list_entry, &s);
2159 g_slist_free(list);
21ad7789 2160
6cdf8854 2161 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2162 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2163 FeatureWordInfo *fw = &feature_word_info[i];
2164
8c3329e5
EH		 2165 (*cpu_fprintf)(f, " ");
2166 listflags(f, cpu_fprintf, fw->feat_names);
2167 (*cpu_fprintf)(f, "\n");
3af60be2 2168 }
c6dc6f63
AP		 2169}
2170
ee465a3e
EH		 2171static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
2172{
2173 ObjectClass *oc = data;
2174 X86CPUClass *cc = X86_CPU_CLASS(oc);
2175 CpuDefinitionInfoList **cpu_list = user_data;
2176 CpuDefinitionInfoList *entry;
2177 CpuDefinitionInfo *info;
2178
2179 info = g_malloc0(sizeof(*info));
2180 info->name = x86_cpu_class_get_model_name(cc);
2181
2182 entry = g_malloc0(sizeof(*entry));
2183 entry->value = info;
2184 entry->next = *cpu_list;
2185 *cpu_list = entry;
2186}
2187
76b64a7a 2188CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2189{
2190 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 2191 GSList *list = get_sorted_cpu_model_list();
2192 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
2193 g_slist_free(list);
e3966126
AL		 2194 return cpu_list;
2195}
2196
84f1b92f
EH		 2197static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2198 bool migratable_only)
27418adf
EH		 2199{
2200 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2201 uint32_t r;
27418adf 2202
fefb41bf 2203 if (kvm_enabled()) {
84f1b92f
EH		 2204 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2205 wi->cpuid_ecx,
2206 wi->cpuid_reg);
fefb41bf 2207 } else if (tcg_enabled()) {
84f1b92f 2208 r = wi->tcg_features;
fefb41bf
EH		 2209 } else {
2210 return ~0;
2211 }
84f1b92f
EH		 2212 if (migratable_only) {
2213 r &= x86_cpu_get_migratable_flags(w);
2214 }
2215 return r;
27418adf
EH		 2216}
2217
51f63aed
EH		 2218/*
2219 * Filters CPU feature words based on host availability of each feature.
2220 *
51f63aed
EH		 2221 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2222 */
27418adf 2223static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2224{
2225 CPUX86State *env = &cpu->env;
bd87d2a2 2226 FeatureWord w;
51f63aed
EH		 2227 int rv = 0;
2228
bd87d2a2 2229 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2230 uint32_t host_feat =
2231 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2232 uint32_t requested_features = env->features[w];
2233 env->features[w] &= host_feat;
2234 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2235 if (cpu->filtered_features[w]) {
2236 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2237 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2238 }
2239 rv = 1;
2240 }
bd87d2a2 2241 }
51f63aed
EH		 2242
2243 return rv;
bc74b7db 2244}
bc74b7db 2245
5114e842
EH		 2246static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2247{
2248 PropValue *pv;
2249 for (pv = props; pv->prop; pv++) {
2250 if (!pv->value) {
2251 continue;
2252 }
2253 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2254 &error_abort);
2255 }
2256}
2257
d940ee9b 2258/* Load data from X86CPUDefinition
c080e30e 2259 */
d940ee9b 2260static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2261{
61dcd775 2262 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2263 const char *vendor;
2264 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2265 FeatureWord w;
c6dc6f63 2266
c39c0edf
EH		 2267 /* CPU models only set _minimum_ values for level/xlevel: */
2268 object_property_set_int(OBJECT(cpu), def->level, "min-level", errp);
2269 object_property_set_int(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
2270
2d64255b
AF		 2271 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2272 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2273 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2274 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2275 for (w = 0; w < FEATURE_WORDS; w++) {
2276 env->features[w] = def->features[w];
2277 }
82beb536 2278
9576de75 2279 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2280 if (kvm_enabled()) {
492a4c94
LT		 2281 if (!kvm_irqchip_in_kernel()) {
2282 x86_cpu_change_kvm_default("x2apic", "off");
2283 }
2284
5114e842 2285 x86_cpu_apply_props(cpu, kvm_default_props);
82beb536 2286 }
5fcca9ff 2287
82beb536 2288 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2289
2290 /* sysenter isn't supported in compatibility mode on AMD,
2291 * syscall isn't supported in compatibility mode on Intel.
2292 * Normally we advertise the actual CPU vendor, but you can
2293 * override this using the 'vendor' property if you want to use
2294 * KVM's sysenter/syscall emulation in compatibility mode and
2295 * when doing cross vendor migration
2296 */
74f54bc4 2297 vendor = def->vendor;
7c08db30
EH		 2298 if (kvm_enabled()) {
2299 uint32_t ebx = 0, ecx = 0, edx = 0;
2300 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2301 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2302 vendor = host_vendor;
2303 }
2304
2305 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2306
c6dc6f63
AP		 2307}
2308
0856579c 2309X86CPU *cpu_x86_init(const char *cpu_model)
7f833247 2310{
a57d0163 2311 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
5c3c6a68
AF		 2312}
2313
d940ee9b
EH		 2314static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2315{
2316 X86CPUDefinition *cpudef = data;
2317 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2318
2319 xcc->cpu_def = cpudef;
2320}
2321
2322static void x86_register_cpudef_type(X86CPUDefinition *def)
2323{
2324 char *typename = x86_cpu_type_name(def->name);
2325 TypeInfo ti = {
2326 .name = typename,
2327 .parent = TYPE_X86_CPU,
2328 .class_init = x86_cpu_cpudef_class_init,
2329 .class_data = def,
2330 };
2331
2332 type_register(&ti);
2333 g_free(typename);
2334}
2335
c6dc6f63 2336#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2337
0e26b7b8
BS		 2338void cpu_clear_apic_feature(CPUX86State *env)
2339{
0514ef2f 2340 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2341}
2342
c6dc6f63
AP		 2343#endif /* !CONFIG_USER_ONLY */
2344
c6dc6f63
AP		 2345void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2346 uint32_t *eax, uint32_t *ebx,
2347 uint32_t *ecx, uint32_t *edx)
2348{
a60f24b5
AF		 2349 X86CPU *cpu = x86_env_get_cpu(env);
2350 CPUState *cs = CPU(cpu);
14c985cf 2351 uint32_t pkg_offset;
a60f24b5 2352
c6dc6f63
AP		 2353 /* test if maximum index reached */
2354 if (index & 0x80000000) {
b3baa152
BW		 2355 if (index > env->cpuid_xlevel) {
2356 if (env->cpuid_xlevel2 > 0) {
2357 /* Handle the Centaur's CPUID instruction. */
2358 if (index > env->cpuid_xlevel2) {
2359 index = env->cpuid_xlevel2;
2360 } else if (index < 0xC0000000) {
2361 index = env->cpuid_xlevel;
2362 }
2363 } else {
57f26ae7
EH		 2364 /* Intel documentation states that invalid EAX input will
2365 * return the same information as EAX=cpuid_level
2366 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2367 */
2368 index = env->cpuid_level;
b3baa152
BW		 2369 }
2370 }
c6dc6f63
AP		 2371 } else {
2372 if (index > env->cpuid_level)
2373 index = env->cpuid_level;
2374 }
2375
2376 switch(index) {
2377 case 0:
2378 *eax = env->cpuid_level;
5eb2f7a4
EH		 2379 *ebx = env->cpuid_vendor1;
2380 *edx = env->cpuid_vendor2;
2381 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2382 break;
2383 case 1:
2384 *eax = env->cpuid_version;
7e72a45c
EH		 2385 *ebx = (cpu->apic_id << 24) |
2386 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2387 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2388 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2389 *ecx |= CPUID_EXT_OSXSAVE;
2390 }
0514ef2f 2391 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2392 if (cs->nr_cores * cs->nr_threads > 1) {
2393 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2394 *edx |= CPUID_HT;
c6dc6f63
AP		 2395 }
2396 break;
2397 case 2:
2398 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2399 if (cpu->cache_info_passthrough) {
2400 host_cpuid(index, 0, eax, ebx, ecx, edx);
2401 break;
2402 }
5e891bf8 2403 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 2404 *ebx = 0;
14c985cf
LM		 2405 if (!cpu->enable_l3_cache) {
2406 *ecx = 0;
2407 } else {
2408 *ecx = L3_N_DESCRIPTOR;
2409 }
5e891bf8
EH		 2410 *edx = (L1D_DESCRIPTOR << 16) | \
2411 (L1I_DESCRIPTOR << 8) | \
2412 (L2_DESCRIPTOR);
c6dc6f63
AP		 2413 break;
2414 case 4:
2415 /* cache info: needed for Core compatibility */
787aaf57
BC		 2416 if (cpu->cache_info_passthrough) {
2417 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2418 *eax &= ~0xFC000000;
c6dc6f63 2419 } else {
2f7a21c4 2420 *eax = 0;
76c2975a 2421 switch (count) {
c6dc6f63 2422 case 0: /* L1 dcache info */
5e891bf8
EH		 2423 *eax |= CPUID_4_TYPE_DCACHE | \
2424 CPUID_4_LEVEL(1) | \
2425 CPUID_4_SELF_INIT_LEVEL;
2426 *ebx = (L1D_LINE_SIZE - 1) | \
2427 ((L1D_PARTITIONS - 1) << 12) | \
2428 ((L1D_ASSOCIATIVITY - 1) << 22);
2429 *ecx = L1D_SETS - 1;
2430 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2431 break;
2432 case 1: /* L1 icache info */
5e891bf8
EH		 2433 *eax |= CPUID_4_TYPE_ICACHE | \
2434 CPUID_4_LEVEL(1) | \
2435 CPUID_4_SELF_INIT_LEVEL;
2436 *ebx = (L1I_LINE_SIZE - 1) | \
2437 ((L1I_PARTITIONS - 1) << 12) | \
2438 ((L1I_ASSOCIATIVITY - 1) << 22);
2439 *ecx = L1I_SETS - 1;
2440 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2441 break;
2442 case 2: /* L2 cache info */
5e891bf8
EH		 2443 *eax |= CPUID_4_TYPE_UNIFIED | \
2444 CPUID_4_LEVEL(2) | \
2445 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2446 if (cs->nr_threads > 1) {
2447 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2448 }
5e891bf8
EH		 2449 *ebx = (L2_LINE_SIZE - 1) | \
2450 ((L2_PARTITIONS - 1) << 12) | \
2451 ((L2_ASSOCIATIVITY - 1) << 22);
2452 *ecx = L2_SETS - 1;
2453 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63 2454 break;
14c985cf
LM		 2455 case 3: /* L3 cache info */
2456 if (!cpu->enable_l3_cache) {
2457 *eax = 0;
2458 *ebx = 0;
2459 *ecx = 0;
2460 *edx = 0;
2461 break;
2462 }
2463 *eax |= CPUID_4_TYPE_UNIFIED | \
2464 CPUID_4_LEVEL(3) | \
2465 CPUID_4_SELF_INIT_LEVEL;
2466 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2467 *eax |= ((1 << pkg_offset) - 1) << 14;
2468 *ebx = (L3_N_LINE_SIZE - 1) | \
2469 ((L3_N_PARTITIONS - 1) << 12) | \
2470 ((L3_N_ASSOCIATIVITY - 1) << 22);
2471 *ecx = L3_N_SETS - 1;
2472 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2473 break;
c6dc6f63
AP		 2474 default: /* end of info */
2475 *eax = 0;
2476 *ebx = 0;
2477 *ecx = 0;
2478 *edx = 0;
2479 break;
76c2975a
PB		 2480 }
2481 }
2482
2483 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2484 if ((*eax & 31) && cs->nr_cores > 1) {
2485 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2486 }
2487 break;
2488 case 5:
2489 /* mwait info: needed for Core compatibility */
2490 *eax = 0; /* Smallest monitor-line size in bytes */
2491 *ebx = 0; /* Largest monitor-line size in bytes */
2492 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2493 *edx = 0;
2494 break;
2495 case 6:
2496 /* Thermal and Power Leaf */
28b8e4d0 2497 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2498 *ebx = 0;
2499 *ecx = 0;
2500 *edx = 0;
2501 break;
f7911686 2502 case 7:
13526728
EH		 2503 /* Structured Extended Feature Flags Enumeration Leaf */
2504 if (count == 0) {
2505 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2506 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2507 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2508 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2509 *ecx |= CPUID_7_0_ECX_OSPKE;
2510 }
13526728 2511 *edx = 0; /* Reserved */
f7911686
YW		 2512 } else {
2513 *eax = 0;
2514 *ebx = 0;
2515 *ecx = 0;
2516 *edx = 0;
2517 }
2518 break;
c6dc6f63
AP		 2519 case 9:
2520 /* Direct Cache Access Information Leaf */
2521 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2522 *ebx = 0;
2523 *ecx = 0;
2524 *edx = 0;
2525 break;
2526 case 0xA:
2527 /* Architectural Performance Monitoring Leaf */
9337e3b6 2528 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2529 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2530
2531 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2532 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2533 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2534 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2535 } else {
2536 *eax = 0;
2537 *ebx = 0;
2538 *ecx = 0;
2539 *edx = 0;
2540 }
c6dc6f63 2541 break;
5232d00a
RK		 2542 case 0xB:
2543 /* Extended Topology Enumeration Leaf */
2544 if (!cpu->enable_cpuid_0xb) {
2545 *eax = *ebx = *ecx = *edx = 0;
2546 break;
2547 }
2548
2549 *ecx = count & 0xff;
2550 *edx = cpu->apic_id;
2551
2552 switch (count) {
2553 case 0:
eab60fb9
MAL		 2554 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
2555 *ebx = cs->nr_threads;
5232d00a
RK		 2556 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2557 break;
2558 case 1:
eab60fb9
MAL		 2559 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2560 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 2561 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2562 break;
2563 default:
2564 *eax = 0;
2565 *ebx = 0;
2566 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2567 }
2568
2569 assert(!(*eax & ~0x1f));
2570 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2571 break;
2560f19f 2572 case 0xD: {
51e49430 2573 /* Processor Extended State */
2560f19f
PB		 2574 *eax = 0;
2575 *ebx = 0;
2576 *ecx = 0;
2577 *edx = 0;
19dc85db 2578 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2579 break;
2580 }
4928cd6d 2581
2560f19f 2582 if (count == 0) {
96193c22
EH		 2583 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
2584 *eax = env->features[FEAT_XSAVE_COMP_LO];
2585 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 2586 *ebx = *ecx;
2587 } else if (count == 1) {
0bb0b2d2 2588 *eax = env->features[FEAT_XSAVE];
f4f1110e 2589 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 2590 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
2591 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 2592 *eax = esa->size;
2593 *ebx = esa->offset;
2560f19f 2594 }
51e49430
SY		 2595 }
2596 break;
2560f19f 2597 }
c6dc6f63
AP		 2598 case 0x80000000:
2599 *eax = env->cpuid_xlevel;
2600 *ebx = env->cpuid_vendor1;
2601 *edx = env->cpuid_vendor2;
2602 *ecx = env->cpuid_vendor3;
2603 break;
2604 case 0x80000001:
2605 *eax = env->cpuid_version;
2606 *ebx = 0;
0514ef2f
EH		 2607 *ecx = env->features[FEAT_8000_0001_ECX];
2608 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2609
2610 /* The Linux kernel checks for the CMPLegacy bit and
2611 * discards multiple thread information if it is set.
cb8d4c8f 2612 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2613 */
ce3960eb 2614 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2615 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2616 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2617 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2618 *ecx |= 1 << 1; /* CmpLegacy bit */
2619 }
2620 }
c6dc6f63
AP		 2621 break;
2622 case 0x80000002:
2623 case 0x80000003:
2624 case 0x80000004:
2625 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2626 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2627 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2628 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2629 break;
2630 case 0x80000005:
2631 /* cache info (L1 cache) */
787aaf57
BC		 2632 if (cpu->cache_info_passthrough) {
2633 host_cpuid(index, 0, eax, ebx, ecx, edx);
2634 break;
2635 }
5e891bf8
EH		 2636 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2637 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2638 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2639 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2640 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2641 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2642 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2643 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2644 break;
2645 case 0x80000006:
2646 /* cache info (L2 cache) */
787aaf57
BC		 2647 if (cpu->cache_info_passthrough) {
2648 host_cpuid(index, 0, eax, ebx, ecx, edx);
2649 break;
2650 }
5e891bf8
EH		 2651 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2652 (L2_DTLB_2M_ENTRIES << 16) | \
2653 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2654 (L2_ITLB_2M_ENTRIES);
2655 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2656 (L2_DTLB_4K_ENTRIES << 16) | \
2657 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2658 (L2_ITLB_4K_ENTRIES);
2659 *ecx = (L2_SIZE_KB_AMD << 16) | \
2660 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2661 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
14c985cf
LM		 2662 if (!cpu->enable_l3_cache) {
2663 *edx = ((L3_SIZE_KB / 512) << 18) | \
2664 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2665 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2666 } else {
2667 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
2668 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
2669 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
2670 }
c6dc6f63 2671 break;
303752a9
MT		 2672 case 0x80000007:
2673 *eax = 0;
2674 *ebx = 0;
2675 *ecx = 0;
2676 *edx = env->features[FEAT_8000_0007_EDX];
2677 break;
c6dc6f63
AP		 2678 case 0x80000008:
2679 /* virtual & phys address size in low 2 bytes. */
0514ef2f 2680 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a
DDAG		 2681 /* 64 bit processor, 48 bits virtual, configurable
2682 * physical bits.
2683 */
2684 *eax = 0x00003000 + cpu->phys_bits;
c6dc6f63 2685 } else {
af45907a 2686 *eax = cpu->phys_bits;
c6dc6f63
AP		 2687 }
2688 *ebx = 0;
2689 *ecx = 0;
2690 *edx = 0;
ce3960eb
AF		 2691 if (cs->nr_cores * cs->nr_threads > 1) {
2692 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2693 }
2694 break;
2695 case 0x8000000A:
0514ef2f 2696 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2697 *eax = 0x00000001; /* SVM Revision */
2698 *ebx = 0x00000010; /* nr of ASIDs */
2699 *ecx = 0;
0514ef2f 2700 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2701 } else {
2702 *eax = 0;
2703 *ebx = 0;
2704 *ecx = 0;
2705 *edx = 0;
2706 }
c6dc6f63 2707 break;
b3baa152
BW		 2708 case 0xC0000000:
2709 *eax = env->cpuid_xlevel2;
2710 *ebx = 0;
2711 *ecx = 0;
2712 *edx = 0;
2713 break;
2714 case 0xC0000001:
2715 /* Support for VIA CPU's CPUID instruction */
2716 *eax = env->cpuid_version;
2717 *ebx = 0;
2718 *ecx = 0;
0514ef2f 2719 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2720 break;
2721 case 0xC0000002:
2722 case 0xC0000003:
2723 case 0xC0000004:
2724 /* Reserved for the future, and now filled with zero */
2725 *eax = 0;
2726 *ebx = 0;
2727 *ecx = 0;
2728 *edx = 0;
2729 break;
c6dc6f63
AP		 2730 default:
2731 /* reserved values: zero */
2732 *eax = 0;
2733 *ebx = 0;
2734 *ecx = 0;
2735 *edx = 0;
2736 break;
2737 }
2738}
5fd2087a
AF		 2739
2740/* CPUClass::reset() */
2741static void x86_cpu_reset(CPUState *s)
2742{
2743 X86CPU *cpu = X86_CPU(s);
2744 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2745 CPUX86State *env = &cpu->env;
a114d25d
RH		 2746 target_ulong cr4;
2747 uint64_t xcr0;
c1958aea
AF		 2748 int i;
2749
5fd2087a
AF		 2750 xcc->parent_reset(s);
2751
5e992a8e 2752 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 2753
00c8cb0a 2754 tlb_flush(s, 1);
c1958aea
AF		 2755
2756 env->old_exception = -1;
2757
2758 /* init to reset state */
2759
c1958aea
AF		 2760 env->hflags2 |= HF2_GIF_MASK;
2761
2762 cpu_x86_update_cr0(env, 0x60000010);
2763 env->a20_mask = ~0x0;
2764 env->smbase = 0x30000;
2765
2766 env->idt.limit = 0xffff;
2767 env->gdt.limit = 0xffff;
2768 env->ldt.limit = 0xffff;
2769 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2770 env->tr.limit = 0xffff;
2771 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2772
2773 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2774 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2775 DESC_R_MASK | DESC_A_MASK);
2776 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2777 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2778 DESC_A_MASK);
2779 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2780 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2781 DESC_A_MASK);
2782 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2783 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2784 DESC_A_MASK);
2785 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2786 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2787 DESC_A_MASK);
2788 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2789 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2790 DESC_A_MASK);
2791
2792 env->eip = 0xfff0;
2793 env->regs[R_EDX] = env->cpuid_version;
2794
2795 env->eflags = 0x2;
2796
2797 /* FPU init */
2798 for (i = 0; i < 8; i++) {
2799 env->fptags[i] = 1;
2800 }
5bde1407 2801 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2802
2803 env->mxcsr = 0x1f80;
a114d25d
RH		 2804 /* All units are in INIT state. */
2805 env->xstate_bv = 0;
c1958aea
AF		 2806
2807 env->pat = 0x0007040600070406ULL;
2808 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2809
2810 memset(env->dr, 0, sizeof(env->dr));
2811 env->dr[6] = DR6_FIXED_1;
2812 env->dr[7] = DR7_FIXED_1;
b3310ab3 2813 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2814 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2815
a114d25d 2816 cr4 = 0;
cfc3b074 2817 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 2818
2819#ifdef CONFIG_USER_ONLY
2820 /* Enable all the features for user-mode. */
2821 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 2822 xcr0 |= XSTATE_SSE_MASK;
a114d25d 2823 }
0f70ed47
PB		 2824 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2825 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 2826 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 2827 xcr0 |= 1ull << i;
2828 }
a114d25d 2829 }
0f70ed47 2830
a114d25d
RH		 2831 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2832 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2833 }
07929f2a
RH		 2834 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2835 cr4 |= CR4_FSGSBASE_MASK;
2836 }
a114d25d
RH		 2837#endif
2838
2839 env->xcr0 = xcr0;
2840 cpu_x86_update_cr4(env, cr4);
0522604b 2841
9db2efd9
AW		 2842 /*
2843 * SDM 11.11.5 requires:
2844 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2845 * - IA32_MTRR_PHYSMASKn.V = 0
2846 * All other bits are undefined. For simplification, zero it all.
2847 */
2848 env->mtrr_deftype = 0;
2849 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2850 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2851
dd673288
IM		 2852#if !defined(CONFIG_USER_ONLY)
2853 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2854 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2855
259186a7 2856 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2857
2858 if (kvm_enabled()) {
2859 kvm_arch_reset_vcpu(cpu);
2860 }
dd673288 2861#endif
5fd2087a
AF		 2862}
2863
dd673288
IM		 2864#ifndef CONFIG_USER_ONLY
2865bool cpu_is_bsp(X86CPU *cpu)
2866{
02e51483 2867 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2868}
65dee380
IM		 2869
2870/* TODO: remove me, when reset over QOM tree is implemented */
2871static void x86_cpu_machine_reset_cb(void *opaque)
2872{
2873 X86CPU *cpu = opaque;
2874 cpu_reset(CPU(cpu));
2875}
dd673288
IM		 2876#endif
2877
de024815
AF		 2878static void mce_init(X86CPU *cpu)
2879{
2880 CPUX86State *cenv = &cpu->env;
2881 unsigned int bank;
2882
2883 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2884 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 2885 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 2886 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
2887 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 2888 cenv->mcg_ctl = ~(uint64_t)0;
2889 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2890 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2891 }
2892 }
2893}
2894
bdeec802 2895#ifndef CONFIG_USER_ONLY
d3c64d6a 2896static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2897{
449994eb 2898 APICCommonState *apic;
bdeec802
IM		 2899 const char *apic_type = "apic";
2900
15eafc2e 2901 if (kvm_apic_in_kernel()) {
bdeec802
IM		 2902 apic_type = "kvm-apic";
2903 } else if (xen_enabled()) {
2904 apic_type = "xen-apic";
2905 }
2906
46232aaa 2907 cpu->apic_state = DEVICE(object_new(apic_type));
bdeec802 2908
6816b1b3
IM		 2909 object_property_add_child(OBJECT(cpu), "lapic",
2910 OBJECT(cpu->apic_state), &error_abort);
67e55caa 2911 object_unref(OBJECT(cpu->apic_state));
6816b1b3 2912
7e72a45c 2913 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2914 /* TODO: convert to link<> */
02e51483 2915 apic = APIC_COMMON(cpu->apic_state);
60671e58 2916 apic->cpu = cpu;
8d42d2d3 2917 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 2918}
2919
2920static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2921{
8d42d2d3
CF		 2922 APICCommonState *apic;
2923 static bool apic_mmio_map_once;
2924
02e51483 2925 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2926 return;
2927 }
6e8e2651
MA		 2928 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2929 errp);
8d42d2d3
CF		 2930
2931 /* Map APIC MMIO area */
2932 apic = APIC_COMMON(cpu->apic_state);
2933 if (!apic_mmio_map_once) {
2934 memory_region_add_subregion_overlap(get_system_memory(),
2935 apic->apicbase &
2936 MSR_IA32_APICBASE_BASE,
2937 &apic->io_memory,
2938 0x1000);
2939 apic_mmio_map_once = true;
2940 }
bdeec802 2941}
f809c605
PB		 2942
2943static void x86_cpu_machine_done(Notifier *n, void *unused)
2944{
2945 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2946 MemoryRegion *smram =
2947 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2948
2949 if (smram) {
2950 cpu->smram = g_new(MemoryRegion, 1);
2951 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2952 smram, 0, 1ull << 32);
2953 memory_region_set_enabled(cpu->smram, false);
2954 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2955 }
2956}
d3c64d6a
IM		 2957#else
2958static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2959{
2960}
bdeec802
IM		 2961#endif
2962
11f6fee5
DDAG		 2963/* Note: Only safe for use on x86(-64) hosts */
2964static uint32_t x86_host_phys_bits(void)
2965{
2966 uint32_t eax;
2967 uint32_t host_phys_bits;
2968
2969 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
2970 if (eax >= 0x80000008) {
2971 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
2972 /* Note: According to AMD doc 25481 rev 2.34 they have a field
2973 * at 23:16 that can specify a maximum physical address bits for
2974 * the guest that can override this value; but I've not seen
2975 * anything with that set.
2976 */
2977 host_phys_bits = eax & 0xff;
2978 } else {
2979 /* It's an odd 64 bit machine that doesn't have the leaf for
2980 * physical address bits; fall back to 36 that's most older
2981 * Intel.
2982 */
2983 host_phys_bits = 36;
2984 }
2985
2986 return host_phys_bits;
2987}
e48638fd 2988
c39c0edf
EH		 2989static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
2990{
2991 if (*min < value) {
2992 *min = value;
2993 }
2994}
2995
2996/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
2997static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
2998{
2999 CPUX86State *env = &cpu->env;
3000 FeatureWordInfo *fi = &feature_word_info[w];
3001 uint32_t eax = fi->cpuid_eax;
3002 uint32_t region = eax & 0xF0000000;
3003
3004 if (!env->features[w]) {
3005 return;
3006 }
3007
3008 switch (region) {
3009 case 0x00000000:
3010 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
3011 break;
3012 case 0x80000000:
3013 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
3014 break;
3015 case 0xC0000000:
3016 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
3017 break;
3018 }
3019}
3020
2ca8a8be
EH		 3021/* Calculate XSAVE components based on the configured CPU feature flags */
3022static void x86_cpu_enable_xsave_components(X86CPU *cpu)
3023{
3024 CPUX86State *env = &cpu->env;
3025 int i;
96193c22 3026 uint64_t mask;
2ca8a8be
EH		 3027
3028 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
3029 return;
3030 }
3031
96193c22 3032 mask = (XSTATE_FP_MASK | XSTATE_SSE_MASK);
2ca8a8be
EH		 3033 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
3034 const ExtSaveArea *esa = &x86_ext_save_areas[i];
3035 if (env->features[esa->feature] & esa->bits) {
96193c22 3036 mask |= (1ULL << i);
2ca8a8be
EH		 3037 }
3038 }
3039
96193c22
EH		 3040 env->features[FEAT_XSAVE_COMP_LO] = mask;
3041 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 3042}
3043
e48638fd
WH		 3044#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3045 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3046 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3047#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3048 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3049 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 3050static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 3051{
14a10fc3 3052 CPUState *cs = CPU(dev);
2b6f294c
AF		 3053 X86CPU *cpu = X86_CPU(dev);
3054 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 3055 CPUX86State *env = &cpu->env;
2b6f294c 3056 Error *local_err = NULL;
e48638fd 3057 static bool ht_warned;
dc15c051 3058 FeatureWord w;
b34d12d1 3059
104494ea
IM		 3060 if (xcc->kvm_required && !kvm_enabled()) {
3061 char *name = x86_cpu_class_get_model_name(xcc);
3062 error_setg(&local_err, "CPU model '%s' requires KVM", name);
3063 g_free(name);
3064 goto out;
3065 }
3066
d9c84f19 3067 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
9886e834
EH		 3068 error_setg(errp, "apic-id property was not initialized properly");
3069 return;
3070 }
3071
dc15c051
IM		 3072 /*TODO: cpu->host_features incorrectly overwrites features
3073 * set using "feat=on|off". Once we fix this, we can convert
3074 * plus_features & minus_features to global properties
3075 * inside x86_cpu_parse_featurestr() too.
3076 */
3077 if (cpu->host_features) {
3078 for (w = 0; w < FEATURE_WORDS; w++) {
3079 env->features[w] =
3080 x86_cpu_get_supported_feature_word(w, cpu->migratable);
3081 }
3082 }
3083
3084 for (w = 0; w < FEATURE_WORDS; w++) {
3085 cpu->env.features[w] |= plus_features[w];
3086 cpu->env.features[w] &= ~minus_features[w];
3087 }
3088
aec661de
EH		 3089 if (!kvm_enabled() || !cpu->expose_kvm) {
3090 env->features[FEAT_KVM] = 0;
3091 }
3092
2ca8a8be 3093 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 3094
3095 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3096 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
3097 if (cpu->full_cpuid_auto_level) {
3098 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
3099 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
3100 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
3101 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
3102 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
3103 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
3104 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
3105 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
3106 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
3107 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 3108 /* SVM requires CPUID[0x8000000A] */
3109 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
3110 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
3111 }
c39c0edf
EH		 3112 }
3113
3114 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3115 if (env->cpuid_level == UINT32_MAX) {
3116 env->cpuid_level = env->cpuid_min_level;
3117 }
3118 if (env->cpuid_xlevel == UINT32_MAX) {
3119 env->cpuid_xlevel = env->cpuid_min_xlevel;
3120 }
3121 if (env->cpuid_xlevel2 == UINT32_MAX) {
3122 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 3123 }
7a059953 3124
9997cf7b
EH		 3125 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
3126 error_setg(&local_err,
3127 kvm_enabled() ?
3128 "Host doesn't support requested features" :
3129 "TCG doesn't support requested features");
3130 goto out;
3131 }
3132
9b15cd9e
IM		 3133 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3134 * CPUID[1].EDX.
3135 */
e48638fd 3136 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 3137 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3138 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 3139 & CPUID_EXT2_AMD_ALIASES);
3140 }
3141
11f6fee5
DDAG		 3142 /* For 64bit systems think about the number of physical bits to present.
3143 * ideally this should be the same as the host; anything other than matching
3144 * the host can cause incorrect guest behaviour.
3145 * QEMU used to pick the magic value of 40 bits that corresponds to
3146 * consumer AMD devices but nothing else.
3147 */
af45907a 3148 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a 3149 if (kvm_enabled()) {
11f6fee5
DDAG		 3150 uint32_t host_phys_bits = x86_host_phys_bits();
3151 static bool warned;
3152
3153 if (cpu->host_phys_bits) {
3154 /* The user asked for us to use the host physical bits */
3155 cpu->phys_bits = host_phys_bits;
3156 }
3157
3158 /* Print a warning if the user set it to a value that's not the
3159 * host value.
3160 */
3161 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3162 !warned) {
3163 error_report("Warning: Host physical bits (%u)"
3164 " does not match phys-bits property (%u)",
3165 host_phys_bits, cpu->phys_bits);
3166 warned = true;
3167 }
3168
3169 if (cpu->phys_bits &&
3170 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3171 cpu->phys_bits < 32)) {
af45907a
DDAG		 3172 error_setg(errp, "phys-bits should be between 32 and %u "
3173 " (but is %u)",
3174 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3175 return;
3176 }
3177 } else {
11f6fee5 3178 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 3179 error_setg(errp, "TCG only supports phys-bits=%u",
3180 TCG_PHYS_ADDR_BITS);
3181 return;
3182 }
3183 }
11f6fee5
DDAG		 3184 /* 0 means it was not explicitly set by the user (or by machine
3185 * compat_props or by the host code above). In this case, the default
3186 * is the value used by TCG (40).
3187 */
3188 if (cpu->phys_bits == 0) {
3189 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3190 }
af45907a
DDAG		 3191 } else {
3192 /* For 32 bit systems don't use the user set value, but keep
3193 * phys_bits consistent with what we tell the guest.
3194 */
3195 if (cpu->phys_bits != 0) {
3196 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3197 return;
3198 }
fefb41bf 3199
af45907a
DDAG		 3200 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3201 cpu->phys_bits = 36;
3202 } else {
3203 cpu->phys_bits = 32;
3204 }
3205 }
42ecabaa
EH		 3206 cpu_exec_init(cs, &error_abort);
3207
57f2453a
EH		 3208 if (tcg_enabled()) {
3209 tcg_x86_init();
3210 }
3211
65dee380
IM		 3212#ifndef CONFIG_USER_ONLY
3213 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 3214
0514ef2f 3215 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 3216 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 3217 if (local_err != NULL) {
4dc1f449 3218 goto out;
bdeec802
IM		 3219 }
3220 }
65dee380
IM		 3221#endif
3222
7a059953 3223 mce_init(cpu);
2001d0cd
PB		 3224
3225#ifndef CONFIG_USER_ONLY
3226 if (tcg_enabled()) {
56943e8c
PM		 3227 AddressSpace *newas = g_new(AddressSpace, 1);
3228
f809c605 3229 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 3230 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 3231
3232 /* Outer container... */
3233 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 3234 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 3235
3236 /* ... with two regions inside: normal system memory with low
3237 * priority, and...
3238 */
3239 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3240 get_system_memory(), 0, ~0ull);
3241 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3242 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 3243 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 3244 cs->num_ases = 1;
56943e8c 3245 cpu_address_space_init(cs, newas, 0);
f809c605
PB		 3246
3247 /* ... SMRAM with higher priority, linked from /machine/smram. */
3248 cpu->machine_done.notify = x86_cpu_machine_done;
3249 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 3250 }
3251#endif
3252
14a10fc3 3253 qemu_init_vcpu(cs);
d3c64d6a 3254
e48638fd
WH		 3255 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3256 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3257 * based on inputs (sockets,cores,threads), it is still better to gives
3258 * users a warning.
3259 *
3260 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3261 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3262 */
3263 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3264 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3265 " -smp options properly.");
3266 ht_warned = true;
3267 }
3268
d3c64d6a
IM		 3269 x86_cpu_apic_realize(cpu, &local_err);
3270 if (local_err != NULL) {
3271 goto out;
3272 }
14a10fc3 3273 cpu_reset(cs);
2b6f294c 3274
4dc1f449 3275 xcc->parent_realize(dev, &local_err);
2001d0cd 3276
4dc1f449
IM		 3277out:
3278 if (local_err != NULL) {
3279 error_propagate(errp, local_err);
3280 return;
3281 }
7a059953
AF		 3282}
3283
c884776e
IM		 3284static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3285{
3286 X86CPU *cpu = X86_CPU(dev);
3287
3288#ifndef CONFIG_USER_ONLY
3289 cpu_remove_sync(CPU(dev));
3290 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3291#endif
3292
3293 if (cpu->apic_state) {
3294 object_unparent(OBJECT(cpu->apic_state));
3295 cpu->apic_state = NULL;
3296 }
3297}
3298
38e5c119
EH		 3299typedef struct BitProperty {
3300 uint32_t *ptr;
3301 uint32_t mask;
3302} BitProperty;
3303
d7bce999
EB		 3304static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3305 void *opaque, Error **errp)
38e5c119
EH		 3306{
3307 BitProperty *fp = opaque;
3308 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 3309 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3310}
3311
d7bce999
EB		 3312static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3313 void *opaque, Error **errp)
38e5c119
EH		 3314{
3315 DeviceState *dev = DEVICE(obj);
3316 BitProperty *fp = opaque;
3317 Error *local_err = NULL;
3318 bool value;
3319
3320 if (dev->realized) {
3321 qdev_prop_set_after_realize(dev, name, errp);
3322 return;
3323 }
3324
51e72bc1 3325 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3326 if (local_err) {
3327 error_propagate(errp, local_err);
3328 return;
3329 }
3330
3331 if (value) {
3332 *fp->ptr |= fp->mask;
3333 } else {
3334 *fp->ptr &= ~fp->mask;
3335 }
3336}
3337
3338static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3339 void *opaque)
3340{
3341 BitProperty *prop = opaque;
3342 g_free(prop);
3343}
3344
3345/* Register a boolean property to get/set a single bit in a uint32_t field.
3346 *
3347 * The same property name can be registered multiple times to make it affect
3348 * multiple bits in the same FeatureWord. In that case, the getter will return
3349 * true only if all bits are set.
3350 */
3351static void x86_cpu_register_bit_prop(X86CPU *cpu,
3352 const char *prop_name,
3353 uint32_t *field,
3354 int bitnr)
3355{
3356 BitProperty *fp;
3357 ObjectProperty *op;
3358 uint32_t mask = (1UL << bitnr);
3359
3360 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3361 if (op) {
3362 fp = op->opaque;
3363 assert(fp->ptr == field);
3364 fp->mask |= mask;
3365 } else {
3366 fp = g_new0(BitProperty, 1);
3367 fp->ptr = field;
3368 fp->mask = mask;
3369 object_property_add(OBJECT(cpu), prop_name, "bool",
3370 x86_cpu_get_bit_prop,
3371 x86_cpu_set_bit_prop,
3372 x86_cpu_release_bit_prop, fp, &error_abort);
3373 }
3374}
3375
3376static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3377 FeatureWord w,
3378 int bitnr)
3379{
3380 Object *obj = OBJECT(cpu);
3381 int i;
3382 char **names;
3383 FeatureWordInfo *fi = &feature_word_info[w];
3384
38e5c119
EH		 3385 if (!fi->feat_names[bitnr]) {
3386 return;
3387 }
3388
3389 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
3390
3391 feat2prop(names[0]);
3392 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
3393
3394 for (i = 1; names[i]; i++) {
3395 feat2prop(names[i]);
d461a44c 3396 object_property_add_alias(obj, names[i], obj, names[0],
38e5c119
EH		 3397 &error_abort);
3398 }
3399
3400 g_strfreev(names);
3401}
3402
de024815
AF		 3403static void x86_cpu_initfn(Object *obj)
3404{
55e5c285 3405 CPUState *cs = CPU(obj);
de024815 3406 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3407 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3408 CPUX86State *env = &cpu->env;
38e5c119 3409 FeatureWord w;
de024815 3410
c05efcb1 3411 cs->env_ptr = env;
71ad61d3
AF		 3412
3413 object_property_add(obj, "family", "int",
95b8519d 3414 x86_cpuid_version_get_family,
71ad61d3 3415 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3416 object_property_add(obj, "model", "int",
67e30c83 3417 x86_cpuid_version_get_model,
c5291a4f 3418 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3419 object_property_add(obj, "stepping", "int",
35112e41 3420 x86_cpuid_version_get_stepping,
036e2222 3421 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3422 object_property_add_str(obj, "vendor",
3423 x86_cpuid_get_vendor,
3424 x86_cpuid_set_vendor, NULL);
938d4c25 3425 object_property_add_str(obj, "model-id",
63e886eb 3426 x86_cpuid_get_model_id,
938d4c25 3427 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3428 object_property_add(obj, "tsc-frequency", "int",
3429 x86_cpuid_get_tsc_freq,
3430 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 3431 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3432 x86_cpu_get_feature_words,
7e5292b5
EH		 3433 NULL, NULL, (void *)env->features, NULL);
3434 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3435 x86_cpu_get_feature_words,
3436 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3437
92067bf4 3438 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3439
38e5c119
EH		 3440 for (w = 0; w < FEATURE_WORDS; w++) {
3441 int bitnr;
3442
3443 for (bitnr = 0; bitnr < 32; bitnr++) {
3444 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3445 }
3446 }
3447
d940ee9b 3448 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
de024815
AF		 3449}
3450
997395d3
IM		 3451static int64_t x86_cpu_get_arch_id(CPUState *cs)
3452{
3453 X86CPU *cpu = X86_CPU(cs);
997395d3 3454
7e72a45c 3455 return cpu->apic_id;
997395d3
IM		 3456}
3457
444d5590
AF		 3458static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3459{
3460 X86CPU *cpu = X86_CPU(cs);
3461
3462 return cpu->env.cr[0] & CR0_PG_MASK;
3463}
3464
f45748f1
AF		 3465static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3466{
3467 X86CPU *cpu = X86_CPU(cs);
3468
3469 cpu->env.eip = value;
3470}
3471
bdf7ae5b
AF		 3472static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3473{
3474 X86CPU *cpu = X86_CPU(cs);
3475
3476 cpu->env.eip = tb->pc - tb->cs_base;
3477}
3478
8c2e1b00
AF		 3479static bool x86_cpu_has_work(CPUState *cs)
3480{
3481 X86CPU *cpu = X86_CPU(cs);
3482 CPUX86State *env = &cpu->env;
3483
6220e900
PD		 3484 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3485 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3486 (env->eflags & IF_MASK)) ||
3487 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3488 CPU_INTERRUPT_INIT |
3489 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3490 CPU_INTERRUPT_MCE)) ||
3491 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3492 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3493}
3494
9337e3b6 3495static Property x86_cpu_properties[] = {
2da00e31
IM		 3496#ifdef CONFIG_USER_ONLY
3497 /* apic_id = 0 by default for *-user, see commit 9886e834 */
3498 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 3499 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
3500 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
3501 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 3502#else
3503 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 3504 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
3505 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
3506 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 3507#endif
9337e3b6 3508 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3509 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3510 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3511 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3512 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3513 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3514 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3515 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3516 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3517 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3518 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3519 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3520 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3521 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 3522 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 3523 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 3524 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 3525 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
3526 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
3527 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
3528 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
3529 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
3530 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
3531 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 3532 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 3533 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 3534 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 3535 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
9337e3b6
EH		 3536 DEFINE_PROP_END_OF_LIST()
3537};
3538
5fd2087a
AF		 3539static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3540{
3541 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3542 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3543 DeviceClass *dc = DEVICE_CLASS(oc);
3544
3545 xcc->parent_realize = dc->realize;
3546 dc->realize = x86_cpu_realizefn;
c884776e 3547 dc->unrealize = x86_cpu_unrealizefn;
9337e3b6 3548 dc->props = x86_cpu_properties;
5fd2087a
AF		 3549
3550 xcc->parent_reset = cc->reset;
3551 cc->reset = x86_cpu_reset;
91b1df8c 3552 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3553
500050d1 3554 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3555 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3556 cc->has_work = x86_cpu_has_work;
97a8ea5a 3557 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3558 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3559 cc->dump_state = x86_cpu_dump_state;
f45748f1 3560 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3561 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3562 cc->gdb_read_register = x86_cpu_gdb_read_register;
3563 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3564 cc->get_arch_id = x86_cpu_get_arch_id;
3565 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3566#ifdef CONFIG_USER_ONLY
3567 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3568#else
a23bbfda 3569 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3570 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3571 cc->write_elf64_note = x86_cpu_write_elf64_note;
3572 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3573 cc->write_elf32_note = x86_cpu_write_elf32_note;
3574 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3575 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3576#endif
a0e372f0 3577 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3578#ifndef CONFIG_USER_ONLY
3579 cc->debug_excp_handler = breakpoint_handler;
3580#endif
374e0cd4
RH		 3581 cc->cpu_exec_enter = x86_cpu_exec_enter;
3582 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27 3583
edd12111 3584 dc->cannot_instantiate_with_device_add_yet = false;
4c315c27
MA		 3585 /*
3586 * Reason: x86_cpu_initfn() calls cpu_exec_init(), which saves the
3587 * object in cpus -> dangling pointer after final object_unref().
3588 */
3589 dc->cannot_destroy_with_object_finalize_yet = true;
5fd2087a
AF		 3590}
3591
3592static const TypeInfo x86_cpu_type_info = {
3593 .name = TYPE_X86_CPU,
3594 .parent = TYPE_CPU,
3595 .instance_size = sizeof(X86CPU),
de024815 3596 .instance_init = x86_cpu_initfn,
d940ee9b 3597 .abstract = true,
5fd2087a
AF		 3598 .class_size = sizeof(X86CPUClass),
3599 .class_init = x86_cpu_common_class_init,
3600};
3601
3602static void x86_cpu_register_types(void)
3603{
d940ee9b
EH		 3604 int i;
3605
5fd2087a 3606 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3607 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3608 x86_register_cpudef_type(&builtin_x86_defs[i]);
3609 }
3610#ifdef CONFIG_KVM
3611 type_register_static(&host_x86_cpu_type_info);
3612#endif
5fd2087a
AF		 3613}
3614
3615type_init(x86_cpu_register_types)
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