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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
00b27a3e | 21 | #include "cpuid.h" |
d62caabb | 22 | #include "lapic.h" |
e495606d | 23 | |
edf88417 | 24 | #include <linux/kvm_host.h> |
6aa8b732 | 25 | #include <linux/module.h> |
9d8f549d | 26 | #include <linux/kernel.h> |
6aa8b732 AK |
27 | #include <linux/mm.h> |
28 | #include <linux/highmem.h> | |
e8edc6e0 | 29 | #include <linux/sched.h> |
c7addb90 | 30 | #include <linux/moduleparam.h> |
e9bda3b3 | 31 | #include <linux/mod_devicetable.h> |
af658dca | 32 | #include <linux/trace_events.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
cafd6659 | 34 | #include <linux/tboot.h> |
f4124500 | 35 | #include <linux/hrtimer.h> |
5fdbf976 | 36 | #include "kvm_cache_regs.h" |
35920a35 | 37 | #include "x86.h" |
e495606d | 38 | |
28b835d6 | 39 | #include <asm/cpu.h> |
6aa8b732 | 40 | #include <asm/io.h> |
3b3be0d1 | 41 | #include <asm/desc.h> |
13673a90 | 42 | #include <asm/vmx.h> |
6210e37b | 43 | #include <asm/virtext.h> |
a0861c02 | 44 | #include <asm/mce.h> |
952f07ec | 45 | #include <asm/fpu/internal.h> |
d7cd9796 | 46 | #include <asm/perf_event.h> |
81908bf4 | 47 | #include <asm/debugreg.h> |
8f536b76 | 48 | #include <asm/kexec.h> |
dab2087d | 49 | #include <asm/apic.h> |
efc64404 | 50 | #include <asm/irq_remapping.h> |
6aa8b732 | 51 | |
229456fc | 52 | #include "trace.h" |
25462f7f | 53 | #include "pmu.h" |
229456fc | 54 | |
4ecac3fd | 55 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
5e520e62 AK |
56 | #define __ex_clear(x, reg) \ |
57 | ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) | |
4ecac3fd | 58 | |
6aa8b732 AK |
59 | MODULE_AUTHOR("Qumranet"); |
60 | MODULE_LICENSE("GPL"); | |
61 | ||
e9bda3b3 JT |
62 | static const struct x86_cpu_id vmx_cpu_id[] = { |
63 | X86_FEATURE_MATCH(X86_FEATURE_VMX), | |
64 | {} | |
65 | }; | |
66 | MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); | |
67 | ||
476bc001 | 68 | static bool __read_mostly enable_vpid = 1; |
736caefe | 69 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 70 | |
476bc001 | 71 | static bool __read_mostly flexpriority_enabled = 1; |
736caefe | 72 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 73 | |
476bc001 | 74 | static bool __read_mostly enable_ept = 1; |
736caefe | 75 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 76 | |
476bc001 | 77 | static bool __read_mostly enable_unrestricted_guest = 1; |
3a624e29 NK |
78 | module_param_named(unrestricted_guest, |
79 | enable_unrestricted_guest, bool, S_IRUGO); | |
80 | ||
83c3a331 XH |
81 | static bool __read_mostly enable_ept_ad_bits = 1; |
82 | module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); | |
83 | ||
a27685c3 | 84 | static bool __read_mostly emulate_invalid_guest_state = true; |
c1f8bc04 | 85 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 86 | |
476bc001 | 87 | static bool __read_mostly vmm_exclusive = 1; |
b923e62e DX |
88 | module_param(vmm_exclusive, bool, S_IRUGO); |
89 | ||
476bc001 | 90 | static bool __read_mostly fasteoi = 1; |
58fbbf26 KT |
91 | module_param(fasteoi, bool, S_IRUGO); |
92 | ||
5a71785d | 93 | static bool __read_mostly enable_apicv = 1; |
01e439be | 94 | module_param(enable_apicv, bool, S_IRUGO); |
83d4c286 | 95 | |
abc4fc58 AG |
96 | static bool __read_mostly enable_shadow_vmcs = 1; |
97 | module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); | |
801d3424 NHE |
98 | /* |
99 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
100 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
101 | * use VMX instructions. | |
102 | */ | |
476bc001 | 103 | static bool __read_mostly nested = 0; |
801d3424 NHE |
104 | module_param(nested, bool, S_IRUGO); |
105 | ||
20300099 WL |
106 | static u64 __read_mostly host_xss; |
107 | ||
843e4330 KH |
108 | static bool __read_mostly enable_pml = 1; |
109 | module_param_named(pml, enable_pml, bool, S_IRUGO); | |
110 | ||
64903d61 HZ |
111 | #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL |
112 | ||
64672c95 YJ |
113 | /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ |
114 | static int __read_mostly cpu_preemption_timer_multi; | |
115 | static bool __read_mostly enable_preemption_timer = 1; | |
116 | #ifdef CONFIG_X86_64 | |
117 | module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); | |
118 | #endif | |
119 | ||
5037878e GN |
120 | #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD) |
121 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE) | |
cdc0e244 AK |
122 | #define KVM_VM_CR0_ALWAYS_ON \ |
123 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
124 | #define KVM_CR4_GUEST_OWNED_BITS \ |
125 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
52ce3c21 | 126 | | X86_CR4_OSXMMEXCPT | X86_CR4_TSD) |
4c38609a | 127 | |
cdc0e244 AK |
128 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
129 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
130 | ||
78ac8b47 AK |
131 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
132 | ||
f4124500 JK |
133 | #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 |
134 | ||
4b8d54f9 ZE |
135 | /* |
136 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
137 | * ple_gap: upper bound on the amount of time between two successive | |
138 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 139 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
140 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
141 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
142 | * less than 2^12 cycles | |
143 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
144 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
145 | */ | |
b4a2d31d RK |
146 | #define KVM_VMX_DEFAULT_PLE_GAP 128 |
147 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 | |
148 | #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2 | |
149 | #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0 | |
150 | #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \ | |
151 | INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW | |
152 | ||
4b8d54f9 ZE |
153 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; |
154 | module_param(ple_gap, int, S_IRUGO); | |
155 | ||
156 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
157 | module_param(ple_window, int, S_IRUGO); | |
158 | ||
b4a2d31d RK |
159 | /* Default doubles per-vcpu window every exit. */ |
160 | static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW; | |
161 | module_param(ple_window_grow, int, S_IRUGO); | |
162 | ||
163 | /* Default resets per-vcpu window every exit to ple_window. */ | |
164 | static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK; | |
165 | module_param(ple_window_shrink, int, S_IRUGO); | |
166 | ||
167 | /* Default is to compute the maximum so we can never overflow. */ | |
168 | static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
169 | static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
170 | module_param(ple_window_max, int, S_IRUGO); | |
171 | ||
83287ea4 AK |
172 | extern const ulong vmx_return; |
173 | ||
8bf00a52 | 174 | #define NR_AUTOLOAD_MSRS 8 |
ff2f6fe9 | 175 | #define VMCS02_POOL_SIZE 1 |
61d2ef2c | 176 | |
a2fa3e9f GH |
177 | struct vmcs { |
178 | u32 revision_id; | |
179 | u32 abort; | |
180 | char data[0]; | |
181 | }; | |
182 | ||
d462b819 NHE |
183 | /* |
184 | * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also | |
185 | * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs | |
186 | * loaded on this CPU (so we can clear them if the CPU goes down). | |
187 | */ | |
188 | struct loaded_vmcs { | |
189 | struct vmcs *vmcs; | |
190 | int cpu; | |
191 | int launched; | |
192 | struct list_head loaded_vmcss_on_cpu_link; | |
193 | }; | |
194 | ||
26bb0981 AK |
195 | struct shared_msr_entry { |
196 | unsigned index; | |
197 | u64 data; | |
d5696725 | 198 | u64 mask; |
26bb0981 AK |
199 | }; |
200 | ||
a9d30f33 NHE |
201 | /* |
202 | * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a | |
203 | * single nested guest (L2), hence the name vmcs12. Any VMX implementation has | |
204 | * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is | |
205 | * stored in guest memory specified by VMPTRLD, but is opaque to the guest, | |
206 | * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. | |
207 | * More than one of these structures may exist, if L1 runs multiple L2 guests. | |
208 | * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the | |
209 | * underlying hardware which will be used to run L2. | |
210 | * This structure is packed to ensure that its layout is identical across | |
211 | * machines (necessary for live migration). | |
212 | * If there are changes in this struct, VMCS12_REVISION must be changed. | |
213 | */ | |
22bd0358 | 214 | typedef u64 natural_width; |
a9d30f33 NHE |
215 | struct __packed vmcs12 { |
216 | /* According to the Intel spec, a VMCS region must start with the | |
217 | * following two fields. Then follow implementation-specific data. | |
218 | */ | |
219 | u32 revision_id; | |
220 | u32 abort; | |
22bd0358 | 221 | |
27d6c865 NHE |
222 | u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ |
223 | u32 padding[7]; /* room for future expansion */ | |
224 | ||
22bd0358 NHE |
225 | u64 io_bitmap_a; |
226 | u64 io_bitmap_b; | |
227 | u64 msr_bitmap; | |
228 | u64 vm_exit_msr_store_addr; | |
229 | u64 vm_exit_msr_load_addr; | |
230 | u64 vm_entry_msr_load_addr; | |
231 | u64 tsc_offset; | |
232 | u64 virtual_apic_page_addr; | |
233 | u64 apic_access_addr; | |
705699a1 | 234 | u64 posted_intr_desc_addr; |
22bd0358 | 235 | u64 ept_pointer; |
608406e2 WV |
236 | u64 eoi_exit_bitmap0; |
237 | u64 eoi_exit_bitmap1; | |
238 | u64 eoi_exit_bitmap2; | |
239 | u64 eoi_exit_bitmap3; | |
81dc01f7 | 240 | u64 xss_exit_bitmap; |
22bd0358 NHE |
241 | u64 guest_physical_address; |
242 | u64 vmcs_link_pointer; | |
243 | u64 guest_ia32_debugctl; | |
244 | u64 guest_ia32_pat; | |
245 | u64 guest_ia32_efer; | |
246 | u64 guest_ia32_perf_global_ctrl; | |
247 | u64 guest_pdptr0; | |
248 | u64 guest_pdptr1; | |
249 | u64 guest_pdptr2; | |
250 | u64 guest_pdptr3; | |
36be0b9d | 251 | u64 guest_bndcfgs; |
22bd0358 NHE |
252 | u64 host_ia32_pat; |
253 | u64 host_ia32_efer; | |
254 | u64 host_ia32_perf_global_ctrl; | |
255 | u64 padding64[8]; /* room for future expansion */ | |
256 | /* | |
257 | * To allow migration of L1 (complete with its L2 guests) between | |
258 | * machines of different natural widths (32 or 64 bit), we cannot have | |
259 | * unsigned long fields with no explict size. We use u64 (aliased | |
260 | * natural_width) instead. Luckily, x86 is little-endian. | |
261 | */ | |
262 | natural_width cr0_guest_host_mask; | |
263 | natural_width cr4_guest_host_mask; | |
264 | natural_width cr0_read_shadow; | |
265 | natural_width cr4_read_shadow; | |
266 | natural_width cr3_target_value0; | |
267 | natural_width cr3_target_value1; | |
268 | natural_width cr3_target_value2; | |
269 | natural_width cr3_target_value3; | |
270 | natural_width exit_qualification; | |
271 | natural_width guest_linear_address; | |
272 | natural_width guest_cr0; | |
273 | natural_width guest_cr3; | |
274 | natural_width guest_cr4; | |
275 | natural_width guest_es_base; | |
276 | natural_width guest_cs_base; | |
277 | natural_width guest_ss_base; | |
278 | natural_width guest_ds_base; | |
279 | natural_width guest_fs_base; | |
280 | natural_width guest_gs_base; | |
281 | natural_width guest_ldtr_base; | |
282 | natural_width guest_tr_base; | |
283 | natural_width guest_gdtr_base; | |
284 | natural_width guest_idtr_base; | |
285 | natural_width guest_dr7; | |
286 | natural_width guest_rsp; | |
287 | natural_width guest_rip; | |
288 | natural_width guest_rflags; | |
289 | natural_width guest_pending_dbg_exceptions; | |
290 | natural_width guest_sysenter_esp; | |
291 | natural_width guest_sysenter_eip; | |
292 | natural_width host_cr0; | |
293 | natural_width host_cr3; | |
294 | natural_width host_cr4; | |
295 | natural_width host_fs_base; | |
296 | natural_width host_gs_base; | |
297 | natural_width host_tr_base; | |
298 | natural_width host_gdtr_base; | |
299 | natural_width host_idtr_base; | |
300 | natural_width host_ia32_sysenter_esp; | |
301 | natural_width host_ia32_sysenter_eip; | |
302 | natural_width host_rsp; | |
303 | natural_width host_rip; | |
304 | natural_width paddingl[8]; /* room for future expansion */ | |
305 | u32 pin_based_vm_exec_control; | |
306 | u32 cpu_based_vm_exec_control; | |
307 | u32 exception_bitmap; | |
308 | u32 page_fault_error_code_mask; | |
309 | u32 page_fault_error_code_match; | |
310 | u32 cr3_target_count; | |
311 | u32 vm_exit_controls; | |
312 | u32 vm_exit_msr_store_count; | |
313 | u32 vm_exit_msr_load_count; | |
314 | u32 vm_entry_controls; | |
315 | u32 vm_entry_msr_load_count; | |
316 | u32 vm_entry_intr_info_field; | |
317 | u32 vm_entry_exception_error_code; | |
318 | u32 vm_entry_instruction_len; | |
319 | u32 tpr_threshold; | |
320 | u32 secondary_vm_exec_control; | |
321 | u32 vm_instruction_error; | |
322 | u32 vm_exit_reason; | |
323 | u32 vm_exit_intr_info; | |
324 | u32 vm_exit_intr_error_code; | |
325 | u32 idt_vectoring_info_field; | |
326 | u32 idt_vectoring_error_code; | |
327 | u32 vm_exit_instruction_len; | |
328 | u32 vmx_instruction_info; | |
329 | u32 guest_es_limit; | |
330 | u32 guest_cs_limit; | |
331 | u32 guest_ss_limit; | |
332 | u32 guest_ds_limit; | |
333 | u32 guest_fs_limit; | |
334 | u32 guest_gs_limit; | |
335 | u32 guest_ldtr_limit; | |
336 | u32 guest_tr_limit; | |
337 | u32 guest_gdtr_limit; | |
338 | u32 guest_idtr_limit; | |
339 | u32 guest_es_ar_bytes; | |
340 | u32 guest_cs_ar_bytes; | |
341 | u32 guest_ss_ar_bytes; | |
342 | u32 guest_ds_ar_bytes; | |
343 | u32 guest_fs_ar_bytes; | |
344 | u32 guest_gs_ar_bytes; | |
345 | u32 guest_ldtr_ar_bytes; | |
346 | u32 guest_tr_ar_bytes; | |
347 | u32 guest_interruptibility_info; | |
348 | u32 guest_activity_state; | |
349 | u32 guest_sysenter_cs; | |
350 | u32 host_ia32_sysenter_cs; | |
0238ea91 JK |
351 | u32 vmx_preemption_timer_value; |
352 | u32 padding32[7]; /* room for future expansion */ | |
22bd0358 | 353 | u16 virtual_processor_id; |
705699a1 | 354 | u16 posted_intr_nv; |
22bd0358 NHE |
355 | u16 guest_es_selector; |
356 | u16 guest_cs_selector; | |
357 | u16 guest_ss_selector; | |
358 | u16 guest_ds_selector; | |
359 | u16 guest_fs_selector; | |
360 | u16 guest_gs_selector; | |
361 | u16 guest_ldtr_selector; | |
362 | u16 guest_tr_selector; | |
608406e2 | 363 | u16 guest_intr_status; |
22bd0358 NHE |
364 | u16 host_es_selector; |
365 | u16 host_cs_selector; | |
366 | u16 host_ss_selector; | |
367 | u16 host_ds_selector; | |
368 | u16 host_fs_selector; | |
369 | u16 host_gs_selector; | |
370 | u16 host_tr_selector; | |
a9d30f33 NHE |
371 | }; |
372 | ||
373 | /* | |
374 | * VMCS12_REVISION is an arbitrary id that should be changed if the content or | |
375 | * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and | |
376 | * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. | |
377 | */ | |
378 | #define VMCS12_REVISION 0x11e57ed0 | |
379 | ||
380 | /* | |
381 | * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region | |
382 | * and any VMCS region. Although only sizeof(struct vmcs12) are used by the | |
383 | * current implementation, 4K are reserved to avoid future complications. | |
384 | */ | |
385 | #define VMCS12_SIZE 0x1000 | |
386 | ||
ff2f6fe9 NHE |
387 | /* Used to remember the last vmcs02 used for some recently used vmcs12s */ |
388 | struct vmcs02_list { | |
389 | struct list_head list; | |
390 | gpa_t vmptr; | |
391 | struct loaded_vmcs vmcs02; | |
392 | }; | |
393 | ||
ec378aee NHE |
394 | /* |
395 | * The nested_vmx structure is part of vcpu_vmx, and holds information we need | |
396 | * for correct emulation of VMX (i.e., nested VMX) on this vcpu. | |
397 | */ | |
398 | struct nested_vmx { | |
399 | /* Has the level1 guest done vmxon? */ | |
400 | bool vmxon; | |
3573e22c | 401 | gpa_t vmxon_ptr; |
a9d30f33 NHE |
402 | |
403 | /* The guest-physical address of the current VMCS L1 keeps for L2 */ | |
404 | gpa_t current_vmptr; | |
405 | /* The host-usable pointer to the above */ | |
406 | struct page *current_vmcs12_page; | |
407 | struct vmcs12 *current_vmcs12; | |
8de48833 | 408 | struct vmcs *current_shadow_vmcs; |
012f83cb AG |
409 | /* |
410 | * Indicates if the shadow vmcs must be updated with the | |
411 | * data hold by vmcs12 | |
412 | */ | |
413 | bool sync_shadow_vmcs; | |
ff2f6fe9 NHE |
414 | |
415 | /* vmcs02_list cache of VMCSs recently used to run L2 guests */ | |
416 | struct list_head vmcs02_pool; | |
417 | int vmcs02_num; | |
fe3ef05c | 418 | u64 vmcs01_tsc_offset; |
644d711a NHE |
419 | /* L2 must run next, and mustn't decide to exit to L1. */ |
420 | bool nested_run_pending; | |
fe3ef05c NHE |
421 | /* |
422 | * Guest pages referred to in vmcs02 with host-physical pointers, so | |
423 | * we must keep them pinned while L2 runs. | |
424 | */ | |
425 | struct page *apic_access_page; | |
a7c0b07d | 426 | struct page *virtual_apic_page; |
705699a1 WV |
427 | struct page *pi_desc_page; |
428 | struct pi_desc *pi_desc; | |
429 | bool pi_pending; | |
430 | u16 posted_intr_nv; | |
b3897a49 | 431 | u64 msr_ia32_feature_control; |
f4124500 JK |
432 | |
433 | struct hrtimer preemption_timer; | |
434 | bool preemption_timer_expired; | |
2996fca0 JK |
435 | |
436 | /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ | |
437 | u64 vmcs01_debugctl; | |
b9c237bb | 438 | |
5c614b35 WL |
439 | u16 vpid02; |
440 | u16 last_vpid; | |
441 | ||
b9c237bb WV |
442 | u32 nested_vmx_procbased_ctls_low; |
443 | u32 nested_vmx_procbased_ctls_high; | |
444 | u32 nested_vmx_true_procbased_ctls_low; | |
445 | u32 nested_vmx_secondary_ctls_low; | |
446 | u32 nested_vmx_secondary_ctls_high; | |
447 | u32 nested_vmx_pinbased_ctls_low; | |
448 | u32 nested_vmx_pinbased_ctls_high; | |
449 | u32 nested_vmx_exit_ctls_low; | |
450 | u32 nested_vmx_exit_ctls_high; | |
451 | u32 nested_vmx_true_exit_ctls_low; | |
452 | u32 nested_vmx_entry_ctls_low; | |
453 | u32 nested_vmx_entry_ctls_high; | |
454 | u32 nested_vmx_true_entry_ctls_low; | |
455 | u32 nested_vmx_misc_low; | |
456 | u32 nested_vmx_misc_high; | |
457 | u32 nested_vmx_ept_caps; | |
99b83ac8 | 458 | u32 nested_vmx_vpid_caps; |
ec378aee NHE |
459 | }; |
460 | ||
01e439be | 461 | #define POSTED_INTR_ON 0 |
ebbfc765 FW |
462 | #define POSTED_INTR_SN 1 |
463 | ||
01e439be YZ |
464 | /* Posted-Interrupt Descriptor */ |
465 | struct pi_desc { | |
466 | u32 pir[8]; /* Posted interrupt requested */ | |
6ef1522f FW |
467 | union { |
468 | struct { | |
469 | /* bit 256 - Outstanding Notification */ | |
470 | u16 on : 1, | |
471 | /* bit 257 - Suppress Notification */ | |
472 | sn : 1, | |
473 | /* bit 271:258 - Reserved */ | |
474 | rsvd_1 : 14; | |
475 | /* bit 279:272 - Notification Vector */ | |
476 | u8 nv; | |
477 | /* bit 287:280 - Reserved */ | |
478 | u8 rsvd_2; | |
479 | /* bit 319:288 - Notification Destination */ | |
480 | u32 ndst; | |
481 | }; | |
482 | u64 control; | |
483 | }; | |
484 | u32 rsvd[6]; | |
01e439be YZ |
485 | } __aligned(64); |
486 | ||
a20ed54d YZ |
487 | static bool pi_test_and_set_on(struct pi_desc *pi_desc) |
488 | { | |
489 | return test_and_set_bit(POSTED_INTR_ON, | |
490 | (unsigned long *)&pi_desc->control); | |
491 | } | |
492 | ||
493 | static bool pi_test_and_clear_on(struct pi_desc *pi_desc) | |
494 | { | |
495 | return test_and_clear_bit(POSTED_INTR_ON, | |
496 | (unsigned long *)&pi_desc->control); | |
497 | } | |
498 | ||
499 | static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) | |
500 | { | |
501 | return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); | |
502 | } | |
503 | ||
ebbfc765 FW |
504 | static inline void pi_clear_sn(struct pi_desc *pi_desc) |
505 | { | |
506 | return clear_bit(POSTED_INTR_SN, | |
507 | (unsigned long *)&pi_desc->control); | |
508 | } | |
509 | ||
510 | static inline void pi_set_sn(struct pi_desc *pi_desc) | |
511 | { | |
512 | return set_bit(POSTED_INTR_SN, | |
513 | (unsigned long *)&pi_desc->control); | |
514 | } | |
515 | ||
516 | static inline int pi_test_on(struct pi_desc *pi_desc) | |
517 | { | |
518 | return test_bit(POSTED_INTR_ON, | |
519 | (unsigned long *)&pi_desc->control); | |
520 | } | |
521 | ||
522 | static inline int pi_test_sn(struct pi_desc *pi_desc) | |
523 | { | |
524 | return test_bit(POSTED_INTR_SN, | |
525 | (unsigned long *)&pi_desc->control); | |
526 | } | |
527 | ||
a2fa3e9f | 528 | struct vcpu_vmx { |
fb3f0f51 | 529 | struct kvm_vcpu vcpu; |
313dbd49 | 530 | unsigned long host_rsp; |
29bd8a78 | 531 | u8 fail; |
9d58b931 | 532 | bool nmi_known_unmasked; |
51aa01d1 | 533 | u32 exit_intr_info; |
1155f76a | 534 | u32 idt_vectoring_info; |
6de12732 | 535 | ulong rflags; |
26bb0981 | 536 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
537 | int nmsrs; |
538 | int save_nmsrs; | |
a547c6db | 539 | unsigned long host_idt_base; |
a2fa3e9f | 540 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
541 | u64 msr_host_kernel_gs_base; |
542 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f | 543 | #endif |
2961e876 GN |
544 | u32 vm_entry_controls_shadow; |
545 | u32 vm_exit_controls_shadow; | |
d462b819 NHE |
546 | /* |
547 | * loaded_vmcs points to the VMCS currently used in this vcpu. For a | |
548 | * non-nested (L1) guest, it always points to vmcs01. For a nested | |
549 | * guest (L2), it points to a different VMCS. | |
550 | */ | |
551 | struct loaded_vmcs vmcs01; | |
552 | struct loaded_vmcs *loaded_vmcs; | |
553 | bool __launched; /* temporary, used in vmx_vcpu_run */ | |
61d2ef2c AK |
554 | struct msr_autoload { |
555 | unsigned nr; | |
556 | struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; | |
557 | struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; | |
558 | } msr_autoload; | |
a2fa3e9f GH |
559 | struct { |
560 | int loaded; | |
561 | u16 fs_sel, gs_sel, ldt_sel; | |
b2da15ac AK |
562 | #ifdef CONFIG_X86_64 |
563 | u16 ds_sel, es_sel; | |
564 | #endif | |
152d3f2f LV |
565 | int gs_ldt_reload_needed; |
566 | int fs_reload_needed; | |
da8999d3 | 567 | u64 msr_host_bndcfgs; |
d974baa3 | 568 | unsigned long vmcs_host_cr4; /* May not match real cr4 */ |
d77c26fc | 569 | } host_state; |
9c8cba37 | 570 | struct { |
7ffd92c5 | 571 | int vm86_active; |
78ac8b47 | 572 | ulong save_rflags; |
f5f7b2fe AK |
573 | struct kvm_segment segs[8]; |
574 | } rmode; | |
575 | struct { | |
576 | u32 bitmask; /* 4 bits per segment (1 bit per field) */ | |
7ffd92c5 AK |
577 | struct kvm_save_segment { |
578 | u16 selector; | |
579 | unsigned long base; | |
580 | u32 limit; | |
581 | u32 ar; | |
f5f7b2fe | 582 | } seg[8]; |
2fb92db1 | 583 | } segment_cache; |
2384d2b3 | 584 | int vpid; |
04fa4d32 | 585 | bool emulation_required; |
3b86cd99 JK |
586 | |
587 | /* Support for vnmi-less CPUs */ | |
588 | int soft_vnmi_blocked; | |
589 | ktime_t entry_time; | |
590 | s64 vnmi_blocked_time; | |
a0861c02 | 591 | u32 exit_reason; |
4e47c7a6 | 592 | |
01e439be YZ |
593 | /* Posted interrupt descriptor */ |
594 | struct pi_desc pi_desc; | |
595 | ||
ec378aee NHE |
596 | /* Support for a guest hypervisor (nested VMX) */ |
597 | struct nested_vmx nested; | |
a7653ecd RK |
598 | |
599 | /* Dynamic PLE window. */ | |
600 | int ple_window; | |
601 | bool ple_window_dirty; | |
843e4330 KH |
602 | |
603 | /* Support for PML */ | |
604 | #define PML_ENTITY_NUM 512 | |
605 | struct page *pml_pg; | |
2680d6da | 606 | |
64672c95 YJ |
607 | /* apic deadline value in host tsc */ |
608 | u64 hv_deadline_tsc; | |
609 | ||
2680d6da | 610 | u64 current_tsc_ratio; |
1be0e61c XG |
611 | |
612 | bool guest_pkru_valid; | |
613 | u32 guest_pkru; | |
614 | u32 host_pkru; | |
a2fa3e9f GH |
615 | }; |
616 | ||
2fb92db1 AK |
617 | enum segment_cache_field { |
618 | SEG_FIELD_SEL = 0, | |
619 | SEG_FIELD_BASE = 1, | |
620 | SEG_FIELD_LIMIT = 2, | |
621 | SEG_FIELD_AR = 3, | |
622 | ||
623 | SEG_FIELD_NR = 4 | |
624 | }; | |
625 | ||
a2fa3e9f GH |
626 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
627 | { | |
fb3f0f51 | 628 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
629 | } |
630 | ||
efc64404 FW |
631 | static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu) |
632 | { | |
633 | return &(to_vmx(vcpu)->pi_desc); | |
634 | } | |
635 | ||
22bd0358 NHE |
636 | #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x) |
637 | #define FIELD(number, name) [number] = VMCS12_OFFSET(name) | |
638 | #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \ | |
639 | [number##_HIGH] = VMCS12_OFFSET(name)+4 | |
640 | ||
4607c2d7 | 641 | |
fe2b201b | 642 | static unsigned long shadow_read_only_fields[] = { |
4607c2d7 AG |
643 | /* |
644 | * We do NOT shadow fields that are modified when L0 | |
645 | * traps and emulates any vmx instruction (e.g. VMPTRLD, | |
646 | * VMXON...) executed by L1. | |
647 | * For example, VM_INSTRUCTION_ERROR is read | |
648 | * by L1 if a vmx instruction fails (part of the error path). | |
649 | * Note the code assumes this logic. If for some reason | |
650 | * we start shadowing these fields then we need to | |
651 | * force a shadow sync when L0 emulates vmx instructions | |
652 | * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified | |
653 | * by nested_vmx_failValid) | |
654 | */ | |
655 | VM_EXIT_REASON, | |
656 | VM_EXIT_INTR_INFO, | |
657 | VM_EXIT_INSTRUCTION_LEN, | |
658 | IDT_VECTORING_INFO_FIELD, | |
659 | IDT_VECTORING_ERROR_CODE, | |
660 | VM_EXIT_INTR_ERROR_CODE, | |
661 | EXIT_QUALIFICATION, | |
662 | GUEST_LINEAR_ADDRESS, | |
663 | GUEST_PHYSICAL_ADDRESS | |
664 | }; | |
fe2b201b | 665 | static int max_shadow_read_only_fields = |
4607c2d7 AG |
666 | ARRAY_SIZE(shadow_read_only_fields); |
667 | ||
fe2b201b | 668 | static unsigned long shadow_read_write_fields[] = { |
a7c0b07d | 669 | TPR_THRESHOLD, |
4607c2d7 AG |
670 | GUEST_RIP, |
671 | GUEST_RSP, | |
672 | GUEST_CR0, | |
673 | GUEST_CR3, | |
674 | GUEST_CR4, | |
675 | GUEST_INTERRUPTIBILITY_INFO, | |
676 | GUEST_RFLAGS, | |
677 | GUEST_CS_SELECTOR, | |
678 | GUEST_CS_AR_BYTES, | |
679 | GUEST_CS_LIMIT, | |
680 | GUEST_CS_BASE, | |
681 | GUEST_ES_BASE, | |
36be0b9d | 682 | GUEST_BNDCFGS, |
4607c2d7 AG |
683 | CR0_GUEST_HOST_MASK, |
684 | CR0_READ_SHADOW, | |
685 | CR4_READ_SHADOW, | |
686 | TSC_OFFSET, | |
687 | EXCEPTION_BITMAP, | |
688 | CPU_BASED_VM_EXEC_CONTROL, | |
689 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
690 | VM_ENTRY_INTR_INFO_FIELD, | |
691 | VM_ENTRY_INSTRUCTION_LEN, | |
692 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
693 | HOST_FS_BASE, | |
694 | HOST_GS_BASE, | |
695 | HOST_FS_SELECTOR, | |
696 | HOST_GS_SELECTOR | |
697 | }; | |
fe2b201b | 698 | static int max_shadow_read_write_fields = |
4607c2d7 AG |
699 | ARRAY_SIZE(shadow_read_write_fields); |
700 | ||
772e0318 | 701 | static const unsigned short vmcs_field_to_offset_table[] = { |
22bd0358 | 702 | FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id), |
705699a1 | 703 | FIELD(POSTED_INTR_NV, posted_intr_nv), |
22bd0358 NHE |
704 | FIELD(GUEST_ES_SELECTOR, guest_es_selector), |
705 | FIELD(GUEST_CS_SELECTOR, guest_cs_selector), | |
706 | FIELD(GUEST_SS_SELECTOR, guest_ss_selector), | |
707 | FIELD(GUEST_DS_SELECTOR, guest_ds_selector), | |
708 | FIELD(GUEST_FS_SELECTOR, guest_fs_selector), | |
709 | FIELD(GUEST_GS_SELECTOR, guest_gs_selector), | |
710 | FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector), | |
711 | FIELD(GUEST_TR_SELECTOR, guest_tr_selector), | |
608406e2 | 712 | FIELD(GUEST_INTR_STATUS, guest_intr_status), |
22bd0358 NHE |
713 | FIELD(HOST_ES_SELECTOR, host_es_selector), |
714 | FIELD(HOST_CS_SELECTOR, host_cs_selector), | |
715 | FIELD(HOST_SS_SELECTOR, host_ss_selector), | |
716 | FIELD(HOST_DS_SELECTOR, host_ds_selector), | |
717 | FIELD(HOST_FS_SELECTOR, host_fs_selector), | |
718 | FIELD(HOST_GS_SELECTOR, host_gs_selector), | |
719 | FIELD(HOST_TR_SELECTOR, host_tr_selector), | |
720 | FIELD64(IO_BITMAP_A, io_bitmap_a), | |
721 | FIELD64(IO_BITMAP_B, io_bitmap_b), | |
722 | FIELD64(MSR_BITMAP, msr_bitmap), | |
723 | FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr), | |
724 | FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr), | |
725 | FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr), | |
726 | FIELD64(TSC_OFFSET, tsc_offset), | |
727 | FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), | |
728 | FIELD64(APIC_ACCESS_ADDR, apic_access_addr), | |
705699a1 | 729 | FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr), |
22bd0358 | 730 | FIELD64(EPT_POINTER, ept_pointer), |
608406e2 WV |
731 | FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0), |
732 | FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1), | |
733 | FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2), | |
734 | FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3), | |
81dc01f7 | 735 | FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap), |
22bd0358 NHE |
736 | FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), |
737 | FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), | |
738 | FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), | |
739 | FIELD64(GUEST_IA32_PAT, guest_ia32_pat), | |
740 | FIELD64(GUEST_IA32_EFER, guest_ia32_efer), | |
741 | FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl), | |
742 | FIELD64(GUEST_PDPTR0, guest_pdptr0), | |
743 | FIELD64(GUEST_PDPTR1, guest_pdptr1), | |
744 | FIELD64(GUEST_PDPTR2, guest_pdptr2), | |
745 | FIELD64(GUEST_PDPTR3, guest_pdptr3), | |
36be0b9d | 746 | FIELD64(GUEST_BNDCFGS, guest_bndcfgs), |
22bd0358 NHE |
747 | FIELD64(HOST_IA32_PAT, host_ia32_pat), |
748 | FIELD64(HOST_IA32_EFER, host_ia32_efer), | |
749 | FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), | |
750 | FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), | |
751 | FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), | |
752 | FIELD(EXCEPTION_BITMAP, exception_bitmap), | |
753 | FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask), | |
754 | FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match), | |
755 | FIELD(CR3_TARGET_COUNT, cr3_target_count), | |
756 | FIELD(VM_EXIT_CONTROLS, vm_exit_controls), | |
757 | FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count), | |
758 | FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count), | |
759 | FIELD(VM_ENTRY_CONTROLS, vm_entry_controls), | |
760 | FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count), | |
761 | FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field), | |
762 | FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code), | |
763 | FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len), | |
764 | FIELD(TPR_THRESHOLD, tpr_threshold), | |
765 | FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control), | |
766 | FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error), | |
767 | FIELD(VM_EXIT_REASON, vm_exit_reason), | |
768 | FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info), | |
769 | FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code), | |
770 | FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field), | |
771 | FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code), | |
772 | FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len), | |
773 | FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info), | |
774 | FIELD(GUEST_ES_LIMIT, guest_es_limit), | |
775 | FIELD(GUEST_CS_LIMIT, guest_cs_limit), | |
776 | FIELD(GUEST_SS_LIMIT, guest_ss_limit), | |
777 | FIELD(GUEST_DS_LIMIT, guest_ds_limit), | |
778 | FIELD(GUEST_FS_LIMIT, guest_fs_limit), | |
779 | FIELD(GUEST_GS_LIMIT, guest_gs_limit), | |
780 | FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit), | |
781 | FIELD(GUEST_TR_LIMIT, guest_tr_limit), | |
782 | FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit), | |
783 | FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit), | |
784 | FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes), | |
785 | FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes), | |
786 | FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes), | |
787 | FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes), | |
788 | FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes), | |
789 | FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes), | |
790 | FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes), | |
791 | FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes), | |
792 | FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info), | |
793 | FIELD(GUEST_ACTIVITY_STATE, guest_activity_state), | |
794 | FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs), | |
795 | FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs), | |
0238ea91 | 796 | FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value), |
22bd0358 NHE |
797 | FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask), |
798 | FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask), | |
799 | FIELD(CR0_READ_SHADOW, cr0_read_shadow), | |
800 | FIELD(CR4_READ_SHADOW, cr4_read_shadow), | |
801 | FIELD(CR3_TARGET_VALUE0, cr3_target_value0), | |
802 | FIELD(CR3_TARGET_VALUE1, cr3_target_value1), | |
803 | FIELD(CR3_TARGET_VALUE2, cr3_target_value2), | |
804 | FIELD(CR3_TARGET_VALUE3, cr3_target_value3), | |
805 | FIELD(EXIT_QUALIFICATION, exit_qualification), | |
806 | FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address), | |
807 | FIELD(GUEST_CR0, guest_cr0), | |
808 | FIELD(GUEST_CR3, guest_cr3), | |
809 | FIELD(GUEST_CR4, guest_cr4), | |
810 | FIELD(GUEST_ES_BASE, guest_es_base), | |
811 | FIELD(GUEST_CS_BASE, guest_cs_base), | |
812 | FIELD(GUEST_SS_BASE, guest_ss_base), | |
813 | FIELD(GUEST_DS_BASE, guest_ds_base), | |
814 | FIELD(GUEST_FS_BASE, guest_fs_base), | |
815 | FIELD(GUEST_GS_BASE, guest_gs_base), | |
816 | FIELD(GUEST_LDTR_BASE, guest_ldtr_base), | |
817 | FIELD(GUEST_TR_BASE, guest_tr_base), | |
818 | FIELD(GUEST_GDTR_BASE, guest_gdtr_base), | |
819 | FIELD(GUEST_IDTR_BASE, guest_idtr_base), | |
820 | FIELD(GUEST_DR7, guest_dr7), | |
821 | FIELD(GUEST_RSP, guest_rsp), | |
822 | FIELD(GUEST_RIP, guest_rip), | |
823 | FIELD(GUEST_RFLAGS, guest_rflags), | |
824 | FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions), | |
825 | FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp), | |
826 | FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip), | |
827 | FIELD(HOST_CR0, host_cr0), | |
828 | FIELD(HOST_CR3, host_cr3), | |
829 | FIELD(HOST_CR4, host_cr4), | |
830 | FIELD(HOST_FS_BASE, host_fs_base), | |
831 | FIELD(HOST_GS_BASE, host_gs_base), | |
832 | FIELD(HOST_TR_BASE, host_tr_base), | |
833 | FIELD(HOST_GDTR_BASE, host_gdtr_base), | |
834 | FIELD(HOST_IDTR_BASE, host_idtr_base), | |
835 | FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp), | |
836 | FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip), | |
837 | FIELD(HOST_RSP, host_rsp), | |
838 | FIELD(HOST_RIP, host_rip), | |
839 | }; | |
22bd0358 NHE |
840 | |
841 | static inline short vmcs_field_to_offset(unsigned long field) | |
842 | { | |
a2ae9df7 PB |
843 | BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX); |
844 | ||
845 | if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) || | |
846 | vmcs_field_to_offset_table[field] == 0) | |
847 | return -ENOENT; | |
848 | ||
22bd0358 NHE |
849 | return vmcs_field_to_offset_table[field]; |
850 | } | |
851 | ||
a9d30f33 NHE |
852 | static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
853 | { | |
854 | return to_vmx(vcpu)->nested.current_vmcs12; | |
855 | } | |
856 | ||
857 | static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr) | |
858 | { | |
54bf36aa | 859 | struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT); |
32cad84f | 860 | if (is_error_page(page)) |
a9d30f33 | 861 | return NULL; |
32cad84f | 862 | |
a9d30f33 NHE |
863 | return page; |
864 | } | |
865 | ||
866 | static void nested_release_page(struct page *page) | |
867 | { | |
868 | kvm_release_page_dirty(page); | |
869 | } | |
870 | ||
871 | static void nested_release_page_clean(struct page *page) | |
872 | { | |
873 | kvm_release_page_clean(page); | |
874 | } | |
875 | ||
bfd0a56b | 876 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu); |
4e1096d2 | 877 | static u64 construct_eptp(unsigned long root_hpa); |
4610c9cc DX |
878 | static void kvm_cpu_vmxon(u64 addr); |
879 | static void kvm_cpu_vmxoff(void); | |
f53cd63c | 880 | static bool vmx_xsaves_supported(void); |
776e58ea | 881 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr); |
b246dd5d OW |
882 | static void vmx_set_segment(struct kvm_vcpu *vcpu, |
883 | struct kvm_segment *var, int seg); | |
884 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
885 | struct kvm_segment *var, int seg); | |
d99e4152 GN |
886 | static bool guest_state_valid(struct kvm_vcpu *vcpu); |
887 | static u32 vmx_segment_access_rights(struct kvm_segment *var); | |
c3114420 | 888 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx); |
16f5b903 | 889 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx); |
a255d479 | 890 | static int alloc_identity_pagetable(struct kvm *kvm); |
75880a01 | 891 | |
6aa8b732 AK |
892 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
893 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
d462b819 NHE |
894 | /* |
895 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
896 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
897 | */ | |
898 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
3444d7da | 899 | static DEFINE_PER_CPU(struct desc_ptr, host_gdt); |
6aa8b732 | 900 | |
bf9f6ac8 FW |
901 | /* |
902 | * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we | |
903 | * can find which vCPU should be waken up. | |
904 | */ | |
905 | static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); | |
906 | static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); | |
907 | ||
3e7c73e9 AK |
908 | static unsigned long *vmx_io_bitmap_a; |
909 | static unsigned long *vmx_io_bitmap_b; | |
5897297b AK |
910 | static unsigned long *vmx_msr_bitmap_legacy; |
911 | static unsigned long *vmx_msr_bitmap_longmode; | |
8d14695f YZ |
912 | static unsigned long *vmx_msr_bitmap_legacy_x2apic; |
913 | static unsigned long *vmx_msr_bitmap_longmode_x2apic; | |
3af18d9c | 914 | static unsigned long *vmx_msr_bitmap_nested; |
4607c2d7 AG |
915 | static unsigned long *vmx_vmread_bitmap; |
916 | static unsigned long *vmx_vmwrite_bitmap; | |
fdef3ad1 | 917 | |
110312c8 | 918 | static bool cpu_has_load_ia32_efer; |
8bf00a52 | 919 | static bool cpu_has_load_perf_global_ctrl; |
110312c8 | 920 | |
2384d2b3 SY |
921 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
922 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
923 | ||
1c3d14fe | 924 | static struct vmcs_config { |
6aa8b732 AK |
925 | int size; |
926 | int order; | |
927 | u32 revision_id; | |
1c3d14fe YS |
928 | u32 pin_based_exec_ctrl; |
929 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 930 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
931 | u32 vmexit_ctrl; |
932 | u32 vmentry_ctrl; | |
933 | } vmcs_config; | |
6aa8b732 | 934 | |
efff9e53 | 935 | static struct vmx_capability { |
d56f546d SY |
936 | u32 ept; |
937 | u32 vpid; | |
938 | } vmx_capability; | |
939 | ||
6aa8b732 AK |
940 | #define VMX_SEGMENT_FIELD(seg) \ |
941 | [VCPU_SREG_##seg] = { \ | |
942 | .selector = GUEST_##seg##_SELECTOR, \ | |
943 | .base = GUEST_##seg##_BASE, \ | |
944 | .limit = GUEST_##seg##_LIMIT, \ | |
945 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
946 | } | |
947 | ||
772e0318 | 948 | static const struct kvm_vmx_segment_field { |
6aa8b732 AK |
949 | unsigned selector; |
950 | unsigned base; | |
951 | unsigned limit; | |
952 | unsigned ar_bytes; | |
953 | } kvm_vmx_segment_fields[] = { | |
954 | VMX_SEGMENT_FIELD(CS), | |
955 | VMX_SEGMENT_FIELD(DS), | |
956 | VMX_SEGMENT_FIELD(ES), | |
957 | VMX_SEGMENT_FIELD(FS), | |
958 | VMX_SEGMENT_FIELD(GS), | |
959 | VMX_SEGMENT_FIELD(SS), | |
960 | VMX_SEGMENT_FIELD(TR), | |
961 | VMX_SEGMENT_FIELD(LDTR), | |
962 | }; | |
963 | ||
26bb0981 AK |
964 | static u64 host_efer; |
965 | ||
6de4f3ad AK |
966 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
967 | ||
4d56c8a7 | 968 | /* |
8c06585d | 969 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
970 | * away by decrementing the array size. |
971 | */ | |
6aa8b732 | 972 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 973 | #ifdef CONFIG_X86_64 |
44ea2b17 | 974 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 975 | #endif |
8c06585d | 976 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 977 | }; |
6aa8b732 | 978 | |
5bb16016 | 979 | static inline bool is_exception_n(u32 intr_info, u8 vector) |
6aa8b732 AK |
980 | { |
981 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
982 | INTR_INFO_VALID_MASK)) == | |
5bb16016 JK |
983 | (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK); |
984 | } | |
985 | ||
6f05485d JK |
986 | static inline bool is_debug(u32 intr_info) |
987 | { | |
988 | return is_exception_n(intr_info, DB_VECTOR); | |
989 | } | |
990 | ||
991 | static inline bool is_breakpoint(u32 intr_info) | |
992 | { | |
993 | return is_exception_n(intr_info, BP_VECTOR); | |
994 | } | |
995 | ||
5bb16016 JK |
996 | static inline bool is_page_fault(u32 intr_info) |
997 | { | |
998 | return is_exception_n(intr_info, PF_VECTOR); | |
6aa8b732 AK |
999 | } |
1000 | ||
31299944 | 1001 | static inline bool is_no_device(u32 intr_info) |
2ab455cc | 1002 | { |
5bb16016 | 1003 | return is_exception_n(intr_info, NM_VECTOR); |
2ab455cc AL |
1004 | } |
1005 | ||
31299944 | 1006 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 | 1007 | { |
5bb16016 | 1008 | return is_exception_n(intr_info, UD_VECTOR); |
7aa81cc0 AL |
1009 | } |
1010 | ||
31299944 | 1011 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
1012 | { |
1013 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1014 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1015 | } | |
1016 | ||
31299944 | 1017 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
1018 | { |
1019 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1020 | INTR_INFO_VALID_MASK)) == | |
1021 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
1022 | } | |
1023 | ||
31299944 | 1024 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 1025 | { |
04547156 | 1026 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
1027 | } |
1028 | ||
31299944 | 1029 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 1030 | { |
04547156 | 1031 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
1032 | } |
1033 | ||
35754c98 | 1034 | static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) |
6e5d865c | 1035 | { |
35754c98 | 1036 | return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); |
6e5d865c YS |
1037 | } |
1038 | ||
31299944 | 1039 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 1040 | { |
04547156 SY |
1041 | return vmcs_config.cpu_based_exec_ctrl & |
1042 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
1043 | } |
1044 | ||
774ead3a | 1045 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 1046 | { |
04547156 SY |
1047 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1048 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1049 | } | |
1050 | ||
8d14695f YZ |
1051 | static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) |
1052 | { | |
1053 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1054 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
1055 | } | |
1056 | ||
83d4c286 YZ |
1057 | static inline bool cpu_has_vmx_apic_register_virt(void) |
1058 | { | |
1059 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1060 | SECONDARY_EXEC_APIC_REGISTER_VIRT; | |
1061 | } | |
1062 | ||
c7c9c56c YZ |
1063 | static inline bool cpu_has_vmx_virtual_intr_delivery(void) |
1064 | { | |
1065 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1066 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; | |
1067 | } | |
1068 | ||
64672c95 YJ |
1069 | /* |
1070 | * Comment's format: document - errata name - stepping - processor name. | |
1071 | * Refer from | |
1072 | * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp | |
1073 | */ | |
1074 | static u32 vmx_preemption_cpu_tfms[] = { | |
1075 | /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ | |
1076 | 0x000206E6, | |
1077 | /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ | |
1078 | /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ | |
1079 | /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1080 | 0x00020652, | |
1081 | /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1082 | 0x00020655, | |
1083 | /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ | |
1084 | /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ | |
1085 | /* | |
1086 | * 320767.pdf - AAP86 - B1 - | |
1087 | * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile | |
1088 | */ | |
1089 | 0x000106E5, | |
1090 | /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ | |
1091 | 0x000106A0, | |
1092 | /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ | |
1093 | 0x000106A1, | |
1094 | /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ | |
1095 | 0x000106A4, | |
1096 | /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ | |
1097 | /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ | |
1098 | /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ | |
1099 | 0x000106A5, | |
1100 | }; | |
1101 | ||
1102 | static inline bool cpu_has_broken_vmx_preemption_timer(void) | |
1103 | { | |
1104 | u32 eax = cpuid_eax(0x00000001), i; | |
1105 | ||
1106 | /* Clear the reserved bits */ | |
1107 | eax &= ~(0x3U << 14 | 0xfU << 28); | |
1108 | for (i = 0; i < sizeof(vmx_preemption_cpu_tfms)/sizeof(u32); i++) | |
1109 | if (eax == vmx_preemption_cpu_tfms[i]) | |
1110 | return true; | |
1111 | ||
1112 | return false; | |
1113 | } | |
1114 | ||
1115 | static inline bool cpu_has_vmx_preemption_timer(void) | |
1116 | { | |
1117 | if (cpu_has_broken_vmx_preemption_timer()) | |
1118 | return false; | |
1119 | ||
1120 | return vmcs_config.pin_based_exec_ctrl & | |
1121 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1122 | } | |
1123 | ||
01e439be YZ |
1124 | static inline bool cpu_has_vmx_posted_intr(void) |
1125 | { | |
d6a858d1 PB |
1126 | return IS_ENABLED(CONFIG_X86_LOCAL_APIC) && |
1127 | vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; | |
01e439be YZ |
1128 | } |
1129 | ||
1130 | static inline bool cpu_has_vmx_apicv(void) | |
1131 | { | |
1132 | return cpu_has_vmx_apic_register_virt() && | |
1133 | cpu_has_vmx_virtual_intr_delivery() && | |
1134 | cpu_has_vmx_posted_intr(); | |
1135 | } | |
1136 | ||
04547156 SY |
1137 | static inline bool cpu_has_vmx_flexpriority(void) |
1138 | { | |
1139 | return cpu_has_vmx_tpr_shadow() && | |
1140 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
1141 | } |
1142 | ||
e799794e MT |
1143 | static inline bool cpu_has_vmx_ept_execute_only(void) |
1144 | { | |
31299944 | 1145 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
1146 | } |
1147 | ||
e799794e MT |
1148 | static inline bool cpu_has_vmx_ept_2m_page(void) |
1149 | { | |
31299944 | 1150 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
1151 | } |
1152 | ||
878403b7 SY |
1153 | static inline bool cpu_has_vmx_ept_1g_page(void) |
1154 | { | |
31299944 | 1155 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
1156 | } |
1157 | ||
4bc9b982 SY |
1158 | static inline bool cpu_has_vmx_ept_4levels(void) |
1159 | { | |
1160 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
1161 | } | |
1162 | ||
83c3a331 XH |
1163 | static inline bool cpu_has_vmx_ept_ad_bits(void) |
1164 | { | |
1165 | return vmx_capability.ept & VMX_EPT_AD_BIT; | |
1166 | } | |
1167 | ||
31299944 | 1168 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 1169 | { |
31299944 | 1170 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
1171 | } |
1172 | ||
31299944 | 1173 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 1174 | { |
31299944 | 1175 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
1176 | } |
1177 | ||
518c8aee GJ |
1178 | static inline bool cpu_has_vmx_invvpid_single(void) |
1179 | { | |
1180 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
1181 | } | |
1182 | ||
b9d762fa GJ |
1183 | static inline bool cpu_has_vmx_invvpid_global(void) |
1184 | { | |
1185 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
1186 | } | |
1187 | ||
31299944 | 1188 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 1189 | { |
04547156 SY |
1190 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1191 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
1192 | } |
1193 | ||
31299944 | 1194 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
1195 | { |
1196 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1197 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
1198 | } | |
1199 | ||
31299944 | 1200 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
1201 | { |
1202 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1203 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
1204 | } | |
1205 | ||
35754c98 | 1206 | static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) |
f78e0e2e | 1207 | { |
35754c98 | 1208 | return flexpriority_enabled && lapic_in_kernel(vcpu); |
f78e0e2e SY |
1209 | } |
1210 | ||
31299944 | 1211 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 1212 | { |
04547156 SY |
1213 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1214 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
1215 | } |
1216 | ||
31299944 | 1217 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
1218 | { |
1219 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1220 | SECONDARY_EXEC_RDTSCP; | |
1221 | } | |
1222 | ||
ad756a16 MJ |
1223 | static inline bool cpu_has_vmx_invpcid(void) |
1224 | { | |
1225 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1226 | SECONDARY_EXEC_ENABLE_INVPCID; | |
1227 | } | |
1228 | ||
31299944 | 1229 | static inline bool cpu_has_virtual_nmis(void) |
f08864b4 SY |
1230 | { |
1231 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
1232 | } | |
1233 | ||
f5f48ee1 SY |
1234 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
1235 | { | |
1236 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1237 | SECONDARY_EXEC_WBINVD_EXITING; | |
1238 | } | |
1239 | ||
abc4fc58 AG |
1240 | static inline bool cpu_has_vmx_shadow_vmcs(void) |
1241 | { | |
1242 | u64 vmx_msr; | |
1243 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
1244 | /* check if the cpu supports writing r/o exit information fields */ | |
1245 | if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) | |
1246 | return false; | |
1247 | ||
1248 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1249 | SECONDARY_EXEC_SHADOW_VMCS; | |
1250 | } | |
1251 | ||
843e4330 KH |
1252 | static inline bool cpu_has_vmx_pml(void) |
1253 | { | |
1254 | return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; | |
1255 | } | |
1256 | ||
64903d61 HZ |
1257 | static inline bool cpu_has_vmx_tsc_scaling(void) |
1258 | { | |
1259 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1260 | SECONDARY_EXEC_TSC_SCALING; | |
1261 | } | |
1262 | ||
04547156 SY |
1263 | static inline bool report_flexpriority(void) |
1264 | { | |
1265 | return flexpriority_enabled; | |
1266 | } | |
1267 | ||
fe3ef05c NHE |
1268 | static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) |
1269 | { | |
1270 | return vmcs12->cpu_based_vm_exec_control & bit; | |
1271 | } | |
1272 | ||
1273 | static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) | |
1274 | { | |
1275 | return (vmcs12->cpu_based_vm_exec_control & | |
1276 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && | |
1277 | (vmcs12->secondary_vm_exec_control & bit); | |
1278 | } | |
1279 | ||
f5c4368f | 1280 | static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12) |
644d711a NHE |
1281 | { |
1282 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS; | |
1283 | } | |
1284 | ||
f4124500 JK |
1285 | static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) |
1286 | { | |
1287 | return vmcs12->pin_based_vm_exec_control & | |
1288 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1289 | } | |
1290 | ||
155a97a3 NHE |
1291 | static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) |
1292 | { | |
1293 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); | |
1294 | } | |
1295 | ||
81dc01f7 WL |
1296 | static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) |
1297 | { | |
1298 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) && | |
1299 | vmx_xsaves_supported(); | |
1300 | } | |
1301 | ||
f2b93280 WV |
1302 | static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) |
1303 | { | |
1304 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); | |
1305 | } | |
1306 | ||
5c614b35 WL |
1307 | static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) |
1308 | { | |
1309 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); | |
1310 | } | |
1311 | ||
82f0dd4b WV |
1312 | static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) |
1313 | { | |
1314 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); | |
1315 | } | |
1316 | ||
608406e2 WV |
1317 | static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) |
1318 | { | |
1319 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
1320 | } | |
1321 | ||
705699a1 WV |
1322 | static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) |
1323 | { | |
1324 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; | |
1325 | } | |
1326 | ||
644d711a NHE |
1327 | static inline bool is_exception(u32 intr_info) |
1328 | { | |
1329 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1330 | == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK); | |
1331 | } | |
1332 | ||
533558bc JK |
1333 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
1334 | u32 exit_intr_info, | |
1335 | unsigned long exit_qualification); | |
7c177938 NHE |
1336 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, |
1337 | struct vmcs12 *vmcs12, | |
1338 | u32 reason, unsigned long qualification); | |
1339 | ||
8b9cf98c | 1340 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
1341 | { |
1342 | int i; | |
1343 | ||
a2fa3e9f | 1344 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 1345 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
1346 | return i; |
1347 | return -1; | |
1348 | } | |
1349 | ||
2384d2b3 SY |
1350 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
1351 | { | |
1352 | struct { | |
1353 | u64 vpid : 16; | |
1354 | u64 rsvd : 48; | |
1355 | u64 gva; | |
1356 | } operand = { vpid, 0, gva }; | |
1357 | ||
4ecac3fd | 1358 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
1359 | /* CF==1 or ZF==1 --> rc = -1 */ |
1360 | "; ja 1f ; ud2 ; 1:" | |
1361 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
1362 | } | |
1363 | ||
1439442c SY |
1364 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
1365 | { | |
1366 | struct { | |
1367 | u64 eptp, gpa; | |
1368 | } operand = {eptp, gpa}; | |
1369 | ||
4ecac3fd | 1370 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
1371 | /* CF==1 or ZF==1 --> rc = -1 */ |
1372 | "; ja 1f ; ud2 ; 1:\n" | |
1373 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
1374 | } | |
1375 | ||
26bb0981 | 1376 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
1377 | { |
1378 | int i; | |
1379 | ||
8b9cf98c | 1380 | i = __find_msr_index(vmx, msr); |
a75beee6 | 1381 | if (i >= 0) |
a2fa3e9f | 1382 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 1383 | return NULL; |
7725f0ba AK |
1384 | } |
1385 | ||
6aa8b732 AK |
1386 | static void vmcs_clear(struct vmcs *vmcs) |
1387 | { | |
1388 | u64 phys_addr = __pa(vmcs); | |
1389 | u8 error; | |
1390 | ||
4ecac3fd | 1391 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 1392 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
1393 | : "cc", "memory"); |
1394 | if (error) | |
1395 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
1396 | vmcs, phys_addr); | |
1397 | } | |
1398 | ||
d462b819 NHE |
1399 | static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
1400 | { | |
1401 | vmcs_clear(loaded_vmcs->vmcs); | |
1402 | loaded_vmcs->cpu = -1; | |
1403 | loaded_vmcs->launched = 0; | |
1404 | } | |
1405 | ||
7725b894 DX |
1406 | static void vmcs_load(struct vmcs *vmcs) |
1407 | { | |
1408 | u64 phys_addr = __pa(vmcs); | |
1409 | u8 error; | |
1410 | ||
1411 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
16d8f72f | 1412 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
1413 | : "cc", "memory"); |
1414 | if (error) | |
2844d849 | 1415 | printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n", |
7725b894 DX |
1416 | vmcs, phys_addr); |
1417 | } | |
1418 | ||
2965faa5 | 1419 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
1420 | /* |
1421 | * This bitmap is used to indicate whether the vmclear | |
1422 | * operation is enabled on all cpus. All disabled by | |
1423 | * default. | |
1424 | */ | |
1425 | static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; | |
1426 | ||
1427 | static inline void crash_enable_local_vmclear(int cpu) | |
1428 | { | |
1429 | cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1430 | } | |
1431 | ||
1432 | static inline void crash_disable_local_vmclear(int cpu) | |
1433 | { | |
1434 | cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1435 | } | |
1436 | ||
1437 | static inline int crash_local_vmclear_enabled(int cpu) | |
1438 | { | |
1439 | return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1440 | } | |
1441 | ||
1442 | static void crash_vmclear_local_loaded_vmcss(void) | |
1443 | { | |
1444 | int cpu = raw_smp_processor_id(); | |
1445 | struct loaded_vmcs *v; | |
1446 | ||
1447 | if (!crash_local_vmclear_enabled(cpu)) | |
1448 | return; | |
1449 | ||
1450 | list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), | |
1451 | loaded_vmcss_on_cpu_link) | |
1452 | vmcs_clear(v->vmcs); | |
1453 | } | |
1454 | #else | |
1455 | static inline void crash_enable_local_vmclear(int cpu) { } | |
1456 | static inline void crash_disable_local_vmclear(int cpu) { } | |
2965faa5 | 1457 | #endif /* CONFIG_KEXEC_CORE */ |
8f536b76 | 1458 | |
d462b819 | 1459 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 1460 | { |
d462b819 | 1461 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 1462 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 1463 | |
d462b819 NHE |
1464 | if (loaded_vmcs->cpu != cpu) |
1465 | return; /* vcpu migration can race with cpu offline */ | |
1466 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 1467 | per_cpu(current_vmcs, cpu) = NULL; |
8f536b76 | 1468 | crash_disable_local_vmclear(cpu); |
d462b819 | 1469 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
5a560f8b XG |
1470 | |
1471 | /* | |
1472 | * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link | |
1473 | * is before setting loaded_vmcs->vcpu to -1 which is done in | |
1474 | * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist | |
1475 | * then adds the vmcs into percpu list before it is deleted. | |
1476 | */ | |
1477 | smp_wmb(); | |
1478 | ||
d462b819 | 1479 | loaded_vmcs_init(loaded_vmcs); |
8f536b76 | 1480 | crash_enable_local_vmclear(cpu); |
6aa8b732 AK |
1481 | } |
1482 | ||
d462b819 | 1483 | static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 1484 | { |
e6c7d321 XG |
1485 | int cpu = loaded_vmcs->cpu; |
1486 | ||
1487 | if (cpu != -1) | |
1488 | smp_call_function_single(cpu, | |
1489 | __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
1490 | } |
1491 | ||
dd5f5341 | 1492 | static inline void vpid_sync_vcpu_single(int vpid) |
2384d2b3 | 1493 | { |
dd5f5341 | 1494 | if (vpid == 0) |
2384d2b3 SY |
1495 | return; |
1496 | ||
518c8aee | 1497 | if (cpu_has_vmx_invvpid_single()) |
dd5f5341 | 1498 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0); |
2384d2b3 SY |
1499 | } |
1500 | ||
b9d762fa GJ |
1501 | static inline void vpid_sync_vcpu_global(void) |
1502 | { | |
1503 | if (cpu_has_vmx_invvpid_global()) | |
1504 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
1505 | } | |
1506 | ||
dd5f5341 | 1507 | static inline void vpid_sync_context(int vpid) |
b9d762fa GJ |
1508 | { |
1509 | if (cpu_has_vmx_invvpid_single()) | |
dd5f5341 | 1510 | vpid_sync_vcpu_single(vpid); |
b9d762fa GJ |
1511 | else |
1512 | vpid_sync_vcpu_global(); | |
1513 | } | |
1514 | ||
1439442c SY |
1515 | static inline void ept_sync_global(void) |
1516 | { | |
1517 | if (cpu_has_vmx_invept_global()) | |
1518 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
1519 | } | |
1520 | ||
1521 | static inline void ept_sync_context(u64 eptp) | |
1522 | { | |
089d034e | 1523 | if (enable_ept) { |
1439442c SY |
1524 | if (cpu_has_vmx_invept_context()) |
1525 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
1526 | else | |
1527 | ept_sync_global(); | |
1528 | } | |
1529 | } | |
1530 | ||
8a86aea9 PB |
1531 | static __always_inline void vmcs_check16(unsigned long field) |
1532 | { | |
1533 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1534 | "16-bit accessor invalid for 64-bit field"); | |
1535 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1536 | "16-bit accessor invalid for 64-bit high field"); | |
1537 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1538 | "16-bit accessor invalid for 32-bit high field"); | |
1539 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1540 | "16-bit accessor invalid for natural width field"); | |
1541 | } | |
1542 | ||
1543 | static __always_inline void vmcs_check32(unsigned long field) | |
1544 | { | |
1545 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1546 | "32-bit accessor invalid for 16-bit field"); | |
1547 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1548 | "32-bit accessor invalid for natural width field"); | |
1549 | } | |
1550 | ||
1551 | static __always_inline void vmcs_check64(unsigned long field) | |
1552 | { | |
1553 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1554 | "64-bit accessor invalid for 16-bit field"); | |
1555 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1556 | "64-bit accessor invalid for 64-bit high field"); | |
1557 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1558 | "64-bit accessor invalid for 32-bit field"); | |
1559 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1560 | "64-bit accessor invalid for natural width field"); | |
1561 | } | |
1562 | ||
1563 | static __always_inline void vmcs_checkl(unsigned long field) | |
1564 | { | |
1565 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1566 | "Natural width accessor invalid for 16-bit field"); | |
1567 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1568 | "Natural width accessor invalid for 64-bit field"); | |
1569 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1570 | "Natural width accessor invalid for 64-bit high field"); | |
1571 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1572 | "Natural width accessor invalid for 32-bit field"); | |
1573 | } | |
1574 | ||
1575 | static __always_inline unsigned long __vmcs_readl(unsigned long field) | |
6aa8b732 | 1576 | { |
5e520e62 | 1577 | unsigned long value; |
6aa8b732 | 1578 | |
5e520e62 AK |
1579 | asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
1580 | : "=a"(value) : "d"(field) : "cc"); | |
6aa8b732 AK |
1581 | return value; |
1582 | } | |
1583 | ||
96304217 | 1584 | static __always_inline u16 vmcs_read16(unsigned long field) |
6aa8b732 | 1585 | { |
8a86aea9 PB |
1586 | vmcs_check16(field); |
1587 | return __vmcs_readl(field); | |
6aa8b732 AK |
1588 | } |
1589 | ||
96304217 | 1590 | static __always_inline u32 vmcs_read32(unsigned long field) |
6aa8b732 | 1591 | { |
8a86aea9 PB |
1592 | vmcs_check32(field); |
1593 | return __vmcs_readl(field); | |
6aa8b732 AK |
1594 | } |
1595 | ||
96304217 | 1596 | static __always_inline u64 vmcs_read64(unsigned long field) |
6aa8b732 | 1597 | { |
8a86aea9 | 1598 | vmcs_check64(field); |
05b3e0c2 | 1599 | #ifdef CONFIG_X86_64 |
8a86aea9 | 1600 | return __vmcs_readl(field); |
6aa8b732 | 1601 | #else |
8a86aea9 | 1602 | return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32); |
6aa8b732 AK |
1603 | #endif |
1604 | } | |
1605 | ||
8a86aea9 PB |
1606 | static __always_inline unsigned long vmcs_readl(unsigned long field) |
1607 | { | |
1608 | vmcs_checkl(field); | |
1609 | return __vmcs_readl(field); | |
1610 | } | |
1611 | ||
e52de1b8 AK |
1612 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
1613 | { | |
1614 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
1615 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1616 | dump_stack(); | |
1617 | } | |
1618 | ||
8a86aea9 | 1619 | static __always_inline void __vmcs_writel(unsigned long field, unsigned long value) |
6aa8b732 AK |
1620 | { |
1621 | u8 error; | |
1622 | ||
4ecac3fd | 1623 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 1624 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
1625 | if (unlikely(error)) |
1626 | vmwrite_error(field, value); | |
6aa8b732 AK |
1627 | } |
1628 | ||
8a86aea9 | 1629 | static __always_inline void vmcs_write16(unsigned long field, u16 value) |
6aa8b732 | 1630 | { |
8a86aea9 PB |
1631 | vmcs_check16(field); |
1632 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1633 | } |
1634 | ||
8a86aea9 | 1635 | static __always_inline void vmcs_write32(unsigned long field, u32 value) |
6aa8b732 | 1636 | { |
8a86aea9 PB |
1637 | vmcs_check32(field); |
1638 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1639 | } |
1640 | ||
8a86aea9 | 1641 | static __always_inline void vmcs_write64(unsigned long field, u64 value) |
6aa8b732 | 1642 | { |
8a86aea9 PB |
1643 | vmcs_check64(field); |
1644 | __vmcs_writel(field, value); | |
7682f2d0 | 1645 | #ifndef CONFIG_X86_64 |
6aa8b732 | 1646 | asm volatile (""); |
8a86aea9 | 1647 | __vmcs_writel(field+1, value >> 32); |
6aa8b732 AK |
1648 | #endif |
1649 | } | |
1650 | ||
8a86aea9 | 1651 | static __always_inline void vmcs_writel(unsigned long field, unsigned long value) |
2ab455cc | 1652 | { |
8a86aea9 PB |
1653 | vmcs_checkl(field); |
1654 | __vmcs_writel(field, value); | |
2ab455cc AL |
1655 | } |
1656 | ||
8a86aea9 | 1657 | static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask) |
2ab455cc | 1658 | { |
8a86aea9 PB |
1659 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1660 | "vmcs_clear_bits does not support 64-bit fields"); | |
1661 | __vmcs_writel(field, __vmcs_readl(field) & ~mask); | |
2ab455cc AL |
1662 | } |
1663 | ||
8a86aea9 | 1664 | static __always_inline void vmcs_set_bits(unsigned long field, u32 mask) |
2ab455cc | 1665 | { |
8a86aea9 PB |
1666 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1667 | "vmcs_set_bits does not support 64-bit fields"); | |
1668 | __vmcs_writel(field, __vmcs_readl(field) | mask); | |
2ab455cc AL |
1669 | } |
1670 | ||
2961e876 GN |
1671 | static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val) |
1672 | { | |
1673 | vmcs_write32(VM_ENTRY_CONTROLS, val); | |
1674 | vmx->vm_entry_controls_shadow = val; | |
1675 | } | |
1676 | ||
1677 | static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1678 | { | |
1679 | if (vmx->vm_entry_controls_shadow != val) | |
1680 | vm_entry_controls_init(vmx, val); | |
1681 | } | |
1682 | ||
1683 | static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx) | |
1684 | { | |
1685 | return vmx->vm_entry_controls_shadow; | |
1686 | } | |
1687 | ||
1688 | ||
1689 | static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1690 | { | |
1691 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val); | |
1692 | } | |
1693 | ||
1694 | static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1695 | { | |
1696 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val); | |
1697 | } | |
1698 | ||
1699 | static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val) | |
1700 | { | |
1701 | vmcs_write32(VM_EXIT_CONTROLS, val); | |
1702 | vmx->vm_exit_controls_shadow = val; | |
1703 | } | |
1704 | ||
1705 | static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1706 | { | |
1707 | if (vmx->vm_exit_controls_shadow != val) | |
1708 | vm_exit_controls_init(vmx, val); | |
1709 | } | |
1710 | ||
1711 | static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx) | |
1712 | { | |
1713 | return vmx->vm_exit_controls_shadow; | |
1714 | } | |
1715 | ||
1716 | ||
1717 | static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1718 | { | |
1719 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val); | |
1720 | } | |
1721 | ||
1722 | static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1723 | { | |
1724 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val); | |
1725 | } | |
1726 | ||
2fb92db1 AK |
1727 | static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
1728 | { | |
1729 | vmx->segment_cache.bitmask = 0; | |
1730 | } | |
1731 | ||
1732 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, | |
1733 | unsigned field) | |
1734 | { | |
1735 | bool ret; | |
1736 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
1737 | ||
1738 | if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { | |
1739 | vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); | |
1740 | vmx->segment_cache.bitmask = 0; | |
1741 | } | |
1742 | ret = vmx->segment_cache.bitmask & mask; | |
1743 | vmx->segment_cache.bitmask |= mask; | |
1744 | return ret; | |
1745 | } | |
1746 | ||
1747 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
1748 | { | |
1749 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
1750 | ||
1751 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
1752 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
1753 | return *p; | |
1754 | } | |
1755 | ||
1756 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
1757 | { | |
1758 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
1759 | ||
1760 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
1761 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
1762 | return *p; | |
1763 | } | |
1764 | ||
1765 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
1766 | { | |
1767 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
1768 | ||
1769 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
1770 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
1771 | return *p; | |
1772 | } | |
1773 | ||
1774 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
1775 | { | |
1776 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
1777 | ||
1778 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
1779 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
1780 | return *p; | |
1781 | } | |
1782 | ||
abd3f2d6 AK |
1783 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
1784 | { | |
1785 | u32 eb; | |
1786 | ||
fd7373cc | 1787 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
54a20552 | 1788 | (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR); |
fd7373cc JK |
1789 | if ((vcpu->guest_debug & |
1790 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
1791 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
1792 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 1793 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 1794 | eb = ~0; |
089d034e | 1795 | if (enable_ept) |
1439442c | 1796 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
02daab21 AK |
1797 | if (vcpu->fpu_active) |
1798 | eb &= ~(1u << NM_VECTOR); | |
36cf24e0 NHE |
1799 | |
1800 | /* When we are running a nested L2 guest and L1 specified for it a | |
1801 | * certain exception bitmap, we must trap the same exceptions and pass | |
1802 | * them to L1. When running L2, we will only handle the exceptions | |
1803 | * specified above if L1 did not want them. | |
1804 | */ | |
1805 | if (is_guest_mode(vcpu)) | |
1806 | eb |= get_vmcs12(vcpu)->exception_bitmap; | |
1807 | ||
abd3f2d6 AK |
1808 | vmcs_write32(EXCEPTION_BITMAP, eb); |
1809 | } | |
1810 | ||
2961e876 GN |
1811 | static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1812 | unsigned long entry, unsigned long exit) | |
8bf00a52 | 1813 | { |
2961e876 GN |
1814 | vm_entry_controls_clearbit(vmx, entry); |
1815 | vm_exit_controls_clearbit(vmx, exit); | |
8bf00a52 GN |
1816 | } |
1817 | ||
61d2ef2c AK |
1818 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
1819 | { | |
1820 | unsigned i; | |
1821 | struct msr_autoload *m = &vmx->msr_autoload; | |
1822 | ||
8bf00a52 GN |
1823 | switch (msr) { |
1824 | case MSR_EFER: | |
1825 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1826 | clear_atomic_switch_msr_special(vmx, |
1827 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1828 | VM_EXIT_LOAD_IA32_EFER); |
1829 | return; | |
1830 | } | |
1831 | break; | |
1832 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1833 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1834 | clear_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1835 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1836 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
1837 | return; | |
1838 | } | |
1839 | break; | |
110312c8 AK |
1840 | } |
1841 | ||
61d2ef2c AK |
1842 | for (i = 0; i < m->nr; ++i) |
1843 | if (m->guest[i].index == msr) | |
1844 | break; | |
1845 | ||
1846 | if (i == m->nr) | |
1847 | return; | |
1848 | --m->nr; | |
1849 | m->guest[i] = m->guest[m->nr]; | |
1850 | m->host[i] = m->host[m->nr]; | |
1851 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1852 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1853 | } | |
1854 | ||
2961e876 GN |
1855 | static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1856 | unsigned long entry, unsigned long exit, | |
1857 | unsigned long guest_val_vmcs, unsigned long host_val_vmcs, | |
1858 | u64 guest_val, u64 host_val) | |
8bf00a52 GN |
1859 | { |
1860 | vmcs_write64(guest_val_vmcs, guest_val); | |
1861 | vmcs_write64(host_val_vmcs, host_val); | |
2961e876 GN |
1862 | vm_entry_controls_setbit(vmx, entry); |
1863 | vm_exit_controls_setbit(vmx, exit); | |
8bf00a52 GN |
1864 | } |
1865 | ||
61d2ef2c AK |
1866 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
1867 | u64 guest_val, u64 host_val) | |
1868 | { | |
1869 | unsigned i; | |
1870 | struct msr_autoload *m = &vmx->msr_autoload; | |
1871 | ||
8bf00a52 GN |
1872 | switch (msr) { |
1873 | case MSR_EFER: | |
1874 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1875 | add_atomic_switch_msr_special(vmx, |
1876 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1877 | VM_EXIT_LOAD_IA32_EFER, |
1878 | GUEST_IA32_EFER, | |
1879 | HOST_IA32_EFER, | |
1880 | guest_val, host_val); | |
1881 | return; | |
1882 | } | |
1883 | break; | |
1884 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1885 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1886 | add_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1887 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1888 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, | |
1889 | GUEST_IA32_PERF_GLOBAL_CTRL, | |
1890 | HOST_IA32_PERF_GLOBAL_CTRL, | |
1891 | guest_val, host_val); | |
1892 | return; | |
1893 | } | |
1894 | break; | |
7099e2e1 RK |
1895 | case MSR_IA32_PEBS_ENABLE: |
1896 | /* PEBS needs a quiescent period after being disabled (to write | |
1897 | * a record). Disabling PEBS through VMX MSR swapping doesn't | |
1898 | * provide that period, so a CPU could write host's record into | |
1899 | * guest's memory. | |
1900 | */ | |
1901 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
110312c8 AK |
1902 | } |
1903 | ||
61d2ef2c AK |
1904 | for (i = 0; i < m->nr; ++i) |
1905 | if (m->guest[i].index == msr) | |
1906 | break; | |
1907 | ||
e7fc6f93 | 1908 | if (i == NR_AUTOLOAD_MSRS) { |
60266204 | 1909 | printk_once(KERN_WARNING "Not enough msr switch entries. " |
e7fc6f93 GN |
1910 | "Can't add msr %x\n", msr); |
1911 | return; | |
1912 | } else if (i == m->nr) { | |
61d2ef2c AK |
1913 | ++m->nr; |
1914 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1915 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1916 | } | |
1917 | ||
1918 | m->guest[i].index = msr; | |
1919 | m->guest[i].value = guest_val; | |
1920 | m->host[i].index = msr; | |
1921 | m->host[i].value = host_val; | |
1922 | } | |
1923 | ||
33ed6329 AK |
1924 | static void reload_tss(void) |
1925 | { | |
33ed6329 AK |
1926 | /* |
1927 | * VT restores TR but not its size. Useless. | |
1928 | */ | |
89cbc767 | 1929 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); |
a5f61300 | 1930 | struct desc_struct *descs; |
33ed6329 | 1931 | |
d359192f | 1932 | descs = (void *)gdt->address; |
33ed6329 AK |
1933 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ |
1934 | load_TR_desc(); | |
33ed6329 AK |
1935 | } |
1936 | ||
92c0d900 | 1937 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 1938 | { |
844a5fe2 PB |
1939 | u64 guest_efer = vmx->vcpu.arch.efer; |
1940 | u64 ignore_bits = 0; | |
1941 | ||
1942 | if (!enable_ept) { | |
1943 | /* | |
1944 | * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing | |
1945 | * host CPUID is more efficient than testing guest CPUID | |
1946 | * or CR4. Host SMEP is anyway a requirement for guest SMEP. | |
1947 | */ | |
1948 | if (boot_cpu_has(X86_FEATURE_SMEP)) | |
1949 | guest_efer |= EFER_NX; | |
1950 | else if (!(guest_efer & EFER_NX)) | |
1951 | ignore_bits |= EFER_NX; | |
1952 | } | |
3a34a881 | 1953 | |
51c6cf66 | 1954 | /* |
844a5fe2 | 1955 | * LMA and LME handled by hardware; SCE meaningless outside long mode. |
51c6cf66 | 1956 | */ |
844a5fe2 | 1957 | ignore_bits |= EFER_SCE; |
51c6cf66 AK |
1958 | #ifdef CONFIG_X86_64 |
1959 | ignore_bits |= EFER_LMA | EFER_LME; | |
1960 | /* SCE is meaningful only in long mode on Intel */ | |
1961 | if (guest_efer & EFER_LMA) | |
1962 | ignore_bits &= ~(u64)EFER_SCE; | |
1963 | #endif | |
84ad33ef AK |
1964 | |
1965 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
f6577a5f AL |
1966 | |
1967 | /* | |
1968 | * On EPT, we can't emulate NX, so we must switch EFER atomically. | |
1969 | * On CPUs that support "load IA32_EFER", always switch EFER | |
1970 | * atomically, since it's faster than switching it manually. | |
1971 | */ | |
1972 | if (cpu_has_load_ia32_efer || | |
1973 | (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { | |
84ad33ef AK |
1974 | if (!(guest_efer & EFER_LMA)) |
1975 | guest_efer &= ~EFER_LME; | |
54b98bff AL |
1976 | if (guest_efer != host_efer) |
1977 | add_atomic_switch_msr(vmx, MSR_EFER, | |
1978 | guest_efer, host_efer); | |
84ad33ef | 1979 | return false; |
844a5fe2 PB |
1980 | } else { |
1981 | guest_efer &= ~ignore_bits; | |
1982 | guest_efer |= host_efer & ignore_bits; | |
1983 | ||
1984 | vmx->guest_msrs[efer_offset].data = guest_efer; | |
1985 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; | |
84ad33ef | 1986 | |
844a5fe2 PB |
1987 | return true; |
1988 | } | |
51c6cf66 AK |
1989 | } |
1990 | ||
2d49ec72 GN |
1991 | static unsigned long segment_base(u16 selector) |
1992 | { | |
89cbc767 | 1993 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); |
2d49ec72 GN |
1994 | struct desc_struct *d; |
1995 | unsigned long table_base; | |
1996 | unsigned long v; | |
1997 | ||
1998 | if (!(selector & ~3)) | |
1999 | return 0; | |
2000 | ||
d359192f | 2001 | table_base = gdt->address; |
2d49ec72 GN |
2002 | |
2003 | if (selector & 4) { /* from ldt */ | |
2004 | u16 ldt_selector = kvm_read_ldt(); | |
2005 | ||
2006 | if (!(ldt_selector & ~3)) | |
2007 | return 0; | |
2008 | ||
2009 | table_base = segment_base(ldt_selector); | |
2010 | } | |
2011 | d = (struct desc_struct *)(table_base + (selector & ~7)); | |
2012 | v = get_desc_base(d); | |
2013 | #ifdef CONFIG_X86_64 | |
2014 | if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) | |
2015 | v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; | |
2016 | #endif | |
2017 | return v; | |
2018 | } | |
2019 | ||
2020 | static inline unsigned long kvm_read_tr_base(void) | |
2021 | { | |
2022 | u16 tr; | |
2023 | asm("str %0" : "=g"(tr)); | |
2024 | return segment_base(tr); | |
2025 | } | |
2026 | ||
04d2cc77 | 2027 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 2028 | { |
04d2cc77 | 2029 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 2030 | int i; |
04d2cc77 | 2031 | |
a2fa3e9f | 2032 | if (vmx->host_state.loaded) |
33ed6329 AK |
2033 | return; |
2034 | ||
a2fa3e9f | 2035 | vmx->host_state.loaded = 1; |
33ed6329 AK |
2036 | /* |
2037 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
2038 | * allow segment selectors with cpl > 0 or ti == 1. | |
2039 | */ | |
d6e88aec | 2040 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 2041 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 2042 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 2043 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 2044 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
2045 | vmx->host_state.fs_reload_needed = 0; |
2046 | } else { | |
33ed6329 | 2047 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 2048 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 2049 | } |
9581d442 | 2050 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
2051 | if (!(vmx->host_state.gs_sel & 7)) |
2052 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
2053 | else { |
2054 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 2055 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
2056 | } |
2057 | ||
b2da15ac AK |
2058 | #ifdef CONFIG_X86_64 |
2059 | savesegment(ds, vmx->host_state.ds_sel); | |
2060 | savesegment(es, vmx->host_state.es_sel); | |
2061 | #endif | |
2062 | ||
33ed6329 AK |
2063 | #ifdef CONFIG_X86_64 |
2064 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
2065 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
2066 | #else | |
a2fa3e9f GH |
2067 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
2068 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 2069 | #endif |
707c0874 AK |
2070 | |
2071 | #ifdef CONFIG_X86_64 | |
c8770e7b AK |
2072 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
2073 | if (is_long_mode(&vmx->vcpu)) | |
44ea2b17 | 2074 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
707c0874 | 2075 | #endif |
da8999d3 LJ |
2076 | if (boot_cpu_has(X86_FEATURE_MPX)) |
2077 | rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
26bb0981 AK |
2078 | for (i = 0; i < vmx->save_nmsrs; ++i) |
2079 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
2080 | vmx->guest_msrs[i].data, |
2081 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
2082 | } |
2083 | ||
a9b21b62 | 2084 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 2085 | { |
a2fa3e9f | 2086 | if (!vmx->host_state.loaded) |
33ed6329 AK |
2087 | return; |
2088 | ||
e1beb1d3 | 2089 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 2090 | vmx->host_state.loaded = 0; |
c8770e7b AK |
2091 | #ifdef CONFIG_X86_64 |
2092 | if (is_long_mode(&vmx->vcpu)) | |
2093 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
2094 | #endif | |
152d3f2f | 2095 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 2096 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 2097 | #ifdef CONFIG_X86_64 |
9581d442 | 2098 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
2099 | #else |
2100 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 2101 | #endif |
33ed6329 | 2102 | } |
0a77fe4c AK |
2103 | if (vmx->host_state.fs_reload_needed) |
2104 | loadsegment(fs, vmx->host_state.fs_sel); | |
b2da15ac AK |
2105 | #ifdef CONFIG_X86_64 |
2106 | if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) { | |
2107 | loadsegment(ds, vmx->host_state.ds_sel); | |
2108 | loadsegment(es, vmx->host_state.es_sel); | |
2109 | } | |
b2da15ac | 2110 | #endif |
152d3f2f | 2111 | reload_tss(); |
44ea2b17 | 2112 | #ifdef CONFIG_X86_64 |
c8770e7b | 2113 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 2114 | #endif |
da8999d3 LJ |
2115 | if (vmx->host_state.msr_host_bndcfgs) |
2116 | wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
b1a74bf8 SS |
2117 | /* |
2118 | * If the FPU is not active (through the host task or | |
2119 | * the guest vcpu), then restore the cr0.TS bit. | |
2120 | */ | |
3c6dffa9 | 2121 | if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded) |
b1a74bf8 | 2122 | stts(); |
89cbc767 | 2123 | load_gdt(this_cpu_ptr(&host_gdt)); |
33ed6329 AK |
2124 | } |
2125 | ||
a9b21b62 AK |
2126 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
2127 | { | |
2128 | preempt_disable(); | |
2129 | __vmx_load_host_state(vmx); | |
2130 | preempt_enable(); | |
2131 | } | |
2132 | ||
28b835d6 FW |
2133 | static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) |
2134 | { | |
2135 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2136 | struct pi_desc old, new; | |
2137 | unsigned int dest; | |
2138 | ||
2139 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
2140 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
2141 | return; | |
2142 | ||
2143 | do { | |
2144 | old.control = new.control = pi_desc->control; | |
2145 | ||
2146 | /* | |
2147 | * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there | |
2148 | * are two possible cases: | |
2149 | * 1. After running 'pre_block', context switch | |
2150 | * happened. For this case, 'sn' was set in | |
2151 | * vmx_vcpu_put(), so we need to clear it here. | |
2152 | * 2. After running 'pre_block', we were blocked, | |
2153 | * and woken up by some other guy. For this case, | |
2154 | * we don't need to do anything, 'pi_post_block' | |
2155 | * will do everything for us. However, we cannot | |
2156 | * check whether it is case #1 or case #2 here | |
2157 | * (maybe, not needed), so we also clear sn here, | |
2158 | * I think it is not a big deal. | |
2159 | */ | |
2160 | if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) { | |
2161 | if (vcpu->cpu != cpu) { | |
2162 | dest = cpu_physical_id(cpu); | |
2163 | ||
2164 | if (x2apic_enabled()) | |
2165 | new.ndst = dest; | |
2166 | else | |
2167 | new.ndst = (dest << 8) & 0xFF00; | |
2168 | } | |
2169 | ||
2170 | /* set 'NV' to 'notification vector' */ | |
2171 | new.nv = POSTED_INTR_VECTOR; | |
2172 | } | |
2173 | ||
2174 | /* Allow posting non-urgent interrupts */ | |
2175 | new.sn = 0; | |
2176 | } while (cmpxchg(&pi_desc->control, old.control, | |
2177 | new.control) != old.control); | |
2178 | } | |
1be0e61c | 2179 | |
6aa8b732 AK |
2180 | /* |
2181 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
2182 | * vcpu mutex is already taken. | |
2183 | */ | |
15ad7146 | 2184 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 2185 | { |
a2fa3e9f | 2186 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4610c9cc | 2187 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); |
6aa8b732 | 2188 | |
4610c9cc DX |
2189 | if (!vmm_exclusive) |
2190 | kvm_cpu_vmxon(phys_addr); | |
d462b819 NHE |
2191 | else if (vmx->loaded_vmcs->cpu != cpu) |
2192 | loaded_vmcs_clear(vmx->loaded_vmcs); | |
6aa8b732 | 2193 | |
d462b819 NHE |
2194 | if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { |
2195 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; | |
2196 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
6aa8b732 AK |
2197 | } |
2198 | ||
d462b819 | 2199 | if (vmx->loaded_vmcs->cpu != cpu) { |
89cbc767 | 2200 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); |
6aa8b732 AK |
2201 | unsigned long sysenter_esp; |
2202 | ||
a8eeb04a | 2203 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
92fe13be | 2204 | local_irq_disable(); |
8f536b76 | 2205 | crash_disable_local_vmclear(cpu); |
5a560f8b XG |
2206 | |
2207 | /* | |
2208 | * Read loaded_vmcs->cpu should be before fetching | |
2209 | * loaded_vmcs->loaded_vmcss_on_cpu_link. | |
2210 | * See the comments in __loaded_vmcs_clear(). | |
2211 | */ | |
2212 | smp_rmb(); | |
2213 | ||
d462b819 NHE |
2214 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
2215 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
8f536b76 | 2216 | crash_enable_local_vmclear(cpu); |
92fe13be DX |
2217 | local_irq_enable(); |
2218 | ||
6aa8b732 AK |
2219 | /* |
2220 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
2221 | * processors. | |
2222 | */ | |
d6e88aec | 2223 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
d359192f | 2224 | vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */ |
6aa8b732 AK |
2225 | |
2226 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
2227 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
ff2c3a18 | 2228 | |
d462b819 | 2229 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 2230 | } |
28b835d6 | 2231 | |
2680d6da OH |
2232 | /* Setup TSC multiplier */ |
2233 | if (kvm_has_tsc_control && | |
2234 | vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) { | |
2235 | vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio; | |
2236 | vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); | |
2237 | } | |
2238 | ||
28b835d6 | 2239 | vmx_vcpu_pi_load(vcpu, cpu); |
1be0e61c | 2240 | vmx->host_pkru = read_pkru(); |
28b835d6 FW |
2241 | } |
2242 | ||
2243 | static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) | |
2244 | { | |
2245 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2246 | ||
2247 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
2248 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
2249 | return; | |
2250 | ||
2251 | /* Set SN when the vCPU is preempted */ | |
2252 | if (vcpu->preempted) | |
2253 | pi_set_sn(pi_desc); | |
6aa8b732 AK |
2254 | } |
2255 | ||
2256 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
2257 | { | |
28b835d6 FW |
2258 | vmx_vcpu_pi_put(vcpu); |
2259 | ||
a9b21b62 | 2260 | __vmx_load_host_state(to_vmx(vcpu)); |
4610c9cc | 2261 | if (!vmm_exclusive) { |
d462b819 NHE |
2262 | __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs); |
2263 | vcpu->cpu = -1; | |
4610c9cc DX |
2264 | kvm_cpu_vmxoff(); |
2265 | } | |
6aa8b732 AK |
2266 | } |
2267 | ||
5fd86fcf AK |
2268 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
2269 | { | |
81231c69 AK |
2270 | ulong cr0; |
2271 | ||
5fd86fcf AK |
2272 | if (vcpu->fpu_active) |
2273 | return; | |
2274 | vcpu->fpu_active = 1; | |
81231c69 AK |
2275 | cr0 = vmcs_readl(GUEST_CR0); |
2276 | cr0 &= ~(X86_CR0_TS | X86_CR0_MP); | |
2277 | cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP); | |
2278 | vmcs_writel(GUEST_CR0, cr0); | |
5fd86fcf | 2279 | update_exception_bitmap(vcpu); |
edcafe3c | 2280 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
36cf24e0 NHE |
2281 | if (is_guest_mode(vcpu)) |
2282 | vcpu->arch.cr0_guest_owned_bits &= | |
2283 | ~get_vmcs12(vcpu)->cr0_guest_host_mask; | |
edcafe3c | 2284 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); |
5fd86fcf AK |
2285 | } |
2286 | ||
edcafe3c AK |
2287 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
2288 | ||
fe3ef05c NHE |
2289 | /* |
2290 | * Return the cr0 value that a nested guest would read. This is a combination | |
2291 | * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by | |
2292 | * its hypervisor (cr0_read_shadow). | |
2293 | */ | |
2294 | static inline unsigned long nested_read_cr0(struct vmcs12 *fields) | |
2295 | { | |
2296 | return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | | |
2297 | (fields->cr0_read_shadow & fields->cr0_guest_host_mask); | |
2298 | } | |
2299 | static inline unsigned long nested_read_cr4(struct vmcs12 *fields) | |
2300 | { | |
2301 | return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | | |
2302 | (fields->cr4_read_shadow & fields->cr4_guest_host_mask); | |
2303 | } | |
2304 | ||
5fd86fcf AK |
2305 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) |
2306 | { | |
36cf24e0 NHE |
2307 | /* Note that there is no vcpu->fpu_active = 0 here. The caller must |
2308 | * set this *before* calling this function. | |
2309 | */ | |
edcafe3c | 2310 | vmx_decache_cr0_guest_bits(vcpu); |
81231c69 | 2311 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP); |
5fd86fcf | 2312 | update_exception_bitmap(vcpu); |
edcafe3c AK |
2313 | vcpu->arch.cr0_guest_owned_bits = 0; |
2314 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
36cf24e0 NHE |
2315 | if (is_guest_mode(vcpu)) { |
2316 | /* | |
2317 | * L1's specified read shadow might not contain the TS bit, | |
2318 | * so now that we turned on shadowing of this bit, we need to | |
2319 | * set this bit of the shadow. Like in nested_vmx_run we need | |
2320 | * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet | |
2321 | * up-to-date here because we just decached cr0.TS (and we'll | |
2322 | * only update vmcs12->guest_cr0 on nested exit). | |
2323 | */ | |
2324 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2325 | vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) | | |
2326 | (vcpu->arch.cr0 & X86_CR0_TS); | |
2327 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
2328 | } else | |
2329 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf AK |
2330 | } |
2331 | ||
6aa8b732 AK |
2332 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
2333 | { | |
78ac8b47 | 2334 | unsigned long rflags, save_rflags; |
345dcaa8 | 2335 | |
6de12732 AK |
2336 | if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
2337 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); | |
2338 | rflags = vmcs_readl(GUEST_RFLAGS); | |
2339 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
2340 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2341 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
2342 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2343 | } | |
2344 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 | 2345 | } |
6de12732 | 2346 | return to_vmx(vcpu)->rflags; |
6aa8b732 AK |
2347 | } |
2348 | ||
2349 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
2350 | { | |
6de12732 AK |
2351 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
2352 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 AK |
2353 | if (to_vmx(vcpu)->rmode.vm86_active) { |
2354 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 2355 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 2356 | } |
6aa8b732 AK |
2357 | vmcs_writel(GUEST_RFLAGS, rflags); |
2358 | } | |
2359 | ||
be94f6b7 HH |
2360 | static u32 vmx_get_pkru(struct kvm_vcpu *vcpu) |
2361 | { | |
2362 | return to_vmx(vcpu)->guest_pkru; | |
2363 | } | |
2364 | ||
37ccdcbe | 2365 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
2366 | { |
2367 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2368 | int ret = 0; | |
2369 | ||
2370 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 2371 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 2372 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 2373 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 | 2374 | |
37ccdcbe | 2375 | return ret; |
2809f5d2 GC |
2376 | } |
2377 | ||
2378 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
2379 | { | |
2380 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2381 | u32 interruptibility = interruptibility_old; | |
2382 | ||
2383 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
2384 | ||
48005f64 | 2385 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 2386 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 2387 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
2388 | interruptibility |= GUEST_INTR_STATE_STI; |
2389 | ||
2390 | if ((interruptibility != interruptibility_old)) | |
2391 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
2392 | } | |
2393 | ||
6aa8b732 AK |
2394 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
2395 | { | |
2396 | unsigned long rip; | |
6aa8b732 | 2397 | |
5fdbf976 | 2398 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 2399 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 2400 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 2401 | |
2809f5d2 GC |
2402 | /* skipping an emulated instruction also counts */ |
2403 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
2404 | } |
2405 | ||
0b6ac343 NHE |
2406 | /* |
2407 | * KVM wants to inject page-faults which it got to the guest. This function | |
2408 | * checks whether in a nested guest, we need to inject them to L1 or L2. | |
0b6ac343 | 2409 | */ |
e011c663 | 2410 | static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr) |
0b6ac343 NHE |
2411 | { |
2412 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2413 | ||
e011c663 | 2414 | if (!(vmcs12->exception_bitmap & (1u << nr))) |
0b6ac343 NHE |
2415 | return 0; |
2416 | ||
533558bc JK |
2417 | nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason, |
2418 | vmcs_read32(VM_EXIT_INTR_INFO), | |
2419 | vmcs_readl(EXIT_QUALIFICATION)); | |
0b6ac343 NHE |
2420 | return 1; |
2421 | } | |
2422 | ||
298101da | 2423 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
2424 | bool has_error_code, u32 error_code, |
2425 | bool reinject) | |
298101da | 2426 | { |
77ab6db0 | 2427 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8ab2d2e2 | 2428 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 2429 | |
e011c663 GN |
2430 | if (!reinject && is_guest_mode(vcpu) && |
2431 | nested_vmx_check_exception(vcpu, nr)) | |
0b6ac343 NHE |
2432 | return; |
2433 | ||
8ab2d2e2 | 2434 | if (has_error_code) { |
77ab6db0 | 2435 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
2436 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
2437 | } | |
77ab6db0 | 2438 | |
7ffd92c5 | 2439 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
2440 | int inc_eip = 0; |
2441 | if (kvm_exception_is_soft(nr)) | |
2442 | inc_eip = vcpu->arch.event_exit_inst_len; | |
2443 | if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) | |
a92601bb | 2444 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
77ab6db0 JK |
2445 | return; |
2446 | } | |
2447 | ||
66fd3f7f GN |
2448 | if (kvm_exception_is_soft(nr)) { |
2449 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2450 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
2451 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
2452 | } else | |
2453 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2454 | ||
2455 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
298101da AK |
2456 | } |
2457 | ||
4e47c7a6 SY |
2458 | static bool vmx_rdtscp_supported(void) |
2459 | { | |
2460 | return cpu_has_vmx_rdtscp(); | |
2461 | } | |
2462 | ||
ad756a16 MJ |
2463 | static bool vmx_invpcid_supported(void) |
2464 | { | |
2465 | return cpu_has_vmx_invpcid() && enable_ept; | |
2466 | } | |
2467 | ||
a75beee6 ED |
2468 | /* |
2469 | * Swap MSR entry in host/guest MSR entry array. | |
2470 | */ | |
8b9cf98c | 2471 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 2472 | { |
26bb0981 | 2473 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
2474 | |
2475 | tmp = vmx->guest_msrs[to]; | |
2476 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
2477 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
2478 | } |
2479 | ||
8d14695f YZ |
2480 | static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu) |
2481 | { | |
2482 | unsigned long *msr_bitmap; | |
2483 | ||
670125bd WV |
2484 | if (is_guest_mode(vcpu)) |
2485 | msr_bitmap = vmx_msr_bitmap_nested; | |
3ce424e4 RK |
2486 | else if (cpu_has_secondary_exec_ctrls() && |
2487 | (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) & | |
2488 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { | |
8d14695f YZ |
2489 | if (is_long_mode(vcpu)) |
2490 | msr_bitmap = vmx_msr_bitmap_longmode_x2apic; | |
2491 | else | |
2492 | msr_bitmap = vmx_msr_bitmap_legacy_x2apic; | |
2493 | } else { | |
2494 | if (is_long_mode(vcpu)) | |
2495 | msr_bitmap = vmx_msr_bitmap_longmode; | |
2496 | else | |
2497 | msr_bitmap = vmx_msr_bitmap_legacy; | |
2498 | } | |
2499 | ||
2500 | vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); | |
2501 | } | |
2502 | ||
e38aea3e AK |
2503 | /* |
2504 | * Set up the vmcs to automatically save and restore system | |
2505 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
2506 | * mode, as fiddling with msrs is very expensive. | |
2507 | */ | |
8b9cf98c | 2508 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 2509 | { |
26bb0981 | 2510 | int save_nmsrs, index; |
e38aea3e | 2511 | |
a75beee6 ED |
2512 | save_nmsrs = 0; |
2513 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 2514 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 2515 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 2516 | if (index >= 0) |
8b9cf98c RR |
2517 | move_msr_up(vmx, index, save_nmsrs++); |
2518 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 2519 | if (index >= 0) |
8b9cf98c RR |
2520 | move_msr_up(vmx, index, save_nmsrs++); |
2521 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 2522 | if (index >= 0) |
8b9cf98c | 2523 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 | 2524 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
1cea0ce6 | 2525 | if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu)) |
4e47c7a6 | 2526 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 | 2527 | /* |
8c06585d | 2528 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
2529 | * if efer.sce is enabled. |
2530 | */ | |
8c06585d | 2531 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 2532 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 2533 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
2534 | } |
2535 | #endif | |
92c0d900 AK |
2536 | index = __find_msr_index(vmx, MSR_EFER); |
2537 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 2538 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 2539 | |
26bb0981 | 2540 | vmx->save_nmsrs = save_nmsrs; |
5897297b | 2541 | |
8d14695f YZ |
2542 | if (cpu_has_vmx_msr_bitmap()) |
2543 | vmx_set_msr_bitmap(&vmx->vcpu); | |
e38aea3e AK |
2544 | } |
2545 | ||
6aa8b732 AK |
2546 | /* |
2547 | * reads and returns guest's timestamp counter "register" | |
be7b263e HZ |
2548 | * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset |
2549 | * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3 | |
6aa8b732 | 2550 | */ |
be7b263e | 2551 | static u64 guest_read_tsc(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
2552 | { |
2553 | u64 host_tsc, tsc_offset; | |
2554 | ||
4ea1636b | 2555 | host_tsc = rdtsc(); |
6aa8b732 | 2556 | tsc_offset = vmcs_read64(TSC_OFFSET); |
be7b263e | 2557 | return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset; |
6aa8b732 AK |
2558 | } |
2559 | ||
d5c1785d NHE |
2560 | /* |
2561 | * Like guest_read_tsc, but always returns L1's notion of the timestamp | |
2562 | * counter, even if a nested guest (L2) is currently running. | |
2563 | */ | |
48d89b92 | 2564 | static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
d5c1785d | 2565 | { |
886b470c | 2566 | u64 tsc_offset; |
d5c1785d | 2567 | |
d5c1785d NHE |
2568 | tsc_offset = is_guest_mode(vcpu) ? |
2569 | to_vmx(vcpu)->nested.vmcs01_tsc_offset : | |
2570 | vmcs_read64(TSC_OFFSET); | |
2571 | return host_tsc + tsc_offset; | |
2572 | } | |
2573 | ||
ba904635 WA |
2574 | static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu) |
2575 | { | |
2576 | return vmcs_read64(TSC_OFFSET); | |
2577 | } | |
2578 | ||
6aa8b732 | 2579 | /* |
99e3e30a | 2580 | * writes 'offset' into guest's timestamp counter offset register |
6aa8b732 | 2581 | */ |
99e3e30a | 2582 | static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 2583 | { |
27fc51b2 | 2584 | if (is_guest_mode(vcpu)) { |
7991825b | 2585 | /* |
27fc51b2 NHE |
2586 | * We're here if L1 chose not to trap WRMSR to TSC. According |
2587 | * to the spec, this should set L1's TSC; The offset that L1 | |
2588 | * set for L2 remains unchanged, and still needs to be added | |
2589 | * to the newly set TSC to get L2's TSC. | |
7991825b | 2590 | */ |
27fc51b2 NHE |
2591 | struct vmcs12 *vmcs12; |
2592 | to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset; | |
2593 | /* recalculate vmcs02.TSC_OFFSET: */ | |
2594 | vmcs12 = get_vmcs12(vcpu); | |
2595 | vmcs_write64(TSC_OFFSET, offset + | |
2596 | (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ? | |
2597 | vmcs12->tsc_offset : 0)); | |
2598 | } else { | |
489223ed YY |
2599 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2600 | vmcs_read64(TSC_OFFSET), offset); | |
27fc51b2 NHE |
2601 | vmcs_write64(TSC_OFFSET, offset); |
2602 | } | |
6aa8b732 AK |
2603 | } |
2604 | ||
58ea6767 | 2605 | static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment) |
e48672fa ZA |
2606 | { |
2607 | u64 offset = vmcs_read64(TSC_OFFSET); | |
489223ed | 2608 | |
e48672fa | 2609 | vmcs_write64(TSC_OFFSET, offset + adjustment); |
7991825b NHE |
2610 | if (is_guest_mode(vcpu)) { |
2611 | /* Even when running L2, the adjustment needs to apply to L1 */ | |
2612 | to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment; | |
489223ed YY |
2613 | } else |
2614 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset, | |
2615 | offset + adjustment); | |
e48672fa ZA |
2616 | } |
2617 | ||
801d3424 NHE |
2618 | static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu) |
2619 | { | |
2620 | struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
2621 | return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31))); | |
2622 | } | |
2623 | ||
2624 | /* | |
2625 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
2626 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
2627 | * all guests if the "nested" module option is off, and can also be disabled | |
2628 | * for a single guest by disabling its VMX cpuid bit. | |
2629 | */ | |
2630 | static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) | |
2631 | { | |
2632 | return nested && guest_cpuid_has_vmx(vcpu); | |
2633 | } | |
2634 | ||
b87a51ae NHE |
2635 | /* |
2636 | * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be | |
2637 | * returned for the various VMX controls MSRs when nested VMX is enabled. | |
2638 | * The same values should also be used to verify that vmcs12 control fields are | |
2639 | * valid during nested entry from L1 to L2. | |
2640 | * Each of these control msrs has a low and high 32-bit half: A low bit is on | |
2641 | * if the corresponding bit in the (32-bit) control field *must* be on, and a | |
2642 | * bit in the high half is on if the corresponding bit in the control field | |
2643 | * may be on. See also vmx_control_verify(). | |
b87a51ae | 2644 | */ |
b9c237bb | 2645 | static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx) |
b87a51ae NHE |
2646 | { |
2647 | /* | |
2648 | * Note that as a general rule, the high half of the MSRs (bits in | |
2649 | * the control fields which may be 1) should be initialized by the | |
2650 | * intersection of the underlying hardware's MSR (i.e., features which | |
2651 | * can be supported) and the list of features we want to expose - | |
2652 | * because they are known to be properly supported in our code. | |
2653 | * Also, usually, the low half of the MSRs (bits which must be 1) can | |
2654 | * be set to 0, meaning that L1 may turn off any of these bits. The | |
2655 | * reason is that if one of these bits is necessary, it will appear | |
2656 | * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control | |
2657 | * fields of vmcs01 and vmcs02, will turn these bits off - and | |
2658 | * nested_vmx_exit_handled() will not pass related exits to L1. | |
2659 | * These rules have exceptions below. | |
2660 | */ | |
2661 | ||
2662 | /* pin-based controls */ | |
eabeaacc | 2663 | rdmsr(MSR_IA32_VMX_PINBASED_CTLS, |
b9c237bb WV |
2664 | vmx->nested.nested_vmx_pinbased_ctls_low, |
2665 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
2666 | vmx->nested.nested_vmx_pinbased_ctls_low |= | |
2667 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2668 | vmx->nested.nested_vmx_pinbased_ctls_high &= | |
2669 | PIN_BASED_EXT_INTR_MASK | | |
2670 | PIN_BASED_NMI_EXITING | | |
2671 | PIN_BASED_VIRTUAL_NMIS; | |
2672 | vmx->nested.nested_vmx_pinbased_ctls_high |= | |
2673 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
0238ea91 | 2674 | PIN_BASED_VMX_PREEMPTION_TIMER; |
d62caabb | 2675 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) |
705699a1 WV |
2676 | vmx->nested.nested_vmx_pinbased_ctls_high |= |
2677 | PIN_BASED_POSTED_INTR; | |
b87a51ae | 2678 | |
3dbcd8da | 2679 | /* exit controls */ |
c0dfee58 | 2680 | rdmsr(MSR_IA32_VMX_EXIT_CTLS, |
b9c237bb WV |
2681 | vmx->nested.nested_vmx_exit_ctls_low, |
2682 | vmx->nested.nested_vmx_exit_ctls_high); | |
2683 | vmx->nested.nested_vmx_exit_ctls_low = | |
2684 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
e0ba1a6f | 2685 | |
b9c237bb | 2686 | vmx->nested.nested_vmx_exit_ctls_high &= |
b87a51ae | 2687 | #ifdef CONFIG_X86_64 |
c0dfee58 | 2688 | VM_EXIT_HOST_ADDR_SPACE_SIZE | |
b87a51ae | 2689 | #endif |
f4124500 | 2690 | VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT; |
b9c237bb WV |
2691 | vmx->nested.nested_vmx_exit_ctls_high |= |
2692 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | | |
f4124500 | 2693 | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | |
e0ba1a6f BD |
2694 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; |
2695 | ||
a87036ad | 2696 | if (kvm_mpx_supported()) |
b9c237bb | 2697 | vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; |
b87a51ae | 2698 | |
2996fca0 | 2699 | /* We support free control of debug control saving. */ |
b9c237bb WV |
2700 | vmx->nested.nested_vmx_true_exit_ctls_low = |
2701 | vmx->nested.nested_vmx_exit_ctls_low & | |
2996fca0 JK |
2702 | ~VM_EXIT_SAVE_DEBUG_CONTROLS; |
2703 | ||
b87a51ae NHE |
2704 | /* entry controls */ |
2705 | rdmsr(MSR_IA32_VMX_ENTRY_CTLS, | |
b9c237bb WV |
2706 | vmx->nested.nested_vmx_entry_ctls_low, |
2707 | vmx->nested.nested_vmx_entry_ctls_high); | |
2708 | vmx->nested.nested_vmx_entry_ctls_low = | |
2709 | VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
2710 | vmx->nested.nested_vmx_entry_ctls_high &= | |
57435349 JK |
2711 | #ifdef CONFIG_X86_64 |
2712 | VM_ENTRY_IA32E_MODE | | |
2713 | #endif | |
2714 | VM_ENTRY_LOAD_IA32_PAT; | |
b9c237bb WV |
2715 | vmx->nested.nested_vmx_entry_ctls_high |= |
2716 | (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER); | |
a87036ad | 2717 | if (kvm_mpx_supported()) |
b9c237bb | 2718 | vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; |
57435349 | 2719 | |
2996fca0 | 2720 | /* We support free control of debug control loading. */ |
b9c237bb WV |
2721 | vmx->nested.nested_vmx_true_entry_ctls_low = |
2722 | vmx->nested.nested_vmx_entry_ctls_low & | |
2996fca0 JK |
2723 | ~VM_ENTRY_LOAD_DEBUG_CONTROLS; |
2724 | ||
b87a51ae NHE |
2725 | /* cpu-based controls */ |
2726 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, | |
b9c237bb WV |
2727 | vmx->nested.nested_vmx_procbased_ctls_low, |
2728 | vmx->nested.nested_vmx_procbased_ctls_high); | |
2729 | vmx->nested.nested_vmx_procbased_ctls_low = | |
2730 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2731 | vmx->nested.nested_vmx_procbased_ctls_high &= | |
a294c9bb JK |
2732 | CPU_BASED_VIRTUAL_INTR_PENDING | |
2733 | CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING | | |
b87a51ae NHE |
2734 | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | |
2735 | CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | | |
2736 | CPU_BASED_CR3_STORE_EXITING | | |
2737 | #ifdef CONFIG_X86_64 | |
2738 | CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | | |
2739 | #endif | |
2740 | CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | | |
5f3d45e7 MD |
2741 | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG | |
2742 | CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING | | |
2743 | CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING | | |
2744 | CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
b87a51ae NHE |
2745 | /* |
2746 | * We can allow some features even when not supported by the | |
2747 | * hardware. For example, L1 can specify an MSR bitmap - and we | |
2748 | * can use it to avoid exits to L1 - even when L0 runs L2 | |
2749 | * without MSR bitmaps. | |
2750 | */ | |
b9c237bb WV |
2751 | vmx->nested.nested_vmx_procbased_ctls_high |= |
2752 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
560b7ee1 | 2753 | CPU_BASED_USE_MSR_BITMAPS; |
b87a51ae | 2754 | |
3dcdf3ec | 2755 | /* We support free control of CR3 access interception. */ |
b9c237bb WV |
2756 | vmx->nested.nested_vmx_true_procbased_ctls_low = |
2757 | vmx->nested.nested_vmx_procbased_ctls_low & | |
3dcdf3ec JK |
2758 | ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); |
2759 | ||
b87a51ae NHE |
2760 | /* secondary cpu-based controls */ |
2761 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, | |
b9c237bb WV |
2762 | vmx->nested.nested_vmx_secondary_ctls_low, |
2763 | vmx->nested.nested_vmx_secondary_ctls_high); | |
2764 | vmx->nested.nested_vmx_secondary_ctls_low = 0; | |
2765 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
d6851fbe | 2766 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
b3a2a907 | 2767 | SECONDARY_EXEC_RDTSCP | |
f2b93280 | 2768 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
5c614b35 | 2769 | SECONDARY_EXEC_ENABLE_VPID | |
82f0dd4b | 2770 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
608406e2 | 2771 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
81dc01f7 | 2772 | SECONDARY_EXEC_WBINVD_EXITING | |
8b3e34e4 XG |
2773 | SECONDARY_EXEC_XSAVES | |
2774 | SECONDARY_EXEC_PCOMMIT; | |
c18911a2 | 2775 | |
afa61f75 NHE |
2776 | if (enable_ept) { |
2777 | /* nested EPT: emulate EPT also to L1 */ | |
b9c237bb | 2778 | vmx->nested.nested_vmx_secondary_ctls_high |= |
0790ec17 | 2779 | SECONDARY_EXEC_ENABLE_EPT; |
b9c237bb | 2780 | vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT | |
d3134dbf JK |
2781 | VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT | |
2782 | VMX_EPT_INVEPT_BIT; | |
b9c237bb | 2783 | vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept; |
afa61f75 | 2784 | /* |
4b855078 BD |
2785 | * For nested guests, we don't do anything specific |
2786 | * for single context invalidation. Hence, only advertise | |
2787 | * support for global context invalidation. | |
afa61f75 | 2788 | */ |
b9c237bb | 2789 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT; |
afa61f75 | 2790 | } else |
b9c237bb | 2791 | vmx->nested.nested_vmx_ept_caps = 0; |
afa61f75 | 2792 | |
ef697a71 PB |
2793 | /* |
2794 | * Old versions of KVM use the single-context version without | |
2795 | * checking for support, so declare that it is supported even | |
2796 | * though it is treated as global context. The alternative is | |
2797 | * not failing the single-context invvpid, and it is worse. | |
2798 | */ | |
089d7b6e WL |
2799 | if (enable_vpid) |
2800 | vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT | | |
ef697a71 | 2801 | VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | |
089d7b6e WL |
2802 | VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; |
2803 | else | |
2804 | vmx->nested.nested_vmx_vpid_caps = 0; | |
99b83ac8 | 2805 | |
0790ec17 RK |
2806 | if (enable_unrestricted_guest) |
2807 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2808 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
2809 | ||
c18911a2 | 2810 | /* miscellaneous data */ |
b9c237bb WV |
2811 | rdmsr(MSR_IA32_VMX_MISC, |
2812 | vmx->nested.nested_vmx_misc_low, | |
2813 | vmx->nested.nested_vmx_misc_high); | |
2814 | vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA; | |
2815 | vmx->nested.nested_vmx_misc_low |= | |
2816 | VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | | |
f4124500 | 2817 | VMX_MISC_ACTIVITY_HLT; |
b9c237bb | 2818 | vmx->nested.nested_vmx_misc_high = 0; |
b87a51ae NHE |
2819 | } |
2820 | ||
2821 | static inline bool vmx_control_verify(u32 control, u32 low, u32 high) | |
2822 | { | |
2823 | /* | |
2824 | * Bits 0 in high must be 0, and bits 1 in low must be 1. | |
2825 | */ | |
2826 | return ((control & high) | low) == control; | |
2827 | } | |
2828 | ||
2829 | static inline u64 vmx_control_msr(u32 low, u32 high) | |
2830 | { | |
2831 | return low | ((u64)high << 32); | |
2832 | } | |
2833 | ||
cae50139 | 2834 | /* Returns 0 on success, non-0 otherwise. */ |
b87a51ae NHE |
2835 | static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) |
2836 | { | |
b9c237bb WV |
2837 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2838 | ||
b87a51ae | 2839 | switch (msr_index) { |
b87a51ae NHE |
2840 | case MSR_IA32_VMX_BASIC: |
2841 | /* | |
2842 | * This MSR reports some information about VMX support. We | |
2843 | * should return information about the VMX we emulate for the | |
2844 | * guest, and the VMCS structure we give it - not about the | |
2845 | * VMX support of the underlying hardware. | |
2846 | */ | |
3dbcd8da | 2847 | *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS | |
b87a51ae NHE |
2848 | ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | |
2849 | (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); | |
2850 | break; | |
2851 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
2852 | case MSR_IA32_VMX_PINBASED_CTLS: | |
b9c237bb WV |
2853 | *pdata = vmx_control_msr( |
2854 | vmx->nested.nested_vmx_pinbased_ctls_low, | |
2855 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
b87a51ae NHE |
2856 | break; |
2857 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
b9c237bb WV |
2858 | *pdata = vmx_control_msr( |
2859 | vmx->nested.nested_vmx_true_procbased_ctls_low, | |
2860 | vmx->nested.nested_vmx_procbased_ctls_high); | |
3dcdf3ec | 2861 | break; |
b87a51ae | 2862 | case MSR_IA32_VMX_PROCBASED_CTLS: |
b9c237bb WV |
2863 | *pdata = vmx_control_msr( |
2864 | vmx->nested.nested_vmx_procbased_ctls_low, | |
2865 | vmx->nested.nested_vmx_procbased_ctls_high); | |
b87a51ae NHE |
2866 | break; |
2867 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
b9c237bb WV |
2868 | *pdata = vmx_control_msr( |
2869 | vmx->nested.nested_vmx_true_exit_ctls_low, | |
2870 | vmx->nested.nested_vmx_exit_ctls_high); | |
2996fca0 | 2871 | break; |
b87a51ae | 2872 | case MSR_IA32_VMX_EXIT_CTLS: |
b9c237bb WV |
2873 | *pdata = vmx_control_msr( |
2874 | vmx->nested.nested_vmx_exit_ctls_low, | |
2875 | vmx->nested.nested_vmx_exit_ctls_high); | |
b87a51ae NHE |
2876 | break; |
2877 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
b9c237bb WV |
2878 | *pdata = vmx_control_msr( |
2879 | vmx->nested.nested_vmx_true_entry_ctls_low, | |
2880 | vmx->nested.nested_vmx_entry_ctls_high); | |
2996fca0 | 2881 | break; |
b87a51ae | 2882 | case MSR_IA32_VMX_ENTRY_CTLS: |
b9c237bb WV |
2883 | *pdata = vmx_control_msr( |
2884 | vmx->nested.nested_vmx_entry_ctls_low, | |
2885 | vmx->nested.nested_vmx_entry_ctls_high); | |
b87a51ae NHE |
2886 | break; |
2887 | case MSR_IA32_VMX_MISC: | |
b9c237bb WV |
2888 | *pdata = vmx_control_msr( |
2889 | vmx->nested.nested_vmx_misc_low, | |
2890 | vmx->nested.nested_vmx_misc_high); | |
b87a51ae NHE |
2891 | break; |
2892 | /* | |
2893 | * These MSRs specify bits which the guest must keep fixed (on or off) | |
2894 | * while L1 is in VMXON mode (in L1's root mode, or running an L2). | |
2895 | * We picked the standard core2 setting. | |
2896 | */ | |
2897 | #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) | |
2898 | #define VMXON_CR4_ALWAYSON X86_CR4_VMXE | |
2899 | case MSR_IA32_VMX_CR0_FIXED0: | |
2900 | *pdata = VMXON_CR0_ALWAYSON; | |
2901 | break; | |
2902 | case MSR_IA32_VMX_CR0_FIXED1: | |
2903 | *pdata = -1ULL; | |
2904 | break; | |
2905 | case MSR_IA32_VMX_CR4_FIXED0: | |
2906 | *pdata = VMXON_CR4_ALWAYSON; | |
2907 | break; | |
2908 | case MSR_IA32_VMX_CR4_FIXED1: | |
2909 | *pdata = -1ULL; | |
2910 | break; | |
2911 | case MSR_IA32_VMX_VMCS_ENUM: | |
5381417f | 2912 | *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */ |
b87a51ae NHE |
2913 | break; |
2914 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
b9c237bb WV |
2915 | *pdata = vmx_control_msr( |
2916 | vmx->nested.nested_vmx_secondary_ctls_low, | |
2917 | vmx->nested.nested_vmx_secondary_ctls_high); | |
b87a51ae NHE |
2918 | break; |
2919 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
afa61f75 | 2920 | /* Currently, no nested vpid support */ |
089d7b6e WL |
2921 | *pdata = vmx->nested.nested_vmx_ept_caps | |
2922 | ((u64)vmx->nested.nested_vmx_vpid_caps << 32); | |
b87a51ae NHE |
2923 | break; |
2924 | default: | |
b87a51ae | 2925 | return 1; |
b3897a49 NHE |
2926 | } |
2927 | ||
b87a51ae NHE |
2928 | return 0; |
2929 | } | |
2930 | ||
6aa8b732 AK |
2931 | /* |
2932 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2933 | * Returns 0 on success, non-0 otherwise. | |
2934 | * Assumes vcpu_load() was already called. | |
2935 | */ | |
609e36d3 | 2936 | static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 2937 | { |
26bb0981 | 2938 | struct shared_msr_entry *msr; |
6aa8b732 | 2939 | |
609e36d3 | 2940 | switch (msr_info->index) { |
05b3e0c2 | 2941 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2942 | case MSR_FS_BASE: |
609e36d3 | 2943 | msr_info->data = vmcs_readl(GUEST_FS_BASE); |
6aa8b732 AK |
2944 | break; |
2945 | case MSR_GS_BASE: | |
609e36d3 | 2946 | msr_info->data = vmcs_readl(GUEST_GS_BASE); |
6aa8b732 | 2947 | break; |
44ea2b17 AK |
2948 | case MSR_KERNEL_GS_BASE: |
2949 | vmx_load_host_state(to_vmx(vcpu)); | |
609e36d3 | 2950 | msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base; |
44ea2b17 | 2951 | break; |
26bb0981 | 2952 | #endif |
6aa8b732 | 2953 | case MSR_EFER: |
609e36d3 | 2954 | return kvm_get_msr_common(vcpu, msr_info); |
af24a4e4 | 2955 | case MSR_IA32_TSC: |
be7b263e | 2956 | msr_info->data = guest_read_tsc(vcpu); |
6aa8b732 AK |
2957 | break; |
2958 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 2959 | msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); |
6aa8b732 AK |
2960 | break; |
2961 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 2962 | msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
2963 | break; |
2964 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 2965 | msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 2966 | break; |
0dd376e7 | 2967 | case MSR_IA32_BNDCFGS: |
a87036ad | 2968 | if (!kvm_mpx_supported()) |
93c4adc7 | 2969 | return 1; |
609e36d3 | 2970 | msr_info->data = vmcs_read64(GUEST_BNDCFGS); |
0dd376e7 | 2971 | break; |
cae50139 JK |
2972 | case MSR_IA32_FEATURE_CONTROL: |
2973 | if (!nested_vmx_allowed(vcpu)) | |
2974 | return 1; | |
609e36d3 | 2975 | msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control; |
cae50139 JK |
2976 | break; |
2977 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
2978 | if (!nested_vmx_allowed(vcpu)) | |
2979 | return 1; | |
609e36d3 | 2980 | return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data); |
20300099 WL |
2981 | case MSR_IA32_XSS: |
2982 | if (!vmx_xsaves_supported()) | |
2983 | return 1; | |
609e36d3 | 2984 | msr_info->data = vcpu->arch.ia32_xss; |
20300099 | 2985 | break; |
4e47c7a6 | 2986 | case MSR_TSC_AUX: |
81b1b9ca | 2987 | if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated) |
4e47c7a6 SY |
2988 | return 1; |
2989 | /* Otherwise falls through */ | |
6aa8b732 | 2990 | default: |
609e36d3 | 2991 | msr = find_msr_entry(to_vmx(vcpu), msr_info->index); |
3bab1f5d | 2992 | if (msr) { |
609e36d3 | 2993 | msr_info->data = msr->data; |
3bab1f5d | 2994 | break; |
6aa8b732 | 2995 | } |
609e36d3 | 2996 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
2997 | } |
2998 | ||
6aa8b732 AK |
2999 | return 0; |
3000 | } | |
3001 | ||
cae50139 JK |
3002 | static void vmx_leave_nested(struct kvm_vcpu *vcpu); |
3003 | ||
6aa8b732 AK |
3004 | /* |
3005 | * Writes msr value into into the appropriate "register". | |
3006 | * Returns 0 on success, non-0 otherwise. | |
3007 | * Assumes vcpu_load() was already called. | |
3008 | */ | |
8fe8ab46 | 3009 | static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3010 | { |
a2fa3e9f | 3011 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 3012 | struct shared_msr_entry *msr; |
2cc51560 | 3013 | int ret = 0; |
8fe8ab46 WA |
3014 | u32 msr_index = msr_info->index; |
3015 | u64 data = msr_info->data; | |
2cc51560 | 3016 | |
6aa8b732 | 3017 | switch (msr_index) { |
3bab1f5d | 3018 | case MSR_EFER: |
8fe8ab46 | 3019 | ret = kvm_set_msr_common(vcpu, msr_info); |
2cc51560 | 3020 | break; |
16175a79 | 3021 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3022 | case MSR_FS_BASE: |
2fb92db1 | 3023 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3024 | vmcs_writel(GUEST_FS_BASE, data); |
3025 | break; | |
3026 | case MSR_GS_BASE: | |
2fb92db1 | 3027 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3028 | vmcs_writel(GUEST_GS_BASE, data); |
3029 | break; | |
44ea2b17 AK |
3030 | case MSR_KERNEL_GS_BASE: |
3031 | vmx_load_host_state(vmx); | |
3032 | vmx->msr_guest_kernel_gs_base = data; | |
3033 | break; | |
6aa8b732 AK |
3034 | #endif |
3035 | case MSR_IA32_SYSENTER_CS: | |
3036 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
3037 | break; | |
3038 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 3039 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
3040 | break; |
3041 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 3042 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 3043 | break; |
0dd376e7 | 3044 | case MSR_IA32_BNDCFGS: |
a87036ad | 3045 | if (!kvm_mpx_supported()) |
93c4adc7 | 3046 | return 1; |
0dd376e7 LJ |
3047 | vmcs_write64(GUEST_BNDCFGS, data); |
3048 | break; | |
af24a4e4 | 3049 | case MSR_IA32_TSC: |
8fe8ab46 | 3050 | kvm_write_tsc(vcpu, msr_info); |
6aa8b732 | 3051 | break; |
468d472f SY |
3052 | case MSR_IA32_CR_PAT: |
3053 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
4566654b NA |
3054 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) |
3055 | return 1; | |
468d472f SY |
3056 | vmcs_write64(GUEST_IA32_PAT, data); |
3057 | vcpu->arch.pat = data; | |
3058 | break; | |
3059 | } | |
8fe8ab46 | 3060 | ret = kvm_set_msr_common(vcpu, msr_info); |
4e47c7a6 | 3061 | break; |
ba904635 WA |
3062 | case MSR_IA32_TSC_ADJUST: |
3063 | ret = kvm_set_msr_common(vcpu, msr_info); | |
4e47c7a6 | 3064 | break; |
cae50139 JK |
3065 | case MSR_IA32_FEATURE_CONTROL: |
3066 | if (!nested_vmx_allowed(vcpu) || | |
3067 | (to_vmx(vcpu)->nested.msr_ia32_feature_control & | |
3068 | FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) | |
3069 | return 1; | |
3070 | vmx->nested.msr_ia32_feature_control = data; | |
3071 | if (msr_info->host_initiated && data == 0) | |
3072 | vmx_leave_nested(vcpu); | |
3073 | break; | |
3074 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
3075 | return 1; /* they are read-only */ | |
20300099 WL |
3076 | case MSR_IA32_XSS: |
3077 | if (!vmx_xsaves_supported()) | |
3078 | return 1; | |
3079 | /* | |
3080 | * The only supported bit as of Skylake is bit 8, but | |
3081 | * it is not supported on KVM. | |
3082 | */ | |
3083 | if (data != 0) | |
3084 | return 1; | |
3085 | vcpu->arch.ia32_xss = data; | |
3086 | if (vcpu->arch.ia32_xss != host_xss) | |
3087 | add_atomic_switch_msr(vmx, MSR_IA32_XSS, | |
3088 | vcpu->arch.ia32_xss, host_xss); | |
3089 | else | |
3090 | clear_atomic_switch_msr(vmx, MSR_IA32_XSS); | |
3091 | break; | |
4e47c7a6 | 3092 | case MSR_TSC_AUX: |
81b1b9ca | 3093 | if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated) |
4e47c7a6 SY |
3094 | return 1; |
3095 | /* Check reserved bit, higher 32 bits should be zero */ | |
3096 | if ((data >> 32) != 0) | |
3097 | return 1; | |
3098 | /* Otherwise falls through */ | |
6aa8b732 | 3099 | default: |
8b9cf98c | 3100 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 3101 | if (msr) { |
8b3c3104 | 3102 | u64 old_msr_data = msr->data; |
3bab1f5d | 3103 | msr->data = data; |
2225fd56 AK |
3104 | if (msr - vmx->guest_msrs < vmx->save_nmsrs) { |
3105 | preempt_disable(); | |
8b3c3104 AH |
3106 | ret = kvm_set_shared_msr(msr->index, msr->data, |
3107 | msr->mask); | |
2225fd56 | 3108 | preempt_enable(); |
8b3c3104 AH |
3109 | if (ret) |
3110 | msr->data = old_msr_data; | |
2225fd56 | 3111 | } |
3bab1f5d | 3112 | break; |
6aa8b732 | 3113 | } |
8fe8ab46 | 3114 | ret = kvm_set_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3115 | } |
3116 | ||
2cc51560 | 3117 | return ret; |
6aa8b732 AK |
3118 | } |
3119 | ||
5fdbf976 | 3120 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 3121 | { |
5fdbf976 MT |
3122 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
3123 | switch (reg) { | |
3124 | case VCPU_REGS_RSP: | |
3125 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
3126 | break; | |
3127 | case VCPU_REGS_RIP: | |
3128 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
3129 | break; | |
6de4f3ad AK |
3130 | case VCPU_EXREG_PDPTR: |
3131 | if (enable_ept) | |
3132 | ept_save_pdptrs(vcpu); | |
3133 | break; | |
5fdbf976 MT |
3134 | default: |
3135 | break; | |
3136 | } | |
6aa8b732 AK |
3137 | } |
3138 | ||
6aa8b732 AK |
3139 | static __init int cpu_has_kvm_support(void) |
3140 | { | |
6210e37b | 3141 | return cpu_has_vmx(); |
6aa8b732 AK |
3142 | } |
3143 | ||
3144 | static __init int vmx_disabled_by_bios(void) | |
3145 | { | |
3146 | u64 msr; | |
3147 | ||
3148 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 3149 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 3150 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
3151 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
3152 | && tboot_enabled()) | |
3153 | return 1; | |
23f3e991 | 3154 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 3155 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 3156 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
3157 | && !tboot_enabled()) { |
3158 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 3159 | "activate TXT before enabling KVM\n"); |
cafd6659 | 3160 | return 1; |
f9335afe | 3161 | } |
23f3e991 JC |
3162 | /* launched w/o TXT and VMX disabled */ |
3163 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
3164 | && !tboot_enabled()) | |
3165 | return 1; | |
cafd6659 SW |
3166 | } |
3167 | ||
3168 | return 0; | |
6aa8b732 AK |
3169 | } |
3170 | ||
7725b894 DX |
3171 | static void kvm_cpu_vmxon(u64 addr) |
3172 | { | |
1c5ac21a AS |
3173 | intel_pt_handle_vmx(1); |
3174 | ||
7725b894 DX |
3175 | asm volatile (ASM_VMX_VMXON_RAX |
3176 | : : "a"(&addr), "m"(addr) | |
3177 | : "memory", "cc"); | |
3178 | } | |
3179 | ||
13a34e06 | 3180 | static int hardware_enable(void) |
6aa8b732 AK |
3181 | { |
3182 | int cpu = raw_smp_processor_id(); | |
3183 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 3184 | u64 old, test_bits; |
6aa8b732 | 3185 | |
1e02ce4c | 3186 | if (cr4_read_shadow() & X86_CR4_VMXE) |
10474ae8 AG |
3187 | return -EBUSY; |
3188 | ||
d462b819 | 3189 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
bf9f6ac8 FW |
3190 | INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); |
3191 | spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
8f536b76 ZY |
3192 | |
3193 | /* | |
3194 | * Now we can enable the vmclear operation in kdump | |
3195 | * since the loaded_vmcss_on_cpu list on this cpu | |
3196 | * has been initialized. | |
3197 | * | |
3198 | * Though the cpu is not in VMX operation now, there | |
3199 | * is no problem to enable the vmclear operation | |
3200 | * for the loaded_vmcss_on_cpu list is empty! | |
3201 | */ | |
3202 | crash_enable_local_vmclear(cpu); | |
3203 | ||
6aa8b732 | 3204 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
3205 | |
3206 | test_bits = FEATURE_CONTROL_LOCKED; | |
3207 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
3208 | if (tboot_enabled()) | |
3209 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
3210 | ||
3211 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 3212 | /* enable and lock */ |
cafd6659 SW |
3213 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
3214 | } | |
375074cc | 3215 | cr4_set_bits(X86_CR4_VMXE); |
10474ae8 | 3216 | |
4610c9cc DX |
3217 | if (vmm_exclusive) { |
3218 | kvm_cpu_vmxon(phys_addr); | |
3219 | ept_sync_global(); | |
3220 | } | |
10474ae8 | 3221 | |
89cbc767 | 3222 | native_store_gdt(this_cpu_ptr(&host_gdt)); |
3444d7da | 3223 | |
10474ae8 | 3224 | return 0; |
6aa8b732 AK |
3225 | } |
3226 | ||
d462b819 | 3227 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
3228 | { |
3229 | int cpu = raw_smp_processor_id(); | |
d462b819 | 3230 | struct loaded_vmcs *v, *n; |
543e4243 | 3231 | |
d462b819 NHE |
3232 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
3233 | loaded_vmcss_on_cpu_link) | |
3234 | __loaded_vmcs_clear(v); | |
543e4243 AK |
3235 | } |
3236 | ||
710ff4a8 EH |
3237 | |
3238 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
3239 | * tricks. | |
3240 | */ | |
3241 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 3242 | { |
4ecac3fd | 3243 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
1c5ac21a AS |
3244 | |
3245 | intel_pt_handle_vmx(0); | |
6aa8b732 AK |
3246 | } |
3247 | ||
13a34e06 | 3248 | static void hardware_disable(void) |
710ff4a8 | 3249 | { |
4610c9cc | 3250 | if (vmm_exclusive) { |
d462b819 | 3251 | vmclear_local_loaded_vmcss(); |
4610c9cc DX |
3252 | kvm_cpu_vmxoff(); |
3253 | } | |
375074cc | 3254 | cr4_clear_bits(X86_CR4_VMXE); |
710ff4a8 EH |
3255 | } |
3256 | ||
1c3d14fe | 3257 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 3258 | u32 msr, u32 *result) |
1c3d14fe YS |
3259 | { |
3260 | u32 vmx_msr_low, vmx_msr_high; | |
3261 | u32 ctl = ctl_min | ctl_opt; | |
3262 | ||
3263 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3264 | ||
3265 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
3266 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
3267 | ||
3268 | /* Ensure minimum (required) set of control bits are supported. */ | |
3269 | if (ctl_min & ~ctl) | |
002c7f7c | 3270 | return -EIO; |
1c3d14fe YS |
3271 | |
3272 | *result = ctl; | |
3273 | return 0; | |
3274 | } | |
3275 | ||
110312c8 AK |
3276 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
3277 | { | |
3278 | u32 vmx_msr_low, vmx_msr_high; | |
3279 | ||
3280 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3281 | return vmx_msr_high & ctl; | |
3282 | } | |
3283 | ||
002c7f7c | 3284 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
3285 | { |
3286 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 3287 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
3288 | u32 _pin_based_exec_control = 0; |
3289 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 3290 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
3291 | u32 _vmexit_control = 0; |
3292 | u32 _vmentry_control = 0; | |
3293 | ||
10166744 | 3294 | min = CPU_BASED_HLT_EXITING | |
1c3d14fe YS |
3295 | #ifdef CONFIG_X86_64 |
3296 | CPU_BASED_CR8_LOAD_EXITING | | |
3297 | CPU_BASED_CR8_STORE_EXITING | | |
3298 | #endif | |
d56f546d SY |
3299 | CPU_BASED_CR3_LOAD_EXITING | |
3300 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
3301 | CPU_BASED_USE_IO_BITMAPS | |
3302 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 3303 | CPU_BASED_USE_TSC_OFFSETING | |
59708670 SY |
3304 | CPU_BASED_MWAIT_EXITING | |
3305 | CPU_BASED_MONITOR_EXITING | | |
fee84b07 AK |
3306 | CPU_BASED_INVLPG_EXITING | |
3307 | CPU_BASED_RDPMC_EXITING; | |
443381a8 | 3308 | |
f78e0e2e | 3309 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 3310 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 3311 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
3312 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
3313 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 3314 | return -EIO; |
6e5d865c YS |
3315 | #ifdef CONFIG_X86_64 |
3316 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3317 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
3318 | ~CPU_BASED_CR8_STORE_EXITING; | |
3319 | #endif | |
f78e0e2e | 3320 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
3321 | min2 = 0; |
3322 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
8d14695f | 3323 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2384d2b3 | 3324 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 3325 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 3326 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 3327 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 | 3328 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
ad756a16 | 3329 | SECONDARY_EXEC_RDTSCP | |
83d4c286 | 3330 | SECONDARY_EXEC_ENABLE_INVPCID | |
c7c9c56c | 3331 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
abc4fc58 | 3332 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
20300099 | 3333 | SECONDARY_EXEC_SHADOW_VMCS | |
843e4330 | 3334 | SECONDARY_EXEC_XSAVES | |
8b3e34e4 | 3335 | SECONDARY_EXEC_ENABLE_PML | |
64903d61 HZ |
3336 | SECONDARY_EXEC_PCOMMIT | |
3337 | SECONDARY_EXEC_TSC_SCALING; | |
d56f546d SY |
3338 | if (adjust_vmx_controls(min2, opt2, |
3339 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
3340 | &_cpu_based_2nd_exec_control) < 0) |
3341 | return -EIO; | |
3342 | } | |
3343 | #ifndef CONFIG_X86_64 | |
3344 | if (!(_cpu_based_2nd_exec_control & | |
3345 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
3346 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
3347 | #endif | |
83d4c286 YZ |
3348 | |
3349 | if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3350 | _cpu_based_2nd_exec_control &= ~( | |
8d14695f | 3351 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
c7c9c56c YZ |
3352 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
3353 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
83d4c286 | 3354 | |
d56f546d | 3355 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
3356 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
3357 | enabled */ | |
5fff7d27 GN |
3358 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
3359 | CPU_BASED_CR3_STORE_EXITING | | |
3360 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
3361 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, |
3362 | vmx_capability.ept, vmx_capability.vpid); | |
3363 | } | |
1c3d14fe | 3364 | |
81908bf4 | 3365 | min = VM_EXIT_SAVE_DEBUG_CONTROLS; |
1c3d14fe YS |
3366 | #ifdef CONFIG_X86_64 |
3367 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
3368 | #endif | |
a547c6db | 3369 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT | |
da8999d3 | 3370 | VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS; |
1c3d14fe YS |
3371 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
3372 | &_vmexit_control) < 0) | |
002c7f7c | 3373 | return -EIO; |
1c3d14fe | 3374 | |
01e439be | 3375 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; |
64672c95 YJ |
3376 | opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | |
3377 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
3378 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
3379 | &_pin_based_exec_control) < 0) | |
3380 | return -EIO; | |
3381 | ||
3382 | if (!(_cpu_based_2nd_exec_control & | |
3383 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) || | |
3384 | !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT)) | |
3385 | _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; | |
3386 | ||
c845f9c6 | 3387 | min = VM_ENTRY_LOAD_DEBUG_CONTROLS; |
da8999d3 | 3388 | opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS; |
1c3d14fe YS |
3389 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
3390 | &_vmentry_control) < 0) | |
002c7f7c | 3391 | return -EIO; |
6aa8b732 | 3392 | |
c68876fd | 3393 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
3394 | |
3395 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
3396 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 3397 | return -EIO; |
1c3d14fe YS |
3398 | |
3399 | #ifdef CONFIG_X86_64 | |
3400 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
3401 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 3402 | return -EIO; |
1c3d14fe YS |
3403 | #endif |
3404 | ||
3405 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
3406 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 3407 | return -EIO; |
1c3d14fe | 3408 | |
002c7f7c YS |
3409 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
3410 | vmcs_conf->order = get_order(vmcs_config.size); | |
3411 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 3412 | |
002c7f7c YS |
3413 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
3414 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 3415 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
3416 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
3417 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 3418 | |
110312c8 AK |
3419 | cpu_has_load_ia32_efer = |
3420 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3421 | VM_ENTRY_LOAD_IA32_EFER) | |
3422 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3423 | VM_EXIT_LOAD_IA32_EFER); | |
3424 | ||
8bf00a52 GN |
3425 | cpu_has_load_perf_global_ctrl = |
3426 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3427 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
3428 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3429 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
3430 | ||
3431 | /* | |
3432 | * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL | |
bb3541f1 | 3433 | * but due to errata below it can't be used. Workaround is to use |
8bf00a52 GN |
3434 | * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. |
3435 | * | |
3436 | * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] | |
3437 | * | |
3438 | * AAK155 (model 26) | |
3439 | * AAP115 (model 30) | |
3440 | * AAT100 (model 37) | |
3441 | * BC86,AAY89,BD102 (model 44) | |
3442 | * BA97 (model 46) | |
3443 | * | |
3444 | */ | |
3445 | if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) { | |
3446 | switch (boot_cpu_data.x86_model) { | |
3447 | case 26: | |
3448 | case 30: | |
3449 | case 37: | |
3450 | case 44: | |
3451 | case 46: | |
3452 | cpu_has_load_perf_global_ctrl = false; | |
3453 | printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " | |
3454 | "does not work properly. Using workaround\n"); | |
3455 | break; | |
3456 | default: | |
3457 | break; | |
3458 | } | |
3459 | } | |
3460 | ||
782511b0 | 3461 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
20300099 WL |
3462 | rdmsrl(MSR_IA32_XSS, host_xss); |
3463 | ||
1c3d14fe | 3464 | return 0; |
c68876fd | 3465 | } |
6aa8b732 AK |
3466 | |
3467 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
3468 | { | |
3469 | int node = cpu_to_node(cpu); | |
3470 | struct page *pages; | |
3471 | struct vmcs *vmcs; | |
3472 | ||
96db800f | 3473 | pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
3474 | if (!pages) |
3475 | return NULL; | |
3476 | vmcs = page_address(pages); | |
1c3d14fe YS |
3477 | memset(vmcs, 0, vmcs_config.size); |
3478 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
3479 | return vmcs; |
3480 | } | |
3481 | ||
3482 | static struct vmcs *alloc_vmcs(void) | |
3483 | { | |
d3b2c338 | 3484 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
3485 | } |
3486 | ||
3487 | static void free_vmcs(struct vmcs *vmcs) | |
3488 | { | |
1c3d14fe | 3489 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
3490 | } |
3491 | ||
d462b819 NHE |
3492 | /* |
3493 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
3494 | */ | |
3495 | static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
3496 | { | |
3497 | if (!loaded_vmcs->vmcs) | |
3498 | return; | |
3499 | loaded_vmcs_clear(loaded_vmcs); | |
3500 | free_vmcs(loaded_vmcs->vmcs); | |
3501 | loaded_vmcs->vmcs = NULL; | |
3502 | } | |
3503 | ||
39959588 | 3504 | static void free_kvm_area(void) |
6aa8b732 AK |
3505 | { |
3506 | int cpu; | |
3507 | ||
3230bb47 | 3508 | for_each_possible_cpu(cpu) { |
6aa8b732 | 3509 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
3510 | per_cpu(vmxarea, cpu) = NULL; |
3511 | } | |
6aa8b732 AK |
3512 | } |
3513 | ||
fe2b201b BD |
3514 | static void init_vmcs_shadow_fields(void) |
3515 | { | |
3516 | int i, j; | |
3517 | ||
3518 | /* No checks for read only fields yet */ | |
3519 | ||
3520 | for (i = j = 0; i < max_shadow_read_write_fields; i++) { | |
3521 | switch (shadow_read_write_fields[i]) { | |
3522 | case GUEST_BNDCFGS: | |
a87036ad | 3523 | if (!kvm_mpx_supported()) |
fe2b201b BD |
3524 | continue; |
3525 | break; | |
3526 | default: | |
3527 | break; | |
3528 | } | |
3529 | ||
3530 | if (j < i) | |
3531 | shadow_read_write_fields[j] = | |
3532 | shadow_read_write_fields[i]; | |
3533 | j++; | |
3534 | } | |
3535 | max_shadow_read_write_fields = j; | |
3536 | ||
3537 | /* shadowed fields guest access without vmexit */ | |
3538 | for (i = 0; i < max_shadow_read_write_fields; i++) { | |
3539 | clear_bit(shadow_read_write_fields[i], | |
3540 | vmx_vmwrite_bitmap); | |
3541 | clear_bit(shadow_read_write_fields[i], | |
3542 | vmx_vmread_bitmap); | |
3543 | } | |
3544 | for (i = 0; i < max_shadow_read_only_fields; i++) | |
3545 | clear_bit(shadow_read_only_fields[i], | |
3546 | vmx_vmread_bitmap); | |
3547 | } | |
3548 | ||
6aa8b732 AK |
3549 | static __init int alloc_kvm_area(void) |
3550 | { | |
3551 | int cpu; | |
3552 | ||
3230bb47 | 3553 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
3554 | struct vmcs *vmcs; |
3555 | ||
3556 | vmcs = alloc_vmcs_cpu(cpu); | |
3557 | if (!vmcs) { | |
3558 | free_kvm_area(); | |
3559 | return -ENOMEM; | |
3560 | } | |
3561 | ||
3562 | per_cpu(vmxarea, cpu) = vmcs; | |
3563 | } | |
3564 | return 0; | |
3565 | } | |
3566 | ||
14168786 GN |
3567 | static bool emulation_required(struct kvm_vcpu *vcpu) |
3568 | { | |
3569 | return emulate_invalid_guest_state && !guest_state_valid(vcpu); | |
3570 | } | |
3571 | ||
91b0aa2c | 3572 | static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, |
d99e4152 | 3573 | struct kvm_segment *save) |
6aa8b732 | 3574 | { |
d99e4152 GN |
3575 | if (!emulate_invalid_guest_state) { |
3576 | /* | |
3577 | * CS and SS RPL should be equal during guest entry according | |
3578 | * to VMX spec, but in reality it is not always so. Since vcpu | |
3579 | * is in the middle of the transition from real mode to | |
3580 | * protected mode it is safe to assume that RPL 0 is a good | |
3581 | * default value. | |
3582 | */ | |
3583 | if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) | |
b32a9918 NA |
3584 | save->selector &= ~SEGMENT_RPL_MASK; |
3585 | save->dpl = save->selector & SEGMENT_RPL_MASK; | |
d99e4152 | 3586 | save->s = 1; |
6aa8b732 | 3587 | } |
d99e4152 | 3588 | vmx_set_segment(vcpu, save, seg); |
6aa8b732 AK |
3589 | } |
3590 | ||
3591 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
3592 | { | |
3593 | unsigned long flags; | |
a89a8fb9 | 3594 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3595 | |
d99e4152 GN |
3596 | /* |
3597 | * Update real mode segment cache. It may be not up-to-date if sement | |
3598 | * register was written while vcpu was in a guest mode. | |
3599 | */ | |
3600 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3601 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3602 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3603 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
3604 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); | |
3605 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
3606 | ||
7ffd92c5 | 3607 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 3608 | |
2fb92db1 AK |
3609 | vmx_segment_cache_clear(vmx); |
3610 | ||
f5f7b2fe | 3611 | vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
6aa8b732 AK |
3612 | |
3613 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
3614 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
3615 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
3616 | vmcs_writel(GUEST_RFLAGS, flags); |
3617 | ||
66aee91a RR |
3618 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
3619 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
3620 | |
3621 | update_exception_bitmap(vcpu); | |
3622 | ||
91b0aa2c GN |
3623 | fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); |
3624 | fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); | |
3625 | fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
3626 | fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
3627 | fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
3628 | fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
6aa8b732 AK |
3629 | } |
3630 | ||
f5f7b2fe | 3631 | static void fix_rmode_seg(int seg, struct kvm_segment *save) |
6aa8b732 | 3632 | { |
772e0318 | 3633 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
d99e4152 GN |
3634 | struct kvm_segment var = *save; |
3635 | ||
3636 | var.dpl = 0x3; | |
3637 | if (seg == VCPU_SREG_CS) | |
3638 | var.type = 0x3; | |
3639 | ||
3640 | if (!emulate_invalid_guest_state) { | |
3641 | var.selector = var.base >> 4; | |
3642 | var.base = var.base & 0xffff0; | |
3643 | var.limit = 0xffff; | |
3644 | var.g = 0; | |
3645 | var.db = 0; | |
3646 | var.present = 1; | |
3647 | var.s = 1; | |
3648 | var.l = 0; | |
3649 | var.unusable = 0; | |
3650 | var.type = 0x3; | |
3651 | var.avl = 0; | |
3652 | if (save->base & 0xf) | |
3653 | printk_once(KERN_WARNING "kvm: segment base is not " | |
3654 | "paragraph aligned when entering " | |
3655 | "protected mode (seg=%d)", seg); | |
3656 | } | |
6aa8b732 | 3657 | |
d99e4152 GN |
3658 | vmcs_write16(sf->selector, var.selector); |
3659 | vmcs_write32(sf->base, var.base); | |
3660 | vmcs_write32(sf->limit, var.limit); | |
3661 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); | |
6aa8b732 AK |
3662 | } |
3663 | ||
3664 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
3665 | { | |
3666 | unsigned long flags; | |
a89a8fb9 | 3667 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3668 | |
f5f7b2fe AK |
3669 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
3670 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3671 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3672 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3673 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
c6ad1153 GN |
3674 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); |
3675 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
f5f7b2fe | 3676 | |
7ffd92c5 | 3677 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 3678 | |
776e58ea GN |
3679 | /* |
3680 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
4918c6ca | 3681 | * vcpu. Warn the user that an update is overdue. |
776e58ea | 3682 | */ |
4918c6ca | 3683 | if (!vcpu->kvm->arch.tss_addr) |
776e58ea GN |
3684 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " |
3685 | "called before entering vcpu\n"); | |
776e58ea | 3686 | |
2fb92db1 AK |
3687 | vmx_segment_cache_clear(vmx); |
3688 | ||
4918c6ca | 3689 | vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr); |
6aa8b732 | 3690 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
6aa8b732 AK |
3691 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
3692 | ||
3693 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 3694 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 3695 | |
053de044 | 3696 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
3697 | |
3698 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 3699 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
3700 | update_exception_bitmap(vcpu); |
3701 | ||
d99e4152 GN |
3702 | fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); |
3703 | fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); | |
3704 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
3705 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
3706 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
3707 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
b246dd5d | 3708 | |
8668a3c4 | 3709 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
3710 | } |
3711 | ||
401d10de AS |
3712 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
3713 | { | |
3714 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
3715 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
3716 | ||
3717 | if (!msr) | |
3718 | return; | |
401d10de | 3719 | |
44ea2b17 AK |
3720 | /* |
3721 | * Force kernel_gs_base reloading before EFER changes, as control | |
3722 | * of this msr depends on is_long_mode(). | |
3723 | */ | |
3724 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 3725 | vcpu->arch.efer = efer; |
401d10de | 3726 | if (efer & EFER_LMA) { |
2961e876 | 3727 | vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
3728 | msr->data = efer; |
3729 | } else { | |
2961e876 | 3730 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
3731 | |
3732 | msr->data = efer & ~EFER_LME; | |
3733 | } | |
3734 | setup_msrs(vmx); | |
3735 | } | |
3736 | ||
05b3e0c2 | 3737 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
3738 | |
3739 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
3740 | { | |
3741 | u32 guest_tr_ar; | |
3742 | ||
2fb92db1 AK |
3743 | vmx_segment_cache_clear(to_vmx(vcpu)); |
3744 | ||
6aa8b732 | 3745 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
4d283ec9 | 3746 | if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { |
bd80158a JK |
3747 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
3748 | __func__); | |
6aa8b732 | 3749 | vmcs_write32(GUEST_TR_AR_BYTES, |
4d283ec9 AL |
3750 | (guest_tr_ar & ~VMX_AR_TYPE_MASK) |
3751 | | VMX_AR_TYPE_BUSY_64_TSS); | |
6aa8b732 | 3752 | } |
da38f438 | 3753 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
3754 | } |
3755 | ||
3756 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
3757 | { | |
2961e876 | 3758 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
da38f438 | 3759 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
3760 | } |
3761 | ||
3762 | #endif | |
3763 | ||
dd5f5341 | 3764 | static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid) |
2384d2b3 | 3765 | { |
dd5f5341 | 3766 | vpid_sync_context(vpid); |
dd180b3e XG |
3767 | if (enable_ept) { |
3768 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3769 | return; | |
4e1096d2 | 3770 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); |
dd180b3e | 3771 | } |
2384d2b3 SY |
3772 | } |
3773 | ||
dd5f5341 WL |
3774 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
3775 | { | |
3776 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid); | |
3777 | } | |
3778 | ||
e8467fda AK |
3779 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
3780 | { | |
3781 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
3782 | ||
3783 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
3784 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
3785 | } | |
3786 | ||
aff48baa AK |
3787 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
3788 | { | |
3789 | if (enable_ept && is_paging(vcpu)) | |
3790 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
3791 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
3792 | } | |
3793 | ||
25c4c276 | 3794 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 3795 | { |
fc78f519 AK |
3796 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
3797 | ||
3798 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
3799 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
3800 | } |
3801 | ||
1439442c SY |
3802 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
3803 | { | |
d0d538b9 GN |
3804 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
3805 | ||
6de4f3ad AK |
3806 | if (!test_bit(VCPU_EXREG_PDPTR, |
3807 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
3808 | return; | |
3809 | ||
1439442c | 3810 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
3811 | vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); |
3812 | vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); | |
3813 | vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); | |
3814 | vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); | |
1439442c SY |
3815 | } |
3816 | } | |
3817 | ||
8f5d549f AK |
3818 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
3819 | { | |
d0d538b9 GN |
3820 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
3821 | ||
8f5d549f | 3822 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
3823 | mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
3824 | mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
3825 | mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
3826 | mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 3827 | } |
6de4f3ad AK |
3828 | |
3829 | __set_bit(VCPU_EXREG_PDPTR, | |
3830 | (unsigned long *)&vcpu->arch.regs_avail); | |
3831 | __set_bit(VCPU_EXREG_PDPTR, | |
3832 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
3833 | } |
3834 | ||
5e1746d6 | 3835 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1439442c SY |
3836 | |
3837 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
3838 | unsigned long cr0, | |
3839 | struct kvm_vcpu *vcpu) | |
3840 | { | |
5233dd51 MT |
3841 | if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
3842 | vmx_decache_cr3(vcpu); | |
1439442c SY |
3843 | if (!(cr0 & X86_CR0_PG)) { |
3844 | /* From paging/starting to nonpaging */ | |
3845 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 3846 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
3847 | (CPU_BASED_CR3_LOAD_EXITING | |
3848 | CPU_BASED_CR3_STORE_EXITING)); | |
3849 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 3850 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
3851 | } else if (!is_paging(vcpu)) { |
3852 | /* From nonpaging to paging */ | |
3853 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 3854 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
3855 | ~(CPU_BASED_CR3_LOAD_EXITING | |
3856 | CPU_BASED_CR3_STORE_EXITING)); | |
3857 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 3858 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 3859 | } |
95eb84a7 SY |
3860 | |
3861 | if (!(cr0 & X86_CR0_WP)) | |
3862 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
3863 | } |
3864 | ||
6aa8b732 AK |
3865 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
3866 | { | |
7ffd92c5 | 3867 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
3868 | unsigned long hw_cr0; |
3869 | ||
5037878e | 3870 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK); |
3a624e29 | 3871 | if (enable_unrestricted_guest) |
5037878e | 3872 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; |
218e763f | 3873 | else { |
5037878e | 3874 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; |
1439442c | 3875 | |
218e763f GN |
3876 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
3877 | enter_pmode(vcpu); | |
6aa8b732 | 3878 | |
218e763f GN |
3879 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
3880 | enter_rmode(vcpu); | |
3881 | } | |
6aa8b732 | 3882 | |
05b3e0c2 | 3883 | #ifdef CONFIG_X86_64 |
f6801dff | 3884 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 3885 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 3886 | enter_lmode(vcpu); |
707d92fa | 3887 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
3888 | exit_lmode(vcpu); |
3889 | } | |
3890 | #endif | |
3891 | ||
089d034e | 3892 | if (enable_ept) |
1439442c SY |
3893 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
3894 | ||
02daab21 | 3895 | if (!vcpu->fpu_active) |
81231c69 | 3896 | hw_cr0 |= X86_CR0_TS | X86_CR0_MP; |
02daab21 | 3897 | |
6aa8b732 | 3898 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 3899 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 3900 | vcpu->arch.cr0 = cr0; |
14168786 GN |
3901 | |
3902 | /* depends on vcpu->arch.cr0 to be set to a new value */ | |
3903 | vmx->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
3904 | } |
3905 | ||
1439442c SY |
3906 | static u64 construct_eptp(unsigned long root_hpa) |
3907 | { | |
3908 | u64 eptp; | |
3909 | ||
3910 | /* TODO write the value reading from MSR */ | |
3911 | eptp = VMX_EPT_DEFAULT_MT | | |
3912 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
b38f9934 XH |
3913 | if (enable_ept_ad_bits) |
3914 | eptp |= VMX_EPT_AD_ENABLE_BIT; | |
1439442c SY |
3915 | eptp |= (root_hpa & PAGE_MASK); |
3916 | ||
3917 | return eptp; | |
3918 | } | |
3919 | ||
6aa8b732 AK |
3920 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
3921 | { | |
1439442c SY |
3922 | unsigned long guest_cr3; |
3923 | u64 eptp; | |
3924 | ||
3925 | guest_cr3 = cr3; | |
089d034e | 3926 | if (enable_ept) { |
1439442c SY |
3927 | eptp = construct_eptp(cr3); |
3928 | vmcs_write64(EPT_POINTER, eptp); | |
59ab5a8f JK |
3929 | if (is_paging(vcpu) || is_guest_mode(vcpu)) |
3930 | guest_cr3 = kvm_read_cr3(vcpu); | |
3931 | else | |
3932 | guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr; | |
7c93be44 | 3933 | ept_load_pdptrs(vcpu); |
1439442c SY |
3934 | } |
3935 | ||
2384d2b3 | 3936 | vmx_flush_tlb(vcpu); |
1439442c | 3937 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
3938 | } |
3939 | ||
5e1746d6 | 3940 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 3941 | { |
085e68ee BS |
3942 | /* |
3943 | * Pass through host's Machine Check Enable value to hw_cr4, which | |
3944 | * is in force while we are in guest mode. Do not let guests control | |
3945 | * this bit, even if host CR4.MCE == 0. | |
3946 | */ | |
3947 | unsigned long hw_cr4 = | |
3948 | (cr4_read_shadow() & X86_CR4_MCE) | | |
3949 | (cr4 & ~X86_CR4_MCE) | | |
3950 | (to_vmx(vcpu)->rmode.vm86_active ? | |
3951 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1439442c | 3952 | |
5e1746d6 NHE |
3953 | if (cr4 & X86_CR4_VMXE) { |
3954 | /* | |
3955 | * To use VMXON (and later other VMX instructions), a guest | |
3956 | * must first be able to turn on cr4.VMXE (see handle_vmon()). | |
3957 | * So basically the check on whether to allow nested VMX | |
3958 | * is here. | |
3959 | */ | |
3960 | if (!nested_vmx_allowed(vcpu)) | |
3961 | return 1; | |
1a0d74e6 JK |
3962 | } |
3963 | if (to_vmx(vcpu)->nested.vmxon && | |
3964 | ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) | |
5e1746d6 NHE |
3965 | return 1; |
3966 | ||
ad312c7c | 3967 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
3968 | if (enable_ept) { |
3969 | if (!is_paging(vcpu)) { | |
3970 | hw_cr4 &= ~X86_CR4_PAE; | |
3971 | hw_cr4 |= X86_CR4_PSE; | |
3972 | } else if (!(cr4 & X86_CR4_PAE)) { | |
3973 | hw_cr4 &= ~X86_CR4_PAE; | |
3974 | } | |
3975 | } | |
1439442c | 3976 | |
656ec4a4 RK |
3977 | if (!enable_unrestricted_guest && !is_paging(vcpu)) |
3978 | /* | |
ddba2628 HH |
3979 | * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in |
3980 | * hardware. To emulate this behavior, SMEP/SMAP/PKU needs | |
3981 | * to be manually disabled when guest switches to non-paging | |
3982 | * mode. | |
3983 | * | |
3984 | * If !enable_unrestricted_guest, the CPU is always running | |
3985 | * with CR0.PG=1 and CR4 needs to be modified. | |
3986 | * If enable_unrestricted_guest, the CPU automatically | |
3987 | * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. | |
656ec4a4 | 3988 | */ |
ddba2628 | 3989 | hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); |
656ec4a4 | 3990 | |
1439442c SY |
3991 | vmcs_writel(CR4_READ_SHADOW, cr4); |
3992 | vmcs_writel(GUEST_CR4, hw_cr4); | |
5e1746d6 | 3993 | return 0; |
6aa8b732 AK |
3994 | } |
3995 | ||
6aa8b732 AK |
3996 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
3997 | struct kvm_segment *var, int seg) | |
3998 | { | |
a9179499 | 3999 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
4000 | u32 ar; |
4001 | ||
c6ad1153 | 4002 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
f5f7b2fe | 4003 | *var = vmx->rmode.segs[seg]; |
a9179499 | 4004 | if (seg == VCPU_SREG_TR |
2fb92db1 | 4005 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
f5f7b2fe | 4006 | return; |
1390a28b AK |
4007 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4008 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4009 | return; | |
a9179499 | 4010 | } |
2fb92db1 AK |
4011 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4012 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
4013 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4014 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
03617c18 | 4015 | var->unusable = (ar >> 16) & 1; |
6aa8b732 AK |
4016 | var->type = ar & 15; |
4017 | var->s = (ar >> 4) & 1; | |
4018 | var->dpl = (ar >> 5) & 3; | |
03617c18 GN |
4019 | /* |
4020 | * Some userspaces do not preserve unusable property. Since usable | |
4021 | * segment has to be present according to VMX spec we can use present | |
4022 | * property to amend userspace bug by making unusable segment always | |
4023 | * nonpresent. vmx_segment_access_rights() already marks nonpresent | |
4024 | * segment as unusable. | |
4025 | */ | |
4026 | var->present = !var->unusable; | |
6aa8b732 AK |
4027 | var->avl = (ar >> 12) & 1; |
4028 | var->l = (ar >> 13) & 1; | |
4029 | var->db = (ar >> 14) & 1; | |
4030 | var->g = (ar >> 15) & 1; | |
6aa8b732 AK |
4031 | } |
4032 | ||
a9179499 AK |
4033 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4034 | { | |
a9179499 AK |
4035 | struct kvm_segment s; |
4036 | ||
4037 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
4038 | vmx_get_segment(vcpu, &s, seg); | |
4039 | return s.base; | |
4040 | } | |
2fb92db1 | 4041 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
4042 | } |
4043 | ||
b09408d0 | 4044 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 4045 | { |
b09408d0 MT |
4046 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4047 | ||
ae9fedc7 | 4048 | if (unlikely(vmx->rmode.vm86_active)) |
2e4d2653 | 4049 | return 0; |
ae9fedc7 PB |
4050 | else { |
4051 | int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); | |
4d283ec9 | 4052 | return VMX_AR_DPL(ar); |
69c73028 | 4053 | } |
69c73028 AK |
4054 | } |
4055 | ||
653e3108 | 4056 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 4057 | { |
6aa8b732 AK |
4058 | u32 ar; |
4059 | ||
f0495f9b | 4060 | if (var->unusable || !var->present) |
6aa8b732 AK |
4061 | ar = 1 << 16; |
4062 | else { | |
4063 | ar = var->type & 15; | |
4064 | ar |= (var->s & 1) << 4; | |
4065 | ar |= (var->dpl & 3) << 5; | |
4066 | ar |= (var->present & 1) << 7; | |
4067 | ar |= (var->avl & 1) << 12; | |
4068 | ar |= (var->l & 1) << 13; | |
4069 | ar |= (var->db & 1) << 14; | |
4070 | ar |= (var->g & 1) << 15; | |
4071 | } | |
653e3108 AK |
4072 | |
4073 | return ar; | |
4074 | } | |
4075 | ||
4076 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
4077 | struct kvm_segment *var, int seg) | |
4078 | { | |
7ffd92c5 | 4079 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
772e0318 | 4080 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
653e3108 | 4081 | |
2fb92db1 AK |
4082 | vmx_segment_cache_clear(vmx); |
4083 | ||
1ecd50a9 GN |
4084 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
4085 | vmx->rmode.segs[seg] = *var; | |
4086 | if (seg == VCPU_SREG_TR) | |
4087 | vmcs_write16(sf->selector, var->selector); | |
4088 | else if (var->s) | |
4089 | fix_rmode_seg(seg, &vmx->rmode.segs[seg]); | |
d99e4152 | 4090 | goto out; |
653e3108 | 4091 | } |
1ecd50a9 | 4092 | |
653e3108 AK |
4093 | vmcs_writel(sf->base, var->base); |
4094 | vmcs_write32(sf->limit, var->limit); | |
4095 | vmcs_write16(sf->selector, var->selector); | |
3a624e29 NK |
4096 | |
4097 | /* | |
4098 | * Fix the "Accessed" bit in AR field of segment registers for older | |
4099 | * qemu binaries. | |
4100 | * IA32 arch specifies that at the time of processor reset the | |
4101 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
0fa06071 | 4102 | * is setting it to 0 in the userland code. This causes invalid guest |
3a624e29 NK |
4103 | * state vmexit when "unrestricted guest" mode is turned on. |
4104 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
4105 | * tree. Newer qemu binaries with that qemu fix would not need this | |
4106 | * kvm hack. | |
4107 | */ | |
4108 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
f924d66d | 4109 | var->type |= 0x1; /* Accessed */ |
3a624e29 | 4110 | |
f924d66d | 4111 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); |
d99e4152 GN |
4112 | |
4113 | out: | |
98eb2f8b | 4114 | vmx->emulation_required = emulation_required(vcpu); |
6aa8b732 AK |
4115 | } |
4116 | ||
6aa8b732 AK |
4117 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
4118 | { | |
2fb92db1 | 4119 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
4120 | |
4121 | *db = (ar >> 14) & 1; | |
4122 | *l = (ar >> 13) & 1; | |
4123 | } | |
4124 | ||
89a27f4d | 4125 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4126 | { |
89a27f4d GN |
4127 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
4128 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
4129 | } |
4130 | ||
89a27f4d | 4131 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4132 | { |
89a27f4d GN |
4133 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
4134 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
4135 | } |
4136 | ||
89a27f4d | 4137 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4138 | { |
89a27f4d GN |
4139 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
4140 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
4141 | } |
4142 | ||
89a27f4d | 4143 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4144 | { |
89a27f4d GN |
4145 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
4146 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
4147 | } |
4148 | ||
648dfaa7 MG |
4149 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
4150 | { | |
4151 | struct kvm_segment var; | |
4152 | u32 ar; | |
4153 | ||
4154 | vmx_get_segment(vcpu, &var, seg); | |
07f42f5f | 4155 | var.dpl = 0x3; |
0647f4aa GN |
4156 | if (seg == VCPU_SREG_CS) |
4157 | var.type = 0x3; | |
648dfaa7 MG |
4158 | ar = vmx_segment_access_rights(&var); |
4159 | ||
4160 | if (var.base != (var.selector << 4)) | |
4161 | return false; | |
89efbed0 | 4162 | if (var.limit != 0xffff) |
648dfaa7 | 4163 | return false; |
07f42f5f | 4164 | if (ar != 0xf3) |
648dfaa7 MG |
4165 | return false; |
4166 | ||
4167 | return true; | |
4168 | } | |
4169 | ||
4170 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
4171 | { | |
4172 | struct kvm_segment cs; | |
4173 | unsigned int cs_rpl; | |
4174 | ||
4175 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
b32a9918 | 4176 | cs_rpl = cs.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4177 | |
1872a3f4 AK |
4178 | if (cs.unusable) |
4179 | return false; | |
4d283ec9 | 4180 | if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) |
648dfaa7 MG |
4181 | return false; |
4182 | if (!cs.s) | |
4183 | return false; | |
4d283ec9 | 4184 | if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
4185 | if (cs.dpl > cs_rpl) |
4186 | return false; | |
1872a3f4 | 4187 | } else { |
648dfaa7 MG |
4188 | if (cs.dpl != cs_rpl) |
4189 | return false; | |
4190 | } | |
4191 | if (!cs.present) | |
4192 | return false; | |
4193 | ||
4194 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
4195 | return true; | |
4196 | } | |
4197 | ||
4198 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
4199 | { | |
4200 | struct kvm_segment ss; | |
4201 | unsigned int ss_rpl; | |
4202 | ||
4203 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
b32a9918 | 4204 | ss_rpl = ss.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4205 | |
1872a3f4 AK |
4206 | if (ss.unusable) |
4207 | return true; | |
4208 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
4209 | return false; |
4210 | if (!ss.s) | |
4211 | return false; | |
4212 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
4213 | return false; | |
4214 | if (!ss.present) | |
4215 | return false; | |
4216 | ||
4217 | return true; | |
4218 | } | |
4219 | ||
4220 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
4221 | { | |
4222 | struct kvm_segment var; | |
4223 | unsigned int rpl; | |
4224 | ||
4225 | vmx_get_segment(vcpu, &var, seg); | |
b32a9918 | 4226 | rpl = var.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4227 | |
1872a3f4 AK |
4228 | if (var.unusable) |
4229 | return true; | |
648dfaa7 MG |
4230 | if (!var.s) |
4231 | return false; | |
4232 | if (!var.present) | |
4233 | return false; | |
4d283ec9 | 4234 | if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { |
648dfaa7 MG |
4235 | if (var.dpl < rpl) /* DPL < RPL */ |
4236 | return false; | |
4237 | } | |
4238 | ||
4239 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
4240 | * rights flags | |
4241 | */ | |
4242 | return true; | |
4243 | } | |
4244 | ||
4245 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
4246 | { | |
4247 | struct kvm_segment tr; | |
4248 | ||
4249 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
4250 | ||
1872a3f4 AK |
4251 | if (tr.unusable) |
4252 | return false; | |
b32a9918 | 4253 | if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 | 4254 | return false; |
1872a3f4 | 4255 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
4256 | return false; |
4257 | if (!tr.present) | |
4258 | return false; | |
4259 | ||
4260 | return true; | |
4261 | } | |
4262 | ||
4263 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
4264 | { | |
4265 | struct kvm_segment ldtr; | |
4266 | ||
4267 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
4268 | ||
1872a3f4 AK |
4269 | if (ldtr.unusable) |
4270 | return true; | |
b32a9918 | 4271 | if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 MG |
4272 | return false; |
4273 | if (ldtr.type != 2) | |
4274 | return false; | |
4275 | if (!ldtr.present) | |
4276 | return false; | |
4277 | ||
4278 | return true; | |
4279 | } | |
4280 | ||
4281 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
4282 | { | |
4283 | struct kvm_segment cs, ss; | |
4284 | ||
4285 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
4286 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
4287 | ||
b32a9918 NA |
4288 | return ((cs.selector & SEGMENT_RPL_MASK) == |
4289 | (ss.selector & SEGMENT_RPL_MASK)); | |
648dfaa7 MG |
4290 | } |
4291 | ||
4292 | /* | |
4293 | * Check if guest state is valid. Returns true if valid, false if | |
4294 | * not. | |
4295 | * We assume that registers are always usable | |
4296 | */ | |
4297 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
4298 | { | |
c5e97c80 GN |
4299 | if (enable_unrestricted_guest) |
4300 | return true; | |
4301 | ||
648dfaa7 | 4302 | /* real mode guest state checks */ |
f13882d8 | 4303 | if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { |
648dfaa7 MG |
4304 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
4305 | return false; | |
4306 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
4307 | return false; | |
4308 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
4309 | return false; | |
4310 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
4311 | return false; | |
4312 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
4313 | return false; | |
4314 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
4315 | return false; | |
4316 | } else { | |
4317 | /* protected mode guest state checks */ | |
4318 | if (!cs_ss_rpl_check(vcpu)) | |
4319 | return false; | |
4320 | if (!code_segment_valid(vcpu)) | |
4321 | return false; | |
4322 | if (!stack_segment_valid(vcpu)) | |
4323 | return false; | |
4324 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
4325 | return false; | |
4326 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
4327 | return false; | |
4328 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
4329 | return false; | |
4330 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
4331 | return false; | |
4332 | if (!tr_valid(vcpu)) | |
4333 | return false; | |
4334 | if (!ldtr_valid(vcpu)) | |
4335 | return false; | |
4336 | } | |
4337 | /* TODO: | |
4338 | * - Add checks on RIP | |
4339 | * - Add checks on RFLAGS | |
4340 | */ | |
4341 | ||
4342 | return true; | |
4343 | } | |
4344 | ||
d77c26fc | 4345 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 4346 | { |
40dcaa9f | 4347 | gfn_t fn; |
195aefde | 4348 | u16 data = 0; |
1f755a82 | 4349 | int idx, r; |
6aa8b732 | 4350 | |
40dcaa9f | 4351 | idx = srcu_read_lock(&kvm->srcu); |
4918c6ca | 4352 | fn = kvm->arch.tss_addr >> PAGE_SHIFT; |
195aefde IE |
4353 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4354 | if (r < 0) | |
10589a46 | 4355 | goto out; |
195aefde | 4356 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
4357 | r = kvm_write_guest_page(kvm, fn++, &data, |
4358 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 4359 | if (r < 0) |
10589a46 | 4360 | goto out; |
195aefde IE |
4361 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
4362 | if (r < 0) | |
10589a46 | 4363 | goto out; |
195aefde IE |
4364 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4365 | if (r < 0) | |
10589a46 | 4366 | goto out; |
195aefde | 4367 | data = ~0; |
10589a46 MT |
4368 | r = kvm_write_guest_page(kvm, fn, &data, |
4369 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
4370 | sizeof(u8)); | |
10589a46 | 4371 | out: |
40dcaa9f | 4372 | srcu_read_unlock(&kvm->srcu, idx); |
1f755a82 | 4373 | return r; |
6aa8b732 AK |
4374 | } |
4375 | ||
b7ebfb05 SY |
4376 | static int init_rmode_identity_map(struct kvm *kvm) |
4377 | { | |
f51770ed | 4378 | int i, idx, r = 0; |
ba049e93 | 4379 | kvm_pfn_t identity_map_pfn; |
b7ebfb05 SY |
4380 | u32 tmp; |
4381 | ||
089d034e | 4382 | if (!enable_ept) |
f51770ed | 4383 | return 0; |
a255d479 TC |
4384 | |
4385 | /* Protect kvm->arch.ept_identity_pagetable_done. */ | |
4386 | mutex_lock(&kvm->slots_lock); | |
4387 | ||
f51770ed | 4388 | if (likely(kvm->arch.ept_identity_pagetable_done)) |
a255d479 | 4389 | goto out2; |
a255d479 | 4390 | |
b927a3ce | 4391 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
a255d479 TC |
4392 | |
4393 | r = alloc_identity_pagetable(kvm); | |
f51770ed | 4394 | if (r < 0) |
a255d479 TC |
4395 | goto out2; |
4396 | ||
40dcaa9f | 4397 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
4398 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
4399 | if (r < 0) | |
4400 | goto out; | |
4401 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
4402 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
4403 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
4404 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
4405 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
4406 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
4407 | if (r < 0) | |
4408 | goto out; | |
4409 | } | |
4410 | kvm->arch.ept_identity_pagetable_done = true; | |
f51770ed | 4411 | |
b7ebfb05 | 4412 | out: |
40dcaa9f | 4413 | srcu_read_unlock(&kvm->srcu, idx); |
a255d479 TC |
4414 | |
4415 | out2: | |
4416 | mutex_unlock(&kvm->slots_lock); | |
f51770ed | 4417 | return r; |
b7ebfb05 SY |
4418 | } |
4419 | ||
6aa8b732 AK |
4420 | static void seg_setup(int seg) |
4421 | { | |
772e0318 | 4422 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
3a624e29 | 4423 | unsigned int ar; |
6aa8b732 AK |
4424 | |
4425 | vmcs_write16(sf->selector, 0); | |
4426 | vmcs_writel(sf->base, 0); | |
4427 | vmcs_write32(sf->limit, 0xffff); | |
d54d07b2 GN |
4428 | ar = 0x93; |
4429 | if (seg == VCPU_SREG_CS) | |
4430 | ar |= 0x08; /* code segment */ | |
3a624e29 NK |
4431 | |
4432 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
4433 | } |
4434 | ||
f78e0e2e SY |
4435 | static int alloc_apic_access_page(struct kvm *kvm) |
4436 | { | |
4484141a | 4437 | struct page *page; |
f78e0e2e SY |
4438 | int r = 0; |
4439 | ||
79fac95e | 4440 | mutex_lock(&kvm->slots_lock); |
c24ae0dc | 4441 | if (kvm->arch.apic_access_page_done) |
f78e0e2e | 4442 | goto out; |
1d8007bd PB |
4443 | r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, |
4444 | APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); | |
f78e0e2e SY |
4445 | if (r) |
4446 | goto out; | |
72dc67a6 | 4447 | |
73a6d941 | 4448 | page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
4484141a XG |
4449 | if (is_error_page(page)) { |
4450 | r = -EFAULT; | |
4451 | goto out; | |
4452 | } | |
4453 | ||
c24ae0dc TC |
4454 | /* |
4455 | * Do not pin the page in memory, so that memory hot-unplug | |
4456 | * is able to migrate it. | |
4457 | */ | |
4458 | put_page(page); | |
4459 | kvm->arch.apic_access_page_done = true; | |
f78e0e2e | 4460 | out: |
79fac95e | 4461 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
4462 | return r; |
4463 | } | |
4464 | ||
b7ebfb05 SY |
4465 | static int alloc_identity_pagetable(struct kvm *kvm) |
4466 | { | |
a255d479 TC |
4467 | /* Called with kvm->slots_lock held. */ |
4468 | ||
b7ebfb05 SY |
4469 | int r = 0; |
4470 | ||
a255d479 TC |
4471 | BUG_ON(kvm->arch.ept_identity_pagetable_done); |
4472 | ||
1d8007bd PB |
4473 | r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, |
4474 | kvm->arch.ept_identity_map_addr, PAGE_SIZE); | |
b7ebfb05 | 4475 | |
b7ebfb05 SY |
4476 | return r; |
4477 | } | |
4478 | ||
991e7a0e | 4479 | static int allocate_vpid(void) |
2384d2b3 SY |
4480 | { |
4481 | int vpid; | |
4482 | ||
919818ab | 4483 | if (!enable_vpid) |
991e7a0e | 4484 | return 0; |
2384d2b3 SY |
4485 | spin_lock(&vmx_vpid_lock); |
4486 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
991e7a0e | 4487 | if (vpid < VMX_NR_VPIDS) |
2384d2b3 | 4488 | __set_bit(vpid, vmx_vpid_bitmap); |
991e7a0e WL |
4489 | else |
4490 | vpid = 0; | |
2384d2b3 | 4491 | spin_unlock(&vmx_vpid_lock); |
991e7a0e | 4492 | return vpid; |
2384d2b3 SY |
4493 | } |
4494 | ||
991e7a0e | 4495 | static void free_vpid(int vpid) |
cdbecfc3 | 4496 | { |
991e7a0e | 4497 | if (!enable_vpid || vpid == 0) |
cdbecfc3 LJ |
4498 | return; |
4499 | spin_lock(&vmx_vpid_lock); | |
991e7a0e | 4500 | __clear_bit(vpid, vmx_vpid_bitmap); |
cdbecfc3 LJ |
4501 | spin_unlock(&vmx_vpid_lock); |
4502 | } | |
4503 | ||
8d14695f YZ |
4504 | #define MSR_TYPE_R 1 |
4505 | #define MSR_TYPE_W 2 | |
4506 | static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, | |
4507 | u32 msr, int type) | |
25c5f225 | 4508 | { |
3e7c73e9 | 4509 | int f = sizeof(unsigned long); |
25c5f225 SY |
4510 | |
4511 | if (!cpu_has_vmx_msr_bitmap()) | |
4512 | return; | |
4513 | ||
4514 | /* | |
4515 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4516 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4517 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4518 | */ | |
25c5f225 | 4519 | if (msr <= 0x1fff) { |
8d14695f YZ |
4520 | if (type & MSR_TYPE_R) |
4521 | /* read-low */ | |
4522 | __clear_bit(msr, msr_bitmap + 0x000 / f); | |
4523 | ||
4524 | if (type & MSR_TYPE_W) | |
4525 | /* write-low */ | |
4526 | __clear_bit(msr, msr_bitmap + 0x800 / f); | |
4527 | ||
25c5f225 SY |
4528 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
4529 | msr &= 0x1fff; | |
8d14695f YZ |
4530 | if (type & MSR_TYPE_R) |
4531 | /* read-high */ | |
4532 | __clear_bit(msr, msr_bitmap + 0x400 / f); | |
4533 | ||
4534 | if (type & MSR_TYPE_W) | |
4535 | /* write-high */ | |
4536 | __clear_bit(msr, msr_bitmap + 0xc00 / f); | |
4537 | ||
4538 | } | |
4539 | } | |
4540 | ||
4541 | static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, | |
4542 | u32 msr, int type) | |
4543 | { | |
4544 | int f = sizeof(unsigned long); | |
4545 | ||
4546 | if (!cpu_has_vmx_msr_bitmap()) | |
4547 | return; | |
4548 | ||
4549 | /* | |
4550 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4551 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4552 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4553 | */ | |
4554 | if (msr <= 0x1fff) { | |
4555 | if (type & MSR_TYPE_R) | |
4556 | /* read-low */ | |
4557 | __set_bit(msr, msr_bitmap + 0x000 / f); | |
4558 | ||
4559 | if (type & MSR_TYPE_W) | |
4560 | /* write-low */ | |
4561 | __set_bit(msr, msr_bitmap + 0x800 / f); | |
4562 | ||
4563 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
4564 | msr &= 0x1fff; | |
4565 | if (type & MSR_TYPE_R) | |
4566 | /* read-high */ | |
4567 | __set_bit(msr, msr_bitmap + 0x400 / f); | |
4568 | ||
4569 | if (type & MSR_TYPE_W) | |
4570 | /* write-high */ | |
4571 | __set_bit(msr, msr_bitmap + 0xc00 / f); | |
4572 | ||
25c5f225 | 4573 | } |
25c5f225 SY |
4574 | } |
4575 | ||
f2b93280 WV |
4576 | /* |
4577 | * If a msr is allowed by L0, we should check whether it is allowed by L1. | |
4578 | * The corresponding bit will be cleared unless both of L0 and L1 allow it. | |
4579 | */ | |
4580 | static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1, | |
4581 | unsigned long *msr_bitmap_nested, | |
4582 | u32 msr, int type) | |
4583 | { | |
4584 | int f = sizeof(unsigned long); | |
4585 | ||
4586 | if (!cpu_has_vmx_msr_bitmap()) { | |
4587 | WARN_ON(1); | |
4588 | return; | |
4589 | } | |
4590 | ||
4591 | /* | |
4592 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4593 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4594 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4595 | */ | |
4596 | if (msr <= 0x1fff) { | |
4597 | if (type & MSR_TYPE_R && | |
4598 | !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) | |
4599 | /* read-low */ | |
4600 | __clear_bit(msr, msr_bitmap_nested + 0x000 / f); | |
4601 | ||
4602 | if (type & MSR_TYPE_W && | |
4603 | !test_bit(msr, msr_bitmap_l1 + 0x800 / f)) | |
4604 | /* write-low */ | |
4605 | __clear_bit(msr, msr_bitmap_nested + 0x800 / f); | |
4606 | ||
4607 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
4608 | msr &= 0x1fff; | |
4609 | if (type & MSR_TYPE_R && | |
4610 | !test_bit(msr, msr_bitmap_l1 + 0x400 / f)) | |
4611 | /* read-high */ | |
4612 | __clear_bit(msr, msr_bitmap_nested + 0x400 / f); | |
4613 | ||
4614 | if (type & MSR_TYPE_W && | |
4615 | !test_bit(msr, msr_bitmap_l1 + 0xc00 / f)) | |
4616 | /* write-high */ | |
4617 | __clear_bit(msr, msr_bitmap_nested + 0xc00 / f); | |
4618 | ||
4619 | } | |
4620 | } | |
4621 | ||
5897297b AK |
4622 | static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) |
4623 | { | |
4624 | if (!longmode_only) | |
8d14695f YZ |
4625 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, |
4626 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
4627 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, | |
4628 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
4629 | } | |
4630 | ||
4631 | static void vmx_enable_intercept_msr_read_x2apic(u32 msr) | |
4632 | { | |
4633 | __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, | |
4634 | msr, MSR_TYPE_R); | |
4635 | __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, | |
4636 | msr, MSR_TYPE_R); | |
4637 | } | |
4638 | ||
4639 | static void vmx_disable_intercept_msr_read_x2apic(u32 msr) | |
4640 | { | |
4641 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, | |
4642 | msr, MSR_TYPE_R); | |
4643 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, | |
4644 | msr, MSR_TYPE_R); | |
4645 | } | |
4646 | ||
4647 | static void vmx_disable_intercept_msr_write_x2apic(u32 msr) | |
4648 | { | |
4649 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, | |
4650 | msr, MSR_TYPE_W); | |
4651 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, | |
4652 | msr, MSR_TYPE_W); | |
5897297b AK |
4653 | } |
4654 | ||
d62caabb | 4655 | static bool vmx_get_enable_apicv(void) |
d50ab6c1 | 4656 | { |
d62caabb | 4657 | return enable_apicv; |
d50ab6c1 PB |
4658 | } |
4659 | ||
705699a1 WV |
4660 | static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu) |
4661 | { | |
4662 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4663 | int max_irr; | |
4664 | void *vapic_page; | |
4665 | u16 status; | |
4666 | ||
4667 | if (vmx->nested.pi_desc && | |
4668 | vmx->nested.pi_pending) { | |
4669 | vmx->nested.pi_pending = false; | |
4670 | if (!pi_test_and_clear_on(vmx->nested.pi_desc)) | |
4671 | return 0; | |
4672 | ||
4673 | max_irr = find_last_bit( | |
4674 | (unsigned long *)vmx->nested.pi_desc->pir, 256); | |
4675 | ||
4676 | if (max_irr == 256) | |
4677 | return 0; | |
4678 | ||
4679 | vapic_page = kmap(vmx->nested.virtual_apic_page); | |
4680 | if (!vapic_page) { | |
4681 | WARN_ON(1); | |
4682 | return -ENOMEM; | |
4683 | } | |
4684 | __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page); | |
4685 | kunmap(vmx->nested.virtual_apic_page); | |
4686 | ||
4687 | status = vmcs_read16(GUEST_INTR_STATUS); | |
4688 | if ((u8)max_irr > ((u8)status & 0xff)) { | |
4689 | status &= ~0xff; | |
4690 | status |= (u8)max_irr; | |
4691 | vmcs_write16(GUEST_INTR_STATUS, status); | |
4692 | } | |
4693 | } | |
4694 | return 0; | |
4695 | } | |
4696 | ||
21bc8dc5 RK |
4697 | static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu) |
4698 | { | |
4699 | #ifdef CONFIG_SMP | |
4700 | if (vcpu->mode == IN_GUEST_MODE) { | |
28b835d6 FW |
4701 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4702 | ||
4703 | /* | |
4704 | * Currently, we don't support urgent interrupt, | |
4705 | * all interrupts are recognized as non-urgent | |
4706 | * interrupt, so we cannot post interrupts when | |
4707 | * 'SN' is set. | |
4708 | * | |
4709 | * If the vcpu is in guest mode, it means it is | |
4710 | * running instead of being scheduled out and | |
4711 | * waiting in the run queue, and that's the only | |
4712 | * case when 'SN' is set currently, warning if | |
4713 | * 'SN' is set. | |
4714 | */ | |
4715 | WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc)); | |
4716 | ||
21bc8dc5 RK |
4717 | apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), |
4718 | POSTED_INTR_VECTOR); | |
4719 | return true; | |
4720 | } | |
4721 | #endif | |
4722 | return false; | |
4723 | } | |
4724 | ||
705699a1 WV |
4725 | static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, |
4726 | int vector) | |
4727 | { | |
4728 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4729 | ||
4730 | if (is_guest_mode(vcpu) && | |
4731 | vector == vmx->nested.posted_intr_nv) { | |
4732 | /* the PIR and ON have been set by L1. */ | |
21bc8dc5 | 4733 | kvm_vcpu_trigger_posted_interrupt(vcpu); |
705699a1 WV |
4734 | /* |
4735 | * If a posted intr is not recognized by hardware, | |
4736 | * we will accomplish it in the next vmentry. | |
4737 | */ | |
4738 | vmx->nested.pi_pending = true; | |
4739 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4740 | return 0; | |
4741 | } | |
4742 | return -1; | |
4743 | } | |
a20ed54d YZ |
4744 | /* |
4745 | * Send interrupt to vcpu via posted interrupt way. | |
4746 | * 1. If target vcpu is running(non-root mode), send posted interrupt | |
4747 | * notification to vcpu and hardware will sync PIR to vIRR atomically. | |
4748 | * 2. If target vcpu isn't running(root mode), kick it to pick up the | |
4749 | * interrupt from PIR in next vmentry. | |
4750 | */ | |
4751 | static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) | |
4752 | { | |
4753 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4754 | int r; | |
4755 | ||
705699a1 WV |
4756 | r = vmx_deliver_nested_posted_interrupt(vcpu, vector); |
4757 | if (!r) | |
4758 | return; | |
4759 | ||
a20ed54d YZ |
4760 | if (pi_test_and_set_pir(vector, &vmx->pi_desc)) |
4761 | return; | |
4762 | ||
4763 | r = pi_test_and_set_on(&vmx->pi_desc); | |
4764 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
21bc8dc5 | 4765 | if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu)) |
a20ed54d YZ |
4766 | kvm_vcpu_kick(vcpu); |
4767 | } | |
4768 | ||
4769 | static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) | |
4770 | { | |
4771 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4772 | ||
4773 | if (!pi_test_and_clear_on(&vmx->pi_desc)) | |
4774 | return; | |
4775 | ||
4776 | kvm_apic_update_irr(vcpu, vmx->pi_desc.pir); | |
4777 | } | |
4778 | ||
a3a8ff8e NHE |
4779 | /* |
4780 | * Set up the vmcs's constant host-state fields, i.e., host-state fields that | |
4781 | * will not change in the lifetime of the guest. | |
4782 | * Note that host-state that does change is set elsewhere. E.g., host-state | |
4783 | * that is set differently for each CPU is set in vmx_vcpu_load(), not here. | |
4784 | */ | |
a547c6db | 4785 | static void vmx_set_constant_host_state(struct vcpu_vmx *vmx) |
a3a8ff8e NHE |
4786 | { |
4787 | u32 low32, high32; | |
4788 | unsigned long tmpl; | |
4789 | struct desc_ptr dt; | |
d974baa3 | 4790 | unsigned long cr4; |
a3a8ff8e | 4791 | |
b1a74bf8 | 4792 | vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */ |
a3a8ff8e NHE |
4793 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ |
4794 | ||
d974baa3 | 4795 | /* Save the most likely value for this task's CR4 in the VMCS. */ |
1e02ce4c | 4796 | cr4 = cr4_read_shadow(); |
d974baa3 AL |
4797 | vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ |
4798 | vmx->host_state.vmcs_host_cr4 = cr4; | |
4799 | ||
a3a8ff8e | 4800 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ |
b2da15ac AK |
4801 | #ifdef CONFIG_X86_64 |
4802 | /* | |
4803 | * Load null selectors, so we can avoid reloading them in | |
4804 | * __vmx_load_host_state(), in case userspace uses the null selectors | |
4805 | * too (the expected case). | |
4806 | */ | |
4807 | vmcs_write16(HOST_DS_SELECTOR, 0); | |
4808 | vmcs_write16(HOST_ES_SELECTOR, 0); | |
4809 | #else | |
a3a8ff8e NHE |
4810 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
4811 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
b2da15ac | 4812 | #endif |
a3a8ff8e NHE |
4813 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
4814 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
4815 | ||
4816 | native_store_idt(&dt); | |
4817 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ | |
a547c6db | 4818 | vmx->host_idt_base = dt.address; |
a3a8ff8e | 4819 | |
83287ea4 | 4820 | vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */ |
a3a8ff8e NHE |
4821 | |
4822 | rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); | |
4823 | vmcs_write32(HOST_IA32_SYSENTER_CS, low32); | |
4824 | rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); | |
4825 | vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ | |
4826 | ||
4827 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { | |
4828 | rdmsr(MSR_IA32_CR_PAT, low32, high32); | |
4829 | vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); | |
4830 | } | |
4831 | } | |
4832 | ||
bf8179a0 NHE |
4833 | static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) |
4834 | { | |
4835 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; | |
4836 | if (enable_ept) | |
4837 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
fe3ef05c NHE |
4838 | if (is_guest_mode(&vmx->vcpu)) |
4839 | vmx->vcpu.arch.cr4_guest_owned_bits &= | |
4840 | ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; | |
bf8179a0 NHE |
4841 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
4842 | } | |
4843 | ||
01e439be YZ |
4844 | static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) |
4845 | { | |
4846 | u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; | |
4847 | ||
d62caabb | 4848 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
01e439be | 4849 | pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; |
64672c95 YJ |
4850 | /* Enable the preemption timer dynamically */ |
4851 | pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
4852 | return pin_based_exec_ctrl; |
4853 | } | |
4854 | ||
d62caabb AS |
4855 | static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
4856 | { | |
4857 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4858 | ||
4859 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); | |
3ce424e4 RK |
4860 | if (cpu_has_secondary_exec_ctrls()) { |
4861 | if (kvm_vcpu_apicv_active(vcpu)) | |
4862 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
4863 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
4864 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
4865 | else | |
4866 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
4867 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
4868 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
4869 | } | |
4870 | ||
4871 | if (cpu_has_vmx_msr_bitmap()) | |
4872 | vmx_set_msr_bitmap(vcpu); | |
d62caabb AS |
4873 | } |
4874 | ||
bf8179a0 NHE |
4875 | static u32 vmx_exec_control(struct vcpu_vmx *vmx) |
4876 | { | |
4877 | u32 exec_control = vmcs_config.cpu_based_exec_ctrl; | |
d16c293e PB |
4878 | |
4879 | if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) | |
4880 | exec_control &= ~CPU_BASED_MOV_DR_EXITING; | |
4881 | ||
35754c98 | 4882 | if (!cpu_need_tpr_shadow(&vmx->vcpu)) { |
bf8179a0 NHE |
4883 | exec_control &= ~CPU_BASED_TPR_SHADOW; |
4884 | #ifdef CONFIG_X86_64 | |
4885 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
4886 | CPU_BASED_CR8_LOAD_EXITING; | |
4887 | #endif | |
4888 | } | |
4889 | if (!enable_ept) | |
4890 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
4891 | CPU_BASED_CR3_LOAD_EXITING | | |
4892 | CPU_BASED_INVLPG_EXITING; | |
4893 | return exec_control; | |
4894 | } | |
4895 | ||
4896 | static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx) | |
4897 | { | |
4898 | u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
35754c98 | 4899 | if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu)) |
bf8179a0 NHE |
4900 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
4901 | if (vmx->vpid == 0) | |
4902 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
4903 | if (!enable_ept) { | |
4904 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
4905 | enable_unrestricted_guest = 0; | |
ad756a16 MJ |
4906 | /* Enable INVPCID for non-ept guests may cause performance regression. */ |
4907 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
bf8179a0 NHE |
4908 | } |
4909 | if (!enable_unrestricted_guest) | |
4910 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
4911 | if (!ple_gap) | |
4912 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
d62caabb | 4913 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
c7c9c56c YZ |
4914 | exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | |
4915 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
8d14695f | 4916 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; |
abc4fc58 AG |
4917 | /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD |
4918 | (handle_vmptrld). | |
4919 | We can NOT enable shadow_vmcs here because we don't have yet | |
4920 | a current VMCS12 | |
4921 | */ | |
4922 | exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
a3eaa864 KH |
4923 | |
4924 | if (!enable_pml) | |
4925 | exec_control &= ~SECONDARY_EXEC_ENABLE_PML; | |
843e4330 | 4926 | |
8b3e34e4 XG |
4927 | /* Currently, we allow L1 guest to directly run pcommit instruction. */ |
4928 | exec_control &= ~SECONDARY_EXEC_PCOMMIT; | |
4929 | ||
bf8179a0 NHE |
4930 | return exec_control; |
4931 | } | |
4932 | ||
ce88decf XG |
4933 | static void ept_set_mmio_spte_mask(void) |
4934 | { | |
4935 | /* | |
4936 | * EPT Misconfigurations can be generated if the value of bits 2:0 | |
4937 | * of an EPT paging-structure entry is 110b (write/execute). | |
885032b9 | 4938 | * Also, magic bits (0x3ull << 62) is set to quickly identify mmio |
ce88decf XG |
4939 | * spte. |
4940 | */ | |
885032b9 | 4941 | kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull); |
ce88decf XG |
4942 | } |
4943 | ||
f53cd63c | 4944 | #define VMX_XSS_EXIT_BITMAP 0 |
6aa8b732 AK |
4945 | /* |
4946 | * Sets up the vmcs for emulated real mode. | |
4947 | */ | |
8b9cf98c | 4948 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 4949 | { |
2e4ce7f5 | 4950 | #ifdef CONFIG_X86_64 |
6aa8b732 | 4951 | unsigned long a; |
2e4ce7f5 | 4952 | #endif |
6aa8b732 | 4953 | int i; |
6aa8b732 | 4954 | |
6aa8b732 | 4955 | /* I/O */ |
3e7c73e9 AK |
4956 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
4957 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 4958 | |
4607c2d7 AG |
4959 | if (enable_shadow_vmcs) { |
4960 | vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); | |
4961 | vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); | |
4962 | } | |
25c5f225 | 4963 | if (cpu_has_vmx_msr_bitmap()) |
5897297b | 4964 | vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy)); |
25c5f225 | 4965 | |
6aa8b732 AK |
4966 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
4967 | ||
6aa8b732 | 4968 | /* Control */ |
01e439be | 4969 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); |
64672c95 | 4970 | vmx->hv_deadline_tsc = -1; |
6e5d865c | 4971 | |
bf8179a0 | 4972 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx)); |
6aa8b732 | 4973 | |
8b3e34e4 | 4974 | if (cpu_has_secondary_exec_ctrls()) |
bf8179a0 NHE |
4975 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, |
4976 | vmx_secondary_exec_control(vmx)); | |
f78e0e2e | 4977 | |
d62caabb | 4978 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) { |
c7c9c56c YZ |
4979 | vmcs_write64(EOI_EXIT_BITMAP0, 0); |
4980 | vmcs_write64(EOI_EXIT_BITMAP1, 0); | |
4981 | vmcs_write64(EOI_EXIT_BITMAP2, 0); | |
4982 | vmcs_write64(EOI_EXIT_BITMAP3, 0); | |
4983 | ||
4984 | vmcs_write16(GUEST_INTR_STATUS, 0); | |
01e439be | 4985 | |
0bcf261c | 4986 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
01e439be | 4987 | vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); |
c7c9c56c YZ |
4988 | } |
4989 | ||
4b8d54f9 ZE |
4990 | if (ple_gap) { |
4991 | vmcs_write32(PLE_GAP, ple_gap); | |
a7653ecd RK |
4992 | vmx->ple_window = ple_window; |
4993 | vmx->ple_window_dirty = true; | |
4b8d54f9 ZE |
4994 | } |
4995 | ||
c3707958 XG |
4996 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
4997 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
6aa8b732 AK |
4998 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
4999 | ||
9581d442 AK |
5000 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
5001 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
a547c6db | 5002 | vmx_set_constant_host_state(vmx); |
05b3e0c2 | 5003 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
5004 | rdmsrl(MSR_FS_BASE, a); |
5005 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
5006 | rdmsrl(MSR_GS_BASE, a); | |
5007 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
5008 | #else | |
5009 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
5010 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
5011 | #endif | |
5012 | ||
2cc51560 ED |
5013 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
5014 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
61d2ef2c | 5015 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); |
2cc51560 | 5016 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
61d2ef2c | 5017 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); |
6aa8b732 | 5018 | |
74545705 RK |
5019 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) |
5020 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); | |
468d472f | 5021 | |
03916db9 | 5022 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { |
6aa8b732 AK |
5023 | u32 index = vmx_msr_index[i]; |
5024 | u32 data_low, data_high; | |
a2fa3e9f | 5025 | int j = vmx->nmsrs; |
6aa8b732 AK |
5026 | |
5027 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
5028 | continue; | |
432bd6cb AK |
5029 | if (wrmsr_safe(index, data_low, data_high) < 0) |
5030 | continue; | |
26bb0981 AK |
5031 | vmx->guest_msrs[j].index = i; |
5032 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 5033 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 5034 | ++vmx->nmsrs; |
6aa8b732 | 5035 | } |
6aa8b732 | 5036 | |
2961e876 GN |
5037 | |
5038 | vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl); | |
6aa8b732 AK |
5039 | |
5040 | /* 22.2.1, 20.8.1 */ | |
2961e876 | 5041 | vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl); |
1c3d14fe | 5042 | |
e00c8cf2 | 5043 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
bf8179a0 | 5044 | set_cr4_guest_host_mask(vmx); |
e00c8cf2 | 5045 | |
f53cd63c WL |
5046 | if (vmx_xsaves_supported()) |
5047 | vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); | |
5048 | ||
e00c8cf2 AK |
5049 | return 0; |
5050 | } | |
5051 | ||
d28bc9dd | 5052 | static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e00c8cf2 AK |
5053 | { |
5054 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
58cb628d | 5055 | struct msr_data apic_base_msr; |
d28bc9dd | 5056 | u64 cr0; |
e00c8cf2 | 5057 | |
7ffd92c5 | 5058 | vmx->rmode.vm86_active = 0; |
e00c8cf2 | 5059 | |
3b86cd99 JK |
5060 | vmx->soft_vnmi_blocked = 0; |
5061 | ||
ad312c7c | 5062 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
d28bc9dd NA |
5063 | kvm_set_cr8(vcpu, 0); |
5064 | ||
5065 | if (!init_event) { | |
5066 | apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | | |
5067 | MSR_IA32_APICBASE_ENABLE; | |
5068 | if (kvm_vcpu_is_reset_bsp(vcpu)) | |
5069 | apic_base_msr.data |= MSR_IA32_APICBASE_BSP; | |
5070 | apic_base_msr.host_initiated = true; | |
5071 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
5072 | } | |
e00c8cf2 | 5073 | |
2fb92db1 AK |
5074 | vmx_segment_cache_clear(vmx); |
5075 | ||
5706be0d | 5076 | seg_setup(VCPU_SREG_CS); |
66450a21 | 5077 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
f3531054 | 5078 | vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); |
e00c8cf2 AK |
5079 | |
5080 | seg_setup(VCPU_SREG_DS); | |
5081 | seg_setup(VCPU_SREG_ES); | |
5082 | seg_setup(VCPU_SREG_FS); | |
5083 | seg_setup(VCPU_SREG_GS); | |
5084 | seg_setup(VCPU_SREG_SS); | |
5085 | ||
5086 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
5087 | vmcs_writel(GUEST_TR_BASE, 0); | |
5088 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
5089 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
5090 | ||
5091 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
5092 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
5093 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
5094 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
5095 | ||
d28bc9dd NA |
5096 | if (!init_event) { |
5097 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
5098 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
5099 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
5100 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
5101 | } | |
e00c8cf2 AK |
5102 | |
5103 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
66450a21 | 5104 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 5105 | |
e00c8cf2 AK |
5106 | vmcs_writel(GUEST_GDTR_BASE, 0); |
5107 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
5108 | ||
5109 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
5110 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
5111 | ||
443381a8 | 5112 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 | 5113 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
f3531054 | 5114 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); |
e00c8cf2 | 5115 | |
e00c8cf2 AK |
5116 | setup_msrs(vmx); |
5117 | ||
6aa8b732 AK |
5118 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
5119 | ||
d28bc9dd | 5120 | if (cpu_has_vmx_tpr_shadow() && !init_event) { |
f78e0e2e | 5121 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); |
35754c98 | 5122 | if (cpu_need_tpr_shadow(vcpu)) |
f78e0e2e | 5123 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, |
d28bc9dd | 5124 | __pa(vcpu->arch.apic->regs)); |
f78e0e2e SY |
5125 | vmcs_write32(TPR_THRESHOLD, 0); |
5126 | } | |
5127 | ||
a73896cb | 5128 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
6aa8b732 | 5129 | |
d62caabb | 5130 | if (kvm_vcpu_apicv_active(vcpu)) |
01e439be YZ |
5131 | memset(&vmx->pi_desc, 0, sizeof(struct pi_desc)); |
5132 | ||
2384d2b3 SY |
5133 | if (vmx->vpid != 0) |
5134 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
5135 | ||
d28bc9dd | 5136 | cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
d28bc9dd | 5137 | vmx->vcpu.arch.cr0 = cr0; |
f2463247 | 5138 | vmx_set_cr0(vcpu, cr0); /* enter rmode */ |
d28bc9dd | 5139 | vmx_set_cr4(vcpu, 0); |
5690891b | 5140 | vmx_set_efer(vcpu, 0); |
d28bc9dd NA |
5141 | vmx_fpu_activate(vcpu); |
5142 | update_exception_bitmap(vcpu); | |
6aa8b732 | 5143 | |
dd5f5341 | 5144 | vpid_sync_context(vmx->vpid); |
6aa8b732 AK |
5145 | } |
5146 | ||
b6f1250e NHE |
5147 | /* |
5148 | * In nested virtualization, check if L1 asked to exit on external interrupts. | |
5149 | * For most existing hypervisors, this will always return true. | |
5150 | */ | |
5151 | static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) | |
5152 | { | |
5153 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5154 | PIN_BASED_EXT_INTR_MASK; | |
5155 | } | |
5156 | ||
77b0f5d6 BD |
5157 | /* |
5158 | * In nested virtualization, check if L1 has set | |
5159 | * VM_EXIT_ACK_INTR_ON_EXIT | |
5160 | */ | |
5161 | static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) | |
5162 | { | |
5163 | return get_vmcs12(vcpu)->vm_exit_controls & | |
5164 | VM_EXIT_ACK_INTR_ON_EXIT; | |
5165 | } | |
5166 | ||
ea8ceb83 JK |
5167 | static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) |
5168 | { | |
5169 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5170 | PIN_BASED_NMI_EXITING; | |
5171 | } | |
5172 | ||
c9a7953f | 5173 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3b86cd99 JK |
5174 | { |
5175 | u32 cpu_based_vm_exec_control; | |
730dca42 | 5176 | |
3b86cd99 JK |
5177 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); |
5178 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
5179 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
5180 | } | |
5181 | ||
c9a7953f | 5182 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
3b86cd99 JK |
5183 | { |
5184 | u32 cpu_based_vm_exec_control; | |
5185 | ||
c9a7953f JK |
5186 | if (!cpu_has_virtual_nmis() || |
5187 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { | |
5188 | enable_irq_window(vcpu); | |
5189 | return; | |
5190 | } | |
3b86cd99 JK |
5191 | |
5192 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
5193 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
5194 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
5195 | } | |
5196 | ||
66fd3f7f | 5197 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 5198 | { |
9c8cba37 | 5199 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
5200 | uint32_t intr; |
5201 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 5202 | |
229456fc | 5203 | trace_kvm_inj_virq(irq); |
2714d1d3 | 5204 | |
fa89a817 | 5205 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 5206 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
5207 | int inc_eip = 0; |
5208 | if (vcpu->arch.interrupt.soft) | |
5209 | inc_eip = vcpu->arch.event_exit_inst_len; | |
5210 | if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) | |
a92601bb | 5211 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
85f455f7 ED |
5212 | return; |
5213 | } | |
66fd3f7f GN |
5214 | intr = irq | INTR_INFO_VALID_MASK; |
5215 | if (vcpu->arch.interrupt.soft) { | |
5216 | intr |= INTR_TYPE_SOFT_INTR; | |
5217 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
5218 | vmx->vcpu.arch.event_exit_inst_len); | |
5219 | } else | |
5220 | intr |= INTR_TYPE_EXT_INTR; | |
5221 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
85f455f7 ED |
5222 | } |
5223 | ||
f08864b4 SY |
5224 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
5225 | { | |
66a5a347 JK |
5226 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5227 | ||
0b6ac343 NHE |
5228 | if (is_guest_mode(vcpu)) |
5229 | return; | |
5230 | ||
3b86cd99 JK |
5231 | if (!cpu_has_virtual_nmis()) { |
5232 | /* | |
5233 | * Tracking the NMI-blocked state in software is built upon | |
5234 | * finding the next open IRQ window. This, in turn, depends on | |
5235 | * well-behaving guests: They have to keep IRQs disabled at | |
5236 | * least as long as the NMI handler runs. Otherwise we may | |
5237 | * cause NMI nesting, maybe breaking the guest. But as this is | |
5238 | * highly unlikely, we can live with the residual risk. | |
5239 | */ | |
5240 | vmx->soft_vnmi_blocked = 1; | |
5241 | vmx->vnmi_blocked_time = 0; | |
5242 | } | |
5243 | ||
487b391d | 5244 | ++vcpu->stat.nmi_injections; |
9d58b931 | 5245 | vmx->nmi_known_unmasked = false; |
7ffd92c5 | 5246 | if (vmx->rmode.vm86_active) { |
71f9833b | 5247 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) |
a92601bb | 5248 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
66a5a347 JK |
5249 | return; |
5250 | } | |
f08864b4 SY |
5251 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
5252 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
5253 | } |
5254 | ||
3cfc3092 JK |
5255 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
5256 | { | |
5257 | if (!cpu_has_virtual_nmis()) | |
5258 | return to_vmx(vcpu)->soft_vnmi_blocked; | |
9d58b931 AK |
5259 | if (to_vmx(vcpu)->nmi_known_unmasked) |
5260 | return false; | |
c332c83a | 5261 | return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
3cfc3092 JK |
5262 | } |
5263 | ||
5264 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
5265 | { | |
5266 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5267 | ||
5268 | if (!cpu_has_virtual_nmis()) { | |
5269 | if (vmx->soft_vnmi_blocked != masked) { | |
5270 | vmx->soft_vnmi_blocked = masked; | |
5271 | vmx->vnmi_blocked_time = 0; | |
5272 | } | |
5273 | } else { | |
9d58b931 | 5274 | vmx->nmi_known_unmasked = !masked; |
3cfc3092 JK |
5275 | if (masked) |
5276 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5277 | GUEST_INTR_STATE_NMI); | |
5278 | else | |
5279 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5280 | GUEST_INTR_STATE_NMI); | |
5281 | } | |
5282 | } | |
5283 | ||
2505dc9f JK |
5284 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
5285 | { | |
b6b8a145 JK |
5286 | if (to_vmx(vcpu)->nested.nested_run_pending) |
5287 | return 0; | |
ea8ceb83 | 5288 | |
2505dc9f JK |
5289 | if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked) |
5290 | return 0; | |
5291 | ||
5292 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & | |
5293 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | |
5294 | | GUEST_INTR_STATE_NMI)); | |
5295 | } | |
5296 | ||
78646121 GN |
5297 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
5298 | { | |
b6b8a145 JK |
5299 | return (!to_vmx(vcpu)->nested.nested_run_pending && |
5300 | vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
c4282df9 GN |
5301 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
5302 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
5303 | } |
5304 | ||
cbc94022 IE |
5305 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
5306 | { | |
5307 | int ret; | |
cbc94022 | 5308 | |
1d8007bd PB |
5309 | ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, |
5310 | PAGE_SIZE * 3); | |
cbc94022 IE |
5311 | if (ret) |
5312 | return ret; | |
bfc6d222 | 5313 | kvm->arch.tss_addr = addr; |
1f755a82 | 5314 | return init_rmode_tss(kvm); |
cbc94022 IE |
5315 | } |
5316 | ||
0ca1b4f4 | 5317 | static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) |
6aa8b732 | 5318 | { |
77ab6db0 | 5319 | switch (vec) { |
77ab6db0 | 5320 | case BP_VECTOR: |
c573cd22 JK |
5321 | /* |
5322 | * Update instruction length as we may reinject the exception | |
5323 | * from user space while in guest debugging mode. | |
5324 | */ | |
5325 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
5326 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 | 5327 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
0ca1b4f4 GN |
5328 | return false; |
5329 | /* fall through */ | |
5330 | case DB_VECTOR: | |
5331 | if (vcpu->guest_debug & | |
5332 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
5333 | return false; | |
d0bfb940 JK |
5334 | /* fall through */ |
5335 | case DE_VECTOR: | |
77ab6db0 JK |
5336 | case OF_VECTOR: |
5337 | case BR_VECTOR: | |
5338 | case UD_VECTOR: | |
5339 | case DF_VECTOR: | |
5340 | case SS_VECTOR: | |
5341 | case GP_VECTOR: | |
5342 | case MF_VECTOR: | |
0ca1b4f4 GN |
5343 | return true; |
5344 | break; | |
77ab6db0 | 5345 | } |
0ca1b4f4 GN |
5346 | return false; |
5347 | } | |
5348 | ||
5349 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
5350 | int vec, u32 err_code) | |
5351 | { | |
5352 | /* | |
5353 | * Instruction with address size override prefix opcode 0x67 | |
5354 | * Cause the #SS fault with 0 error code in VM86 mode. | |
5355 | */ | |
5356 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { | |
5357 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) { | |
5358 | if (vcpu->arch.halt_request) { | |
5359 | vcpu->arch.halt_request = 0; | |
5cb56059 | 5360 | return kvm_vcpu_halt(vcpu); |
0ca1b4f4 GN |
5361 | } |
5362 | return 1; | |
5363 | } | |
5364 | return 0; | |
5365 | } | |
5366 | ||
5367 | /* | |
5368 | * Forward all other exceptions that are valid in real mode. | |
5369 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
5370 | * the required debugging infrastructure rework. | |
5371 | */ | |
5372 | kvm_queue_exception(vcpu, vec); | |
5373 | return 1; | |
6aa8b732 AK |
5374 | } |
5375 | ||
a0861c02 AK |
5376 | /* |
5377 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
5378 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
5379 | * We pass a fake environment to the machine check handler because we want | |
5380 | * the guest to be always treated like user space, no matter what context | |
5381 | * it used internally. | |
5382 | */ | |
5383 | static void kvm_machine_check(void) | |
5384 | { | |
5385 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
5386 | struct pt_regs regs = { | |
5387 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
5388 | .flags = X86_EFLAGS_IF, | |
5389 | }; | |
5390 | ||
5391 | do_machine_check(®s, 0); | |
5392 | #endif | |
5393 | } | |
5394 | ||
851ba692 | 5395 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
5396 | { |
5397 | /* already handled by vcpu_run */ | |
5398 | return 1; | |
5399 | } | |
5400 | ||
851ba692 | 5401 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 5402 | { |
1155f76a | 5403 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 5404 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 5405 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 5406 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
5407 | u32 vect_info; |
5408 | enum emulation_result er; | |
5409 | ||
1155f76a | 5410 | vect_info = vmx->idt_vectoring_info; |
88786475 | 5411 | intr_info = vmx->exit_intr_info; |
6aa8b732 | 5412 | |
a0861c02 | 5413 | if (is_machine_check(intr_info)) |
851ba692 | 5414 | return handle_machine_check(vcpu); |
a0861c02 | 5415 | |
e4a41889 | 5416 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR) |
1b6269db | 5417 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc AL |
5418 | |
5419 | if (is_no_device(intr_info)) { | |
5fd86fcf | 5420 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
5421 | return 1; |
5422 | } | |
5423 | ||
7aa81cc0 | 5424 | if (is_invalid_opcode(intr_info)) { |
ae1f5767 JK |
5425 | if (is_guest_mode(vcpu)) { |
5426 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5427 | return 1; | |
5428 | } | |
51d8b661 | 5429 | er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 5430 | if (er != EMULATE_DONE) |
7ee5d940 | 5431 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
5432 | return 1; |
5433 | } | |
5434 | ||
6aa8b732 | 5435 | error_code = 0; |
2e11384c | 5436 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 | 5437 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
bf4ca23e XG |
5438 | |
5439 | /* | |
5440 | * The #PF with PFEC.RSVD = 1 indicates the guest is accessing | |
5441 | * MMIO, it is better to report an internal error. | |
5442 | * See the comments in vmx_handle_exit. | |
5443 | */ | |
5444 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
5445 | !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { | |
5446 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
5447 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
80f0e95d | 5448 | vcpu->run->internal.ndata = 3; |
bf4ca23e XG |
5449 | vcpu->run->internal.data[0] = vect_info; |
5450 | vcpu->run->internal.data[1] = intr_info; | |
80f0e95d | 5451 | vcpu->run->internal.data[2] = error_code; |
bf4ca23e XG |
5452 | return 0; |
5453 | } | |
5454 | ||
6aa8b732 | 5455 | if (is_page_fault(intr_info)) { |
1439442c | 5456 | /* EPT won't cause page fault directly */ |
cf3ace79 | 5457 | BUG_ON(enable_ept); |
6aa8b732 | 5458 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
229456fc MT |
5459 | trace_kvm_page_fault(cr2, error_code); |
5460 | ||
3298b75c | 5461 | if (kvm_event_needs_reinjection(vcpu)) |
577bdc49 | 5462 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
dc25e89e | 5463 | return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0); |
6aa8b732 AK |
5464 | } |
5465 | ||
d0bfb940 | 5466 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
0ca1b4f4 GN |
5467 | |
5468 | if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) | |
5469 | return handle_rmode_exception(vcpu, ex_no, error_code); | |
5470 | ||
42dbaa5a | 5471 | switch (ex_no) { |
54a20552 EN |
5472 | case AC_VECTOR: |
5473 | kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); | |
5474 | return 1; | |
42dbaa5a JK |
5475 | case DB_VECTOR: |
5476 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
5477 | if (!(vcpu->guest_debug & | |
5478 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
8246bf52 | 5479 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 5480 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
fd2a445a HD |
5481 | if (!(dr6 & ~DR6_RESERVED)) /* icebp */ |
5482 | skip_emulated_instruction(vcpu); | |
5483 | ||
42dbaa5a JK |
5484 | kvm_queue_exception(vcpu, DB_VECTOR); |
5485 | return 1; | |
5486 | } | |
5487 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
5488 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
5489 | /* fall through */ | |
5490 | case BP_VECTOR: | |
c573cd22 JK |
5491 | /* |
5492 | * Update instruction length as we may reinject #BP from | |
5493 | * user space while in guest debugging mode. Reading it for | |
5494 | * #DB as well causes no harm, it is not used in that case. | |
5495 | */ | |
5496 | vmx->vcpu.arch.event_exit_inst_len = | |
5497 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 5498 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 5499 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
5500 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
5501 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
5502 | break; |
5503 | default: | |
d0bfb940 JK |
5504 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
5505 | kvm_run->ex.exception = ex_no; | |
5506 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 5507 | break; |
6aa8b732 | 5508 | } |
6aa8b732 AK |
5509 | return 0; |
5510 | } | |
5511 | ||
851ba692 | 5512 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 5513 | { |
1165f5fe | 5514 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
5515 | return 1; |
5516 | } | |
5517 | ||
851ba692 | 5518 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 5519 | { |
851ba692 | 5520 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
988ad74f AK |
5521 | return 0; |
5522 | } | |
6aa8b732 | 5523 | |
851ba692 | 5524 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 5525 | { |
bfdaab09 | 5526 | unsigned long exit_qualification; |
34c33d16 | 5527 | int size, in, string; |
039576c0 | 5528 | unsigned port; |
6aa8b732 | 5529 | |
bfdaab09 | 5530 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 5531 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 5532 | in = (exit_qualification & 8) != 0; |
e70669ab | 5533 | |
cf8f70bf | 5534 | ++vcpu->stat.io_exits; |
e70669ab | 5535 | |
cf8f70bf | 5536 | if (string || in) |
51d8b661 | 5537 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 5538 | |
cf8f70bf GN |
5539 | port = exit_qualification >> 16; |
5540 | size = (exit_qualification & 7) + 1; | |
e93f36bc | 5541 | skip_emulated_instruction(vcpu); |
cf8f70bf GN |
5542 | |
5543 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
5544 | } |
5545 | ||
102d8325 IM |
5546 | static void |
5547 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
5548 | { | |
5549 | /* | |
5550 | * Patch in the VMCALL instruction: | |
5551 | */ | |
5552 | hypercall[0] = 0x0f; | |
5553 | hypercall[1] = 0x01; | |
5554 | hypercall[2] = 0xc1; | |
102d8325 IM |
5555 | } |
5556 | ||
b9c237bb | 5557 | static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) |
92fbc7b1 JK |
5558 | { |
5559 | unsigned long always_on = VMXON_CR0_ALWAYSON; | |
b9c237bb | 5560 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
92fbc7b1 | 5561 | |
b9c237bb | 5562 | if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high & |
92fbc7b1 JK |
5563 | SECONDARY_EXEC_UNRESTRICTED_GUEST && |
5564 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) | |
5565 | always_on &= ~(X86_CR0_PE | X86_CR0_PG); | |
5566 | return (val & always_on) == always_on; | |
5567 | } | |
5568 | ||
0fa06071 | 5569 | /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ |
eeadf9e7 NHE |
5570 | static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) |
5571 | { | |
eeadf9e7 | 5572 | if (is_guest_mode(vcpu)) { |
1a0d74e6 JK |
5573 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
5574 | unsigned long orig_val = val; | |
5575 | ||
eeadf9e7 NHE |
5576 | /* |
5577 | * We get here when L2 changed cr0 in a way that did not change | |
5578 | * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), | |
1a0d74e6 JK |
5579 | * but did change L0 shadowed bits. So we first calculate the |
5580 | * effective cr0 value that L1 would like to write into the | |
5581 | * hardware. It consists of the L2-owned bits from the new | |
5582 | * value combined with the L1-owned bits from L1's guest_cr0. | |
eeadf9e7 | 5583 | */ |
1a0d74e6 JK |
5584 | val = (val & ~vmcs12->cr0_guest_host_mask) | |
5585 | (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); | |
5586 | ||
b9c237bb | 5587 | if (!nested_cr0_valid(vcpu, val)) |
eeadf9e7 | 5588 | return 1; |
1a0d74e6 JK |
5589 | |
5590 | if (kvm_set_cr0(vcpu, val)) | |
5591 | return 1; | |
5592 | vmcs_writel(CR0_READ_SHADOW, orig_val); | |
eeadf9e7 | 5593 | return 0; |
1a0d74e6 JK |
5594 | } else { |
5595 | if (to_vmx(vcpu)->nested.vmxon && | |
5596 | ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)) | |
5597 | return 1; | |
eeadf9e7 | 5598 | return kvm_set_cr0(vcpu, val); |
1a0d74e6 | 5599 | } |
eeadf9e7 NHE |
5600 | } |
5601 | ||
5602 | static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) | |
5603 | { | |
5604 | if (is_guest_mode(vcpu)) { | |
1a0d74e6 JK |
5605 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
5606 | unsigned long orig_val = val; | |
5607 | ||
5608 | /* analogously to handle_set_cr0 */ | |
5609 | val = (val & ~vmcs12->cr4_guest_host_mask) | | |
5610 | (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); | |
5611 | if (kvm_set_cr4(vcpu, val)) | |
eeadf9e7 | 5612 | return 1; |
1a0d74e6 | 5613 | vmcs_writel(CR4_READ_SHADOW, orig_val); |
eeadf9e7 NHE |
5614 | return 0; |
5615 | } else | |
5616 | return kvm_set_cr4(vcpu, val); | |
5617 | } | |
5618 | ||
6a6256f9 | 5619 | /* called to set cr0 as appropriate for clts instruction exit. */ |
eeadf9e7 NHE |
5620 | static void handle_clts(struct kvm_vcpu *vcpu) |
5621 | { | |
5622 | if (is_guest_mode(vcpu)) { | |
5623 | /* | |
5624 | * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS | |
5625 | * but we did (!fpu_active). We need to keep GUEST_CR0.TS on, | |
5626 | * just pretend it's off (also in arch.cr0 for fpu_activate). | |
5627 | */ | |
5628 | vmcs_writel(CR0_READ_SHADOW, | |
5629 | vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS); | |
5630 | vcpu->arch.cr0 &= ~X86_CR0_TS; | |
5631 | } else | |
5632 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); | |
5633 | } | |
5634 | ||
851ba692 | 5635 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5636 | { |
229456fc | 5637 | unsigned long exit_qualification, val; |
6aa8b732 AK |
5638 | int cr; |
5639 | int reg; | |
49a9b07e | 5640 | int err; |
6aa8b732 | 5641 | |
bfdaab09 | 5642 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
5643 | cr = exit_qualification & 15; |
5644 | reg = (exit_qualification >> 8) & 15; | |
5645 | switch ((exit_qualification >> 4) & 3) { | |
5646 | case 0: /* mov to cr */ | |
1e32c079 | 5647 | val = kvm_register_readl(vcpu, reg); |
229456fc | 5648 | trace_kvm_cr_write(cr, val); |
6aa8b732 AK |
5649 | switch (cr) { |
5650 | case 0: | |
eeadf9e7 | 5651 | err = handle_set_cr0(vcpu, val); |
db8fcefa | 5652 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 AK |
5653 | return 1; |
5654 | case 3: | |
2390218b | 5655 | err = kvm_set_cr3(vcpu, val); |
db8fcefa | 5656 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 AK |
5657 | return 1; |
5658 | case 4: | |
eeadf9e7 | 5659 | err = handle_set_cr4(vcpu, val); |
db8fcefa | 5660 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 5661 | return 1; |
0a5fff19 GN |
5662 | case 8: { |
5663 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
1e32c079 | 5664 | u8 cr8 = (u8)val; |
eea1cff9 | 5665 | err = kvm_set_cr8(vcpu, cr8); |
db8fcefa | 5666 | kvm_complete_insn_gp(vcpu, err); |
35754c98 | 5667 | if (lapic_in_kernel(vcpu)) |
0a5fff19 GN |
5668 | return 1; |
5669 | if (cr8_prev <= cr8) | |
5670 | return 1; | |
851ba692 | 5671 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
5672 | return 0; |
5673 | } | |
4b8073e4 | 5674 | } |
6aa8b732 | 5675 | break; |
25c4c276 | 5676 | case 2: /* clts */ |
eeadf9e7 | 5677 | handle_clts(vcpu); |
4d4ec087 | 5678 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
25c4c276 | 5679 | skip_emulated_instruction(vcpu); |
6b52d186 | 5680 | vmx_fpu_activate(vcpu); |
25c4c276 | 5681 | return 1; |
6aa8b732 AK |
5682 | case 1: /*mov from cr*/ |
5683 | switch (cr) { | |
5684 | case 3: | |
9f8fe504 AK |
5685 | val = kvm_read_cr3(vcpu); |
5686 | kvm_register_write(vcpu, reg, val); | |
5687 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
5688 | skip_emulated_instruction(vcpu); |
5689 | return 1; | |
5690 | case 8: | |
229456fc MT |
5691 | val = kvm_get_cr8(vcpu); |
5692 | kvm_register_write(vcpu, reg, val); | |
5693 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
5694 | skip_emulated_instruction(vcpu); |
5695 | return 1; | |
5696 | } | |
5697 | break; | |
5698 | case 3: /* lmsw */ | |
a1f83a74 | 5699 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 5700 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 5701 | kvm_lmsw(vcpu, val); |
6aa8b732 AK |
5702 | |
5703 | skip_emulated_instruction(vcpu); | |
5704 | return 1; | |
5705 | default: | |
5706 | break; | |
5707 | } | |
851ba692 | 5708 | vcpu->run->exit_reason = 0; |
a737f256 | 5709 | vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
5710 | (int)(exit_qualification >> 4) & 3, cr); |
5711 | return 0; | |
5712 | } | |
5713 | ||
851ba692 | 5714 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5715 | { |
bfdaab09 | 5716 | unsigned long exit_qualification; |
16f8a6f9 NA |
5717 | int dr, dr7, reg; |
5718 | ||
5719 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5720 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; | |
5721 | ||
5722 | /* First, if DR does not exist, trigger UD */ | |
5723 | if (!kvm_require_dr(vcpu, dr)) | |
5724 | return 1; | |
6aa8b732 | 5725 | |
f2483415 | 5726 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
5727 | if (!kvm_require_cpl(vcpu, 0)) |
5728 | return 1; | |
16f8a6f9 NA |
5729 | dr7 = vmcs_readl(GUEST_DR7); |
5730 | if (dr7 & DR7_GD) { | |
42dbaa5a JK |
5731 | /* |
5732 | * As the vm-exit takes precedence over the debug trap, we | |
5733 | * need to emulate the latter, either for the host or the | |
5734 | * guest debugging itself. | |
5735 | */ | |
5736 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 | 5737 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
16f8a6f9 | 5738 | vcpu->run->debug.arch.dr7 = dr7; |
82b32774 | 5739 | vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
851ba692 AK |
5740 | vcpu->run->debug.arch.exception = DB_VECTOR; |
5741 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
5742 | return 0; |
5743 | } else { | |
7305eb5d | 5744 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 5745 | vcpu->arch.dr6 |= DR6_BD | DR6_RTM; |
42dbaa5a JK |
5746 | kvm_queue_exception(vcpu, DB_VECTOR); |
5747 | return 1; | |
5748 | } | |
5749 | } | |
5750 | ||
81908bf4 | 5751 | if (vcpu->guest_debug == 0) { |
8f22372f PB |
5752 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
5753 | CPU_BASED_MOV_DR_EXITING); | |
81908bf4 PB |
5754 | |
5755 | /* | |
5756 | * No more DR vmexits; force a reload of the debug registers | |
5757 | * and reenter on this instruction. The next vmexit will | |
5758 | * retrieve the full state of the debug registers. | |
5759 | */ | |
5760 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
5761 | return 1; | |
5762 | } | |
5763 | ||
42dbaa5a JK |
5764 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); |
5765 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 | 5766 | unsigned long val; |
4c4d563b JK |
5767 | |
5768 | if (kvm_get_dr(vcpu, dr, &val)) | |
5769 | return 1; | |
5770 | kvm_register_write(vcpu, reg, val); | |
020df079 | 5771 | } else |
5777392e | 5772 | if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) |
4c4d563b JK |
5773 | return 1; |
5774 | ||
6aa8b732 AK |
5775 | skip_emulated_instruction(vcpu); |
5776 | return 1; | |
5777 | } | |
5778 | ||
73aaf249 JK |
5779 | static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) |
5780 | { | |
5781 | return vcpu->arch.dr6; | |
5782 | } | |
5783 | ||
5784 | static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) | |
5785 | { | |
5786 | } | |
5787 | ||
81908bf4 PB |
5788 | static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
5789 | { | |
81908bf4 PB |
5790 | get_debugreg(vcpu->arch.db[0], 0); |
5791 | get_debugreg(vcpu->arch.db[1], 1); | |
5792 | get_debugreg(vcpu->arch.db[2], 2); | |
5793 | get_debugreg(vcpu->arch.db[3], 3); | |
5794 | get_debugreg(vcpu->arch.dr6, 6); | |
5795 | vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); | |
5796 | ||
5797 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
8f22372f | 5798 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING); |
81908bf4 PB |
5799 | } |
5800 | ||
020df079 GN |
5801 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
5802 | { | |
5803 | vmcs_writel(GUEST_DR7, val); | |
5804 | } | |
5805 | ||
851ba692 | 5806 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 5807 | { |
06465c5a AK |
5808 | kvm_emulate_cpuid(vcpu); |
5809 | return 1; | |
6aa8b732 AK |
5810 | } |
5811 | ||
851ba692 | 5812 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5813 | { |
ad312c7c | 5814 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
609e36d3 | 5815 | struct msr_data msr_info; |
6aa8b732 | 5816 | |
609e36d3 PB |
5817 | msr_info.index = ecx; |
5818 | msr_info.host_initiated = false; | |
5819 | if (vmx_get_msr(vcpu, &msr_info)) { | |
59200273 | 5820 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 5821 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
5822 | return 1; |
5823 | } | |
5824 | ||
609e36d3 | 5825 | trace_kvm_msr_read(ecx, msr_info.data); |
2714d1d3 | 5826 | |
6aa8b732 | 5827 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
609e36d3 PB |
5828 | vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u; |
5829 | vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u; | |
6aa8b732 AK |
5830 | skip_emulated_instruction(vcpu); |
5831 | return 1; | |
5832 | } | |
5833 | ||
851ba692 | 5834 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5835 | { |
8fe8ab46 | 5836 | struct msr_data msr; |
ad312c7c ZX |
5837 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
5838 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
5839 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 5840 | |
8fe8ab46 WA |
5841 | msr.data = data; |
5842 | msr.index = ecx; | |
5843 | msr.host_initiated = false; | |
854e8bb1 | 5844 | if (kvm_set_msr(vcpu, &msr) != 0) { |
59200273 | 5845 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 5846 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
5847 | return 1; |
5848 | } | |
5849 | ||
59200273 | 5850 | trace_kvm_msr_write(ecx, data); |
6aa8b732 AK |
5851 | skip_emulated_instruction(vcpu); |
5852 | return 1; | |
5853 | } | |
5854 | ||
851ba692 | 5855 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 5856 | { |
3842d135 | 5857 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6e5d865c YS |
5858 | return 1; |
5859 | } | |
5860 | ||
851ba692 | 5861 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 5862 | { |
85f455f7 ED |
5863 | u32 cpu_based_vm_exec_control; |
5864 | ||
5865 | /* clear pending irq */ | |
5866 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
5867 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
5868 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 | 5869 | |
3842d135 AK |
5870 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5871 | ||
a26bf12a | 5872 | ++vcpu->stat.irq_window_exits; |
6aa8b732 AK |
5873 | return 1; |
5874 | } | |
5875 | ||
851ba692 | 5876 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 | 5877 | { |
d3bef15f | 5878 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
5879 | } |
5880 | ||
851ba692 | 5881 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 5882 | { |
0d9c055e | 5883 | return kvm_emulate_hypercall(vcpu); |
c21415e8 IM |
5884 | } |
5885 | ||
ec25d5e6 GN |
5886 | static int handle_invd(struct kvm_vcpu *vcpu) |
5887 | { | |
51d8b661 | 5888 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
5889 | } |
5890 | ||
851ba692 | 5891 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 5892 | { |
f9c617f6 | 5893 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
5894 | |
5895 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
5896 | skip_emulated_instruction(vcpu); | |
5897 | return 1; | |
5898 | } | |
5899 | ||
fee84b07 AK |
5900 | static int handle_rdpmc(struct kvm_vcpu *vcpu) |
5901 | { | |
5902 | int err; | |
5903 | ||
5904 | err = kvm_rdpmc(vcpu); | |
5905 | kvm_complete_insn_gp(vcpu, err); | |
5906 | ||
5907 | return 1; | |
5908 | } | |
5909 | ||
851ba692 | 5910 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 | 5911 | { |
f5f48ee1 | 5912 | kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
5913 | return 1; |
5914 | } | |
5915 | ||
2acf923e DC |
5916 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
5917 | { | |
5918 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
5919 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5920 | ||
5921 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
5922 | skip_emulated_instruction(vcpu); | |
5923 | return 1; | |
5924 | } | |
5925 | ||
f53cd63c WL |
5926 | static int handle_xsaves(struct kvm_vcpu *vcpu) |
5927 | { | |
5928 | skip_emulated_instruction(vcpu); | |
5929 | WARN(1, "this should never happen\n"); | |
5930 | return 1; | |
5931 | } | |
5932 | ||
5933 | static int handle_xrstors(struct kvm_vcpu *vcpu) | |
5934 | { | |
5935 | skip_emulated_instruction(vcpu); | |
5936 | WARN(1, "this should never happen\n"); | |
5937 | return 1; | |
5938 | } | |
5939 | ||
851ba692 | 5940 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 5941 | { |
58fbbf26 KT |
5942 | if (likely(fasteoi)) { |
5943 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5944 | int access_type, offset; | |
5945 | ||
5946 | access_type = exit_qualification & APIC_ACCESS_TYPE; | |
5947 | offset = exit_qualification & APIC_ACCESS_OFFSET; | |
5948 | /* | |
5949 | * Sane guest uses MOV to write EOI, with written value | |
5950 | * not cared. So make a short-circuit here by avoiding | |
5951 | * heavy instruction emulation. | |
5952 | */ | |
5953 | if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && | |
5954 | (offset == APIC_EOI)) { | |
5955 | kvm_lapic_set_eoi(vcpu); | |
5956 | skip_emulated_instruction(vcpu); | |
5957 | return 1; | |
5958 | } | |
5959 | } | |
51d8b661 | 5960 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
5961 | } |
5962 | ||
c7c9c56c YZ |
5963 | static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) |
5964 | { | |
5965 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5966 | int vector = exit_qualification & 0xff; | |
5967 | ||
5968 | /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ | |
5969 | kvm_apic_set_eoi_accelerated(vcpu, vector); | |
5970 | return 1; | |
5971 | } | |
5972 | ||
83d4c286 YZ |
5973 | static int handle_apic_write(struct kvm_vcpu *vcpu) |
5974 | { | |
5975 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5976 | u32 offset = exit_qualification & 0xfff; | |
5977 | ||
5978 | /* APIC-write VM exit is trap-like and thus no need to adjust IP */ | |
5979 | kvm_apic_write_nodecode(vcpu, offset); | |
5980 | return 1; | |
5981 | } | |
5982 | ||
851ba692 | 5983 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 5984 | { |
60637aac | 5985 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 5986 | unsigned long exit_qualification; |
e269fb21 JK |
5987 | bool has_error_code = false; |
5988 | u32 error_code = 0; | |
37817f29 | 5989 | u16 tss_selector; |
7f3d35fd | 5990 | int reason, type, idt_v, idt_index; |
64a7ec06 GN |
5991 | |
5992 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
7f3d35fd | 5993 | idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); |
64a7ec06 | 5994 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); |
37817f29 IE |
5995 | |
5996 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5997 | ||
5998 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
5999 | if (reason == TASK_SWITCH_GATE && idt_v) { |
6000 | switch (type) { | |
6001 | case INTR_TYPE_NMI_INTR: | |
6002 | vcpu->arch.nmi_injected = false; | |
654f06fc | 6003 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
6004 | break; |
6005 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 6006 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
6007 | kvm_clear_interrupt_queue(vcpu); |
6008 | break; | |
6009 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
6010 | if (vmx->idt_vectoring_info & |
6011 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
6012 | has_error_code = true; | |
6013 | error_code = | |
6014 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
6015 | } | |
6016 | /* fall through */ | |
64a7ec06 GN |
6017 | case INTR_TYPE_SOFT_EXCEPTION: |
6018 | kvm_clear_exception_queue(vcpu); | |
6019 | break; | |
6020 | default: | |
6021 | break; | |
6022 | } | |
60637aac | 6023 | } |
37817f29 IE |
6024 | tss_selector = exit_qualification; |
6025 | ||
64a7ec06 GN |
6026 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
6027 | type != INTR_TYPE_EXT_INTR && | |
6028 | type != INTR_TYPE_NMI_INTR)) | |
6029 | skip_emulated_instruction(vcpu); | |
6030 | ||
7f3d35fd KW |
6031 | if (kvm_task_switch(vcpu, tss_selector, |
6032 | type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason, | |
6033 | has_error_code, error_code) == EMULATE_FAIL) { | |
acb54517 GN |
6034 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
6035 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6036 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 6037 | return 0; |
acb54517 | 6038 | } |
42dbaa5a | 6039 | |
42dbaa5a JK |
6040 | /* |
6041 | * TODO: What about debug traps on tss switch? | |
6042 | * Are we supposed to inject them and update dr6? | |
6043 | */ | |
6044 | ||
6045 | return 1; | |
37817f29 IE |
6046 | } |
6047 | ||
851ba692 | 6048 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 6049 | { |
f9c617f6 | 6050 | unsigned long exit_qualification; |
1439442c | 6051 | gpa_t gpa; |
4f5982a5 | 6052 | u32 error_code; |
1439442c | 6053 | int gla_validity; |
1439442c | 6054 | |
f9c617f6 | 6055 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c | 6056 | |
1439442c SY |
6057 | gla_validity = (exit_qualification >> 7) & 0x3; |
6058 | if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) { | |
6059 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | |
6060 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
6061 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
f9c617f6 | 6062 | vmcs_readl(GUEST_LINEAR_ADDRESS)); |
1439442c SY |
6063 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", |
6064 | (long unsigned int)exit_qualification); | |
851ba692 AK |
6065 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
6066 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION; | |
596ae895 | 6067 | return 0; |
1439442c SY |
6068 | } |
6069 | ||
0be9c7a8 GN |
6070 | /* |
6071 | * EPT violation happened while executing iret from NMI, | |
6072 | * "blocked by NMI" bit has to be set before next VM entry. | |
6073 | * There are errata that may cause this bit to not be set: | |
6074 | * AAK134, BY25. | |
6075 | */ | |
bcd1c294 GN |
6076 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && |
6077 | cpu_has_virtual_nmis() && | |
6078 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) | |
0be9c7a8 GN |
6079 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); |
6080 | ||
1439442c | 6081 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
229456fc | 6082 | trace_kvm_page_fault(gpa, exit_qualification); |
4f5982a5 XG |
6083 | |
6084 | /* It is a write fault? */ | |
81ed33e4 | 6085 | error_code = exit_qualification & PFERR_WRITE_MASK; |
25d92081 | 6086 | /* It is a fetch fault? */ |
81ed33e4 | 6087 | error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK; |
4f5982a5 | 6088 | /* ept page table is present? */ |
81ed33e4 | 6089 | error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK; |
4f5982a5 | 6090 | |
25d92081 YZ |
6091 | vcpu->arch.exit_qualification = exit_qualification; |
6092 | ||
4f5982a5 | 6093 | return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); |
1439442c SY |
6094 | } |
6095 | ||
851ba692 | 6096 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 | 6097 | { |
f735d4af | 6098 | int ret; |
68f89400 MT |
6099 | gpa_t gpa; |
6100 | ||
6101 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
e32edf4f | 6102 | if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { |
68c3b4d1 | 6103 | skip_emulated_instruction(vcpu); |
931c33b1 | 6104 | trace_kvm_fast_mmio(gpa); |
68c3b4d1 MT |
6105 | return 1; |
6106 | } | |
68f89400 | 6107 | |
450869d6 | 6108 | ret = handle_mmio_page_fault(vcpu, gpa, true); |
b37fbea6 | 6109 | if (likely(ret == RET_MMIO_PF_EMULATE)) |
ce88decf XG |
6110 | return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) == |
6111 | EMULATE_DONE; | |
f8f55942 XG |
6112 | |
6113 | if (unlikely(ret == RET_MMIO_PF_INVALID)) | |
6114 | return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0); | |
6115 | ||
b37fbea6 | 6116 | if (unlikely(ret == RET_MMIO_PF_RETRY)) |
ce88decf XG |
6117 | return 1; |
6118 | ||
6119 | /* It is the real ept misconfig */ | |
f735d4af | 6120 | WARN_ON(1); |
68f89400 | 6121 | |
851ba692 AK |
6122 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
6123 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
6124 | |
6125 | return 0; | |
6126 | } | |
6127 | ||
851ba692 | 6128 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 SY |
6129 | { |
6130 | u32 cpu_based_vm_exec_control; | |
6131 | ||
6132 | /* clear pending NMI */ | |
6133 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
6134 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
6135 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
6136 | ++vcpu->stat.nmi_window_exits; | |
3842d135 | 6137 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
6138 | |
6139 | return 1; | |
6140 | } | |
6141 | ||
80ced186 | 6142 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 6143 | { |
8b3079a5 AK |
6144 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6145 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 6146 | int ret = 1; |
49e9d557 AK |
6147 | u32 cpu_exec_ctrl; |
6148 | bool intr_window_requested; | |
b8405c18 | 6149 | unsigned count = 130; |
49e9d557 AK |
6150 | |
6151 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
6152 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 | 6153 | |
98eb2f8b | 6154 | while (vmx->emulation_required && count-- != 0) { |
bdea48e3 | 6155 | if (intr_window_requested && vmx_interrupt_allowed(vcpu)) |
49e9d557 AK |
6156 | return handle_interrupt_window(&vmx->vcpu); |
6157 | ||
de87dcdd AK |
6158 | if (test_bit(KVM_REQ_EVENT, &vcpu->requests)) |
6159 | return 1; | |
6160 | ||
991eebf9 | 6161 | err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE); |
ea953ef0 | 6162 | |
ac0a48c3 | 6163 | if (err == EMULATE_USER_EXIT) { |
94452b9e | 6164 | ++vcpu->stat.mmio_exits; |
80ced186 MG |
6165 | ret = 0; |
6166 | goto out; | |
6167 | } | |
1d5a4d9b | 6168 | |
de5f70e0 AK |
6169 | if (err != EMULATE_DONE) { |
6170 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6171 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6172 | vcpu->run->internal.ndata = 0; | |
6d77dbfc | 6173 | return 0; |
de5f70e0 | 6174 | } |
ea953ef0 | 6175 | |
8d76c49e GN |
6176 | if (vcpu->arch.halt_request) { |
6177 | vcpu->arch.halt_request = 0; | |
5cb56059 | 6178 | ret = kvm_vcpu_halt(vcpu); |
8d76c49e GN |
6179 | goto out; |
6180 | } | |
6181 | ||
ea953ef0 | 6182 | if (signal_pending(current)) |
80ced186 | 6183 | goto out; |
ea953ef0 MG |
6184 | if (need_resched()) |
6185 | schedule(); | |
6186 | } | |
6187 | ||
80ced186 MG |
6188 | out: |
6189 | return ret; | |
ea953ef0 MG |
6190 | } |
6191 | ||
b4a2d31d RK |
6192 | static int __grow_ple_window(int val) |
6193 | { | |
6194 | if (ple_window_grow < 1) | |
6195 | return ple_window; | |
6196 | ||
6197 | val = min(val, ple_window_actual_max); | |
6198 | ||
6199 | if (ple_window_grow < ple_window) | |
6200 | val *= ple_window_grow; | |
6201 | else | |
6202 | val += ple_window_grow; | |
6203 | ||
6204 | return val; | |
6205 | } | |
6206 | ||
6207 | static int __shrink_ple_window(int val, int modifier, int minimum) | |
6208 | { | |
6209 | if (modifier < 1) | |
6210 | return ple_window; | |
6211 | ||
6212 | if (modifier < ple_window) | |
6213 | val /= modifier; | |
6214 | else | |
6215 | val -= modifier; | |
6216 | ||
6217 | return max(val, minimum); | |
6218 | } | |
6219 | ||
6220 | static void grow_ple_window(struct kvm_vcpu *vcpu) | |
6221 | { | |
6222 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6223 | int old = vmx->ple_window; | |
6224 | ||
6225 | vmx->ple_window = __grow_ple_window(old); | |
6226 | ||
6227 | if (vmx->ple_window != old) | |
6228 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6229 | |
6230 | trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6231 | } |
6232 | ||
6233 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
6234 | { | |
6235 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6236 | int old = vmx->ple_window; | |
6237 | ||
6238 | vmx->ple_window = __shrink_ple_window(old, | |
6239 | ple_window_shrink, ple_window); | |
6240 | ||
6241 | if (vmx->ple_window != old) | |
6242 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6243 | |
6244 | trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6245 | } |
6246 | ||
6247 | /* | |
6248 | * ple_window_actual_max is computed to be one grow_ple_window() below | |
6249 | * ple_window_max. (See __grow_ple_window for the reason.) | |
6250 | * This prevents overflows, because ple_window_max is int. | |
6251 | * ple_window_max effectively rounded down to a multiple of ple_window_grow in | |
6252 | * this process. | |
6253 | * ple_window_max is also prevented from setting vmx->ple_window < ple_window. | |
6254 | */ | |
6255 | static void update_ple_window_actual_max(void) | |
6256 | { | |
6257 | ple_window_actual_max = | |
6258 | __shrink_ple_window(max(ple_window_max, ple_window), | |
6259 | ple_window_grow, INT_MIN); | |
6260 | } | |
6261 | ||
bf9f6ac8 FW |
6262 | /* |
6263 | * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. | |
6264 | */ | |
6265 | static void wakeup_handler(void) | |
6266 | { | |
6267 | struct kvm_vcpu *vcpu; | |
6268 | int cpu = smp_processor_id(); | |
6269 | ||
6270 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6271 | list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), | |
6272 | blocked_vcpu_list) { | |
6273 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
6274 | ||
6275 | if (pi_test_on(pi_desc) == 1) | |
6276 | kvm_vcpu_kick(vcpu); | |
6277 | } | |
6278 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6279 | } | |
6280 | ||
f2c7648d TC |
6281 | static __init int hardware_setup(void) |
6282 | { | |
34a1cd60 TC |
6283 | int r = -ENOMEM, i, msr; |
6284 | ||
6285 | rdmsrl_safe(MSR_EFER, &host_efer); | |
6286 | ||
6287 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) | |
6288 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
6289 | ||
6290 | vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6291 | if (!vmx_io_bitmap_a) | |
6292 | return r; | |
6293 | ||
6294 | vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6295 | if (!vmx_io_bitmap_b) | |
6296 | goto out; | |
6297 | ||
6298 | vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6299 | if (!vmx_msr_bitmap_legacy) | |
6300 | goto out1; | |
6301 | ||
6302 | vmx_msr_bitmap_legacy_x2apic = | |
6303 | (unsigned long *)__get_free_page(GFP_KERNEL); | |
6304 | if (!vmx_msr_bitmap_legacy_x2apic) | |
6305 | goto out2; | |
6306 | ||
6307 | vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6308 | if (!vmx_msr_bitmap_longmode) | |
6309 | goto out3; | |
6310 | ||
6311 | vmx_msr_bitmap_longmode_x2apic = | |
6312 | (unsigned long *)__get_free_page(GFP_KERNEL); | |
6313 | if (!vmx_msr_bitmap_longmode_x2apic) | |
6314 | goto out4; | |
3af18d9c WV |
6315 | |
6316 | if (nested) { | |
6317 | vmx_msr_bitmap_nested = | |
6318 | (unsigned long *)__get_free_page(GFP_KERNEL); | |
6319 | if (!vmx_msr_bitmap_nested) | |
6320 | goto out5; | |
6321 | } | |
6322 | ||
34a1cd60 TC |
6323 | vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL); |
6324 | if (!vmx_vmread_bitmap) | |
3af18d9c | 6325 | goto out6; |
34a1cd60 TC |
6326 | |
6327 | vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6328 | if (!vmx_vmwrite_bitmap) | |
3af18d9c | 6329 | goto out7; |
34a1cd60 TC |
6330 | |
6331 | memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); | |
6332 | memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); | |
6333 | ||
6334 | /* | |
6335 | * Allow direct access to the PC debug port (it is often used for I/O | |
6336 | * delays, but the vmexits simply slow things down). | |
6337 | */ | |
6338 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); | |
6339 | clear_bit(0x80, vmx_io_bitmap_a); | |
6340 | ||
6341 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); | |
6342 | ||
6343 | memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE); | |
6344 | memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE); | |
3af18d9c WV |
6345 | if (nested) |
6346 | memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE); | |
34a1cd60 | 6347 | |
34a1cd60 TC |
6348 | if (setup_vmcs_config(&vmcs_config) < 0) { |
6349 | r = -EIO; | |
3af18d9c | 6350 | goto out8; |
baa03522 | 6351 | } |
f2c7648d TC |
6352 | |
6353 | if (boot_cpu_has(X86_FEATURE_NX)) | |
6354 | kvm_enable_efer_bits(EFER_NX); | |
6355 | ||
6356 | if (!cpu_has_vmx_vpid()) | |
6357 | enable_vpid = 0; | |
6358 | if (!cpu_has_vmx_shadow_vmcs()) | |
6359 | enable_shadow_vmcs = 0; | |
6360 | if (enable_shadow_vmcs) | |
6361 | init_vmcs_shadow_fields(); | |
6362 | ||
6363 | if (!cpu_has_vmx_ept() || | |
6364 | !cpu_has_vmx_ept_4levels()) { | |
6365 | enable_ept = 0; | |
6366 | enable_unrestricted_guest = 0; | |
6367 | enable_ept_ad_bits = 0; | |
6368 | } | |
6369 | ||
6370 | if (!cpu_has_vmx_ept_ad_bits()) | |
6371 | enable_ept_ad_bits = 0; | |
6372 | ||
6373 | if (!cpu_has_vmx_unrestricted_guest()) | |
6374 | enable_unrestricted_guest = 0; | |
6375 | ||
ad15a296 | 6376 | if (!cpu_has_vmx_flexpriority()) |
f2c7648d TC |
6377 | flexpriority_enabled = 0; |
6378 | ||
ad15a296 PB |
6379 | /* |
6380 | * set_apic_access_page_addr() is used to reload apic access | |
6381 | * page upon invalidation. No need to do anything if not | |
6382 | * using the APIC_ACCESS_ADDR VMCS field. | |
6383 | */ | |
6384 | if (!flexpriority_enabled) | |
f2c7648d | 6385 | kvm_x86_ops->set_apic_access_page_addr = NULL; |
f2c7648d TC |
6386 | |
6387 | if (!cpu_has_vmx_tpr_shadow()) | |
6388 | kvm_x86_ops->update_cr8_intercept = NULL; | |
6389 | ||
6390 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) | |
6391 | kvm_disable_largepages(); | |
6392 | ||
6393 | if (!cpu_has_vmx_ple()) | |
6394 | ple_gap = 0; | |
6395 | ||
6396 | if (!cpu_has_vmx_apicv()) | |
6397 | enable_apicv = 0; | |
6398 | ||
64903d61 HZ |
6399 | if (cpu_has_vmx_tsc_scaling()) { |
6400 | kvm_has_tsc_control = true; | |
6401 | kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; | |
6402 | kvm_tsc_scaling_ratio_frac_bits = 48; | |
6403 | } | |
6404 | ||
baa03522 TC |
6405 | vmx_disable_intercept_for_msr(MSR_FS_BASE, false); |
6406 | vmx_disable_intercept_for_msr(MSR_GS_BASE, false); | |
6407 | vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); | |
6408 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); | |
6409 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); | |
6410 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); | |
6411 | vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true); | |
6412 | ||
6413 | memcpy(vmx_msr_bitmap_legacy_x2apic, | |
6414 | vmx_msr_bitmap_legacy, PAGE_SIZE); | |
6415 | memcpy(vmx_msr_bitmap_longmode_x2apic, | |
6416 | vmx_msr_bitmap_longmode, PAGE_SIZE); | |
6417 | ||
04bb92e4 WL |
6418 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
6419 | ||
3ce424e4 RK |
6420 | for (msr = 0x800; msr <= 0x8ff; msr++) |
6421 | vmx_disable_intercept_msr_read_x2apic(msr); | |
6422 | ||
6423 | /* According SDM, in x2apic mode, the whole id reg is used. But in | |
6424 | * KVM, it only use the highest eight bits. Need to intercept it */ | |
6425 | vmx_enable_intercept_msr_read_x2apic(0x802); | |
6426 | /* TMCCT */ | |
6427 | vmx_enable_intercept_msr_read_x2apic(0x839); | |
6428 | /* TPR */ | |
6429 | vmx_disable_intercept_msr_write_x2apic(0x808); | |
6430 | /* EOI */ | |
6431 | vmx_disable_intercept_msr_write_x2apic(0x80b); | |
6432 | /* SELF-IPI */ | |
6433 | vmx_disable_intercept_msr_write_x2apic(0x83f); | |
baa03522 TC |
6434 | |
6435 | if (enable_ept) { | |
6436 | kvm_mmu_set_mask_ptes(0ull, | |
6437 | (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull, | |
6438 | (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull, | |
6439 | 0ull, VMX_EPT_EXECUTABLE_MASK); | |
6440 | ept_set_mmio_spte_mask(); | |
6441 | kvm_enable_tdp(); | |
6442 | } else | |
6443 | kvm_disable_tdp(); | |
6444 | ||
6445 | update_ple_window_actual_max(); | |
6446 | ||
843e4330 KH |
6447 | /* |
6448 | * Only enable PML when hardware supports PML feature, and both EPT | |
6449 | * and EPT A/D bit features are enabled -- PML depends on them to work. | |
6450 | */ | |
6451 | if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) | |
6452 | enable_pml = 0; | |
6453 | ||
6454 | if (!enable_pml) { | |
6455 | kvm_x86_ops->slot_enable_log_dirty = NULL; | |
6456 | kvm_x86_ops->slot_disable_log_dirty = NULL; | |
6457 | kvm_x86_ops->flush_log_dirty = NULL; | |
6458 | kvm_x86_ops->enable_log_dirty_pt_masked = NULL; | |
6459 | } | |
6460 | ||
64672c95 YJ |
6461 | if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) { |
6462 | u64 vmx_msr; | |
6463 | ||
6464 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
6465 | cpu_preemption_timer_multi = | |
6466 | vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; | |
6467 | } else { | |
6468 | kvm_x86_ops->set_hv_timer = NULL; | |
6469 | kvm_x86_ops->cancel_hv_timer = NULL; | |
6470 | } | |
6471 | ||
bf9f6ac8 FW |
6472 | kvm_set_posted_intr_wakeup_handler(wakeup_handler); |
6473 | ||
f2c7648d | 6474 | return alloc_kvm_area(); |
34a1cd60 | 6475 | |
3af18d9c | 6476 | out8: |
34a1cd60 | 6477 | free_page((unsigned long)vmx_vmwrite_bitmap); |
3af18d9c | 6478 | out7: |
34a1cd60 | 6479 | free_page((unsigned long)vmx_vmread_bitmap); |
3af18d9c WV |
6480 | out6: |
6481 | if (nested) | |
6482 | free_page((unsigned long)vmx_msr_bitmap_nested); | |
34a1cd60 TC |
6483 | out5: |
6484 | free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic); | |
6485 | out4: | |
6486 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
6487 | out3: | |
6488 | free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic); | |
6489 | out2: | |
6490 | free_page((unsigned long)vmx_msr_bitmap_legacy); | |
6491 | out1: | |
6492 | free_page((unsigned long)vmx_io_bitmap_b); | |
6493 | out: | |
6494 | free_page((unsigned long)vmx_io_bitmap_a); | |
6495 | ||
6496 | return r; | |
f2c7648d TC |
6497 | } |
6498 | ||
6499 | static __exit void hardware_unsetup(void) | |
6500 | { | |
34a1cd60 TC |
6501 | free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic); |
6502 | free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic); | |
6503 | free_page((unsigned long)vmx_msr_bitmap_legacy); | |
6504 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
6505 | free_page((unsigned long)vmx_io_bitmap_b); | |
6506 | free_page((unsigned long)vmx_io_bitmap_a); | |
6507 | free_page((unsigned long)vmx_vmwrite_bitmap); | |
6508 | free_page((unsigned long)vmx_vmread_bitmap); | |
3af18d9c WV |
6509 | if (nested) |
6510 | free_page((unsigned long)vmx_msr_bitmap_nested); | |
34a1cd60 | 6511 | |
f2c7648d TC |
6512 | free_kvm_area(); |
6513 | } | |
6514 | ||
4b8d54f9 ZE |
6515 | /* |
6516 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
6517 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
6518 | */ | |
9fb41ba8 | 6519 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 | 6520 | { |
b4a2d31d RK |
6521 | if (ple_gap) |
6522 | grow_ple_window(vcpu); | |
6523 | ||
4b8d54f9 ZE |
6524 | skip_emulated_instruction(vcpu); |
6525 | kvm_vcpu_on_spin(vcpu); | |
6526 | ||
6527 | return 1; | |
6528 | } | |
6529 | ||
87c00572 | 6530 | static int handle_nop(struct kvm_vcpu *vcpu) |
59708670 | 6531 | { |
87c00572 | 6532 | skip_emulated_instruction(vcpu); |
59708670 SY |
6533 | return 1; |
6534 | } | |
6535 | ||
87c00572 GS |
6536 | static int handle_mwait(struct kvm_vcpu *vcpu) |
6537 | { | |
6538 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
6539 | return handle_nop(vcpu); | |
6540 | } | |
6541 | ||
5f3d45e7 MD |
6542 | static int handle_monitor_trap(struct kvm_vcpu *vcpu) |
6543 | { | |
6544 | return 1; | |
6545 | } | |
6546 | ||
87c00572 GS |
6547 | static int handle_monitor(struct kvm_vcpu *vcpu) |
6548 | { | |
6549 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
6550 | return handle_nop(vcpu); | |
6551 | } | |
6552 | ||
ff2f6fe9 NHE |
6553 | /* |
6554 | * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12. | |
6555 | * We could reuse a single VMCS for all the L2 guests, but we also want the | |
6556 | * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this | |
6557 | * allows keeping them loaded on the processor, and in the future will allow | |
6558 | * optimizations where prepare_vmcs02 doesn't need to set all the fields on | |
6559 | * every entry if they never change. | |
6560 | * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE | |
6561 | * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first. | |
6562 | * | |
6563 | * The following functions allocate and free a vmcs02 in this pool. | |
6564 | */ | |
6565 | ||
6566 | /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */ | |
6567 | static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx) | |
6568 | { | |
6569 | struct vmcs02_list *item; | |
6570 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6571 | if (item->vmptr == vmx->nested.current_vmptr) { | |
6572 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6573 | return &item->vmcs02; | |
6574 | } | |
6575 | ||
6576 | if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) { | |
6577 | /* Recycle the least recently used VMCS. */ | |
d74c0e6b GT |
6578 | item = list_last_entry(&vmx->nested.vmcs02_pool, |
6579 | struct vmcs02_list, list); | |
ff2f6fe9 NHE |
6580 | item->vmptr = vmx->nested.current_vmptr; |
6581 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6582 | return &item->vmcs02; | |
6583 | } | |
6584 | ||
6585 | /* Create a new VMCS */ | |
0fa24ce3 | 6586 | item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL); |
ff2f6fe9 NHE |
6587 | if (!item) |
6588 | return NULL; | |
6589 | item->vmcs02.vmcs = alloc_vmcs(); | |
6590 | if (!item->vmcs02.vmcs) { | |
6591 | kfree(item); | |
6592 | return NULL; | |
6593 | } | |
6594 | loaded_vmcs_init(&item->vmcs02); | |
6595 | item->vmptr = vmx->nested.current_vmptr; | |
6596 | list_add(&(item->list), &(vmx->nested.vmcs02_pool)); | |
6597 | vmx->nested.vmcs02_num++; | |
6598 | return &item->vmcs02; | |
6599 | } | |
6600 | ||
6601 | /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */ | |
6602 | static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr) | |
6603 | { | |
6604 | struct vmcs02_list *item; | |
6605 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6606 | if (item->vmptr == vmptr) { | |
6607 | free_loaded_vmcs(&item->vmcs02); | |
6608 | list_del(&item->list); | |
6609 | kfree(item); | |
6610 | vmx->nested.vmcs02_num--; | |
6611 | return; | |
6612 | } | |
6613 | } | |
6614 | ||
6615 | /* | |
6616 | * Free all VMCSs saved for this vcpu, except the one pointed by | |
4fa7734c PB |
6617 | * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs |
6618 | * must be &vmx->vmcs01. | |
ff2f6fe9 NHE |
6619 | */ |
6620 | static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx) | |
6621 | { | |
6622 | struct vmcs02_list *item, *n; | |
4fa7734c PB |
6623 | |
6624 | WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01); | |
ff2f6fe9 | 6625 | list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) { |
4fa7734c PB |
6626 | /* |
6627 | * Something will leak if the above WARN triggers. Better than | |
6628 | * a use-after-free. | |
6629 | */ | |
6630 | if (vmx->loaded_vmcs == &item->vmcs02) | |
6631 | continue; | |
6632 | ||
6633 | free_loaded_vmcs(&item->vmcs02); | |
ff2f6fe9 NHE |
6634 | list_del(&item->list); |
6635 | kfree(item); | |
4fa7734c | 6636 | vmx->nested.vmcs02_num--; |
ff2f6fe9 | 6637 | } |
ff2f6fe9 NHE |
6638 | } |
6639 | ||
0658fbaa ACL |
6640 | /* |
6641 | * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), | |
6642 | * set the success or error code of an emulated VMX instruction, as specified | |
6643 | * by Vol 2B, VMX Instruction Reference, "Conventions". | |
6644 | */ | |
6645 | static void nested_vmx_succeed(struct kvm_vcpu *vcpu) | |
6646 | { | |
6647 | vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) | |
6648 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
6649 | X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); | |
6650 | } | |
6651 | ||
6652 | static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu) | |
6653 | { | |
6654 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
6655 | & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | | |
6656 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
6657 | | X86_EFLAGS_CF); | |
6658 | } | |
6659 | ||
145c28dd | 6660 | static void nested_vmx_failValid(struct kvm_vcpu *vcpu, |
0658fbaa ACL |
6661 | u32 vm_instruction_error) |
6662 | { | |
6663 | if (to_vmx(vcpu)->nested.current_vmptr == -1ull) { | |
6664 | /* | |
6665 | * failValid writes the error number to the current VMCS, which | |
6666 | * can't be done there isn't a current VMCS. | |
6667 | */ | |
6668 | nested_vmx_failInvalid(vcpu); | |
6669 | return; | |
6670 | } | |
6671 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
6672 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
6673 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
6674 | | X86_EFLAGS_ZF); | |
6675 | get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; | |
6676 | /* | |
6677 | * We don't need to force a shadow sync because | |
6678 | * VM_INSTRUCTION_ERROR is not shadowed | |
6679 | */ | |
6680 | } | |
145c28dd | 6681 | |
ff651cb6 WV |
6682 | static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator) |
6683 | { | |
6684 | /* TODO: not to reset guest simply here. */ | |
6685 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
6686 | pr_warn("kvm: nested vmx abort, indicator %d\n", indicator); | |
6687 | } | |
6688 | ||
f4124500 JK |
6689 | static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) |
6690 | { | |
6691 | struct vcpu_vmx *vmx = | |
6692 | container_of(timer, struct vcpu_vmx, nested.preemption_timer); | |
6693 | ||
6694 | vmx->nested.preemption_timer_expired = true; | |
6695 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); | |
6696 | kvm_vcpu_kick(&vmx->vcpu); | |
6697 | ||
6698 | return HRTIMER_NORESTART; | |
6699 | } | |
6700 | ||
19677e32 BD |
6701 | /* |
6702 | * Decode the memory-address operand of a vmx instruction, as recorded on an | |
6703 | * exit caused by such an instruction (run by a guest hypervisor). | |
6704 | * On success, returns 0. When the operand is invalid, returns 1 and throws | |
6705 | * #UD or #GP. | |
6706 | */ | |
6707 | static int get_vmx_mem_address(struct kvm_vcpu *vcpu, | |
6708 | unsigned long exit_qualification, | |
f9eb4af6 | 6709 | u32 vmx_instruction_info, bool wr, gva_t *ret) |
19677e32 | 6710 | { |
f9eb4af6 EK |
6711 | gva_t off; |
6712 | bool exn; | |
6713 | struct kvm_segment s; | |
6714 | ||
19677e32 BD |
6715 | /* |
6716 | * According to Vol. 3B, "Information for VM Exits Due to Instruction | |
6717 | * Execution", on an exit, vmx_instruction_info holds most of the | |
6718 | * addressing components of the operand. Only the displacement part | |
6719 | * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). | |
6720 | * For how an actual address is calculated from all these components, | |
6721 | * refer to Vol. 1, "Operand Addressing". | |
6722 | */ | |
6723 | int scaling = vmx_instruction_info & 3; | |
6724 | int addr_size = (vmx_instruction_info >> 7) & 7; | |
6725 | bool is_reg = vmx_instruction_info & (1u << 10); | |
6726 | int seg_reg = (vmx_instruction_info >> 15) & 7; | |
6727 | int index_reg = (vmx_instruction_info >> 18) & 0xf; | |
6728 | bool index_is_valid = !(vmx_instruction_info & (1u << 22)); | |
6729 | int base_reg = (vmx_instruction_info >> 23) & 0xf; | |
6730 | bool base_is_valid = !(vmx_instruction_info & (1u << 27)); | |
6731 | ||
6732 | if (is_reg) { | |
6733 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6734 | return 1; | |
6735 | } | |
6736 | ||
6737 | /* Addr = segment_base + offset */ | |
6738 | /* offset = base + [index * scale] + displacement */ | |
f9eb4af6 | 6739 | off = exit_qualification; /* holds the displacement */ |
19677e32 | 6740 | if (base_is_valid) |
f9eb4af6 | 6741 | off += kvm_register_read(vcpu, base_reg); |
19677e32 | 6742 | if (index_is_valid) |
f9eb4af6 EK |
6743 | off += kvm_register_read(vcpu, index_reg)<<scaling; |
6744 | vmx_get_segment(vcpu, &s, seg_reg); | |
6745 | *ret = s.base + off; | |
19677e32 BD |
6746 | |
6747 | if (addr_size == 1) /* 32 bit */ | |
6748 | *ret &= 0xffffffff; | |
6749 | ||
f9eb4af6 EK |
6750 | /* Checks for #GP/#SS exceptions. */ |
6751 | exn = false; | |
6752 | if (is_protmode(vcpu)) { | |
6753 | /* Protected mode: apply checks for segment validity in the | |
6754 | * following order: | |
6755 | * - segment type check (#GP(0) may be thrown) | |
6756 | * - usability check (#GP(0)/#SS(0)) | |
6757 | * - limit check (#GP(0)/#SS(0)) | |
6758 | */ | |
6759 | if (wr) | |
6760 | /* #GP(0) if the destination operand is located in a | |
6761 | * read-only data segment or any code segment. | |
6762 | */ | |
6763 | exn = ((s.type & 0xa) == 0 || (s.type & 8)); | |
6764 | else | |
6765 | /* #GP(0) if the source operand is located in an | |
6766 | * execute-only code segment | |
6767 | */ | |
6768 | exn = ((s.type & 0xa) == 8); | |
6769 | } | |
6770 | if (exn) { | |
6771 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
6772 | return 1; | |
6773 | } | |
6774 | if (is_long_mode(vcpu)) { | |
6775 | /* Long mode: #GP(0)/#SS(0) if the memory address is in a | |
6776 | * non-canonical form. This is an only check for long mode. | |
6777 | */ | |
6778 | exn = is_noncanonical_address(*ret); | |
6779 | } else if (is_protmode(vcpu)) { | |
6780 | /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. | |
6781 | */ | |
6782 | exn = (s.unusable != 0); | |
6783 | /* Protected mode: #GP(0)/#SS(0) if the memory | |
6784 | * operand is outside the segment limit. | |
6785 | */ | |
6786 | exn = exn || (off + sizeof(u64) > s.limit); | |
6787 | } | |
6788 | if (exn) { | |
6789 | kvm_queue_exception_e(vcpu, | |
6790 | seg_reg == VCPU_SREG_SS ? | |
6791 | SS_VECTOR : GP_VECTOR, | |
6792 | 0); | |
6793 | return 1; | |
6794 | } | |
6795 | ||
19677e32 BD |
6796 | return 0; |
6797 | } | |
6798 | ||
3573e22c BD |
6799 | /* |
6800 | * This function performs the various checks including | |
6801 | * - if it's 4KB aligned | |
6802 | * - No bits beyond the physical address width are set | |
6803 | * - Returns 0 on success or else 1 | |
4291b588 | 6804 | * (Intel SDM Section 30.3) |
3573e22c | 6805 | */ |
4291b588 BD |
6806 | static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason, |
6807 | gpa_t *vmpointer) | |
3573e22c BD |
6808 | { |
6809 | gva_t gva; | |
6810 | gpa_t vmptr; | |
6811 | struct x86_exception e; | |
6812 | struct page *page; | |
6813 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6814 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
6815 | ||
6816 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 6817 | vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva)) |
3573e22c BD |
6818 | return 1; |
6819 | ||
6820 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr, | |
6821 | sizeof(vmptr), &e)) { | |
6822 | kvm_inject_page_fault(vcpu, &e); | |
6823 | return 1; | |
6824 | } | |
6825 | ||
6826 | switch (exit_reason) { | |
6827 | case EXIT_REASON_VMON: | |
6828 | /* | |
6829 | * SDM 3: 24.11.5 | |
6830 | * The first 4 bytes of VMXON region contain the supported | |
6831 | * VMCS revision identifier | |
6832 | * | |
6833 | * Note - IA32_VMX_BASIC[48] will never be 1 | |
6834 | * for the nested case; | |
6835 | * which replaces physical address width with 32 | |
6836 | * | |
6837 | */ | |
bc39c4db | 6838 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
3573e22c BD |
6839 | nested_vmx_failInvalid(vcpu); |
6840 | skip_emulated_instruction(vcpu); | |
6841 | return 1; | |
6842 | } | |
6843 | ||
6844 | page = nested_get_page(vcpu, vmptr); | |
6845 | if (page == NULL || | |
6846 | *(u32 *)kmap(page) != VMCS12_REVISION) { | |
6847 | nested_vmx_failInvalid(vcpu); | |
6848 | kunmap(page); | |
6849 | skip_emulated_instruction(vcpu); | |
6850 | return 1; | |
6851 | } | |
6852 | kunmap(page); | |
6853 | vmx->nested.vmxon_ptr = vmptr; | |
6854 | break; | |
4291b588 | 6855 | case EXIT_REASON_VMCLEAR: |
bc39c4db | 6856 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
4291b588 BD |
6857 | nested_vmx_failValid(vcpu, |
6858 | VMXERR_VMCLEAR_INVALID_ADDRESS); | |
6859 | skip_emulated_instruction(vcpu); | |
6860 | return 1; | |
6861 | } | |
6862 | ||
6863 | if (vmptr == vmx->nested.vmxon_ptr) { | |
6864 | nested_vmx_failValid(vcpu, | |
6865 | VMXERR_VMCLEAR_VMXON_POINTER); | |
6866 | skip_emulated_instruction(vcpu); | |
6867 | return 1; | |
6868 | } | |
6869 | break; | |
6870 | case EXIT_REASON_VMPTRLD: | |
bc39c4db | 6871 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
4291b588 BD |
6872 | nested_vmx_failValid(vcpu, |
6873 | VMXERR_VMPTRLD_INVALID_ADDRESS); | |
6874 | skip_emulated_instruction(vcpu); | |
6875 | return 1; | |
6876 | } | |
3573e22c | 6877 | |
4291b588 BD |
6878 | if (vmptr == vmx->nested.vmxon_ptr) { |
6879 | nested_vmx_failValid(vcpu, | |
6880 | VMXERR_VMCLEAR_VMXON_POINTER); | |
6881 | skip_emulated_instruction(vcpu); | |
6882 | return 1; | |
6883 | } | |
6884 | break; | |
3573e22c BD |
6885 | default: |
6886 | return 1; /* shouldn't happen */ | |
6887 | } | |
6888 | ||
4291b588 BD |
6889 | if (vmpointer) |
6890 | *vmpointer = vmptr; | |
3573e22c BD |
6891 | return 0; |
6892 | } | |
6893 | ||
ec378aee NHE |
6894 | /* |
6895 | * Emulate the VMXON instruction. | |
6896 | * Currently, we just remember that VMX is active, and do not save or even | |
6897 | * inspect the argument to VMXON (the so-called "VMXON pointer") because we | |
6898 | * do not currently need to store anything in that guest-allocated memory | |
6899 | * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their | |
6900 | * argument is different from the VMXON pointer (which the spec says they do). | |
6901 | */ | |
6902 | static int handle_vmon(struct kvm_vcpu *vcpu) | |
6903 | { | |
6904 | struct kvm_segment cs; | |
6905 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8de48833 | 6906 | struct vmcs *shadow_vmcs; |
b3897a49 NHE |
6907 | const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED |
6908 | | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
ec378aee NHE |
6909 | |
6910 | /* The Intel VMX Instruction Reference lists a bunch of bits that | |
6911 | * are prerequisite to running VMXON, most notably cr4.VMXE must be | |
6912 | * set to 1 (see vmx_set_cr4() for when we allow the guest to set this). | |
6913 | * Otherwise, we should fail with #UD. We test these now: | |
6914 | */ | |
6915 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) || | |
6916 | !kvm_read_cr0_bits(vcpu, X86_CR0_PE) || | |
6917 | (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { | |
6918 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6919 | return 1; | |
6920 | } | |
6921 | ||
6922 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
6923 | if (is_long_mode(vcpu) && !cs.l) { | |
6924 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6925 | return 1; | |
6926 | } | |
6927 | ||
6928 | if (vmx_get_cpl(vcpu)) { | |
6929 | kvm_inject_gp(vcpu, 0); | |
6930 | return 1; | |
6931 | } | |
3573e22c | 6932 | |
4291b588 | 6933 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL)) |
3573e22c BD |
6934 | return 1; |
6935 | ||
145c28dd AG |
6936 | if (vmx->nested.vmxon) { |
6937 | nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); | |
6938 | skip_emulated_instruction(vcpu); | |
6939 | return 1; | |
6940 | } | |
b3897a49 NHE |
6941 | |
6942 | if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES) | |
6943 | != VMXON_NEEDED_FEATURES) { | |
6944 | kvm_inject_gp(vcpu, 0); | |
6945 | return 1; | |
6946 | } | |
6947 | ||
8de48833 AG |
6948 | if (enable_shadow_vmcs) { |
6949 | shadow_vmcs = alloc_vmcs(); | |
6950 | if (!shadow_vmcs) | |
6951 | return -ENOMEM; | |
6952 | /* mark vmcs as shadow */ | |
6953 | shadow_vmcs->revision_id |= (1u << 31); | |
6954 | /* init shadow vmcs */ | |
6955 | vmcs_clear(shadow_vmcs); | |
6956 | vmx->nested.current_shadow_vmcs = shadow_vmcs; | |
6957 | } | |
ec378aee | 6958 | |
ff2f6fe9 NHE |
6959 | INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool)); |
6960 | vmx->nested.vmcs02_num = 0; | |
6961 | ||
f4124500 JK |
6962 | hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, |
6963 | HRTIMER_MODE_REL); | |
6964 | vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; | |
6965 | ||
ec378aee NHE |
6966 | vmx->nested.vmxon = true; |
6967 | ||
6968 | skip_emulated_instruction(vcpu); | |
a25eb114 | 6969 | nested_vmx_succeed(vcpu); |
ec378aee NHE |
6970 | return 1; |
6971 | } | |
6972 | ||
6973 | /* | |
6974 | * Intel's VMX Instruction Reference specifies a common set of prerequisites | |
6975 | * for running VMX instructions (except VMXON, whose prerequisites are | |
6976 | * slightly different). It also specifies what exception to inject otherwise. | |
6977 | */ | |
6978 | static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) | |
6979 | { | |
6980 | struct kvm_segment cs; | |
6981 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6982 | ||
6983 | if (!vmx->nested.vmxon) { | |
6984 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6985 | return 0; | |
6986 | } | |
6987 | ||
6988 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
6989 | if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) || | |
6990 | (is_long_mode(vcpu) && !cs.l)) { | |
6991 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6992 | return 0; | |
6993 | } | |
6994 | ||
6995 | if (vmx_get_cpl(vcpu)) { | |
6996 | kvm_inject_gp(vcpu, 0); | |
6997 | return 0; | |
6998 | } | |
6999 | ||
7000 | return 1; | |
7001 | } | |
7002 | ||
e7953d7f AG |
7003 | static inline void nested_release_vmcs12(struct vcpu_vmx *vmx) |
7004 | { | |
9a2a05b9 PB |
7005 | if (vmx->nested.current_vmptr == -1ull) |
7006 | return; | |
7007 | ||
7008 | /* current_vmptr and current_vmcs12 are always set/reset together */ | |
7009 | if (WARN_ON(vmx->nested.current_vmcs12 == NULL)) | |
7010 | return; | |
7011 | ||
012f83cb | 7012 | if (enable_shadow_vmcs) { |
9a2a05b9 PB |
7013 | /* copy to memory all shadowed fields in case |
7014 | they were modified */ | |
7015 | copy_shadow_to_vmcs12(vmx); | |
7016 | vmx->nested.sync_shadow_vmcs = false; | |
7ec36296 XG |
7017 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, |
7018 | SECONDARY_EXEC_SHADOW_VMCS); | |
9a2a05b9 | 7019 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
012f83cb | 7020 | } |
705699a1 | 7021 | vmx->nested.posted_intr_nv = -1; |
e7953d7f AG |
7022 | kunmap(vmx->nested.current_vmcs12_page); |
7023 | nested_release_page(vmx->nested.current_vmcs12_page); | |
9a2a05b9 PB |
7024 | vmx->nested.current_vmptr = -1ull; |
7025 | vmx->nested.current_vmcs12 = NULL; | |
e7953d7f AG |
7026 | } |
7027 | ||
ec378aee NHE |
7028 | /* |
7029 | * Free whatever needs to be freed from vmx->nested when L1 goes down, or | |
7030 | * just stops using VMX. | |
7031 | */ | |
7032 | static void free_nested(struct vcpu_vmx *vmx) | |
7033 | { | |
7034 | if (!vmx->nested.vmxon) | |
7035 | return; | |
9a2a05b9 | 7036 | |
ec378aee | 7037 | vmx->nested.vmxon = false; |
5c614b35 | 7038 | free_vpid(vmx->nested.vpid02); |
9a2a05b9 | 7039 | nested_release_vmcs12(vmx); |
e7953d7f AG |
7040 | if (enable_shadow_vmcs) |
7041 | free_vmcs(vmx->nested.current_shadow_vmcs); | |
fe3ef05c NHE |
7042 | /* Unpin physical memory we referred to in current vmcs02 */ |
7043 | if (vmx->nested.apic_access_page) { | |
7044 | nested_release_page(vmx->nested.apic_access_page); | |
48d89b92 | 7045 | vmx->nested.apic_access_page = NULL; |
fe3ef05c | 7046 | } |
a7c0b07d WL |
7047 | if (vmx->nested.virtual_apic_page) { |
7048 | nested_release_page(vmx->nested.virtual_apic_page); | |
48d89b92 | 7049 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 7050 | } |
705699a1 WV |
7051 | if (vmx->nested.pi_desc_page) { |
7052 | kunmap(vmx->nested.pi_desc_page); | |
7053 | nested_release_page(vmx->nested.pi_desc_page); | |
7054 | vmx->nested.pi_desc_page = NULL; | |
7055 | vmx->nested.pi_desc = NULL; | |
7056 | } | |
ff2f6fe9 NHE |
7057 | |
7058 | nested_free_all_saved_vmcss(vmx); | |
ec378aee NHE |
7059 | } |
7060 | ||
7061 | /* Emulate the VMXOFF instruction */ | |
7062 | static int handle_vmoff(struct kvm_vcpu *vcpu) | |
7063 | { | |
7064 | if (!nested_vmx_check_permission(vcpu)) | |
7065 | return 1; | |
7066 | free_nested(to_vmx(vcpu)); | |
7067 | skip_emulated_instruction(vcpu); | |
a25eb114 | 7068 | nested_vmx_succeed(vcpu); |
ec378aee NHE |
7069 | return 1; |
7070 | } | |
7071 | ||
27d6c865 NHE |
7072 | /* Emulate the VMCLEAR instruction */ |
7073 | static int handle_vmclear(struct kvm_vcpu *vcpu) | |
7074 | { | |
7075 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
27d6c865 NHE |
7076 | gpa_t vmptr; |
7077 | struct vmcs12 *vmcs12; | |
7078 | struct page *page; | |
27d6c865 NHE |
7079 | |
7080 | if (!nested_vmx_check_permission(vcpu)) | |
7081 | return 1; | |
7082 | ||
4291b588 | 7083 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr)) |
27d6c865 | 7084 | return 1; |
27d6c865 | 7085 | |
9a2a05b9 | 7086 | if (vmptr == vmx->nested.current_vmptr) |
e7953d7f | 7087 | nested_release_vmcs12(vmx); |
27d6c865 NHE |
7088 | |
7089 | page = nested_get_page(vcpu, vmptr); | |
7090 | if (page == NULL) { | |
7091 | /* | |
7092 | * For accurate processor emulation, VMCLEAR beyond available | |
7093 | * physical memory should do nothing at all. However, it is | |
7094 | * possible that a nested vmx bug, not a guest hypervisor bug, | |
7095 | * resulted in this case, so let's shut down before doing any | |
7096 | * more damage: | |
7097 | */ | |
7098 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
7099 | return 1; | |
7100 | } | |
7101 | vmcs12 = kmap(page); | |
7102 | vmcs12->launch_state = 0; | |
7103 | kunmap(page); | |
7104 | nested_release_page(page); | |
7105 | ||
7106 | nested_free_vmcs02(vmx, vmptr); | |
7107 | ||
7108 | skip_emulated_instruction(vcpu); | |
7109 | nested_vmx_succeed(vcpu); | |
7110 | return 1; | |
7111 | } | |
7112 | ||
cd232ad0 NHE |
7113 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch); |
7114 | ||
7115 | /* Emulate the VMLAUNCH instruction */ | |
7116 | static int handle_vmlaunch(struct kvm_vcpu *vcpu) | |
7117 | { | |
7118 | return nested_vmx_run(vcpu, true); | |
7119 | } | |
7120 | ||
7121 | /* Emulate the VMRESUME instruction */ | |
7122 | static int handle_vmresume(struct kvm_vcpu *vcpu) | |
7123 | { | |
7124 | ||
7125 | return nested_vmx_run(vcpu, false); | |
7126 | } | |
7127 | ||
49f705c5 NHE |
7128 | enum vmcs_field_type { |
7129 | VMCS_FIELD_TYPE_U16 = 0, | |
7130 | VMCS_FIELD_TYPE_U64 = 1, | |
7131 | VMCS_FIELD_TYPE_U32 = 2, | |
7132 | VMCS_FIELD_TYPE_NATURAL_WIDTH = 3 | |
7133 | }; | |
7134 | ||
7135 | static inline int vmcs_field_type(unsigned long field) | |
7136 | { | |
7137 | if (0x1 & field) /* the *_HIGH fields are all 32 bit */ | |
7138 | return VMCS_FIELD_TYPE_U32; | |
7139 | return (field >> 13) & 0x3 ; | |
7140 | } | |
7141 | ||
7142 | static inline int vmcs_field_readonly(unsigned long field) | |
7143 | { | |
7144 | return (((field >> 10) & 0x3) == 1); | |
7145 | } | |
7146 | ||
7147 | /* | |
7148 | * Read a vmcs12 field. Since these can have varying lengths and we return | |
7149 | * one type, we chose the biggest type (u64) and zero-extend the return value | |
7150 | * to that size. Note that the caller, handle_vmread, might need to use only | |
7151 | * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of | |
7152 | * 64-bit fields are to be returned). | |
7153 | */ | |
a2ae9df7 PB |
7154 | static inline int vmcs12_read_any(struct kvm_vcpu *vcpu, |
7155 | unsigned long field, u64 *ret) | |
49f705c5 NHE |
7156 | { |
7157 | short offset = vmcs_field_to_offset(field); | |
7158 | char *p; | |
7159 | ||
7160 | if (offset < 0) | |
a2ae9df7 | 7161 | return offset; |
49f705c5 NHE |
7162 | |
7163 | p = ((char *)(get_vmcs12(vcpu))) + offset; | |
7164 | ||
7165 | switch (vmcs_field_type(field)) { | |
7166 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7167 | *ret = *((natural_width *)p); | |
a2ae9df7 | 7168 | return 0; |
49f705c5 NHE |
7169 | case VMCS_FIELD_TYPE_U16: |
7170 | *ret = *((u16 *)p); | |
a2ae9df7 | 7171 | return 0; |
49f705c5 NHE |
7172 | case VMCS_FIELD_TYPE_U32: |
7173 | *ret = *((u32 *)p); | |
a2ae9df7 | 7174 | return 0; |
49f705c5 NHE |
7175 | case VMCS_FIELD_TYPE_U64: |
7176 | *ret = *((u64 *)p); | |
a2ae9df7 | 7177 | return 0; |
49f705c5 | 7178 | default: |
a2ae9df7 PB |
7179 | WARN_ON(1); |
7180 | return -ENOENT; | |
49f705c5 NHE |
7181 | } |
7182 | } | |
7183 | ||
20b97fea | 7184 | |
a2ae9df7 PB |
7185 | static inline int vmcs12_write_any(struct kvm_vcpu *vcpu, |
7186 | unsigned long field, u64 field_value){ | |
20b97fea AG |
7187 | short offset = vmcs_field_to_offset(field); |
7188 | char *p = ((char *) get_vmcs12(vcpu)) + offset; | |
7189 | if (offset < 0) | |
a2ae9df7 | 7190 | return offset; |
20b97fea AG |
7191 | |
7192 | switch (vmcs_field_type(field)) { | |
7193 | case VMCS_FIELD_TYPE_U16: | |
7194 | *(u16 *)p = field_value; | |
a2ae9df7 | 7195 | return 0; |
20b97fea AG |
7196 | case VMCS_FIELD_TYPE_U32: |
7197 | *(u32 *)p = field_value; | |
a2ae9df7 | 7198 | return 0; |
20b97fea AG |
7199 | case VMCS_FIELD_TYPE_U64: |
7200 | *(u64 *)p = field_value; | |
a2ae9df7 | 7201 | return 0; |
20b97fea AG |
7202 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: |
7203 | *(natural_width *)p = field_value; | |
a2ae9df7 | 7204 | return 0; |
20b97fea | 7205 | default: |
a2ae9df7 PB |
7206 | WARN_ON(1); |
7207 | return -ENOENT; | |
20b97fea AG |
7208 | } |
7209 | ||
7210 | } | |
7211 | ||
16f5b903 AG |
7212 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) |
7213 | { | |
7214 | int i; | |
7215 | unsigned long field; | |
7216 | u64 field_value; | |
7217 | struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs; | |
c2bae893 MK |
7218 | const unsigned long *fields = shadow_read_write_fields; |
7219 | const int num_fields = max_shadow_read_write_fields; | |
16f5b903 | 7220 | |
282da870 JK |
7221 | preempt_disable(); |
7222 | ||
16f5b903 AG |
7223 | vmcs_load(shadow_vmcs); |
7224 | ||
7225 | for (i = 0; i < num_fields; i++) { | |
7226 | field = fields[i]; | |
7227 | switch (vmcs_field_type(field)) { | |
7228 | case VMCS_FIELD_TYPE_U16: | |
7229 | field_value = vmcs_read16(field); | |
7230 | break; | |
7231 | case VMCS_FIELD_TYPE_U32: | |
7232 | field_value = vmcs_read32(field); | |
7233 | break; | |
7234 | case VMCS_FIELD_TYPE_U64: | |
7235 | field_value = vmcs_read64(field); | |
7236 | break; | |
7237 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7238 | field_value = vmcs_readl(field); | |
7239 | break; | |
a2ae9df7 PB |
7240 | default: |
7241 | WARN_ON(1); | |
7242 | continue; | |
16f5b903 AG |
7243 | } |
7244 | vmcs12_write_any(&vmx->vcpu, field, field_value); | |
7245 | } | |
7246 | ||
7247 | vmcs_clear(shadow_vmcs); | |
7248 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
282da870 JK |
7249 | |
7250 | preempt_enable(); | |
16f5b903 AG |
7251 | } |
7252 | ||
c3114420 AG |
7253 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) |
7254 | { | |
c2bae893 MK |
7255 | const unsigned long *fields[] = { |
7256 | shadow_read_write_fields, | |
7257 | shadow_read_only_fields | |
c3114420 | 7258 | }; |
c2bae893 | 7259 | const int max_fields[] = { |
c3114420 AG |
7260 | max_shadow_read_write_fields, |
7261 | max_shadow_read_only_fields | |
7262 | }; | |
7263 | int i, q; | |
7264 | unsigned long field; | |
7265 | u64 field_value = 0; | |
7266 | struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs; | |
7267 | ||
7268 | vmcs_load(shadow_vmcs); | |
7269 | ||
c2bae893 | 7270 | for (q = 0; q < ARRAY_SIZE(fields); q++) { |
c3114420 AG |
7271 | for (i = 0; i < max_fields[q]; i++) { |
7272 | field = fields[q][i]; | |
7273 | vmcs12_read_any(&vmx->vcpu, field, &field_value); | |
7274 | ||
7275 | switch (vmcs_field_type(field)) { | |
7276 | case VMCS_FIELD_TYPE_U16: | |
7277 | vmcs_write16(field, (u16)field_value); | |
7278 | break; | |
7279 | case VMCS_FIELD_TYPE_U32: | |
7280 | vmcs_write32(field, (u32)field_value); | |
7281 | break; | |
7282 | case VMCS_FIELD_TYPE_U64: | |
7283 | vmcs_write64(field, (u64)field_value); | |
7284 | break; | |
7285 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7286 | vmcs_writel(field, (long)field_value); | |
7287 | break; | |
a2ae9df7 PB |
7288 | default: |
7289 | WARN_ON(1); | |
7290 | break; | |
c3114420 AG |
7291 | } |
7292 | } | |
7293 | } | |
7294 | ||
7295 | vmcs_clear(shadow_vmcs); | |
7296 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
7297 | } | |
7298 | ||
49f705c5 NHE |
7299 | /* |
7300 | * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was | |
7301 | * used before) all generate the same failure when it is missing. | |
7302 | */ | |
7303 | static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu) | |
7304 | { | |
7305 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7306 | if (vmx->nested.current_vmptr == -1ull) { | |
7307 | nested_vmx_failInvalid(vcpu); | |
7308 | skip_emulated_instruction(vcpu); | |
7309 | return 0; | |
7310 | } | |
7311 | return 1; | |
7312 | } | |
7313 | ||
7314 | static int handle_vmread(struct kvm_vcpu *vcpu) | |
7315 | { | |
7316 | unsigned long field; | |
7317 | u64 field_value; | |
7318 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7319 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7320 | gva_t gva = 0; | |
7321 | ||
7322 | if (!nested_vmx_check_permission(vcpu) || | |
7323 | !nested_vmx_check_vmcs12(vcpu)) | |
7324 | return 1; | |
7325 | ||
7326 | /* Decode instruction info and find the field to read */ | |
27e6fb5d | 7327 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 | 7328 | /* Read the field, zero-extended to a u64 field_value */ |
a2ae9df7 | 7329 | if (vmcs12_read_any(vcpu, field, &field_value) < 0) { |
49f705c5 NHE |
7330 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
7331 | skip_emulated_instruction(vcpu); | |
7332 | return 1; | |
7333 | } | |
7334 | /* | |
7335 | * Now copy part of this value to register or memory, as requested. | |
7336 | * Note that the number of bits actually copied is 32 or 64 depending | |
7337 | * on the guest's mode (32 or 64 bit), not on the given field's length. | |
7338 | */ | |
7339 | if (vmx_instruction_info & (1u << 10)) { | |
27e6fb5d | 7340 | kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf), |
49f705c5 NHE |
7341 | field_value); |
7342 | } else { | |
7343 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7344 | vmx_instruction_info, true, &gva)) |
49f705c5 NHE |
7345 | return 1; |
7346 | /* _system ok, as nested_vmx_check_permission verified cpl=0 */ | |
7347 | kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva, | |
7348 | &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL); | |
7349 | } | |
7350 | ||
7351 | nested_vmx_succeed(vcpu); | |
7352 | skip_emulated_instruction(vcpu); | |
7353 | return 1; | |
7354 | } | |
7355 | ||
7356 | ||
7357 | static int handle_vmwrite(struct kvm_vcpu *vcpu) | |
7358 | { | |
7359 | unsigned long field; | |
7360 | gva_t gva; | |
7361 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7362 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
49f705c5 NHE |
7363 | /* The value to write might be 32 or 64 bits, depending on L1's long |
7364 | * mode, and eventually we need to write that into a field of several | |
7365 | * possible lengths. The code below first zero-extends the value to 64 | |
6a6256f9 | 7366 | * bit (field_value), and then copies only the appropriate number of |
49f705c5 NHE |
7367 | * bits into the vmcs12 field. |
7368 | */ | |
7369 | u64 field_value = 0; | |
7370 | struct x86_exception e; | |
7371 | ||
7372 | if (!nested_vmx_check_permission(vcpu) || | |
7373 | !nested_vmx_check_vmcs12(vcpu)) | |
7374 | return 1; | |
7375 | ||
7376 | if (vmx_instruction_info & (1u << 10)) | |
27e6fb5d | 7377 | field_value = kvm_register_readl(vcpu, |
49f705c5 NHE |
7378 | (((vmx_instruction_info) >> 3) & 0xf)); |
7379 | else { | |
7380 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7381 | vmx_instruction_info, false, &gva)) |
49f705c5 NHE |
7382 | return 1; |
7383 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, | |
27e6fb5d | 7384 | &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) { |
49f705c5 NHE |
7385 | kvm_inject_page_fault(vcpu, &e); |
7386 | return 1; | |
7387 | } | |
7388 | } | |
7389 | ||
7390 | ||
27e6fb5d | 7391 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 NHE |
7392 | if (vmcs_field_readonly(field)) { |
7393 | nested_vmx_failValid(vcpu, | |
7394 | VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); | |
7395 | skip_emulated_instruction(vcpu); | |
7396 | return 1; | |
7397 | } | |
7398 | ||
a2ae9df7 | 7399 | if (vmcs12_write_any(vcpu, field, field_value) < 0) { |
49f705c5 NHE |
7400 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
7401 | skip_emulated_instruction(vcpu); | |
7402 | return 1; | |
7403 | } | |
7404 | ||
7405 | nested_vmx_succeed(vcpu); | |
7406 | skip_emulated_instruction(vcpu); | |
7407 | return 1; | |
7408 | } | |
7409 | ||
63846663 NHE |
7410 | /* Emulate the VMPTRLD instruction */ |
7411 | static int handle_vmptrld(struct kvm_vcpu *vcpu) | |
7412 | { | |
7413 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
63846663 | 7414 | gpa_t vmptr; |
63846663 NHE |
7415 | |
7416 | if (!nested_vmx_check_permission(vcpu)) | |
7417 | return 1; | |
7418 | ||
4291b588 | 7419 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr)) |
63846663 | 7420 | return 1; |
63846663 NHE |
7421 | |
7422 | if (vmx->nested.current_vmptr != vmptr) { | |
7423 | struct vmcs12 *new_vmcs12; | |
7424 | struct page *page; | |
7425 | page = nested_get_page(vcpu, vmptr); | |
7426 | if (page == NULL) { | |
7427 | nested_vmx_failInvalid(vcpu); | |
7428 | skip_emulated_instruction(vcpu); | |
7429 | return 1; | |
7430 | } | |
7431 | new_vmcs12 = kmap(page); | |
7432 | if (new_vmcs12->revision_id != VMCS12_REVISION) { | |
7433 | kunmap(page); | |
7434 | nested_release_page_clean(page); | |
7435 | nested_vmx_failValid(vcpu, | |
7436 | VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); | |
7437 | skip_emulated_instruction(vcpu); | |
7438 | return 1; | |
7439 | } | |
63846663 | 7440 | |
9a2a05b9 | 7441 | nested_release_vmcs12(vmx); |
63846663 NHE |
7442 | vmx->nested.current_vmptr = vmptr; |
7443 | vmx->nested.current_vmcs12 = new_vmcs12; | |
7444 | vmx->nested.current_vmcs12_page = page; | |
012f83cb | 7445 | if (enable_shadow_vmcs) { |
7ec36296 XG |
7446 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, |
7447 | SECONDARY_EXEC_SHADOW_VMCS); | |
8a1b9dd0 AG |
7448 | vmcs_write64(VMCS_LINK_POINTER, |
7449 | __pa(vmx->nested.current_shadow_vmcs)); | |
012f83cb AG |
7450 | vmx->nested.sync_shadow_vmcs = true; |
7451 | } | |
63846663 NHE |
7452 | } |
7453 | ||
7454 | nested_vmx_succeed(vcpu); | |
7455 | skip_emulated_instruction(vcpu); | |
7456 | return 1; | |
7457 | } | |
7458 | ||
6a4d7550 NHE |
7459 | /* Emulate the VMPTRST instruction */ |
7460 | static int handle_vmptrst(struct kvm_vcpu *vcpu) | |
7461 | { | |
7462 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7463 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7464 | gva_t vmcs_gva; | |
7465 | struct x86_exception e; | |
7466 | ||
7467 | if (!nested_vmx_check_permission(vcpu)) | |
7468 | return 1; | |
7469 | ||
7470 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7471 | vmx_instruction_info, true, &vmcs_gva)) |
6a4d7550 NHE |
7472 | return 1; |
7473 | /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */ | |
7474 | if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva, | |
7475 | (void *)&to_vmx(vcpu)->nested.current_vmptr, | |
7476 | sizeof(u64), &e)) { | |
7477 | kvm_inject_page_fault(vcpu, &e); | |
7478 | return 1; | |
7479 | } | |
7480 | nested_vmx_succeed(vcpu); | |
7481 | skip_emulated_instruction(vcpu); | |
7482 | return 1; | |
7483 | } | |
7484 | ||
bfd0a56b NHE |
7485 | /* Emulate the INVEPT instruction */ |
7486 | static int handle_invept(struct kvm_vcpu *vcpu) | |
7487 | { | |
b9c237bb | 7488 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
bfd0a56b NHE |
7489 | u32 vmx_instruction_info, types; |
7490 | unsigned long type; | |
7491 | gva_t gva; | |
7492 | struct x86_exception e; | |
7493 | struct { | |
7494 | u64 eptp, gpa; | |
7495 | } operand; | |
bfd0a56b | 7496 | |
b9c237bb WV |
7497 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & |
7498 | SECONDARY_EXEC_ENABLE_EPT) || | |
7499 | !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) { | |
bfd0a56b NHE |
7500 | kvm_queue_exception(vcpu, UD_VECTOR); |
7501 | return 1; | |
7502 | } | |
7503 | ||
7504 | if (!nested_vmx_check_permission(vcpu)) | |
7505 | return 1; | |
7506 | ||
7507 | if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) { | |
7508 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7509 | return 1; | |
7510 | } | |
7511 | ||
7512 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
27e6fb5d | 7513 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); |
bfd0a56b | 7514 | |
b9c237bb | 7515 | types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; |
bfd0a56b NHE |
7516 | |
7517 | if (!(types & (1UL << type))) { | |
7518 | nested_vmx_failValid(vcpu, | |
7519 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
2849eb4f | 7520 | skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
7521 | return 1; |
7522 | } | |
7523 | ||
7524 | /* According to the Intel VMX instruction reference, the memory | |
7525 | * operand is read even if it isn't needed (e.g., for type==global) | |
7526 | */ | |
7527 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7528 | vmx_instruction_info, false, &gva)) |
bfd0a56b NHE |
7529 | return 1; |
7530 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand, | |
7531 | sizeof(operand), &e)) { | |
7532 | kvm_inject_page_fault(vcpu, &e); | |
7533 | return 1; | |
7534 | } | |
7535 | ||
7536 | switch (type) { | |
bfd0a56b NHE |
7537 | case VMX_EPT_EXTENT_GLOBAL: |
7538 | kvm_mmu_sync_roots(vcpu); | |
77c3913b | 7539 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
bfd0a56b NHE |
7540 | nested_vmx_succeed(vcpu); |
7541 | break; | |
7542 | default: | |
4b855078 | 7543 | /* Trap single context invalidation invept calls */ |
bfd0a56b NHE |
7544 | BUG_ON(1); |
7545 | break; | |
7546 | } | |
7547 | ||
7548 | skip_emulated_instruction(vcpu); | |
7549 | return 1; | |
7550 | } | |
7551 | ||
a642fc30 PM |
7552 | static int handle_invvpid(struct kvm_vcpu *vcpu) |
7553 | { | |
99b83ac8 WL |
7554 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7555 | u32 vmx_instruction_info; | |
7556 | unsigned long type, types; | |
7557 | gva_t gva; | |
7558 | struct x86_exception e; | |
7559 | int vpid; | |
7560 | ||
7561 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & | |
7562 | SECONDARY_EXEC_ENABLE_VPID) || | |
7563 | !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) { | |
7564 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7565 | return 1; | |
7566 | } | |
7567 | ||
7568 | if (!nested_vmx_check_permission(vcpu)) | |
7569 | return 1; | |
7570 | ||
7571 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7572 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); | |
7573 | ||
7574 | types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7; | |
7575 | ||
7576 | if (!(types & (1UL << type))) { | |
7577 | nested_vmx_failValid(vcpu, | |
7578 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
f6870ee9 | 7579 | skip_emulated_instruction(vcpu); |
99b83ac8 WL |
7580 | return 1; |
7581 | } | |
7582 | ||
7583 | /* according to the intel vmx instruction reference, the memory | |
7584 | * operand is read even if it isn't needed (e.g., for type==global) | |
7585 | */ | |
7586 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
7587 | vmx_instruction_info, false, &gva)) | |
7588 | return 1; | |
7589 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid, | |
7590 | sizeof(u32), &e)) { | |
7591 | kvm_inject_page_fault(vcpu, &e); | |
7592 | return 1; | |
7593 | } | |
7594 | ||
7595 | switch (type) { | |
ef697a71 PB |
7596 | case VMX_VPID_EXTENT_SINGLE_CONTEXT: |
7597 | /* | |
7598 | * Old versions of KVM use the single-context version so we | |
7599 | * have to support it; just treat it the same as all-context. | |
7600 | */ | |
99b83ac8 | 7601 | case VMX_VPID_EXTENT_ALL_CONTEXT: |
5c614b35 | 7602 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02); |
99b83ac8 WL |
7603 | nested_vmx_succeed(vcpu); |
7604 | break; | |
7605 | default: | |
ef697a71 | 7606 | /* Trap individual address invalidation invvpid calls */ |
99b83ac8 WL |
7607 | BUG_ON(1); |
7608 | break; | |
7609 | } | |
7610 | ||
7611 | skip_emulated_instruction(vcpu); | |
a642fc30 PM |
7612 | return 1; |
7613 | } | |
7614 | ||
843e4330 KH |
7615 | static int handle_pml_full(struct kvm_vcpu *vcpu) |
7616 | { | |
7617 | unsigned long exit_qualification; | |
7618 | ||
7619 | trace_kvm_pml_full(vcpu->vcpu_id); | |
7620 | ||
7621 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7622 | ||
7623 | /* | |
7624 | * PML buffer FULL happened while executing iret from NMI, | |
7625 | * "blocked by NMI" bit has to be set before next VM entry. | |
7626 | */ | |
7627 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && | |
7628 | cpu_has_virtual_nmis() && | |
7629 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) | |
7630 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
7631 | GUEST_INTR_STATE_NMI); | |
7632 | ||
7633 | /* | |
7634 | * PML buffer already flushed at beginning of VMEXIT. Nothing to do | |
7635 | * here.., and there's no userspace involvement needed for PML. | |
7636 | */ | |
7637 | return 1; | |
7638 | } | |
7639 | ||
8b3e34e4 XG |
7640 | static int handle_pcommit(struct kvm_vcpu *vcpu) |
7641 | { | |
7642 | /* we never catch pcommit instruct for L1 guest. */ | |
7643 | WARN_ON(1); | |
7644 | return 1; | |
7645 | } | |
7646 | ||
64672c95 YJ |
7647 | static int handle_preemption_timer(struct kvm_vcpu *vcpu) |
7648 | { | |
7649 | kvm_lapic_expired_hv_timer(vcpu); | |
7650 | return 1; | |
7651 | } | |
7652 | ||
6aa8b732 AK |
7653 | /* |
7654 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
7655 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
7656 | * to be done to userspace and return 0. | |
7657 | */ | |
772e0318 | 7658 | static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
7659 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
7660 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 7661 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 7662 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 7663 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
7664 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
7665 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
7666 | [EXIT_REASON_CPUID] = handle_cpuid, | |
7667 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
7668 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
7669 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
7670 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 7671 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 7672 | [EXIT_REASON_INVLPG] = handle_invlpg, |
fee84b07 | 7673 | [EXIT_REASON_RDPMC] = handle_rdpmc, |
c21415e8 | 7674 | [EXIT_REASON_VMCALL] = handle_vmcall, |
27d6c865 | 7675 | [EXIT_REASON_VMCLEAR] = handle_vmclear, |
cd232ad0 | 7676 | [EXIT_REASON_VMLAUNCH] = handle_vmlaunch, |
63846663 | 7677 | [EXIT_REASON_VMPTRLD] = handle_vmptrld, |
6a4d7550 | 7678 | [EXIT_REASON_VMPTRST] = handle_vmptrst, |
49f705c5 | 7679 | [EXIT_REASON_VMREAD] = handle_vmread, |
cd232ad0 | 7680 | [EXIT_REASON_VMRESUME] = handle_vmresume, |
49f705c5 | 7681 | [EXIT_REASON_VMWRITE] = handle_vmwrite, |
ec378aee NHE |
7682 | [EXIT_REASON_VMOFF] = handle_vmoff, |
7683 | [EXIT_REASON_VMON] = handle_vmon, | |
f78e0e2e SY |
7684 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
7685 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
83d4c286 | 7686 | [EXIT_REASON_APIC_WRITE] = handle_apic_write, |
c7c9c56c | 7687 | [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, |
e5edaa01 | 7688 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 7689 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 7690 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 7691 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
7692 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
7693 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 7694 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
87c00572 | 7695 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, |
5f3d45e7 | 7696 | [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, |
87c00572 | 7697 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, |
bfd0a56b | 7698 | [EXIT_REASON_INVEPT] = handle_invept, |
a642fc30 | 7699 | [EXIT_REASON_INVVPID] = handle_invvpid, |
f53cd63c WL |
7700 | [EXIT_REASON_XSAVES] = handle_xsaves, |
7701 | [EXIT_REASON_XRSTORS] = handle_xrstors, | |
843e4330 | 7702 | [EXIT_REASON_PML_FULL] = handle_pml_full, |
8b3e34e4 | 7703 | [EXIT_REASON_PCOMMIT] = handle_pcommit, |
64672c95 | 7704 | [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, |
6aa8b732 AK |
7705 | }; |
7706 | ||
7707 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 7708 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 7709 | |
908a7bdd JK |
7710 | static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, |
7711 | struct vmcs12 *vmcs12) | |
7712 | { | |
7713 | unsigned long exit_qualification; | |
7714 | gpa_t bitmap, last_bitmap; | |
7715 | unsigned int port; | |
7716 | int size; | |
7717 | u8 b; | |
7718 | ||
908a7bdd | 7719 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) |
2f0a6397 | 7720 | return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); |
908a7bdd JK |
7721 | |
7722 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7723 | ||
7724 | port = exit_qualification >> 16; | |
7725 | size = (exit_qualification & 7) + 1; | |
7726 | ||
7727 | last_bitmap = (gpa_t)-1; | |
7728 | b = -1; | |
7729 | ||
7730 | while (size > 0) { | |
7731 | if (port < 0x8000) | |
7732 | bitmap = vmcs12->io_bitmap_a; | |
7733 | else if (port < 0x10000) | |
7734 | bitmap = vmcs12->io_bitmap_b; | |
7735 | else | |
1d804d07 | 7736 | return true; |
908a7bdd JK |
7737 | bitmap += (port & 0x7fff) / 8; |
7738 | ||
7739 | if (last_bitmap != bitmap) | |
54bf36aa | 7740 | if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1)) |
1d804d07 | 7741 | return true; |
908a7bdd | 7742 | if (b & (1 << (port & 7))) |
1d804d07 | 7743 | return true; |
908a7bdd JK |
7744 | |
7745 | port++; | |
7746 | size--; | |
7747 | last_bitmap = bitmap; | |
7748 | } | |
7749 | ||
1d804d07 | 7750 | return false; |
908a7bdd JK |
7751 | } |
7752 | ||
644d711a NHE |
7753 | /* |
7754 | * Return 1 if we should exit from L2 to L1 to handle an MSR access access, | |
7755 | * rather than handle it ourselves in L0. I.e., check whether L1 expressed | |
7756 | * disinterest in the current event (read or write a specific MSR) by using an | |
7757 | * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. | |
7758 | */ | |
7759 | static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, | |
7760 | struct vmcs12 *vmcs12, u32 exit_reason) | |
7761 | { | |
7762 | u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
7763 | gpa_t bitmap; | |
7764 | ||
cbd29cb6 | 7765 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
1d804d07 | 7766 | return true; |
644d711a NHE |
7767 | |
7768 | /* | |
7769 | * The MSR_BITMAP page is divided into four 1024-byte bitmaps, | |
7770 | * for the four combinations of read/write and low/high MSR numbers. | |
7771 | * First we need to figure out which of the four to use: | |
7772 | */ | |
7773 | bitmap = vmcs12->msr_bitmap; | |
7774 | if (exit_reason == EXIT_REASON_MSR_WRITE) | |
7775 | bitmap += 2048; | |
7776 | if (msr_index >= 0xc0000000) { | |
7777 | msr_index -= 0xc0000000; | |
7778 | bitmap += 1024; | |
7779 | } | |
7780 | ||
7781 | /* Then read the msr_index'th bit from this bitmap: */ | |
7782 | if (msr_index < 1024*8) { | |
7783 | unsigned char b; | |
54bf36aa | 7784 | if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1)) |
1d804d07 | 7785 | return true; |
644d711a NHE |
7786 | return 1 & (b >> (msr_index & 7)); |
7787 | } else | |
1d804d07 | 7788 | return true; /* let L1 handle the wrong parameter */ |
644d711a NHE |
7789 | } |
7790 | ||
7791 | /* | |
7792 | * Return 1 if we should exit from L2 to L1 to handle a CR access exit, | |
7793 | * rather than handle it ourselves in L0. I.e., check if L1 wanted to | |
7794 | * intercept (via guest_host_mask etc.) the current event. | |
7795 | */ | |
7796 | static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, | |
7797 | struct vmcs12 *vmcs12) | |
7798 | { | |
7799 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7800 | int cr = exit_qualification & 15; | |
7801 | int reg = (exit_qualification >> 8) & 15; | |
1e32c079 | 7802 | unsigned long val = kvm_register_readl(vcpu, reg); |
644d711a NHE |
7803 | |
7804 | switch ((exit_qualification >> 4) & 3) { | |
7805 | case 0: /* mov to cr */ | |
7806 | switch (cr) { | |
7807 | case 0: | |
7808 | if (vmcs12->cr0_guest_host_mask & | |
7809 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 7810 | return true; |
644d711a NHE |
7811 | break; |
7812 | case 3: | |
7813 | if ((vmcs12->cr3_target_count >= 1 && | |
7814 | vmcs12->cr3_target_value0 == val) || | |
7815 | (vmcs12->cr3_target_count >= 2 && | |
7816 | vmcs12->cr3_target_value1 == val) || | |
7817 | (vmcs12->cr3_target_count >= 3 && | |
7818 | vmcs12->cr3_target_value2 == val) || | |
7819 | (vmcs12->cr3_target_count >= 4 && | |
7820 | vmcs12->cr3_target_value3 == val)) | |
1d804d07 | 7821 | return false; |
644d711a | 7822 | if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) |
1d804d07 | 7823 | return true; |
644d711a NHE |
7824 | break; |
7825 | case 4: | |
7826 | if (vmcs12->cr4_guest_host_mask & | |
7827 | (vmcs12->cr4_read_shadow ^ val)) | |
1d804d07 | 7828 | return true; |
644d711a NHE |
7829 | break; |
7830 | case 8: | |
7831 | if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) | |
1d804d07 | 7832 | return true; |
644d711a NHE |
7833 | break; |
7834 | } | |
7835 | break; | |
7836 | case 2: /* clts */ | |
7837 | if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && | |
7838 | (vmcs12->cr0_read_shadow & X86_CR0_TS)) | |
1d804d07 | 7839 | return true; |
644d711a NHE |
7840 | break; |
7841 | case 1: /* mov from cr */ | |
7842 | switch (cr) { | |
7843 | case 3: | |
7844 | if (vmcs12->cpu_based_vm_exec_control & | |
7845 | CPU_BASED_CR3_STORE_EXITING) | |
1d804d07 | 7846 | return true; |
644d711a NHE |
7847 | break; |
7848 | case 8: | |
7849 | if (vmcs12->cpu_based_vm_exec_control & | |
7850 | CPU_BASED_CR8_STORE_EXITING) | |
1d804d07 | 7851 | return true; |
644d711a NHE |
7852 | break; |
7853 | } | |
7854 | break; | |
7855 | case 3: /* lmsw */ | |
7856 | /* | |
7857 | * lmsw can change bits 1..3 of cr0, and only set bit 0 of | |
7858 | * cr0. Other attempted changes are ignored, with no exit. | |
7859 | */ | |
7860 | if (vmcs12->cr0_guest_host_mask & 0xe & | |
7861 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 7862 | return true; |
644d711a NHE |
7863 | if ((vmcs12->cr0_guest_host_mask & 0x1) && |
7864 | !(vmcs12->cr0_read_shadow & 0x1) && | |
7865 | (val & 0x1)) | |
1d804d07 | 7866 | return true; |
644d711a NHE |
7867 | break; |
7868 | } | |
1d804d07 | 7869 | return false; |
644d711a NHE |
7870 | } |
7871 | ||
7872 | /* | |
7873 | * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we | |
7874 | * should handle it ourselves in L0 (and then continue L2). Only call this | |
7875 | * when in is_guest_mode (L2). | |
7876 | */ | |
7877 | static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu) | |
7878 | { | |
644d711a NHE |
7879 | u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
7880 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7881 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
957c897e | 7882 | u32 exit_reason = vmx->exit_reason; |
644d711a | 7883 | |
542060ea JK |
7884 | trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason, |
7885 | vmcs_readl(EXIT_QUALIFICATION), | |
7886 | vmx->idt_vectoring_info, | |
7887 | intr_info, | |
7888 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
7889 | KVM_ISA_VMX); | |
7890 | ||
644d711a | 7891 | if (vmx->nested.nested_run_pending) |
1d804d07 | 7892 | return false; |
644d711a NHE |
7893 | |
7894 | if (unlikely(vmx->fail)) { | |
bd80158a JK |
7895 | pr_info_ratelimited("%s failed vm entry %x\n", __func__, |
7896 | vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1d804d07 | 7897 | return true; |
644d711a NHE |
7898 | } |
7899 | ||
7900 | switch (exit_reason) { | |
7901 | case EXIT_REASON_EXCEPTION_NMI: | |
7902 | if (!is_exception(intr_info)) | |
1d804d07 | 7903 | return false; |
644d711a NHE |
7904 | else if (is_page_fault(intr_info)) |
7905 | return enable_ept; | |
e504c909 | 7906 | else if (is_no_device(intr_info) && |
ccf9844e | 7907 | !(vmcs12->guest_cr0 & X86_CR0_TS)) |
1d804d07 | 7908 | return false; |
6f05485d JK |
7909 | else if (is_debug(intr_info) && |
7910 | vcpu->guest_debug & | |
7911 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
7912 | return false; | |
7913 | else if (is_breakpoint(intr_info) && | |
7914 | vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
7915 | return false; | |
644d711a NHE |
7916 | return vmcs12->exception_bitmap & |
7917 | (1u << (intr_info & INTR_INFO_VECTOR_MASK)); | |
7918 | case EXIT_REASON_EXTERNAL_INTERRUPT: | |
1d804d07 | 7919 | return false; |
644d711a | 7920 | case EXIT_REASON_TRIPLE_FAULT: |
1d804d07 | 7921 | return true; |
644d711a | 7922 | case EXIT_REASON_PENDING_INTERRUPT: |
3b656cf7 | 7923 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING); |
644d711a | 7924 | case EXIT_REASON_NMI_WINDOW: |
3b656cf7 | 7925 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING); |
644d711a | 7926 | case EXIT_REASON_TASK_SWITCH: |
1d804d07 | 7927 | return true; |
644d711a | 7928 | case EXIT_REASON_CPUID: |
bc613494 | 7929 | if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa) |
1d804d07 JP |
7930 | return false; |
7931 | return true; | |
644d711a NHE |
7932 | case EXIT_REASON_HLT: |
7933 | return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); | |
7934 | case EXIT_REASON_INVD: | |
1d804d07 | 7935 | return true; |
644d711a NHE |
7936 | case EXIT_REASON_INVLPG: |
7937 | return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
7938 | case EXIT_REASON_RDPMC: | |
7939 | return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); | |
b3a2a907 | 7940 | case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP: |
644d711a NHE |
7941 | return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); |
7942 | case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: | |
7943 | case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: | |
7944 | case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD: | |
7945 | case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE: | |
7946 | case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: | |
a642fc30 | 7947 | case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: |
644d711a NHE |
7948 | /* |
7949 | * VMX instructions trap unconditionally. This allows L1 to | |
7950 | * emulate them for its L2 guest, i.e., allows 3-level nesting! | |
7951 | */ | |
1d804d07 | 7952 | return true; |
644d711a NHE |
7953 | case EXIT_REASON_CR_ACCESS: |
7954 | return nested_vmx_exit_handled_cr(vcpu, vmcs12); | |
7955 | case EXIT_REASON_DR_ACCESS: | |
7956 | return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); | |
7957 | case EXIT_REASON_IO_INSTRUCTION: | |
908a7bdd | 7958 | return nested_vmx_exit_handled_io(vcpu, vmcs12); |
644d711a NHE |
7959 | case EXIT_REASON_MSR_READ: |
7960 | case EXIT_REASON_MSR_WRITE: | |
7961 | return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); | |
7962 | case EXIT_REASON_INVALID_STATE: | |
1d804d07 | 7963 | return true; |
644d711a NHE |
7964 | case EXIT_REASON_MWAIT_INSTRUCTION: |
7965 | return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); | |
5f3d45e7 MD |
7966 | case EXIT_REASON_MONITOR_TRAP_FLAG: |
7967 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); | |
644d711a NHE |
7968 | case EXIT_REASON_MONITOR_INSTRUCTION: |
7969 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); | |
7970 | case EXIT_REASON_PAUSE_INSTRUCTION: | |
7971 | return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || | |
7972 | nested_cpu_has2(vmcs12, | |
7973 | SECONDARY_EXEC_PAUSE_LOOP_EXITING); | |
7974 | case EXIT_REASON_MCE_DURING_VMENTRY: | |
1d804d07 | 7975 | return false; |
644d711a | 7976 | case EXIT_REASON_TPR_BELOW_THRESHOLD: |
a7c0b07d | 7977 | return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); |
644d711a NHE |
7978 | case EXIT_REASON_APIC_ACCESS: |
7979 | return nested_cpu_has2(vmcs12, | |
7980 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
82f0dd4b | 7981 | case EXIT_REASON_APIC_WRITE: |
608406e2 WV |
7982 | case EXIT_REASON_EOI_INDUCED: |
7983 | /* apic_write and eoi_induced should exit unconditionally. */ | |
1d804d07 | 7984 | return true; |
644d711a | 7985 | case EXIT_REASON_EPT_VIOLATION: |
2b1be677 NHE |
7986 | /* |
7987 | * L0 always deals with the EPT violation. If nested EPT is | |
7988 | * used, and the nested mmu code discovers that the address is | |
7989 | * missing in the guest EPT table (EPT12), the EPT violation | |
7990 | * will be injected with nested_ept_inject_page_fault() | |
7991 | */ | |
1d804d07 | 7992 | return false; |
644d711a | 7993 | case EXIT_REASON_EPT_MISCONFIG: |
2b1be677 NHE |
7994 | /* |
7995 | * L2 never uses directly L1's EPT, but rather L0's own EPT | |
7996 | * table (shadow on EPT) or a merged EPT table that L0 built | |
7997 | * (EPT on EPT). So any problems with the structure of the | |
7998 | * table is L0's fault. | |
7999 | */ | |
1d804d07 | 8000 | return false; |
644d711a NHE |
8001 | case EXIT_REASON_WBINVD: |
8002 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); | |
8003 | case EXIT_REASON_XSETBV: | |
1d804d07 | 8004 | return true; |
81dc01f7 WL |
8005 | case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: |
8006 | /* | |
8007 | * This should never happen, since it is not possible to | |
8008 | * set XSS to a non-zero value---neither in L1 nor in L2. | |
8009 | * If if it were, XSS would have to be checked against | |
8010 | * the XSS exit bitmap in vmcs12. | |
8011 | */ | |
8012 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); | |
8b3e34e4 XG |
8013 | case EXIT_REASON_PCOMMIT: |
8014 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT); | |
644d711a | 8015 | default: |
1d804d07 | 8016 | return true; |
644d711a NHE |
8017 | } |
8018 | } | |
8019 | ||
586f9607 AK |
8020 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
8021 | { | |
8022 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
8023 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
8024 | } | |
8025 | ||
a3eaa864 | 8026 | static int vmx_create_pml_buffer(struct vcpu_vmx *vmx) |
843e4330 KH |
8027 | { |
8028 | struct page *pml_pg; | |
843e4330 KH |
8029 | |
8030 | pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
8031 | if (!pml_pg) | |
8032 | return -ENOMEM; | |
8033 | ||
8034 | vmx->pml_pg = pml_pg; | |
8035 | ||
8036 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
8037 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
8038 | ||
843e4330 KH |
8039 | return 0; |
8040 | } | |
8041 | ||
a3eaa864 | 8042 | static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) |
843e4330 | 8043 | { |
a3eaa864 KH |
8044 | if (vmx->pml_pg) { |
8045 | __free_page(vmx->pml_pg); | |
8046 | vmx->pml_pg = NULL; | |
8047 | } | |
843e4330 KH |
8048 | } |
8049 | ||
54bf36aa | 8050 | static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) |
843e4330 | 8051 | { |
54bf36aa | 8052 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
843e4330 KH |
8053 | u64 *pml_buf; |
8054 | u16 pml_idx; | |
8055 | ||
8056 | pml_idx = vmcs_read16(GUEST_PML_INDEX); | |
8057 | ||
8058 | /* Do nothing if PML buffer is empty */ | |
8059 | if (pml_idx == (PML_ENTITY_NUM - 1)) | |
8060 | return; | |
8061 | ||
8062 | /* PML index always points to next available PML buffer entity */ | |
8063 | if (pml_idx >= PML_ENTITY_NUM) | |
8064 | pml_idx = 0; | |
8065 | else | |
8066 | pml_idx++; | |
8067 | ||
8068 | pml_buf = page_address(vmx->pml_pg); | |
8069 | for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { | |
8070 | u64 gpa; | |
8071 | ||
8072 | gpa = pml_buf[pml_idx]; | |
8073 | WARN_ON(gpa & (PAGE_SIZE - 1)); | |
54bf36aa | 8074 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
843e4330 KH |
8075 | } |
8076 | ||
8077 | /* reset PML index */ | |
8078 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
8079 | } | |
8080 | ||
8081 | /* | |
8082 | * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. | |
8083 | * Called before reporting dirty_bitmap to userspace. | |
8084 | */ | |
8085 | static void kvm_flush_pml_buffers(struct kvm *kvm) | |
8086 | { | |
8087 | int i; | |
8088 | struct kvm_vcpu *vcpu; | |
8089 | /* | |
8090 | * We only need to kick vcpu out of guest mode here, as PML buffer | |
8091 | * is flushed at beginning of all VMEXITs, and it's obvious that only | |
8092 | * vcpus running in guest are possible to have unflushed GPAs in PML | |
8093 | * buffer. | |
8094 | */ | |
8095 | kvm_for_each_vcpu(i, vcpu, kvm) | |
8096 | kvm_vcpu_kick(vcpu); | |
8097 | } | |
8098 | ||
4eb64dce PB |
8099 | static void vmx_dump_sel(char *name, uint32_t sel) |
8100 | { | |
8101 | pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", | |
8102 | name, vmcs_read32(sel), | |
8103 | vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), | |
8104 | vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), | |
8105 | vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); | |
8106 | } | |
8107 | ||
8108 | static void vmx_dump_dtsel(char *name, uint32_t limit) | |
8109 | { | |
8110 | pr_err("%s limit=0x%08x, base=0x%016lx\n", | |
8111 | name, vmcs_read32(limit), | |
8112 | vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); | |
8113 | } | |
8114 | ||
8115 | static void dump_vmcs(void) | |
8116 | { | |
8117 | u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); | |
8118 | u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); | |
8119 | u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
8120 | u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); | |
8121 | u32 secondary_exec_control = 0; | |
8122 | unsigned long cr4 = vmcs_readl(GUEST_CR4); | |
f3531054 | 8123 | u64 efer = vmcs_read64(GUEST_IA32_EFER); |
4eb64dce PB |
8124 | int i, n; |
8125 | ||
8126 | if (cpu_has_secondary_exec_ctrls()) | |
8127 | secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8128 | ||
8129 | pr_err("*** Guest State ***\n"); | |
8130 | pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8131 | vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), | |
8132 | vmcs_readl(CR0_GUEST_HOST_MASK)); | |
8133 | pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8134 | cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); | |
8135 | pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); | |
8136 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && | |
8137 | (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) | |
8138 | { | |
845c5b40 PB |
8139 | pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", |
8140 | vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); | |
8141 | pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", | |
8142 | vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); | |
4eb64dce PB |
8143 | } |
8144 | pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", | |
8145 | vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); | |
8146 | pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", | |
8147 | vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); | |
8148 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8149 | vmcs_readl(GUEST_SYSENTER_ESP), | |
8150 | vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); | |
8151 | vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); | |
8152 | vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); | |
8153 | vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); | |
8154 | vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); | |
8155 | vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); | |
8156 | vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); | |
8157 | vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); | |
8158 | vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); | |
8159 | vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); | |
8160 | vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); | |
8161 | if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || | |
8162 | (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) | |
845c5b40 PB |
8163 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8164 | efer, vmcs_read64(GUEST_IA32_PAT)); | |
8165 | pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", | |
8166 | vmcs_read64(GUEST_IA32_DEBUGCTL), | |
4eb64dce PB |
8167 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); |
8168 | if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
845c5b40 PB |
8169 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8170 | vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce | 8171 | if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) |
845c5b40 | 8172 | pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); |
4eb64dce PB |
8173 | pr_err("Interruptibility = %08x ActivityState = %08x\n", |
8174 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), | |
8175 | vmcs_read32(GUEST_ACTIVITY_STATE)); | |
8176 | if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) | |
8177 | pr_err("InterruptStatus = %04x\n", | |
8178 | vmcs_read16(GUEST_INTR_STATUS)); | |
8179 | ||
8180 | pr_err("*** Host State ***\n"); | |
8181 | pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", | |
8182 | vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); | |
8183 | pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", | |
8184 | vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), | |
8185 | vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), | |
8186 | vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), | |
8187 | vmcs_read16(HOST_TR_SELECTOR)); | |
8188 | pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", | |
8189 | vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), | |
8190 | vmcs_readl(HOST_TR_BASE)); | |
8191 | pr_err("GDTBase=%016lx IDTBase=%016lx\n", | |
8192 | vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); | |
8193 | pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", | |
8194 | vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), | |
8195 | vmcs_readl(HOST_CR4)); | |
8196 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8197 | vmcs_readl(HOST_IA32_SYSENTER_ESP), | |
8198 | vmcs_read32(HOST_IA32_SYSENTER_CS), | |
8199 | vmcs_readl(HOST_IA32_SYSENTER_EIP)); | |
8200 | if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) | |
845c5b40 PB |
8201 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8202 | vmcs_read64(HOST_IA32_EFER), | |
8203 | vmcs_read64(HOST_IA32_PAT)); | |
4eb64dce | 8204 | if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
845c5b40 PB |
8205 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8206 | vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce PB |
8207 | |
8208 | pr_err("*** Control State ***\n"); | |
8209 | pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", | |
8210 | pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); | |
8211 | pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); | |
8212 | pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", | |
8213 | vmcs_read32(EXCEPTION_BITMAP), | |
8214 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), | |
8215 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); | |
8216 | pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8217 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
8218 | vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), | |
8219 | vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); | |
8220 | pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8221 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8222 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8223 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
8224 | pr_err(" reason=%08x qualification=%016lx\n", | |
8225 | vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); | |
8226 | pr_err("IDTVectoring: info=%08x errcode=%08x\n", | |
8227 | vmcs_read32(IDT_VECTORING_INFO_FIELD), | |
8228 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
845c5b40 | 8229 | pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); |
8cfe9866 | 8230 | if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) |
845c5b40 PB |
8231 | pr_err("TSC Multiplier = 0x%016llx\n", |
8232 | vmcs_read64(TSC_MULTIPLIER)); | |
4eb64dce PB |
8233 | if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) |
8234 | pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); | |
8235 | if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) | |
8236 | pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); | |
8237 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) | |
845c5b40 | 8238 | pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); |
4eb64dce PB |
8239 | n = vmcs_read32(CR3_TARGET_COUNT); |
8240 | for (i = 0; i + 1 < n; i += 4) | |
8241 | pr_err("CR3 target%u=%016lx target%u=%016lx\n", | |
8242 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), | |
8243 | i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); | |
8244 | if (i < n) | |
8245 | pr_err("CR3 target%u=%016lx\n", | |
8246 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); | |
8247 | if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) | |
8248 | pr_err("PLE Gap=%08x Window=%08x\n", | |
8249 | vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); | |
8250 | if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) | |
8251 | pr_err("Virtual processor ID = 0x%04x\n", | |
8252 | vmcs_read16(VIRTUAL_PROCESSOR_ID)); | |
8253 | } | |
8254 | ||
6aa8b732 AK |
8255 | /* |
8256 | * The guest has exited. See if we can fix it or if we need userspace | |
8257 | * assistance. | |
8258 | */ | |
851ba692 | 8259 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 8260 | { |
29bd8a78 | 8261 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 8262 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 8263 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 8264 | |
8b89fe1f PB |
8265 | trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); |
8266 | ||
843e4330 KH |
8267 | /* |
8268 | * Flush logged GPAs PML buffer, this will make dirty_bitmap more | |
8269 | * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before | |
8270 | * querying dirty_bitmap, we only need to kick all vcpus out of guest | |
8271 | * mode as if vcpus is in root mode, the PML buffer must has been | |
8272 | * flushed already. | |
8273 | */ | |
8274 | if (enable_pml) | |
54bf36aa | 8275 | vmx_flush_pml_buffer(vcpu); |
843e4330 | 8276 | |
80ced186 | 8277 | /* If guest state is invalid, start emulating */ |
14168786 | 8278 | if (vmx->emulation_required) |
80ced186 | 8279 | return handle_invalid_guest_state(vcpu); |
1d5a4d9b | 8280 | |
644d711a | 8281 | if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) { |
533558bc JK |
8282 | nested_vmx_vmexit(vcpu, exit_reason, |
8283 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8284 | vmcs_readl(EXIT_QUALIFICATION)); | |
644d711a NHE |
8285 | return 1; |
8286 | } | |
8287 | ||
5120702e | 8288 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
4eb64dce | 8289 | dump_vmcs(); |
5120702e MG |
8290 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8291 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
8292 | = exit_reason; | |
8293 | return 0; | |
8294 | } | |
8295 | ||
29bd8a78 | 8296 | if (unlikely(vmx->fail)) { |
851ba692 AK |
8297 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8298 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
8299 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
8300 | return 0; | |
8301 | } | |
6aa8b732 | 8302 | |
b9bf6882 XG |
8303 | /* |
8304 | * Note: | |
8305 | * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by | |
8306 | * delivery event since it indicates guest is accessing MMIO. | |
8307 | * The vm-exit can be triggered again after return to guest that | |
8308 | * will cause infinite loop. | |
8309 | */ | |
d77c26fc | 8310 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 8311 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac | 8312 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
b9bf6882 XG |
8313 | exit_reason != EXIT_REASON_TASK_SWITCH)) { |
8314 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
8315 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; | |
8316 | vcpu->run->internal.ndata = 2; | |
8317 | vcpu->run->internal.data[0] = vectoring_info; | |
8318 | vcpu->run->internal.data[1] = exit_reason; | |
8319 | return 0; | |
8320 | } | |
3b86cd99 | 8321 | |
644d711a NHE |
8322 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked && |
8323 | !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis( | |
f5c4368f | 8324 | get_vmcs12(vcpu))))) { |
c4282df9 | 8325 | if (vmx_interrupt_allowed(vcpu)) { |
3b86cd99 | 8326 | vmx->soft_vnmi_blocked = 0; |
3b86cd99 | 8327 | } else if (vmx->vnmi_blocked_time > 1000000000LL && |
4531220b | 8328 | vcpu->arch.nmi_pending) { |
3b86cd99 JK |
8329 | /* |
8330 | * This CPU don't support us in finding the end of an | |
8331 | * NMI-blocked window if the guest runs with IRQs | |
8332 | * disabled. So we pull the trigger after 1 s of | |
8333 | * futile waiting, but inform the user about this. | |
8334 | */ | |
8335 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
8336 | "state on VCPU %d after 1 s timeout\n", | |
8337 | __func__, vcpu->vcpu_id); | |
8338 | vmx->soft_vnmi_blocked = 0; | |
3b86cd99 | 8339 | } |
3b86cd99 JK |
8340 | } |
8341 | ||
6aa8b732 AK |
8342 | if (exit_reason < kvm_vmx_max_exit_handlers |
8343 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 8344 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 8345 | else { |
2bc19dc3 MT |
8346 | WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason); |
8347 | kvm_queue_exception(vcpu, UD_VECTOR); | |
8348 | return 1; | |
6aa8b732 | 8349 | } |
6aa8b732 AK |
8350 | } |
8351 | ||
95ba8273 | 8352 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 8353 | { |
a7c0b07d WL |
8354 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
8355 | ||
8356 | if (is_guest_mode(vcpu) && | |
8357 | nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
8358 | return; | |
8359 | ||
95ba8273 | 8360 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
8361 | vmcs_write32(TPR_THRESHOLD, 0); |
8362 | return; | |
8363 | } | |
8364 | ||
95ba8273 | 8365 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
8366 | } |
8367 | ||
8d14695f YZ |
8368 | static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
8369 | { | |
8370 | u32 sec_exec_control; | |
8371 | ||
8372 | /* | |
8373 | * There is not point to enable virtualize x2apic without enable | |
8374 | * apicv | |
8375 | */ | |
c7c9c56c | 8376 | if (!cpu_has_vmx_virtualize_x2apic_mode() || |
d62caabb | 8377 | !kvm_vcpu_apicv_active(vcpu)) |
8d14695f YZ |
8378 | return; |
8379 | ||
35754c98 | 8380 | if (!cpu_need_tpr_shadow(vcpu)) |
8d14695f YZ |
8381 | return; |
8382 | ||
8383 | sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8384 | ||
8385 | if (set) { | |
8386 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
8387 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8388 | } else { | |
8389 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8390 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
8391 | } | |
8392 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control); | |
8393 | ||
8394 | vmx_set_msr_bitmap(vcpu); | |
8395 | } | |
8396 | ||
38b99173 TC |
8397 | static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) |
8398 | { | |
8399 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8400 | ||
8401 | /* | |
8402 | * Currently we do not handle the nested case where L2 has an | |
8403 | * APIC access page of its own; that page is still pinned. | |
8404 | * Hence, we skip the case where the VCPU is in guest mode _and_ | |
8405 | * L1 prepared an APIC access page for L2. | |
8406 | * | |
8407 | * For the case where L1 and L2 share the same APIC access page | |
8408 | * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear | |
8409 | * in the vmcs12), this function will only update either the vmcs01 | |
8410 | * or the vmcs02. If the former, the vmcs02 will be updated by | |
8411 | * prepare_vmcs02. If the latter, the vmcs01 will be updated in | |
8412 | * the next L2->L1 exit. | |
8413 | */ | |
8414 | if (!is_guest_mode(vcpu) || | |
8415 | !nested_cpu_has2(vmx->nested.current_vmcs12, | |
8416 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
8417 | vmcs_write64(APIC_ACCESS_ADDR, hpa); | |
8418 | } | |
8419 | ||
67c9dddc | 8420 | static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
c7c9c56c YZ |
8421 | { |
8422 | u16 status; | |
8423 | u8 old; | |
8424 | ||
67c9dddc PB |
8425 | if (max_isr == -1) |
8426 | max_isr = 0; | |
c7c9c56c YZ |
8427 | |
8428 | status = vmcs_read16(GUEST_INTR_STATUS); | |
8429 | old = status >> 8; | |
67c9dddc | 8430 | if (max_isr != old) { |
c7c9c56c | 8431 | status &= 0xff; |
67c9dddc | 8432 | status |= max_isr << 8; |
c7c9c56c YZ |
8433 | vmcs_write16(GUEST_INTR_STATUS, status); |
8434 | } | |
8435 | } | |
8436 | ||
8437 | static void vmx_set_rvi(int vector) | |
8438 | { | |
8439 | u16 status; | |
8440 | u8 old; | |
8441 | ||
4114c27d WW |
8442 | if (vector == -1) |
8443 | vector = 0; | |
8444 | ||
c7c9c56c YZ |
8445 | status = vmcs_read16(GUEST_INTR_STATUS); |
8446 | old = (u8)status & 0xff; | |
8447 | if ((u8)vector != old) { | |
8448 | status &= ~0xff; | |
8449 | status |= (u8)vector; | |
8450 | vmcs_write16(GUEST_INTR_STATUS, status); | |
8451 | } | |
8452 | } | |
8453 | ||
8454 | static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
8455 | { | |
4114c27d WW |
8456 | if (!is_guest_mode(vcpu)) { |
8457 | vmx_set_rvi(max_irr); | |
8458 | return; | |
8459 | } | |
8460 | ||
c7c9c56c YZ |
8461 | if (max_irr == -1) |
8462 | return; | |
8463 | ||
963fee16 | 8464 | /* |
4114c27d WW |
8465 | * In guest mode. If a vmexit is needed, vmx_check_nested_events |
8466 | * handles it. | |
963fee16 | 8467 | */ |
4114c27d | 8468 | if (nested_exit_on_intr(vcpu)) |
963fee16 WL |
8469 | return; |
8470 | ||
963fee16 | 8471 | /* |
4114c27d | 8472 | * Else, fall back to pre-APICv interrupt injection since L2 |
963fee16 WL |
8473 | * is run without virtual interrupt delivery. |
8474 | */ | |
8475 | if (!kvm_event_needs_reinjection(vcpu) && | |
8476 | vmx_interrupt_allowed(vcpu)) { | |
8477 | kvm_queue_interrupt(vcpu, max_irr, false); | |
8478 | vmx_inject_irq(vcpu); | |
8479 | } | |
c7c9c56c YZ |
8480 | } |
8481 | ||
6308630b | 8482 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c | 8483 | { |
d62caabb | 8484 | if (!kvm_vcpu_apicv_active(vcpu)) |
3d81bc7e YZ |
8485 | return; |
8486 | ||
c7c9c56c YZ |
8487 | vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); |
8488 | vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); | |
8489 | vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); | |
8490 | vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); | |
8491 | } | |
8492 | ||
51aa01d1 | 8493 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 8494 | { |
00eba012 AK |
8495 | u32 exit_intr_info; |
8496 | ||
8497 | if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY | |
8498 | || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)) | |
8499 | return; | |
8500 | ||
c5ca8e57 | 8501 | vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
00eba012 | 8502 | exit_intr_info = vmx->exit_intr_info; |
a0861c02 AK |
8503 | |
8504 | /* Handle machine checks before interrupts are enabled */ | |
00eba012 | 8505 | if (is_machine_check(exit_intr_info)) |
a0861c02 AK |
8506 | kvm_machine_check(); |
8507 | ||
20f65983 | 8508 | /* We need to handle NMIs before interrupts are enabled */ |
00eba012 | 8509 | if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR && |
ff9d07a0 ZY |
8510 | (exit_intr_info & INTR_INFO_VALID_MASK)) { |
8511 | kvm_before_handle_nmi(&vmx->vcpu); | |
20f65983 | 8512 | asm("int $2"); |
ff9d07a0 ZY |
8513 | kvm_after_handle_nmi(&vmx->vcpu); |
8514 | } | |
51aa01d1 | 8515 | } |
20f65983 | 8516 | |
a547c6db YZ |
8517 | static void vmx_handle_external_intr(struct kvm_vcpu *vcpu) |
8518 | { | |
8519 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
3f62de5f | 8520 | register void *__sp asm(_ASM_SP); |
a547c6db YZ |
8521 | |
8522 | /* | |
8523 | * If external interrupt exists, IF bit is set in rflags/eflags on the | |
8524 | * interrupt stack frame, and interrupt will be enabled on a return | |
8525 | * from interrupt handler. | |
8526 | */ | |
8527 | if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK)) | |
8528 | == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) { | |
8529 | unsigned int vector; | |
8530 | unsigned long entry; | |
8531 | gate_desc *desc; | |
8532 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8533 | #ifdef CONFIG_X86_64 | |
8534 | unsigned long tmp; | |
8535 | #endif | |
8536 | ||
8537 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
8538 | desc = (gate_desc *)vmx->host_idt_base + vector; | |
8539 | entry = gate_offset(*desc); | |
8540 | asm volatile( | |
8541 | #ifdef CONFIG_X86_64 | |
8542 | "mov %%" _ASM_SP ", %[sp]\n\t" | |
8543 | "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" | |
8544 | "push $%c[ss]\n\t" | |
8545 | "push %[sp]\n\t" | |
8546 | #endif | |
8547 | "pushf\n\t" | |
8548 | "orl $0x200, (%%" _ASM_SP ")\n\t" | |
8549 | __ASM_SIZE(push) " $%c[cs]\n\t" | |
8550 | "call *%[entry]\n\t" | |
8551 | : | |
8552 | #ifdef CONFIG_X86_64 | |
3f62de5f | 8553 | [sp]"=&r"(tmp), |
a547c6db | 8554 | #endif |
3f62de5f | 8555 | "+r"(__sp) |
a547c6db YZ |
8556 | : |
8557 | [entry]"r"(entry), | |
8558 | [ss]"i"(__KERNEL_DS), | |
8559 | [cs]"i"(__KERNEL_CS) | |
8560 | ); | |
8561 | } else | |
8562 | local_irq_enable(); | |
8563 | } | |
8564 | ||
6d396b55 PB |
8565 | static bool vmx_has_high_real_mode_segbase(void) |
8566 | { | |
8567 | return enable_unrestricted_guest || emulate_invalid_guest_state; | |
8568 | } | |
8569 | ||
da8999d3 LJ |
8570 | static bool vmx_mpx_supported(void) |
8571 | { | |
8572 | return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && | |
8573 | (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); | |
8574 | } | |
8575 | ||
55412b2e WL |
8576 | static bool vmx_xsaves_supported(void) |
8577 | { | |
8578 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
8579 | SECONDARY_EXEC_XSAVES; | |
8580 | } | |
8581 | ||
51aa01d1 AK |
8582 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
8583 | { | |
c5ca8e57 | 8584 | u32 exit_intr_info; |
51aa01d1 AK |
8585 | bool unblock_nmi; |
8586 | u8 vector; | |
8587 | bool idtv_info_valid; | |
8588 | ||
8589 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 8590 | |
cf393f75 | 8591 | if (cpu_has_virtual_nmis()) { |
9d58b931 AK |
8592 | if (vmx->nmi_known_unmasked) |
8593 | return; | |
c5ca8e57 AK |
8594 | /* |
8595 | * Can't use vmx->exit_intr_info since we're not sure what | |
8596 | * the exit reason is. | |
8597 | */ | |
8598 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
cf393f75 AK |
8599 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; |
8600 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
8601 | /* | |
7b4a25cb | 8602 | * SDM 3: 27.7.1.2 (September 2008) |
cf393f75 AK |
8603 | * Re-set bit "block by NMI" before VM entry if vmexit caused by |
8604 | * a guest IRET fault. | |
7b4a25cb GN |
8605 | * SDM 3: 23.2.2 (September 2008) |
8606 | * Bit 12 is undefined in any of the following cases: | |
8607 | * If the VM exit sets the valid bit in the IDT-vectoring | |
8608 | * information field. | |
8609 | * If the VM exit is due to a double fault. | |
cf393f75 | 8610 | */ |
7b4a25cb GN |
8611 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && |
8612 | vector != DF_VECTOR && !idtv_info_valid) | |
cf393f75 AK |
8613 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, |
8614 | GUEST_INTR_STATE_NMI); | |
9d58b931 AK |
8615 | else |
8616 | vmx->nmi_known_unmasked = | |
8617 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | |
8618 | & GUEST_INTR_STATE_NMI); | |
3b86cd99 JK |
8619 | } else if (unlikely(vmx->soft_vnmi_blocked)) |
8620 | vmx->vnmi_blocked_time += | |
8621 | ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time)); | |
51aa01d1 AK |
8622 | } |
8623 | ||
3ab66e8a | 8624 | static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, |
83422e17 AK |
8625 | u32 idt_vectoring_info, |
8626 | int instr_len_field, | |
8627 | int error_code_field) | |
51aa01d1 | 8628 | { |
51aa01d1 AK |
8629 | u8 vector; |
8630 | int type; | |
8631 | bool idtv_info_valid; | |
8632 | ||
8633 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 8634 | |
3ab66e8a JK |
8635 | vcpu->arch.nmi_injected = false; |
8636 | kvm_clear_exception_queue(vcpu); | |
8637 | kvm_clear_interrupt_queue(vcpu); | |
37b96e98 GN |
8638 | |
8639 | if (!idtv_info_valid) | |
8640 | return; | |
8641 | ||
3ab66e8a | 8642 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3842d135 | 8643 | |
668f612f AK |
8644 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
8645 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 8646 | |
64a7ec06 | 8647 | switch (type) { |
37b96e98 | 8648 | case INTR_TYPE_NMI_INTR: |
3ab66e8a | 8649 | vcpu->arch.nmi_injected = true; |
668f612f | 8650 | /* |
7b4a25cb | 8651 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
8652 | * Clear bit "block by NMI" before VM entry if a NMI |
8653 | * delivery faulted. | |
668f612f | 8654 | */ |
3ab66e8a | 8655 | vmx_set_nmi_mask(vcpu, false); |
37b96e98 | 8656 | break; |
37b96e98 | 8657 | case INTR_TYPE_SOFT_EXCEPTION: |
3ab66e8a | 8658 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f GN |
8659 | /* fall through */ |
8660 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 8661 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 8662 | u32 err = vmcs_read32(error_code_field); |
851eb667 | 8663 | kvm_requeue_exception_e(vcpu, vector, err); |
35920a35 | 8664 | } else |
851eb667 | 8665 | kvm_requeue_exception(vcpu, vector); |
37b96e98 | 8666 | break; |
66fd3f7f | 8667 | case INTR_TYPE_SOFT_INTR: |
3ab66e8a | 8668 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f | 8669 | /* fall through */ |
37b96e98 | 8670 | case INTR_TYPE_EXT_INTR: |
3ab66e8a | 8671 | kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); |
37b96e98 GN |
8672 | break; |
8673 | default: | |
8674 | break; | |
f7d9238f | 8675 | } |
cf393f75 AK |
8676 | } |
8677 | ||
83422e17 AK |
8678 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
8679 | { | |
3ab66e8a | 8680 | __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, |
83422e17 AK |
8681 | VM_EXIT_INSTRUCTION_LEN, |
8682 | IDT_VECTORING_ERROR_CODE); | |
8683 | } | |
8684 | ||
b463a6f7 AK |
8685 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
8686 | { | |
3ab66e8a | 8687 | __vmx_complete_interrupts(vcpu, |
b463a6f7 AK |
8688 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), |
8689 | VM_ENTRY_INSTRUCTION_LEN, | |
8690 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
8691 | ||
8692 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
8693 | } | |
8694 | ||
d7cd9796 GN |
8695 | static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) |
8696 | { | |
8697 | int i, nr_msrs; | |
8698 | struct perf_guest_switch_msr *msrs; | |
8699 | ||
8700 | msrs = perf_guest_get_msrs(&nr_msrs); | |
8701 | ||
8702 | if (!msrs) | |
8703 | return; | |
8704 | ||
8705 | for (i = 0; i < nr_msrs; i++) | |
8706 | if (msrs[i].host == msrs[i].guest) | |
8707 | clear_atomic_switch_msr(vmx, msrs[i].msr); | |
8708 | else | |
8709 | add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, | |
8710 | msrs[i].host); | |
8711 | } | |
8712 | ||
64672c95 YJ |
8713 | void vmx_arm_hv_timer(struct kvm_vcpu *vcpu) |
8714 | { | |
8715 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8716 | u64 tscl; | |
8717 | u32 delta_tsc; | |
8718 | ||
8719 | if (vmx->hv_deadline_tsc == -1) | |
8720 | return; | |
8721 | ||
8722 | tscl = rdtsc(); | |
8723 | if (vmx->hv_deadline_tsc > tscl) | |
8724 | /* sure to be 32 bit only because checked on set_hv_timer */ | |
8725 | delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> | |
8726 | cpu_preemption_timer_multi); | |
8727 | else | |
8728 | delta_tsc = 0; | |
8729 | ||
8730 | vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); | |
8731 | } | |
8732 | ||
a3b5ba49 | 8733 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 8734 | { |
a2fa3e9f | 8735 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
d974baa3 | 8736 | unsigned long debugctlmsr, cr4; |
104f226b AK |
8737 | |
8738 | /* Record the guest's net vcpu time for enforced NMI injections. */ | |
8739 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) | |
8740 | vmx->entry_time = ktime_get(); | |
8741 | ||
8742 | /* Don't enter VMX if guest state is invalid, let the exit handler | |
8743 | start emulation until we arrive back to a valid state */ | |
14168786 | 8744 | if (vmx->emulation_required) |
104f226b AK |
8745 | return; |
8746 | ||
a7653ecd RK |
8747 | if (vmx->ple_window_dirty) { |
8748 | vmx->ple_window_dirty = false; | |
8749 | vmcs_write32(PLE_WINDOW, vmx->ple_window); | |
8750 | } | |
8751 | ||
012f83cb AG |
8752 | if (vmx->nested.sync_shadow_vmcs) { |
8753 | copy_vmcs12_to_shadow(vmx); | |
8754 | vmx->nested.sync_shadow_vmcs = false; | |
8755 | } | |
8756 | ||
104f226b AK |
8757 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
8758 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
8759 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
8760 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
8761 | ||
1e02ce4c | 8762 | cr4 = cr4_read_shadow(); |
d974baa3 AL |
8763 | if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) { |
8764 | vmcs_writel(HOST_CR4, cr4); | |
8765 | vmx->host_state.vmcs_host_cr4 = cr4; | |
8766 | } | |
8767 | ||
104f226b AK |
8768 | /* When single-stepping over STI and MOV SS, we must clear the |
8769 | * corresponding interruptibility bits in the guest state. Otherwise | |
8770 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
8771 | * exceptions being set, but that's not correct for the guest debugging | |
8772 | * case. */ | |
8773 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
8774 | vmx_set_interrupt_shadow(vcpu, 0); | |
8775 | ||
1be0e61c XG |
8776 | if (vmx->guest_pkru_valid) |
8777 | __write_pkru(vmx->guest_pkru); | |
8778 | ||
d7cd9796 | 8779 | atomic_switch_perf_msrs(vmx); |
2a7921b7 | 8780 | debugctlmsr = get_debugctlmsr(); |
d7cd9796 | 8781 | |
64672c95 YJ |
8782 | vmx_arm_hv_timer(vcpu); |
8783 | ||
d462b819 | 8784 | vmx->__launched = vmx->loaded_vmcs->launched; |
104f226b | 8785 | asm( |
6aa8b732 | 8786 | /* Store host registers */ |
b188c81f AK |
8787 | "push %%" _ASM_DX "; push %%" _ASM_BP ";" |
8788 | "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */ | |
8789 | "push %%" _ASM_CX " \n\t" | |
8790 | "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t" | |
313dbd49 | 8791 | "je 1f \n\t" |
b188c81f | 8792 | "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t" |
4ecac3fd | 8793 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 8794 | "1: \n\t" |
d3edefc0 | 8795 | /* Reload cr2 if changed */ |
b188c81f AK |
8796 | "mov %c[cr2](%0), %%" _ASM_AX " \n\t" |
8797 | "mov %%cr2, %%" _ASM_DX " \n\t" | |
8798 | "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t" | |
d3edefc0 | 8799 | "je 2f \n\t" |
b188c81f | 8800 | "mov %%" _ASM_AX", %%cr2 \n\t" |
d3edefc0 | 8801 | "2: \n\t" |
6aa8b732 | 8802 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 8803 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 8804 | /* Load guest registers. Don't clobber flags. */ |
b188c81f AK |
8805 | "mov %c[rax](%0), %%" _ASM_AX " \n\t" |
8806 | "mov %c[rbx](%0), %%" _ASM_BX " \n\t" | |
8807 | "mov %c[rdx](%0), %%" _ASM_DX " \n\t" | |
8808 | "mov %c[rsi](%0), %%" _ASM_SI " \n\t" | |
8809 | "mov %c[rdi](%0), %%" _ASM_DI " \n\t" | |
8810 | "mov %c[rbp](%0), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 8811 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
8812 | "mov %c[r8](%0), %%r8 \n\t" |
8813 | "mov %c[r9](%0), %%r9 \n\t" | |
8814 | "mov %c[r10](%0), %%r10 \n\t" | |
8815 | "mov %c[r11](%0), %%r11 \n\t" | |
8816 | "mov %c[r12](%0), %%r12 \n\t" | |
8817 | "mov %c[r13](%0), %%r13 \n\t" | |
8818 | "mov %c[r14](%0), %%r14 \n\t" | |
8819 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 8820 | #endif |
b188c81f | 8821 | "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */ |
c801949d | 8822 | |
6aa8b732 | 8823 | /* Enter guest mode */ |
83287ea4 | 8824 | "jne 1f \n\t" |
4ecac3fd | 8825 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
83287ea4 AK |
8826 | "jmp 2f \n\t" |
8827 | "1: " __ex(ASM_VMX_VMRESUME) "\n\t" | |
8828 | "2: " | |
6aa8b732 | 8829 | /* Save guest registers, load host registers, keep flags */ |
b188c81f | 8830 | "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t" |
40712fae | 8831 | "pop %0 \n\t" |
b188c81f AK |
8832 | "mov %%" _ASM_AX ", %c[rax](%0) \n\t" |
8833 | "mov %%" _ASM_BX ", %c[rbx](%0) \n\t" | |
8834 | __ASM_SIZE(pop) " %c[rcx](%0) \n\t" | |
8835 | "mov %%" _ASM_DX ", %c[rdx](%0) \n\t" | |
8836 | "mov %%" _ASM_SI ", %c[rsi](%0) \n\t" | |
8837 | "mov %%" _ASM_DI ", %c[rdi](%0) \n\t" | |
8838 | "mov %%" _ASM_BP ", %c[rbp](%0) \n\t" | |
05b3e0c2 | 8839 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
8840 | "mov %%r8, %c[r8](%0) \n\t" |
8841 | "mov %%r9, %c[r9](%0) \n\t" | |
8842 | "mov %%r10, %c[r10](%0) \n\t" | |
8843 | "mov %%r11, %c[r11](%0) \n\t" | |
8844 | "mov %%r12, %c[r12](%0) \n\t" | |
8845 | "mov %%r13, %c[r13](%0) \n\t" | |
8846 | "mov %%r14, %c[r14](%0) \n\t" | |
8847 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 8848 | #endif |
b188c81f AK |
8849 | "mov %%cr2, %%" _ASM_AX " \n\t" |
8850 | "mov %%" _ASM_AX ", %c[cr2](%0) \n\t" | |
c801949d | 8851 | |
b188c81f | 8852 | "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t" |
e08aa78a | 8853 | "setbe %c[fail](%0) \n\t" |
83287ea4 AK |
8854 | ".pushsection .rodata \n\t" |
8855 | ".global vmx_return \n\t" | |
8856 | "vmx_return: " _ASM_PTR " 2b \n\t" | |
8857 | ".popsection" | |
e08aa78a | 8858 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), |
d462b819 | 8859 | [launched]"i"(offsetof(struct vcpu_vmx, __launched)), |
e08aa78a | 8860 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), |
313dbd49 | 8861 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
8862 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
8863 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
8864 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
8865 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
8866 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
8867 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
8868 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 8869 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
8870 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
8871 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
8872 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
8873 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
8874 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
8875 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
8876 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
8877 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 8878 | #endif |
40712fae AK |
8879 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
8880 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 LV |
8881 | : "cc", "memory" |
8882 | #ifdef CONFIG_X86_64 | |
b188c81f | 8883 | , "rax", "rbx", "rdi", "rsi" |
c2036300 | 8884 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
b188c81f AK |
8885 | #else |
8886 | , "eax", "ebx", "edi", "esi" | |
c2036300 LV |
8887 | #endif |
8888 | ); | |
6aa8b732 | 8889 | |
2a7921b7 GN |
8890 | /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ |
8891 | if (debugctlmsr) | |
8892 | update_debugctlmsr(debugctlmsr); | |
8893 | ||
aa67f609 AK |
8894 | #ifndef CONFIG_X86_64 |
8895 | /* | |
8896 | * The sysexit path does not restore ds/es, so we must set them to | |
8897 | * a reasonable value ourselves. | |
8898 | * | |
8899 | * We can't defer this to vmx_load_host_state() since that function | |
8900 | * may be executed in interrupt context, which saves and restore segments | |
8901 | * around it, nullifying its effect. | |
8902 | */ | |
8903 | loadsegment(ds, __USER_DS); | |
8904 | loadsegment(es, __USER_DS); | |
8905 | #endif | |
8906 | ||
6de4f3ad | 8907 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
6de12732 | 8908 | | (1 << VCPU_EXREG_RFLAGS) |
aff48baa | 8909 | | (1 << VCPU_EXREG_PDPTR) |
2fb92db1 | 8910 | | (1 << VCPU_EXREG_SEGMENTS) |
aff48baa | 8911 | | (1 << VCPU_EXREG_CR3)); |
5fdbf976 MT |
8912 | vcpu->arch.regs_dirty = 0; |
8913 | ||
1155f76a AK |
8914 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
8915 | ||
d462b819 | 8916 | vmx->loaded_vmcs->launched = 1; |
1b6269db | 8917 | |
51aa01d1 | 8918 | vmx->exit_reason = vmcs_read32(VM_EXIT_REASON); |
51aa01d1 | 8919 | |
1be0e61c XG |
8920 | /* |
8921 | * eager fpu is enabled if PKEY is supported and CR4 is switched | |
8922 | * back on host, so it is safe to read guest PKRU from current | |
8923 | * XSAVE. | |
8924 | */ | |
8925 | if (boot_cpu_has(X86_FEATURE_OSPKE)) { | |
8926 | vmx->guest_pkru = __read_pkru(); | |
8927 | if (vmx->guest_pkru != vmx->host_pkru) { | |
8928 | vmx->guest_pkru_valid = true; | |
8929 | __write_pkru(vmx->host_pkru); | |
8930 | } else | |
8931 | vmx->guest_pkru_valid = false; | |
8932 | } | |
8933 | ||
e0b890d3 GN |
8934 | /* |
8935 | * the KVM_REQ_EVENT optimization bit is only on for one entry, and if | |
8936 | * we did not inject a still-pending event to L1 now because of | |
8937 | * nested_run_pending, we need to re-enable this bit. | |
8938 | */ | |
8939 | if (vmx->nested.nested_run_pending) | |
8940 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8941 | ||
8942 | vmx->nested.nested_run_pending = 0; | |
8943 | ||
51aa01d1 AK |
8944 | vmx_complete_atomic_exit(vmx); |
8945 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 8946 | vmx_complete_interrupts(vmx); |
6aa8b732 AK |
8947 | } |
8948 | ||
4fa7734c PB |
8949 | static void vmx_load_vmcs01(struct kvm_vcpu *vcpu) |
8950 | { | |
8951 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8952 | int cpu; | |
8953 | ||
8954 | if (vmx->loaded_vmcs == &vmx->vmcs01) | |
8955 | return; | |
8956 | ||
8957 | cpu = get_cpu(); | |
8958 | vmx->loaded_vmcs = &vmx->vmcs01; | |
8959 | vmx_vcpu_put(vcpu); | |
8960 | vmx_vcpu_load(vcpu, cpu); | |
8961 | vcpu->cpu = cpu; | |
8962 | put_cpu(); | |
8963 | } | |
8964 | ||
6aa8b732 AK |
8965 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
8966 | { | |
fb3f0f51 RR |
8967 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8968 | ||
843e4330 | 8969 | if (enable_pml) |
a3eaa864 | 8970 | vmx_destroy_pml_buffer(vmx); |
991e7a0e | 8971 | free_vpid(vmx->vpid); |
4fa7734c PB |
8972 | leave_guest_mode(vcpu); |
8973 | vmx_load_vmcs01(vcpu); | |
26a865f4 | 8974 | free_nested(vmx); |
4fa7734c | 8975 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 RR |
8976 | kfree(vmx->guest_msrs); |
8977 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 8978 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
8979 | } |
8980 | ||
fb3f0f51 | 8981 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 8982 | { |
fb3f0f51 | 8983 | int err; |
c16f862d | 8984 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 8985 | int cpu; |
6aa8b732 | 8986 | |
a2fa3e9f | 8987 | if (!vmx) |
fb3f0f51 RR |
8988 | return ERR_PTR(-ENOMEM); |
8989 | ||
991e7a0e | 8990 | vmx->vpid = allocate_vpid(); |
2384d2b3 | 8991 | |
fb3f0f51 RR |
8992 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
8993 | if (err) | |
8994 | goto free_vcpu; | |
965b58a5 | 8995 | |
a2fa3e9f | 8996 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
03916db9 PB |
8997 | BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0]) |
8998 | > PAGE_SIZE); | |
0123be42 | 8999 | |
be6d05cf | 9000 | err = -ENOMEM; |
fb3f0f51 | 9001 | if (!vmx->guest_msrs) { |
fb3f0f51 RR |
9002 | goto uninit_vcpu; |
9003 | } | |
965b58a5 | 9004 | |
d462b819 NHE |
9005 | vmx->loaded_vmcs = &vmx->vmcs01; |
9006 | vmx->loaded_vmcs->vmcs = alloc_vmcs(); | |
9007 | if (!vmx->loaded_vmcs->vmcs) | |
fb3f0f51 | 9008 | goto free_msrs; |
d462b819 NHE |
9009 | if (!vmm_exclusive) |
9010 | kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id()))); | |
9011 | loaded_vmcs_init(vmx->loaded_vmcs); | |
9012 | if (!vmm_exclusive) | |
9013 | kvm_cpu_vmxoff(); | |
a2fa3e9f | 9014 | |
15ad7146 AK |
9015 | cpu = get_cpu(); |
9016 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 9017 | vmx->vcpu.cpu = cpu; |
8b9cf98c | 9018 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 9019 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 9020 | put_cpu(); |
fb3f0f51 RR |
9021 | if (err) |
9022 | goto free_vmcs; | |
35754c98 | 9023 | if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
be6d05cf JK |
9024 | err = alloc_apic_access_page(kvm); |
9025 | if (err) | |
5e4a0b3c | 9026 | goto free_vmcs; |
a63cb560 | 9027 | } |
fb3f0f51 | 9028 | |
b927a3ce SY |
9029 | if (enable_ept) { |
9030 | if (!kvm->arch.ept_identity_map_addr) | |
9031 | kvm->arch.ept_identity_map_addr = | |
9032 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
f51770ed TC |
9033 | err = init_rmode_identity_map(kvm); |
9034 | if (err) | |
93ea5388 | 9035 | goto free_vmcs; |
b927a3ce | 9036 | } |
b7ebfb05 | 9037 | |
5c614b35 | 9038 | if (nested) { |
b9c237bb | 9039 | nested_vmx_setup_ctls_msrs(vmx); |
5c614b35 WL |
9040 | vmx->nested.vpid02 = allocate_vpid(); |
9041 | } | |
b9c237bb | 9042 | |
705699a1 | 9043 | vmx->nested.posted_intr_nv = -1; |
a9d30f33 NHE |
9044 | vmx->nested.current_vmptr = -1ull; |
9045 | vmx->nested.current_vmcs12 = NULL; | |
9046 | ||
843e4330 KH |
9047 | /* |
9048 | * If PML is turned on, failure on enabling PML just results in failure | |
9049 | * of creating the vcpu, therefore we can simplify PML logic (by | |
9050 | * avoiding dealing with cases, such as enabling PML partially on vcpus | |
9051 | * for the guest, etc. | |
9052 | */ | |
9053 | if (enable_pml) { | |
a3eaa864 | 9054 | err = vmx_create_pml_buffer(vmx); |
843e4330 KH |
9055 | if (err) |
9056 | goto free_vmcs; | |
9057 | } | |
9058 | ||
fb3f0f51 RR |
9059 | return &vmx->vcpu; |
9060 | ||
9061 | free_vmcs: | |
5c614b35 | 9062 | free_vpid(vmx->nested.vpid02); |
5f3fbc34 | 9063 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 | 9064 | free_msrs: |
fb3f0f51 RR |
9065 | kfree(vmx->guest_msrs); |
9066 | uninit_vcpu: | |
9067 | kvm_vcpu_uninit(&vmx->vcpu); | |
9068 | free_vcpu: | |
991e7a0e | 9069 | free_vpid(vmx->vpid); |
a4770347 | 9070 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 9071 | return ERR_PTR(err); |
6aa8b732 AK |
9072 | } |
9073 | ||
002c7f7c YS |
9074 | static void __init vmx_check_processor_compat(void *rtn) |
9075 | { | |
9076 | struct vmcs_config vmcs_conf; | |
9077 | ||
9078 | *(int *)rtn = 0; | |
9079 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
9080 | *(int *)rtn = -EIO; | |
9081 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
9082 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
9083 | smp_processor_id()); | |
9084 | *(int *)rtn = -EIO; | |
9085 | } | |
9086 | } | |
9087 | ||
67253af5 SY |
9088 | static int get_ept_level(void) |
9089 | { | |
9090 | return VMX_EPT_DEFAULT_GAW + 1; | |
9091 | } | |
9092 | ||
4b12f0de | 9093 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 9094 | { |
b18d5431 XG |
9095 | u8 cache; |
9096 | u64 ipat = 0; | |
4b12f0de | 9097 | |
522c68c4 | 9098 | /* For VT-d and EPT combination |
606decd6 | 9099 | * 1. MMIO: always map as UC |
522c68c4 SY |
9100 | * 2. EPT with VT-d: |
9101 | * a. VT-d without snooping control feature: can't guarantee the | |
606decd6 | 9102 | * result, try to trust guest. |
522c68c4 SY |
9103 | * b. VT-d with snooping control feature: snooping control feature of |
9104 | * VT-d engine can guarantee the cache correctness. Just set it | |
9105 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 9106 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
9107 | * consistent with host MTRR |
9108 | */ | |
606decd6 PB |
9109 | if (is_mmio) { |
9110 | cache = MTRR_TYPE_UNCACHABLE; | |
9111 | goto exit; | |
9112 | } | |
9113 | ||
9114 | if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { | |
b18d5431 XG |
9115 | ipat = VMX_EPT_IPAT_BIT; |
9116 | cache = MTRR_TYPE_WRBACK; | |
9117 | goto exit; | |
9118 | } | |
9119 | ||
9120 | if (kvm_read_cr0(vcpu) & X86_CR0_CD) { | |
9121 | ipat = VMX_EPT_IPAT_BIT; | |
0da029ed | 9122 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) |
fb279950 XG |
9123 | cache = MTRR_TYPE_WRBACK; |
9124 | else | |
9125 | cache = MTRR_TYPE_UNCACHABLE; | |
b18d5431 XG |
9126 | goto exit; |
9127 | } | |
9128 | ||
ff53604b | 9129 | cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); |
b18d5431 XG |
9130 | |
9131 | exit: | |
9132 | return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; | |
64d4d521 SY |
9133 | } |
9134 | ||
17cc3935 | 9135 | static int vmx_get_lpage_level(void) |
344f414f | 9136 | { |
878403b7 SY |
9137 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
9138 | return PT_DIRECTORY_LEVEL; | |
9139 | else | |
9140 | /* For shadow and EPT supported 1GB page */ | |
9141 | return PT_PDPE_LEVEL; | |
344f414f JR |
9142 | } |
9143 | ||
feda805f XG |
9144 | static void vmcs_set_secondary_exec_control(u32 new_ctl) |
9145 | { | |
9146 | /* | |
9147 | * These bits in the secondary execution controls field | |
9148 | * are dynamic, the others are mostly based on the hypervisor | |
9149 | * architecture and the guest's CPUID. Do not touch the | |
9150 | * dynamic bits. | |
9151 | */ | |
9152 | u32 mask = | |
9153 | SECONDARY_EXEC_SHADOW_VMCS | | |
9154 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | | |
9155 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
9156 | ||
9157 | u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
9158 | ||
9159 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
9160 | (new_ctl & ~mask) | (cur_ctl & mask)); | |
9161 | } | |
9162 | ||
0e851880 SY |
9163 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
9164 | { | |
4e47c7a6 SY |
9165 | struct kvm_cpuid_entry2 *best; |
9166 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
feda805f | 9167 | u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx); |
4e47c7a6 | 9168 | |
4e47c7a6 | 9169 | if (vmx_rdtscp_supported()) { |
1cea0ce6 XG |
9170 | bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu); |
9171 | if (!rdtscp_enabled) | |
feda805f | 9172 | secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP; |
f36201e5 | 9173 | |
8b97265a | 9174 | if (nested) { |
1cea0ce6 | 9175 | if (rdtscp_enabled) |
8b97265a PB |
9176 | vmx->nested.nested_vmx_secondary_ctls_high |= |
9177 | SECONDARY_EXEC_RDTSCP; | |
9178 | else | |
9179 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
9180 | ~SECONDARY_EXEC_RDTSCP; | |
9181 | } | |
4e47c7a6 | 9182 | } |
ad756a16 | 9183 | |
ad756a16 MJ |
9184 | /* Exposing INVPCID only when PCID is exposed */ |
9185 | best = kvm_find_cpuid_entry(vcpu, 0x7, 0); | |
9186 | if (vmx_invpcid_supported() && | |
29541bb8 XG |
9187 | (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) || |
9188 | !guest_cpuid_has_pcid(vcpu))) { | |
feda805f | 9189 | secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID; |
29541bb8 | 9190 | |
ad756a16 | 9191 | if (best) |
4f977045 | 9192 | best->ebx &= ~bit(X86_FEATURE_INVPCID); |
ad756a16 | 9193 | } |
8b3e34e4 | 9194 | |
45bdbcfd HH |
9195 | if (cpu_has_secondary_exec_ctrls()) |
9196 | vmcs_set_secondary_exec_control(secondary_exec_ctl); | |
feda805f | 9197 | |
8b3e34e4 XG |
9198 | if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) { |
9199 | if (guest_cpuid_has_pcommit(vcpu)) | |
9200 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
9201 | SECONDARY_EXEC_PCOMMIT; | |
9202 | else | |
9203 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
9204 | ~SECONDARY_EXEC_PCOMMIT; | |
9205 | } | |
0e851880 SY |
9206 | } |
9207 | ||
d4330ef2 JR |
9208 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
9209 | { | |
7b8050f5 NHE |
9210 | if (func == 1 && nested) |
9211 | entry->ecx |= bit(X86_FEATURE_VMX); | |
d4330ef2 JR |
9212 | } |
9213 | ||
25d92081 YZ |
9214 | static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, |
9215 | struct x86_exception *fault) | |
9216 | { | |
533558bc JK |
9217 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
9218 | u32 exit_reason; | |
25d92081 YZ |
9219 | |
9220 | if (fault->error_code & PFERR_RSVD_MASK) | |
533558bc | 9221 | exit_reason = EXIT_REASON_EPT_MISCONFIG; |
25d92081 | 9222 | else |
533558bc JK |
9223 | exit_reason = EXIT_REASON_EPT_VIOLATION; |
9224 | nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification); | |
25d92081 YZ |
9225 | vmcs12->guest_physical_address = fault->address; |
9226 | } | |
9227 | ||
155a97a3 NHE |
9228 | /* Callbacks for nested_ept_init_mmu_context: */ |
9229 | ||
9230 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu) | |
9231 | { | |
9232 | /* return the page table to be shadowed - in our case, EPT12 */ | |
9233 | return get_vmcs12(vcpu)->ept_pointer; | |
9234 | } | |
9235 | ||
8a3c1a33 | 9236 | static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) |
155a97a3 | 9237 | { |
ad896af0 PB |
9238 | WARN_ON(mmu_is_nested(vcpu)); |
9239 | kvm_init_shadow_ept_mmu(vcpu, | |
b9c237bb WV |
9240 | to_vmx(vcpu)->nested.nested_vmx_ept_caps & |
9241 | VMX_EPT_EXECUTE_ONLY_BIT); | |
155a97a3 NHE |
9242 | vcpu->arch.mmu.set_cr3 = vmx_set_cr3; |
9243 | vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3; | |
9244 | vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault; | |
9245 | ||
9246 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
155a97a3 NHE |
9247 | } |
9248 | ||
9249 | static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
9250 | { | |
9251 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
9252 | } | |
9253 | ||
19d5f10b EK |
9254 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, |
9255 | u16 error_code) | |
9256 | { | |
9257 | bool inequality, bit; | |
9258 | ||
9259 | bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0; | |
9260 | inequality = | |
9261 | (error_code & vmcs12->page_fault_error_code_mask) != | |
9262 | vmcs12->page_fault_error_code_match; | |
9263 | return inequality ^ bit; | |
9264 | } | |
9265 | ||
feaf0c7d GN |
9266 | static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, |
9267 | struct x86_exception *fault) | |
9268 | { | |
9269 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
9270 | ||
9271 | WARN_ON(!is_guest_mode(vcpu)); | |
9272 | ||
19d5f10b | 9273 | if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code)) |
533558bc JK |
9274 | nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason, |
9275 | vmcs_read32(VM_EXIT_INTR_INFO), | |
9276 | vmcs_readl(EXIT_QUALIFICATION)); | |
feaf0c7d GN |
9277 | else |
9278 | kvm_inject_page_fault(vcpu, fault); | |
9279 | } | |
9280 | ||
a2bcba50 WL |
9281 | static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu, |
9282 | struct vmcs12 *vmcs12) | |
9283 | { | |
9284 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9090422f | 9285 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
a2bcba50 WL |
9286 | |
9287 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
9090422f EK |
9288 | if (!PAGE_ALIGNED(vmcs12->apic_access_addr) || |
9289 | vmcs12->apic_access_addr >> maxphyaddr) | |
a2bcba50 WL |
9290 | return false; |
9291 | ||
9292 | /* | |
9293 | * Translate L1 physical address to host physical | |
9294 | * address for vmcs02. Keep the page pinned, so this | |
9295 | * physical address remains valid. We keep a reference | |
9296 | * to it so we can release it later. | |
9297 | */ | |
9298 | if (vmx->nested.apic_access_page) /* shouldn't happen */ | |
9299 | nested_release_page(vmx->nested.apic_access_page); | |
9300 | vmx->nested.apic_access_page = | |
9301 | nested_get_page(vcpu, vmcs12->apic_access_addr); | |
9302 | } | |
a7c0b07d WL |
9303 | |
9304 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
9090422f EK |
9305 | if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) || |
9306 | vmcs12->virtual_apic_page_addr >> maxphyaddr) | |
a7c0b07d WL |
9307 | return false; |
9308 | ||
9309 | if (vmx->nested.virtual_apic_page) /* shouldn't happen */ | |
9310 | nested_release_page(vmx->nested.virtual_apic_page); | |
9311 | vmx->nested.virtual_apic_page = | |
9312 | nested_get_page(vcpu, vmcs12->virtual_apic_page_addr); | |
9313 | ||
9314 | /* | |
9315 | * Failing the vm entry is _not_ what the processor does | |
9316 | * but it's basically the only possibility we have. | |
9317 | * We could still enter the guest if CR8 load exits are | |
9318 | * enabled, CR8 store exits are enabled, and virtualize APIC | |
9319 | * access is disabled; in this case the processor would never | |
9320 | * use the TPR shadow and we could simply clear the bit from | |
9321 | * the execution control. But such a configuration is useless, | |
9322 | * so let's keep the code simple. | |
9323 | */ | |
9324 | if (!vmx->nested.virtual_apic_page) | |
9325 | return false; | |
9326 | } | |
9327 | ||
705699a1 | 9328 | if (nested_cpu_has_posted_intr(vmcs12)) { |
9090422f EK |
9329 | if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) || |
9330 | vmcs12->posted_intr_desc_addr >> maxphyaddr) | |
705699a1 WV |
9331 | return false; |
9332 | ||
9333 | if (vmx->nested.pi_desc_page) { /* shouldn't happen */ | |
9334 | kunmap(vmx->nested.pi_desc_page); | |
9335 | nested_release_page(vmx->nested.pi_desc_page); | |
9336 | } | |
9337 | vmx->nested.pi_desc_page = | |
9338 | nested_get_page(vcpu, vmcs12->posted_intr_desc_addr); | |
9339 | if (!vmx->nested.pi_desc_page) | |
9340 | return false; | |
9341 | ||
9342 | vmx->nested.pi_desc = | |
9343 | (struct pi_desc *)kmap(vmx->nested.pi_desc_page); | |
9344 | if (!vmx->nested.pi_desc) { | |
9345 | nested_release_page_clean(vmx->nested.pi_desc_page); | |
9346 | return false; | |
9347 | } | |
9348 | vmx->nested.pi_desc = | |
9349 | (struct pi_desc *)((void *)vmx->nested.pi_desc + | |
9350 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
9351 | (PAGE_SIZE - 1))); | |
9352 | } | |
9353 | ||
a2bcba50 WL |
9354 | return true; |
9355 | } | |
9356 | ||
f4124500 JK |
9357 | static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu) |
9358 | { | |
9359 | u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value; | |
9360 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9361 | ||
9362 | if (vcpu->arch.virtual_tsc_khz == 0) | |
9363 | return; | |
9364 | ||
9365 | /* Make sure short timeouts reliably trigger an immediate vmexit. | |
9366 | * hrtimer_start does not guarantee this. */ | |
9367 | if (preemption_timeout <= 1) { | |
9368 | vmx_preemption_timer_fn(&vmx->nested.preemption_timer); | |
9369 | return; | |
9370 | } | |
9371 | ||
9372 | preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
9373 | preemption_timeout *= 1000000; | |
9374 | do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); | |
9375 | hrtimer_start(&vmx->nested.preemption_timer, | |
9376 | ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL); | |
9377 | } | |
9378 | ||
3af18d9c WV |
9379 | static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, |
9380 | struct vmcs12 *vmcs12) | |
9381 | { | |
9382 | int maxphyaddr; | |
9383 | u64 addr; | |
9384 | ||
9385 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) | |
9386 | return 0; | |
9387 | ||
9388 | if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) { | |
9389 | WARN_ON(1); | |
9390 | return -EINVAL; | |
9391 | } | |
9392 | maxphyaddr = cpuid_maxphyaddr(vcpu); | |
9393 | ||
9394 | if (!PAGE_ALIGNED(vmcs12->msr_bitmap) || | |
9395 | ((addr + PAGE_SIZE) >> maxphyaddr)) | |
9396 | return -EINVAL; | |
9397 | ||
9398 | return 0; | |
9399 | } | |
9400 | ||
9401 | /* | |
9402 | * Merge L0's and L1's MSR bitmap, return false to indicate that | |
9403 | * we do not use the hardware. | |
9404 | */ | |
9405 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, | |
9406 | struct vmcs12 *vmcs12) | |
9407 | { | |
82f0dd4b | 9408 | int msr; |
f2b93280 WV |
9409 | struct page *page; |
9410 | unsigned long *msr_bitmap; | |
9411 | ||
9412 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12)) | |
9413 | return false; | |
9414 | ||
9415 | page = nested_get_page(vcpu, vmcs12->msr_bitmap); | |
9416 | if (!page) { | |
9417 | WARN_ON(1); | |
9418 | return false; | |
9419 | } | |
9420 | msr_bitmap = (unsigned long *)kmap(page); | |
9421 | if (!msr_bitmap) { | |
9422 | nested_release_page_clean(page); | |
9423 | WARN_ON(1); | |
9424 | return false; | |
9425 | } | |
9426 | ||
9427 | if (nested_cpu_has_virt_x2apic_mode(vmcs12)) { | |
82f0dd4b WV |
9428 | if (nested_cpu_has_apic_reg_virt(vmcs12)) |
9429 | for (msr = 0x800; msr <= 0x8ff; msr++) | |
9430 | nested_vmx_disable_intercept_for_msr( | |
9431 | msr_bitmap, | |
9432 | vmx_msr_bitmap_nested, | |
9433 | msr, MSR_TYPE_R); | |
f2b93280 WV |
9434 | /* TPR is allowed */ |
9435 | nested_vmx_disable_intercept_for_msr(msr_bitmap, | |
9436 | vmx_msr_bitmap_nested, | |
9437 | APIC_BASE_MSR + (APIC_TASKPRI >> 4), | |
9438 | MSR_TYPE_R | MSR_TYPE_W); | |
608406e2 WV |
9439 | if (nested_cpu_has_vid(vmcs12)) { |
9440 | /* EOI and self-IPI are allowed */ | |
9441 | nested_vmx_disable_intercept_for_msr( | |
9442 | msr_bitmap, | |
9443 | vmx_msr_bitmap_nested, | |
9444 | APIC_BASE_MSR + (APIC_EOI >> 4), | |
9445 | MSR_TYPE_W); | |
9446 | nested_vmx_disable_intercept_for_msr( | |
9447 | msr_bitmap, | |
9448 | vmx_msr_bitmap_nested, | |
9449 | APIC_BASE_MSR + (APIC_SELF_IPI >> 4), | |
9450 | MSR_TYPE_W); | |
9451 | } | |
82f0dd4b WV |
9452 | } else { |
9453 | /* | |
9454 | * Enable reading intercept of all the x2apic | |
9455 | * MSRs. We should not rely on vmcs12 to do any | |
9456 | * optimizations here, it may have been modified | |
9457 | * by L1. | |
9458 | */ | |
9459 | for (msr = 0x800; msr <= 0x8ff; msr++) | |
9460 | __vmx_enable_intercept_for_msr( | |
9461 | vmx_msr_bitmap_nested, | |
9462 | msr, | |
9463 | MSR_TYPE_R); | |
9464 | ||
f2b93280 WV |
9465 | __vmx_enable_intercept_for_msr( |
9466 | vmx_msr_bitmap_nested, | |
9467 | APIC_BASE_MSR + (APIC_TASKPRI >> 4), | |
82f0dd4b | 9468 | MSR_TYPE_W); |
608406e2 WV |
9469 | __vmx_enable_intercept_for_msr( |
9470 | vmx_msr_bitmap_nested, | |
9471 | APIC_BASE_MSR + (APIC_EOI >> 4), | |
9472 | MSR_TYPE_W); | |
9473 | __vmx_enable_intercept_for_msr( | |
9474 | vmx_msr_bitmap_nested, | |
9475 | APIC_BASE_MSR + (APIC_SELF_IPI >> 4), | |
9476 | MSR_TYPE_W); | |
82f0dd4b | 9477 | } |
f2b93280 WV |
9478 | kunmap(page); |
9479 | nested_release_page_clean(page); | |
9480 | ||
9481 | return true; | |
9482 | } | |
9483 | ||
9484 | static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu, | |
9485 | struct vmcs12 *vmcs12) | |
9486 | { | |
82f0dd4b | 9487 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && |
608406e2 | 9488 | !nested_cpu_has_apic_reg_virt(vmcs12) && |
705699a1 WV |
9489 | !nested_cpu_has_vid(vmcs12) && |
9490 | !nested_cpu_has_posted_intr(vmcs12)) | |
f2b93280 WV |
9491 | return 0; |
9492 | ||
9493 | /* | |
9494 | * If virtualize x2apic mode is enabled, | |
9495 | * virtualize apic access must be disabled. | |
9496 | */ | |
82f0dd4b WV |
9497 | if (nested_cpu_has_virt_x2apic_mode(vmcs12) && |
9498 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
f2b93280 WV |
9499 | return -EINVAL; |
9500 | ||
608406e2 WV |
9501 | /* |
9502 | * If virtual interrupt delivery is enabled, | |
9503 | * we must exit on external interrupts. | |
9504 | */ | |
9505 | if (nested_cpu_has_vid(vmcs12) && | |
9506 | !nested_exit_on_intr(vcpu)) | |
9507 | return -EINVAL; | |
9508 | ||
705699a1 WV |
9509 | /* |
9510 | * bits 15:8 should be zero in posted_intr_nv, | |
9511 | * the descriptor address has been already checked | |
9512 | * in nested_get_vmcs12_pages. | |
9513 | */ | |
9514 | if (nested_cpu_has_posted_intr(vmcs12) && | |
9515 | (!nested_cpu_has_vid(vmcs12) || | |
9516 | !nested_exit_intr_ack_set(vcpu) || | |
9517 | vmcs12->posted_intr_nv & 0xff00)) | |
9518 | return -EINVAL; | |
9519 | ||
f2b93280 WV |
9520 | /* tpr shadow is needed by all apicv features. */ |
9521 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
9522 | return -EINVAL; | |
9523 | ||
9524 | return 0; | |
3af18d9c WV |
9525 | } |
9526 | ||
e9ac033e EK |
9527 | static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu, |
9528 | unsigned long count_field, | |
92d71bc6 | 9529 | unsigned long addr_field) |
ff651cb6 | 9530 | { |
92d71bc6 | 9531 | int maxphyaddr; |
e9ac033e EK |
9532 | u64 count, addr; |
9533 | ||
9534 | if (vmcs12_read_any(vcpu, count_field, &count) || | |
9535 | vmcs12_read_any(vcpu, addr_field, &addr)) { | |
9536 | WARN_ON(1); | |
9537 | return -EINVAL; | |
9538 | } | |
9539 | if (count == 0) | |
9540 | return 0; | |
92d71bc6 | 9541 | maxphyaddr = cpuid_maxphyaddr(vcpu); |
e9ac033e EK |
9542 | if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr || |
9543 | (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) { | |
9544 | pr_warn_ratelimited( | |
9545 | "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)", | |
9546 | addr_field, maxphyaddr, count, addr); | |
9547 | return -EINVAL; | |
9548 | } | |
9549 | return 0; | |
9550 | } | |
9551 | ||
9552 | static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu, | |
9553 | struct vmcs12 *vmcs12) | |
9554 | { | |
e9ac033e EK |
9555 | if (vmcs12->vm_exit_msr_load_count == 0 && |
9556 | vmcs12->vm_exit_msr_store_count == 0 && | |
9557 | vmcs12->vm_entry_msr_load_count == 0) | |
9558 | return 0; /* Fast path */ | |
e9ac033e | 9559 | if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT, |
92d71bc6 | 9560 | VM_EXIT_MSR_LOAD_ADDR) || |
e9ac033e | 9561 | nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT, |
92d71bc6 | 9562 | VM_EXIT_MSR_STORE_ADDR) || |
e9ac033e | 9563 | nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT, |
92d71bc6 | 9564 | VM_ENTRY_MSR_LOAD_ADDR)) |
e9ac033e EK |
9565 | return -EINVAL; |
9566 | return 0; | |
9567 | } | |
9568 | ||
9569 | static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu, | |
9570 | struct vmx_msr_entry *e) | |
9571 | { | |
9572 | /* x2APIC MSR accesses are not allowed */ | |
8a9781f7 | 9573 | if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8) |
e9ac033e EK |
9574 | return -EINVAL; |
9575 | if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */ | |
9576 | e->index == MSR_IA32_UCODE_REV) | |
9577 | return -EINVAL; | |
9578 | if (e->reserved != 0) | |
ff651cb6 WV |
9579 | return -EINVAL; |
9580 | return 0; | |
9581 | } | |
9582 | ||
e9ac033e EK |
9583 | static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu, |
9584 | struct vmx_msr_entry *e) | |
ff651cb6 WV |
9585 | { |
9586 | if (e->index == MSR_FS_BASE || | |
9587 | e->index == MSR_GS_BASE || | |
e9ac033e EK |
9588 | e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */ |
9589 | nested_vmx_msr_check_common(vcpu, e)) | |
9590 | return -EINVAL; | |
9591 | return 0; | |
9592 | } | |
9593 | ||
9594 | static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu, | |
9595 | struct vmx_msr_entry *e) | |
9596 | { | |
9597 | if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */ | |
9598 | nested_vmx_msr_check_common(vcpu, e)) | |
ff651cb6 WV |
9599 | return -EINVAL; |
9600 | return 0; | |
9601 | } | |
9602 | ||
9603 | /* | |
9604 | * Load guest's/host's msr at nested entry/exit. | |
9605 | * return 0 for success, entry index for failure. | |
9606 | */ | |
9607 | static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
9608 | { | |
9609 | u32 i; | |
9610 | struct vmx_msr_entry e; | |
9611 | struct msr_data msr; | |
9612 | ||
9613 | msr.host_initiated = false; | |
9614 | for (i = 0; i < count; i++) { | |
54bf36aa PB |
9615 | if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e), |
9616 | &e, sizeof(e))) { | |
e9ac033e EK |
9617 | pr_warn_ratelimited( |
9618 | "%s cannot read MSR entry (%u, 0x%08llx)\n", | |
9619 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 9620 | goto fail; |
e9ac033e EK |
9621 | } |
9622 | if (nested_vmx_load_msr_check(vcpu, &e)) { | |
9623 | pr_warn_ratelimited( | |
9624 | "%s check failed (%u, 0x%x, 0x%x)\n", | |
9625 | __func__, i, e.index, e.reserved); | |
9626 | goto fail; | |
9627 | } | |
ff651cb6 WV |
9628 | msr.index = e.index; |
9629 | msr.data = e.value; | |
e9ac033e EK |
9630 | if (kvm_set_msr(vcpu, &msr)) { |
9631 | pr_warn_ratelimited( | |
9632 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", | |
9633 | __func__, i, e.index, e.value); | |
ff651cb6 | 9634 | goto fail; |
e9ac033e | 9635 | } |
ff651cb6 WV |
9636 | } |
9637 | return 0; | |
9638 | fail: | |
9639 | return i + 1; | |
9640 | } | |
9641 | ||
9642 | static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
9643 | { | |
9644 | u32 i; | |
9645 | struct vmx_msr_entry e; | |
9646 | ||
9647 | for (i = 0; i < count; i++) { | |
609e36d3 | 9648 | struct msr_data msr_info; |
54bf36aa PB |
9649 | if (kvm_vcpu_read_guest(vcpu, |
9650 | gpa + i * sizeof(e), | |
9651 | &e, 2 * sizeof(u32))) { | |
e9ac033e EK |
9652 | pr_warn_ratelimited( |
9653 | "%s cannot read MSR entry (%u, 0x%08llx)\n", | |
9654 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 9655 | return -EINVAL; |
e9ac033e EK |
9656 | } |
9657 | if (nested_vmx_store_msr_check(vcpu, &e)) { | |
9658 | pr_warn_ratelimited( | |
9659 | "%s check failed (%u, 0x%x, 0x%x)\n", | |
9660 | __func__, i, e.index, e.reserved); | |
ff651cb6 | 9661 | return -EINVAL; |
e9ac033e | 9662 | } |
609e36d3 PB |
9663 | msr_info.host_initiated = false; |
9664 | msr_info.index = e.index; | |
9665 | if (kvm_get_msr(vcpu, &msr_info)) { | |
e9ac033e EK |
9666 | pr_warn_ratelimited( |
9667 | "%s cannot read MSR (%u, 0x%x)\n", | |
9668 | __func__, i, e.index); | |
9669 | return -EINVAL; | |
9670 | } | |
54bf36aa PB |
9671 | if (kvm_vcpu_write_guest(vcpu, |
9672 | gpa + i * sizeof(e) + | |
9673 | offsetof(struct vmx_msr_entry, value), | |
9674 | &msr_info.data, sizeof(msr_info.data))) { | |
e9ac033e EK |
9675 | pr_warn_ratelimited( |
9676 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", | |
609e36d3 | 9677 | __func__, i, e.index, msr_info.data); |
e9ac033e EK |
9678 | return -EINVAL; |
9679 | } | |
ff651cb6 WV |
9680 | } |
9681 | return 0; | |
9682 | } | |
9683 | ||
fe3ef05c NHE |
9684 | /* |
9685 | * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested | |
9686 | * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it | |
b4619660 | 9687 | * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 |
fe3ef05c NHE |
9688 | * guest in a way that will both be appropriate to L1's requests, and our |
9689 | * needs. In addition to modifying the active vmcs (which is vmcs02), this | |
9690 | * function also has additional necessary side-effects, like setting various | |
9691 | * vcpu->arch fields. | |
9692 | */ | |
9693 | static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
9694 | { | |
9695 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9696 | u32 exec_control; | |
9697 | ||
9698 | vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); | |
9699 | vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); | |
9700 | vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); | |
9701 | vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); | |
9702 | vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); | |
9703 | vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); | |
9704 | vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); | |
9705 | vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); | |
9706 | vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); | |
9707 | vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); | |
9708 | vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); | |
9709 | vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); | |
9710 | vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); | |
9711 | vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); | |
9712 | vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); | |
9713 | vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); | |
9714 | vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); | |
9715 | vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); | |
9716 | vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); | |
9717 | vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); | |
9718 | vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); | |
9719 | vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); | |
9720 | vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); | |
9721 | vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); | |
9722 | vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); | |
9723 | vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); | |
9724 | vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); | |
9725 | vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); | |
9726 | vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); | |
9727 | vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); | |
9728 | vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); | |
9729 | vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); | |
9730 | vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); | |
9731 | vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); | |
9732 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); | |
9733 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); | |
9734 | ||
2996fca0 JK |
9735 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) { |
9736 | kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); | |
9737 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); | |
9738 | } else { | |
9739 | kvm_set_dr(vcpu, 7, vcpu->arch.dr7); | |
9740 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl); | |
9741 | } | |
fe3ef05c NHE |
9742 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
9743 | vmcs12->vm_entry_intr_info_field); | |
9744 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
9745 | vmcs12->vm_entry_exception_error_code); | |
9746 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
9747 | vmcs12->vm_entry_instruction_len); | |
9748 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
9749 | vmcs12->guest_interruptibility_info); | |
fe3ef05c | 9750 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); |
63fbf59f | 9751 | vmx_set_rflags(vcpu, vmcs12->guest_rflags); |
fe3ef05c NHE |
9752 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, |
9753 | vmcs12->guest_pending_dbg_exceptions); | |
9754 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); | |
9755 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); | |
9756 | ||
81dc01f7 WL |
9757 | if (nested_cpu_has_xsaves(vmcs12)) |
9758 | vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); | |
fe3ef05c NHE |
9759 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
9760 | ||
f4124500 JK |
9761 | exec_control = vmcs12->pin_based_vm_exec_control; |
9762 | exec_control |= vmcs_config.pin_based_exec_ctrl; | |
705699a1 WV |
9763 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; |
9764 | ||
9765 | if (nested_cpu_has_posted_intr(vmcs12)) { | |
9766 | /* | |
9767 | * Note that we use L0's vector here and in | |
9768 | * vmx_deliver_nested_posted_interrupt. | |
9769 | */ | |
9770 | vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv; | |
9771 | vmx->nested.pi_pending = false; | |
0bcf261c | 9772 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
705699a1 WV |
9773 | vmcs_write64(POSTED_INTR_DESC_ADDR, |
9774 | page_to_phys(vmx->nested.pi_desc_page) + | |
9775 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
9776 | (PAGE_SIZE - 1))); | |
9777 | } else | |
9778 | exec_control &= ~PIN_BASED_POSTED_INTR; | |
9779 | ||
f4124500 | 9780 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control); |
fe3ef05c | 9781 | |
f4124500 JK |
9782 | vmx->nested.preemption_timer_expired = false; |
9783 | if (nested_cpu_has_preemption_timer(vmcs12)) | |
9784 | vmx_start_preemption_timer(vcpu); | |
0238ea91 | 9785 | |
fe3ef05c NHE |
9786 | /* |
9787 | * Whether page-faults are trapped is determined by a combination of | |
9788 | * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. | |
9789 | * If enable_ept, L0 doesn't care about page faults and we should | |
9790 | * set all of these to L1's desires. However, if !enable_ept, L0 does | |
9791 | * care about (at least some) page faults, and because it is not easy | |
9792 | * (if at all possible?) to merge L0 and L1's desires, we simply ask | |
9793 | * to exit on each and every L2 page fault. This is done by setting | |
9794 | * MASK=MATCH=0 and (see below) EB.PF=1. | |
9795 | * Note that below we don't need special code to set EB.PF beyond the | |
9796 | * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, | |
9797 | * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when | |
9798 | * !enable_ept, EB.PF is 1, so the "or" will always be 1. | |
9799 | * | |
9800 | * A problem with this approach (when !enable_ept) is that L1 may be | |
9801 | * injected with more page faults than it asked for. This could have | |
9802 | * caused problems, but in practice existing hypervisors don't care. | |
9803 | * To fix this, we will need to emulate the PFEC checking (on the L1 | |
9804 | * page tables), using walk_addr(), when injecting PFs to L1. | |
9805 | */ | |
9806 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, | |
9807 | enable_ept ? vmcs12->page_fault_error_code_mask : 0); | |
9808 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, | |
9809 | enable_ept ? vmcs12->page_fault_error_code_match : 0); | |
9810 | ||
9811 | if (cpu_has_secondary_exec_ctrls()) { | |
f4124500 | 9812 | exec_control = vmx_secondary_exec_control(vmx); |
e2821620 | 9813 | |
fe3ef05c | 9814 | /* Take the following fields only from vmcs12 */ |
696dfd95 | 9815 | exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
b3a2a907 | 9816 | SECONDARY_EXEC_RDTSCP | |
696dfd95 | 9817 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
8b3e34e4 XG |
9818 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
9819 | SECONDARY_EXEC_PCOMMIT); | |
fe3ef05c NHE |
9820 | if (nested_cpu_has(vmcs12, |
9821 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) | |
9822 | exec_control |= vmcs12->secondary_vm_exec_control; | |
9823 | ||
9824 | if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) { | |
fe3ef05c NHE |
9825 | /* |
9826 | * If translation failed, no matter: This feature asks | |
9827 | * to exit when accessing the given address, and if it | |
9828 | * can never be accessed, this feature won't do | |
9829 | * anything anyway. | |
9830 | */ | |
9831 | if (!vmx->nested.apic_access_page) | |
9832 | exec_control &= | |
9833 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
9834 | else | |
9835 | vmcs_write64(APIC_ACCESS_ADDR, | |
9836 | page_to_phys(vmx->nested.apic_access_page)); | |
f2b93280 | 9837 | } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) && |
35754c98 | 9838 | cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
ca3f257a JK |
9839 | exec_control |= |
9840 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
38b99173 | 9841 | kvm_vcpu_reload_apic_access_page(vcpu); |
fe3ef05c NHE |
9842 | } |
9843 | ||
608406e2 WV |
9844 | if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { |
9845 | vmcs_write64(EOI_EXIT_BITMAP0, | |
9846 | vmcs12->eoi_exit_bitmap0); | |
9847 | vmcs_write64(EOI_EXIT_BITMAP1, | |
9848 | vmcs12->eoi_exit_bitmap1); | |
9849 | vmcs_write64(EOI_EXIT_BITMAP2, | |
9850 | vmcs12->eoi_exit_bitmap2); | |
9851 | vmcs_write64(EOI_EXIT_BITMAP3, | |
9852 | vmcs12->eoi_exit_bitmap3); | |
9853 | vmcs_write16(GUEST_INTR_STATUS, | |
9854 | vmcs12->guest_intr_status); | |
9855 | } | |
9856 | ||
fe3ef05c NHE |
9857 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
9858 | } | |
9859 | ||
9860 | ||
9861 | /* | |
9862 | * Set host-state according to L0's settings (vmcs12 is irrelevant here) | |
9863 | * Some constant fields are set here by vmx_set_constant_host_state(). | |
9864 | * Other fields are different per CPU, and will be set later when | |
9865 | * vmx_vcpu_load() is called, and when vmx_save_host_state() is called. | |
9866 | */ | |
a547c6db | 9867 | vmx_set_constant_host_state(vmx); |
fe3ef05c NHE |
9868 | |
9869 | /* | |
9870 | * HOST_RSP is normally set correctly in vmx_vcpu_run() just before | |
9871 | * entry, but only if the current (host) sp changed from the value | |
9872 | * we wrote last (vmx->host_rsp). This cache is no longer relevant | |
9873 | * if we switch vmcs, and rather than hold a separate cache per vmcs, | |
9874 | * here we just force the write to happen on entry. | |
9875 | */ | |
9876 | vmx->host_rsp = 0; | |
9877 | ||
9878 | exec_control = vmx_exec_control(vmx); /* L0's desires */ | |
9879 | exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
9880 | exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
9881 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
9882 | exec_control |= vmcs12->cpu_based_vm_exec_control; | |
a7c0b07d WL |
9883 | |
9884 | if (exec_control & CPU_BASED_TPR_SHADOW) { | |
9885 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
9886 | page_to_phys(vmx->nested.virtual_apic_page)); | |
9887 | vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); | |
9888 | } | |
9889 | ||
3af18d9c | 9890 | if (cpu_has_vmx_msr_bitmap() && |
670125bd WV |
9891 | exec_control & CPU_BASED_USE_MSR_BITMAPS) { |
9892 | nested_vmx_merge_msr_bitmap(vcpu, vmcs12); | |
9893 | /* MSR_BITMAP will be set by following vmx_set_efer. */ | |
3af18d9c WV |
9894 | } else |
9895 | exec_control &= ~CPU_BASED_USE_MSR_BITMAPS; | |
9896 | ||
fe3ef05c | 9897 | /* |
3af18d9c | 9898 | * Merging of IO bitmap not currently supported. |
fe3ef05c NHE |
9899 | * Rather, exit every time. |
9900 | */ | |
fe3ef05c NHE |
9901 | exec_control &= ~CPU_BASED_USE_IO_BITMAPS; |
9902 | exec_control |= CPU_BASED_UNCOND_IO_EXITING; | |
9903 | ||
9904 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
9905 | ||
9906 | /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the | |
9907 | * bitwise-or of what L1 wants to trap for L2, and what we want to | |
9908 | * trap. Note that CR0.TS also needs updating - we do this later. | |
9909 | */ | |
9910 | update_exception_bitmap(vcpu); | |
9911 | vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; | |
9912 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
9913 | ||
8049d651 NHE |
9914 | /* L2->L1 exit controls are emulated - the hardware exit is to L0 so |
9915 | * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER | |
9916 | * bits are further modified by vmx_set_efer() below. | |
9917 | */ | |
f4124500 | 9918 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
8049d651 NHE |
9919 | |
9920 | /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are | |
9921 | * emulated by vmx_set_efer(), below. | |
9922 | */ | |
2961e876 | 9923 | vm_entry_controls_init(vmx, |
8049d651 NHE |
9924 | (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER & |
9925 | ~VM_ENTRY_IA32E_MODE) | | |
fe3ef05c NHE |
9926 | (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE)); |
9927 | ||
44811c02 | 9928 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) { |
fe3ef05c | 9929 | vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); |
44811c02 JK |
9930 | vcpu->arch.pat = vmcs12->guest_ia32_pat; |
9931 | } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) | |
fe3ef05c NHE |
9932 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); |
9933 | ||
9934 | ||
9935 | set_cr4_guest_host_mask(vmx); | |
9936 | ||
36be0b9d PB |
9937 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) |
9938 | vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); | |
9939 | ||
27fc51b2 NHE |
9940 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
9941 | vmcs_write64(TSC_OFFSET, | |
9942 | vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset); | |
9943 | else | |
9944 | vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset); | |
fe3ef05c NHE |
9945 | |
9946 | if (enable_vpid) { | |
9947 | /* | |
5c614b35 WL |
9948 | * There is no direct mapping between vpid02 and vpid12, the |
9949 | * vpid02 is per-vCPU for L0 and reused while the value of | |
9950 | * vpid12 is changed w/ one invvpid during nested vmentry. | |
9951 | * The vpid12 is allocated by L1 for L2, so it will not | |
9952 | * influence global bitmap(for vpid01 and vpid02 allocation) | |
9953 | * even if spawn a lot of nested vCPUs. | |
fe3ef05c | 9954 | */ |
5c614b35 WL |
9955 | if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) { |
9956 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02); | |
9957 | if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) { | |
9958 | vmx->nested.last_vpid = vmcs12->virtual_processor_id; | |
9959 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02); | |
9960 | } | |
9961 | } else { | |
9962 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
9963 | vmx_flush_tlb(vcpu); | |
9964 | } | |
9965 | ||
fe3ef05c NHE |
9966 | } |
9967 | ||
155a97a3 NHE |
9968 | if (nested_cpu_has_ept(vmcs12)) { |
9969 | kvm_mmu_unload(vcpu); | |
9970 | nested_ept_init_mmu_context(vcpu); | |
9971 | } | |
9972 | ||
fe3ef05c NHE |
9973 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) |
9974 | vcpu->arch.efer = vmcs12->guest_ia32_efer; | |
d1fa0352 | 9975 | else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) |
fe3ef05c NHE |
9976 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
9977 | else | |
9978 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
9979 | /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ | |
9980 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
9981 | ||
9982 | /* | |
9983 | * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified | |
9984 | * TS bit (for lazy fpu) and bits which we consider mandatory enabled. | |
9985 | * The CR0_READ_SHADOW is what L2 should have expected to read given | |
9986 | * the specifications by L1; It's not enough to take | |
9987 | * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we | |
9988 | * have more bits than L1 expected. | |
9989 | */ | |
9990 | vmx_set_cr0(vcpu, vmcs12->guest_cr0); | |
9991 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
9992 | ||
9993 | vmx_set_cr4(vcpu, vmcs12->guest_cr4); | |
9994 | vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); | |
9995 | ||
9996 | /* shadow page tables on either EPT or shadow page tables */ | |
9997 | kvm_set_cr3(vcpu, vmcs12->guest_cr3); | |
9998 | kvm_mmu_reset_context(vcpu); | |
9999 | ||
feaf0c7d GN |
10000 | if (!enable_ept) |
10001 | vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; | |
10002 | ||
3633cfc3 NHE |
10003 | /* |
10004 | * L1 may access the L2's PDPTR, so save them to construct vmcs12 | |
10005 | */ | |
10006 | if (enable_ept) { | |
10007 | vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); | |
10008 | vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); | |
10009 | vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); | |
10010 | vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); | |
10011 | } | |
10012 | ||
fe3ef05c NHE |
10013 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp); |
10014 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip); | |
10015 | } | |
10016 | ||
cd232ad0 NHE |
10017 | /* |
10018 | * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 | |
10019 | * for running an L2 nested guest. | |
10020 | */ | |
10021 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) | |
10022 | { | |
10023 | struct vmcs12 *vmcs12; | |
10024 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10025 | int cpu; | |
10026 | struct loaded_vmcs *vmcs02; | |
384bb783 | 10027 | bool ia32e; |
ff651cb6 | 10028 | u32 msr_entry_idx; |
cd232ad0 NHE |
10029 | |
10030 | if (!nested_vmx_check_permission(vcpu) || | |
10031 | !nested_vmx_check_vmcs12(vcpu)) | |
10032 | return 1; | |
10033 | ||
10034 | skip_emulated_instruction(vcpu); | |
10035 | vmcs12 = get_vmcs12(vcpu); | |
10036 | ||
012f83cb AG |
10037 | if (enable_shadow_vmcs) |
10038 | copy_shadow_to_vmcs12(vmx); | |
10039 | ||
7c177938 NHE |
10040 | /* |
10041 | * The nested entry process starts with enforcing various prerequisites | |
10042 | * on vmcs12 as required by the Intel SDM, and act appropriately when | |
10043 | * they fail: As the SDM explains, some conditions should cause the | |
10044 | * instruction to fail, while others will cause the instruction to seem | |
10045 | * to succeed, but return an EXIT_REASON_INVALID_STATE. | |
10046 | * To speed up the normal (success) code path, we should avoid checking | |
10047 | * for misconfigurations which will anyway be caught by the processor | |
10048 | * when using the merged vmcs02. | |
10049 | */ | |
10050 | if (vmcs12->launch_state == launch) { | |
10051 | nested_vmx_failValid(vcpu, | |
10052 | launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS | |
10053 | : VMXERR_VMRESUME_NONLAUNCHED_VMCS); | |
10054 | return 1; | |
10055 | } | |
10056 | ||
6dfacadd JK |
10057 | if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && |
10058 | vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) { | |
26539bd0 PB |
10059 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
10060 | return 1; | |
10061 | } | |
10062 | ||
3af18d9c | 10063 | if (!nested_get_vmcs12_pages(vcpu, vmcs12)) { |
7c177938 NHE |
10064 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
10065 | return 1; | |
10066 | } | |
10067 | ||
3af18d9c | 10068 | if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) { |
7c177938 NHE |
10069 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
10070 | return 1; | |
10071 | } | |
10072 | ||
f2b93280 WV |
10073 | if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) { |
10074 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
10075 | return 1; | |
10076 | } | |
10077 | ||
e9ac033e EK |
10078 | if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) { |
10079 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
10080 | return 1; | |
10081 | } | |
10082 | ||
7c177938 | 10083 | if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, |
b9c237bb WV |
10084 | vmx->nested.nested_vmx_true_procbased_ctls_low, |
10085 | vmx->nested.nested_vmx_procbased_ctls_high) || | |
7c177938 | 10086 | !vmx_control_verify(vmcs12->secondary_vm_exec_control, |
b9c237bb WV |
10087 | vmx->nested.nested_vmx_secondary_ctls_low, |
10088 | vmx->nested.nested_vmx_secondary_ctls_high) || | |
7c177938 | 10089 | !vmx_control_verify(vmcs12->pin_based_vm_exec_control, |
b9c237bb WV |
10090 | vmx->nested.nested_vmx_pinbased_ctls_low, |
10091 | vmx->nested.nested_vmx_pinbased_ctls_high) || | |
7c177938 | 10092 | !vmx_control_verify(vmcs12->vm_exit_controls, |
b9c237bb WV |
10093 | vmx->nested.nested_vmx_true_exit_ctls_low, |
10094 | vmx->nested.nested_vmx_exit_ctls_high) || | |
7c177938 | 10095 | !vmx_control_verify(vmcs12->vm_entry_controls, |
b9c237bb WV |
10096 | vmx->nested.nested_vmx_true_entry_ctls_low, |
10097 | vmx->nested.nested_vmx_entry_ctls_high)) | |
7c177938 NHE |
10098 | { |
10099 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
10100 | return 1; | |
10101 | } | |
10102 | ||
10103 | if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) || | |
10104 | ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) { | |
10105 | nested_vmx_failValid(vcpu, | |
10106 | VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); | |
10107 | return 1; | |
10108 | } | |
10109 | ||
b9c237bb | 10110 | if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) || |
7c177938 NHE |
10111 | ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) { |
10112 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10113 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
10114 | return 1; | |
10115 | } | |
10116 | if (vmcs12->vmcs_link_pointer != -1ull) { | |
10117 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10118 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR); | |
10119 | return 1; | |
10120 | } | |
10121 | ||
384bb783 | 10122 | /* |
cb0c8cda | 10123 | * If the load IA32_EFER VM-entry control is 1, the following checks |
384bb783 JK |
10124 | * are performed on the field for the IA32_EFER MSR: |
10125 | * - Bits reserved in the IA32_EFER MSR must be 0. | |
10126 | * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of | |
10127 | * the IA-32e mode guest VM-exit control. It must also be identical | |
10128 | * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to | |
10129 | * CR0.PG) is 1. | |
10130 | */ | |
10131 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) { | |
10132 | ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; | |
10133 | if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) || | |
10134 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) || | |
10135 | ((vmcs12->guest_cr0 & X86_CR0_PG) && | |
10136 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) { | |
10137 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10138 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
10139 | return 1; | |
10140 | } | |
10141 | } | |
10142 | ||
10143 | /* | |
10144 | * If the load IA32_EFER VM-exit control is 1, bits reserved in the | |
10145 | * IA32_EFER MSR must be 0 in the field for that register. In addition, | |
10146 | * the values of the LMA and LME bits in the field must each be that of | |
10147 | * the host address-space size VM-exit control. | |
10148 | */ | |
10149 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { | |
10150 | ia32e = (vmcs12->vm_exit_controls & | |
10151 | VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0; | |
10152 | if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) || | |
10153 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) || | |
10154 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) { | |
10155 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10156 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
10157 | return 1; | |
10158 | } | |
10159 | } | |
10160 | ||
7c177938 NHE |
10161 | /* |
10162 | * We're finally done with prerequisite checking, and can start with | |
10163 | * the nested entry. | |
10164 | */ | |
10165 | ||
cd232ad0 NHE |
10166 | vmcs02 = nested_get_current_vmcs02(vmx); |
10167 | if (!vmcs02) | |
10168 | return -ENOMEM; | |
10169 | ||
10170 | enter_guest_mode(vcpu); | |
10171 | ||
10172 | vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET); | |
10173 | ||
2996fca0 JK |
10174 | if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) |
10175 | vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
10176 | ||
cd232ad0 NHE |
10177 | cpu = get_cpu(); |
10178 | vmx->loaded_vmcs = vmcs02; | |
10179 | vmx_vcpu_put(vcpu); | |
10180 | vmx_vcpu_load(vcpu, cpu); | |
10181 | vcpu->cpu = cpu; | |
10182 | put_cpu(); | |
10183 | ||
36c3cc42 JK |
10184 | vmx_segment_cache_clear(vmx); |
10185 | ||
cd232ad0 NHE |
10186 | prepare_vmcs02(vcpu, vmcs12); |
10187 | ||
ff651cb6 WV |
10188 | msr_entry_idx = nested_vmx_load_msr(vcpu, |
10189 | vmcs12->vm_entry_msr_load_addr, | |
10190 | vmcs12->vm_entry_msr_load_count); | |
10191 | if (msr_entry_idx) { | |
10192 | leave_guest_mode(vcpu); | |
10193 | vmx_load_vmcs01(vcpu); | |
10194 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10195 | EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx); | |
10196 | return 1; | |
10197 | } | |
10198 | ||
10199 | vmcs12->launch_state = 1; | |
10200 | ||
6dfacadd | 10201 | if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) |
5cb56059 | 10202 | return kvm_vcpu_halt(vcpu); |
6dfacadd | 10203 | |
7af40ad3 JK |
10204 | vmx->nested.nested_run_pending = 1; |
10205 | ||
cd232ad0 NHE |
10206 | /* |
10207 | * Note no nested_vmx_succeed or nested_vmx_fail here. At this point | |
10208 | * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet | |
10209 | * returned as far as L1 is concerned. It will only return (and set | |
10210 | * the success flag) when L2 exits (see nested_vmx_vmexit()). | |
10211 | */ | |
10212 | return 1; | |
10213 | } | |
10214 | ||
4704d0be NHE |
10215 | /* |
10216 | * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date | |
10217 | * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK). | |
10218 | * This function returns the new value we should put in vmcs12.guest_cr0. | |
10219 | * It's not enough to just return the vmcs02 GUEST_CR0. Rather, | |
10220 | * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now | |
10221 | * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 | |
10222 | * didn't trap the bit, because if L1 did, so would L0). | |
10223 | * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have | |
10224 | * been modified by L2, and L1 knows it. So just leave the old value of | |
10225 | * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 | |
10226 | * isn't relevant, because if L0 traps this bit it can set it to anything. | |
10227 | * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have | |
10228 | * changed these bits, and therefore they need to be updated, but L0 | |
10229 | * didn't necessarily allow them to be changed in GUEST_CR0 - and rather | |
10230 | * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. | |
10231 | */ | |
10232 | static inline unsigned long | |
10233 | vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
10234 | { | |
10235 | return | |
10236 | /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | | |
10237 | /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | | |
10238 | /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | | |
10239 | vcpu->arch.cr0_guest_owned_bits)); | |
10240 | } | |
10241 | ||
10242 | static inline unsigned long | |
10243 | vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
10244 | { | |
10245 | return | |
10246 | /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | | |
10247 | /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | | |
10248 | /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | | |
10249 | vcpu->arch.cr4_guest_owned_bits)); | |
10250 | } | |
10251 | ||
5f3d5799 JK |
10252 | static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, |
10253 | struct vmcs12 *vmcs12) | |
10254 | { | |
10255 | u32 idt_vectoring; | |
10256 | unsigned int nr; | |
10257 | ||
851eb667 | 10258 | if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) { |
5f3d5799 JK |
10259 | nr = vcpu->arch.exception.nr; |
10260 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
10261 | ||
10262 | if (kvm_exception_is_soft(nr)) { | |
10263 | vmcs12->vm_exit_instruction_len = | |
10264 | vcpu->arch.event_exit_inst_len; | |
10265 | idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; | |
10266 | } else | |
10267 | idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; | |
10268 | ||
10269 | if (vcpu->arch.exception.has_error_code) { | |
10270 | idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; | |
10271 | vmcs12->idt_vectoring_error_code = | |
10272 | vcpu->arch.exception.error_code; | |
10273 | } | |
10274 | ||
10275 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
cd2633c5 | 10276 | } else if (vcpu->arch.nmi_injected) { |
5f3d5799 JK |
10277 | vmcs12->idt_vectoring_info_field = |
10278 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; | |
10279 | } else if (vcpu->arch.interrupt.pending) { | |
10280 | nr = vcpu->arch.interrupt.nr; | |
10281 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
10282 | ||
10283 | if (vcpu->arch.interrupt.soft) { | |
10284 | idt_vectoring |= INTR_TYPE_SOFT_INTR; | |
10285 | vmcs12->vm_entry_instruction_len = | |
10286 | vcpu->arch.event_exit_inst_len; | |
10287 | } else | |
10288 | idt_vectoring |= INTR_TYPE_EXT_INTR; | |
10289 | ||
10290 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
10291 | } | |
10292 | } | |
10293 | ||
b6b8a145 JK |
10294 | static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) |
10295 | { | |
10296 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10297 | ||
f4124500 JK |
10298 | if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && |
10299 | vmx->nested.preemption_timer_expired) { | |
10300 | if (vmx->nested.nested_run_pending) | |
10301 | return -EBUSY; | |
10302 | nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); | |
10303 | return 0; | |
10304 | } | |
10305 | ||
b6b8a145 | 10306 | if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) { |
220c5672 JK |
10307 | if (vmx->nested.nested_run_pending || |
10308 | vcpu->arch.interrupt.pending) | |
b6b8a145 JK |
10309 | return -EBUSY; |
10310 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
10311 | NMI_VECTOR | INTR_TYPE_NMI_INTR | | |
10312 | INTR_INFO_VALID_MASK, 0); | |
10313 | /* | |
10314 | * The NMI-triggered VM exit counts as injection: | |
10315 | * clear this one and block further NMIs. | |
10316 | */ | |
10317 | vcpu->arch.nmi_pending = 0; | |
10318 | vmx_set_nmi_mask(vcpu, true); | |
10319 | return 0; | |
10320 | } | |
10321 | ||
10322 | if ((kvm_cpu_has_interrupt(vcpu) || external_intr) && | |
10323 | nested_exit_on_intr(vcpu)) { | |
10324 | if (vmx->nested.nested_run_pending) | |
10325 | return -EBUSY; | |
10326 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); | |
705699a1 | 10327 | return 0; |
b6b8a145 JK |
10328 | } |
10329 | ||
705699a1 | 10330 | return vmx_complete_nested_posted_interrupt(vcpu); |
b6b8a145 JK |
10331 | } |
10332 | ||
f4124500 JK |
10333 | static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) |
10334 | { | |
10335 | ktime_t remaining = | |
10336 | hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); | |
10337 | u64 value; | |
10338 | ||
10339 | if (ktime_to_ns(remaining) <= 0) | |
10340 | return 0; | |
10341 | ||
10342 | value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; | |
10343 | do_div(value, 1000000); | |
10344 | return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
10345 | } | |
10346 | ||
4704d0be NHE |
10347 | /* |
10348 | * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits | |
10349 | * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), | |
10350 | * and this function updates it to reflect the changes to the guest state while | |
10351 | * L2 was running (and perhaps made some exits which were handled directly by L0 | |
10352 | * without going back to L1), and to reflect the exit reason. | |
10353 | * Note that we do not have to copy here all VMCS fields, just those that | |
10354 | * could have changed by the L2 guest or the exit - i.e., the guest-state and | |
10355 | * exit-information fields only. Other fields are modified by L1 with VMWRITE, | |
10356 | * which already writes to vmcs12 directly. | |
10357 | */ | |
533558bc JK |
10358 | static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, |
10359 | u32 exit_reason, u32 exit_intr_info, | |
10360 | unsigned long exit_qualification) | |
4704d0be NHE |
10361 | { |
10362 | /* update guest state fields: */ | |
10363 | vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); | |
10364 | vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); | |
10365 | ||
4704d0be NHE |
10366 | vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); |
10367 | vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP); | |
10368 | vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); | |
10369 | ||
10370 | vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); | |
10371 | vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); | |
10372 | vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); | |
10373 | vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); | |
10374 | vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); | |
10375 | vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); | |
10376 | vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); | |
10377 | vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); | |
10378 | vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); | |
10379 | vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); | |
10380 | vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
10381 | vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); | |
10382 | vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); | |
10383 | vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); | |
10384 | vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); | |
10385 | vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); | |
10386 | vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
10387 | vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
10388 | vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); | |
10389 | vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); | |
10390 | vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); | |
10391 | vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); | |
10392 | vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); | |
10393 | vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); | |
10394 | vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); | |
10395 | vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); | |
10396 | vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); | |
10397 | vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); | |
10398 | vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); | |
10399 | vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); | |
10400 | vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); | |
10401 | vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); | |
10402 | vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); | |
10403 | vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); | |
10404 | vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); | |
10405 | vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); | |
10406 | ||
4704d0be NHE |
10407 | vmcs12->guest_interruptibility_info = |
10408 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
10409 | vmcs12->guest_pending_dbg_exceptions = | |
10410 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); | |
3edf1e69 JK |
10411 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
10412 | vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; | |
10413 | else | |
10414 | vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; | |
4704d0be | 10415 | |
f4124500 JK |
10416 | if (nested_cpu_has_preemption_timer(vmcs12)) { |
10417 | if (vmcs12->vm_exit_controls & | |
10418 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER) | |
10419 | vmcs12->vmx_preemption_timer_value = | |
10420 | vmx_get_preemption_timer_value(vcpu); | |
10421 | hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); | |
10422 | } | |
7854cbca | 10423 | |
3633cfc3 NHE |
10424 | /* |
10425 | * In some cases (usually, nested EPT), L2 is allowed to change its | |
10426 | * own CR3 without exiting. If it has changed it, we must keep it. | |
10427 | * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined | |
10428 | * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. | |
10429 | * | |
10430 | * Additionally, restore L2's PDPTR to vmcs12. | |
10431 | */ | |
10432 | if (enable_ept) { | |
f3531054 | 10433 | vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3); |
3633cfc3 NHE |
10434 | vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); |
10435 | vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); | |
10436 | vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); | |
10437 | vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); | |
10438 | } | |
10439 | ||
608406e2 WV |
10440 | if (nested_cpu_has_vid(vmcs12)) |
10441 | vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS); | |
10442 | ||
c18911a2 JK |
10443 | vmcs12->vm_entry_controls = |
10444 | (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | | |
2961e876 | 10445 | (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); |
c18911a2 | 10446 | |
2996fca0 JK |
10447 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) { |
10448 | kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); | |
10449 | vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
10450 | } | |
10451 | ||
4704d0be NHE |
10452 | /* TODO: These cannot have changed unless we have MSR bitmaps and |
10453 | * the relevant bit asks not to trap the change */ | |
b8c07d55 | 10454 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) |
4704d0be | 10455 | vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT); |
10ba54a5 JK |
10456 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) |
10457 | vmcs12->guest_ia32_efer = vcpu->arch.efer; | |
4704d0be NHE |
10458 | vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS); |
10459 | vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP); | |
10460 | vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP); | |
a87036ad | 10461 | if (kvm_mpx_supported()) |
36be0b9d | 10462 | vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); |
81dc01f7 WL |
10463 | if (nested_cpu_has_xsaves(vmcs12)) |
10464 | vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP); | |
4704d0be NHE |
10465 | |
10466 | /* update exit information fields: */ | |
10467 | ||
533558bc JK |
10468 | vmcs12->vm_exit_reason = exit_reason; |
10469 | vmcs12->exit_qualification = exit_qualification; | |
4704d0be | 10470 | |
533558bc | 10471 | vmcs12->vm_exit_intr_info = exit_intr_info; |
c0d1c770 JK |
10472 | if ((vmcs12->vm_exit_intr_info & |
10473 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) == | |
10474 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) | |
10475 | vmcs12->vm_exit_intr_error_code = | |
10476 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
5f3d5799 | 10477 | vmcs12->idt_vectoring_info_field = 0; |
4704d0be NHE |
10478 | vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
10479 | vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
10480 | ||
5f3d5799 JK |
10481 | if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { |
10482 | /* vm_entry_intr_info_field is cleared on exit. Emulate this | |
10483 | * instead of reading the real value. */ | |
4704d0be | 10484 | vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; |
5f3d5799 JK |
10485 | |
10486 | /* | |
10487 | * Transfer the event that L0 or L1 may wanted to inject into | |
10488 | * L2 to IDT_VECTORING_INFO_FIELD. | |
10489 | */ | |
10490 | vmcs12_save_pending_event(vcpu, vmcs12); | |
10491 | } | |
10492 | ||
10493 | /* | |
10494 | * Drop what we picked up for L2 via vmx_complete_interrupts. It is | |
10495 | * preserved above and would only end up incorrectly in L1. | |
10496 | */ | |
10497 | vcpu->arch.nmi_injected = false; | |
10498 | kvm_clear_exception_queue(vcpu); | |
10499 | kvm_clear_interrupt_queue(vcpu); | |
4704d0be NHE |
10500 | } |
10501 | ||
10502 | /* | |
10503 | * A part of what we need to when the nested L2 guest exits and we want to | |
10504 | * run its L1 parent, is to reset L1's guest state to the host state specified | |
10505 | * in vmcs12. | |
10506 | * This function is to be called not only on normal nested exit, but also on | |
10507 | * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry | |
10508 | * Failures During or After Loading Guest State"). | |
10509 | * This function should be called when the active VMCS is L1's (vmcs01). | |
10510 | */ | |
733568f9 JK |
10511 | static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, |
10512 | struct vmcs12 *vmcs12) | |
4704d0be | 10513 | { |
21feb4eb ACL |
10514 | struct kvm_segment seg; |
10515 | ||
4704d0be NHE |
10516 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) |
10517 | vcpu->arch.efer = vmcs12->host_ia32_efer; | |
d1fa0352 | 10518 | else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) |
4704d0be NHE |
10519 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
10520 | else | |
10521 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
10522 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
10523 | ||
10524 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp); | |
10525 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip); | |
1adfa76a | 10526 | vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); |
4704d0be NHE |
10527 | /* |
10528 | * Note that calling vmx_set_cr0 is important, even if cr0 hasn't | |
10529 | * actually changed, because it depends on the current state of | |
10530 | * fpu_active (which may have changed). | |
10531 | * Note that vmx_set_cr0 refers to efer set above. | |
10532 | */ | |
9e3e4dbf | 10533 | vmx_set_cr0(vcpu, vmcs12->host_cr0); |
4704d0be NHE |
10534 | /* |
10535 | * If we did fpu_activate()/fpu_deactivate() during L2's run, we need | |
10536 | * to apply the same changes to L1's vmcs. We just set cr0 correctly, | |
10537 | * but we also need to update cr0_guest_host_mask and exception_bitmap. | |
10538 | */ | |
10539 | update_exception_bitmap(vcpu); | |
10540 | vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0); | |
10541 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
10542 | ||
10543 | /* | |
10544 | * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01 | |
10545 | * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask(); | |
10546 | */ | |
10547 | vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); | |
10548 | kvm_set_cr4(vcpu, vmcs12->host_cr4); | |
10549 | ||
29bf08f1 | 10550 | nested_ept_uninit_mmu_context(vcpu); |
155a97a3 | 10551 | |
4704d0be NHE |
10552 | kvm_set_cr3(vcpu, vmcs12->host_cr3); |
10553 | kvm_mmu_reset_context(vcpu); | |
10554 | ||
feaf0c7d GN |
10555 | if (!enable_ept) |
10556 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
10557 | ||
4704d0be NHE |
10558 | if (enable_vpid) { |
10559 | /* | |
10560 | * Trivially support vpid by letting L2s share their parent | |
10561 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
10562 | * each L2 its own vpid and exposing the vpid feature to L1. | |
10563 | */ | |
10564 | vmx_flush_tlb(vcpu); | |
10565 | } | |
10566 | ||
10567 | ||
10568 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); | |
10569 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); | |
10570 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); | |
10571 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); | |
10572 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); | |
4704d0be | 10573 | |
36be0b9d PB |
10574 | /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ |
10575 | if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) | |
10576 | vmcs_write64(GUEST_BNDCFGS, 0); | |
10577 | ||
44811c02 | 10578 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { |
4704d0be | 10579 | vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); |
44811c02 JK |
10580 | vcpu->arch.pat = vmcs12->host_ia32_pat; |
10581 | } | |
4704d0be NHE |
10582 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
10583 | vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, | |
10584 | vmcs12->host_ia32_perf_global_ctrl); | |
503cd0c5 | 10585 | |
21feb4eb ACL |
10586 | /* Set L1 segment info according to Intel SDM |
10587 | 27.5.2 Loading Host Segment and Descriptor-Table Registers */ | |
10588 | seg = (struct kvm_segment) { | |
10589 | .base = 0, | |
10590 | .limit = 0xFFFFFFFF, | |
10591 | .selector = vmcs12->host_cs_selector, | |
10592 | .type = 11, | |
10593 | .present = 1, | |
10594 | .s = 1, | |
10595 | .g = 1 | |
10596 | }; | |
10597 | if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) | |
10598 | seg.l = 1; | |
10599 | else | |
10600 | seg.db = 1; | |
10601 | vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); | |
10602 | seg = (struct kvm_segment) { | |
10603 | .base = 0, | |
10604 | .limit = 0xFFFFFFFF, | |
10605 | .type = 3, | |
10606 | .present = 1, | |
10607 | .s = 1, | |
10608 | .db = 1, | |
10609 | .g = 1 | |
10610 | }; | |
10611 | seg.selector = vmcs12->host_ds_selector; | |
10612 | vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); | |
10613 | seg.selector = vmcs12->host_es_selector; | |
10614 | vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); | |
10615 | seg.selector = vmcs12->host_ss_selector; | |
10616 | vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); | |
10617 | seg.selector = vmcs12->host_fs_selector; | |
10618 | seg.base = vmcs12->host_fs_base; | |
10619 | vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); | |
10620 | seg.selector = vmcs12->host_gs_selector; | |
10621 | seg.base = vmcs12->host_gs_base; | |
10622 | vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); | |
10623 | seg = (struct kvm_segment) { | |
205befd9 | 10624 | .base = vmcs12->host_tr_base, |
21feb4eb ACL |
10625 | .limit = 0x67, |
10626 | .selector = vmcs12->host_tr_selector, | |
10627 | .type = 11, | |
10628 | .present = 1 | |
10629 | }; | |
10630 | vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); | |
10631 | ||
503cd0c5 JK |
10632 | kvm_set_dr(vcpu, 7, 0x400); |
10633 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
ff651cb6 | 10634 | |
3af18d9c WV |
10635 | if (cpu_has_vmx_msr_bitmap()) |
10636 | vmx_set_msr_bitmap(vcpu); | |
10637 | ||
ff651cb6 WV |
10638 | if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr, |
10639 | vmcs12->vm_exit_msr_load_count)) | |
10640 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); | |
4704d0be NHE |
10641 | } |
10642 | ||
10643 | /* | |
10644 | * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 | |
10645 | * and modify vmcs12 to make it see what it would expect to see there if | |
10646 | * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) | |
10647 | */ | |
533558bc JK |
10648 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
10649 | u32 exit_intr_info, | |
10650 | unsigned long exit_qualification) | |
4704d0be NHE |
10651 | { |
10652 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4704d0be NHE |
10653 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
10654 | ||
5f3d5799 JK |
10655 | /* trying to cancel vmlaunch/vmresume is a bug */ |
10656 | WARN_ON_ONCE(vmx->nested.nested_run_pending); | |
10657 | ||
4704d0be | 10658 | leave_guest_mode(vcpu); |
533558bc JK |
10659 | prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info, |
10660 | exit_qualification); | |
4704d0be | 10661 | |
ff651cb6 WV |
10662 | if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr, |
10663 | vmcs12->vm_exit_msr_store_count)) | |
10664 | nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL); | |
10665 | ||
f3380ca5 WL |
10666 | vmx_load_vmcs01(vcpu); |
10667 | ||
77b0f5d6 BD |
10668 | if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) |
10669 | && nested_exit_intr_ack_set(vcpu)) { | |
10670 | int irq = kvm_cpu_get_interrupt(vcpu); | |
10671 | WARN_ON(irq < 0); | |
10672 | vmcs12->vm_exit_intr_info = irq | | |
10673 | INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; | |
10674 | } | |
10675 | ||
542060ea JK |
10676 | trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, |
10677 | vmcs12->exit_qualification, | |
10678 | vmcs12->idt_vectoring_info_field, | |
10679 | vmcs12->vm_exit_intr_info, | |
10680 | vmcs12->vm_exit_intr_error_code, | |
10681 | KVM_ISA_VMX); | |
4704d0be | 10682 | |
2961e876 GN |
10683 | vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS)); |
10684 | vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS)); | |
36c3cc42 JK |
10685 | vmx_segment_cache_clear(vmx); |
10686 | ||
4704d0be NHE |
10687 | /* if no vmcs02 cache requested, remove the one we used */ |
10688 | if (VMCS02_POOL_SIZE == 0) | |
10689 | nested_free_vmcs02(vmx, vmx->nested.current_vmptr); | |
10690 | ||
10691 | load_vmcs12_host_state(vcpu, vmcs12); | |
10692 | ||
27fc51b2 | 10693 | /* Update TSC_OFFSET if TSC was changed while L2 ran */ |
4704d0be NHE |
10694 | vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset); |
10695 | ||
10696 | /* This is needed for same reason as it was needed in prepare_vmcs02 */ | |
10697 | vmx->host_rsp = 0; | |
10698 | ||
10699 | /* Unpin physical memory we referred to in vmcs02 */ | |
10700 | if (vmx->nested.apic_access_page) { | |
10701 | nested_release_page(vmx->nested.apic_access_page); | |
48d89b92 | 10702 | vmx->nested.apic_access_page = NULL; |
4704d0be | 10703 | } |
a7c0b07d WL |
10704 | if (vmx->nested.virtual_apic_page) { |
10705 | nested_release_page(vmx->nested.virtual_apic_page); | |
48d89b92 | 10706 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 10707 | } |
705699a1 WV |
10708 | if (vmx->nested.pi_desc_page) { |
10709 | kunmap(vmx->nested.pi_desc_page); | |
10710 | nested_release_page(vmx->nested.pi_desc_page); | |
10711 | vmx->nested.pi_desc_page = NULL; | |
10712 | vmx->nested.pi_desc = NULL; | |
10713 | } | |
4704d0be | 10714 | |
38b99173 TC |
10715 | /* |
10716 | * We are now running in L2, mmu_notifier will force to reload the | |
10717 | * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1. | |
10718 | */ | |
10719 | kvm_vcpu_reload_apic_access_page(vcpu); | |
10720 | ||
4704d0be NHE |
10721 | /* |
10722 | * Exiting from L2 to L1, we're now back to L1 which thinks it just | |
10723 | * finished a VMLAUNCH or VMRESUME instruction, so we need to set the | |
10724 | * success or failure flag accordingly. | |
10725 | */ | |
10726 | if (unlikely(vmx->fail)) { | |
10727 | vmx->fail = 0; | |
10728 | nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
10729 | } else | |
10730 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
10731 | if (enable_shadow_vmcs) |
10732 | vmx->nested.sync_shadow_vmcs = true; | |
b6b8a145 JK |
10733 | |
10734 | /* in case we halted in L2 */ | |
10735 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4704d0be NHE |
10736 | } |
10737 | ||
42124925 JK |
10738 | /* |
10739 | * Forcibly leave nested mode in order to be able to reset the VCPU later on. | |
10740 | */ | |
10741 | static void vmx_leave_nested(struct kvm_vcpu *vcpu) | |
10742 | { | |
10743 | if (is_guest_mode(vcpu)) | |
533558bc | 10744 | nested_vmx_vmexit(vcpu, -1, 0, 0); |
42124925 JK |
10745 | free_nested(to_vmx(vcpu)); |
10746 | } | |
10747 | ||
7c177938 NHE |
10748 | /* |
10749 | * L1's failure to enter L2 is a subset of a normal exit, as explained in | |
10750 | * 23.7 "VM-entry failures during or after loading guest state" (this also | |
10751 | * lists the acceptable exit-reason and exit-qualification parameters). | |
10752 | * It should only be called before L2 actually succeeded to run, and when | |
10753 | * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss). | |
10754 | */ | |
10755 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, | |
10756 | struct vmcs12 *vmcs12, | |
10757 | u32 reason, unsigned long qualification) | |
10758 | { | |
10759 | load_vmcs12_host_state(vcpu, vmcs12); | |
10760 | vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY; | |
10761 | vmcs12->exit_qualification = qualification; | |
10762 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
10763 | if (enable_shadow_vmcs) |
10764 | to_vmx(vcpu)->nested.sync_shadow_vmcs = true; | |
7c177938 NHE |
10765 | } |
10766 | ||
8a76d7f2 JR |
10767 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
10768 | struct x86_instruction_info *info, | |
10769 | enum x86_intercept_stage stage) | |
10770 | { | |
10771 | return X86EMUL_CONTINUE; | |
10772 | } | |
10773 | ||
64672c95 YJ |
10774 | #ifdef CONFIG_X86_64 |
10775 | /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ | |
10776 | static inline int u64_shl_div_u64(u64 a, unsigned int shift, | |
10777 | u64 divisor, u64 *result) | |
10778 | { | |
10779 | u64 low = a << shift, high = a >> (64 - shift); | |
10780 | ||
10781 | /* To avoid the overflow on divq */ | |
10782 | if (high >= divisor) | |
10783 | return 1; | |
10784 | ||
10785 | /* Low hold the result, high hold rem which is discarded */ | |
10786 | asm("divq %2\n\t" : "=a" (low), "=d" (high) : | |
10787 | "rm" (divisor), "0" (low), "1" (high)); | |
10788 | *result = low; | |
10789 | ||
10790 | return 0; | |
10791 | } | |
10792 | ||
10793 | static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc) | |
10794 | { | |
10795 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10796 | u64 tscl = rdtsc(), delta_tsc; | |
10797 | ||
10798 | delta_tsc = guest_deadline_tsc - kvm_read_l1_tsc(vcpu, tscl); | |
10799 | ||
10800 | /* Convert to host delta tsc if tsc scaling is enabled */ | |
10801 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && | |
10802 | u64_shl_div_u64(delta_tsc, | |
10803 | kvm_tsc_scaling_ratio_frac_bits, | |
10804 | vcpu->arch.tsc_scaling_ratio, | |
10805 | &delta_tsc)) | |
10806 | return -ERANGE; | |
10807 | ||
10808 | /* | |
10809 | * If the delta tsc can't fit in the 32 bit after the multi shift, | |
10810 | * we can't use the preemption timer. | |
10811 | * It's possible that it fits on later vmentries, but checking | |
10812 | * on every vmentry is costly so we just use an hrtimer. | |
10813 | */ | |
10814 | if (delta_tsc >> (cpu_preemption_timer_multi + 32)) | |
10815 | return -ERANGE; | |
10816 | ||
10817 | vmx->hv_deadline_tsc = tscl + delta_tsc; | |
10818 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
10819 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
10820 | return 0; | |
10821 | } | |
10822 | ||
10823 | static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) | |
10824 | { | |
10825 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10826 | vmx->hv_deadline_tsc = -1; | |
10827 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
10828 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
10829 | } | |
10830 | #endif | |
10831 | ||
48d89b92 | 10832 | static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) |
ae97a3b8 | 10833 | { |
b4a2d31d RK |
10834 | if (ple_gap) |
10835 | shrink_ple_window(vcpu); | |
ae97a3b8 RK |
10836 | } |
10837 | ||
843e4330 KH |
10838 | static void vmx_slot_enable_log_dirty(struct kvm *kvm, |
10839 | struct kvm_memory_slot *slot) | |
10840 | { | |
10841 | kvm_mmu_slot_leaf_clear_dirty(kvm, slot); | |
10842 | kvm_mmu_slot_largepage_remove_write_access(kvm, slot); | |
10843 | } | |
10844 | ||
10845 | static void vmx_slot_disable_log_dirty(struct kvm *kvm, | |
10846 | struct kvm_memory_slot *slot) | |
10847 | { | |
10848 | kvm_mmu_slot_set_dirty(kvm, slot); | |
10849 | } | |
10850 | ||
10851 | static void vmx_flush_log_dirty(struct kvm *kvm) | |
10852 | { | |
10853 | kvm_flush_pml_buffers(kvm); | |
10854 | } | |
10855 | ||
10856 | static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, | |
10857 | struct kvm_memory_slot *memslot, | |
10858 | gfn_t offset, unsigned long mask) | |
10859 | { | |
10860 | kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); | |
10861 | } | |
10862 | ||
bf9f6ac8 FW |
10863 | /* |
10864 | * This routine does the following things for vCPU which is going | |
10865 | * to be blocked if VT-d PI is enabled. | |
10866 | * - Store the vCPU to the wakeup list, so when interrupts happen | |
10867 | * we can find the right vCPU to wake up. | |
10868 | * - Change the Posted-interrupt descriptor as below: | |
10869 | * 'NDST' <-- vcpu->pre_pcpu | |
10870 | * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR | |
10871 | * - If 'ON' is set during this process, which means at least one | |
10872 | * interrupt is posted for this vCPU, we cannot block it, in | |
10873 | * this case, return 1, otherwise, return 0. | |
10874 | * | |
10875 | */ | |
bc22512b | 10876 | static int pi_pre_block(struct kvm_vcpu *vcpu) |
bf9f6ac8 FW |
10877 | { |
10878 | unsigned long flags; | |
10879 | unsigned int dest; | |
10880 | struct pi_desc old, new; | |
10881 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
10882 | ||
10883 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
10884 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
10885 | return 0; | |
10886 | ||
10887 | vcpu->pre_pcpu = vcpu->cpu; | |
10888 | spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock, | |
10889 | vcpu->pre_pcpu), flags); | |
10890 | list_add_tail(&vcpu->blocked_vcpu_list, | |
10891 | &per_cpu(blocked_vcpu_on_cpu, | |
10892 | vcpu->pre_pcpu)); | |
10893 | spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock, | |
10894 | vcpu->pre_pcpu), flags); | |
10895 | ||
10896 | do { | |
10897 | old.control = new.control = pi_desc->control; | |
10898 | ||
10899 | /* | |
10900 | * We should not block the vCPU if | |
10901 | * an interrupt is posted for it. | |
10902 | */ | |
10903 | if (pi_test_on(pi_desc) == 1) { | |
10904 | spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock, | |
10905 | vcpu->pre_pcpu), flags); | |
10906 | list_del(&vcpu->blocked_vcpu_list); | |
10907 | spin_unlock_irqrestore( | |
10908 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
10909 | vcpu->pre_pcpu), flags); | |
10910 | vcpu->pre_pcpu = -1; | |
10911 | ||
10912 | return 1; | |
10913 | } | |
10914 | ||
10915 | WARN((pi_desc->sn == 1), | |
10916 | "Warning: SN field of posted-interrupts " | |
10917 | "is set before blocking\n"); | |
10918 | ||
10919 | /* | |
10920 | * Since vCPU can be preempted during this process, | |
10921 | * vcpu->cpu could be different with pre_pcpu, we | |
10922 | * need to set pre_pcpu as the destination of wakeup | |
10923 | * notification event, then we can find the right vCPU | |
10924 | * to wakeup in wakeup handler if interrupts happen | |
10925 | * when the vCPU is in blocked state. | |
10926 | */ | |
10927 | dest = cpu_physical_id(vcpu->pre_pcpu); | |
10928 | ||
10929 | if (x2apic_enabled()) | |
10930 | new.ndst = dest; | |
10931 | else | |
10932 | new.ndst = (dest << 8) & 0xFF00; | |
10933 | ||
10934 | /* set 'NV' to 'wakeup vector' */ | |
10935 | new.nv = POSTED_INTR_WAKEUP_VECTOR; | |
10936 | } while (cmpxchg(&pi_desc->control, old.control, | |
10937 | new.control) != old.control); | |
10938 | ||
10939 | return 0; | |
10940 | } | |
10941 | ||
bc22512b YJ |
10942 | static int vmx_pre_block(struct kvm_vcpu *vcpu) |
10943 | { | |
10944 | if (pi_pre_block(vcpu)) | |
10945 | return 1; | |
10946 | ||
64672c95 YJ |
10947 | if (kvm_lapic_hv_timer_in_use(vcpu)) |
10948 | kvm_lapic_switch_to_sw_timer(vcpu); | |
10949 | ||
bc22512b YJ |
10950 | return 0; |
10951 | } | |
10952 | ||
10953 | static void pi_post_block(struct kvm_vcpu *vcpu) | |
bf9f6ac8 FW |
10954 | { |
10955 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
10956 | struct pi_desc old, new; | |
10957 | unsigned int dest; | |
10958 | unsigned long flags; | |
10959 | ||
10960 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
10961 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
10962 | return; | |
10963 | ||
10964 | do { | |
10965 | old.control = new.control = pi_desc->control; | |
10966 | ||
10967 | dest = cpu_physical_id(vcpu->cpu); | |
10968 | ||
10969 | if (x2apic_enabled()) | |
10970 | new.ndst = dest; | |
10971 | else | |
10972 | new.ndst = (dest << 8) & 0xFF00; | |
10973 | ||
10974 | /* Allow posting non-urgent interrupts */ | |
10975 | new.sn = 0; | |
10976 | ||
10977 | /* set 'NV' to 'notification vector' */ | |
10978 | new.nv = POSTED_INTR_VECTOR; | |
10979 | } while (cmpxchg(&pi_desc->control, old.control, | |
10980 | new.control) != old.control); | |
10981 | ||
10982 | if(vcpu->pre_pcpu != -1) { | |
10983 | spin_lock_irqsave( | |
10984 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
10985 | vcpu->pre_pcpu), flags); | |
10986 | list_del(&vcpu->blocked_vcpu_list); | |
10987 | spin_unlock_irqrestore( | |
10988 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
10989 | vcpu->pre_pcpu), flags); | |
10990 | vcpu->pre_pcpu = -1; | |
10991 | } | |
10992 | } | |
10993 | ||
bc22512b YJ |
10994 | static void vmx_post_block(struct kvm_vcpu *vcpu) |
10995 | { | |
64672c95 YJ |
10996 | if (kvm_x86_ops->set_hv_timer) |
10997 | kvm_lapic_switch_to_hv_timer(vcpu); | |
10998 | ||
bc22512b YJ |
10999 | pi_post_block(vcpu); |
11000 | } | |
11001 | ||
efc64404 FW |
11002 | /* |
11003 | * vmx_update_pi_irte - set IRTE for Posted-Interrupts | |
11004 | * | |
11005 | * @kvm: kvm | |
11006 | * @host_irq: host irq of the interrupt | |
11007 | * @guest_irq: gsi of the interrupt | |
11008 | * @set: set or unset PI | |
11009 | * returns 0 on success, < 0 on failure | |
11010 | */ | |
11011 | static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
11012 | uint32_t guest_irq, bool set) | |
11013 | { | |
11014 | struct kvm_kernel_irq_routing_entry *e; | |
11015 | struct kvm_irq_routing_table *irq_rt; | |
11016 | struct kvm_lapic_irq irq; | |
11017 | struct kvm_vcpu *vcpu; | |
11018 | struct vcpu_data vcpu_info; | |
11019 | int idx, ret = -EINVAL; | |
11020 | ||
11021 | if (!kvm_arch_has_assigned_device(kvm) || | |
11022 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
11023 | return 0; | |
11024 | ||
11025 | idx = srcu_read_lock(&kvm->irq_srcu); | |
11026 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
11027 | BUG_ON(guest_irq >= irq_rt->nr_rt_entries); | |
11028 | ||
11029 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
11030 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
11031 | continue; | |
11032 | /* | |
11033 | * VT-d PI cannot support posting multicast/broadcast | |
11034 | * interrupts to a vCPU, we still use interrupt remapping | |
11035 | * for these kind of interrupts. | |
11036 | * | |
11037 | * For lowest-priority interrupts, we only support | |
11038 | * those with single CPU as the destination, e.g. user | |
11039 | * configures the interrupts via /proc/irq or uses | |
11040 | * irqbalance to make the interrupts single-CPU. | |
11041 | * | |
11042 | * We will support full lowest-priority interrupt later. | |
11043 | */ | |
11044 | ||
11045 | kvm_set_msi_irq(e, &irq); | |
23a1c257 FW |
11046 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { |
11047 | /* | |
11048 | * Make sure the IRTE is in remapped mode if | |
11049 | * we don't handle it in posted mode. | |
11050 | */ | |
11051 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
11052 | if (ret < 0) { | |
11053 | printk(KERN_INFO | |
11054 | "failed to back to remapped mode, irq: %u\n", | |
11055 | host_irq); | |
11056 | goto out; | |
11057 | } | |
11058 | ||
efc64404 | 11059 | continue; |
23a1c257 | 11060 | } |
efc64404 FW |
11061 | |
11062 | vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); | |
11063 | vcpu_info.vector = irq.vector; | |
11064 | ||
b6ce9780 | 11065 | trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi, |
efc64404 FW |
11066 | vcpu_info.vector, vcpu_info.pi_desc_addr, set); |
11067 | ||
11068 | if (set) | |
11069 | ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); | |
11070 | else { | |
11071 | /* suppress notification event before unposting */ | |
11072 | pi_set_sn(vcpu_to_pi_desc(vcpu)); | |
11073 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
11074 | pi_clear_sn(vcpu_to_pi_desc(vcpu)); | |
11075 | } | |
11076 | ||
11077 | if (ret < 0) { | |
11078 | printk(KERN_INFO "%s: failed to update PI IRTE\n", | |
11079 | __func__); | |
11080 | goto out; | |
11081 | } | |
11082 | } | |
11083 | ||
11084 | ret = 0; | |
11085 | out: | |
11086 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
11087 | return ret; | |
11088 | } | |
11089 | ||
cbdd1bea | 11090 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
11091 | .cpu_has_kvm_support = cpu_has_kvm_support, |
11092 | .disabled_by_bios = vmx_disabled_by_bios, | |
11093 | .hardware_setup = hardware_setup, | |
11094 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 11095 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
11096 | .hardware_enable = hardware_enable, |
11097 | .hardware_disable = hardware_disable, | |
04547156 | 11098 | .cpu_has_accelerated_tpr = report_flexpriority, |
6d396b55 | 11099 | .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase, |
6aa8b732 AK |
11100 | |
11101 | .vcpu_create = vmx_create_vcpu, | |
11102 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 11103 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 11104 | |
04d2cc77 | 11105 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
11106 | .vcpu_load = vmx_vcpu_load, |
11107 | .vcpu_put = vmx_vcpu_put, | |
11108 | ||
a96036b8 | 11109 | .update_bp_intercept = update_exception_bitmap, |
6aa8b732 AK |
11110 | .get_msr = vmx_get_msr, |
11111 | .set_msr = vmx_set_msr, | |
11112 | .get_segment_base = vmx_get_segment_base, | |
11113 | .get_segment = vmx_get_segment, | |
11114 | .set_segment = vmx_set_segment, | |
2e4d2653 | 11115 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 11116 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 11117 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 11118 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 11119 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 11120 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
11121 | .set_cr3 = vmx_set_cr3, |
11122 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 11123 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
11124 | .get_idt = vmx_get_idt, |
11125 | .set_idt = vmx_set_idt, | |
11126 | .get_gdt = vmx_get_gdt, | |
11127 | .set_gdt = vmx_set_gdt, | |
73aaf249 JK |
11128 | .get_dr6 = vmx_get_dr6, |
11129 | .set_dr6 = vmx_set_dr6, | |
020df079 | 11130 | .set_dr7 = vmx_set_dr7, |
81908bf4 | 11131 | .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, |
5fdbf976 | 11132 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
11133 | .get_rflags = vmx_get_rflags, |
11134 | .set_rflags = vmx_set_rflags, | |
be94f6b7 HH |
11135 | |
11136 | .get_pkru = vmx_get_pkru, | |
11137 | ||
0fdd74f7 | 11138 | .fpu_activate = vmx_fpu_activate, |
02daab21 | 11139 | .fpu_deactivate = vmx_fpu_deactivate, |
6aa8b732 AK |
11140 | |
11141 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 11142 | |
6aa8b732 | 11143 | .run = vmx_vcpu_run, |
6062d012 | 11144 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 11145 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
11146 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
11147 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 11148 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 11149 | .set_irq = vmx_inject_irq, |
95ba8273 | 11150 | .set_nmi = vmx_inject_nmi, |
298101da | 11151 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 11152 | .cancel_injection = vmx_cancel_injection, |
78646121 | 11153 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 11154 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
11155 | .get_nmi_mask = vmx_get_nmi_mask, |
11156 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
11157 | .enable_nmi_window = enable_nmi_window, |
11158 | .enable_irq_window = enable_irq_window, | |
11159 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 11160 | .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode, |
38b99173 | 11161 | .set_apic_access_page_addr = vmx_set_apic_access_page_addr, |
d62caabb AS |
11162 | .get_enable_apicv = vmx_get_enable_apicv, |
11163 | .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, | |
c7c9c56c YZ |
11164 | .load_eoi_exitmap = vmx_load_eoi_exitmap, |
11165 | .hwapic_irr_update = vmx_hwapic_irr_update, | |
11166 | .hwapic_isr_update = vmx_hwapic_isr_update, | |
a20ed54d YZ |
11167 | .sync_pir_to_irr = vmx_sync_pir_to_irr, |
11168 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, | |
95ba8273 | 11169 | |
cbc94022 | 11170 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 11171 | .get_tdp_level = get_ept_level, |
4b12f0de | 11172 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 11173 | |
586f9607 | 11174 | .get_exit_info = vmx_get_exit_info, |
586f9607 | 11175 | |
17cc3935 | 11176 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
11177 | |
11178 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
11179 | |
11180 | .rdtscp_supported = vmx_rdtscp_supported, | |
ad756a16 | 11181 | .invpcid_supported = vmx_invpcid_supported, |
d4330ef2 JR |
11182 | |
11183 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
11184 | |
11185 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a | 11186 | |
ba904635 | 11187 | .read_tsc_offset = vmx_read_tsc_offset, |
99e3e30a | 11188 | .write_tsc_offset = vmx_write_tsc_offset, |
58ea6767 | 11189 | .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest, |
d5c1785d | 11190 | .read_l1_tsc = vmx_read_l1_tsc, |
1c97f0a0 JR |
11191 | |
11192 | .set_tdp_cr3 = vmx_set_cr3, | |
8a76d7f2 JR |
11193 | |
11194 | .check_intercept = vmx_check_intercept, | |
a547c6db | 11195 | .handle_external_intr = vmx_handle_external_intr, |
da8999d3 | 11196 | .mpx_supported = vmx_mpx_supported, |
55412b2e | 11197 | .xsaves_supported = vmx_xsaves_supported, |
b6b8a145 JK |
11198 | |
11199 | .check_nested_events = vmx_check_nested_events, | |
ae97a3b8 RK |
11200 | |
11201 | .sched_in = vmx_sched_in, | |
843e4330 KH |
11202 | |
11203 | .slot_enable_log_dirty = vmx_slot_enable_log_dirty, | |
11204 | .slot_disable_log_dirty = vmx_slot_disable_log_dirty, | |
11205 | .flush_log_dirty = vmx_flush_log_dirty, | |
11206 | .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, | |
25462f7f | 11207 | |
bf9f6ac8 FW |
11208 | .pre_block = vmx_pre_block, |
11209 | .post_block = vmx_post_block, | |
11210 | ||
25462f7f | 11211 | .pmu_ops = &intel_pmu_ops, |
efc64404 FW |
11212 | |
11213 | .update_pi_irte = vmx_update_pi_irte, | |
64672c95 YJ |
11214 | |
11215 | #ifdef CONFIG_X86_64 | |
11216 | .set_hv_timer = vmx_set_hv_timer, | |
11217 | .cancel_hv_timer = vmx_cancel_hv_timer, | |
11218 | #endif | |
6aa8b732 AK |
11219 | }; |
11220 | ||
11221 | static int __init vmx_init(void) | |
11222 | { | |
34a1cd60 TC |
11223 | int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
11224 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
fdef3ad1 | 11225 | if (r) |
34a1cd60 | 11226 | return r; |
25c5f225 | 11227 | |
2965faa5 | 11228 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
11229 | rcu_assign_pointer(crash_vmclear_loaded_vmcss, |
11230 | crash_vmclear_local_loaded_vmcss); | |
11231 | #endif | |
11232 | ||
fdef3ad1 | 11233 | return 0; |
6aa8b732 AK |
11234 | } |
11235 | ||
11236 | static void __exit vmx_exit(void) | |
11237 | { | |
2965faa5 | 11238 | #ifdef CONFIG_KEXEC_CORE |
3b63a43f | 11239 | RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); |
8f536b76 ZY |
11240 | synchronize_rcu(); |
11241 | #endif | |
11242 | ||
cb498ea2 | 11243 | kvm_exit(); |
6aa8b732 AK |
11244 | } |
11245 | ||
11246 | module_init(vmx_init) | |
11247 | module_exit(vmx_exit) |