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pc: Leave max apic_id_limit only in legacy cpu hotplug code
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
b834b508 38#if defined(CONFIG_KVM)
ef8621b1 39#include <linux/kvm_para.h>
b834b508 40#endif
65dee380 41
9c17d615 42#include "sysemu/sysemu.h"
53a89e26 43#include "hw/qdev-properties.h"
5232d00a 44#include "hw/i386/topology.h"
bdeec802 45#ifndef CONFIG_USER_ONLY
2001d0cd 46#include "exec/address-spaces.h"
741da0d3 47#include "hw/hw.h"
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
14c985cf 60#define CPUID_2_L3_16MB_16WAY_64B 0x4d
5e891bf8
EH		 61
62
63/* CPUID Leaf 4 constants: */
64
65/* EAX: */
66#define CPUID_4_TYPE_DCACHE 1
67#define CPUID_4_TYPE_ICACHE 2
68#define CPUID_4_TYPE_UNIFIED 3
69
70#define CPUID_4_LEVEL(l) ((l) << 5)
71
72#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73#define CPUID_4_FULLY_ASSOC (1 << 9)
74
75/* EDX: */
76#define CPUID_4_NO_INVD_SHARING (1 << 0)
77#define CPUID_4_INCLUSIVE (1 << 1)
78#define CPUID_4_COMPLEX_IDX (1 << 2)
79
80#define ASSOC_FULL 0xFF
81
82/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
84 a == 2 ? 0x2 : \
85 a == 4 ? 0x4 : \
86 a == 8 ? 0x6 : \
87 a == 16 ? 0x8 : \
88 a == 32 ? 0xA : \
89 a == 48 ? 0xB : \
90 a == 64 ? 0xC : \
91 a == 96 ? 0xD : \
92 a == 128 ? 0xE : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
95
96
97/* Definitions of the hardcoded cache entries we expose: */
98
99/* L1 data cache: */
100#define L1D_LINE_SIZE 64
101#define L1D_ASSOCIATIVITY 8
102#define L1D_SETS 64
103#define L1D_PARTITIONS 1
104/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107#define L1D_LINES_PER_TAG 1
108#define L1D_SIZE_KB_AMD 64
109#define L1D_ASSOCIATIVITY_AMD 2
110
111/* L1 instruction cache: */
112#define L1I_LINE_SIZE 64
113#define L1I_ASSOCIATIVITY 8
114#define L1I_SETS 64
115#define L1I_PARTITIONS 1
116/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119#define L1I_LINES_PER_TAG 1
120#define L1I_SIZE_KB_AMD 64
121#define L1I_ASSOCIATIVITY_AMD 2
122
123/* Level 2 unified cache: */
124#define L2_LINE_SIZE 64
125#define L2_ASSOCIATIVITY 16
126#define L2_SETS 4096
127#define L2_PARTITIONS 1
128/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132#define L2_LINES_PER_TAG 1
133#define L2_SIZE_KB_AMD 512
134
14c985cf 135/* Level 3 unified cache: */
5e891bf8
EH		 136#define L3_SIZE_KB 0 /* disabled */
137#define L3_ASSOCIATIVITY 0 /* disabled */
138#define L3_LINES_PER_TAG 0 /* disabled */
139#define L3_LINE_SIZE 0 /* disabled */
14c985cf
LM		 140#define L3_N_LINE_SIZE 64
141#define L3_N_ASSOCIATIVITY 16
142#define L3_N_SETS 16384
143#define L3_N_PARTITIONS 1
144#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
145#define L3_N_LINES_PER_TAG 1
146#define L3_N_SIZE_KB_AMD 16384
5e891bf8
EH		 147
148/* TLB definitions: */
149
150#define L1_DTLB_2M_ASSOC 1
151#define L1_DTLB_2M_ENTRIES 255
152#define L1_DTLB_4K_ASSOC 1
153#define L1_DTLB_4K_ENTRIES 255
154
155#define L1_ITLB_2M_ASSOC 1
156#define L1_ITLB_2M_ENTRIES 255
157#define L1_ITLB_4K_ASSOC 1
158#define L1_ITLB_4K_ENTRIES 255
159
160#define L2_DTLB_2M_ASSOC 0 /* disabled */
161#define L2_DTLB_2M_ENTRIES 0 /* disabled */
162#define L2_DTLB_4K_ASSOC 4
163#define L2_DTLB_4K_ENTRIES 512
164
165#define L2_ITLB_2M_ASSOC 0 /* disabled */
166#define L2_ITLB_2M_ENTRIES 0 /* disabled */
167#define L2_ITLB_4K_ASSOC 4
168#define L2_ITLB_4K_ENTRIES 512
169
170
171
99b88a17
IM		 172static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
173 uint32_t vendor2, uint32_t vendor3)
174{
175 int i;
176 for (i = 0; i < 4; i++) {
177 dst[i] = vendor1 >> (8 * i);
178 dst[i + 4] = vendor2 >> (8 * i);
179 dst[i + 8] = vendor3 >> (8 * i);
180 }
181 dst[CPUID_VENDOR_SZ] = '\0';
182}
183
621626ce
EH		 184#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
185#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
186 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
187#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
188 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
189 CPUID_PSE36 | CPUID_FXSR)
190#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
191#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
192 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
193 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
194 CPUID_PAE | CPUID_SEP | CPUID_APIC)
195
196#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
197 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
198 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
199 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 200 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 201 /* partly implemented:
202 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
203 /* missing:
204 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
205#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
206 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
207 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 208 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 209 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
210 /* missing:
211 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
212 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
213 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 214 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
215 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 216
217#ifdef TARGET_X86_64
218#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
219#else
220#define TCG_EXT2_X86_64_FEATURES 0
221#endif
222
223#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
224 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
225 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
226 TCG_EXT2_X86_64_FEATURES)
227#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
228 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
229#define TCG_EXT4_FEATURES 0
230#define TCG_SVM_FEATURES 0
231#define TCG_KVM_FEATURES 0
232#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 233 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
234 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 235 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
236 CPUID_7_0_EBX_ERMS)
621626ce 237 /* missing:
07929f2a 238 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 239 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 240 CPUID_7_0_EBX_RDSEED */
0f70ed47 241#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
303752a9 242#define TCG_APM_FEATURES 0
28b8e4d0 243#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 244#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
245 /* missing:
246 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 247
5ef57876 248typedef struct FeatureWordInfo {
2d5312da
EH		 249 /* feature flags names are taken from "Intel Processor Identification and
250 * the CPUID Instruction" and AMD's "CPUID Specification".
251 * In cases of disagreement between feature naming conventions,
252 * aliases may be added.
253 */
254 const char *feat_names[32];
04d104b6
EH		 255 uint32_t cpuid_eax; /* Input EAX for CPUID */
256 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
257 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
258 int cpuid_reg; /* output register (R_* constant) */
37ce3522 259 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 260 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 261 uint32_t migratable_flags; /* Feature flags known to be migratable */
5ef57876
EH		 262} FeatureWordInfo;
263
264static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 265 [FEAT_1_EDX] = {
2d5312da
EH		 266 .feat_names = {
267 "fpu", "vme", "de", "pse",
268 "tsc", "msr", "pae", "mce",
269 "cx8", "apic", NULL, "sep",
270 "mtrr", "pge", "mca", "cmov",
271 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
272 NULL, "ds" /* Intel dts */, "acpi", "mmx",
273 "fxsr", "sse", "sse2", "ss",
274 "ht" /* Intel htt */, "tm", "ia64", "pbe",
275 },
bffd67b0 276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 277 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 278 },
279 [FEAT_1_ECX] = {
2d5312da 280 .feat_names = {
16d2fcaa 281 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 282 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 283 "tm2", "ssse3", "cid", NULL,
284 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 285 NULL, "pcid", "dca", "sse4.1",
286 "sse4.2", "x2apic", "movbe", "popcnt",
2d5312da
EH		 287 "tsc-deadline", "aes", "xsave", "osxsave",
288 "avx", "f16c", "rdrand", "hypervisor",
289 },
bffd67b0 290 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 291 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 292 },
2d5312da
EH		 293 /* Feature names that are already defined on feature_name[] but
294 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
295 * names on feat_names below. They are copied automatically
296 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
297 */
bffd67b0 298 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 299 .feat_names = {
300 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
301 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
302 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
303 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
304 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 305 "nx", NULL, "mmxext", NULL /* mmx */,
306 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
307 NULL, "lm", "3dnowext", "3dnow",
2d5312da 308 },
bffd67b0 309 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 310 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 311 },
312 [FEAT_8000_0001_ECX] = {
2d5312da 313 .feat_names = {
fc7dfd20 314 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 315 "cr8legacy", "abm", "sse4a", "misalignsse",
316 "3dnowprefetch", "osvw", "ibs", "xop",
317 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 318 "fma4", "tce", NULL, "nodeid-msr",
319 NULL, "tbm", "topoext", "perfctr-core",
320 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 321 NULL, NULL, NULL, NULL,
322 },
bffd67b0 323 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 324 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 325 },
89e49c8b 326 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 327 .feat_names = {
328 NULL, NULL, "xstore", "xstore-en",
329 NULL, NULL, "xcrypt", "xcrypt-en",
330 "ace2", "ace2-en", "phe", "phe-en",
331 "pmm", "pmm-en", NULL, NULL,
332 NULL, NULL, NULL, NULL,
333 NULL, NULL, NULL, NULL,
334 NULL, NULL, NULL, NULL,
335 NULL, NULL, NULL, NULL,
336 },
89e49c8b 337 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 338 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 339 },
bffd67b0 340 [FEAT_KVM] = {
2d5312da 341 .feat_names = {
fc7dfd20
EH		 342 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
343 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
2d5312da
EH		 344 NULL, NULL, NULL, NULL,
345 NULL, NULL, NULL, NULL,
346 NULL, NULL, NULL, NULL,
347 NULL, NULL, NULL, NULL,
348 "kvmclock-stable-bit", NULL, NULL, NULL,
349 NULL, NULL, NULL, NULL,
350 },
bffd67b0 351 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 352 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 353 },
c35bd19a 354 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 355 .feat_names = {
356 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
357 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
358 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
359 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
360 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
361 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
362 NULL, NULL, NULL, NULL,
363 NULL, NULL, NULL, NULL,
364 NULL, NULL, NULL, NULL,
365 NULL, NULL, NULL, NULL,
366 NULL, NULL, NULL, NULL,
367 },
c35bd19a
EY		 368 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
369 },
370 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 371 .feat_names = {
372 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
373 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
374 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
375 NULL /* hv_create_port */, NULL /* hv_connect_port */,
376 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
377 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
378 NULL, NULL,
379 NULL, NULL, NULL, NULL,
380 NULL, NULL, NULL, NULL,
381 NULL, NULL, NULL, NULL,
382 NULL, NULL, NULL, NULL,
383 },
c35bd19a
EY		 384 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
385 },
386 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 387 .feat_names = {
388 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
389 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
390 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
391 NULL, NULL,
392 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
393 NULL, NULL, NULL, NULL,
394 NULL, NULL, NULL, NULL,
395 NULL, NULL, NULL, NULL,
396 NULL, NULL, NULL, NULL,
397 NULL, NULL, NULL, NULL,
398 },
c35bd19a
EY		 399 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
400 },
bffd67b0 401 [FEAT_SVM] = {
2d5312da 402 .feat_names = {
fc7dfd20
EH		 403 "npt", "lbrv", "svm-lock", "nrip-save",
404 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
405 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 406 "pfthreshold", NULL, NULL, NULL,
407 NULL, NULL, NULL, NULL,
408 NULL, NULL, NULL, NULL,
409 NULL, NULL, NULL, NULL,
410 NULL, NULL, NULL, NULL,
411 },
bffd67b0 412 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 413 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 414 },
415 [FEAT_7_0_EBX] = {
2d5312da 416 .feat_names = {
fc7dfd20 417 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 418 "hle", "avx2", NULL, "smep",
419 "bmi2", "erms", "invpcid", "rtm",
420 NULL, NULL, "mpx", NULL,
421 "avx512f", "avx512dq", "rdseed", "adx",
422 "smap", "avx512ifma", "pcommit", "clflushopt",
423 "clwb", NULL, "avx512pf", "avx512er",
424 "avx512cd", NULL, "avx512bw", "avx512vl",
425 },
04d104b6
EH		 426 .cpuid_eax = 7,
427 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
428 .cpuid_reg = R_EBX,
37ce3522 429 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 430 },
f74eefe0 431 [FEAT_7_0_ECX] = {
2d5312da
EH		 432 .feat_names = {
433 NULL, "avx512vbmi", "umip", "pku",
434 "ospke", NULL, NULL, NULL,
435 NULL, NULL, NULL, NULL,
436 NULL, NULL, NULL, NULL,
437 NULL, NULL, NULL, NULL,
438 NULL, NULL, "rdpid", NULL,
439 NULL, NULL, NULL, NULL,
440 NULL, NULL, NULL, NULL,
441 },
f74eefe0
HH		 442 .cpuid_eax = 7,
443 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
444 .cpuid_reg = R_ECX,
445 .tcg_features = TCG_7_0_ECX_FEATURES,
446 },
303752a9 447 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 448 .feat_names = {
449 NULL, NULL, NULL, NULL,
450 NULL, NULL, NULL, NULL,
451 "invtsc", NULL, NULL, NULL,
452 NULL, NULL, NULL, NULL,
453 NULL, NULL, NULL, NULL,
454 NULL, NULL, NULL, NULL,
455 NULL, NULL, NULL, NULL,
456 NULL, NULL, NULL, NULL,
457 },
303752a9
MT		 458 .cpuid_eax = 0x80000007,
459 .cpuid_reg = R_EDX,
460 .tcg_features = TCG_APM_FEATURES,
461 .unmigratable_flags = CPUID_APM_INVTSC,
462 },
0bb0b2d2 463 [FEAT_XSAVE] = {
2d5312da
EH		 464 .feat_names = {
465 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
466 NULL, NULL, NULL, NULL,
467 NULL, NULL, NULL, NULL,
468 NULL, NULL, NULL, NULL,
469 NULL, NULL, NULL, NULL,
470 NULL, NULL, NULL, NULL,
471 NULL, NULL, NULL, NULL,
472 NULL, NULL, NULL, NULL,
473 },
0bb0b2d2
PB		 474 .cpuid_eax = 0xd,
475 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
476 .cpuid_reg = R_EAX,
c9cfe8f9 477 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 478 },
28b8e4d0 479 [FEAT_6_EAX] = {
2d5312da
EH		 480 .feat_names = {
481 NULL, NULL, "arat", NULL,
482 NULL, NULL, NULL, NULL,
483 NULL, NULL, NULL, NULL,
484 NULL, NULL, NULL, NULL,
485 NULL, NULL, NULL, NULL,
486 NULL, NULL, NULL, NULL,
487 NULL, NULL, NULL, NULL,
488 NULL, NULL, NULL, NULL,
489 },
28b8e4d0
JK		 490 .cpuid_eax = 6, .cpuid_reg = R_EAX,
491 .tcg_features = TCG_6_EAX_FEATURES,
492 },
96193c22
EH		 493 [FEAT_XSAVE_COMP_LO] = {
494 .cpuid_eax = 0xD,
495 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
496 .cpuid_reg = R_EAX,
497 .tcg_features = ~0U,
6fb2fff7
EH		 498 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
499 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
500 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
501 XSTATE_PKRU_MASK,
96193c22
EH		 502 },
503 [FEAT_XSAVE_COMP_HI] = {
504 .cpuid_eax = 0xD,
505 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
506 .cpuid_reg = R_EDX,
507 .tcg_features = ~0U,
508 },
5ef57876
EH		 509};
510
8e8aba50
EH		 511typedef struct X86RegisterInfo32 {
512 /* Name of register */
513 const char *name;
514 /* QAPI enum value register */
515 X86CPURegister32 qapi_enum;
516} X86RegisterInfo32;
517
518#define REGISTER(reg) \
5d371f41 519 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 520static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 521 REGISTER(EAX),
522 REGISTER(ECX),
523 REGISTER(EDX),
524 REGISTER(EBX),
525 REGISTER(ESP),
526 REGISTER(EBP),
527 REGISTER(ESI),
528 REGISTER(EDI),
529};
530#undef REGISTER
531
3f32bd21
RH		 532typedef struct ExtSaveArea {
533 uint32_t feature, bits;
534 uint32_t offset, size;
535} ExtSaveArea;
536
537static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 538 [XSTATE_FP_BIT] = {
539 /* x87 FP state component is always enabled if XSAVE is supported */
540 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
541 /* x87 state is in the legacy region of the XSAVE area */
542 .offset = 0,
543 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
544 },
545 [XSTATE_SSE_BIT] = {
546 /* SSE state component is always enabled if XSAVE is supported */
547 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
548 /* SSE state is in the legacy region of the XSAVE area */
549 .offset = 0,
550 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
551 },
cfc3b074
PB		 552 [XSTATE_YMM_BIT] =
553 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 554 .offset = offsetof(X86XSaveArea, avx_state),
555 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 556 [XSTATE_BNDREGS_BIT] =
557 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 558 .offset = offsetof(X86XSaveArea, bndreg_state),
559 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 560 [XSTATE_BNDCSR_BIT] =
561 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 562 .offset = offsetof(X86XSaveArea, bndcsr_state),
563 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 564 [XSTATE_OPMASK_BIT] =
565 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 566 .offset = offsetof(X86XSaveArea, opmask_state),
567 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 568 [XSTATE_ZMM_Hi256_BIT] =
569 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 570 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
571 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 572 [XSTATE_Hi16_ZMM_BIT] =
573 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 574 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
575 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 576 [XSTATE_PKRU_BIT] =
577 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 578 .offset = offsetof(X86XSaveArea, pkru_state),
579 .size = sizeof(XSavePKRU) },
2560f19f 580};
8e8aba50 581
1fda6198
EH		 582static uint32_t xsave_area_size(uint64_t mask)
583{
584 int i;
e3c9022b 585 uint64_t ret = 0;
1fda6198 586
e3c9022b 587 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 588 const ExtSaveArea *esa = &x86_ext_save_areas[i];
589 if ((mask >> i) & 1) {
590 ret = MAX(ret, esa->offset + esa->size);
591 }
592 }
593 return ret;
594}
595
96193c22
EH		 596static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
597{
598 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
599 cpu->env.features[FEAT_XSAVE_COMP_LO];
600}
601
8b4beddc
EH		 602const char *get_register_name_32(unsigned int reg)
603{
31ccdde2 604 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 605 return NULL;
606 }
8e8aba50 607 return x86_reg_info_32[reg].name;
8b4beddc
EH		 608}
609
84f1b92f
EH		 610/*
611 * Returns the set of feature flags that are supported and migratable by
612 * QEMU, for a given FeatureWord.
613 */
614static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
615{
616 FeatureWordInfo *wi = &feature_word_info[w];
617 uint32_t r = 0;
618 int i;
619
620 for (i = 0; i < 32; i++) {
621 uint32_t f = 1U << i;
6fb2fff7
EH		 622
623 /* If the feature name is known, it is implicitly considered migratable,
624 * unless it is explicitly set in unmigratable_flags */
625 if ((wi->migratable_flags & f) ||
626 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
627 r |= f;
84f1b92f 628 }
84f1b92f
EH		 629 }
630 return r;
631}
632
bb44e0d1
JK		 633void host_cpuid(uint32_t function, uint32_t count,
634 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 635{
a1fd24af
AL		 636 uint32_t vec[4];
637
638#ifdef __x86_64__
639 asm volatile("cpuid"
640 : "=a"(vec[0]), "=b"(vec[1]),
641 "=c"(vec[2]), "=d"(vec[3])
642 : "0"(function), "c"(count) : "cc");
c1f41226 643#elif defined(__i386__)
a1fd24af
AL		 644 asm volatile("pusha \n\t"
645 "cpuid \n\t"
646 "mov %%eax, 0(%2) \n\t"
647 "mov %%ebx, 4(%2) \n\t"
648 "mov %%ecx, 8(%2) \n\t"
649 "mov %%edx, 12(%2) \n\t"
650 "popa"
651 : : "a"(function), "c"(count), "S"(vec)
652 : "memory", "cc");
c1f41226
EH		 653#else
654 abort();
a1fd24af
AL		 655#endif
656
bdde476a 657 if (eax)
a1fd24af 658 *eax = vec[0];
bdde476a 659 if (ebx)
a1fd24af 660 *ebx = vec[1];
bdde476a 661 if (ecx)
a1fd24af 662 *ecx = vec[2];
bdde476a 663 if (edx)
a1fd24af 664 *edx = vec[3];
bdde476a 665}
c6dc6f63 666
d940ee9b
EH		 667/* CPU class name definitions: */
668
669#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
670#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
671
672/* Return type name for a given CPU model name
673 * Caller is responsible for freeing the returned string.
674 */
675static char *x86_cpu_type_name(const char *model_name)
676{
677 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
678}
679
500050d1
AF		 680static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
681{
d940ee9b
EH		 682 ObjectClass *oc;
683 char *typename;
684
500050d1
AF		 685 if (cpu_model == NULL) {
686 return NULL;
687 }
688
d940ee9b
EH		 689 typename = x86_cpu_type_name(cpu_model);
690 oc = object_class_by_name(typename);
691 g_free(typename);
692 return oc;
500050d1
AF		 693}
694
104494ea
IM		 695static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
696{
697 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
698 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
699 return g_strndup(class_name,
700 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
701}
702
d940ee9b 703struct X86CPUDefinition {
c6dc6f63
AP		 704 const char *name;
705 uint32_t level;
90e4b0c3 706 uint32_t xlevel;
99b88a17
IM		 707 /* vendor is zero-terminated, 12 character ASCII string */
708 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 709 int family;
710 int model;
711 int stepping;
0514ef2f 712 FeatureWordArray features;
c6dc6f63 713 char model_id[48];
d940ee9b 714};
c6dc6f63 715
9576de75 716static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 717 {
718 .name = "qemu64",
3046bb5d 719 .level = 0xd,
99b88a17 720 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 721 .family = 6,
f8e6a11a 722 .model = 6,
c6dc6f63 723 .stepping = 3,
0514ef2f 724 .features[FEAT_1_EDX] =
27861ecc 725 PPRO_FEATURES |
c6dc6f63 726 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 727 CPUID_PSE36,
0514ef2f 728 .features[FEAT_1_ECX] =
6aa91e4a 729 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 730 .features[FEAT_8000_0001_EDX] =
c6dc6f63 731 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 732 .features[FEAT_8000_0001_ECX] =
71195672 733 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 734 .xlevel = 0x8000000A,
9cf2cc3d 735 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 736 },
737 {
738 .name = "phenom",
739 .level = 5,
99b88a17 740 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 741 .family = 16,
742 .model = 2,
743 .stepping = 3,
b9fc20bc 744 /* Missing: CPUID_HT */
0514ef2f 745 .features[FEAT_1_EDX] =
27861ecc 746 PPRO_FEATURES |
c6dc6f63 747 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 748 CPUID_PSE36 | CPUID_VME,
0514ef2f 749 .features[FEAT_1_ECX] =
27861ecc 750 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 751 CPUID_EXT_POPCNT,
0514ef2f 752 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 753 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
754 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 755 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 756 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
757 CPUID_EXT3_CR8LEG,
758 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
759 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 760 .features[FEAT_8000_0001_ECX] =
27861ecc 761 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 762 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 763 /* Missing: CPUID_SVM_LBRV */
0514ef2f 764 .features[FEAT_SVM] =
b9fc20bc 765 CPUID_SVM_NPT,
c6dc6f63
AP		 766 .xlevel = 0x8000001A,
767 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
768 },
769 {
770 .name = "core2duo",
771 .level = 10,
99b88a17 772 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 773 .family = 6,
774 .model = 15,
775 .stepping = 11,
b9fc20bc 776 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 777 .features[FEAT_1_EDX] =
27861ecc 778 PPRO_FEATURES |
c6dc6f63 779 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 780 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
781 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 782 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 783 .features[FEAT_1_ECX] =
27861ecc 784 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 785 CPUID_EXT_CX16,
0514ef2f 786 .features[FEAT_8000_0001_EDX] =
27861ecc 787 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 788 .features[FEAT_8000_0001_ECX] =
27861ecc 789 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 790 .xlevel = 0x80000008,
791 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
792 },
793 {
794 .name = "kvm64",
3046bb5d 795 .level = 0xd,
99b88a17 796 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 797 .family = 15,
798 .model = 6,
799 .stepping = 1,
b3a4f0b1 800 /* Missing: CPUID_HT */
0514ef2f 801 .features[FEAT_1_EDX] =
b3a4f0b1 802 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 803 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
804 CPUID_PSE36,
805 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 806 .features[FEAT_1_ECX] =
27861ecc 807 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 808 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 809 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 810 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
811 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
812 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
813 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
814 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 815 .features[FEAT_8000_0001_ECX] =
27861ecc 816 0,
c6dc6f63
AP		 817 .xlevel = 0x80000008,
818 .model_id = "Common KVM processor"
819 },
c6dc6f63
AP		 820 {
821 .name = "qemu32",
822 .level = 4,
99b88a17 823 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 824 .family = 6,
f8e6a11a 825 .model = 6,
c6dc6f63 826 .stepping = 3,
0514ef2f 827 .features[FEAT_1_EDX] =
27861ecc 828 PPRO_FEATURES,
0514ef2f 829 .features[FEAT_1_ECX] =
6aa91e4a 830 CPUID_EXT_SSE3,
58012d66 831 .xlevel = 0x80000004,
9cf2cc3d 832 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 833 },
eafaf1e5
AP		 834 {
835 .name = "kvm32",
836 .level = 5,
99b88a17 837 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 838 .family = 15,
839 .model = 6,
840 .stepping = 1,
0514ef2f 841 .features[FEAT_1_EDX] =
b3a4f0b1 842 PPRO_FEATURES | CPUID_VME |
eafaf1e5 843 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 844 .features[FEAT_1_ECX] =
27861ecc 845 CPUID_EXT_SSE3,
0514ef2f 846 .features[FEAT_8000_0001_ECX] =
27861ecc 847 0,
eafaf1e5
AP		 848 .xlevel = 0x80000008,
849 .model_id = "Common 32-bit KVM processor"
850 },
c6dc6f63
AP		 851 {
852 .name = "coreduo",
853 .level = 10,
99b88a17 854 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 855 .family = 6,
856 .model = 14,
857 .stepping = 8,
b9fc20bc 858 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 859 .features[FEAT_1_EDX] =
27861ecc 860 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 861 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
862 CPUID_SS,
863 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 864 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 865 .features[FEAT_1_ECX] =
e93abc14 866 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 867 .features[FEAT_8000_0001_EDX] =
27861ecc 868 CPUID_EXT2_NX,
c6dc6f63
AP		 869 .xlevel = 0x80000008,
870 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
871 },
872 {
873 .name = "486",
58012d66 874 .level = 1,
99b88a17 875 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 876 .family = 4,
b2a856d9 877 .model = 8,
c6dc6f63 878 .stepping = 0,
0514ef2f 879 .features[FEAT_1_EDX] =
27861ecc 880 I486_FEATURES,
c6dc6f63
AP		 881 .xlevel = 0,
882 },
883 {
884 .name = "pentium",
885 .level = 1,
99b88a17 886 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 887 .family = 5,
888 .model = 4,
889 .stepping = 3,
0514ef2f 890 .features[FEAT_1_EDX] =
27861ecc 891 PENTIUM_FEATURES,
c6dc6f63
AP		 892 .xlevel = 0,
893 },
894 {
895 .name = "pentium2",
896 .level = 2,
99b88a17 897 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 898 .family = 6,
899 .model = 5,
900 .stepping = 2,
0514ef2f 901 .features[FEAT_1_EDX] =
27861ecc 902 PENTIUM2_FEATURES,
c6dc6f63
AP		 903 .xlevel = 0,
904 },
905 {
906 .name = "pentium3",
3046bb5d 907 .level = 3,
99b88a17 908 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 909 .family = 6,
910 .model = 7,
911 .stepping = 3,
0514ef2f 912 .features[FEAT_1_EDX] =
27861ecc 913 PENTIUM3_FEATURES,
c6dc6f63
AP		 914 .xlevel = 0,
915 },
916 {
917 .name = "athlon",
918 .level = 2,
99b88a17 919 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 920 .family = 6,
921 .model = 2,
922 .stepping = 3,
0514ef2f 923 .features[FEAT_1_EDX] =
27861ecc 924 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 925 CPUID_MCA,
0514ef2f 926 .features[FEAT_8000_0001_EDX] =
60032ac0 927 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 928 .xlevel = 0x80000008,
9cf2cc3d 929 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 930 },
931 {
932 .name = "n270",
3046bb5d 933 .level = 10,
99b88a17 934 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 935 .family = 6,
936 .model = 28,
937 .stepping = 2,
b9fc20bc 938 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 939 .features[FEAT_1_EDX] =
27861ecc 940 PPRO_FEATURES |
b9fc20bc
EH		 941 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
942 CPUID_ACPI | CPUID_SS,
c6dc6f63 943 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 944 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
945 * CPUID_EXT_XTPR */
0514ef2f 946 .features[FEAT_1_ECX] =
27861ecc 947 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 948 CPUID_EXT_MOVBE,
0514ef2f 949 .features[FEAT_8000_0001_EDX] =
60032ac0 950 CPUID_EXT2_NX,
0514ef2f 951 .features[FEAT_8000_0001_ECX] =
27861ecc 952 CPUID_EXT3_LAHF_LM,
3046bb5d 953 .xlevel = 0x80000008,
c6dc6f63
AP		 954 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
955 },
3eca4642
EH		 956 {
957 .name = "Conroe",
3046bb5d 958 .level = 10,
99b88a17 959 .vendor = CPUID_VENDOR_INTEL,
3eca4642 960 .family = 6,
ffce9ebb 961 .model = 15,
3eca4642 962 .stepping = 3,
0514ef2f 963 .features[FEAT_1_EDX] =
b3a4f0b1 964 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 965 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
966 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
967 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
968 CPUID_DE | CPUID_FP87,
0514ef2f 969 .features[FEAT_1_ECX] =
27861ecc 970 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 971 .features[FEAT_8000_0001_EDX] =
27861ecc 972 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 973 .features[FEAT_8000_0001_ECX] =
27861ecc 974 CPUID_EXT3_LAHF_LM,
3046bb5d 975 .xlevel = 0x80000008,
3eca4642
EH		 976 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
977 },
978 {
979 .name = "Penryn",
3046bb5d 980 .level = 10,
99b88a17 981 .vendor = CPUID_VENDOR_INTEL,
3eca4642 982 .family = 6,
ffce9ebb 983 .model = 23,
3eca4642 984 .stepping = 3,
0514ef2f 985 .features[FEAT_1_EDX] =
b3a4f0b1 986 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 987 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
988 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
989 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
990 CPUID_DE | CPUID_FP87,
0514ef2f 991 .features[FEAT_1_ECX] =
27861ecc 992 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 993 CPUID_EXT_SSE3,
0514ef2f 994 .features[FEAT_8000_0001_EDX] =
27861ecc 995 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 996 .features[FEAT_8000_0001_ECX] =
27861ecc 997 CPUID_EXT3_LAHF_LM,
3046bb5d 998 .xlevel = 0x80000008,
3eca4642
EH		 999 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1000 },
1001 {
1002 .name = "Nehalem",
3046bb5d 1003 .level = 11,
99b88a17 1004 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1005 .family = 6,
ffce9ebb 1006 .model = 26,
3eca4642 1007 .stepping = 3,
0514ef2f 1008 .features[FEAT_1_EDX] =
b3a4f0b1 1009 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1010 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1011 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1012 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1013 CPUID_DE | CPUID_FP87,
0514ef2f 1014 .features[FEAT_1_ECX] =
27861ecc 1015 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1016 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1017 .features[FEAT_8000_0001_EDX] =
27861ecc 1018 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1019 .features[FEAT_8000_0001_ECX] =
27861ecc 1020 CPUID_EXT3_LAHF_LM,
3046bb5d 1021 .xlevel = 0x80000008,
3eca4642
EH		 1022 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1023 },
1024 {
1025 .name = "Westmere",
1026 .level = 11,
99b88a17 1027 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1028 .family = 6,
1029 .model = 44,
1030 .stepping = 1,
0514ef2f 1031 .features[FEAT_1_EDX] =
b3a4f0b1 1032 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1033 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1034 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1035 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1036 CPUID_DE | CPUID_FP87,
0514ef2f 1037 .features[FEAT_1_ECX] =
27861ecc 1038 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1039 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1040 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1041 .features[FEAT_8000_0001_EDX] =
27861ecc 1042 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1043 .features[FEAT_8000_0001_ECX] =
27861ecc 1044 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1045 .features[FEAT_6_EAX] =
1046 CPUID_6_EAX_ARAT,
3046bb5d 1047 .xlevel = 0x80000008,
3eca4642
EH		 1048 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1049 },
1050 {
1051 .name = "SandyBridge",
1052 .level = 0xd,
99b88a17 1053 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1054 .family = 6,
1055 .model = 42,
1056 .stepping = 1,
0514ef2f 1057 .features[FEAT_1_EDX] =
b3a4f0b1 1058 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1059 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1060 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1061 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1062 CPUID_DE | CPUID_FP87,
0514ef2f 1063 .features[FEAT_1_ECX] =
27861ecc 1064 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1065 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1066 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1067 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1068 CPUID_EXT_SSE3,
0514ef2f 1069 .features[FEAT_8000_0001_EDX] =
27861ecc 1070 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1071 CPUID_EXT2_SYSCALL,
0514ef2f 1072 .features[FEAT_8000_0001_ECX] =
27861ecc 1073 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1074 .features[FEAT_XSAVE] =
1075 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1076 .features[FEAT_6_EAX] =
1077 CPUID_6_EAX_ARAT,
3046bb5d 1078 .xlevel = 0x80000008,
3eca4642
EH		 1079 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1080 },
2f9ac42a
PB		 1081 {
1082 .name = "IvyBridge",
1083 .level = 0xd,
1084 .vendor = CPUID_VENDOR_INTEL,
1085 .family = 6,
1086 .model = 58,
1087 .stepping = 9,
1088 .features[FEAT_1_EDX] =
1089 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1090 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1091 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1092 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1093 CPUID_DE | CPUID_FP87,
1094 .features[FEAT_1_ECX] =
1095 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1096 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1097 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1098 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1099 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1100 .features[FEAT_7_0_EBX] =
1101 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1102 CPUID_7_0_EBX_ERMS,
1103 .features[FEAT_8000_0001_EDX] =
1104 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1105 CPUID_EXT2_SYSCALL,
1106 .features[FEAT_8000_0001_ECX] =
1107 CPUID_EXT3_LAHF_LM,
1108 .features[FEAT_XSAVE] =
1109 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1110 .features[FEAT_6_EAX] =
1111 CPUID_6_EAX_ARAT,
3046bb5d 1112 .xlevel = 0x80000008,
2f9ac42a
PB		 1113 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1114 },
37507094 1115 {
a356850b
EH		 1116 .name = "Haswell-noTSX",
1117 .level = 0xd,
1118 .vendor = CPUID_VENDOR_INTEL,
1119 .family = 6,
1120 .model = 60,
1121 .stepping = 1,
1122 .features[FEAT_1_EDX] =
1123 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1124 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1125 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1126 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1127 CPUID_DE | CPUID_FP87,
1128 .features[FEAT_1_ECX] =
1129 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1130 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1131 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1132 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1133 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1134 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1135 .features[FEAT_8000_0001_EDX] =
1136 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1137 CPUID_EXT2_SYSCALL,
1138 .features[FEAT_8000_0001_ECX] =
becb6667 1139 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1140 .features[FEAT_7_0_EBX] =
1141 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1142 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1143 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1144 .features[FEAT_XSAVE] =
1145 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1146 .features[FEAT_6_EAX] =
1147 CPUID_6_EAX_ARAT,
3046bb5d 1148 .xlevel = 0x80000008,
a356850b
EH		 1149 .model_id = "Intel Core Processor (Haswell, no TSX)",
1150 }, {
37507094
EH		 1151 .name = "Haswell",
1152 .level = 0xd,
99b88a17 1153 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1154 .family = 6,
1155 .model = 60,
1156 .stepping = 1,
0514ef2f 1157 .features[FEAT_1_EDX] =
b3a4f0b1 1158 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1159 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1160 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1161 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1162 CPUID_DE | CPUID_FP87,
0514ef2f 1163 .features[FEAT_1_ECX] =
27861ecc 1164 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1165 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1166 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1167 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1168 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1169 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1170 .features[FEAT_8000_0001_EDX] =
27861ecc 1171 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1172 CPUID_EXT2_SYSCALL,
0514ef2f 1173 .features[FEAT_8000_0001_ECX] =
becb6667 1174 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1175 .features[FEAT_7_0_EBX] =
27861ecc 1176 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1177 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1178 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1179 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1180 .features[FEAT_XSAVE] =
1181 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1182 .features[FEAT_6_EAX] =
1183 CPUID_6_EAX_ARAT,
3046bb5d 1184 .xlevel = 0x80000008,
37507094
EH		 1185 .model_id = "Intel Core Processor (Haswell)",
1186 },
a356850b
EH		 1187 {
1188 .name = "Broadwell-noTSX",
1189 .level = 0xd,
1190 .vendor = CPUID_VENDOR_INTEL,
1191 .family = 6,
1192 .model = 61,
1193 .stepping = 2,
1194 .features[FEAT_1_EDX] =
1195 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1196 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1197 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1198 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1199 CPUID_DE | CPUID_FP87,
1200 .features[FEAT_1_ECX] =
1201 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1202 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1203 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1204 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1205 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1206 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1207 .features[FEAT_8000_0001_EDX] =
1208 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1209 CPUID_EXT2_SYSCALL,
1210 .features[FEAT_8000_0001_ECX] =
becb6667 1211 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1212 .features[FEAT_7_0_EBX] =
1213 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1214 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1215 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1216 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1217 CPUID_7_0_EBX_SMAP,
1218 .features[FEAT_XSAVE] =
1219 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1220 .features[FEAT_6_EAX] =
1221 CPUID_6_EAX_ARAT,
3046bb5d 1222 .xlevel = 0x80000008,
a356850b
EH		 1223 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1224 },
ece01354
EH		 1225 {
1226 .name = "Broadwell",
1227 .level = 0xd,
1228 .vendor = CPUID_VENDOR_INTEL,
1229 .family = 6,
1230 .model = 61,
1231 .stepping = 2,
1232 .features[FEAT_1_EDX] =
b3a4f0b1 1233 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1234 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1235 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1236 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1237 CPUID_DE | CPUID_FP87,
1238 .features[FEAT_1_ECX] =
1239 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1240 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1241 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1242 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1243 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1244 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1245 .features[FEAT_8000_0001_EDX] =
1246 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1247 CPUID_EXT2_SYSCALL,
1248 .features[FEAT_8000_0001_ECX] =
becb6667 1249 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1250 .features[FEAT_7_0_EBX] =
1251 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1252 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1253 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1254 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1255 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1256 .features[FEAT_XSAVE] =
1257 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1258 .features[FEAT_6_EAX] =
1259 CPUID_6_EAX_ARAT,
3046bb5d 1260 .xlevel = 0x80000008,
ece01354
EH		 1261 .model_id = "Intel Core Processor (Broadwell)",
1262 },
f6f949e9
EH		 1263 {
1264 .name = "Skylake-Client",
1265 .level = 0xd,
1266 .vendor = CPUID_VENDOR_INTEL,
1267 .family = 6,
1268 .model = 94,
1269 .stepping = 3,
1270 .features[FEAT_1_EDX] =
1271 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1272 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1273 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1274 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1275 CPUID_DE | CPUID_FP87,
1276 .features[FEAT_1_ECX] =
1277 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1278 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1279 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1280 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1281 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1282 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1283 .features[FEAT_8000_0001_EDX] =
1284 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1285 CPUID_EXT2_SYSCALL,
1286 .features[FEAT_8000_0001_ECX] =
1287 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1288 .features[FEAT_7_0_EBX] =
1289 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1290 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1291 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1292 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1293 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1294 /* Missing: XSAVES (not supported by some Linux versions,
1295 * including v4.1 to v4.6).
1296 * KVM doesn't yet expose any XSAVES state save component,
1297 * and the only one defined in Skylake (processor tracing)
1298 * probably will block migration anyway.
1299 */
1300 .features[FEAT_XSAVE] =
1301 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1302 CPUID_XSAVE_XGETBV1,
1303 .features[FEAT_6_EAX] =
1304 CPUID_6_EAX_ARAT,
1305 .xlevel = 0x80000008,
1306 .model_id = "Intel Core Processor (Skylake)",
1307 },
3eca4642
EH		 1308 {
1309 .name = "Opteron_G1",
1310 .level = 5,
99b88a17 1311 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1312 .family = 15,
1313 .model = 6,
1314 .stepping = 1,
0514ef2f 1315 .features[FEAT_1_EDX] =
b3a4f0b1 1316 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1317 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1318 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1319 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1320 CPUID_DE | CPUID_FP87,
0514ef2f 1321 .features[FEAT_1_ECX] =
27861ecc 1322 CPUID_EXT_SSE3,
0514ef2f 1323 .features[FEAT_8000_0001_EDX] =
27861ecc 1324 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1325 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1326 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1327 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1328 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1329 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1330 .xlevel = 0x80000008,
1331 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1332 },
1333 {
1334 .name = "Opteron_G2",
1335 .level = 5,
99b88a17 1336 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1337 .family = 15,
1338 .model = 6,
1339 .stepping = 1,
0514ef2f 1340 .features[FEAT_1_EDX] =
b3a4f0b1 1341 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1342 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1343 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1344 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1345 CPUID_DE | CPUID_FP87,
0514ef2f 1346 .features[FEAT_1_ECX] =
27861ecc 1347 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1348 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1349 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1350 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1351 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1352 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1353 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1354 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1355 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1356 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1357 .features[FEAT_8000_0001_ECX] =
27861ecc 1358 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1359 .xlevel = 0x80000008,
1360 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1361 },
1362 {
1363 .name = "Opteron_G3",
1364 .level = 5,
99b88a17 1365 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 1366 .family = 16,
1367 .model = 2,
1368 .stepping = 3,
0514ef2f 1369 .features[FEAT_1_EDX] =
b3a4f0b1 1370 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1371 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1372 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1373 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1374 CPUID_DE | CPUID_FP87,
0514ef2f 1375 .features[FEAT_1_ECX] =
27861ecc 1376 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1377 CPUID_EXT_SSE3,
33b5e8c0 1378 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1379 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1380 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1381 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1382 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1383 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1384 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1385 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1386 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1387 .features[FEAT_8000_0001_ECX] =
27861ecc 1388 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1389 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1390 .xlevel = 0x80000008,
1391 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1392 },
1393 {
1394 .name = "Opteron_G4",
1395 .level = 0xd,
99b88a17 1396 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1397 .family = 21,
1398 .model = 1,
1399 .stepping = 2,
0514ef2f 1400 .features[FEAT_1_EDX] =
b3a4f0b1 1401 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1402 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1403 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1404 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1405 CPUID_DE | CPUID_FP87,
0514ef2f 1406 .features[FEAT_1_ECX] =
27861ecc 1407 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1408 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1409 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1410 CPUID_EXT_SSE3,
33b5e8c0 1411 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1412 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1413 CPUID_EXT2_LM |
b3fb3a20
EH		 1414 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1415 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1416 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1417 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1418 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1419 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1420 .features[FEAT_8000_0001_ECX] =
27861ecc 1421 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1422 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1423 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1424 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1425 /* no xsaveopt! */
3eca4642
EH		 1426 .xlevel = 0x8000001A,
1427 .model_id = "AMD Opteron 62xx class CPU",
1428 },
021941b9
AP		 1429 {
1430 .name = "Opteron_G5",
1431 .level = 0xd,
99b88a17 1432 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1433 .family = 21,
1434 .model = 2,
1435 .stepping = 0,
0514ef2f 1436 .features[FEAT_1_EDX] =
b3a4f0b1 1437 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1438 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1439 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1440 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1441 CPUID_DE | CPUID_FP87,
0514ef2f 1442 .features[FEAT_1_ECX] =
27861ecc 1443 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1444 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1445 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1446 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1447 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1448 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1449 CPUID_EXT2_LM |
b3fb3a20
EH		 1450 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1451 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1452 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1453 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1454 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1455 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1456 .features[FEAT_8000_0001_ECX] =
27861ecc 1457 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1458 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1459 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1460 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1461 /* no xsaveopt! */
021941b9
AP		 1462 .xlevel = 0x8000001A,
1463 .model_id = "AMD Opteron 63xx class CPU",
1464 },
c6dc6f63
AP		 1465};
1466
5114e842
EH		 1467typedef struct PropValue {
1468 const char *prop, *value;
1469} PropValue;
1470
1471/* KVM-specific features that are automatically added/removed
1472 * from all CPU models when KVM is enabled.
1473 */
1474static PropValue kvm_default_props[] = {
1475 { "kvmclock", "on" },
1476 { "kvm-nopiodelay", "on" },
1477 { "kvm-asyncpf", "on" },
1478 { "kvm-steal-time", "on" },
1479 { "kvm-pv-eoi", "on" },
1480 { "kvmclock-stable-bit", "on" },
1481 { "x2apic", "on" },
1482 { "acpi", "off" },
1483 { "monitor", "off" },
1484 { "svm", "off" },
1485 { NULL, NULL },
1486};
1487
04d99c3c
EH		 1488/* TCG-specific defaults that override all CPU models when using TCG
1489 */
1490static PropValue tcg_default_props[] = {
1491 { "vme", "off" },
1492 { NULL, NULL },
1493};
1494
1495
5114e842
EH		 1496void x86_cpu_change_kvm_default(const char *prop, const char *value)
1497{
1498 PropValue *pv;
1499 for (pv = kvm_default_props; pv->prop; pv++) {
1500 if (!strcmp(pv->prop, prop)) {
1501 pv->value = value;
1502 break;
1503 }
1504 }
1505
1506 /* It is valid to call this function only for properties that
1507 * are already present in the kvm_default_props table.
1508 */
1509 assert(pv->prop);
1510}
1511
4d1b279b
EH		 1512static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1513 bool migratable_only);
1514
d940ee9b
EH		 1515#ifdef CONFIG_KVM
1516
40bfe48f
HZ		 1517static bool lmce_supported(void)
1518{
1519 uint64_t mce_cap;
1520
1521 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1522 return false;
1523 }
1524
1525 return !!(mce_cap & MCG_LMCE_P);
1526}
1527
c6dc6f63
AP		 1528static int cpu_x86_fill_model_id(char *str)
1529{
1530 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1531 int i;
1532
1533 for (i = 0; i < 3; i++) {
1534 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1535 memcpy(str + i * 16 + 0, &eax, 4);
1536 memcpy(str + i * 16 + 4, &ebx, 4);
1537 memcpy(str + i * 16 + 8, &ecx, 4);
1538 memcpy(str + i * 16 + 12, &edx, 4);
1539 }
1540 return 0;
1541}
1542
d940ee9b
EH		 1543static X86CPUDefinition host_cpudef;
1544
84f1b92f 1545static Property host_x86_cpu_properties[] = {
120eee7d 1546 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1547 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1548 DEFINE_PROP_END_OF_LIST()
1549};
1550
d940ee9b 1551/* class_init for the "host" CPU model
6e746f30 1552 *
d940ee9b 1553 * This function may be called before KVM is initialized.
6e746f30 1554 */
d940ee9b 1555static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1556{
84f1b92f 1557 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1558 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1559 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1560
d940ee9b 1561 xcc->kvm_required = true;
6e746f30 1562
c6dc6f63 1563 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1564 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1565
1566 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1567 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1568 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1569 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1570
d940ee9b 1571 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1572
d940ee9b 1573 xcc->cpu_def = &host_cpudef;
ee465a3e
EH		 1574 xcc->model_description =
1575 "KVM processor with all supported host features "
1576 "(only available in KVM mode)";
d940ee9b
EH		 1577
1578 /* level, xlevel, xlevel2, and the feature words are initialized on
1579 * instance_init, because they require KVM to be initialized.
1580 */
84f1b92f
EH		 1581
1582 dc->props = host_x86_cpu_properties;
4c315c27
MA		 1583 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1584 dc->cannot_destroy_with_object_finalize_yet = true;
d940ee9b
EH		 1585}
1586
1587static void host_x86_cpu_initfn(Object *obj)
1588{
1589 X86CPU *cpu = X86_CPU(obj);
1590 CPUX86State *env = &cpu->env;
1591 KVMState *s = kvm_state;
d940ee9b 1592
4d1b279b
EH		 1593 /* We can't fill the features array here because we don't know yet if
1594 * "migratable" is true or false.
1595 */
1596 cpu->host_features = true;
1597
104494ea 1598 /* If KVM is disabled, x86_cpu_realizefn() will report an error later */
e4356010 1599 if (kvm_enabled()) {
c39c0edf
EH		 1600 env->cpuid_min_level =
1601 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1602 env->cpuid_min_xlevel =
1603 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1604 env->cpuid_min_xlevel2 =
1605 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
40bfe48f
HZ		 1606
1607 if (lmce_supported()) {
1608 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1609 }
e4356010 1610 }
2a573259 1611
d940ee9b 1612 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1613}
1614
d940ee9b
EH		 1615static const TypeInfo host_x86_cpu_type_info = {
1616 .name = X86_CPU_TYPE_NAME("host"),
1617 .parent = TYPE_X86_CPU,
1618 .instance_init = host_x86_cpu_initfn,
1619 .class_init = host_x86_cpu_class_init,
1620};
1621
1622#endif
1623
8459e396 1624static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1625{
8459e396 1626 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1627 int i;
1628
857aee33 1629 for (i = 0; i < 32; ++i) {
72370dc1 1630 if ((1UL << i) & mask) {
bffd67b0 1631 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1632 assert(reg);
fefb41bf 1633 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1634 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1635 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1636 f->cpuid_eax, reg,
1637 f->feat_names[i] ? "." : "",
1638 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1639 }
857aee33 1640 }
c6dc6f63
AP		 1641}
1642
d7bce999
EB		 1643static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1644 const char *name, void *opaque,
1645 Error **errp)
95b8519d
AF		 1646{
1647 X86CPU *cpu = X86_CPU(obj);
1648 CPUX86State *env = &cpu->env;
1649 int64_t value;
1650
1651 value = (env->cpuid_version >> 8) & 0xf;
1652 if (value == 0xf) {
1653 value += (env->cpuid_version >> 20) & 0xff;
1654 }
51e72bc1 1655 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1656}
1657
d7bce999
EB		 1658static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1659 const char *name, void *opaque,
1660 Error **errp)
ed5e1ec3 1661{
71ad61d3
AF		 1662 X86CPU *cpu = X86_CPU(obj);
1663 CPUX86State *env = &cpu->env;
1664 const int64_t min = 0;
1665 const int64_t max = 0xff + 0xf;
65cd9064 1666 Error *local_err = NULL;
71ad61d3
AF		 1667 int64_t value;
1668
51e72bc1 1669 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1670 if (local_err) {
1671 error_propagate(errp, local_err);
71ad61d3
AF		 1672 return;
1673 }
1674 if (value < min || value > max) {
c6bd8c70
MA		 1675 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1676 name ? name : "null", value, min, max);
71ad61d3
AF		 1677 return;
1678 }
1679
ed5e1ec3 1680 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1681 if (value > 0x0f) {
1682 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1683 } else {
71ad61d3 1684 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1685 }
1686}
1687
d7bce999
EB		 1688static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1689 const char *name, void *opaque,
1690 Error **errp)
67e30c83
AF		 1691{
1692 X86CPU *cpu = X86_CPU(obj);
1693 CPUX86State *env = &cpu->env;
1694 int64_t value;
1695
1696 value = (env->cpuid_version >> 4) & 0xf;
1697 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1698 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1699}
1700
d7bce999
EB		 1701static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1702 const char *name, void *opaque,
1703 Error **errp)
b0704cbd 1704{
c5291a4f
AF		 1705 X86CPU *cpu = X86_CPU(obj);
1706 CPUX86State *env = &cpu->env;
1707 const int64_t min = 0;
1708 const int64_t max = 0xff;
65cd9064 1709 Error *local_err = NULL;
c5291a4f
AF		 1710 int64_t value;
1711
51e72bc1 1712 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1713 if (local_err) {
1714 error_propagate(errp, local_err);
c5291a4f
AF		 1715 return;
1716 }
1717 if (value < min || value > max) {
c6bd8c70
MA		 1718 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1719 name ? name : "null", value, min, max);
c5291a4f
AF		 1720 return;
1721 }
1722
b0704cbd 1723 env->cpuid_version &= ~0xf00f0;
c5291a4f 1724 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1725}
1726
35112e41 1727static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1728 const char *name, void *opaque,
35112e41
AF		 1729 Error **errp)
1730{
1731 X86CPU *cpu = X86_CPU(obj);
1732 CPUX86State *env = &cpu->env;
1733 int64_t value;
1734
1735 value = env->cpuid_version & 0xf;
51e72bc1 1736 visit_type_int(v, name, &value, errp);
35112e41
AF		 1737}
1738
036e2222 1739static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1740 const char *name, void *opaque,
036e2222 1741 Error **errp)
38c3dc46 1742{
036e2222
AF		 1743 X86CPU *cpu = X86_CPU(obj);
1744 CPUX86State *env = &cpu->env;
1745 const int64_t min = 0;
1746 const int64_t max = 0xf;
65cd9064 1747 Error *local_err = NULL;
036e2222
AF		 1748 int64_t value;
1749
51e72bc1 1750 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1751 if (local_err) {
1752 error_propagate(errp, local_err);
036e2222
AF		 1753 return;
1754 }
1755 if (value < min || value > max) {
c6bd8c70
MA		 1756 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1757 name ? name : "null", value, min, max);
036e2222
AF		 1758 return;
1759 }
1760
38c3dc46 1761 env->cpuid_version &= ~0xf;
036e2222 1762 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1763}
1764
d480e1af
AF		 1765static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1766{
1767 X86CPU *cpu = X86_CPU(obj);
1768 CPUX86State *env = &cpu->env;
1769 char *value;
d480e1af 1770
e42a92ae 1771 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1772 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1773 env->cpuid_vendor3);
d480e1af
AF		 1774 return value;
1775}
1776
1777static void x86_cpuid_set_vendor(Object *obj, const char *value,
1778 Error **errp)
1779{
1780 X86CPU *cpu = X86_CPU(obj);
1781 CPUX86State *env = &cpu->env;
1782 int i;
1783
9df694ee 1784 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1785 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1786 return;
1787 }
1788
1789 env->cpuid_vendor1 = 0;
1790 env->cpuid_vendor2 = 0;
1791 env->cpuid_vendor3 = 0;
1792 for (i = 0; i < 4; i++) {
1793 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1794 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1795 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1796 }
d480e1af
AF		 1797}
1798
63e886eb
AF		 1799static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1800{
1801 X86CPU *cpu = X86_CPU(obj);
1802 CPUX86State *env = &cpu->env;
1803 char *value;
1804 int i;
1805
1806 value = g_malloc(48 + 1);
1807 for (i = 0; i < 48; i++) {
1808 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1809 }
1810 value[48] = '\0';
1811 return value;
1812}
1813
938d4c25
AF		 1814static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1815 Error **errp)
dcce6675 1816{
938d4c25
AF		 1817 X86CPU *cpu = X86_CPU(obj);
1818 CPUX86State *env = &cpu->env;
dcce6675
AF		 1819 int c, len, i;
1820
1821 if (model_id == NULL) {
1822 model_id = "";
1823 }
1824 len = strlen(model_id);
d0a6acf4 1825 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1826 for (i = 0; i < 48; i++) {
1827 if (i >= len) {
1828 c = '\0';
1829 } else {
1830 c = (uint8_t)model_id[i];
1831 }
1832 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1833 }
1834}
1835
d7bce999
EB		 1836static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1837 void *opaque, Error **errp)
89e48965
AF		 1838{
1839 X86CPU *cpu = X86_CPU(obj);
1840 int64_t value;
1841
1842 value = cpu->env.tsc_khz * 1000;
51e72bc1 1843 visit_type_int(v, name, &value, errp);
89e48965
AF		 1844}
1845
d7bce999
EB		 1846static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1847 void *opaque, Error **errp)
89e48965
AF		 1848{
1849 X86CPU *cpu = X86_CPU(obj);
1850 const int64_t min = 0;
2e84849a 1851 const int64_t max = INT64_MAX;
65cd9064 1852 Error *local_err = NULL;
89e48965
AF		 1853 int64_t value;
1854
51e72bc1 1855 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1856 if (local_err) {
1857 error_propagate(errp, local_err);
89e48965
AF		 1858 return;
1859 }
1860 if (value < min || value > max) {
c6bd8c70
MA		 1861 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1862 name ? name : "null", value, min, max);
89e48965
AF		 1863 return;
1864 }
1865
36f96c4b 1866 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1867}
1868
7e5292b5 1869/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1870static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1871 const char *name, void *opaque,
1872 Error **errp)
8e8aba50 1873{
7e5292b5 1874 uint32_t *array = (uint32_t *)opaque;
8e8aba50 1875 FeatureWord w;
8e8aba50
EH		 1876 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1877 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1878 X86CPUFeatureWordInfoList *list = NULL;
1879
1880 for (w = 0; w < FEATURE_WORDS; w++) {
1881 FeatureWordInfo *wi = &feature_word_info[w];
1882 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1883 qwi->cpuid_input_eax = wi->cpuid_eax;
1884 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1885 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1886 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1887 qwi->features = array[w];
8e8aba50
EH		 1888
1889 /* List will be in reverse order, but order shouldn't matter */
1890 list_entries[w].next = list;
1891 list_entries[w].value = &word_infos[w];
1892 list = &list_entries[w];
1893 }
1894
6b62d961 1895 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 1896}
1897
d7bce999
EB		 1898static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1899 void *opaque, Error **errp)
c8f0f88e
IM		 1900{
1901 X86CPU *cpu = X86_CPU(obj);
1902 int64_t value = cpu->hyperv_spinlock_attempts;
1903
51e72bc1 1904 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1905}
1906
d7bce999
EB		 1907static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1908 void *opaque, Error **errp)
c8f0f88e
IM		 1909{
1910 const int64_t min = 0xFFF;
1911 const int64_t max = UINT_MAX;
1912 X86CPU *cpu = X86_CPU(obj);
1913 Error *err = NULL;
1914 int64_t value;
1915
51e72bc1 1916 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1917 if (err) {
1918 error_propagate(errp, err);
1919 return;
1920 }
1921
1922 if (value < min || value > max) {
1923 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1924 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1925 object_get_typename(obj), name ? name : "null",
1926 value, min, max);
c8f0f88e
IM		 1927 return;
1928 }
1929 cpu->hyperv_spinlock_attempts = value;
1930}
1931
1932static PropertyInfo qdev_prop_spinlocks = {
1933 .name = "int",
1934 .get = x86_get_hv_spinlocks,
1935 .set = x86_set_hv_spinlocks,
1936};
1937
72ac2e87
IM		 1938/* Convert all '_' in a feature string option name to '-', to make feature
1939 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1940 */
1941static inline void feat2prop(char *s)
1942{
1943 while ((s = strchr(s, '_'))) {
1944 *s = '-';
1945 }
1946}
1947
b54c9377
EH		 1948/* Return the feature property name for a feature flag bit */
1949static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
1950{
1951 /* XSAVE components are automatically enabled by other features,
1952 * so return the original feature name instead
1953 */
1954 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
1955 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
1956
1957 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
1958 x86_ext_save_areas[comp].bits) {
1959 w = x86_ext_save_areas[comp].feature;
1960 bitnr = ctz32(x86_ext_save_areas[comp].bits);
1961 }
1962 }
1963
1964 assert(bitnr < 32);
1965 assert(w < FEATURE_WORDS);
1966 return feature_word_info[w].feat_names[bitnr];
1967}
1968
dc15c051
IM		 1969/* Compatibily hack to maintain legacy +-feat semantic,
1970 * where +-feat overwrites any feature set by
1971 * feat=on|feat even if the later is parsed after +-feat
1972 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
1973 */
2fae0d96 1974static GList *plus_features, *minus_features;
dc15c051 1975
8f961357
EH		 1976/* Parse "+feature,-feature,feature=foo" CPU feature string
1977 */
62a48a2a 1978static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 1979 Error **errp)
8f961357 1980{
8f961357 1981 char *featurestr; /* Single 'key=value" string being parsed */
94a444b2 1982 Error *local_err = NULL;
62a48a2a
IM		 1983 static bool cpu_globals_initialized;
1984
1985 if (cpu_globals_initialized) {
1986 return;
1987 }
1988 cpu_globals_initialized = true;
8f961357 1989
f6750e95
EH		 1990 if (!features) {
1991 return;
1992 }
1993
1994 for (featurestr = strtok(features, ",");
1995 featurestr && !local_err;
1996 featurestr = strtok(NULL, ",")) {
1997 const char *name;
1998 const char *val = NULL;
1999 char *eq = NULL;
cf2887c9 2000 char num[32];
62a48a2a 2001 GlobalProperty *prop;
c6dc6f63 2002
f6750e95 2003 /* Compatibility syntax: */
c6dc6f63 2004 if (featurestr[0] == '+') {
2fae0d96
EH		 2005 plus_features = g_list_append(plus_features,
2006 g_strdup(featurestr + 1));
f6750e95 2007 continue;
c6dc6f63 2008 } else if (featurestr[0] == '-') {
2fae0d96
EH		 2009 minus_features = g_list_append(minus_features,
2010 g_strdup(featurestr + 1));
f6750e95
EH		 2011 continue;
2012 }
2013
2014 eq = strchr(featurestr, '=');
2015 if (eq) {
2016 *eq++ = 0;
2017 val = eq;
c6dc6f63 2018 } else {
f6750e95 2019 val = "on";
a91987c2 2020 }
f6750e95
EH		 2021
2022 feat2prop(featurestr);
2023 name = featurestr;
2024
2025 /* Special case: */
2026 if (!strcmp(name, "tsc-freq")) {
2027 int64_t tsc_freq;
2028 char *err;
f6750e95
EH		 2029
2030 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
2031 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
2032 if (tsc_freq < 0 || *err) {
2033 error_setg(errp, "bad numerical value %s", val);
2034 return;
2035 }
2036 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2037 val = num;
2038 name = "tsc-frequency";
c6dc6f63 2039 }
f6750e95 2040
62a48a2a
IM		 2041 prop = g_new0(typeof(*prop), 1);
2042 prop->driver = typename;
2043 prop->property = g_strdup(name);
2044 prop->value = g_strdup(val);
2045 prop->errp = &error_fatal;
2046 qdev_prop_register_global(prop);
f6750e95
EH		 2047 }
2048
2049 if (local_err) {
2050 error_propagate(errp, local_err);
c6dc6f63 2051 }
c6dc6f63
AP		 2052}
2053
b54c9377
EH		 2054static void x86_cpu_load_features(X86CPU *cpu, Error **errp);
2055static int x86_cpu_filter_features(X86CPU *cpu);
2056
2057/* Check for missing features that may prevent the CPU class from
2058 * running using the current machine and accelerator.
2059 */
2060static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
2061 strList **missing_feats)
2062{
2063 X86CPU *xc;
2064 FeatureWord w;
2065 Error *err = NULL;
2066 strList **next = missing_feats;
2067
2068 if (xcc->kvm_required && !kvm_enabled()) {
2069 strList *new = g_new0(strList, 1);
2070 new->value = g_strdup("kvm");;
2071 *missing_feats = new;
2072 return;
2073 }
2074
2075 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2076
2077 x86_cpu_load_features(xc, &err);
2078 if (err) {
2079 /* Errors at x86_cpu_load_features should never happen,
2080 * but in case it does, just report the model as not
2081 * runnable at all using the "type" property.
2082 */
2083 strList *new = g_new0(strList, 1);
2084 new->value = g_strdup("type");
2085 *next = new;
2086 next = &new->next;
2087 }
2088
2089 x86_cpu_filter_features(xc);
2090
2091 for (w = 0; w < FEATURE_WORDS; w++) {
2092 uint32_t filtered = xc->filtered_features[w];
2093 int i;
2094 for (i = 0; i < 32; i++) {
2095 if (filtered & (1UL << i)) {
2096 strList *new = g_new0(strList, 1);
2097 new->value = g_strdup(x86_cpu_feature_name(w, i));
2098 *next = new;
2099 next = &new->next;
2100 }
2101 }
2102 }
2103
2104 object_unref(OBJECT(xc));
2105}
2106
8c3329e5 2107/* Print all cpuid feature names in featureset
c6dc6f63 2108 */
8c3329e5 2109static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2110{
8c3329e5
EH		 2111 int bit;
2112 bool first = true;
2113
2114 for (bit = 0; bit < 32; bit++) {
2115 if (featureset[bit]) {
2116 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2117 first = false;
c6dc6f63 2118 }
8c3329e5 2119 }
c6dc6f63
AP		 2120}
2121
ee465a3e
EH		 2122/* Sort alphabetically by type name, listing kvm_required models last. */
2123static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
2124{
2125 ObjectClass *class_a = (ObjectClass *)a;
2126 ObjectClass *class_b = (ObjectClass *)b;
2127 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
2128 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
2129 const char *name_a, *name_b;
2130
2131 if (cc_a->kvm_required != cc_b->kvm_required) {
2132 /* kvm_required items go last */
2133 return cc_a->kvm_required ? 1 : -1;
2134 } else {
2135 name_a = object_class_get_name(class_a);
2136 name_b = object_class_get_name(class_b);
2137 return strcmp(name_a, name_b);
2138 }
2139}
2140
2141static GSList *get_sorted_cpu_model_list(void)
2142{
2143 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
2144 list = g_slist_sort(list, x86_cpu_list_compare);
2145 return list;
2146}
2147
2148static void x86_cpu_list_entry(gpointer data, gpointer user_data)
2149{
2150 ObjectClass *oc = data;
2151 X86CPUClass *cc = X86_CPU_CLASS(oc);
2152 CPUListState *s = user_data;
2153 char *name = x86_cpu_class_get_model_name(cc);
2154 const char *desc = cc->model_description;
2155 if (!desc) {
2156 desc = cc->cpu_def->model_id;
2157 }
2158
2159 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
2160 name, desc);
2161 g_free(name);
2162}
2163
2164/* list available CPU models and flags */
e916cbf8 2165void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2166{
7fc9b714 2167 int i;
ee465a3e
EH		 2168 CPUListState s = {
2169 .file = f,
2170 .cpu_fprintf = cpu_fprintf,
2171 };
2172 GSList *list;
c6dc6f63 2173
ee465a3e
EH		 2174 (*cpu_fprintf)(f, "Available CPUs:\n");
2175 list = get_sorted_cpu_model_list();
2176 g_slist_foreach(list, x86_cpu_list_entry, &s);
2177 g_slist_free(list);
21ad7789 2178
6cdf8854 2179 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2180 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2181 FeatureWordInfo *fw = &feature_word_info[i];
2182
8c3329e5
EH		 2183 (*cpu_fprintf)(f, " ");
2184 listflags(f, cpu_fprintf, fw->feat_names);
2185 (*cpu_fprintf)(f, "\n");
3af60be2 2186 }
c6dc6f63
AP		 2187}
2188
ee465a3e
EH		 2189static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
2190{
2191 ObjectClass *oc = data;
2192 X86CPUClass *cc = X86_CPU_CLASS(oc);
2193 CpuDefinitionInfoList **cpu_list = user_data;
2194 CpuDefinitionInfoList *entry;
2195 CpuDefinitionInfo *info;
2196
2197 info = g_malloc0(sizeof(*info));
2198 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 2199 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
2200 info->has_unavailable_features = true;
ee465a3e
EH		 2201
2202 entry = g_malloc0(sizeof(*entry));
2203 entry->value = info;
2204 entry->next = *cpu_list;
2205 *cpu_list = entry;
2206}
2207
76b64a7a 2208CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2209{
2210 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 2211 GSList *list = get_sorted_cpu_model_list();
2212 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
2213 g_slist_free(list);
e3966126
AL		 2214 return cpu_list;
2215}
2216
84f1b92f
EH		 2217static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2218 bool migratable_only)
27418adf
EH		 2219{
2220 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2221 uint32_t r;
27418adf 2222
fefb41bf 2223 if (kvm_enabled()) {
84f1b92f
EH		 2224 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2225 wi->cpuid_ecx,
2226 wi->cpuid_reg);
fefb41bf 2227 } else if (tcg_enabled()) {
84f1b92f 2228 r = wi->tcg_features;
fefb41bf
EH		 2229 } else {
2230 return ~0;
2231 }
84f1b92f
EH		 2232 if (migratable_only) {
2233 r &= x86_cpu_get_migratable_flags(w);
2234 }
2235 return r;
27418adf
EH		 2236}
2237
51f63aed
EH		 2238/*
2239 * Filters CPU feature words based on host availability of each feature.
2240 *
51f63aed
EH		 2241 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2242 */
27418adf 2243static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2244{
2245 CPUX86State *env = &cpu->env;
bd87d2a2 2246 FeatureWord w;
51f63aed
EH		 2247 int rv = 0;
2248
bd87d2a2 2249 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f 2250 uint32_t host_feat =
46c032f3 2251 x86_cpu_get_supported_feature_word(w, false);
034acf4a
EH		 2252 uint32_t requested_features = env->features[w];
2253 env->features[w] &= host_feat;
2254 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed 2255 if (cpu->filtered_features[w]) {
51f63aed
EH		 2256 rv = 1;
2257 }
bd87d2a2 2258 }
51f63aed
EH		 2259
2260 return rv;
bc74b7db 2261}
bc74b7db 2262
8ca30e86
EH		 2263static void x86_cpu_report_filtered_features(X86CPU *cpu)
2264{
2265 FeatureWord w;
2266
2267 for (w = 0; w < FEATURE_WORDS; w++) {
2268 report_unavailable_features(w, cpu->filtered_features[w]);
2269 }
2270}
2271
5114e842
EH		 2272static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2273{
2274 PropValue *pv;
2275 for (pv = props; pv->prop; pv++) {
2276 if (!pv->value) {
2277 continue;
2278 }
2279 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2280 &error_abort);
2281 }
2282}
2283
d940ee9b 2284/* Load data from X86CPUDefinition
c080e30e 2285 */
d940ee9b 2286static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2287{
61dcd775 2288 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2289 const char *vendor;
2290 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2291 FeatureWord w;
c6dc6f63 2292
c39c0edf
EH		 2293 /* CPU models only set _minimum_ values for level/xlevel: */
2294 object_property_set_int(OBJECT(cpu), def->level, "min-level", errp);
2295 object_property_set_int(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
2296
2d64255b
AF		 2297 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2298 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2299 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2300 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2301 for (w = 0; w < FEATURE_WORDS; w++) {
2302 env->features[w] = def->features[w];
2303 }
82beb536 2304
9576de75 2305 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2306 if (kvm_enabled()) {
492a4c94
LT		 2307 if (!kvm_irqchip_in_kernel()) {
2308 x86_cpu_change_kvm_default("x2apic", "off");
2309 }
2310
5114e842 2311 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 2312 } else if (tcg_enabled()) {
2313 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 2314 }
5fcca9ff 2315
82beb536 2316 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2317
2318 /* sysenter isn't supported in compatibility mode on AMD,
2319 * syscall isn't supported in compatibility mode on Intel.
2320 * Normally we advertise the actual CPU vendor, but you can
2321 * override this using the 'vendor' property if you want to use
2322 * KVM's sysenter/syscall emulation in compatibility mode and
2323 * when doing cross vendor migration
2324 */
74f54bc4 2325 vendor = def->vendor;
7c08db30
EH		 2326 if (kvm_enabled()) {
2327 uint32_t ebx = 0, ecx = 0, edx = 0;
2328 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2329 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2330 vendor = host_vendor;
2331 }
2332
2333 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2334
c6dc6f63
AP		 2335}
2336
0856579c 2337X86CPU *cpu_x86_init(const char *cpu_model)
7f833247 2338{
a57d0163 2339 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
5c3c6a68
AF		 2340}
2341
d940ee9b
EH		 2342static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2343{
2344 X86CPUDefinition *cpudef = data;
2345 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2346
2347 xcc->cpu_def = cpudef;
2348}
2349
2350static void x86_register_cpudef_type(X86CPUDefinition *def)
2351{
2352 char *typename = x86_cpu_type_name(def->name);
2353 TypeInfo ti = {
2354 .name = typename,
2355 .parent = TYPE_X86_CPU,
2356 .class_init = x86_cpu_cpudef_class_init,
2357 .class_data = def,
2358 };
2359
2360 type_register(&ti);
2361 g_free(typename);
2362}
2363
c6dc6f63 2364#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2365
0e26b7b8
BS		 2366void cpu_clear_apic_feature(CPUX86State *env)
2367{
0514ef2f 2368 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2369}
2370
c6dc6f63
AP		 2371#endif /* !CONFIG_USER_ONLY */
2372
c6dc6f63
AP		 2373void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2374 uint32_t *eax, uint32_t *ebx,
2375 uint32_t *ecx, uint32_t *edx)
2376{
a60f24b5
AF		 2377 X86CPU *cpu = x86_env_get_cpu(env);
2378 CPUState *cs = CPU(cpu);
14c985cf 2379 uint32_t pkg_offset;
a60f24b5 2380
c6dc6f63
AP		 2381 /* test if maximum index reached */
2382 if (index & 0x80000000) {
b3baa152
BW		 2383 if (index > env->cpuid_xlevel) {
2384 if (env->cpuid_xlevel2 > 0) {
2385 /* Handle the Centaur's CPUID instruction. */
2386 if (index > env->cpuid_xlevel2) {
2387 index = env->cpuid_xlevel2;
2388 } else if (index < 0xC0000000) {
2389 index = env->cpuid_xlevel;
2390 }
2391 } else {
57f26ae7
EH		 2392 /* Intel documentation states that invalid EAX input will
2393 * return the same information as EAX=cpuid_level
2394 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2395 */
2396 index = env->cpuid_level;
b3baa152
BW		 2397 }
2398 }
c6dc6f63
AP		 2399 } else {
2400 if (index > env->cpuid_level)
2401 index = env->cpuid_level;
2402 }
2403
2404 switch(index) {
2405 case 0:
2406 *eax = env->cpuid_level;
5eb2f7a4
EH		 2407 *ebx = env->cpuid_vendor1;
2408 *edx = env->cpuid_vendor2;
2409 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2410 break;
2411 case 1:
2412 *eax = env->cpuid_version;
7e72a45c
EH		 2413 *ebx = (cpu->apic_id << 24) |
2414 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2415 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2416 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2417 *ecx |= CPUID_EXT_OSXSAVE;
2418 }
0514ef2f 2419 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2420 if (cs->nr_cores * cs->nr_threads > 1) {
2421 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2422 *edx |= CPUID_HT;
c6dc6f63
AP		 2423 }
2424 break;
2425 case 2:
2426 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2427 if (cpu->cache_info_passthrough) {
2428 host_cpuid(index, 0, eax, ebx, ecx, edx);
2429 break;
2430 }
5e891bf8 2431 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 2432 *ebx = 0;
14c985cf
LM		 2433 if (!cpu->enable_l3_cache) {
2434 *ecx = 0;
2435 } else {
2436 *ecx = L3_N_DESCRIPTOR;
2437 }
5e891bf8
EH		 2438 *edx = (L1D_DESCRIPTOR << 16) | \
2439 (L1I_DESCRIPTOR << 8) | \
2440 (L2_DESCRIPTOR);
c6dc6f63
AP		 2441 break;
2442 case 4:
2443 /* cache info: needed for Core compatibility */
787aaf57
BC		 2444 if (cpu->cache_info_passthrough) {
2445 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2446 *eax &= ~0xFC000000;
c6dc6f63 2447 } else {
2f7a21c4 2448 *eax = 0;
76c2975a 2449 switch (count) {
c6dc6f63 2450 case 0: /* L1 dcache info */
5e891bf8
EH		 2451 *eax |= CPUID_4_TYPE_DCACHE | \
2452 CPUID_4_LEVEL(1) | \
2453 CPUID_4_SELF_INIT_LEVEL;
2454 *ebx = (L1D_LINE_SIZE - 1) | \
2455 ((L1D_PARTITIONS - 1) << 12) | \
2456 ((L1D_ASSOCIATIVITY - 1) << 22);
2457 *ecx = L1D_SETS - 1;
2458 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2459 break;
2460 case 1: /* L1 icache info */
5e891bf8
EH		 2461 *eax |= CPUID_4_TYPE_ICACHE | \
2462 CPUID_4_LEVEL(1) | \
2463 CPUID_4_SELF_INIT_LEVEL;
2464 *ebx = (L1I_LINE_SIZE - 1) | \
2465 ((L1I_PARTITIONS - 1) << 12) | \
2466 ((L1I_ASSOCIATIVITY - 1) << 22);
2467 *ecx = L1I_SETS - 1;
2468 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2469 break;
2470 case 2: /* L2 cache info */
5e891bf8
EH		 2471 *eax |= CPUID_4_TYPE_UNIFIED | \
2472 CPUID_4_LEVEL(2) | \
2473 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2474 if (cs->nr_threads > 1) {
2475 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2476 }
5e891bf8
EH		 2477 *ebx = (L2_LINE_SIZE - 1) | \
2478 ((L2_PARTITIONS - 1) << 12) | \
2479 ((L2_ASSOCIATIVITY - 1) << 22);
2480 *ecx = L2_SETS - 1;
2481 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63 2482 break;
14c985cf
LM		 2483 case 3: /* L3 cache info */
2484 if (!cpu->enable_l3_cache) {
2485 *eax = 0;
2486 *ebx = 0;
2487 *ecx = 0;
2488 *edx = 0;
2489 break;
2490 }
2491 *eax |= CPUID_4_TYPE_UNIFIED | \
2492 CPUID_4_LEVEL(3) | \
2493 CPUID_4_SELF_INIT_LEVEL;
2494 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2495 *eax |= ((1 << pkg_offset) - 1) << 14;
2496 *ebx = (L3_N_LINE_SIZE - 1) | \
2497 ((L3_N_PARTITIONS - 1) << 12) | \
2498 ((L3_N_ASSOCIATIVITY - 1) << 22);
2499 *ecx = L3_N_SETS - 1;
2500 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2501 break;
c6dc6f63
AP		 2502 default: /* end of info */
2503 *eax = 0;
2504 *ebx = 0;
2505 *ecx = 0;
2506 *edx = 0;
2507 break;
76c2975a
PB		 2508 }
2509 }
2510
2511 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2512 if ((*eax & 31) && cs->nr_cores > 1) {
2513 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2514 }
2515 break;
2516 case 5:
2517 /* mwait info: needed for Core compatibility */
2518 *eax = 0; /* Smallest monitor-line size in bytes */
2519 *ebx = 0; /* Largest monitor-line size in bytes */
2520 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2521 *edx = 0;
2522 break;
2523 case 6:
2524 /* Thermal and Power Leaf */
28b8e4d0 2525 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2526 *ebx = 0;
2527 *ecx = 0;
2528 *edx = 0;
2529 break;
f7911686 2530 case 7:
13526728
EH		 2531 /* Structured Extended Feature Flags Enumeration Leaf */
2532 if (count == 0) {
2533 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2534 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2535 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2536 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2537 *ecx |= CPUID_7_0_ECX_OSPKE;
2538 }
13526728 2539 *edx = 0; /* Reserved */
f7911686
YW		 2540 } else {
2541 *eax = 0;
2542 *ebx = 0;
2543 *ecx = 0;
2544 *edx = 0;
2545 }
2546 break;
c6dc6f63
AP		 2547 case 9:
2548 /* Direct Cache Access Information Leaf */
2549 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2550 *ebx = 0;
2551 *ecx = 0;
2552 *edx = 0;
2553 break;
2554 case 0xA:
2555 /* Architectural Performance Monitoring Leaf */
9337e3b6 2556 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2557 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2558
2559 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2560 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2561 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2562 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2563 } else {
2564 *eax = 0;
2565 *ebx = 0;
2566 *ecx = 0;
2567 *edx = 0;
2568 }
c6dc6f63 2569 break;
5232d00a
RK		 2570 case 0xB:
2571 /* Extended Topology Enumeration Leaf */
2572 if (!cpu->enable_cpuid_0xb) {
2573 *eax = *ebx = *ecx = *edx = 0;
2574 break;
2575 }
2576
2577 *ecx = count & 0xff;
2578 *edx = cpu->apic_id;
2579
2580 switch (count) {
2581 case 0:
eab60fb9
MAL		 2582 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
2583 *ebx = cs->nr_threads;
5232d00a
RK		 2584 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2585 break;
2586 case 1:
eab60fb9
MAL		 2587 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2588 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 2589 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2590 break;
2591 default:
2592 *eax = 0;
2593 *ebx = 0;
2594 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2595 }
2596
2597 assert(!(*eax & ~0x1f));
2598 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2599 break;
2560f19f 2600 case 0xD: {
51e49430 2601 /* Processor Extended State */
2560f19f
PB		 2602 *eax = 0;
2603 *ebx = 0;
2604 *ecx = 0;
2605 *edx = 0;
19dc85db 2606 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2607 break;
2608 }
4928cd6d 2609
2560f19f 2610 if (count == 0) {
96193c22
EH		 2611 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
2612 *eax = env->features[FEAT_XSAVE_COMP_LO];
2613 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 2614 *ebx = *ecx;
2615 } else if (count == 1) {
0bb0b2d2 2616 *eax = env->features[FEAT_XSAVE];
f4f1110e 2617 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 2618 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
2619 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 2620 *eax = esa->size;
2621 *ebx = esa->offset;
2560f19f 2622 }
51e49430
SY		 2623 }
2624 break;
2560f19f 2625 }
c6dc6f63
AP		 2626 case 0x80000000:
2627 *eax = env->cpuid_xlevel;
2628 *ebx = env->cpuid_vendor1;
2629 *edx = env->cpuid_vendor2;
2630 *ecx = env->cpuid_vendor3;
2631 break;
2632 case 0x80000001:
2633 *eax = env->cpuid_version;
2634 *ebx = 0;
0514ef2f
EH		 2635 *ecx = env->features[FEAT_8000_0001_ECX];
2636 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2637
2638 /* The Linux kernel checks for the CMPLegacy bit and
2639 * discards multiple thread information if it is set.
cb8d4c8f 2640 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2641 */
ce3960eb 2642 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2643 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2644 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2645 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2646 *ecx |= 1 << 1; /* CmpLegacy bit */
2647 }
2648 }
c6dc6f63
AP		 2649 break;
2650 case 0x80000002:
2651 case 0x80000003:
2652 case 0x80000004:
2653 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2654 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2655 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2656 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2657 break;
2658 case 0x80000005:
2659 /* cache info (L1 cache) */
787aaf57
BC		 2660 if (cpu->cache_info_passthrough) {
2661 host_cpuid(index, 0, eax, ebx, ecx, edx);
2662 break;
2663 }
5e891bf8
EH		 2664 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2665 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2666 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2667 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2668 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2669 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2670 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2671 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2672 break;
2673 case 0x80000006:
2674 /* cache info (L2 cache) */
787aaf57
BC		 2675 if (cpu->cache_info_passthrough) {
2676 host_cpuid(index, 0, eax, ebx, ecx, edx);
2677 break;
2678 }
5e891bf8
EH		 2679 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2680 (L2_DTLB_2M_ENTRIES << 16) | \
2681 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2682 (L2_ITLB_2M_ENTRIES);
2683 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2684 (L2_DTLB_4K_ENTRIES << 16) | \
2685 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2686 (L2_ITLB_4K_ENTRIES);
2687 *ecx = (L2_SIZE_KB_AMD << 16) | \
2688 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2689 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
14c985cf
LM		 2690 if (!cpu->enable_l3_cache) {
2691 *edx = ((L3_SIZE_KB / 512) << 18) | \
2692 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2693 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2694 } else {
2695 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
2696 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
2697 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
2698 }
c6dc6f63 2699 break;
303752a9
MT		 2700 case 0x80000007:
2701 *eax = 0;
2702 *ebx = 0;
2703 *ecx = 0;
2704 *edx = env->features[FEAT_8000_0007_EDX];
2705 break;
c6dc6f63
AP		 2706 case 0x80000008:
2707 /* virtual & phys address size in low 2 bytes. */
0514ef2f 2708 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a
DDAG		 2709 /* 64 bit processor, 48 bits virtual, configurable
2710 * physical bits.
2711 */
2712 *eax = 0x00003000 + cpu->phys_bits;
c6dc6f63 2713 } else {
af45907a 2714 *eax = cpu->phys_bits;
c6dc6f63
AP		 2715 }
2716 *ebx = 0;
2717 *ecx = 0;
2718 *edx = 0;
ce3960eb
AF		 2719 if (cs->nr_cores * cs->nr_threads > 1) {
2720 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2721 }
2722 break;
2723 case 0x8000000A:
0514ef2f 2724 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2725 *eax = 0x00000001; /* SVM Revision */
2726 *ebx = 0x00000010; /* nr of ASIDs */
2727 *ecx = 0;
0514ef2f 2728 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2729 } else {
2730 *eax = 0;
2731 *ebx = 0;
2732 *ecx = 0;
2733 *edx = 0;
2734 }
c6dc6f63 2735 break;
b3baa152
BW		 2736 case 0xC0000000:
2737 *eax = env->cpuid_xlevel2;
2738 *ebx = 0;
2739 *ecx = 0;
2740 *edx = 0;
2741 break;
2742 case 0xC0000001:
2743 /* Support for VIA CPU's CPUID instruction */
2744 *eax = env->cpuid_version;
2745 *ebx = 0;
2746 *ecx = 0;
0514ef2f 2747 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2748 break;
2749 case 0xC0000002:
2750 case 0xC0000003:
2751 case 0xC0000004:
2752 /* Reserved for the future, and now filled with zero */
2753 *eax = 0;
2754 *ebx = 0;
2755 *ecx = 0;
2756 *edx = 0;
2757 break;
c6dc6f63
AP		 2758 default:
2759 /* reserved values: zero */
2760 *eax = 0;
2761 *ebx = 0;
2762 *ecx = 0;
2763 *edx = 0;
2764 break;
2765 }
2766}
5fd2087a
AF		 2767
2768/* CPUClass::reset() */
2769static void x86_cpu_reset(CPUState *s)
2770{
2771 X86CPU *cpu = X86_CPU(s);
2772 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2773 CPUX86State *env = &cpu->env;
a114d25d
RH		 2774 target_ulong cr4;
2775 uint64_t xcr0;
c1958aea
AF		 2776 int i;
2777
5fd2087a
AF		 2778 xcc->parent_reset(s);
2779
5e992a8e 2780 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 2781
00c8cb0a 2782 tlb_flush(s, 1);
c1958aea
AF		 2783
2784 env->old_exception = -1;
2785
2786 /* init to reset state */
2787
c1958aea
AF		 2788 env->hflags2 |= HF2_GIF_MASK;
2789
2790 cpu_x86_update_cr0(env, 0x60000010);
2791 env->a20_mask = ~0x0;
2792 env->smbase = 0x30000;
2793
2794 env->idt.limit = 0xffff;
2795 env->gdt.limit = 0xffff;
2796 env->ldt.limit = 0xffff;
2797 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2798 env->tr.limit = 0xffff;
2799 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2800
2801 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2802 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2803 DESC_R_MASK | DESC_A_MASK);
2804 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2805 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2806 DESC_A_MASK);
2807 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2808 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2809 DESC_A_MASK);
2810 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2811 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2812 DESC_A_MASK);
2813 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2814 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2815 DESC_A_MASK);
2816 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2817 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2818 DESC_A_MASK);
2819
2820 env->eip = 0xfff0;
2821 env->regs[R_EDX] = env->cpuid_version;
2822
2823 env->eflags = 0x2;
2824
2825 /* FPU init */
2826 for (i = 0; i < 8; i++) {
2827 env->fptags[i] = 1;
2828 }
5bde1407 2829 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2830
2831 env->mxcsr = 0x1f80;
a114d25d
RH		 2832 /* All units are in INIT state. */
2833 env->xstate_bv = 0;
c1958aea
AF		 2834
2835 env->pat = 0x0007040600070406ULL;
2836 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2837
2838 memset(env->dr, 0, sizeof(env->dr));
2839 env->dr[6] = DR6_FIXED_1;
2840 env->dr[7] = DR7_FIXED_1;
b3310ab3 2841 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2842 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2843
a114d25d 2844 cr4 = 0;
cfc3b074 2845 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 2846
2847#ifdef CONFIG_USER_ONLY
2848 /* Enable all the features for user-mode. */
2849 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 2850 xcr0 |= XSTATE_SSE_MASK;
a114d25d 2851 }
0f70ed47
PB		 2852 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2853 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 2854 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 2855 xcr0 |= 1ull << i;
2856 }
a114d25d 2857 }
0f70ed47 2858
a114d25d
RH		 2859 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2860 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2861 }
07929f2a
RH		 2862 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2863 cr4 |= CR4_FSGSBASE_MASK;
2864 }
a114d25d
RH		 2865#endif
2866
2867 env->xcr0 = xcr0;
2868 cpu_x86_update_cr4(env, cr4);
0522604b 2869
9db2efd9
AW		 2870 /*
2871 * SDM 11.11.5 requires:
2872 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2873 * - IA32_MTRR_PHYSMASKn.V = 0
2874 * All other bits are undefined. For simplification, zero it all.
2875 */
2876 env->mtrr_deftype = 0;
2877 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2878 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2879
dd673288
IM		 2880#if !defined(CONFIG_USER_ONLY)
2881 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2882 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2883
259186a7 2884 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2885
2886 if (kvm_enabled()) {
2887 kvm_arch_reset_vcpu(cpu);
2888 }
dd673288 2889#endif
5fd2087a
AF		 2890}
2891
dd673288
IM		 2892#ifndef CONFIG_USER_ONLY
2893bool cpu_is_bsp(X86CPU *cpu)
2894{
02e51483 2895 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2896}
65dee380
IM		 2897
2898/* TODO: remove me, when reset over QOM tree is implemented */
2899static void x86_cpu_machine_reset_cb(void *opaque)
2900{
2901 X86CPU *cpu = opaque;
2902 cpu_reset(CPU(cpu));
2903}
dd673288
IM		 2904#endif
2905
de024815
AF		 2906static void mce_init(X86CPU *cpu)
2907{
2908 CPUX86State *cenv = &cpu->env;
2909 unsigned int bank;
2910
2911 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2912 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 2913 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 2914 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
2915 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 2916 cenv->mcg_ctl = ~(uint64_t)0;
2917 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2918 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2919 }
2920 }
2921}
2922
bdeec802 2923#ifndef CONFIG_USER_ONLY
2f114315 2924APICCommonClass *apic_get_class(void)
bdeec802 2925{
bdeec802
IM		 2926 const char *apic_type = "apic";
2927
15eafc2e 2928 if (kvm_apic_in_kernel()) {
bdeec802
IM		 2929 apic_type = "kvm-apic";
2930 } else if (xen_enabled()) {
2931 apic_type = "xen-apic";
2932 }
2933
2f114315
RK		 2934 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
2935}
2936
2937static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2938{
2939 APICCommonState *apic;
2940 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
2941
2942 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 2943
6816b1b3
IM		 2944 object_property_add_child(OBJECT(cpu), "lapic",
2945 OBJECT(cpu->apic_state), &error_abort);
67e55caa 2946 object_unref(OBJECT(cpu->apic_state));
6816b1b3 2947
7e72a45c 2948 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2949 /* TODO: convert to link<> */
02e51483 2950 apic = APIC_COMMON(cpu->apic_state);
60671e58 2951 apic->cpu = cpu;
8d42d2d3 2952 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 2953}
2954
2955static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2956{
8d42d2d3
CF		 2957 APICCommonState *apic;
2958 static bool apic_mmio_map_once;
2959
02e51483 2960 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2961 return;
2962 }
6e8e2651
MA		 2963 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2964 errp);
8d42d2d3
CF		 2965
2966 /* Map APIC MMIO area */
2967 apic = APIC_COMMON(cpu->apic_state);
2968 if (!apic_mmio_map_once) {
2969 memory_region_add_subregion_overlap(get_system_memory(),
2970 apic->apicbase &
2971 MSR_IA32_APICBASE_BASE,
2972 &apic->io_memory,
2973 0x1000);
2974 apic_mmio_map_once = true;
2975 }
bdeec802 2976}
f809c605
PB		 2977
2978static void x86_cpu_machine_done(Notifier *n, void *unused)
2979{
2980 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2981 MemoryRegion *smram =
2982 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2983
2984 if (smram) {
2985 cpu->smram = g_new(MemoryRegion, 1);
2986 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2987 smram, 0, 1ull << 32);
2988 memory_region_set_enabled(cpu->smram, false);
2989 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2990 }
2991}
d3c64d6a
IM		 2992#else
2993static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2994{
2995}
bdeec802
IM		 2996#endif
2997
11f6fee5
DDAG		 2998/* Note: Only safe for use on x86(-64) hosts */
2999static uint32_t x86_host_phys_bits(void)
3000{
3001 uint32_t eax;
3002 uint32_t host_phys_bits;
3003
3004 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
3005 if (eax >= 0x80000008) {
3006 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
3007 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3008 * at 23:16 that can specify a maximum physical address bits for
3009 * the guest that can override this value; but I've not seen
3010 * anything with that set.
3011 */
3012 host_phys_bits = eax & 0xff;
3013 } else {
3014 /* It's an odd 64 bit machine that doesn't have the leaf for
3015 * physical address bits; fall back to 36 that's most older
3016 * Intel.
3017 */
3018 host_phys_bits = 36;
3019 }
3020
3021 return host_phys_bits;
3022}
e48638fd 3023
c39c0edf
EH		 3024static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
3025{
3026 if (*min < value) {
3027 *min = value;
3028 }
3029}
3030
3031/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3032static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
3033{
3034 CPUX86State *env = &cpu->env;
3035 FeatureWordInfo *fi = &feature_word_info[w];
3036 uint32_t eax = fi->cpuid_eax;
3037 uint32_t region = eax & 0xF0000000;
3038
3039 if (!env->features[w]) {
3040 return;
3041 }
3042
3043 switch (region) {
3044 case 0x00000000:
3045 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
3046 break;
3047 case 0x80000000:
3048 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
3049 break;
3050 case 0xC0000000:
3051 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
3052 break;
3053 }
3054}
3055
2ca8a8be
EH		 3056/* Calculate XSAVE components based on the configured CPU feature flags */
3057static void x86_cpu_enable_xsave_components(X86CPU *cpu)
3058{
3059 CPUX86State *env = &cpu->env;
3060 int i;
96193c22 3061 uint64_t mask;
2ca8a8be
EH		 3062
3063 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
3064 return;
3065 }
3066
e3c9022b
EH		 3067 mask = 0;
3068 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 3069 const ExtSaveArea *esa = &x86_ext_save_areas[i];
3070 if (env->features[esa->feature] & esa->bits) {
96193c22 3071 mask |= (1ULL << i);
2ca8a8be
EH		 3072 }
3073 }
3074
96193c22
EH		 3075 env->features[FEAT_XSAVE_COMP_LO] = mask;
3076 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 3077}
3078
41f3d4d6
EH		 3079/* Load CPUID data based on configured features */
3080static void x86_cpu_load_features(X86CPU *cpu, Error **errp)
7a059953 3081{
b34d12d1 3082 CPUX86State *env = &cpu->env;
dc15c051 3083 FeatureWord w;
2fae0d96 3084 GList *l;
41f3d4d6 3085 Error *local_err = NULL;
9886e834 3086
dc15c051
IM		 3087 /*TODO: cpu->host_features incorrectly overwrites features
3088 * set using "feat=on|off". Once we fix this, we can convert
3089 * plus_features & minus_features to global properties
3090 * inside x86_cpu_parse_featurestr() too.
3091 */
3092 if (cpu->host_features) {
3093 for (w = 0; w < FEATURE_WORDS; w++) {
3094 env->features[w] =
3095 x86_cpu_get_supported_feature_word(w, cpu->migratable);
3096 }
3097 }
3098
2fae0d96
EH		 3099 for (l = plus_features; l; l = l->next) {
3100 const char *prop = l->data;
3101 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
3102 if (local_err) {
3103 goto out;
3104 }
3105 }
3106
3107 for (l = minus_features; l; l = l->next) {
3108 const char *prop = l->data;
3109 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
3110 if (local_err) {
3111 goto out;
3112 }
dc15c051
IM		 3113 }
3114
aec661de
EH		 3115 if (!kvm_enabled() || !cpu->expose_kvm) {
3116 env->features[FEAT_KVM] = 0;
3117 }
3118
2ca8a8be 3119 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 3120
3121 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3122 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
3123 if (cpu->full_cpuid_auto_level) {
3124 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
3125 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
3126 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
3127 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
3128 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
3129 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
3130 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
3131 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
3132 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
3133 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 3134 /* SVM requires CPUID[0x8000000A] */
3135 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
3136 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
3137 }
c39c0edf
EH		 3138 }
3139
3140 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3141 if (env->cpuid_level == UINT32_MAX) {
3142 env->cpuid_level = env->cpuid_min_level;
3143 }
3144 if (env->cpuid_xlevel == UINT32_MAX) {
3145 env->cpuid_xlevel = env->cpuid_min_xlevel;
3146 }
3147 if (env->cpuid_xlevel2 == UINT32_MAX) {
3148 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 3149 }
7a059953 3150
41f3d4d6
EH		 3151out:
3152 if (local_err != NULL) {
3153 error_propagate(errp, local_err);
3154 }
3155}
3156
3157#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3158 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3159 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3160#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3161 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3162 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
3163static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
3164{
3165 CPUState *cs = CPU(dev);
3166 X86CPU *cpu = X86_CPU(dev);
3167 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3168 CPUX86State *env = &cpu->env;
3169 Error *local_err = NULL;
3170 static bool ht_warned;
3171
3172 if (xcc->kvm_required && !kvm_enabled()) {
3173 char *name = x86_cpu_class_get_model_name(xcc);
3174 error_setg(&local_err, "CPU model '%s' requires KVM", name);
3175 g_free(name);
3176 goto out;
3177 }
3178
3179 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
3180 error_setg(errp, "apic-id property was not initialized properly");
3181 return;
3182 }
3183
3184 x86_cpu_load_features(cpu, &local_err);
3185 if (local_err) {
3186 goto out;
3187 }
3188
8ca30e86
EH		 3189 if (x86_cpu_filter_features(cpu) &&
3190 (cpu->check_cpuid || cpu->enforce_cpuid)) {
3191 x86_cpu_report_filtered_features(cpu);
3192 if (cpu->enforce_cpuid) {
3193 error_setg(&local_err,
3194 kvm_enabled() ?
3195 "Host doesn't support requested features" :
3196 "TCG doesn't support requested features");
3197 goto out;
3198 }
9997cf7b
EH		 3199 }
3200
9b15cd9e
IM		 3201 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3202 * CPUID[1].EDX.
3203 */
e48638fd 3204 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 3205 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3206 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 3207 & CPUID_EXT2_AMD_ALIASES);
3208 }
3209
11f6fee5
DDAG		 3210 /* For 64bit systems think about the number of physical bits to present.
3211 * ideally this should be the same as the host; anything other than matching
3212 * the host can cause incorrect guest behaviour.
3213 * QEMU used to pick the magic value of 40 bits that corresponds to
3214 * consumer AMD devices but nothing else.
3215 */
af45907a 3216 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a 3217 if (kvm_enabled()) {
11f6fee5
DDAG		 3218 uint32_t host_phys_bits = x86_host_phys_bits();
3219 static bool warned;
3220
3221 if (cpu->host_phys_bits) {
3222 /* The user asked for us to use the host physical bits */
3223 cpu->phys_bits = host_phys_bits;
3224 }
3225
3226 /* Print a warning if the user set it to a value that's not the
3227 * host value.
3228 */
3229 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3230 !warned) {
3231 error_report("Warning: Host physical bits (%u)"
3232 " does not match phys-bits property (%u)",
3233 host_phys_bits, cpu->phys_bits);
3234 warned = true;
3235 }
3236
3237 if (cpu->phys_bits &&
3238 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3239 cpu->phys_bits < 32)) {
af45907a
DDAG		 3240 error_setg(errp, "phys-bits should be between 32 and %u "
3241 " (but is %u)",
3242 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3243 return;
3244 }
3245 } else {
11f6fee5 3246 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 3247 error_setg(errp, "TCG only supports phys-bits=%u",
3248 TCG_PHYS_ADDR_BITS);
3249 return;
3250 }
3251 }
11f6fee5
DDAG		 3252 /* 0 means it was not explicitly set by the user (or by machine
3253 * compat_props or by the host code above). In this case, the default
3254 * is the value used by TCG (40).
3255 */
3256 if (cpu->phys_bits == 0) {
3257 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3258 }
af45907a
DDAG		 3259 } else {
3260 /* For 32 bit systems don't use the user set value, but keep
3261 * phys_bits consistent with what we tell the guest.
3262 */
3263 if (cpu->phys_bits != 0) {
3264 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3265 return;
3266 }
fefb41bf 3267
af45907a
DDAG		 3268 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3269 cpu->phys_bits = 36;
3270 } else {
3271 cpu->phys_bits = 32;
3272 }
3273 }
42ecabaa
EH		 3274 cpu_exec_init(cs, &error_abort);
3275
57f2453a
EH		 3276 if (tcg_enabled()) {
3277 tcg_x86_init();
3278 }
3279
65dee380
IM		 3280#ifndef CONFIG_USER_ONLY
3281 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 3282
0514ef2f 3283 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 3284 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 3285 if (local_err != NULL) {
4dc1f449 3286 goto out;
bdeec802
IM		 3287 }
3288 }
65dee380
IM		 3289#endif
3290
7a059953 3291 mce_init(cpu);
2001d0cd
PB		 3292
3293#ifndef CONFIG_USER_ONLY
3294 if (tcg_enabled()) {
56943e8c
PM		 3295 AddressSpace *newas = g_new(AddressSpace, 1);
3296
f809c605 3297 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 3298 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 3299
3300 /* Outer container... */
3301 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 3302 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 3303
3304 /* ... with two regions inside: normal system memory with low
3305 * priority, and...
3306 */
3307 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3308 get_system_memory(), 0, ~0ull);
3309 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3310 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 3311 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 3312 cs->num_ases = 1;
56943e8c 3313 cpu_address_space_init(cs, newas, 0);
f809c605
PB		 3314
3315 /* ... SMRAM with higher priority, linked from /machine/smram. */
3316 cpu->machine_done.notify = x86_cpu_machine_done;
3317 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 3318 }
3319#endif
3320
14a10fc3 3321 qemu_init_vcpu(cs);
d3c64d6a 3322
e48638fd
WH		 3323 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3324 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3325 * based on inputs (sockets,cores,threads), it is still better to gives
3326 * users a warning.
3327 *
3328 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3329 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3330 */
3331 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3332 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3333 " -smp options properly.");
3334 ht_warned = true;
3335 }
3336
d3c64d6a
IM		 3337 x86_cpu_apic_realize(cpu, &local_err);
3338 if (local_err != NULL) {
3339 goto out;
3340 }
14a10fc3 3341 cpu_reset(cs);
2b6f294c 3342
4dc1f449 3343 xcc->parent_realize(dev, &local_err);
2001d0cd 3344
4dc1f449
IM		 3345out:
3346 if (local_err != NULL) {
3347 error_propagate(errp, local_err);
3348 return;
3349 }
7a059953
AF		 3350}
3351
c884776e
IM		 3352static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3353{
3354 X86CPU *cpu = X86_CPU(dev);
3355
3356#ifndef CONFIG_USER_ONLY
3357 cpu_remove_sync(CPU(dev));
3358 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3359#endif
3360
3361 if (cpu->apic_state) {
3362 object_unparent(OBJECT(cpu->apic_state));
3363 cpu->apic_state = NULL;
3364 }
3365}
3366
38e5c119
EH		 3367typedef struct BitProperty {
3368 uint32_t *ptr;
3369 uint32_t mask;
3370} BitProperty;
3371
d7bce999
EB		 3372static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3373 void *opaque, Error **errp)
38e5c119
EH		 3374{
3375 BitProperty *fp = opaque;
3376 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 3377 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3378}
3379
d7bce999
EB		 3380static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3381 void *opaque, Error **errp)
38e5c119
EH		 3382{
3383 DeviceState *dev = DEVICE(obj);
3384 BitProperty *fp = opaque;
3385 Error *local_err = NULL;
3386 bool value;
3387
3388 if (dev->realized) {
3389 qdev_prop_set_after_realize(dev, name, errp);
3390 return;
3391 }
3392
51e72bc1 3393 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3394 if (local_err) {
3395 error_propagate(errp, local_err);
3396 return;
3397 }
3398
3399 if (value) {
3400 *fp->ptr |= fp->mask;
3401 } else {
3402 *fp->ptr &= ~fp->mask;
3403 }
3404}
3405
3406static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3407 void *opaque)
3408{
3409 BitProperty *prop = opaque;
3410 g_free(prop);
3411}
3412
3413/* Register a boolean property to get/set a single bit in a uint32_t field.
3414 *
3415 * The same property name can be registered multiple times to make it affect
3416 * multiple bits in the same FeatureWord. In that case, the getter will return
3417 * true only if all bits are set.
3418 */
3419static void x86_cpu_register_bit_prop(X86CPU *cpu,
3420 const char *prop_name,
3421 uint32_t *field,
3422 int bitnr)
3423{
3424 BitProperty *fp;
3425 ObjectProperty *op;
3426 uint32_t mask = (1UL << bitnr);
3427
3428 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3429 if (op) {
3430 fp = op->opaque;
3431 assert(fp->ptr == field);
3432 fp->mask |= mask;
3433 } else {
3434 fp = g_new0(BitProperty, 1);
3435 fp->ptr = field;
3436 fp->mask = mask;
3437 object_property_add(OBJECT(cpu), prop_name, "bool",
3438 x86_cpu_get_bit_prop,
3439 x86_cpu_set_bit_prop,
3440 x86_cpu_release_bit_prop, fp, &error_abort);
3441 }
3442}
3443
3444static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3445 FeatureWord w,
3446 int bitnr)
3447{
38e5c119 3448 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 3449 const char *name = fi->feat_names[bitnr];
38e5c119 3450
16d2fcaa 3451 if (!name) {
38e5c119
EH		 3452 return;
3453 }
3454
fc7dfd20
EH		 3455 /* Property names should use "-" instead of "_".
3456 * Old names containing underscores are registered as aliases
3457 * using object_property_add_alias()
3458 */
16d2fcaa
EH		 3459 assert(!strchr(name, '_'));
3460 /* aliases don't use "|" delimiters anymore, they are registered
3461 * manually using object_property_add_alias() */
3462 assert(!strchr(name, '|'));
3463 x86_cpu_register_bit_prop(cpu, name, &cpu->env.features[w], bitnr);
38e5c119
EH		 3464}
3465
de024815
AF		 3466static void x86_cpu_initfn(Object *obj)
3467{
55e5c285 3468 CPUState *cs = CPU(obj);
de024815 3469 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3470 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3471 CPUX86State *env = &cpu->env;
38e5c119 3472 FeatureWord w;
de024815 3473
c05efcb1 3474 cs->env_ptr = env;
71ad61d3
AF		 3475
3476 object_property_add(obj, "family", "int",
95b8519d 3477 x86_cpuid_version_get_family,
71ad61d3 3478 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3479 object_property_add(obj, "model", "int",
67e30c83 3480 x86_cpuid_version_get_model,
c5291a4f 3481 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3482 object_property_add(obj, "stepping", "int",
35112e41 3483 x86_cpuid_version_get_stepping,
036e2222 3484 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3485 object_property_add_str(obj, "vendor",
3486 x86_cpuid_get_vendor,
3487 x86_cpuid_set_vendor, NULL);
938d4c25 3488 object_property_add_str(obj, "model-id",
63e886eb 3489 x86_cpuid_get_model_id,
938d4c25 3490 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3491 object_property_add(obj, "tsc-frequency", "int",
3492 x86_cpuid_get_tsc_freq,
3493 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 3494 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3495 x86_cpu_get_feature_words,
7e5292b5
EH		 3496 NULL, NULL, (void *)env->features, NULL);
3497 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3498 x86_cpu_get_feature_words,
3499 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3500
92067bf4 3501 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3502
38e5c119
EH		 3503 for (w = 0; w < FEATURE_WORDS; w++) {
3504 int bitnr;
3505
3506 for (bitnr = 0; bitnr < 32; bitnr++) {
3507 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3508 }
3509 }
3510
16d2fcaa
EH		 3511 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
3512 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
3513 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
3514 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
3515 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
3516 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
3517 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
3518
54b8dc7c
EH		 3519 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
3520 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
3521 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
3522 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
3523 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
3524 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
3525 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
3526 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
3527 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
3528 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
3529 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
3530 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
3531 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
3532 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
3533 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
3534 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
3535 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
3536 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
3537 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
3538 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
3539 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
3540
d940ee9b 3541 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
de024815
AF		 3542}
3543
997395d3
IM		 3544static int64_t x86_cpu_get_arch_id(CPUState *cs)
3545{
3546 X86CPU *cpu = X86_CPU(cs);
997395d3 3547
7e72a45c 3548 return cpu->apic_id;
997395d3
IM		 3549}
3550
444d5590
AF		 3551static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3552{
3553 X86CPU *cpu = X86_CPU(cs);
3554
3555 return cpu->env.cr[0] & CR0_PG_MASK;
3556}
3557
f45748f1
AF		 3558static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3559{
3560 X86CPU *cpu = X86_CPU(cs);
3561
3562 cpu->env.eip = value;
3563}
3564
bdf7ae5b
AF		 3565static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3566{
3567 X86CPU *cpu = X86_CPU(cs);
3568
3569 cpu->env.eip = tb->pc - tb->cs_base;
3570}
3571
8c2e1b00
AF		 3572static bool x86_cpu_has_work(CPUState *cs)
3573{
3574 X86CPU *cpu = X86_CPU(cs);
3575 CPUX86State *env = &cpu->env;
3576
6220e900
PD		 3577 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3578 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3579 (env->eflags & IF_MASK)) ||
3580 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3581 CPU_INTERRUPT_INIT |
3582 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3583 CPU_INTERRUPT_MCE)) ||
3584 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3585 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3586}
3587
9337e3b6 3588static Property x86_cpu_properties[] = {
2da00e31
IM		 3589#ifdef CONFIG_USER_ONLY
3590 /* apic_id = 0 by default for *-user, see commit 9886e834 */
3591 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 3592 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
3593 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
3594 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 3595#else
3596 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 3597 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
3598 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
3599 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 3600#endif
9337e3b6 3601 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3602 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3603 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3604 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3605 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3606 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3607 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3608 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3609 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3610 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3611 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3612 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3613 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3614 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 3615 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 3616 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 3617 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 3618 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
3619 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
3620 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
3621 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
3622 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
3623 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
3624 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 3625 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 3626 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 3627 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 3628 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
9337e3b6
EH		 3629 DEFINE_PROP_END_OF_LIST()
3630};
3631
5fd2087a
AF		 3632static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3633{
3634 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3635 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3636 DeviceClass *dc = DEVICE_CLASS(oc);
3637
3638 xcc->parent_realize = dc->realize;
3639 dc->realize = x86_cpu_realizefn;
c884776e 3640 dc->unrealize = x86_cpu_unrealizefn;
9337e3b6 3641 dc->props = x86_cpu_properties;
5fd2087a
AF		 3642
3643 xcc->parent_reset = cc->reset;
3644 cc->reset = x86_cpu_reset;
91b1df8c 3645 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3646
500050d1 3647 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3648 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3649 cc->has_work = x86_cpu_has_work;
97a8ea5a 3650 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3651 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3652 cc->dump_state = x86_cpu_dump_state;
f45748f1 3653 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3654 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3655 cc->gdb_read_register = x86_cpu_gdb_read_register;
3656 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3657 cc->get_arch_id = x86_cpu_get_arch_id;
3658 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3659#ifdef CONFIG_USER_ONLY
3660 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3661#else
a23bbfda 3662 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3663 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3664 cc->write_elf64_note = x86_cpu_write_elf64_note;
3665 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3666 cc->write_elf32_note = x86_cpu_write_elf32_note;
3667 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3668 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3669#endif
a0e372f0 3670 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3671#ifndef CONFIG_USER_ONLY
3672 cc->debug_excp_handler = breakpoint_handler;
3673#endif
374e0cd4
RH		 3674 cc->cpu_exec_enter = x86_cpu_exec_enter;
3675 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27 3676
edd12111 3677 dc->cannot_instantiate_with_device_add_yet = false;
5fd2087a
AF		 3678}
3679
3680static const TypeInfo x86_cpu_type_info = {
3681 .name = TYPE_X86_CPU,
3682 .parent = TYPE_CPU,
3683 .instance_size = sizeof(X86CPU),
de024815 3684 .instance_init = x86_cpu_initfn,
d940ee9b 3685 .abstract = true,
5fd2087a
AF		 3686 .class_size = sizeof(X86CPUClass),
3687 .class_init = x86_cpu_common_class_init,
3688};
3689
3690static void x86_cpu_register_types(void)
3691{
d940ee9b
EH		 3692 int i;
3693
5fd2087a 3694 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3695 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3696 x86_register_cpudef_type(&builtin_x86_defs[i]);
3697 }
3698#ifdef CONFIG_KVM
3699 type_register_static(&host_x86_cpu_type_info);
3700#endif
5fd2087a
AF		 3701}
3702
3703type_init(x86_cpu_register_types)
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