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KVM: vmx: move sync_pir_to_irr from apic_find_highest_irr to callers
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
d62caabb 22#include "lapic.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732 25#include <linux/module.h>
9d8f549d 26#include <linux/kernel.h>
6aa8b732
AK		 27#include <linux/mm.h>
28#include <linux/highmem.h>
e8edc6e0 29#include <linux/sched.h>
c7addb90 30#include <linux/moduleparam.h>
e9bda3b3 31#include <linux/mod_devicetable.h>
af658dca 32#include <linux/trace_events.h>
5a0e3ad6 33#include <linux/slab.h>
cafd6659 34#include <linux/tboot.h>
f4124500 35#include <linux/hrtimer.h>
5fdbf976 36#include "kvm_cache_regs.h"
35920a35 37#include "x86.h"
e495606d 38
28b835d6 39#include <asm/cpu.h>
6aa8b732 40#include <asm/io.h>
3b3be0d1 41#include <asm/desc.h>
13673a90 42#include <asm/vmx.h>
6210e37b 43#include <asm/virtext.h>
a0861c02 44#include <asm/mce.h>
952f07ec 45#include <asm/fpu/internal.h>
d7cd9796 46#include <asm/perf_event.h>
81908bf4 47#include <asm/debugreg.h>
8f536b76 48#include <asm/kexec.h>
dab2087d 49#include <asm/apic.h>
efc64404 50#include <asm/irq_remapping.h>
6aa8b732 51
229456fc 52#include "trace.h"
25462f7f 53#include "pmu.h"
229456fc 54
4ecac3fd 55#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 56#define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 58
6aa8b732
AK		 59MODULE_AUTHOR("Qumranet");
60MODULE_LICENSE("GPL");
61
e9bda3b3
JT		 62static const struct x86_cpu_id vmx_cpu_id[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX),
64 {}
65};
66MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
67
476bc001 68static bool __read_mostly enable_vpid = 1;
736caefe 69module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 70
476bc001 71static bool __read_mostly flexpriority_enabled = 1;
736caefe 72module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 73
476bc001 74static bool __read_mostly enable_ept = 1;
736caefe 75module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 76
476bc001 77static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 78module_param_named(unrestricted_guest,
79 enable_unrestricted_guest, bool, S_IRUGO);
80
83c3a331
XH		 81static bool __read_mostly enable_ept_ad_bits = 1;
82module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
83
a27685c3 84static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 85module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 86
476bc001 87static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 88module_param(vmm_exclusive, bool, S_IRUGO);
89
476bc001 90static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 91module_param(fasteoi, bool, S_IRUGO);
92
5a71785d 93static bool __read_mostly enable_apicv = 1;
01e439be 94module_param(enable_apicv, bool, S_IRUGO);
83d4c286 95
abc4fc58
AG		 96static bool __read_mostly enable_shadow_vmcs = 1;
97module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 98/*
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
102 */
476bc001 103static bool __read_mostly nested = 0;
801d3424
NHE		 104module_param(nested, bool, S_IRUGO);
105
20300099
WL		 106static u64 __read_mostly host_xss;
107
843e4330
KH		 108static bool __read_mostly enable_pml = 1;
109module_param_named(pml, enable_pml, bool, S_IRUGO);
110
64903d61
HZ		 111#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112
64672c95
YJ		 113/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
114static int __read_mostly cpu_preemption_timer_multi;
115static bool __read_mostly enable_preemption_timer = 1;
116#ifdef CONFIG_X86_64
117module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
118#endif
119
5037878e
GN		 120#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
121#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 122#define KVM_VM_CR0_ALWAYS_ON \
123 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 124#define KVM_CR4_GUEST_OWNED_BITS \
125 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 126 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 127
cdc0e244
AK		 128#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
129#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
130
78ac8b47
AK		 131#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
132
f4124500
JK		 133#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
134
16c2aec6
JD		 135/*
136 * Hyper-V requires all of these, so mark them as supported even though
137 * they are just treated the same as all-context.
138 */
139#define VMX_VPID_EXTENT_SUPPORTED_MASK \
140 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
141 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
143 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
144
4b8d54f9
ZE		 145/*
146 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
147 * ple_gap: upper bound on the amount of time between two successive
148 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 149 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 150 * ple_window: upper bound on the amount of time a guest is allowed to execute
151 * in a PAUSE loop. Tests indicate that most spinlocks are held for
152 * less than 2^12 cycles
153 * Time is measured based on a counter that runs at the same rate as the TSC,
154 * refer SDM volume 3b section 21.6.13 & 22.1.3.
155 */
b4a2d31d
RK		 156#define KVM_VMX_DEFAULT_PLE_GAP 128
157#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
158#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
159#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
160#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
161 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
162
4b8d54f9
ZE		 163static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
164module_param(ple_gap, int, S_IRUGO);
165
166static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167module_param(ple_window, int, S_IRUGO);
168
b4a2d31d
RK		 169/* Default doubles per-vcpu window every exit. */
170static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
171module_param(ple_window_grow, int, S_IRUGO);
172
173/* Default resets per-vcpu window every exit to ple_window. */
174static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
175module_param(ple_window_shrink, int, S_IRUGO);
176
177/* Default is to compute the maximum so we can never overflow. */
178static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
180module_param(ple_window_max, int, S_IRUGO);
181
83287ea4
AK		 182extern const ulong vmx_return;
183
8bf00a52 184#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 185#define VMCS02_POOL_SIZE 1
61d2ef2c 186
a2fa3e9f
GH		 187struct vmcs {
188 u32 revision_id;
189 u32 abort;
190 char data[0];
191};
192
d462b819
NHE		 193/*
194 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
195 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
196 * loaded on this CPU (so we can clear them if the CPU goes down).
197 */
198struct loaded_vmcs {
199 struct vmcs *vmcs;
355f4fb1 200 struct vmcs *shadow_vmcs;
d462b819
NHE		 201 int cpu;
202 int launched;
203 struct list_head loaded_vmcss_on_cpu_link;
204};
205
26bb0981
AK		 206struct shared_msr_entry {
207 unsigned index;
208 u64 data;
d5696725 209 u64 mask;
26bb0981
AK		 210};
211
a9d30f33
NHE		 212/*
213 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
214 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
215 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
216 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
217 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
218 * More than one of these structures may exist, if L1 runs multiple L2 guests.
219 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
220 * underlying hardware which will be used to run L2.
221 * This structure is packed to ensure that its layout is identical across
222 * machines (necessary for live migration).
223 * If there are changes in this struct, VMCS12_REVISION must be changed.
224 */
22bd0358 225typedef u64 natural_width;
a9d30f33
NHE		 226struct __packed vmcs12 {
227 /* According to the Intel spec, a VMCS region must start with the
228 * following two fields. Then follow implementation-specific data.
229 */
230 u32 revision_id;
231 u32 abort;
22bd0358 232
27d6c865
NHE		 233 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
234 u32 padding[7]; /* room for future expansion */
235
22bd0358
NHE		 236 u64 io_bitmap_a;
237 u64 io_bitmap_b;
238 u64 msr_bitmap;
239 u64 vm_exit_msr_store_addr;
240 u64 vm_exit_msr_load_addr;
241 u64 vm_entry_msr_load_addr;
242 u64 tsc_offset;
243 u64 virtual_apic_page_addr;
244 u64 apic_access_addr;
705699a1 245 u64 posted_intr_desc_addr;
22bd0358 246 u64 ept_pointer;
608406e2
WV		 247 u64 eoi_exit_bitmap0;
248 u64 eoi_exit_bitmap1;
249 u64 eoi_exit_bitmap2;
250 u64 eoi_exit_bitmap3;
81dc01f7 251 u64 xss_exit_bitmap;
22bd0358
NHE		 252 u64 guest_physical_address;
253 u64 vmcs_link_pointer;
254 u64 guest_ia32_debugctl;
255 u64 guest_ia32_pat;
256 u64 guest_ia32_efer;
257 u64 guest_ia32_perf_global_ctrl;
258 u64 guest_pdptr0;
259 u64 guest_pdptr1;
260 u64 guest_pdptr2;
261 u64 guest_pdptr3;
36be0b9d 262 u64 guest_bndcfgs;
22bd0358
NHE		 263 u64 host_ia32_pat;
264 u64 host_ia32_efer;
265 u64 host_ia32_perf_global_ctrl;
266 u64 padding64[8]; /* room for future expansion */
267 /*
268 * To allow migration of L1 (complete with its L2 guests) between
269 * machines of different natural widths (32 or 64 bit), we cannot have
270 * unsigned long fields with no explict size. We use u64 (aliased
271 * natural_width) instead. Luckily, x86 is little-endian.
272 */
273 natural_width cr0_guest_host_mask;
274 natural_width cr4_guest_host_mask;
275 natural_width cr0_read_shadow;
276 natural_width cr4_read_shadow;
277 natural_width cr3_target_value0;
278 natural_width cr3_target_value1;
279 natural_width cr3_target_value2;
280 natural_width cr3_target_value3;
281 natural_width exit_qualification;
282 natural_width guest_linear_address;
283 natural_width guest_cr0;
284 natural_width guest_cr3;
285 natural_width guest_cr4;
286 natural_width guest_es_base;
287 natural_width guest_cs_base;
288 natural_width guest_ss_base;
289 natural_width guest_ds_base;
290 natural_width guest_fs_base;
291 natural_width guest_gs_base;
292 natural_width guest_ldtr_base;
293 natural_width guest_tr_base;
294 natural_width guest_gdtr_base;
295 natural_width guest_idtr_base;
296 natural_width guest_dr7;
297 natural_width guest_rsp;
298 natural_width guest_rip;
299 natural_width guest_rflags;
300 natural_width guest_pending_dbg_exceptions;
301 natural_width guest_sysenter_esp;
302 natural_width guest_sysenter_eip;
303 natural_width host_cr0;
304 natural_width host_cr3;
305 natural_width host_cr4;
306 natural_width host_fs_base;
307 natural_width host_gs_base;
308 natural_width host_tr_base;
309 natural_width host_gdtr_base;
310 natural_width host_idtr_base;
311 natural_width host_ia32_sysenter_esp;
312 natural_width host_ia32_sysenter_eip;
313 natural_width host_rsp;
314 natural_width host_rip;
315 natural_width paddingl[8]; /* room for future expansion */
316 u32 pin_based_vm_exec_control;
317 u32 cpu_based_vm_exec_control;
318 u32 exception_bitmap;
319 u32 page_fault_error_code_mask;
320 u32 page_fault_error_code_match;
321 u32 cr3_target_count;
322 u32 vm_exit_controls;
323 u32 vm_exit_msr_store_count;
324 u32 vm_exit_msr_load_count;
325 u32 vm_entry_controls;
326 u32 vm_entry_msr_load_count;
327 u32 vm_entry_intr_info_field;
328 u32 vm_entry_exception_error_code;
329 u32 vm_entry_instruction_len;
330 u32 tpr_threshold;
331 u32 secondary_vm_exec_control;
332 u32 vm_instruction_error;
333 u32 vm_exit_reason;
334 u32 vm_exit_intr_info;
335 u32 vm_exit_intr_error_code;
336 u32 idt_vectoring_info_field;
337 u32 idt_vectoring_error_code;
338 u32 vm_exit_instruction_len;
339 u32 vmx_instruction_info;
340 u32 guest_es_limit;
341 u32 guest_cs_limit;
342 u32 guest_ss_limit;
343 u32 guest_ds_limit;
344 u32 guest_fs_limit;
345 u32 guest_gs_limit;
346 u32 guest_ldtr_limit;
347 u32 guest_tr_limit;
348 u32 guest_gdtr_limit;
349 u32 guest_idtr_limit;
350 u32 guest_es_ar_bytes;
351 u32 guest_cs_ar_bytes;
352 u32 guest_ss_ar_bytes;
353 u32 guest_ds_ar_bytes;
354 u32 guest_fs_ar_bytes;
355 u32 guest_gs_ar_bytes;
356 u32 guest_ldtr_ar_bytes;
357 u32 guest_tr_ar_bytes;
358 u32 guest_interruptibility_info;
359 u32 guest_activity_state;
360 u32 guest_sysenter_cs;
361 u32 host_ia32_sysenter_cs;
0238ea91
JK		 362 u32 vmx_preemption_timer_value;
363 u32 padding32[7]; /* room for future expansion */
22bd0358 364 u16 virtual_processor_id;
705699a1 365 u16 posted_intr_nv;
22bd0358
NHE		 366 u16 guest_es_selector;
367 u16 guest_cs_selector;
368 u16 guest_ss_selector;
369 u16 guest_ds_selector;
370 u16 guest_fs_selector;
371 u16 guest_gs_selector;
372 u16 guest_ldtr_selector;
373 u16 guest_tr_selector;
608406e2 374 u16 guest_intr_status;
22bd0358
NHE		 375 u16 host_es_selector;
376 u16 host_cs_selector;
377 u16 host_ss_selector;
378 u16 host_ds_selector;
379 u16 host_fs_selector;
380 u16 host_gs_selector;
381 u16 host_tr_selector;
a9d30f33
NHE		 382};
383
384/*
385 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
386 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
387 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
388 */
389#define VMCS12_REVISION 0x11e57ed0
390
391/*
392 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
393 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
394 * current implementation, 4K are reserved to avoid future complications.
395 */
396#define VMCS12_SIZE 0x1000
397
ff2f6fe9
NHE		 398/* Used to remember the last vmcs02 used for some recently used vmcs12s */
399struct vmcs02_list {
400 struct list_head list;
401 gpa_t vmptr;
402 struct loaded_vmcs vmcs02;
403};
404
ec378aee
NHE		 405/*
406 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
407 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
408 */
409struct nested_vmx {
410 /* Has the level1 guest done vmxon? */
411 bool vmxon;
3573e22c 412 gpa_t vmxon_ptr;
a9d30f33
NHE		 413
414 /* The guest-physical address of the current VMCS L1 keeps for L2 */
415 gpa_t current_vmptr;
416 /* The host-usable pointer to the above */
417 struct page *current_vmcs12_page;
418 struct vmcs12 *current_vmcs12;
4f2777bc
DM		 419 /*
420 * Cache of the guest's VMCS, existing outside of guest memory.
421 * Loaded from guest memory during VMPTRLD. Flushed to guest
422 * memory during VMXOFF, VMCLEAR, VMPTRLD.
423 */
424 struct vmcs12 *cached_vmcs12;
012f83cb
AG		 425 /*
426 * Indicates if the shadow vmcs must be updated with the
427 * data hold by vmcs12
428 */
429 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 430
431 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
432 struct list_head vmcs02_pool;
433 int vmcs02_num;
dccbfcf5 434 bool change_vmcs01_virtual_x2apic_mode;
644d711a
NHE		 435 /* L2 must run next, and mustn't decide to exit to L1. */
436 bool nested_run_pending;
fe3ef05c
NHE		 437 /*
438 * Guest pages referred to in vmcs02 with host-physical pointers, so
439 * we must keep them pinned while L2 runs.
440 */
441 struct page *apic_access_page;
a7c0b07d 442 struct page *virtual_apic_page;
705699a1
WV		 443 struct page *pi_desc_page;
444 struct pi_desc *pi_desc;
445 bool pi_pending;
446 u16 posted_intr_nv;
f4124500 447
d048c098
RK		 448 unsigned long *msr_bitmap;
449
f4124500
JK		 450 struct hrtimer preemption_timer;
451 bool preemption_timer_expired;
2996fca0
JK		 452
453 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
454 u64 vmcs01_debugctl;
b9c237bb 455
5c614b35
WL		 456 u16 vpid02;
457 u16 last_vpid;
458
0115f9cb
DM		 459 /*
460 * We only store the "true" versions of the VMX capability MSRs. We
461 * generate the "non-true" versions by setting the must-be-1 bits
462 * according to the SDM.
463 */
b9c237bb
WV		 464 u32 nested_vmx_procbased_ctls_low;
465 u32 nested_vmx_procbased_ctls_high;
b9c237bb
WV		 466 u32 nested_vmx_secondary_ctls_low;
467 u32 nested_vmx_secondary_ctls_high;
468 u32 nested_vmx_pinbased_ctls_low;
469 u32 nested_vmx_pinbased_ctls_high;
470 u32 nested_vmx_exit_ctls_low;
471 u32 nested_vmx_exit_ctls_high;
b9c237bb
WV		 472 u32 nested_vmx_entry_ctls_low;
473 u32 nested_vmx_entry_ctls_high;
b9c237bb
WV		 474 u32 nested_vmx_misc_low;
475 u32 nested_vmx_misc_high;
476 u32 nested_vmx_ept_caps;
99b83ac8 477 u32 nested_vmx_vpid_caps;
62cc6b9d
DM		 478 u64 nested_vmx_basic;
479 u64 nested_vmx_cr0_fixed0;
480 u64 nested_vmx_cr0_fixed1;
481 u64 nested_vmx_cr4_fixed0;
482 u64 nested_vmx_cr4_fixed1;
483 u64 nested_vmx_vmcs_enum;
ec378aee
NHE		 484};
485
01e439be 486#define POSTED_INTR_ON 0
ebbfc765
FW		 487#define POSTED_INTR_SN 1
488
01e439be
YZ		 489/* Posted-Interrupt Descriptor */
490struct pi_desc {
491 u32 pir[8]; /* Posted interrupt requested */
6ef1522f
FW		 492 union {
493 struct {
494 /* bit 256 - Outstanding Notification */
495 u16 on : 1,
496 /* bit 257 - Suppress Notification */
497 sn : 1,
498 /* bit 271:258 - Reserved */
499 rsvd_1 : 14;
500 /* bit 279:272 - Notification Vector */
501 u8 nv;
502 /* bit 287:280 - Reserved */
503 u8 rsvd_2;
504 /* bit 319:288 - Notification Destination */
505 u32 ndst;
506 };
507 u64 control;
508 };
509 u32 rsvd[6];
01e439be
YZ		 510} __aligned(64);
511
a20ed54d
YZ		 512static bool pi_test_and_set_on(struct pi_desc *pi_desc)
513{
514 return test_and_set_bit(POSTED_INTR_ON,
515 (unsigned long *)&pi_desc->control);
516}
517
518static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
519{
520 return test_and_clear_bit(POSTED_INTR_ON,
521 (unsigned long *)&pi_desc->control);
522}
523
524static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
525{
526 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
527}
528
ebbfc765
FW		 529static inline void pi_clear_sn(struct pi_desc *pi_desc)
530{
531 return clear_bit(POSTED_INTR_SN,
532 (unsigned long *)&pi_desc->control);
533}
534
535static inline void pi_set_sn(struct pi_desc *pi_desc)
536{
537 return set_bit(POSTED_INTR_SN,
538 (unsigned long *)&pi_desc->control);
539}
540
ad361091
PB		 541static inline void pi_clear_on(struct pi_desc *pi_desc)
542{
543 clear_bit(POSTED_INTR_ON,
544 (unsigned long *)&pi_desc->control);
545}
546
ebbfc765
FW		 547static inline int pi_test_on(struct pi_desc *pi_desc)
548{
549 return test_bit(POSTED_INTR_ON,
550 (unsigned long *)&pi_desc->control);
551}
552
553static inline int pi_test_sn(struct pi_desc *pi_desc)
554{
555 return test_bit(POSTED_INTR_SN,
556 (unsigned long *)&pi_desc->control);
557}
558
a2fa3e9f 559struct vcpu_vmx {
fb3f0f51 560 struct kvm_vcpu vcpu;
313dbd49 561 unsigned long host_rsp;
29bd8a78 562 u8 fail;
9d58b931 563 bool nmi_known_unmasked;
51aa01d1 564 u32 exit_intr_info;
1155f76a 565 u32 idt_vectoring_info;
6de12732 566 ulong rflags;
26bb0981 567 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 568 int nmsrs;
569 int save_nmsrs;
a547c6db 570 unsigned long host_idt_base;
a2fa3e9f 571#ifdef CONFIG_X86_64
44ea2b17
AK		 572 u64 msr_host_kernel_gs_base;
573 u64 msr_guest_kernel_gs_base;
a2fa3e9f 574#endif
2961e876
GN		 575 u32 vm_entry_controls_shadow;
576 u32 vm_exit_controls_shadow;
d462b819
NHE		 577 /*
578 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
579 * non-nested (L1) guest, it always points to vmcs01. For a nested
580 * guest (L2), it points to a different VMCS.
581 */
582 struct loaded_vmcs vmcs01;
583 struct loaded_vmcs *loaded_vmcs;
584 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 585 struct msr_autoload {
586 unsigned nr;
587 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
588 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
589 } msr_autoload;
a2fa3e9f
GH		 590 struct {
591 int loaded;
592 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 593#ifdef CONFIG_X86_64
594 u16 ds_sel, es_sel;
595#endif
152d3f2f
LV		 596 int gs_ldt_reload_needed;
597 int fs_reload_needed;
da8999d3 598 u64 msr_host_bndcfgs;
d974baa3 599 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 600 } host_state;
9c8cba37 601 struct {
7ffd92c5 602 int vm86_active;
78ac8b47 603 ulong save_rflags;
f5f7b2fe
AK		 604 struct kvm_segment segs[8];
605 } rmode;
606 struct {
607 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 608 struct kvm_save_segment {
609 u16 selector;
610 unsigned long base;
611 u32 limit;
612 u32 ar;
f5f7b2fe 613 } seg[8];
2fb92db1 614 } segment_cache;
2384d2b3 615 int vpid;
04fa4d32 616 bool emulation_required;
3b86cd99
JK		 617
618 /* Support for vnmi-less CPUs */
619 int soft_vnmi_blocked;
620 ktime_t entry_time;
621 s64 vnmi_blocked_time;
a0861c02 622 u32 exit_reason;
4e47c7a6 623
01e439be
YZ		 624 /* Posted interrupt descriptor */
625 struct pi_desc pi_desc;
626
ec378aee
NHE		 627 /* Support for a guest hypervisor (nested VMX) */
628 struct nested_vmx nested;
a7653ecd
RK		 629
630 /* Dynamic PLE window. */
631 int ple_window;
632 bool ple_window_dirty;
843e4330
KH		 633
634 /* Support for PML */
635#define PML_ENTITY_NUM 512
636 struct page *pml_pg;
2680d6da 637
64672c95
YJ		 638 /* apic deadline value in host tsc */
639 u64 hv_deadline_tsc;
640
2680d6da 641 u64 current_tsc_ratio;
1be0e61c
XG		 642
643 bool guest_pkru_valid;
644 u32 guest_pkru;
645 u32 host_pkru;
3b84080b 646
37e4c997
HZ		 647 /*
648 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
649 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
650 * in msr_ia32_feature_control_valid_bits.
651 */
3b84080b 652 u64 msr_ia32_feature_control;
37e4c997 653 u64 msr_ia32_feature_control_valid_bits;
a2fa3e9f
GH		 654};
655
2fb92db1
AK		 656enum segment_cache_field {
657 SEG_FIELD_SEL = 0,
658 SEG_FIELD_BASE = 1,
659 SEG_FIELD_LIMIT = 2,
660 SEG_FIELD_AR = 3,
661
662 SEG_FIELD_NR = 4
663};
664
a2fa3e9f
GH		 665static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
666{
fb3f0f51 667 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 668}
669
efc64404
FW		 670static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
671{
672 return &(to_vmx(vcpu)->pi_desc);
673}
674
22bd0358
NHE		 675#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
676#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
677#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
678 [number##_HIGH] = VMCS12_OFFSET(name)+4
679
4607c2d7 680
fe2b201b 681static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 682 /*
683 * We do NOT shadow fields that are modified when L0
684 * traps and emulates any vmx instruction (e.g. VMPTRLD,
685 * VMXON...) executed by L1.
686 * For example, VM_INSTRUCTION_ERROR is read
687 * by L1 if a vmx instruction fails (part of the error path).
688 * Note the code assumes this logic. If for some reason
689 * we start shadowing these fields then we need to
690 * force a shadow sync when L0 emulates vmx instructions
691 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
692 * by nested_vmx_failValid)
693 */
694 VM_EXIT_REASON,
695 VM_EXIT_INTR_INFO,
696 VM_EXIT_INSTRUCTION_LEN,
697 IDT_VECTORING_INFO_FIELD,
698 IDT_VECTORING_ERROR_CODE,
699 VM_EXIT_INTR_ERROR_CODE,
700 EXIT_QUALIFICATION,
701 GUEST_LINEAR_ADDRESS,
702 GUEST_PHYSICAL_ADDRESS
703};
fe2b201b 704static int max_shadow_read_only_fields =
4607c2d7
AG		 705 ARRAY_SIZE(shadow_read_only_fields);
706
fe2b201b 707static unsigned long shadow_read_write_fields[] = {
a7c0b07d 708 TPR_THRESHOLD,
4607c2d7
AG		 709 GUEST_RIP,
710 GUEST_RSP,
711 GUEST_CR0,
712 GUEST_CR3,
713 GUEST_CR4,
714 GUEST_INTERRUPTIBILITY_INFO,
715 GUEST_RFLAGS,
716 GUEST_CS_SELECTOR,
717 GUEST_CS_AR_BYTES,
718 GUEST_CS_LIMIT,
719 GUEST_CS_BASE,
720 GUEST_ES_BASE,
36be0b9d 721 GUEST_BNDCFGS,
4607c2d7
AG		 722 CR0_GUEST_HOST_MASK,
723 CR0_READ_SHADOW,
724 CR4_READ_SHADOW,
725 TSC_OFFSET,
726 EXCEPTION_BITMAP,
727 CPU_BASED_VM_EXEC_CONTROL,
728 VM_ENTRY_EXCEPTION_ERROR_CODE,
729 VM_ENTRY_INTR_INFO_FIELD,
730 VM_ENTRY_INSTRUCTION_LEN,
731 VM_ENTRY_EXCEPTION_ERROR_CODE,
732 HOST_FS_BASE,
733 HOST_GS_BASE,
734 HOST_FS_SELECTOR,
735 HOST_GS_SELECTOR
736};
fe2b201b 737static int max_shadow_read_write_fields =
4607c2d7
AG		 738 ARRAY_SIZE(shadow_read_write_fields);
739
772e0318 740static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 741 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 742 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE		 743 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
744 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
745 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
746 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
747 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
748 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
749 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
750 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 751 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 752 FIELD(HOST_ES_SELECTOR, host_es_selector),
753 FIELD(HOST_CS_SELECTOR, host_cs_selector),
754 FIELD(HOST_SS_SELECTOR, host_ss_selector),
755 FIELD(HOST_DS_SELECTOR, host_ds_selector),
756 FIELD(HOST_FS_SELECTOR, host_fs_selector),
757 FIELD(HOST_GS_SELECTOR, host_gs_selector),
758 FIELD(HOST_TR_SELECTOR, host_tr_selector),
759 FIELD64(IO_BITMAP_A, io_bitmap_a),
760 FIELD64(IO_BITMAP_B, io_bitmap_b),
761 FIELD64(MSR_BITMAP, msr_bitmap),
762 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
763 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
764 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
765 FIELD64(TSC_OFFSET, tsc_offset),
766 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
767 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 768 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 769 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 770 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
771 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
772 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
773 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 774 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 775 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
776 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
777 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
778 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
779 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
780 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
781 FIELD64(GUEST_PDPTR0, guest_pdptr0),
782 FIELD64(GUEST_PDPTR1, guest_pdptr1),
783 FIELD64(GUEST_PDPTR2, guest_pdptr2),
784 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 785 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 786 FIELD64(HOST_IA32_PAT, host_ia32_pat),
787 FIELD64(HOST_IA32_EFER, host_ia32_efer),
788 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
789 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
790 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
791 FIELD(EXCEPTION_BITMAP, exception_bitmap),
792 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
793 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
794 FIELD(CR3_TARGET_COUNT, cr3_target_count),
795 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
796 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
797 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
798 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
799 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
800 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
801 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
802 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
803 FIELD(TPR_THRESHOLD, tpr_threshold),
804 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
805 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
806 FIELD(VM_EXIT_REASON, vm_exit_reason),
807 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
808 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
809 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
810 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
811 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
812 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
813 FIELD(GUEST_ES_LIMIT, guest_es_limit),
814 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
815 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
816 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
817 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
818 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
819 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
820 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
821 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
822 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
823 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
824 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
825 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
826 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
827 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
828 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
829 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
830 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
831 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
832 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
833 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
834 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 835 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 836 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
837 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
838 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
839 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
840 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
841 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
842 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
843 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
844 FIELD(EXIT_QUALIFICATION, exit_qualification),
845 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
846 FIELD(GUEST_CR0, guest_cr0),
847 FIELD(GUEST_CR3, guest_cr3),
848 FIELD(GUEST_CR4, guest_cr4),
849 FIELD(GUEST_ES_BASE, guest_es_base),
850 FIELD(GUEST_CS_BASE, guest_cs_base),
851 FIELD(GUEST_SS_BASE, guest_ss_base),
852 FIELD(GUEST_DS_BASE, guest_ds_base),
853 FIELD(GUEST_FS_BASE, guest_fs_base),
854 FIELD(GUEST_GS_BASE, guest_gs_base),
855 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
856 FIELD(GUEST_TR_BASE, guest_tr_base),
857 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
858 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
859 FIELD(GUEST_DR7, guest_dr7),
860 FIELD(GUEST_RSP, guest_rsp),
861 FIELD(GUEST_RIP, guest_rip),
862 FIELD(GUEST_RFLAGS, guest_rflags),
863 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
864 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
865 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
866 FIELD(HOST_CR0, host_cr0),
867 FIELD(HOST_CR3, host_cr3),
868 FIELD(HOST_CR4, host_cr4),
869 FIELD(HOST_FS_BASE, host_fs_base),
870 FIELD(HOST_GS_BASE, host_gs_base),
871 FIELD(HOST_TR_BASE, host_tr_base),
872 FIELD(HOST_GDTR_BASE, host_gdtr_base),
873 FIELD(HOST_IDTR_BASE, host_idtr_base),
874 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
875 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
876 FIELD(HOST_RSP, host_rsp),
877 FIELD(HOST_RIP, host_rip),
878};
22bd0358
NHE		 879
880static inline short vmcs_field_to_offset(unsigned long field)
881{
a2ae9df7
PB		 882 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
883
884 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
885 vmcs_field_to_offset_table[field] == 0)
886 return -ENOENT;
887
22bd0358
NHE		 888 return vmcs_field_to_offset_table[field];
889}
890
a9d30f33
NHE		 891static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
892{
4f2777bc 893 return to_vmx(vcpu)->nested.cached_vmcs12;
a9d30f33
NHE		 894}
895
896static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
897{
54bf36aa 898 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 899 if (is_error_page(page))
a9d30f33 900 return NULL;
32cad84f 901
a9d30f33
NHE		 902 return page;
903}
904
905static void nested_release_page(struct page *page)
906{
907 kvm_release_page_dirty(page);
908}
909
910static void nested_release_page_clean(struct page *page)
911{
912 kvm_release_page_clean(page);
913}
914
bfd0a56b 915static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 916static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 917static void kvm_cpu_vmxon(u64 addr);
918static void kvm_cpu_vmxoff(void);
f53cd63c 919static bool vmx_xsaves_supported(void);
776e58ea 920static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 921static void vmx_set_segment(struct kvm_vcpu *vcpu,
922 struct kvm_segment *var, int seg);
923static void vmx_get_segment(struct kvm_vcpu *vcpu,
924 struct kvm_segment *var, int seg);
d99e4152
GN		 925static bool guest_state_valid(struct kvm_vcpu *vcpu);
926static u32 vmx_segment_access_rights(struct kvm_segment *var);
c3114420 927static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 928static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 929static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 930
6aa8b732
AK		 931static DEFINE_PER_CPU(struct vmcs *, vmxarea);
932static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 933/*
934 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
935 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
936 */
937static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 938static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 939
bf9f6ac8
FW		 940/*
941 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
942 * can find which vCPU should be waken up.
943 */
944static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
945static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
946
23611332
RK		 947enum {
948 VMX_IO_BITMAP_A,
949 VMX_IO_BITMAP_B,
950 VMX_MSR_BITMAP_LEGACY,
951 VMX_MSR_BITMAP_LONGMODE,
952 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
953 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
954 VMX_MSR_BITMAP_LEGACY_X2APIC,
955 VMX_MSR_BITMAP_LONGMODE_X2APIC,
956 VMX_VMREAD_BITMAP,
957 VMX_VMWRITE_BITMAP,
958 VMX_BITMAP_NR
959};
960
961static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
962
963#define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
964#define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
965#define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
966#define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
967#define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
968#define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
969#define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
970#define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
971#define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
972#define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
fdef3ad1 973
110312c8 974static bool cpu_has_load_ia32_efer;
8bf00a52 975static bool cpu_has_load_perf_global_ctrl;
110312c8 976
2384d2b3
SY		 977static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
978static DEFINE_SPINLOCK(vmx_vpid_lock);
979
1c3d14fe 980static struct vmcs_config {
6aa8b732
AK		 981 int size;
982 int order;
9ac7e3e8 983 u32 basic_cap;
6aa8b732 984 u32 revision_id;
1c3d14fe
YS		 985 u32 pin_based_exec_ctrl;
986 u32 cpu_based_exec_ctrl;
f78e0e2e 987 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 988 u32 vmexit_ctrl;
989 u32 vmentry_ctrl;
990} vmcs_config;
6aa8b732 991
efff9e53 992static struct vmx_capability {
d56f546d
SY		 993 u32 ept;
994 u32 vpid;
995} vmx_capability;
996
6aa8b732
AK		 997#define VMX_SEGMENT_FIELD(seg) \
998 [VCPU_SREG_##seg] = { \
999 .selector = GUEST_##seg##_SELECTOR, \
1000 .base = GUEST_##seg##_BASE, \
1001 .limit = GUEST_##seg##_LIMIT, \
1002 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1003 }
1004
772e0318 1005static const struct kvm_vmx_segment_field {
6aa8b732
AK		 1006 unsigned selector;
1007 unsigned base;
1008 unsigned limit;
1009 unsigned ar_bytes;
1010} kvm_vmx_segment_fields[] = {
1011 VMX_SEGMENT_FIELD(CS),
1012 VMX_SEGMENT_FIELD(DS),
1013 VMX_SEGMENT_FIELD(ES),
1014 VMX_SEGMENT_FIELD(FS),
1015 VMX_SEGMENT_FIELD(GS),
1016 VMX_SEGMENT_FIELD(SS),
1017 VMX_SEGMENT_FIELD(TR),
1018 VMX_SEGMENT_FIELD(LDTR),
1019};
1020
26bb0981
AK		 1021static u64 host_efer;
1022
6de4f3ad
AK		 1023static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1024
4d56c8a7 1025/*
8c06585d 1026 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 1027 * away by decrementing the array size.
1028 */
6aa8b732 1029static const u32 vmx_msr_index[] = {
05b3e0c2 1030#ifdef CONFIG_X86_64
44ea2b17 1031 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 1032#endif
8c06585d 1033 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 1034};
6aa8b732 1035
5bb16016 1036static inline bool is_exception_n(u32 intr_info, u8 vector)
6aa8b732
AK		 1037{
1038 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1039 INTR_INFO_VALID_MASK)) ==
5bb16016
JK		 1040 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1041}
1042
6f05485d
JK		 1043static inline bool is_debug(u32 intr_info)
1044{
1045 return is_exception_n(intr_info, DB_VECTOR);
1046}
1047
1048static inline bool is_breakpoint(u32 intr_info)
1049{
1050 return is_exception_n(intr_info, BP_VECTOR);
1051}
1052
5bb16016
JK		 1053static inline bool is_page_fault(u32 intr_info)
1054{
1055 return is_exception_n(intr_info, PF_VECTOR);
6aa8b732
AK		 1056}
1057
31299944 1058static inline bool is_no_device(u32 intr_info)
2ab455cc 1059{
5bb16016 1060 return is_exception_n(intr_info, NM_VECTOR);
2ab455cc
AL		 1061}
1062
31299944 1063static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0 1064{
5bb16016 1065 return is_exception_n(intr_info, UD_VECTOR);
7aa81cc0
AL		 1066}
1067
31299944 1068static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 1069{
1070 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1071 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1072}
1073
31299944 1074static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 1075{
1076 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1077 INTR_INFO_VALID_MASK)) ==
1078 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1079}
1080
31299944 1081static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 1082{
04547156 1083 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 1084}
1085
31299944 1086static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 1087{
04547156 1088 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 1089}
1090
35754c98 1091static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 1092{
35754c98 1093 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS		 1094}
1095
31299944 1096static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 1097{
04547156
SY		 1098 return vmcs_config.cpu_based_exec_ctrl &
1099 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 1100}
1101
774ead3a 1102static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 1103{
04547156
SY		 1104 return vmcs_config.cpu_based_2nd_exec_ctrl &
1105 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1106}
1107
8d14695f
YZ		 1108static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1109{
1110 return vmcs_config.cpu_based_2nd_exec_ctrl &
1111 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1112}
1113
83d4c286
YZ		 1114static inline bool cpu_has_vmx_apic_register_virt(void)
1115{
1116 return vmcs_config.cpu_based_2nd_exec_ctrl &
1117 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1118}
1119
c7c9c56c
YZ		 1120static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1121{
1122 return vmcs_config.cpu_based_2nd_exec_ctrl &
1123 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1124}
1125
64672c95
YJ		 1126/*
1127 * Comment's format: document - errata name - stepping - processor name.
1128 * Refer from
1129 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1130 */
1131static u32 vmx_preemption_cpu_tfms[] = {
1132/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
11330x000206E6,
1134/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1135/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
11370x00020652,
1138/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
11390x00020655,
1140/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1141/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1142/*
1143 * 320767.pdf - AAP86 - B1 -
1144 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1145 */
11460x000106E5,
1147/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
11480x000106A0,
1149/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
11500x000106A1,
1151/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
11520x000106A4,
1153 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
11560x000106A5,
1157};
1158
1159static inline bool cpu_has_broken_vmx_preemption_timer(void)
1160{
1161 u32 eax = cpuid_eax(0x00000001), i;
1162
1163 /* Clear the reserved bits */
1164 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 1165 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ		 1166 if (eax == vmx_preemption_cpu_tfms[i])
1167 return true;
1168
1169 return false;
1170}
1171
1172static inline bool cpu_has_vmx_preemption_timer(void)
1173{
64672c95
YJ		 1174 return vmcs_config.pin_based_exec_ctrl &
1175 PIN_BASED_VMX_PREEMPTION_TIMER;
1176}
1177
01e439be
YZ		 1178static inline bool cpu_has_vmx_posted_intr(void)
1179{
d6a858d1
PB		 1180 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1181 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ		 1182}
1183
1184static inline bool cpu_has_vmx_apicv(void)
1185{
1186 return cpu_has_vmx_apic_register_virt() &&
1187 cpu_has_vmx_virtual_intr_delivery() &&
1188 cpu_has_vmx_posted_intr();
1189}
1190
04547156
SY		 1191static inline bool cpu_has_vmx_flexpriority(void)
1192{
1193 return cpu_has_vmx_tpr_shadow() &&
1194 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 1195}
1196
e799794e
MT		 1197static inline bool cpu_has_vmx_ept_execute_only(void)
1198{
31299944 1199 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 1200}
1201
e799794e
MT		 1202static inline bool cpu_has_vmx_ept_2m_page(void)
1203{
31299944 1204 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1205}
1206
878403b7
SY		 1207static inline bool cpu_has_vmx_ept_1g_page(void)
1208{
31299944 1209 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1210}
1211
4bc9b982
SY		 1212static inline bool cpu_has_vmx_ept_4levels(void)
1213{
1214 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1215}
1216
83c3a331
XH		 1217static inline bool cpu_has_vmx_ept_ad_bits(void)
1218{
1219 return vmx_capability.ept & VMX_EPT_AD_BIT;
1220}
1221
31299944 1222static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1223{
31299944 1224 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1225}
1226
31299944 1227static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1228{
31299944 1229 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1230}
1231
518c8aee
GJ		 1232static inline bool cpu_has_vmx_invvpid_single(void)
1233{
1234 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1235}
1236
b9d762fa
GJ		 1237static inline bool cpu_has_vmx_invvpid_global(void)
1238{
1239 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1240}
1241
31299944 1242static inline bool cpu_has_vmx_ept(void)
d56f546d 1243{
04547156
SY		 1244 return vmcs_config.cpu_based_2nd_exec_ctrl &
1245 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1246}
1247
31299944 1248static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1249{
1250 return vmcs_config.cpu_based_2nd_exec_ctrl &
1251 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1252}
1253
31299944 1254static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1255{
1256 return vmcs_config.cpu_based_2nd_exec_ctrl &
1257 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1258}
1259
9ac7e3e8
JD		 1260static inline bool cpu_has_vmx_basic_inout(void)
1261{
1262 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1263}
1264
35754c98 1265static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1266{
35754c98 1267 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 1268}
1269
31299944 1270static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1271{
04547156
SY		 1272 return vmcs_config.cpu_based_2nd_exec_ctrl &
1273 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1274}
1275
31299944 1276static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1277{
1278 return vmcs_config.cpu_based_2nd_exec_ctrl &
1279 SECONDARY_EXEC_RDTSCP;
1280}
1281
ad756a16
MJ		 1282static inline bool cpu_has_vmx_invpcid(void)
1283{
1284 return vmcs_config.cpu_based_2nd_exec_ctrl &
1285 SECONDARY_EXEC_ENABLE_INVPCID;
1286}
1287
31299944 1288static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1289{
1290 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1291}
1292
f5f48ee1
SY		 1293static inline bool cpu_has_vmx_wbinvd_exit(void)
1294{
1295 return vmcs_config.cpu_based_2nd_exec_ctrl &
1296 SECONDARY_EXEC_WBINVD_EXITING;
1297}
1298
abc4fc58
AG		 1299static inline bool cpu_has_vmx_shadow_vmcs(void)
1300{
1301 u64 vmx_msr;
1302 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1303 /* check if the cpu supports writing r/o exit information fields */
1304 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1305 return false;
1306
1307 return vmcs_config.cpu_based_2nd_exec_ctrl &
1308 SECONDARY_EXEC_SHADOW_VMCS;
1309}
1310
843e4330
KH		 1311static inline bool cpu_has_vmx_pml(void)
1312{
1313 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1314}
1315
64903d61
HZ		 1316static inline bool cpu_has_vmx_tsc_scaling(void)
1317{
1318 return vmcs_config.cpu_based_2nd_exec_ctrl &
1319 SECONDARY_EXEC_TSC_SCALING;
1320}
1321
04547156
SY		 1322static inline bool report_flexpriority(void)
1323{
1324 return flexpriority_enabled;
1325}
1326
fe3ef05c
NHE		 1327static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1328{
1329 return vmcs12->cpu_based_vm_exec_control & bit;
1330}
1331
1332static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1333{
1334 return (vmcs12->cpu_based_vm_exec_control &
1335 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1336 (vmcs12->secondary_vm_exec_control & bit);
1337}
1338
f5c4368f 1339static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1340{
1341 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1342}
1343
f4124500
JK		 1344static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1345{
1346 return vmcs12->pin_based_vm_exec_control &
1347 PIN_BASED_VMX_PREEMPTION_TIMER;
1348}
1349
155a97a3
NHE		 1350static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1351{
1352 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1353}
1354
81dc01f7
WL		 1355static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1356{
1357 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1358 vmx_xsaves_supported();
1359}
1360
f2b93280
WV		 1361static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1362{
1363 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1364}
1365
5c614b35
WL		 1366static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1367{
1368 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1369}
1370
82f0dd4b
WV		 1371static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1372{
1373 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1374}
1375
608406e2
WV		 1376static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1377{
1378 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1379}
1380
705699a1
WV		 1381static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1382{
1383 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1384}
1385
ef85b673 1386static inline bool is_nmi(u32 intr_info)
644d711a
NHE		 1387{
1388 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
ef85b673 1389 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
644d711a
NHE		 1390}
1391
533558bc
JK		 1392static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1393 u32 exit_intr_info,
1394 unsigned long exit_qualification);
7c177938
NHE		 1395static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1396 struct vmcs12 *vmcs12,
1397 u32 reason, unsigned long qualification);
1398
8b9cf98c 1399static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1400{
1401 int i;
1402
a2fa3e9f 1403 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1404 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1405 return i;
1406 return -1;
1407}
1408
2384d2b3
SY		 1409static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1410{
1411 struct {
1412 u64 vpid : 16;
1413 u64 rsvd : 48;
1414 u64 gva;
1415 } operand = { vpid, 0, gva };
1416
4ecac3fd 1417 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1418 /* CF==1 or ZF==1 --> rc = -1 */
1419 "; ja 1f ; ud2 ; 1:"
1420 : : "a"(&operand), "c"(ext) : "cc", "memory");
1421}
1422
1439442c
SY		 1423static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1424{
1425 struct {
1426 u64 eptp, gpa;
1427 } operand = {eptp, gpa};
1428
4ecac3fd 1429 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1430 /* CF==1 or ZF==1 --> rc = -1 */
1431 "; ja 1f ; ud2 ; 1:\n"
1432 : : "a" (&operand), "c" (ext) : "cc", "memory");
1433}
1434
26bb0981 1435static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1436{
1437 int i;
1438
8b9cf98c 1439 i = __find_msr_index(vmx, msr);
a75beee6 1440 if (i >= 0)
a2fa3e9f 1441 return &vmx->guest_msrs[i];
8b6d44c7 1442 return NULL;
7725f0ba
AK		 1443}
1444
6aa8b732
AK		 1445static void vmcs_clear(struct vmcs *vmcs)
1446{
1447 u64 phys_addr = __pa(vmcs);
1448 u8 error;
1449
4ecac3fd 1450 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1451 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1452 : "cc", "memory");
1453 if (error)
1454 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1455 vmcs, phys_addr);
1456}
1457
d462b819
NHE		 1458static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1459{
1460 vmcs_clear(loaded_vmcs->vmcs);
355f4fb1
JM		 1461 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1462 vmcs_clear(loaded_vmcs->shadow_vmcs);
d462b819
NHE		 1463 loaded_vmcs->cpu = -1;
1464 loaded_vmcs->launched = 0;
1465}
1466
7725b894
DX		 1467static void vmcs_load(struct vmcs *vmcs)
1468{
1469 u64 phys_addr = __pa(vmcs);
1470 u8 error;
1471
1472 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1473 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1474 : "cc", "memory");
1475 if (error)
2844d849 1476 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1477 vmcs, phys_addr);
1478}
1479
2965faa5 1480#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 1481/*
1482 * This bitmap is used to indicate whether the vmclear
1483 * operation is enabled on all cpus. All disabled by
1484 * default.
1485 */
1486static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1487
1488static inline void crash_enable_local_vmclear(int cpu)
1489{
1490 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1491}
1492
1493static inline void crash_disable_local_vmclear(int cpu)
1494{
1495 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1496}
1497
1498static inline int crash_local_vmclear_enabled(int cpu)
1499{
1500 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1501}
1502
1503static void crash_vmclear_local_loaded_vmcss(void)
1504{
1505 int cpu = raw_smp_processor_id();
1506 struct loaded_vmcs *v;
1507
1508 if (!crash_local_vmclear_enabled(cpu))
1509 return;
1510
1511 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1512 loaded_vmcss_on_cpu_link)
1513 vmcs_clear(v->vmcs);
1514}
1515#else
1516static inline void crash_enable_local_vmclear(int cpu) { }
1517static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1518#endif /* CONFIG_KEXEC_CORE */
8f536b76 1519
d462b819 1520static void __loaded_vmcs_clear(void *arg)
6aa8b732 1521{
d462b819 1522 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1523 int cpu = raw_smp_processor_id();
6aa8b732 1524
d462b819
NHE		 1525 if (loaded_vmcs->cpu != cpu)
1526 return; /* vcpu migration can race with cpu offline */
1527 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1528 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1529 crash_disable_local_vmclear(cpu);
d462b819 1530 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1531
1532 /*
1533 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1534 * is before setting loaded_vmcs->vcpu to -1 which is done in
1535 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1536 * then adds the vmcs into percpu list before it is deleted.
1537 */
1538 smp_wmb();
1539
d462b819 1540 loaded_vmcs_init(loaded_vmcs);
8f536b76 1541 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1542}
1543
d462b819 1544static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1545{
e6c7d321
XG		 1546 int cpu = loaded_vmcs->cpu;
1547
1548 if (cpu != -1)
1549 smp_call_function_single(cpu,
1550 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1551}
1552
dd5f5341 1553static inline void vpid_sync_vcpu_single(int vpid)
2384d2b3 1554{
dd5f5341 1555 if (vpid == 0)
2384d2b3
SY		 1556 return;
1557
518c8aee 1558 if (cpu_has_vmx_invvpid_single())
dd5f5341 1559 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
2384d2b3
SY		 1560}
1561
b9d762fa
GJ		 1562static inline void vpid_sync_vcpu_global(void)
1563{
1564 if (cpu_has_vmx_invvpid_global())
1565 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1566}
1567
dd5f5341 1568static inline void vpid_sync_context(int vpid)
b9d762fa
GJ		 1569{
1570 if (cpu_has_vmx_invvpid_single())
dd5f5341 1571 vpid_sync_vcpu_single(vpid);
b9d762fa
GJ		 1572 else
1573 vpid_sync_vcpu_global();
1574}
1575
1439442c
SY		 1576static inline void ept_sync_global(void)
1577{
1578 if (cpu_has_vmx_invept_global())
1579 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1580}
1581
1582static inline void ept_sync_context(u64 eptp)
1583{
089d034e 1584 if (enable_ept) {
1439442c
SY		 1585 if (cpu_has_vmx_invept_context())
1586 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1587 else
1588 ept_sync_global();
1589 }
1590}
1591
8a86aea9
PB		 1592static __always_inline void vmcs_check16(unsigned long field)
1593{
1594 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1595 "16-bit accessor invalid for 64-bit field");
1596 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1597 "16-bit accessor invalid for 64-bit high field");
1598 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1599 "16-bit accessor invalid for 32-bit high field");
1600 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1601 "16-bit accessor invalid for natural width field");
1602}
1603
1604static __always_inline void vmcs_check32(unsigned long field)
1605{
1606 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1607 "32-bit accessor invalid for 16-bit field");
1608 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1609 "32-bit accessor invalid for natural width field");
1610}
1611
1612static __always_inline void vmcs_check64(unsigned long field)
1613{
1614 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1615 "64-bit accessor invalid for 16-bit field");
1616 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1617 "64-bit accessor invalid for 64-bit high field");
1618 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1619 "64-bit accessor invalid for 32-bit field");
1620 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1621 "64-bit accessor invalid for natural width field");
1622}
1623
1624static __always_inline void vmcs_checkl(unsigned long field)
1625{
1626 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1627 "Natural width accessor invalid for 16-bit field");
1628 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1629 "Natural width accessor invalid for 64-bit field");
1630 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1631 "Natural width accessor invalid for 64-bit high field");
1632 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1633 "Natural width accessor invalid for 32-bit field");
1634}
1635
1636static __always_inline unsigned long __vmcs_readl(unsigned long field)
6aa8b732 1637{
5e520e62 1638 unsigned long value;
6aa8b732 1639
5e520e62
AK		 1640 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1641 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1642 return value;
1643}
1644
96304217 1645static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732 1646{
8a86aea9
PB		 1647 vmcs_check16(field);
1648 return __vmcs_readl(field);
6aa8b732
AK		 1649}
1650
96304217 1651static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732 1652{
8a86aea9
PB		 1653 vmcs_check32(field);
1654 return __vmcs_readl(field);
6aa8b732
AK		 1655}
1656
96304217 1657static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1658{
8a86aea9 1659 vmcs_check64(field);
05b3e0c2 1660#ifdef CONFIG_X86_64
8a86aea9 1661 return __vmcs_readl(field);
6aa8b732 1662#else
8a86aea9 1663 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
6aa8b732
AK		 1664#endif
1665}
1666
8a86aea9
PB		 1667static __always_inline unsigned long vmcs_readl(unsigned long field)
1668{
1669 vmcs_checkl(field);
1670 return __vmcs_readl(field);
1671}
1672
e52de1b8
AK		 1673static noinline void vmwrite_error(unsigned long field, unsigned long value)
1674{
1675 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1676 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1677 dump_stack();
1678}
1679
8a86aea9 1680static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
6aa8b732
AK		 1681{
1682 u8 error;
1683
4ecac3fd 1684 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1685 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1686 if (unlikely(error))
1687 vmwrite_error(field, value);
6aa8b732
AK		 1688}
1689
8a86aea9 1690static __always_inline void vmcs_write16(unsigned long field, u16 value)
6aa8b732 1691{
8a86aea9
PB		 1692 vmcs_check16(field);
1693 __vmcs_writel(field, value);
6aa8b732
AK		 1694}
1695
8a86aea9 1696static __always_inline void vmcs_write32(unsigned long field, u32 value)
6aa8b732 1697{
8a86aea9
PB		 1698 vmcs_check32(field);
1699 __vmcs_writel(field, value);
6aa8b732
AK		 1700}
1701
8a86aea9 1702static __always_inline void vmcs_write64(unsigned long field, u64 value)
6aa8b732 1703{
8a86aea9
PB		 1704 vmcs_check64(field);
1705 __vmcs_writel(field, value);
7682f2d0 1706#ifndef CONFIG_X86_64
6aa8b732 1707 asm volatile ("");
8a86aea9 1708 __vmcs_writel(field+1, value >> 32);
6aa8b732
AK		 1709#endif
1710}
1711
8a86aea9 1712static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2ab455cc 1713{
8a86aea9
PB		 1714 vmcs_checkl(field);
1715 __vmcs_writel(field, value);
2ab455cc
AL		 1716}
1717
8a86aea9 1718static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2ab455cc 1719{
8a86aea9
PB		 1720 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1721 "vmcs_clear_bits does not support 64-bit fields");
1722 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2ab455cc
AL		 1723}
1724
8a86aea9 1725static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2ab455cc 1726{
8a86aea9
PB		 1727 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1728 "vmcs_set_bits does not support 64-bit fields");
1729 __vmcs_writel(field, __vmcs_readl(field) | mask);
2ab455cc
AL		 1730}
1731
8391ce44
PB		 1732static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1733{
1734 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1735}
1736
2961e876
GN		 1737static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1738{
1739 vmcs_write32(VM_ENTRY_CONTROLS, val);
1740 vmx->vm_entry_controls_shadow = val;
1741}
1742
1743static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1744{
1745 if (vmx->vm_entry_controls_shadow != val)
1746 vm_entry_controls_init(vmx, val);
1747}
1748
1749static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1750{
1751 return vmx->vm_entry_controls_shadow;
1752}
1753
1754
1755static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1756{
1757 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1758}
1759
1760static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1761{
1762 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1763}
1764
8391ce44
PB		 1765static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1766{
1767 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1768}
1769
2961e876
GN		 1770static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1771{
1772 vmcs_write32(VM_EXIT_CONTROLS, val);
1773 vmx->vm_exit_controls_shadow = val;
1774}
1775
1776static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1777{
1778 if (vmx->vm_exit_controls_shadow != val)
1779 vm_exit_controls_init(vmx, val);
1780}
1781
1782static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1783{
1784 return vmx->vm_exit_controls_shadow;
1785}
1786
1787
1788static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1789{
1790 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1791}
1792
1793static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1794{
1795 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1796}
1797
2fb92db1
AK		 1798static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1799{
1800 vmx->segment_cache.bitmask = 0;
1801}
1802
1803static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1804 unsigned field)
1805{
1806 bool ret;
1807 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1808
1809 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1810 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1811 vmx->segment_cache.bitmask = 0;
1812 }
1813 ret = vmx->segment_cache.bitmask & mask;
1814 vmx->segment_cache.bitmask |= mask;
1815 return ret;
1816}
1817
1818static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1819{
1820 u16 *p = &vmx->segment_cache.seg[seg].selector;
1821
1822 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1823 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1824 return *p;
1825}
1826
1827static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1828{
1829 ulong *p = &vmx->segment_cache.seg[seg].base;
1830
1831 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1832 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1833 return *p;
1834}
1835
1836static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1837{
1838 u32 *p = &vmx->segment_cache.seg[seg].limit;
1839
1840 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1841 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1842 return *p;
1843}
1844
1845static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1846{
1847 u32 *p = &vmx->segment_cache.seg[seg].ar;
1848
1849 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1850 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1851 return *p;
1852}
1853
abd3f2d6
AK		 1854static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1855{
1856 u32 eb;
1857
fd7373cc 1858 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
54a20552 1859 (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
fd7373cc
JK		 1860 if ((vcpu->guest_debug &
1861 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1862 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1863 eb |= 1u << BP_VECTOR;
7ffd92c5 1864 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1865 eb = ~0;
089d034e 1866 if (enable_ept)
1439442c 1867 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1868 if (vcpu->fpu_active)
1869 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1870
1871 /* When we are running a nested L2 guest and L1 specified for it a
1872 * certain exception bitmap, we must trap the same exceptions and pass
1873 * them to L1. When running L2, we will only handle the exceptions
1874 * specified above if L1 did not want them.
1875 */
1876 if (is_guest_mode(vcpu))
1877 eb |= get_vmcs12(vcpu)->exception_bitmap;
1878
abd3f2d6
AK		 1879 vmcs_write32(EXCEPTION_BITMAP, eb);
1880}
1881
2961e876
GN		 1882static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1883 unsigned long entry, unsigned long exit)
8bf00a52 1884{
2961e876
GN		 1885 vm_entry_controls_clearbit(vmx, entry);
1886 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1887}
1888
61d2ef2c
AK		 1889static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1890{
1891 unsigned i;
1892 struct msr_autoload *m = &vmx->msr_autoload;
1893
8bf00a52
GN		 1894 switch (msr) {
1895 case MSR_EFER:
1896 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1897 clear_atomic_switch_msr_special(vmx,
1898 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1899 VM_EXIT_LOAD_IA32_EFER);
1900 return;
1901 }
1902 break;
1903 case MSR_CORE_PERF_GLOBAL_CTRL:
1904 if (cpu_has_load_perf_global_ctrl) {
2961e876 1905 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1906 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1907 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1908 return;
1909 }
1910 break;
110312c8
AK		 1911 }
1912
61d2ef2c
AK		 1913 for (i = 0; i < m->nr; ++i)
1914 if (m->guest[i].index == msr)
1915 break;
1916
1917 if (i == m->nr)
1918 return;
1919 --m->nr;
1920 m->guest[i] = m->guest[m->nr];
1921 m->host[i] = m->host[m->nr];
1922 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1923 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1924}
1925
2961e876
GN		 1926static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1927 unsigned long entry, unsigned long exit,
1928 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1929 u64 guest_val, u64 host_val)
8bf00a52
GN		 1930{
1931 vmcs_write64(guest_val_vmcs, guest_val);
1932 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1933 vm_entry_controls_setbit(vmx, entry);
1934 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1935}
1936
61d2ef2c
AK		 1937static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1938 u64 guest_val, u64 host_val)
1939{
1940 unsigned i;
1941 struct msr_autoload *m = &vmx->msr_autoload;
1942
8bf00a52
GN		 1943 switch (msr) {
1944 case MSR_EFER:
1945 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1946 add_atomic_switch_msr_special(vmx,
1947 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1948 VM_EXIT_LOAD_IA32_EFER,
1949 GUEST_IA32_EFER,
1950 HOST_IA32_EFER,
1951 guest_val, host_val);
1952 return;
1953 }
1954 break;
1955 case MSR_CORE_PERF_GLOBAL_CTRL:
1956 if (cpu_has_load_perf_global_ctrl) {
2961e876 1957 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1958 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1959 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1960 GUEST_IA32_PERF_GLOBAL_CTRL,
1961 HOST_IA32_PERF_GLOBAL_CTRL,
1962 guest_val, host_val);
1963 return;
1964 }
1965 break;
7099e2e1
RK		 1966 case MSR_IA32_PEBS_ENABLE:
1967 /* PEBS needs a quiescent period after being disabled (to write
1968 * a record). Disabling PEBS through VMX MSR swapping doesn't
1969 * provide that period, so a CPU could write host's record into
1970 * guest's memory.
1971 */
1972 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK		 1973 }
1974
61d2ef2c
AK		 1975 for (i = 0; i < m->nr; ++i)
1976 if (m->guest[i].index == msr)
1977 break;
1978
e7fc6f93 1979 if (i == NR_AUTOLOAD_MSRS) {
60266204 1980 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1981 "Can't add msr %x\n", msr);
1982 return;
1983 } else if (i == m->nr) {
61d2ef2c
AK		 1984 ++m->nr;
1985 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1986 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1987 }
1988
1989 m->guest[i].index = msr;
1990 m->guest[i].value = guest_val;
1991 m->host[i].index = msr;
1992 m->host[i].value = host_val;
1993}
1994
33ed6329
AK		 1995static void reload_tss(void)
1996{
33ed6329
AK		 1997 /*
1998 * VT restores TR but not its size. Useless.
1999 */
89cbc767 2000 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 2001 struct desc_struct *descs;
33ed6329 2002
d359192f 2003 descs = (void *)gdt->address;
33ed6329
AK		 2004 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
2005 load_TR_desc();
33ed6329
AK		 2006}
2007
92c0d900 2008static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 2009{
844a5fe2
PB		 2010 u64 guest_efer = vmx->vcpu.arch.efer;
2011 u64 ignore_bits = 0;
2012
2013 if (!enable_ept) {
2014 /*
2015 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2016 * host CPUID is more efficient than testing guest CPUID
2017 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2018 */
2019 if (boot_cpu_has(X86_FEATURE_SMEP))
2020 guest_efer |= EFER_NX;
2021 else if (!(guest_efer & EFER_NX))
2022 ignore_bits |= EFER_NX;
2023 }
3a34a881 2024
51c6cf66 2025 /*
844a5fe2 2026 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 2027 */
844a5fe2 2028 ignore_bits |= EFER_SCE;
51c6cf66
AK		 2029#ifdef CONFIG_X86_64
2030 ignore_bits |= EFER_LMA | EFER_LME;
2031 /* SCE is meaningful only in long mode on Intel */
2032 if (guest_efer & EFER_LMA)
2033 ignore_bits &= ~(u64)EFER_SCE;
2034#endif
84ad33ef
AK		 2035
2036 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 2037
2038 /*
2039 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2040 * On CPUs that support "load IA32_EFER", always switch EFER
2041 * atomically, since it's faster than switching it manually.
2042 */
2043 if (cpu_has_load_ia32_efer ||
2044 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 2045 if (!(guest_efer & EFER_LMA))
2046 guest_efer &= ~EFER_LME;
54b98bff
AL		 2047 if (guest_efer != host_efer)
2048 add_atomic_switch_msr(vmx, MSR_EFER,
2049 guest_efer, host_efer);
84ad33ef 2050 return false;
844a5fe2
PB		 2051 } else {
2052 guest_efer &= ~ignore_bits;
2053 guest_efer |= host_efer & ignore_bits;
2054
2055 vmx->guest_msrs[efer_offset].data = guest_efer;
2056 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 2057
844a5fe2
PB		 2058 return true;
2059 }
51c6cf66
AK		 2060}
2061
2d49ec72
GN		 2062static unsigned long segment_base(u16 selector)
2063{
89cbc767 2064 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 2065 struct desc_struct *d;
2066 unsigned long table_base;
2067 unsigned long v;
2068
2069 if (!(selector & ~3))
2070 return 0;
2071
d359192f 2072 table_base = gdt->address;
2d49ec72
GN		 2073
2074 if (selector & 4) { /* from ldt */
2075 u16 ldt_selector = kvm_read_ldt();
2076
2077 if (!(ldt_selector & ~3))
2078 return 0;
2079
2080 table_base = segment_base(ldt_selector);
2081 }
2082 d = (struct desc_struct *)(table_base + (selector & ~7));
2083 v = get_desc_base(d);
2084#ifdef CONFIG_X86_64
2085 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2086 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2087#endif
2088 return v;
2089}
2090
2091static inline unsigned long kvm_read_tr_base(void)
2092{
2093 u16 tr;
2094 asm("str %0" : "=g"(tr));
2095 return segment_base(tr);
2096}
2097
04d2cc77 2098static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 2099{
04d2cc77 2100 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2101 int i;
04d2cc77 2102
a2fa3e9f 2103 if (vmx->host_state.loaded)
33ed6329
AK		 2104 return;
2105
a2fa3e9f 2106 vmx->host_state.loaded = 1;
33ed6329
AK		 2107 /*
2108 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2109 * allow segment selectors with cpl > 0 or ti == 1.
2110 */
d6e88aec 2111 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 2112 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 2113 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 2114 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 2115 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 2116 vmx->host_state.fs_reload_needed = 0;
2117 } else {
33ed6329 2118 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 2119 vmx->host_state.fs_reload_needed = 1;
33ed6329 2120 }
9581d442 2121 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 2122 if (!(vmx->host_state.gs_sel & 7))
2123 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 2124 else {
2125 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 2126 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 2127 }
2128
b2da15ac
AK		 2129#ifdef CONFIG_X86_64
2130 savesegment(ds, vmx->host_state.ds_sel);
2131 savesegment(es, vmx->host_state.es_sel);
2132#endif
2133
33ed6329
AK		 2134#ifdef CONFIG_X86_64
2135 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2136 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2137#else
a2fa3e9f
GH		 2138 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2139 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 2140#endif
707c0874
AK		 2141
2142#ifdef CONFIG_X86_64
c8770e7b
AK		 2143 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2144 if (is_long_mode(&vmx->vcpu))
44ea2b17 2145 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 2146#endif
da8999d3
LJ		 2147 if (boot_cpu_has(X86_FEATURE_MPX))
2148 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 2149 for (i = 0; i < vmx->save_nmsrs; ++i)
2150 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 2151 vmx->guest_msrs[i].data,
2152 vmx->guest_msrs[i].mask);
33ed6329
AK		 2153}
2154
a9b21b62 2155static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 2156{
a2fa3e9f 2157 if (!vmx->host_state.loaded)
33ed6329
AK		 2158 return;
2159
e1beb1d3 2160 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 2161 vmx->host_state.loaded = 0;
c8770e7b
AK		 2162#ifdef CONFIG_X86_64
2163 if (is_long_mode(&vmx->vcpu))
2164 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2165#endif
152d3f2f 2166 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 2167 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 2168#ifdef CONFIG_X86_64
9581d442 2169 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 2170#else
2171 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 2172#endif
33ed6329 2173 }
0a77fe4c
AK		 2174 if (vmx->host_state.fs_reload_needed)
2175 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 2176#ifdef CONFIG_X86_64
2177 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2178 loadsegment(ds, vmx->host_state.ds_sel);
2179 loadsegment(es, vmx->host_state.es_sel);
2180 }
b2da15ac 2181#endif
152d3f2f 2182 reload_tss();
44ea2b17 2183#ifdef CONFIG_X86_64
c8770e7b 2184 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 2185#endif
da8999d3
LJ		 2186 if (vmx->host_state.msr_host_bndcfgs)
2187 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
89cbc767 2188 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 2189}
2190
a9b21b62
AK		 2191static void vmx_load_host_state(struct vcpu_vmx *vmx)
2192{
2193 preempt_disable();
2194 __vmx_load_host_state(vmx);
2195 preempt_enable();
2196}
2197
28b835d6
FW		 2198static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2199{
2200 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2201 struct pi_desc old, new;
2202 unsigned int dest;
2203
2204 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 2205 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2206 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW		 2207 return;
2208
2209 do {
2210 old.control = new.control = pi_desc->control;
2211
2212 /*
2213 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2214 * are two possible cases:
2215 * 1. After running 'pre_block', context switch
2216 * happened. For this case, 'sn' was set in
2217 * vmx_vcpu_put(), so we need to clear it here.
2218 * 2. After running 'pre_block', we were blocked,
2219 * and woken up by some other guy. For this case,
2220 * we don't need to do anything, 'pi_post_block'
2221 * will do everything for us. However, we cannot
2222 * check whether it is case #1 or case #2 here
2223 * (maybe, not needed), so we also clear sn here,
2224 * I think it is not a big deal.
2225 */
2226 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2227 if (vcpu->cpu != cpu) {
2228 dest = cpu_physical_id(cpu);
2229
2230 if (x2apic_enabled())
2231 new.ndst = dest;
2232 else
2233 new.ndst = (dest << 8) & 0xFF00;
2234 }
2235
2236 /* set 'NV' to 'notification vector' */
2237 new.nv = POSTED_INTR_VECTOR;
2238 }
2239
2240 /* Allow posting non-urgent interrupts */
2241 new.sn = 0;
2242 } while (cmpxchg(&pi_desc->control, old.control,
2243 new.control) != old.control);
2244}
1be0e61c 2245
c95ba92a
PF		 2246static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2247{
2248 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2249 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2250}
2251
6aa8b732
AK		 2252/*
2253 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2254 * vcpu mutex is already taken.
2255 */
15ad7146 2256static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 2257{
a2fa3e9f 2258 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 2259 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
b80c76ec 2260 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 2261
4610c9cc
DX		 2262 if (!vmm_exclusive)
2263 kvm_cpu_vmxon(phys_addr);
b80c76ec 2264 else if (!already_loaded)
d462b819 2265 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 2266
b80c76ec 2267 if (!already_loaded) {
92fe13be 2268 local_irq_disable();
8f536b76 2269 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 2270
2271 /*
2272 * Read loaded_vmcs->cpu should be before fetching
2273 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2274 * See the comments in __loaded_vmcs_clear().
2275 */
2276 smp_rmb();
2277
d462b819
NHE		 2278 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2279 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 2280 crash_enable_local_vmclear(cpu);
92fe13be 2281 local_irq_enable();
b80c76ec
JM		 2282 }
2283
2284 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2285 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2286 vmcs_load(vmx->loaded_vmcs->vmcs);
2287 }
2288
2289 if (!already_loaded) {
2290 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2291 unsigned long sysenter_esp;
2292
2293 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 2294
6aa8b732
AK		 2295 /*
2296 * Linux uses per-cpu TSS and GDT, so set these when switching
2297 * processors.
2298 */
d6e88aec 2299 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 2300 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 2301
2302 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2303 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 2304
d462b819 2305 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 2306 }
28b835d6 2307
2680d6da
OH		 2308 /* Setup TSC multiplier */
2309 if (kvm_has_tsc_control &&
c95ba92a
PF		 2310 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2311 decache_tsc_multiplier(vmx);
2680d6da 2312
28b835d6 2313 vmx_vcpu_pi_load(vcpu, cpu);
1be0e61c 2314 vmx->host_pkru = read_pkru();
28b835d6
FW		 2315}
2316
2317static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2318{
2319 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2320
2321 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 2322 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2323 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW		 2324 return;
2325
2326 /* Set SN when the vCPU is preempted */
2327 if (vcpu->preempted)
2328 pi_set_sn(pi_desc);
6aa8b732
AK		 2329}
2330
2331static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2332{
28b835d6
FW		 2333 vmx_vcpu_pi_put(vcpu);
2334
a9b21b62 2335 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 2336 if (!vmm_exclusive) {
d462b819
NHE		 2337 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2338 vcpu->cpu = -1;
4610c9cc
DX		 2339 kvm_cpu_vmxoff();
2340 }
6aa8b732
AK		 2341}
2342
5fd86fcf
AK		 2343static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2344{
81231c69
AK		 2345 ulong cr0;
2346
5fd86fcf
AK		 2347 if (vcpu->fpu_active)
2348 return;
2349 vcpu->fpu_active = 1;
81231c69
AK		 2350 cr0 = vmcs_readl(GUEST_CR0);
2351 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2352 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2353 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 2354 update_exception_bitmap(vcpu);
edcafe3c 2355 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 2356 if (is_guest_mode(vcpu))
2357 vcpu->arch.cr0_guest_owned_bits &=
2358 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 2359 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 2360}
2361
edcafe3c
AK		 2362static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2363
fe3ef05c
NHE		 2364/*
2365 * Return the cr0 value that a nested guest would read. This is a combination
2366 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2367 * its hypervisor (cr0_read_shadow).
2368 */
2369static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2370{
2371 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2372 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2373}
2374static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2375{
2376 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2377 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2378}
2379
5fd86fcf
AK		 2380static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2381{
36cf24e0
NHE		 2382 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2383 * set this *before* calling this function.
2384 */
edcafe3c 2385 vmx_decache_cr0_guest_bits(vcpu);
81231c69 2386 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 2387 update_exception_bitmap(vcpu);
edcafe3c
AK		 2388 vcpu->arch.cr0_guest_owned_bits = 0;
2389 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 2390 if (is_guest_mode(vcpu)) {
2391 /*
2392 * L1's specified read shadow might not contain the TS bit,
2393 * so now that we turned on shadowing of this bit, we need to
2394 * set this bit of the shadow. Like in nested_vmx_run we need
2395 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2396 * up-to-date here because we just decached cr0.TS (and we'll
2397 * only update vmcs12->guest_cr0 on nested exit).
2398 */
2399 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2400 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2401 (vcpu->arch.cr0 & X86_CR0_TS);
2402 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2403 } else
2404 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2405}
2406
6aa8b732
AK		 2407static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2408{
78ac8b47 2409 unsigned long rflags, save_rflags;
345dcaa8 2410
6de12732
AK		 2411 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2412 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2413 rflags = vmcs_readl(GUEST_RFLAGS);
2414 if (to_vmx(vcpu)->rmode.vm86_active) {
2415 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2416 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2417 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2418 }
2419 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2420 }
6de12732 2421 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2422}
2423
2424static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2425{
6de12732
AK		 2426 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2427 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2428 if (to_vmx(vcpu)->rmode.vm86_active) {
2429 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2430 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2431 }
6aa8b732
AK		 2432 vmcs_writel(GUEST_RFLAGS, rflags);
2433}
2434
be94f6b7
HH		 2435static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2436{
2437 return to_vmx(vcpu)->guest_pkru;
2438}
2439
37ccdcbe 2440static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2441{
2442 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2443 int ret = 0;
2444
2445 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2446 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2447 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2448 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2449
37ccdcbe 2450 return ret;
2809f5d2
GC		 2451}
2452
2453static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2454{
2455 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2456 u32 interruptibility = interruptibility_old;
2457
2458 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2459
48005f64 2460 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2461 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2462 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2463 interruptibility |= GUEST_INTR_STATE_STI;
2464
2465 if ((interruptibility != interruptibility_old))
2466 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2467}
2468
6aa8b732
AK		 2469static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2470{
2471 unsigned long rip;
6aa8b732 2472
5fdbf976 2473 rip = kvm_rip_read(vcpu);
6aa8b732 2474 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2475 kvm_rip_write(vcpu, rip);
6aa8b732 2476
2809f5d2
GC		 2477 /* skipping an emulated instruction also counts */
2478 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2479}
2480
0b6ac343
NHE		 2481/*
2482 * KVM wants to inject page-faults which it got to the guest. This function
2483 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2484 */
e011c663 2485static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2486{
2487 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2488
e011c663 2489 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2490 return 0;
2491
533558bc
JK		 2492 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2493 vmcs_read32(VM_EXIT_INTR_INFO),
2494 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2495 return 1;
2496}
2497
298101da 2498static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2499 bool has_error_code, u32 error_code,
2500 bool reinject)
298101da 2501{
77ab6db0 2502 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2503 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2504
e011c663
GN		 2505 if (!reinject && is_guest_mode(vcpu) &&
2506 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2507 return;
2508
8ab2d2e2 2509 if (has_error_code) {
77ab6db0 2510 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2511 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2512 }
77ab6db0 2513
7ffd92c5 2514 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2515 int inc_eip = 0;
2516 if (kvm_exception_is_soft(nr))
2517 inc_eip = vcpu->arch.event_exit_inst_len;
2518 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2519 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2520 return;
2521 }
2522
66fd3f7f
GN		 2523 if (kvm_exception_is_soft(nr)) {
2524 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2525 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2526 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2527 } else
2528 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2529
2530 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2531}
2532
4e47c7a6
SY		 2533static bool vmx_rdtscp_supported(void)
2534{
2535 return cpu_has_vmx_rdtscp();
2536}
2537
ad756a16
MJ		 2538static bool vmx_invpcid_supported(void)
2539{
2540 return cpu_has_vmx_invpcid() && enable_ept;
2541}
2542
a75beee6
ED		 2543/*
2544 * Swap MSR entry in host/guest MSR entry array.
2545 */
8b9cf98c 2546static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2547{
26bb0981 2548 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2549
2550 tmp = vmx->guest_msrs[to];
2551 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2552 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2553}
2554
8d14695f
YZ		 2555static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2556{
2557 unsigned long *msr_bitmap;
2558
670125bd 2559 if (is_guest_mode(vcpu))
d048c098 2560 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
3ce424e4
RK		 2561 else if (cpu_has_secondary_exec_ctrls() &&
2562 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2563 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
f6e90f9e
WL		 2564 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2565 if (is_long_mode(vcpu))
c63e4563 2566 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
f6e90f9e 2567 else
c63e4563 2568 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
f6e90f9e
WL		 2569 } else {
2570 if (is_long_mode(vcpu))
c63e4563 2571 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
f6e90f9e 2572 else
c63e4563 2573 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
f6e90f9e 2574 }
8d14695f
YZ		 2575 } else {
2576 if (is_long_mode(vcpu))
2577 msr_bitmap = vmx_msr_bitmap_longmode;
2578 else
2579 msr_bitmap = vmx_msr_bitmap_legacy;
2580 }
2581
2582 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2583}
2584
e38aea3e
AK		 2585/*
2586 * Set up the vmcs to automatically save and restore system
2587 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2588 * mode, as fiddling with msrs is very expensive.
2589 */
8b9cf98c 2590static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2591{
26bb0981 2592 int save_nmsrs, index;
e38aea3e 2593
a75beee6
ED		 2594 save_nmsrs = 0;
2595#ifdef CONFIG_X86_64
8b9cf98c 2596 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2597 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2598 if (index >= 0)
8b9cf98c
RR		 2599 move_msr_up(vmx, index, save_nmsrs++);
2600 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2601 if (index >= 0)
8b9cf98c
RR		 2602 move_msr_up(vmx, index, save_nmsrs++);
2603 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2604 if (index >= 0)
8b9cf98c 2605 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6 2606 index = __find_msr_index(vmx, MSR_TSC_AUX);
1cea0ce6 2607 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
4e47c7a6 2608 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2609 /*
8c06585d 2610 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2611 * if efer.sce is enabled.
2612 */
8c06585d 2613 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2614 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2615 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2616 }
2617#endif
92c0d900
AK		 2618 index = __find_msr_index(vmx, MSR_EFER);
2619 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2620 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2621
26bb0981 2622 vmx->save_nmsrs = save_nmsrs;
5897297b 2623
8d14695f
YZ		 2624 if (cpu_has_vmx_msr_bitmap())
2625 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2626}
2627
6aa8b732
AK		 2628/*
2629 * reads and returns guest's timestamp counter "register"
be7b263e
HZ		 2630 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2631 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
6aa8b732 2632 */
be7b263e 2633static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
6aa8b732
AK		 2634{
2635 u64 host_tsc, tsc_offset;
2636
4ea1636b 2637 host_tsc = rdtsc();
6aa8b732 2638 tsc_offset = vmcs_read64(TSC_OFFSET);
be7b263e 2639 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
6aa8b732
AK		 2640}
2641
2642/*
99e3e30a 2643 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2644 */
99e3e30a 2645static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2646{
27fc51b2 2647 if (is_guest_mode(vcpu)) {
7991825b 2648 /*
27fc51b2
NHE		 2649 * We're here if L1 chose not to trap WRMSR to TSC. According
2650 * to the spec, this should set L1's TSC; The offset that L1
2651 * set for L2 remains unchanged, and still needs to be added
2652 * to the newly set TSC to get L2's TSC.
7991825b 2653 */
27fc51b2 2654 struct vmcs12 *vmcs12;
27fc51b2
NHE		 2655 /* recalculate vmcs02.TSC_OFFSET: */
2656 vmcs12 = get_vmcs12(vcpu);
2657 vmcs_write64(TSC_OFFSET, offset +
2658 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2659 vmcs12->tsc_offset : 0));
2660 } else {
489223ed
YY		 2661 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2662 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2663 vmcs_write64(TSC_OFFSET, offset);
2664 }
6aa8b732
AK		 2665}
2666
801d3424
NHE		 2667static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2668{
2669 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2670 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2671}
2672
2673/*
2674 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2675 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2676 * all guests if the "nested" module option is off, and can also be disabled
2677 * for a single guest by disabling its VMX cpuid bit.
2678 */
2679static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2680{
2681 return nested && guest_cpuid_has_vmx(vcpu);
2682}
2683
b87a51ae
NHE		 2684/*
2685 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2686 * returned for the various VMX controls MSRs when nested VMX is enabled.
2687 * The same values should also be used to verify that vmcs12 control fields are
2688 * valid during nested entry from L1 to L2.
2689 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2690 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2691 * bit in the high half is on if the corresponding bit in the control field
2692 * may be on. See also vmx_control_verify().
b87a51ae 2693 */
b9c237bb 2694static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2695{
2696 /*
2697 * Note that as a general rule, the high half of the MSRs (bits in
2698 * the control fields which may be 1) should be initialized by the
2699 * intersection of the underlying hardware's MSR (i.e., features which
2700 * can be supported) and the list of features we want to expose -
2701 * because they are known to be properly supported in our code.
2702 * Also, usually, the low half of the MSRs (bits which must be 1) can
2703 * be set to 0, meaning that L1 may turn off any of these bits. The
2704 * reason is that if one of these bits is necessary, it will appear
2705 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2706 * fields of vmcs01 and vmcs02, will turn these bits off - and
2707 * nested_vmx_exit_handled() will not pass related exits to L1.
2708 * These rules have exceptions below.
2709 */
2710
2711 /* pin-based controls */
eabeaacc 2712 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2713 vmx->nested.nested_vmx_pinbased_ctls_low,
2714 vmx->nested.nested_vmx_pinbased_ctls_high);
2715 vmx->nested.nested_vmx_pinbased_ctls_low |=
2716 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2717 vmx->nested.nested_vmx_pinbased_ctls_high &=
2718 PIN_BASED_EXT_INTR_MASK |
2719 PIN_BASED_NMI_EXITING |
2720 PIN_BASED_VIRTUAL_NMIS;
2721 vmx->nested.nested_vmx_pinbased_ctls_high |=
2722 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2723 PIN_BASED_VMX_PREEMPTION_TIMER;
d62caabb 2724 if (kvm_vcpu_apicv_active(&vmx->vcpu))
705699a1
WV		 2725 vmx->nested.nested_vmx_pinbased_ctls_high |=
2726 PIN_BASED_POSTED_INTR;
b87a51ae 2727
3dbcd8da 2728 /* exit controls */
c0dfee58 2729 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2730 vmx->nested.nested_vmx_exit_ctls_low,
2731 vmx->nested.nested_vmx_exit_ctls_high);
2732 vmx->nested.nested_vmx_exit_ctls_low =
2733 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2734
b9c237bb 2735 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2736#ifdef CONFIG_X86_64
c0dfee58 2737 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2738#endif
f4124500 2739 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2740 vmx->nested.nested_vmx_exit_ctls_high |=
2741 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2742 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2743 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2744
a87036ad 2745 if (kvm_mpx_supported())
b9c237bb 2746 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2747
2996fca0 2748 /* We support free control of debug control saving. */
0115f9cb 2749 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2996fca0 2750
b87a51ae
NHE		 2751 /* entry controls */
2752 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2753 vmx->nested.nested_vmx_entry_ctls_low,
2754 vmx->nested.nested_vmx_entry_ctls_high);
2755 vmx->nested.nested_vmx_entry_ctls_low =
2756 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2757 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2758#ifdef CONFIG_X86_64
2759 VM_ENTRY_IA32E_MODE |
2760#endif
2761 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2762 vmx->nested.nested_vmx_entry_ctls_high |=
2763 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
a87036ad 2764 if (kvm_mpx_supported())
b9c237bb 2765 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2766
2996fca0 2767 /* We support free control of debug control loading. */
0115f9cb 2768 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2996fca0 2769
b87a51ae
NHE		 2770 /* cpu-based controls */
2771 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2772 vmx->nested.nested_vmx_procbased_ctls_low,
2773 vmx->nested.nested_vmx_procbased_ctls_high);
2774 vmx->nested.nested_vmx_procbased_ctls_low =
2775 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2776 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2777 CPU_BASED_VIRTUAL_INTR_PENDING |
2778 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2779 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2780 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2781 CPU_BASED_CR3_STORE_EXITING |
2782#ifdef CONFIG_X86_64
2783 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2784#endif
2785 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD		 2786 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2787 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2788 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2789 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE		 2790 /*
2791 * We can allow some features even when not supported by the
2792 * hardware. For example, L1 can specify an MSR bitmap - and we
2793 * can use it to avoid exits to L1 - even when L0 runs L2
2794 * without MSR bitmaps.
2795 */
b9c237bb
WV		 2796 vmx->nested.nested_vmx_procbased_ctls_high |=
2797 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2798 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2799
3dcdf3ec 2800 /* We support free control of CR3 access interception. */
0115f9cb 2801 vmx->nested.nested_vmx_procbased_ctls_low &=
3dcdf3ec
JK		 2802 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2803
b87a51ae
NHE		 2804 /* secondary cpu-based controls */
2805 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2806 vmx->nested.nested_vmx_secondary_ctls_low,
2807 vmx->nested.nested_vmx_secondary_ctls_high);
2808 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2809 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2810 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2811 SECONDARY_EXEC_RDTSCP |
1b07304c 2812 SECONDARY_EXEC_DESC |
f2b93280 2813 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
5c614b35 2814 SECONDARY_EXEC_ENABLE_VPID |
82f0dd4b 2815 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2816 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7 2817 SECONDARY_EXEC_WBINVD_EXITING |
dfa169bb 2818 SECONDARY_EXEC_XSAVES;
c18911a2 2819
afa61f75
NHE		 2820 if (enable_ept) {
2821 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2822 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2823 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2824 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2825 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2826 VMX_EPT_INVEPT_BIT;
02120c45
BD		 2827 if (cpu_has_vmx_ept_execute_only())
2828 vmx->nested.nested_vmx_ept_caps |=
2829 VMX_EPT_EXECUTE_ONLY_BIT;
b9c237bb 2830 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
45e11817
BD		 2831 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2832 VMX_EPT_EXTENT_CONTEXT_BIT;
afa61f75 2833 } else
b9c237bb 2834 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2835
ef697a71
PB		 2836 /*
2837 * Old versions of KVM use the single-context version without
2838 * checking for support, so declare that it is supported even
2839 * though it is treated as global context. The alternative is
2840 * not failing the single-context invvpid, and it is worse.
2841 */
089d7b6e
WL		 2842 if (enable_vpid)
2843 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
bcdde302 2844 VMX_VPID_EXTENT_SUPPORTED_MASK;
089d7b6e
WL		 2845 else
2846 vmx->nested.nested_vmx_vpid_caps = 0;
99b83ac8 2847
0790ec17
RK		 2848 if (enable_unrestricted_guest)
2849 vmx->nested.nested_vmx_secondary_ctls_high |=
2850 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2851
c18911a2 2852 /* miscellaneous data */
b9c237bb
WV		 2853 rdmsr(MSR_IA32_VMX_MISC,
2854 vmx->nested.nested_vmx_misc_low,
2855 vmx->nested.nested_vmx_misc_high);
2856 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2857 vmx->nested.nested_vmx_misc_low |=
2858 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2859 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2860 vmx->nested.nested_vmx_misc_high = 0;
62cc6b9d
DM		 2861
2862 /*
2863 * This MSR reports some information about VMX support. We
2864 * should return information about the VMX we emulate for the
2865 * guest, and the VMCS structure we give it - not about the
2866 * VMX support of the underlying hardware.
2867 */
2868 vmx->nested.nested_vmx_basic =
2869 VMCS12_REVISION |
2870 VMX_BASIC_TRUE_CTLS |
2871 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2872 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2873
2874 if (cpu_has_vmx_basic_inout())
2875 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2876
2877 /*
8322ebbb 2878 * These MSRs specify bits which the guest must keep fixed on
62cc6b9d
DM		 2879 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2880 * We picked the standard core2 setting.
2881 */
2882#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2883#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2884 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
62cc6b9d 2885 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
8322ebbb
DM		 2886
2887 /* These MSRs specify bits which the guest must keep fixed off. */
2888 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2889 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
62cc6b9d
DM		 2890
2891 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2892 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
b87a51ae
NHE		 2893}
2894
3899152c
DM		 2895/*
2896 * if fixed0[i] == 1: val[i] must be 1
2897 * if fixed1[i] == 0: val[i] must be 0
2898 */
2899static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2900{
2901 return ((val & fixed1) | fixed0) == val;
b87a51ae
NHE		 2902}
2903
2904static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2905{
3899152c 2906 return fixed_bits_valid(control, low, high);
b87a51ae
NHE		 2907}
2908
2909static inline u64 vmx_control_msr(u32 low, u32 high)
2910{
2911 return low | ((u64)high << 32);
2912}
2913
62cc6b9d
DM		 2914static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2915{
2916 superset &= mask;
2917 subset &= mask;
2918
2919 return (superset | subset) == superset;
2920}
2921
2922static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2923{
2924 const u64 feature_and_reserved =
2925 /* feature (except bit 48; see below) */
2926 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2927 /* reserved */
2928 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2929 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2930
2931 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2932 return -EINVAL;
2933
2934 /*
2935 * KVM does not emulate a version of VMX that constrains physical
2936 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2937 */
2938 if (data & BIT_ULL(48))
2939 return -EINVAL;
2940
2941 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2942 vmx_basic_vmcs_revision_id(data))
2943 return -EINVAL;
2944
2945 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2946 return -EINVAL;
2947
2948 vmx->nested.nested_vmx_basic = data;
2949 return 0;
2950}
2951
2952static int
2953vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2954{
2955 u64 supported;
2956 u32 *lowp, *highp;
2957
2958 switch (msr_index) {
2959 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2960 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2961 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2962 break;
2963 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2964 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2965 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2966 break;
2967 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2968 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2969 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2970 break;
2971 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2972 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2973 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2974 break;
2975 case MSR_IA32_VMX_PROCBASED_CTLS2:
2976 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2977 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2978 break;
2979 default:
2980 BUG();
2981 }
2982
2983 supported = vmx_control_msr(*lowp, *highp);
2984
2985 /* Check must-be-1 bits are still 1. */
2986 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2987 return -EINVAL;
2988
2989 /* Check must-be-0 bits are still 0. */
2990 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2991 return -EINVAL;
2992
2993 *lowp = data;
2994 *highp = data >> 32;
2995 return 0;
2996}
2997
2998static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2999{
3000 const u64 feature_and_reserved_bits =
3001 /* feature */
3002 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3003 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3004 /* reserved */
3005 GENMASK_ULL(13, 9) | BIT_ULL(31);
3006 u64 vmx_misc;
3007
3008 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3009 vmx->nested.nested_vmx_misc_high);
3010
3011 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3012 return -EINVAL;
3013
3014 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3015 PIN_BASED_VMX_PREEMPTION_TIMER) &&
3016 vmx_misc_preemption_timer_rate(data) !=
3017 vmx_misc_preemption_timer_rate(vmx_misc))
3018 return -EINVAL;
3019
3020 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3021 return -EINVAL;
3022
3023 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3024 return -EINVAL;
3025
3026 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3027 return -EINVAL;
3028
3029 vmx->nested.nested_vmx_misc_low = data;
3030 vmx->nested.nested_vmx_misc_high = data >> 32;
3031 return 0;
3032}
3033
3034static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3035{
3036 u64 vmx_ept_vpid_cap;
3037
3038 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3039 vmx->nested.nested_vmx_vpid_caps);
3040
3041 /* Every bit is either reserved or a feature bit. */
3042 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3043 return -EINVAL;
3044
3045 vmx->nested.nested_vmx_ept_caps = data;
3046 vmx->nested.nested_vmx_vpid_caps = data >> 32;
3047 return 0;
3048}
3049
3050static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3051{
3052 u64 *msr;
3053
3054 switch (msr_index) {
3055 case MSR_IA32_VMX_CR0_FIXED0:
3056 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3057 break;
3058 case MSR_IA32_VMX_CR4_FIXED0:
3059 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3060 break;
3061 default:
3062 BUG();
3063 }
3064
3065 /*
3066 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3067 * must be 1 in the restored value.
3068 */
3069 if (!is_bitwise_subset(data, *msr, -1ULL))
3070 return -EINVAL;
3071
3072 *msr = data;
3073 return 0;
3074}
3075
3076/*
3077 * Called when userspace is restoring VMX MSRs.
3078 *
3079 * Returns 0 on success, non-0 otherwise.
3080 */
3081static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
b87a51ae 3082{
b9c237bb
WV		 3083 struct vcpu_vmx *vmx = to_vmx(vcpu);
3084
b87a51ae 3085 switch (msr_index) {
b87a51ae 3086 case MSR_IA32_VMX_BASIC:
62cc6b9d
DM		 3087 return vmx_restore_vmx_basic(vmx, data);
3088 case MSR_IA32_VMX_PINBASED_CTLS:
3089 case MSR_IA32_VMX_PROCBASED_CTLS:
3090 case MSR_IA32_VMX_EXIT_CTLS:
3091 case MSR_IA32_VMX_ENTRY_CTLS:
b87a51ae 3092 /*
62cc6b9d
DM		 3093 * The "non-true" VMX capability MSRs are generated from the
3094 * "true" MSRs, so we do not support restoring them directly.
3095 *
3096 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3097 * should restore the "true" MSRs with the must-be-1 bits
3098 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3099 * DEFAULT SETTINGS".
b87a51ae 3100 */
62cc6b9d
DM		 3101 return -EINVAL;
3102 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3103 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3104 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3105 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3106 case MSR_IA32_VMX_PROCBASED_CTLS2:
3107 return vmx_restore_control_msr(vmx, msr_index, data);
3108 case MSR_IA32_VMX_MISC:
3109 return vmx_restore_vmx_misc(vmx, data);
3110 case MSR_IA32_VMX_CR0_FIXED0:
3111 case MSR_IA32_VMX_CR4_FIXED0:
3112 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3113 case MSR_IA32_VMX_CR0_FIXED1:
3114 case MSR_IA32_VMX_CR4_FIXED1:
3115 /*
3116 * These MSRs are generated based on the vCPU's CPUID, so we
3117 * do not support restoring them directly.
3118 */
3119 return -EINVAL;
3120 case MSR_IA32_VMX_EPT_VPID_CAP:
3121 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3122 case MSR_IA32_VMX_VMCS_ENUM:
3123 vmx->nested.nested_vmx_vmcs_enum = data;
3124 return 0;
3125 default:
b87a51ae 3126 /*
62cc6b9d 3127 * The rest of the VMX capability MSRs do not support restore.
b87a51ae 3128 */
62cc6b9d
DM		 3129 return -EINVAL;
3130 }
3131}
3132
3133/* Returns 0 on success, non-0 otherwise. */
3134static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3135{
3136 struct vcpu_vmx *vmx = to_vmx(vcpu);
3137
3138 switch (msr_index) {
3139 case MSR_IA32_VMX_BASIC:
3140 *pdata = vmx->nested.nested_vmx_basic;
b87a51ae
NHE		 3141 break;
3142 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3143 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 3144 *pdata = vmx_control_msr(
3145 vmx->nested.nested_vmx_pinbased_ctls_low,
3146 vmx->nested.nested_vmx_pinbased_ctls_high);
0115f9cb
DM		 3147 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3148 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 3149 break;
3150 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3151 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 3152 *pdata = vmx_control_msr(
3153 vmx->nested.nested_vmx_procbased_ctls_low,
3154 vmx->nested.nested_vmx_procbased_ctls_high);
0115f9cb
DM		 3155 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3156 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 3157 break;
3158 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3159 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 3160 *pdata = vmx_control_msr(
3161 vmx->nested.nested_vmx_exit_ctls_low,
3162 vmx->nested.nested_vmx_exit_ctls_high);
0115f9cb
DM		 3163 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3164 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 3165 break;
3166 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3167 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 3168 *pdata = vmx_control_msr(
3169 vmx->nested.nested_vmx_entry_ctls_low,
3170 vmx->nested.nested_vmx_entry_ctls_high);
0115f9cb
DM		 3171 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3172 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 3173 break;
3174 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 3175 *pdata = vmx_control_msr(
3176 vmx->nested.nested_vmx_misc_low,
3177 vmx->nested.nested_vmx_misc_high);
b87a51ae 3178 break;
b87a51ae 3179 case MSR_IA32_VMX_CR0_FIXED0:
62cc6b9d 3180 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
b87a51ae
NHE		 3181 break;
3182 case MSR_IA32_VMX_CR0_FIXED1:
62cc6b9d 3183 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
b87a51ae
NHE		 3184 break;
3185 case MSR_IA32_VMX_CR4_FIXED0:
62cc6b9d 3186 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
b87a51ae
NHE		 3187 break;
3188 case MSR_IA32_VMX_CR4_FIXED1:
62cc6b9d 3189 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
b87a51ae
NHE		 3190 break;
3191 case MSR_IA32_VMX_VMCS_ENUM:
62cc6b9d 3192 *pdata = vmx->nested.nested_vmx_vmcs_enum;
b87a51ae
NHE		 3193 break;
3194 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 3195 *pdata = vmx_control_msr(
3196 vmx->nested.nested_vmx_secondary_ctls_low,
3197 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 3198 break;
3199 case MSR_IA32_VMX_EPT_VPID_CAP:
089d7b6e
WL		 3200 *pdata = vmx->nested.nested_vmx_ept_caps |
3201 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
b87a51ae
NHE		 3202 break;
3203 default:
b87a51ae 3204 return 1;
b3897a49
NHE		 3205 }
3206
b87a51ae
NHE		 3207 return 0;
3208}
3209
37e4c997
HZ		 3210static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3211 uint64_t val)
3212{
3213 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3214
3215 return !(val & ~valid_bits);
3216}
3217
6aa8b732
AK		 3218/*
3219 * Reads an msr value (of 'msr_index') into 'pdata'.
3220 * Returns 0 on success, non-0 otherwise.
3221 * Assumes vcpu_load() was already called.
3222 */
609e36d3 3223static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 3224{
26bb0981 3225 struct shared_msr_entry *msr;
6aa8b732 3226
609e36d3 3227 switch (msr_info->index) {
05b3e0c2 3228#ifdef CONFIG_X86_64
6aa8b732 3229 case MSR_FS_BASE:
609e36d3 3230 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK		 3231 break;
3232 case MSR_GS_BASE:
609e36d3 3233 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 3234 break;
44ea2b17
AK		 3235 case MSR_KERNEL_GS_BASE:
3236 vmx_load_host_state(to_vmx(vcpu));
609e36d3 3237 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 3238 break;
26bb0981 3239#endif
6aa8b732 3240 case MSR_EFER:
609e36d3 3241 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 3242 case MSR_IA32_TSC:
be7b263e 3243 msr_info->data = guest_read_tsc(vcpu);
6aa8b732
AK		 3244 break;
3245 case MSR_IA32_SYSENTER_CS:
609e36d3 3246 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 3247 break;
3248 case MSR_IA32_SYSENTER_EIP:
609e36d3 3249 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 3250 break;
3251 case MSR_IA32_SYSENTER_ESP:
609e36d3 3252 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 3253 break;
0dd376e7 3254 case MSR_IA32_BNDCFGS:
a87036ad 3255 if (!kvm_mpx_supported())
93c4adc7 3256 return 1;
609e36d3 3257 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 3258 break;
c45dcc71
AR		 3259 case MSR_IA32_MCG_EXT_CTL:
3260 if (!msr_info->host_initiated &&
3261 !(to_vmx(vcpu)->msr_ia32_feature_control &
3262 FEATURE_CONTROL_LMCE))
cae50139 3263 return 1;
c45dcc71
AR		 3264 msr_info->data = vcpu->arch.mcg_ext_ctl;
3265 break;
cae50139 3266 case MSR_IA32_FEATURE_CONTROL:
3b84080b 3267 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
cae50139
JK		 3268 break;
3269 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3270 if (!nested_vmx_allowed(vcpu))
3271 return 1;
609e36d3 3272 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL		 3273 case MSR_IA32_XSS:
3274 if (!vmx_xsaves_supported())
3275 return 1;
609e36d3 3276 msr_info->data = vcpu->arch.ia32_xss;
20300099 3277 break;
4e47c7a6 3278 case MSR_TSC_AUX:
81b1b9ca 3279 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
4e47c7a6
SY		 3280 return 1;
3281 /* Otherwise falls through */
6aa8b732 3282 default:
609e36d3 3283 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 3284 if (msr) {
609e36d3 3285 msr_info->data = msr->data;
3bab1f5d 3286 break;
6aa8b732 3287 }
609e36d3 3288 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 3289 }
3290
6aa8b732
AK		 3291 return 0;
3292}
3293
cae50139
JK		 3294static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3295
6aa8b732
AK		 3296/*
3297 * Writes msr value into into the appropriate "register".
3298 * Returns 0 on success, non-0 otherwise.
3299 * Assumes vcpu_load() was already called.
3300 */
8fe8ab46 3301static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 3302{
a2fa3e9f 3303 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 3304 struct shared_msr_entry *msr;
2cc51560 3305 int ret = 0;
8fe8ab46
WA		 3306 u32 msr_index = msr_info->index;
3307 u64 data = msr_info->data;
2cc51560 3308
6aa8b732 3309 switch (msr_index) {
3bab1f5d 3310 case MSR_EFER:
8fe8ab46 3311 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 3312 break;
16175a79 3313#ifdef CONFIG_X86_64
6aa8b732 3314 case MSR_FS_BASE:
2fb92db1 3315 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 3316 vmcs_writel(GUEST_FS_BASE, data);
3317 break;
3318 case MSR_GS_BASE:
2fb92db1 3319 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 3320 vmcs_writel(GUEST_GS_BASE, data);
3321 break;
44ea2b17
AK		 3322 case MSR_KERNEL_GS_BASE:
3323 vmx_load_host_state(vmx);
3324 vmx->msr_guest_kernel_gs_base = data;
3325 break;
6aa8b732
AK		 3326#endif
3327 case MSR_IA32_SYSENTER_CS:
3328 vmcs_write32(GUEST_SYSENTER_CS, data);
3329 break;
3330 case MSR_IA32_SYSENTER_EIP:
f5b42c33 3331 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 3332 break;
3333 case MSR_IA32_SYSENTER_ESP:
f5b42c33 3334 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 3335 break;
0dd376e7 3336 case MSR_IA32_BNDCFGS:
a87036ad 3337 if (!kvm_mpx_supported())
93c4adc7 3338 return 1;
0dd376e7
LJ		 3339 vmcs_write64(GUEST_BNDCFGS, data);
3340 break;
af24a4e4 3341 case MSR_IA32_TSC:
8fe8ab46 3342 kvm_write_tsc(vcpu, msr_info);
6aa8b732 3343 break;
468d472f
SY		 3344 case MSR_IA32_CR_PAT:
3345 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 3346 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3347 return 1;
468d472f
SY		 3348 vmcs_write64(GUEST_IA32_PAT, data);
3349 vcpu->arch.pat = data;
3350 break;
3351 }
8fe8ab46 3352 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 3353 break;
ba904635
WA		 3354 case MSR_IA32_TSC_ADJUST:
3355 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 3356 break;
c45dcc71
AR		 3357 case MSR_IA32_MCG_EXT_CTL:
3358 if ((!msr_info->host_initiated &&
3359 !(to_vmx(vcpu)->msr_ia32_feature_control &
3360 FEATURE_CONTROL_LMCE)) ||
3361 (data & ~MCG_EXT_CTL_LMCE_EN))
3362 return 1;
3363 vcpu->arch.mcg_ext_ctl = data;
3364 break;
cae50139 3365 case MSR_IA32_FEATURE_CONTROL:
37e4c997 3366 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 3367 (to_vmx(vcpu)->msr_ia32_feature_control &
cae50139
JK		 3368 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3369 return 1;
3b84080b 3370 vmx->msr_ia32_feature_control = data;
cae50139
JK		 3371 if (msr_info->host_initiated && data == 0)
3372 vmx_leave_nested(vcpu);
3373 break;
3374 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM		 3375 if (!msr_info->host_initiated)
3376 return 1; /* they are read-only */
3377 if (!nested_vmx_allowed(vcpu))
3378 return 1;
3379 return vmx_set_vmx_msr(vcpu, msr_index, data);
20300099
WL		 3380 case MSR_IA32_XSS:
3381 if (!vmx_xsaves_supported())
3382 return 1;
3383 /*
3384 * The only supported bit as of Skylake is bit 8, but
3385 * it is not supported on KVM.
3386 */
3387 if (data != 0)
3388 return 1;
3389 vcpu->arch.ia32_xss = data;
3390 if (vcpu->arch.ia32_xss != host_xss)
3391 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3392 vcpu->arch.ia32_xss, host_xss);
3393 else
3394 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3395 break;
4e47c7a6 3396 case MSR_TSC_AUX:
81b1b9ca 3397 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
4e47c7a6
SY		 3398 return 1;
3399 /* Check reserved bit, higher 32 bits should be zero */
3400 if ((data >> 32) != 0)
3401 return 1;
3402 /* Otherwise falls through */
6aa8b732 3403 default:
8b9cf98c 3404 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 3405 if (msr) {
8b3c3104 3406 u64 old_msr_data = msr->data;
3bab1f5d 3407 msr->data = data;
2225fd56
AK		 3408 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3409 preempt_disable();
8b3c3104
AH		 3410 ret = kvm_set_shared_msr(msr->index, msr->data,
3411 msr->mask);
2225fd56 3412 preempt_enable();
8b3c3104
AH		 3413 if (ret)
3414 msr->data = old_msr_data;
2225fd56 3415 }
3bab1f5d 3416 break;
6aa8b732 3417 }
8fe8ab46 3418 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 3419 }
3420
2cc51560 3421 return ret;
6aa8b732
AK		 3422}
3423
5fdbf976 3424static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 3425{
5fdbf976
MT		 3426 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3427 switch (reg) {
3428 case VCPU_REGS_RSP:
3429 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3430 break;
3431 case VCPU_REGS_RIP:
3432 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3433 break;
6de4f3ad
AK		 3434 case VCPU_EXREG_PDPTR:
3435 if (enable_ept)
3436 ept_save_pdptrs(vcpu);
3437 break;
5fdbf976
MT		 3438 default:
3439 break;
3440 }
6aa8b732
AK		 3441}
3442
6aa8b732
AK		 3443static __init int cpu_has_kvm_support(void)
3444{
6210e37b 3445 return cpu_has_vmx();
6aa8b732
AK		 3446}
3447
3448static __init int vmx_disabled_by_bios(void)
3449{
3450 u64 msr;
3451
3452 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 3453 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 3454 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 3455 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3456 && tboot_enabled())
3457 return 1;
23f3e991 3458 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 3459 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 3460 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 3461 && !tboot_enabled()) {
3462 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 3463 "activate TXT before enabling KVM\n");
cafd6659 3464 return 1;
f9335afe 3465 }
23f3e991
JC		 3466 /* launched w/o TXT and VMX disabled */
3467 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3468 && !tboot_enabled())
3469 return 1;
cafd6659
SW		 3470 }
3471
3472 return 0;
6aa8b732
AK		 3473}
3474
7725b894
DX		 3475static void kvm_cpu_vmxon(u64 addr)
3476{
1c5ac21a
AS		 3477 intel_pt_handle_vmx(1);
3478
7725b894
DX		 3479 asm volatile (ASM_VMX_VMXON_RAX
3480 : : "a"(&addr), "m"(addr)
3481 : "memory", "cc");
3482}
3483
13a34e06 3484static int hardware_enable(void)
6aa8b732
AK		 3485{
3486 int cpu = raw_smp_processor_id();
3487 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 3488 u64 old, test_bits;
6aa8b732 3489
1e02ce4c 3490 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 3491 return -EBUSY;
3492
d462b819 3493 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW		 3494 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3495 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY		 3496
3497 /*
3498 * Now we can enable the vmclear operation in kdump
3499 * since the loaded_vmcss_on_cpu list on this cpu
3500 * has been initialized.
3501 *
3502 * Though the cpu is not in VMX operation now, there
3503 * is no problem to enable the vmclear operation
3504 * for the loaded_vmcss_on_cpu list is empty!
3505 */
3506 crash_enable_local_vmclear(cpu);
3507
6aa8b732 3508 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 3509
3510 test_bits = FEATURE_CONTROL_LOCKED;
3511 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3512 if (tboot_enabled())
3513 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3514
3515 if ((old & test_bits) != test_bits) {
6aa8b732 3516 /* enable and lock */
cafd6659
SW		 3517 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3518 }
375074cc 3519 cr4_set_bits(X86_CR4_VMXE);
10474ae8 3520
4610c9cc
DX		 3521 if (vmm_exclusive) {
3522 kvm_cpu_vmxon(phys_addr);
3523 ept_sync_global();
3524 }
10474ae8 3525
89cbc767 3526 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 3527
10474ae8 3528 return 0;
6aa8b732
AK		 3529}
3530
d462b819 3531static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 3532{
3533 int cpu = raw_smp_processor_id();
d462b819 3534 struct loaded_vmcs *v, *n;
543e4243 3535
d462b819
NHE		 3536 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3537 loaded_vmcss_on_cpu_link)
3538 __loaded_vmcs_clear(v);
543e4243
AK		 3539}
3540
710ff4a8
EH		 3541
3542/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3543 * tricks.
3544 */
3545static void kvm_cpu_vmxoff(void)
6aa8b732 3546{
4ecac3fd 3547 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1c5ac21a
AS		 3548
3549 intel_pt_handle_vmx(0);
6aa8b732
AK		 3550}
3551
13a34e06 3552static void hardware_disable(void)
710ff4a8 3553{
4610c9cc 3554 if (vmm_exclusive) {
d462b819 3555 vmclear_local_loaded_vmcss();
4610c9cc
DX		 3556 kvm_cpu_vmxoff();
3557 }
375074cc 3558 cr4_clear_bits(X86_CR4_VMXE);
710ff4a8
EH		 3559}
3560
1c3d14fe 3561static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 3562 u32 msr, u32 *result)
1c3d14fe
YS		 3563{
3564 u32 vmx_msr_low, vmx_msr_high;
3565 u32 ctl = ctl_min | ctl_opt;
3566
3567 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3568
3569 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3570 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3571
3572 /* Ensure minimum (required) set of control bits are supported. */
3573 if (ctl_min & ~ctl)
002c7f7c 3574 return -EIO;
1c3d14fe
YS		 3575
3576 *result = ctl;
3577 return 0;
3578}
3579
110312c8
AK		 3580static __init bool allow_1_setting(u32 msr, u32 ctl)
3581{
3582 u32 vmx_msr_low, vmx_msr_high;
3583
3584 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3585 return vmx_msr_high & ctl;
3586}
3587
002c7f7c 3588static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 3589{
3590 u32 vmx_msr_low, vmx_msr_high;
d56f546d 3591 u32 min, opt, min2, opt2;
1c3d14fe
YS		 3592 u32 _pin_based_exec_control = 0;
3593 u32 _cpu_based_exec_control = 0;
f78e0e2e 3594 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 3595 u32 _vmexit_control = 0;
3596 u32 _vmentry_control = 0;
3597
10166744 3598 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 3599#ifdef CONFIG_X86_64
3600 CPU_BASED_CR8_LOAD_EXITING |
3601 CPU_BASED_CR8_STORE_EXITING |
3602#endif
d56f546d
SY		 3603 CPU_BASED_CR3_LOAD_EXITING |
3604 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 3605 CPU_BASED_USE_IO_BITMAPS |
3606 CPU_BASED_MOV_DR_EXITING |
a7052897 3607 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 3608 CPU_BASED_MWAIT_EXITING |
3609 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 3610 CPU_BASED_INVLPG_EXITING |
3611 CPU_BASED_RDPMC_EXITING;
443381a8 3612
f78e0e2e 3613 opt = CPU_BASED_TPR_SHADOW |
25c5f225 3614 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 3615 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 3616 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3617 &_cpu_based_exec_control) < 0)
002c7f7c 3618 return -EIO;
6e5d865c
YS		 3619#ifdef CONFIG_X86_64
3620 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3621 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3622 ~CPU_BASED_CR8_STORE_EXITING;
3623#endif
f78e0e2e 3624 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 3625 min2 = 0;
3626 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3627 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3628 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3629 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3630 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3631 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3632 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3633 SECONDARY_EXEC_RDTSCP |
83d4c286 3634 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3635 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3636 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3637 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 3638 SECONDARY_EXEC_XSAVES |
8b3e34e4 3639 SECONDARY_EXEC_ENABLE_PML |
64903d61 3640 SECONDARY_EXEC_TSC_SCALING;
d56f546d
SY		 3641 if (adjust_vmx_controls(min2, opt2,
3642 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3643 &_cpu_based_2nd_exec_control) < 0)
3644 return -EIO;
3645 }
3646#ifndef CONFIG_X86_64
3647 if (!(_cpu_based_2nd_exec_control &
3648 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3649 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3650#endif
83d4c286
YZ		 3651
3652 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3653 _cpu_based_2nd_exec_control &= ~(
8d14695f 3654 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3655 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3656 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3657
d56f546d 3658 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3659 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3660 enabled */
5fff7d27
GN		 3661 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3662 CPU_BASED_CR3_STORE_EXITING |
3663 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3664 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3665 vmx_capability.ept, vmx_capability.vpid);
3666 }
1c3d14fe 3667
91fa0f8e 3668 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 3669#ifdef CONFIG_X86_64
3670 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3671#endif
a547c6db 3672 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
91fa0f8e 3673 VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3674 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3675 &_vmexit_control) < 0)
002c7f7c 3676 return -EIO;
1c3d14fe 3677
01e439be 3678 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
64672c95
YJ		 3679 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3680 PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 3681 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3682 &_pin_based_exec_control) < 0)
3683 return -EIO;
3684
1c17c3e6
PB		 3685 if (cpu_has_broken_vmx_preemption_timer())
3686 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 3687 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 3688 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ		 3689 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3690
c845f9c6 3691 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3692 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3693 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3694 &_vmentry_control) < 0)
002c7f7c 3695 return -EIO;
6aa8b732 3696
c68876fd 3697 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3698
3699 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3700 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3701 return -EIO;
1c3d14fe
YS		 3702
3703#ifdef CONFIG_X86_64
3704 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3705 if (vmx_msr_high & (1u<<16))
002c7f7c 3706 return -EIO;
1c3d14fe
YS		 3707#endif
3708
3709 /* Require Write-Back (WB) memory type for VMCS accesses. */
3710 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3711 return -EIO;
1c3d14fe 3712
002c7f7c 3713 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 3714 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 3715 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
002c7f7c 3716 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3717
002c7f7c
YS		 3718 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3719 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3720 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3721 vmcs_conf->vmexit_ctrl = _vmexit_control;
3722 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3723
110312c8
AK		 3724 cpu_has_load_ia32_efer =
3725 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3726 VM_ENTRY_LOAD_IA32_EFER)
3727 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3728 VM_EXIT_LOAD_IA32_EFER);
3729
8bf00a52
GN		 3730 cpu_has_load_perf_global_ctrl =
3731 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3732 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3733 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3734 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3735
3736 /*
3737 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
bb3541f1 3738 * but due to errata below it can't be used. Workaround is to use
8bf00a52
GN		 3739 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3740 *
3741 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3742 *
3743 * AAK155 (model 26)
3744 * AAP115 (model 30)
3745 * AAT100 (model 37)
3746 * BC86,AAY89,BD102 (model 44)
3747 * BA97 (model 46)
3748 *
3749 */
3750 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3751 switch (boot_cpu_data.x86_model) {
3752 case 26:
3753 case 30:
3754 case 37:
3755 case 44:
3756 case 46:
3757 cpu_has_load_perf_global_ctrl = false;
3758 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3759 "does not work properly. Using workaround\n");
3760 break;
3761 default:
3762 break;
3763 }
3764 }
3765
782511b0 3766 if (boot_cpu_has(X86_FEATURE_XSAVES))
20300099
WL		 3767 rdmsrl(MSR_IA32_XSS, host_xss);
3768
1c3d14fe 3769 return 0;
c68876fd 3770}
6aa8b732
AK		 3771
3772static struct vmcs *alloc_vmcs_cpu(int cpu)
3773{
3774 int node = cpu_to_node(cpu);
3775 struct page *pages;
3776 struct vmcs *vmcs;
3777
96db800f 3778 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3779 if (!pages)
3780 return NULL;
3781 vmcs = page_address(pages);
1c3d14fe
YS		 3782 memset(vmcs, 0, vmcs_config.size);
3783 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3784 return vmcs;
3785}
3786
3787static struct vmcs *alloc_vmcs(void)
3788{
d3b2c338 3789 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3790}
3791
3792static void free_vmcs(struct vmcs *vmcs)
3793{
1c3d14fe 3794 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3795}
3796
d462b819
NHE		 3797/*
3798 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3799 */
3800static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3801{
3802 if (!loaded_vmcs->vmcs)
3803 return;
3804 loaded_vmcs_clear(loaded_vmcs);
3805 free_vmcs(loaded_vmcs->vmcs);
3806 loaded_vmcs->vmcs = NULL;
355f4fb1 3807 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE		 3808}
3809
39959588 3810static void free_kvm_area(void)
6aa8b732
AK		 3811{
3812 int cpu;
3813
3230bb47 3814 for_each_possible_cpu(cpu) {
6aa8b732 3815 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3816 per_cpu(vmxarea, cpu) = NULL;
3817 }
6aa8b732
AK		 3818}
3819
fe2b201b
BD		 3820static void init_vmcs_shadow_fields(void)
3821{
3822 int i, j;
3823
3824 /* No checks for read only fields yet */
3825
3826 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3827 switch (shadow_read_write_fields[i]) {
3828 case GUEST_BNDCFGS:
a87036ad 3829 if (!kvm_mpx_supported())
fe2b201b
BD		 3830 continue;
3831 break;
3832 default:
3833 break;
3834 }
3835
3836 if (j < i)
3837 shadow_read_write_fields[j] =
3838 shadow_read_write_fields[i];
3839 j++;
3840 }
3841 max_shadow_read_write_fields = j;
3842
3843 /* shadowed fields guest access without vmexit */
3844 for (i = 0; i < max_shadow_read_write_fields; i++) {
3845 clear_bit(shadow_read_write_fields[i],
3846 vmx_vmwrite_bitmap);
3847 clear_bit(shadow_read_write_fields[i],
3848 vmx_vmread_bitmap);
3849 }
3850 for (i = 0; i < max_shadow_read_only_fields; i++)
3851 clear_bit(shadow_read_only_fields[i],
3852 vmx_vmread_bitmap);
3853}
3854
6aa8b732
AK		 3855static __init int alloc_kvm_area(void)
3856{
3857 int cpu;
3858
3230bb47 3859 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3860 struct vmcs *vmcs;
3861
3862 vmcs = alloc_vmcs_cpu(cpu);
3863 if (!vmcs) {
3864 free_kvm_area();
3865 return -ENOMEM;
3866 }
3867
3868 per_cpu(vmxarea, cpu) = vmcs;
3869 }
3870 return 0;
3871}
3872
14168786
GN		 3873static bool emulation_required(struct kvm_vcpu *vcpu)
3874{
3875 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3876}
3877
91b0aa2c 3878static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3879 struct kvm_segment *save)
6aa8b732 3880{
d99e4152
GN		 3881 if (!emulate_invalid_guest_state) {
3882 /*
3883 * CS and SS RPL should be equal during guest entry according
3884 * to VMX spec, but in reality it is not always so. Since vcpu
3885 * is in the middle of the transition from real mode to
3886 * protected mode it is safe to assume that RPL 0 is a good
3887 * default value.
3888 */
3889 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 3890 save->selector &= ~SEGMENT_RPL_MASK;
3891 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3892 save->s = 1;
6aa8b732 3893 }
d99e4152 3894 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3895}
3896
3897static void enter_pmode(struct kvm_vcpu *vcpu)
3898{
3899 unsigned long flags;
a89a8fb9 3900 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3901
d99e4152
GN		 3902 /*
3903 * Update real mode segment cache. It may be not up-to-date if sement
3904 * register was written while vcpu was in a guest mode.
3905 */
3906 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3907 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3908 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3909 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3910 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3911 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3912
7ffd92c5 3913 vmx->rmode.vm86_active = 0;
6aa8b732 3914
2fb92db1
AK		 3915 vmx_segment_cache_clear(vmx);
3916
f5f7b2fe 3917 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3918
3919 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3920 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3921 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3922 vmcs_writel(GUEST_RFLAGS, flags);
3923
66aee91a
RR		 3924 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3925 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3926
3927 update_exception_bitmap(vcpu);
3928
91b0aa2c
GN		 3929 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3930 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3931 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3932 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3933 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3934 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3935}
3936
f5f7b2fe 3937static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3938{
772e0318 3939 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3940 struct kvm_segment var = *save;
3941
3942 var.dpl = 0x3;
3943 if (seg == VCPU_SREG_CS)
3944 var.type = 0x3;
3945
3946 if (!emulate_invalid_guest_state) {
3947 var.selector = var.base >> 4;
3948 var.base = var.base & 0xffff0;
3949 var.limit = 0xffff;
3950 var.g = 0;
3951 var.db = 0;
3952 var.present = 1;
3953 var.s = 1;
3954 var.l = 0;
3955 var.unusable = 0;
3956 var.type = 0x3;
3957 var.avl = 0;
3958 if (save->base & 0xf)
3959 printk_once(KERN_WARNING "kvm: segment base is not "
3960 "paragraph aligned when entering "
3961 "protected mode (seg=%d)", seg);
3962 }
6aa8b732 3963
d99e4152
GN		 3964 vmcs_write16(sf->selector, var.selector);
3965 vmcs_write32(sf->base, var.base);
3966 vmcs_write32(sf->limit, var.limit);
3967 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3968}
3969
3970static void enter_rmode(struct kvm_vcpu *vcpu)
3971{
3972 unsigned long flags;
a89a8fb9 3973 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3974
f5f7b2fe
AK		 3975 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3976 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3977 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3978 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3979 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3980 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3981 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3982
7ffd92c5 3983 vmx->rmode.vm86_active = 1;
6aa8b732 3984
776e58ea
GN		 3985 /*
3986 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3987 * vcpu. Warn the user that an update is overdue.
776e58ea 3988 */
4918c6ca 3989 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3990 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3991 "called before entering vcpu\n");
776e58ea 3992
2fb92db1
AK		 3993 vmx_segment_cache_clear(vmx);
3994
4918c6ca 3995 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3996 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3997 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3998
3999 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 4000 vmx->rmode.save_rflags = flags;
6aa8b732 4001
053de044 4002 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 4003
4004 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 4005 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 4006 update_exception_bitmap(vcpu);
4007
d99e4152
GN		 4008 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4009 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4010 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4011 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4012 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4013 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 4014
8668a3c4 4015 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 4016}
4017
401d10de
AS		 4018static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4019{
4020 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 4021 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4022
4023 if (!msr)
4024 return;
401d10de 4025
44ea2b17
AK		 4026 /*
4027 * Force kernel_gs_base reloading before EFER changes, as control
4028 * of this msr depends on is_long_mode().
4029 */
4030 vmx_load_host_state(to_vmx(vcpu));
f6801dff 4031 vcpu->arch.efer = efer;
401d10de 4032 if (efer & EFER_LMA) {
2961e876 4033 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 4034 msr->data = efer;
4035 } else {
2961e876 4036 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 4037
4038 msr->data = efer & ~EFER_LME;
4039 }
4040 setup_msrs(vmx);
4041}
4042
05b3e0c2 4043#ifdef CONFIG_X86_64
6aa8b732
AK		 4044
4045static void enter_lmode(struct kvm_vcpu *vcpu)
4046{
4047 u32 guest_tr_ar;
4048
2fb92db1
AK		 4049 vmx_segment_cache_clear(to_vmx(vcpu));
4050
6aa8b732 4051 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 4052 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 4053 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4054 __func__);
6aa8b732 4055 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 4056 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4057 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 4058 }
da38f438 4059 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 4060}
4061
4062static void exit_lmode(struct kvm_vcpu *vcpu)
4063{
2961e876 4064 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 4065 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 4066}
4067
4068#endif
4069
dd5f5341 4070static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
2384d2b3 4071{
dd5f5341 4072 vpid_sync_context(vpid);
dd180b3e
XG		 4073 if (enable_ept) {
4074 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4075 return;
4e1096d2 4076 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 4077 }
2384d2b3
SY		 4078}
4079
dd5f5341
WL		 4080static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4081{
4082 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4083}
4084
e8467fda
AK		 4085static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4086{
4087 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4088
4089 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4090 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4091}
4092
aff48baa
AK		 4093static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4094{
4095 if (enable_ept && is_paging(vcpu))
4096 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4097 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4098}
4099
25c4c276 4100static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 4101{
fc78f519
AK		 4102 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4103
4104 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4105 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 4106}
4107
1439442c
SY		 4108static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4109{
d0d538b9
GN		 4110 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4111
6de4f3ad
AK		 4112 if (!test_bit(VCPU_EXREG_PDPTR,
4113 (unsigned long *)&vcpu->arch.regs_dirty))
4114 return;
4115
1439442c 4116 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 4117 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4118 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4119 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4120 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 4121 }
4122}
4123
8f5d549f
AK		 4124static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4125{
d0d538b9
GN		 4126 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4127
8f5d549f 4128 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 4129 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4130 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4131 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4132 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 4133 }
6de4f3ad
AK		 4134
4135 __set_bit(VCPU_EXREG_PDPTR,
4136 (unsigned long *)&vcpu->arch.regs_avail);
4137 __set_bit(VCPU_EXREG_PDPTR,
4138 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 4139}
4140
3899152c
DM		 4141static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4142{
4143 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4144 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4145 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4146
4147 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4148 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4149 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4150 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4151
4152 return fixed_bits_valid(val, fixed0, fixed1);
4153}
4154
4155static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4156{
4157 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4158 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4159
4160 return fixed_bits_valid(val, fixed0, fixed1);
4161}
4162
4163static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4164{
4165 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4166 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4167
4168 return fixed_bits_valid(val, fixed0, fixed1);
4169}
4170
4171/* No difference in the restrictions on guest and host CR4 in VMX operation. */
4172#define nested_guest_cr4_valid nested_cr4_valid
4173#define nested_host_cr4_valid nested_cr4_valid
4174
5e1746d6 4175static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 4176
4177static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4178 unsigned long cr0,
4179 struct kvm_vcpu *vcpu)
4180{
5233dd51
MT		 4181 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4182 vmx_decache_cr3(vcpu);
1439442c
SY		 4183 if (!(cr0 & X86_CR0_PG)) {
4184 /* From paging/starting to nonpaging */
4185 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 4186 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 4187 (CPU_BASED_CR3_LOAD_EXITING |
4188 CPU_BASED_CR3_STORE_EXITING));
4189 vcpu->arch.cr0 = cr0;
fc78f519 4190 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 4191 } else if (!is_paging(vcpu)) {
4192 /* From nonpaging to paging */
4193 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 4194 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 4195 ~(CPU_BASED_CR3_LOAD_EXITING |
4196 CPU_BASED_CR3_STORE_EXITING));
4197 vcpu->arch.cr0 = cr0;
fc78f519 4198 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 4199 }
95eb84a7
SY		 4200
4201 if (!(cr0 & X86_CR0_WP))
4202 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 4203}
4204
6aa8b732
AK		 4205static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4206{
7ffd92c5 4207 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 4208 unsigned long hw_cr0;
4209
5037878e 4210 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 4211 if (enable_unrestricted_guest)
5037878e 4212 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 4213 else {
5037878e 4214 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 4215
218e763f
GN		 4216 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4217 enter_pmode(vcpu);
6aa8b732 4218
218e763f
GN		 4219 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4220 enter_rmode(vcpu);
4221 }
6aa8b732 4222
05b3e0c2 4223#ifdef CONFIG_X86_64
f6801dff 4224 if (vcpu->arch.efer & EFER_LME) {
707d92fa 4225 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 4226 enter_lmode(vcpu);
707d92fa 4227 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 4228 exit_lmode(vcpu);
4229 }
4230#endif
4231
089d034e 4232 if (enable_ept)
1439442c
SY		 4233 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4234
02daab21 4235 if (!vcpu->fpu_active)
81231c69 4236 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 4237
6aa8b732 4238 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 4239 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 4240 vcpu->arch.cr0 = cr0;
14168786
GN		 4241
4242 /* depends on vcpu->arch.cr0 to be set to a new value */
4243 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 4244}
4245
1439442c
SY		 4246static u64 construct_eptp(unsigned long root_hpa)
4247{
4248 u64 eptp;
4249
4250 /* TODO write the value reading from MSR */
4251 eptp = VMX_EPT_DEFAULT_MT |
4252 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 4253 if (enable_ept_ad_bits)
4254 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 4255 eptp |= (root_hpa & PAGE_MASK);
4256
4257 return eptp;
4258}
4259
6aa8b732
AK		 4260static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4261{
1439442c
SY		 4262 unsigned long guest_cr3;
4263 u64 eptp;
4264
4265 guest_cr3 = cr3;
089d034e 4266 if (enable_ept) {
1439442c
SY		 4267 eptp = construct_eptp(cr3);
4268 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 4269 if (is_paging(vcpu) || is_guest_mode(vcpu))
4270 guest_cr3 = kvm_read_cr3(vcpu);
4271 else
4272 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 4273 ept_load_pdptrs(vcpu);
1439442c
SY		 4274 }
4275
2384d2b3 4276 vmx_flush_tlb(vcpu);
1439442c 4277 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 4278}
4279
5e1746d6 4280static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 4281{
085e68ee
BS		 4282 /*
4283 * Pass through host's Machine Check Enable value to hw_cr4, which
4284 * is in force while we are in guest mode. Do not let guests control
4285 * this bit, even if host CR4.MCE == 0.
4286 */
4287 unsigned long hw_cr4 =
4288 (cr4_read_shadow() & X86_CR4_MCE) |
4289 (cr4 & ~X86_CR4_MCE) |
4290 (to_vmx(vcpu)->rmode.vm86_active ?
4291 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 4292
5e1746d6
NHE		 4293 if (cr4 & X86_CR4_VMXE) {
4294 /*
4295 * To use VMXON (and later other VMX instructions), a guest
4296 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4297 * So basically the check on whether to allow nested VMX
4298 * is here.
4299 */
4300 if (!nested_vmx_allowed(vcpu))
4301 return 1;
1a0d74e6 4302 }
3899152c
DM		 4303
4304 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE		 4305 return 1;
4306
ad312c7c 4307 vcpu->arch.cr4 = cr4;
bc23008b
AK		 4308 if (enable_ept) {
4309 if (!is_paging(vcpu)) {
4310 hw_cr4 &= ~X86_CR4_PAE;
4311 hw_cr4 |= X86_CR4_PSE;
4312 } else if (!(cr4 & X86_CR4_PAE)) {
4313 hw_cr4 &= ~X86_CR4_PAE;
4314 }
4315 }
1439442c 4316
656ec4a4
RK		 4317 if (!enable_unrestricted_guest && !is_paging(vcpu))
4318 /*
ddba2628
HH		 4319 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4320 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4321 * to be manually disabled when guest switches to non-paging
4322 * mode.
4323 *
4324 * If !enable_unrestricted_guest, the CPU is always running
4325 * with CR0.PG=1 and CR4 needs to be modified.
4326 * If enable_unrestricted_guest, the CPU automatically
4327 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 4328 */
ddba2628 4329 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
656ec4a4 4330
1439442c
SY		 4331 vmcs_writel(CR4_READ_SHADOW, cr4);
4332 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 4333 return 0;
6aa8b732
AK		 4334}
4335
6aa8b732
AK		 4336static void vmx_get_segment(struct kvm_vcpu *vcpu,
4337 struct kvm_segment *var, int seg)
4338{
a9179499 4339 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 4340 u32 ar;
4341
c6ad1153 4342 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 4343 *var = vmx->rmode.segs[seg];
a9179499 4344 if (seg == VCPU_SREG_TR
2fb92db1 4345 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 4346 return;
1390a28b
AK		 4347 var->base = vmx_read_guest_seg_base(vmx, seg);
4348 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4349 return;
a9179499 4350 }
2fb92db1
AK		 4351 var->base = vmx_read_guest_seg_base(vmx, seg);
4352 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4353 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4354 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 4355 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 4356 var->type = ar & 15;
4357 var->s = (ar >> 4) & 1;
4358 var->dpl = (ar >> 5) & 3;
03617c18
GN		 4359 /*
4360 * Some userspaces do not preserve unusable property. Since usable
4361 * segment has to be present according to VMX spec we can use present
4362 * property to amend userspace bug by making unusable segment always
4363 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4364 * segment as unusable.
4365 */
4366 var->present = !var->unusable;
6aa8b732
AK		 4367 var->avl = (ar >> 12) & 1;
4368 var->l = (ar >> 13) & 1;
4369 var->db = (ar >> 14) & 1;
4370 var->g = (ar >> 15) & 1;
6aa8b732
AK		 4371}
4372
a9179499
AK		 4373static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4374{
a9179499
AK		 4375 struct kvm_segment s;
4376
4377 if (to_vmx(vcpu)->rmode.vm86_active) {
4378 vmx_get_segment(vcpu, &s, seg);
4379 return s.base;
4380 }
2fb92db1 4381 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 4382}
4383
b09408d0 4384static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 4385{
b09408d0
MT		 4386 struct vcpu_vmx *vmx = to_vmx(vcpu);
4387
ae9fedc7 4388 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 4389 return 0;
ae9fedc7
PB		 4390 else {
4391 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 4392 return VMX_AR_DPL(ar);
69c73028 4393 }
69c73028
AK		 4394}
4395
653e3108 4396static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 4397{
6aa8b732
AK		 4398 u32 ar;
4399
f0495f9b 4400 if (var->unusable || !var->present)
6aa8b732
AK		 4401 ar = 1 << 16;
4402 else {
4403 ar = var->type & 15;
4404 ar |= (var->s & 1) << 4;
4405 ar |= (var->dpl & 3) << 5;
4406 ar |= (var->present & 1) << 7;
4407 ar |= (var->avl & 1) << 12;
4408 ar |= (var->l & 1) << 13;
4409 ar |= (var->db & 1) << 14;
4410 ar |= (var->g & 1) << 15;
4411 }
653e3108
AK		 4412
4413 return ar;
4414}
4415
4416static void vmx_set_segment(struct kvm_vcpu *vcpu,
4417 struct kvm_segment *var, int seg)
4418{
7ffd92c5 4419 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 4420 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 4421
2fb92db1
AK		 4422 vmx_segment_cache_clear(vmx);
4423
1ecd50a9
GN		 4424 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4425 vmx->rmode.segs[seg] = *var;
4426 if (seg == VCPU_SREG_TR)
4427 vmcs_write16(sf->selector, var->selector);
4428 else if (var->s)
4429 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 4430 goto out;
653e3108 4431 }
1ecd50a9 4432
653e3108
AK		 4433 vmcs_writel(sf->base, var->base);
4434 vmcs_write32(sf->limit, var->limit);
4435 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 4436
4437 /*
4438 * Fix the "Accessed" bit in AR field of segment registers for older
4439 * qemu binaries.
4440 * IA32 arch specifies that at the time of processor reset the
4441 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 4442 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 4443 * state vmexit when "unrestricted guest" mode is turned on.
4444 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4445 * tree. Newer qemu binaries with that qemu fix would not need this
4446 * kvm hack.
4447 */
4448 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 4449 var->type |= 0x1; /* Accessed */
3a624e29 4450
f924d66d 4451 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 4452
4453out:
98eb2f8b 4454 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 4455}
4456
6aa8b732
AK		 4457static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4458{
2fb92db1 4459 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 4460
4461 *db = (ar >> 14) & 1;
4462 *l = (ar >> 13) & 1;
4463}
4464
89a27f4d 4465static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4466{
89a27f4d
GN		 4467 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4468 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 4469}
4470
89a27f4d 4471static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4472{
89a27f4d
GN		 4473 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4474 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 4475}
4476
89a27f4d 4477static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4478{
89a27f4d
GN		 4479 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4480 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 4481}
4482
89a27f4d 4483static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4484{
89a27f4d
GN		 4485 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4486 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 4487}
4488
648dfaa7
MG		 4489static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4490{
4491 struct kvm_segment var;
4492 u32 ar;
4493
4494 vmx_get_segment(vcpu, &var, seg);
07f42f5f 4495 var.dpl = 0x3;
0647f4aa
GN		 4496 if (seg == VCPU_SREG_CS)
4497 var.type = 0x3;
648dfaa7
MG		 4498 ar = vmx_segment_access_rights(&var);
4499
4500 if (var.base != (var.selector << 4))
4501 return false;
89efbed0 4502 if (var.limit != 0xffff)
648dfaa7 4503 return false;
07f42f5f 4504 if (ar != 0xf3)
648dfaa7
MG		 4505 return false;
4506
4507 return true;
4508}
4509
4510static bool code_segment_valid(struct kvm_vcpu *vcpu)
4511{
4512 struct kvm_segment cs;
4513 unsigned int cs_rpl;
4514
4515 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 4516 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 4517
1872a3f4
AK		 4518 if (cs.unusable)
4519 return false;
4d283ec9 4520 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 4521 return false;
4522 if (!cs.s)
4523 return false;
4d283ec9 4524 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 4525 if (cs.dpl > cs_rpl)
4526 return false;
1872a3f4 4527 } else {
648dfaa7
MG		 4528 if (cs.dpl != cs_rpl)
4529 return false;
4530 }
4531 if (!cs.present)
4532 return false;
4533
4534 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4535 return true;
4536}
4537
4538static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4539{
4540 struct kvm_segment ss;
4541 unsigned int ss_rpl;
4542
4543 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 4544 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 4545
1872a3f4
AK		 4546 if (ss.unusable)
4547 return true;
4548 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 4549 return false;
4550 if (!ss.s)
4551 return false;
4552 if (ss.dpl != ss_rpl) /* DPL != RPL */
4553 return false;
4554 if (!ss.present)
4555 return false;
4556
4557 return true;
4558}
4559
4560static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4561{
4562 struct kvm_segment var;
4563 unsigned int rpl;
4564
4565 vmx_get_segment(vcpu, &var, seg);
b32a9918 4566 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 4567
1872a3f4
AK		 4568 if (var.unusable)
4569 return true;
648dfaa7
MG		 4570 if (!var.s)
4571 return false;
4572 if (!var.present)
4573 return false;
4d283ec9 4574 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 4575 if (var.dpl < rpl) /* DPL < RPL */
4576 return false;
4577 }
4578
4579 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4580 * rights flags
4581 */
4582 return true;
4583}
4584
4585static bool tr_valid(struct kvm_vcpu *vcpu)
4586{
4587 struct kvm_segment tr;
4588
4589 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4590
1872a3f4
AK		 4591 if (tr.unusable)
4592 return false;
b32a9918 4593 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 4594 return false;
1872a3f4 4595 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 4596 return false;
4597 if (!tr.present)
4598 return false;
4599
4600 return true;
4601}
4602
4603static bool ldtr_valid(struct kvm_vcpu *vcpu)
4604{
4605 struct kvm_segment ldtr;
4606
4607 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4608
1872a3f4
AK		 4609 if (ldtr.unusable)
4610 return true;
b32a9918 4611 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 4612 return false;
4613 if (ldtr.type != 2)
4614 return false;
4615 if (!ldtr.present)
4616 return false;
4617
4618 return true;
4619}
4620
4621static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4622{
4623 struct kvm_segment cs, ss;
4624
4625 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4626 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4627
b32a9918
NA		 4628 return ((cs.selector & SEGMENT_RPL_MASK) ==
4629 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 4630}
4631
4632/*
4633 * Check if guest state is valid. Returns true if valid, false if
4634 * not.
4635 * We assume that registers are always usable
4636 */
4637static bool guest_state_valid(struct kvm_vcpu *vcpu)
4638{
c5e97c80
GN		 4639 if (enable_unrestricted_guest)
4640 return true;
4641
648dfaa7 4642 /* real mode guest state checks */
f13882d8 4643 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 4644 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4645 return false;
4646 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4647 return false;
4648 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4649 return false;
4650 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4651 return false;
4652 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4653 return false;
4654 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4655 return false;
4656 } else {
4657 /* protected mode guest state checks */
4658 if (!cs_ss_rpl_check(vcpu))
4659 return false;
4660 if (!code_segment_valid(vcpu))
4661 return false;
4662 if (!stack_segment_valid(vcpu))
4663 return false;
4664 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4665 return false;
4666 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4667 return false;
4668 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4669 return false;
4670 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4671 return false;
4672 if (!tr_valid(vcpu))
4673 return false;
4674 if (!ldtr_valid(vcpu))
4675 return false;
4676 }
4677 /* TODO:
4678 * - Add checks on RIP
4679 * - Add checks on RFLAGS
4680 */
4681
4682 return true;
4683}
4684
d77c26fc 4685static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4686{
40dcaa9f 4687 gfn_t fn;
195aefde 4688 u16 data = 0;
1f755a82 4689 int idx, r;
6aa8b732 4690
40dcaa9f 4691 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4692 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 4693 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4694 if (r < 0)
10589a46 4695 goto out;
195aefde 4696 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4697 r = kvm_write_guest_page(kvm, fn++, &data,
4698 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4699 if (r < 0)
10589a46 4700 goto out;
195aefde
IE		 4701 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4702 if (r < 0)
10589a46 4703 goto out;
195aefde
IE		 4704 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4705 if (r < 0)
10589a46 4706 goto out;
195aefde 4707 data = ~0;
10589a46
MT		 4708 r = kvm_write_guest_page(kvm, fn, &data,
4709 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4710 sizeof(u8));
10589a46 4711out:
40dcaa9f 4712 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4713 return r;
6aa8b732
AK		 4714}
4715
b7ebfb05
SY		 4716static int init_rmode_identity_map(struct kvm *kvm)
4717{
f51770ed 4718 int i, idx, r = 0;
ba049e93 4719 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY		 4720 u32 tmp;
4721
089d034e 4722 if (!enable_ept)
f51770ed 4723 return 0;
a255d479
TC		 4724
4725 /* Protect kvm->arch.ept_identity_pagetable_done. */
4726 mutex_lock(&kvm->slots_lock);
4727
f51770ed 4728 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4729 goto out2;
a255d479 4730
b927a3ce 4731 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4732
4733 r = alloc_identity_pagetable(kvm);
f51770ed 4734 if (r < 0)
a255d479
TC		 4735 goto out2;
4736
40dcaa9f 4737 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4738 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4739 if (r < 0)
4740 goto out;
4741 /* Set up identity-mapping pagetable for EPT in real mode */
4742 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4743 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4744 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4745 r = kvm_write_guest_page(kvm, identity_map_pfn,
4746 &tmp, i * sizeof(tmp), sizeof(tmp));
4747 if (r < 0)
4748 goto out;
4749 }
4750 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4751
b7ebfb05 4752out:
40dcaa9f 4753 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4754
4755out2:
4756 mutex_unlock(&kvm->slots_lock);
f51770ed 4757 return r;
b7ebfb05
SY		 4758}
4759
6aa8b732
AK		 4760static void seg_setup(int seg)
4761{
772e0318 4762 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4763 unsigned int ar;
6aa8b732
AK		 4764
4765 vmcs_write16(sf->selector, 0);
4766 vmcs_writel(sf->base, 0);
4767 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4768 ar = 0x93;
4769 if (seg == VCPU_SREG_CS)
4770 ar |= 0x08; /* code segment */
3a624e29
NK		 4771
4772 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4773}
4774
f78e0e2e
SY		 4775static int alloc_apic_access_page(struct kvm *kvm)
4776{
4484141a 4777 struct page *page;
f78e0e2e
SY		 4778 int r = 0;
4779
79fac95e 4780 mutex_lock(&kvm->slots_lock);
c24ae0dc 4781 if (kvm->arch.apic_access_page_done)
f78e0e2e 4782 goto out;
1d8007bd
PB		 4783 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4784 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY		 4785 if (r)
4786 goto out;
72dc67a6 4787
73a6d941 4788 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4789 if (is_error_page(page)) {
4790 r = -EFAULT;
4791 goto out;
4792 }
4793
c24ae0dc
TC		 4794 /*
4795 * Do not pin the page in memory, so that memory hot-unplug
4796 * is able to migrate it.
4797 */
4798 put_page(page);
4799 kvm->arch.apic_access_page_done = true;
f78e0e2e 4800out:
79fac95e 4801 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4802 return r;
4803}
4804
b7ebfb05
SY		 4805static int alloc_identity_pagetable(struct kvm *kvm)
4806{
a255d479
TC		 4807 /* Called with kvm->slots_lock held. */
4808
b7ebfb05
SY		 4809 int r = 0;
4810
a255d479
TC		 4811 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4812
1d8007bd
PB		 4813 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4814 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
b7ebfb05 4815
b7ebfb05
SY		 4816 return r;
4817}
4818
991e7a0e 4819static int allocate_vpid(void)
2384d2b3
SY		 4820{
4821 int vpid;
4822
919818ab 4823 if (!enable_vpid)
991e7a0e 4824 return 0;
2384d2b3
SY		 4825 spin_lock(&vmx_vpid_lock);
4826 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 4827 if (vpid < VMX_NR_VPIDS)
2384d2b3 4828 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL		 4829 else
4830 vpid = 0;
2384d2b3 4831 spin_unlock(&vmx_vpid_lock);
991e7a0e 4832 return vpid;
2384d2b3
SY		 4833}
4834
991e7a0e 4835static void free_vpid(int vpid)
cdbecfc3 4836{
991e7a0e 4837 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ		 4838 return;
4839 spin_lock(&vmx_vpid_lock);
991e7a0e 4840 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ		 4841 spin_unlock(&vmx_vpid_lock);
4842}
4843
8d14695f
YZ		 4844#define MSR_TYPE_R 1
4845#define MSR_TYPE_W 2
4846static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4847 u32 msr, int type)
25c5f225 4848{
3e7c73e9 4849 int f = sizeof(unsigned long);
25c5f225
SY		 4850
4851 if (!cpu_has_vmx_msr_bitmap())
4852 return;
4853
4854 /*
4855 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4856 * have the write-low and read-high bitmap offsets the wrong way round.
4857 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4858 */
25c5f225 4859 if (msr <= 0x1fff) {
8d14695f
YZ		 4860 if (type & MSR_TYPE_R)
4861 /* read-low */
4862 __clear_bit(msr, msr_bitmap + 0x000 / f);
4863
4864 if (type & MSR_TYPE_W)
4865 /* write-low */
4866 __clear_bit(msr, msr_bitmap + 0x800 / f);
4867
25c5f225
SY		 4868 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4869 msr &= 0x1fff;
8d14695f
YZ		 4870 if (type & MSR_TYPE_R)
4871 /* read-high */
4872 __clear_bit(msr, msr_bitmap + 0x400 / f);
4873
4874 if (type & MSR_TYPE_W)
4875 /* write-high */
4876 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4877
4878 }
4879}
4880
f2b93280
WV		 4881/*
4882 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4883 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4884 */
4885static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4886 unsigned long *msr_bitmap_nested,
4887 u32 msr, int type)
4888{
4889 int f = sizeof(unsigned long);
4890
4891 if (!cpu_has_vmx_msr_bitmap()) {
4892 WARN_ON(1);
4893 return;
4894 }
4895
4896 /*
4897 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4898 * have the write-low and read-high bitmap offsets the wrong way round.
4899 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4900 */
4901 if (msr <= 0x1fff) {
4902 if (type & MSR_TYPE_R &&
4903 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4904 /* read-low */
4905 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4906
4907 if (type & MSR_TYPE_W &&
4908 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4909 /* write-low */
4910 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4911
4912 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4913 msr &= 0x1fff;
4914 if (type & MSR_TYPE_R &&
4915 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4916 /* read-high */
4917 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4918
4919 if (type & MSR_TYPE_W &&
4920 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4921 /* write-high */
4922 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4923
4924 }
4925}
4926
5897297b
AK		 4927static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4928{
4929 if (!longmode_only)
8d14695f
YZ		 4930 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4931 msr, MSR_TYPE_R | MSR_TYPE_W);
4932 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4933 msr, MSR_TYPE_R | MSR_TYPE_W);
4934}
4935
2e69f865 4936static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
8d14695f 4937{
f6e90f9e 4938 if (apicv_active) {
c63e4563 4939 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
2e69f865 4940 msr, type);
c63e4563 4941 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
2e69f865 4942 msr, type);
f6e90f9e 4943 } else {
f6e90f9e 4944 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
2e69f865 4945 msr, type);
f6e90f9e 4946 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
2e69f865 4947 msr, type);
f6e90f9e 4948 }
5897297b
AK		 4949}
4950
d62caabb 4951static bool vmx_get_enable_apicv(void)
d50ab6c1 4952{
d62caabb 4953 return enable_apicv;
d50ab6c1
PB		 4954}
4955
6342c50a 4956static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
705699a1
WV		 4957{
4958 struct vcpu_vmx *vmx = to_vmx(vcpu);
4959 int max_irr;
4960 void *vapic_page;
4961 u16 status;
4962
4963 if (vmx->nested.pi_desc &&
4964 vmx->nested.pi_pending) {
4965 vmx->nested.pi_pending = false;
4966 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
6342c50a 4967 return;
705699a1
WV		 4968
4969 max_irr = find_last_bit(
4970 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4971
4972 if (max_irr == 256)
6342c50a 4973 return;
705699a1
WV		 4974
4975 vapic_page = kmap(vmx->nested.virtual_apic_page);
705699a1
WV		 4976 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4977 kunmap(vmx->nested.virtual_apic_page);
4978
4979 status = vmcs_read16(GUEST_INTR_STATUS);
4980 if ((u8)max_irr > ((u8)status & 0xff)) {
4981 status &= ~0xff;
4982 status |= (u8)max_irr;
4983 vmcs_write16(GUEST_INTR_STATUS, status);
4984 }
4985 }
705699a1
WV		 4986}
4987
21bc8dc5
RK		 4988static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4989{
4990#ifdef CONFIG_SMP
4991 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6
FW		 4992 struct vcpu_vmx *vmx = to_vmx(vcpu);
4993
4994 /*
4995 * Currently, we don't support urgent interrupt,
4996 * all interrupts are recognized as non-urgent
4997 * interrupt, so we cannot post interrupts when
4998 * 'SN' is set.
4999 *
5000 * If the vcpu is in guest mode, it means it is
5001 * running instead of being scheduled out and
5002 * waiting in the run queue, and that's the only
5003 * case when 'SN' is set currently, warning if
5004 * 'SN' is set.
5005 */
5006 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
5007
21bc8dc5
RK		 5008 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
5009 POSTED_INTR_VECTOR);
5010 return true;
5011 }
5012#endif
5013 return false;
5014}
5015
705699a1
WV		 5016static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5017 int vector)
5018{
5019 struct vcpu_vmx *vmx = to_vmx(vcpu);
5020
5021 if (is_guest_mode(vcpu) &&
5022 vector == vmx->nested.posted_intr_nv) {
5023 /* the PIR and ON have been set by L1. */
21bc8dc5 5024 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV		 5025 /*
5026 * If a posted intr is not recognized by hardware,
5027 * we will accomplish it in the next vmentry.
5028 */
5029 vmx->nested.pi_pending = true;
5030 kvm_make_request(KVM_REQ_EVENT, vcpu);
5031 return 0;
5032 }
5033 return -1;
5034}
a20ed54d
YZ		 5035/*
5036 * Send interrupt to vcpu via posted interrupt way.
5037 * 1. If target vcpu is running(non-root mode), send posted interrupt
5038 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5039 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5040 * interrupt from PIR in next vmentry.
5041 */
5042static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5043{
5044 struct vcpu_vmx *vmx = to_vmx(vcpu);
5045 int r;
5046
705699a1
WV		 5047 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5048 if (!r)
5049 return;
5050
a20ed54d
YZ		 5051 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5052 return;
5053
5054 r = pi_test_and_set_on(&vmx->pi_desc);
5055 kvm_make_request(KVM_REQ_EVENT, vcpu);
21bc8dc5 5056 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ		 5057 kvm_vcpu_kick(vcpu);
5058}
5059
a3a8ff8e
NHE		 5060/*
5061 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5062 * will not change in the lifetime of the guest.
5063 * Note that host-state that does change is set elsewhere. E.g., host-state
5064 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5065 */
a547c6db 5066static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 5067{
5068 u32 low32, high32;
5069 unsigned long tmpl;
5070 struct desc_ptr dt;
04ac88ab 5071 unsigned long cr0, cr4;
a3a8ff8e 5072
04ac88ab
AL		 5073 cr0 = read_cr0();
5074 WARN_ON(cr0 & X86_CR0_TS);
5075 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
a3a8ff8e
NHE		 5076 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
5077
d974baa3 5078 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 5079 cr4 = cr4_read_shadow();
d974baa3
AL		 5080 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5081 vmx->host_state.vmcs_host_cr4 = cr4;
5082
a3a8ff8e 5083 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 5084#ifdef CONFIG_X86_64
5085 /*
5086 * Load null selectors, so we can avoid reloading them in
5087 * __vmx_load_host_state(), in case userspace uses the null selectors
5088 * too (the expected case).
5089 */
5090 vmcs_write16(HOST_DS_SELECTOR, 0);
5091 vmcs_write16(HOST_ES_SELECTOR, 0);
5092#else
a3a8ff8e
NHE		 5093 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5094 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 5095#endif
a3a8ff8e
NHE		 5096 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5097 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5098
5099 native_store_idt(&dt);
5100 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 5101 vmx->host_idt_base = dt.address;
a3a8ff8e 5102
83287ea4 5103 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 5104
5105 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5106 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5107 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5108 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5109
5110 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5111 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5112 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5113 }
5114}
5115
bf8179a0
NHE		 5116static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5117{
5118 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5119 if (enable_ept)
5120 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 5121 if (is_guest_mode(&vmx->vcpu))
5122 vmx->vcpu.arch.cr4_guest_owned_bits &=
5123 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 5124 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5125}
5126
01e439be
YZ		 5127static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5128{
5129 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5130
d62caabb 5131 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 5132 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
64672c95
YJ		 5133 /* Enable the preemption timer dynamically */
5134 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 5135 return pin_based_exec_ctrl;
5136}
5137
d62caabb
AS		 5138static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5139{
5140 struct vcpu_vmx *vmx = to_vmx(vcpu);
5141
5142 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK		 5143 if (cpu_has_secondary_exec_ctrls()) {
5144 if (kvm_vcpu_apicv_active(vcpu))
5145 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5146 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5147 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5148 else
5149 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5150 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5151 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5152 }
5153
5154 if (cpu_has_vmx_msr_bitmap())
5155 vmx_set_msr_bitmap(vcpu);
d62caabb
AS		 5156}
5157
bf8179a0
NHE		 5158static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5159{
5160 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 5161
5162 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5163 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5164
35754c98 5165 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE		 5166 exec_control &= ~CPU_BASED_TPR_SHADOW;
5167#ifdef CONFIG_X86_64
5168 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5169 CPU_BASED_CR8_LOAD_EXITING;
5170#endif
5171 }
5172 if (!enable_ept)
5173 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5174 CPU_BASED_CR3_LOAD_EXITING |
5175 CPU_BASED_INVLPG_EXITING;
5176 return exec_control;
5177}
5178
5179static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5180{
5181 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 5182 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE		 5183 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5184 if (vmx->vpid == 0)
5185 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5186 if (!enable_ept) {
5187 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5188 enable_unrestricted_guest = 0;
ad756a16
MJ		 5189 /* Enable INVPCID for non-ept guests may cause performance regression. */
5190 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 5191 }
5192 if (!enable_unrestricted_guest)
5193 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5194 if (!ple_gap)
5195 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
d62caabb 5196 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
c7c9c56c
YZ		 5197 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5198 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 5199 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 5200 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5201 (handle_vmptrld).
5202 We can NOT enable shadow_vmcs here because we don't have yet
5203 a current VMCS12
5204 */
5205 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH		 5206
5207 if (!enable_pml)
5208 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 5209
bf8179a0
NHE		 5210 return exec_control;
5211}
5212
ce88decf
XG		 5213static void ept_set_mmio_spte_mask(void)
5214{
5215 /*
5216 * EPT Misconfigurations can be generated if the value of bits 2:0
5217 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 5218 */
312b616b 5219 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
ce88decf
XG		 5220}
5221
f53cd63c 5222#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 5223/*
5224 * Sets up the vmcs for emulated real mode.
5225 */
8b9cf98c 5226static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 5227{
2e4ce7f5 5228#ifdef CONFIG_X86_64
6aa8b732 5229 unsigned long a;
2e4ce7f5 5230#endif
6aa8b732 5231 int i;
6aa8b732 5232
6aa8b732 5233 /* I/O */
3e7c73e9
AK		 5234 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5235 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 5236
4607c2d7
AG		 5237 if (enable_shadow_vmcs) {
5238 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5239 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5240 }
25c5f225 5241 if (cpu_has_vmx_msr_bitmap())
5897297b 5242 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 5243
6aa8b732
AK		 5244 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5245
6aa8b732 5246 /* Control */
01e439be 5247 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
64672c95 5248 vmx->hv_deadline_tsc = -1;
6e5d865c 5249
bf8179a0 5250 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 5251
dfa169bb 5252 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 5253 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5254 vmx_secondary_exec_control(vmx));
dfa169bb 5255 }
f78e0e2e 5256
d62caabb 5257 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ		 5258 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5259 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5260 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5261 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5262
5263 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 5264
0bcf261c 5265 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 5266 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 5267 }
5268
4b8d54f9
ZE		 5269 if (ple_gap) {
5270 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 5271 vmx->ple_window = ple_window;
5272 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 5273 }
5274
c3707958
XG		 5275 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5276 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 5277 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5278
9581d442
AK		 5279 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5280 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 5281 vmx_set_constant_host_state(vmx);
05b3e0c2 5282#ifdef CONFIG_X86_64
6aa8b732
AK		 5283 rdmsrl(MSR_FS_BASE, a);
5284 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5285 rdmsrl(MSR_GS_BASE, a);
5286 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5287#else
5288 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5289 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5290#endif
5291
2cc51560
ED		 5292 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5293 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 5294 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 5295 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 5296 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 5297
74545705
RK		 5298 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5299 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 5300
03916db9 5301 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 5302 u32 index = vmx_msr_index[i];
5303 u32 data_low, data_high;
a2fa3e9f 5304 int j = vmx->nmsrs;
6aa8b732
AK		 5305
5306 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5307 continue;
432bd6cb
AK		 5308 if (wrmsr_safe(index, data_low, data_high) < 0)
5309 continue;
26bb0981
AK		 5310 vmx->guest_msrs[j].index = i;
5311 vmx->guest_msrs[j].data = 0;
d5696725 5312 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 5313 ++vmx->nmsrs;
6aa8b732 5314 }
6aa8b732 5315
2961e876
GN		 5316
5317 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 5318
5319 /* 22.2.1, 20.8.1 */
2961e876 5320 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 5321
e00c8cf2 5322 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 5323 set_cr4_guest_host_mask(vmx);
e00c8cf2 5324
f53cd63c
WL		 5325 if (vmx_xsaves_supported())
5326 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5327
4e59516a
PF		 5328 if (enable_pml) {
5329 ASSERT(vmx->pml_pg);
5330 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5331 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5332 }
5333
e00c8cf2
AK		 5334 return 0;
5335}
5336
d28bc9dd 5337static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 5338{
5339 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 5340 struct msr_data apic_base_msr;
d28bc9dd 5341 u64 cr0;
e00c8cf2 5342
7ffd92c5 5343 vmx->rmode.vm86_active = 0;
e00c8cf2 5344
3b86cd99
JK		 5345 vmx->soft_vnmi_blocked = 0;
5346
ad312c7c 5347 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 5348 kvm_set_cr8(vcpu, 0);
5349
5350 if (!init_event) {
5351 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5352 MSR_IA32_APICBASE_ENABLE;
5353 if (kvm_vcpu_is_reset_bsp(vcpu))
5354 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5355 apic_base_msr.host_initiated = true;
5356 kvm_set_apic_base(vcpu, &apic_base_msr);
5357 }
e00c8cf2 5358
2fb92db1
AK		 5359 vmx_segment_cache_clear(vmx);
5360
5706be0d 5361 seg_setup(VCPU_SREG_CS);
66450a21 5362 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 5363 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK		 5364
5365 seg_setup(VCPU_SREG_DS);
5366 seg_setup(VCPU_SREG_ES);
5367 seg_setup(VCPU_SREG_FS);
5368 seg_setup(VCPU_SREG_GS);
5369 seg_setup(VCPU_SREG_SS);
5370
5371 vmcs_write16(GUEST_TR_SELECTOR, 0);
5372 vmcs_writel(GUEST_TR_BASE, 0);
5373 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5374 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5375
5376 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5377 vmcs_writel(GUEST_LDTR_BASE, 0);
5378 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5379 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5380
d28bc9dd
NA		 5381 if (!init_event) {
5382 vmcs_write32(GUEST_SYSENTER_CS, 0);
5383 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5384 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5385 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5386 }
e00c8cf2
AK		 5387
5388 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 5389 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 5390
e00c8cf2
AK		 5391 vmcs_writel(GUEST_GDTR_BASE, 0);
5392 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5393
5394 vmcs_writel(GUEST_IDTR_BASE, 0);
5395 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5396
443381a8 5397 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 5398 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 5399 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
e00c8cf2 5400
e00c8cf2
AK		 5401 setup_msrs(vmx);
5402
6aa8b732
AK		 5403 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5404
d28bc9dd 5405 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 5406 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 5407 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 5408 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 5409 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 5410 vmcs_write32(TPR_THRESHOLD, 0);
5411 }
5412
a73896cb 5413 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 5414
d62caabb 5415 if (kvm_vcpu_apicv_active(vcpu))
01e439be
YZ		 5416 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5417
2384d2b3
SY		 5418 if (vmx->vpid != 0)
5419 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5420
d28bc9dd 5421 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 5422 vmx->vcpu.arch.cr0 = cr0;
f2463247 5423 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 5424 vmx_set_cr4(vcpu, 0);
5690891b 5425 vmx_set_efer(vcpu, 0);
d28bc9dd
NA		 5426 vmx_fpu_activate(vcpu);
5427 update_exception_bitmap(vcpu);
6aa8b732 5428
dd5f5341 5429 vpid_sync_context(vmx->vpid);
6aa8b732
AK		 5430}
5431
b6f1250e
NHE		 5432/*
5433 * In nested virtualization, check if L1 asked to exit on external interrupts.
5434 * For most existing hypervisors, this will always return true.
5435 */
5436static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5437{
5438 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5439 PIN_BASED_EXT_INTR_MASK;
5440}
5441
77b0f5d6
BD		 5442/*
5443 * In nested virtualization, check if L1 has set
5444 * VM_EXIT_ACK_INTR_ON_EXIT
5445 */
5446static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5447{
5448 return get_vmcs12(vcpu)->vm_exit_controls &
5449 VM_EXIT_ACK_INTR_ON_EXIT;
5450}
5451
ea8ceb83
JK		 5452static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5453{
5454 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5455 PIN_BASED_NMI_EXITING;
5456}
5457
c9a7953f 5458static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 5459{
5460 u32 cpu_based_vm_exec_control;
730dca42 5461
3b86cd99
JK		 5462 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5463 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5464 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5465}
5466
c9a7953f 5467static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 5468{
5469 u32 cpu_based_vm_exec_control;
5470
c9a7953f
JK		 5471 if (!cpu_has_virtual_nmis() ||
5472 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5473 enable_irq_window(vcpu);
5474 return;
5475 }
3b86cd99
JK		 5476
5477 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5478 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5479 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5480}
5481
66fd3f7f 5482static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 5483{
9c8cba37 5484 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 5485 uint32_t intr;
5486 int irq = vcpu->arch.interrupt.nr;
9c8cba37 5487
229456fc 5488 trace_kvm_inj_virq(irq);
2714d1d3 5489
fa89a817 5490 ++vcpu->stat.irq_injections;
7ffd92c5 5491 if (vmx->rmode.vm86_active) {
71f9833b
SH		 5492 int inc_eip = 0;
5493 if (vcpu->arch.interrupt.soft)
5494 inc_eip = vcpu->arch.event_exit_inst_len;
5495 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 5496 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 5497 return;
5498 }
66fd3f7f
GN		 5499 intr = irq | INTR_INFO_VALID_MASK;
5500 if (vcpu->arch.interrupt.soft) {
5501 intr |= INTR_TYPE_SOFT_INTR;
5502 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5503 vmx->vcpu.arch.event_exit_inst_len);
5504 } else
5505 intr |= INTR_TYPE_EXT_INTR;
5506 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 5507}
5508
f08864b4
SY		 5509static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5510{
66a5a347
JK		 5511 struct vcpu_vmx *vmx = to_vmx(vcpu);
5512
c5a6d5f7
WL		 5513 if (!is_guest_mode(vcpu)) {
5514 if (!cpu_has_virtual_nmis()) {
5515 /*
5516 * Tracking the NMI-blocked state in software is built upon
5517 * finding the next open IRQ window. This, in turn, depends on
5518 * well-behaving guests: They have to keep IRQs disabled at
5519 * least as long as the NMI handler runs. Otherwise we may
5520 * cause NMI nesting, maybe breaking the guest. But as this is
5521 * highly unlikely, we can live with the residual risk.
5522 */
5523 vmx->soft_vnmi_blocked = 1;
5524 vmx->vnmi_blocked_time = 0;
5525 }
0b6ac343 5526
c5a6d5f7
WL		 5527 ++vcpu->stat.nmi_injections;
5528 vmx->nmi_known_unmasked = false;
3b86cd99
JK		 5529 }
5530
7ffd92c5 5531 if (vmx->rmode.vm86_active) {
71f9833b 5532 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 5533 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 5534 return;
5535 }
c5a6d5f7 5536
f08864b4
SY		 5537 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5538 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 5539}
5540
3cfc3092
JK		 5541static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5542{
5543 if (!cpu_has_virtual_nmis())
5544 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 5545 if (to_vmx(vcpu)->nmi_known_unmasked)
5546 return false;
c332c83a 5547 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 5548}
5549
5550static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5551{
5552 struct vcpu_vmx *vmx = to_vmx(vcpu);
5553
5554 if (!cpu_has_virtual_nmis()) {
5555 if (vmx->soft_vnmi_blocked != masked) {
5556 vmx->soft_vnmi_blocked = masked;
5557 vmx->vnmi_blocked_time = 0;
5558 }
5559 } else {
9d58b931 5560 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 5561 if (masked)
5562 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5563 GUEST_INTR_STATE_NMI);
5564 else
5565 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5566 GUEST_INTR_STATE_NMI);
5567 }
5568}
5569
2505dc9f
JK		 5570static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5571{
b6b8a145
JK		 5572 if (to_vmx(vcpu)->nested.nested_run_pending)
5573 return 0;
ea8ceb83 5574
2505dc9f
JK		 5575 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5576 return 0;
5577
5578 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5579 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5580 | GUEST_INTR_STATE_NMI));
5581}
5582
78646121
GN		 5583static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5584{
b6b8a145
JK		 5585 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5586 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 5587 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5588 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 5589}
5590
cbc94022
IE		 5591static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5592{
5593 int ret;
cbc94022 5594
1d8007bd
PB		 5595 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5596 PAGE_SIZE * 3);
cbc94022
IE		 5597 if (ret)
5598 return ret;
bfc6d222 5599 kvm->arch.tss_addr = addr;
1f755a82 5600 return init_rmode_tss(kvm);
cbc94022
IE		 5601}
5602
0ca1b4f4 5603static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 5604{
77ab6db0 5605 switch (vec) {
77ab6db0 5606 case BP_VECTOR:
c573cd22
JK		 5607 /*
5608 * Update instruction length as we may reinject the exception
5609 * from user space while in guest debugging mode.
5610 */
5611 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5612 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 5613 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 5614 return false;
5615 /* fall through */
5616 case DB_VECTOR:
5617 if (vcpu->guest_debug &
5618 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5619 return false;
d0bfb940
JK		 5620 /* fall through */
5621 case DE_VECTOR:
77ab6db0
JK		 5622 case OF_VECTOR:
5623 case BR_VECTOR:
5624 case UD_VECTOR:
5625 case DF_VECTOR:
5626 case SS_VECTOR:
5627 case GP_VECTOR:
5628 case MF_VECTOR:
0ca1b4f4
GN		 5629 return true;
5630 break;
77ab6db0 5631 }
0ca1b4f4
GN		 5632 return false;
5633}
5634
5635static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5636 int vec, u32 err_code)
5637{
5638 /*
5639 * Instruction with address size override prefix opcode 0x67
5640 * Cause the #SS fault with 0 error code in VM86 mode.
5641 */
5642 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5643 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5644 if (vcpu->arch.halt_request) {
5645 vcpu->arch.halt_request = 0;
5cb56059 5646 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 5647 }
5648 return 1;
5649 }
5650 return 0;
5651 }
5652
5653 /*
5654 * Forward all other exceptions that are valid in real mode.
5655 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5656 * the required debugging infrastructure rework.
5657 */
5658 kvm_queue_exception(vcpu, vec);
5659 return 1;
6aa8b732
AK		 5660}
5661
a0861c02
AK		 5662/*
5663 * Trigger machine check on the host. We assume all the MSRs are already set up
5664 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5665 * We pass a fake environment to the machine check handler because we want
5666 * the guest to be always treated like user space, no matter what context
5667 * it used internally.
5668 */
5669static void kvm_machine_check(void)
5670{
5671#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5672 struct pt_regs regs = {
5673 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5674 .flags = X86_EFLAGS_IF,
5675 };
5676
5677 do_machine_check(&regs, 0);
5678#endif
5679}
5680
851ba692 5681static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 5682{
5683 /* already handled by vcpu_run */
5684 return 1;
5685}
5686
851ba692 5687static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5688{
1155f76a 5689 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5690 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5691 u32 intr_info, ex_no, error_code;
42dbaa5a 5692 unsigned long cr2, rip, dr6;
6aa8b732
AK		 5693 u32 vect_info;
5694 enum emulation_result er;
5695
1155f76a 5696 vect_info = vmx->idt_vectoring_info;
88786475 5697 intr_info = vmx->exit_intr_info;
6aa8b732 5698
a0861c02 5699 if (is_machine_check(intr_info))
851ba692 5700 return handle_machine_check(vcpu);
a0861c02 5701
ef85b673 5702 if (is_nmi(intr_info))
1b6269db 5703 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 5704
5705 if (is_no_device(intr_info)) {
5fd86fcf 5706 vmx_fpu_activate(vcpu);
2ab455cc
AL		 5707 return 1;
5708 }
5709
7aa81cc0 5710 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK		 5711 if (is_guest_mode(vcpu)) {
5712 kvm_queue_exception(vcpu, UD_VECTOR);
5713 return 1;
5714 }
51d8b661 5715 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5716 if (er != EMULATE_DONE)
7ee5d940 5717 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 5718 return 1;
5719 }
5720
6aa8b732 5721 error_code = 0;
2e11384c 5722 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5723 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 5724
5725 /*
5726 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5727 * MMIO, it is better to report an internal error.
5728 * See the comments in vmx_handle_exit.
5729 */
5730 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5731 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5732 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5733 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5734 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 5735 vcpu->run->internal.data[0] = vect_info;
5736 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5737 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 5738 return 0;
5739 }
5740
6aa8b732 5741 if (is_page_fault(intr_info)) {
1439442c 5742 /* EPT won't cause page fault directly */
cf3ace79 5743 BUG_ON(enable_ept);
6aa8b732 5744 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5745 trace_kvm_page_fault(cr2, error_code);
5746
3298b75c 5747 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5748 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5749 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5750 }
5751
d0bfb940 5752 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5753
5754 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5755 return handle_rmode_exception(vcpu, ex_no, error_code);
5756
42dbaa5a 5757 switch (ex_no) {
54a20552
EN		 5758 case AC_VECTOR:
5759 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5760 return 1;
42dbaa5a
JK		 5761 case DB_VECTOR:
5762 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5763 if (!(vcpu->guest_debug &
5764 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5765 vcpu->arch.dr6 &= ~15;
6f43ed01 5766 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5767 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5768 skip_emulated_instruction(vcpu);
5769
42dbaa5a
JK		 5770 kvm_queue_exception(vcpu, DB_VECTOR);
5771 return 1;
5772 }
5773 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5774 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5775 /* fall through */
5776 case BP_VECTOR:
c573cd22
JK		 5777 /*
5778 * Update instruction length as we may reinject #BP from
5779 * user space while in guest debugging mode. Reading it for
5780 * #DB as well causes no harm, it is not used in that case.
5781 */
5782 vmx->vcpu.arch.event_exit_inst_len =
5783 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5784 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5785 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5786 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5787 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5788 break;
5789 default:
d0bfb940
JK		 5790 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5791 kvm_run->ex.exception = ex_no;
5792 kvm_run->ex.error_code = error_code;
42dbaa5a 5793 break;
6aa8b732 5794 }
6aa8b732
AK		 5795 return 0;
5796}
5797
851ba692 5798static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5799{
1165f5fe 5800 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5801 return 1;
5802}
5803
851ba692 5804static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5805{
851ba692 5806 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5807 return 0;
5808}
6aa8b732 5809
851ba692 5810static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5811{
bfdaab09 5812 unsigned long exit_qualification;
6affcbed 5813 int size, in, string, ret;
039576c0 5814 unsigned port;
6aa8b732 5815
bfdaab09 5816 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5817 string = (exit_qualification & 16) != 0;
cf8f70bf 5818 in = (exit_qualification & 8) != 0;
e70669ab 5819
cf8f70bf 5820 ++vcpu->stat.io_exits;
e70669ab 5821
cf8f70bf 5822 if (string || in)
51d8b661 5823 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5824
cf8f70bf
GN		 5825 port = exit_qualification >> 16;
5826 size = (exit_qualification & 7) + 1;
cf8f70bf 5827
6affcbed
KH		 5828 ret = kvm_skip_emulated_instruction(vcpu);
5829
5830 /*
5831 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5832 * KVM_EXIT_DEBUG here.
5833 */
5834 return kvm_fast_pio_out(vcpu, size, port) && ret;
6aa8b732
AK		 5835}
5836
102d8325
IM		 5837static void
5838vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5839{
5840 /*
5841 * Patch in the VMCALL instruction:
5842 */
5843 hypercall[0] = 0x0f;
5844 hypercall[1] = 0x01;
5845 hypercall[2] = 0xc1;
102d8325
IM		 5846}
5847
0fa06071 5848/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5849static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5850{
eeadf9e7 5851 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5852 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5853 unsigned long orig_val = val;
5854
eeadf9e7
NHE		 5855 /*
5856 * We get here when L2 changed cr0 in a way that did not change
5857 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5858 * but did change L0 shadowed bits. So we first calculate the
5859 * effective cr0 value that L1 would like to write into the
5860 * hardware. It consists of the L2-owned bits from the new
5861 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5862 */
1a0d74e6
JK		 5863 val = (val & ~vmcs12->cr0_guest_host_mask) |
5864 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5865
3899152c 5866 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 5867 return 1;
1a0d74e6
JK		 5868
5869 if (kvm_set_cr0(vcpu, val))
5870 return 1;
5871 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5872 return 0;
1a0d74e6
JK		 5873 } else {
5874 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 5875 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 5876 return 1;
3899152c 5877
eeadf9e7 5878 return kvm_set_cr0(vcpu, val);
1a0d74e6 5879 }
eeadf9e7
NHE		 5880}
5881
5882static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5883{
5884 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5885 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5886 unsigned long orig_val = val;
5887
5888 /* analogously to handle_set_cr0 */
5889 val = (val & ~vmcs12->cr4_guest_host_mask) |
5890 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5891 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5892 return 1;
1a0d74e6 5893 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5894 return 0;
5895 } else
5896 return kvm_set_cr4(vcpu, val);
5897}
5898
6a6256f9 5899/* called to set cr0 as appropriate for clts instruction exit. */
eeadf9e7
NHE		 5900static void handle_clts(struct kvm_vcpu *vcpu)
5901{
5902 if (is_guest_mode(vcpu)) {
5903 /*
5904 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5905 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5906 * just pretend it's off (also in arch.cr0 for fpu_activate).
5907 */
5908 vmcs_writel(CR0_READ_SHADOW,
5909 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5910 vcpu->arch.cr0 &= ~X86_CR0_TS;
5911 } else
5912 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5913}
5914
851ba692 5915static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5916{
229456fc 5917 unsigned long exit_qualification, val;
6aa8b732
AK		 5918 int cr;
5919 int reg;
49a9b07e 5920 int err;
6affcbed 5921 int ret;
6aa8b732 5922
bfdaab09 5923 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5924 cr = exit_qualification & 15;
5925 reg = (exit_qualification >> 8) & 15;
5926 switch ((exit_qualification >> 4) & 3) {
5927 case 0: /* mov to cr */
1e32c079 5928 val = kvm_register_readl(vcpu, reg);
229456fc 5929 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5930 switch (cr) {
5931 case 0:
eeadf9e7 5932 err = handle_set_cr0(vcpu, val);
6affcbed 5933 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 5934 case 3:
2390218b 5935 err = kvm_set_cr3(vcpu, val);
6affcbed 5936 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 5937 case 4:
eeadf9e7 5938 err = handle_set_cr4(vcpu, val);
6affcbed 5939 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5940 case 8: {
5941 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5942 u8 cr8 = (u8)val;
eea1cff9 5943 err = kvm_set_cr8(vcpu, cr8);
6affcbed 5944 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 5945 if (lapic_in_kernel(vcpu))
6affcbed 5946 return ret;
0a5fff19 5947 if (cr8_prev <= cr8)
6affcbed
KH		 5948 return ret;
5949 /*
5950 * TODO: we might be squashing a
5951 * KVM_GUESTDBG_SINGLESTEP-triggered
5952 * KVM_EXIT_DEBUG here.
5953 */
851ba692 5954 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5955 return 0;
5956 }
4b8073e4 5957 }
6aa8b732 5958 break;
25c4c276 5959 case 2: /* clts */
eeadf9e7 5960 handle_clts(vcpu);
4d4ec087 5961 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6b52d186 5962 vmx_fpu_activate(vcpu);
6affcbed 5963 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 5964 case 1: /*mov from cr*/
5965 switch (cr) {
5966 case 3:
9f8fe504
AK		 5967 val = kvm_read_cr3(vcpu);
5968 kvm_register_write(vcpu, reg, val);
5969 trace_kvm_cr_read(cr, val);
6affcbed 5970 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 5971 case 8:
229456fc
MT		 5972 val = kvm_get_cr8(vcpu);
5973 kvm_register_write(vcpu, reg, val);
5974 trace_kvm_cr_read(cr, val);
6affcbed 5975 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 5976 }
5977 break;
5978 case 3: /* lmsw */
a1f83a74 5979 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5980 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5981 kvm_lmsw(vcpu, val);
6aa8b732 5982
6affcbed 5983 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 5984 default:
5985 break;
5986 }
851ba692 5987 vcpu->run->exit_reason = 0;
a737f256 5988 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5989 (int)(exit_qualification >> 4) & 3, cr);
5990 return 0;
5991}
5992
851ba692 5993static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5994{
bfdaab09 5995 unsigned long exit_qualification;
16f8a6f9
NA		 5996 int dr, dr7, reg;
5997
5998 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5999 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6000
6001 /* First, if DR does not exist, trigger UD */
6002 if (!kvm_require_dr(vcpu, dr))
6003 return 1;
6aa8b732 6004
f2483415 6005 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 6006 if (!kvm_require_cpl(vcpu, 0))
6007 return 1;
16f8a6f9
NA		 6008 dr7 = vmcs_readl(GUEST_DR7);
6009 if (dr7 & DR7_GD) {
42dbaa5a
JK		 6010 /*
6011 * As the vm-exit takes precedence over the debug trap, we
6012 * need to emulate the latter, either for the host or the
6013 * guest debugging itself.
6014 */
6015 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 6016 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 6017 vcpu->run->debug.arch.dr7 = dr7;
82b32774 6018 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 6019 vcpu->run->debug.arch.exception = DB_VECTOR;
6020 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 6021 return 0;
6022 } else {
7305eb5d 6023 vcpu->arch.dr6 &= ~15;
6f43ed01 6024 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 6025 kvm_queue_exception(vcpu, DB_VECTOR);
6026 return 1;
6027 }
6028 }
6029
81908bf4 6030 if (vcpu->guest_debug == 0) {
8f22372f
PB		 6031 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6032 CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 6033
6034 /*
6035 * No more DR vmexits; force a reload of the debug registers
6036 * and reenter on this instruction. The next vmexit will
6037 * retrieve the full state of the debug registers.
6038 */
6039 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6040 return 1;
6041 }
6042
42dbaa5a
JK		 6043 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6044 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 6045 unsigned long val;
4c4d563b
JK		 6046
6047 if (kvm_get_dr(vcpu, dr, &val))
6048 return 1;
6049 kvm_register_write(vcpu, reg, val);
020df079 6050 } else
5777392e 6051 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 6052 return 1;
6053
6affcbed 6054 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 6055}
6056
73aaf249
JK		 6057static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6058{
6059 return vcpu->arch.dr6;
6060}
6061
6062static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6063{
6064}
6065
81908bf4
PB		 6066static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6067{
81908bf4
PB		 6068 get_debugreg(vcpu->arch.db[0], 0);
6069 get_debugreg(vcpu->arch.db[1], 1);
6070 get_debugreg(vcpu->arch.db[2], 2);
6071 get_debugreg(vcpu->arch.db[3], 3);
6072 get_debugreg(vcpu->arch.dr6, 6);
6073 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6074
6075 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
8f22372f 6076 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 6077}
6078
020df079
GN		 6079static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6080{
6081 vmcs_writel(GUEST_DR7, val);
6082}
6083
851ba692 6084static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 6085{
6a908b62 6086 return kvm_emulate_cpuid(vcpu);
6aa8b732
AK		 6087}
6088
851ba692 6089static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 6090{
ad312c7c 6091 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 6092 struct msr_data msr_info;
6aa8b732 6093
609e36d3
PB		 6094 msr_info.index = ecx;
6095 msr_info.host_initiated = false;
6096 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 6097 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 6098 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 6099 return 1;
6100 }
6101
609e36d3 6102 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 6103
6aa8b732 6104 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB		 6105 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6106 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6affcbed 6107 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 6108}
6109
851ba692 6110static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 6111{
8fe8ab46 6112 struct msr_data msr;
ad312c7c
ZX		 6113 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6114 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6115 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 6116
8fe8ab46
WA		 6117 msr.data = data;
6118 msr.index = ecx;
6119 msr.host_initiated = false;
854e8bb1 6120 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 6121 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 6122 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 6123 return 1;
6124 }
6125
59200273 6126 trace_kvm_msr_write(ecx, data);
6affcbed 6127 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 6128}
6129
851ba692 6130static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 6131{
eb90f341 6132 kvm_apic_update_ppr(vcpu);
6e5d865c
YS		 6133 return 1;
6134}
6135
851ba692 6136static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 6137{
85f455f7
ED		 6138 u32 cpu_based_vm_exec_control;
6139
6140 /* clear pending irq */
6141 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6142 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6143 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 6144
3842d135
AK		 6145 kvm_make_request(KVM_REQ_EVENT, vcpu);
6146
a26bf12a 6147 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 6148 return 1;
6149}
6150
851ba692 6151static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 6152{
d3bef15f 6153 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 6154}
6155
851ba692 6156static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 6157{
0d9c055e 6158 return kvm_emulate_hypercall(vcpu);
c21415e8
IM		 6159}
6160
ec25d5e6
GN		 6161static int handle_invd(struct kvm_vcpu *vcpu)
6162{
51d8b661 6163 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 6164}
6165
851ba692 6166static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 6167{
f9c617f6 6168 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 6169
6170 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 6171 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT		 6172}
6173
fee84b07
AK		 6174static int handle_rdpmc(struct kvm_vcpu *vcpu)
6175{
6176 int err;
6177
6178 err = kvm_rdpmc(vcpu);
6affcbed 6179 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK		 6180}
6181
851ba692 6182static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 6183{
6affcbed 6184 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 6185}
6186
2acf923e
DC		 6187static int handle_xsetbv(struct kvm_vcpu *vcpu)
6188{
6189 u64 new_bv = kvm_read_edx_eax(vcpu);
6190 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6191
6192 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 6193 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC		 6194 return 1;
6195}
6196
f53cd63c
WL		 6197static int handle_xsaves(struct kvm_vcpu *vcpu)
6198{
6affcbed 6199 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL		 6200 WARN(1, "this should never happen\n");
6201 return 1;
6202}
6203
6204static int handle_xrstors(struct kvm_vcpu *vcpu)
6205{
6affcbed 6206 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL		 6207 WARN(1, "this should never happen\n");
6208 return 1;
6209}
6210
851ba692 6211static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 6212{
58fbbf26
KT		 6213 if (likely(fasteoi)) {
6214 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6215 int access_type, offset;
6216
6217 access_type = exit_qualification & APIC_ACCESS_TYPE;
6218 offset = exit_qualification & APIC_ACCESS_OFFSET;
6219 /*
6220 * Sane guest uses MOV to write EOI, with written value
6221 * not cared. So make a short-circuit here by avoiding
6222 * heavy instruction emulation.
6223 */
6224 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6225 (offset == APIC_EOI)) {
6226 kvm_lapic_set_eoi(vcpu);
6affcbed 6227 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT		 6228 }
6229 }
51d8b661 6230 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 6231}
6232
c7c9c56c
YZ		 6233static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6234{
6235 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6236 int vector = exit_qualification & 0xff;
6237
6238 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6239 kvm_apic_set_eoi_accelerated(vcpu, vector);
6240 return 1;
6241}
6242
83d4c286
YZ		 6243static int handle_apic_write(struct kvm_vcpu *vcpu)
6244{
6245 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6246 u32 offset = exit_qualification & 0xfff;
6247
6248 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6249 kvm_apic_write_nodecode(vcpu, offset);
6250 return 1;
6251}
6252
851ba692 6253static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 6254{
60637aac 6255 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 6256 unsigned long exit_qualification;
e269fb21
JK		 6257 bool has_error_code = false;
6258 u32 error_code = 0;
37817f29 6259 u16 tss_selector;
7f3d35fd 6260 int reason, type, idt_v, idt_index;
64a7ec06
GN		 6261
6262 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 6263 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 6264 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 6265
6266 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6267
6268 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 6269 if (reason == TASK_SWITCH_GATE && idt_v) {
6270 switch (type) {
6271 case INTR_TYPE_NMI_INTR:
6272 vcpu->arch.nmi_injected = false;
654f06fc 6273 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 6274 break;
6275 case INTR_TYPE_EXT_INTR:
66fd3f7f 6276 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 6277 kvm_clear_interrupt_queue(vcpu);
6278 break;
6279 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 6280 if (vmx->idt_vectoring_info &
6281 VECTORING_INFO_DELIVER_CODE_MASK) {
6282 has_error_code = true;
6283 error_code =
6284 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6285 }
6286 /* fall through */
64a7ec06
GN		 6287 case INTR_TYPE_SOFT_EXCEPTION:
6288 kvm_clear_exception_queue(vcpu);
6289 break;
6290 default:
6291 break;
6292 }
60637aac 6293 }
37817f29
IE		 6294 tss_selector = exit_qualification;
6295
64a7ec06
GN		 6296 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6297 type != INTR_TYPE_EXT_INTR &&
6298 type != INTR_TYPE_NMI_INTR))
6299 skip_emulated_instruction(vcpu);
6300
7f3d35fd
KW		 6301 if (kvm_task_switch(vcpu, tss_selector,
6302 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6303 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 6304 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6305 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6306 vcpu->run->internal.ndata = 0;
42dbaa5a 6307 return 0;
acb54517 6308 }
42dbaa5a 6309
42dbaa5a
JK		 6310 /*
6311 * TODO: What about debug traps on tss switch?
6312 * Are we supposed to inject them and update dr6?
6313 */
6314
6315 return 1;
37817f29
IE		 6316}
6317
851ba692 6318static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 6319{
f9c617f6 6320 unsigned long exit_qualification;
1439442c 6321 gpa_t gpa;
4f5982a5 6322 u32 error_code;
1439442c 6323 int gla_validity;
1439442c 6324
f9c617f6 6325 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 6326
1439442c 6327 gla_validity = (exit_qualification >> 7) & 0x3;
72e0ae58 6328 if (gla_validity == 0x2) {
1439442c
SY		 6329 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6330 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6331 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 6332 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 6333 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6334 (long unsigned int)exit_qualification);
851ba692
AK		 6335 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6336 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 6337 return 0;
1439442c
SY		 6338 }
6339
0be9c7a8
GN		 6340 /*
6341 * EPT violation happened while executing iret from NMI,
6342 * "blocked by NMI" bit has to be set before next VM entry.
6343 * There are errata that may cause this bit to not be set:
6344 * AAK134, BY25.
6345 */
bcd1c294
GN		 6346 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6347 cpu_has_virtual_nmis() &&
6348 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 6349 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6350
1439442c 6351 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 6352 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 6353
27959a44 6354 /* Is it a read fault? */
ab22a473 6355 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS		 6356 ? PFERR_USER_MASK : 0;
6357 /* Is it a write fault? */
ab22a473 6358 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS		 6359 ? PFERR_WRITE_MASK : 0;
6360 /* Is it a fetch fault? */
ab22a473 6361 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS		 6362 ? PFERR_FETCH_MASK : 0;
6363 /* ept page table entry is present? */
6364 error_code |= (exit_qualification &
6365 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6366 EPT_VIOLATION_EXECUTABLE))
6367 ? PFERR_PRESENT_MASK : 0;
4f5982a5 6368
db1c056c 6369 vcpu->arch.gpa_available = true;
25d92081
YZ		 6370 vcpu->arch.exit_qualification = exit_qualification;
6371
4f5982a5 6372 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 6373}
6374
851ba692 6375static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 6376{
f735d4af 6377 int ret;
68f89400
MT		 6378 gpa_t gpa;
6379
6380 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 6381 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 6382 trace_kvm_fast_mmio(gpa);
6affcbed 6383 return kvm_skip_emulated_instruction(vcpu);
68c3b4d1 6384 }
68f89400 6385
450869d6 6386 ret = handle_mmio_page_fault(vcpu, gpa, true);
db1c056c 6387 vcpu->arch.gpa_available = true;
b37fbea6 6388 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 6389 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6390 EMULATE_DONE;
f8f55942
XG		 6391
6392 if (unlikely(ret == RET_MMIO_PF_INVALID))
6393 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6394
b37fbea6 6395 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 6396 return 1;
6397
6398 /* It is the real ept misconfig */
f735d4af 6399 WARN_ON(1);
68f89400 6400
851ba692
AK		 6401 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6402 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 6403
6404 return 0;
6405}
6406
851ba692 6407static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 6408{
6409 u32 cpu_based_vm_exec_control;
6410
6411 /* clear pending NMI */
6412 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6413 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6414 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6415 ++vcpu->stat.nmi_window_exits;
3842d135 6416 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 6417
6418 return 1;
6419}
6420
80ced186 6421static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 6422{
8b3079a5
AK		 6423 struct vcpu_vmx *vmx = to_vmx(vcpu);
6424 enum emulation_result err = EMULATE_DONE;
80ced186 6425 int ret = 1;
49e9d557
AK		 6426 u32 cpu_exec_ctrl;
6427 bool intr_window_requested;
b8405c18 6428 unsigned count = 130;
49e9d557
AK		 6429
6430 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6431 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 6432
98eb2f8b 6433 while (vmx->emulation_required && count-- != 0) {
bdea48e3 6434 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 6435 return handle_interrupt_window(&vmx->vcpu);
6436
de87dcdd
AK		 6437 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6438 return 1;
6439
991eebf9 6440 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 6441
ac0a48c3 6442 if (err == EMULATE_USER_EXIT) {
94452b9e 6443 ++vcpu->stat.mmio_exits;
80ced186
MG		 6444 ret = 0;
6445 goto out;
6446 }
1d5a4d9b 6447
de5f70e0
AK		 6448 if (err != EMULATE_DONE) {
6449 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6450 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6451 vcpu->run->internal.ndata = 0;
6d77dbfc 6452 return 0;
de5f70e0 6453 }
ea953ef0 6454
8d76c49e
GN		 6455 if (vcpu->arch.halt_request) {
6456 vcpu->arch.halt_request = 0;
5cb56059 6457 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 6458 goto out;
6459 }
6460
ea953ef0 6461 if (signal_pending(current))
80ced186 6462 goto out;
ea953ef0
MG		 6463 if (need_resched())
6464 schedule();
6465 }
6466
80ced186
MG		 6467out:
6468 return ret;
ea953ef0
MG		 6469}
6470
b4a2d31d
RK		 6471static int __grow_ple_window(int val)
6472{
6473 if (ple_window_grow < 1)
6474 return ple_window;
6475
6476 val = min(val, ple_window_actual_max);
6477
6478 if (ple_window_grow < ple_window)
6479 val *= ple_window_grow;
6480 else
6481 val += ple_window_grow;
6482
6483 return val;
6484}
6485
6486static int __shrink_ple_window(int val, int modifier, int minimum)
6487{
6488 if (modifier < 1)
6489 return ple_window;
6490
6491 if (modifier < ple_window)
6492 val /= modifier;
6493 else
6494 val -= modifier;
6495
6496 return max(val, minimum);
6497}
6498
6499static void grow_ple_window(struct kvm_vcpu *vcpu)
6500{
6501 struct vcpu_vmx *vmx = to_vmx(vcpu);
6502 int old = vmx->ple_window;
6503
6504 vmx->ple_window = __grow_ple_window(old);
6505
6506 if (vmx->ple_window != old)
6507 vmx->ple_window_dirty = true;
7b46268d
RK		 6508
6509 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 6510}
6511
6512static void shrink_ple_window(struct kvm_vcpu *vcpu)
6513{
6514 struct vcpu_vmx *vmx = to_vmx(vcpu);
6515 int old = vmx->ple_window;
6516
6517 vmx->ple_window = __shrink_ple_window(old,
6518 ple_window_shrink, ple_window);
6519
6520 if (vmx->ple_window != old)
6521 vmx->ple_window_dirty = true;
7b46268d
RK		 6522
6523 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 6524}
6525
6526/*
6527 * ple_window_actual_max is computed to be one grow_ple_window() below
6528 * ple_window_max. (See __grow_ple_window for the reason.)
6529 * This prevents overflows, because ple_window_max is int.
6530 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6531 * this process.
6532 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6533 */
6534static void update_ple_window_actual_max(void)
6535{
6536 ple_window_actual_max =
6537 __shrink_ple_window(max(ple_window_max, ple_window),
6538 ple_window_grow, INT_MIN);
6539}
6540
bf9f6ac8
FW		 6541/*
6542 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6543 */
6544static void wakeup_handler(void)
6545{
6546 struct kvm_vcpu *vcpu;
6547 int cpu = smp_processor_id();
6548
6549 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6550 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6551 blocked_vcpu_list) {
6552 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6553
6554 if (pi_test_on(pi_desc) == 1)
6555 kvm_vcpu_kick(vcpu);
6556 }
6557 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6558}
6559
f160c7b7
JS		 6560void vmx_enable_tdp(void)
6561{
6562 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6563 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6564 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6565 0ull, VMX_EPT_EXECUTABLE_MASK,
6566 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
312b616b 6567 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
f160c7b7
JS		 6568
6569 ept_set_mmio_spte_mask();
6570 kvm_enable_tdp();
6571}
6572
f2c7648d
TC		 6573static __init int hardware_setup(void)
6574{
34a1cd60
TC		 6575 int r = -ENOMEM, i, msr;
6576
6577 rdmsrl_safe(MSR_EFER, &host_efer);
6578
6579 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6580 kvm_define_shared_msr(i, vmx_msr_index[i]);
6581
23611332
RK		 6582 for (i = 0; i < VMX_BITMAP_NR; i++) {
6583 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6584 if (!vmx_bitmap[i])
6585 goto out;
6586 }
34a1cd60
TC		 6587
6588 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
34a1cd60
TC		 6589 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6590 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6591
6592 /*
6593 * Allow direct access to the PC debug port (it is often used for I/O
6594 * delays, but the vmexits simply slow things down).
6595 */
6596 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6597 clear_bit(0x80, vmx_io_bitmap_a);
6598
6599 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6600
6601 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6602 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6603
34a1cd60
TC		 6604 if (setup_vmcs_config(&vmcs_config) < 0) {
6605 r = -EIO;
23611332 6606 goto out;
baa03522 6607 }
f2c7648d
TC		 6608
6609 if (boot_cpu_has(X86_FEATURE_NX))
6610 kvm_enable_efer_bits(EFER_NX);
6611
6612 if (!cpu_has_vmx_vpid())
6613 enable_vpid = 0;
6614 if (!cpu_has_vmx_shadow_vmcs())
6615 enable_shadow_vmcs = 0;
6616 if (enable_shadow_vmcs)
6617 init_vmcs_shadow_fields();
6618
6619 if (!cpu_has_vmx_ept() ||
6620 !cpu_has_vmx_ept_4levels()) {
6621 enable_ept = 0;
6622 enable_unrestricted_guest = 0;
6623 enable_ept_ad_bits = 0;
6624 }
6625
6626 if (!cpu_has_vmx_ept_ad_bits())
6627 enable_ept_ad_bits = 0;
6628
6629 if (!cpu_has_vmx_unrestricted_guest())
6630 enable_unrestricted_guest = 0;
6631
ad15a296 6632 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6633 flexpriority_enabled = 0;
6634
ad15a296
PB		 6635 /*
6636 * set_apic_access_page_addr() is used to reload apic access
6637 * page upon invalidation. No need to do anything if not
6638 * using the APIC_ACCESS_ADDR VMCS field.
6639 */
6640 if (!flexpriority_enabled)
f2c7648d 6641 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6642
6643 if (!cpu_has_vmx_tpr_shadow())
6644 kvm_x86_ops->update_cr8_intercept = NULL;
6645
6646 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6647 kvm_disable_largepages();
6648
6649 if (!cpu_has_vmx_ple())
6650 ple_gap = 0;
6651
6652 if (!cpu_has_vmx_apicv())
6653 enable_apicv = 0;
6654
64903d61
HZ		 6655 if (cpu_has_vmx_tsc_scaling()) {
6656 kvm_has_tsc_control = true;
6657 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6658 kvm_tsc_scaling_ratio_frac_bits = 48;
6659 }
6660
baa03522
TC		 6661 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6662 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6663 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6664 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6665 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6666 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6667 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6668
c63e4563 6669 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
baa03522 6670 vmx_msr_bitmap_legacy, PAGE_SIZE);
c63e4563 6671 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
baa03522 6672 vmx_msr_bitmap_longmode, PAGE_SIZE);
c63e4563 6673 memcpy(vmx_msr_bitmap_legacy_x2apic,
f6e90f9e 6674 vmx_msr_bitmap_legacy, PAGE_SIZE);
c63e4563 6675 memcpy(vmx_msr_bitmap_longmode_x2apic,
f6e90f9e 6676 vmx_msr_bitmap_longmode, PAGE_SIZE);
baa03522 6677
04bb92e4
WL		 6678 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6679
40d8338d
RK		 6680 for (msr = 0x800; msr <= 0x8ff; msr++) {
6681 if (msr == 0x839 /* TMCCT */)
6682 continue;
2e69f865 6683 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
40d8338d 6684 }
3ce424e4 6685
f6e90f9e 6686 /*
2e69f865
RK		 6687 * TPR reads and writes can be virtualized even if virtual interrupt
6688 * delivery is not in use.
f6e90f9e 6689 */
2e69f865
RK		 6690 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6691 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
3ce424e4 6692
3ce424e4 6693 /* EOI */
2e69f865 6694 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
3ce424e4 6695 /* SELF-IPI */
2e69f865 6696 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
baa03522 6697
f160c7b7
JS		 6698 if (enable_ept)
6699 vmx_enable_tdp();
6700 else
baa03522
TC		 6701 kvm_disable_tdp();
6702
6703 update_ple_window_actual_max();
6704
843e4330
KH		 6705 /*
6706 * Only enable PML when hardware supports PML feature, and both EPT
6707 * and EPT A/D bit features are enabled -- PML depends on them to work.
6708 */
6709 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6710 enable_pml = 0;
6711
6712 if (!enable_pml) {
6713 kvm_x86_ops->slot_enable_log_dirty = NULL;
6714 kvm_x86_ops->slot_disable_log_dirty = NULL;
6715 kvm_x86_ops->flush_log_dirty = NULL;
6716 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6717 }
6718
64672c95
YJ		 6719 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6720 u64 vmx_msr;
6721
6722 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6723 cpu_preemption_timer_multi =
6724 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6725 } else {
6726 kvm_x86_ops->set_hv_timer = NULL;
6727 kvm_x86_ops->cancel_hv_timer = NULL;
6728 }
6729
bf9f6ac8
FW		 6730 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6731
c45dcc71
AR		 6732 kvm_mce_cap_supported |= MCG_LMCE_P;
6733
f2c7648d 6734 return alloc_kvm_area();
34a1cd60 6735
34a1cd60 6736out:
23611332
RK		 6737 for (i = 0; i < VMX_BITMAP_NR; i++)
6738 free_page((unsigned long)vmx_bitmap[i]);
34a1cd60
TC		 6739
6740 return r;
f2c7648d
TC		 6741}
6742
6743static __exit void hardware_unsetup(void)
6744{
23611332
RK		 6745 int i;
6746
6747 for (i = 0; i < VMX_BITMAP_NR; i++)
6748 free_page((unsigned long)vmx_bitmap[i]);
34a1cd60 6749
f2c7648d
TC		 6750 free_kvm_area();
6751}
6752
4b8d54f9
ZE		 6753/*
6754 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6755 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6756 */
9fb41ba8 6757static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6758{
b4a2d31d
RK		 6759 if (ple_gap)
6760 grow_ple_window(vcpu);
6761
4b8d54f9 6762 kvm_vcpu_on_spin(vcpu);
6affcbed 6763 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE		 6764}
6765
87c00572 6766static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6767{
6affcbed 6768 return kvm_skip_emulated_instruction(vcpu);
59708670
SY		 6769}
6770
87c00572
GS		 6771static int handle_mwait(struct kvm_vcpu *vcpu)
6772{
6773 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6774 return handle_nop(vcpu);
6775}
6776
5f3d45e7
MD		 6777static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6778{
6779 return 1;
6780}
6781
87c00572
GS		 6782static int handle_monitor(struct kvm_vcpu *vcpu)
6783{
6784 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6785 return handle_nop(vcpu);
6786}
6787
ff2f6fe9
NHE		 6788/*
6789 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6790 * We could reuse a single VMCS for all the L2 guests, but we also want the
6791 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6792 * allows keeping them loaded on the processor, and in the future will allow
6793 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6794 * every entry if they never change.
6795 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6796 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6797 *
6798 * The following functions allocate and free a vmcs02 in this pool.
6799 */
6800
6801/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6802static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6803{
6804 struct vmcs02_list *item;
6805 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6806 if (item->vmptr == vmx->nested.current_vmptr) {
6807 list_move(&item->list, &vmx->nested.vmcs02_pool);
6808 return &item->vmcs02;
6809 }
6810
6811 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6812 /* Recycle the least recently used VMCS. */
d74c0e6b
GT		 6813 item = list_last_entry(&vmx->nested.vmcs02_pool,
6814 struct vmcs02_list, list);
ff2f6fe9
NHE		 6815 item->vmptr = vmx->nested.current_vmptr;
6816 list_move(&item->list, &vmx->nested.vmcs02_pool);
6817 return &item->vmcs02;
6818 }
6819
6820 /* Create a new VMCS */
0fa24ce3 6821 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6822 if (!item)
6823 return NULL;
6824 item->vmcs02.vmcs = alloc_vmcs();
355f4fb1 6825 item->vmcs02.shadow_vmcs = NULL;
ff2f6fe9
NHE		 6826 if (!item->vmcs02.vmcs) {
6827 kfree(item);
6828 return NULL;
6829 }
6830 loaded_vmcs_init(&item->vmcs02);
6831 item->vmptr = vmx->nested.current_vmptr;
6832 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6833 vmx->nested.vmcs02_num++;
6834 return &item->vmcs02;
6835}
6836
6837/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6838static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6839{
6840 struct vmcs02_list *item;
6841 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6842 if (item->vmptr == vmptr) {
6843 free_loaded_vmcs(&item->vmcs02);
6844 list_del(&item->list);
6845 kfree(item);
6846 vmx->nested.vmcs02_num--;
6847 return;
6848 }
6849}
6850
6851/*
6852 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6853 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6854 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6855 */
6856static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6857{
6858 struct vmcs02_list *item, *n;
4fa7734c
PB		 6859
6860 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6861 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6862 /*
6863 * Something will leak if the above WARN triggers. Better than
6864 * a use-after-free.
6865 */
6866 if (vmx->loaded_vmcs == &item->vmcs02)
6867 continue;
6868
6869 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6870 list_del(&item->list);
6871 kfree(item);
4fa7734c 6872 vmx->nested.vmcs02_num--;
ff2f6fe9 6873 }
ff2f6fe9
NHE		 6874}
6875
0658fbaa
ACL		 6876/*
6877 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6878 * set the success or error code of an emulated VMX instruction, as specified
6879 * by Vol 2B, VMX Instruction Reference, "Conventions".
6880 */
6881static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6882{
6883 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6884 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6885 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6886}
6887
6888static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6889{
6890 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6891 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6892 X86_EFLAGS_SF | X86_EFLAGS_OF))
6893 | X86_EFLAGS_CF);
6894}
6895
145c28dd 6896static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6897 u32 vm_instruction_error)
6898{
6899 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6900 /*
6901 * failValid writes the error number to the current VMCS, which
6902 * can't be done there isn't a current VMCS.
6903 */
6904 nested_vmx_failInvalid(vcpu);
6905 return;
6906 }
6907 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6908 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6909 X86_EFLAGS_SF | X86_EFLAGS_OF))
6910 | X86_EFLAGS_ZF);
6911 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6912 /*
6913 * We don't need to force a shadow sync because
6914 * VM_INSTRUCTION_ERROR is not shadowed
6915 */
6916}
145c28dd 6917
ff651cb6
WV		 6918static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6919{
6920 /* TODO: not to reset guest simply here. */
6921 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
bbe41b95 6922 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
ff651cb6
WV		 6923}
6924
f4124500
JK		 6925static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6926{
6927 struct vcpu_vmx *vmx =
6928 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6929
6930 vmx->nested.preemption_timer_expired = true;
6931 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6932 kvm_vcpu_kick(&vmx->vcpu);
6933
6934 return HRTIMER_NORESTART;
6935}
6936
19677e32
BD		 6937/*
6938 * Decode the memory-address operand of a vmx instruction, as recorded on an
6939 * exit caused by such an instruction (run by a guest hypervisor).
6940 * On success, returns 0. When the operand is invalid, returns 1 and throws
6941 * #UD or #GP.
6942 */
6943static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6944 unsigned long exit_qualification,
f9eb4af6 6945 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6946{
f9eb4af6
EK		 6947 gva_t off;
6948 bool exn;
6949 struct kvm_segment s;
6950
19677e32
BD		 6951 /*
6952 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6953 * Execution", on an exit, vmx_instruction_info holds most of the
6954 * addressing components of the operand. Only the displacement part
6955 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6956 * For how an actual address is calculated from all these components,
6957 * refer to Vol. 1, "Operand Addressing".
6958 */
6959 int scaling = vmx_instruction_info & 3;
6960 int addr_size = (vmx_instruction_info >> 7) & 7;
6961 bool is_reg = vmx_instruction_info & (1u << 10);
6962 int seg_reg = (vmx_instruction_info >> 15) & 7;
6963 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6964 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6965 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6966 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6967
6968 if (is_reg) {
6969 kvm_queue_exception(vcpu, UD_VECTOR);
6970 return 1;
6971 }
6972
6973 /* Addr = segment_base + offset */
6974 /* offset = base + [index * scale] + displacement */
f9eb4af6 6975 off = exit_qualification; /* holds the displacement */
19677e32 6976 if (base_is_valid)
f9eb4af6 6977 off += kvm_register_read(vcpu, base_reg);
19677e32 6978 if (index_is_valid)
f9eb4af6
EK		 6979 off += kvm_register_read(vcpu, index_reg)<<scaling;
6980 vmx_get_segment(vcpu, &s, seg_reg);
6981 *ret = s.base + off;
19677e32
BD		 6982
6983 if (addr_size == 1) /* 32 bit */
6984 *ret &= 0xffffffff;
6985
f9eb4af6
EK		 6986 /* Checks for #GP/#SS exceptions. */
6987 exn = false;
ff30ef40
QC		 6988 if (is_long_mode(vcpu)) {
6989 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6990 * non-canonical form. This is the only check on the memory
6991 * destination for long mode!
6992 */
6993 exn = is_noncanonical_address(*ret);
6994 } else if (is_protmode(vcpu)) {
f9eb4af6
EK		 6995 /* Protected mode: apply checks for segment validity in the
6996 * following order:
6997 * - segment type check (#GP(0) may be thrown)
6998 * - usability check (#GP(0)/#SS(0))
6999 * - limit check (#GP(0)/#SS(0))
7000 */
7001 if (wr)
7002 /* #GP(0) if the destination operand is located in a
7003 * read-only data segment or any code segment.
7004 */
7005 exn = ((s.type & 0xa) == 0 || (s.type & 8));
7006 else
7007 /* #GP(0) if the source operand is located in an
7008 * execute-only code segment
7009 */
7010 exn = ((s.type & 0xa) == 8);
ff30ef40
QC		 7011 if (exn) {
7012 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7013 return 1;
7014 }
f9eb4af6
EK		 7015 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7016 */
7017 exn = (s.unusable != 0);
7018 /* Protected mode: #GP(0)/#SS(0) if the memory
7019 * operand is outside the segment limit.
7020 */
7021 exn = exn || (off + sizeof(u64) > s.limit);
7022 }
7023 if (exn) {
7024 kvm_queue_exception_e(vcpu,
7025 seg_reg == VCPU_SREG_SS ?
7026 SS_VECTOR : GP_VECTOR,
7027 0);
7028 return 1;
7029 }
7030
19677e32
BD		 7031 return 0;
7032}
7033
3573e22c
BD		 7034/*
7035 * This function performs the various checks including
7036 * - if it's 4KB aligned
7037 * - No bits beyond the physical address width are set
7038 * - Returns 0 on success or else 1
4291b588 7039 * (Intel SDM Section 30.3)
3573e22c 7040 */
4291b588
BD		 7041static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
7042 gpa_t *vmpointer)
3573e22c
BD		 7043{
7044 gva_t gva;
7045 gpa_t vmptr;
7046 struct x86_exception e;
7047 struct page *page;
7048 struct vcpu_vmx *vmx = to_vmx(vcpu);
7049 int maxphyaddr = cpuid_maxphyaddr(vcpu);
7050
7051 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7052 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD		 7053 return 1;
7054
7055 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
7056 sizeof(vmptr), &e)) {
7057 kvm_inject_page_fault(vcpu, &e);
7058 return 1;
7059 }
7060
7061 switch (exit_reason) {
7062 case EXIT_REASON_VMON:
7063 /*
7064 * SDM 3: 24.11.5
7065 * The first 4 bytes of VMXON region contain the supported
7066 * VMCS revision identifier
7067 *
7068 * Note - IA32_VMX_BASIC[48] will never be 1
7069 * for the nested case;
7070 * which replaces physical address width with 32
7071 *
7072 */
bc39c4db 7073 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c 7074 nested_vmx_failInvalid(vcpu);
6affcbed 7075 return kvm_skip_emulated_instruction(vcpu);
3573e22c
BD		 7076 }
7077
7078 page = nested_get_page(vcpu, vmptr);
7079 if (page == NULL ||
7080 *(u32 *)kmap(page) != VMCS12_REVISION) {
7081 nested_vmx_failInvalid(vcpu);
7082 kunmap(page);
6affcbed 7083 return kvm_skip_emulated_instruction(vcpu);
3573e22c
BD		 7084 }
7085 kunmap(page);
7086 vmx->nested.vmxon_ptr = vmptr;
7087 break;
4291b588 7088 case EXIT_REASON_VMCLEAR:
bc39c4db 7089 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 7090 nested_vmx_failValid(vcpu,
7091 VMXERR_VMCLEAR_INVALID_ADDRESS);
6affcbed 7092 return kvm_skip_emulated_instruction(vcpu);
4291b588
BD		 7093 }
7094
7095 if (vmptr == vmx->nested.vmxon_ptr) {
7096 nested_vmx_failValid(vcpu,
7097 VMXERR_VMCLEAR_VMXON_POINTER);
6affcbed 7098 return kvm_skip_emulated_instruction(vcpu);
4291b588
BD		 7099 }
7100 break;
7101 case EXIT_REASON_VMPTRLD:
bc39c4db 7102 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 7103 nested_vmx_failValid(vcpu,
7104 VMXERR_VMPTRLD_INVALID_ADDRESS);
6affcbed 7105 return kvm_skip_emulated_instruction(vcpu);
4291b588 7106 }
3573e22c 7107
4291b588
BD		 7108 if (vmptr == vmx->nested.vmxon_ptr) {
7109 nested_vmx_failValid(vcpu,
37b9a671 7110 VMXERR_VMPTRLD_VMXON_POINTER);
6affcbed 7111 return kvm_skip_emulated_instruction(vcpu);
4291b588
BD		 7112 }
7113 break;
3573e22c
BD		 7114 default:
7115 return 1; /* shouldn't happen */
7116 }
7117
4291b588
BD		 7118 if (vmpointer)
7119 *vmpointer = vmptr;
3573e22c
BD		 7120 return 0;
7121}
7122
ec378aee
NHE		 7123/*
7124 * Emulate the VMXON instruction.
7125 * Currently, we just remember that VMX is active, and do not save or even
7126 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7127 * do not currently need to store anything in that guest-allocated memory
7128 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7129 * argument is different from the VMXON pointer (which the spec says they do).
7130 */
7131static int handle_vmon(struct kvm_vcpu *vcpu)
7132{
7133 struct kvm_segment cs;
7134 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 7135 struct vmcs *shadow_vmcs;
b3897a49
NHE		 7136 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7137 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 7138
7139 /* The Intel VMX Instruction Reference lists a bunch of bits that
7140 * are prerequisite to running VMXON, most notably cr4.VMXE must be
7141 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7142 * Otherwise, we should fail with #UD. We test these now:
7143 */
7144 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7145 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7146 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7147 kvm_queue_exception(vcpu, UD_VECTOR);
7148 return 1;
7149 }
7150
7151 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7152 if (is_long_mode(vcpu) && !cs.l) {
7153 kvm_queue_exception(vcpu, UD_VECTOR);
7154 return 1;
7155 }
7156
7157 if (vmx_get_cpl(vcpu)) {
7158 kvm_inject_gp(vcpu, 0);
7159 return 1;
7160 }
3573e22c 7161
145c28dd
AG		 7162 if (vmx->nested.vmxon) {
7163 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6affcbed 7164 return kvm_skip_emulated_instruction(vcpu);
145c28dd 7165 }
b3897a49 7166
3b84080b 7167 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
b3897a49
NHE		 7168 != VMXON_NEEDED_FEATURES) {
7169 kvm_inject_gp(vcpu, 0);
7170 return 1;
7171 }
7172
21e7fbe7
JM		 7173 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7174 return 1;
7175
d048c098
RK		 7176 if (cpu_has_vmx_msr_bitmap()) {
7177 vmx->nested.msr_bitmap =
7178 (unsigned long *)__get_free_page(GFP_KERNEL);
7179 if (!vmx->nested.msr_bitmap)
7180 goto out_msr_bitmap;
7181 }
7182
4f2777bc
DM		 7183 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7184 if (!vmx->nested.cached_vmcs12)
d048c098 7185 goto out_cached_vmcs12;
4f2777bc 7186
8de48833
AG		 7187 if (enable_shadow_vmcs) {
7188 shadow_vmcs = alloc_vmcs();
d048c098
RK		 7189 if (!shadow_vmcs)
7190 goto out_shadow_vmcs;
8de48833
AG		 7191 /* mark vmcs as shadow */
7192 shadow_vmcs->revision_id |= (1u << 31);
7193 /* init shadow vmcs */
7194 vmcs_clear(shadow_vmcs);
355f4fb1 7195 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
8de48833 7196 }
ec378aee 7197
ff2f6fe9
NHE		 7198 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7199 vmx->nested.vmcs02_num = 0;
7200
f4124500 7201 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
f15a75ee 7202 HRTIMER_MODE_REL_PINNED);
f4124500
JK		 7203 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7204
ec378aee
NHE		 7205 vmx->nested.vmxon = true;
7206
a25eb114 7207 nested_vmx_succeed(vcpu);
6affcbed 7208 return kvm_skip_emulated_instruction(vcpu);
d048c098
RK		 7209
7210out_shadow_vmcs:
7211 kfree(vmx->nested.cached_vmcs12);
7212
7213out_cached_vmcs12:
7214 free_page((unsigned long)vmx->nested.msr_bitmap);
7215
7216out_msr_bitmap:
7217 return -ENOMEM;
ec378aee
NHE		 7218}
7219
7220/*
7221 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7222 * for running VMX instructions (except VMXON, whose prerequisites are
7223 * slightly different). It also specifies what exception to inject otherwise.
7224 */
7225static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7226{
7227 struct kvm_segment cs;
7228 struct vcpu_vmx *vmx = to_vmx(vcpu);
7229
7230 if (!vmx->nested.vmxon) {
7231 kvm_queue_exception(vcpu, UD_VECTOR);
7232 return 0;
7233 }
7234
7235 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7236 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7237 (is_long_mode(vcpu) && !cs.l)) {
7238 kvm_queue_exception(vcpu, UD_VECTOR);
7239 return 0;
7240 }
7241
7242 if (vmx_get_cpl(vcpu)) {
7243 kvm_inject_gp(vcpu, 0);
7244 return 0;
7245 }
7246
7247 return 1;
7248}
7249
e7953d7f
AG		 7250static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7251{
9a2a05b9
PB		 7252 if (vmx->nested.current_vmptr == -1ull)
7253 return;
7254
7255 /* current_vmptr and current_vmcs12 are always set/reset together */
7256 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7257 return;
7258
012f83cb 7259 if (enable_shadow_vmcs) {
9a2a05b9
PB		 7260 /* copy to memory all shadowed fields in case
7261 they were modified */
7262 copy_shadow_to_vmcs12(vmx);
7263 vmx->nested.sync_shadow_vmcs = false;
7ec36296
XG		 7264 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7265 SECONDARY_EXEC_SHADOW_VMCS);
9a2a05b9 7266 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 7267 }
705699a1 7268 vmx->nested.posted_intr_nv = -1;
4f2777bc
DM		 7269
7270 /* Flush VMCS12 to guest memory */
7271 memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7272 VMCS12_SIZE);
7273
e7953d7f
AG		 7274 kunmap(vmx->nested.current_vmcs12_page);
7275 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 7276 vmx->nested.current_vmptr = -1ull;
7277 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 7278}
7279
ec378aee
NHE		 7280/*
7281 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7282 * just stops using VMX.
7283 */
7284static void free_nested(struct vcpu_vmx *vmx)
7285{
7286 if (!vmx->nested.vmxon)
7287 return;
9a2a05b9 7288
ec378aee 7289 vmx->nested.vmxon = false;
5c614b35 7290 free_vpid(vmx->nested.vpid02);
9a2a05b9 7291 nested_release_vmcs12(vmx);
d048c098
RK		 7292 if (vmx->nested.msr_bitmap) {
7293 free_page((unsigned long)vmx->nested.msr_bitmap);
7294 vmx->nested.msr_bitmap = NULL;
7295 }
355f4fb1
JM		 7296 if (enable_shadow_vmcs) {
7297 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7298 free_vmcs(vmx->vmcs01.shadow_vmcs);
7299 vmx->vmcs01.shadow_vmcs = NULL;
7300 }
4f2777bc 7301 kfree(vmx->nested.cached_vmcs12);
fe3ef05c
NHE		 7302 /* Unpin physical memory we referred to in current vmcs02 */
7303 if (vmx->nested.apic_access_page) {
7304 nested_release_page(vmx->nested.apic_access_page);
48d89b92 7305 vmx->nested.apic_access_page = NULL;
fe3ef05c 7306 }
a7c0b07d
WL		 7307 if (vmx->nested.virtual_apic_page) {
7308 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 7309 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 7310 }
705699a1
WV		 7311 if (vmx->nested.pi_desc_page) {
7312 kunmap(vmx->nested.pi_desc_page);
7313 nested_release_page(vmx->nested.pi_desc_page);
7314 vmx->nested.pi_desc_page = NULL;
7315 vmx->nested.pi_desc = NULL;
7316 }
ff2f6fe9
NHE		 7317
7318 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 7319}
7320
7321/* Emulate the VMXOFF instruction */
7322static int handle_vmoff(struct kvm_vcpu *vcpu)
7323{
7324 if (!nested_vmx_check_permission(vcpu))
7325 return 1;
7326 free_nested(to_vmx(vcpu));
a25eb114 7327 nested_vmx_succeed(vcpu);
6affcbed 7328 return kvm_skip_emulated_instruction(vcpu);
ec378aee
NHE		 7329}
7330
27d6c865
NHE		 7331/* Emulate the VMCLEAR instruction */
7332static int handle_vmclear(struct kvm_vcpu *vcpu)
7333{
7334 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 7335 gpa_t vmptr;
7336 struct vmcs12 *vmcs12;
7337 struct page *page;
27d6c865
NHE		 7338
7339 if (!nested_vmx_check_permission(vcpu))
7340 return 1;
7341
4291b588 7342 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 7343 return 1;
27d6c865 7344
9a2a05b9 7345 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 7346 nested_release_vmcs12(vmx);
27d6c865
NHE		 7347
7348 page = nested_get_page(vcpu, vmptr);
7349 if (page == NULL) {
7350 /*
7351 * For accurate processor emulation, VMCLEAR beyond available
7352 * physical memory should do nothing at all. However, it is
7353 * possible that a nested vmx bug, not a guest hypervisor bug,
7354 * resulted in this case, so let's shut down before doing any
7355 * more damage:
7356 */
7357 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7358 return 1;
7359 }
7360 vmcs12 = kmap(page);
7361 vmcs12->launch_state = 0;
7362 kunmap(page);
7363 nested_release_page(page);
7364
7365 nested_free_vmcs02(vmx, vmptr);
7366
27d6c865 7367 nested_vmx_succeed(vcpu);
6affcbed 7368 return kvm_skip_emulated_instruction(vcpu);
27d6c865
NHE		 7369}
7370
cd232ad0
NHE		 7371static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7372
7373/* Emulate the VMLAUNCH instruction */
7374static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7375{
7376 return nested_vmx_run(vcpu, true);
7377}
7378
7379/* Emulate the VMRESUME instruction */
7380static int handle_vmresume(struct kvm_vcpu *vcpu)
7381{
7382
7383 return nested_vmx_run(vcpu, false);
7384}
7385
49f705c5
NHE		 7386enum vmcs_field_type {
7387 VMCS_FIELD_TYPE_U16 = 0,
7388 VMCS_FIELD_TYPE_U64 = 1,
7389 VMCS_FIELD_TYPE_U32 = 2,
7390 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7391};
7392
7393static inline int vmcs_field_type(unsigned long field)
7394{
7395 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
7396 return VMCS_FIELD_TYPE_U32;
7397 return (field >> 13) & 0x3 ;
7398}
7399
7400static inline int vmcs_field_readonly(unsigned long field)
7401{
7402 return (((field >> 10) & 0x3) == 1);
7403}
7404
7405/*
7406 * Read a vmcs12 field. Since these can have varying lengths and we return
7407 * one type, we chose the biggest type (u64) and zero-extend the return value
7408 * to that size. Note that the caller, handle_vmread, might need to use only
7409 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7410 * 64-bit fields are to be returned).
7411 */
a2ae9df7
PB		 7412static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7413 unsigned long field, u64 *ret)
49f705c5
NHE		 7414{
7415 short offset = vmcs_field_to_offset(field);
7416 char *p;
7417
7418 if (offset < 0)
a2ae9df7 7419 return offset;
49f705c5
NHE		 7420
7421 p = ((char *)(get_vmcs12(vcpu))) + offset;
7422
7423 switch (vmcs_field_type(field)) {
7424 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7425 *ret = *((natural_width *)p);
a2ae9df7 7426 return 0;
49f705c5
NHE		 7427 case VMCS_FIELD_TYPE_U16:
7428 *ret = *((u16 *)p);
a2ae9df7 7429 return 0;
49f705c5
NHE		 7430 case VMCS_FIELD_TYPE_U32:
7431 *ret = *((u32 *)p);
a2ae9df7 7432 return 0;
49f705c5
NHE		 7433 case VMCS_FIELD_TYPE_U64:
7434 *ret = *((u64 *)p);
a2ae9df7 7435 return 0;
49f705c5 7436 default:
a2ae9df7
PB		 7437 WARN_ON(1);
7438 return -ENOENT;
49f705c5
NHE		 7439 }
7440}
7441
20b97fea 7442
a2ae9df7
PB		 7443static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7444 unsigned long field, u64 field_value){
20b97fea
AG		 7445 short offset = vmcs_field_to_offset(field);
7446 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7447 if (offset < 0)
a2ae9df7 7448 return offset;
20b97fea
AG		 7449
7450 switch (vmcs_field_type(field)) {
7451 case VMCS_FIELD_TYPE_U16:
7452 *(u16 *)p = field_value;
a2ae9df7 7453 return 0;
20b97fea
AG		 7454 case VMCS_FIELD_TYPE_U32:
7455 *(u32 *)p = field_value;
a2ae9df7 7456 return 0;
20b97fea
AG		 7457 case VMCS_FIELD_TYPE_U64:
7458 *(u64 *)p = field_value;
a2ae9df7 7459 return 0;
20b97fea
AG		 7460 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7461 *(natural_width *)p = field_value;
a2ae9df7 7462 return 0;
20b97fea 7463 default:
a2ae9df7
PB		 7464 WARN_ON(1);
7465 return -ENOENT;
20b97fea
AG		 7466 }
7467
7468}
7469
16f5b903
AG		 7470static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7471{
7472 int i;
7473 unsigned long field;
7474 u64 field_value;
355f4fb1 7475 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
c2bae893
MK		 7476 const unsigned long *fields = shadow_read_write_fields;
7477 const int num_fields = max_shadow_read_write_fields;
16f5b903 7478
282da870
JK		 7479 preempt_disable();
7480
16f5b903
AG		 7481 vmcs_load(shadow_vmcs);
7482
7483 for (i = 0; i < num_fields; i++) {
7484 field = fields[i];
7485 switch (vmcs_field_type(field)) {
7486 case VMCS_FIELD_TYPE_U16:
7487 field_value = vmcs_read16(field);
7488 break;
7489 case VMCS_FIELD_TYPE_U32:
7490 field_value = vmcs_read32(field);
7491 break;
7492 case VMCS_FIELD_TYPE_U64:
7493 field_value = vmcs_read64(field);
7494 break;
7495 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7496 field_value = vmcs_readl(field);
7497 break;
a2ae9df7
PB		 7498 default:
7499 WARN_ON(1);
7500 continue;
16f5b903
AG		 7501 }
7502 vmcs12_write_any(&vmx->vcpu, field, field_value);
7503 }
7504
7505 vmcs_clear(shadow_vmcs);
7506 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 7507
7508 preempt_enable();
16f5b903
AG		 7509}
7510
c3114420
AG		 7511static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7512{
c2bae893
MK		 7513 const unsigned long *fields[] = {
7514 shadow_read_write_fields,
7515 shadow_read_only_fields
c3114420 7516 };
c2bae893 7517 const int max_fields[] = {
c3114420
AG		 7518 max_shadow_read_write_fields,
7519 max_shadow_read_only_fields
7520 };
7521 int i, q;
7522 unsigned long field;
7523 u64 field_value = 0;
355f4fb1 7524 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
c3114420
AG		 7525
7526 vmcs_load(shadow_vmcs);
7527
c2bae893 7528 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 7529 for (i = 0; i < max_fields[q]; i++) {
7530 field = fields[q][i];
7531 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7532
7533 switch (vmcs_field_type(field)) {
7534 case VMCS_FIELD_TYPE_U16:
7535 vmcs_write16(field, (u16)field_value);
7536 break;
7537 case VMCS_FIELD_TYPE_U32:
7538 vmcs_write32(field, (u32)field_value);
7539 break;
7540 case VMCS_FIELD_TYPE_U64:
7541 vmcs_write64(field, (u64)field_value);
7542 break;
7543 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7544 vmcs_writel(field, (long)field_value);
7545 break;
a2ae9df7
PB		 7546 default:
7547 WARN_ON(1);
7548 break;
c3114420
AG		 7549 }
7550 }
7551 }
7552
7553 vmcs_clear(shadow_vmcs);
7554 vmcs_load(vmx->loaded_vmcs->vmcs);
7555}
7556
49f705c5
NHE		 7557/*
7558 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7559 * used before) all generate the same failure when it is missing.
7560 */
7561static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7562{
7563 struct vcpu_vmx *vmx = to_vmx(vcpu);
7564 if (vmx->nested.current_vmptr == -1ull) {
7565 nested_vmx_failInvalid(vcpu);
49f705c5
NHE		 7566 return 0;
7567 }
7568 return 1;
7569}
7570
7571static int handle_vmread(struct kvm_vcpu *vcpu)
7572{
7573 unsigned long field;
7574 u64 field_value;
7575 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7576 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7577 gva_t gva = 0;
7578
eb277562 7579 if (!nested_vmx_check_permission(vcpu))
49f705c5
NHE		 7580 return 1;
7581
6affcbed
KH		 7582 if (!nested_vmx_check_vmcs12(vcpu))
7583 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE		 7584
7585 /* Decode instruction info and find the field to read */
27e6fb5d 7586 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 7587 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 7588 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5 7589 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6affcbed 7590 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE		 7591 }
7592 /*
7593 * Now copy part of this value to register or memory, as requested.
7594 * Note that the number of bits actually copied is 32 or 64 depending
7595 * on the guest's mode (32 or 64 bit), not on the given field's length.
7596 */
7597 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 7598 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 7599 field_value);
7600 } else {
7601 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7602 vmx_instruction_info, true, &gva))
49f705c5
NHE		 7603 return 1;
7604 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7605 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7606 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7607 }
7608
7609 nested_vmx_succeed(vcpu);
6affcbed 7610 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE		 7611}
7612
7613
7614static int handle_vmwrite(struct kvm_vcpu *vcpu)
7615{
7616 unsigned long field;
7617 gva_t gva;
7618 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7619 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 7620 /* The value to write might be 32 or 64 bits, depending on L1's long
7621 * mode, and eventually we need to write that into a field of several
7622 * possible lengths. The code below first zero-extends the value to 64
6a6256f9 7623 * bit (field_value), and then copies only the appropriate number of
49f705c5
NHE		 7624 * bits into the vmcs12 field.
7625 */
7626 u64 field_value = 0;
7627 struct x86_exception e;
7628
eb277562 7629 if (!nested_vmx_check_permission(vcpu))
49f705c5
NHE		 7630 return 1;
7631
6affcbed
KH		 7632 if (!nested_vmx_check_vmcs12(vcpu))
7633 return kvm_skip_emulated_instruction(vcpu);
eb277562 7634
49f705c5 7635 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7636 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 7637 (((vmx_instruction_info) >> 3) & 0xf));
7638 else {
7639 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7640 vmx_instruction_info, false, &gva))
49f705c5
NHE		 7641 return 1;
7642 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7643 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 7644 kvm_inject_page_fault(vcpu, &e);
7645 return 1;
7646 }
7647 }
7648
7649
27e6fb5d 7650 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 7651 if (vmcs_field_readonly(field)) {
7652 nested_vmx_failValid(vcpu,
7653 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6affcbed 7654 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE		 7655 }
7656
a2ae9df7 7657 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5 7658 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6affcbed 7659 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE		 7660 }
7661
7662 nested_vmx_succeed(vcpu);
6affcbed 7663 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE		 7664}
7665
63846663
NHE		 7666/* Emulate the VMPTRLD instruction */
7667static int handle_vmptrld(struct kvm_vcpu *vcpu)
7668{
7669 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7670 gpa_t vmptr;
63846663
NHE		 7671
7672 if (!nested_vmx_check_permission(vcpu))
7673 return 1;
7674
4291b588 7675 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 7676 return 1;
63846663
NHE		 7677
7678 if (vmx->nested.current_vmptr != vmptr) {
7679 struct vmcs12 *new_vmcs12;
7680 struct page *page;
7681 page = nested_get_page(vcpu, vmptr);
7682 if (page == NULL) {
7683 nested_vmx_failInvalid(vcpu);
6affcbed 7684 return kvm_skip_emulated_instruction(vcpu);
63846663
NHE		 7685 }
7686 new_vmcs12 = kmap(page);
7687 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7688 kunmap(page);
7689 nested_release_page_clean(page);
7690 nested_vmx_failValid(vcpu,
7691 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6affcbed 7692 return kvm_skip_emulated_instruction(vcpu);
63846663 7693 }
63846663 7694
9a2a05b9 7695 nested_release_vmcs12(vmx);
63846663
NHE		 7696 vmx->nested.current_vmptr = vmptr;
7697 vmx->nested.current_vmcs12 = new_vmcs12;
7698 vmx->nested.current_vmcs12_page = page;
4f2777bc
DM		 7699 /*
7700 * Load VMCS12 from guest memory since it is not already
7701 * cached.
7702 */
7703 memcpy(vmx->nested.cached_vmcs12,
7704 vmx->nested.current_vmcs12, VMCS12_SIZE);
7705
012f83cb 7706 if (enable_shadow_vmcs) {
7ec36296
XG		 7707 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7708 SECONDARY_EXEC_SHADOW_VMCS);
8a1b9dd0 7709 vmcs_write64(VMCS_LINK_POINTER,
355f4fb1 7710 __pa(vmx->vmcs01.shadow_vmcs));
012f83cb
AG		 7711 vmx->nested.sync_shadow_vmcs = true;
7712 }
63846663
NHE		 7713 }
7714
7715 nested_vmx_succeed(vcpu);
6affcbed 7716 return kvm_skip_emulated_instruction(vcpu);
63846663
NHE		 7717}
7718
6a4d7550
NHE		 7719/* Emulate the VMPTRST instruction */
7720static int handle_vmptrst(struct kvm_vcpu *vcpu)
7721{
7722 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7723 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7724 gva_t vmcs_gva;
7725 struct x86_exception e;
7726
7727 if (!nested_vmx_check_permission(vcpu))
7728 return 1;
7729
7730 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7731 vmx_instruction_info, true, &vmcs_gva))
6a4d7550
NHE		 7732 return 1;
7733 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7734 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7735 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7736 sizeof(u64), &e)) {
7737 kvm_inject_page_fault(vcpu, &e);
7738 return 1;
7739 }
7740 nested_vmx_succeed(vcpu);
6affcbed 7741 return kvm_skip_emulated_instruction(vcpu);
6a4d7550
NHE		 7742}
7743
bfd0a56b
NHE		 7744/* Emulate the INVEPT instruction */
7745static int handle_invept(struct kvm_vcpu *vcpu)
7746{
b9c237bb 7747 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7748 u32 vmx_instruction_info, types;
7749 unsigned long type;
7750 gva_t gva;
7751 struct x86_exception e;
7752 struct {
7753 u64 eptp, gpa;
7754 } operand;
bfd0a56b 7755
b9c237bb
WV		 7756 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7757 SECONDARY_EXEC_ENABLE_EPT) ||
7758 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7759 kvm_queue_exception(vcpu, UD_VECTOR);
7760 return 1;
7761 }
7762
7763 if (!nested_vmx_check_permission(vcpu))
7764 return 1;
7765
7766 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7767 kvm_queue_exception(vcpu, UD_VECTOR);
7768 return 1;
7769 }
7770
7771 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7772 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7773
b9c237bb 7774 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b 7775
85c856b3 7776 if (type >= 32 || !(types & (1 << type))) {
bfd0a56b
NHE		 7777 nested_vmx_failValid(vcpu,
7778 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7779 return kvm_skip_emulated_instruction(vcpu);
bfd0a56b
NHE		 7780 }
7781
7782 /* According to the Intel VMX instruction reference, the memory
7783 * operand is read even if it isn't needed (e.g., for type==global)
7784 */
7785 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7786 vmx_instruction_info, false, &gva))
bfd0a56b
NHE		 7787 return 1;
7788 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7789 sizeof(operand), &e)) {
7790 kvm_inject_page_fault(vcpu, &e);
7791 return 1;
7792 }
7793
7794 switch (type) {
bfd0a56b 7795 case VMX_EPT_EXTENT_GLOBAL:
45e11817
BD		 7796 /*
7797 * TODO: track mappings and invalidate
7798 * single context requests appropriately
7799 */
7800 case VMX_EPT_EXTENT_CONTEXT:
bfd0a56b 7801 kvm_mmu_sync_roots(vcpu);
77c3913b 7802 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7803 nested_vmx_succeed(vcpu);
7804 break;
7805 default:
7806 BUG_ON(1);
7807 break;
7808 }
7809
6affcbed 7810 return kvm_skip_emulated_instruction(vcpu);
bfd0a56b
NHE		 7811}
7812
a642fc30
PM		 7813static int handle_invvpid(struct kvm_vcpu *vcpu)
7814{
99b83ac8
WL		 7815 struct vcpu_vmx *vmx = to_vmx(vcpu);
7816 u32 vmx_instruction_info;
7817 unsigned long type, types;
7818 gva_t gva;
7819 struct x86_exception e;
7820 int vpid;
7821
7822 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7823 SECONDARY_EXEC_ENABLE_VPID) ||
7824 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7825 kvm_queue_exception(vcpu, UD_VECTOR);
7826 return 1;
7827 }
7828
7829 if (!nested_vmx_check_permission(vcpu))
7830 return 1;
7831
7832 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7833 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7834
bcdde302
JD		 7835 types = (vmx->nested.nested_vmx_vpid_caps &
7836 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
99b83ac8 7837
85c856b3 7838 if (type >= 32 || !(types & (1 << type))) {
99b83ac8
WL		 7839 nested_vmx_failValid(vcpu,
7840 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7841 return kvm_skip_emulated_instruction(vcpu);
99b83ac8
WL		 7842 }
7843
7844 /* according to the intel vmx instruction reference, the memory
7845 * operand is read even if it isn't needed (e.g., for type==global)
7846 */
7847 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7848 vmx_instruction_info, false, &gva))
7849 return 1;
7850 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7851 sizeof(u32), &e)) {
7852 kvm_inject_page_fault(vcpu, &e);
7853 return 1;
7854 }
7855
7856 switch (type) {
bcdde302 7857 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
ef697a71 7858 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
bcdde302
JD		 7859 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7860 if (!vpid) {
7861 nested_vmx_failValid(vcpu,
7862 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7863 return kvm_skip_emulated_instruction(vcpu);
bcdde302
JD		 7864 }
7865 break;
99b83ac8 7866 case VMX_VPID_EXTENT_ALL_CONTEXT:
99b83ac8
WL		 7867 break;
7868 default:
bcdde302 7869 WARN_ON_ONCE(1);
6affcbed 7870 return kvm_skip_emulated_instruction(vcpu);
99b83ac8
WL		 7871 }
7872
bcdde302
JD		 7873 __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7874 nested_vmx_succeed(vcpu);
7875
6affcbed 7876 return kvm_skip_emulated_instruction(vcpu);
a642fc30
PM		 7877}
7878
843e4330
KH		 7879static int handle_pml_full(struct kvm_vcpu *vcpu)
7880{
7881 unsigned long exit_qualification;
7882
7883 trace_kvm_pml_full(vcpu->vcpu_id);
7884
7885 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7886
7887 /*
7888 * PML buffer FULL happened while executing iret from NMI,
7889 * "blocked by NMI" bit has to be set before next VM entry.
7890 */
7891 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7892 cpu_has_virtual_nmis() &&
7893 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7894 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7895 GUEST_INTR_STATE_NMI);
7896
7897 /*
7898 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7899 * here.., and there's no userspace involvement needed for PML.
7900 */
7901 return 1;
7902}
7903
64672c95
YJ		 7904static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7905{
7906 kvm_lapic_expired_hv_timer(vcpu);
7907 return 1;
7908}
7909
6aa8b732
AK		 7910/*
7911 * The exit handlers return 1 if the exit was handled fully and guest execution
7912 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7913 * to be done to userspace and return 0.
7914 */
772e0318 7915static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7916 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7917 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7918 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7919 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7920 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7921 [EXIT_REASON_CR_ACCESS] = handle_cr,
7922 [EXIT_REASON_DR_ACCESS] = handle_dr,
7923 [EXIT_REASON_CPUID] = handle_cpuid,
7924 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7925 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7926 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7927 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7928 [EXIT_REASON_INVD] = handle_invd,
a7052897 7929 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7930 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7931 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7932 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7933 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7934 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7935 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7936 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7937 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7938 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7939 [EXIT_REASON_VMOFF] = handle_vmoff,
7940 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7941 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7942 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7943 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7944 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7945 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7946 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7947 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7948 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7949 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7950 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7951 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7952 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7953 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7954 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7955 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7956 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7957 [EXIT_REASON_XSAVES] = handle_xsaves,
7958 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7959 [EXIT_REASON_PML_FULL] = handle_pml_full,
64672c95 7960 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
6aa8b732
AK		 7961};
7962
7963static const int kvm_vmx_max_exit_handlers =
50a3485c 7964 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7965
908a7bdd
JK		 7966static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7967 struct vmcs12 *vmcs12)
7968{
7969 unsigned long exit_qualification;
7970 gpa_t bitmap, last_bitmap;
7971 unsigned int port;
7972 int size;
7973 u8 b;
7974
908a7bdd 7975 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7976 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7977
7978 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7979
7980 port = exit_qualification >> 16;
7981 size = (exit_qualification & 7) + 1;
7982
7983 last_bitmap = (gpa_t)-1;
7984 b = -1;
7985
7986 while (size > 0) {
7987 if (port < 0x8000)
7988 bitmap = vmcs12->io_bitmap_a;
7989 else if (port < 0x10000)
7990 bitmap = vmcs12->io_bitmap_b;
7991 else
1d804d07 7992 return true;
908a7bdd
JK		 7993 bitmap += (port & 0x7fff) / 8;
7994
7995 if (last_bitmap != bitmap)
54bf36aa 7996 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7997 return true;
908a7bdd 7998 if (b & (1 << (port & 7)))
1d804d07 7999 return true;
908a7bdd
JK		 8000
8001 port++;
8002 size--;
8003 last_bitmap = bitmap;
8004 }
8005
1d804d07 8006 return false;
908a7bdd
JK		 8007}
8008
644d711a
NHE		 8009/*
8010 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8011 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8012 * disinterest in the current event (read or write a specific MSR) by using an
8013 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8014 */
8015static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8016 struct vmcs12 *vmcs12, u32 exit_reason)
8017{
8018 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8019 gpa_t bitmap;
8020
cbd29cb6 8021 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 8022 return true;
644d711a
NHE		 8023
8024 /*
8025 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8026 * for the four combinations of read/write and low/high MSR numbers.
8027 * First we need to figure out which of the four to use:
8028 */
8029 bitmap = vmcs12->msr_bitmap;
8030 if (exit_reason == EXIT_REASON_MSR_WRITE)
8031 bitmap += 2048;
8032 if (msr_index >= 0xc0000000) {
8033 msr_index -= 0xc0000000;
8034 bitmap += 1024;
8035 }
8036
8037 /* Then read the msr_index'th bit from this bitmap: */
8038 if (msr_index < 1024*8) {
8039 unsigned char b;
54bf36aa 8040 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 8041 return true;
644d711a
NHE		 8042 return 1 & (b >> (msr_index & 7));
8043 } else
1d804d07 8044 return true; /* let L1 handle the wrong parameter */
644d711a
NHE		 8045}
8046
8047/*
8048 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8049 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8050 * intercept (via guest_host_mask etc.) the current event.
8051 */
8052static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8053 struct vmcs12 *vmcs12)
8054{
8055 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8056 int cr = exit_qualification & 15;
8057 int reg = (exit_qualification >> 8) & 15;
1e32c079 8058 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 8059
8060 switch ((exit_qualification >> 4) & 3) {
8061 case 0: /* mov to cr */
8062 switch (cr) {
8063 case 0:
8064 if (vmcs12->cr0_guest_host_mask &
8065 (val ^ vmcs12->cr0_read_shadow))
1d804d07 8066 return true;
644d711a
NHE		 8067 break;
8068 case 3:
8069 if ((vmcs12->cr3_target_count >= 1 &&
8070 vmcs12->cr3_target_value0 == val) ||
8071 (vmcs12->cr3_target_count >= 2 &&
8072 vmcs12->cr3_target_value1 == val) ||
8073 (vmcs12->cr3_target_count >= 3 &&
8074 vmcs12->cr3_target_value2 == val) ||
8075 (vmcs12->cr3_target_count >= 4 &&
8076 vmcs12->cr3_target_value3 == val))
1d804d07 8077 return false;
644d711a 8078 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 8079 return true;
644d711a
NHE		 8080 break;
8081 case 4:
8082 if (vmcs12->cr4_guest_host_mask &
8083 (vmcs12->cr4_read_shadow ^ val))
1d804d07 8084 return true;
644d711a
NHE		 8085 break;
8086 case 8:
8087 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 8088 return true;
644d711a
NHE		 8089 break;
8090 }
8091 break;
8092 case 2: /* clts */
8093 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8094 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 8095 return true;
644d711a
NHE		 8096 break;
8097 case 1: /* mov from cr */
8098 switch (cr) {
8099 case 3:
8100 if (vmcs12->cpu_based_vm_exec_control &
8101 CPU_BASED_CR3_STORE_EXITING)
1d804d07 8102 return true;
644d711a
NHE		 8103 break;
8104 case 8:
8105 if (vmcs12->cpu_based_vm_exec_control &
8106 CPU_BASED_CR8_STORE_EXITING)
1d804d07 8107 return true;
644d711a
NHE		 8108 break;
8109 }
8110 break;
8111 case 3: /* lmsw */
8112 /*
8113 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8114 * cr0. Other attempted changes are ignored, with no exit.
8115 */
8116 if (vmcs12->cr0_guest_host_mask & 0xe &
8117 (val ^ vmcs12->cr0_read_shadow))
1d804d07 8118 return true;
644d711a
NHE		 8119 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8120 !(vmcs12->cr0_read_shadow & 0x1) &&
8121 (val & 0x1))
1d804d07 8122 return true;
644d711a
NHE		 8123 break;
8124 }
1d804d07 8125 return false;
644d711a
NHE		 8126}
8127
8128/*
8129 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8130 * should handle it ourselves in L0 (and then continue L2). Only call this
8131 * when in is_guest_mode (L2).
8132 */
8133static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8134{
644d711a
NHE		 8135 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8136 struct vcpu_vmx *vmx = to_vmx(vcpu);
8137 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 8138 u32 exit_reason = vmx->exit_reason;
644d711a 8139
542060ea
JK		 8140 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8141 vmcs_readl(EXIT_QUALIFICATION),
8142 vmx->idt_vectoring_info,
8143 intr_info,
8144 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8145 KVM_ISA_VMX);
8146
644d711a 8147 if (vmx->nested.nested_run_pending)
1d804d07 8148 return false;
644d711a
NHE		 8149
8150 if (unlikely(vmx->fail)) {
bd80158a
JK		 8151 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8152 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 8153 return true;
644d711a
NHE		 8154 }
8155
8156 switch (exit_reason) {
8157 case EXIT_REASON_EXCEPTION_NMI:
ef85b673 8158 if (is_nmi(intr_info))
1d804d07 8159 return false;
644d711a
NHE		 8160 else if (is_page_fault(intr_info))
8161 return enable_ept;
e504c909 8162 else if (is_no_device(intr_info) &&
ccf9844e 8163 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 8164 return false;
6f05485d
JK		 8165 else if (is_debug(intr_info) &&
8166 vcpu->guest_debug &
8167 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8168 return false;
8169 else if (is_breakpoint(intr_info) &&
8170 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8171 return false;
644d711a
NHE		 8172 return vmcs12->exception_bitmap &
8173 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8174 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 8175 return false;
644d711a 8176 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 8177 return true;
644d711a 8178 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 8179 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 8180 case EXIT_REASON_NMI_WINDOW:
3b656cf7 8181 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 8182 case EXIT_REASON_TASK_SWITCH:
1d804d07 8183 return true;
644d711a 8184 case EXIT_REASON_CPUID:
1d804d07 8185 return true;
644d711a
NHE		 8186 case EXIT_REASON_HLT:
8187 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8188 case EXIT_REASON_INVD:
1d804d07 8189 return true;
644d711a
NHE		 8190 case EXIT_REASON_INVLPG:
8191 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8192 case EXIT_REASON_RDPMC:
8193 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
b3a2a907 8194 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE		 8195 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8196 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8197 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8198 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8199 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8200 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 8201 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 8202 /*
8203 * VMX instructions trap unconditionally. This allows L1 to
8204 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8205 */
1d804d07 8206 return true;
644d711a
NHE		 8207 case EXIT_REASON_CR_ACCESS:
8208 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8209 case EXIT_REASON_DR_ACCESS:
8210 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8211 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 8212 return nested_vmx_exit_handled_io(vcpu, vmcs12);
1b07304c
PB		 8213 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8214 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
644d711a
NHE		 8215 case EXIT_REASON_MSR_READ:
8216 case EXIT_REASON_MSR_WRITE:
8217 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8218 case EXIT_REASON_INVALID_STATE:
1d804d07 8219 return true;
644d711a
NHE		 8220 case EXIT_REASON_MWAIT_INSTRUCTION:
8221 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD		 8222 case EXIT_REASON_MONITOR_TRAP_FLAG:
8223 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE		 8224 case EXIT_REASON_MONITOR_INSTRUCTION:
8225 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8226 case EXIT_REASON_PAUSE_INSTRUCTION:
8227 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8228 nested_cpu_has2(vmcs12,
8229 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8230 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 8231 return false;
644d711a 8232 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 8233 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 8234 case EXIT_REASON_APIC_ACCESS:
8235 return nested_cpu_has2(vmcs12,
8236 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 8237 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 8238 case EXIT_REASON_EOI_INDUCED:
8239 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 8240 return true;
644d711a 8241 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 8242 /*
8243 * L0 always deals with the EPT violation. If nested EPT is
8244 * used, and the nested mmu code discovers that the address is
8245 * missing in the guest EPT table (EPT12), the EPT violation
8246 * will be injected with nested_ept_inject_page_fault()
8247 */
1d804d07 8248 return false;
644d711a 8249 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 8250 /*
8251 * L2 never uses directly L1's EPT, but rather L0's own EPT
8252 * table (shadow on EPT) or a merged EPT table that L0 built
8253 * (EPT on EPT). So any problems with the structure of the
8254 * table is L0's fault.
8255 */
1d804d07 8256 return false;
644d711a
NHE		 8257 case EXIT_REASON_WBINVD:
8258 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8259 case EXIT_REASON_XSETBV:
1d804d07 8260 return true;
81dc01f7
WL		 8261 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8262 /*
8263 * This should never happen, since it is not possible to
8264 * set XSS to a non-zero value---neither in L1 nor in L2.
8265 * If if it were, XSS would have to be checked against
8266 * the XSS exit bitmap in vmcs12.
8267 */
8268 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
55123e3c
WL		 8269 case EXIT_REASON_PREEMPTION_TIMER:
8270 return false;
644d711a 8271 default:
1d804d07 8272 return true;
644d711a
NHE		 8273 }
8274}
8275
586f9607
AK		 8276static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8277{
8278 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8279 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8280}
8281
a3eaa864 8282static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
843e4330 8283{
a3eaa864
KH		 8284 if (vmx->pml_pg) {
8285 __free_page(vmx->pml_pg);
8286 vmx->pml_pg = NULL;
8287 }
843e4330
KH		 8288}
8289
54bf36aa 8290static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 8291{
54bf36aa 8292 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH		 8293 u64 *pml_buf;
8294 u16 pml_idx;
8295
8296 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8297
8298 /* Do nothing if PML buffer is empty */
8299 if (pml_idx == (PML_ENTITY_NUM - 1))
8300 return;
8301
8302 /* PML index always points to next available PML buffer entity */
8303 if (pml_idx >= PML_ENTITY_NUM)
8304 pml_idx = 0;
8305 else
8306 pml_idx++;
8307
8308 pml_buf = page_address(vmx->pml_pg);
8309 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8310 u64 gpa;
8311
8312 gpa = pml_buf[pml_idx];
8313 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 8314 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH		 8315 }
8316
8317 /* reset PML index */
8318 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8319}
8320
8321/*
8322 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8323 * Called before reporting dirty_bitmap to userspace.
8324 */
8325static void kvm_flush_pml_buffers(struct kvm *kvm)
8326{
8327 int i;
8328 struct kvm_vcpu *vcpu;
8329 /*
8330 * We only need to kick vcpu out of guest mode here, as PML buffer
8331 * is flushed at beginning of all VMEXITs, and it's obvious that only
8332 * vcpus running in guest are possible to have unflushed GPAs in PML
8333 * buffer.
8334 */
8335 kvm_for_each_vcpu(i, vcpu, kvm)
8336 kvm_vcpu_kick(vcpu);
8337}
8338
4eb64dce
PB		 8339static void vmx_dump_sel(char *name, uint32_t sel)
8340{
8341 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8342 name, vmcs_read32(sel),
8343 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8344 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8345 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8346}
8347
8348static void vmx_dump_dtsel(char *name, uint32_t limit)
8349{
8350 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8351 name, vmcs_read32(limit),
8352 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8353}
8354
8355static void dump_vmcs(void)
8356{
8357 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8358 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8359 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8360 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8361 u32 secondary_exec_control = 0;
8362 unsigned long cr4 = vmcs_readl(GUEST_CR4);
f3531054 8363 u64 efer = vmcs_read64(GUEST_IA32_EFER);
4eb64dce
PB		 8364 int i, n;
8365
8366 if (cpu_has_secondary_exec_ctrls())
8367 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8368
8369 pr_err("*** Guest State ***\n");
8370 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8371 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8372 vmcs_readl(CR0_GUEST_HOST_MASK));
8373 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8374 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8375 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8376 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8377 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8378 {
845c5b40
PB		 8379 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8380 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8381 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8382 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
4eb64dce
PB		 8383 }
8384 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8385 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8386 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8387 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8388 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8389 vmcs_readl(GUEST_SYSENTER_ESP),
8390 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8391 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8392 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8393 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8394 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8395 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8396 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8397 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8398 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8399 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8400 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8401 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8402 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
845c5b40
PB		 8403 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8404 efer, vmcs_read64(GUEST_IA32_PAT));
8405 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8406 vmcs_read64(GUEST_IA32_DEBUGCTL),
4eb64dce
PB		 8407 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8408 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
845c5b40
PB		 8409 pr_err("PerfGlobCtl = 0x%016llx\n",
8410 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
4eb64dce 8411 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
845c5b40 8412 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
4eb64dce
PB		 8413 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8414 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8415 vmcs_read32(GUEST_ACTIVITY_STATE));
8416 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8417 pr_err("InterruptStatus = %04x\n",
8418 vmcs_read16(GUEST_INTR_STATUS));
8419
8420 pr_err("*** Host State ***\n");
8421 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8422 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8423 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8424 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8425 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8426 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8427 vmcs_read16(HOST_TR_SELECTOR));
8428 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8429 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8430 vmcs_readl(HOST_TR_BASE));
8431 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8432 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8433 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8434 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8435 vmcs_readl(HOST_CR4));
8436 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8437 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8438 vmcs_read32(HOST_IA32_SYSENTER_CS),
8439 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8440 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
845c5b40
PB		 8441 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8442 vmcs_read64(HOST_IA32_EFER),
8443 vmcs_read64(HOST_IA32_PAT));
4eb64dce 8444 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
845c5b40
PB		 8445 pr_err("PerfGlobCtl = 0x%016llx\n",
8446 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
4eb64dce
PB		 8447
8448 pr_err("*** Control State ***\n");
8449 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8450 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8451 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8452 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8453 vmcs_read32(EXCEPTION_BITMAP),
8454 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8455 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8456 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8457 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8458 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8459 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8460 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8461 vmcs_read32(VM_EXIT_INTR_INFO),
8462 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8463 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8464 pr_err(" reason=%08x qualification=%016lx\n",
8465 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8466 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8467 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8468 vmcs_read32(IDT_VECTORING_ERROR_CODE));
845c5b40 8469 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8cfe9866 8470 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
845c5b40
PB		 8471 pr_err("TSC Multiplier = 0x%016llx\n",
8472 vmcs_read64(TSC_MULTIPLIER));
4eb64dce
PB		 8473 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8474 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8475 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8476 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8477 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
845c5b40 8478 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
4eb64dce
PB		 8479 n = vmcs_read32(CR3_TARGET_COUNT);
8480 for (i = 0; i + 1 < n; i += 4)
8481 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8482 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8483 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8484 if (i < n)
8485 pr_err("CR3 target%u=%016lx\n",
8486 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8487 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8488 pr_err("PLE Gap=%08x Window=%08x\n",
8489 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8490 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8491 pr_err("Virtual processor ID = 0x%04x\n",
8492 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8493}
8494
6aa8b732
AK		 8495/*
8496 * The guest has exited. See if we can fix it or if we need userspace
8497 * assistance.
8498 */
851ba692 8499static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 8500{
29bd8a78 8501 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 8502 u32 exit_reason = vmx->exit_reason;
1155f76a 8503 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 8504
8b89fe1f 8505 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
db1c056c 8506 vcpu->arch.gpa_available = false;
8b89fe1f 8507
843e4330
KH		 8508 /*
8509 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8510 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8511 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8512 * mode as if vcpus is in root mode, the PML buffer must has been
8513 * flushed already.
8514 */
8515 if (enable_pml)
54bf36aa 8516 vmx_flush_pml_buffer(vcpu);
843e4330 8517
80ced186 8518 /* If guest state is invalid, start emulating */
14168786 8519 if (vmx->emulation_required)
80ced186 8520 return handle_invalid_guest_state(vcpu);
1d5a4d9b 8521
644d711a 8522 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 8523 nested_vmx_vmexit(vcpu, exit_reason,
8524 vmcs_read32(VM_EXIT_INTR_INFO),
8525 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 8526 return 1;
8527 }
8528
5120702e 8529 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 8530 dump_vmcs();
5120702e
MG		 8531 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8532 vcpu->run->fail_entry.hardware_entry_failure_reason
8533 = exit_reason;
8534 return 0;
8535 }
8536
29bd8a78 8537 if (unlikely(vmx->fail)) {
851ba692
AK		 8538 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8539 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 8540 = vmcs_read32(VM_INSTRUCTION_ERROR);
8541 return 0;
8542 }
6aa8b732 8543
b9bf6882
XG		 8544 /*
8545 * Note:
8546 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8547 * delivery event since it indicates guest is accessing MMIO.
8548 * The vm-exit can be triggered again after return to guest that
8549 * will cause infinite loop.
8550 */
d77c26fc 8551 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 8552 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 8553 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b244c9fc 8554 exit_reason != EXIT_REASON_PML_FULL &&
b9bf6882
XG		 8555 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8556 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8557 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8558 vcpu->run->internal.ndata = 2;
8559 vcpu->run->internal.data[0] = vectoring_info;
8560 vcpu->run->internal.data[1] = exit_reason;
8561 return 0;
8562 }
3b86cd99 8563
644d711a
NHE		 8564 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8565 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 8566 get_vmcs12(vcpu))))) {
c4282df9 8567 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 8568 vmx->soft_vnmi_blocked = 0;
3b86cd99 8569 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 8570 vcpu->arch.nmi_pending) {
3b86cd99
JK		 8571 /*
8572 * This CPU don't support us in finding the end of an
8573 * NMI-blocked window if the guest runs with IRQs
8574 * disabled. So we pull the trigger after 1 s of
8575 * futile waiting, but inform the user about this.
8576 */
8577 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8578 "state on VCPU %d after 1 s timeout\n",
8579 __func__, vcpu->vcpu_id);
8580 vmx->soft_vnmi_blocked = 0;
3b86cd99 8581 }
3b86cd99
JK		 8582 }
8583
6aa8b732
AK		 8584 if (exit_reason < kvm_vmx_max_exit_handlers
8585 && kvm_vmx_exit_handlers[exit_reason])
851ba692 8586 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 8587 else {
2bc19dc3
MT		 8588 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8589 kvm_queue_exception(vcpu, UD_VECTOR);
8590 return 1;
6aa8b732 8591 }
6aa8b732
AK		 8592}
8593
95ba8273 8594static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 8595{
a7c0b07d
WL		 8596 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8597
8598 if (is_guest_mode(vcpu) &&
8599 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8600 return;
8601
95ba8273 8602 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 8603 vmcs_write32(TPR_THRESHOLD, 0);
8604 return;
8605 }
8606
95ba8273 8607 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 8608}
8609
8d14695f
YZ		 8610static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8611{
8612 u32 sec_exec_control;
8613
dccbfcf5
RK		 8614 /* Postpone execution until vmcs01 is the current VMCS. */
8615 if (is_guest_mode(vcpu)) {
8616 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8617 return;
8618 }
8619
f6e90f9e 8620 if (!cpu_has_vmx_virtualize_x2apic_mode())
8d14695f
YZ		 8621 return;
8622
35754c98 8623 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ		 8624 return;
8625
8626 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8627
8628 if (set) {
8629 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8630 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8631 } else {
8632 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8633 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8634 }
8635 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8636
8637 vmx_set_msr_bitmap(vcpu);
8638}
8639
38b99173
TC		 8640static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8641{
8642 struct vcpu_vmx *vmx = to_vmx(vcpu);
8643
8644 /*
8645 * Currently we do not handle the nested case where L2 has an
8646 * APIC access page of its own; that page is still pinned.
8647 * Hence, we skip the case where the VCPU is in guest mode _and_
8648 * L1 prepared an APIC access page for L2.
8649 *
8650 * For the case where L1 and L2 share the same APIC access page
8651 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8652 * in the vmcs12), this function will only update either the vmcs01
8653 * or the vmcs02. If the former, the vmcs02 will be updated by
8654 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8655 * the next L2->L1 exit.
8656 */
8657 if (!is_guest_mode(vcpu) ||
4f2777bc 8658 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
38b99173
TC		 8659 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8660 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8661}
8662
67c9dddc 8663static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
c7c9c56c
YZ		 8664{
8665 u16 status;
8666 u8 old;
8667
67c9dddc
PB		 8668 if (max_isr == -1)
8669 max_isr = 0;
c7c9c56c
YZ		 8670
8671 status = vmcs_read16(GUEST_INTR_STATUS);
8672 old = status >> 8;
67c9dddc 8673 if (max_isr != old) {
c7c9c56c 8674 status &= 0xff;
67c9dddc 8675 status |= max_isr << 8;
c7c9c56c
YZ		 8676 vmcs_write16(GUEST_INTR_STATUS, status);
8677 }
8678}
8679
8680static void vmx_set_rvi(int vector)
8681{
8682 u16 status;
8683 u8 old;
8684
4114c27d
WW		 8685 if (vector == -1)
8686 vector = 0;
8687
c7c9c56c
YZ		 8688 status = vmcs_read16(GUEST_INTR_STATUS);
8689 old = (u8)status & 0xff;
8690 if ((u8)vector != old) {
8691 status &= ~0xff;
8692 status |= (u8)vector;
8693 vmcs_write16(GUEST_INTR_STATUS, status);
8694 }
8695}
8696
8697static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8698{
4114c27d
WW		 8699 if (!is_guest_mode(vcpu)) {
8700 vmx_set_rvi(max_irr);
8701 return;
8702 }
8703
c7c9c56c
YZ		 8704 if (max_irr == -1)
8705 return;
8706
963fee16 8707 /*
4114c27d
WW		 8708 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8709 * handles it.
963fee16 8710 */
4114c27d 8711 if (nested_exit_on_intr(vcpu))
963fee16
WL		 8712 return;
8713
963fee16 8714 /*
4114c27d 8715 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 8716 * is run without virtual interrupt delivery.
8717 */
8718 if (!kvm_event_needs_reinjection(vcpu) &&
8719 vmx_interrupt_allowed(vcpu)) {
8720 kvm_queue_interrupt(vcpu, max_irr, false);
8721 vmx_inject_irq(vcpu);
8722 }
c7c9c56c
YZ		 8723}
8724
810e6def
PB		 8725static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8726{
8727 struct vcpu_vmx *vmx = to_vmx(vcpu);
8728
8729 if (!pi_test_on(&vmx->pi_desc))
8730 return;
8731
8732 pi_clear_on(&vmx->pi_desc);
8733 /*
8734 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8735 * But on x86 this is just a compiler barrier anyway.
8736 */
8737 smp_mb__after_atomic();
8738 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8739}
8740
6308630b 8741static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
c7c9c56c 8742{
d62caabb 8743 if (!kvm_vcpu_apicv_active(vcpu))
3d81bc7e
YZ		 8744 return;
8745
c7c9c56c
YZ		 8746 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8747 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8748 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8749 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8750}
8751
967235d3
PB		 8752static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8753{
8754 struct vcpu_vmx *vmx = to_vmx(vcpu);
8755
8756 pi_clear_on(&vmx->pi_desc);
8757 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8758}
8759
51aa01d1 8760static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8761{
00eba012
AK		 8762 u32 exit_intr_info;
8763
8764 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8765 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8766 return;
8767
c5ca8e57 8768 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 8769 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 8770
8771 /* Handle machine checks before interrupts are enabled */
00eba012 8772 if (is_machine_check(exit_intr_info))
a0861c02
AK		 8773 kvm_machine_check();
8774
20f65983 8775 /* We need to handle NMIs before interrupts are enabled */
ef85b673 8776 if (is_nmi(exit_intr_info)) {
ff9d07a0 8777 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8778 asm("int $2");
ff9d07a0
ZY		 8779 kvm_after_handle_nmi(&vmx->vcpu);
8780 }
51aa01d1 8781}
20f65983 8782
a547c6db
YZ		 8783static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8784{
8785 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3f62de5f 8786 register void *__sp asm(_ASM_SP);
a547c6db 8787
a547c6db
YZ		 8788 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8789 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8790 unsigned int vector;
8791 unsigned long entry;
8792 gate_desc *desc;
8793 struct vcpu_vmx *vmx = to_vmx(vcpu);
8794#ifdef CONFIG_X86_64
8795 unsigned long tmp;
8796#endif
8797
8798 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8799 desc = (gate_desc *)vmx->host_idt_base + vector;
8800 entry = gate_offset(*desc);
8801 asm volatile(
8802#ifdef CONFIG_X86_64
8803 "mov %%" _ASM_SP ", %[sp]\n\t"
8804 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8805 "push $%c[ss]\n\t"
8806 "push %[sp]\n\t"
8807#endif
8808 "pushf\n\t"
a547c6db
YZ		 8809 __ASM_SIZE(push) " $%c[cs]\n\t"
8810 "call *%[entry]\n\t"
8811 :
8812#ifdef CONFIG_X86_64
3f62de5f 8813 [sp]"=&r"(tmp),
a547c6db 8814#endif
3f62de5f 8815 "+r"(__sp)
a547c6db
YZ		 8816 :
8817 [entry]"r"(entry),
8818 [ss]"i"(__KERNEL_DS),
8819 [cs]"i"(__KERNEL_CS)
8820 );
f2485b3e 8821 }
a547c6db
YZ		 8822}
8823
6d396b55
PB		 8824static bool vmx_has_high_real_mode_segbase(void)
8825{
8826 return enable_unrestricted_guest || emulate_invalid_guest_state;
8827}
8828
da8999d3
LJ		 8829static bool vmx_mpx_supported(void)
8830{
8831 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8832 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8833}
8834
55412b2e
WL		 8835static bool vmx_xsaves_supported(void)
8836{
8837 return vmcs_config.cpu_based_2nd_exec_ctrl &
8838 SECONDARY_EXEC_XSAVES;
8839}
8840
51aa01d1
AK		 8841static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8842{
c5ca8e57 8843 u32 exit_intr_info;
51aa01d1
AK		 8844 bool unblock_nmi;
8845 u8 vector;
8846 bool idtv_info_valid;
8847
8848 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8849
cf393f75 8850 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 8851 if (vmx->nmi_known_unmasked)
8852 return;
c5ca8e57
AK		 8853 /*
8854 * Can't use vmx->exit_intr_info since we're not sure what
8855 * the exit reason is.
8856 */
8857 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 8858 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8859 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8860 /*
7b4a25cb 8861 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 8862 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8863 * a guest IRET fault.
7b4a25cb
GN		 8864 * SDM 3: 23.2.2 (September 2008)
8865 * Bit 12 is undefined in any of the following cases:
8866 * If the VM exit sets the valid bit in the IDT-vectoring
8867 * information field.
8868 * If the VM exit is due to a double fault.
cf393f75 8869 */
7b4a25cb
GN		 8870 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8871 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 8872 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8873 GUEST_INTR_STATE_NMI);
9d58b931
AK		 8874 else
8875 vmx->nmi_known_unmasked =
8876 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8877 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 8878 } else if (unlikely(vmx->soft_vnmi_blocked))
8879 vmx->vnmi_blocked_time +=
8880 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 8881}
8882
3ab66e8a 8883static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 8884 u32 idt_vectoring_info,
8885 int instr_len_field,
8886 int error_code_field)
51aa01d1 8887{
51aa01d1
AK		 8888 u8 vector;
8889 int type;
8890 bool idtv_info_valid;
8891
8892 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8893
3ab66e8a
JK		 8894 vcpu->arch.nmi_injected = false;
8895 kvm_clear_exception_queue(vcpu);
8896 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 8897
8898 if (!idtv_info_valid)
8899 return;
8900
3ab66e8a 8901 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8902
668f612f
AK		 8903 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8904 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8905
64a7ec06 8906 switch (type) {
37b96e98 8907 case INTR_TYPE_NMI_INTR:
3ab66e8a 8908 vcpu->arch.nmi_injected = true;
668f612f 8909 /*
7b4a25cb 8910 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 8911 * Clear bit "block by NMI" before VM entry if a NMI
8912 * delivery faulted.
668f612f 8913 */
3ab66e8a 8914 vmx_set_nmi_mask(vcpu, false);
37b96e98 8915 break;
37b96e98 8916 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8917 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 8918 /* fall through */
8919 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8920 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8921 u32 err = vmcs_read32(error_code_field);
851eb667 8922 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8923 } else
851eb667 8924 kvm_requeue_exception(vcpu, vector);
37b96e98 8925 break;
66fd3f7f 8926 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8927 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8928 /* fall through */
37b96e98 8929 case INTR_TYPE_EXT_INTR:
3ab66e8a 8930 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 8931 break;
8932 default:
8933 break;
f7d9238f 8934 }
cf393f75
AK		 8935}
8936
83422e17
AK		 8937static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8938{
3ab66e8a 8939 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8940 VM_EXIT_INSTRUCTION_LEN,
8941 IDT_VECTORING_ERROR_CODE);
8942}
8943
b463a6f7
AK		 8944static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8945{
3ab66e8a 8946 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8947 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8948 VM_ENTRY_INSTRUCTION_LEN,
8949 VM_ENTRY_EXCEPTION_ERROR_CODE);
8950
8951 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8952}
8953
d7cd9796
GN		 8954static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8955{
8956 int i, nr_msrs;
8957 struct perf_guest_switch_msr *msrs;
8958
8959 msrs = perf_guest_get_msrs(&nr_msrs);
8960
8961 if (!msrs)
8962 return;
8963
8964 for (i = 0; i < nr_msrs; i++)
8965 if (msrs[i].host == msrs[i].guest)
8966 clear_atomic_switch_msr(vmx, msrs[i].msr);
8967 else
8968 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8969 msrs[i].host);
8970}
8971
33365e7a 8972static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
64672c95
YJ		 8973{
8974 struct vcpu_vmx *vmx = to_vmx(vcpu);
8975 u64 tscl;
8976 u32 delta_tsc;
8977
8978 if (vmx->hv_deadline_tsc == -1)
8979 return;
8980
8981 tscl = rdtsc();
8982 if (vmx->hv_deadline_tsc > tscl)
8983 /* sure to be 32 bit only because checked on set_hv_timer */
8984 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8985 cpu_preemption_timer_multi);
8986 else
8987 delta_tsc = 0;
8988
8989 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8990}
8991
a3b5ba49 8992static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8993{
a2fa3e9f 8994 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8995 unsigned long debugctlmsr, cr4;
104f226b
AK		 8996
8997 /* Record the guest's net vcpu time for enforced NMI injections. */
8998 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8999 vmx->entry_time = ktime_get();
9000
9001 /* Don't enter VMX if guest state is invalid, let the exit handler
9002 start emulation until we arrive back to a valid state */
14168786 9003 if (vmx->emulation_required)
104f226b
AK		 9004 return;
9005
a7653ecd
RK		 9006 if (vmx->ple_window_dirty) {
9007 vmx->ple_window_dirty = false;
9008 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9009 }
9010
012f83cb
AG		 9011 if (vmx->nested.sync_shadow_vmcs) {
9012 copy_vmcs12_to_shadow(vmx);
9013 vmx->nested.sync_shadow_vmcs = false;
9014 }
9015
104f226b
AK		 9016 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9017 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9018 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9019 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9020
1e02ce4c 9021 cr4 = cr4_read_shadow();
d974baa3
AL		 9022 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
9023 vmcs_writel(HOST_CR4, cr4);
9024 vmx->host_state.vmcs_host_cr4 = cr4;
9025 }
9026
104f226b
AK		 9027 /* When single-stepping over STI and MOV SS, we must clear the
9028 * corresponding interruptibility bits in the guest state. Otherwise
9029 * vmentry fails as it then expects bit 14 (BS) in pending debug
9030 * exceptions being set, but that's not correct for the guest debugging
9031 * case. */
9032 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9033 vmx_set_interrupt_shadow(vcpu, 0);
9034
1be0e61c
XG		 9035 if (vmx->guest_pkru_valid)
9036 __write_pkru(vmx->guest_pkru);
9037
d7cd9796 9038 atomic_switch_perf_msrs(vmx);
2a7921b7 9039 debugctlmsr = get_debugctlmsr();
d7cd9796 9040
64672c95
YJ		 9041 vmx_arm_hv_timer(vcpu);
9042
d462b819 9043 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 9044 asm(
6aa8b732 9045 /* Store host registers */
b188c81f
AK		 9046 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9047 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9048 "push %%" _ASM_CX " \n\t"
9049 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 9050 "je 1f \n\t"
b188c81f 9051 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 9052 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 9053 "1: \n\t"
d3edefc0 9054 /* Reload cr2 if changed */
b188c81f
AK		 9055 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9056 "mov %%cr2, %%" _ASM_DX " \n\t"
9057 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 9058 "je 2f \n\t"
b188c81f 9059 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 9060 "2: \n\t"
6aa8b732 9061 /* Check if vmlaunch of vmresume is needed */
e08aa78a 9062 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 9063 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 9064 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9065 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9066 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9067 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9068 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9069 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 9070#ifdef CONFIG_X86_64
e08aa78a
AK		 9071 "mov %c[r8](%0), %%r8 \n\t"
9072 "mov %c[r9](%0), %%r9 \n\t"
9073 "mov %c[r10](%0), %%r10 \n\t"
9074 "mov %c[r11](%0), %%r11 \n\t"
9075 "mov %c[r12](%0), %%r12 \n\t"
9076 "mov %c[r13](%0), %%r13 \n\t"
9077 "mov %c[r14](%0), %%r14 \n\t"
9078 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 9079#endif
b188c81f 9080 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 9081
6aa8b732 9082 /* Enter guest mode */
83287ea4 9083 "jne 1f \n\t"
4ecac3fd 9084 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 9085 "jmp 2f \n\t"
9086 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9087 "2: "
6aa8b732 9088 /* Save guest registers, load host registers, keep flags */
b188c81f 9089 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 9090 "pop %0 \n\t"
b188c81f
AK		 9091 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9092 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9093 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9094 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9095 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9096 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9097 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 9098#ifdef CONFIG_X86_64
e08aa78a
AK		 9099 "mov %%r8, %c[r8](%0) \n\t"
9100 "mov %%r9, %c[r9](%0) \n\t"
9101 "mov %%r10, %c[r10](%0) \n\t"
9102 "mov %%r11, %c[r11](%0) \n\t"
9103 "mov %%r12, %c[r12](%0) \n\t"
9104 "mov %%r13, %c[r13](%0) \n\t"
9105 "mov %%r14, %c[r14](%0) \n\t"
9106 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 9107#endif
b188c81f
AK		 9108 "mov %%cr2, %%" _ASM_AX " \n\t"
9109 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 9110
b188c81f 9111 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 9112 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 9113 ".pushsection .rodata \n\t"
9114 ".global vmx_return \n\t"
9115 "vmx_return: " _ASM_PTR " 2b \n\t"
9116 ".popsection"
e08aa78a 9117 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 9118 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 9119 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 9120 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 9121 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9122 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9123 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9124 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9125 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9126 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9127 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 9128#ifdef CONFIG_X86_64
ad312c7c
ZX		 9129 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9130 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9131 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9132 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9133 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9134 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9135 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9136 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 9137#endif
40712fae
AK		 9138 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9139 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 9140 : "cc", "memory"
9141#ifdef CONFIG_X86_64
b188c81f 9142 , "rax", "rbx", "rdi", "rsi"
c2036300 9143 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 9144#else
9145 , "eax", "ebx", "edi", "esi"
c2036300
LV		 9146#endif
9147 );
6aa8b732 9148
2a7921b7
GN		 9149 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9150 if (debugctlmsr)
9151 update_debugctlmsr(debugctlmsr);
9152
aa67f609
AK		 9153#ifndef CONFIG_X86_64
9154 /*
9155 * The sysexit path does not restore ds/es, so we must set them to
9156 * a reasonable value ourselves.
9157 *
9158 * We can't defer this to vmx_load_host_state() since that function
9159 * may be executed in interrupt context, which saves and restore segments
9160 * around it, nullifying its effect.
9161 */
9162 loadsegment(ds, __USER_DS);
9163 loadsegment(es, __USER_DS);
9164#endif
9165
6de4f3ad 9166 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 9167 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 9168 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 9169 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 9170 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 9171 vcpu->arch.regs_dirty = 0;
9172
1155f76a
AK		 9173 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9174
d462b819 9175 vmx->loaded_vmcs->launched = 1;
1b6269db 9176
51aa01d1 9177 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1 9178
1be0e61c
XG		 9179 /*
9180 * eager fpu is enabled if PKEY is supported and CR4 is switched
9181 * back on host, so it is safe to read guest PKRU from current
9182 * XSAVE.
9183 */
9184 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9185 vmx->guest_pkru = __read_pkru();
9186 if (vmx->guest_pkru != vmx->host_pkru) {
9187 vmx->guest_pkru_valid = true;
9188 __write_pkru(vmx->host_pkru);
9189 } else
9190 vmx->guest_pkru_valid = false;
9191 }
9192
e0b890d3
GN		 9193 /*
9194 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9195 * we did not inject a still-pending event to L1 now because of
9196 * nested_run_pending, we need to re-enable this bit.
9197 */
9198 if (vmx->nested.nested_run_pending)
9199 kvm_make_request(KVM_REQ_EVENT, vcpu);
9200
9201 vmx->nested.nested_run_pending = 0;
9202
51aa01d1
AK		 9203 vmx_complete_atomic_exit(vmx);
9204 vmx_recover_nmi_blocking(vmx);
cf393f75 9205 vmx_complete_interrupts(vmx);
6aa8b732
AK		 9206}
9207
4fa7734c
PB		 9208static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9209{
9210 struct vcpu_vmx *vmx = to_vmx(vcpu);
9211 int cpu;
9212
9213 if (vmx->loaded_vmcs == &vmx->vmcs01)
9214 return;
9215
9216 cpu = get_cpu();
9217 vmx->loaded_vmcs = &vmx->vmcs01;
9218 vmx_vcpu_put(vcpu);
9219 vmx_vcpu_load(vcpu, cpu);
9220 vcpu->cpu = cpu;
9221 put_cpu();
9222}
9223
2f1fe811
JM		 9224/*
9225 * Ensure that the current vmcs of the logical processor is the
9226 * vmcs01 of the vcpu before calling free_nested().
9227 */
9228static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9229{
9230 struct vcpu_vmx *vmx = to_vmx(vcpu);
9231 int r;
9232
9233 r = vcpu_load(vcpu);
9234 BUG_ON(r);
9235 vmx_load_vmcs01(vcpu);
9236 free_nested(vmx);
9237 vcpu_put(vcpu);
9238}
9239
6aa8b732
AK		 9240static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9241{
fb3f0f51
RR		 9242 struct vcpu_vmx *vmx = to_vmx(vcpu);
9243
843e4330 9244 if (enable_pml)
a3eaa864 9245 vmx_destroy_pml_buffer(vmx);
991e7a0e 9246 free_vpid(vmx->vpid);
4fa7734c 9247 leave_guest_mode(vcpu);
2f1fe811 9248 vmx_free_vcpu_nested(vcpu);
4fa7734c 9249 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 9250 kfree(vmx->guest_msrs);
9251 kvm_vcpu_uninit(vcpu);
a4770347 9252 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 9253}
9254
fb3f0f51 9255static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 9256{
fb3f0f51 9257 int err;
c16f862d 9258 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 9259 int cpu;
6aa8b732 9260
a2fa3e9f 9261 if (!vmx)
fb3f0f51
RR		 9262 return ERR_PTR(-ENOMEM);
9263
991e7a0e 9264 vmx->vpid = allocate_vpid();
2384d2b3 9265
fb3f0f51
RR		 9266 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9267 if (err)
9268 goto free_vcpu;
965b58a5 9269
4e59516a
PF		 9270 err = -ENOMEM;
9271
9272 /*
9273 * If PML is turned on, failure on enabling PML just results in failure
9274 * of creating the vcpu, therefore we can simplify PML logic (by
9275 * avoiding dealing with cases, such as enabling PML partially on vcpus
9276 * for the guest, etc.
9277 */
9278 if (enable_pml) {
9279 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9280 if (!vmx->pml_pg)
9281 goto uninit_vcpu;
9282 }
9283
a2fa3e9f 9284 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 9285 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9286 > PAGE_SIZE);
0123be42 9287
4e59516a
PF		 9288 if (!vmx->guest_msrs)
9289 goto free_pml;
965b58a5 9290
d462b819
NHE		 9291 vmx->loaded_vmcs = &vmx->vmcs01;
9292 vmx->loaded_vmcs->vmcs = alloc_vmcs();
355f4fb1 9293 vmx->loaded_vmcs->shadow_vmcs = NULL;
d462b819 9294 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 9295 goto free_msrs;
d462b819
NHE		 9296 if (!vmm_exclusive)
9297 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9298 loaded_vmcs_init(vmx->loaded_vmcs);
9299 if (!vmm_exclusive)
9300 kvm_cpu_vmxoff();
a2fa3e9f 9301
15ad7146
AK		 9302 cpu = get_cpu();
9303 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 9304 vmx->vcpu.cpu = cpu;
8b9cf98c 9305 err = vmx_vcpu_setup(vmx);
fb3f0f51 9306 vmx_vcpu_put(&vmx->vcpu);
15ad7146 9307 put_cpu();
fb3f0f51
RR		 9308 if (err)
9309 goto free_vmcs;
35754c98 9310 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK		 9311 err = alloc_apic_access_page(kvm);
9312 if (err)
5e4a0b3c 9313 goto free_vmcs;
a63cb560 9314 }
fb3f0f51 9315
b927a3ce
SY		 9316 if (enable_ept) {
9317 if (!kvm->arch.ept_identity_map_addr)
9318 kvm->arch.ept_identity_map_addr =
9319 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 9320 err = init_rmode_identity_map(kvm);
9321 if (err)
93ea5388 9322 goto free_vmcs;
b927a3ce 9323 }
b7ebfb05 9324
5c614b35 9325 if (nested) {
b9c237bb 9326 nested_vmx_setup_ctls_msrs(vmx);
5c614b35
WL		 9327 vmx->nested.vpid02 = allocate_vpid();
9328 }
b9c237bb 9329
705699a1 9330 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE		 9331 vmx->nested.current_vmptr = -1ull;
9332 vmx->nested.current_vmcs12 = NULL;
9333
37e4c997
HZ		 9334 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9335
fb3f0f51
RR		 9336 return &vmx->vcpu;
9337
9338free_vmcs:
5c614b35 9339 free_vpid(vmx->nested.vpid02);
5f3fbc34 9340 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 9341free_msrs:
fb3f0f51 9342 kfree(vmx->guest_msrs);
4e59516a
PF		 9343free_pml:
9344 vmx_destroy_pml_buffer(vmx);
fb3f0f51
RR		 9345uninit_vcpu:
9346 kvm_vcpu_uninit(&vmx->vcpu);
9347free_vcpu:
991e7a0e 9348 free_vpid(vmx->vpid);
a4770347 9349 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 9350 return ERR_PTR(err);
6aa8b732
AK		 9351}
9352
002c7f7c
YS		 9353static void __init vmx_check_processor_compat(void *rtn)
9354{
9355 struct vmcs_config vmcs_conf;
9356
9357 *(int *)rtn = 0;
9358 if (setup_vmcs_config(&vmcs_conf) < 0)
9359 *(int *)rtn = -EIO;
9360 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9361 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9362 smp_processor_id());
9363 *(int *)rtn = -EIO;
9364 }
9365}
9366
67253af5
SY		 9367static int get_ept_level(void)
9368{
9369 return VMX_EPT_DEFAULT_GAW + 1;
9370}
9371
4b12f0de 9372static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 9373{
b18d5431
XG		 9374 u8 cache;
9375 u64 ipat = 0;
4b12f0de 9376
522c68c4 9377 /* For VT-d and EPT combination
606decd6 9378 * 1. MMIO: always map as UC
522c68c4
SY		 9379 * 2. EPT with VT-d:
9380 * a. VT-d without snooping control feature: can't guarantee the
606decd6 9381 * result, try to trust guest.
522c68c4
SY		 9382 * b. VT-d with snooping control feature: snooping control feature of
9383 * VT-d engine can guarantee the cache correctness. Just set it
9384 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 9385 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 9386 * consistent with host MTRR
9387 */
606decd6
PB		 9388 if (is_mmio) {
9389 cache = MTRR_TYPE_UNCACHABLE;
9390 goto exit;
9391 }
9392
9393 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG		 9394 ipat = VMX_EPT_IPAT_BIT;
9395 cache = MTRR_TYPE_WRBACK;
9396 goto exit;
9397 }
9398
9399 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9400 ipat = VMX_EPT_IPAT_BIT;
0da029ed 9401 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG		 9402 cache = MTRR_TYPE_WRBACK;
9403 else
9404 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG		 9405 goto exit;
9406 }
9407
ff53604b 9408 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG		 9409
9410exit:
9411 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY		 9412}
9413
17cc3935 9414static int vmx_get_lpage_level(void)
344f414f 9415{
878403b7
SY		 9416 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9417 return PT_DIRECTORY_LEVEL;
9418 else
9419 /* For shadow and EPT supported 1GB page */
9420 return PT_PDPE_LEVEL;
344f414f
JR		 9421}
9422
feda805f
XG		 9423static void vmcs_set_secondary_exec_control(u32 new_ctl)
9424{
9425 /*
9426 * These bits in the secondary execution controls field
9427 * are dynamic, the others are mostly based on the hypervisor
9428 * architecture and the guest's CPUID. Do not touch the
9429 * dynamic bits.
9430 */
9431 u32 mask =
9432 SECONDARY_EXEC_SHADOW_VMCS |
9433 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9434 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9435
9436 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9437
9438 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9439 (new_ctl & ~mask) | (cur_ctl & mask));
9440}
9441
8322ebbb
DM		 9442/*
9443 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9444 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9445 */
9446static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9447{
9448 struct vcpu_vmx *vmx = to_vmx(vcpu);
9449 struct kvm_cpuid_entry2 *entry;
9450
9451 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9452 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9453
9454#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9455 if (entry && (entry->_reg & (_cpuid_mask))) \
9456 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9457} while (0)
9458
9459 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9460 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
9461 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
9462 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
9463 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
9464 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
9465 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
9466 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
9467 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
9468 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
9469 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9470 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
9471 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
9472 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
9473 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
9474
9475 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9476 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
9477 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
9478 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
9479 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
9480 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9481 cr4_fixed1_update(bit(11), ecx, bit(2));
9482
9483#undef cr4_fixed1_update
9484}
9485
0e851880
SY		 9486static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9487{
4e47c7a6
SY		 9488 struct kvm_cpuid_entry2 *best;
9489 struct vcpu_vmx *vmx = to_vmx(vcpu);
feda805f 9490 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
4e47c7a6 9491
4e47c7a6 9492 if (vmx_rdtscp_supported()) {
1cea0ce6
XG		 9493 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9494 if (!rdtscp_enabled)
feda805f 9495 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
f36201e5 9496
8b97265a 9497 if (nested) {
1cea0ce6 9498 if (rdtscp_enabled)
8b97265a
PB		 9499 vmx->nested.nested_vmx_secondary_ctls_high |=
9500 SECONDARY_EXEC_RDTSCP;
9501 else
9502 vmx->nested.nested_vmx_secondary_ctls_high &=
9503 ~SECONDARY_EXEC_RDTSCP;
9504 }
4e47c7a6 9505 }
ad756a16 9506
ad756a16
MJ		 9507 /* Exposing INVPCID only when PCID is exposed */
9508 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9509 if (vmx_invpcid_supported() &&
29541bb8
XG		 9510 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9511 !guest_cpuid_has_pcid(vcpu))) {
feda805f 9512 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
29541bb8 9513
ad756a16 9514 if (best)
4f977045 9515 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 9516 }
8b3e34e4 9517
45bdbcfd
HH		 9518 if (cpu_has_secondary_exec_ctrls())
9519 vmcs_set_secondary_exec_control(secondary_exec_ctl);
feda805f 9520
37e4c997
HZ		 9521 if (nested_vmx_allowed(vcpu))
9522 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9523 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9524 else
9525 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9526 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
8322ebbb
DM		 9527
9528 if (nested_vmx_allowed(vcpu))
9529 nested_vmx_cr_fixed1_bits_update(vcpu);
0e851880
SY		 9530}
9531
d4330ef2
JR		 9532static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9533{
7b8050f5
NHE		 9534 if (func == 1 && nested)
9535 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 9536}
9537
25d92081
YZ		 9538static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9539 struct x86_exception *fault)
9540{
533558bc
JK		 9541 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9542 u32 exit_reason;
25d92081
YZ		 9543
9544 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 9545 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 9546 else
533558bc
JK		 9547 exit_reason = EXIT_REASON_EPT_VIOLATION;
9548 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 9549 vmcs12->guest_physical_address = fault->address;
9550}
9551
155a97a3
NHE		 9552/* Callbacks for nested_ept_init_mmu_context: */
9553
9554static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9555{
9556 /* return the page table to be shadowed - in our case, EPT12 */
9557 return get_vmcs12(vcpu)->ept_pointer;
9558}
9559
8a3c1a33 9560static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 9561{
ad896af0
PB		 9562 WARN_ON(mmu_is_nested(vcpu));
9563 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 9564 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9565 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 9566 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9567 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9568 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9569
9570 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 9571}
9572
9573static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9574{
9575 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9576}
9577
19d5f10b
EK		 9578static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9579 u16 error_code)
9580{
9581 bool inequality, bit;
9582
9583 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9584 inequality =
9585 (error_code & vmcs12->page_fault_error_code_mask) !=
9586 vmcs12->page_fault_error_code_match;
9587 return inequality ^ bit;
9588}
9589
feaf0c7d
GN		 9590static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9591 struct x86_exception *fault)
9592{
9593 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9594
9595 WARN_ON(!is_guest_mode(vcpu));
9596
19d5f10b 9597 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 9598 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9599 vmcs_read32(VM_EXIT_INTR_INFO),
9600 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 9601 else
9602 kvm_inject_page_fault(vcpu, fault);
9603}
9604
a2bcba50
WL		 9605static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9606 struct vmcs12 *vmcs12)
9607{
9608 struct vcpu_vmx *vmx = to_vmx(vcpu);
9090422f 9609 int maxphyaddr = cpuid_maxphyaddr(vcpu);
a2bcba50
WL		 9610
9611 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9090422f
EK		 9612 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9613 vmcs12->apic_access_addr >> maxphyaddr)
a2bcba50
WL		 9614 return false;
9615
9616 /*
9617 * Translate L1 physical address to host physical
9618 * address for vmcs02. Keep the page pinned, so this
9619 * physical address remains valid. We keep a reference
9620 * to it so we can release it later.
9621 */
9622 if (vmx->nested.apic_access_page) /* shouldn't happen */
9623 nested_release_page(vmx->nested.apic_access_page);
9624 vmx->nested.apic_access_page =
9625 nested_get_page(vcpu, vmcs12->apic_access_addr);
9626 }
a7c0b07d
WL		 9627
9628 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9090422f
EK		 9629 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9630 vmcs12->virtual_apic_page_addr >> maxphyaddr)
a7c0b07d
WL		 9631 return false;
9632
9633 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9634 nested_release_page(vmx->nested.virtual_apic_page);
9635 vmx->nested.virtual_apic_page =
9636 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9637
9638 /*
9639 * Failing the vm entry is _not_ what the processor does
9640 * but it's basically the only possibility we have.
9641 * We could still enter the guest if CR8 load exits are
9642 * enabled, CR8 store exits are enabled, and virtualize APIC
9643 * access is disabled; in this case the processor would never
9644 * use the TPR shadow and we could simply clear the bit from
9645 * the execution control. But such a configuration is useless,
9646 * so let's keep the code simple.
9647 */
9648 if (!vmx->nested.virtual_apic_page)
9649 return false;
9650 }
9651
705699a1 9652 if (nested_cpu_has_posted_intr(vmcs12)) {
9090422f
EK		 9653 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9654 vmcs12->posted_intr_desc_addr >> maxphyaddr)
705699a1
WV		 9655 return false;
9656
9657 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9658 kunmap(vmx->nested.pi_desc_page);
9659 nested_release_page(vmx->nested.pi_desc_page);
9660 }
9661 vmx->nested.pi_desc_page =
9662 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9663 if (!vmx->nested.pi_desc_page)
9664 return false;
9665
9666 vmx->nested.pi_desc =
9667 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9668 if (!vmx->nested.pi_desc) {
9669 nested_release_page_clean(vmx->nested.pi_desc_page);
9670 return false;
9671 }
9672 vmx->nested.pi_desc =
9673 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9674 (unsigned long)(vmcs12->posted_intr_desc_addr &
9675 (PAGE_SIZE - 1)));
9676 }
9677
a2bcba50
WL		 9678 return true;
9679}
9680
f4124500
JK		 9681static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9682{
9683 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9684 struct vcpu_vmx *vmx = to_vmx(vcpu);
9685
9686 if (vcpu->arch.virtual_tsc_khz == 0)
9687 return;
9688
9689 /* Make sure short timeouts reliably trigger an immediate vmexit.
9690 * hrtimer_start does not guarantee this. */
9691 if (preemption_timeout <= 1) {
9692 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9693 return;
9694 }
9695
9696 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9697 preemption_timeout *= 1000000;
9698 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9699 hrtimer_start(&vmx->nested.preemption_timer,
9700 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9701}
9702
3af18d9c
WV		 9703static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9704 struct vmcs12 *vmcs12)
9705{
9706 int maxphyaddr;
9707 u64 addr;
9708
9709 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9710 return 0;
9711
9712 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9713 WARN_ON(1);
9714 return -EINVAL;
9715 }
9716 maxphyaddr = cpuid_maxphyaddr(vcpu);
9717
9718 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9719 ((addr + PAGE_SIZE) >> maxphyaddr))
9720 return -EINVAL;
9721
9722 return 0;
9723}
9724
9725/*
9726 * Merge L0's and L1's MSR bitmap, return false to indicate that
9727 * we do not use the hardware.
9728 */
9729static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9730 struct vmcs12 *vmcs12)
9731{
82f0dd4b 9732 int msr;
f2b93280 9733 struct page *page;
d048c098
RK		 9734 unsigned long *msr_bitmap_l1;
9735 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
f2b93280 9736
d048c098 9737 /* This shortcut is ok because we support only x2APIC MSRs so far. */
f2b93280
WV		 9738 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9739 return false;
9740
9741 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9742 if (!page) {
9743 WARN_ON(1);
9744 return false;
9745 }
d048c098 9746 msr_bitmap_l1 = (unsigned long *)kmap(page);
f2b93280 9747
d048c098
RK		 9748 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9749
f2b93280 9750 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 9751 if (nested_cpu_has_apic_reg_virt(vmcs12))
9752 for (msr = 0x800; msr <= 0x8ff; msr++)
9753 nested_vmx_disable_intercept_for_msr(
d048c098 9754 msr_bitmap_l1, msr_bitmap_l0,
82f0dd4b 9755 msr, MSR_TYPE_R);
d048c098
RK		 9756
9757 nested_vmx_disable_intercept_for_msr(
9758 msr_bitmap_l1, msr_bitmap_l0,
f2b93280
WV		 9759 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9760 MSR_TYPE_R | MSR_TYPE_W);
d048c098 9761
608406e2 9762 if (nested_cpu_has_vid(vmcs12)) {
608406e2 9763 nested_vmx_disable_intercept_for_msr(
d048c098 9764 msr_bitmap_l1, msr_bitmap_l0,
608406e2
WV		 9765 APIC_BASE_MSR + (APIC_EOI >> 4),
9766 MSR_TYPE_W);
9767 nested_vmx_disable_intercept_for_msr(
d048c098 9768 msr_bitmap_l1, msr_bitmap_l0,
608406e2
WV		 9769 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9770 MSR_TYPE_W);
9771 }
82f0dd4b 9772 }
f2b93280
WV		 9773 kunmap(page);
9774 nested_release_page_clean(page);
9775
9776 return true;
9777}
9778
9779static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9780 struct vmcs12 *vmcs12)
9781{
82f0dd4b 9782 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 9783 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV		 9784 !nested_cpu_has_vid(vmcs12) &&
9785 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV		 9786 return 0;
9787
9788 /*
9789 * If virtualize x2apic mode is enabled,
9790 * virtualize apic access must be disabled.
9791 */
82f0dd4b
WV		 9792 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9793 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 9794 return -EINVAL;
9795
608406e2
WV		 9796 /*
9797 * If virtual interrupt delivery is enabled,
9798 * we must exit on external interrupts.
9799 */
9800 if (nested_cpu_has_vid(vmcs12) &&
9801 !nested_exit_on_intr(vcpu))
9802 return -EINVAL;
9803
705699a1
WV		 9804 /*
9805 * bits 15:8 should be zero in posted_intr_nv,
9806 * the descriptor address has been already checked
9807 * in nested_get_vmcs12_pages.
9808 */
9809 if (nested_cpu_has_posted_intr(vmcs12) &&
9810 (!nested_cpu_has_vid(vmcs12) ||
9811 !nested_exit_intr_ack_set(vcpu) ||
9812 vmcs12->posted_intr_nv & 0xff00))
9813 return -EINVAL;
9814
f2b93280
WV		 9815 /* tpr shadow is needed by all apicv features. */
9816 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9817 return -EINVAL;
9818
9819 return 0;
3af18d9c
WV		 9820}
9821
e9ac033e
EK		 9822static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9823 unsigned long count_field,
92d71bc6 9824 unsigned long addr_field)
ff651cb6 9825{
92d71bc6 9826 int maxphyaddr;
e9ac033e
EK		 9827 u64 count, addr;
9828
9829 if (vmcs12_read_any(vcpu, count_field, &count) ||
9830 vmcs12_read_any(vcpu, addr_field, &addr)) {
9831 WARN_ON(1);
9832 return -EINVAL;
9833 }
9834 if (count == 0)
9835 return 0;
92d71bc6 9836 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK		 9837 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9838 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
bbe41b95 9839 pr_debug_ratelimited(
e9ac033e
EK		 9840 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9841 addr_field, maxphyaddr, count, addr);
9842 return -EINVAL;
9843 }
9844 return 0;
9845}
9846
9847static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9848 struct vmcs12 *vmcs12)
9849{
e9ac033e
EK		 9850 if (vmcs12->vm_exit_msr_load_count == 0 &&
9851 vmcs12->vm_exit_msr_store_count == 0 &&
9852 vmcs12->vm_entry_msr_load_count == 0)
9853 return 0; /* Fast path */
e9ac033e 9854 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9855 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9856 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9857 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9858 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9859 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK		 9860 return -EINVAL;
9861 return 0;
9862}
9863
9864static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9865 struct vmx_msr_entry *e)
9866{
9867 /* x2APIC MSR accesses are not allowed */
8a9781f7 9868 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK		 9869 return -EINVAL;
9870 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9871 e->index == MSR_IA32_UCODE_REV)
9872 return -EINVAL;
9873 if (e->reserved != 0)
ff651cb6
WV		 9874 return -EINVAL;
9875 return 0;
9876}
9877
e9ac033e
EK		 9878static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9879 struct vmx_msr_entry *e)
ff651cb6
WV		 9880{
9881 if (e->index == MSR_FS_BASE ||
9882 e->index == MSR_GS_BASE ||
e9ac033e
EK		 9883 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9884 nested_vmx_msr_check_common(vcpu, e))
9885 return -EINVAL;
9886 return 0;
9887}
9888
9889static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9890 struct vmx_msr_entry *e)
9891{
9892 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9893 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 9894 return -EINVAL;
9895 return 0;
9896}
9897
9898/*
9899 * Load guest's/host's msr at nested entry/exit.
9900 * return 0 for success, entry index for failure.
9901 */
9902static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9903{
9904 u32 i;
9905 struct vmx_msr_entry e;
9906 struct msr_data msr;
9907
9908 msr.host_initiated = false;
9909 for (i = 0; i < count; i++) {
54bf36aa
PB		 9910 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9911 &e, sizeof(e))) {
bbe41b95 9912 pr_debug_ratelimited(
e9ac033e
EK		 9913 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9914 __func__, i, gpa + i * sizeof(e));
ff651cb6 9915 goto fail;
e9ac033e
EK		 9916 }
9917 if (nested_vmx_load_msr_check(vcpu, &e)) {
bbe41b95 9918 pr_debug_ratelimited(
e9ac033e
EK		 9919 "%s check failed (%u, 0x%x, 0x%x)\n",
9920 __func__, i, e.index, e.reserved);
9921 goto fail;
9922 }
ff651cb6
WV		 9923 msr.index = e.index;
9924 msr.data = e.value;
e9ac033e 9925 if (kvm_set_msr(vcpu, &msr)) {
bbe41b95 9926 pr_debug_ratelimited(
e9ac033e
EK		 9927 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9928 __func__, i, e.index, e.value);
ff651cb6 9929 goto fail;
e9ac033e 9930 }
ff651cb6
WV		 9931 }
9932 return 0;
9933fail:
9934 return i + 1;
9935}
9936
9937static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9938{
9939 u32 i;
9940 struct vmx_msr_entry e;
9941
9942 for (i = 0; i < count; i++) {
609e36d3 9943 struct msr_data msr_info;
54bf36aa
PB		 9944 if (kvm_vcpu_read_guest(vcpu,
9945 gpa + i * sizeof(e),
9946 &e, 2 * sizeof(u32))) {
bbe41b95 9947 pr_debug_ratelimited(
e9ac033e
EK		 9948 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9949 __func__, i, gpa + i * sizeof(e));
ff651cb6 9950 return -EINVAL;
e9ac033e
EK		 9951 }
9952 if (nested_vmx_store_msr_check(vcpu, &e)) {
bbe41b95 9953 pr_debug_ratelimited(
e9ac033e
EK		 9954 "%s check failed (%u, 0x%x, 0x%x)\n",
9955 __func__, i, e.index, e.reserved);
ff651cb6 9956 return -EINVAL;
e9ac033e 9957 }
609e36d3
PB		 9958 msr_info.host_initiated = false;
9959 msr_info.index = e.index;
9960 if (kvm_get_msr(vcpu, &msr_info)) {
bbe41b95 9961 pr_debug_ratelimited(
e9ac033e
EK		 9962 "%s cannot read MSR (%u, 0x%x)\n",
9963 __func__, i, e.index);
9964 return -EINVAL;
9965 }
54bf36aa
PB		 9966 if (kvm_vcpu_write_guest(vcpu,
9967 gpa + i * sizeof(e) +
9968 offsetof(struct vmx_msr_entry, value),
9969 &msr_info.data, sizeof(msr_info.data))) {
bbe41b95 9970 pr_debug_ratelimited(
e9ac033e 9971 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9972 __func__, i, e.index, msr_info.data);
e9ac033e
EK		 9973 return -EINVAL;
9974 }
ff651cb6
WV		 9975 }
9976 return 0;
9977}
9978
1dc35dac
LP		 9979static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9980{
9981 unsigned long invalid_mask;
9982
9983 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9984 return (val & invalid_mask) == 0;
9985}
9986
9ed38ffa
LP		 9987/*
9988 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9989 * emulating VM entry into a guest with EPT enabled.
9990 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9991 * is assigned to entry_failure_code on failure.
9992 */
9993static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9994 unsigned long *entry_failure_code)
9995{
9ed38ffa 9996 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
1dc35dac 9997 if (!nested_cr3_valid(vcpu, cr3)) {
9ed38ffa
LP		 9998 *entry_failure_code = ENTRY_FAIL_DEFAULT;
9999 return 1;
10000 }
10001
10002 /*
10003 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10004 * must not be dereferenced.
10005 */
10006 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10007 !nested_ept) {
10008 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10009 *entry_failure_code = ENTRY_FAIL_PDPTE;
10010 return 1;
10011 }
10012 }
10013
10014 vcpu->arch.cr3 = cr3;
10015 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10016 }
10017
10018 kvm_mmu_reset_context(vcpu);
10019 return 0;
10020}
10021
fe3ef05c
NHE		 10022/*
10023 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10024 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 10025 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 10026 * guest in a way that will both be appropriate to L1's requests, and our
10027 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10028 * function also has additional necessary side-effects, like setting various
10029 * vcpu->arch fields.
ee146c1c
LP		 10030 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10031 * is assigned to entry_failure_code on failure.
fe3ef05c 10032 */
ee146c1c
LP		 10033static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10034 unsigned long *entry_failure_code)
fe3ef05c
NHE		 10035{
10036 struct vcpu_vmx *vmx = to_vmx(vcpu);
10037 u32 exec_control;
7ca29de2 10038 bool nested_ept_enabled = false;
fe3ef05c
NHE		 10039
10040 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10041 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10042 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10043 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10044 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10045 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10046 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10047 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10048 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10049 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10050 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10051 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10052 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10053 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10054 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10055 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10056 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10057 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10058 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10059 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10060 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10061 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10062 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10063 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10064 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10065 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10066 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10067 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10068 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10069 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10070 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10071 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10072 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10073 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10074 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10075 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10076
2996fca0
JK		 10077 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
10078 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10079 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10080 } else {
10081 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10082 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10083 }
fe3ef05c
NHE		 10084 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10085 vmcs12->vm_entry_intr_info_field);
10086 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10087 vmcs12->vm_entry_exception_error_code);
10088 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10089 vmcs12->vm_entry_instruction_len);
10090 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10091 vmcs12->guest_interruptibility_info);
fe3ef05c 10092 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 10093 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 10094 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10095 vmcs12->guest_pending_dbg_exceptions);
10096 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10097 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10098
81dc01f7
WL		 10099 if (nested_cpu_has_xsaves(vmcs12))
10100 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 10101 vmcs_write64(VMCS_LINK_POINTER, -1ull);
10102
f4124500 10103 exec_control = vmcs12->pin_based_vm_exec_control;
9314006d
PB		 10104
10105 /* Preemption timer setting is only taken from vmcs01. */
705699a1 10106 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9314006d
PB		 10107 exec_control |= vmcs_config.pin_based_exec_ctrl;
10108 if (vmx->hv_deadline_tsc == -1)
10109 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
705699a1 10110
9314006d 10111 /* Posted interrupts setting is only taken from vmcs12. */
705699a1
WV		 10112 if (nested_cpu_has_posted_intr(vmcs12)) {
10113 /*
10114 * Note that we use L0's vector here and in
10115 * vmx_deliver_nested_posted_interrupt.
10116 */
10117 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10118 vmx->nested.pi_pending = false;
0bcf261c 10119 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
705699a1
WV		 10120 vmcs_write64(POSTED_INTR_DESC_ADDR,
10121 page_to_phys(vmx->nested.pi_desc_page) +
10122 (unsigned long)(vmcs12->posted_intr_desc_addr &
10123 (PAGE_SIZE - 1)));
10124 } else
10125 exec_control &= ~PIN_BASED_POSTED_INTR;
10126
f4124500 10127 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 10128
f4124500
JK		 10129 vmx->nested.preemption_timer_expired = false;
10130 if (nested_cpu_has_preemption_timer(vmcs12))
10131 vmx_start_preemption_timer(vcpu);
0238ea91 10132
fe3ef05c
NHE		 10133 /*
10134 * Whether page-faults are trapped is determined by a combination of
10135 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10136 * If enable_ept, L0 doesn't care about page faults and we should
10137 * set all of these to L1's desires. However, if !enable_ept, L0 does
10138 * care about (at least some) page faults, and because it is not easy
10139 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10140 * to exit on each and every L2 page fault. This is done by setting
10141 * MASK=MATCH=0 and (see below) EB.PF=1.
10142 * Note that below we don't need special code to set EB.PF beyond the
10143 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10144 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10145 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10146 *
10147 * A problem with this approach (when !enable_ept) is that L1 may be
10148 * injected with more page faults than it asked for. This could have
10149 * caused problems, but in practice existing hypervisors don't care.
10150 * To fix this, we will need to emulate the PFEC checking (on the L1
10151 * page tables), using walk_addr(), when injecting PFs to L1.
10152 */
10153 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10154 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10155 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10156 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10157
10158 if (cpu_has_secondary_exec_ctrls()) {
f4124500 10159 exec_control = vmx_secondary_exec_control(vmx);
e2821620 10160
fe3ef05c 10161 /* Take the following fields only from vmcs12 */
696dfd95 10162 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 10163 SECONDARY_EXEC_RDTSCP |
696dfd95 10164 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
dfa169bb 10165 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 10166 if (nested_cpu_has(vmcs12,
10167 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10168 exec_control |= vmcs12->secondary_vm_exec_control;
10169
10170 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 10171 /*
10172 * If translation failed, no matter: This feature asks
10173 * to exit when accessing the given address, and if it
10174 * can never be accessed, this feature won't do
10175 * anything anyway.
10176 */
10177 if (!vmx->nested.apic_access_page)
10178 exec_control &=
10179 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
10180 else
10181 vmcs_write64(APIC_ACCESS_ADDR,
10182 page_to_phys(vmx->nested.apic_access_page));
f2b93280 10183 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
35754c98 10184 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
ca3f257a
JK		 10185 exec_control |=
10186 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 10187 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 10188 }
10189
608406e2
WV		 10190 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10191 vmcs_write64(EOI_EXIT_BITMAP0,
10192 vmcs12->eoi_exit_bitmap0);
10193 vmcs_write64(EOI_EXIT_BITMAP1,
10194 vmcs12->eoi_exit_bitmap1);
10195 vmcs_write64(EOI_EXIT_BITMAP2,
10196 vmcs12->eoi_exit_bitmap2);
10197 vmcs_write64(EOI_EXIT_BITMAP3,
10198 vmcs12->eoi_exit_bitmap3);
10199 vmcs_write16(GUEST_INTR_STATUS,
10200 vmcs12->guest_intr_status);
10201 }
10202
7ca29de2 10203 nested_ept_enabled = (exec_control & SECONDARY_EXEC_ENABLE_EPT) != 0;
fe3ef05c
NHE		 10204 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10205 }
10206
10207
10208 /*
10209 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10210 * Some constant fields are set here by vmx_set_constant_host_state().
10211 * Other fields are different per CPU, and will be set later when
10212 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10213 */
a547c6db 10214 vmx_set_constant_host_state(vmx);
fe3ef05c 10215
83bafef1
JM		 10216 /*
10217 * Set the MSR load/store lists to match L0's settings.
10218 */
10219 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10220 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10221 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10222 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10223 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10224
fe3ef05c
NHE		 10225 /*
10226 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10227 * entry, but only if the current (host) sp changed from the value
10228 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10229 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10230 * here we just force the write to happen on entry.
10231 */
10232 vmx->host_rsp = 0;
10233
10234 exec_control = vmx_exec_control(vmx); /* L0's desires */
10235 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10236 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10237 exec_control &= ~CPU_BASED_TPR_SHADOW;
10238 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 10239
10240 if (exec_control & CPU_BASED_TPR_SHADOW) {
10241 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
10242 page_to_phys(vmx->nested.virtual_apic_page));
10243 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10244 }
10245
3af18d9c 10246 if (cpu_has_vmx_msr_bitmap() &&
d048c098
RK		 10247 exec_control & CPU_BASED_USE_MSR_BITMAPS &&
10248 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
10249 ; /* MSR_BITMAP will be set by following vmx_set_efer. */
10250 else
3af18d9c
WV		 10251 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
10252
fe3ef05c 10253 /*
3af18d9c 10254 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 10255 * Rather, exit every time.
10256 */
fe3ef05c
NHE		 10257 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10258 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10259
10260 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10261
10262 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10263 * bitwise-or of what L1 wants to trap for L2, and what we want to
10264 * trap. Note that CR0.TS also needs updating - we do this later.
10265 */
10266 update_exception_bitmap(vcpu);
10267 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10268 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10269
8049d651
NHE		 10270 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10271 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10272 * bits are further modified by vmx_set_efer() below.
10273 */
f4124500 10274 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 10275
10276 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10277 * emulated by vmx_set_efer(), below.
10278 */
2961e876 10279 vm_entry_controls_init(vmx,
8049d651
NHE		 10280 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10281 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 10282 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10283
44811c02 10284 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 10285 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 10286 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10287 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 10288 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10289
10290
10291 set_cr4_guest_host_mask(vmx);
10292
36be0b9d
PB		 10293 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10294 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10295
27fc51b2
NHE		 10296 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10297 vmcs_write64(TSC_OFFSET,
ea26e4ec 10298 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
27fc51b2 10299 else
ea26e4ec 10300 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
c95ba92a
PF		 10301 if (kvm_has_tsc_control)
10302 decache_tsc_multiplier(vmx);
fe3ef05c
NHE		 10303
10304 if (enable_vpid) {
10305 /*
5c614b35
WL		 10306 * There is no direct mapping between vpid02 and vpid12, the
10307 * vpid02 is per-vCPU for L0 and reused while the value of
10308 * vpid12 is changed w/ one invvpid during nested vmentry.
10309 * The vpid12 is allocated by L1 for L2, so it will not
10310 * influence global bitmap(for vpid01 and vpid02 allocation)
10311 * even if spawn a lot of nested vCPUs.
fe3ef05c 10312 */
5c614b35
WL		 10313 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10314 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10315 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10316 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10317 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10318 }
10319 } else {
10320 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10321 vmx_flush_tlb(vcpu);
10322 }
10323
fe3ef05c
NHE		 10324 }
10325
155a97a3
NHE		 10326 if (nested_cpu_has_ept(vmcs12)) {
10327 kvm_mmu_unload(vcpu);
10328 nested_ept_init_mmu_context(vcpu);
10329 }
10330
fe3ef05c
NHE		 10331 /*
10332 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10333 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10334 * The CR0_READ_SHADOW is what L2 should have expected to read given
10335 * the specifications by L1; It's not enough to take
10336 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10337 * have more bits than L1 expected.
10338 */
10339 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10340 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10341
10342 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10343 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10344
5a6a9748
DM		 10345 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
10346 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10347 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10348 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10349 else
10350 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10351 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10352 vmx_set_efer(vcpu, vcpu->arch.efer);
10353
9ed38ffa
LP		 10354 /* Shadow page tables on either EPT or shadow page tables. */
10355 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_ept_enabled,
10356 entry_failure_code))
10357 return 1;
7ca29de2 10358
fe3ef05c
NHE		 10359 kvm_mmu_reset_context(vcpu);
10360
feaf0c7d
GN		 10361 if (!enable_ept)
10362 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10363
3633cfc3
NHE		 10364 /*
10365 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10366 */
10367 if (enable_ept) {
10368 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10369 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10370 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10371 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10372 }
10373
fe3ef05c
NHE		 10374 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10375 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
ee146c1c 10376 return 0;
fe3ef05c
NHE		 10377}
10378
cd232ad0
NHE		 10379/*
10380 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10381 * for running an L2 nested guest.
10382 */
10383static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10384{
10385 struct vmcs12 *vmcs12;
10386 struct vcpu_vmx *vmx = to_vmx(vcpu);
10387 int cpu;
10388 struct loaded_vmcs *vmcs02;
384bb783 10389 bool ia32e;
ff651cb6 10390 u32 msr_entry_idx;
ee146c1c 10391 unsigned long exit_qualification;
cd232ad0 10392
eb277562 10393 if (!nested_vmx_check_permission(vcpu))
cd232ad0
NHE		 10394 return 1;
10395
eb277562
KH		 10396 if (!nested_vmx_check_vmcs12(vcpu))
10397 goto out;
10398
cd232ad0
NHE		 10399 vmcs12 = get_vmcs12(vcpu);
10400
012f83cb
AG		 10401 if (enable_shadow_vmcs)
10402 copy_shadow_to_vmcs12(vmx);
10403
7c177938
NHE		 10404 /*
10405 * The nested entry process starts with enforcing various prerequisites
10406 * on vmcs12 as required by the Intel SDM, and act appropriately when
10407 * they fail: As the SDM explains, some conditions should cause the
10408 * instruction to fail, while others will cause the instruction to seem
10409 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10410 * To speed up the normal (success) code path, we should avoid checking
10411 * for misconfigurations which will anyway be caught by the processor
10412 * when using the merged vmcs02.
10413 */
10414 if (vmcs12->launch_state == launch) {
10415 nested_vmx_failValid(vcpu,
10416 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10417 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
eb277562 10418 goto out;
7c177938
NHE		 10419 }
10420
6dfacadd
JK		 10421 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10422 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0 10423 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
eb277562 10424 goto out;
26539bd0
PB		 10425 }
10426
3af18d9c 10427 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938 10428 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
eb277562 10429 goto out;
7c177938
NHE		 10430 }
10431
3af18d9c 10432 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938 10433 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
eb277562 10434 goto out;
7c177938
NHE		 10435 }
10436
f2b93280
WV		 10437 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
10438 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
eb277562 10439 goto out;
f2b93280
WV		 10440 }
10441
e9ac033e
EK		 10442 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
10443 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
eb277562 10444 goto out;
e9ac033e
EK		 10445 }
10446
7c177938 10447 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
0115f9cb 10448 vmx->nested.nested_vmx_procbased_ctls_low,
b9c237bb 10449 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 10450 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 10451 vmx->nested.nested_vmx_secondary_ctls_low,
10452 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 10453 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 10454 vmx->nested.nested_vmx_pinbased_ctls_low,
10455 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 10456 !vmx_control_verify(vmcs12->vm_exit_controls,
0115f9cb 10457 vmx->nested.nested_vmx_exit_ctls_low,
b9c237bb 10458 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 10459 !vmx_control_verify(vmcs12->vm_entry_controls,
0115f9cb 10460 vmx->nested.nested_vmx_entry_ctls_low,
b9c237bb 10461 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 10462 {
10463 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
eb277562 10464 goto out;
7c177938
NHE		 10465 }
10466
3899152c 10467 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
1dc35dac
LP		 10468 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10469 !nested_cr3_valid(vcpu, vmcs12->host_cr3)) {
7c177938
NHE		 10470 nested_vmx_failValid(vcpu,
10471 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
eb277562 10472 goto out;
7c177938
NHE		 10473 }
10474
3899152c
DM		 10475 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10476 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)) {
7c177938
NHE		 10477 nested_vmx_entry_failure(vcpu, vmcs12,
10478 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
b428018a 10479 return 1;
7c177938
NHE		 10480 }
10481 if (vmcs12->vmcs_link_pointer != -1ull) {
10482 nested_vmx_entry_failure(vcpu, vmcs12,
10483 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
b428018a 10484 return 1;
7c177938
NHE		 10485 }
10486
384bb783 10487 /*
cb0c8cda 10488 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 10489 * are performed on the field for the IA32_EFER MSR:
10490 * - Bits reserved in the IA32_EFER MSR must be 0.
10491 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10492 * the IA-32e mode guest VM-exit control. It must also be identical
10493 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10494 * CR0.PG) is 1.
10495 */
10496 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10497 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10498 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10499 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10500 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10501 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10502 nested_vmx_entry_failure(vcpu, vmcs12,
10503 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
b428018a 10504 return 1;
384bb783
JK		 10505 }
10506 }
10507
10508 /*
10509 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10510 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10511 * the values of the LMA and LME bits in the field must each be that of
10512 * the host address-space size VM-exit control.
10513 */
10514 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10515 ia32e = (vmcs12->vm_exit_controls &
10516 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10517 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10518 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10519 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10520 nested_vmx_entry_failure(vcpu, vmcs12,
10521 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
b428018a 10522 return 1;
384bb783
JK		 10523 }
10524 }
10525
7c177938
NHE		 10526 /*
10527 * We're finally done with prerequisite checking, and can start with
10528 * the nested entry.
10529 */
10530
cd232ad0
NHE		 10531 vmcs02 = nested_get_current_vmcs02(vmx);
10532 if (!vmcs02)
10533 return -ENOMEM;
10534
6affcbed
KH		 10535 /*
10536 * After this point, the trap flag no longer triggers a singlestep trap
10537 * on the vm entry instructions. Don't call
10538 * kvm_skip_emulated_instruction.
10539 */
eb277562 10540 skip_emulated_instruction(vcpu);
cd232ad0
NHE		 10541 enter_guest_mode(vcpu);
10542
2996fca0
JK		 10543 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10544 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10545
cd232ad0
NHE		 10546 cpu = get_cpu();
10547 vmx->loaded_vmcs = vmcs02;
10548 vmx_vcpu_put(vcpu);
10549 vmx_vcpu_load(vcpu, cpu);
10550 vcpu->cpu = cpu;
10551 put_cpu();
10552
36c3cc42
JK		 10553 vmx_segment_cache_clear(vmx);
10554
ee146c1c
LP		 10555 if (prepare_vmcs02(vcpu, vmcs12, &exit_qualification)) {
10556 leave_guest_mode(vcpu);
10557 vmx_load_vmcs01(vcpu);
10558 nested_vmx_entry_failure(vcpu, vmcs12,
10559 EXIT_REASON_INVALID_STATE, exit_qualification);
10560 return 1;
10561 }
cd232ad0 10562
ff651cb6
WV		 10563 msr_entry_idx = nested_vmx_load_msr(vcpu,
10564 vmcs12->vm_entry_msr_load_addr,
10565 vmcs12->vm_entry_msr_load_count);
10566 if (msr_entry_idx) {
10567 leave_guest_mode(vcpu);
10568 vmx_load_vmcs01(vcpu);
10569 nested_vmx_entry_failure(vcpu, vmcs12,
10570 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10571 return 1;
10572 }
10573
10574 vmcs12->launch_state = 1;
10575
6dfacadd 10576 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 10577 return kvm_vcpu_halt(vcpu);
6dfacadd 10578
7af40ad3
JK		 10579 vmx->nested.nested_run_pending = 1;
10580
cd232ad0
NHE		 10581 /*
10582 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10583 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10584 * returned as far as L1 is concerned. It will only return (and set
10585 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10586 */
10587 return 1;
eb277562
KH		 10588
10589out:
6affcbed 10590 return kvm_skip_emulated_instruction(vcpu);
cd232ad0
NHE		 10591}
10592
4704d0be
NHE		 10593/*
10594 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10595 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10596 * This function returns the new value we should put in vmcs12.guest_cr0.
10597 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10598 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10599 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10600 * didn't trap the bit, because if L1 did, so would L0).
10601 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10602 * been modified by L2, and L1 knows it. So just leave the old value of
10603 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10604 * isn't relevant, because if L0 traps this bit it can set it to anything.
10605 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10606 * changed these bits, and therefore they need to be updated, but L0
10607 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10608 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10609 */
10610static inline unsigned long
10611vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10612{
10613 return
10614 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10615 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10616 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10617 vcpu->arch.cr0_guest_owned_bits));
10618}
10619
10620static inline unsigned long
10621vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10622{
10623 return
10624 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10625 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10626 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10627 vcpu->arch.cr4_guest_owned_bits));
10628}
10629
5f3d5799
JK		 10630static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10631 struct vmcs12 *vmcs12)
10632{
10633 u32 idt_vectoring;
10634 unsigned int nr;
10635
851eb667 10636 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 10637 nr = vcpu->arch.exception.nr;
10638 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10639
10640 if (kvm_exception_is_soft(nr)) {
10641 vmcs12->vm_exit_instruction_len =
10642 vcpu->arch.event_exit_inst_len;
10643 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10644 } else
10645 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10646
10647 if (vcpu->arch.exception.has_error_code) {
10648 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10649 vmcs12->idt_vectoring_error_code =
10650 vcpu->arch.exception.error_code;
10651 }
10652
10653 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 10654 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 10655 vmcs12->idt_vectoring_info_field =
10656 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10657 } else if (vcpu->arch.interrupt.pending) {
10658 nr = vcpu->arch.interrupt.nr;
10659 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10660
10661 if (vcpu->arch.interrupt.soft) {
10662 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10663 vmcs12->vm_entry_instruction_len =
10664 vcpu->arch.event_exit_inst_len;
10665 } else
10666 idt_vectoring |= INTR_TYPE_EXT_INTR;
10667
10668 vmcs12->idt_vectoring_info_field = idt_vectoring;
10669 }
10670}
10671
b6b8a145
JK		 10672static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10673{
10674 struct vcpu_vmx *vmx = to_vmx(vcpu);
10675
f4124500
JK		 10676 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10677 vmx->nested.preemption_timer_expired) {
10678 if (vmx->nested.nested_run_pending)
10679 return -EBUSY;
10680 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10681 return 0;
10682 }
10683
b6b8a145 10684 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 10685 if (vmx->nested.nested_run_pending ||
10686 vcpu->arch.interrupt.pending)
b6b8a145
JK		 10687 return -EBUSY;
10688 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10689 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10690 INTR_INFO_VALID_MASK, 0);
10691 /*
10692 * The NMI-triggered VM exit counts as injection:
10693 * clear this one and block further NMIs.
10694 */
10695 vcpu->arch.nmi_pending = 0;
10696 vmx_set_nmi_mask(vcpu, true);
10697 return 0;
10698 }
10699
10700 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10701 nested_exit_on_intr(vcpu)) {
10702 if (vmx->nested.nested_run_pending)
10703 return -EBUSY;
10704 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 10705 return 0;
b6b8a145
JK		 10706 }
10707
6342c50a
DH		 10708 vmx_complete_nested_posted_interrupt(vcpu);
10709 return 0;
b6b8a145
JK		 10710}
10711
f4124500
JK		 10712static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10713{
10714 ktime_t remaining =
10715 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10716 u64 value;
10717
10718 if (ktime_to_ns(remaining) <= 0)
10719 return 0;
10720
10721 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10722 do_div(value, 1000000);
10723 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10724}
10725
4704d0be
NHE		 10726/*
10727 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10728 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10729 * and this function updates it to reflect the changes to the guest state while
10730 * L2 was running (and perhaps made some exits which were handled directly by L0
10731 * without going back to L1), and to reflect the exit reason.
10732 * Note that we do not have to copy here all VMCS fields, just those that
10733 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10734 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10735 * which already writes to vmcs12 directly.
10736 */
533558bc
JK		 10737static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10738 u32 exit_reason, u32 exit_intr_info,
10739 unsigned long exit_qualification)
4704d0be
NHE		 10740{
10741 /* update guest state fields: */
10742 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10743 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10744
4704d0be
NHE		 10745 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10746 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10747 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10748
10749 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10750 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10751 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10752 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10753 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10754 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10755 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10756 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10757 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10758 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10759 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10760 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10761 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10762 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10763 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10764 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10765 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10766 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10767 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10768 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10769 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10770 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10771 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10772 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10773 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10774 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10775 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10776 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10777 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10778 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10779 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10780 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10781 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10782 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10783 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10784 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10785
4704d0be
NHE		 10786 vmcs12->guest_interruptibility_info =
10787 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10788 vmcs12->guest_pending_dbg_exceptions =
10789 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 10790 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10791 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10792 else
10793 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 10794
f4124500
JK		 10795 if (nested_cpu_has_preemption_timer(vmcs12)) {
10796 if (vmcs12->vm_exit_controls &
10797 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10798 vmcs12->vmx_preemption_timer_value =
10799 vmx_get_preemption_timer_value(vcpu);
10800 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10801 }
7854cbca 10802
3633cfc3
NHE		 10803 /*
10804 * In some cases (usually, nested EPT), L2 is allowed to change its
10805 * own CR3 without exiting. If it has changed it, we must keep it.
10806 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10807 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10808 *
10809 * Additionally, restore L2's PDPTR to vmcs12.
10810 */
10811 if (enable_ept) {
f3531054 10812 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
3633cfc3
NHE		 10813 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10814 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10815 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10816 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10817 }
10818
119a9c01
JD		 10819 if (nested_cpu_has_ept(vmcs12))
10820 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10821
608406e2
WV		 10822 if (nested_cpu_has_vid(vmcs12))
10823 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10824
c18911a2
JK		 10825 vmcs12->vm_entry_controls =
10826 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 10827 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 10828
2996fca0
JK		 10829 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10830 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10831 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10832 }
10833
4704d0be
NHE		 10834 /* TODO: These cannot have changed unless we have MSR bitmaps and
10835 * the relevant bit asks not to trap the change */
b8c07d55 10836 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 10837 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 10838 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10839 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 10840 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10841 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10842 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
a87036ad 10843 if (kvm_mpx_supported())
36be0b9d 10844 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 10845 if (nested_cpu_has_xsaves(vmcs12))
10846 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 10847
10848 /* update exit information fields: */
10849
533558bc
JK		 10850 vmcs12->vm_exit_reason = exit_reason;
10851 vmcs12->exit_qualification = exit_qualification;
4704d0be 10852
533558bc 10853 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 10854 if ((vmcs12->vm_exit_intr_info &
10855 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10856 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10857 vmcs12->vm_exit_intr_error_code =
10858 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 10859 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 10860 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10861 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10862
5f3d5799
JK		 10863 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10864 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10865 * instead of reading the real value. */
4704d0be 10866 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 10867
10868 /*
10869 * Transfer the event that L0 or L1 may wanted to inject into
10870 * L2 to IDT_VECTORING_INFO_FIELD.
10871 */
10872 vmcs12_save_pending_event(vcpu, vmcs12);
10873 }
10874
10875 /*
10876 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10877 * preserved above and would only end up incorrectly in L1.
10878 */
10879 vcpu->arch.nmi_injected = false;
10880 kvm_clear_exception_queue(vcpu);
10881 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 10882}
10883
10884/*
10885 * A part of what we need to when the nested L2 guest exits and we want to
10886 * run its L1 parent, is to reset L1's guest state to the host state specified
10887 * in vmcs12.
10888 * This function is to be called not only on normal nested exit, but also on
10889 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10890 * Failures During or After Loading Guest State").
10891 * This function should be called when the active VMCS is L1's (vmcs01).
10892 */
733568f9
JK		 10893static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10894 struct vmcs12 *vmcs12)
4704d0be 10895{
21feb4eb 10896 struct kvm_segment seg;
1dc35dac 10897 unsigned long entry_failure_code;
21feb4eb 10898
4704d0be
NHE		 10899 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10900 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10901 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 10902 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10903 else
10904 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10905 vmx_set_efer(vcpu, vcpu->arch.efer);
10906
10907 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10908 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10909 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 10910 /*
10911 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10912 * actually changed, because it depends on the current state of
10913 * fpu_active (which may have changed).
10914 * Note that vmx_set_cr0 refers to efer set above.
10915 */
9e3e4dbf 10916 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 10917 /*
10918 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10919 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10920 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10921 */
10922 update_exception_bitmap(vcpu);
10923 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10924 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10925
10926 /*
10927 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10928 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10929 */
10930 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10931 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10932
29bf08f1 10933 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10934
1dc35dac
LP		 10935 /*
10936 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10937 * couldn't have changed.
10938 */
10939 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10940 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
4704d0be 10941
feaf0c7d
GN		 10942 if (!enable_ept)
10943 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10944
4704d0be
NHE		 10945 if (enable_vpid) {
10946 /*
10947 * Trivially support vpid by letting L2s share their parent
10948 * L1's vpid. TODO: move to a more elaborate solution, giving
10949 * each L2 its own vpid and exposing the vpid feature to L1.
10950 */
10951 vmx_flush_tlb(vcpu);
10952 }
10953
10954
10955 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10956 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10957 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10958 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10959 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10960
36be0b9d
PB		 10961 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10962 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10963 vmcs_write64(GUEST_BNDCFGS, 0);
10964
44811c02 10965 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10966 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 10967 vcpu->arch.pat = vmcs12->host_ia32_pat;
10968 }
4704d0be
NHE		 10969 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10970 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10971 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10972
21feb4eb
ACL		 10973 /* Set L1 segment info according to Intel SDM
10974 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10975 seg = (struct kvm_segment) {
10976 .base = 0,
10977 .limit = 0xFFFFFFFF,
10978 .selector = vmcs12->host_cs_selector,
10979 .type = 11,
10980 .present = 1,
10981 .s = 1,
10982 .g = 1
10983 };
10984 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10985 seg.l = 1;
10986 else
10987 seg.db = 1;
10988 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10989 seg = (struct kvm_segment) {
10990 .base = 0,
10991 .limit = 0xFFFFFFFF,
10992 .type = 3,
10993 .present = 1,
10994 .s = 1,
10995 .db = 1,
10996 .g = 1
10997 };
10998 seg.selector = vmcs12->host_ds_selector;
10999 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11000 seg.selector = vmcs12->host_es_selector;
11001 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11002 seg.selector = vmcs12->host_ss_selector;
11003 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11004 seg.selector = vmcs12->host_fs_selector;
11005 seg.base = vmcs12->host_fs_base;
11006 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11007 seg.selector = vmcs12->host_gs_selector;
11008 seg.base = vmcs12->host_gs_base;
11009 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11010 seg = (struct kvm_segment) {
205befd9 11011 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 11012 .limit = 0x67,
11013 .selector = vmcs12->host_tr_selector,
11014 .type = 11,
11015 .present = 1
11016 };
11017 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11018
503cd0c5
JK		 11019 kvm_set_dr(vcpu, 7, 0x400);
11020 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 11021
3af18d9c
WV		 11022 if (cpu_has_vmx_msr_bitmap())
11023 vmx_set_msr_bitmap(vcpu);
11024
ff651cb6
WV		 11025 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11026 vmcs12->vm_exit_msr_load_count))
11027 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 11028}
11029
11030/*
11031 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11032 * and modify vmcs12 to make it see what it would expect to see there if
11033 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11034 */
533558bc
JK		 11035static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11036 u32 exit_intr_info,
11037 unsigned long exit_qualification)
4704d0be
NHE		 11038{
11039 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 11040 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
cf3215d9 11041 u32 vm_inst_error = 0;
4704d0be 11042
5f3d5799
JK		 11043 /* trying to cancel vmlaunch/vmresume is a bug */
11044 WARN_ON_ONCE(vmx->nested.nested_run_pending);
11045
4704d0be 11046 leave_guest_mode(vcpu);
533558bc
JK		 11047 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11048 exit_qualification);
4704d0be 11049
ff651cb6
WV		 11050 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11051 vmcs12->vm_exit_msr_store_count))
11052 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11053
cf3215d9
JM		 11054 if (unlikely(vmx->fail))
11055 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11056
f3380ca5
WL		 11057 vmx_load_vmcs01(vcpu);
11058
77b0f5d6
BD		 11059 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11060 && nested_exit_intr_ack_set(vcpu)) {
11061 int irq = kvm_cpu_get_interrupt(vcpu);
11062 WARN_ON(irq < 0);
11063 vmcs12->vm_exit_intr_info = irq |
11064 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11065 }
11066
542060ea
JK		 11067 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11068 vmcs12->exit_qualification,
11069 vmcs12->idt_vectoring_info_field,
11070 vmcs12->vm_exit_intr_info,
11071 vmcs12->vm_exit_intr_error_code,
11072 KVM_ISA_VMX);
4704d0be 11073
8391ce44
PB		 11074 vm_entry_controls_reset_shadow(vmx);
11075 vm_exit_controls_reset_shadow(vmx);
36c3cc42
JK		 11076 vmx_segment_cache_clear(vmx);
11077
4704d0be
NHE		 11078 /* if no vmcs02 cache requested, remove the one we used */
11079 if (VMCS02_POOL_SIZE == 0)
11080 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11081
11082 load_vmcs12_host_state(vcpu, vmcs12);
11083
9314006d 11084 /* Update any VMCS fields that might have changed while L2 ran */
83bafef1
JM		 11085 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11086 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
ea26e4ec 11087 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
9314006d
PB		 11088 if (vmx->hv_deadline_tsc == -1)
11089 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11090 PIN_BASED_VMX_PREEMPTION_TIMER);
11091 else
11092 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11093 PIN_BASED_VMX_PREEMPTION_TIMER);
c95ba92a
PF		 11094 if (kvm_has_tsc_control)
11095 decache_tsc_multiplier(vmx);
4704d0be 11096
dccbfcf5
RK		 11097 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11098 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11099 vmx_set_virtual_x2apic_mode(vcpu,
11100 vcpu->arch.apic_base & X2APIC_ENABLE);
11101 }
4704d0be
NHE		 11102
11103 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11104 vmx->host_rsp = 0;
11105
11106 /* Unpin physical memory we referred to in vmcs02 */
11107 if (vmx->nested.apic_access_page) {
11108 nested_release_page(vmx->nested.apic_access_page);
48d89b92 11109 vmx->nested.apic_access_page = NULL;
4704d0be 11110 }
a7c0b07d
WL		 11111 if (vmx->nested.virtual_apic_page) {
11112 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 11113 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 11114 }
705699a1
WV		 11115 if (vmx->nested.pi_desc_page) {
11116 kunmap(vmx->nested.pi_desc_page);
11117 nested_release_page(vmx->nested.pi_desc_page);
11118 vmx->nested.pi_desc_page = NULL;
11119 vmx->nested.pi_desc = NULL;
11120 }
4704d0be 11121
38b99173
TC		 11122 /*
11123 * We are now running in L2, mmu_notifier will force to reload the
11124 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11125 */
c83b6d15 11126 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
38b99173 11127
4704d0be
NHE		 11128 /*
11129 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11130 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11131 * success or failure flag accordingly.
11132 */
11133 if (unlikely(vmx->fail)) {
11134 vmx->fail = 0;
cf3215d9 11135 nested_vmx_failValid(vcpu, vm_inst_error);
4704d0be
NHE		 11136 } else
11137 nested_vmx_succeed(vcpu);
012f83cb
AG		 11138 if (enable_shadow_vmcs)
11139 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 11140
11141 /* in case we halted in L2 */
11142 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 11143}
11144
42124925
JK		 11145/*
11146 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11147 */
11148static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11149{
11150 if (is_guest_mode(vcpu))
533558bc 11151 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 11152 free_nested(to_vmx(vcpu));
11153}
11154
7c177938
NHE		 11155/*
11156 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11157 * 23.7 "VM-entry failures during or after loading guest state" (this also
11158 * lists the acceptable exit-reason and exit-qualification parameters).
11159 * It should only be called before L2 actually succeeded to run, and when
11160 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11161 */
11162static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11163 struct vmcs12 *vmcs12,
11164 u32 reason, unsigned long qualification)
11165{
11166 load_vmcs12_host_state(vcpu, vmcs12);
11167 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11168 vmcs12->exit_qualification = qualification;
11169 nested_vmx_succeed(vcpu);
012f83cb
AG		 11170 if (enable_shadow_vmcs)
11171 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 11172}
11173
8a76d7f2
JR		 11174static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11175 struct x86_instruction_info *info,
11176 enum x86_intercept_stage stage)
11177{
11178 return X86EMUL_CONTINUE;
11179}
11180
64672c95
YJ		 11181#ifdef CONFIG_X86_64
11182/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11183static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11184 u64 divisor, u64 *result)
11185{
11186 u64 low = a << shift, high = a >> (64 - shift);
11187
11188 /* To avoid the overflow on divq */
11189 if (high >= divisor)
11190 return 1;
11191
11192 /* Low hold the result, high hold rem which is discarded */
11193 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11194 "rm" (divisor), "0" (low), "1" (high));
11195 *result = low;
11196
11197 return 0;
11198}
11199
11200static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11201{
11202 struct vcpu_vmx *vmx = to_vmx(vcpu);
9175d2e9
PB		 11203 u64 tscl = rdtsc();
11204 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11205 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
64672c95
YJ		 11206
11207 /* Convert to host delta tsc if tsc scaling is enabled */
11208 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11209 u64_shl_div_u64(delta_tsc,
11210 kvm_tsc_scaling_ratio_frac_bits,
11211 vcpu->arch.tsc_scaling_ratio,
11212 &delta_tsc))
11213 return -ERANGE;
11214
11215 /*
11216 * If the delta tsc can't fit in the 32 bit after the multi shift,
11217 * we can't use the preemption timer.
11218 * It's possible that it fits on later vmentries, but checking
11219 * on every vmentry is costly so we just use an hrtimer.
11220 */
11221 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11222 return -ERANGE;
11223
11224 vmx->hv_deadline_tsc = tscl + delta_tsc;
11225 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11226 PIN_BASED_VMX_PREEMPTION_TIMER);
11227 return 0;
11228}
11229
11230static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11231{
11232 struct vcpu_vmx *vmx = to_vmx(vcpu);
11233 vmx->hv_deadline_tsc = -1;
11234 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11235 PIN_BASED_VMX_PREEMPTION_TIMER);
11236}
11237#endif
11238
48d89b92 11239static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 11240{
b4a2d31d
RK		 11241 if (ple_gap)
11242 shrink_ple_window(vcpu);
ae97a3b8
RK		 11243}
11244
843e4330
KH		 11245static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11246 struct kvm_memory_slot *slot)
11247{
11248 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11249 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11250}
11251
11252static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11253 struct kvm_memory_slot *slot)
11254{
11255 kvm_mmu_slot_set_dirty(kvm, slot);
11256}
11257
11258static void vmx_flush_log_dirty(struct kvm *kvm)
11259{
11260 kvm_flush_pml_buffers(kvm);
11261}
11262
11263static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11264 struct kvm_memory_slot *memslot,
11265 gfn_t offset, unsigned long mask)
11266{
11267 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11268}
11269
bf9f6ac8
FW		 11270/*
11271 * This routine does the following things for vCPU which is going
11272 * to be blocked if VT-d PI is enabled.
11273 * - Store the vCPU to the wakeup list, so when interrupts happen
11274 * we can find the right vCPU to wake up.
11275 * - Change the Posted-interrupt descriptor as below:
11276 * 'NDST' <-- vcpu->pre_pcpu
11277 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11278 * - If 'ON' is set during this process, which means at least one
11279 * interrupt is posted for this vCPU, we cannot block it, in
11280 * this case, return 1, otherwise, return 0.
11281 *
11282 */
bc22512b 11283static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8
FW		 11284{
11285 unsigned long flags;
11286 unsigned int dest;
11287 struct pi_desc old, new;
11288 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11289
11290 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 11291 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11292 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW		 11293 return 0;
11294
11295 vcpu->pre_pcpu = vcpu->cpu;
11296 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11297 vcpu->pre_pcpu), flags);
11298 list_add_tail(&vcpu->blocked_vcpu_list,
11299 &per_cpu(blocked_vcpu_on_cpu,
11300 vcpu->pre_pcpu));
11301 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11302 vcpu->pre_pcpu), flags);
11303
11304 do {
11305 old.control = new.control = pi_desc->control;
11306
11307 /*
11308 * We should not block the vCPU if
11309 * an interrupt is posted for it.
11310 */
11311 if (pi_test_on(pi_desc) == 1) {
11312 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11313 vcpu->pre_pcpu), flags);
11314 list_del(&vcpu->blocked_vcpu_list);
11315 spin_unlock_irqrestore(
11316 &per_cpu(blocked_vcpu_on_cpu_lock,
11317 vcpu->pre_pcpu), flags);
11318 vcpu->pre_pcpu = -1;
11319
11320 return 1;
11321 }
11322
11323 WARN((pi_desc->sn == 1),
11324 "Warning: SN field of posted-interrupts "
11325 "is set before blocking\n");
11326
11327 /*
11328 * Since vCPU can be preempted during this process,
11329 * vcpu->cpu could be different with pre_pcpu, we
11330 * need to set pre_pcpu as the destination of wakeup
11331 * notification event, then we can find the right vCPU
11332 * to wakeup in wakeup handler if interrupts happen
11333 * when the vCPU is in blocked state.
11334 */
11335 dest = cpu_physical_id(vcpu->pre_pcpu);
11336
11337 if (x2apic_enabled())
11338 new.ndst = dest;
11339 else
11340 new.ndst = (dest << 8) & 0xFF00;
11341
11342 /* set 'NV' to 'wakeup vector' */
11343 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11344 } while (cmpxchg(&pi_desc->control, old.control,
11345 new.control) != old.control);
11346
11347 return 0;
11348}
11349
bc22512b
YJ		 11350static int vmx_pre_block(struct kvm_vcpu *vcpu)
11351{
11352 if (pi_pre_block(vcpu))
11353 return 1;
11354
64672c95
YJ		 11355 if (kvm_lapic_hv_timer_in_use(vcpu))
11356 kvm_lapic_switch_to_sw_timer(vcpu);
11357
bc22512b
YJ		 11358 return 0;
11359}
11360
11361static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8
FW		 11362{
11363 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11364 struct pi_desc old, new;
11365 unsigned int dest;
11366 unsigned long flags;
11367
11368 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 11369 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11370 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW		 11371 return;
11372
11373 do {
11374 old.control = new.control = pi_desc->control;
11375
11376 dest = cpu_physical_id(vcpu->cpu);
11377
11378 if (x2apic_enabled())
11379 new.ndst = dest;
11380 else
11381 new.ndst = (dest << 8) & 0xFF00;
11382
11383 /* Allow posting non-urgent interrupts */
11384 new.sn = 0;
11385
11386 /* set 'NV' to 'notification vector' */
11387 new.nv = POSTED_INTR_VECTOR;
11388 } while (cmpxchg(&pi_desc->control, old.control,
11389 new.control) != old.control);
11390
11391 if(vcpu->pre_pcpu != -1) {
11392 spin_lock_irqsave(
11393 &per_cpu(blocked_vcpu_on_cpu_lock,
11394 vcpu->pre_pcpu), flags);
11395 list_del(&vcpu->blocked_vcpu_list);
11396 spin_unlock_irqrestore(
11397 &per_cpu(blocked_vcpu_on_cpu_lock,
11398 vcpu->pre_pcpu), flags);
11399 vcpu->pre_pcpu = -1;
11400 }
11401}
11402
bc22512b
YJ		 11403static void vmx_post_block(struct kvm_vcpu *vcpu)
11404{
64672c95
YJ		 11405 if (kvm_x86_ops->set_hv_timer)
11406 kvm_lapic_switch_to_hv_timer(vcpu);
11407
bc22512b
YJ		 11408 pi_post_block(vcpu);
11409}
11410
efc64404
FW		 11411/*
11412 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11413 *
11414 * @kvm: kvm
11415 * @host_irq: host irq of the interrupt
11416 * @guest_irq: gsi of the interrupt
11417 * @set: set or unset PI
11418 * returns 0 on success, < 0 on failure
11419 */
11420static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11421 uint32_t guest_irq, bool set)
11422{
11423 struct kvm_kernel_irq_routing_entry *e;
11424 struct kvm_irq_routing_table *irq_rt;
11425 struct kvm_lapic_irq irq;
11426 struct kvm_vcpu *vcpu;
11427 struct vcpu_data vcpu_info;
11428 int idx, ret = -EINVAL;
11429
11430 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ		 11431 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11432 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW		 11433 return 0;
11434
11435 idx = srcu_read_lock(&kvm->irq_srcu);
11436 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11437 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11438
11439 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11440 if (e->type != KVM_IRQ_ROUTING_MSI)
11441 continue;
11442 /*
11443 * VT-d PI cannot support posting multicast/broadcast
11444 * interrupts to a vCPU, we still use interrupt remapping
11445 * for these kind of interrupts.
11446 *
11447 * For lowest-priority interrupts, we only support
11448 * those with single CPU as the destination, e.g. user
11449 * configures the interrupts via /proc/irq or uses
11450 * irqbalance to make the interrupts single-CPU.
11451 *
11452 * We will support full lowest-priority interrupt later.
11453 */
11454
37131313 11455 kvm_set_msi_irq(kvm, e, &irq);
23a1c257
FW		 11456 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11457 /*
11458 * Make sure the IRTE is in remapped mode if
11459 * we don't handle it in posted mode.
11460 */
11461 ret = irq_set_vcpu_affinity(host_irq, NULL);
11462 if (ret < 0) {
11463 printk(KERN_INFO
11464 "failed to back to remapped mode, irq: %u\n",
11465 host_irq);
11466 goto out;
11467 }
11468
efc64404 11469 continue;
23a1c257 11470 }
efc64404
FW		 11471
11472 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11473 vcpu_info.vector = irq.vector;
11474
b6ce9780 11475 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
efc64404
FW		 11476 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11477
11478 if (set)
11479 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11480 else {
11481 /* suppress notification event before unposting */
11482 pi_set_sn(vcpu_to_pi_desc(vcpu));
11483 ret = irq_set_vcpu_affinity(host_irq, NULL);
11484 pi_clear_sn(vcpu_to_pi_desc(vcpu));
11485 }
11486
11487 if (ret < 0) {
11488 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11489 __func__);
11490 goto out;
11491 }
11492 }
11493
11494 ret = 0;
11495out:
11496 srcu_read_unlock(&kvm->irq_srcu, idx);
11497 return ret;
11498}
11499
c45dcc71
AR		 11500static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11501{
11502 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11503 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11504 FEATURE_CONTROL_LMCE;
11505 else
11506 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11507 ~FEATURE_CONTROL_LMCE;
11508}
11509
404f6aac 11510static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK		 11511 .cpu_has_kvm_support = cpu_has_kvm_support,
11512 .disabled_by_bios = vmx_disabled_by_bios,
11513 .hardware_setup = hardware_setup,
11514 .hardware_unsetup = hardware_unsetup,
002c7f7c 11515 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 11516 .hardware_enable = hardware_enable,
11517 .hardware_disable = hardware_disable,
04547156 11518 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 11519 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK		 11520
11521 .vcpu_create = vmx_create_vcpu,
11522 .vcpu_free = vmx_free_vcpu,
04d2cc77 11523 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 11524
04d2cc77 11525 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 11526 .vcpu_load = vmx_vcpu_load,
11527 .vcpu_put = vmx_vcpu_put,
11528
a96036b8 11529 .update_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 11530 .get_msr = vmx_get_msr,
11531 .set_msr = vmx_set_msr,
11532 .get_segment_base = vmx_get_segment_base,
11533 .get_segment = vmx_get_segment,
11534 .set_segment = vmx_set_segment,
2e4d2653 11535 .get_cpl = vmx_get_cpl,
6aa8b732 11536 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 11537 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 11538 .decache_cr3 = vmx_decache_cr3,
25c4c276 11539 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 11540 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 11541 .set_cr3 = vmx_set_cr3,
11542 .set_cr4 = vmx_set_cr4,
6aa8b732 11543 .set_efer = vmx_set_efer,
6aa8b732
AK		 11544 .get_idt = vmx_get_idt,
11545 .set_idt = vmx_set_idt,
11546 .get_gdt = vmx_get_gdt,
11547 .set_gdt = vmx_set_gdt,
73aaf249
JK		 11548 .get_dr6 = vmx_get_dr6,
11549 .set_dr6 = vmx_set_dr6,
020df079 11550 .set_dr7 = vmx_set_dr7,
81908bf4 11551 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 11552 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 11553 .get_rflags = vmx_get_rflags,
11554 .set_rflags = vmx_set_rflags,
be94f6b7
HH		 11555
11556 .get_pkru = vmx_get_pkru,
11557
0fdd74f7 11558 .fpu_activate = vmx_fpu_activate,
02daab21 11559 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 11560
11561 .tlb_flush = vmx_flush_tlb,
6aa8b732 11562
6aa8b732 11563 .run = vmx_vcpu_run,
6062d012 11564 .handle_exit = vmx_handle_exit,
6aa8b732 11565 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 11566 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11567 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 11568 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 11569 .set_irq = vmx_inject_irq,
95ba8273 11570 .set_nmi = vmx_inject_nmi,
298101da 11571 .queue_exception = vmx_queue_exception,
b463a6f7 11572 .cancel_injection = vmx_cancel_injection,
78646121 11573 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 11574 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 11575 .get_nmi_mask = vmx_get_nmi_mask,
11576 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 11577 .enable_nmi_window = enable_nmi_window,
11578 .enable_irq_window = enable_irq_window,
11579 .update_cr8_intercept = update_cr8_intercept,
8d14695f 11580 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 11581 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb
AS		 11582 .get_enable_apicv = vmx_get_enable_apicv,
11583 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 11584 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 11585 .apicv_post_state_restore = vmx_apicv_post_state_restore,
c7c9c56c
YZ		 11586 .hwapic_irr_update = vmx_hwapic_irr_update,
11587 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 11588 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11589 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 11590
cbc94022 11591 .set_tss_addr = vmx_set_tss_addr,
67253af5 11592 .get_tdp_level = get_ept_level,
4b12f0de 11593 .get_mt_mask = vmx_get_mt_mask,
229456fc 11594
586f9607 11595 .get_exit_info = vmx_get_exit_info,
586f9607 11596
17cc3935 11597 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 11598
11599 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 11600
11601 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 11602 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 11603
11604 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 11605
11606 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA		 11607
11608 .write_tsc_offset = vmx_write_tsc_offset,
1c97f0a0
JR		 11609
11610 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 11611
11612 .check_intercept = vmx_check_intercept,
a547c6db 11613 .handle_external_intr = vmx_handle_external_intr,
da8999d3 11614 .mpx_supported = vmx_mpx_supported,
55412b2e 11615 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 11616
11617 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 11618
11619 .sched_in = vmx_sched_in,
843e4330
KH		 11620
11621 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11622 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11623 .flush_log_dirty = vmx_flush_log_dirty,
11624 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
25462f7f 11625
bf9f6ac8
FW		 11626 .pre_block = vmx_pre_block,
11627 .post_block = vmx_post_block,
11628
25462f7f 11629 .pmu_ops = &intel_pmu_ops,
efc64404
FW		 11630
11631 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ		 11632
11633#ifdef CONFIG_X86_64
11634 .set_hv_timer = vmx_set_hv_timer,
11635 .cancel_hv_timer = vmx_cancel_hv_timer,
11636#endif
c45dcc71
AR		 11637
11638 .setup_mce = vmx_setup_mce,
6aa8b732
AK		 11639};
11640
11641static int __init vmx_init(void)
11642{
34a1cd60
TC		 11643 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11644 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 11645 if (r)
34a1cd60 11646 return r;
25c5f225 11647
2965faa5 11648#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 11649 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11650 crash_vmclear_local_loaded_vmcss);
11651#endif
11652
fdef3ad1 11653 return 0;
6aa8b732
AK		 11654}
11655
11656static void __exit vmx_exit(void)
11657{
2965faa5 11658#ifdef CONFIG_KEXEC_CORE
3b63a43f 11659 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 11660 synchronize_rcu();
11661#endif
11662
cb498ea2 11663 kvm_exit();
6aa8b732
AK		 11664}
11665
11666module_init(vmx_init)
11667module_exit(vmx_exit)
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