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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
00b27a3e | 21 | #include "cpuid.h" |
d62caabb | 22 | #include "lapic.h" |
e495606d | 23 | |
edf88417 | 24 | #include <linux/kvm_host.h> |
6aa8b732 | 25 | #include <linux/module.h> |
9d8f549d | 26 | #include <linux/kernel.h> |
6aa8b732 AK |
27 | #include <linux/mm.h> |
28 | #include <linux/highmem.h> | |
e8edc6e0 | 29 | #include <linux/sched.h> |
c7addb90 | 30 | #include <linux/moduleparam.h> |
e9bda3b3 | 31 | #include <linux/mod_devicetable.h> |
af658dca | 32 | #include <linux/trace_events.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
cafd6659 | 34 | #include <linux/tboot.h> |
f4124500 | 35 | #include <linux/hrtimer.h> |
5fdbf976 | 36 | #include "kvm_cache_regs.h" |
35920a35 | 37 | #include "x86.h" |
e495606d | 38 | |
28b835d6 | 39 | #include <asm/cpu.h> |
6aa8b732 | 40 | #include <asm/io.h> |
3b3be0d1 | 41 | #include <asm/desc.h> |
13673a90 | 42 | #include <asm/vmx.h> |
6210e37b | 43 | #include <asm/virtext.h> |
a0861c02 | 44 | #include <asm/mce.h> |
952f07ec | 45 | #include <asm/fpu/internal.h> |
d7cd9796 | 46 | #include <asm/perf_event.h> |
81908bf4 | 47 | #include <asm/debugreg.h> |
8f536b76 | 48 | #include <asm/kexec.h> |
dab2087d | 49 | #include <asm/apic.h> |
efc64404 | 50 | #include <asm/irq_remapping.h> |
6aa8b732 | 51 | |
229456fc | 52 | #include "trace.h" |
25462f7f | 53 | #include "pmu.h" |
229456fc | 54 | |
4ecac3fd | 55 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
5e520e62 AK |
56 | #define __ex_clear(x, reg) \ |
57 | ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) | |
4ecac3fd | 58 | |
6aa8b732 AK |
59 | MODULE_AUTHOR("Qumranet"); |
60 | MODULE_LICENSE("GPL"); | |
61 | ||
e9bda3b3 JT |
62 | static const struct x86_cpu_id vmx_cpu_id[] = { |
63 | X86_FEATURE_MATCH(X86_FEATURE_VMX), | |
64 | {} | |
65 | }; | |
66 | MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); | |
67 | ||
476bc001 | 68 | static bool __read_mostly enable_vpid = 1; |
736caefe | 69 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 70 | |
476bc001 | 71 | static bool __read_mostly flexpriority_enabled = 1; |
736caefe | 72 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 73 | |
476bc001 | 74 | static bool __read_mostly enable_ept = 1; |
736caefe | 75 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 76 | |
476bc001 | 77 | static bool __read_mostly enable_unrestricted_guest = 1; |
3a624e29 NK |
78 | module_param_named(unrestricted_guest, |
79 | enable_unrestricted_guest, bool, S_IRUGO); | |
80 | ||
83c3a331 XH |
81 | static bool __read_mostly enable_ept_ad_bits = 1; |
82 | module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); | |
83 | ||
a27685c3 | 84 | static bool __read_mostly emulate_invalid_guest_state = true; |
c1f8bc04 | 85 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 86 | |
476bc001 | 87 | static bool __read_mostly vmm_exclusive = 1; |
b923e62e DX |
88 | module_param(vmm_exclusive, bool, S_IRUGO); |
89 | ||
476bc001 | 90 | static bool __read_mostly fasteoi = 1; |
58fbbf26 KT |
91 | module_param(fasteoi, bool, S_IRUGO); |
92 | ||
5a71785d | 93 | static bool __read_mostly enable_apicv = 1; |
01e439be | 94 | module_param(enable_apicv, bool, S_IRUGO); |
83d4c286 | 95 | |
abc4fc58 AG |
96 | static bool __read_mostly enable_shadow_vmcs = 1; |
97 | module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); | |
801d3424 NHE |
98 | /* |
99 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
100 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
101 | * use VMX instructions. | |
102 | */ | |
476bc001 | 103 | static bool __read_mostly nested = 0; |
801d3424 NHE |
104 | module_param(nested, bool, S_IRUGO); |
105 | ||
20300099 WL |
106 | static u64 __read_mostly host_xss; |
107 | ||
843e4330 KH |
108 | static bool __read_mostly enable_pml = 1; |
109 | module_param_named(pml, enable_pml, bool, S_IRUGO); | |
110 | ||
64903d61 HZ |
111 | #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL |
112 | ||
64672c95 YJ |
113 | /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ |
114 | static int __read_mostly cpu_preemption_timer_multi; | |
115 | static bool __read_mostly enable_preemption_timer = 1; | |
116 | #ifdef CONFIG_X86_64 | |
117 | module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); | |
118 | #endif | |
119 | ||
5037878e GN |
120 | #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD) |
121 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE) | |
cdc0e244 AK |
122 | #define KVM_VM_CR0_ALWAYS_ON \ |
123 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
124 | #define KVM_CR4_GUEST_OWNED_BITS \ |
125 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
52ce3c21 | 126 | | X86_CR4_OSXMMEXCPT | X86_CR4_TSD) |
4c38609a | 127 | |
cdc0e244 AK |
128 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
129 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
130 | ||
78ac8b47 AK |
131 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
132 | ||
f4124500 JK |
133 | #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 |
134 | ||
4b8d54f9 ZE |
135 | /* |
136 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
137 | * ple_gap: upper bound on the amount of time between two successive | |
138 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 139 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
140 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
141 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
142 | * less than 2^12 cycles | |
143 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
144 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
145 | */ | |
b4a2d31d RK |
146 | #define KVM_VMX_DEFAULT_PLE_GAP 128 |
147 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 | |
148 | #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2 | |
149 | #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0 | |
150 | #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \ | |
151 | INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW | |
152 | ||
4b8d54f9 ZE |
153 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; |
154 | module_param(ple_gap, int, S_IRUGO); | |
155 | ||
156 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
157 | module_param(ple_window, int, S_IRUGO); | |
158 | ||
b4a2d31d RK |
159 | /* Default doubles per-vcpu window every exit. */ |
160 | static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW; | |
161 | module_param(ple_window_grow, int, S_IRUGO); | |
162 | ||
163 | /* Default resets per-vcpu window every exit to ple_window. */ | |
164 | static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK; | |
165 | module_param(ple_window_shrink, int, S_IRUGO); | |
166 | ||
167 | /* Default is to compute the maximum so we can never overflow. */ | |
168 | static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
169 | static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
170 | module_param(ple_window_max, int, S_IRUGO); | |
171 | ||
83287ea4 AK |
172 | extern const ulong vmx_return; |
173 | ||
8bf00a52 | 174 | #define NR_AUTOLOAD_MSRS 8 |
ff2f6fe9 | 175 | #define VMCS02_POOL_SIZE 1 |
61d2ef2c | 176 | |
a2fa3e9f GH |
177 | struct vmcs { |
178 | u32 revision_id; | |
179 | u32 abort; | |
180 | char data[0]; | |
181 | }; | |
182 | ||
d462b819 NHE |
183 | /* |
184 | * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also | |
185 | * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs | |
186 | * loaded on this CPU (so we can clear them if the CPU goes down). | |
187 | */ | |
188 | struct loaded_vmcs { | |
189 | struct vmcs *vmcs; | |
355f4fb1 | 190 | struct vmcs *shadow_vmcs; |
d462b819 NHE |
191 | int cpu; |
192 | int launched; | |
193 | struct list_head loaded_vmcss_on_cpu_link; | |
194 | }; | |
195 | ||
26bb0981 AK |
196 | struct shared_msr_entry { |
197 | unsigned index; | |
198 | u64 data; | |
d5696725 | 199 | u64 mask; |
26bb0981 AK |
200 | }; |
201 | ||
a9d30f33 NHE |
202 | /* |
203 | * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a | |
204 | * single nested guest (L2), hence the name vmcs12. Any VMX implementation has | |
205 | * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is | |
206 | * stored in guest memory specified by VMPTRLD, but is opaque to the guest, | |
207 | * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. | |
208 | * More than one of these structures may exist, if L1 runs multiple L2 guests. | |
209 | * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the | |
210 | * underlying hardware which will be used to run L2. | |
211 | * This structure is packed to ensure that its layout is identical across | |
212 | * machines (necessary for live migration). | |
213 | * If there are changes in this struct, VMCS12_REVISION must be changed. | |
214 | */ | |
22bd0358 | 215 | typedef u64 natural_width; |
a9d30f33 NHE |
216 | struct __packed vmcs12 { |
217 | /* According to the Intel spec, a VMCS region must start with the | |
218 | * following two fields. Then follow implementation-specific data. | |
219 | */ | |
220 | u32 revision_id; | |
221 | u32 abort; | |
22bd0358 | 222 | |
27d6c865 NHE |
223 | u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ |
224 | u32 padding[7]; /* room for future expansion */ | |
225 | ||
22bd0358 NHE |
226 | u64 io_bitmap_a; |
227 | u64 io_bitmap_b; | |
228 | u64 msr_bitmap; | |
229 | u64 vm_exit_msr_store_addr; | |
230 | u64 vm_exit_msr_load_addr; | |
231 | u64 vm_entry_msr_load_addr; | |
232 | u64 tsc_offset; | |
233 | u64 virtual_apic_page_addr; | |
234 | u64 apic_access_addr; | |
705699a1 | 235 | u64 posted_intr_desc_addr; |
22bd0358 | 236 | u64 ept_pointer; |
608406e2 WV |
237 | u64 eoi_exit_bitmap0; |
238 | u64 eoi_exit_bitmap1; | |
239 | u64 eoi_exit_bitmap2; | |
240 | u64 eoi_exit_bitmap3; | |
81dc01f7 | 241 | u64 xss_exit_bitmap; |
22bd0358 NHE |
242 | u64 guest_physical_address; |
243 | u64 vmcs_link_pointer; | |
244 | u64 guest_ia32_debugctl; | |
245 | u64 guest_ia32_pat; | |
246 | u64 guest_ia32_efer; | |
247 | u64 guest_ia32_perf_global_ctrl; | |
248 | u64 guest_pdptr0; | |
249 | u64 guest_pdptr1; | |
250 | u64 guest_pdptr2; | |
251 | u64 guest_pdptr3; | |
36be0b9d | 252 | u64 guest_bndcfgs; |
22bd0358 NHE |
253 | u64 host_ia32_pat; |
254 | u64 host_ia32_efer; | |
255 | u64 host_ia32_perf_global_ctrl; | |
256 | u64 padding64[8]; /* room for future expansion */ | |
257 | /* | |
258 | * To allow migration of L1 (complete with its L2 guests) between | |
259 | * machines of different natural widths (32 or 64 bit), we cannot have | |
260 | * unsigned long fields with no explict size. We use u64 (aliased | |
261 | * natural_width) instead. Luckily, x86 is little-endian. | |
262 | */ | |
263 | natural_width cr0_guest_host_mask; | |
264 | natural_width cr4_guest_host_mask; | |
265 | natural_width cr0_read_shadow; | |
266 | natural_width cr4_read_shadow; | |
267 | natural_width cr3_target_value0; | |
268 | natural_width cr3_target_value1; | |
269 | natural_width cr3_target_value2; | |
270 | natural_width cr3_target_value3; | |
271 | natural_width exit_qualification; | |
272 | natural_width guest_linear_address; | |
273 | natural_width guest_cr0; | |
274 | natural_width guest_cr3; | |
275 | natural_width guest_cr4; | |
276 | natural_width guest_es_base; | |
277 | natural_width guest_cs_base; | |
278 | natural_width guest_ss_base; | |
279 | natural_width guest_ds_base; | |
280 | natural_width guest_fs_base; | |
281 | natural_width guest_gs_base; | |
282 | natural_width guest_ldtr_base; | |
283 | natural_width guest_tr_base; | |
284 | natural_width guest_gdtr_base; | |
285 | natural_width guest_idtr_base; | |
286 | natural_width guest_dr7; | |
287 | natural_width guest_rsp; | |
288 | natural_width guest_rip; | |
289 | natural_width guest_rflags; | |
290 | natural_width guest_pending_dbg_exceptions; | |
291 | natural_width guest_sysenter_esp; | |
292 | natural_width guest_sysenter_eip; | |
293 | natural_width host_cr0; | |
294 | natural_width host_cr3; | |
295 | natural_width host_cr4; | |
296 | natural_width host_fs_base; | |
297 | natural_width host_gs_base; | |
298 | natural_width host_tr_base; | |
299 | natural_width host_gdtr_base; | |
300 | natural_width host_idtr_base; | |
301 | natural_width host_ia32_sysenter_esp; | |
302 | natural_width host_ia32_sysenter_eip; | |
303 | natural_width host_rsp; | |
304 | natural_width host_rip; | |
305 | natural_width paddingl[8]; /* room for future expansion */ | |
306 | u32 pin_based_vm_exec_control; | |
307 | u32 cpu_based_vm_exec_control; | |
308 | u32 exception_bitmap; | |
309 | u32 page_fault_error_code_mask; | |
310 | u32 page_fault_error_code_match; | |
311 | u32 cr3_target_count; | |
312 | u32 vm_exit_controls; | |
313 | u32 vm_exit_msr_store_count; | |
314 | u32 vm_exit_msr_load_count; | |
315 | u32 vm_entry_controls; | |
316 | u32 vm_entry_msr_load_count; | |
317 | u32 vm_entry_intr_info_field; | |
318 | u32 vm_entry_exception_error_code; | |
319 | u32 vm_entry_instruction_len; | |
320 | u32 tpr_threshold; | |
321 | u32 secondary_vm_exec_control; | |
322 | u32 vm_instruction_error; | |
323 | u32 vm_exit_reason; | |
324 | u32 vm_exit_intr_info; | |
325 | u32 vm_exit_intr_error_code; | |
326 | u32 idt_vectoring_info_field; | |
327 | u32 idt_vectoring_error_code; | |
328 | u32 vm_exit_instruction_len; | |
329 | u32 vmx_instruction_info; | |
330 | u32 guest_es_limit; | |
331 | u32 guest_cs_limit; | |
332 | u32 guest_ss_limit; | |
333 | u32 guest_ds_limit; | |
334 | u32 guest_fs_limit; | |
335 | u32 guest_gs_limit; | |
336 | u32 guest_ldtr_limit; | |
337 | u32 guest_tr_limit; | |
338 | u32 guest_gdtr_limit; | |
339 | u32 guest_idtr_limit; | |
340 | u32 guest_es_ar_bytes; | |
341 | u32 guest_cs_ar_bytes; | |
342 | u32 guest_ss_ar_bytes; | |
343 | u32 guest_ds_ar_bytes; | |
344 | u32 guest_fs_ar_bytes; | |
345 | u32 guest_gs_ar_bytes; | |
346 | u32 guest_ldtr_ar_bytes; | |
347 | u32 guest_tr_ar_bytes; | |
348 | u32 guest_interruptibility_info; | |
349 | u32 guest_activity_state; | |
350 | u32 guest_sysenter_cs; | |
351 | u32 host_ia32_sysenter_cs; | |
0238ea91 JK |
352 | u32 vmx_preemption_timer_value; |
353 | u32 padding32[7]; /* room for future expansion */ | |
22bd0358 | 354 | u16 virtual_processor_id; |
705699a1 | 355 | u16 posted_intr_nv; |
22bd0358 NHE |
356 | u16 guest_es_selector; |
357 | u16 guest_cs_selector; | |
358 | u16 guest_ss_selector; | |
359 | u16 guest_ds_selector; | |
360 | u16 guest_fs_selector; | |
361 | u16 guest_gs_selector; | |
362 | u16 guest_ldtr_selector; | |
363 | u16 guest_tr_selector; | |
608406e2 | 364 | u16 guest_intr_status; |
22bd0358 NHE |
365 | u16 host_es_selector; |
366 | u16 host_cs_selector; | |
367 | u16 host_ss_selector; | |
368 | u16 host_ds_selector; | |
369 | u16 host_fs_selector; | |
370 | u16 host_gs_selector; | |
371 | u16 host_tr_selector; | |
a9d30f33 NHE |
372 | }; |
373 | ||
374 | /* | |
375 | * VMCS12_REVISION is an arbitrary id that should be changed if the content or | |
376 | * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and | |
377 | * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. | |
378 | */ | |
379 | #define VMCS12_REVISION 0x11e57ed0 | |
380 | ||
381 | /* | |
382 | * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region | |
383 | * and any VMCS region. Although only sizeof(struct vmcs12) are used by the | |
384 | * current implementation, 4K are reserved to avoid future complications. | |
385 | */ | |
386 | #define VMCS12_SIZE 0x1000 | |
387 | ||
ff2f6fe9 NHE |
388 | /* Used to remember the last vmcs02 used for some recently used vmcs12s */ |
389 | struct vmcs02_list { | |
390 | struct list_head list; | |
391 | gpa_t vmptr; | |
392 | struct loaded_vmcs vmcs02; | |
393 | }; | |
394 | ||
ec378aee NHE |
395 | /* |
396 | * The nested_vmx structure is part of vcpu_vmx, and holds information we need | |
397 | * for correct emulation of VMX (i.e., nested VMX) on this vcpu. | |
398 | */ | |
399 | struct nested_vmx { | |
400 | /* Has the level1 guest done vmxon? */ | |
401 | bool vmxon; | |
3573e22c | 402 | gpa_t vmxon_ptr; |
a9d30f33 NHE |
403 | |
404 | /* The guest-physical address of the current VMCS L1 keeps for L2 */ | |
405 | gpa_t current_vmptr; | |
406 | /* The host-usable pointer to the above */ | |
407 | struct page *current_vmcs12_page; | |
408 | struct vmcs12 *current_vmcs12; | |
4f2777bc DM |
409 | /* |
410 | * Cache of the guest's VMCS, existing outside of guest memory. | |
411 | * Loaded from guest memory during VMPTRLD. Flushed to guest | |
412 | * memory during VMXOFF, VMCLEAR, VMPTRLD. | |
413 | */ | |
414 | struct vmcs12 *cached_vmcs12; | |
012f83cb AG |
415 | /* |
416 | * Indicates if the shadow vmcs must be updated with the | |
417 | * data hold by vmcs12 | |
418 | */ | |
419 | bool sync_shadow_vmcs; | |
ff2f6fe9 NHE |
420 | |
421 | /* vmcs02_list cache of VMCSs recently used to run L2 guests */ | |
422 | struct list_head vmcs02_pool; | |
423 | int vmcs02_num; | |
dccbfcf5 | 424 | bool change_vmcs01_virtual_x2apic_mode; |
644d711a NHE |
425 | /* L2 must run next, and mustn't decide to exit to L1. */ |
426 | bool nested_run_pending; | |
fe3ef05c NHE |
427 | /* |
428 | * Guest pages referred to in vmcs02 with host-physical pointers, so | |
429 | * we must keep them pinned while L2 runs. | |
430 | */ | |
431 | struct page *apic_access_page; | |
a7c0b07d | 432 | struct page *virtual_apic_page; |
705699a1 WV |
433 | struct page *pi_desc_page; |
434 | struct pi_desc *pi_desc; | |
435 | bool pi_pending; | |
436 | u16 posted_intr_nv; | |
f4124500 | 437 | |
d048c098 RK |
438 | unsigned long *msr_bitmap; |
439 | ||
f4124500 JK |
440 | struct hrtimer preemption_timer; |
441 | bool preemption_timer_expired; | |
2996fca0 JK |
442 | |
443 | /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ | |
444 | u64 vmcs01_debugctl; | |
b9c237bb | 445 | |
5c614b35 WL |
446 | u16 vpid02; |
447 | u16 last_vpid; | |
448 | ||
b9c237bb WV |
449 | u32 nested_vmx_procbased_ctls_low; |
450 | u32 nested_vmx_procbased_ctls_high; | |
451 | u32 nested_vmx_true_procbased_ctls_low; | |
452 | u32 nested_vmx_secondary_ctls_low; | |
453 | u32 nested_vmx_secondary_ctls_high; | |
454 | u32 nested_vmx_pinbased_ctls_low; | |
455 | u32 nested_vmx_pinbased_ctls_high; | |
456 | u32 nested_vmx_exit_ctls_low; | |
457 | u32 nested_vmx_exit_ctls_high; | |
458 | u32 nested_vmx_true_exit_ctls_low; | |
459 | u32 nested_vmx_entry_ctls_low; | |
460 | u32 nested_vmx_entry_ctls_high; | |
461 | u32 nested_vmx_true_entry_ctls_low; | |
462 | u32 nested_vmx_misc_low; | |
463 | u32 nested_vmx_misc_high; | |
464 | u32 nested_vmx_ept_caps; | |
99b83ac8 | 465 | u32 nested_vmx_vpid_caps; |
ec378aee NHE |
466 | }; |
467 | ||
01e439be | 468 | #define POSTED_INTR_ON 0 |
ebbfc765 FW |
469 | #define POSTED_INTR_SN 1 |
470 | ||
01e439be YZ |
471 | /* Posted-Interrupt Descriptor */ |
472 | struct pi_desc { | |
473 | u32 pir[8]; /* Posted interrupt requested */ | |
6ef1522f FW |
474 | union { |
475 | struct { | |
476 | /* bit 256 - Outstanding Notification */ | |
477 | u16 on : 1, | |
478 | /* bit 257 - Suppress Notification */ | |
479 | sn : 1, | |
480 | /* bit 271:258 - Reserved */ | |
481 | rsvd_1 : 14; | |
482 | /* bit 279:272 - Notification Vector */ | |
483 | u8 nv; | |
484 | /* bit 287:280 - Reserved */ | |
485 | u8 rsvd_2; | |
486 | /* bit 319:288 - Notification Destination */ | |
487 | u32 ndst; | |
488 | }; | |
489 | u64 control; | |
490 | }; | |
491 | u32 rsvd[6]; | |
01e439be YZ |
492 | } __aligned(64); |
493 | ||
a20ed54d YZ |
494 | static bool pi_test_and_set_on(struct pi_desc *pi_desc) |
495 | { | |
496 | return test_and_set_bit(POSTED_INTR_ON, | |
497 | (unsigned long *)&pi_desc->control); | |
498 | } | |
499 | ||
500 | static bool pi_test_and_clear_on(struct pi_desc *pi_desc) | |
501 | { | |
502 | return test_and_clear_bit(POSTED_INTR_ON, | |
503 | (unsigned long *)&pi_desc->control); | |
504 | } | |
505 | ||
506 | static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) | |
507 | { | |
508 | return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); | |
509 | } | |
510 | ||
ebbfc765 FW |
511 | static inline void pi_clear_sn(struct pi_desc *pi_desc) |
512 | { | |
513 | return clear_bit(POSTED_INTR_SN, | |
514 | (unsigned long *)&pi_desc->control); | |
515 | } | |
516 | ||
517 | static inline void pi_set_sn(struct pi_desc *pi_desc) | |
518 | { | |
519 | return set_bit(POSTED_INTR_SN, | |
520 | (unsigned long *)&pi_desc->control); | |
521 | } | |
522 | ||
ad361091 PB |
523 | static inline void pi_clear_on(struct pi_desc *pi_desc) |
524 | { | |
525 | clear_bit(POSTED_INTR_ON, | |
526 | (unsigned long *)&pi_desc->control); | |
527 | } | |
528 | ||
ebbfc765 FW |
529 | static inline int pi_test_on(struct pi_desc *pi_desc) |
530 | { | |
531 | return test_bit(POSTED_INTR_ON, | |
532 | (unsigned long *)&pi_desc->control); | |
533 | } | |
534 | ||
535 | static inline int pi_test_sn(struct pi_desc *pi_desc) | |
536 | { | |
537 | return test_bit(POSTED_INTR_SN, | |
538 | (unsigned long *)&pi_desc->control); | |
539 | } | |
540 | ||
a2fa3e9f | 541 | struct vcpu_vmx { |
fb3f0f51 | 542 | struct kvm_vcpu vcpu; |
313dbd49 | 543 | unsigned long host_rsp; |
29bd8a78 | 544 | u8 fail; |
9d58b931 | 545 | bool nmi_known_unmasked; |
51aa01d1 | 546 | u32 exit_intr_info; |
1155f76a | 547 | u32 idt_vectoring_info; |
6de12732 | 548 | ulong rflags; |
26bb0981 | 549 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
550 | int nmsrs; |
551 | int save_nmsrs; | |
a547c6db | 552 | unsigned long host_idt_base; |
a2fa3e9f | 553 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
554 | u64 msr_host_kernel_gs_base; |
555 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f | 556 | #endif |
2961e876 GN |
557 | u32 vm_entry_controls_shadow; |
558 | u32 vm_exit_controls_shadow; | |
d462b819 NHE |
559 | /* |
560 | * loaded_vmcs points to the VMCS currently used in this vcpu. For a | |
561 | * non-nested (L1) guest, it always points to vmcs01. For a nested | |
562 | * guest (L2), it points to a different VMCS. | |
563 | */ | |
564 | struct loaded_vmcs vmcs01; | |
565 | struct loaded_vmcs *loaded_vmcs; | |
566 | bool __launched; /* temporary, used in vmx_vcpu_run */ | |
61d2ef2c AK |
567 | struct msr_autoload { |
568 | unsigned nr; | |
569 | struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; | |
570 | struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; | |
571 | } msr_autoload; | |
a2fa3e9f GH |
572 | struct { |
573 | int loaded; | |
574 | u16 fs_sel, gs_sel, ldt_sel; | |
b2da15ac AK |
575 | #ifdef CONFIG_X86_64 |
576 | u16 ds_sel, es_sel; | |
577 | #endif | |
152d3f2f LV |
578 | int gs_ldt_reload_needed; |
579 | int fs_reload_needed; | |
da8999d3 | 580 | u64 msr_host_bndcfgs; |
d974baa3 | 581 | unsigned long vmcs_host_cr4; /* May not match real cr4 */ |
d77c26fc | 582 | } host_state; |
9c8cba37 | 583 | struct { |
7ffd92c5 | 584 | int vm86_active; |
78ac8b47 | 585 | ulong save_rflags; |
f5f7b2fe AK |
586 | struct kvm_segment segs[8]; |
587 | } rmode; | |
588 | struct { | |
589 | u32 bitmask; /* 4 bits per segment (1 bit per field) */ | |
7ffd92c5 AK |
590 | struct kvm_save_segment { |
591 | u16 selector; | |
592 | unsigned long base; | |
593 | u32 limit; | |
594 | u32 ar; | |
f5f7b2fe | 595 | } seg[8]; |
2fb92db1 | 596 | } segment_cache; |
2384d2b3 | 597 | int vpid; |
04fa4d32 | 598 | bool emulation_required; |
3b86cd99 JK |
599 | |
600 | /* Support for vnmi-less CPUs */ | |
601 | int soft_vnmi_blocked; | |
602 | ktime_t entry_time; | |
603 | s64 vnmi_blocked_time; | |
a0861c02 | 604 | u32 exit_reason; |
4e47c7a6 | 605 | |
01e439be YZ |
606 | /* Posted interrupt descriptor */ |
607 | struct pi_desc pi_desc; | |
608 | ||
ec378aee NHE |
609 | /* Support for a guest hypervisor (nested VMX) */ |
610 | struct nested_vmx nested; | |
a7653ecd RK |
611 | |
612 | /* Dynamic PLE window. */ | |
613 | int ple_window; | |
614 | bool ple_window_dirty; | |
843e4330 KH |
615 | |
616 | /* Support for PML */ | |
617 | #define PML_ENTITY_NUM 512 | |
618 | struct page *pml_pg; | |
2680d6da | 619 | |
64672c95 YJ |
620 | /* apic deadline value in host tsc */ |
621 | u64 hv_deadline_tsc; | |
622 | ||
2680d6da | 623 | u64 current_tsc_ratio; |
1be0e61c XG |
624 | |
625 | bool guest_pkru_valid; | |
626 | u32 guest_pkru; | |
627 | u32 host_pkru; | |
3b84080b | 628 | |
37e4c997 HZ |
629 | /* |
630 | * Only bits masked by msr_ia32_feature_control_valid_bits can be set in | |
631 | * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included | |
632 | * in msr_ia32_feature_control_valid_bits. | |
633 | */ | |
3b84080b | 634 | u64 msr_ia32_feature_control; |
37e4c997 | 635 | u64 msr_ia32_feature_control_valid_bits; |
a2fa3e9f GH |
636 | }; |
637 | ||
2fb92db1 AK |
638 | enum segment_cache_field { |
639 | SEG_FIELD_SEL = 0, | |
640 | SEG_FIELD_BASE = 1, | |
641 | SEG_FIELD_LIMIT = 2, | |
642 | SEG_FIELD_AR = 3, | |
643 | ||
644 | SEG_FIELD_NR = 4 | |
645 | }; | |
646 | ||
a2fa3e9f GH |
647 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
648 | { | |
fb3f0f51 | 649 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
650 | } |
651 | ||
efc64404 FW |
652 | static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu) |
653 | { | |
654 | return &(to_vmx(vcpu)->pi_desc); | |
655 | } | |
656 | ||
22bd0358 NHE |
657 | #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x) |
658 | #define FIELD(number, name) [number] = VMCS12_OFFSET(name) | |
659 | #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \ | |
660 | [number##_HIGH] = VMCS12_OFFSET(name)+4 | |
661 | ||
4607c2d7 | 662 | |
fe2b201b | 663 | static unsigned long shadow_read_only_fields[] = { |
4607c2d7 AG |
664 | /* |
665 | * We do NOT shadow fields that are modified when L0 | |
666 | * traps and emulates any vmx instruction (e.g. VMPTRLD, | |
667 | * VMXON...) executed by L1. | |
668 | * For example, VM_INSTRUCTION_ERROR is read | |
669 | * by L1 if a vmx instruction fails (part of the error path). | |
670 | * Note the code assumes this logic. If for some reason | |
671 | * we start shadowing these fields then we need to | |
672 | * force a shadow sync when L0 emulates vmx instructions | |
673 | * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified | |
674 | * by nested_vmx_failValid) | |
675 | */ | |
676 | VM_EXIT_REASON, | |
677 | VM_EXIT_INTR_INFO, | |
678 | VM_EXIT_INSTRUCTION_LEN, | |
679 | IDT_VECTORING_INFO_FIELD, | |
680 | IDT_VECTORING_ERROR_CODE, | |
681 | VM_EXIT_INTR_ERROR_CODE, | |
682 | EXIT_QUALIFICATION, | |
683 | GUEST_LINEAR_ADDRESS, | |
684 | GUEST_PHYSICAL_ADDRESS | |
685 | }; | |
fe2b201b | 686 | static int max_shadow_read_only_fields = |
4607c2d7 AG |
687 | ARRAY_SIZE(shadow_read_only_fields); |
688 | ||
fe2b201b | 689 | static unsigned long shadow_read_write_fields[] = { |
a7c0b07d | 690 | TPR_THRESHOLD, |
4607c2d7 AG |
691 | GUEST_RIP, |
692 | GUEST_RSP, | |
693 | GUEST_CR0, | |
694 | GUEST_CR3, | |
695 | GUEST_CR4, | |
696 | GUEST_INTERRUPTIBILITY_INFO, | |
697 | GUEST_RFLAGS, | |
698 | GUEST_CS_SELECTOR, | |
699 | GUEST_CS_AR_BYTES, | |
700 | GUEST_CS_LIMIT, | |
701 | GUEST_CS_BASE, | |
702 | GUEST_ES_BASE, | |
36be0b9d | 703 | GUEST_BNDCFGS, |
4607c2d7 AG |
704 | CR0_GUEST_HOST_MASK, |
705 | CR0_READ_SHADOW, | |
706 | CR4_READ_SHADOW, | |
707 | TSC_OFFSET, | |
708 | EXCEPTION_BITMAP, | |
709 | CPU_BASED_VM_EXEC_CONTROL, | |
710 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
711 | VM_ENTRY_INTR_INFO_FIELD, | |
712 | VM_ENTRY_INSTRUCTION_LEN, | |
713 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
714 | HOST_FS_BASE, | |
715 | HOST_GS_BASE, | |
716 | HOST_FS_SELECTOR, | |
717 | HOST_GS_SELECTOR | |
718 | }; | |
fe2b201b | 719 | static int max_shadow_read_write_fields = |
4607c2d7 AG |
720 | ARRAY_SIZE(shadow_read_write_fields); |
721 | ||
772e0318 | 722 | static const unsigned short vmcs_field_to_offset_table[] = { |
22bd0358 | 723 | FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id), |
705699a1 | 724 | FIELD(POSTED_INTR_NV, posted_intr_nv), |
22bd0358 NHE |
725 | FIELD(GUEST_ES_SELECTOR, guest_es_selector), |
726 | FIELD(GUEST_CS_SELECTOR, guest_cs_selector), | |
727 | FIELD(GUEST_SS_SELECTOR, guest_ss_selector), | |
728 | FIELD(GUEST_DS_SELECTOR, guest_ds_selector), | |
729 | FIELD(GUEST_FS_SELECTOR, guest_fs_selector), | |
730 | FIELD(GUEST_GS_SELECTOR, guest_gs_selector), | |
731 | FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector), | |
732 | FIELD(GUEST_TR_SELECTOR, guest_tr_selector), | |
608406e2 | 733 | FIELD(GUEST_INTR_STATUS, guest_intr_status), |
22bd0358 NHE |
734 | FIELD(HOST_ES_SELECTOR, host_es_selector), |
735 | FIELD(HOST_CS_SELECTOR, host_cs_selector), | |
736 | FIELD(HOST_SS_SELECTOR, host_ss_selector), | |
737 | FIELD(HOST_DS_SELECTOR, host_ds_selector), | |
738 | FIELD(HOST_FS_SELECTOR, host_fs_selector), | |
739 | FIELD(HOST_GS_SELECTOR, host_gs_selector), | |
740 | FIELD(HOST_TR_SELECTOR, host_tr_selector), | |
741 | FIELD64(IO_BITMAP_A, io_bitmap_a), | |
742 | FIELD64(IO_BITMAP_B, io_bitmap_b), | |
743 | FIELD64(MSR_BITMAP, msr_bitmap), | |
744 | FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr), | |
745 | FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr), | |
746 | FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr), | |
747 | FIELD64(TSC_OFFSET, tsc_offset), | |
748 | FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), | |
749 | FIELD64(APIC_ACCESS_ADDR, apic_access_addr), | |
705699a1 | 750 | FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr), |
22bd0358 | 751 | FIELD64(EPT_POINTER, ept_pointer), |
608406e2 WV |
752 | FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0), |
753 | FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1), | |
754 | FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2), | |
755 | FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3), | |
81dc01f7 | 756 | FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap), |
22bd0358 NHE |
757 | FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), |
758 | FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), | |
759 | FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), | |
760 | FIELD64(GUEST_IA32_PAT, guest_ia32_pat), | |
761 | FIELD64(GUEST_IA32_EFER, guest_ia32_efer), | |
762 | FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl), | |
763 | FIELD64(GUEST_PDPTR0, guest_pdptr0), | |
764 | FIELD64(GUEST_PDPTR1, guest_pdptr1), | |
765 | FIELD64(GUEST_PDPTR2, guest_pdptr2), | |
766 | FIELD64(GUEST_PDPTR3, guest_pdptr3), | |
36be0b9d | 767 | FIELD64(GUEST_BNDCFGS, guest_bndcfgs), |
22bd0358 NHE |
768 | FIELD64(HOST_IA32_PAT, host_ia32_pat), |
769 | FIELD64(HOST_IA32_EFER, host_ia32_efer), | |
770 | FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), | |
771 | FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), | |
772 | FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), | |
773 | FIELD(EXCEPTION_BITMAP, exception_bitmap), | |
774 | FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask), | |
775 | FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match), | |
776 | FIELD(CR3_TARGET_COUNT, cr3_target_count), | |
777 | FIELD(VM_EXIT_CONTROLS, vm_exit_controls), | |
778 | FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count), | |
779 | FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count), | |
780 | FIELD(VM_ENTRY_CONTROLS, vm_entry_controls), | |
781 | FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count), | |
782 | FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field), | |
783 | FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code), | |
784 | FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len), | |
785 | FIELD(TPR_THRESHOLD, tpr_threshold), | |
786 | FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control), | |
787 | FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error), | |
788 | FIELD(VM_EXIT_REASON, vm_exit_reason), | |
789 | FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info), | |
790 | FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code), | |
791 | FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field), | |
792 | FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code), | |
793 | FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len), | |
794 | FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info), | |
795 | FIELD(GUEST_ES_LIMIT, guest_es_limit), | |
796 | FIELD(GUEST_CS_LIMIT, guest_cs_limit), | |
797 | FIELD(GUEST_SS_LIMIT, guest_ss_limit), | |
798 | FIELD(GUEST_DS_LIMIT, guest_ds_limit), | |
799 | FIELD(GUEST_FS_LIMIT, guest_fs_limit), | |
800 | FIELD(GUEST_GS_LIMIT, guest_gs_limit), | |
801 | FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit), | |
802 | FIELD(GUEST_TR_LIMIT, guest_tr_limit), | |
803 | FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit), | |
804 | FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit), | |
805 | FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes), | |
806 | FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes), | |
807 | FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes), | |
808 | FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes), | |
809 | FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes), | |
810 | FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes), | |
811 | FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes), | |
812 | FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes), | |
813 | FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info), | |
814 | FIELD(GUEST_ACTIVITY_STATE, guest_activity_state), | |
815 | FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs), | |
816 | FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs), | |
0238ea91 | 817 | FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value), |
22bd0358 NHE |
818 | FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask), |
819 | FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask), | |
820 | FIELD(CR0_READ_SHADOW, cr0_read_shadow), | |
821 | FIELD(CR4_READ_SHADOW, cr4_read_shadow), | |
822 | FIELD(CR3_TARGET_VALUE0, cr3_target_value0), | |
823 | FIELD(CR3_TARGET_VALUE1, cr3_target_value1), | |
824 | FIELD(CR3_TARGET_VALUE2, cr3_target_value2), | |
825 | FIELD(CR3_TARGET_VALUE3, cr3_target_value3), | |
826 | FIELD(EXIT_QUALIFICATION, exit_qualification), | |
827 | FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address), | |
828 | FIELD(GUEST_CR0, guest_cr0), | |
829 | FIELD(GUEST_CR3, guest_cr3), | |
830 | FIELD(GUEST_CR4, guest_cr4), | |
831 | FIELD(GUEST_ES_BASE, guest_es_base), | |
832 | FIELD(GUEST_CS_BASE, guest_cs_base), | |
833 | FIELD(GUEST_SS_BASE, guest_ss_base), | |
834 | FIELD(GUEST_DS_BASE, guest_ds_base), | |
835 | FIELD(GUEST_FS_BASE, guest_fs_base), | |
836 | FIELD(GUEST_GS_BASE, guest_gs_base), | |
837 | FIELD(GUEST_LDTR_BASE, guest_ldtr_base), | |
838 | FIELD(GUEST_TR_BASE, guest_tr_base), | |
839 | FIELD(GUEST_GDTR_BASE, guest_gdtr_base), | |
840 | FIELD(GUEST_IDTR_BASE, guest_idtr_base), | |
841 | FIELD(GUEST_DR7, guest_dr7), | |
842 | FIELD(GUEST_RSP, guest_rsp), | |
843 | FIELD(GUEST_RIP, guest_rip), | |
844 | FIELD(GUEST_RFLAGS, guest_rflags), | |
845 | FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions), | |
846 | FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp), | |
847 | FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip), | |
848 | FIELD(HOST_CR0, host_cr0), | |
849 | FIELD(HOST_CR3, host_cr3), | |
850 | FIELD(HOST_CR4, host_cr4), | |
851 | FIELD(HOST_FS_BASE, host_fs_base), | |
852 | FIELD(HOST_GS_BASE, host_gs_base), | |
853 | FIELD(HOST_TR_BASE, host_tr_base), | |
854 | FIELD(HOST_GDTR_BASE, host_gdtr_base), | |
855 | FIELD(HOST_IDTR_BASE, host_idtr_base), | |
856 | FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp), | |
857 | FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip), | |
858 | FIELD(HOST_RSP, host_rsp), | |
859 | FIELD(HOST_RIP, host_rip), | |
860 | }; | |
22bd0358 NHE |
861 | |
862 | static inline short vmcs_field_to_offset(unsigned long field) | |
863 | { | |
a2ae9df7 PB |
864 | BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX); |
865 | ||
866 | if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) || | |
867 | vmcs_field_to_offset_table[field] == 0) | |
868 | return -ENOENT; | |
869 | ||
22bd0358 NHE |
870 | return vmcs_field_to_offset_table[field]; |
871 | } | |
872 | ||
a9d30f33 NHE |
873 | static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
874 | { | |
4f2777bc | 875 | return to_vmx(vcpu)->nested.cached_vmcs12; |
a9d30f33 NHE |
876 | } |
877 | ||
878 | static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr) | |
879 | { | |
54bf36aa | 880 | struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT); |
32cad84f | 881 | if (is_error_page(page)) |
a9d30f33 | 882 | return NULL; |
32cad84f | 883 | |
a9d30f33 NHE |
884 | return page; |
885 | } | |
886 | ||
887 | static void nested_release_page(struct page *page) | |
888 | { | |
889 | kvm_release_page_dirty(page); | |
890 | } | |
891 | ||
892 | static void nested_release_page_clean(struct page *page) | |
893 | { | |
894 | kvm_release_page_clean(page); | |
895 | } | |
896 | ||
bfd0a56b | 897 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu); |
4e1096d2 | 898 | static u64 construct_eptp(unsigned long root_hpa); |
4610c9cc DX |
899 | static void kvm_cpu_vmxon(u64 addr); |
900 | static void kvm_cpu_vmxoff(void); | |
f53cd63c | 901 | static bool vmx_xsaves_supported(void); |
776e58ea | 902 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr); |
b246dd5d OW |
903 | static void vmx_set_segment(struct kvm_vcpu *vcpu, |
904 | struct kvm_segment *var, int seg); | |
905 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
906 | struct kvm_segment *var, int seg); | |
d99e4152 GN |
907 | static bool guest_state_valid(struct kvm_vcpu *vcpu); |
908 | static u32 vmx_segment_access_rights(struct kvm_segment *var); | |
c3114420 | 909 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx); |
16f5b903 | 910 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx); |
a255d479 | 911 | static int alloc_identity_pagetable(struct kvm *kvm); |
75880a01 | 912 | |
6aa8b732 AK |
913 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
914 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
d462b819 NHE |
915 | /* |
916 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
917 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
918 | */ | |
919 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
3444d7da | 920 | static DEFINE_PER_CPU(struct desc_ptr, host_gdt); |
6aa8b732 | 921 | |
bf9f6ac8 FW |
922 | /* |
923 | * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we | |
924 | * can find which vCPU should be waken up. | |
925 | */ | |
926 | static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); | |
927 | static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); | |
928 | ||
23611332 RK |
929 | enum { |
930 | VMX_IO_BITMAP_A, | |
931 | VMX_IO_BITMAP_B, | |
932 | VMX_MSR_BITMAP_LEGACY, | |
933 | VMX_MSR_BITMAP_LONGMODE, | |
934 | VMX_MSR_BITMAP_LEGACY_X2APIC_APICV, | |
935 | VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV, | |
936 | VMX_MSR_BITMAP_LEGACY_X2APIC, | |
937 | VMX_MSR_BITMAP_LONGMODE_X2APIC, | |
938 | VMX_VMREAD_BITMAP, | |
939 | VMX_VMWRITE_BITMAP, | |
940 | VMX_BITMAP_NR | |
941 | }; | |
942 | ||
943 | static unsigned long *vmx_bitmap[VMX_BITMAP_NR]; | |
944 | ||
945 | #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A]) | |
946 | #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B]) | |
947 | #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY]) | |
948 | #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE]) | |
949 | #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV]) | |
950 | #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV]) | |
951 | #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC]) | |
952 | #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC]) | |
953 | #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP]) | |
954 | #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP]) | |
fdef3ad1 | 955 | |
110312c8 | 956 | static bool cpu_has_load_ia32_efer; |
8bf00a52 | 957 | static bool cpu_has_load_perf_global_ctrl; |
110312c8 | 958 | |
2384d2b3 SY |
959 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
960 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
961 | ||
1c3d14fe | 962 | static struct vmcs_config { |
6aa8b732 AK |
963 | int size; |
964 | int order; | |
9ac7e3e8 | 965 | u32 basic_cap; |
6aa8b732 | 966 | u32 revision_id; |
1c3d14fe YS |
967 | u32 pin_based_exec_ctrl; |
968 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 969 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
970 | u32 vmexit_ctrl; |
971 | u32 vmentry_ctrl; | |
972 | } vmcs_config; | |
6aa8b732 | 973 | |
efff9e53 | 974 | static struct vmx_capability { |
d56f546d SY |
975 | u32 ept; |
976 | u32 vpid; | |
977 | } vmx_capability; | |
978 | ||
6aa8b732 AK |
979 | #define VMX_SEGMENT_FIELD(seg) \ |
980 | [VCPU_SREG_##seg] = { \ | |
981 | .selector = GUEST_##seg##_SELECTOR, \ | |
982 | .base = GUEST_##seg##_BASE, \ | |
983 | .limit = GUEST_##seg##_LIMIT, \ | |
984 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
985 | } | |
986 | ||
772e0318 | 987 | static const struct kvm_vmx_segment_field { |
6aa8b732 AK |
988 | unsigned selector; |
989 | unsigned base; | |
990 | unsigned limit; | |
991 | unsigned ar_bytes; | |
992 | } kvm_vmx_segment_fields[] = { | |
993 | VMX_SEGMENT_FIELD(CS), | |
994 | VMX_SEGMENT_FIELD(DS), | |
995 | VMX_SEGMENT_FIELD(ES), | |
996 | VMX_SEGMENT_FIELD(FS), | |
997 | VMX_SEGMENT_FIELD(GS), | |
998 | VMX_SEGMENT_FIELD(SS), | |
999 | VMX_SEGMENT_FIELD(TR), | |
1000 | VMX_SEGMENT_FIELD(LDTR), | |
1001 | }; | |
1002 | ||
26bb0981 AK |
1003 | static u64 host_efer; |
1004 | ||
6de4f3ad AK |
1005 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
1006 | ||
4d56c8a7 | 1007 | /* |
8c06585d | 1008 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
1009 | * away by decrementing the array size. |
1010 | */ | |
6aa8b732 | 1011 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 1012 | #ifdef CONFIG_X86_64 |
44ea2b17 | 1013 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 1014 | #endif |
8c06585d | 1015 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 1016 | }; |
6aa8b732 | 1017 | |
5bb16016 | 1018 | static inline bool is_exception_n(u32 intr_info, u8 vector) |
6aa8b732 AK |
1019 | { |
1020 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1021 | INTR_INFO_VALID_MASK)) == | |
5bb16016 JK |
1022 | (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK); |
1023 | } | |
1024 | ||
6f05485d JK |
1025 | static inline bool is_debug(u32 intr_info) |
1026 | { | |
1027 | return is_exception_n(intr_info, DB_VECTOR); | |
1028 | } | |
1029 | ||
1030 | static inline bool is_breakpoint(u32 intr_info) | |
1031 | { | |
1032 | return is_exception_n(intr_info, BP_VECTOR); | |
1033 | } | |
1034 | ||
5bb16016 JK |
1035 | static inline bool is_page_fault(u32 intr_info) |
1036 | { | |
1037 | return is_exception_n(intr_info, PF_VECTOR); | |
6aa8b732 AK |
1038 | } |
1039 | ||
31299944 | 1040 | static inline bool is_no_device(u32 intr_info) |
2ab455cc | 1041 | { |
5bb16016 | 1042 | return is_exception_n(intr_info, NM_VECTOR); |
2ab455cc AL |
1043 | } |
1044 | ||
31299944 | 1045 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 | 1046 | { |
5bb16016 | 1047 | return is_exception_n(intr_info, UD_VECTOR); |
7aa81cc0 AL |
1048 | } |
1049 | ||
31299944 | 1050 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
1051 | { |
1052 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1053 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1054 | } | |
1055 | ||
31299944 | 1056 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
1057 | { |
1058 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1059 | INTR_INFO_VALID_MASK)) == | |
1060 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
1061 | } | |
1062 | ||
31299944 | 1063 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 1064 | { |
04547156 | 1065 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
1066 | } |
1067 | ||
31299944 | 1068 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 1069 | { |
04547156 | 1070 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
1071 | } |
1072 | ||
35754c98 | 1073 | static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) |
6e5d865c | 1074 | { |
35754c98 | 1075 | return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); |
6e5d865c YS |
1076 | } |
1077 | ||
31299944 | 1078 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 1079 | { |
04547156 SY |
1080 | return vmcs_config.cpu_based_exec_ctrl & |
1081 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
1082 | } |
1083 | ||
774ead3a | 1084 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 1085 | { |
04547156 SY |
1086 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1087 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1088 | } | |
1089 | ||
8d14695f YZ |
1090 | static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) |
1091 | { | |
1092 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1093 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
1094 | } | |
1095 | ||
83d4c286 YZ |
1096 | static inline bool cpu_has_vmx_apic_register_virt(void) |
1097 | { | |
1098 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1099 | SECONDARY_EXEC_APIC_REGISTER_VIRT; | |
1100 | } | |
1101 | ||
c7c9c56c YZ |
1102 | static inline bool cpu_has_vmx_virtual_intr_delivery(void) |
1103 | { | |
1104 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1105 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; | |
1106 | } | |
1107 | ||
64672c95 YJ |
1108 | /* |
1109 | * Comment's format: document - errata name - stepping - processor name. | |
1110 | * Refer from | |
1111 | * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp | |
1112 | */ | |
1113 | static u32 vmx_preemption_cpu_tfms[] = { | |
1114 | /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ | |
1115 | 0x000206E6, | |
1116 | /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ | |
1117 | /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ | |
1118 | /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1119 | 0x00020652, | |
1120 | /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1121 | 0x00020655, | |
1122 | /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ | |
1123 | /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ | |
1124 | /* | |
1125 | * 320767.pdf - AAP86 - B1 - | |
1126 | * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile | |
1127 | */ | |
1128 | 0x000106E5, | |
1129 | /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ | |
1130 | 0x000106A0, | |
1131 | /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ | |
1132 | 0x000106A1, | |
1133 | /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ | |
1134 | 0x000106A4, | |
1135 | /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ | |
1136 | /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ | |
1137 | /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ | |
1138 | 0x000106A5, | |
1139 | }; | |
1140 | ||
1141 | static inline bool cpu_has_broken_vmx_preemption_timer(void) | |
1142 | { | |
1143 | u32 eax = cpuid_eax(0x00000001), i; | |
1144 | ||
1145 | /* Clear the reserved bits */ | |
1146 | eax &= ~(0x3U << 14 | 0xfU << 28); | |
03f6a22a | 1147 | for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) |
64672c95 YJ |
1148 | if (eax == vmx_preemption_cpu_tfms[i]) |
1149 | return true; | |
1150 | ||
1151 | return false; | |
1152 | } | |
1153 | ||
1154 | static inline bool cpu_has_vmx_preemption_timer(void) | |
1155 | { | |
64672c95 YJ |
1156 | return vmcs_config.pin_based_exec_ctrl & |
1157 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1158 | } | |
1159 | ||
01e439be YZ |
1160 | static inline bool cpu_has_vmx_posted_intr(void) |
1161 | { | |
d6a858d1 PB |
1162 | return IS_ENABLED(CONFIG_X86_LOCAL_APIC) && |
1163 | vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; | |
01e439be YZ |
1164 | } |
1165 | ||
1166 | static inline bool cpu_has_vmx_apicv(void) | |
1167 | { | |
1168 | return cpu_has_vmx_apic_register_virt() && | |
1169 | cpu_has_vmx_virtual_intr_delivery() && | |
1170 | cpu_has_vmx_posted_intr(); | |
1171 | } | |
1172 | ||
04547156 SY |
1173 | static inline bool cpu_has_vmx_flexpriority(void) |
1174 | { | |
1175 | return cpu_has_vmx_tpr_shadow() && | |
1176 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
1177 | } |
1178 | ||
e799794e MT |
1179 | static inline bool cpu_has_vmx_ept_execute_only(void) |
1180 | { | |
31299944 | 1181 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
1182 | } |
1183 | ||
e799794e MT |
1184 | static inline bool cpu_has_vmx_ept_2m_page(void) |
1185 | { | |
31299944 | 1186 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
1187 | } |
1188 | ||
878403b7 SY |
1189 | static inline bool cpu_has_vmx_ept_1g_page(void) |
1190 | { | |
31299944 | 1191 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
1192 | } |
1193 | ||
4bc9b982 SY |
1194 | static inline bool cpu_has_vmx_ept_4levels(void) |
1195 | { | |
1196 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
1197 | } | |
1198 | ||
83c3a331 XH |
1199 | static inline bool cpu_has_vmx_ept_ad_bits(void) |
1200 | { | |
1201 | return vmx_capability.ept & VMX_EPT_AD_BIT; | |
1202 | } | |
1203 | ||
31299944 | 1204 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 1205 | { |
31299944 | 1206 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
1207 | } |
1208 | ||
31299944 | 1209 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 1210 | { |
31299944 | 1211 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
1212 | } |
1213 | ||
518c8aee GJ |
1214 | static inline bool cpu_has_vmx_invvpid_single(void) |
1215 | { | |
1216 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
1217 | } | |
1218 | ||
b9d762fa GJ |
1219 | static inline bool cpu_has_vmx_invvpid_global(void) |
1220 | { | |
1221 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
1222 | } | |
1223 | ||
31299944 | 1224 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 1225 | { |
04547156 SY |
1226 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1227 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
1228 | } |
1229 | ||
31299944 | 1230 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
1231 | { |
1232 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1233 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
1234 | } | |
1235 | ||
31299944 | 1236 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
1237 | { |
1238 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1239 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
1240 | } | |
1241 | ||
9ac7e3e8 JD |
1242 | static inline bool cpu_has_vmx_basic_inout(void) |
1243 | { | |
1244 | return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT); | |
1245 | } | |
1246 | ||
35754c98 | 1247 | static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) |
f78e0e2e | 1248 | { |
35754c98 | 1249 | return flexpriority_enabled && lapic_in_kernel(vcpu); |
f78e0e2e SY |
1250 | } |
1251 | ||
31299944 | 1252 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 1253 | { |
04547156 SY |
1254 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1255 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
1256 | } |
1257 | ||
31299944 | 1258 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
1259 | { |
1260 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1261 | SECONDARY_EXEC_RDTSCP; | |
1262 | } | |
1263 | ||
ad756a16 MJ |
1264 | static inline bool cpu_has_vmx_invpcid(void) |
1265 | { | |
1266 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1267 | SECONDARY_EXEC_ENABLE_INVPCID; | |
1268 | } | |
1269 | ||
31299944 | 1270 | static inline bool cpu_has_virtual_nmis(void) |
f08864b4 SY |
1271 | { |
1272 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
1273 | } | |
1274 | ||
f5f48ee1 SY |
1275 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
1276 | { | |
1277 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1278 | SECONDARY_EXEC_WBINVD_EXITING; | |
1279 | } | |
1280 | ||
abc4fc58 AG |
1281 | static inline bool cpu_has_vmx_shadow_vmcs(void) |
1282 | { | |
1283 | u64 vmx_msr; | |
1284 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
1285 | /* check if the cpu supports writing r/o exit information fields */ | |
1286 | if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) | |
1287 | return false; | |
1288 | ||
1289 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1290 | SECONDARY_EXEC_SHADOW_VMCS; | |
1291 | } | |
1292 | ||
843e4330 KH |
1293 | static inline bool cpu_has_vmx_pml(void) |
1294 | { | |
1295 | return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; | |
1296 | } | |
1297 | ||
64903d61 HZ |
1298 | static inline bool cpu_has_vmx_tsc_scaling(void) |
1299 | { | |
1300 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1301 | SECONDARY_EXEC_TSC_SCALING; | |
1302 | } | |
1303 | ||
04547156 SY |
1304 | static inline bool report_flexpriority(void) |
1305 | { | |
1306 | return flexpriority_enabled; | |
1307 | } | |
1308 | ||
fe3ef05c NHE |
1309 | static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) |
1310 | { | |
1311 | return vmcs12->cpu_based_vm_exec_control & bit; | |
1312 | } | |
1313 | ||
1314 | static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) | |
1315 | { | |
1316 | return (vmcs12->cpu_based_vm_exec_control & | |
1317 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && | |
1318 | (vmcs12->secondary_vm_exec_control & bit); | |
1319 | } | |
1320 | ||
f5c4368f | 1321 | static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12) |
644d711a NHE |
1322 | { |
1323 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS; | |
1324 | } | |
1325 | ||
f4124500 JK |
1326 | static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) |
1327 | { | |
1328 | return vmcs12->pin_based_vm_exec_control & | |
1329 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1330 | } | |
1331 | ||
155a97a3 NHE |
1332 | static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) |
1333 | { | |
1334 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); | |
1335 | } | |
1336 | ||
81dc01f7 WL |
1337 | static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) |
1338 | { | |
1339 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) && | |
1340 | vmx_xsaves_supported(); | |
1341 | } | |
1342 | ||
f2b93280 WV |
1343 | static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) |
1344 | { | |
1345 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); | |
1346 | } | |
1347 | ||
5c614b35 WL |
1348 | static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) |
1349 | { | |
1350 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); | |
1351 | } | |
1352 | ||
82f0dd4b WV |
1353 | static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) |
1354 | { | |
1355 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); | |
1356 | } | |
1357 | ||
608406e2 WV |
1358 | static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) |
1359 | { | |
1360 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
1361 | } | |
1362 | ||
705699a1 WV |
1363 | static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) |
1364 | { | |
1365 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; | |
1366 | } | |
1367 | ||
644d711a NHE |
1368 | static inline bool is_exception(u32 intr_info) |
1369 | { | |
1370 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1371 | == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK); | |
1372 | } | |
1373 | ||
533558bc JK |
1374 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
1375 | u32 exit_intr_info, | |
1376 | unsigned long exit_qualification); | |
7c177938 NHE |
1377 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, |
1378 | struct vmcs12 *vmcs12, | |
1379 | u32 reason, unsigned long qualification); | |
1380 | ||
8b9cf98c | 1381 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
1382 | { |
1383 | int i; | |
1384 | ||
a2fa3e9f | 1385 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 1386 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
1387 | return i; |
1388 | return -1; | |
1389 | } | |
1390 | ||
2384d2b3 SY |
1391 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
1392 | { | |
1393 | struct { | |
1394 | u64 vpid : 16; | |
1395 | u64 rsvd : 48; | |
1396 | u64 gva; | |
1397 | } operand = { vpid, 0, gva }; | |
1398 | ||
4ecac3fd | 1399 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
1400 | /* CF==1 or ZF==1 --> rc = -1 */ |
1401 | "; ja 1f ; ud2 ; 1:" | |
1402 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
1403 | } | |
1404 | ||
1439442c SY |
1405 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
1406 | { | |
1407 | struct { | |
1408 | u64 eptp, gpa; | |
1409 | } operand = {eptp, gpa}; | |
1410 | ||
4ecac3fd | 1411 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
1412 | /* CF==1 or ZF==1 --> rc = -1 */ |
1413 | "; ja 1f ; ud2 ; 1:\n" | |
1414 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
1415 | } | |
1416 | ||
26bb0981 | 1417 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
1418 | { |
1419 | int i; | |
1420 | ||
8b9cf98c | 1421 | i = __find_msr_index(vmx, msr); |
a75beee6 | 1422 | if (i >= 0) |
a2fa3e9f | 1423 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 1424 | return NULL; |
7725f0ba AK |
1425 | } |
1426 | ||
6aa8b732 AK |
1427 | static void vmcs_clear(struct vmcs *vmcs) |
1428 | { | |
1429 | u64 phys_addr = __pa(vmcs); | |
1430 | u8 error; | |
1431 | ||
4ecac3fd | 1432 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 1433 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
1434 | : "cc", "memory"); |
1435 | if (error) | |
1436 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
1437 | vmcs, phys_addr); | |
1438 | } | |
1439 | ||
d462b819 NHE |
1440 | static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
1441 | { | |
1442 | vmcs_clear(loaded_vmcs->vmcs); | |
355f4fb1 JM |
1443 | if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) |
1444 | vmcs_clear(loaded_vmcs->shadow_vmcs); | |
d462b819 NHE |
1445 | loaded_vmcs->cpu = -1; |
1446 | loaded_vmcs->launched = 0; | |
1447 | } | |
1448 | ||
7725b894 DX |
1449 | static void vmcs_load(struct vmcs *vmcs) |
1450 | { | |
1451 | u64 phys_addr = __pa(vmcs); | |
1452 | u8 error; | |
1453 | ||
1454 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
16d8f72f | 1455 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
1456 | : "cc", "memory"); |
1457 | if (error) | |
2844d849 | 1458 | printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n", |
7725b894 DX |
1459 | vmcs, phys_addr); |
1460 | } | |
1461 | ||
2965faa5 | 1462 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
1463 | /* |
1464 | * This bitmap is used to indicate whether the vmclear | |
1465 | * operation is enabled on all cpus. All disabled by | |
1466 | * default. | |
1467 | */ | |
1468 | static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; | |
1469 | ||
1470 | static inline void crash_enable_local_vmclear(int cpu) | |
1471 | { | |
1472 | cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1473 | } | |
1474 | ||
1475 | static inline void crash_disable_local_vmclear(int cpu) | |
1476 | { | |
1477 | cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1478 | } | |
1479 | ||
1480 | static inline int crash_local_vmclear_enabled(int cpu) | |
1481 | { | |
1482 | return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1483 | } | |
1484 | ||
1485 | static void crash_vmclear_local_loaded_vmcss(void) | |
1486 | { | |
1487 | int cpu = raw_smp_processor_id(); | |
1488 | struct loaded_vmcs *v; | |
1489 | ||
1490 | if (!crash_local_vmclear_enabled(cpu)) | |
1491 | return; | |
1492 | ||
1493 | list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), | |
1494 | loaded_vmcss_on_cpu_link) | |
1495 | vmcs_clear(v->vmcs); | |
1496 | } | |
1497 | #else | |
1498 | static inline void crash_enable_local_vmclear(int cpu) { } | |
1499 | static inline void crash_disable_local_vmclear(int cpu) { } | |
2965faa5 | 1500 | #endif /* CONFIG_KEXEC_CORE */ |
8f536b76 | 1501 | |
d462b819 | 1502 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 1503 | { |
d462b819 | 1504 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 1505 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 1506 | |
d462b819 NHE |
1507 | if (loaded_vmcs->cpu != cpu) |
1508 | return; /* vcpu migration can race with cpu offline */ | |
1509 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 1510 | per_cpu(current_vmcs, cpu) = NULL; |
8f536b76 | 1511 | crash_disable_local_vmclear(cpu); |
d462b819 | 1512 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
5a560f8b XG |
1513 | |
1514 | /* | |
1515 | * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link | |
1516 | * is before setting loaded_vmcs->vcpu to -1 which is done in | |
1517 | * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist | |
1518 | * then adds the vmcs into percpu list before it is deleted. | |
1519 | */ | |
1520 | smp_wmb(); | |
1521 | ||
d462b819 | 1522 | loaded_vmcs_init(loaded_vmcs); |
8f536b76 | 1523 | crash_enable_local_vmclear(cpu); |
6aa8b732 AK |
1524 | } |
1525 | ||
d462b819 | 1526 | static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 1527 | { |
e6c7d321 XG |
1528 | int cpu = loaded_vmcs->cpu; |
1529 | ||
1530 | if (cpu != -1) | |
1531 | smp_call_function_single(cpu, | |
1532 | __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
1533 | } |
1534 | ||
dd5f5341 | 1535 | static inline void vpid_sync_vcpu_single(int vpid) |
2384d2b3 | 1536 | { |
dd5f5341 | 1537 | if (vpid == 0) |
2384d2b3 SY |
1538 | return; |
1539 | ||
518c8aee | 1540 | if (cpu_has_vmx_invvpid_single()) |
dd5f5341 | 1541 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0); |
2384d2b3 SY |
1542 | } |
1543 | ||
b9d762fa GJ |
1544 | static inline void vpid_sync_vcpu_global(void) |
1545 | { | |
1546 | if (cpu_has_vmx_invvpid_global()) | |
1547 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
1548 | } | |
1549 | ||
dd5f5341 | 1550 | static inline void vpid_sync_context(int vpid) |
b9d762fa GJ |
1551 | { |
1552 | if (cpu_has_vmx_invvpid_single()) | |
dd5f5341 | 1553 | vpid_sync_vcpu_single(vpid); |
b9d762fa GJ |
1554 | else |
1555 | vpid_sync_vcpu_global(); | |
1556 | } | |
1557 | ||
1439442c SY |
1558 | static inline void ept_sync_global(void) |
1559 | { | |
1560 | if (cpu_has_vmx_invept_global()) | |
1561 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
1562 | } | |
1563 | ||
1564 | static inline void ept_sync_context(u64 eptp) | |
1565 | { | |
089d034e | 1566 | if (enable_ept) { |
1439442c SY |
1567 | if (cpu_has_vmx_invept_context()) |
1568 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
1569 | else | |
1570 | ept_sync_global(); | |
1571 | } | |
1572 | } | |
1573 | ||
8a86aea9 PB |
1574 | static __always_inline void vmcs_check16(unsigned long field) |
1575 | { | |
1576 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1577 | "16-bit accessor invalid for 64-bit field"); | |
1578 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1579 | "16-bit accessor invalid for 64-bit high field"); | |
1580 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1581 | "16-bit accessor invalid for 32-bit high field"); | |
1582 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1583 | "16-bit accessor invalid for natural width field"); | |
1584 | } | |
1585 | ||
1586 | static __always_inline void vmcs_check32(unsigned long field) | |
1587 | { | |
1588 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1589 | "32-bit accessor invalid for 16-bit field"); | |
1590 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1591 | "32-bit accessor invalid for natural width field"); | |
1592 | } | |
1593 | ||
1594 | static __always_inline void vmcs_check64(unsigned long field) | |
1595 | { | |
1596 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1597 | "64-bit accessor invalid for 16-bit field"); | |
1598 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1599 | "64-bit accessor invalid for 64-bit high field"); | |
1600 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1601 | "64-bit accessor invalid for 32-bit field"); | |
1602 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1603 | "64-bit accessor invalid for natural width field"); | |
1604 | } | |
1605 | ||
1606 | static __always_inline void vmcs_checkl(unsigned long field) | |
1607 | { | |
1608 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1609 | "Natural width accessor invalid for 16-bit field"); | |
1610 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1611 | "Natural width accessor invalid for 64-bit field"); | |
1612 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1613 | "Natural width accessor invalid for 64-bit high field"); | |
1614 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1615 | "Natural width accessor invalid for 32-bit field"); | |
1616 | } | |
1617 | ||
1618 | static __always_inline unsigned long __vmcs_readl(unsigned long field) | |
6aa8b732 | 1619 | { |
5e520e62 | 1620 | unsigned long value; |
6aa8b732 | 1621 | |
5e520e62 AK |
1622 | asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
1623 | : "=a"(value) : "d"(field) : "cc"); | |
6aa8b732 AK |
1624 | return value; |
1625 | } | |
1626 | ||
96304217 | 1627 | static __always_inline u16 vmcs_read16(unsigned long field) |
6aa8b732 | 1628 | { |
8a86aea9 PB |
1629 | vmcs_check16(field); |
1630 | return __vmcs_readl(field); | |
6aa8b732 AK |
1631 | } |
1632 | ||
96304217 | 1633 | static __always_inline u32 vmcs_read32(unsigned long field) |
6aa8b732 | 1634 | { |
8a86aea9 PB |
1635 | vmcs_check32(field); |
1636 | return __vmcs_readl(field); | |
6aa8b732 AK |
1637 | } |
1638 | ||
96304217 | 1639 | static __always_inline u64 vmcs_read64(unsigned long field) |
6aa8b732 | 1640 | { |
8a86aea9 | 1641 | vmcs_check64(field); |
05b3e0c2 | 1642 | #ifdef CONFIG_X86_64 |
8a86aea9 | 1643 | return __vmcs_readl(field); |
6aa8b732 | 1644 | #else |
8a86aea9 | 1645 | return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32); |
6aa8b732 AK |
1646 | #endif |
1647 | } | |
1648 | ||
8a86aea9 PB |
1649 | static __always_inline unsigned long vmcs_readl(unsigned long field) |
1650 | { | |
1651 | vmcs_checkl(field); | |
1652 | return __vmcs_readl(field); | |
1653 | } | |
1654 | ||
e52de1b8 AK |
1655 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
1656 | { | |
1657 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
1658 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1659 | dump_stack(); | |
1660 | } | |
1661 | ||
8a86aea9 | 1662 | static __always_inline void __vmcs_writel(unsigned long field, unsigned long value) |
6aa8b732 AK |
1663 | { |
1664 | u8 error; | |
1665 | ||
4ecac3fd | 1666 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 1667 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
1668 | if (unlikely(error)) |
1669 | vmwrite_error(field, value); | |
6aa8b732 AK |
1670 | } |
1671 | ||
8a86aea9 | 1672 | static __always_inline void vmcs_write16(unsigned long field, u16 value) |
6aa8b732 | 1673 | { |
8a86aea9 PB |
1674 | vmcs_check16(field); |
1675 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1676 | } |
1677 | ||
8a86aea9 | 1678 | static __always_inline void vmcs_write32(unsigned long field, u32 value) |
6aa8b732 | 1679 | { |
8a86aea9 PB |
1680 | vmcs_check32(field); |
1681 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1682 | } |
1683 | ||
8a86aea9 | 1684 | static __always_inline void vmcs_write64(unsigned long field, u64 value) |
6aa8b732 | 1685 | { |
8a86aea9 PB |
1686 | vmcs_check64(field); |
1687 | __vmcs_writel(field, value); | |
7682f2d0 | 1688 | #ifndef CONFIG_X86_64 |
6aa8b732 | 1689 | asm volatile (""); |
8a86aea9 | 1690 | __vmcs_writel(field+1, value >> 32); |
6aa8b732 AK |
1691 | #endif |
1692 | } | |
1693 | ||
8a86aea9 | 1694 | static __always_inline void vmcs_writel(unsigned long field, unsigned long value) |
2ab455cc | 1695 | { |
8a86aea9 PB |
1696 | vmcs_checkl(field); |
1697 | __vmcs_writel(field, value); | |
2ab455cc AL |
1698 | } |
1699 | ||
8a86aea9 | 1700 | static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask) |
2ab455cc | 1701 | { |
8a86aea9 PB |
1702 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1703 | "vmcs_clear_bits does not support 64-bit fields"); | |
1704 | __vmcs_writel(field, __vmcs_readl(field) & ~mask); | |
2ab455cc AL |
1705 | } |
1706 | ||
8a86aea9 | 1707 | static __always_inline void vmcs_set_bits(unsigned long field, u32 mask) |
2ab455cc | 1708 | { |
8a86aea9 PB |
1709 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1710 | "vmcs_set_bits does not support 64-bit fields"); | |
1711 | __vmcs_writel(field, __vmcs_readl(field) | mask); | |
2ab455cc AL |
1712 | } |
1713 | ||
8391ce44 PB |
1714 | static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx) |
1715 | { | |
1716 | vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS); | |
1717 | } | |
1718 | ||
2961e876 GN |
1719 | static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val) |
1720 | { | |
1721 | vmcs_write32(VM_ENTRY_CONTROLS, val); | |
1722 | vmx->vm_entry_controls_shadow = val; | |
1723 | } | |
1724 | ||
1725 | static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1726 | { | |
1727 | if (vmx->vm_entry_controls_shadow != val) | |
1728 | vm_entry_controls_init(vmx, val); | |
1729 | } | |
1730 | ||
1731 | static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx) | |
1732 | { | |
1733 | return vmx->vm_entry_controls_shadow; | |
1734 | } | |
1735 | ||
1736 | ||
1737 | static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1738 | { | |
1739 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val); | |
1740 | } | |
1741 | ||
1742 | static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1743 | { | |
1744 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val); | |
1745 | } | |
1746 | ||
8391ce44 PB |
1747 | static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx) |
1748 | { | |
1749 | vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS); | |
1750 | } | |
1751 | ||
2961e876 GN |
1752 | static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val) |
1753 | { | |
1754 | vmcs_write32(VM_EXIT_CONTROLS, val); | |
1755 | vmx->vm_exit_controls_shadow = val; | |
1756 | } | |
1757 | ||
1758 | static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1759 | { | |
1760 | if (vmx->vm_exit_controls_shadow != val) | |
1761 | vm_exit_controls_init(vmx, val); | |
1762 | } | |
1763 | ||
1764 | static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx) | |
1765 | { | |
1766 | return vmx->vm_exit_controls_shadow; | |
1767 | } | |
1768 | ||
1769 | ||
1770 | static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1771 | { | |
1772 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val); | |
1773 | } | |
1774 | ||
1775 | static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1776 | { | |
1777 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val); | |
1778 | } | |
1779 | ||
2fb92db1 AK |
1780 | static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
1781 | { | |
1782 | vmx->segment_cache.bitmask = 0; | |
1783 | } | |
1784 | ||
1785 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, | |
1786 | unsigned field) | |
1787 | { | |
1788 | bool ret; | |
1789 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
1790 | ||
1791 | if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { | |
1792 | vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); | |
1793 | vmx->segment_cache.bitmask = 0; | |
1794 | } | |
1795 | ret = vmx->segment_cache.bitmask & mask; | |
1796 | vmx->segment_cache.bitmask |= mask; | |
1797 | return ret; | |
1798 | } | |
1799 | ||
1800 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
1801 | { | |
1802 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
1803 | ||
1804 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
1805 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
1806 | return *p; | |
1807 | } | |
1808 | ||
1809 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
1810 | { | |
1811 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
1812 | ||
1813 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
1814 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
1815 | return *p; | |
1816 | } | |
1817 | ||
1818 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
1819 | { | |
1820 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
1821 | ||
1822 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
1823 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
1824 | return *p; | |
1825 | } | |
1826 | ||
1827 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
1828 | { | |
1829 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
1830 | ||
1831 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
1832 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
1833 | return *p; | |
1834 | } | |
1835 | ||
abd3f2d6 AK |
1836 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
1837 | { | |
1838 | u32 eb; | |
1839 | ||
fd7373cc | 1840 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
54a20552 | 1841 | (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR); |
fd7373cc JK |
1842 | if ((vcpu->guest_debug & |
1843 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
1844 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
1845 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 1846 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 1847 | eb = ~0; |
089d034e | 1848 | if (enable_ept) |
1439442c | 1849 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
02daab21 AK |
1850 | if (vcpu->fpu_active) |
1851 | eb &= ~(1u << NM_VECTOR); | |
36cf24e0 NHE |
1852 | |
1853 | /* When we are running a nested L2 guest and L1 specified for it a | |
1854 | * certain exception bitmap, we must trap the same exceptions and pass | |
1855 | * them to L1. When running L2, we will only handle the exceptions | |
1856 | * specified above if L1 did not want them. | |
1857 | */ | |
1858 | if (is_guest_mode(vcpu)) | |
1859 | eb |= get_vmcs12(vcpu)->exception_bitmap; | |
1860 | ||
abd3f2d6 AK |
1861 | vmcs_write32(EXCEPTION_BITMAP, eb); |
1862 | } | |
1863 | ||
2961e876 GN |
1864 | static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1865 | unsigned long entry, unsigned long exit) | |
8bf00a52 | 1866 | { |
2961e876 GN |
1867 | vm_entry_controls_clearbit(vmx, entry); |
1868 | vm_exit_controls_clearbit(vmx, exit); | |
8bf00a52 GN |
1869 | } |
1870 | ||
61d2ef2c AK |
1871 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
1872 | { | |
1873 | unsigned i; | |
1874 | struct msr_autoload *m = &vmx->msr_autoload; | |
1875 | ||
8bf00a52 GN |
1876 | switch (msr) { |
1877 | case MSR_EFER: | |
1878 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1879 | clear_atomic_switch_msr_special(vmx, |
1880 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1881 | VM_EXIT_LOAD_IA32_EFER); |
1882 | return; | |
1883 | } | |
1884 | break; | |
1885 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1886 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1887 | clear_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1888 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1889 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
1890 | return; | |
1891 | } | |
1892 | break; | |
110312c8 AK |
1893 | } |
1894 | ||
61d2ef2c AK |
1895 | for (i = 0; i < m->nr; ++i) |
1896 | if (m->guest[i].index == msr) | |
1897 | break; | |
1898 | ||
1899 | if (i == m->nr) | |
1900 | return; | |
1901 | --m->nr; | |
1902 | m->guest[i] = m->guest[m->nr]; | |
1903 | m->host[i] = m->host[m->nr]; | |
1904 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1905 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1906 | } | |
1907 | ||
2961e876 GN |
1908 | static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1909 | unsigned long entry, unsigned long exit, | |
1910 | unsigned long guest_val_vmcs, unsigned long host_val_vmcs, | |
1911 | u64 guest_val, u64 host_val) | |
8bf00a52 GN |
1912 | { |
1913 | vmcs_write64(guest_val_vmcs, guest_val); | |
1914 | vmcs_write64(host_val_vmcs, host_val); | |
2961e876 GN |
1915 | vm_entry_controls_setbit(vmx, entry); |
1916 | vm_exit_controls_setbit(vmx, exit); | |
8bf00a52 GN |
1917 | } |
1918 | ||
61d2ef2c AK |
1919 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
1920 | u64 guest_val, u64 host_val) | |
1921 | { | |
1922 | unsigned i; | |
1923 | struct msr_autoload *m = &vmx->msr_autoload; | |
1924 | ||
8bf00a52 GN |
1925 | switch (msr) { |
1926 | case MSR_EFER: | |
1927 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1928 | add_atomic_switch_msr_special(vmx, |
1929 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1930 | VM_EXIT_LOAD_IA32_EFER, |
1931 | GUEST_IA32_EFER, | |
1932 | HOST_IA32_EFER, | |
1933 | guest_val, host_val); | |
1934 | return; | |
1935 | } | |
1936 | break; | |
1937 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1938 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1939 | add_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1940 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1941 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, | |
1942 | GUEST_IA32_PERF_GLOBAL_CTRL, | |
1943 | HOST_IA32_PERF_GLOBAL_CTRL, | |
1944 | guest_val, host_val); | |
1945 | return; | |
1946 | } | |
1947 | break; | |
7099e2e1 RK |
1948 | case MSR_IA32_PEBS_ENABLE: |
1949 | /* PEBS needs a quiescent period after being disabled (to write | |
1950 | * a record). Disabling PEBS through VMX MSR swapping doesn't | |
1951 | * provide that period, so a CPU could write host's record into | |
1952 | * guest's memory. | |
1953 | */ | |
1954 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
110312c8 AK |
1955 | } |
1956 | ||
61d2ef2c AK |
1957 | for (i = 0; i < m->nr; ++i) |
1958 | if (m->guest[i].index == msr) | |
1959 | break; | |
1960 | ||
e7fc6f93 | 1961 | if (i == NR_AUTOLOAD_MSRS) { |
60266204 | 1962 | printk_once(KERN_WARNING "Not enough msr switch entries. " |
e7fc6f93 GN |
1963 | "Can't add msr %x\n", msr); |
1964 | return; | |
1965 | } else if (i == m->nr) { | |
61d2ef2c AK |
1966 | ++m->nr; |
1967 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1968 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1969 | } | |
1970 | ||
1971 | m->guest[i].index = msr; | |
1972 | m->guest[i].value = guest_val; | |
1973 | m->host[i].index = msr; | |
1974 | m->host[i].value = host_val; | |
1975 | } | |
1976 | ||
33ed6329 AK |
1977 | static void reload_tss(void) |
1978 | { | |
33ed6329 AK |
1979 | /* |
1980 | * VT restores TR but not its size. Useless. | |
1981 | */ | |
89cbc767 | 1982 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); |
a5f61300 | 1983 | struct desc_struct *descs; |
33ed6329 | 1984 | |
d359192f | 1985 | descs = (void *)gdt->address; |
33ed6329 AK |
1986 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ |
1987 | load_TR_desc(); | |
33ed6329 AK |
1988 | } |
1989 | ||
92c0d900 | 1990 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 1991 | { |
844a5fe2 PB |
1992 | u64 guest_efer = vmx->vcpu.arch.efer; |
1993 | u64 ignore_bits = 0; | |
1994 | ||
1995 | if (!enable_ept) { | |
1996 | /* | |
1997 | * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing | |
1998 | * host CPUID is more efficient than testing guest CPUID | |
1999 | * or CR4. Host SMEP is anyway a requirement for guest SMEP. | |
2000 | */ | |
2001 | if (boot_cpu_has(X86_FEATURE_SMEP)) | |
2002 | guest_efer |= EFER_NX; | |
2003 | else if (!(guest_efer & EFER_NX)) | |
2004 | ignore_bits |= EFER_NX; | |
2005 | } | |
3a34a881 | 2006 | |
51c6cf66 | 2007 | /* |
844a5fe2 | 2008 | * LMA and LME handled by hardware; SCE meaningless outside long mode. |
51c6cf66 | 2009 | */ |
844a5fe2 | 2010 | ignore_bits |= EFER_SCE; |
51c6cf66 AK |
2011 | #ifdef CONFIG_X86_64 |
2012 | ignore_bits |= EFER_LMA | EFER_LME; | |
2013 | /* SCE is meaningful only in long mode on Intel */ | |
2014 | if (guest_efer & EFER_LMA) | |
2015 | ignore_bits &= ~(u64)EFER_SCE; | |
2016 | #endif | |
84ad33ef AK |
2017 | |
2018 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
f6577a5f AL |
2019 | |
2020 | /* | |
2021 | * On EPT, we can't emulate NX, so we must switch EFER atomically. | |
2022 | * On CPUs that support "load IA32_EFER", always switch EFER | |
2023 | * atomically, since it's faster than switching it manually. | |
2024 | */ | |
2025 | if (cpu_has_load_ia32_efer || | |
2026 | (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { | |
84ad33ef AK |
2027 | if (!(guest_efer & EFER_LMA)) |
2028 | guest_efer &= ~EFER_LME; | |
54b98bff AL |
2029 | if (guest_efer != host_efer) |
2030 | add_atomic_switch_msr(vmx, MSR_EFER, | |
2031 | guest_efer, host_efer); | |
84ad33ef | 2032 | return false; |
844a5fe2 PB |
2033 | } else { |
2034 | guest_efer &= ~ignore_bits; | |
2035 | guest_efer |= host_efer & ignore_bits; | |
2036 | ||
2037 | vmx->guest_msrs[efer_offset].data = guest_efer; | |
2038 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; | |
84ad33ef | 2039 | |
844a5fe2 PB |
2040 | return true; |
2041 | } | |
51c6cf66 AK |
2042 | } |
2043 | ||
2d49ec72 GN |
2044 | static unsigned long segment_base(u16 selector) |
2045 | { | |
89cbc767 | 2046 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); |
2d49ec72 GN |
2047 | struct desc_struct *d; |
2048 | unsigned long table_base; | |
2049 | unsigned long v; | |
2050 | ||
2051 | if (!(selector & ~3)) | |
2052 | return 0; | |
2053 | ||
d359192f | 2054 | table_base = gdt->address; |
2d49ec72 GN |
2055 | |
2056 | if (selector & 4) { /* from ldt */ | |
2057 | u16 ldt_selector = kvm_read_ldt(); | |
2058 | ||
2059 | if (!(ldt_selector & ~3)) | |
2060 | return 0; | |
2061 | ||
2062 | table_base = segment_base(ldt_selector); | |
2063 | } | |
2064 | d = (struct desc_struct *)(table_base + (selector & ~7)); | |
2065 | v = get_desc_base(d); | |
2066 | #ifdef CONFIG_X86_64 | |
2067 | if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) | |
2068 | v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; | |
2069 | #endif | |
2070 | return v; | |
2071 | } | |
2072 | ||
2073 | static inline unsigned long kvm_read_tr_base(void) | |
2074 | { | |
2075 | u16 tr; | |
2076 | asm("str %0" : "=g"(tr)); | |
2077 | return segment_base(tr); | |
2078 | } | |
2079 | ||
04d2cc77 | 2080 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 2081 | { |
04d2cc77 | 2082 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 2083 | int i; |
04d2cc77 | 2084 | |
a2fa3e9f | 2085 | if (vmx->host_state.loaded) |
33ed6329 AK |
2086 | return; |
2087 | ||
a2fa3e9f | 2088 | vmx->host_state.loaded = 1; |
33ed6329 AK |
2089 | /* |
2090 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
2091 | * allow segment selectors with cpl > 0 or ti == 1. | |
2092 | */ | |
d6e88aec | 2093 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 2094 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 2095 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 2096 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 2097 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
2098 | vmx->host_state.fs_reload_needed = 0; |
2099 | } else { | |
33ed6329 | 2100 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 2101 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 2102 | } |
9581d442 | 2103 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
2104 | if (!(vmx->host_state.gs_sel & 7)) |
2105 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
2106 | else { |
2107 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 2108 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
2109 | } |
2110 | ||
b2da15ac AK |
2111 | #ifdef CONFIG_X86_64 |
2112 | savesegment(ds, vmx->host_state.ds_sel); | |
2113 | savesegment(es, vmx->host_state.es_sel); | |
2114 | #endif | |
2115 | ||
33ed6329 AK |
2116 | #ifdef CONFIG_X86_64 |
2117 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
2118 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
2119 | #else | |
a2fa3e9f GH |
2120 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
2121 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 2122 | #endif |
707c0874 AK |
2123 | |
2124 | #ifdef CONFIG_X86_64 | |
c8770e7b AK |
2125 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
2126 | if (is_long_mode(&vmx->vcpu)) | |
44ea2b17 | 2127 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
707c0874 | 2128 | #endif |
da8999d3 LJ |
2129 | if (boot_cpu_has(X86_FEATURE_MPX)) |
2130 | rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
26bb0981 AK |
2131 | for (i = 0; i < vmx->save_nmsrs; ++i) |
2132 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
2133 | vmx->guest_msrs[i].data, |
2134 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
2135 | } |
2136 | ||
a9b21b62 | 2137 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 2138 | { |
a2fa3e9f | 2139 | if (!vmx->host_state.loaded) |
33ed6329 AK |
2140 | return; |
2141 | ||
e1beb1d3 | 2142 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 2143 | vmx->host_state.loaded = 0; |
c8770e7b AK |
2144 | #ifdef CONFIG_X86_64 |
2145 | if (is_long_mode(&vmx->vcpu)) | |
2146 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
2147 | #endif | |
152d3f2f | 2148 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 2149 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 2150 | #ifdef CONFIG_X86_64 |
9581d442 | 2151 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
2152 | #else |
2153 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 2154 | #endif |
33ed6329 | 2155 | } |
0a77fe4c AK |
2156 | if (vmx->host_state.fs_reload_needed) |
2157 | loadsegment(fs, vmx->host_state.fs_sel); | |
b2da15ac AK |
2158 | #ifdef CONFIG_X86_64 |
2159 | if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) { | |
2160 | loadsegment(ds, vmx->host_state.ds_sel); | |
2161 | loadsegment(es, vmx->host_state.es_sel); | |
2162 | } | |
b2da15ac | 2163 | #endif |
152d3f2f | 2164 | reload_tss(); |
44ea2b17 | 2165 | #ifdef CONFIG_X86_64 |
c8770e7b | 2166 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 2167 | #endif |
da8999d3 LJ |
2168 | if (vmx->host_state.msr_host_bndcfgs) |
2169 | wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
b1a74bf8 SS |
2170 | /* |
2171 | * If the FPU is not active (through the host task or | |
2172 | * the guest vcpu), then restore the cr0.TS bit. | |
2173 | */ | |
3c6dffa9 | 2174 | if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded) |
b1a74bf8 | 2175 | stts(); |
89cbc767 | 2176 | load_gdt(this_cpu_ptr(&host_gdt)); |
33ed6329 AK |
2177 | } |
2178 | ||
a9b21b62 AK |
2179 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
2180 | { | |
2181 | preempt_disable(); | |
2182 | __vmx_load_host_state(vmx); | |
2183 | preempt_enable(); | |
2184 | } | |
2185 | ||
28b835d6 FW |
2186 | static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) |
2187 | { | |
2188 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2189 | struct pi_desc old, new; | |
2190 | unsigned int dest; | |
2191 | ||
2192 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
2193 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
2194 | !kvm_vcpu_apicv_active(vcpu)) | |
28b835d6 FW |
2195 | return; |
2196 | ||
2197 | do { | |
2198 | old.control = new.control = pi_desc->control; | |
2199 | ||
2200 | /* | |
2201 | * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there | |
2202 | * are two possible cases: | |
2203 | * 1. After running 'pre_block', context switch | |
2204 | * happened. For this case, 'sn' was set in | |
2205 | * vmx_vcpu_put(), so we need to clear it here. | |
2206 | * 2. After running 'pre_block', we were blocked, | |
2207 | * and woken up by some other guy. For this case, | |
2208 | * we don't need to do anything, 'pi_post_block' | |
2209 | * will do everything for us. However, we cannot | |
2210 | * check whether it is case #1 or case #2 here | |
2211 | * (maybe, not needed), so we also clear sn here, | |
2212 | * I think it is not a big deal. | |
2213 | */ | |
2214 | if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) { | |
2215 | if (vcpu->cpu != cpu) { | |
2216 | dest = cpu_physical_id(cpu); | |
2217 | ||
2218 | if (x2apic_enabled()) | |
2219 | new.ndst = dest; | |
2220 | else | |
2221 | new.ndst = (dest << 8) & 0xFF00; | |
2222 | } | |
2223 | ||
2224 | /* set 'NV' to 'notification vector' */ | |
2225 | new.nv = POSTED_INTR_VECTOR; | |
2226 | } | |
2227 | ||
2228 | /* Allow posting non-urgent interrupts */ | |
2229 | new.sn = 0; | |
2230 | } while (cmpxchg(&pi_desc->control, old.control, | |
2231 | new.control) != old.control); | |
2232 | } | |
1be0e61c | 2233 | |
c95ba92a PF |
2234 | static void decache_tsc_multiplier(struct vcpu_vmx *vmx) |
2235 | { | |
2236 | vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio; | |
2237 | vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); | |
2238 | } | |
2239 | ||
6aa8b732 AK |
2240 | /* |
2241 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
2242 | * vcpu mutex is already taken. | |
2243 | */ | |
15ad7146 | 2244 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 2245 | { |
a2fa3e9f | 2246 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4610c9cc | 2247 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); |
b80c76ec | 2248 | bool already_loaded = vmx->loaded_vmcs->cpu == cpu; |
6aa8b732 | 2249 | |
4610c9cc DX |
2250 | if (!vmm_exclusive) |
2251 | kvm_cpu_vmxon(phys_addr); | |
b80c76ec | 2252 | else if (!already_loaded) |
d462b819 | 2253 | loaded_vmcs_clear(vmx->loaded_vmcs); |
6aa8b732 | 2254 | |
b80c76ec | 2255 | if (!already_loaded) { |
92fe13be | 2256 | local_irq_disable(); |
8f536b76 | 2257 | crash_disable_local_vmclear(cpu); |
5a560f8b XG |
2258 | |
2259 | /* | |
2260 | * Read loaded_vmcs->cpu should be before fetching | |
2261 | * loaded_vmcs->loaded_vmcss_on_cpu_link. | |
2262 | * See the comments in __loaded_vmcs_clear(). | |
2263 | */ | |
2264 | smp_rmb(); | |
2265 | ||
d462b819 NHE |
2266 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
2267 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
8f536b76 | 2268 | crash_enable_local_vmclear(cpu); |
92fe13be | 2269 | local_irq_enable(); |
b80c76ec JM |
2270 | } |
2271 | ||
2272 | if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { | |
2273 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; | |
2274 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
2275 | } | |
2276 | ||
2277 | if (!already_loaded) { | |
2278 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); | |
2279 | unsigned long sysenter_esp; | |
2280 | ||
2281 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
92fe13be | 2282 | |
6aa8b732 AK |
2283 | /* |
2284 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
2285 | * processors. | |
2286 | */ | |
d6e88aec | 2287 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
d359192f | 2288 | vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */ |
6aa8b732 AK |
2289 | |
2290 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
2291 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
ff2c3a18 | 2292 | |
d462b819 | 2293 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 2294 | } |
28b835d6 | 2295 | |
2680d6da OH |
2296 | /* Setup TSC multiplier */ |
2297 | if (kvm_has_tsc_control && | |
c95ba92a PF |
2298 | vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) |
2299 | decache_tsc_multiplier(vmx); | |
2680d6da | 2300 | |
28b835d6 | 2301 | vmx_vcpu_pi_load(vcpu, cpu); |
1be0e61c | 2302 | vmx->host_pkru = read_pkru(); |
28b835d6 FW |
2303 | } |
2304 | ||
2305 | static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) | |
2306 | { | |
2307 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2308 | ||
2309 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
2310 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
2311 | !kvm_vcpu_apicv_active(vcpu)) | |
28b835d6 FW |
2312 | return; |
2313 | ||
2314 | /* Set SN when the vCPU is preempted */ | |
2315 | if (vcpu->preempted) | |
2316 | pi_set_sn(pi_desc); | |
6aa8b732 AK |
2317 | } |
2318 | ||
2319 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
2320 | { | |
28b835d6 FW |
2321 | vmx_vcpu_pi_put(vcpu); |
2322 | ||
a9b21b62 | 2323 | __vmx_load_host_state(to_vmx(vcpu)); |
4610c9cc | 2324 | if (!vmm_exclusive) { |
d462b819 NHE |
2325 | __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs); |
2326 | vcpu->cpu = -1; | |
4610c9cc DX |
2327 | kvm_cpu_vmxoff(); |
2328 | } | |
6aa8b732 AK |
2329 | } |
2330 | ||
5fd86fcf AK |
2331 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
2332 | { | |
81231c69 AK |
2333 | ulong cr0; |
2334 | ||
5fd86fcf AK |
2335 | if (vcpu->fpu_active) |
2336 | return; | |
2337 | vcpu->fpu_active = 1; | |
81231c69 AK |
2338 | cr0 = vmcs_readl(GUEST_CR0); |
2339 | cr0 &= ~(X86_CR0_TS | X86_CR0_MP); | |
2340 | cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP); | |
2341 | vmcs_writel(GUEST_CR0, cr0); | |
5fd86fcf | 2342 | update_exception_bitmap(vcpu); |
edcafe3c | 2343 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
36cf24e0 NHE |
2344 | if (is_guest_mode(vcpu)) |
2345 | vcpu->arch.cr0_guest_owned_bits &= | |
2346 | ~get_vmcs12(vcpu)->cr0_guest_host_mask; | |
edcafe3c | 2347 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); |
5fd86fcf AK |
2348 | } |
2349 | ||
edcafe3c AK |
2350 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
2351 | ||
fe3ef05c NHE |
2352 | /* |
2353 | * Return the cr0 value that a nested guest would read. This is a combination | |
2354 | * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by | |
2355 | * its hypervisor (cr0_read_shadow). | |
2356 | */ | |
2357 | static inline unsigned long nested_read_cr0(struct vmcs12 *fields) | |
2358 | { | |
2359 | return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | | |
2360 | (fields->cr0_read_shadow & fields->cr0_guest_host_mask); | |
2361 | } | |
2362 | static inline unsigned long nested_read_cr4(struct vmcs12 *fields) | |
2363 | { | |
2364 | return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | | |
2365 | (fields->cr4_read_shadow & fields->cr4_guest_host_mask); | |
2366 | } | |
2367 | ||
5fd86fcf AK |
2368 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) |
2369 | { | |
36cf24e0 NHE |
2370 | /* Note that there is no vcpu->fpu_active = 0 here. The caller must |
2371 | * set this *before* calling this function. | |
2372 | */ | |
edcafe3c | 2373 | vmx_decache_cr0_guest_bits(vcpu); |
81231c69 | 2374 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP); |
5fd86fcf | 2375 | update_exception_bitmap(vcpu); |
edcafe3c AK |
2376 | vcpu->arch.cr0_guest_owned_bits = 0; |
2377 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
36cf24e0 NHE |
2378 | if (is_guest_mode(vcpu)) { |
2379 | /* | |
2380 | * L1's specified read shadow might not contain the TS bit, | |
2381 | * so now that we turned on shadowing of this bit, we need to | |
2382 | * set this bit of the shadow. Like in nested_vmx_run we need | |
2383 | * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet | |
2384 | * up-to-date here because we just decached cr0.TS (and we'll | |
2385 | * only update vmcs12->guest_cr0 on nested exit). | |
2386 | */ | |
2387 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2388 | vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) | | |
2389 | (vcpu->arch.cr0 & X86_CR0_TS); | |
2390 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
2391 | } else | |
2392 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf AK |
2393 | } |
2394 | ||
6aa8b732 AK |
2395 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
2396 | { | |
78ac8b47 | 2397 | unsigned long rflags, save_rflags; |
345dcaa8 | 2398 | |
6de12732 AK |
2399 | if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
2400 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); | |
2401 | rflags = vmcs_readl(GUEST_RFLAGS); | |
2402 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
2403 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2404 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
2405 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2406 | } | |
2407 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 | 2408 | } |
6de12732 | 2409 | return to_vmx(vcpu)->rflags; |
6aa8b732 AK |
2410 | } |
2411 | ||
2412 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
2413 | { | |
6de12732 AK |
2414 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
2415 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 AK |
2416 | if (to_vmx(vcpu)->rmode.vm86_active) { |
2417 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 2418 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 2419 | } |
6aa8b732 AK |
2420 | vmcs_writel(GUEST_RFLAGS, rflags); |
2421 | } | |
2422 | ||
be94f6b7 HH |
2423 | static u32 vmx_get_pkru(struct kvm_vcpu *vcpu) |
2424 | { | |
2425 | return to_vmx(vcpu)->guest_pkru; | |
2426 | } | |
2427 | ||
37ccdcbe | 2428 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
2429 | { |
2430 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2431 | int ret = 0; | |
2432 | ||
2433 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 2434 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 2435 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 2436 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 | 2437 | |
37ccdcbe | 2438 | return ret; |
2809f5d2 GC |
2439 | } |
2440 | ||
2441 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
2442 | { | |
2443 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2444 | u32 interruptibility = interruptibility_old; | |
2445 | ||
2446 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
2447 | ||
48005f64 | 2448 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 2449 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 2450 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
2451 | interruptibility |= GUEST_INTR_STATE_STI; |
2452 | ||
2453 | if ((interruptibility != interruptibility_old)) | |
2454 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
2455 | } | |
2456 | ||
6aa8b732 AK |
2457 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
2458 | { | |
2459 | unsigned long rip; | |
6aa8b732 | 2460 | |
5fdbf976 | 2461 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 2462 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 2463 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 2464 | |
2809f5d2 GC |
2465 | /* skipping an emulated instruction also counts */ |
2466 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
2467 | } |
2468 | ||
0b6ac343 NHE |
2469 | /* |
2470 | * KVM wants to inject page-faults which it got to the guest. This function | |
2471 | * checks whether in a nested guest, we need to inject them to L1 or L2. | |
0b6ac343 | 2472 | */ |
e011c663 | 2473 | static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr) |
0b6ac343 NHE |
2474 | { |
2475 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2476 | ||
e011c663 | 2477 | if (!(vmcs12->exception_bitmap & (1u << nr))) |
0b6ac343 NHE |
2478 | return 0; |
2479 | ||
533558bc JK |
2480 | nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason, |
2481 | vmcs_read32(VM_EXIT_INTR_INFO), | |
2482 | vmcs_readl(EXIT_QUALIFICATION)); | |
0b6ac343 NHE |
2483 | return 1; |
2484 | } | |
2485 | ||
298101da | 2486 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
2487 | bool has_error_code, u32 error_code, |
2488 | bool reinject) | |
298101da | 2489 | { |
77ab6db0 | 2490 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8ab2d2e2 | 2491 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 2492 | |
e011c663 GN |
2493 | if (!reinject && is_guest_mode(vcpu) && |
2494 | nested_vmx_check_exception(vcpu, nr)) | |
0b6ac343 NHE |
2495 | return; |
2496 | ||
8ab2d2e2 | 2497 | if (has_error_code) { |
77ab6db0 | 2498 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
2499 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
2500 | } | |
77ab6db0 | 2501 | |
7ffd92c5 | 2502 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
2503 | int inc_eip = 0; |
2504 | if (kvm_exception_is_soft(nr)) | |
2505 | inc_eip = vcpu->arch.event_exit_inst_len; | |
2506 | if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) | |
a92601bb | 2507 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
77ab6db0 JK |
2508 | return; |
2509 | } | |
2510 | ||
66fd3f7f GN |
2511 | if (kvm_exception_is_soft(nr)) { |
2512 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2513 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
2514 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
2515 | } else | |
2516 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2517 | ||
2518 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
298101da AK |
2519 | } |
2520 | ||
4e47c7a6 SY |
2521 | static bool vmx_rdtscp_supported(void) |
2522 | { | |
2523 | return cpu_has_vmx_rdtscp(); | |
2524 | } | |
2525 | ||
ad756a16 MJ |
2526 | static bool vmx_invpcid_supported(void) |
2527 | { | |
2528 | return cpu_has_vmx_invpcid() && enable_ept; | |
2529 | } | |
2530 | ||
a75beee6 ED |
2531 | /* |
2532 | * Swap MSR entry in host/guest MSR entry array. | |
2533 | */ | |
8b9cf98c | 2534 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 2535 | { |
26bb0981 | 2536 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
2537 | |
2538 | tmp = vmx->guest_msrs[to]; | |
2539 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
2540 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
2541 | } |
2542 | ||
8d14695f YZ |
2543 | static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu) |
2544 | { | |
2545 | unsigned long *msr_bitmap; | |
2546 | ||
670125bd | 2547 | if (is_guest_mode(vcpu)) |
d048c098 | 2548 | msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap; |
3ce424e4 RK |
2549 | else if (cpu_has_secondary_exec_ctrls() && |
2550 | (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) & | |
2551 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { | |
f6e90f9e WL |
2552 | if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) { |
2553 | if (is_long_mode(vcpu)) | |
c63e4563 | 2554 | msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv; |
f6e90f9e | 2555 | else |
c63e4563 | 2556 | msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv; |
f6e90f9e WL |
2557 | } else { |
2558 | if (is_long_mode(vcpu)) | |
c63e4563 | 2559 | msr_bitmap = vmx_msr_bitmap_longmode_x2apic; |
f6e90f9e | 2560 | else |
c63e4563 | 2561 | msr_bitmap = vmx_msr_bitmap_legacy_x2apic; |
f6e90f9e | 2562 | } |
8d14695f YZ |
2563 | } else { |
2564 | if (is_long_mode(vcpu)) | |
2565 | msr_bitmap = vmx_msr_bitmap_longmode; | |
2566 | else | |
2567 | msr_bitmap = vmx_msr_bitmap_legacy; | |
2568 | } | |
2569 | ||
2570 | vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); | |
2571 | } | |
2572 | ||
e38aea3e AK |
2573 | /* |
2574 | * Set up the vmcs to automatically save and restore system | |
2575 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
2576 | * mode, as fiddling with msrs is very expensive. | |
2577 | */ | |
8b9cf98c | 2578 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 2579 | { |
26bb0981 | 2580 | int save_nmsrs, index; |
e38aea3e | 2581 | |
a75beee6 ED |
2582 | save_nmsrs = 0; |
2583 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 2584 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 2585 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 2586 | if (index >= 0) |
8b9cf98c RR |
2587 | move_msr_up(vmx, index, save_nmsrs++); |
2588 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 2589 | if (index >= 0) |
8b9cf98c RR |
2590 | move_msr_up(vmx, index, save_nmsrs++); |
2591 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 2592 | if (index >= 0) |
8b9cf98c | 2593 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 | 2594 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
1cea0ce6 | 2595 | if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu)) |
4e47c7a6 | 2596 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 | 2597 | /* |
8c06585d | 2598 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
2599 | * if efer.sce is enabled. |
2600 | */ | |
8c06585d | 2601 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 2602 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 2603 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
2604 | } |
2605 | #endif | |
92c0d900 AK |
2606 | index = __find_msr_index(vmx, MSR_EFER); |
2607 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 2608 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 2609 | |
26bb0981 | 2610 | vmx->save_nmsrs = save_nmsrs; |
5897297b | 2611 | |
8d14695f YZ |
2612 | if (cpu_has_vmx_msr_bitmap()) |
2613 | vmx_set_msr_bitmap(&vmx->vcpu); | |
e38aea3e AK |
2614 | } |
2615 | ||
6aa8b732 AK |
2616 | /* |
2617 | * reads and returns guest's timestamp counter "register" | |
be7b263e HZ |
2618 | * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset |
2619 | * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3 | |
6aa8b732 | 2620 | */ |
be7b263e | 2621 | static u64 guest_read_tsc(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
2622 | { |
2623 | u64 host_tsc, tsc_offset; | |
2624 | ||
4ea1636b | 2625 | host_tsc = rdtsc(); |
6aa8b732 | 2626 | tsc_offset = vmcs_read64(TSC_OFFSET); |
be7b263e | 2627 | return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset; |
6aa8b732 AK |
2628 | } |
2629 | ||
2630 | /* | |
99e3e30a | 2631 | * writes 'offset' into guest's timestamp counter offset register |
6aa8b732 | 2632 | */ |
99e3e30a | 2633 | static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 2634 | { |
27fc51b2 | 2635 | if (is_guest_mode(vcpu)) { |
7991825b | 2636 | /* |
27fc51b2 NHE |
2637 | * We're here if L1 chose not to trap WRMSR to TSC. According |
2638 | * to the spec, this should set L1's TSC; The offset that L1 | |
2639 | * set for L2 remains unchanged, and still needs to be added | |
2640 | * to the newly set TSC to get L2's TSC. | |
7991825b | 2641 | */ |
27fc51b2 | 2642 | struct vmcs12 *vmcs12; |
27fc51b2 NHE |
2643 | /* recalculate vmcs02.TSC_OFFSET: */ |
2644 | vmcs12 = get_vmcs12(vcpu); | |
2645 | vmcs_write64(TSC_OFFSET, offset + | |
2646 | (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ? | |
2647 | vmcs12->tsc_offset : 0)); | |
2648 | } else { | |
489223ed YY |
2649 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2650 | vmcs_read64(TSC_OFFSET), offset); | |
27fc51b2 NHE |
2651 | vmcs_write64(TSC_OFFSET, offset); |
2652 | } | |
6aa8b732 AK |
2653 | } |
2654 | ||
801d3424 NHE |
2655 | static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu) |
2656 | { | |
2657 | struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
2658 | return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31))); | |
2659 | } | |
2660 | ||
2661 | /* | |
2662 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
2663 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
2664 | * all guests if the "nested" module option is off, and can also be disabled | |
2665 | * for a single guest by disabling its VMX cpuid bit. | |
2666 | */ | |
2667 | static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) | |
2668 | { | |
2669 | return nested && guest_cpuid_has_vmx(vcpu); | |
2670 | } | |
2671 | ||
b87a51ae NHE |
2672 | /* |
2673 | * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be | |
2674 | * returned for the various VMX controls MSRs when nested VMX is enabled. | |
2675 | * The same values should also be used to verify that vmcs12 control fields are | |
2676 | * valid during nested entry from L1 to L2. | |
2677 | * Each of these control msrs has a low and high 32-bit half: A low bit is on | |
2678 | * if the corresponding bit in the (32-bit) control field *must* be on, and a | |
2679 | * bit in the high half is on if the corresponding bit in the control field | |
2680 | * may be on. See also vmx_control_verify(). | |
b87a51ae | 2681 | */ |
b9c237bb | 2682 | static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx) |
b87a51ae NHE |
2683 | { |
2684 | /* | |
2685 | * Note that as a general rule, the high half of the MSRs (bits in | |
2686 | * the control fields which may be 1) should be initialized by the | |
2687 | * intersection of the underlying hardware's MSR (i.e., features which | |
2688 | * can be supported) and the list of features we want to expose - | |
2689 | * because they are known to be properly supported in our code. | |
2690 | * Also, usually, the low half of the MSRs (bits which must be 1) can | |
2691 | * be set to 0, meaning that L1 may turn off any of these bits. The | |
2692 | * reason is that if one of these bits is necessary, it will appear | |
2693 | * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control | |
2694 | * fields of vmcs01 and vmcs02, will turn these bits off - and | |
2695 | * nested_vmx_exit_handled() will not pass related exits to L1. | |
2696 | * These rules have exceptions below. | |
2697 | */ | |
2698 | ||
2699 | /* pin-based controls */ | |
eabeaacc | 2700 | rdmsr(MSR_IA32_VMX_PINBASED_CTLS, |
b9c237bb WV |
2701 | vmx->nested.nested_vmx_pinbased_ctls_low, |
2702 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
2703 | vmx->nested.nested_vmx_pinbased_ctls_low |= | |
2704 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2705 | vmx->nested.nested_vmx_pinbased_ctls_high &= | |
2706 | PIN_BASED_EXT_INTR_MASK | | |
2707 | PIN_BASED_NMI_EXITING | | |
2708 | PIN_BASED_VIRTUAL_NMIS; | |
2709 | vmx->nested.nested_vmx_pinbased_ctls_high |= | |
2710 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
0238ea91 | 2711 | PIN_BASED_VMX_PREEMPTION_TIMER; |
d62caabb | 2712 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) |
705699a1 WV |
2713 | vmx->nested.nested_vmx_pinbased_ctls_high |= |
2714 | PIN_BASED_POSTED_INTR; | |
b87a51ae | 2715 | |
3dbcd8da | 2716 | /* exit controls */ |
c0dfee58 | 2717 | rdmsr(MSR_IA32_VMX_EXIT_CTLS, |
b9c237bb WV |
2718 | vmx->nested.nested_vmx_exit_ctls_low, |
2719 | vmx->nested.nested_vmx_exit_ctls_high); | |
2720 | vmx->nested.nested_vmx_exit_ctls_low = | |
2721 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
e0ba1a6f | 2722 | |
b9c237bb | 2723 | vmx->nested.nested_vmx_exit_ctls_high &= |
b87a51ae | 2724 | #ifdef CONFIG_X86_64 |
c0dfee58 | 2725 | VM_EXIT_HOST_ADDR_SPACE_SIZE | |
b87a51ae | 2726 | #endif |
f4124500 | 2727 | VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT; |
b9c237bb WV |
2728 | vmx->nested.nested_vmx_exit_ctls_high |= |
2729 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | | |
f4124500 | 2730 | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | |
e0ba1a6f BD |
2731 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; |
2732 | ||
a87036ad | 2733 | if (kvm_mpx_supported()) |
b9c237bb | 2734 | vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; |
b87a51ae | 2735 | |
2996fca0 | 2736 | /* We support free control of debug control saving. */ |
b9c237bb WV |
2737 | vmx->nested.nested_vmx_true_exit_ctls_low = |
2738 | vmx->nested.nested_vmx_exit_ctls_low & | |
2996fca0 JK |
2739 | ~VM_EXIT_SAVE_DEBUG_CONTROLS; |
2740 | ||
b87a51ae NHE |
2741 | /* entry controls */ |
2742 | rdmsr(MSR_IA32_VMX_ENTRY_CTLS, | |
b9c237bb WV |
2743 | vmx->nested.nested_vmx_entry_ctls_low, |
2744 | vmx->nested.nested_vmx_entry_ctls_high); | |
2745 | vmx->nested.nested_vmx_entry_ctls_low = | |
2746 | VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
2747 | vmx->nested.nested_vmx_entry_ctls_high &= | |
57435349 JK |
2748 | #ifdef CONFIG_X86_64 |
2749 | VM_ENTRY_IA32E_MODE | | |
2750 | #endif | |
2751 | VM_ENTRY_LOAD_IA32_PAT; | |
b9c237bb WV |
2752 | vmx->nested.nested_vmx_entry_ctls_high |= |
2753 | (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER); | |
a87036ad | 2754 | if (kvm_mpx_supported()) |
b9c237bb | 2755 | vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; |
57435349 | 2756 | |
2996fca0 | 2757 | /* We support free control of debug control loading. */ |
b9c237bb WV |
2758 | vmx->nested.nested_vmx_true_entry_ctls_low = |
2759 | vmx->nested.nested_vmx_entry_ctls_low & | |
2996fca0 JK |
2760 | ~VM_ENTRY_LOAD_DEBUG_CONTROLS; |
2761 | ||
b87a51ae NHE |
2762 | /* cpu-based controls */ |
2763 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, | |
b9c237bb WV |
2764 | vmx->nested.nested_vmx_procbased_ctls_low, |
2765 | vmx->nested.nested_vmx_procbased_ctls_high); | |
2766 | vmx->nested.nested_vmx_procbased_ctls_low = | |
2767 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2768 | vmx->nested.nested_vmx_procbased_ctls_high &= | |
a294c9bb JK |
2769 | CPU_BASED_VIRTUAL_INTR_PENDING | |
2770 | CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING | | |
b87a51ae NHE |
2771 | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | |
2772 | CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | | |
2773 | CPU_BASED_CR3_STORE_EXITING | | |
2774 | #ifdef CONFIG_X86_64 | |
2775 | CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | | |
2776 | #endif | |
2777 | CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | | |
5f3d45e7 MD |
2778 | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG | |
2779 | CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING | | |
2780 | CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING | | |
2781 | CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
b87a51ae NHE |
2782 | /* |
2783 | * We can allow some features even when not supported by the | |
2784 | * hardware. For example, L1 can specify an MSR bitmap - and we | |
2785 | * can use it to avoid exits to L1 - even when L0 runs L2 | |
2786 | * without MSR bitmaps. | |
2787 | */ | |
b9c237bb WV |
2788 | vmx->nested.nested_vmx_procbased_ctls_high |= |
2789 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
560b7ee1 | 2790 | CPU_BASED_USE_MSR_BITMAPS; |
b87a51ae | 2791 | |
3dcdf3ec | 2792 | /* We support free control of CR3 access interception. */ |
b9c237bb WV |
2793 | vmx->nested.nested_vmx_true_procbased_ctls_low = |
2794 | vmx->nested.nested_vmx_procbased_ctls_low & | |
3dcdf3ec JK |
2795 | ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); |
2796 | ||
b87a51ae NHE |
2797 | /* secondary cpu-based controls */ |
2798 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, | |
b9c237bb WV |
2799 | vmx->nested.nested_vmx_secondary_ctls_low, |
2800 | vmx->nested.nested_vmx_secondary_ctls_high); | |
2801 | vmx->nested.nested_vmx_secondary_ctls_low = 0; | |
2802 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
d6851fbe | 2803 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
b3a2a907 | 2804 | SECONDARY_EXEC_RDTSCP | |
1b07304c | 2805 | SECONDARY_EXEC_DESC | |
f2b93280 | 2806 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
5c614b35 | 2807 | SECONDARY_EXEC_ENABLE_VPID | |
82f0dd4b | 2808 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
608406e2 | 2809 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
81dc01f7 | 2810 | SECONDARY_EXEC_WBINVD_EXITING | |
dfa169bb | 2811 | SECONDARY_EXEC_XSAVES; |
c18911a2 | 2812 | |
afa61f75 NHE |
2813 | if (enable_ept) { |
2814 | /* nested EPT: emulate EPT also to L1 */ | |
b9c237bb | 2815 | vmx->nested.nested_vmx_secondary_ctls_high |= |
0790ec17 | 2816 | SECONDARY_EXEC_ENABLE_EPT; |
b9c237bb | 2817 | vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT | |
d3134dbf JK |
2818 | VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT | |
2819 | VMX_EPT_INVEPT_BIT; | |
02120c45 BD |
2820 | if (cpu_has_vmx_ept_execute_only()) |
2821 | vmx->nested.nested_vmx_ept_caps |= | |
2822 | VMX_EPT_EXECUTE_ONLY_BIT; | |
b9c237bb | 2823 | vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept; |
45e11817 BD |
2824 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT | |
2825 | VMX_EPT_EXTENT_CONTEXT_BIT; | |
afa61f75 | 2826 | } else |
b9c237bb | 2827 | vmx->nested.nested_vmx_ept_caps = 0; |
afa61f75 | 2828 | |
ef697a71 PB |
2829 | /* |
2830 | * Old versions of KVM use the single-context version without | |
2831 | * checking for support, so declare that it is supported even | |
2832 | * though it is treated as global context. The alternative is | |
2833 | * not failing the single-context invvpid, and it is worse. | |
2834 | */ | |
089d7b6e WL |
2835 | if (enable_vpid) |
2836 | vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT | | |
ef697a71 | 2837 | VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | |
089d7b6e WL |
2838 | VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; |
2839 | else | |
2840 | vmx->nested.nested_vmx_vpid_caps = 0; | |
99b83ac8 | 2841 | |
0790ec17 RK |
2842 | if (enable_unrestricted_guest) |
2843 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2844 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
2845 | ||
c18911a2 | 2846 | /* miscellaneous data */ |
b9c237bb WV |
2847 | rdmsr(MSR_IA32_VMX_MISC, |
2848 | vmx->nested.nested_vmx_misc_low, | |
2849 | vmx->nested.nested_vmx_misc_high); | |
2850 | vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA; | |
2851 | vmx->nested.nested_vmx_misc_low |= | |
2852 | VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | | |
f4124500 | 2853 | VMX_MISC_ACTIVITY_HLT; |
b9c237bb | 2854 | vmx->nested.nested_vmx_misc_high = 0; |
b87a51ae NHE |
2855 | } |
2856 | ||
2857 | static inline bool vmx_control_verify(u32 control, u32 low, u32 high) | |
2858 | { | |
2859 | /* | |
2860 | * Bits 0 in high must be 0, and bits 1 in low must be 1. | |
2861 | */ | |
2862 | return ((control & high) | low) == control; | |
2863 | } | |
2864 | ||
2865 | static inline u64 vmx_control_msr(u32 low, u32 high) | |
2866 | { | |
2867 | return low | ((u64)high << 32); | |
2868 | } | |
2869 | ||
cae50139 | 2870 | /* Returns 0 on success, non-0 otherwise. */ |
b87a51ae NHE |
2871 | static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) |
2872 | { | |
b9c237bb WV |
2873 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2874 | ||
b87a51ae | 2875 | switch (msr_index) { |
b87a51ae NHE |
2876 | case MSR_IA32_VMX_BASIC: |
2877 | /* | |
2878 | * This MSR reports some information about VMX support. We | |
2879 | * should return information about the VMX we emulate for the | |
2880 | * guest, and the VMCS structure we give it - not about the | |
2881 | * VMX support of the underlying hardware. | |
2882 | */ | |
3dbcd8da | 2883 | *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS | |
b87a51ae NHE |
2884 | ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | |
2885 | (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); | |
9ac7e3e8 JD |
2886 | if (cpu_has_vmx_basic_inout()) |
2887 | *pdata |= VMX_BASIC_INOUT; | |
b87a51ae NHE |
2888 | break; |
2889 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
2890 | case MSR_IA32_VMX_PINBASED_CTLS: | |
b9c237bb WV |
2891 | *pdata = vmx_control_msr( |
2892 | vmx->nested.nested_vmx_pinbased_ctls_low, | |
2893 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
b87a51ae NHE |
2894 | break; |
2895 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
b9c237bb WV |
2896 | *pdata = vmx_control_msr( |
2897 | vmx->nested.nested_vmx_true_procbased_ctls_low, | |
2898 | vmx->nested.nested_vmx_procbased_ctls_high); | |
3dcdf3ec | 2899 | break; |
b87a51ae | 2900 | case MSR_IA32_VMX_PROCBASED_CTLS: |
b9c237bb WV |
2901 | *pdata = vmx_control_msr( |
2902 | vmx->nested.nested_vmx_procbased_ctls_low, | |
2903 | vmx->nested.nested_vmx_procbased_ctls_high); | |
b87a51ae NHE |
2904 | break; |
2905 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
b9c237bb WV |
2906 | *pdata = vmx_control_msr( |
2907 | vmx->nested.nested_vmx_true_exit_ctls_low, | |
2908 | vmx->nested.nested_vmx_exit_ctls_high); | |
2996fca0 | 2909 | break; |
b87a51ae | 2910 | case MSR_IA32_VMX_EXIT_CTLS: |
b9c237bb WV |
2911 | *pdata = vmx_control_msr( |
2912 | vmx->nested.nested_vmx_exit_ctls_low, | |
2913 | vmx->nested.nested_vmx_exit_ctls_high); | |
b87a51ae NHE |
2914 | break; |
2915 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
b9c237bb WV |
2916 | *pdata = vmx_control_msr( |
2917 | vmx->nested.nested_vmx_true_entry_ctls_low, | |
2918 | vmx->nested.nested_vmx_entry_ctls_high); | |
2996fca0 | 2919 | break; |
b87a51ae | 2920 | case MSR_IA32_VMX_ENTRY_CTLS: |
b9c237bb WV |
2921 | *pdata = vmx_control_msr( |
2922 | vmx->nested.nested_vmx_entry_ctls_low, | |
2923 | vmx->nested.nested_vmx_entry_ctls_high); | |
b87a51ae NHE |
2924 | break; |
2925 | case MSR_IA32_VMX_MISC: | |
b9c237bb WV |
2926 | *pdata = vmx_control_msr( |
2927 | vmx->nested.nested_vmx_misc_low, | |
2928 | vmx->nested.nested_vmx_misc_high); | |
b87a51ae NHE |
2929 | break; |
2930 | /* | |
2931 | * These MSRs specify bits which the guest must keep fixed (on or off) | |
2932 | * while L1 is in VMXON mode (in L1's root mode, or running an L2). | |
2933 | * We picked the standard core2 setting. | |
2934 | */ | |
2935 | #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) | |
2936 | #define VMXON_CR4_ALWAYSON X86_CR4_VMXE | |
2937 | case MSR_IA32_VMX_CR0_FIXED0: | |
2938 | *pdata = VMXON_CR0_ALWAYSON; | |
2939 | break; | |
2940 | case MSR_IA32_VMX_CR0_FIXED1: | |
2941 | *pdata = -1ULL; | |
2942 | break; | |
2943 | case MSR_IA32_VMX_CR4_FIXED0: | |
2944 | *pdata = VMXON_CR4_ALWAYSON; | |
2945 | break; | |
2946 | case MSR_IA32_VMX_CR4_FIXED1: | |
2947 | *pdata = -1ULL; | |
2948 | break; | |
2949 | case MSR_IA32_VMX_VMCS_ENUM: | |
5381417f | 2950 | *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */ |
b87a51ae NHE |
2951 | break; |
2952 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
b9c237bb WV |
2953 | *pdata = vmx_control_msr( |
2954 | vmx->nested.nested_vmx_secondary_ctls_low, | |
2955 | vmx->nested.nested_vmx_secondary_ctls_high); | |
b87a51ae NHE |
2956 | break; |
2957 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
089d7b6e WL |
2958 | *pdata = vmx->nested.nested_vmx_ept_caps | |
2959 | ((u64)vmx->nested.nested_vmx_vpid_caps << 32); | |
b87a51ae NHE |
2960 | break; |
2961 | default: | |
b87a51ae | 2962 | return 1; |
b3897a49 NHE |
2963 | } |
2964 | ||
b87a51ae NHE |
2965 | return 0; |
2966 | } | |
2967 | ||
37e4c997 HZ |
2968 | static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, |
2969 | uint64_t val) | |
2970 | { | |
2971 | uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; | |
2972 | ||
2973 | return !(val & ~valid_bits); | |
2974 | } | |
2975 | ||
6aa8b732 AK |
2976 | /* |
2977 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2978 | * Returns 0 on success, non-0 otherwise. | |
2979 | * Assumes vcpu_load() was already called. | |
2980 | */ | |
609e36d3 | 2981 | static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 2982 | { |
26bb0981 | 2983 | struct shared_msr_entry *msr; |
6aa8b732 | 2984 | |
609e36d3 | 2985 | switch (msr_info->index) { |
05b3e0c2 | 2986 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2987 | case MSR_FS_BASE: |
609e36d3 | 2988 | msr_info->data = vmcs_readl(GUEST_FS_BASE); |
6aa8b732 AK |
2989 | break; |
2990 | case MSR_GS_BASE: | |
609e36d3 | 2991 | msr_info->data = vmcs_readl(GUEST_GS_BASE); |
6aa8b732 | 2992 | break; |
44ea2b17 AK |
2993 | case MSR_KERNEL_GS_BASE: |
2994 | vmx_load_host_state(to_vmx(vcpu)); | |
609e36d3 | 2995 | msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base; |
44ea2b17 | 2996 | break; |
26bb0981 | 2997 | #endif |
6aa8b732 | 2998 | case MSR_EFER: |
609e36d3 | 2999 | return kvm_get_msr_common(vcpu, msr_info); |
af24a4e4 | 3000 | case MSR_IA32_TSC: |
be7b263e | 3001 | msr_info->data = guest_read_tsc(vcpu); |
6aa8b732 AK |
3002 | break; |
3003 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 3004 | msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); |
6aa8b732 AK |
3005 | break; |
3006 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3007 | msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
3008 | break; |
3009 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3010 | msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 3011 | break; |
0dd376e7 | 3012 | case MSR_IA32_BNDCFGS: |
a87036ad | 3013 | if (!kvm_mpx_supported()) |
93c4adc7 | 3014 | return 1; |
609e36d3 | 3015 | msr_info->data = vmcs_read64(GUEST_BNDCFGS); |
0dd376e7 | 3016 | break; |
c45dcc71 AR |
3017 | case MSR_IA32_MCG_EXT_CTL: |
3018 | if (!msr_info->host_initiated && | |
3019 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3020 | FEATURE_CONTROL_LMCE)) | |
cae50139 | 3021 | return 1; |
c45dcc71 AR |
3022 | msr_info->data = vcpu->arch.mcg_ext_ctl; |
3023 | break; | |
cae50139 | 3024 | case MSR_IA32_FEATURE_CONTROL: |
3b84080b | 3025 | msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control; |
cae50139 JK |
3026 | break; |
3027 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
3028 | if (!nested_vmx_allowed(vcpu)) | |
3029 | return 1; | |
609e36d3 | 3030 | return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data); |
20300099 WL |
3031 | case MSR_IA32_XSS: |
3032 | if (!vmx_xsaves_supported()) | |
3033 | return 1; | |
609e36d3 | 3034 | msr_info->data = vcpu->arch.ia32_xss; |
20300099 | 3035 | break; |
4e47c7a6 | 3036 | case MSR_TSC_AUX: |
81b1b9ca | 3037 | if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated) |
4e47c7a6 SY |
3038 | return 1; |
3039 | /* Otherwise falls through */ | |
6aa8b732 | 3040 | default: |
609e36d3 | 3041 | msr = find_msr_entry(to_vmx(vcpu), msr_info->index); |
3bab1f5d | 3042 | if (msr) { |
609e36d3 | 3043 | msr_info->data = msr->data; |
3bab1f5d | 3044 | break; |
6aa8b732 | 3045 | } |
609e36d3 | 3046 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3047 | } |
3048 | ||
6aa8b732 AK |
3049 | return 0; |
3050 | } | |
3051 | ||
cae50139 JK |
3052 | static void vmx_leave_nested(struct kvm_vcpu *vcpu); |
3053 | ||
6aa8b732 AK |
3054 | /* |
3055 | * Writes msr value into into the appropriate "register". | |
3056 | * Returns 0 on success, non-0 otherwise. | |
3057 | * Assumes vcpu_load() was already called. | |
3058 | */ | |
8fe8ab46 | 3059 | static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3060 | { |
a2fa3e9f | 3061 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 3062 | struct shared_msr_entry *msr; |
2cc51560 | 3063 | int ret = 0; |
8fe8ab46 WA |
3064 | u32 msr_index = msr_info->index; |
3065 | u64 data = msr_info->data; | |
2cc51560 | 3066 | |
6aa8b732 | 3067 | switch (msr_index) { |
3bab1f5d | 3068 | case MSR_EFER: |
8fe8ab46 | 3069 | ret = kvm_set_msr_common(vcpu, msr_info); |
2cc51560 | 3070 | break; |
16175a79 | 3071 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3072 | case MSR_FS_BASE: |
2fb92db1 | 3073 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3074 | vmcs_writel(GUEST_FS_BASE, data); |
3075 | break; | |
3076 | case MSR_GS_BASE: | |
2fb92db1 | 3077 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3078 | vmcs_writel(GUEST_GS_BASE, data); |
3079 | break; | |
44ea2b17 AK |
3080 | case MSR_KERNEL_GS_BASE: |
3081 | vmx_load_host_state(vmx); | |
3082 | vmx->msr_guest_kernel_gs_base = data; | |
3083 | break; | |
6aa8b732 AK |
3084 | #endif |
3085 | case MSR_IA32_SYSENTER_CS: | |
3086 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
3087 | break; | |
3088 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 3089 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
3090 | break; |
3091 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 3092 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 3093 | break; |
0dd376e7 | 3094 | case MSR_IA32_BNDCFGS: |
a87036ad | 3095 | if (!kvm_mpx_supported()) |
93c4adc7 | 3096 | return 1; |
0dd376e7 LJ |
3097 | vmcs_write64(GUEST_BNDCFGS, data); |
3098 | break; | |
af24a4e4 | 3099 | case MSR_IA32_TSC: |
8fe8ab46 | 3100 | kvm_write_tsc(vcpu, msr_info); |
6aa8b732 | 3101 | break; |
468d472f SY |
3102 | case MSR_IA32_CR_PAT: |
3103 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
4566654b NA |
3104 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) |
3105 | return 1; | |
468d472f SY |
3106 | vmcs_write64(GUEST_IA32_PAT, data); |
3107 | vcpu->arch.pat = data; | |
3108 | break; | |
3109 | } | |
8fe8ab46 | 3110 | ret = kvm_set_msr_common(vcpu, msr_info); |
4e47c7a6 | 3111 | break; |
ba904635 WA |
3112 | case MSR_IA32_TSC_ADJUST: |
3113 | ret = kvm_set_msr_common(vcpu, msr_info); | |
4e47c7a6 | 3114 | break; |
c45dcc71 AR |
3115 | case MSR_IA32_MCG_EXT_CTL: |
3116 | if ((!msr_info->host_initiated && | |
3117 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3118 | FEATURE_CONTROL_LMCE)) || | |
3119 | (data & ~MCG_EXT_CTL_LMCE_EN)) | |
3120 | return 1; | |
3121 | vcpu->arch.mcg_ext_ctl = data; | |
3122 | break; | |
cae50139 | 3123 | case MSR_IA32_FEATURE_CONTROL: |
37e4c997 | 3124 | if (!vmx_feature_control_msr_valid(vcpu, data) || |
3b84080b | 3125 | (to_vmx(vcpu)->msr_ia32_feature_control & |
cae50139 JK |
3126 | FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) |
3127 | return 1; | |
3b84080b | 3128 | vmx->msr_ia32_feature_control = data; |
cae50139 JK |
3129 | if (msr_info->host_initiated && data == 0) |
3130 | vmx_leave_nested(vcpu); | |
3131 | break; | |
3132 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
3133 | return 1; /* they are read-only */ | |
20300099 WL |
3134 | case MSR_IA32_XSS: |
3135 | if (!vmx_xsaves_supported()) | |
3136 | return 1; | |
3137 | /* | |
3138 | * The only supported bit as of Skylake is bit 8, but | |
3139 | * it is not supported on KVM. | |
3140 | */ | |
3141 | if (data != 0) | |
3142 | return 1; | |
3143 | vcpu->arch.ia32_xss = data; | |
3144 | if (vcpu->arch.ia32_xss != host_xss) | |
3145 | add_atomic_switch_msr(vmx, MSR_IA32_XSS, | |
3146 | vcpu->arch.ia32_xss, host_xss); | |
3147 | else | |
3148 | clear_atomic_switch_msr(vmx, MSR_IA32_XSS); | |
3149 | break; | |
4e47c7a6 | 3150 | case MSR_TSC_AUX: |
81b1b9ca | 3151 | if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated) |
4e47c7a6 SY |
3152 | return 1; |
3153 | /* Check reserved bit, higher 32 bits should be zero */ | |
3154 | if ((data >> 32) != 0) | |
3155 | return 1; | |
3156 | /* Otherwise falls through */ | |
6aa8b732 | 3157 | default: |
8b9cf98c | 3158 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 3159 | if (msr) { |
8b3c3104 | 3160 | u64 old_msr_data = msr->data; |
3bab1f5d | 3161 | msr->data = data; |
2225fd56 AK |
3162 | if (msr - vmx->guest_msrs < vmx->save_nmsrs) { |
3163 | preempt_disable(); | |
8b3c3104 AH |
3164 | ret = kvm_set_shared_msr(msr->index, msr->data, |
3165 | msr->mask); | |
2225fd56 | 3166 | preempt_enable(); |
8b3c3104 AH |
3167 | if (ret) |
3168 | msr->data = old_msr_data; | |
2225fd56 | 3169 | } |
3bab1f5d | 3170 | break; |
6aa8b732 | 3171 | } |
8fe8ab46 | 3172 | ret = kvm_set_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3173 | } |
3174 | ||
2cc51560 | 3175 | return ret; |
6aa8b732 AK |
3176 | } |
3177 | ||
5fdbf976 | 3178 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 3179 | { |
5fdbf976 MT |
3180 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
3181 | switch (reg) { | |
3182 | case VCPU_REGS_RSP: | |
3183 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
3184 | break; | |
3185 | case VCPU_REGS_RIP: | |
3186 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
3187 | break; | |
6de4f3ad AK |
3188 | case VCPU_EXREG_PDPTR: |
3189 | if (enable_ept) | |
3190 | ept_save_pdptrs(vcpu); | |
3191 | break; | |
5fdbf976 MT |
3192 | default: |
3193 | break; | |
3194 | } | |
6aa8b732 AK |
3195 | } |
3196 | ||
6aa8b732 AK |
3197 | static __init int cpu_has_kvm_support(void) |
3198 | { | |
6210e37b | 3199 | return cpu_has_vmx(); |
6aa8b732 AK |
3200 | } |
3201 | ||
3202 | static __init int vmx_disabled_by_bios(void) | |
3203 | { | |
3204 | u64 msr; | |
3205 | ||
3206 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 3207 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 3208 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
3209 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
3210 | && tboot_enabled()) | |
3211 | return 1; | |
23f3e991 | 3212 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 3213 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 3214 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
3215 | && !tboot_enabled()) { |
3216 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 3217 | "activate TXT before enabling KVM\n"); |
cafd6659 | 3218 | return 1; |
f9335afe | 3219 | } |
23f3e991 JC |
3220 | /* launched w/o TXT and VMX disabled */ |
3221 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
3222 | && !tboot_enabled()) | |
3223 | return 1; | |
cafd6659 SW |
3224 | } |
3225 | ||
3226 | return 0; | |
6aa8b732 AK |
3227 | } |
3228 | ||
7725b894 DX |
3229 | static void kvm_cpu_vmxon(u64 addr) |
3230 | { | |
1c5ac21a AS |
3231 | intel_pt_handle_vmx(1); |
3232 | ||
7725b894 DX |
3233 | asm volatile (ASM_VMX_VMXON_RAX |
3234 | : : "a"(&addr), "m"(addr) | |
3235 | : "memory", "cc"); | |
3236 | } | |
3237 | ||
13a34e06 | 3238 | static int hardware_enable(void) |
6aa8b732 AK |
3239 | { |
3240 | int cpu = raw_smp_processor_id(); | |
3241 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 3242 | u64 old, test_bits; |
6aa8b732 | 3243 | |
1e02ce4c | 3244 | if (cr4_read_shadow() & X86_CR4_VMXE) |
10474ae8 AG |
3245 | return -EBUSY; |
3246 | ||
d462b819 | 3247 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
bf9f6ac8 FW |
3248 | INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); |
3249 | spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
8f536b76 ZY |
3250 | |
3251 | /* | |
3252 | * Now we can enable the vmclear operation in kdump | |
3253 | * since the loaded_vmcss_on_cpu list on this cpu | |
3254 | * has been initialized. | |
3255 | * | |
3256 | * Though the cpu is not in VMX operation now, there | |
3257 | * is no problem to enable the vmclear operation | |
3258 | * for the loaded_vmcss_on_cpu list is empty! | |
3259 | */ | |
3260 | crash_enable_local_vmclear(cpu); | |
3261 | ||
6aa8b732 | 3262 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
3263 | |
3264 | test_bits = FEATURE_CONTROL_LOCKED; | |
3265 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
3266 | if (tboot_enabled()) | |
3267 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
3268 | ||
3269 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 3270 | /* enable and lock */ |
cafd6659 SW |
3271 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
3272 | } | |
375074cc | 3273 | cr4_set_bits(X86_CR4_VMXE); |
10474ae8 | 3274 | |
4610c9cc DX |
3275 | if (vmm_exclusive) { |
3276 | kvm_cpu_vmxon(phys_addr); | |
3277 | ept_sync_global(); | |
3278 | } | |
10474ae8 | 3279 | |
89cbc767 | 3280 | native_store_gdt(this_cpu_ptr(&host_gdt)); |
3444d7da | 3281 | |
10474ae8 | 3282 | return 0; |
6aa8b732 AK |
3283 | } |
3284 | ||
d462b819 | 3285 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
3286 | { |
3287 | int cpu = raw_smp_processor_id(); | |
d462b819 | 3288 | struct loaded_vmcs *v, *n; |
543e4243 | 3289 | |
d462b819 NHE |
3290 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
3291 | loaded_vmcss_on_cpu_link) | |
3292 | __loaded_vmcs_clear(v); | |
543e4243 AK |
3293 | } |
3294 | ||
710ff4a8 EH |
3295 | |
3296 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
3297 | * tricks. | |
3298 | */ | |
3299 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 3300 | { |
4ecac3fd | 3301 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
1c5ac21a AS |
3302 | |
3303 | intel_pt_handle_vmx(0); | |
6aa8b732 AK |
3304 | } |
3305 | ||
13a34e06 | 3306 | static void hardware_disable(void) |
710ff4a8 | 3307 | { |
4610c9cc | 3308 | if (vmm_exclusive) { |
d462b819 | 3309 | vmclear_local_loaded_vmcss(); |
4610c9cc DX |
3310 | kvm_cpu_vmxoff(); |
3311 | } | |
375074cc | 3312 | cr4_clear_bits(X86_CR4_VMXE); |
710ff4a8 EH |
3313 | } |
3314 | ||
1c3d14fe | 3315 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 3316 | u32 msr, u32 *result) |
1c3d14fe YS |
3317 | { |
3318 | u32 vmx_msr_low, vmx_msr_high; | |
3319 | u32 ctl = ctl_min | ctl_opt; | |
3320 | ||
3321 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3322 | ||
3323 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
3324 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
3325 | ||
3326 | /* Ensure minimum (required) set of control bits are supported. */ | |
3327 | if (ctl_min & ~ctl) | |
002c7f7c | 3328 | return -EIO; |
1c3d14fe YS |
3329 | |
3330 | *result = ctl; | |
3331 | return 0; | |
3332 | } | |
3333 | ||
110312c8 AK |
3334 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
3335 | { | |
3336 | u32 vmx_msr_low, vmx_msr_high; | |
3337 | ||
3338 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3339 | return vmx_msr_high & ctl; | |
3340 | } | |
3341 | ||
002c7f7c | 3342 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
3343 | { |
3344 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 3345 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
3346 | u32 _pin_based_exec_control = 0; |
3347 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 3348 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
3349 | u32 _vmexit_control = 0; |
3350 | u32 _vmentry_control = 0; | |
3351 | ||
10166744 | 3352 | min = CPU_BASED_HLT_EXITING | |
1c3d14fe YS |
3353 | #ifdef CONFIG_X86_64 |
3354 | CPU_BASED_CR8_LOAD_EXITING | | |
3355 | CPU_BASED_CR8_STORE_EXITING | | |
3356 | #endif | |
d56f546d SY |
3357 | CPU_BASED_CR3_LOAD_EXITING | |
3358 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
3359 | CPU_BASED_USE_IO_BITMAPS | |
3360 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 3361 | CPU_BASED_USE_TSC_OFFSETING | |
59708670 SY |
3362 | CPU_BASED_MWAIT_EXITING | |
3363 | CPU_BASED_MONITOR_EXITING | | |
fee84b07 AK |
3364 | CPU_BASED_INVLPG_EXITING | |
3365 | CPU_BASED_RDPMC_EXITING; | |
443381a8 | 3366 | |
f78e0e2e | 3367 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 3368 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 3369 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
3370 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
3371 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 3372 | return -EIO; |
6e5d865c YS |
3373 | #ifdef CONFIG_X86_64 |
3374 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3375 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
3376 | ~CPU_BASED_CR8_STORE_EXITING; | |
3377 | #endif | |
f78e0e2e | 3378 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
3379 | min2 = 0; |
3380 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
8d14695f | 3381 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2384d2b3 | 3382 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 3383 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 3384 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 3385 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 | 3386 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
ad756a16 | 3387 | SECONDARY_EXEC_RDTSCP | |
83d4c286 | 3388 | SECONDARY_EXEC_ENABLE_INVPCID | |
c7c9c56c | 3389 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
abc4fc58 | 3390 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
20300099 | 3391 | SECONDARY_EXEC_SHADOW_VMCS | |
843e4330 | 3392 | SECONDARY_EXEC_XSAVES | |
8b3e34e4 | 3393 | SECONDARY_EXEC_ENABLE_PML | |
64903d61 | 3394 | SECONDARY_EXEC_TSC_SCALING; |
d56f546d SY |
3395 | if (adjust_vmx_controls(min2, opt2, |
3396 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
3397 | &_cpu_based_2nd_exec_control) < 0) |
3398 | return -EIO; | |
3399 | } | |
3400 | #ifndef CONFIG_X86_64 | |
3401 | if (!(_cpu_based_2nd_exec_control & | |
3402 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
3403 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
3404 | #endif | |
83d4c286 YZ |
3405 | |
3406 | if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3407 | _cpu_based_2nd_exec_control &= ~( | |
8d14695f | 3408 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
c7c9c56c YZ |
3409 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
3410 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
83d4c286 | 3411 | |
d56f546d | 3412 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
3413 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
3414 | enabled */ | |
5fff7d27 GN |
3415 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
3416 | CPU_BASED_CR3_STORE_EXITING | | |
3417 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
3418 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, |
3419 | vmx_capability.ept, vmx_capability.vpid); | |
3420 | } | |
1c3d14fe | 3421 | |
91fa0f8e | 3422 | min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; |
1c3d14fe YS |
3423 | #ifdef CONFIG_X86_64 |
3424 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
3425 | #endif | |
a547c6db | 3426 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT | |
91fa0f8e | 3427 | VM_EXIT_CLEAR_BNDCFGS; |
1c3d14fe YS |
3428 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
3429 | &_vmexit_control) < 0) | |
002c7f7c | 3430 | return -EIO; |
1c3d14fe | 3431 | |
01e439be | 3432 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; |
64672c95 YJ |
3433 | opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | |
3434 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
3435 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
3436 | &_pin_based_exec_control) < 0) | |
3437 | return -EIO; | |
3438 | ||
1c17c3e6 PB |
3439 | if (cpu_has_broken_vmx_preemption_timer()) |
3440 | _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be | 3441 | if (!(_cpu_based_2nd_exec_control & |
91fa0f8e | 3442 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) |
01e439be YZ |
3443 | _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; |
3444 | ||
c845f9c6 | 3445 | min = VM_ENTRY_LOAD_DEBUG_CONTROLS; |
da8999d3 | 3446 | opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS; |
1c3d14fe YS |
3447 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
3448 | &_vmentry_control) < 0) | |
002c7f7c | 3449 | return -EIO; |
6aa8b732 | 3450 | |
c68876fd | 3451 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
3452 | |
3453 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
3454 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 3455 | return -EIO; |
1c3d14fe YS |
3456 | |
3457 | #ifdef CONFIG_X86_64 | |
3458 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
3459 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 3460 | return -EIO; |
1c3d14fe YS |
3461 | #endif |
3462 | ||
3463 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
3464 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 3465 | return -EIO; |
1c3d14fe | 3466 | |
002c7f7c | 3467 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
16cb0255 | 3468 | vmcs_conf->order = get_order(vmcs_conf->size); |
9ac7e3e8 | 3469 | vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; |
002c7f7c | 3470 | vmcs_conf->revision_id = vmx_msr_low; |
1c3d14fe | 3471 | |
002c7f7c YS |
3472 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
3473 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 3474 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
3475 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
3476 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 3477 | |
110312c8 AK |
3478 | cpu_has_load_ia32_efer = |
3479 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3480 | VM_ENTRY_LOAD_IA32_EFER) | |
3481 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3482 | VM_EXIT_LOAD_IA32_EFER); | |
3483 | ||
8bf00a52 GN |
3484 | cpu_has_load_perf_global_ctrl = |
3485 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3486 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
3487 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3488 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
3489 | ||
3490 | /* | |
3491 | * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL | |
bb3541f1 | 3492 | * but due to errata below it can't be used. Workaround is to use |
8bf00a52 GN |
3493 | * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. |
3494 | * | |
3495 | * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] | |
3496 | * | |
3497 | * AAK155 (model 26) | |
3498 | * AAP115 (model 30) | |
3499 | * AAT100 (model 37) | |
3500 | * BC86,AAY89,BD102 (model 44) | |
3501 | * BA97 (model 46) | |
3502 | * | |
3503 | */ | |
3504 | if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) { | |
3505 | switch (boot_cpu_data.x86_model) { | |
3506 | case 26: | |
3507 | case 30: | |
3508 | case 37: | |
3509 | case 44: | |
3510 | case 46: | |
3511 | cpu_has_load_perf_global_ctrl = false; | |
3512 | printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " | |
3513 | "does not work properly. Using workaround\n"); | |
3514 | break; | |
3515 | default: | |
3516 | break; | |
3517 | } | |
3518 | } | |
3519 | ||
782511b0 | 3520 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
20300099 WL |
3521 | rdmsrl(MSR_IA32_XSS, host_xss); |
3522 | ||
1c3d14fe | 3523 | return 0; |
c68876fd | 3524 | } |
6aa8b732 AK |
3525 | |
3526 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
3527 | { | |
3528 | int node = cpu_to_node(cpu); | |
3529 | struct page *pages; | |
3530 | struct vmcs *vmcs; | |
3531 | ||
96db800f | 3532 | pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
3533 | if (!pages) |
3534 | return NULL; | |
3535 | vmcs = page_address(pages); | |
1c3d14fe YS |
3536 | memset(vmcs, 0, vmcs_config.size); |
3537 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
3538 | return vmcs; |
3539 | } | |
3540 | ||
3541 | static struct vmcs *alloc_vmcs(void) | |
3542 | { | |
d3b2c338 | 3543 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
3544 | } |
3545 | ||
3546 | static void free_vmcs(struct vmcs *vmcs) | |
3547 | { | |
1c3d14fe | 3548 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
3549 | } |
3550 | ||
d462b819 NHE |
3551 | /* |
3552 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
3553 | */ | |
3554 | static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
3555 | { | |
3556 | if (!loaded_vmcs->vmcs) | |
3557 | return; | |
3558 | loaded_vmcs_clear(loaded_vmcs); | |
3559 | free_vmcs(loaded_vmcs->vmcs); | |
3560 | loaded_vmcs->vmcs = NULL; | |
355f4fb1 | 3561 | WARN_ON(loaded_vmcs->shadow_vmcs != NULL); |
d462b819 NHE |
3562 | } |
3563 | ||
39959588 | 3564 | static void free_kvm_area(void) |
6aa8b732 AK |
3565 | { |
3566 | int cpu; | |
3567 | ||
3230bb47 | 3568 | for_each_possible_cpu(cpu) { |
6aa8b732 | 3569 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
3570 | per_cpu(vmxarea, cpu) = NULL; |
3571 | } | |
6aa8b732 AK |
3572 | } |
3573 | ||
fe2b201b BD |
3574 | static void init_vmcs_shadow_fields(void) |
3575 | { | |
3576 | int i, j; | |
3577 | ||
3578 | /* No checks for read only fields yet */ | |
3579 | ||
3580 | for (i = j = 0; i < max_shadow_read_write_fields; i++) { | |
3581 | switch (shadow_read_write_fields[i]) { | |
3582 | case GUEST_BNDCFGS: | |
a87036ad | 3583 | if (!kvm_mpx_supported()) |
fe2b201b BD |
3584 | continue; |
3585 | break; | |
3586 | default: | |
3587 | break; | |
3588 | } | |
3589 | ||
3590 | if (j < i) | |
3591 | shadow_read_write_fields[j] = | |
3592 | shadow_read_write_fields[i]; | |
3593 | j++; | |
3594 | } | |
3595 | max_shadow_read_write_fields = j; | |
3596 | ||
3597 | /* shadowed fields guest access without vmexit */ | |
3598 | for (i = 0; i < max_shadow_read_write_fields; i++) { | |
3599 | clear_bit(shadow_read_write_fields[i], | |
3600 | vmx_vmwrite_bitmap); | |
3601 | clear_bit(shadow_read_write_fields[i], | |
3602 | vmx_vmread_bitmap); | |
3603 | } | |
3604 | for (i = 0; i < max_shadow_read_only_fields; i++) | |
3605 | clear_bit(shadow_read_only_fields[i], | |
3606 | vmx_vmread_bitmap); | |
3607 | } | |
3608 | ||
6aa8b732 AK |
3609 | static __init int alloc_kvm_area(void) |
3610 | { | |
3611 | int cpu; | |
3612 | ||
3230bb47 | 3613 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
3614 | struct vmcs *vmcs; |
3615 | ||
3616 | vmcs = alloc_vmcs_cpu(cpu); | |
3617 | if (!vmcs) { | |
3618 | free_kvm_area(); | |
3619 | return -ENOMEM; | |
3620 | } | |
3621 | ||
3622 | per_cpu(vmxarea, cpu) = vmcs; | |
3623 | } | |
3624 | return 0; | |
3625 | } | |
3626 | ||
14168786 GN |
3627 | static bool emulation_required(struct kvm_vcpu *vcpu) |
3628 | { | |
3629 | return emulate_invalid_guest_state && !guest_state_valid(vcpu); | |
3630 | } | |
3631 | ||
91b0aa2c | 3632 | static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, |
d99e4152 | 3633 | struct kvm_segment *save) |
6aa8b732 | 3634 | { |
d99e4152 GN |
3635 | if (!emulate_invalid_guest_state) { |
3636 | /* | |
3637 | * CS and SS RPL should be equal during guest entry according | |
3638 | * to VMX spec, but in reality it is not always so. Since vcpu | |
3639 | * is in the middle of the transition from real mode to | |
3640 | * protected mode it is safe to assume that RPL 0 is a good | |
3641 | * default value. | |
3642 | */ | |
3643 | if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) | |
b32a9918 NA |
3644 | save->selector &= ~SEGMENT_RPL_MASK; |
3645 | save->dpl = save->selector & SEGMENT_RPL_MASK; | |
d99e4152 | 3646 | save->s = 1; |
6aa8b732 | 3647 | } |
d99e4152 | 3648 | vmx_set_segment(vcpu, save, seg); |
6aa8b732 AK |
3649 | } |
3650 | ||
3651 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
3652 | { | |
3653 | unsigned long flags; | |
a89a8fb9 | 3654 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3655 | |
d99e4152 GN |
3656 | /* |
3657 | * Update real mode segment cache. It may be not up-to-date if sement | |
3658 | * register was written while vcpu was in a guest mode. | |
3659 | */ | |
3660 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3661 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3662 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3663 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
3664 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); | |
3665 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
3666 | ||
7ffd92c5 | 3667 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 3668 | |
2fb92db1 AK |
3669 | vmx_segment_cache_clear(vmx); |
3670 | ||
f5f7b2fe | 3671 | vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
6aa8b732 AK |
3672 | |
3673 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
3674 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
3675 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
3676 | vmcs_writel(GUEST_RFLAGS, flags); |
3677 | ||
66aee91a RR |
3678 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
3679 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
3680 | |
3681 | update_exception_bitmap(vcpu); | |
3682 | ||
91b0aa2c GN |
3683 | fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); |
3684 | fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); | |
3685 | fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
3686 | fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
3687 | fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
3688 | fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
6aa8b732 AK |
3689 | } |
3690 | ||
f5f7b2fe | 3691 | static void fix_rmode_seg(int seg, struct kvm_segment *save) |
6aa8b732 | 3692 | { |
772e0318 | 3693 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
d99e4152 GN |
3694 | struct kvm_segment var = *save; |
3695 | ||
3696 | var.dpl = 0x3; | |
3697 | if (seg == VCPU_SREG_CS) | |
3698 | var.type = 0x3; | |
3699 | ||
3700 | if (!emulate_invalid_guest_state) { | |
3701 | var.selector = var.base >> 4; | |
3702 | var.base = var.base & 0xffff0; | |
3703 | var.limit = 0xffff; | |
3704 | var.g = 0; | |
3705 | var.db = 0; | |
3706 | var.present = 1; | |
3707 | var.s = 1; | |
3708 | var.l = 0; | |
3709 | var.unusable = 0; | |
3710 | var.type = 0x3; | |
3711 | var.avl = 0; | |
3712 | if (save->base & 0xf) | |
3713 | printk_once(KERN_WARNING "kvm: segment base is not " | |
3714 | "paragraph aligned when entering " | |
3715 | "protected mode (seg=%d)", seg); | |
3716 | } | |
6aa8b732 | 3717 | |
d99e4152 GN |
3718 | vmcs_write16(sf->selector, var.selector); |
3719 | vmcs_write32(sf->base, var.base); | |
3720 | vmcs_write32(sf->limit, var.limit); | |
3721 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); | |
6aa8b732 AK |
3722 | } |
3723 | ||
3724 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
3725 | { | |
3726 | unsigned long flags; | |
a89a8fb9 | 3727 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3728 | |
f5f7b2fe AK |
3729 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
3730 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3731 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3732 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3733 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
c6ad1153 GN |
3734 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); |
3735 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
f5f7b2fe | 3736 | |
7ffd92c5 | 3737 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 3738 | |
776e58ea GN |
3739 | /* |
3740 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
4918c6ca | 3741 | * vcpu. Warn the user that an update is overdue. |
776e58ea | 3742 | */ |
4918c6ca | 3743 | if (!vcpu->kvm->arch.tss_addr) |
776e58ea GN |
3744 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " |
3745 | "called before entering vcpu\n"); | |
776e58ea | 3746 | |
2fb92db1 AK |
3747 | vmx_segment_cache_clear(vmx); |
3748 | ||
4918c6ca | 3749 | vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr); |
6aa8b732 | 3750 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
6aa8b732 AK |
3751 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
3752 | ||
3753 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 3754 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 3755 | |
053de044 | 3756 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
3757 | |
3758 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 3759 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
3760 | update_exception_bitmap(vcpu); |
3761 | ||
d99e4152 GN |
3762 | fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); |
3763 | fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); | |
3764 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
3765 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
3766 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
3767 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
b246dd5d | 3768 | |
8668a3c4 | 3769 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
3770 | } |
3771 | ||
401d10de AS |
3772 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
3773 | { | |
3774 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
3775 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
3776 | ||
3777 | if (!msr) | |
3778 | return; | |
401d10de | 3779 | |
44ea2b17 AK |
3780 | /* |
3781 | * Force kernel_gs_base reloading before EFER changes, as control | |
3782 | * of this msr depends on is_long_mode(). | |
3783 | */ | |
3784 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 3785 | vcpu->arch.efer = efer; |
401d10de | 3786 | if (efer & EFER_LMA) { |
2961e876 | 3787 | vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
3788 | msr->data = efer; |
3789 | } else { | |
2961e876 | 3790 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
3791 | |
3792 | msr->data = efer & ~EFER_LME; | |
3793 | } | |
3794 | setup_msrs(vmx); | |
3795 | } | |
3796 | ||
05b3e0c2 | 3797 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
3798 | |
3799 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
3800 | { | |
3801 | u32 guest_tr_ar; | |
3802 | ||
2fb92db1 AK |
3803 | vmx_segment_cache_clear(to_vmx(vcpu)); |
3804 | ||
6aa8b732 | 3805 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
4d283ec9 | 3806 | if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { |
bd80158a JK |
3807 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
3808 | __func__); | |
6aa8b732 | 3809 | vmcs_write32(GUEST_TR_AR_BYTES, |
4d283ec9 AL |
3810 | (guest_tr_ar & ~VMX_AR_TYPE_MASK) |
3811 | | VMX_AR_TYPE_BUSY_64_TSS); | |
6aa8b732 | 3812 | } |
da38f438 | 3813 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
3814 | } |
3815 | ||
3816 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
3817 | { | |
2961e876 | 3818 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
da38f438 | 3819 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
3820 | } |
3821 | ||
3822 | #endif | |
3823 | ||
dd5f5341 | 3824 | static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid) |
2384d2b3 | 3825 | { |
dd5f5341 | 3826 | vpid_sync_context(vpid); |
dd180b3e XG |
3827 | if (enable_ept) { |
3828 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3829 | return; | |
4e1096d2 | 3830 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); |
dd180b3e | 3831 | } |
2384d2b3 SY |
3832 | } |
3833 | ||
dd5f5341 WL |
3834 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
3835 | { | |
3836 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid); | |
3837 | } | |
3838 | ||
e8467fda AK |
3839 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
3840 | { | |
3841 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
3842 | ||
3843 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
3844 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
3845 | } | |
3846 | ||
aff48baa AK |
3847 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
3848 | { | |
3849 | if (enable_ept && is_paging(vcpu)) | |
3850 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
3851 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
3852 | } | |
3853 | ||
25c4c276 | 3854 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 3855 | { |
fc78f519 AK |
3856 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
3857 | ||
3858 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
3859 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
3860 | } |
3861 | ||
1439442c SY |
3862 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
3863 | { | |
d0d538b9 GN |
3864 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
3865 | ||
6de4f3ad AK |
3866 | if (!test_bit(VCPU_EXREG_PDPTR, |
3867 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
3868 | return; | |
3869 | ||
1439442c | 3870 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
3871 | vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); |
3872 | vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); | |
3873 | vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); | |
3874 | vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); | |
1439442c SY |
3875 | } |
3876 | } | |
3877 | ||
8f5d549f AK |
3878 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
3879 | { | |
d0d538b9 GN |
3880 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
3881 | ||
8f5d549f | 3882 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
3883 | mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
3884 | mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
3885 | mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
3886 | mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 3887 | } |
6de4f3ad AK |
3888 | |
3889 | __set_bit(VCPU_EXREG_PDPTR, | |
3890 | (unsigned long *)&vcpu->arch.regs_avail); | |
3891 | __set_bit(VCPU_EXREG_PDPTR, | |
3892 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
3893 | } |
3894 | ||
5e1746d6 | 3895 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1439442c SY |
3896 | |
3897 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
3898 | unsigned long cr0, | |
3899 | struct kvm_vcpu *vcpu) | |
3900 | { | |
5233dd51 MT |
3901 | if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
3902 | vmx_decache_cr3(vcpu); | |
1439442c SY |
3903 | if (!(cr0 & X86_CR0_PG)) { |
3904 | /* From paging/starting to nonpaging */ | |
3905 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 3906 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
3907 | (CPU_BASED_CR3_LOAD_EXITING | |
3908 | CPU_BASED_CR3_STORE_EXITING)); | |
3909 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 3910 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
3911 | } else if (!is_paging(vcpu)) { |
3912 | /* From nonpaging to paging */ | |
3913 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 3914 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
3915 | ~(CPU_BASED_CR3_LOAD_EXITING | |
3916 | CPU_BASED_CR3_STORE_EXITING)); | |
3917 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 3918 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 3919 | } |
95eb84a7 SY |
3920 | |
3921 | if (!(cr0 & X86_CR0_WP)) | |
3922 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
3923 | } |
3924 | ||
6aa8b732 AK |
3925 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
3926 | { | |
7ffd92c5 | 3927 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
3928 | unsigned long hw_cr0; |
3929 | ||
5037878e | 3930 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK); |
3a624e29 | 3931 | if (enable_unrestricted_guest) |
5037878e | 3932 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; |
218e763f | 3933 | else { |
5037878e | 3934 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; |
1439442c | 3935 | |
218e763f GN |
3936 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
3937 | enter_pmode(vcpu); | |
6aa8b732 | 3938 | |
218e763f GN |
3939 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
3940 | enter_rmode(vcpu); | |
3941 | } | |
6aa8b732 | 3942 | |
05b3e0c2 | 3943 | #ifdef CONFIG_X86_64 |
f6801dff | 3944 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 3945 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 3946 | enter_lmode(vcpu); |
707d92fa | 3947 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
3948 | exit_lmode(vcpu); |
3949 | } | |
3950 | #endif | |
3951 | ||
089d034e | 3952 | if (enable_ept) |
1439442c SY |
3953 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
3954 | ||
02daab21 | 3955 | if (!vcpu->fpu_active) |
81231c69 | 3956 | hw_cr0 |= X86_CR0_TS | X86_CR0_MP; |
02daab21 | 3957 | |
6aa8b732 | 3958 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 3959 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 3960 | vcpu->arch.cr0 = cr0; |
14168786 GN |
3961 | |
3962 | /* depends on vcpu->arch.cr0 to be set to a new value */ | |
3963 | vmx->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
3964 | } |
3965 | ||
1439442c SY |
3966 | static u64 construct_eptp(unsigned long root_hpa) |
3967 | { | |
3968 | u64 eptp; | |
3969 | ||
3970 | /* TODO write the value reading from MSR */ | |
3971 | eptp = VMX_EPT_DEFAULT_MT | | |
3972 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
b38f9934 XH |
3973 | if (enable_ept_ad_bits) |
3974 | eptp |= VMX_EPT_AD_ENABLE_BIT; | |
1439442c SY |
3975 | eptp |= (root_hpa & PAGE_MASK); |
3976 | ||
3977 | return eptp; | |
3978 | } | |
3979 | ||
6aa8b732 AK |
3980 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
3981 | { | |
1439442c SY |
3982 | unsigned long guest_cr3; |
3983 | u64 eptp; | |
3984 | ||
3985 | guest_cr3 = cr3; | |
089d034e | 3986 | if (enable_ept) { |
1439442c SY |
3987 | eptp = construct_eptp(cr3); |
3988 | vmcs_write64(EPT_POINTER, eptp); | |
59ab5a8f JK |
3989 | if (is_paging(vcpu) || is_guest_mode(vcpu)) |
3990 | guest_cr3 = kvm_read_cr3(vcpu); | |
3991 | else | |
3992 | guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr; | |
7c93be44 | 3993 | ept_load_pdptrs(vcpu); |
1439442c SY |
3994 | } |
3995 | ||
2384d2b3 | 3996 | vmx_flush_tlb(vcpu); |
1439442c | 3997 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
3998 | } |
3999 | ||
5e1746d6 | 4000 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 4001 | { |
085e68ee BS |
4002 | /* |
4003 | * Pass through host's Machine Check Enable value to hw_cr4, which | |
4004 | * is in force while we are in guest mode. Do not let guests control | |
4005 | * this bit, even if host CR4.MCE == 0. | |
4006 | */ | |
4007 | unsigned long hw_cr4 = | |
4008 | (cr4_read_shadow() & X86_CR4_MCE) | | |
4009 | (cr4 & ~X86_CR4_MCE) | | |
4010 | (to_vmx(vcpu)->rmode.vm86_active ? | |
4011 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1439442c | 4012 | |
5e1746d6 NHE |
4013 | if (cr4 & X86_CR4_VMXE) { |
4014 | /* | |
4015 | * To use VMXON (and later other VMX instructions), a guest | |
4016 | * must first be able to turn on cr4.VMXE (see handle_vmon()). | |
4017 | * So basically the check on whether to allow nested VMX | |
4018 | * is here. | |
4019 | */ | |
4020 | if (!nested_vmx_allowed(vcpu)) | |
4021 | return 1; | |
1a0d74e6 JK |
4022 | } |
4023 | if (to_vmx(vcpu)->nested.vmxon && | |
4024 | ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) | |
5e1746d6 NHE |
4025 | return 1; |
4026 | ||
ad312c7c | 4027 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
4028 | if (enable_ept) { |
4029 | if (!is_paging(vcpu)) { | |
4030 | hw_cr4 &= ~X86_CR4_PAE; | |
4031 | hw_cr4 |= X86_CR4_PSE; | |
4032 | } else if (!(cr4 & X86_CR4_PAE)) { | |
4033 | hw_cr4 &= ~X86_CR4_PAE; | |
4034 | } | |
4035 | } | |
1439442c | 4036 | |
656ec4a4 RK |
4037 | if (!enable_unrestricted_guest && !is_paging(vcpu)) |
4038 | /* | |
ddba2628 HH |
4039 | * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in |
4040 | * hardware. To emulate this behavior, SMEP/SMAP/PKU needs | |
4041 | * to be manually disabled when guest switches to non-paging | |
4042 | * mode. | |
4043 | * | |
4044 | * If !enable_unrestricted_guest, the CPU is always running | |
4045 | * with CR0.PG=1 and CR4 needs to be modified. | |
4046 | * If enable_unrestricted_guest, the CPU automatically | |
4047 | * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. | |
656ec4a4 | 4048 | */ |
ddba2628 | 4049 | hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); |
656ec4a4 | 4050 | |
1439442c SY |
4051 | vmcs_writel(CR4_READ_SHADOW, cr4); |
4052 | vmcs_writel(GUEST_CR4, hw_cr4); | |
5e1746d6 | 4053 | return 0; |
6aa8b732 AK |
4054 | } |
4055 | ||
6aa8b732 AK |
4056 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
4057 | struct kvm_segment *var, int seg) | |
4058 | { | |
a9179499 | 4059 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
4060 | u32 ar; |
4061 | ||
c6ad1153 | 4062 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
f5f7b2fe | 4063 | *var = vmx->rmode.segs[seg]; |
a9179499 | 4064 | if (seg == VCPU_SREG_TR |
2fb92db1 | 4065 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
f5f7b2fe | 4066 | return; |
1390a28b AK |
4067 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4068 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4069 | return; | |
a9179499 | 4070 | } |
2fb92db1 AK |
4071 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4072 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
4073 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4074 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
03617c18 | 4075 | var->unusable = (ar >> 16) & 1; |
6aa8b732 AK |
4076 | var->type = ar & 15; |
4077 | var->s = (ar >> 4) & 1; | |
4078 | var->dpl = (ar >> 5) & 3; | |
03617c18 GN |
4079 | /* |
4080 | * Some userspaces do not preserve unusable property. Since usable | |
4081 | * segment has to be present according to VMX spec we can use present | |
4082 | * property to amend userspace bug by making unusable segment always | |
4083 | * nonpresent. vmx_segment_access_rights() already marks nonpresent | |
4084 | * segment as unusable. | |
4085 | */ | |
4086 | var->present = !var->unusable; | |
6aa8b732 AK |
4087 | var->avl = (ar >> 12) & 1; |
4088 | var->l = (ar >> 13) & 1; | |
4089 | var->db = (ar >> 14) & 1; | |
4090 | var->g = (ar >> 15) & 1; | |
6aa8b732 AK |
4091 | } |
4092 | ||
a9179499 AK |
4093 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4094 | { | |
a9179499 AK |
4095 | struct kvm_segment s; |
4096 | ||
4097 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
4098 | vmx_get_segment(vcpu, &s, seg); | |
4099 | return s.base; | |
4100 | } | |
2fb92db1 | 4101 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
4102 | } |
4103 | ||
b09408d0 | 4104 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 4105 | { |
b09408d0 MT |
4106 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4107 | ||
ae9fedc7 | 4108 | if (unlikely(vmx->rmode.vm86_active)) |
2e4d2653 | 4109 | return 0; |
ae9fedc7 PB |
4110 | else { |
4111 | int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); | |
4d283ec9 | 4112 | return VMX_AR_DPL(ar); |
69c73028 | 4113 | } |
69c73028 AK |
4114 | } |
4115 | ||
653e3108 | 4116 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 4117 | { |
6aa8b732 AK |
4118 | u32 ar; |
4119 | ||
f0495f9b | 4120 | if (var->unusable || !var->present) |
6aa8b732 AK |
4121 | ar = 1 << 16; |
4122 | else { | |
4123 | ar = var->type & 15; | |
4124 | ar |= (var->s & 1) << 4; | |
4125 | ar |= (var->dpl & 3) << 5; | |
4126 | ar |= (var->present & 1) << 7; | |
4127 | ar |= (var->avl & 1) << 12; | |
4128 | ar |= (var->l & 1) << 13; | |
4129 | ar |= (var->db & 1) << 14; | |
4130 | ar |= (var->g & 1) << 15; | |
4131 | } | |
653e3108 AK |
4132 | |
4133 | return ar; | |
4134 | } | |
4135 | ||
4136 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
4137 | struct kvm_segment *var, int seg) | |
4138 | { | |
7ffd92c5 | 4139 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
772e0318 | 4140 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
653e3108 | 4141 | |
2fb92db1 AK |
4142 | vmx_segment_cache_clear(vmx); |
4143 | ||
1ecd50a9 GN |
4144 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
4145 | vmx->rmode.segs[seg] = *var; | |
4146 | if (seg == VCPU_SREG_TR) | |
4147 | vmcs_write16(sf->selector, var->selector); | |
4148 | else if (var->s) | |
4149 | fix_rmode_seg(seg, &vmx->rmode.segs[seg]); | |
d99e4152 | 4150 | goto out; |
653e3108 | 4151 | } |
1ecd50a9 | 4152 | |
653e3108 AK |
4153 | vmcs_writel(sf->base, var->base); |
4154 | vmcs_write32(sf->limit, var->limit); | |
4155 | vmcs_write16(sf->selector, var->selector); | |
3a624e29 NK |
4156 | |
4157 | /* | |
4158 | * Fix the "Accessed" bit in AR field of segment registers for older | |
4159 | * qemu binaries. | |
4160 | * IA32 arch specifies that at the time of processor reset the | |
4161 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
0fa06071 | 4162 | * is setting it to 0 in the userland code. This causes invalid guest |
3a624e29 NK |
4163 | * state vmexit when "unrestricted guest" mode is turned on. |
4164 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
4165 | * tree. Newer qemu binaries with that qemu fix would not need this | |
4166 | * kvm hack. | |
4167 | */ | |
4168 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
f924d66d | 4169 | var->type |= 0x1; /* Accessed */ |
3a624e29 | 4170 | |
f924d66d | 4171 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); |
d99e4152 GN |
4172 | |
4173 | out: | |
98eb2f8b | 4174 | vmx->emulation_required = emulation_required(vcpu); |
6aa8b732 AK |
4175 | } |
4176 | ||
6aa8b732 AK |
4177 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
4178 | { | |
2fb92db1 | 4179 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
4180 | |
4181 | *db = (ar >> 14) & 1; | |
4182 | *l = (ar >> 13) & 1; | |
4183 | } | |
4184 | ||
89a27f4d | 4185 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4186 | { |
89a27f4d GN |
4187 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
4188 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
4189 | } |
4190 | ||
89a27f4d | 4191 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4192 | { |
89a27f4d GN |
4193 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
4194 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
4195 | } |
4196 | ||
89a27f4d | 4197 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4198 | { |
89a27f4d GN |
4199 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
4200 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
4201 | } |
4202 | ||
89a27f4d | 4203 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4204 | { |
89a27f4d GN |
4205 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
4206 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
4207 | } |
4208 | ||
648dfaa7 MG |
4209 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
4210 | { | |
4211 | struct kvm_segment var; | |
4212 | u32 ar; | |
4213 | ||
4214 | vmx_get_segment(vcpu, &var, seg); | |
07f42f5f | 4215 | var.dpl = 0x3; |
0647f4aa GN |
4216 | if (seg == VCPU_SREG_CS) |
4217 | var.type = 0x3; | |
648dfaa7 MG |
4218 | ar = vmx_segment_access_rights(&var); |
4219 | ||
4220 | if (var.base != (var.selector << 4)) | |
4221 | return false; | |
89efbed0 | 4222 | if (var.limit != 0xffff) |
648dfaa7 | 4223 | return false; |
07f42f5f | 4224 | if (ar != 0xf3) |
648dfaa7 MG |
4225 | return false; |
4226 | ||
4227 | return true; | |
4228 | } | |
4229 | ||
4230 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
4231 | { | |
4232 | struct kvm_segment cs; | |
4233 | unsigned int cs_rpl; | |
4234 | ||
4235 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
b32a9918 | 4236 | cs_rpl = cs.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4237 | |
1872a3f4 AK |
4238 | if (cs.unusable) |
4239 | return false; | |
4d283ec9 | 4240 | if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) |
648dfaa7 MG |
4241 | return false; |
4242 | if (!cs.s) | |
4243 | return false; | |
4d283ec9 | 4244 | if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
4245 | if (cs.dpl > cs_rpl) |
4246 | return false; | |
1872a3f4 | 4247 | } else { |
648dfaa7 MG |
4248 | if (cs.dpl != cs_rpl) |
4249 | return false; | |
4250 | } | |
4251 | if (!cs.present) | |
4252 | return false; | |
4253 | ||
4254 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
4255 | return true; | |
4256 | } | |
4257 | ||
4258 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
4259 | { | |
4260 | struct kvm_segment ss; | |
4261 | unsigned int ss_rpl; | |
4262 | ||
4263 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
b32a9918 | 4264 | ss_rpl = ss.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4265 | |
1872a3f4 AK |
4266 | if (ss.unusable) |
4267 | return true; | |
4268 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
4269 | return false; |
4270 | if (!ss.s) | |
4271 | return false; | |
4272 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
4273 | return false; | |
4274 | if (!ss.present) | |
4275 | return false; | |
4276 | ||
4277 | return true; | |
4278 | } | |
4279 | ||
4280 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
4281 | { | |
4282 | struct kvm_segment var; | |
4283 | unsigned int rpl; | |
4284 | ||
4285 | vmx_get_segment(vcpu, &var, seg); | |
b32a9918 | 4286 | rpl = var.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4287 | |
1872a3f4 AK |
4288 | if (var.unusable) |
4289 | return true; | |
648dfaa7 MG |
4290 | if (!var.s) |
4291 | return false; | |
4292 | if (!var.present) | |
4293 | return false; | |
4d283ec9 | 4294 | if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { |
648dfaa7 MG |
4295 | if (var.dpl < rpl) /* DPL < RPL */ |
4296 | return false; | |
4297 | } | |
4298 | ||
4299 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
4300 | * rights flags | |
4301 | */ | |
4302 | return true; | |
4303 | } | |
4304 | ||
4305 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
4306 | { | |
4307 | struct kvm_segment tr; | |
4308 | ||
4309 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
4310 | ||
1872a3f4 AK |
4311 | if (tr.unusable) |
4312 | return false; | |
b32a9918 | 4313 | if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 | 4314 | return false; |
1872a3f4 | 4315 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
4316 | return false; |
4317 | if (!tr.present) | |
4318 | return false; | |
4319 | ||
4320 | return true; | |
4321 | } | |
4322 | ||
4323 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
4324 | { | |
4325 | struct kvm_segment ldtr; | |
4326 | ||
4327 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
4328 | ||
1872a3f4 AK |
4329 | if (ldtr.unusable) |
4330 | return true; | |
b32a9918 | 4331 | if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 MG |
4332 | return false; |
4333 | if (ldtr.type != 2) | |
4334 | return false; | |
4335 | if (!ldtr.present) | |
4336 | return false; | |
4337 | ||
4338 | return true; | |
4339 | } | |
4340 | ||
4341 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
4342 | { | |
4343 | struct kvm_segment cs, ss; | |
4344 | ||
4345 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
4346 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
4347 | ||
b32a9918 NA |
4348 | return ((cs.selector & SEGMENT_RPL_MASK) == |
4349 | (ss.selector & SEGMENT_RPL_MASK)); | |
648dfaa7 MG |
4350 | } |
4351 | ||
4352 | /* | |
4353 | * Check if guest state is valid. Returns true if valid, false if | |
4354 | * not. | |
4355 | * We assume that registers are always usable | |
4356 | */ | |
4357 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
4358 | { | |
c5e97c80 GN |
4359 | if (enable_unrestricted_guest) |
4360 | return true; | |
4361 | ||
648dfaa7 | 4362 | /* real mode guest state checks */ |
f13882d8 | 4363 | if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { |
648dfaa7 MG |
4364 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
4365 | return false; | |
4366 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
4367 | return false; | |
4368 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
4369 | return false; | |
4370 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
4371 | return false; | |
4372 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
4373 | return false; | |
4374 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
4375 | return false; | |
4376 | } else { | |
4377 | /* protected mode guest state checks */ | |
4378 | if (!cs_ss_rpl_check(vcpu)) | |
4379 | return false; | |
4380 | if (!code_segment_valid(vcpu)) | |
4381 | return false; | |
4382 | if (!stack_segment_valid(vcpu)) | |
4383 | return false; | |
4384 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
4385 | return false; | |
4386 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
4387 | return false; | |
4388 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
4389 | return false; | |
4390 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
4391 | return false; | |
4392 | if (!tr_valid(vcpu)) | |
4393 | return false; | |
4394 | if (!ldtr_valid(vcpu)) | |
4395 | return false; | |
4396 | } | |
4397 | /* TODO: | |
4398 | * - Add checks on RIP | |
4399 | * - Add checks on RFLAGS | |
4400 | */ | |
4401 | ||
4402 | return true; | |
4403 | } | |
4404 | ||
d77c26fc | 4405 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 4406 | { |
40dcaa9f | 4407 | gfn_t fn; |
195aefde | 4408 | u16 data = 0; |
1f755a82 | 4409 | int idx, r; |
6aa8b732 | 4410 | |
40dcaa9f | 4411 | idx = srcu_read_lock(&kvm->srcu); |
4918c6ca | 4412 | fn = kvm->arch.tss_addr >> PAGE_SHIFT; |
195aefde IE |
4413 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4414 | if (r < 0) | |
10589a46 | 4415 | goto out; |
195aefde | 4416 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
4417 | r = kvm_write_guest_page(kvm, fn++, &data, |
4418 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 4419 | if (r < 0) |
10589a46 | 4420 | goto out; |
195aefde IE |
4421 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
4422 | if (r < 0) | |
10589a46 | 4423 | goto out; |
195aefde IE |
4424 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4425 | if (r < 0) | |
10589a46 | 4426 | goto out; |
195aefde | 4427 | data = ~0; |
10589a46 MT |
4428 | r = kvm_write_guest_page(kvm, fn, &data, |
4429 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
4430 | sizeof(u8)); | |
10589a46 | 4431 | out: |
40dcaa9f | 4432 | srcu_read_unlock(&kvm->srcu, idx); |
1f755a82 | 4433 | return r; |
6aa8b732 AK |
4434 | } |
4435 | ||
b7ebfb05 SY |
4436 | static int init_rmode_identity_map(struct kvm *kvm) |
4437 | { | |
f51770ed | 4438 | int i, idx, r = 0; |
ba049e93 | 4439 | kvm_pfn_t identity_map_pfn; |
b7ebfb05 SY |
4440 | u32 tmp; |
4441 | ||
089d034e | 4442 | if (!enable_ept) |
f51770ed | 4443 | return 0; |
a255d479 TC |
4444 | |
4445 | /* Protect kvm->arch.ept_identity_pagetable_done. */ | |
4446 | mutex_lock(&kvm->slots_lock); | |
4447 | ||
f51770ed | 4448 | if (likely(kvm->arch.ept_identity_pagetable_done)) |
a255d479 | 4449 | goto out2; |
a255d479 | 4450 | |
b927a3ce | 4451 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
a255d479 TC |
4452 | |
4453 | r = alloc_identity_pagetable(kvm); | |
f51770ed | 4454 | if (r < 0) |
a255d479 TC |
4455 | goto out2; |
4456 | ||
40dcaa9f | 4457 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
4458 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
4459 | if (r < 0) | |
4460 | goto out; | |
4461 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
4462 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
4463 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
4464 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
4465 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
4466 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
4467 | if (r < 0) | |
4468 | goto out; | |
4469 | } | |
4470 | kvm->arch.ept_identity_pagetable_done = true; | |
f51770ed | 4471 | |
b7ebfb05 | 4472 | out: |
40dcaa9f | 4473 | srcu_read_unlock(&kvm->srcu, idx); |
a255d479 TC |
4474 | |
4475 | out2: | |
4476 | mutex_unlock(&kvm->slots_lock); | |
f51770ed | 4477 | return r; |
b7ebfb05 SY |
4478 | } |
4479 | ||
6aa8b732 AK |
4480 | static void seg_setup(int seg) |
4481 | { | |
772e0318 | 4482 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
3a624e29 | 4483 | unsigned int ar; |
6aa8b732 AK |
4484 | |
4485 | vmcs_write16(sf->selector, 0); | |
4486 | vmcs_writel(sf->base, 0); | |
4487 | vmcs_write32(sf->limit, 0xffff); | |
d54d07b2 GN |
4488 | ar = 0x93; |
4489 | if (seg == VCPU_SREG_CS) | |
4490 | ar |= 0x08; /* code segment */ | |
3a624e29 NK |
4491 | |
4492 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
4493 | } |
4494 | ||
f78e0e2e SY |
4495 | static int alloc_apic_access_page(struct kvm *kvm) |
4496 | { | |
4484141a | 4497 | struct page *page; |
f78e0e2e SY |
4498 | int r = 0; |
4499 | ||
79fac95e | 4500 | mutex_lock(&kvm->slots_lock); |
c24ae0dc | 4501 | if (kvm->arch.apic_access_page_done) |
f78e0e2e | 4502 | goto out; |
1d8007bd PB |
4503 | r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, |
4504 | APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); | |
f78e0e2e SY |
4505 | if (r) |
4506 | goto out; | |
72dc67a6 | 4507 | |
73a6d941 | 4508 | page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
4484141a XG |
4509 | if (is_error_page(page)) { |
4510 | r = -EFAULT; | |
4511 | goto out; | |
4512 | } | |
4513 | ||
c24ae0dc TC |
4514 | /* |
4515 | * Do not pin the page in memory, so that memory hot-unplug | |
4516 | * is able to migrate it. | |
4517 | */ | |
4518 | put_page(page); | |
4519 | kvm->arch.apic_access_page_done = true; | |
f78e0e2e | 4520 | out: |
79fac95e | 4521 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
4522 | return r; |
4523 | } | |
4524 | ||
b7ebfb05 SY |
4525 | static int alloc_identity_pagetable(struct kvm *kvm) |
4526 | { | |
a255d479 TC |
4527 | /* Called with kvm->slots_lock held. */ |
4528 | ||
b7ebfb05 SY |
4529 | int r = 0; |
4530 | ||
a255d479 TC |
4531 | BUG_ON(kvm->arch.ept_identity_pagetable_done); |
4532 | ||
1d8007bd PB |
4533 | r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, |
4534 | kvm->arch.ept_identity_map_addr, PAGE_SIZE); | |
b7ebfb05 | 4535 | |
b7ebfb05 SY |
4536 | return r; |
4537 | } | |
4538 | ||
991e7a0e | 4539 | static int allocate_vpid(void) |
2384d2b3 SY |
4540 | { |
4541 | int vpid; | |
4542 | ||
919818ab | 4543 | if (!enable_vpid) |
991e7a0e | 4544 | return 0; |
2384d2b3 SY |
4545 | spin_lock(&vmx_vpid_lock); |
4546 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
991e7a0e | 4547 | if (vpid < VMX_NR_VPIDS) |
2384d2b3 | 4548 | __set_bit(vpid, vmx_vpid_bitmap); |
991e7a0e WL |
4549 | else |
4550 | vpid = 0; | |
2384d2b3 | 4551 | spin_unlock(&vmx_vpid_lock); |
991e7a0e | 4552 | return vpid; |
2384d2b3 SY |
4553 | } |
4554 | ||
991e7a0e | 4555 | static void free_vpid(int vpid) |
cdbecfc3 | 4556 | { |
991e7a0e | 4557 | if (!enable_vpid || vpid == 0) |
cdbecfc3 LJ |
4558 | return; |
4559 | spin_lock(&vmx_vpid_lock); | |
991e7a0e | 4560 | __clear_bit(vpid, vmx_vpid_bitmap); |
cdbecfc3 LJ |
4561 | spin_unlock(&vmx_vpid_lock); |
4562 | } | |
4563 | ||
8d14695f YZ |
4564 | #define MSR_TYPE_R 1 |
4565 | #define MSR_TYPE_W 2 | |
4566 | static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, | |
4567 | u32 msr, int type) | |
25c5f225 | 4568 | { |
3e7c73e9 | 4569 | int f = sizeof(unsigned long); |
25c5f225 SY |
4570 | |
4571 | if (!cpu_has_vmx_msr_bitmap()) | |
4572 | return; | |
4573 | ||
4574 | /* | |
4575 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4576 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4577 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4578 | */ | |
25c5f225 | 4579 | if (msr <= 0x1fff) { |
8d14695f YZ |
4580 | if (type & MSR_TYPE_R) |
4581 | /* read-low */ | |
4582 | __clear_bit(msr, msr_bitmap + 0x000 / f); | |
4583 | ||
4584 | if (type & MSR_TYPE_W) | |
4585 | /* write-low */ | |
4586 | __clear_bit(msr, msr_bitmap + 0x800 / f); | |
4587 | ||
25c5f225 SY |
4588 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
4589 | msr &= 0x1fff; | |
8d14695f YZ |
4590 | if (type & MSR_TYPE_R) |
4591 | /* read-high */ | |
4592 | __clear_bit(msr, msr_bitmap + 0x400 / f); | |
4593 | ||
4594 | if (type & MSR_TYPE_W) | |
4595 | /* write-high */ | |
4596 | __clear_bit(msr, msr_bitmap + 0xc00 / f); | |
4597 | ||
4598 | } | |
4599 | } | |
4600 | ||
f2b93280 WV |
4601 | /* |
4602 | * If a msr is allowed by L0, we should check whether it is allowed by L1. | |
4603 | * The corresponding bit will be cleared unless both of L0 and L1 allow it. | |
4604 | */ | |
4605 | static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1, | |
4606 | unsigned long *msr_bitmap_nested, | |
4607 | u32 msr, int type) | |
4608 | { | |
4609 | int f = sizeof(unsigned long); | |
4610 | ||
4611 | if (!cpu_has_vmx_msr_bitmap()) { | |
4612 | WARN_ON(1); | |
4613 | return; | |
4614 | } | |
4615 | ||
4616 | /* | |
4617 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4618 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4619 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4620 | */ | |
4621 | if (msr <= 0x1fff) { | |
4622 | if (type & MSR_TYPE_R && | |
4623 | !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) | |
4624 | /* read-low */ | |
4625 | __clear_bit(msr, msr_bitmap_nested + 0x000 / f); | |
4626 | ||
4627 | if (type & MSR_TYPE_W && | |
4628 | !test_bit(msr, msr_bitmap_l1 + 0x800 / f)) | |
4629 | /* write-low */ | |
4630 | __clear_bit(msr, msr_bitmap_nested + 0x800 / f); | |
4631 | ||
4632 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
4633 | msr &= 0x1fff; | |
4634 | if (type & MSR_TYPE_R && | |
4635 | !test_bit(msr, msr_bitmap_l1 + 0x400 / f)) | |
4636 | /* read-high */ | |
4637 | __clear_bit(msr, msr_bitmap_nested + 0x400 / f); | |
4638 | ||
4639 | if (type & MSR_TYPE_W && | |
4640 | !test_bit(msr, msr_bitmap_l1 + 0xc00 / f)) | |
4641 | /* write-high */ | |
4642 | __clear_bit(msr, msr_bitmap_nested + 0xc00 / f); | |
4643 | ||
4644 | } | |
4645 | } | |
4646 | ||
5897297b AK |
4647 | static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) |
4648 | { | |
4649 | if (!longmode_only) | |
8d14695f YZ |
4650 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, |
4651 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
4652 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, | |
4653 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
4654 | } | |
4655 | ||
2e69f865 | 4656 | static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active) |
8d14695f | 4657 | { |
f6e90f9e | 4658 | if (apicv_active) { |
c63e4563 | 4659 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv, |
2e69f865 | 4660 | msr, type); |
c63e4563 | 4661 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv, |
2e69f865 | 4662 | msr, type); |
f6e90f9e | 4663 | } else { |
c63e4563 | 4664 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, |
2e69f865 | 4665 | msr, type); |
c63e4563 | 4666 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, |
2e69f865 | 4667 | msr, type); |
f6e90f9e | 4668 | } |
5897297b AK |
4669 | } |
4670 | ||
d62caabb | 4671 | static bool vmx_get_enable_apicv(void) |
d50ab6c1 | 4672 | { |
d62caabb | 4673 | return enable_apicv; |
d50ab6c1 PB |
4674 | } |
4675 | ||
705699a1 WV |
4676 | static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu) |
4677 | { | |
4678 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4679 | int max_irr; | |
4680 | void *vapic_page; | |
4681 | u16 status; | |
4682 | ||
4683 | if (vmx->nested.pi_desc && | |
4684 | vmx->nested.pi_pending) { | |
4685 | vmx->nested.pi_pending = false; | |
4686 | if (!pi_test_and_clear_on(vmx->nested.pi_desc)) | |
4687 | return 0; | |
4688 | ||
4689 | max_irr = find_last_bit( | |
4690 | (unsigned long *)vmx->nested.pi_desc->pir, 256); | |
4691 | ||
4692 | if (max_irr == 256) | |
4693 | return 0; | |
4694 | ||
4695 | vapic_page = kmap(vmx->nested.virtual_apic_page); | |
4696 | if (!vapic_page) { | |
4697 | WARN_ON(1); | |
4698 | return -ENOMEM; | |
4699 | } | |
4700 | __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page); | |
4701 | kunmap(vmx->nested.virtual_apic_page); | |
4702 | ||
4703 | status = vmcs_read16(GUEST_INTR_STATUS); | |
4704 | if ((u8)max_irr > ((u8)status & 0xff)) { | |
4705 | status &= ~0xff; | |
4706 | status |= (u8)max_irr; | |
4707 | vmcs_write16(GUEST_INTR_STATUS, status); | |
4708 | } | |
4709 | } | |
4710 | return 0; | |
4711 | } | |
4712 | ||
21bc8dc5 RK |
4713 | static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu) |
4714 | { | |
4715 | #ifdef CONFIG_SMP | |
4716 | if (vcpu->mode == IN_GUEST_MODE) { | |
28b835d6 FW |
4717 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4718 | ||
4719 | /* | |
4720 | * Currently, we don't support urgent interrupt, | |
4721 | * all interrupts are recognized as non-urgent | |
4722 | * interrupt, so we cannot post interrupts when | |
4723 | * 'SN' is set. | |
4724 | * | |
4725 | * If the vcpu is in guest mode, it means it is | |
4726 | * running instead of being scheduled out and | |
4727 | * waiting in the run queue, and that's the only | |
4728 | * case when 'SN' is set currently, warning if | |
4729 | * 'SN' is set. | |
4730 | */ | |
4731 | WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc)); | |
4732 | ||
21bc8dc5 RK |
4733 | apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), |
4734 | POSTED_INTR_VECTOR); | |
4735 | return true; | |
4736 | } | |
4737 | #endif | |
4738 | return false; | |
4739 | } | |
4740 | ||
705699a1 WV |
4741 | static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, |
4742 | int vector) | |
4743 | { | |
4744 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4745 | ||
4746 | if (is_guest_mode(vcpu) && | |
4747 | vector == vmx->nested.posted_intr_nv) { | |
4748 | /* the PIR and ON have been set by L1. */ | |
21bc8dc5 | 4749 | kvm_vcpu_trigger_posted_interrupt(vcpu); |
705699a1 WV |
4750 | /* |
4751 | * If a posted intr is not recognized by hardware, | |
4752 | * we will accomplish it in the next vmentry. | |
4753 | */ | |
4754 | vmx->nested.pi_pending = true; | |
4755 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4756 | return 0; | |
4757 | } | |
4758 | return -1; | |
4759 | } | |
a20ed54d YZ |
4760 | /* |
4761 | * Send interrupt to vcpu via posted interrupt way. | |
4762 | * 1. If target vcpu is running(non-root mode), send posted interrupt | |
4763 | * notification to vcpu and hardware will sync PIR to vIRR atomically. | |
4764 | * 2. If target vcpu isn't running(root mode), kick it to pick up the | |
4765 | * interrupt from PIR in next vmentry. | |
4766 | */ | |
4767 | static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) | |
4768 | { | |
4769 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4770 | int r; | |
4771 | ||
705699a1 WV |
4772 | r = vmx_deliver_nested_posted_interrupt(vcpu, vector); |
4773 | if (!r) | |
4774 | return; | |
4775 | ||
a20ed54d YZ |
4776 | if (pi_test_and_set_pir(vector, &vmx->pi_desc)) |
4777 | return; | |
4778 | ||
4779 | r = pi_test_and_set_on(&vmx->pi_desc); | |
4780 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
21bc8dc5 | 4781 | if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu)) |
a20ed54d YZ |
4782 | kvm_vcpu_kick(vcpu); |
4783 | } | |
4784 | ||
4785 | static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) | |
4786 | { | |
4787 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4788 | ||
ad361091 | 4789 | if (!pi_test_on(&vmx->pi_desc)) |
a20ed54d YZ |
4790 | return; |
4791 | ||
ad361091 PB |
4792 | pi_clear_on(&vmx->pi_desc); |
4793 | /* | |
4794 | * IOMMU can write to PIR.ON, so the barrier matters even on UP. | |
4795 | * But on x86 this is just a compiler barrier anyway. | |
4796 | */ | |
4797 | smp_mb__after_atomic(); | |
a20ed54d YZ |
4798 | kvm_apic_update_irr(vcpu, vmx->pi_desc.pir); |
4799 | } | |
4800 | ||
a3a8ff8e NHE |
4801 | /* |
4802 | * Set up the vmcs's constant host-state fields, i.e., host-state fields that | |
4803 | * will not change in the lifetime of the guest. | |
4804 | * Note that host-state that does change is set elsewhere. E.g., host-state | |
4805 | * that is set differently for each CPU is set in vmx_vcpu_load(), not here. | |
4806 | */ | |
a547c6db | 4807 | static void vmx_set_constant_host_state(struct vcpu_vmx *vmx) |
a3a8ff8e NHE |
4808 | { |
4809 | u32 low32, high32; | |
4810 | unsigned long tmpl; | |
4811 | struct desc_ptr dt; | |
d974baa3 | 4812 | unsigned long cr4; |
a3a8ff8e | 4813 | |
b1a74bf8 | 4814 | vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */ |
a3a8ff8e NHE |
4815 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ |
4816 | ||
d974baa3 | 4817 | /* Save the most likely value for this task's CR4 in the VMCS. */ |
1e02ce4c | 4818 | cr4 = cr4_read_shadow(); |
d974baa3 AL |
4819 | vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ |
4820 | vmx->host_state.vmcs_host_cr4 = cr4; | |
4821 | ||
a3a8ff8e | 4822 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ |
b2da15ac AK |
4823 | #ifdef CONFIG_X86_64 |
4824 | /* | |
4825 | * Load null selectors, so we can avoid reloading them in | |
4826 | * __vmx_load_host_state(), in case userspace uses the null selectors | |
4827 | * too (the expected case). | |
4828 | */ | |
4829 | vmcs_write16(HOST_DS_SELECTOR, 0); | |
4830 | vmcs_write16(HOST_ES_SELECTOR, 0); | |
4831 | #else | |
a3a8ff8e NHE |
4832 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
4833 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
b2da15ac | 4834 | #endif |
a3a8ff8e NHE |
4835 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
4836 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
4837 | ||
4838 | native_store_idt(&dt); | |
4839 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ | |
a547c6db | 4840 | vmx->host_idt_base = dt.address; |
a3a8ff8e | 4841 | |
83287ea4 | 4842 | vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */ |
a3a8ff8e NHE |
4843 | |
4844 | rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); | |
4845 | vmcs_write32(HOST_IA32_SYSENTER_CS, low32); | |
4846 | rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); | |
4847 | vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ | |
4848 | ||
4849 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { | |
4850 | rdmsr(MSR_IA32_CR_PAT, low32, high32); | |
4851 | vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); | |
4852 | } | |
4853 | } | |
4854 | ||
bf8179a0 NHE |
4855 | static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) |
4856 | { | |
4857 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; | |
4858 | if (enable_ept) | |
4859 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
fe3ef05c NHE |
4860 | if (is_guest_mode(&vmx->vcpu)) |
4861 | vmx->vcpu.arch.cr4_guest_owned_bits &= | |
4862 | ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; | |
bf8179a0 NHE |
4863 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
4864 | } | |
4865 | ||
01e439be YZ |
4866 | static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) |
4867 | { | |
4868 | u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; | |
4869 | ||
d62caabb | 4870 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
01e439be | 4871 | pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; |
64672c95 YJ |
4872 | /* Enable the preemption timer dynamically */ |
4873 | pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
4874 | return pin_based_exec_ctrl; |
4875 | } | |
4876 | ||
d62caabb AS |
4877 | static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
4878 | { | |
4879 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4880 | ||
4881 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); | |
3ce424e4 RK |
4882 | if (cpu_has_secondary_exec_ctrls()) { |
4883 | if (kvm_vcpu_apicv_active(vcpu)) | |
4884 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
4885 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
4886 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
4887 | else | |
4888 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
4889 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
4890 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
4891 | } | |
4892 | ||
4893 | if (cpu_has_vmx_msr_bitmap()) | |
4894 | vmx_set_msr_bitmap(vcpu); | |
d62caabb AS |
4895 | } |
4896 | ||
bf8179a0 NHE |
4897 | static u32 vmx_exec_control(struct vcpu_vmx *vmx) |
4898 | { | |
4899 | u32 exec_control = vmcs_config.cpu_based_exec_ctrl; | |
d16c293e PB |
4900 | |
4901 | if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) | |
4902 | exec_control &= ~CPU_BASED_MOV_DR_EXITING; | |
4903 | ||
35754c98 | 4904 | if (!cpu_need_tpr_shadow(&vmx->vcpu)) { |
bf8179a0 NHE |
4905 | exec_control &= ~CPU_BASED_TPR_SHADOW; |
4906 | #ifdef CONFIG_X86_64 | |
4907 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
4908 | CPU_BASED_CR8_LOAD_EXITING; | |
4909 | #endif | |
4910 | } | |
4911 | if (!enable_ept) | |
4912 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
4913 | CPU_BASED_CR3_LOAD_EXITING | | |
4914 | CPU_BASED_INVLPG_EXITING; | |
4915 | return exec_control; | |
4916 | } | |
4917 | ||
4918 | static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx) | |
4919 | { | |
4920 | u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
35754c98 | 4921 | if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu)) |
bf8179a0 NHE |
4922 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
4923 | if (vmx->vpid == 0) | |
4924 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
4925 | if (!enable_ept) { | |
4926 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
4927 | enable_unrestricted_guest = 0; | |
ad756a16 MJ |
4928 | /* Enable INVPCID for non-ept guests may cause performance regression. */ |
4929 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
bf8179a0 NHE |
4930 | } |
4931 | if (!enable_unrestricted_guest) | |
4932 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
4933 | if (!ple_gap) | |
4934 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
d62caabb | 4935 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
c7c9c56c YZ |
4936 | exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | |
4937 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
8d14695f | 4938 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; |
abc4fc58 AG |
4939 | /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD |
4940 | (handle_vmptrld). | |
4941 | We can NOT enable shadow_vmcs here because we don't have yet | |
4942 | a current VMCS12 | |
4943 | */ | |
4944 | exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
a3eaa864 KH |
4945 | |
4946 | if (!enable_pml) | |
4947 | exec_control &= ~SECONDARY_EXEC_ENABLE_PML; | |
843e4330 | 4948 | |
bf8179a0 NHE |
4949 | return exec_control; |
4950 | } | |
4951 | ||
ce88decf XG |
4952 | static void ept_set_mmio_spte_mask(void) |
4953 | { | |
4954 | /* | |
4955 | * EPT Misconfigurations can be generated if the value of bits 2:0 | |
4956 | * of an EPT paging-structure entry is 110b (write/execute). | |
885032b9 | 4957 | * Also, magic bits (0x3ull << 62) is set to quickly identify mmio |
ce88decf XG |
4958 | * spte. |
4959 | */ | |
885032b9 | 4960 | kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull); |
ce88decf XG |
4961 | } |
4962 | ||
f53cd63c | 4963 | #define VMX_XSS_EXIT_BITMAP 0 |
6aa8b732 AK |
4964 | /* |
4965 | * Sets up the vmcs for emulated real mode. | |
4966 | */ | |
8b9cf98c | 4967 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 4968 | { |
2e4ce7f5 | 4969 | #ifdef CONFIG_X86_64 |
6aa8b732 | 4970 | unsigned long a; |
2e4ce7f5 | 4971 | #endif |
6aa8b732 | 4972 | int i; |
6aa8b732 | 4973 | |
6aa8b732 | 4974 | /* I/O */ |
3e7c73e9 AK |
4975 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
4976 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 4977 | |
4607c2d7 AG |
4978 | if (enable_shadow_vmcs) { |
4979 | vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); | |
4980 | vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); | |
4981 | } | |
25c5f225 | 4982 | if (cpu_has_vmx_msr_bitmap()) |
5897297b | 4983 | vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy)); |
25c5f225 | 4984 | |
6aa8b732 AK |
4985 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
4986 | ||
6aa8b732 | 4987 | /* Control */ |
01e439be | 4988 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); |
64672c95 | 4989 | vmx->hv_deadline_tsc = -1; |
6e5d865c | 4990 | |
bf8179a0 | 4991 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx)); |
6aa8b732 | 4992 | |
dfa169bb | 4993 | if (cpu_has_secondary_exec_ctrls()) { |
bf8179a0 NHE |
4994 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, |
4995 | vmx_secondary_exec_control(vmx)); | |
dfa169bb | 4996 | } |
f78e0e2e | 4997 | |
d62caabb | 4998 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) { |
c7c9c56c YZ |
4999 | vmcs_write64(EOI_EXIT_BITMAP0, 0); |
5000 | vmcs_write64(EOI_EXIT_BITMAP1, 0); | |
5001 | vmcs_write64(EOI_EXIT_BITMAP2, 0); | |
5002 | vmcs_write64(EOI_EXIT_BITMAP3, 0); | |
5003 | ||
5004 | vmcs_write16(GUEST_INTR_STATUS, 0); | |
01e439be | 5005 | |
0bcf261c | 5006 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
01e439be | 5007 | vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); |
c7c9c56c YZ |
5008 | } |
5009 | ||
4b8d54f9 ZE |
5010 | if (ple_gap) { |
5011 | vmcs_write32(PLE_GAP, ple_gap); | |
a7653ecd RK |
5012 | vmx->ple_window = ple_window; |
5013 | vmx->ple_window_dirty = true; | |
4b8d54f9 ZE |
5014 | } |
5015 | ||
c3707958 XG |
5016 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
5017 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
6aa8b732 AK |
5018 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
5019 | ||
9581d442 AK |
5020 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
5021 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
a547c6db | 5022 | vmx_set_constant_host_state(vmx); |
05b3e0c2 | 5023 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
5024 | rdmsrl(MSR_FS_BASE, a); |
5025 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
5026 | rdmsrl(MSR_GS_BASE, a); | |
5027 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
5028 | #else | |
5029 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
5030 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
5031 | #endif | |
5032 | ||
2cc51560 ED |
5033 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
5034 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
61d2ef2c | 5035 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); |
2cc51560 | 5036 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
61d2ef2c | 5037 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); |
6aa8b732 | 5038 | |
74545705 RK |
5039 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) |
5040 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); | |
468d472f | 5041 | |
03916db9 | 5042 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { |
6aa8b732 AK |
5043 | u32 index = vmx_msr_index[i]; |
5044 | u32 data_low, data_high; | |
a2fa3e9f | 5045 | int j = vmx->nmsrs; |
6aa8b732 AK |
5046 | |
5047 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
5048 | continue; | |
432bd6cb AK |
5049 | if (wrmsr_safe(index, data_low, data_high) < 0) |
5050 | continue; | |
26bb0981 AK |
5051 | vmx->guest_msrs[j].index = i; |
5052 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 5053 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 5054 | ++vmx->nmsrs; |
6aa8b732 | 5055 | } |
6aa8b732 | 5056 | |
2961e876 GN |
5057 | |
5058 | vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl); | |
6aa8b732 AK |
5059 | |
5060 | /* 22.2.1, 20.8.1 */ | |
2961e876 | 5061 | vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl); |
1c3d14fe | 5062 | |
e00c8cf2 | 5063 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
bf8179a0 | 5064 | set_cr4_guest_host_mask(vmx); |
e00c8cf2 | 5065 | |
f53cd63c WL |
5066 | if (vmx_xsaves_supported()) |
5067 | vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); | |
5068 | ||
4e59516a PF |
5069 | if (enable_pml) { |
5070 | ASSERT(vmx->pml_pg); | |
5071 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
5072 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
5073 | } | |
5074 | ||
e00c8cf2 AK |
5075 | return 0; |
5076 | } | |
5077 | ||
d28bc9dd | 5078 | static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e00c8cf2 AK |
5079 | { |
5080 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
58cb628d | 5081 | struct msr_data apic_base_msr; |
d28bc9dd | 5082 | u64 cr0; |
e00c8cf2 | 5083 | |
7ffd92c5 | 5084 | vmx->rmode.vm86_active = 0; |
e00c8cf2 | 5085 | |
3b86cd99 JK |
5086 | vmx->soft_vnmi_blocked = 0; |
5087 | ||
ad312c7c | 5088 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
d28bc9dd NA |
5089 | kvm_set_cr8(vcpu, 0); |
5090 | ||
5091 | if (!init_event) { | |
5092 | apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | | |
5093 | MSR_IA32_APICBASE_ENABLE; | |
5094 | if (kvm_vcpu_is_reset_bsp(vcpu)) | |
5095 | apic_base_msr.data |= MSR_IA32_APICBASE_BSP; | |
5096 | apic_base_msr.host_initiated = true; | |
5097 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
5098 | } | |
e00c8cf2 | 5099 | |
2fb92db1 AK |
5100 | vmx_segment_cache_clear(vmx); |
5101 | ||
5706be0d | 5102 | seg_setup(VCPU_SREG_CS); |
66450a21 | 5103 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
f3531054 | 5104 | vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); |
e00c8cf2 AK |
5105 | |
5106 | seg_setup(VCPU_SREG_DS); | |
5107 | seg_setup(VCPU_SREG_ES); | |
5108 | seg_setup(VCPU_SREG_FS); | |
5109 | seg_setup(VCPU_SREG_GS); | |
5110 | seg_setup(VCPU_SREG_SS); | |
5111 | ||
5112 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
5113 | vmcs_writel(GUEST_TR_BASE, 0); | |
5114 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
5115 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
5116 | ||
5117 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
5118 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
5119 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
5120 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
5121 | ||
d28bc9dd NA |
5122 | if (!init_event) { |
5123 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
5124 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
5125 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
5126 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
5127 | } | |
e00c8cf2 AK |
5128 | |
5129 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
66450a21 | 5130 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 5131 | |
e00c8cf2 AK |
5132 | vmcs_writel(GUEST_GDTR_BASE, 0); |
5133 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
5134 | ||
5135 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
5136 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
5137 | ||
443381a8 | 5138 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 | 5139 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
f3531054 | 5140 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); |
e00c8cf2 | 5141 | |
e00c8cf2 AK |
5142 | setup_msrs(vmx); |
5143 | ||
6aa8b732 AK |
5144 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
5145 | ||
d28bc9dd | 5146 | if (cpu_has_vmx_tpr_shadow() && !init_event) { |
f78e0e2e | 5147 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); |
35754c98 | 5148 | if (cpu_need_tpr_shadow(vcpu)) |
f78e0e2e | 5149 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, |
d28bc9dd | 5150 | __pa(vcpu->arch.apic->regs)); |
f78e0e2e SY |
5151 | vmcs_write32(TPR_THRESHOLD, 0); |
5152 | } | |
5153 | ||
a73896cb | 5154 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
6aa8b732 | 5155 | |
d62caabb | 5156 | if (kvm_vcpu_apicv_active(vcpu)) |
01e439be YZ |
5157 | memset(&vmx->pi_desc, 0, sizeof(struct pi_desc)); |
5158 | ||
2384d2b3 SY |
5159 | if (vmx->vpid != 0) |
5160 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
5161 | ||
d28bc9dd | 5162 | cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
d28bc9dd | 5163 | vmx->vcpu.arch.cr0 = cr0; |
f2463247 | 5164 | vmx_set_cr0(vcpu, cr0); /* enter rmode */ |
d28bc9dd | 5165 | vmx_set_cr4(vcpu, 0); |
5690891b | 5166 | vmx_set_efer(vcpu, 0); |
d28bc9dd NA |
5167 | vmx_fpu_activate(vcpu); |
5168 | update_exception_bitmap(vcpu); | |
6aa8b732 | 5169 | |
dd5f5341 | 5170 | vpid_sync_context(vmx->vpid); |
6aa8b732 AK |
5171 | } |
5172 | ||
b6f1250e NHE |
5173 | /* |
5174 | * In nested virtualization, check if L1 asked to exit on external interrupts. | |
5175 | * For most existing hypervisors, this will always return true. | |
5176 | */ | |
5177 | static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) | |
5178 | { | |
5179 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5180 | PIN_BASED_EXT_INTR_MASK; | |
5181 | } | |
5182 | ||
77b0f5d6 BD |
5183 | /* |
5184 | * In nested virtualization, check if L1 has set | |
5185 | * VM_EXIT_ACK_INTR_ON_EXIT | |
5186 | */ | |
5187 | static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) | |
5188 | { | |
5189 | return get_vmcs12(vcpu)->vm_exit_controls & | |
5190 | VM_EXIT_ACK_INTR_ON_EXIT; | |
5191 | } | |
5192 | ||
ea8ceb83 JK |
5193 | static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) |
5194 | { | |
5195 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5196 | PIN_BASED_NMI_EXITING; | |
5197 | } | |
5198 | ||
c9a7953f | 5199 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3b86cd99 JK |
5200 | { |
5201 | u32 cpu_based_vm_exec_control; | |
730dca42 | 5202 | |
3b86cd99 JK |
5203 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); |
5204 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
5205 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
5206 | } | |
5207 | ||
c9a7953f | 5208 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
3b86cd99 JK |
5209 | { |
5210 | u32 cpu_based_vm_exec_control; | |
5211 | ||
c9a7953f JK |
5212 | if (!cpu_has_virtual_nmis() || |
5213 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { | |
5214 | enable_irq_window(vcpu); | |
5215 | return; | |
5216 | } | |
3b86cd99 JK |
5217 | |
5218 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
5219 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
5220 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
5221 | } | |
5222 | ||
66fd3f7f | 5223 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 5224 | { |
9c8cba37 | 5225 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
5226 | uint32_t intr; |
5227 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 5228 | |
229456fc | 5229 | trace_kvm_inj_virq(irq); |
2714d1d3 | 5230 | |
fa89a817 | 5231 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 5232 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
5233 | int inc_eip = 0; |
5234 | if (vcpu->arch.interrupt.soft) | |
5235 | inc_eip = vcpu->arch.event_exit_inst_len; | |
5236 | if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) | |
a92601bb | 5237 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
85f455f7 ED |
5238 | return; |
5239 | } | |
66fd3f7f GN |
5240 | intr = irq | INTR_INFO_VALID_MASK; |
5241 | if (vcpu->arch.interrupt.soft) { | |
5242 | intr |= INTR_TYPE_SOFT_INTR; | |
5243 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
5244 | vmx->vcpu.arch.event_exit_inst_len); | |
5245 | } else | |
5246 | intr |= INTR_TYPE_EXT_INTR; | |
5247 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
85f455f7 ED |
5248 | } |
5249 | ||
f08864b4 SY |
5250 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
5251 | { | |
66a5a347 JK |
5252 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5253 | ||
c5a6d5f7 WL |
5254 | if (!is_guest_mode(vcpu)) { |
5255 | if (!cpu_has_virtual_nmis()) { | |
5256 | /* | |
5257 | * Tracking the NMI-blocked state in software is built upon | |
5258 | * finding the next open IRQ window. This, in turn, depends on | |
5259 | * well-behaving guests: They have to keep IRQs disabled at | |
5260 | * least as long as the NMI handler runs. Otherwise we may | |
5261 | * cause NMI nesting, maybe breaking the guest. But as this is | |
5262 | * highly unlikely, we can live with the residual risk. | |
5263 | */ | |
5264 | vmx->soft_vnmi_blocked = 1; | |
5265 | vmx->vnmi_blocked_time = 0; | |
5266 | } | |
0b6ac343 | 5267 | |
c5a6d5f7 WL |
5268 | ++vcpu->stat.nmi_injections; |
5269 | vmx->nmi_known_unmasked = false; | |
3b86cd99 JK |
5270 | } |
5271 | ||
7ffd92c5 | 5272 | if (vmx->rmode.vm86_active) { |
71f9833b | 5273 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) |
a92601bb | 5274 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
66a5a347 JK |
5275 | return; |
5276 | } | |
c5a6d5f7 | 5277 | |
f08864b4 SY |
5278 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
5279 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
5280 | } |
5281 | ||
3cfc3092 JK |
5282 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
5283 | { | |
5284 | if (!cpu_has_virtual_nmis()) | |
5285 | return to_vmx(vcpu)->soft_vnmi_blocked; | |
9d58b931 AK |
5286 | if (to_vmx(vcpu)->nmi_known_unmasked) |
5287 | return false; | |
c332c83a | 5288 | return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
3cfc3092 JK |
5289 | } |
5290 | ||
5291 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
5292 | { | |
5293 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5294 | ||
5295 | if (!cpu_has_virtual_nmis()) { | |
5296 | if (vmx->soft_vnmi_blocked != masked) { | |
5297 | vmx->soft_vnmi_blocked = masked; | |
5298 | vmx->vnmi_blocked_time = 0; | |
5299 | } | |
5300 | } else { | |
9d58b931 | 5301 | vmx->nmi_known_unmasked = !masked; |
3cfc3092 JK |
5302 | if (masked) |
5303 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5304 | GUEST_INTR_STATE_NMI); | |
5305 | else | |
5306 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5307 | GUEST_INTR_STATE_NMI); | |
5308 | } | |
5309 | } | |
5310 | ||
2505dc9f JK |
5311 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
5312 | { | |
b6b8a145 JK |
5313 | if (to_vmx(vcpu)->nested.nested_run_pending) |
5314 | return 0; | |
ea8ceb83 | 5315 | |
2505dc9f JK |
5316 | if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked) |
5317 | return 0; | |
5318 | ||
5319 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & | |
5320 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | |
5321 | | GUEST_INTR_STATE_NMI)); | |
5322 | } | |
5323 | ||
78646121 GN |
5324 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
5325 | { | |
b6b8a145 JK |
5326 | return (!to_vmx(vcpu)->nested.nested_run_pending && |
5327 | vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
c4282df9 GN |
5328 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
5329 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
5330 | } |
5331 | ||
cbc94022 IE |
5332 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
5333 | { | |
5334 | int ret; | |
cbc94022 | 5335 | |
1d8007bd PB |
5336 | ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, |
5337 | PAGE_SIZE * 3); | |
cbc94022 IE |
5338 | if (ret) |
5339 | return ret; | |
bfc6d222 | 5340 | kvm->arch.tss_addr = addr; |
1f755a82 | 5341 | return init_rmode_tss(kvm); |
cbc94022 IE |
5342 | } |
5343 | ||
0ca1b4f4 | 5344 | static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) |
6aa8b732 | 5345 | { |
77ab6db0 | 5346 | switch (vec) { |
77ab6db0 | 5347 | case BP_VECTOR: |
c573cd22 JK |
5348 | /* |
5349 | * Update instruction length as we may reinject the exception | |
5350 | * from user space while in guest debugging mode. | |
5351 | */ | |
5352 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
5353 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 | 5354 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
0ca1b4f4 GN |
5355 | return false; |
5356 | /* fall through */ | |
5357 | case DB_VECTOR: | |
5358 | if (vcpu->guest_debug & | |
5359 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
5360 | return false; | |
d0bfb940 JK |
5361 | /* fall through */ |
5362 | case DE_VECTOR: | |
77ab6db0 JK |
5363 | case OF_VECTOR: |
5364 | case BR_VECTOR: | |
5365 | case UD_VECTOR: | |
5366 | case DF_VECTOR: | |
5367 | case SS_VECTOR: | |
5368 | case GP_VECTOR: | |
5369 | case MF_VECTOR: | |
0ca1b4f4 GN |
5370 | return true; |
5371 | break; | |
77ab6db0 | 5372 | } |
0ca1b4f4 GN |
5373 | return false; |
5374 | } | |
5375 | ||
5376 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
5377 | int vec, u32 err_code) | |
5378 | { | |
5379 | /* | |
5380 | * Instruction with address size override prefix opcode 0x67 | |
5381 | * Cause the #SS fault with 0 error code in VM86 mode. | |
5382 | */ | |
5383 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { | |
5384 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) { | |
5385 | if (vcpu->arch.halt_request) { | |
5386 | vcpu->arch.halt_request = 0; | |
5cb56059 | 5387 | return kvm_vcpu_halt(vcpu); |
0ca1b4f4 GN |
5388 | } |
5389 | return 1; | |
5390 | } | |
5391 | return 0; | |
5392 | } | |
5393 | ||
5394 | /* | |
5395 | * Forward all other exceptions that are valid in real mode. | |
5396 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
5397 | * the required debugging infrastructure rework. | |
5398 | */ | |
5399 | kvm_queue_exception(vcpu, vec); | |
5400 | return 1; | |
6aa8b732 AK |
5401 | } |
5402 | ||
a0861c02 AK |
5403 | /* |
5404 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
5405 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
5406 | * We pass a fake environment to the machine check handler because we want | |
5407 | * the guest to be always treated like user space, no matter what context | |
5408 | * it used internally. | |
5409 | */ | |
5410 | static void kvm_machine_check(void) | |
5411 | { | |
5412 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
5413 | struct pt_regs regs = { | |
5414 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
5415 | .flags = X86_EFLAGS_IF, | |
5416 | }; | |
5417 | ||
5418 | do_machine_check(®s, 0); | |
5419 | #endif | |
5420 | } | |
5421 | ||
851ba692 | 5422 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
5423 | { |
5424 | /* already handled by vcpu_run */ | |
5425 | return 1; | |
5426 | } | |
5427 | ||
851ba692 | 5428 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 5429 | { |
1155f76a | 5430 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 5431 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 5432 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 5433 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
5434 | u32 vect_info; |
5435 | enum emulation_result er; | |
5436 | ||
1155f76a | 5437 | vect_info = vmx->idt_vectoring_info; |
88786475 | 5438 | intr_info = vmx->exit_intr_info; |
6aa8b732 | 5439 | |
a0861c02 | 5440 | if (is_machine_check(intr_info)) |
851ba692 | 5441 | return handle_machine_check(vcpu); |
a0861c02 | 5442 | |
e4a41889 | 5443 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR) |
1b6269db | 5444 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc AL |
5445 | |
5446 | if (is_no_device(intr_info)) { | |
5fd86fcf | 5447 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
5448 | return 1; |
5449 | } | |
5450 | ||
7aa81cc0 | 5451 | if (is_invalid_opcode(intr_info)) { |
ae1f5767 JK |
5452 | if (is_guest_mode(vcpu)) { |
5453 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5454 | return 1; | |
5455 | } | |
51d8b661 | 5456 | er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 5457 | if (er != EMULATE_DONE) |
7ee5d940 | 5458 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
5459 | return 1; |
5460 | } | |
5461 | ||
6aa8b732 | 5462 | error_code = 0; |
2e11384c | 5463 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 | 5464 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
bf4ca23e XG |
5465 | |
5466 | /* | |
5467 | * The #PF with PFEC.RSVD = 1 indicates the guest is accessing | |
5468 | * MMIO, it is better to report an internal error. | |
5469 | * See the comments in vmx_handle_exit. | |
5470 | */ | |
5471 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
5472 | !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { | |
5473 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
5474 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
80f0e95d | 5475 | vcpu->run->internal.ndata = 3; |
bf4ca23e XG |
5476 | vcpu->run->internal.data[0] = vect_info; |
5477 | vcpu->run->internal.data[1] = intr_info; | |
80f0e95d | 5478 | vcpu->run->internal.data[2] = error_code; |
bf4ca23e XG |
5479 | return 0; |
5480 | } | |
5481 | ||
6aa8b732 | 5482 | if (is_page_fault(intr_info)) { |
1439442c | 5483 | /* EPT won't cause page fault directly */ |
cf3ace79 | 5484 | BUG_ON(enable_ept); |
6aa8b732 | 5485 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
229456fc MT |
5486 | trace_kvm_page_fault(cr2, error_code); |
5487 | ||
3298b75c | 5488 | if (kvm_event_needs_reinjection(vcpu)) |
577bdc49 | 5489 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
dc25e89e | 5490 | return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0); |
6aa8b732 AK |
5491 | } |
5492 | ||
d0bfb940 | 5493 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
0ca1b4f4 GN |
5494 | |
5495 | if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) | |
5496 | return handle_rmode_exception(vcpu, ex_no, error_code); | |
5497 | ||
42dbaa5a | 5498 | switch (ex_no) { |
54a20552 EN |
5499 | case AC_VECTOR: |
5500 | kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); | |
5501 | return 1; | |
42dbaa5a JK |
5502 | case DB_VECTOR: |
5503 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
5504 | if (!(vcpu->guest_debug & | |
5505 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
8246bf52 | 5506 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 5507 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
fd2a445a HD |
5508 | if (!(dr6 & ~DR6_RESERVED)) /* icebp */ |
5509 | skip_emulated_instruction(vcpu); | |
5510 | ||
42dbaa5a JK |
5511 | kvm_queue_exception(vcpu, DB_VECTOR); |
5512 | return 1; | |
5513 | } | |
5514 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
5515 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
5516 | /* fall through */ | |
5517 | case BP_VECTOR: | |
c573cd22 JK |
5518 | /* |
5519 | * Update instruction length as we may reinject #BP from | |
5520 | * user space while in guest debugging mode. Reading it for | |
5521 | * #DB as well causes no harm, it is not used in that case. | |
5522 | */ | |
5523 | vmx->vcpu.arch.event_exit_inst_len = | |
5524 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 5525 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 5526 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
5527 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
5528 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
5529 | break; |
5530 | default: | |
d0bfb940 JK |
5531 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
5532 | kvm_run->ex.exception = ex_no; | |
5533 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 5534 | break; |
6aa8b732 | 5535 | } |
6aa8b732 AK |
5536 | return 0; |
5537 | } | |
5538 | ||
851ba692 | 5539 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 5540 | { |
1165f5fe | 5541 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
5542 | return 1; |
5543 | } | |
5544 | ||
851ba692 | 5545 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 5546 | { |
851ba692 | 5547 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
988ad74f AK |
5548 | return 0; |
5549 | } | |
6aa8b732 | 5550 | |
851ba692 | 5551 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 5552 | { |
bfdaab09 | 5553 | unsigned long exit_qualification; |
34c33d16 | 5554 | int size, in, string; |
039576c0 | 5555 | unsigned port; |
6aa8b732 | 5556 | |
bfdaab09 | 5557 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 5558 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 5559 | in = (exit_qualification & 8) != 0; |
e70669ab | 5560 | |
cf8f70bf | 5561 | ++vcpu->stat.io_exits; |
e70669ab | 5562 | |
cf8f70bf | 5563 | if (string || in) |
51d8b661 | 5564 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 5565 | |
cf8f70bf GN |
5566 | port = exit_qualification >> 16; |
5567 | size = (exit_qualification & 7) + 1; | |
e93f36bc | 5568 | skip_emulated_instruction(vcpu); |
cf8f70bf GN |
5569 | |
5570 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
5571 | } |
5572 | ||
102d8325 IM |
5573 | static void |
5574 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
5575 | { | |
5576 | /* | |
5577 | * Patch in the VMCALL instruction: | |
5578 | */ | |
5579 | hypercall[0] = 0x0f; | |
5580 | hypercall[1] = 0x01; | |
5581 | hypercall[2] = 0xc1; | |
102d8325 IM |
5582 | } |
5583 | ||
b9c237bb | 5584 | static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) |
92fbc7b1 JK |
5585 | { |
5586 | unsigned long always_on = VMXON_CR0_ALWAYSON; | |
b9c237bb | 5587 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
92fbc7b1 | 5588 | |
b9c237bb | 5589 | if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high & |
92fbc7b1 JK |
5590 | SECONDARY_EXEC_UNRESTRICTED_GUEST && |
5591 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) | |
5592 | always_on &= ~(X86_CR0_PE | X86_CR0_PG); | |
5593 | return (val & always_on) == always_on; | |
5594 | } | |
5595 | ||
0fa06071 | 5596 | /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ |
eeadf9e7 NHE |
5597 | static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) |
5598 | { | |
eeadf9e7 | 5599 | if (is_guest_mode(vcpu)) { |
1a0d74e6 JK |
5600 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
5601 | unsigned long orig_val = val; | |
5602 | ||
eeadf9e7 NHE |
5603 | /* |
5604 | * We get here when L2 changed cr0 in a way that did not change | |
5605 | * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), | |
1a0d74e6 JK |
5606 | * but did change L0 shadowed bits. So we first calculate the |
5607 | * effective cr0 value that L1 would like to write into the | |
5608 | * hardware. It consists of the L2-owned bits from the new | |
5609 | * value combined with the L1-owned bits from L1's guest_cr0. | |
eeadf9e7 | 5610 | */ |
1a0d74e6 JK |
5611 | val = (val & ~vmcs12->cr0_guest_host_mask) | |
5612 | (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); | |
5613 | ||
b9c237bb | 5614 | if (!nested_cr0_valid(vcpu, val)) |
eeadf9e7 | 5615 | return 1; |
1a0d74e6 JK |
5616 | |
5617 | if (kvm_set_cr0(vcpu, val)) | |
5618 | return 1; | |
5619 | vmcs_writel(CR0_READ_SHADOW, orig_val); | |
eeadf9e7 | 5620 | return 0; |
1a0d74e6 JK |
5621 | } else { |
5622 | if (to_vmx(vcpu)->nested.vmxon && | |
5623 | ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)) | |
5624 | return 1; | |
eeadf9e7 | 5625 | return kvm_set_cr0(vcpu, val); |
1a0d74e6 | 5626 | } |
eeadf9e7 NHE |
5627 | } |
5628 | ||
5629 | static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) | |
5630 | { | |
5631 | if (is_guest_mode(vcpu)) { | |
1a0d74e6 JK |
5632 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
5633 | unsigned long orig_val = val; | |
5634 | ||
5635 | /* analogously to handle_set_cr0 */ | |
5636 | val = (val & ~vmcs12->cr4_guest_host_mask) | | |
5637 | (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); | |
5638 | if (kvm_set_cr4(vcpu, val)) | |
eeadf9e7 | 5639 | return 1; |
1a0d74e6 | 5640 | vmcs_writel(CR4_READ_SHADOW, orig_val); |
eeadf9e7 NHE |
5641 | return 0; |
5642 | } else | |
5643 | return kvm_set_cr4(vcpu, val); | |
5644 | } | |
5645 | ||
6a6256f9 | 5646 | /* called to set cr0 as appropriate for clts instruction exit. */ |
eeadf9e7 NHE |
5647 | static void handle_clts(struct kvm_vcpu *vcpu) |
5648 | { | |
5649 | if (is_guest_mode(vcpu)) { | |
5650 | /* | |
5651 | * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS | |
5652 | * but we did (!fpu_active). We need to keep GUEST_CR0.TS on, | |
5653 | * just pretend it's off (also in arch.cr0 for fpu_activate). | |
5654 | */ | |
5655 | vmcs_writel(CR0_READ_SHADOW, | |
5656 | vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS); | |
5657 | vcpu->arch.cr0 &= ~X86_CR0_TS; | |
5658 | } else | |
5659 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); | |
5660 | } | |
5661 | ||
851ba692 | 5662 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5663 | { |
229456fc | 5664 | unsigned long exit_qualification, val; |
6aa8b732 AK |
5665 | int cr; |
5666 | int reg; | |
49a9b07e | 5667 | int err; |
6aa8b732 | 5668 | |
bfdaab09 | 5669 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
5670 | cr = exit_qualification & 15; |
5671 | reg = (exit_qualification >> 8) & 15; | |
5672 | switch ((exit_qualification >> 4) & 3) { | |
5673 | case 0: /* mov to cr */ | |
1e32c079 | 5674 | val = kvm_register_readl(vcpu, reg); |
229456fc | 5675 | trace_kvm_cr_write(cr, val); |
6aa8b732 AK |
5676 | switch (cr) { |
5677 | case 0: | |
eeadf9e7 | 5678 | err = handle_set_cr0(vcpu, val); |
db8fcefa | 5679 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 AK |
5680 | return 1; |
5681 | case 3: | |
2390218b | 5682 | err = kvm_set_cr3(vcpu, val); |
db8fcefa | 5683 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 AK |
5684 | return 1; |
5685 | case 4: | |
eeadf9e7 | 5686 | err = handle_set_cr4(vcpu, val); |
db8fcefa | 5687 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 5688 | return 1; |
0a5fff19 GN |
5689 | case 8: { |
5690 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
1e32c079 | 5691 | u8 cr8 = (u8)val; |
eea1cff9 | 5692 | err = kvm_set_cr8(vcpu, cr8); |
db8fcefa | 5693 | kvm_complete_insn_gp(vcpu, err); |
35754c98 | 5694 | if (lapic_in_kernel(vcpu)) |
0a5fff19 GN |
5695 | return 1; |
5696 | if (cr8_prev <= cr8) | |
5697 | return 1; | |
851ba692 | 5698 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
5699 | return 0; |
5700 | } | |
4b8073e4 | 5701 | } |
6aa8b732 | 5702 | break; |
25c4c276 | 5703 | case 2: /* clts */ |
eeadf9e7 | 5704 | handle_clts(vcpu); |
4d4ec087 | 5705 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
25c4c276 | 5706 | skip_emulated_instruction(vcpu); |
6b52d186 | 5707 | vmx_fpu_activate(vcpu); |
25c4c276 | 5708 | return 1; |
6aa8b732 AK |
5709 | case 1: /*mov from cr*/ |
5710 | switch (cr) { | |
5711 | case 3: | |
9f8fe504 AK |
5712 | val = kvm_read_cr3(vcpu); |
5713 | kvm_register_write(vcpu, reg, val); | |
5714 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
5715 | skip_emulated_instruction(vcpu); |
5716 | return 1; | |
5717 | case 8: | |
229456fc MT |
5718 | val = kvm_get_cr8(vcpu); |
5719 | kvm_register_write(vcpu, reg, val); | |
5720 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
5721 | skip_emulated_instruction(vcpu); |
5722 | return 1; | |
5723 | } | |
5724 | break; | |
5725 | case 3: /* lmsw */ | |
a1f83a74 | 5726 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 5727 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 5728 | kvm_lmsw(vcpu, val); |
6aa8b732 AK |
5729 | |
5730 | skip_emulated_instruction(vcpu); | |
5731 | return 1; | |
5732 | default: | |
5733 | break; | |
5734 | } | |
851ba692 | 5735 | vcpu->run->exit_reason = 0; |
a737f256 | 5736 | vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
5737 | (int)(exit_qualification >> 4) & 3, cr); |
5738 | return 0; | |
5739 | } | |
5740 | ||
851ba692 | 5741 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5742 | { |
bfdaab09 | 5743 | unsigned long exit_qualification; |
16f8a6f9 NA |
5744 | int dr, dr7, reg; |
5745 | ||
5746 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5747 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; | |
5748 | ||
5749 | /* First, if DR does not exist, trigger UD */ | |
5750 | if (!kvm_require_dr(vcpu, dr)) | |
5751 | return 1; | |
6aa8b732 | 5752 | |
f2483415 | 5753 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
5754 | if (!kvm_require_cpl(vcpu, 0)) |
5755 | return 1; | |
16f8a6f9 NA |
5756 | dr7 = vmcs_readl(GUEST_DR7); |
5757 | if (dr7 & DR7_GD) { | |
42dbaa5a JK |
5758 | /* |
5759 | * As the vm-exit takes precedence over the debug trap, we | |
5760 | * need to emulate the latter, either for the host or the | |
5761 | * guest debugging itself. | |
5762 | */ | |
5763 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 | 5764 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
16f8a6f9 | 5765 | vcpu->run->debug.arch.dr7 = dr7; |
82b32774 | 5766 | vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
851ba692 AK |
5767 | vcpu->run->debug.arch.exception = DB_VECTOR; |
5768 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
5769 | return 0; |
5770 | } else { | |
7305eb5d | 5771 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 5772 | vcpu->arch.dr6 |= DR6_BD | DR6_RTM; |
42dbaa5a JK |
5773 | kvm_queue_exception(vcpu, DB_VECTOR); |
5774 | return 1; | |
5775 | } | |
5776 | } | |
5777 | ||
81908bf4 | 5778 | if (vcpu->guest_debug == 0) { |
8f22372f PB |
5779 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
5780 | CPU_BASED_MOV_DR_EXITING); | |
81908bf4 PB |
5781 | |
5782 | /* | |
5783 | * No more DR vmexits; force a reload of the debug registers | |
5784 | * and reenter on this instruction. The next vmexit will | |
5785 | * retrieve the full state of the debug registers. | |
5786 | */ | |
5787 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
5788 | return 1; | |
5789 | } | |
5790 | ||
42dbaa5a JK |
5791 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); |
5792 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 | 5793 | unsigned long val; |
4c4d563b JK |
5794 | |
5795 | if (kvm_get_dr(vcpu, dr, &val)) | |
5796 | return 1; | |
5797 | kvm_register_write(vcpu, reg, val); | |
020df079 | 5798 | } else |
5777392e | 5799 | if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) |
4c4d563b JK |
5800 | return 1; |
5801 | ||
6aa8b732 AK |
5802 | skip_emulated_instruction(vcpu); |
5803 | return 1; | |
5804 | } | |
5805 | ||
73aaf249 JK |
5806 | static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) |
5807 | { | |
5808 | return vcpu->arch.dr6; | |
5809 | } | |
5810 | ||
5811 | static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) | |
5812 | { | |
5813 | } | |
5814 | ||
81908bf4 PB |
5815 | static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
5816 | { | |
81908bf4 PB |
5817 | get_debugreg(vcpu->arch.db[0], 0); |
5818 | get_debugreg(vcpu->arch.db[1], 1); | |
5819 | get_debugreg(vcpu->arch.db[2], 2); | |
5820 | get_debugreg(vcpu->arch.db[3], 3); | |
5821 | get_debugreg(vcpu->arch.dr6, 6); | |
5822 | vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); | |
5823 | ||
5824 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
8f22372f | 5825 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING); |
81908bf4 PB |
5826 | } |
5827 | ||
020df079 GN |
5828 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
5829 | { | |
5830 | vmcs_writel(GUEST_DR7, val); | |
5831 | } | |
5832 | ||
851ba692 | 5833 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 5834 | { |
06465c5a AK |
5835 | kvm_emulate_cpuid(vcpu); |
5836 | return 1; | |
6aa8b732 AK |
5837 | } |
5838 | ||
851ba692 | 5839 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5840 | { |
ad312c7c | 5841 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
609e36d3 | 5842 | struct msr_data msr_info; |
6aa8b732 | 5843 | |
609e36d3 PB |
5844 | msr_info.index = ecx; |
5845 | msr_info.host_initiated = false; | |
5846 | if (vmx_get_msr(vcpu, &msr_info)) { | |
59200273 | 5847 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 5848 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
5849 | return 1; |
5850 | } | |
5851 | ||
609e36d3 | 5852 | trace_kvm_msr_read(ecx, msr_info.data); |
2714d1d3 | 5853 | |
6aa8b732 | 5854 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
609e36d3 PB |
5855 | vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u; |
5856 | vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u; | |
6aa8b732 AK |
5857 | skip_emulated_instruction(vcpu); |
5858 | return 1; | |
5859 | } | |
5860 | ||
851ba692 | 5861 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5862 | { |
8fe8ab46 | 5863 | struct msr_data msr; |
ad312c7c ZX |
5864 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
5865 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
5866 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 5867 | |
8fe8ab46 WA |
5868 | msr.data = data; |
5869 | msr.index = ecx; | |
5870 | msr.host_initiated = false; | |
854e8bb1 | 5871 | if (kvm_set_msr(vcpu, &msr) != 0) { |
59200273 | 5872 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 5873 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
5874 | return 1; |
5875 | } | |
5876 | ||
59200273 | 5877 | trace_kvm_msr_write(ecx, data); |
6aa8b732 AK |
5878 | skip_emulated_instruction(vcpu); |
5879 | return 1; | |
5880 | } | |
5881 | ||
851ba692 | 5882 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 5883 | { |
3842d135 | 5884 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6e5d865c YS |
5885 | return 1; |
5886 | } | |
5887 | ||
851ba692 | 5888 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 5889 | { |
85f455f7 ED |
5890 | u32 cpu_based_vm_exec_control; |
5891 | ||
5892 | /* clear pending irq */ | |
5893 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
5894 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
5895 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 | 5896 | |
3842d135 AK |
5897 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5898 | ||
a26bf12a | 5899 | ++vcpu->stat.irq_window_exits; |
6aa8b732 AK |
5900 | return 1; |
5901 | } | |
5902 | ||
851ba692 | 5903 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 | 5904 | { |
d3bef15f | 5905 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
5906 | } |
5907 | ||
851ba692 | 5908 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 5909 | { |
0d9c055e | 5910 | return kvm_emulate_hypercall(vcpu); |
c21415e8 IM |
5911 | } |
5912 | ||
ec25d5e6 GN |
5913 | static int handle_invd(struct kvm_vcpu *vcpu) |
5914 | { | |
51d8b661 | 5915 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
5916 | } |
5917 | ||
851ba692 | 5918 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 5919 | { |
f9c617f6 | 5920 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
5921 | |
5922 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
5923 | skip_emulated_instruction(vcpu); | |
5924 | return 1; | |
5925 | } | |
5926 | ||
fee84b07 AK |
5927 | static int handle_rdpmc(struct kvm_vcpu *vcpu) |
5928 | { | |
5929 | int err; | |
5930 | ||
5931 | err = kvm_rdpmc(vcpu); | |
5932 | kvm_complete_insn_gp(vcpu, err); | |
5933 | ||
5934 | return 1; | |
5935 | } | |
5936 | ||
851ba692 | 5937 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 | 5938 | { |
f5f48ee1 | 5939 | kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
5940 | return 1; |
5941 | } | |
5942 | ||
2acf923e DC |
5943 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
5944 | { | |
5945 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
5946 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5947 | ||
5948 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
5949 | skip_emulated_instruction(vcpu); | |
5950 | return 1; | |
5951 | } | |
5952 | ||
f53cd63c WL |
5953 | static int handle_xsaves(struct kvm_vcpu *vcpu) |
5954 | { | |
5955 | skip_emulated_instruction(vcpu); | |
5956 | WARN(1, "this should never happen\n"); | |
5957 | return 1; | |
5958 | } | |
5959 | ||
5960 | static int handle_xrstors(struct kvm_vcpu *vcpu) | |
5961 | { | |
5962 | skip_emulated_instruction(vcpu); | |
5963 | WARN(1, "this should never happen\n"); | |
5964 | return 1; | |
5965 | } | |
5966 | ||
851ba692 | 5967 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 5968 | { |
58fbbf26 KT |
5969 | if (likely(fasteoi)) { |
5970 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5971 | int access_type, offset; | |
5972 | ||
5973 | access_type = exit_qualification & APIC_ACCESS_TYPE; | |
5974 | offset = exit_qualification & APIC_ACCESS_OFFSET; | |
5975 | /* | |
5976 | * Sane guest uses MOV to write EOI, with written value | |
5977 | * not cared. So make a short-circuit here by avoiding | |
5978 | * heavy instruction emulation. | |
5979 | */ | |
5980 | if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && | |
5981 | (offset == APIC_EOI)) { | |
5982 | kvm_lapic_set_eoi(vcpu); | |
5983 | skip_emulated_instruction(vcpu); | |
5984 | return 1; | |
5985 | } | |
5986 | } | |
51d8b661 | 5987 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
5988 | } |
5989 | ||
c7c9c56c YZ |
5990 | static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) |
5991 | { | |
5992 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5993 | int vector = exit_qualification & 0xff; | |
5994 | ||
5995 | /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ | |
5996 | kvm_apic_set_eoi_accelerated(vcpu, vector); | |
5997 | return 1; | |
5998 | } | |
5999 | ||
83d4c286 YZ |
6000 | static int handle_apic_write(struct kvm_vcpu *vcpu) |
6001 | { | |
6002 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6003 | u32 offset = exit_qualification & 0xfff; | |
6004 | ||
6005 | /* APIC-write VM exit is trap-like and thus no need to adjust IP */ | |
6006 | kvm_apic_write_nodecode(vcpu, offset); | |
6007 | return 1; | |
6008 | } | |
6009 | ||
851ba692 | 6010 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 6011 | { |
60637aac | 6012 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 6013 | unsigned long exit_qualification; |
e269fb21 JK |
6014 | bool has_error_code = false; |
6015 | u32 error_code = 0; | |
37817f29 | 6016 | u16 tss_selector; |
7f3d35fd | 6017 | int reason, type, idt_v, idt_index; |
64a7ec06 GN |
6018 | |
6019 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
7f3d35fd | 6020 | idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); |
64a7ec06 | 6021 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); |
37817f29 IE |
6022 | |
6023 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6024 | ||
6025 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
6026 | if (reason == TASK_SWITCH_GATE && idt_v) { |
6027 | switch (type) { | |
6028 | case INTR_TYPE_NMI_INTR: | |
6029 | vcpu->arch.nmi_injected = false; | |
654f06fc | 6030 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
6031 | break; |
6032 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 6033 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
6034 | kvm_clear_interrupt_queue(vcpu); |
6035 | break; | |
6036 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
6037 | if (vmx->idt_vectoring_info & |
6038 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
6039 | has_error_code = true; | |
6040 | error_code = | |
6041 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
6042 | } | |
6043 | /* fall through */ | |
64a7ec06 GN |
6044 | case INTR_TYPE_SOFT_EXCEPTION: |
6045 | kvm_clear_exception_queue(vcpu); | |
6046 | break; | |
6047 | default: | |
6048 | break; | |
6049 | } | |
60637aac | 6050 | } |
37817f29 IE |
6051 | tss_selector = exit_qualification; |
6052 | ||
64a7ec06 GN |
6053 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
6054 | type != INTR_TYPE_EXT_INTR && | |
6055 | type != INTR_TYPE_NMI_INTR)) | |
6056 | skip_emulated_instruction(vcpu); | |
6057 | ||
7f3d35fd KW |
6058 | if (kvm_task_switch(vcpu, tss_selector, |
6059 | type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason, | |
6060 | has_error_code, error_code) == EMULATE_FAIL) { | |
acb54517 GN |
6061 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
6062 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6063 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 6064 | return 0; |
acb54517 | 6065 | } |
42dbaa5a | 6066 | |
42dbaa5a JK |
6067 | /* |
6068 | * TODO: What about debug traps on tss switch? | |
6069 | * Are we supposed to inject them and update dr6? | |
6070 | */ | |
6071 | ||
6072 | return 1; | |
37817f29 IE |
6073 | } |
6074 | ||
851ba692 | 6075 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 6076 | { |
f9c617f6 | 6077 | unsigned long exit_qualification; |
1439442c | 6078 | gpa_t gpa; |
4f5982a5 | 6079 | u32 error_code; |
1439442c | 6080 | int gla_validity; |
1439442c | 6081 | |
f9c617f6 | 6082 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c | 6083 | |
1439442c | 6084 | gla_validity = (exit_qualification >> 7) & 0x3; |
72e0ae58 | 6085 | if (gla_validity == 0x2) { |
1439442c SY |
6086 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); |
6087 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
6088 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
f9c617f6 | 6089 | vmcs_readl(GUEST_LINEAR_ADDRESS)); |
1439442c SY |
6090 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", |
6091 | (long unsigned int)exit_qualification); | |
851ba692 AK |
6092 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
6093 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION; | |
596ae895 | 6094 | return 0; |
1439442c SY |
6095 | } |
6096 | ||
0be9c7a8 GN |
6097 | /* |
6098 | * EPT violation happened while executing iret from NMI, | |
6099 | * "blocked by NMI" bit has to be set before next VM entry. | |
6100 | * There are errata that may cause this bit to not be set: | |
6101 | * AAK134, BY25. | |
6102 | */ | |
bcd1c294 GN |
6103 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && |
6104 | cpu_has_virtual_nmis() && | |
6105 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) | |
0be9c7a8 GN |
6106 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); |
6107 | ||
1439442c | 6108 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
229456fc | 6109 | trace_kvm_page_fault(gpa, exit_qualification); |
4f5982a5 | 6110 | |
d95c5568 BD |
6111 | /* it is a read fault? */ |
6112 | error_code = (exit_qualification << 2) & PFERR_USER_MASK; | |
6113 | /* it is a write fault? */ | |
6114 | error_code |= exit_qualification & PFERR_WRITE_MASK; | |
25d92081 | 6115 | /* It is a fetch fault? */ |
81ed33e4 | 6116 | error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK; |
4f5982a5 | 6117 | /* ept page table is present? */ |
d95c5568 | 6118 | error_code |= (exit_qualification & 0x38) != 0; |
4f5982a5 | 6119 | |
25d92081 YZ |
6120 | vcpu->arch.exit_qualification = exit_qualification; |
6121 | ||
4f5982a5 | 6122 | return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); |
1439442c SY |
6123 | } |
6124 | ||
851ba692 | 6125 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 | 6126 | { |
f735d4af | 6127 | int ret; |
68f89400 MT |
6128 | gpa_t gpa; |
6129 | ||
6130 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
e32edf4f | 6131 | if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { |
68c3b4d1 | 6132 | skip_emulated_instruction(vcpu); |
931c33b1 | 6133 | trace_kvm_fast_mmio(gpa); |
68c3b4d1 MT |
6134 | return 1; |
6135 | } | |
68f89400 | 6136 | |
450869d6 | 6137 | ret = handle_mmio_page_fault(vcpu, gpa, true); |
b37fbea6 | 6138 | if (likely(ret == RET_MMIO_PF_EMULATE)) |
ce88decf XG |
6139 | return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) == |
6140 | EMULATE_DONE; | |
f8f55942 XG |
6141 | |
6142 | if (unlikely(ret == RET_MMIO_PF_INVALID)) | |
6143 | return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0); | |
6144 | ||
b37fbea6 | 6145 | if (unlikely(ret == RET_MMIO_PF_RETRY)) |
ce88decf XG |
6146 | return 1; |
6147 | ||
6148 | /* It is the real ept misconfig */ | |
f735d4af | 6149 | WARN_ON(1); |
68f89400 | 6150 | |
851ba692 AK |
6151 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
6152 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
6153 | |
6154 | return 0; | |
6155 | } | |
6156 | ||
851ba692 | 6157 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 SY |
6158 | { |
6159 | u32 cpu_based_vm_exec_control; | |
6160 | ||
6161 | /* clear pending NMI */ | |
6162 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
6163 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
6164 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
6165 | ++vcpu->stat.nmi_window_exits; | |
3842d135 | 6166 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
6167 | |
6168 | return 1; | |
6169 | } | |
6170 | ||
80ced186 | 6171 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 6172 | { |
8b3079a5 AK |
6173 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6174 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 6175 | int ret = 1; |
49e9d557 AK |
6176 | u32 cpu_exec_ctrl; |
6177 | bool intr_window_requested; | |
b8405c18 | 6178 | unsigned count = 130; |
49e9d557 AK |
6179 | |
6180 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
6181 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 | 6182 | |
98eb2f8b | 6183 | while (vmx->emulation_required && count-- != 0) { |
bdea48e3 | 6184 | if (intr_window_requested && vmx_interrupt_allowed(vcpu)) |
49e9d557 AK |
6185 | return handle_interrupt_window(&vmx->vcpu); |
6186 | ||
de87dcdd AK |
6187 | if (test_bit(KVM_REQ_EVENT, &vcpu->requests)) |
6188 | return 1; | |
6189 | ||
991eebf9 | 6190 | err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE); |
ea953ef0 | 6191 | |
ac0a48c3 | 6192 | if (err == EMULATE_USER_EXIT) { |
94452b9e | 6193 | ++vcpu->stat.mmio_exits; |
80ced186 MG |
6194 | ret = 0; |
6195 | goto out; | |
6196 | } | |
1d5a4d9b | 6197 | |
de5f70e0 AK |
6198 | if (err != EMULATE_DONE) { |
6199 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6200 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6201 | vcpu->run->internal.ndata = 0; | |
6d77dbfc | 6202 | return 0; |
de5f70e0 | 6203 | } |
ea953ef0 | 6204 | |
8d76c49e GN |
6205 | if (vcpu->arch.halt_request) { |
6206 | vcpu->arch.halt_request = 0; | |
5cb56059 | 6207 | ret = kvm_vcpu_halt(vcpu); |
8d76c49e GN |
6208 | goto out; |
6209 | } | |
6210 | ||
ea953ef0 | 6211 | if (signal_pending(current)) |
80ced186 | 6212 | goto out; |
ea953ef0 MG |
6213 | if (need_resched()) |
6214 | schedule(); | |
6215 | } | |
6216 | ||
80ced186 MG |
6217 | out: |
6218 | return ret; | |
ea953ef0 MG |
6219 | } |
6220 | ||
b4a2d31d RK |
6221 | static int __grow_ple_window(int val) |
6222 | { | |
6223 | if (ple_window_grow < 1) | |
6224 | return ple_window; | |
6225 | ||
6226 | val = min(val, ple_window_actual_max); | |
6227 | ||
6228 | if (ple_window_grow < ple_window) | |
6229 | val *= ple_window_grow; | |
6230 | else | |
6231 | val += ple_window_grow; | |
6232 | ||
6233 | return val; | |
6234 | } | |
6235 | ||
6236 | static int __shrink_ple_window(int val, int modifier, int minimum) | |
6237 | { | |
6238 | if (modifier < 1) | |
6239 | return ple_window; | |
6240 | ||
6241 | if (modifier < ple_window) | |
6242 | val /= modifier; | |
6243 | else | |
6244 | val -= modifier; | |
6245 | ||
6246 | return max(val, minimum); | |
6247 | } | |
6248 | ||
6249 | static void grow_ple_window(struct kvm_vcpu *vcpu) | |
6250 | { | |
6251 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6252 | int old = vmx->ple_window; | |
6253 | ||
6254 | vmx->ple_window = __grow_ple_window(old); | |
6255 | ||
6256 | if (vmx->ple_window != old) | |
6257 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6258 | |
6259 | trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6260 | } |
6261 | ||
6262 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
6263 | { | |
6264 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6265 | int old = vmx->ple_window; | |
6266 | ||
6267 | vmx->ple_window = __shrink_ple_window(old, | |
6268 | ple_window_shrink, ple_window); | |
6269 | ||
6270 | if (vmx->ple_window != old) | |
6271 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6272 | |
6273 | trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6274 | } |
6275 | ||
6276 | /* | |
6277 | * ple_window_actual_max is computed to be one grow_ple_window() below | |
6278 | * ple_window_max. (See __grow_ple_window for the reason.) | |
6279 | * This prevents overflows, because ple_window_max is int. | |
6280 | * ple_window_max effectively rounded down to a multiple of ple_window_grow in | |
6281 | * this process. | |
6282 | * ple_window_max is also prevented from setting vmx->ple_window < ple_window. | |
6283 | */ | |
6284 | static void update_ple_window_actual_max(void) | |
6285 | { | |
6286 | ple_window_actual_max = | |
6287 | __shrink_ple_window(max(ple_window_max, ple_window), | |
6288 | ple_window_grow, INT_MIN); | |
6289 | } | |
6290 | ||
bf9f6ac8 FW |
6291 | /* |
6292 | * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. | |
6293 | */ | |
6294 | static void wakeup_handler(void) | |
6295 | { | |
6296 | struct kvm_vcpu *vcpu; | |
6297 | int cpu = smp_processor_id(); | |
6298 | ||
6299 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6300 | list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), | |
6301 | blocked_vcpu_list) { | |
6302 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
6303 | ||
6304 | if (pi_test_on(pi_desc) == 1) | |
6305 | kvm_vcpu_kick(vcpu); | |
6306 | } | |
6307 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6308 | } | |
6309 | ||
f2c7648d TC |
6310 | static __init int hardware_setup(void) |
6311 | { | |
34a1cd60 TC |
6312 | int r = -ENOMEM, i, msr; |
6313 | ||
6314 | rdmsrl_safe(MSR_EFER, &host_efer); | |
6315 | ||
6316 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) | |
6317 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
6318 | ||
23611332 RK |
6319 | for (i = 0; i < VMX_BITMAP_NR; i++) { |
6320 | vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6321 | if (!vmx_bitmap[i]) | |
6322 | goto out; | |
6323 | } | |
34a1cd60 TC |
6324 | |
6325 | vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL); | |
34a1cd60 TC |
6326 | memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); |
6327 | memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); | |
6328 | ||
6329 | /* | |
6330 | * Allow direct access to the PC debug port (it is often used for I/O | |
6331 | * delays, but the vmexits simply slow things down). | |
6332 | */ | |
6333 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); | |
6334 | clear_bit(0x80, vmx_io_bitmap_a); | |
6335 | ||
6336 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); | |
6337 | ||
6338 | memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE); | |
6339 | memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE); | |
6340 | ||
34a1cd60 TC |
6341 | if (setup_vmcs_config(&vmcs_config) < 0) { |
6342 | r = -EIO; | |
23611332 | 6343 | goto out; |
baa03522 | 6344 | } |
f2c7648d TC |
6345 | |
6346 | if (boot_cpu_has(X86_FEATURE_NX)) | |
6347 | kvm_enable_efer_bits(EFER_NX); | |
6348 | ||
6349 | if (!cpu_has_vmx_vpid()) | |
6350 | enable_vpid = 0; | |
6351 | if (!cpu_has_vmx_shadow_vmcs()) | |
6352 | enable_shadow_vmcs = 0; | |
6353 | if (enable_shadow_vmcs) | |
6354 | init_vmcs_shadow_fields(); | |
6355 | ||
6356 | if (!cpu_has_vmx_ept() || | |
6357 | !cpu_has_vmx_ept_4levels()) { | |
6358 | enable_ept = 0; | |
6359 | enable_unrestricted_guest = 0; | |
6360 | enable_ept_ad_bits = 0; | |
6361 | } | |
6362 | ||
6363 | if (!cpu_has_vmx_ept_ad_bits()) | |
6364 | enable_ept_ad_bits = 0; | |
6365 | ||
6366 | if (!cpu_has_vmx_unrestricted_guest()) | |
6367 | enable_unrestricted_guest = 0; | |
6368 | ||
ad15a296 | 6369 | if (!cpu_has_vmx_flexpriority()) |
f2c7648d TC |
6370 | flexpriority_enabled = 0; |
6371 | ||
ad15a296 PB |
6372 | /* |
6373 | * set_apic_access_page_addr() is used to reload apic access | |
6374 | * page upon invalidation. No need to do anything if not | |
6375 | * using the APIC_ACCESS_ADDR VMCS field. | |
6376 | */ | |
6377 | if (!flexpriority_enabled) | |
f2c7648d | 6378 | kvm_x86_ops->set_apic_access_page_addr = NULL; |
f2c7648d TC |
6379 | |
6380 | if (!cpu_has_vmx_tpr_shadow()) | |
6381 | kvm_x86_ops->update_cr8_intercept = NULL; | |
6382 | ||
6383 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) | |
6384 | kvm_disable_largepages(); | |
6385 | ||
6386 | if (!cpu_has_vmx_ple()) | |
6387 | ple_gap = 0; | |
6388 | ||
6389 | if (!cpu_has_vmx_apicv()) | |
6390 | enable_apicv = 0; | |
6391 | ||
64903d61 HZ |
6392 | if (cpu_has_vmx_tsc_scaling()) { |
6393 | kvm_has_tsc_control = true; | |
6394 | kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; | |
6395 | kvm_tsc_scaling_ratio_frac_bits = 48; | |
6396 | } | |
6397 | ||
baa03522 TC |
6398 | vmx_disable_intercept_for_msr(MSR_FS_BASE, false); |
6399 | vmx_disable_intercept_for_msr(MSR_GS_BASE, false); | |
6400 | vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); | |
6401 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); | |
6402 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); | |
6403 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); | |
6404 | vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true); | |
6405 | ||
c63e4563 | 6406 | memcpy(vmx_msr_bitmap_legacy_x2apic_apicv, |
baa03522 | 6407 | vmx_msr_bitmap_legacy, PAGE_SIZE); |
c63e4563 | 6408 | memcpy(vmx_msr_bitmap_longmode_x2apic_apicv, |
baa03522 | 6409 | vmx_msr_bitmap_longmode, PAGE_SIZE); |
c63e4563 | 6410 | memcpy(vmx_msr_bitmap_legacy_x2apic, |
f6e90f9e | 6411 | vmx_msr_bitmap_legacy, PAGE_SIZE); |
c63e4563 | 6412 | memcpy(vmx_msr_bitmap_longmode_x2apic, |
f6e90f9e | 6413 | vmx_msr_bitmap_longmode, PAGE_SIZE); |
baa03522 | 6414 | |
04bb92e4 WL |
6415 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
6416 | ||
40d8338d RK |
6417 | for (msr = 0x800; msr <= 0x8ff; msr++) { |
6418 | if (msr == 0x839 /* TMCCT */) | |
6419 | continue; | |
2e69f865 | 6420 | vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true); |
40d8338d | 6421 | } |
3ce424e4 | 6422 | |
f6e90f9e | 6423 | /* |
2e69f865 RK |
6424 | * TPR reads and writes can be virtualized even if virtual interrupt |
6425 | * delivery is not in use. | |
f6e90f9e | 6426 | */ |
2e69f865 RK |
6427 | vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true); |
6428 | vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false); | |
6429 | ||
6430 | /* EOI */ | |
6431 | vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true); | |
6432 | /* SELF-IPI */ | |
6433 | vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true); | |
baa03522 TC |
6434 | |
6435 | if (enable_ept) { | |
d95c5568 | 6436 | kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, |
baa03522 TC |
6437 | (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull, |
6438 | (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull, | |
d95c5568 BD |
6439 | 0ull, VMX_EPT_EXECUTABLE_MASK, |
6440 | cpu_has_vmx_ept_execute_only() ? | |
6441 | 0ull : VMX_EPT_READABLE_MASK); | |
baa03522 TC |
6442 | ept_set_mmio_spte_mask(); |
6443 | kvm_enable_tdp(); | |
6444 | } else | |
6445 | kvm_disable_tdp(); | |
6446 | ||
6447 | update_ple_window_actual_max(); | |
6448 | ||
843e4330 KH |
6449 | /* |
6450 | * Only enable PML when hardware supports PML feature, and both EPT | |
6451 | * and EPT A/D bit features are enabled -- PML depends on them to work. | |
6452 | */ | |
6453 | if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) | |
6454 | enable_pml = 0; | |
6455 | ||
6456 | if (!enable_pml) { | |
6457 | kvm_x86_ops->slot_enable_log_dirty = NULL; | |
6458 | kvm_x86_ops->slot_disable_log_dirty = NULL; | |
6459 | kvm_x86_ops->flush_log_dirty = NULL; | |
6460 | kvm_x86_ops->enable_log_dirty_pt_masked = NULL; | |
6461 | } | |
6462 | ||
64672c95 YJ |
6463 | if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) { |
6464 | u64 vmx_msr; | |
6465 | ||
6466 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
6467 | cpu_preemption_timer_multi = | |
6468 | vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; | |
6469 | } else { | |
6470 | kvm_x86_ops->set_hv_timer = NULL; | |
6471 | kvm_x86_ops->cancel_hv_timer = NULL; | |
6472 | } | |
6473 | ||
bf9f6ac8 FW |
6474 | kvm_set_posted_intr_wakeup_handler(wakeup_handler); |
6475 | ||
c45dcc71 AR |
6476 | kvm_mce_cap_supported |= MCG_LMCE_P; |
6477 | ||
f2c7648d | 6478 | return alloc_kvm_area(); |
34a1cd60 | 6479 | |
34a1cd60 | 6480 | out: |
23611332 RK |
6481 | for (i = 0; i < VMX_BITMAP_NR; i++) |
6482 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 TC |
6483 | |
6484 | return r; | |
f2c7648d TC |
6485 | } |
6486 | ||
6487 | static __exit void hardware_unsetup(void) | |
6488 | { | |
23611332 RK |
6489 | int i; |
6490 | ||
6491 | for (i = 0; i < VMX_BITMAP_NR; i++) | |
6492 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 | 6493 | |
f2c7648d TC |
6494 | free_kvm_area(); |
6495 | } | |
6496 | ||
4b8d54f9 ZE |
6497 | /* |
6498 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
6499 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
6500 | */ | |
9fb41ba8 | 6501 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 | 6502 | { |
b4a2d31d RK |
6503 | if (ple_gap) |
6504 | grow_ple_window(vcpu); | |
6505 | ||
4b8d54f9 ZE |
6506 | skip_emulated_instruction(vcpu); |
6507 | kvm_vcpu_on_spin(vcpu); | |
6508 | ||
6509 | return 1; | |
6510 | } | |
6511 | ||
87c00572 | 6512 | static int handle_nop(struct kvm_vcpu *vcpu) |
59708670 | 6513 | { |
87c00572 | 6514 | skip_emulated_instruction(vcpu); |
59708670 SY |
6515 | return 1; |
6516 | } | |
6517 | ||
87c00572 GS |
6518 | static int handle_mwait(struct kvm_vcpu *vcpu) |
6519 | { | |
6520 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
6521 | return handle_nop(vcpu); | |
6522 | } | |
6523 | ||
5f3d45e7 MD |
6524 | static int handle_monitor_trap(struct kvm_vcpu *vcpu) |
6525 | { | |
6526 | return 1; | |
6527 | } | |
6528 | ||
87c00572 GS |
6529 | static int handle_monitor(struct kvm_vcpu *vcpu) |
6530 | { | |
6531 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
6532 | return handle_nop(vcpu); | |
6533 | } | |
6534 | ||
ff2f6fe9 NHE |
6535 | /* |
6536 | * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12. | |
6537 | * We could reuse a single VMCS for all the L2 guests, but we also want the | |
6538 | * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this | |
6539 | * allows keeping them loaded on the processor, and in the future will allow | |
6540 | * optimizations where prepare_vmcs02 doesn't need to set all the fields on | |
6541 | * every entry if they never change. | |
6542 | * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE | |
6543 | * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first. | |
6544 | * | |
6545 | * The following functions allocate and free a vmcs02 in this pool. | |
6546 | */ | |
6547 | ||
6548 | /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */ | |
6549 | static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx) | |
6550 | { | |
6551 | struct vmcs02_list *item; | |
6552 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6553 | if (item->vmptr == vmx->nested.current_vmptr) { | |
6554 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6555 | return &item->vmcs02; | |
6556 | } | |
6557 | ||
6558 | if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) { | |
6559 | /* Recycle the least recently used VMCS. */ | |
d74c0e6b GT |
6560 | item = list_last_entry(&vmx->nested.vmcs02_pool, |
6561 | struct vmcs02_list, list); | |
ff2f6fe9 NHE |
6562 | item->vmptr = vmx->nested.current_vmptr; |
6563 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6564 | return &item->vmcs02; | |
6565 | } | |
6566 | ||
6567 | /* Create a new VMCS */ | |
0fa24ce3 | 6568 | item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL); |
ff2f6fe9 NHE |
6569 | if (!item) |
6570 | return NULL; | |
6571 | item->vmcs02.vmcs = alloc_vmcs(); | |
355f4fb1 | 6572 | item->vmcs02.shadow_vmcs = NULL; |
ff2f6fe9 NHE |
6573 | if (!item->vmcs02.vmcs) { |
6574 | kfree(item); | |
6575 | return NULL; | |
6576 | } | |
6577 | loaded_vmcs_init(&item->vmcs02); | |
6578 | item->vmptr = vmx->nested.current_vmptr; | |
6579 | list_add(&(item->list), &(vmx->nested.vmcs02_pool)); | |
6580 | vmx->nested.vmcs02_num++; | |
6581 | return &item->vmcs02; | |
6582 | } | |
6583 | ||
6584 | /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */ | |
6585 | static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr) | |
6586 | { | |
6587 | struct vmcs02_list *item; | |
6588 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6589 | if (item->vmptr == vmptr) { | |
6590 | free_loaded_vmcs(&item->vmcs02); | |
6591 | list_del(&item->list); | |
6592 | kfree(item); | |
6593 | vmx->nested.vmcs02_num--; | |
6594 | return; | |
6595 | } | |
6596 | } | |
6597 | ||
6598 | /* | |
6599 | * Free all VMCSs saved for this vcpu, except the one pointed by | |
4fa7734c PB |
6600 | * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs |
6601 | * must be &vmx->vmcs01. | |
ff2f6fe9 NHE |
6602 | */ |
6603 | static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx) | |
6604 | { | |
6605 | struct vmcs02_list *item, *n; | |
4fa7734c PB |
6606 | |
6607 | WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01); | |
ff2f6fe9 | 6608 | list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) { |
4fa7734c PB |
6609 | /* |
6610 | * Something will leak if the above WARN triggers. Better than | |
6611 | * a use-after-free. | |
6612 | */ | |
6613 | if (vmx->loaded_vmcs == &item->vmcs02) | |
6614 | continue; | |
6615 | ||
6616 | free_loaded_vmcs(&item->vmcs02); | |
ff2f6fe9 NHE |
6617 | list_del(&item->list); |
6618 | kfree(item); | |
4fa7734c | 6619 | vmx->nested.vmcs02_num--; |
ff2f6fe9 | 6620 | } |
ff2f6fe9 NHE |
6621 | } |
6622 | ||
0658fbaa ACL |
6623 | /* |
6624 | * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), | |
6625 | * set the success or error code of an emulated VMX instruction, as specified | |
6626 | * by Vol 2B, VMX Instruction Reference, "Conventions". | |
6627 | */ | |
6628 | static void nested_vmx_succeed(struct kvm_vcpu *vcpu) | |
6629 | { | |
6630 | vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) | |
6631 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
6632 | X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); | |
6633 | } | |
6634 | ||
6635 | static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu) | |
6636 | { | |
6637 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
6638 | & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | | |
6639 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
6640 | | X86_EFLAGS_CF); | |
6641 | } | |
6642 | ||
145c28dd | 6643 | static void nested_vmx_failValid(struct kvm_vcpu *vcpu, |
0658fbaa ACL |
6644 | u32 vm_instruction_error) |
6645 | { | |
6646 | if (to_vmx(vcpu)->nested.current_vmptr == -1ull) { | |
6647 | /* | |
6648 | * failValid writes the error number to the current VMCS, which | |
6649 | * can't be done there isn't a current VMCS. | |
6650 | */ | |
6651 | nested_vmx_failInvalid(vcpu); | |
6652 | return; | |
6653 | } | |
6654 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
6655 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
6656 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
6657 | | X86_EFLAGS_ZF); | |
6658 | get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; | |
6659 | /* | |
6660 | * We don't need to force a shadow sync because | |
6661 | * VM_INSTRUCTION_ERROR is not shadowed | |
6662 | */ | |
6663 | } | |
145c28dd | 6664 | |
ff651cb6 WV |
6665 | static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator) |
6666 | { | |
6667 | /* TODO: not to reset guest simply here. */ | |
6668 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
bbe41b95 | 6669 | pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator); |
ff651cb6 WV |
6670 | } |
6671 | ||
f4124500 JK |
6672 | static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) |
6673 | { | |
6674 | struct vcpu_vmx *vmx = | |
6675 | container_of(timer, struct vcpu_vmx, nested.preemption_timer); | |
6676 | ||
6677 | vmx->nested.preemption_timer_expired = true; | |
6678 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); | |
6679 | kvm_vcpu_kick(&vmx->vcpu); | |
6680 | ||
6681 | return HRTIMER_NORESTART; | |
6682 | } | |
6683 | ||
19677e32 BD |
6684 | /* |
6685 | * Decode the memory-address operand of a vmx instruction, as recorded on an | |
6686 | * exit caused by such an instruction (run by a guest hypervisor). | |
6687 | * On success, returns 0. When the operand is invalid, returns 1 and throws | |
6688 | * #UD or #GP. | |
6689 | */ | |
6690 | static int get_vmx_mem_address(struct kvm_vcpu *vcpu, | |
6691 | unsigned long exit_qualification, | |
f9eb4af6 | 6692 | u32 vmx_instruction_info, bool wr, gva_t *ret) |
19677e32 | 6693 | { |
f9eb4af6 EK |
6694 | gva_t off; |
6695 | bool exn; | |
6696 | struct kvm_segment s; | |
6697 | ||
19677e32 BD |
6698 | /* |
6699 | * According to Vol. 3B, "Information for VM Exits Due to Instruction | |
6700 | * Execution", on an exit, vmx_instruction_info holds most of the | |
6701 | * addressing components of the operand. Only the displacement part | |
6702 | * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). | |
6703 | * For how an actual address is calculated from all these components, | |
6704 | * refer to Vol. 1, "Operand Addressing". | |
6705 | */ | |
6706 | int scaling = vmx_instruction_info & 3; | |
6707 | int addr_size = (vmx_instruction_info >> 7) & 7; | |
6708 | bool is_reg = vmx_instruction_info & (1u << 10); | |
6709 | int seg_reg = (vmx_instruction_info >> 15) & 7; | |
6710 | int index_reg = (vmx_instruction_info >> 18) & 0xf; | |
6711 | bool index_is_valid = !(vmx_instruction_info & (1u << 22)); | |
6712 | int base_reg = (vmx_instruction_info >> 23) & 0xf; | |
6713 | bool base_is_valid = !(vmx_instruction_info & (1u << 27)); | |
6714 | ||
6715 | if (is_reg) { | |
6716 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6717 | return 1; | |
6718 | } | |
6719 | ||
6720 | /* Addr = segment_base + offset */ | |
6721 | /* offset = base + [index * scale] + displacement */ | |
f9eb4af6 | 6722 | off = exit_qualification; /* holds the displacement */ |
19677e32 | 6723 | if (base_is_valid) |
f9eb4af6 | 6724 | off += kvm_register_read(vcpu, base_reg); |
19677e32 | 6725 | if (index_is_valid) |
f9eb4af6 EK |
6726 | off += kvm_register_read(vcpu, index_reg)<<scaling; |
6727 | vmx_get_segment(vcpu, &s, seg_reg); | |
6728 | *ret = s.base + off; | |
19677e32 BD |
6729 | |
6730 | if (addr_size == 1) /* 32 bit */ | |
6731 | *ret &= 0xffffffff; | |
6732 | ||
f9eb4af6 EK |
6733 | /* Checks for #GP/#SS exceptions. */ |
6734 | exn = false; | |
ff30ef40 QC |
6735 | if (is_long_mode(vcpu)) { |
6736 | /* Long mode: #GP(0)/#SS(0) if the memory address is in a | |
6737 | * non-canonical form. This is the only check on the memory | |
6738 | * destination for long mode! | |
6739 | */ | |
6740 | exn = is_noncanonical_address(*ret); | |
6741 | } else if (is_protmode(vcpu)) { | |
f9eb4af6 EK |
6742 | /* Protected mode: apply checks for segment validity in the |
6743 | * following order: | |
6744 | * - segment type check (#GP(0) may be thrown) | |
6745 | * - usability check (#GP(0)/#SS(0)) | |
6746 | * - limit check (#GP(0)/#SS(0)) | |
6747 | */ | |
6748 | if (wr) | |
6749 | /* #GP(0) if the destination operand is located in a | |
6750 | * read-only data segment or any code segment. | |
6751 | */ | |
6752 | exn = ((s.type & 0xa) == 0 || (s.type & 8)); | |
6753 | else | |
6754 | /* #GP(0) if the source operand is located in an | |
6755 | * execute-only code segment | |
6756 | */ | |
6757 | exn = ((s.type & 0xa) == 8); | |
ff30ef40 QC |
6758 | if (exn) { |
6759 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
6760 | return 1; | |
6761 | } | |
f9eb4af6 EK |
6762 | /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. |
6763 | */ | |
6764 | exn = (s.unusable != 0); | |
6765 | /* Protected mode: #GP(0)/#SS(0) if the memory | |
6766 | * operand is outside the segment limit. | |
6767 | */ | |
6768 | exn = exn || (off + sizeof(u64) > s.limit); | |
6769 | } | |
6770 | if (exn) { | |
6771 | kvm_queue_exception_e(vcpu, | |
6772 | seg_reg == VCPU_SREG_SS ? | |
6773 | SS_VECTOR : GP_VECTOR, | |
6774 | 0); | |
6775 | return 1; | |
6776 | } | |
6777 | ||
19677e32 BD |
6778 | return 0; |
6779 | } | |
6780 | ||
3573e22c BD |
6781 | /* |
6782 | * This function performs the various checks including | |
6783 | * - if it's 4KB aligned | |
6784 | * - No bits beyond the physical address width are set | |
6785 | * - Returns 0 on success or else 1 | |
4291b588 | 6786 | * (Intel SDM Section 30.3) |
3573e22c | 6787 | */ |
4291b588 BD |
6788 | static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason, |
6789 | gpa_t *vmpointer) | |
3573e22c BD |
6790 | { |
6791 | gva_t gva; | |
6792 | gpa_t vmptr; | |
6793 | struct x86_exception e; | |
6794 | struct page *page; | |
6795 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6796 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
6797 | ||
6798 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 6799 | vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva)) |
3573e22c BD |
6800 | return 1; |
6801 | ||
6802 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr, | |
6803 | sizeof(vmptr), &e)) { | |
6804 | kvm_inject_page_fault(vcpu, &e); | |
6805 | return 1; | |
6806 | } | |
6807 | ||
6808 | switch (exit_reason) { | |
6809 | case EXIT_REASON_VMON: | |
6810 | /* | |
6811 | * SDM 3: 24.11.5 | |
6812 | * The first 4 bytes of VMXON region contain the supported | |
6813 | * VMCS revision identifier | |
6814 | * | |
6815 | * Note - IA32_VMX_BASIC[48] will never be 1 | |
6816 | * for the nested case; | |
6817 | * which replaces physical address width with 32 | |
6818 | * | |
6819 | */ | |
bc39c4db | 6820 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
3573e22c BD |
6821 | nested_vmx_failInvalid(vcpu); |
6822 | skip_emulated_instruction(vcpu); | |
6823 | return 1; | |
6824 | } | |
6825 | ||
6826 | page = nested_get_page(vcpu, vmptr); | |
6827 | if (page == NULL || | |
6828 | *(u32 *)kmap(page) != VMCS12_REVISION) { | |
6829 | nested_vmx_failInvalid(vcpu); | |
6830 | kunmap(page); | |
6831 | skip_emulated_instruction(vcpu); | |
6832 | return 1; | |
6833 | } | |
6834 | kunmap(page); | |
6835 | vmx->nested.vmxon_ptr = vmptr; | |
6836 | break; | |
4291b588 | 6837 | case EXIT_REASON_VMCLEAR: |
bc39c4db | 6838 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
4291b588 BD |
6839 | nested_vmx_failValid(vcpu, |
6840 | VMXERR_VMCLEAR_INVALID_ADDRESS); | |
6841 | skip_emulated_instruction(vcpu); | |
6842 | return 1; | |
6843 | } | |
6844 | ||
6845 | if (vmptr == vmx->nested.vmxon_ptr) { | |
6846 | nested_vmx_failValid(vcpu, | |
6847 | VMXERR_VMCLEAR_VMXON_POINTER); | |
6848 | skip_emulated_instruction(vcpu); | |
6849 | return 1; | |
6850 | } | |
6851 | break; | |
6852 | case EXIT_REASON_VMPTRLD: | |
bc39c4db | 6853 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
4291b588 BD |
6854 | nested_vmx_failValid(vcpu, |
6855 | VMXERR_VMPTRLD_INVALID_ADDRESS); | |
6856 | skip_emulated_instruction(vcpu); | |
6857 | return 1; | |
6858 | } | |
3573e22c | 6859 | |
4291b588 BD |
6860 | if (vmptr == vmx->nested.vmxon_ptr) { |
6861 | nested_vmx_failValid(vcpu, | |
6862 | VMXERR_VMCLEAR_VMXON_POINTER); | |
6863 | skip_emulated_instruction(vcpu); | |
6864 | return 1; | |
6865 | } | |
6866 | break; | |
3573e22c BD |
6867 | default: |
6868 | return 1; /* shouldn't happen */ | |
6869 | } | |
6870 | ||
4291b588 BD |
6871 | if (vmpointer) |
6872 | *vmpointer = vmptr; | |
3573e22c BD |
6873 | return 0; |
6874 | } | |
6875 | ||
ec378aee NHE |
6876 | /* |
6877 | * Emulate the VMXON instruction. | |
6878 | * Currently, we just remember that VMX is active, and do not save or even | |
6879 | * inspect the argument to VMXON (the so-called "VMXON pointer") because we | |
6880 | * do not currently need to store anything in that guest-allocated memory | |
6881 | * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their | |
6882 | * argument is different from the VMXON pointer (which the spec says they do). | |
6883 | */ | |
6884 | static int handle_vmon(struct kvm_vcpu *vcpu) | |
6885 | { | |
6886 | struct kvm_segment cs; | |
6887 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8de48833 | 6888 | struct vmcs *shadow_vmcs; |
b3897a49 NHE |
6889 | const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED |
6890 | | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
ec378aee NHE |
6891 | |
6892 | /* The Intel VMX Instruction Reference lists a bunch of bits that | |
6893 | * are prerequisite to running VMXON, most notably cr4.VMXE must be | |
6894 | * set to 1 (see vmx_set_cr4() for when we allow the guest to set this). | |
6895 | * Otherwise, we should fail with #UD. We test these now: | |
6896 | */ | |
6897 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) || | |
6898 | !kvm_read_cr0_bits(vcpu, X86_CR0_PE) || | |
6899 | (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { | |
6900 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6901 | return 1; | |
6902 | } | |
6903 | ||
6904 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
6905 | if (is_long_mode(vcpu) && !cs.l) { | |
6906 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6907 | return 1; | |
6908 | } | |
6909 | ||
6910 | if (vmx_get_cpl(vcpu)) { | |
6911 | kvm_inject_gp(vcpu, 0); | |
6912 | return 1; | |
6913 | } | |
3573e22c | 6914 | |
4291b588 | 6915 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL)) |
3573e22c BD |
6916 | return 1; |
6917 | ||
145c28dd AG |
6918 | if (vmx->nested.vmxon) { |
6919 | nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); | |
6920 | skip_emulated_instruction(vcpu); | |
6921 | return 1; | |
6922 | } | |
b3897a49 | 6923 | |
3b84080b | 6924 | if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES) |
b3897a49 NHE |
6925 | != VMXON_NEEDED_FEATURES) { |
6926 | kvm_inject_gp(vcpu, 0); | |
6927 | return 1; | |
6928 | } | |
6929 | ||
d048c098 RK |
6930 | if (cpu_has_vmx_msr_bitmap()) { |
6931 | vmx->nested.msr_bitmap = | |
6932 | (unsigned long *)__get_free_page(GFP_KERNEL); | |
6933 | if (!vmx->nested.msr_bitmap) | |
6934 | goto out_msr_bitmap; | |
6935 | } | |
6936 | ||
4f2777bc DM |
6937 | vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL); |
6938 | if (!vmx->nested.cached_vmcs12) | |
d048c098 | 6939 | goto out_cached_vmcs12; |
4f2777bc | 6940 | |
8de48833 AG |
6941 | if (enable_shadow_vmcs) { |
6942 | shadow_vmcs = alloc_vmcs(); | |
d048c098 RK |
6943 | if (!shadow_vmcs) |
6944 | goto out_shadow_vmcs; | |
8de48833 AG |
6945 | /* mark vmcs as shadow */ |
6946 | shadow_vmcs->revision_id |= (1u << 31); | |
6947 | /* init shadow vmcs */ | |
6948 | vmcs_clear(shadow_vmcs); | |
355f4fb1 | 6949 | vmx->vmcs01.shadow_vmcs = shadow_vmcs; |
8de48833 | 6950 | } |
ec378aee | 6951 | |
ff2f6fe9 NHE |
6952 | INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool)); |
6953 | vmx->nested.vmcs02_num = 0; | |
6954 | ||
f4124500 | 6955 | hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, |
f15a75ee | 6956 | HRTIMER_MODE_REL_PINNED); |
f4124500 JK |
6957 | vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; |
6958 | ||
ec378aee NHE |
6959 | vmx->nested.vmxon = true; |
6960 | ||
6961 | skip_emulated_instruction(vcpu); | |
a25eb114 | 6962 | nested_vmx_succeed(vcpu); |
ec378aee | 6963 | return 1; |
d048c098 RK |
6964 | |
6965 | out_shadow_vmcs: | |
6966 | kfree(vmx->nested.cached_vmcs12); | |
6967 | ||
6968 | out_cached_vmcs12: | |
6969 | free_page((unsigned long)vmx->nested.msr_bitmap); | |
6970 | ||
6971 | out_msr_bitmap: | |
6972 | return -ENOMEM; | |
ec378aee NHE |
6973 | } |
6974 | ||
6975 | /* | |
6976 | * Intel's VMX Instruction Reference specifies a common set of prerequisites | |
6977 | * for running VMX instructions (except VMXON, whose prerequisites are | |
6978 | * slightly different). It also specifies what exception to inject otherwise. | |
6979 | */ | |
6980 | static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) | |
6981 | { | |
6982 | struct kvm_segment cs; | |
6983 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6984 | ||
6985 | if (!vmx->nested.vmxon) { | |
6986 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6987 | return 0; | |
6988 | } | |
6989 | ||
6990 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
6991 | if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) || | |
6992 | (is_long_mode(vcpu) && !cs.l)) { | |
6993 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6994 | return 0; | |
6995 | } | |
6996 | ||
6997 | if (vmx_get_cpl(vcpu)) { | |
6998 | kvm_inject_gp(vcpu, 0); | |
6999 | return 0; | |
7000 | } | |
7001 | ||
7002 | return 1; | |
7003 | } | |
7004 | ||
e7953d7f AG |
7005 | static inline void nested_release_vmcs12(struct vcpu_vmx *vmx) |
7006 | { | |
9a2a05b9 PB |
7007 | if (vmx->nested.current_vmptr == -1ull) |
7008 | return; | |
7009 | ||
7010 | /* current_vmptr and current_vmcs12 are always set/reset together */ | |
7011 | if (WARN_ON(vmx->nested.current_vmcs12 == NULL)) | |
7012 | return; | |
7013 | ||
012f83cb | 7014 | if (enable_shadow_vmcs) { |
9a2a05b9 PB |
7015 | /* copy to memory all shadowed fields in case |
7016 | they were modified */ | |
7017 | copy_shadow_to_vmcs12(vmx); | |
7018 | vmx->nested.sync_shadow_vmcs = false; | |
7ec36296 XG |
7019 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, |
7020 | SECONDARY_EXEC_SHADOW_VMCS); | |
9a2a05b9 | 7021 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
012f83cb | 7022 | } |
705699a1 | 7023 | vmx->nested.posted_intr_nv = -1; |
4f2777bc DM |
7024 | |
7025 | /* Flush VMCS12 to guest memory */ | |
7026 | memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12, | |
7027 | VMCS12_SIZE); | |
7028 | ||
e7953d7f AG |
7029 | kunmap(vmx->nested.current_vmcs12_page); |
7030 | nested_release_page(vmx->nested.current_vmcs12_page); | |
9a2a05b9 PB |
7031 | vmx->nested.current_vmptr = -1ull; |
7032 | vmx->nested.current_vmcs12 = NULL; | |
e7953d7f AG |
7033 | } |
7034 | ||
ec378aee NHE |
7035 | /* |
7036 | * Free whatever needs to be freed from vmx->nested when L1 goes down, or | |
7037 | * just stops using VMX. | |
7038 | */ | |
7039 | static void free_nested(struct vcpu_vmx *vmx) | |
7040 | { | |
7041 | if (!vmx->nested.vmxon) | |
7042 | return; | |
9a2a05b9 | 7043 | |
ec378aee | 7044 | vmx->nested.vmxon = false; |
5c614b35 | 7045 | free_vpid(vmx->nested.vpid02); |
9a2a05b9 | 7046 | nested_release_vmcs12(vmx); |
d048c098 RK |
7047 | if (vmx->nested.msr_bitmap) { |
7048 | free_page((unsigned long)vmx->nested.msr_bitmap); | |
7049 | vmx->nested.msr_bitmap = NULL; | |
7050 | } | |
355f4fb1 JM |
7051 | if (enable_shadow_vmcs) { |
7052 | vmcs_clear(vmx->vmcs01.shadow_vmcs); | |
7053 | free_vmcs(vmx->vmcs01.shadow_vmcs); | |
7054 | vmx->vmcs01.shadow_vmcs = NULL; | |
7055 | } | |
4f2777bc | 7056 | kfree(vmx->nested.cached_vmcs12); |
fe3ef05c NHE |
7057 | /* Unpin physical memory we referred to in current vmcs02 */ |
7058 | if (vmx->nested.apic_access_page) { | |
7059 | nested_release_page(vmx->nested.apic_access_page); | |
48d89b92 | 7060 | vmx->nested.apic_access_page = NULL; |
fe3ef05c | 7061 | } |
a7c0b07d WL |
7062 | if (vmx->nested.virtual_apic_page) { |
7063 | nested_release_page(vmx->nested.virtual_apic_page); | |
48d89b92 | 7064 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 7065 | } |
705699a1 WV |
7066 | if (vmx->nested.pi_desc_page) { |
7067 | kunmap(vmx->nested.pi_desc_page); | |
7068 | nested_release_page(vmx->nested.pi_desc_page); | |
7069 | vmx->nested.pi_desc_page = NULL; | |
7070 | vmx->nested.pi_desc = NULL; | |
7071 | } | |
ff2f6fe9 NHE |
7072 | |
7073 | nested_free_all_saved_vmcss(vmx); | |
ec378aee NHE |
7074 | } |
7075 | ||
7076 | /* Emulate the VMXOFF instruction */ | |
7077 | static int handle_vmoff(struct kvm_vcpu *vcpu) | |
7078 | { | |
7079 | if (!nested_vmx_check_permission(vcpu)) | |
7080 | return 1; | |
7081 | free_nested(to_vmx(vcpu)); | |
7082 | skip_emulated_instruction(vcpu); | |
a25eb114 | 7083 | nested_vmx_succeed(vcpu); |
ec378aee NHE |
7084 | return 1; |
7085 | } | |
7086 | ||
27d6c865 NHE |
7087 | /* Emulate the VMCLEAR instruction */ |
7088 | static int handle_vmclear(struct kvm_vcpu *vcpu) | |
7089 | { | |
7090 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
27d6c865 NHE |
7091 | gpa_t vmptr; |
7092 | struct vmcs12 *vmcs12; | |
7093 | struct page *page; | |
27d6c865 NHE |
7094 | |
7095 | if (!nested_vmx_check_permission(vcpu)) | |
7096 | return 1; | |
7097 | ||
4291b588 | 7098 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr)) |
27d6c865 | 7099 | return 1; |
27d6c865 | 7100 | |
9a2a05b9 | 7101 | if (vmptr == vmx->nested.current_vmptr) |
e7953d7f | 7102 | nested_release_vmcs12(vmx); |
27d6c865 NHE |
7103 | |
7104 | page = nested_get_page(vcpu, vmptr); | |
7105 | if (page == NULL) { | |
7106 | /* | |
7107 | * For accurate processor emulation, VMCLEAR beyond available | |
7108 | * physical memory should do nothing at all. However, it is | |
7109 | * possible that a nested vmx bug, not a guest hypervisor bug, | |
7110 | * resulted in this case, so let's shut down before doing any | |
7111 | * more damage: | |
7112 | */ | |
7113 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
7114 | return 1; | |
7115 | } | |
7116 | vmcs12 = kmap(page); | |
7117 | vmcs12->launch_state = 0; | |
7118 | kunmap(page); | |
7119 | nested_release_page(page); | |
7120 | ||
7121 | nested_free_vmcs02(vmx, vmptr); | |
7122 | ||
7123 | skip_emulated_instruction(vcpu); | |
7124 | nested_vmx_succeed(vcpu); | |
7125 | return 1; | |
7126 | } | |
7127 | ||
cd232ad0 NHE |
7128 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch); |
7129 | ||
7130 | /* Emulate the VMLAUNCH instruction */ | |
7131 | static int handle_vmlaunch(struct kvm_vcpu *vcpu) | |
7132 | { | |
7133 | return nested_vmx_run(vcpu, true); | |
7134 | } | |
7135 | ||
7136 | /* Emulate the VMRESUME instruction */ | |
7137 | static int handle_vmresume(struct kvm_vcpu *vcpu) | |
7138 | { | |
7139 | ||
7140 | return nested_vmx_run(vcpu, false); | |
7141 | } | |
7142 | ||
49f705c5 NHE |
7143 | enum vmcs_field_type { |
7144 | VMCS_FIELD_TYPE_U16 = 0, | |
7145 | VMCS_FIELD_TYPE_U64 = 1, | |
7146 | VMCS_FIELD_TYPE_U32 = 2, | |
7147 | VMCS_FIELD_TYPE_NATURAL_WIDTH = 3 | |
7148 | }; | |
7149 | ||
7150 | static inline int vmcs_field_type(unsigned long field) | |
7151 | { | |
7152 | if (0x1 & field) /* the *_HIGH fields are all 32 bit */ | |
7153 | return VMCS_FIELD_TYPE_U32; | |
7154 | return (field >> 13) & 0x3 ; | |
7155 | } | |
7156 | ||
7157 | static inline int vmcs_field_readonly(unsigned long field) | |
7158 | { | |
7159 | return (((field >> 10) & 0x3) == 1); | |
7160 | } | |
7161 | ||
7162 | /* | |
7163 | * Read a vmcs12 field. Since these can have varying lengths and we return | |
7164 | * one type, we chose the biggest type (u64) and zero-extend the return value | |
7165 | * to that size. Note that the caller, handle_vmread, might need to use only | |
7166 | * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of | |
7167 | * 64-bit fields are to be returned). | |
7168 | */ | |
a2ae9df7 PB |
7169 | static inline int vmcs12_read_any(struct kvm_vcpu *vcpu, |
7170 | unsigned long field, u64 *ret) | |
49f705c5 NHE |
7171 | { |
7172 | short offset = vmcs_field_to_offset(field); | |
7173 | char *p; | |
7174 | ||
7175 | if (offset < 0) | |
a2ae9df7 | 7176 | return offset; |
49f705c5 NHE |
7177 | |
7178 | p = ((char *)(get_vmcs12(vcpu))) + offset; | |
7179 | ||
7180 | switch (vmcs_field_type(field)) { | |
7181 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7182 | *ret = *((natural_width *)p); | |
a2ae9df7 | 7183 | return 0; |
49f705c5 NHE |
7184 | case VMCS_FIELD_TYPE_U16: |
7185 | *ret = *((u16 *)p); | |
a2ae9df7 | 7186 | return 0; |
49f705c5 NHE |
7187 | case VMCS_FIELD_TYPE_U32: |
7188 | *ret = *((u32 *)p); | |
a2ae9df7 | 7189 | return 0; |
49f705c5 NHE |
7190 | case VMCS_FIELD_TYPE_U64: |
7191 | *ret = *((u64 *)p); | |
a2ae9df7 | 7192 | return 0; |
49f705c5 | 7193 | default: |
a2ae9df7 PB |
7194 | WARN_ON(1); |
7195 | return -ENOENT; | |
49f705c5 NHE |
7196 | } |
7197 | } | |
7198 | ||
20b97fea | 7199 | |
a2ae9df7 PB |
7200 | static inline int vmcs12_write_any(struct kvm_vcpu *vcpu, |
7201 | unsigned long field, u64 field_value){ | |
20b97fea AG |
7202 | short offset = vmcs_field_to_offset(field); |
7203 | char *p = ((char *) get_vmcs12(vcpu)) + offset; | |
7204 | if (offset < 0) | |
a2ae9df7 | 7205 | return offset; |
20b97fea AG |
7206 | |
7207 | switch (vmcs_field_type(field)) { | |
7208 | case VMCS_FIELD_TYPE_U16: | |
7209 | *(u16 *)p = field_value; | |
a2ae9df7 | 7210 | return 0; |
20b97fea AG |
7211 | case VMCS_FIELD_TYPE_U32: |
7212 | *(u32 *)p = field_value; | |
a2ae9df7 | 7213 | return 0; |
20b97fea AG |
7214 | case VMCS_FIELD_TYPE_U64: |
7215 | *(u64 *)p = field_value; | |
a2ae9df7 | 7216 | return 0; |
20b97fea AG |
7217 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: |
7218 | *(natural_width *)p = field_value; | |
a2ae9df7 | 7219 | return 0; |
20b97fea | 7220 | default: |
a2ae9df7 PB |
7221 | WARN_ON(1); |
7222 | return -ENOENT; | |
20b97fea AG |
7223 | } |
7224 | ||
7225 | } | |
7226 | ||
16f5b903 AG |
7227 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) |
7228 | { | |
7229 | int i; | |
7230 | unsigned long field; | |
7231 | u64 field_value; | |
355f4fb1 | 7232 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c2bae893 MK |
7233 | const unsigned long *fields = shadow_read_write_fields; |
7234 | const int num_fields = max_shadow_read_write_fields; | |
16f5b903 | 7235 | |
282da870 JK |
7236 | preempt_disable(); |
7237 | ||
16f5b903 AG |
7238 | vmcs_load(shadow_vmcs); |
7239 | ||
7240 | for (i = 0; i < num_fields; i++) { | |
7241 | field = fields[i]; | |
7242 | switch (vmcs_field_type(field)) { | |
7243 | case VMCS_FIELD_TYPE_U16: | |
7244 | field_value = vmcs_read16(field); | |
7245 | break; | |
7246 | case VMCS_FIELD_TYPE_U32: | |
7247 | field_value = vmcs_read32(field); | |
7248 | break; | |
7249 | case VMCS_FIELD_TYPE_U64: | |
7250 | field_value = vmcs_read64(field); | |
7251 | break; | |
7252 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7253 | field_value = vmcs_readl(field); | |
7254 | break; | |
a2ae9df7 PB |
7255 | default: |
7256 | WARN_ON(1); | |
7257 | continue; | |
16f5b903 AG |
7258 | } |
7259 | vmcs12_write_any(&vmx->vcpu, field, field_value); | |
7260 | } | |
7261 | ||
7262 | vmcs_clear(shadow_vmcs); | |
7263 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
282da870 JK |
7264 | |
7265 | preempt_enable(); | |
16f5b903 AG |
7266 | } |
7267 | ||
c3114420 AG |
7268 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) |
7269 | { | |
c2bae893 MK |
7270 | const unsigned long *fields[] = { |
7271 | shadow_read_write_fields, | |
7272 | shadow_read_only_fields | |
c3114420 | 7273 | }; |
c2bae893 | 7274 | const int max_fields[] = { |
c3114420 AG |
7275 | max_shadow_read_write_fields, |
7276 | max_shadow_read_only_fields | |
7277 | }; | |
7278 | int i, q; | |
7279 | unsigned long field; | |
7280 | u64 field_value = 0; | |
355f4fb1 | 7281 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c3114420 AG |
7282 | |
7283 | vmcs_load(shadow_vmcs); | |
7284 | ||
c2bae893 | 7285 | for (q = 0; q < ARRAY_SIZE(fields); q++) { |
c3114420 AG |
7286 | for (i = 0; i < max_fields[q]; i++) { |
7287 | field = fields[q][i]; | |
7288 | vmcs12_read_any(&vmx->vcpu, field, &field_value); | |
7289 | ||
7290 | switch (vmcs_field_type(field)) { | |
7291 | case VMCS_FIELD_TYPE_U16: | |
7292 | vmcs_write16(field, (u16)field_value); | |
7293 | break; | |
7294 | case VMCS_FIELD_TYPE_U32: | |
7295 | vmcs_write32(field, (u32)field_value); | |
7296 | break; | |
7297 | case VMCS_FIELD_TYPE_U64: | |
7298 | vmcs_write64(field, (u64)field_value); | |
7299 | break; | |
7300 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7301 | vmcs_writel(field, (long)field_value); | |
7302 | break; | |
a2ae9df7 PB |
7303 | default: |
7304 | WARN_ON(1); | |
7305 | break; | |
c3114420 AG |
7306 | } |
7307 | } | |
7308 | } | |
7309 | ||
7310 | vmcs_clear(shadow_vmcs); | |
7311 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
7312 | } | |
7313 | ||
49f705c5 NHE |
7314 | /* |
7315 | * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was | |
7316 | * used before) all generate the same failure when it is missing. | |
7317 | */ | |
7318 | static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu) | |
7319 | { | |
7320 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7321 | if (vmx->nested.current_vmptr == -1ull) { | |
7322 | nested_vmx_failInvalid(vcpu); | |
7323 | skip_emulated_instruction(vcpu); | |
7324 | return 0; | |
7325 | } | |
7326 | return 1; | |
7327 | } | |
7328 | ||
7329 | static int handle_vmread(struct kvm_vcpu *vcpu) | |
7330 | { | |
7331 | unsigned long field; | |
7332 | u64 field_value; | |
7333 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7334 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7335 | gva_t gva = 0; | |
7336 | ||
7337 | if (!nested_vmx_check_permission(vcpu) || | |
7338 | !nested_vmx_check_vmcs12(vcpu)) | |
7339 | return 1; | |
7340 | ||
7341 | /* Decode instruction info and find the field to read */ | |
27e6fb5d | 7342 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 | 7343 | /* Read the field, zero-extended to a u64 field_value */ |
a2ae9df7 | 7344 | if (vmcs12_read_any(vcpu, field, &field_value) < 0) { |
49f705c5 NHE |
7345 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
7346 | skip_emulated_instruction(vcpu); | |
7347 | return 1; | |
7348 | } | |
7349 | /* | |
7350 | * Now copy part of this value to register or memory, as requested. | |
7351 | * Note that the number of bits actually copied is 32 or 64 depending | |
7352 | * on the guest's mode (32 or 64 bit), not on the given field's length. | |
7353 | */ | |
7354 | if (vmx_instruction_info & (1u << 10)) { | |
27e6fb5d | 7355 | kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf), |
49f705c5 NHE |
7356 | field_value); |
7357 | } else { | |
7358 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7359 | vmx_instruction_info, true, &gva)) |
49f705c5 NHE |
7360 | return 1; |
7361 | /* _system ok, as nested_vmx_check_permission verified cpl=0 */ | |
7362 | kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva, | |
7363 | &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL); | |
7364 | } | |
7365 | ||
7366 | nested_vmx_succeed(vcpu); | |
7367 | skip_emulated_instruction(vcpu); | |
7368 | return 1; | |
7369 | } | |
7370 | ||
7371 | ||
7372 | static int handle_vmwrite(struct kvm_vcpu *vcpu) | |
7373 | { | |
7374 | unsigned long field; | |
7375 | gva_t gva; | |
7376 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7377 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
49f705c5 NHE |
7378 | /* The value to write might be 32 or 64 bits, depending on L1's long |
7379 | * mode, and eventually we need to write that into a field of several | |
7380 | * possible lengths. The code below first zero-extends the value to 64 | |
6a6256f9 | 7381 | * bit (field_value), and then copies only the appropriate number of |
49f705c5 NHE |
7382 | * bits into the vmcs12 field. |
7383 | */ | |
7384 | u64 field_value = 0; | |
7385 | struct x86_exception e; | |
7386 | ||
7387 | if (!nested_vmx_check_permission(vcpu) || | |
7388 | !nested_vmx_check_vmcs12(vcpu)) | |
7389 | return 1; | |
7390 | ||
7391 | if (vmx_instruction_info & (1u << 10)) | |
27e6fb5d | 7392 | field_value = kvm_register_readl(vcpu, |
49f705c5 NHE |
7393 | (((vmx_instruction_info) >> 3) & 0xf)); |
7394 | else { | |
7395 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7396 | vmx_instruction_info, false, &gva)) |
49f705c5 NHE |
7397 | return 1; |
7398 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, | |
27e6fb5d | 7399 | &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) { |
49f705c5 NHE |
7400 | kvm_inject_page_fault(vcpu, &e); |
7401 | return 1; | |
7402 | } | |
7403 | } | |
7404 | ||
7405 | ||
27e6fb5d | 7406 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 NHE |
7407 | if (vmcs_field_readonly(field)) { |
7408 | nested_vmx_failValid(vcpu, | |
7409 | VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); | |
7410 | skip_emulated_instruction(vcpu); | |
7411 | return 1; | |
7412 | } | |
7413 | ||
a2ae9df7 | 7414 | if (vmcs12_write_any(vcpu, field, field_value) < 0) { |
49f705c5 NHE |
7415 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
7416 | skip_emulated_instruction(vcpu); | |
7417 | return 1; | |
7418 | } | |
7419 | ||
7420 | nested_vmx_succeed(vcpu); | |
7421 | skip_emulated_instruction(vcpu); | |
7422 | return 1; | |
7423 | } | |
7424 | ||
63846663 NHE |
7425 | /* Emulate the VMPTRLD instruction */ |
7426 | static int handle_vmptrld(struct kvm_vcpu *vcpu) | |
7427 | { | |
7428 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
63846663 | 7429 | gpa_t vmptr; |
63846663 NHE |
7430 | |
7431 | if (!nested_vmx_check_permission(vcpu)) | |
7432 | return 1; | |
7433 | ||
4291b588 | 7434 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr)) |
63846663 | 7435 | return 1; |
63846663 NHE |
7436 | |
7437 | if (vmx->nested.current_vmptr != vmptr) { | |
7438 | struct vmcs12 *new_vmcs12; | |
7439 | struct page *page; | |
7440 | page = nested_get_page(vcpu, vmptr); | |
7441 | if (page == NULL) { | |
7442 | nested_vmx_failInvalid(vcpu); | |
7443 | skip_emulated_instruction(vcpu); | |
7444 | return 1; | |
7445 | } | |
7446 | new_vmcs12 = kmap(page); | |
7447 | if (new_vmcs12->revision_id != VMCS12_REVISION) { | |
7448 | kunmap(page); | |
7449 | nested_release_page_clean(page); | |
7450 | nested_vmx_failValid(vcpu, | |
7451 | VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); | |
7452 | skip_emulated_instruction(vcpu); | |
7453 | return 1; | |
7454 | } | |
63846663 | 7455 | |
9a2a05b9 | 7456 | nested_release_vmcs12(vmx); |
63846663 NHE |
7457 | vmx->nested.current_vmptr = vmptr; |
7458 | vmx->nested.current_vmcs12 = new_vmcs12; | |
7459 | vmx->nested.current_vmcs12_page = page; | |
4f2777bc DM |
7460 | /* |
7461 | * Load VMCS12 from guest memory since it is not already | |
7462 | * cached. | |
7463 | */ | |
7464 | memcpy(vmx->nested.cached_vmcs12, | |
7465 | vmx->nested.current_vmcs12, VMCS12_SIZE); | |
7466 | ||
012f83cb | 7467 | if (enable_shadow_vmcs) { |
7ec36296 XG |
7468 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, |
7469 | SECONDARY_EXEC_SHADOW_VMCS); | |
8a1b9dd0 | 7470 | vmcs_write64(VMCS_LINK_POINTER, |
355f4fb1 | 7471 | __pa(vmx->vmcs01.shadow_vmcs)); |
012f83cb AG |
7472 | vmx->nested.sync_shadow_vmcs = true; |
7473 | } | |
63846663 NHE |
7474 | } |
7475 | ||
7476 | nested_vmx_succeed(vcpu); | |
7477 | skip_emulated_instruction(vcpu); | |
7478 | return 1; | |
7479 | } | |
7480 | ||
6a4d7550 NHE |
7481 | /* Emulate the VMPTRST instruction */ |
7482 | static int handle_vmptrst(struct kvm_vcpu *vcpu) | |
7483 | { | |
7484 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7485 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7486 | gva_t vmcs_gva; | |
7487 | struct x86_exception e; | |
7488 | ||
7489 | if (!nested_vmx_check_permission(vcpu)) | |
7490 | return 1; | |
7491 | ||
7492 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7493 | vmx_instruction_info, true, &vmcs_gva)) |
6a4d7550 NHE |
7494 | return 1; |
7495 | /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */ | |
7496 | if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva, | |
7497 | (void *)&to_vmx(vcpu)->nested.current_vmptr, | |
7498 | sizeof(u64), &e)) { | |
7499 | kvm_inject_page_fault(vcpu, &e); | |
7500 | return 1; | |
7501 | } | |
7502 | nested_vmx_succeed(vcpu); | |
7503 | skip_emulated_instruction(vcpu); | |
7504 | return 1; | |
7505 | } | |
7506 | ||
bfd0a56b NHE |
7507 | /* Emulate the INVEPT instruction */ |
7508 | static int handle_invept(struct kvm_vcpu *vcpu) | |
7509 | { | |
b9c237bb | 7510 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
bfd0a56b NHE |
7511 | u32 vmx_instruction_info, types; |
7512 | unsigned long type; | |
7513 | gva_t gva; | |
7514 | struct x86_exception e; | |
7515 | struct { | |
7516 | u64 eptp, gpa; | |
7517 | } operand; | |
bfd0a56b | 7518 | |
b9c237bb WV |
7519 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & |
7520 | SECONDARY_EXEC_ENABLE_EPT) || | |
7521 | !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) { | |
bfd0a56b NHE |
7522 | kvm_queue_exception(vcpu, UD_VECTOR); |
7523 | return 1; | |
7524 | } | |
7525 | ||
7526 | if (!nested_vmx_check_permission(vcpu)) | |
7527 | return 1; | |
7528 | ||
7529 | if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) { | |
7530 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7531 | return 1; | |
7532 | } | |
7533 | ||
7534 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
27e6fb5d | 7535 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); |
bfd0a56b | 7536 | |
b9c237bb | 7537 | types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; |
bfd0a56b | 7538 | |
85c856b3 | 7539 | if (type >= 32 || !(types & (1 << type))) { |
bfd0a56b NHE |
7540 | nested_vmx_failValid(vcpu, |
7541 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
2849eb4f | 7542 | skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
7543 | return 1; |
7544 | } | |
7545 | ||
7546 | /* According to the Intel VMX instruction reference, the memory | |
7547 | * operand is read even if it isn't needed (e.g., for type==global) | |
7548 | */ | |
7549 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7550 | vmx_instruction_info, false, &gva)) |
bfd0a56b NHE |
7551 | return 1; |
7552 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand, | |
7553 | sizeof(operand), &e)) { | |
7554 | kvm_inject_page_fault(vcpu, &e); | |
7555 | return 1; | |
7556 | } | |
7557 | ||
7558 | switch (type) { | |
bfd0a56b | 7559 | case VMX_EPT_EXTENT_GLOBAL: |
45e11817 BD |
7560 | /* |
7561 | * TODO: track mappings and invalidate | |
7562 | * single context requests appropriately | |
7563 | */ | |
7564 | case VMX_EPT_EXTENT_CONTEXT: | |
bfd0a56b | 7565 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 7566 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
bfd0a56b NHE |
7567 | nested_vmx_succeed(vcpu); |
7568 | break; | |
7569 | default: | |
7570 | BUG_ON(1); | |
7571 | break; | |
7572 | } | |
7573 | ||
7574 | skip_emulated_instruction(vcpu); | |
7575 | return 1; | |
7576 | } | |
7577 | ||
a642fc30 PM |
7578 | static int handle_invvpid(struct kvm_vcpu *vcpu) |
7579 | { | |
99b83ac8 WL |
7580 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7581 | u32 vmx_instruction_info; | |
7582 | unsigned long type, types; | |
7583 | gva_t gva; | |
7584 | struct x86_exception e; | |
7585 | int vpid; | |
7586 | ||
7587 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & | |
7588 | SECONDARY_EXEC_ENABLE_VPID) || | |
7589 | !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) { | |
7590 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7591 | return 1; | |
7592 | } | |
7593 | ||
7594 | if (!nested_vmx_check_permission(vcpu)) | |
7595 | return 1; | |
7596 | ||
7597 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7598 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); | |
7599 | ||
7600 | types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7; | |
7601 | ||
85c856b3 | 7602 | if (type >= 32 || !(types & (1 << type))) { |
99b83ac8 WL |
7603 | nested_vmx_failValid(vcpu, |
7604 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
f6870ee9 | 7605 | skip_emulated_instruction(vcpu); |
99b83ac8 WL |
7606 | return 1; |
7607 | } | |
7608 | ||
7609 | /* according to the intel vmx instruction reference, the memory | |
7610 | * operand is read even if it isn't needed (e.g., for type==global) | |
7611 | */ | |
7612 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
7613 | vmx_instruction_info, false, &gva)) | |
7614 | return 1; | |
7615 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid, | |
7616 | sizeof(u32), &e)) { | |
7617 | kvm_inject_page_fault(vcpu, &e); | |
7618 | return 1; | |
7619 | } | |
7620 | ||
7621 | switch (type) { | |
ef697a71 PB |
7622 | case VMX_VPID_EXTENT_SINGLE_CONTEXT: |
7623 | /* | |
7624 | * Old versions of KVM use the single-context version so we | |
7625 | * have to support it; just treat it the same as all-context. | |
7626 | */ | |
99b83ac8 | 7627 | case VMX_VPID_EXTENT_ALL_CONTEXT: |
5c614b35 | 7628 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02); |
99b83ac8 WL |
7629 | nested_vmx_succeed(vcpu); |
7630 | break; | |
7631 | default: | |
ef697a71 | 7632 | /* Trap individual address invalidation invvpid calls */ |
99b83ac8 WL |
7633 | BUG_ON(1); |
7634 | break; | |
7635 | } | |
7636 | ||
7637 | skip_emulated_instruction(vcpu); | |
a642fc30 PM |
7638 | return 1; |
7639 | } | |
7640 | ||
843e4330 KH |
7641 | static int handle_pml_full(struct kvm_vcpu *vcpu) |
7642 | { | |
7643 | unsigned long exit_qualification; | |
7644 | ||
7645 | trace_kvm_pml_full(vcpu->vcpu_id); | |
7646 | ||
7647 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7648 | ||
7649 | /* | |
7650 | * PML buffer FULL happened while executing iret from NMI, | |
7651 | * "blocked by NMI" bit has to be set before next VM entry. | |
7652 | */ | |
7653 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && | |
7654 | cpu_has_virtual_nmis() && | |
7655 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) | |
7656 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
7657 | GUEST_INTR_STATE_NMI); | |
7658 | ||
7659 | /* | |
7660 | * PML buffer already flushed at beginning of VMEXIT. Nothing to do | |
7661 | * here.., and there's no userspace involvement needed for PML. | |
7662 | */ | |
7663 | return 1; | |
7664 | } | |
7665 | ||
64672c95 YJ |
7666 | static int handle_preemption_timer(struct kvm_vcpu *vcpu) |
7667 | { | |
7668 | kvm_lapic_expired_hv_timer(vcpu); | |
7669 | return 1; | |
7670 | } | |
7671 | ||
6aa8b732 AK |
7672 | /* |
7673 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
7674 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
7675 | * to be done to userspace and return 0. | |
7676 | */ | |
772e0318 | 7677 | static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
7678 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
7679 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 7680 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 7681 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 7682 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
7683 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
7684 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
7685 | [EXIT_REASON_CPUID] = handle_cpuid, | |
7686 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
7687 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
7688 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
7689 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 7690 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 7691 | [EXIT_REASON_INVLPG] = handle_invlpg, |
fee84b07 | 7692 | [EXIT_REASON_RDPMC] = handle_rdpmc, |
c21415e8 | 7693 | [EXIT_REASON_VMCALL] = handle_vmcall, |
27d6c865 | 7694 | [EXIT_REASON_VMCLEAR] = handle_vmclear, |
cd232ad0 | 7695 | [EXIT_REASON_VMLAUNCH] = handle_vmlaunch, |
63846663 | 7696 | [EXIT_REASON_VMPTRLD] = handle_vmptrld, |
6a4d7550 | 7697 | [EXIT_REASON_VMPTRST] = handle_vmptrst, |
49f705c5 | 7698 | [EXIT_REASON_VMREAD] = handle_vmread, |
cd232ad0 | 7699 | [EXIT_REASON_VMRESUME] = handle_vmresume, |
49f705c5 | 7700 | [EXIT_REASON_VMWRITE] = handle_vmwrite, |
ec378aee NHE |
7701 | [EXIT_REASON_VMOFF] = handle_vmoff, |
7702 | [EXIT_REASON_VMON] = handle_vmon, | |
f78e0e2e SY |
7703 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
7704 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
83d4c286 | 7705 | [EXIT_REASON_APIC_WRITE] = handle_apic_write, |
c7c9c56c | 7706 | [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, |
e5edaa01 | 7707 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 7708 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 7709 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 7710 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
7711 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
7712 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 7713 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
87c00572 | 7714 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, |
5f3d45e7 | 7715 | [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, |
87c00572 | 7716 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, |
bfd0a56b | 7717 | [EXIT_REASON_INVEPT] = handle_invept, |
a642fc30 | 7718 | [EXIT_REASON_INVVPID] = handle_invvpid, |
f53cd63c WL |
7719 | [EXIT_REASON_XSAVES] = handle_xsaves, |
7720 | [EXIT_REASON_XRSTORS] = handle_xrstors, | |
843e4330 | 7721 | [EXIT_REASON_PML_FULL] = handle_pml_full, |
64672c95 | 7722 | [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, |
6aa8b732 AK |
7723 | }; |
7724 | ||
7725 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 7726 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 7727 | |
908a7bdd JK |
7728 | static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, |
7729 | struct vmcs12 *vmcs12) | |
7730 | { | |
7731 | unsigned long exit_qualification; | |
7732 | gpa_t bitmap, last_bitmap; | |
7733 | unsigned int port; | |
7734 | int size; | |
7735 | u8 b; | |
7736 | ||
908a7bdd | 7737 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) |
2f0a6397 | 7738 | return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); |
908a7bdd JK |
7739 | |
7740 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7741 | ||
7742 | port = exit_qualification >> 16; | |
7743 | size = (exit_qualification & 7) + 1; | |
7744 | ||
7745 | last_bitmap = (gpa_t)-1; | |
7746 | b = -1; | |
7747 | ||
7748 | while (size > 0) { | |
7749 | if (port < 0x8000) | |
7750 | bitmap = vmcs12->io_bitmap_a; | |
7751 | else if (port < 0x10000) | |
7752 | bitmap = vmcs12->io_bitmap_b; | |
7753 | else | |
1d804d07 | 7754 | return true; |
908a7bdd JK |
7755 | bitmap += (port & 0x7fff) / 8; |
7756 | ||
7757 | if (last_bitmap != bitmap) | |
54bf36aa | 7758 | if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1)) |
1d804d07 | 7759 | return true; |
908a7bdd | 7760 | if (b & (1 << (port & 7))) |
1d804d07 | 7761 | return true; |
908a7bdd JK |
7762 | |
7763 | port++; | |
7764 | size--; | |
7765 | last_bitmap = bitmap; | |
7766 | } | |
7767 | ||
1d804d07 | 7768 | return false; |
908a7bdd JK |
7769 | } |
7770 | ||
644d711a NHE |
7771 | /* |
7772 | * Return 1 if we should exit from L2 to L1 to handle an MSR access access, | |
7773 | * rather than handle it ourselves in L0. I.e., check whether L1 expressed | |
7774 | * disinterest in the current event (read or write a specific MSR) by using an | |
7775 | * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. | |
7776 | */ | |
7777 | static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, | |
7778 | struct vmcs12 *vmcs12, u32 exit_reason) | |
7779 | { | |
7780 | u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
7781 | gpa_t bitmap; | |
7782 | ||
cbd29cb6 | 7783 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
1d804d07 | 7784 | return true; |
644d711a NHE |
7785 | |
7786 | /* | |
7787 | * The MSR_BITMAP page is divided into four 1024-byte bitmaps, | |
7788 | * for the four combinations of read/write and low/high MSR numbers. | |
7789 | * First we need to figure out which of the four to use: | |
7790 | */ | |
7791 | bitmap = vmcs12->msr_bitmap; | |
7792 | if (exit_reason == EXIT_REASON_MSR_WRITE) | |
7793 | bitmap += 2048; | |
7794 | if (msr_index >= 0xc0000000) { | |
7795 | msr_index -= 0xc0000000; | |
7796 | bitmap += 1024; | |
7797 | } | |
7798 | ||
7799 | /* Then read the msr_index'th bit from this bitmap: */ | |
7800 | if (msr_index < 1024*8) { | |
7801 | unsigned char b; | |
54bf36aa | 7802 | if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1)) |
1d804d07 | 7803 | return true; |
644d711a NHE |
7804 | return 1 & (b >> (msr_index & 7)); |
7805 | } else | |
1d804d07 | 7806 | return true; /* let L1 handle the wrong parameter */ |
644d711a NHE |
7807 | } |
7808 | ||
7809 | /* | |
7810 | * Return 1 if we should exit from L2 to L1 to handle a CR access exit, | |
7811 | * rather than handle it ourselves in L0. I.e., check if L1 wanted to | |
7812 | * intercept (via guest_host_mask etc.) the current event. | |
7813 | */ | |
7814 | static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, | |
7815 | struct vmcs12 *vmcs12) | |
7816 | { | |
7817 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7818 | int cr = exit_qualification & 15; | |
7819 | int reg = (exit_qualification >> 8) & 15; | |
1e32c079 | 7820 | unsigned long val = kvm_register_readl(vcpu, reg); |
644d711a NHE |
7821 | |
7822 | switch ((exit_qualification >> 4) & 3) { | |
7823 | case 0: /* mov to cr */ | |
7824 | switch (cr) { | |
7825 | case 0: | |
7826 | if (vmcs12->cr0_guest_host_mask & | |
7827 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 7828 | return true; |
644d711a NHE |
7829 | break; |
7830 | case 3: | |
7831 | if ((vmcs12->cr3_target_count >= 1 && | |
7832 | vmcs12->cr3_target_value0 == val) || | |
7833 | (vmcs12->cr3_target_count >= 2 && | |
7834 | vmcs12->cr3_target_value1 == val) || | |
7835 | (vmcs12->cr3_target_count >= 3 && | |
7836 | vmcs12->cr3_target_value2 == val) || | |
7837 | (vmcs12->cr3_target_count >= 4 && | |
7838 | vmcs12->cr3_target_value3 == val)) | |
1d804d07 | 7839 | return false; |
644d711a | 7840 | if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) |
1d804d07 | 7841 | return true; |
644d711a NHE |
7842 | break; |
7843 | case 4: | |
7844 | if (vmcs12->cr4_guest_host_mask & | |
7845 | (vmcs12->cr4_read_shadow ^ val)) | |
1d804d07 | 7846 | return true; |
644d711a NHE |
7847 | break; |
7848 | case 8: | |
7849 | if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) | |
1d804d07 | 7850 | return true; |
644d711a NHE |
7851 | break; |
7852 | } | |
7853 | break; | |
7854 | case 2: /* clts */ | |
7855 | if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && | |
7856 | (vmcs12->cr0_read_shadow & X86_CR0_TS)) | |
1d804d07 | 7857 | return true; |
644d711a NHE |
7858 | break; |
7859 | case 1: /* mov from cr */ | |
7860 | switch (cr) { | |
7861 | case 3: | |
7862 | if (vmcs12->cpu_based_vm_exec_control & | |
7863 | CPU_BASED_CR3_STORE_EXITING) | |
1d804d07 | 7864 | return true; |
644d711a NHE |
7865 | break; |
7866 | case 8: | |
7867 | if (vmcs12->cpu_based_vm_exec_control & | |
7868 | CPU_BASED_CR8_STORE_EXITING) | |
1d804d07 | 7869 | return true; |
644d711a NHE |
7870 | break; |
7871 | } | |
7872 | break; | |
7873 | case 3: /* lmsw */ | |
7874 | /* | |
7875 | * lmsw can change bits 1..3 of cr0, and only set bit 0 of | |
7876 | * cr0. Other attempted changes are ignored, with no exit. | |
7877 | */ | |
7878 | if (vmcs12->cr0_guest_host_mask & 0xe & | |
7879 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 7880 | return true; |
644d711a NHE |
7881 | if ((vmcs12->cr0_guest_host_mask & 0x1) && |
7882 | !(vmcs12->cr0_read_shadow & 0x1) && | |
7883 | (val & 0x1)) | |
1d804d07 | 7884 | return true; |
644d711a NHE |
7885 | break; |
7886 | } | |
1d804d07 | 7887 | return false; |
644d711a NHE |
7888 | } |
7889 | ||
7890 | /* | |
7891 | * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we | |
7892 | * should handle it ourselves in L0 (and then continue L2). Only call this | |
7893 | * when in is_guest_mode (L2). | |
7894 | */ | |
7895 | static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu) | |
7896 | { | |
644d711a NHE |
7897 | u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
7898 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7899 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
957c897e | 7900 | u32 exit_reason = vmx->exit_reason; |
644d711a | 7901 | |
542060ea JK |
7902 | trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason, |
7903 | vmcs_readl(EXIT_QUALIFICATION), | |
7904 | vmx->idt_vectoring_info, | |
7905 | intr_info, | |
7906 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
7907 | KVM_ISA_VMX); | |
7908 | ||
644d711a | 7909 | if (vmx->nested.nested_run_pending) |
1d804d07 | 7910 | return false; |
644d711a NHE |
7911 | |
7912 | if (unlikely(vmx->fail)) { | |
bd80158a JK |
7913 | pr_info_ratelimited("%s failed vm entry %x\n", __func__, |
7914 | vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1d804d07 | 7915 | return true; |
644d711a NHE |
7916 | } |
7917 | ||
7918 | switch (exit_reason) { | |
7919 | case EXIT_REASON_EXCEPTION_NMI: | |
7920 | if (!is_exception(intr_info)) | |
1d804d07 | 7921 | return false; |
644d711a NHE |
7922 | else if (is_page_fault(intr_info)) |
7923 | return enable_ept; | |
e504c909 | 7924 | else if (is_no_device(intr_info) && |
ccf9844e | 7925 | !(vmcs12->guest_cr0 & X86_CR0_TS)) |
1d804d07 | 7926 | return false; |
6f05485d JK |
7927 | else if (is_debug(intr_info) && |
7928 | vcpu->guest_debug & | |
7929 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
7930 | return false; | |
7931 | else if (is_breakpoint(intr_info) && | |
7932 | vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
7933 | return false; | |
644d711a NHE |
7934 | return vmcs12->exception_bitmap & |
7935 | (1u << (intr_info & INTR_INFO_VECTOR_MASK)); | |
7936 | case EXIT_REASON_EXTERNAL_INTERRUPT: | |
1d804d07 | 7937 | return false; |
644d711a | 7938 | case EXIT_REASON_TRIPLE_FAULT: |
1d804d07 | 7939 | return true; |
644d711a | 7940 | case EXIT_REASON_PENDING_INTERRUPT: |
3b656cf7 | 7941 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING); |
644d711a | 7942 | case EXIT_REASON_NMI_WINDOW: |
3b656cf7 | 7943 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING); |
644d711a | 7944 | case EXIT_REASON_TASK_SWITCH: |
1d804d07 | 7945 | return true; |
644d711a | 7946 | case EXIT_REASON_CPUID: |
bc613494 | 7947 | if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa) |
1d804d07 JP |
7948 | return false; |
7949 | return true; | |
644d711a NHE |
7950 | case EXIT_REASON_HLT: |
7951 | return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); | |
7952 | case EXIT_REASON_INVD: | |
1d804d07 | 7953 | return true; |
644d711a NHE |
7954 | case EXIT_REASON_INVLPG: |
7955 | return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
7956 | case EXIT_REASON_RDPMC: | |
7957 | return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); | |
b3a2a907 | 7958 | case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP: |
644d711a NHE |
7959 | return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); |
7960 | case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: | |
7961 | case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: | |
7962 | case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD: | |
7963 | case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE: | |
7964 | case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: | |
a642fc30 | 7965 | case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: |
644d711a NHE |
7966 | /* |
7967 | * VMX instructions trap unconditionally. This allows L1 to | |
7968 | * emulate them for its L2 guest, i.e., allows 3-level nesting! | |
7969 | */ | |
1d804d07 | 7970 | return true; |
644d711a NHE |
7971 | case EXIT_REASON_CR_ACCESS: |
7972 | return nested_vmx_exit_handled_cr(vcpu, vmcs12); | |
7973 | case EXIT_REASON_DR_ACCESS: | |
7974 | return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); | |
7975 | case EXIT_REASON_IO_INSTRUCTION: | |
908a7bdd | 7976 | return nested_vmx_exit_handled_io(vcpu, vmcs12); |
1b07304c PB |
7977 | case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR: |
7978 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC); | |
644d711a NHE |
7979 | case EXIT_REASON_MSR_READ: |
7980 | case EXIT_REASON_MSR_WRITE: | |
7981 | return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); | |
7982 | case EXIT_REASON_INVALID_STATE: | |
1d804d07 | 7983 | return true; |
644d711a NHE |
7984 | case EXIT_REASON_MWAIT_INSTRUCTION: |
7985 | return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); | |
5f3d45e7 MD |
7986 | case EXIT_REASON_MONITOR_TRAP_FLAG: |
7987 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); | |
644d711a NHE |
7988 | case EXIT_REASON_MONITOR_INSTRUCTION: |
7989 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); | |
7990 | case EXIT_REASON_PAUSE_INSTRUCTION: | |
7991 | return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || | |
7992 | nested_cpu_has2(vmcs12, | |
7993 | SECONDARY_EXEC_PAUSE_LOOP_EXITING); | |
7994 | case EXIT_REASON_MCE_DURING_VMENTRY: | |
1d804d07 | 7995 | return false; |
644d711a | 7996 | case EXIT_REASON_TPR_BELOW_THRESHOLD: |
a7c0b07d | 7997 | return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); |
644d711a NHE |
7998 | case EXIT_REASON_APIC_ACCESS: |
7999 | return nested_cpu_has2(vmcs12, | |
8000 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
82f0dd4b | 8001 | case EXIT_REASON_APIC_WRITE: |
608406e2 WV |
8002 | case EXIT_REASON_EOI_INDUCED: |
8003 | /* apic_write and eoi_induced should exit unconditionally. */ | |
1d804d07 | 8004 | return true; |
644d711a | 8005 | case EXIT_REASON_EPT_VIOLATION: |
2b1be677 NHE |
8006 | /* |
8007 | * L0 always deals with the EPT violation. If nested EPT is | |
8008 | * used, and the nested mmu code discovers that the address is | |
8009 | * missing in the guest EPT table (EPT12), the EPT violation | |
8010 | * will be injected with nested_ept_inject_page_fault() | |
8011 | */ | |
1d804d07 | 8012 | return false; |
644d711a | 8013 | case EXIT_REASON_EPT_MISCONFIG: |
2b1be677 NHE |
8014 | /* |
8015 | * L2 never uses directly L1's EPT, but rather L0's own EPT | |
8016 | * table (shadow on EPT) or a merged EPT table that L0 built | |
8017 | * (EPT on EPT). So any problems with the structure of the | |
8018 | * table is L0's fault. | |
8019 | */ | |
1d804d07 | 8020 | return false; |
644d711a NHE |
8021 | case EXIT_REASON_WBINVD: |
8022 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); | |
8023 | case EXIT_REASON_XSETBV: | |
1d804d07 | 8024 | return true; |
81dc01f7 WL |
8025 | case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: |
8026 | /* | |
8027 | * This should never happen, since it is not possible to | |
8028 | * set XSS to a non-zero value---neither in L1 nor in L2. | |
8029 | * If if it were, XSS would have to be checked against | |
8030 | * the XSS exit bitmap in vmcs12. | |
8031 | */ | |
8032 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); | |
55123e3c WL |
8033 | case EXIT_REASON_PREEMPTION_TIMER: |
8034 | return false; | |
644d711a | 8035 | default: |
1d804d07 | 8036 | return true; |
644d711a NHE |
8037 | } |
8038 | } | |
8039 | ||
586f9607 AK |
8040 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
8041 | { | |
8042 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
8043 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
8044 | } | |
8045 | ||
a3eaa864 | 8046 | static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) |
843e4330 | 8047 | { |
a3eaa864 KH |
8048 | if (vmx->pml_pg) { |
8049 | __free_page(vmx->pml_pg); | |
8050 | vmx->pml_pg = NULL; | |
8051 | } | |
843e4330 KH |
8052 | } |
8053 | ||
54bf36aa | 8054 | static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) |
843e4330 | 8055 | { |
54bf36aa | 8056 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
843e4330 KH |
8057 | u64 *pml_buf; |
8058 | u16 pml_idx; | |
8059 | ||
8060 | pml_idx = vmcs_read16(GUEST_PML_INDEX); | |
8061 | ||
8062 | /* Do nothing if PML buffer is empty */ | |
8063 | if (pml_idx == (PML_ENTITY_NUM - 1)) | |
8064 | return; | |
8065 | ||
8066 | /* PML index always points to next available PML buffer entity */ | |
8067 | if (pml_idx >= PML_ENTITY_NUM) | |
8068 | pml_idx = 0; | |
8069 | else | |
8070 | pml_idx++; | |
8071 | ||
8072 | pml_buf = page_address(vmx->pml_pg); | |
8073 | for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { | |
8074 | u64 gpa; | |
8075 | ||
8076 | gpa = pml_buf[pml_idx]; | |
8077 | WARN_ON(gpa & (PAGE_SIZE - 1)); | |
54bf36aa | 8078 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
843e4330 KH |
8079 | } |
8080 | ||
8081 | /* reset PML index */ | |
8082 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
8083 | } | |
8084 | ||
8085 | /* | |
8086 | * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. | |
8087 | * Called before reporting dirty_bitmap to userspace. | |
8088 | */ | |
8089 | static void kvm_flush_pml_buffers(struct kvm *kvm) | |
8090 | { | |
8091 | int i; | |
8092 | struct kvm_vcpu *vcpu; | |
8093 | /* | |
8094 | * We only need to kick vcpu out of guest mode here, as PML buffer | |
8095 | * is flushed at beginning of all VMEXITs, and it's obvious that only | |
8096 | * vcpus running in guest are possible to have unflushed GPAs in PML | |
8097 | * buffer. | |
8098 | */ | |
8099 | kvm_for_each_vcpu(i, vcpu, kvm) | |
8100 | kvm_vcpu_kick(vcpu); | |
8101 | } | |
8102 | ||
4eb64dce PB |
8103 | static void vmx_dump_sel(char *name, uint32_t sel) |
8104 | { | |
8105 | pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", | |
8106 | name, vmcs_read32(sel), | |
8107 | vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), | |
8108 | vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), | |
8109 | vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); | |
8110 | } | |
8111 | ||
8112 | static void vmx_dump_dtsel(char *name, uint32_t limit) | |
8113 | { | |
8114 | pr_err("%s limit=0x%08x, base=0x%016lx\n", | |
8115 | name, vmcs_read32(limit), | |
8116 | vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); | |
8117 | } | |
8118 | ||
8119 | static void dump_vmcs(void) | |
8120 | { | |
8121 | u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); | |
8122 | u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); | |
8123 | u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
8124 | u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); | |
8125 | u32 secondary_exec_control = 0; | |
8126 | unsigned long cr4 = vmcs_readl(GUEST_CR4); | |
f3531054 | 8127 | u64 efer = vmcs_read64(GUEST_IA32_EFER); |
4eb64dce PB |
8128 | int i, n; |
8129 | ||
8130 | if (cpu_has_secondary_exec_ctrls()) | |
8131 | secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8132 | ||
8133 | pr_err("*** Guest State ***\n"); | |
8134 | pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8135 | vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), | |
8136 | vmcs_readl(CR0_GUEST_HOST_MASK)); | |
8137 | pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8138 | cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); | |
8139 | pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); | |
8140 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && | |
8141 | (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) | |
8142 | { | |
845c5b40 PB |
8143 | pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", |
8144 | vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); | |
8145 | pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", | |
8146 | vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); | |
4eb64dce PB |
8147 | } |
8148 | pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", | |
8149 | vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); | |
8150 | pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", | |
8151 | vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); | |
8152 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8153 | vmcs_readl(GUEST_SYSENTER_ESP), | |
8154 | vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); | |
8155 | vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); | |
8156 | vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); | |
8157 | vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); | |
8158 | vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); | |
8159 | vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); | |
8160 | vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); | |
8161 | vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); | |
8162 | vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); | |
8163 | vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); | |
8164 | vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); | |
8165 | if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || | |
8166 | (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) | |
845c5b40 PB |
8167 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8168 | efer, vmcs_read64(GUEST_IA32_PAT)); | |
8169 | pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", | |
8170 | vmcs_read64(GUEST_IA32_DEBUGCTL), | |
4eb64dce PB |
8171 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); |
8172 | if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
845c5b40 PB |
8173 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8174 | vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce | 8175 | if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) |
845c5b40 | 8176 | pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); |
4eb64dce PB |
8177 | pr_err("Interruptibility = %08x ActivityState = %08x\n", |
8178 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), | |
8179 | vmcs_read32(GUEST_ACTIVITY_STATE)); | |
8180 | if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) | |
8181 | pr_err("InterruptStatus = %04x\n", | |
8182 | vmcs_read16(GUEST_INTR_STATUS)); | |
8183 | ||
8184 | pr_err("*** Host State ***\n"); | |
8185 | pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", | |
8186 | vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); | |
8187 | pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", | |
8188 | vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), | |
8189 | vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), | |
8190 | vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), | |
8191 | vmcs_read16(HOST_TR_SELECTOR)); | |
8192 | pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", | |
8193 | vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), | |
8194 | vmcs_readl(HOST_TR_BASE)); | |
8195 | pr_err("GDTBase=%016lx IDTBase=%016lx\n", | |
8196 | vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); | |
8197 | pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", | |
8198 | vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), | |
8199 | vmcs_readl(HOST_CR4)); | |
8200 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8201 | vmcs_readl(HOST_IA32_SYSENTER_ESP), | |
8202 | vmcs_read32(HOST_IA32_SYSENTER_CS), | |
8203 | vmcs_readl(HOST_IA32_SYSENTER_EIP)); | |
8204 | if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) | |
845c5b40 PB |
8205 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8206 | vmcs_read64(HOST_IA32_EFER), | |
8207 | vmcs_read64(HOST_IA32_PAT)); | |
4eb64dce | 8208 | if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
845c5b40 PB |
8209 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8210 | vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce PB |
8211 | |
8212 | pr_err("*** Control State ***\n"); | |
8213 | pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", | |
8214 | pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); | |
8215 | pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); | |
8216 | pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", | |
8217 | vmcs_read32(EXCEPTION_BITMAP), | |
8218 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), | |
8219 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); | |
8220 | pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8221 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
8222 | vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), | |
8223 | vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); | |
8224 | pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8225 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8226 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8227 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
8228 | pr_err(" reason=%08x qualification=%016lx\n", | |
8229 | vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); | |
8230 | pr_err("IDTVectoring: info=%08x errcode=%08x\n", | |
8231 | vmcs_read32(IDT_VECTORING_INFO_FIELD), | |
8232 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
845c5b40 | 8233 | pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); |
8cfe9866 | 8234 | if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) |
845c5b40 PB |
8235 | pr_err("TSC Multiplier = 0x%016llx\n", |
8236 | vmcs_read64(TSC_MULTIPLIER)); | |
4eb64dce PB |
8237 | if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) |
8238 | pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); | |
8239 | if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) | |
8240 | pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); | |
8241 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) | |
845c5b40 | 8242 | pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); |
4eb64dce PB |
8243 | n = vmcs_read32(CR3_TARGET_COUNT); |
8244 | for (i = 0; i + 1 < n; i += 4) | |
8245 | pr_err("CR3 target%u=%016lx target%u=%016lx\n", | |
8246 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), | |
8247 | i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); | |
8248 | if (i < n) | |
8249 | pr_err("CR3 target%u=%016lx\n", | |
8250 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); | |
8251 | if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) | |
8252 | pr_err("PLE Gap=%08x Window=%08x\n", | |
8253 | vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); | |
8254 | if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) | |
8255 | pr_err("Virtual processor ID = 0x%04x\n", | |
8256 | vmcs_read16(VIRTUAL_PROCESSOR_ID)); | |
8257 | } | |
8258 | ||
6aa8b732 AK |
8259 | /* |
8260 | * The guest has exited. See if we can fix it or if we need userspace | |
8261 | * assistance. | |
8262 | */ | |
851ba692 | 8263 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 8264 | { |
29bd8a78 | 8265 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 8266 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 8267 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 8268 | |
8b89fe1f PB |
8269 | trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); |
8270 | ||
843e4330 KH |
8271 | /* |
8272 | * Flush logged GPAs PML buffer, this will make dirty_bitmap more | |
8273 | * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before | |
8274 | * querying dirty_bitmap, we only need to kick all vcpus out of guest | |
8275 | * mode as if vcpus is in root mode, the PML buffer must has been | |
8276 | * flushed already. | |
8277 | */ | |
8278 | if (enable_pml) | |
54bf36aa | 8279 | vmx_flush_pml_buffer(vcpu); |
843e4330 | 8280 | |
80ced186 | 8281 | /* If guest state is invalid, start emulating */ |
14168786 | 8282 | if (vmx->emulation_required) |
80ced186 | 8283 | return handle_invalid_guest_state(vcpu); |
1d5a4d9b | 8284 | |
644d711a | 8285 | if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) { |
533558bc JK |
8286 | nested_vmx_vmexit(vcpu, exit_reason, |
8287 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8288 | vmcs_readl(EXIT_QUALIFICATION)); | |
644d711a NHE |
8289 | return 1; |
8290 | } | |
8291 | ||
5120702e | 8292 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
4eb64dce | 8293 | dump_vmcs(); |
5120702e MG |
8294 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8295 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
8296 | = exit_reason; | |
8297 | return 0; | |
8298 | } | |
8299 | ||
29bd8a78 | 8300 | if (unlikely(vmx->fail)) { |
851ba692 AK |
8301 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8302 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
8303 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
8304 | return 0; | |
8305 | } | |
6aa8b732 | 8306 | |
b9bf6882 XG |
8307 | /* |
8308 | * Note: | |
8309 | * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by | |
8310 | * delivery event since it indicates guest is accessing MMIO. | |
8311 | * The vm-exit can be triggered again after return to guest that | |
8312 | * will cause infinite loop. | |
8313 | */ | |
d77c26fc | 8314 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 8315 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac | 8316 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
b244c9fc | 8317 | exit_reason != EXIT_REASON_PML_FULL && |
b9bf6882 XG |
8318 | exit_reason != EXIT_REASON_TASK_SWITCH)) { |
8319 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
8320 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; | |
8321 | vcpu->run->internal.ndata = 2; | |
8322 | vcpu->run->internal.data[0] = vectoring_info; | |
8323 | vcpu->run->internal.data[1] = exit_reason; | |
8324 | return 0; | |
8325 | } | |
3b86cd99 | 8326 | |
644d711a NHE |
8327 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked && |
8328 | !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis( | |
f5c4368f | 8329 | get_vmcs12(vcpu))))) { |
c4282df9 | 8330 | if (vmx_interrupt_allowed(vcpu)) { |
3b86cd99 | 8331 | vmx->soft_vnmi_blocked = 0; |
3b86cd99 | 8332 | } else if (vmx->vnmi_blocked_time > 1000000000LL && |
4531220b | 8333 | vcpu->arch.nmi_pending) { |
3b86cd99 JK |
8334 | /* |
8335 | * This CPU don't support us in finding the end of an | |
8336 | * NMI-blocked window if the guest runs with IRQs | |
8337 | * disabled. So we pull the trigger after 1 s of | |
8338 | * futile waiting, but inform the user about this. | |
8339 | */ | |
8340 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
8341 | "state on VCPU %d after 1 s timeout\n", | |
8342 | __func__, vcpu->vcpu_id); | |
8343 | vmx->soft_vnmi_blocked = 0; | |
3b86cd99 | 8344 | } |
3b86cd99 JK |
8345 | } |
8346 | ||
6aa8b732 AK |
8347 | if (exit_reason < kvm_vmx_max_exit_handlers |
8348 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 8349 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 8350 | else { |
2bc19dc3 MT |
8351 | WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason); |
8352 | kvm_queue_exception(vcpu, UD_VECTOR); | |
8353 | return 1; | |
6aa8b732 | 8354 | } |
6aa8b732 AK |
8355 | } |
8356 | ||
95ba8273 | 8357 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 8358 | { |
a7c0b07d WL |
8359 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
8360 | ||
8361 | if (is_guest_mode(vcpu) && | |
8362 | nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
8363 | return; | |
8364 | ||
95ba8273 | 8365 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
8366 | vmcs_write32(TPR_THRESHOLD, 0); |
8367 | return; | |
8368 | } | |
8369 | ||
95ba8273 | 8370 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
8371 | } |
8372 | ||
8d14695f YZ |
8373 | static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
8374 | { | |
8375 | u32 sec_exec_control; | |
8376 | ||
dccbfcf5 RK |
8377 | /* Postpone execution until vmcs01 is the current VMCS. */ |
8378 | if (is_guest_mode(vcpu)) { | |
8379 | to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true; | |
8380 | return; | |
8381 | } | |
8382 | ||
f6e90f9e | 8383 | if (!cpu_has_vmx_virtualize_x2apic_mode()) |
8d14695f YZ |
8384 | return; |
8385 | ||
35754c98 | 8386 | if (!cpu_need_tpr_shadow(vcpu)) |
8d14695f YZ |
8387 | return; |
8388 | ||
8389 | sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8390 | ||
8391 | if (set) { | |
8392 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
8393 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8394 | } else { | |
8395 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8396 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
8397 | } | |
8398 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control); | |
8399 | ||
8400 | vmx_set_msr_bitmap(vcpu); | |
8401 | } | |
8402 | ||
38b99173 TC |
8403 | static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) |
8404 | { | |
8405 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8406 | ||
8407 | /* | |
8408 | * Currently we do not handle the nested case where L2 has an | |
8409 | * APIC access page of its own; that page is still pinned. | |
8410 | * Hence, we skip the case where the VCPU is in guest mode _and_ | |
8411 | * L1 prepared an APIC access page for L2. | |
8412 | * | |
8413 | * For the case where L1 and L2 share the same APIC access page | |
8414 | * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear | |
8415 | * in the vmcs12), this function will only update either the vmcs01 | |
8416 | * or the vmcs02. If the former, the vmcs02 will be updated by | |
8417 | * prepare_vmcs02. If the latter, the vmcs01 will be updated in | |
8418 | * the next L2->L1 exit. | |
8419 | */ | |
8420 | if (!is_guest_mode(vcpu) || | |
4f2777bc | 8421 | !nested_cpu_has2(get_vmcs12(&vmx->vcpu), |
38b99173 TC |
8422 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) |
8423 | vmcs_write64(APIC_ACCESS_ADDR, hpa); | |
8424 | } | |
8425 | ||
67c9dddc | 8426 | static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
c7c9c56c YZ |
8427 | { |
8428 | u16 status; | |
8429 | u8 old; | |
8430 | ||
67c9dddc PB |
8431 | if (max_isr == -1) |
8432 | max_isr = 0; | |
c7c9c56c YZ |
8433 | |
8434 | status = vmcs_read16(GUEST_INTR_STATUS); | |
8435 | old = status >> 8; | |
67c9dddc | 8436 | if (max_isr != old) { |
c7c9c56c | 8437 | status &= 0xff; |
67c9dddc | 8438 | status |= max_isr << 8; |
c7c9c56c YZ |
8439 | vmcs_write16(GUEST_INTR_STATUS, status); |
8440 | } | |
8441 | } | |
8442 | ||
8443 | static void vmx_set_rvi(int vector) | |
8444 | { | |
8445 | u16 status; | |
8446 | u8 old; | |
8447 | ||
4114c27d WW |
8448 | if (vector == -1) |
8449 | vector = 0; | |
8450 | ||
c7c9c56c YZ |
8451 | status = vmcs_read16(GUEST_INTR_STATUS); |
8452 | old = (u8)status & 0xff; | |
8453 | if ((u8)vector != old) { | |
8454 | status &= ~0xff; | |
8455 | status |= (u8)vector; | |
8456 | vmcs_write16(GUEST_INTR_STATUS, status); | |
8457 | } | |
8458 | } | |
8459 | ||
8460 | static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
8461 | { | |
4114c27d WW |
8462 | if (!is_guest_mode(vcpu)) { |
8463 | vmx_set_rvi(max_irr); | |
8464 | return; | |
8465 | } | |
8466 | ||
c7c9c56c YZ |
8467 | if (max_irr == -1) |
8468 | return; | |
8469 | ||
963fee16 | 8470 | /* |
4114c27d WW |
8471 | * In guest mode. If a vmexit is needed, vmx_check_nested_events |
8472 | * handles it. | |
963fee16 | 8473 | */ |
4114c27d | 8474 | if (nested_exit_on_intr(vcpu)) |
963fee16 WL |
8475 | return; |
8476 | ||
963fee16 | 8477 | /* |
4114c27d | 8478 | * Else, fall back to pre-APICv interrupt injection since L2 |
963fee16 WL |
8479 | * is run without virtual interrupt delivery. |
8480 | */ | |
8481 | if (!kvm_event_needs_reinjection(vcpu) && | |
8482 | vmx_interrupt_allowed(vcpu)) { | |
8483 | kvm_queue_interrupt(vcpu, max_irr, false); | |
8484 | vmx_inject_irq(vcpu); | |
8485 | } | |
c7c9c56c YZ |
8486 | } |
8487 | ||
6308630b | 8488 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c | 8489 | { |
d62caabb | 8490 | if (!kvm_vcpu_apicv_active(vcpu)) |
3d81bc7e YZ |
8491 | return; |
8492 | ||
c7c9c56c YZ |
8493 | vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); |
8494 | vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); | |
8495 | vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); | |
8496 | vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); | |
8497 | } | |
8498 | ||
51aa01d1 | 8499 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 8500 | { |
00eba012 AK |
8501 | u32 exit_intr_info; |
8502 | ||
8503 | if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY | |
8504 | || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)) | |
8505 | return; | |
8506 | ||
c5ca8e57 | 8507 | vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
00eba012 | 8508 | exit_intr_info = vmx->exit_intr_info; |
a0861c02 AK |
8509 | |
8510 | /* Handle machine checks before interrupts are enabled */ | |
00eba012 | 8511 | if (is_machine_check(exit_intr_info)) |
a0861c02 AK |
8512 | kvm_machine_check(); |
8513 | ||
20f65983 | 8514 | /* We need to handle NMIs before interrupts are enabled */ |
00eba012 | 8515 | if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR && |
ff9d07a0 ZY |
8516 | (exit_intr_info & INTR_INFO_VALID_MASK)) { |
8517 | kvm_before_handle_nmi(&vmx->vcpu); | |
20f65983 | 8518 | asm("int $2"); |
ff9d07a0 ZY |
8519 | kvm_after_handle_nmi(&vmx->vcpu); |
8520 | } | |
51aa01d1 | 8521 | } |
20f65983 | 8522 | |
a547c6db YZ |
8523 | static void vmx_handle_external_intr(struct kvm_vcpu *vcpu) |
8524 | { | |
8525 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
3f62de5f | 8526 | register void *__sp asm(_ASM_SP); |
a547c6db | 8527 | |
a547c6db YZ |
8528 | if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK)) |
8529 | == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) { | |
8530 | unsigned int vector; | |
8531 | unsigned long entry; | |
8532 | gate_desc *desc; | |
8533 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8534 | #ifdef CONFIG_X86_64 | |
8535 | unsigned long tmp; | |
8536 | #endif | |
8537 | ||
8538 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
8539 | desc = (gate_desc *)vmx->host_idt_base + vector; | |
8540 | entry = gate_offset(*desc); | |
8541 | asm volatile( | |
8542 | #ifdef CONFIG_X86_64 | |
8543 | "mov %%" _ASM_SP ", %[sp]\n\t" | |
8544 | "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" | |
8545 | "push $%c[ss]\n\t" | |
8546 | "push %[sp]\n\t" | |
8547 | #endif | |
8548 | "pushf\n\t" | |
a547c6db YZ |
8549 | __ASM_SIZE(push) " $%c[cs]\n\t" |
8550 | "call *%[entry]\n\t" | |
8551 | : | |
8552 | #ifdef CONFIG_X86_64 | |
3f62de5f | 8553 | [sp]"=&r"(tmp), |
a547c6db | 8554 | #endif |
3f62de5f | 8555 | "+r"(__sp) |
a547c6db YZ |
8556 | : |
8557 | [entry]"r"(entry), | |
8558 | [ss]"i"(__KERNEL_DS), | |
8559 | [cs]"i"(__KERNEL_CS) | |
8560 | ); | |
f2485b3e | 8561 | } |
a547c6db YZ |
8562 | } |
8563 | ||
6d396b55 PB |
8564 | static bool vmx_has_high_real_mode_segbase(void) |
8565 | { | |
8566 | return enable_unrestricted_guest || emulate_invalid_guest_state; | |
8567 | } | |
8568 | ||
da8999d3 LJ |
8569 | static bool vmx_mpx_supported(void) |
8570 | { | |
8571 | return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && | |
8572 | (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); | |
8573 | } | |
8574 | ||
55412b2e WL |
8575 | static bool vmx_xsaves_supported(void) |
8576 | { | |
8577 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
8578 | SECONDARY_EXEC_XSAVES; | |
8579 | } | |
8580 | ||
51aa01d1 AK |
8581 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
8582 | { | |
c5ca8e57 | 8583 | u32 exit_intr_info; |
51aa01d1 AK |
8584 | bool unblock_nmi; |
8585 | u8 vector; | |
8586 | bool idtv_info_valid; | |
8587 | ||
8588 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 8589 | |
cf393f75 | 8590 | if (cpu_has_virtual_nmis()) { |
9d58b931 AK |
8591 | if (vmx->nmi_known_unmasked) |
8592 | return; | |
c5ca8e57 AK |
8593 | /* |
8594 | * Can't use vmx->exit_intr_info since we're not sure what | |
8595 | * the exit reason is. | |
8596 | */ | |
8597 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
cf393f75 AK |
8598 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; |
8599 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
8600 | /* | |
7b4a25cb | 8601 | * SDM 3: 27.7.1.2 (September 2008) |
cf393f75 AK |
8602 | * Re-set bit "block by NMI" before VM entry if vmexit caused by |
8603 | * a guest IRET fault. | |
7b4a25cb GN |
8604 | * SDM 3: 23.2.2 (September 2008) |
8605 | * Bit 12 is undefined in any of the following cases: | |
8606 | * If the VM exit sets the valid bit in the IDT-vectoring | |
8607 | * information field. | |
8608 | * If the VM exit is due to a double fault. | |
cf393f75 | 8609 | */ |
7b4a25cb GN |
8610 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && |
8611 | vector != DF_VECTOR && !idtv_info_valid) | |
cf393f75 AK |
8612 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, |
8613 | GUEST_INTR_STATE_NMI); | |
9d58b931 AK |
8614 | else |
8615 | vmx->nmi_known_unmasked = | |
8616 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | |
8617 | & GUEST_INTR_STATE_NMI); | |
3b86cd99 JK |
8618 | } else if (unlikely(vmx->soft_vnmi_blocked)) |
8619 | vmx->vnmi_blocked_time += | |
8620 | ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time)); | |
51aa01d1 AK |
8621 | } |
8622 | ||
3ab66e8a | 8623 | static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, |
83422e17 AK |
8624 | u32 idt_vectoring_info, |
8625 | int instr_len_field, | |
8626 | int error_code_field) | |
51aa01d1 | 8627 | { |
51aa01d1 AK |
8628 | u8 vector; |
8629 | int type; | |
8630 | bool idtv_info_valid; | |
8631 | ||
8632 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 8633 | |
3ab66e8a JK |
8634 | vcpu->arch.nmi_injected = false; |
8635 | kvm_clear_exception_queue(vcpu); | |
8636 | kvm_clear_interrupt_queue(vcpu); | |
37b96e98 GN |
8637 | |
8638 | if (!idtv_info_valid) | |
8639 | return; | |
8640 | ||
3ab66e8a | 8641 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3842d135 | 8642 | |
668f612f AK |
8643 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
8644 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 8645 | |
64a7ec06 | 8646 | switch (type) { |
37b96e98 | 8647 | case INTR_TYPE_NMI_INTR: |
3ab66e8a | 8648 | vcpu->arch.nmi_injected = true; |
668f612f | 8649 | /* |
7b4a25cb | 8650 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
8651 | * Clear bit "block by NMI" before VM entry if a NMI |
8652 | * delivery faulted. | |
668f612f | 8653 | */ |
3ab66e8a | 8654 | vmx_set_nmi_mask(vcpu, false); |
37b96e98 | 8655 | break; |
37b96e98 | 8656 | case INTR_TYPE_SOFT_EXCEPTION: |
3ab66e8a | 8657 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f GN |
8658 | /* fall through */ |
8659 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 8660 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 8661 | u32 err = vmcs_read32(error_code_field); |
851eb667 | 8662 | kvm_requeue_exception_e(vcpu, vector, err); |
35920a35 | 8663 | } else |
851eb667 | 8664 | kvm_requeue_exception(vcpu, vector); |
37b96e98 | 8665 | break; |
66fd3f7f | 8666 | case INTR_TYPE_SOFT_INTR: |
3ab66e8a | 8667 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f | 8668 | /* fall through */ |
37b96e98 | 8669 | case INTR_TYPE_EXT_INTR: |
3ab66e8a | 8670 | kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); |
37b96e98 GN |
8671 | break; |
8672 | default: | |
8673 | break; | |
f7d9238f | 8674 | } |
cf393f75 AK |
8675 | } |
8676 | ||
83422e17 AK |
8677 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
8678 | { | |
3ab66e8a | 8679 | __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, |
83422e17 AK |
8680 | VM_EXIT_INSTRUCTION_LEN, |
8681 | IDT_VECTORING_ERROR_CODE); | |
8682 | } | |
8683 | ||
b463a6f7 AK |
8684 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
8685 | { | |
3ab66e8a | 8686 | __vmx_complete_interrupts(vcpu, |
b463a6f7 AK |
8687 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), |
8688 | VM_ENTRY_INSTRUCTION_LEN, | |
8689 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
8690 | ||
8691 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
8692 | } | |
8693 | ||
d7cd9796 GN |
8694 | static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) |
8695 | { | |
8696 | int i, nr_msrs; | |
8697 | struct perf_guest_switch_msr *msrs; | |
8698 | ||
8699 | msrs = perf_guest_get_msrs(&nr_msrs); | |
8700 | ||
8701 | if (!msrs) | |
8702 | return; | |
8703 | ||
8704 | for (i = 0; i < nr_msrs; i++) | |
8705 | if (msrs[i].host == msrs[i].guest) | |
8706 | clear_atomic_switch_msr(vmx, msrs[i].msr); | |
8707 | else | |
8708 | add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, | |
8709 | msrs[i].host); | |
8710 | } | |
8711 | ||
64672c95 YJ |
8712 | void vmx_arm_hv_timer(struct kvm_vcpu *vcpu) |
8713 | { | |
8714 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8715 | u64 tscl; | |
8716 | u32 delta_tsc; | |
8717 | ||
8718 | if (vmx->hv_deadline_tsc == -1) | |
8719 | return; | |
8720 | ||
8721 | tscl = rdtsc(); | |
8722 | if (vmx->hv_deadline_tsc > tscl) | |
8723 | /* sure to be 32 bit only because checked on set_hv_timer */ | |
8724 | delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> | |
8725 | cpu_preemption_timer_multi); | |
8726 | else | |
8727 | delta_tsc = 0; | |
8728 | ||
8729 | vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); | |
8730 | } | |
8731 | ||
a3b5ba49 | 8732 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 8733 | { |
a2fa3e9f | 8734 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
d974baa3 | 8735 | unsigned long debugctlmsr, cr4; |
104f226b AK |
8736 | |
8737 | /* Record the guest's net vcpu time for enforced NMI injections. */ | |
8738 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) | |
8739 | vmx->entry_time = ktime_get(); | |
8740 | ||
8741 | /* Don't enter VMX if guest state is invalid, let the exit handler | |
8742 | start emulation until we arrive back to a valid state */ | |
14168786 | 8743 | if (vmx->emulation_required) |
104f226b AK |
8744 | return; |
8745 | ||
a7653ecd RK |
8746 | if (vmx->ple_window_dirty) { |
8747 | vmx->ple_window_dirty = false; | |
8748 | vmcs_write32(PLE_WINDOW, vmx->ple_window); | |
8749 | } | |
8750 | ||
012f83cb AG |
8751 | if (vmx->nested.sync_shadow_vmcs) { |
8752 | copy_vmcs12_to_shadow(vmx); | |
8753 | vmx->nested.sync_shadow_vmcs = false; | |
8754 | } | |
8755 | ||
104f226b AK |
8756 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
8757 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
8758 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
8759 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
8760 | ||
1e02ce4c | 8761 | cr4 = cr4_read_shadow(); |
d974baa3 AL |
8762 | if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) { |
8763 | vmcs_writel(HOST_CR4, cr4); | |
8764 | vmx->host_state.vmcs_host_cr4 = cr4; | |
8765 | } | |
8766 | ||
104f226b AK |
8767 | /* When single-stepping over STI and MOV SS, we must clear the |
8768 | * corresponding interruptibility bits in the guest state. Otherwise | |
8769 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
8770 | * exceptions being set, but that's not correct for the guest debugging | |
8771 | * case. */ | |
8772 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
8773 | vmx_set_interrupt_shadow(vcpu, 0); | |
8774 | ||
1be0e61c XG |
8775 | if (vmx->guest_pkru_valid) |
8776 | __write_pkru(vmx->guest_pkru); | |
8777 | ||
d7cd9796 | 8778 | atomic_switch_perf_msrs(vmx); |
2a7921b7 | 8779 | debugctlmsr = get_debugctlmsr(); |
d7cd9796 | 8780 | |
64672c95 YJ |
8781 | vmx_arm_hv_timer(vcpu); |
8782 | ||
d462b819 | 8783 | vmx->__launched = vmx->loaded_vmcs->launched; |
104f226b | 8784 | asm( |
6aa8b732 | 8785 | /* Store host registers */ |
b188c81f AK |
8786 | "push %%" _ASM_DX "; push %%" _ASM_BP ";" |
8787 | "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */ | |
8788 | "push %%" _ASM_CX " \n\t" | |
8789 | "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t" | |
313dbd49 | 8790 | "je 1f \n\t" |
b188c81f | 8791 | "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t" |
4ecac3fd | 8792 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 8793 | "1: \n\t" |
d3edefc0 | 8794 | /* Reload cr2 if changed */ |
b188c81f AK |
8795 | "mov %c[cr2](%0), %%" _ASM_AX " \n\t" |
8796 | "mov %%cr2, %%" _ASM_DX " \n\t" | |
8797 | "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t" | |
d3edefc0 | 8798 | "je 2f \n\t" |
b188c81f | 8799 | "mov %%" _ASM_AX", %%cr2 \n\t" |
d3edefc0 | 8800 | "2: \n\t" |
6aa8b732 | 8801 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 8802 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 8803 | /* Load guest registers. Don't clobber flags. */ |
b188c81f AK |
8804 | "mov %c[rax](%0), %%" _ASM_AX " \n\t" |
8805 | "mov %c[rbx](%0), %%" _ASM_BX " \n\t" | |
8806 | "mov %c[rdx](%0), %%" _ASM_DX " \n\t" | |
8807 | "mov %c[rsi](%0), %%" _ASM_SI " \n\t" | |
8808 | "mov %c[rdi](%0), %%" _ASM_DI " \n\t" | |
8809 | "mov %c[rbp](%0), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 8810 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
8811 | "mov %c[r8](%0), %%r8 \n\t" |
8812 | "mov %c[r9](%0), %%r9 \n\t" | |
8813 | "mov %c[r10](%0), %%r10 \n\t" | |
8814 | "mov %c[r11](%0), %%r11 \n\t" | |
8815 | "mov %c[r12](%0), %%r12 \n\t" | |
8816 | "mov %c[r13](%0), %%r13 \n\t" | |
8817 | "mov %c[r14](%0), %%r14 \n\t" | |
8818 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 8819 | #endif |
b188c81f | 8820 | "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */ |
c801949d | 8821 | |
6aa8b732 | 8822 | /* Enter guest mode */ |
83287ea4 | 8823 | "jne 1f \n\t" |
4ecac3fd | 8824 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
83287ea4 AK |
8825 | "jmp 2f \n\t" |
8826 | "1: " __ex(ASM_VMX_VMRESUME) "\n\t" | |
8827 | "2: " | |
6aa8b732 | 8828 | /* Save guest registers, load host registers, keep flags */ |
b188c81f | 8829 | "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t" |
40712fae | 8830 | "pop %0 \n\t" |
b188c81f AK |
8831 | "mov %%" _ASM_AX ", %c[rax](%0) \n\t" |
8832 | "mov %%" _ASM_BX ", %c[rbx](%0) \n\t" | |
8833 | __ASM_SIZE(pop) " %c[rcx](%0) \n\t" | |
8834 | "mov %%" _ASM_DX ", %c[rdx](%0) \n\t" | |
8835 | "mov %%" _ASM_SI ", %c[rsi](%0) \n\t" | |
8836 | "mov %%" _ASM_DI ", %c[rdi](%0) \n\t" | |
8837 | "mov %%" _ASM_BP ", %c[rbp](%0) \n\t" | |
05b3e0c2 | 8838 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
8839 | "mov %%r8, %c[r8](%0) \n\t" |
8840 | "mov %%r9, %c[r9](%0) \n\t" | |
8841 | "mov %%r10, %c[r10](%0) \n\t" | |
8842 | "mov %%r11, %c[r11](%0) \n\t" | |
8843 | "mov %%r12, %c[r12](%0) \n\t" | |
8844 | "mov %%r13, %c[r13](%0) \n\t" | |
8845 | "mov %%r14, %c[r14](%0) \n\t" | |
8846 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 8847 | #endif |
b188c81f AK |
8848 | "mov %%cr2, %%" _ASM_AX " \n\t" |
8849 | "mov %%" _ASM_AX ", %c[cr2](%0) \n\t" | |
c801949d | 8850 | |
b188c81f | 8851 | "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t" |
e08aa78a | 8852 | "setbe %c[fail](%0) \n\t" |
83287ea4 AK |
8853 | ".pushsection .rodata \n\t" |
8854 | ".global vmx_return \n\t" | |
8855 | "vmx_return: " _ASM_PTR " 2b \n\t" | |
8856 | ".popsection" | |
e08aa78a | 8857 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), |
d462b819 | 8858 | [launched]"i"(offsetof(struct vcpu_vmx, __launched)), |
e08aa78a | 8859 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), |
313dbd49 | 8860 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
8861 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
8862 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
8863 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
8864 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
8865 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
8866 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
8867 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 8868 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
8869 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
8870 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
8871 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
8872 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
8873 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
8874 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
8875 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
8876 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 8877 | #endif |
40712fae AK |
8878 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
8879 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 LV |
8880 | : "cc", "memory" |
8881 | #ifdef CONFIG_X86_64 | |
b188c81f | 8882 | , "rax", "rbx", "rdi", "rsi" |
c2036300 | 8883 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
b188c81f AK |
8884 | #else |
8885 | , "eax", "ebx", "edi", "esi" | |
c2036300 LV |
8886 | #endif |
8887 | ); | |
6aa8b732 | 8888 | |
2a7921b7 GN |
8889 | /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ |
8890 | if (debugctlmsr) | |
8891 | update_debugctlmsr(debugctlmsr); | |
8892 | ||
aa67f609 AK |
8893 | #ifndef CONFIG_X86_64 |
8894 | /* | |
8895 | * The sysexit path does not restore ds/es, so we must set them to | |
8896 | * a reasonable value ourselves. | |
8897 | * | |
8898 | * We can't defer this to vmx_load_host_state() since that function | |
8899 | * may be executed in interrupt context, which saves and restore segments | |
8900 | * around it, nullifying its effect. | |
8901 | */ | |
8902 | loadsegment(ds, __USER_DS); | |
8903 | loadsegment(es, __USER_DS); | |
8904 | #endif | |
8905 | ||
6de4f3ad | 8906 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
6de12732 | 8907 | | (1 << VCPU_EXREG_RFLAGS) |
aff48baa | 8908 | | (1 << VCPU_EXREG_PDPTR) |
2fb92db1 | 8909 | | (1 << VCPU_EXREG_SEGMENTS) |
aff48baa | 8910 | | (1 << VCPU_EXREG_CR3)); |
5fdbf976 MT |
8911 | vcpu->arch.regs_dirty = 0; |
8912 | ||
1155f76a AK |
8913 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
8914 | ||
d462b819 | 8915 | vmx->loaded_vmcs->launched = 1; |
1b6269db | 8916 | |
51aa01d1 | 8917 | vmx->exit_reason = vmcs_read32(VM_EXIT_REASON); |
51aa01d1 | 8918 | |
1be0e61c XG |
8919 | /* |
8920 | * eager fpu is enabled if PKEY is supported and CR4 is switched | |
8921 | * back on host, so it is safe to read guest PKRU from current | |
8922 | * XSAVE. | |
8923 | */ | |
8924 | if (boot_cpu_has(X86_FEATURE_OSPKE)) { | |
8925 | vmx->guest_pkru = __read_pkru(); | |
8926 | if (vmx->guest_pkru != vmx->host_pkru) { | |
8927 | vmx->guest_pkru_valid = true; | |
8928 | __write_pkru(vmx->host_pkru); | |
8929 | } else | |
8930 | vmx->guest_pkru_valid = false; | |
8931 | } | |
8932 | ||
e0b890d3 GN |
8933 | /* |
8934 | * the KVM_REQ_EVENT optimization bit is only on for one entry, and if | |
8935 | * we did not inject a still-pending event to L1 now because of | |
8936 | * nested_run_pending, we need to re-enable this bit. | |
8937 | */ | |
8938 | if (vmx->nested.nested_run_pending) | |
8939 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8940 | ||
8941 | vmx->nested.nested_run_pending = 0; | |
8942 | ||
51aa01d1 AK |
8943 | vmx_complete_atomic_exit(vmx); |
8944 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 8945 | vmx_complete_interrupts(vmx); |
6aa8b732 AK |
8946 | } |
8947 | ||
4fa7734c PB |
8948 | static void vmx_load_vmcs01(struct kvm_vcpu *vcpu) |
8949 | { | |
8950 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8951 | int cpu; | |
8952 | ||
8953 | if (vmx->loaded_vmcs == &vmx->vmcs01) | |
8954 | return; | |
8955 | ||
8956 | cpu = get_cpu(); | |
8957 | vmx->loaded_vmcs = &vmx->vmcs01; | |
8958 | vmx_vcpu_put(vcpu); | |
8959 | vmx_vcpu_load(vcpu, cpu); | |
8960 | vcpu->cpu = cpu; | |
8961 | put_cpu(); | |
8962 | } | |
8963 | ||
2f1fe811 JM |
8964 | /* |
8965 | * Ensure that the current vmcs of the logical processor is the | |
8966 | * vmcs01 of the vcpu before calling free_nested(). | |
8967 | */ | |
8968 | static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu) | |
8969 | { | |
8970 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8971 | int r; | |
8972 | ||
8973 | r = vcpu_load(vcpu); | |
8974 | BUG_ON(r); | |
8975 | vmx_load_vmcs01(vcpu); | |
8976 | free_nested(vmx); | |
8977 | vcpu_put(vcpu); | |
8978 | } | |
8979 | ||
6aa8b732 AK |
8980 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
8981 | { | |
fb3f0f51 RR |
8982 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8983 | ||
843e4330 | 8984 | if (enable_pml) |
a3eaa864 | 8985 | vmx_destroy_pml_buffer(vmx); |
991e7a0e | 8986 | free_vpid(vmx->vpid); |
4fa7734c | 8987 | leave_guest_mode(vcpu); |
2f1fe811 | 8988 | vmx_free_vcpu_nested(vcpu); |
4fa7734c | 8989 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 RR |
8990 | kfree(vmx->guest_msrs); |
8991 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 8992 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
8993 | } |
8994 | ||
fb3f0f51 | 8995 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 8996 | { |
fb3f0f51 | 8997 | int err; |
c16f862d | 8998 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 8999 | int cpu; |
6aa8b732 | 9000 | |
a2fa3e9f | 9001 | if (!vmx) |
fb3f0f51 RR |
9002 | return ERR_PTR(-ENOMEM); |
9003 | ||
991e7a0e | 9004 | vmx->vpid = allocate_vpid(); |
2384d2b3 | 9005 | |
fb3f0f51 RR |
9006 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
9007 | if (err) | |
9008 | goto free_vcpu; | |
965b58a5 | 9009 | |
4e59516a PF |
9010 | err = -ENOMEM; |
9011 | ||
9012 | /* | |
9013 | * If PML is turned on, failure on enabling PML just results in failure | |
9014 | * of creating the vcpu, therefore we can simplify PML logic (by | |
9015 | * avoiding dealing with cases, such as enabling PML partially on vcpus | |
9016 | * for the guest, etc. | |
9017 | */ | |
9018 | if (enable_pml) { | |
9019 | vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
9020 | if (!vmx->pml_pg) | |
9021 | goto uninit_vcpu; | |
9022 | } | |
9023 | ||
a2fa3e9f | 9024 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
03916db9 PB |
9025 | BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0]) |
9026 | > PAGE_SIZE); | |
0123be42 | 9027 | |
4e59516a PF |
9028 | if (!vmx->guest_msrs) |
9029 | goto free_pml; | |
965b58a5 | 9030 | |
d462b819 NHE |
9031 | vmx->loaded_vmcs = &vmx->vmcs01; |
9032 | vmx->loaded_vmcs->vmcs = alloc_vmcs(); | |
355f4fb1 | 9033 | vmx->loaded_vmcs->shadow_vmcs = NULL; |
d462b819 | 9034 | if (!vmx->loaded_vmcs->vmcs) |
fb3f0f51 | 9035 | goto free_msrs; |
d462b819 NHE |
9036 | if (!vmm_exclusive) |
9037 | kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id()))); | |
9038 | loaded_vmcs_init(vmx->loaded_vmcs); | |
9039 | if (!vmm_exclusive) | |
9040 | kvm_cpu_vmxoff(); | |
a2fa3e9f | 9041 | |
15ad7146 AK |
9042 | cpu = get_cpu(); |
9043 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 9044 | vmx->vcpu.cpu = cpu; |
8b9cf98c | 9045 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 9046 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 9047 | put_cpu(); |
fb3f0f51 RR |
9048 | if (err) |
9049 | goto free_vmcs; | |
35754c98 | 9050 | if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
be6d05cf JK |
9051 | err = alloc_apic_access_page(kvm); |
9052 | if (err) | |
5e4a0b3c | 9053 | goto free_vmcs; |
a63cb560 | 9054 | } |
fb3f0f51 | 9055 | |
b927a3ce SY |
9056 | if (enable_ept) { |
9057 | if (!kvm->arch.ept_identity_map_addr) | |
9058 | kvm->arch.ept_identity_map_addr = | |
9059 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
f51770ed TC |
9060 | err = init_rmode_identity_map(kvm); |
9061 | if (err) | |
93ea5388 | 9062 | goto free_vmcs; |
b927a3ce | 9063 | } |
b7ebfb05 | 9064 | |
5c614b35 | 9065 | if (nested) { |
b9c237bb | 9066 | nested_vmx_setup_ctls_msrs(vmx); |
5c614b35 WL |
9067 | vmx->nested.vpid02 = allocate_vpid(); |
9068 | } | |
b9c237bb | 9069 | |
705699a1 | 9070 | vmx->nested.posted_intr_nv = -1; |
a9d30f33 NHE |
9071 | vmx->nested.current_vmptr = -1ull; |
9072 | vmx->nested.current_vmcs12 = NULL; | |
9073 | ||
37e4c997 HZ |
9074 | vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED; |
9075 | ||
fb3f0f51 RR |
9076 | return &vmx->vcpu; |
9077 | ||
9078 | free_vmcs: | |
5c614b35 | 9079 | free_vpid(vmx->nested.vpid02); |
5f3fbc34 | 9080 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 | 9081 | free_msrs: |
fb3f0f51 | 9082 | kfree(vmx->guest_msrs); |
4e59516a PF |
9083 | free_pml: |
9084 | vmx_destroy_pml_buffer(vmx); | |
fb3f0f51 RR |
9085 | uninit_vcpu: |
9086 | kvm_vcpu_uninit(&vmx->vcpu); | |
9087 | free_vcpu: | |
991e7a0e | 9088 | free_vpid(vmx->vpid); |
a4770347 | 9089 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 9090 | return ERR_PTR(err); |
6aa8b732 AK |
9091 | } |
9092 | ||
002c7f7c YS |
9093 | static void __init vmx_check_processor_compat(void *rtn) |
9094 | { | |
9095 | struct vmcs_config vmcs_conf; | |
9096 | ||
9097 | *(int *)rtn = 0; | |
9098 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
9099 | *(int *)rtn = -EIO; | |
9100 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
9101 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
9102 | smp_processor_id()); | |
9103 | *(int *)rtn = -EIO; | |
9104 | } | |
9105 | } | |
9106 | ||
67253af5 SY |
9107 | static int get_ept_level(void) |
9108 | { | |
9109 | return VMX_EPT_DEFAULT_GAW + 1; | |
9110 | } | |
9111 | ||
4b12f0de | 9112 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 9113 | { |
b18d5431 XG |
9114 | u8 cache; |
9115 | u64 ipat = 0; | |
4b12f0de | 9116 | |
522c68c4 | 9117 | /* For VT-d and EPT combination |
606decd6 | 9118 | * 1. MMIO: always map as UC |
522c68c4 SY |
9119 | * 2. EPT with VT-d: |
9120 | * a. VT-d without snooping control feature: can't guarantee the | |
606decd6 | 9121 | * result, try to trust guest. |
522c68c4 SY |
9122 | * b. VT-d with snooping control feature: snooping control feature of |
9123 | * VT-d engine can guarantee the cache correctness. Just set it | |
9124 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 9125 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
9126 | * consistent with host MTRR |
9127 | */ | |
606decd6 PB |
9128 | if (is_mmio) { |
9129 | cache = MTRR_TYPE_UNCACHABLE; | |
9130 | goto exit; | |
9131 | } | |
9132 | ||
9133 | if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { | |
b18d5431 XG |
9134 | ipat = VMX_EPT_IPAT_BIT; |
9135 | cache = MTRR_TYPE_WRBACK; | |
9136 | goto exit; | |
9137 | } | |
9138 | ||
9139 | if (kvm_read_cr0(vcpu) & X86_CR0_CD) { | |
9140 | ipat = VMX_EPT_IPAT_BIT; | |
0da029ed | 9141 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) |
fb279950 XG |
9142 | cache = MTRR_TYPE_WRBACK; |
9143 | else | |
9144 | cache = MTRR_TYPE_UNCACHABLE; | |
b18d5431 XG |
9145 | goto exit; |
9146 | } | |
9147 | ||
ff53604b | 9148 | cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); |
b18d5431 XG |
9149 | |
9150 | exit: | |
9151 | return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; | |
64d4d521 SY |
9152 | } |
9153 | ||
17cc3935 | 9154 | static int vmx_get_lpage_level(void) |
344f414f | 9155 | { |
878403b7 SY |
9156 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
9157 | return PT_DIRECTORY_LEVEL; | |
9158 | else | |
9159 | /* For shadow and EPT supported 1GB page */ | |
9160 | return PT_PDPE_LEVEL; | |
344f414f JR |
9161 | } |
9162 | ||
feda805f XG |
9163 | static void vmcs_set_secondary_exec_control(u32 new_ctl) |
9164 | { | |
9165 | /* | |
9166 | * These bits in the secondary execution controls field | |
9167 | * are dynamic, the others are mostly based on the hypervisor | |
9168 | * architecture and the guest's CPUID. Do not touch the | |
9169 | * dynamic bits. | |
9170 | */ | |
9171 | u32 mask = | |
9172 | SECONDARY_EXEC_SHADOW_VMCS | | |
9173 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | | |
9174 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
9175 | ||
9176 | u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
9177 | ||
9178 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
9179 | (new_ctl & ~mask) | (cur_ctl & mask)); | |
9180 | } | |
9181 | ||
0e851880 SY |
9182 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
9183 | { | |
4e47c7a6 SY |
9184 | struct kvm_cpuid_entry2 *best; |
9185 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
feda805f | 9186 | u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx); |
4e47c7a6 | 9187 | |
4e47c7a6 | 9188 | if (vmx_rdtscp_supported()) { |
1cea0ce6 XG |
9189 | bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu); |
9190 | if (!rdtscp_enabled) | |
feda805f | 9191 | secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP; |
f36201e5 | 9192 | |
8b97265a | 9193 | if (nested) { |
1cea0ce6 | 9194 | if (rdtscp_enabled) |
8b97265a PB |
9195 | vmx->nested.nested_vmx_secondary_ctls_high |= |
9196 | SECONDARY_EXEC_RDTSCP; | |
9197 | else | |
9198 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
9199 | ~SECONDARY_EXEC_RDTSCP; | |
9200 | } | |
4e47c7a6 | 9201 | } |
ad756a16 | 9202 | |
ad756a16 MJ |
9203 | /* Exposing INVPCID only when PCID is exposed */ |
9204 | best = kvm_find_cpuid_entry(vcpu, 0x7, 0); | |
9205 | if (vmx_invpcid_supported() && | |
29541bb8 XG |
9206 | (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) || |
9207 | !guest_cpuid_has_pcid(vcpu))) { | |
feda805f | 9208 | secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID; |
29541bb8 | 9209 | |
ad756a16 | 9210 | if (best) |
4f977045 | 9211 | best->ebx &= ~bit(X86_FEATURE_INVPCID); |
ad756a16 | 9212 | } |
8b3e34e4 | 9213 | |
45bdbcfd HH |
9214 | if (cpu_has_secondary_exec_ctrls()) |
9215 | vmcs_set_secondary_exec_control(secondary_exec_ctl); | |
feda805f | 9216 | |
37e4c997 HZ |
9217 | if (nested_vmx_allowed(vcpu)) |
9218 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
9219 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
9220 | else | |
9221 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
9222 | ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
0e851880 SY |
9223 | } |
9224 | ||
d4330ef2 JR |
9225 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
9226 | { | |
7b8050f5 NHE |
9227 | if (func == 1 && nested) |
9228 | entry->ecx |= bit(X86_FEATURE_VMX); | |
d4330ef2 JR |
9229 | } |
9230 | ||
25d92081 YZ |
9231 | static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, |
9232 | struct x86_exception *fault) | |
9233 | { | |
533558bc JK |
9234 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
9235 | u32 exit_reason; | |
25d92081 YZ |
9236 | |
9237 | if (fault->error_code & PFERR_RSVD_MASK) | |
533558bc | 9238 | exit_reason = EXIT_REASON_EPT_MISCONFIG; |
25d92081 | 9239 | else |
533558bc JK |
9240 | exit_reason = EXIT_REASON_EPT_VIOLATION; |
9241 | nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification); | |
25d92081 YZ |
9242 | vmcs12->guest_physical_address = fault->address; |
9243 | } | |
9244 | ||
155a97a3 NHE |
9245 | /* Callbacks for nested_ept_init_mmu_context: */ |
9246 | ||
9247 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu) | |
9248 | { | |
9249 | /* return the page table to be shadowed - in our case, EPT12 */ | |
9250 | return get_vmcs12(vcpu)->ept_pointer; | |
9251 | } | |
9252 | ||
8a3c1a33 | 9253 | static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) |
155a97a3 | 9254 | { |
ad896af0 PB |
9255 | WARN_ON(mmu_is_nested(vcpu)); |
9256 | kvm_init_shadow_ept_mmu(vcpu, | |
b9c237bb WV |
9257 | to_vmx(vcpu)->nested.nested_vmx_ept_caps & |
9258 | VMX_EPT_EXECUTE_ONLY_BIT); | |
155a97a3 NHE |
9259 | vcpu->arch.mmu.set_cr3 = vmx_set_cr3; |
9260 | vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3; | |
9261 | vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault; | |
9262 | ||
9263 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
155a97a3 NHE |
9264 | } |
9265 | ||
9266 | static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
9267 | { | |
9268 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
9269 | } | |
9270 | ||
19d5f10b EK |
9271 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, |
9272 | u16 error_code) | |
9273 | { | |
9274 | bool inequality, bit; | |
9275 | ||
9276 | bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0; | |
9277 | inequality = | |
9278 | (error_code & vmcs12->page_fault_error_code_mask) != | |
9279 | vmcs12->page_fault_error_code_match; | |
9280 | return inequality ^ bit; | |
9281 | } | |
9282 | ||
feaf0c7d GN |
9283 | static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, |
9284 | struct x86_exception *fault) | |
9285 | { | |
9286 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
9287 | ||
9288 | WARN_ON(!is_guest_mode(vcpu)); | |
9289 | ||
19d5f10b | 9290 | if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code)) |
533558bc JK |
9291 | nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason, |
9292 | vmcs_read32(VM_EXIT_INTR_INFO), | |
9293 | vmcs_readl(EXIT_QUALIFICATION)); | |
feaf0c7d GN |
9294 | else |
9295 | kvm_inject_page_fault(vcpu, fault); | |
9296 | } | |
9297 | ||
a2bcba50 WL |
9298 | static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu, |
9299 | struct vmcs12 *vmcs12) | |
9300 | { | |
9301 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9090422f | 9302 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
a2bcba50 WL |
9303 | |
9304 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
9090422f EK |
9305 | if (!PAGE_ALIGNED(vmcs12->apic_access_addr) || |
9306 | vmcs12->apic_access_addr >> maxphyaddr) | |
a2bcba50 WL |
9307 | return false; |
9308 | ||
9309 | /* | |
9310 | * Translate L1 physical address to host physical | |
9311 | * address for vmcs02. Keep the page pinned, so this | |
9312 | * physical address remains valid. We keep a reference | |
9313 | * to it so we can release it later. | |
9314 | */ | |
9315 | if (vmx->nested.apic_access_page) /* shouldn't happen */ | |
9316 | nested_release_page(vmx->nested.apic_access_page); | |
9317 | vmx->nested.apic_access_page = | |
9318 | nested_get_page(vcpu, vmcs12->apic_access_addr); | |
9319 | } | |
a7c0b07d WL |
9320 | |
9321 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
9090422f EK |
9322 | if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) || |
9323 | vmcs12->virtual_apic_page_addr >> maxphyaddr) | |
a7c0b07d WL |
9324 | return false; |
9325 | ||
9326 | if (vmx->nested.virtual_apic_page) /* shouldn't happen */ | |
9327 | nested_release_page(vmx->nested.virtual_apic_page); | |
9328 | vmx->nested.virtual_apic_page = | |
9329 | nested_get_page(vcpu, vmcs12->virtual_apic_page_addr); | |
9330 | ||
9331 | /* | |
9332 | * Failing the vm entry is _not_ what the processor does | |
9333 | * but it's basically the only possibility we have. | |
9334 | * We could still enter the guest if CR8 load exits are | |
9335 | * enabled, CR8 store exits are enabled, and virtualize APIC | |
9336 | * access is disabled; in this case the processor would never | |
9337 | * use the TPR shadow and we could simply clear the bit from | |
9338 | * the execution control. But such a configuration is useless, | |
9339 | * so let's keep the code simple. | |
9340 | */ | |
9341 | if (!vmx->nested.virtual_apic_page) | |
9342 | return false; | |
9343 | } | |
9344 | ||
705699a1 | 9345 | if (nested_cpu_has_posted_intr(vmcs12)) { |
9090422f EK |
9346 | if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) || |
9347 | vmcs12->posted_intr_desc_addr >> maxphyaddr) | |
705699a1 WV |
9348 | return false; |
9349 | ||
9350 | if (vmx->nested.pi_desc_page) { /* shouldn't happen */ | |
9351 | kunmap(vmx->nested.pi_desc_page); | |
9352 | nested_release_page(vmx->nested.pi_desc_page); | |
9353 | } | |
9354 | vmx->nested.pi_desc_page = | |
9355 | nested_get_page(vcpu, vmcs12->posted_intr_desc_addr); | |
9356 | if (!vmx->nested.pi_desc_page) | |
9357 | return false; | |
9358 | ||
9359 | vmx->nested.pi_desc = | |
9360 | (struct pi_desc *)kmap(vmx->nested.pi_desc_page); | |
9361 | if (!vmx->nested.pi_desc) { | |
9362 | nested_release_page_clean(vmx->nested.pi_desc_page); | |
9363 | return false; | |
9364 | } | |
9365 | vmx->nested.pi_desc = | |
9366 | (struct pi_desc *)((void *)vmx->nested.pi_desc + | |
9367 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
9368 | (PAGE_SIZE - 1))); | |
9369 | } | |
9370 | ||
a2bcba50 WL |
9371 | return true; |
9372 | } | |
9373 | ||
f4124500 JK |
9374 | static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu) |
9375 | { | |
9376 | u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value; | |
9377 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9378 | ||
9379 | if (vcpu->arch.virtual_tsc_khz == 0) | |
9380 | return; | |
9381 | ||
9382 | /* Make sure short timeouts reliably trigger an immediate vmexit. | |
9383 | * hrtimer_start does not guarantee this. */ | |
9384 | if (preemption_timeout <= 1) { | |
9385 | vmx_preemption_timer_fn(&vmx->nested.preemption_timer); | |
9386 | return; | |
9387 | } | |
9388 | ||
9389 | preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
9390 | preemption_timeout *= 1000000; | |
9391 | do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); | |
9392 | hrtimer_start(&vmx->nested.preemption_timer, | |
9393 | ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL); | |
9394 | } | |
9395 | ||
3af18d9c WV |
9396 | static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, |
9397 | struct vmcs12 *vmcs12) | |
9398 | { | |
9399 | int maxphyaddr; | |
9400 | u64 addr; | |
9401 | ||
9402 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) | |
9403 | return 0; | |
9404 | ||
9405 | if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) { | |
9406 | WARN_ON(1); | |
9407 | return -EINVAL; | |
9408 | } | |
9409 | maxphyaddr = cpuid_maxphyaddr(vcpu); | |
9410 | ||
9411 | if (!PAGE_ALIGNED(vmcs12->msr_bitmap) || | |
9412 | ((addr + PAGE_SIZE) >> maxphyaddr)) | |
9413 | return -EINVAL; | |
9414 | ||
9415 | return 0; | |
9416 | } | |
9417 | ||
9418 | /* | |
9419 | * Merge L0's and L1's MSR bitmap, return false to indicate that | |
9420 | * we do not use the hardware. | |
9421 | */ | |
9422 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, | |
9423 | struct vmcs12 *vmcs12) | |
9424 | { | |
82f0dd4b | 9425 | int msr; |
f2b93280 | 9426 | struct page *page; |
d048c098 RK |
9427 | unsigned long *msr_bitmap_l1; |
9428 | unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap; | |
f2b93280 | 9429 | |
d048c098 | 9430 | /* This shortcut is ok because we support only x2APIC MSRs so far. */ |
f2b93280 WV |
9431 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12)) |
9432 | return false; | |
9433 | ||
9434 | page = nested_get_page(vcpu, vmcs12->msr_bitmap); | |
9435 | if (!page) { | |
9436 | WARN_ON(1); | |
9437 | return false; | |
9438 | } | |
d048c098 RK |
9439 | msr_bitmap_l1 = (unsigned long *)kmap(page); |
9440 | if (!msr_bitmap_l1) { | |
f2b93280 WV |
9441 | nested_release_page_clean(page); |
9442 | WARN_ON(1); | |
9443 | return false; | |
9444 | } | |
9445 | ||
d048c098 RK |
9446 | memset(msr_bitmap_l0, 0xff, PAGE_SIZE); |
9447 | ||
f2b93280 | 9448 | if (nested_cpu_has_virt_x2apic_mode(vmcs12)) { |
82f0dd4b WV |
9449 | if (nested_cpu_has_apic_reg_virt(vmcs12)) |
9450 | for (msr = 0x800; msr <= 0x8ff; msr++) | |
9451 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 9452 | msr_bitmap_l1, msr_bitmap_l0, |
82f0dd4b | 9453 | msr, MSR_TYPE_R); |
d048c098 RK |
9454 | |
9455 | nested_vmx_disable_intercept_for_msr( | |
9456 | msr_bitmap_l1, msr_bitmap_l0, | |
f2b93280 WV |
9457 | APIC_BASE_MSR + (APIC_TASKPRI >> 4), |
9458 | MSR_TYPE_R | MSR_TYPE_W); | |
d048c098 | 9459 | |
608406e2 | 9460 | if (nested_cpu_has_vid(vmcs12)) { |
608406e2 | 9461 | nested_vmx_disable_intercept_for_msr( |
d048c098 | 9462 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
9463 | APIC_BASE_MSR + (APIC_EOI >> 4), |
9464 | MSR_TYPE_W); | |
9465 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 9466 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
9467 | APIC_BASE_MSR + (APIC_SELF_IPI >> 4), |
9468 | MSR_TYPE_W); | |
9469 | } | |
82f0dd4b | 9470 | } |
f2b93280 WV |
9471 | kunmap(page); |
9472 | nested_release_page_clean(page); | |
9473 | ||
9474 | return true; | |
9475 | } | |
9476 | ||
9477 | static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu, | |
9478 | struct vmcs12 *vmcs12) | |
9479 | { | |
82f0dd4b | 9480 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && |
608406e2 | 9481 | !nested_cpu_has_apic_reg_virt(vmcs12) && |
705699a1 WV |
9482 | !nested_cpu_has_vid(vmcs12) && |
9483 | !nested_cpu_has_posted_intr(vmcs12)) | |
f2b93280 WV |
9484 | return 0; |
9485 | ||
9486 | /* | |
9487 | * If virtualize x2apic mode is enabled, | |
9488 | * virtualize apic access must be disabled. | |
9489 | */ | |
82f0dd4b WV |
9490 | if (nested_cpu_has_virt_x2apic_mode(vmcs12) && |
9491 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
f2b93280 WV |
9492 | return -EINVAL; |
9493 | ||
608406e2 WV |
9494 | /* |
9495 | * If virtual interrupt delivery is enabled, | |
9496 | * we must exit on external interrupts. | |
9497 | */ | |
9498 | if (nested_cpu_has_vid(vmcs12) && | |
9499 | !nested_exit_on_intr(vcpu)) | |
9500 | return -EINVAL; | |
9501 | ||
705699a1 WV |
9502 | /* |
9503 | * bits 15:8 should be zero in posted_intr_nv, | |
9504 | * the descriptor address has been already checked | |
9505 | * in nested_get_vmcs12_pages. | |
9506 | */ | |
9507 | if (nested_cpu_has_posted_intr(vmcs12) && | |
9508 | (!nested_cpu_has_vid(vmcs12) || | |
9509 | !nested_exit_intr_ack_set(vcpu) || | |
9510 | vmcs12->posted_intr_nv & 0xff00)) | |
9511 | return -EINVAL; | |
9512 | ||
f2b93280 WV |
9513 | /* tpr shadow is needed by all apicv features. */ |
9514 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
9515 | return -EINVAL; | |
9516 | ||
9517 | return 0; | |
3af18d9c WV |
9518 | } |
9519 | ||
e9ac033e EK |
9520 | static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu, |
9521 | unsigned long count_field, | |
92d71bc6 | 9522 | unsigned long addr_field) |
ff651cb6 | 9523 | { |
92d71bc6 | 9524 | int maxphyaddr; |
e9ac033e EK |
9525 | u64 count, addr; |
9526 | ||
9527 | if (vmcs12_read_any(vcpu, count_field, &count) || | |
9528 | vmcs12_read_any(vcpu, addr_field, &addr)) { | |
9529 | WARN_ON(1); | |
9530 | return -EINVAL; | |
9531 | } | |
9532 | if (count == 0) | |
9533 | return 0; | |
92d71bc6 | 9534 | maxphyaddr = cpuid_maxphyaddr(vcpu); |
e9ac033e EK |
9535 | if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr || |
9536 | (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) { | |
bbe41b95 | 9537 | pr_debug_ratelimited( |
e9ac033e EK |
9538 | "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)", |
9539 | addr_field, maxphyaddr, count, addr); | |
9540 | return -EINVAL; | |
9541 | } | |
9542 | return 0; | |
9543 | } | |
9544 | ||
9545 | static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu, | |
9546 | struct vmcs12 *vmcs12) | |
9547 | { | |
e9ac033e EK |
9548 | if (vmcs12->vm_exit_msr_load_count == 0 && |
9549 | vmcs12->vm_exit_msr_store_count == 0 && | |
9550 | vmcs12->vm_entry_msr_load_count == 0) | |
9551 | return 0; /* Fast path */ | |
e9ac033e | 9552 | if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT, |
92d71bc6 | 9553 | VM_EXIT_MSR_LOAD_ADDR) || |
e9ac033e | 9554 | nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT, |
92d71bc6 | 9555 | VM_EXIT_MSR_STORE_ADDR) || |
e9ac033e | 9556 | nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT, |
92d71bc6 | 9557 | VM_ENTRY_MSR_LOAD_ADDR)) |
e9ac033e EK |
9558 | return -EINVAL; |
9559 | return 0; | |
9560 | } | |
9561 | ||
9562 | static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu, | |
9563 | struct vmx_msr_entry *e) | |
9564 | { | |
9565 | /* x2APIC MSR accesses are not allowed */ | |
8a9781f7 | 9566 | if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8) |
e9ac033e EK |
9567 | return -EINVAL; |
9568 | if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */ | |
9569 | e->index == MSR_IA32_UCODE_REV) | |
9570 | return -EINVAL; | |
9571 | if (e->reserved != 0) | |
ff651cb6 WV |
9572 | return -EINVAL; |
9573 | return 0; | |
9574 | } | |
9575 | ||
e9ac033e EK |
9576 | static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu, |
9577 | struct vmx_msr_entry *e) | |
ff651cb6 WV |
9578 | { |
9579 | if (e->index == MSR_FS_BASE || | |
9580 | e->index == MSR_GS_BASE || | |
e9ac033e EK |
9581 | e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */ |
9582 | nested_vmx_msr_check_common(vcpu, e)) | |
9583 | return -EINVAL; | |
9584 | return 0; | |
9585 | } | |
9586 | ||
9587 | static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu, | |
9588 | struct vmx_msr_entry *e) | |
9589 | { | |
9590 | if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */ | |
9591 | nested_vmx_msr_check_common(vcpu, e)) | |
ff651cb6 WV |
9592 | return -EINVAL; |
9593 | return 0; | |
9594 | } | |
9595 | ||
9596 | /* | |
9597 | * Load guest's/host's msr at nested entry/exit. | |
9598 | * return 0 for success, entry index for failure. | |
9599 | */ | |
9600 | static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
9601 | { | |
9602 | u32 i; | |
9603 | struct vmx_msr_entry e; | |
9604 | struct msr_data msr; | |
9605 | ||
9606 | msr.host_initiated = false; | |
9607 | for (i = 0; i < count; i++) { | |
54bf36aa PB |
9608 | if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e), |
9609 | &e, sizeof(e))) { | |
bbe41b95 | 9610 | pr_debug_ratelimited( |
e9ac033e EK |
9611 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
9612 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 9613 | goto fail; |
e9ac033e EK |
9614 | } |
9615 | if (nested_vmx_load_msr_check(vcpu, &e)) { | |
bbe41b95 | 9616 | pr_debug_ratelimited( |
e9ac033e EK |
9617 | "%s check failed (%u, 0x%x, 0x%x)\n", |
9618 | __func__, i, e.index, e.reserved); | |
9619 | goto fail; | |
9620 | } | |
ff651cb6 WV |
9621 | msr.index = e.index; |
9622 | msr.data = e.value; | |
e9ac033e | 9623 | if (kvm_set_msr(vcpu, &msr)) { |
bbe41b95 | 9624 | pr_debug_ratelimited( |
e9ac033e EK |
9625 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
9626 | __func__, i, e.index, e.value); | |
ff651cb6 | 9627 | goto fail; |
e9ac033e | 9628 | } |
ff651cb6 WV |
9629 | } |
9630 | return 0; | |
9631 | fail: | |
9632 | return i + 1; | |
9633 | } | |
9634 | ||
9635 | static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
9636 | { | |
9637 | u32 i; | |
9638 | struct vmx_msr_entry e; | |
9639 | ||
9640 | for (i = 0; i < count; i++) { | |
609e36d3 | 9641 | struct msr_data msr_info; |
54bf36aa PB |
9642 | if (kvm_vcpu_read_guest(vcpu, |
9643 | gpa + i * sizeof(e), | |
9644 | &e, 2 * sizeof(u32))) { | |
bbe41b95 | 9645 | pr_debug_ratelimited( |
e9ac033e EK |
9646 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
9647 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 9648 | return -EINVAL; |
e9ac033e EK |
9649 | } |
9650 | if (nested_vmx_store_msr_check(vcpu, &e)) { | |
bbe41b95 | 9651 | pr_debug_ratelimited( |
e9ac033e EK |
9652 | "%s check failed (%u, 0x%x, 0x%x)\n", |
9653 | __func__, i, e.index, e.reserved); | |
ff651cb6 | 9654 | return -EINVAL; |
e9ac033e | 9655 | } |
609e36d3 PB |
9656 | msr_info.host_initiated = false; |
9657 | msr_info.index = e.index; | |
9658 | if (kvm_get_msr(vcpu, &msr_info)) { | |
bbe41b95 | 9659 | pr_debug_ratelimited( |
e9ac033e EK |
9660 | "%s cannot read MSR (%u, 0x%x)\n", |
9661 | __func__, i, e.index); | |
9662 | return -EINVAL; | |
9663 | } | |
54bf36aa PB |
9664 | if (kvm_vcpu_write_guest(vcpu, |
9665 | gpa + i * sizeof(e) + | |
9666 | offsetof(struct vmx_msr_entry, value), | |
9667 | &msr_info.data, sizeof(msr_info.data))) { | |
bbe41b95 | 9668 | pr_debug_ratelimited( |
e9ac033e | 9669 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
609e36d3 | 9670 | __func__, i, e.index, msr_info.data); |
e9ac033e EK |
9671 | return -EINVAL; |
9672 | } | |
ff651cb6 WV |
9673 | } |
9674 | return 0; | |
9675 | } | |
9676 | ||
fe3ef05c NHE |
9677 | /* |
9678 | * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested | |
9679 | * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it | |
b4619660 | 9680 | * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 |
fe3ef05c NHE |
9681 | * guest in a way that will both be appropriate to L1's requests, and our |
9682 | * needs. In addition to modifying the active vmcs (which is vmcs02), this | |
9683 | * function also has additional necessary side-effects, like setting various | |
9684 | * vcpu->arch fields. | |
9685 | */ | |
9686 | static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
9687 | { | |
9688 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9689 | u32 exec_control; | |
9690 | ||
9691 | vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); | |
9692 | vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); | |
9693 | vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); | |
9694 | vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); | |
9695 | vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); | |
9696 | vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); | |
9697 | vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); | |
9698 | vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); | |
9699 | vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); | |
9700 | vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); | |
9701 | vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); | |
9702 | vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); | |
9703 | vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); | |
9704 | vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); | |
9705 | vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); | |
9706 | vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); | |
9707 | vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); | |
9708 | vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); | |
9709 | vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); | |
9710 | vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); | |
9711 | vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); | |
9712 | vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); | |
9713 | vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); | |
9714 | vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); | |
9715 | vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); | |
9716 | vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); | |
9717 | vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); | |
9718 | vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); | |
9719 | vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); | |
9720 | vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); | |
9721 | vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); | |
9722 | vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); | |
9723 | vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); | |
9724 | vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); | |
9725 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); | |
9726 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); | |
9727 | ||
2996fca0 JK |
9728 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) { |
9729 | kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); | |
9730 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); | |
9731 | } else { | |
9732 | kvm_set_dr(vcpu, 7, vcpu->arch.dr7); | |
9733 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl); | |
9734 | } | |
fe3ef05c NHE |
9735 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
9736 | vmcs12->vm_entry_intr_info_field); | |
9737 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
9738 | vmcs12->vm_entry_exception_error_code); | |
9739 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
9740 | vmcs12->vm_entry_instruction_len); | |
9741 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
9742 | vmcs12->guest_interruptibility_info); | |
fe3ef05c | 9743 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); |
63fbf59f | 9744 | vmx_set_rflags(vcpu, vmcs12->guest_rflags); |
fe3ef05c NHE |
9745 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, |
9746 | vmcs12->guest_pending_dbg_exceptions); | |
9747 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); | |
9748 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); | |
9749 | ||
81dc01f7 WL |
9750 | if (nested_cpu_has_xsaves(vmcs12)) |
9751 | vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); | |
fe3ef05c NHE |
9752 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
9753 | ||
f4124500 | 9754 | exec_control = vmcs12->pin_based_vm_exec_control; |
9314006d PB |
9755 | |
9756 | /* Preemption timer setting is only taken from vmcs01. */ | |
705699a1 | 9757 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; |
9314006d PB |
9758 | exec_control |= vmcs_config.pin_based_exec_ctrl; |
9759 | if (vmx->hv_deadline_tsc == -1) | |
9760 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
705699a1 | 9761 | |
9314006d | 9762 | /* Posted interrupts setting is only taken from vmcs12. */ |
705699a1 WV |
9763 | if (nested_cpu_has_posted_intr(vmcs12)) { |
9764 | /* | |
9765 | * Note that we use L0's vector here and in | |
9766 | * vmx_deliver_nested_posted_interrupt. | |
9767 | */ | |
9768 | vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv; | |
9769 | vmx->nested.pi_pending = false; | |
0bcf261c | 9770 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
705699a1 WV |
9771 | vmcs_write64(POSTED_INTR_DESC_ADDR, |
9772 | page_to_phys(vmx->nested.pi_desc_page) + | |
9773 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
9774 | (PAGE_SIZE - 1))); | |
9775 | } else | |
9776 | exec_control &= ~PIN_BASED_POSTED_INTR; | |
9777 | ||
f4124500 | 9778 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control); |
fe3ef05c | 9779 | |
f4124500 JK |
9780 | vmx->nested.preemption_timer_expired = false; |
9781 | if (nested_cpu_has_preemption_timer(vmcs12)) | |
9782 | vmx_start_preemption_timer(vcpu); | |
0238ea91 | 9783 | |
fe3ef05c NHE |
9784 | /* |
9785 | * Whether page-faults are trapped is determined by a combination of | |
9786 | * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. | |
9787 | * If enable_ept, L0 doesn't care about page faults and we should | |
9788 | * set all of these to L1's desires. However, if !enable_ept, L0 does | |
9789 | * care about (at least some) page faults, and because it is not easy | |
9790 | * (if at all possible?) to merge L0 and L1's desires, we simply ask | |
9791 | * to exit on each and every L2 page fault. This is done by setting | |
9792 | * MASK=MATCH=0 and (see below) EB.PF=1. | |
9793 | * Note that below we don't need special code to set EB.PF beyond the | |
9794 | * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, | |
9795 | * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when | |
9796 | * !enable_ept, EB.PF is 1, so the "or" will always be 1. | |
9797 | * | |
9798 | * A problem with this approach (when !enable_ept) is that L1 may be | |
9799 | * injected with more page faults than it asked for. This could have | |
9800 | * caused problems, but in practice existing hypervisors don't care. | |
9801 | * To fix this, we will need to emulate the PFEC checking (on the L1 | |
9802 | * page tables), using walk_addr(), when injecting PFs to L1. | |
9803 | */ | |
9804 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, | |
9805 | enable_ept ? vmcs12->page_fault_error_code_mask : 0); | |
9806 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, | |
9807 | enable_ept ? vmcs12->page_fault_error_code_match : 0); | |
9808 | ||
9809 | if (cpu_has_secondary_exec_ctrls()) { | |
f4124500 | 9810 | exec_control = vmx_secondary_exec_control(vmx); |
e2821620 | 9811 | |
fe3ef05c | 9812 | /* Take the following fields only from vmcs12 */ |
696dfd95 | 9813 | exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
b3a2a907 | 9814 | SECONDARY_EXEC_RDTSCP | |
696dfd95 | 9815 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
dfa169bb | 9816 | SECONDARY_EXEC_APIC_REGISTER_VIRT); |
fe3ef05c NHE |
9817 | if (nested_cpu_has(vmcs12, |
9818 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) | |
9819 | exec_control |= vmcs12->secondary_vm_exec_control; | |
9820 | ||
9821 | if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) { | |
fe3ef05c NHE |
9822 | /* |
9823 | * If translation failed, no matter: This feature asks | |
9824 | * to exit when accessing the given address, and if it | |
9825 | * can never be accessed, this feature won't do | |
9826 | * anything anyway. | |
9827 | */ | |
9828 | if (!vmx->nested.apic_access_page) | |
9829 | exec_control &= | |
9830 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
9831 | else | |
9832 | vmcs_write64(APIC_ACCESS_ADDR, | |
9833 | page_to_phys(vmx->nested.apic_access_page)); | |
f2b93280 | 9834 | } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) && |
35754c98 | 9835 | cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
ca3f257a JK |
9836 | exec_control |= |
9837 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
38b99173 | 9838 | kvm_vcpu_reload_apic_access_page(vcpu); |
fe3ef05c NHE |
9839 | } |
9840 | ||
608406e2 WV |
9841 | if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { |
9842 | vmcs_write64(EOI_EXIT_BITMAP0, | |
9843 | vmcs12->eoi_exit_bitmap0); | |
9844 | vmcs_write64(EOI_EXIT_BITMAP1, | |
9845 | vmcs12->eoi_exit_bitmap1); | |
9846 | vmcs_write64(EOI_EXIT_BITMAP2, | |
9847 | vmcs12->eoi_exit_bitmap2); | |
9848 | vmcs_write64(EOI_EXIT_BITMAP3, | |
9849 | vmcs12->eoi_exit_bitmap3); | |
9850 | vmcs_write16(GUEST_INTR_STATUS, | |
9851 | vmcs12->guest_intr_status); | |
9852 | } | |
9853 | ||
fe3ef05c NHE |
9854 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
9855 | } | |
9856 | ||
9857 | ||
9858 | /* | |
9859 | * Set host-state according to L0's settings (vmcs12 is irrelevant here) | |
9860 | * Some constant fields are set here by vmx_set_constant_host_state(). | |
9861 | * Other fields are different per CPU, and will be set later when | |
9862 | * vmx_vcpu_load() is called, and when vmx_save_host_state() is called. | |
9863 | */ | |
a547c6db | 9864 | vmx_set_constant_host_state(vmx); |
fe3ef05c | 9865 | |
83bafef1 JM |
9866 | /* |
9867 | * Set the MSR load/store lists to match L0's settings. | |
9868 | */ | |
9869 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); | |
9870 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
9871 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); | |
9872 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
9873 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); | |
9874 | ||
fe3ef05c NHE |
9875 | /* |
9876 | * HOST_RSP is normally set correctly in vmx_vcpu_run() just before | |
9877 | * entry, but only if the current (host) sp changed from the value | |
9878 | * we wrote last (vmx->host_rsp). This cache is no longer relevant | |
9879 | * if we switch vmcs, and rather than hold a separate cache per vmcs, | |
9880 | * here we just force the write to happen on entry. | |
9881 | */ | |
9882 | vmx->host_rsp = 0; | |
9883 | ||
9884 | exec_control = vmx_exec_control(vmx); /* L0's desires */ | |
9885 | exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
9886 | exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
9887 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
9888 | exec_control |= vmcs12->cpu_based_vm_exec_control; | |
a7c0b07d WL |
9889 | |
9890 | if (exec_control & CPU_BASED_TPR_SHADOW) { | |
9891 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
9892 | page_to_phys(vmx->nested.virtual_apic_page)); | |
9893 | vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); | |
9894 | } | |
9895 | ||
3af18d9c | 9896 | if (cpu_has_vmx_msr_bitmap() && |
d048c098 RK |
9897 | exec_control & CPU_BASED_USE_MSR_BITMAPS && |
9898 | nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) | |
9899 | ; /* MSR_BITMAP will be set by following vmx_set_efer. */ | |
9900 | else | |
3af18d9c WV |
9901 | exec_control &= ~CPU_BASED_USE_MSR_BITMAPS; |
9902 | ||
fe3ef05c | 9903 | /* |
3af18d9c | 9904 | * Merging of IO bitmap not currently supported. |
fe3ef05c NHE |
9905 | * Rather, exit every time. |
9906 | */ | |
fe3ef05c NHE |
9907 | exec_control &= ~CPU_BASED_USE_IO_BITMAPS; |
9908 | exec_control |= CPU_BASED_UNCOND_IO_EXITING; | |
9909 | ||
9910 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
9911 | ||
9912 | /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the | |
9913 | * bitwise-or of what L1 wants to trap for L2, and what we want to | |
9914 | * trap. Note that CR0.TS also needs updating - we do this later. | |
9915 | */ | |
9916 | update_exception_bitmap(vcpu); | |
9917 | vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; | |
9918 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
9919 | ||
8049d651 NHE |
9920 | /* L2->L1 exit controls are emulated - the hardware exit is to L0 so |
9921 | * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER | |
9922 | * bits are further modified by vmx_set_efer() below. | |
9923 | */ | |
f4124500 | 9924 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
8049d651 NHE |
9925 | |
9926 | /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are | |
9927 | * emulated by vmx_set_efer(), below. | |
9928 | */ | |
2961e876 | 9929 | vm_entry_controls_init(vmx, |
8049d651 NHE |
9930 | (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER & |
9931 | ~VM_ENTRY_IA32E_MODE) | | |
fe3ef05c NHE |
9932 | (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE)); |
9933 | ||
44811c02 | 9934 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) { |
fe3ef05c | 9935 | vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); |
44811c02 JK |
9936 | vcpu->arch.pat = vmcs12->guest_ia32_pat; |
9937 | } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) | |
fe3ef05c NHE |
9938 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); |
9939 | ||
9940 | ||
9941 | set_cr4_guest_host_mask(vmx); | |
9942 | ||
36be0b9d PB |
9943 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) |
9944 | vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); | |
9945 | ||
27fc51b2 NHE |
9946 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
9947 | vmcs_write64(TSC_OFFSET, | |
ea26e4ec | 9948 | vcpu->arch.tsc_offset + vmcs12->tsc_offset); |
27fc51b2 | 9949 | else |
ea26e4ec | 9950 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
c95ba92a PF |
9951 | if (kvm_has_tsc_control) |
9952 | decache_tsc_multiplier(vmx); | |
fe3ef05c NHE |
9953 | |
9954 | if (enable_vpid) { | |
9955 | /* | |
5c614b35 WL |
9956 | * There is no direct mapping between vpid02 and vpid12, the |
9957 | * vpid02 is per-vCPU for L0 and reused while the value of | |
9958 | * vpid12 is changed w/ one invvpid during nested vmentry. | |
9959 | * The vpid12 is allocated by L1 for L2, so it will not | |
9960 | * influence global bitmap(for vpid01 and vpid02 allocation) | |
9961 | * even if spawn a lot of nested vCPUs. | |
fe3ef05c | 9962 | */ |
5c614b35 WL |
9963 | if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) { |
9964 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02); | |
9965 | if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) { | |
9966 | vmx->nested.last_vpid = vmcs12->virtual_processor_id; | |
9967 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02); | |
9968 | } | |
9969 | } else { | |
9970 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
9971 | vmx_flush_tlb(vcpu); | |
9972 | } | |
9973 | ||
fe3ef05c NHE |
9974 | } |
9975 | ||
155a97a3 NHE |
9976 | if (nested_cpu_has_ept(vmcs12)) { |
9977 | kvm_mmu_unload(vcpu); | |
9978 | nested_ept_init_mmu_context(vcpu); | |
9979 | } | |
9980 | ||
fe3ef05c NHE |
9981 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) |
9982 | vcpu->arch.efer = vmcs12->guest_ia32_efer; | |
d1fa0352 | 9983 | else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) |
fe3ef05c NHE |
9984 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
9985 | else | |
9986 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
9987 | /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ | |
9988 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
9989 | ||
9990 | /* | |
9991 | * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified | |
9992 | * TS bit (for lazy fpu) and bits which we consider mandatory enabled. | |
9993 | * The CR0_READ_SHADOW is what L2 should have expected to read given | |
9994 | * the specifications by L1; It's not enough to take | |
9995 | * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we | |
9996 | * have more bits than L1 expected. | |
9997 | */ | |
9998 | vmx_set_cr0(vcpu, vmcs12->guest_cr0); | |
9999 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
10000 | ||
10001 | vmx_set_cr4(vcpu, vmcs12->guest_cr4); | |
10002 | vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); | |
10003 | ||
10004 | /* shadow page tables on either EPT or shadow page tables */ | |
10005 | kvm_set_cr3(vcpu, vmcs12->guest_cr3); | |
10006 | kvm_mmu_reset_context(vcpu); | |
10007 | ||
feaf0c7d GN |
10008 | if (!enable_ept) |
10009 | vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; | |
10010 | ||
3633cfc3 NHE |
10011 | /* |
10012 | * L1 may access the L2's PDPTR, so save them to construct vmcs12 | |
10013 | */ | |
10014 | if (enable_ept) { | |
10015 | vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); | |
10016 | vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); | |
10017 | vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); | |
10018 | vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); | |
10019 | } | |
10020 | ||
fe3ef05c NHE |
10021 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp); |
10022 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip); | |
10023 | } | |
10024 | ||
cd232ad0 NHE |
10025 | /* |
10026 | * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 | |
10027 | * for running an L2 nested guest. | |
10028 | */ | |
10029 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) | |
10030 | { | |
10031 | struct vmcs12 *vmcs12; | |
10032 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10033 | int cpu; | |
10034 | struct loaded_vmcs *vmcs02; | |
384bb783 | 10035 | bool ia32e; |
ff651cb6 | 10036 | u32 msr_entry_idx; |
cd232ad0 NHE |
10037 | |
10038 | if (!nested_vmx_check_permission(vcpu) || | |
10039 | !nested_vmx_check_vmcs12(vcpu)) | |
10040 | return 1; | |
10041 | ||
10042 | skip_emulated_instruction(vcpu); | |
10043 | vmcs12 = get_vmcs12(vcpu); | |
10044 | ||
012f83cb AG |
10045 | if (enable_shadow_vmcs) |
10046 | copy_shadow_to_vmcs12(vmx); | |
10047 | ||
7c177938 NHE |
10048 | /* |
10049 | * The nested entry process starts with enforcing various prerequisites | |
10050 | * on vmcs12 as required by the Intel SDM, and act appropriately when | |
10051 | * they fail: As the SDM explains, some conditions should cause the | |
10052 | * instruction to fail, while others will cause the instruction to seem | |
10053 | * to succeed, but return an EXIT_REASON_INVALID_STATE. | |
10054 | * To speed up the normal (success) code path, we should avoid checking | |
10055 | * for misconfigurations which will anyway be caught by the processor | |
10056 | * when using the merged vmcs02. | |
10057 | */ | |
10058 | if (vmcs12->launch_state == launch) { | |
10059 | nested_vmx_failValid(vcpu, | |
10060 | launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS | |
10061 | : VMXERR_VMRESUME_NONLAUNCHED_VMCS); | |
10062 | return 1; | |
10063 | } | |
10064 | ||
6dfacadd JK |
10065 | if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && |
10066 | vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) { | |
26539bd0 PB |
10067 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
10068 | return 1; | |
10069 | } | |
10070 | ||
3af18d9c | 10071 | if (!nested_get_vmcs12_pages(vcpu, vmcs12)) { |
7c177938 NHE |
10072 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
10073 | return 1; | |
10074 | } | |
10075 | ||
3af18d9c | 10076 | if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) { |
7c177938 NHE |
10077 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
10078 | return 1; | |
10079 | } | |
10080 | ||
f2b93280 WV |
10081 | if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) { |
10082 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
10083 | return 1; | |
10084 | } | |
10085 | ||
e9ac033e EK |
10086 | if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) { |
10087 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
10088 | return 1; | |
10089 | } | |
10090 | ||
7c177938 | 10091 | if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, |
b9c237bb WV |
10092 | vmx->nested.nested_vmx_true_procbased_ctls_low, |
10093 | vmx->nested.nested_vmx_procbased_ctls_high) || | |
7c177938 | 10094 | !vmx_control_verify(vmcs12->secondary_vm_exec_control, |
b9c237bb WV |
10095 | vmx->nested.nested_vmx_secondary_ctls_low, |
10096 | vmx->nested.nested_vmx_secondary_ctls_high) || | |
7c177938 | 10097 | !vmx_control_verify(vmcs12->pin_based_vm_exec_control, |
b9c237bb WV |
10098 | vmx->nested.nested_vmx_pinbased_ctls_low, |
10099 | vmx->nested.nested_vmx_pinbased_ctls_high) || | |
7c177938 | 10100 | !vmx_control_verify(vmcs12->vm_exit_controls, |
b9c237bb WV |
10101 | vmx->nested.nested_vmx_true_exit_ctls_low, |
10102 | vmx->nested.nested_vmx_exit_ctls_high) || | |
7c177938 | 10103 | !vmx_control_verify(vmcs12->vm_entry_controls, |
b9c237bb WV |
10104 | vmx->nested.nested_vmx_true_entry_ctls_low, |
10105 | vmx->nested.nested_vmx_entry_ctls_high)) | |
7c177938 NHE |
10106 | { |
10107 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
10108 | return 1; | |
10109 | } | |
10110 | ||
10111 | if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) || | |
10112 | ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) { | |
10113 | nested_vmx_failValid(vcpu, | |
10114 | VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); | |
10115 | return 1; | |
10116 | } | |
10117 | ||
b9c237bb | 10118 | if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) || |
7c177938 NHE |
10119 | ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) { |
10120 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10121 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
10122 | return 1; | |
10123 | } | |
10124 | if (vmcs12->vmcs_link_pointer != -1ull) { | |
10125 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10126 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR); | |
10127 | return 1; | |
10128 | } | |
10129 | ||
384bb783 | 10130 | /* |
cb0c8cda | 10131 | * If the load IA32_EFER VM-entry control is 1, the following checks |
384bb783 JK |
10132 | * are performed on the field for the IA32_EFER MSR: |
10133 | * - Bits reserved in the IA32_EFER MSR must be 0. | |
10134 | * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of | |
10135 | * the IA-32e mode guest VM-exit control. It must also be identical | |
10136 | * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to | |
10137 | * CR0.PG) is 1. | |
10138 | */ | |
10139 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) { | |
10140 | ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; | |
10141 | if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) || | |
10142 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) || | |
10143 | ((vmcs12->guest_cr0 & X86_CR0_PG) && | |
10144 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) { | |
10145 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10146 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
10147 | return 1; | |
10148 | } | |
10149 | } | |
10150 | ||
10151 | /* | |
10152 | * If the load IA32_EFER VM-exit control is 1, bits reserved in the | |
10153 | * IA32_EFER MSR must be 0 in the field for that register. In addition, | |
10154 | * the values of the LMA and LME bits in the field must each be that of | |
10155 | * the host address-space size VM-exit control. | |
10156 | */ | |
10157 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { | |
10158 | ia32e = (vmcs12->vm_exit_controls & | |
10159 | VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0; | |
10160 | if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) || | |
10161 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) || | |
10162 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) { | |
10163 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10164 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
10165 | return 1; | |
10166 | } | |
10167 | } | |
10168 | ||
7c177938 NHE |
10169 | /* |
10170 | * We're finally done with prerequisite checking, and can start with | |
10171 | * the nested entry. | |
10172 | */ | |
10173 | ||
cd232ad0 NHE |
10174 | vmcs02 = nested_get_current_vmcs02(vmx); |
10175 | if (!vmcs02) | |
10176 | return -ENOMEM; | |
10177 | ||
10178 | enter_guest_mode(vcpu); | |
10179 | ||
2996fca0 JK |
10180 | if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) |
10181 | vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
10182 | ||
cd232ad0 NHE |
10183 | cpu = get_cpu(); |
10184 | vmx->loaded_vmcs = vmcs02; | |
10185 | vmx_vcpu_put(vcpu); | |
10186 | vmx_vcpu_load(vcpu, cpu); | |
10187 | vcpu->cpu = cpu; | |
10188 | put_cpu(); | |
10189 | ||
36c3cc42 JK |
10190 | vmx_segment_cache_clear(vmx); |
10191 | ||
cd232ad0 NHE |
10192 | prepare_vmcs02(vcpu, vmcs12); |
10193 | ||
ff651cb6 WV |
10194 | msr_entry_idx = nested_vmx_load_msr(vcpu, |
10195 | vmcs12->vm_entry_msr_load_addr, | |
10196 | vmcs12->vm_entry_msr_load_count); | |
10197 | if (msr_entry_idx) { | |
10198 | leave_guest_mode(vcpu); | |
10199 | vmx_load_vmcs01(vcpu); | |
10200 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10201 | EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx); | |
10202 | return 1; | |
10203 | } | |
10204 | ||
10205 | vmcs12->launch_state = 1; | |
10206 | ||
6dfacadd | 10207 | if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) |
5cb56059 | 10208 | return kvm_vcpu_halt(vcpu); |
6dfacadd | 10209 | |
7af40ad3 JK |
10210 | vmx->nested.nested_run_pending = 1; |
10211 | ||
cd232ad0 NHE |
10212 | /* |
10213 | * Note no nested_vmx_succeed or nested_vmx_fail here. At this point | |
10214 | * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet | |
10215 | * returned as far as L1 is concerned. It will only return (and set | |
10216 | * the success flag) when L2 exits (see nested_vmx_vmexit()). | |
10217 | */ | |
10218 | return 1; | |
10219 | } | |
10220 | ||
4704d0be NHE |
10221 | /* |
10222 | * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date | |
10223 | * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK). | |
10224 | * This function returns the new value we should put in vmcs12.guest_cr0. | |
10225 | * It's not enough to just return the vmcs02 GUEST_CR0. Rather, | |
10226 | * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now | |
10227 | * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 | |
10228 | * didn't trap the bit, because if L1 did, so would L0). | |
10229 | * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have | |
10230 | * been modified by L2, and L1 knows it. So just leave the old value of | |
10231 | * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 | |
10232 | * isn't relevant, because if L0 traps this bit it can set it to anything. | |
10233 | * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have | |
10234 | * changed these bits, and therefore they need to be updated, but L0 | |
10235 | * didn't necessarily allow them to be changed in GUEST_CR0 - and rather | |
10236 | * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. | |
10237 | */ | |
10238 | static inline unsigned long | |
10239 | vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
10240 | { | |
10241 | return | |
10242 | /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | | |
10243 | /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | | |
10244 | /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | | |
10245 | vcpu->arch.cr0_guest_owned_bits)); | |
10246 | } | |
10247 | ||
10248 | static inline unsigned long | |
10249 | vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
10250 | { | |
10251 | return | |
10252 | /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | | |
10253 | /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | | |
10254 | /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | | |
10255 | vcpu->arch.cr4_guest_owned_bits)); | |
10256 | } | |
10257 | ||
5f3d5799 JK |
10258 | static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, |
10259 | struct vmcs12 *vmcs12) | |
10260 | { | |
10261 | u32 idt_vectoring; | |
10262 | unsigned int nr; | |
10263 | ||
851eb667 | 10264 | if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) { |
5f3d5799 JK |
10265 | nr = vcpu->arch.exception.nr; |
10266 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
10267 | ||
10268 | if (kvm_exception_is_soft(nr)) { | |
10269 | vmcs12->vm_exit_instruction_len = | |
10270 | vcpu->arch.event_exit_inst_len; | |
10271 | idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; | |
10272 | } else | |
10273 | idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; | |
10274 | ||
10275 | if (vcpu->arch.exception.has_error_code) { | |
10276 | idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; | |
10277 | vmcs12->idt_vectoring_error_code = | |
10278 | vcpu->arch.exception.error_code; | |
10279 | } | |
10280 | ||
10281 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
cd2633c5 | 10282 | } else if (vcpu->arch.nmi_injected) { |
5f3d5799 JK |
10283 | vmcs12->idt_vectoring_info_field = |
10284 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; | |
10285 | } else if (vcpu->arch.interrupt.pending) { | |
10286 | nr = vcpu->arch.interrupt.nr; | |
10287 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
10288 | ||
10289 | if (vcpu->arch.interrupt.soft) { | |
10290 | idt_vectoring |= INTR_TYPE_SOFT_INTR; | |
10291 | vmcs12->vm_entry_instruction_len = | |
10292 | vcpu->arch.event_exit_inst_len; | |
10293 | } else | |
10294 | idt_vectoring |= INTR_TYPE_EXT_INTR; | |
10295 | ||
10296 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
10297 | } | |
10298 | } | |
10299 | ||
b6b8a145 JK |
10300 | static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) |
10301 | { | |
10302 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10303 | ||
f4124500 JK |
10304 | if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && |
10305 | vmx->nested.preemption_timer_expired) { | |
10306 | if (vmx->nested.nested_run_pending) | |
10307 | return -EBUSY; | |
10308 | nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); | |
10309 | return 0; | |
10310 | } | |
10311 | ||
b6b8a145 | 10312 | if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) { |
220c5672 JK |
10313 | if (vmx->nested.nested_run_pending || |
10314 | vcpu->arch.interrupt.pending) | |
b6b8a145 JK |
10315 | return -EBUSY; |
10316 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
10317 | NMI_VECTOR | INTR_TYPE_NMI_INTR | | |
10318 | INTR_INFO_VALID_MASK, 0); | |
10319 | /* | |
10320 | * The NMI-triggered VM exit counts as injection: | |
10321 | * clear this one and block further NMIs. | |
10322 | */ | |
10323 | vcpu->arch.nmi_pending = 0; | |
10324 | vmx_set_nmi_mask(vcpu, true); | |
10325 | return 0; | |
10326 | } | |
10327 | ||
10328 | if ((kvm_cpu_has_interrupt(vcpu) || external_intr) && | |
10329 | nested_exit_on_intr(vcpu)) { | |
10330 | if (vmx->nested.nested_run_pending) | |
10331 | return -EBUSY; | |
10332 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); | |
705699a1 | 10333 | return 0; |
b6b8a145 JK |
10334 | } |
10335 | ||
705699a1 | 10336 | return vmx_complete_nested_posted_interrupt(vcpu); |
b6b8a145 JK |
10337 | } |
10338 | ||
f4124500 JK |
10339 | static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) |
10340 | { | |
10341 | ktime_t remaining = | |
10342 | hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); | |
10343 | u64 value; | |
10344 | ||
10345 | if (ktime_to_ns(remaining) <= 0) | |
10346 | return 0; | |
10347 | ||
10348 | value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; | |
10349 | do_div(value, 1000000); | |
10350 | return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
10351 | } | |
10352 | ||
4704d0be NHE |
10353 | /* |
10354 | * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits | |
10355 | * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), | |
10356 | * and this function updates it to reflect the changes to the guest state while | |
10357 | * L2 was running (and perhaps made some exits which were handled directly by L0 | |
10358 | * without going back to L1), and to reflect the exit reason. | |
10359 | * Note that we do not have to copy here all VMCS fields, just those that | |
10360 | * could have changed by the L2 guest or the exit - i.e., the guest-state and | |
10361 | * exit-information fields only. Other fields are modified by L1 with VMWRITE, | |
10362 | * which already writes to vmcs12 directly. | |
10363 | */ | |
533558bc JK |
10364 | static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, |
10365 | u32 exit_reason, u32 exit_intr_info, | |
10366 | unsigned long exit_qualification) | |
4704d0be NHE |
10367 | { |
10368 | /* update guest state fields: */ | |
10369 | vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); | |
10370 | vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); | |
10371 | ||
4704d0be NHE |
10372 | vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); |
10373 | vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP); | |
10374 | vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); | |
10375 | ||
10376 | vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); | |
10377 | vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); | |
10378 | vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); | |
10379 | vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); | |
10380 | vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); | |
10381 | vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); | |
10382 | vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); | |
10383 | vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); | |
10384 | vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); | |
10385 | vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); | |
10386 | vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
10387 | vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); | |
10388 | vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); | |
10389 | vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); | |
10390 | vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); | |
10391 | vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); | |
10392 | vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
10393 | vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
10394 | vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); | |
10395 | vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); | |
10396 | vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); | |
10397 | vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); | |
10398 | vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); | |
10399 | vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); | |
10400 | vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); | |
10401 | vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); | |
10402 | vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); | |
10403 | vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); | |
10404 | vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); | |
10405 | vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); | |
10406 | vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); | |
10407 | vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); | |
10408 | vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); | |
10409 | vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); | |
10410 | vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); | |
10411 | vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); | |
10412 | ||
4704d0be NHE |
10413 | vmcs12->guest_interruptibility_info = |
10414 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
10415 | vmcs12->guest_pending_dbg_exceptions = | |
10416 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); | |
3edf1e69 JK |
10417 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
10418 | vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; | |
10419 | else | |
10420 | vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; | |
4704d0be | 10421 | |
f4124500 JK |
10422 | if (nested_cpu_has_preemption_timer(vmcs12)) { |
10423 | if (vmcs12->vm_exit_controls & | |
10424 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER) | |
10425 | vmcs12->vmx_preemption_timer_value = | |
10426 | vmx_get_preemption_timer_value(vcpu); | |
10427 | hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); | |
10428 | } | |
7854cbca | 10429 | |
3633cfc3 NHE |
10430 | /* |
10431 | * In some cases (usually, nested EPT), L2 is allowed to change its | |
10432 | * own CR3 without exiting. If it has changed it, we must keep it. | |
10433 | * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined | |
10434 | * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. | |
10435 | * | |
10436 | * Additionally, restore L2's PDPTR to vmcs12. | |
10437 | */ | |
10438 | if (enable_ept) { | |
f3531054 | 10439 | vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3); |
3633cfc3 NHE |
10440 | vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); |
10441 | vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); | |
10442 | vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); | |
10443 | vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); | |
10444 | } | |
10445 | ||
119a9c01 JD |
10446 | if (nested_cpu_has_ept(vmcs12)) |
10447 | vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS); | |
10448 | ||
608406e2 WV |
10449 | if (nested_cpu_has_vid(vmcs12)) |
10450 | vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS); | |
10451 | ||
c18911a2 JK |
10452 | vmcs12->vm_entry_controls = |
10453 | (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | | |
2961e876 | 10454 | (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); |
c18911a2 | 10455 | |
2996fca0 JK |
10456 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) { |
10457 | kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); | |
10458 | vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
10459 | } | |
10460 | ||
4704d0be NHE |
10461 | /* TODO: These cannot have changed unless we have MSR bitmaps and |
10462 | * the relevant bit asks not to trap the change */ | |
b8c07d55 | 10463 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) |
4704d0be | 10464 | vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT); |
10ba54a5 JK |
10465 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) |
10466 | vmcs12->guest_ia32_efer = vcpu->arch.efer; | |
4704d0be NHE |
10467 | vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS); |
10468 | vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP); | |
10469 | vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP); | |
a87036ad | 10470 | if (kvm_mpx_supported()) |
36be0b9d | 10471 | vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); |
81dc01f7 WL |
10472 | if (nested_cpu_has_xsaves(vmcs12)) |
10473 | vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP); | |
4704d0be NHE |
10474 | |
10475 | /* update exit information fields: */ | |
10476 | ||
533558bc JK |
10477 | vmcs12->vm_exit_reason = exit_reason; |
10478 | vmcs12->exit_qualification = exit_qualification; | |
4704d0be | 10479 | |
533558bc | 10480 | vmcs12->vm_exit_intr_info = exit_intr_info; |
c0d1c770 JK |
10481 | if ((vmcs12->vm_exit_intr_info & |
10482 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) == | |
10483 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) | |
10484 | vmcs12->vm_exit_intr_error_code = | |
10485 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
5f3d5799 | 10486 | vmcs12->idt_vectoring_info_field = 0; |
4704d0be NHE |
10487 | vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
10488 | vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
10489 | ||
5f3d5799 JK |
10490 | if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { |
10491 | /* vm_entry_intr_info_field is cleared on exit. Emulate this | |
10492 | * instead of reading the real value. */ | |
4704d0be | 10493 | vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; |
5f3d5799 JK |
10494 | |
10495 | /* | |
10496 | * Transfer the event that L0 or L1 may wanted to inject into | |
10497 | * L2 to IDT_VECTORING_INFO_FIELD. | |
10498 | */ | |
10499 | vmcs12_save_pending_event(vcpu, vmcs12); | |
10500 | } | |
10501 | ||
10502 | /* | |
10503 | * Drop what we picked up for L2 via vmx_complete_interrupts. It is | |
10504 | * preserved above and would only end up incorrectly in L1. | |
10505 | */ | |
10506 | vcpu->arch.nmi_injected = false; | |
10507 | kvm_clear_exception_queue(vcpu); | |
10508 | kvm_clear_interrupt_queue(vcpu); | |
4704d0be NHE |
10509 | } |
10510 | ||
10511 | /* | |
10512 | * A part of what we need to when the nested L2 guest exits and we want to | |
10513 | * run its L1 parent, is to reset L1's guest state to the host state specified | |
10514 | * in vmcs12. | |
10515 | * This function is to be called not only on normal nested exit, but also on | |
10516 | * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry | |
10517 | * Failures During or After Loading Guest State"). | |
10518 | * This function should be called when the active VMCS is L1's (vmcs01). | |
10519 | */ | |
733568f9 JK |
10520 | static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, |
10521 | struct vmcs12 *vmcs12) | |
4704d0be | 10522 | { |
21feb4eb ACL |
10523 | struct kvm_segment seg; |
10524 | ||
4704d0be NHE |
10525 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) |
10526 | vcpu->arch.efer = vmcs12->host_ia32_efer; | |
d1fa0352 | 10527 | else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) |
4704d0be NHE |
10528 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
10529 | else | |
10530 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
10531 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
10532 | ||
10533 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp); | |
10534 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip); | |
1adfa76a | 10535 | vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); |
4704d0be NHE |
10536 | /* |
10537 | * Note that calling vmx_set_cr0 is important, even if cr0 hasn't | |
10538 | * actually changed, because it depends on the current state of | |
10539 | * fpu_active (which may have changed). | |
10540 | * Note that vmx_set_cr0 refers to efer set above. | |
10541 | */ | |
9e3e4dbf | 10542 | vmx_set_cr0(vcpu, vmcs12->host_cr0); |
4704d0be NHE |
10543 | /* |
10544 | * If we did fpu_activate()/fpu_deactivate() during L2's run, we need | |
10545 | * to apply the same changes to L1's vmcs. We just set cr0 correctly, | |
10546 | * but we also need to update cr0_guest_host_mask and exception_bitmap. | |
10547 | */ | |
10548 | update_exception_bitmap(vcpu); | |
10549 | vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0); | |
10550 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
10551 | ||
10552 | /* | |
10553 | * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01 | |
10554 | * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask(); | |
10555 | */ | |
10556 | vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); | |
10557 | kvm_set_cr4(vcpu, vmcs12->host_cr4); | |
10558 | ||
29bf08f1 | 10559 | nested_ept_uninit_mmu_context(vcpu); |
155a97a3 | 10560 | |
4704d0be NHE |
10561 | kvm_set_cr3(vcpu, vmcs12->host_cr3); |
10562 | kvm_mmu_reset_context(vcpu); | |
10563 | ||
feaf0c7d GN |
10564 | if (!enable_ept) |
10565 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
10566 | ||
4704d0be NHE |
10567 | if (enable_vpid) { |
10568 | /* | |
10569 | * Trivially support vpid by letting L2s share their parent | |
10570 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
10571 | * each L2 its own vpid and exposing the vpid feature to L1. | |
10572 | */ | |
10573 | vmx_flush_tlb(vcpu); | |
10574 | } | |
10575 | ||
10576 | ||
10577 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); | |
10578 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); | |
10579 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); | |
10580 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); | |
10581 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); | |
4704d0be | 10582 | |
36be0b9d PB |
10583 | /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ |
10584 | if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) | |
10585 | vmcs_write64(GUEST_BNDCFGS, 0); | |
10586 | ||
44811c02 | 10587 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { |
4704d0be | 10588 | vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); |
44811c02 JK |
10589 | vcpu->arch.pat = vmcs12->host_ia32_pat; |
10590 | } | |
4704d0be NHE |
10591 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
10592 | vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, | |
10593 | vmcs12->host_ia32_perf_global_ctrl); | |
503cd0c5 | 10594 | |
21feb4eb ACL |
10595 | /* Set L1 segment info according to Intel SDM |
10596 | 27.5.2 Loading Host Segment and Descriptor-Table Registers */ | |
10597 | seg = (struct kvm_segment) { | |
10598 | .base = 0, | |
10599 | .limit = 0xFFFFFFFF, | |
10600 | .selector = vmcs12->host_cs_selector, | |
10601 | .type = 11, | |
10602 | .present = 1, | |
10603 | .s = 1, | |
10604 | .g = 1 | |
10605 | }; | |
10606 | if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) | |
10607 | seg.l = 1; | |
10608 | else | |
10609 | seg.db = 1; | |
10610 | vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); | |
10611 | seg = (struct kvm_segment) { | |
10612 | .base = 0, | |
10613 | .limit = 0xFFFFFFFF, | |
10614 | .type = 3, | |
10615 | .present = 1, | |
10616 | .s = 1, | |
10617 | .db = 1, | |
10618 | .g = 1 | |
10619 | }; | |
10620 | seg.selector = vmcs12->host_ds_selector; | |
10621 | vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); | |
10622 | seg.selector = vmcs12->host_es_selector; | |
10623 | vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); | |
10624 | seg.selector = vmcs12->host_ss_selector; | |
10625 | vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); | |
10626 | seg.selector = vmcs12->host_fs_selector; | |
10627 | seg.base = vmcs12->host_fs_base; | |
10628 | vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); | |
10629 | seg.selector = vmcs12->host_gs_selector; | |
10630 | seg.base = vmcs12->host_gs_base; | |
10631 | vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); | |
10632 | seg = (struct kvm_segment) { | |
205befd9 | 10633 | .base = vmcs12->host_tr_base, |
21feb4eb ACL |
10634 | .limit = 0x67, |
10635 | .selector = vmcs12->host_tr_selector, | |
10636 | .type = 11, | |
10637 | .present = 1 | |
10638 | }; | |
10639 | vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); | |
10640 | ||
503cd0c5 JK |
10641 | kvm_set_dr(vcpu, 7, 0x400); |
10642 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
ff651cb6 | 10643 | |
3af18d9c WV |
10644 | if (cpu_has_vmx_msr_bitmap()) |
10645 | vmx_set_msr_bitmap(vcpu); | |
10646 | ||
ff651cb6 WV |
10647 | if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr, |
10648 | vmcs12->vm_exit_msr_load_count)) | |
10649 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); | |
4704d0be NHE |
10650 | } |
10651 | ||
10652 | /* | |
10653 | * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 | |
10654 | * and modify vmcs12 to make it see what it would expect to see there if | |
10655 | * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) | |
10656 | */ | |
533558bc JK |
10657 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
10658 | u32 exit_intr_info, | |
10659 | unsigned long exit_qualification) | |
4704d0be NHE |
10660 | { |
10661 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4704d0be | 10662 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
cf3215d9 | 10663 | u32 vm_inst_error = 0; |
4704d0be | 10664 | |
5f3d5799 JK |
10665 | /* trying to cancel vmlaunch/vmresume is a bug */ |
10666 | WARN_ON_ONCE(vmx->nested.nested_run_pending); | |
10667 | ||
4704d0be | 10668 | leave_guest_mode(vcpu); |
533558bc JK |
10669 | prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info, |
10670 | exit_qualification); | |
4704d0be | 10671 | |
ff651cb6 WV |
10672 | if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr, |
10673 | vmcs12->vm_exit_msr_store_count)) | |
10674 | nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL); | |
10675 | ||
cf3215d9 JM |
10676 | if (unlikely(vmx->fail)) |
10677 | vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR); | |
10678 | ||
f3380ca5 WL |
10679 | vmx_load_vmcs01(vcpu); |
10680 | ||
77b0f5d6 BD |
10681 | if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) |
10682 | && nested_exit_intr_ack_set(vcpu)) { | |
10683 | int irq = kvm_cpu_get_interrupt(vcpu); | |
10684 | WARN_ON(irq < 0); | |
10685 | vmcs12->vm_exit_intr_info = irq | | |
10686 | INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; | |
10687 | } | |
10688 | ||
542060ea JK |
10689 | trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, |
10690 | vmcs12->exit_qualification, | |
10691 | vmcs12->idt_vectoring_info_field, | |
10692 | vmcs12->vm_exit_intr_info, | |
10693 | vmcs12->vm_exit_intr_error_code, | |
10694 | KVM_ISA_VMX); | |
4704d0be | 10695 | |
8391ce44 PB |
10696 | vm_entry_controls_reset_shadow(vmx); |
10697 | vm_exit_controls_reset_shadow(vmx); | |
36c3cc42 JK |
10698 | vmx_segment_cache_clear(vmx); |
10699 | ||
4704d0be NHE |
10700 | /* if no vmcs02 cache requested, remove the one we used */ |
10701 | if (VMCS02_POOL_SIZE == 0) | |
10702 | nested_free_vmcs02(vmx, vmx->nested.current_vmptr); | |
10703 | ||
10704 | load_vmcs12_host_state(vcpu, vmcs12); | |
10705 | ||
9314006d | 10706 | /* Update any VMCS fields that might have changed while L2 ran */ |
83bafef1 JM |
10707 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr); |
10708 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
ea26e4ec | 10709 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
9314006d PB |
10710 | if (vmx->hv_deadline_tsc == -1) |
10711 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
10712 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
10713 | else | |
10714 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
10715 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c95ba92a PF |
10716 | if (kvm_has_tsc_control) |
10717 | decache_tsc_multiplier(vmx); | |
4704d0be | 10718 | |
dccbfcf5 RK |
10719 | if (vmx->nested.change_vmcs01_virtual_x2apic_mode) { |
10720 | vmx->nested.change_vmcs01_virtual_x2apic_mode = false; | |
10721 | vmx_set_virtual_x2apic_mode(vcpu, | |
10722 | vcpu->arch.apic_base & X2APIC_ENABLE); | |
10723 | } | |
4704d0be NHE |
10724 | |
10725 | /* This is needed for same reason as it was needed in prepare_vmcs02 */ | |
10726 | vmx->host_rsp = 0; | |
10727 | ||
10728 | /* Unpin physical memory we referred to in vmcs02 */ | |
10729 | if (vmx->nested.apic_access_page) { | |
10730 | nested_release_page(vmx->nested.apic_access_page); | |
48d89b92 | 10731 | vmx->nested.apic_access_page = NULL; |
4704d0be | 10732 | } |
a7c0b07d WL |
10733 | if (vmx->nested.virtual_apic_page) { |
10734 | nested_release_page(vmx->nested.virtual_apic_page); | |
48d89b92 | 10735 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 10736 | } |
705699a1 WV |
10737 | if (vmx->nested.pi_desc_page) { |
10738 | kunmap(vmx->nested.pi_desc_page); | |
10739 | nested_release_page(vmx->nested.pi_desc_page); | |
10740 | vmx->nested.pi_desc_page = NULL; | |
10741 | vmx->nested.pi_desc = NULL; | |
10742 | } | |
4704d0be | 10743 | |
38b99173 TC |
10744 | /* |
10745 | * We are now running in L2, mmu_notifier will force to reload the | |
10746 | * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1. | |
10747 | */ | |
c83b6d15 | 10748 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
38b99173 | 10749 | |
4704d0be NHE |
10750 | /* |
10751 | * Exiting from L2 to L1, we're now back to L1 which thinks it just | |
10752 | * finished a VMLAUNCH or VMRESUME instruction, so we need to set the | |
10753 | * success or failure flag accordingly. | |
10754 | */ | |
10755 | if (unlikely(vmx->fail)) { | |
10756 | vmx->fail = 0; | |
cf3215d9 | 10757 | nested_vmx_failValid(vcpu, vm_inst_error); |
4704d0be NHE |
10758 | } else |
10759 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
10760 | if (enable_shadow_vmcs) |
10761 | vmx->nested.sync_shadow_vmcs = true; | |
b6b8a145 JK |
10762 | |
10763 | /* in case we halted in L2 */ | |
10764 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4704d0be NHE |
10765 | } |
10766 | ||
42124925 JK |
10767 | /* |
10768 | * Forcibly leave nested mode in order to be able to reset the VCPU later on. | |
10769 | */ | |
10770 | static void vmx_leave_nested(struct kvm_vcpu *vcpu) | |
10771 | { | |
10772 | if (is_guest_mode(vcpu)) | |
533558bc | 10773 | nested_vmx_vmexit(vcpu, -1, 0, 0); |
42124925 JK |
10774 | free_nested(to_vmx(vcpu)); |
10775 | } | |
10776 | ||
7c177938 NHE |
10777 | /* |
10778 | * L1's failure to enter L2 is a subset of a normal exit, as explained in | |
10779 | * 23.7 "VM-entry failures during or after loading guest state" (this also | |
10780 | * lists the acceptable exit-reason and exit-qualification parameters). | |
10781 | * It should only be called before L2 actually succeeded to run, and when | |
10782 | * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss). | |
10783 | */ | |
10784 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, | |
10785 | struct vmcs12 *vmcs12, | |
10786 | u32 reason, unsigned long qualification) | |
10787 | { | |
10788 | load_vmcs12_host_state(vcpu, vmcs12); | |
10789 | vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY; | |
10790 | vmcs12->exit_qualification = qualification; | |
10791 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
10792 | if (enable_shadow_vmcs) |
10793 | to_vmx(vcpu)->nested.sync_shadow_vmcs = true; | |
7c177938 NHE |
10794 | } |
10795 | ||
8a76d7f2 JR |
10796 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
10797 | struct x86_instruction_info *info, | |
10798 | enum x86_intercept_stage stage) | |
10799 | { | |
10800 | return X86EMUL_CONTINUE; | |
10801 | } | |
10802 | ||
64672c95 YJ |
10803 | #ifdef CONFIG_X86_64 |
10804 | /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ | |
10805 | static inline int u64_shl_div_u64(u64 a, unsigned int shift, | |
10806 | u64 divisor, u64 *result) | |
10807 | { | |
10808 | u64 low = a << shift, high = a >> (64 - shift); | |
10809 | ||
10810 | /* To avoid the overflow on divq */ | |
10811 | if (high >= divisor) | |
10812 | return 1; | |
10813 | ||
10814 | /* Low hold the result, high hold rem which is discarded */ | |
10815 | asm("divq %2\n\t" : "=a" (low), "=d" (high) : | |
10816 | "rm" (divisor), "0" (low), "1" (high)); | |
10817 | *result = low; | |
10818 | ||
10819 | return 0; | |
10820 | } | |
10821 | ||
10822 | static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc) | |
10823 | { | |
10824 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9175d2e9 PB |
10825 | u64 tscl = rdtsc(); |
10826 | u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); | |
10827 | u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; | |
64672c95 YJ |
10828 | |
10829 | /* Convert to host delta tsc if tsc scaling is enabled */ | |
10830 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && | |
10831 | u64_shl_div_u64(delta_tsc, | |
10832 | kvm_tsc_scaling_ratio_frac_bits, | |
10833 | vcpu->arch.tsc_scaling_ratio, | |
10834 | &delta_tsc)) | |
10835 | return -ERANGE; | |
10836 | ||
10837 | /* | |
10838 | * If the delta tsc can't fit in the 32 bit after the multi shift, | |
10839 | * we can't use the preemption timer. | |
10840 | * It's possible that it fits on later vmentries, but checking | |
10841 | * on every vmentry is costly so we just use an hrtimer. | |
10842 | */ | |
10843 | if (delta_tsc >> (cpu_preemption_timer_multi + 32)) | |
10844 | return -ERANGE; | |
10845 | ||
10846 | vmx->hv_deadline_tsc = tscl + delta_tsc; | |
10847 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
10848 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
10849 | return 0; | |
10850 | } | |
10851 | ||
10852 | static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) | |
10853 | { | |
10854 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10855 | vmx->hv_deadline_tsc = -1; | |
10856 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
10857 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
10858 | } | |
10859 | #endif | |
10860 | ||
48d89b92 | 10861 | static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) |
ae97a3b8 | 10862 | { |
b4a2d31d RK |
10863 | if (ple_gap) |
10864 | shrink_ple_window(vcpu); | |
ae97a3b8 RK |
10865 | } |
10866 | ||
843e4330 KH |
10867 | static void vmx_slot_enable_log_dirty(struct kvm *kvm, |
10868 | struct kvm_memory_slot *slot) | |
10869 | { | |
10870 | kvm_mmu_slot_leaf_clear_dirty(kvm, slot); | |
10871 | kvm_mmu_slot_largepage_remove_write_access(kvm, slot); | |
10872 | } | |
10873 | ||
10874 | static void vmx_slot_disable_log_dirty(struct kvm *kvm, | |
10875 | struct kvm_memory_slot *slot) | |
10876 | { | |
10877 | kvm_mmu_slot_set_dirty(kvm, slot); | |
10878 | } | |
10879 | ||
10880 | static void vmx_flush_log_dirty(struct kvm *kvm) | |
10881 | { | |
10882 | kvm_flush_pml_buffers(kvm); | |
10883 | } | |
10884 | ||
10885 | static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, | |
10886 | struct kvm_memory_slot *memslot, | |
10887 | gfn_t offset, unsigned long mask) | |
10888 | { | |
10889 | kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); | |
10890 | } | |
10891 | ||
bf9f6ac8 FW |
10892 | /* |
10893 | * This routine does the following things for vCPU which is going | |
10894 | * to be blocked if VT-d PI is enabled. | |
10895 | * - Store the vCPU to the wakeup list, so when interrupts happen | |
10896 | * we can find the right vCPU to wake up. | |
10897 | * - Change the Posted-interrupt descriptor as below: | |
10898 | * 'NDST' <-- vcpu->pre_pcpu | |
10899 | * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR | |
10900 | * - If 'ON' is set during this process, which means at least one | |
10901 | * interrupt is posted for this vCPU, we cannot block it, in | |
10902 | * this case, return 1, otherwise, return 0. | |
10903 | * | |
10904 | */ | |
bc22512b | 10905 | static int pi_pre_block(struct kvm_vcpu *vcpu) |
bf9f6ac8 FW |
10906 | { |
10907 | unsigned long flags; | |
10908 | unsigned int dest; | |
10909 | struct pi_desc old, new; | |
10910 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
10911 | ||
10912 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
10913 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
10914 | !kvm_vcpu_apicv_active(vcpu)) | |
bf9f6ac8 FW |
10915 | return 0; |
10916 | ||
10917 | vcpu->pre_pcpu = vcpu->cpu; | |
10918 | spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock, | |
10919 | vcpu->pre_pcpu), flags); | |
10920 | list_add_tail(&vcpu->blocked_vcpu_list, | |
10921 | &per_cpu(blocked_vcpu_on_cpu, | |
10922 | vcpu->pre_pcpu)); | |
10923 | spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock, | |
10924 | vcpu->pre_pcpu), flags); | |
10925 | ||
10926 | do { | |
10927 | old.control = new.control = pi_desc->control; | |
10928 | ||
10929 | /* | |
10930 | * We should not block the vCPU if | |
10931 | * an interrupt is posted for it. | |
10932 | */ | |
10933 | if (pi_test_on(pi_desc) == 1) { | |
10934 | spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock, | |
10935 | vcpu->pre_pcpu), flags); | |
10936 | list_del(&vcpu->blocked_vcpu_list); | |
10937 | spin_unlock_irqrestore( | |
10938 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
10939 | vcpu->pre_pcpu), flags); | |
10940 | vcpu->pre_pcpu = -1; | |
10941 | ||
10942 | return 1; | |
10943 | } | |
10944 | ||
10945 | WARN((pi_desc->sn == 1), | |
10946 | "Warning: SN field of posted-interrupts " | |
10947 | "is set before blocking\n"); | |
10948 | ||
10949 | /* | |
10950 | * Since vCPU can be preempted during this process, | |
10951 | * vcpu->cpu could be different with pre_pcpu, we | |
10952 | * need to set pre_pcpu as the destination of wakeup | |
10953 | * notification event, then we can find the right vCPU | |
10954 | * to wakeup in wakeup handler if interrupts happen | |
10955 | * when the vCPU is in blocked state. | |
10956 | */ | |
10957 | dest = cpu_physical_id(vcpu->pre_pcpu); | |
10958 | ||
10959 | if (x2apic_enabled()) | |
10960 | new.ndst = dest; | |
10961 | else | |
10962 | new.ndst = (dest << 8) & 0xFF00; | |
10963 | ||
10964 | /* set 'NV' to 'wakeup vector' */ | |
10965 | new.nv = POSTED_INTR_WAKEUP_VECTOR; | |
10966 | } while (cmpxchg(&pi_desc->control, old.control, | |
10967 | new.control) != old.control); | |
10968 | ||
10969 | return 0; | |
10970 | } | |
10971 | ||
bc22512b YJ |
10972 | static int vmx_pre_block(struct kvm_vcpu *vcpu) |
10973 | { | |
10974 | if (pi_pre_block(vcpu)) | |
10975 | return 1; | |
10976 | ||
64672c95 YJ |
10977 | if (kvm_lapic_hv_timer_in_use(vcpu)) |
10978 | kvm_lapic_switch_to_sw_timer(vcpu); | |
10979 | ||
bc22512b YJ |
10980 | return 0; |
10981 | } | |
10982 | ||
10983 | static void pi_post_block(struct kvm_vcpu *vcpu) | |
bf9f6ac8 FW |
10984 | { |
10985 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
10986 | struct pi_desc old, new; | |
10987 | unsigned int dest; | |
10988 | unsigned long flags; | |
10989 | ||
10990 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
10991 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
10992 | !kvm_vcpu_apicv_active(vcpu)) | |
bf9f6ac8 FW |
10993 | return; |
10994 | ||
10995 | do { | |
10996 | old.control = new.control = pi_desc->control; | |
10997 | ||
10998 | dest = cpu_physical_id(vcpu->cpu); | |
10999 | ||
11000 | if (x2apic_enabled()) | |
11001 | new.ndst = dest; | |
11002 | else | |
11003 | new.ndst = (dest << 8) & 0xFF00; | |
11004 | ||
11005 | /* Allow posting non-urgent interrupts */ | |
11006 | new.sn = 0; | |
11007 | ||
11008 | /* set 'NV' to 'notification vector' */ | |
11009 | new.nv = POSTED_INTR_VECTOR; | |
11010 | } while (cmpxchg(&pi_desc->control, old.control, | |
11011 | new.control) != old.control); | |
11012 | ||
11013 | if(vcpu->pre_pcpu != -1) { | |
11014 | spin_lock_irqsave( | |
11015 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
11016 | vcpu->pre_pcpu), flags); | |
11017 | list_del(&vcpu->blocked_vcpu_list); | |
11018 | spin_unlock_irqrestore( | |
11019 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
11020 | vcpu->pre_pcpu), flags); | |
11021 | vcpu->pre_pcpu = -1; | |
11022 | } | |
11023 | } | |
11024 | ||
bc22512b YJ |
11025 | static void vmx_post_block(struct kvm_vcpu *vcpu) |
11026 | { | |
64672c95 YJ |
11027 | if (kvm_x86_ops->set_hv_timer) |
11028 | kvm_lapic_switch_to_hv_timer(vcpu); | |
11029 | ||
bc22512b YJ |
11030 | pi_post_block(vcpu); |
11031 | } | |
11032 | ||
efc64404 FW |
11033 | /* |
11034 | * vmx_update_pi_irte - set IRTE for Posted-Interrupts | |
11035 | * | |
11036 | * @kvm: kvm | |
11037 | * @host_irq: host irq of the interrupt | |
11038 | * @guest_irq: gsi of the interrupt | |
11039 | * @set: set or unset PI | |
11040 | * returns 0 on success, < 0 on failure | |
11041 | */ | |
11042 | static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
11043 | uint32_t guest_irq, bool set) | |
11044 | { | |
11045 | struct kvm_kernel_irq_routing_entry *e; | |
11046 | struct kvm_irq_routing_table *irq_rt; | |
11047 | struct kvm_lapic_irq irq; | |
11048 | struct kvm_vcpu *vcpu; | |
11049 | struct vcpu_data vcpu_info; | |
11050 | int idx, ret = -EINVAL; | |
11051 | ||
11052 | if (!kvm_arch_has_assigned_device(kvm) || | |
a0052191 YZ |
11053 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
11054 | !kvm_vcpu_apicv_active(kvm->vcpus[0])) | |
efc64404 FW |
11055 | return 0; |
11056 | ||
11057 | idx = srcu_read_lock(&kvm->irq_srcu); | |
11058 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
11059 | BUG_ON(guest_irq >= irq_rt->nr_rt_entries); | |
11060 | ||
11061 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
11062 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
11063 | continue; | |
11064 | /* | |
11065 | * VT-d PI cannot support posting multicast/broadcast | |
11066 | * interrupts to a vCPU, we still use interrupt remapping | |
11067 | * for these kind of interrupts. | |
11068 | * | |
11069 | * For lowest-priority interrupts, we only support | |
11070 | * those with single CPU as the destination, e.g. user | |
11071 | * configures the interrupts via /proc/irq or uses | |
11072 | * irqbalance to make the interrupts single-CPU. | |
11073 | * | |
11074 | * We will support full lowest-priority interrupt later. | |
11075 | */ | |
11076 | ||
37131313 | 11077 | kvm_set_msi_irq(kvm, e, &irq); |
23a1c257 FW |
11078 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { |
11079 | /* | |
11080 | * Make sure the IRTE is in remapped mode if | |
11081 | * we don't handle it in posted mode. | |
11082 | */ | |
11083 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
11084 | if (ret < 0) { | |
11085 | printk(KERN_INFO | |
11086 | "failed to back to remapped mode, irq: %u\n", | |
11087 | host_irq); | |
11088 | goto out; | |
11089 | } | |
11090 | ||
efc64404 | 11091 | continue; |
23a1c257 | 11092 | } |
efc64404 FW |
11093 | |
11094 | vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); | |
11095 | vcpu_info.vector = irq.vector; | |
11096 | ||
b6ce9780 | 11097 | trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi, |
efc64404 FW |
11098 | vcpu_info.vector, vcpu_info.pi_desc_addr, set); |
11099 | ||
11100 | if (set) | |
11101 | ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); | |
11102 | else { | |
11103 | /* suppress notification event before unposting */ | |
11104 | pi_set_sn(vcpu_to_pi_desc(vcpu)); | |
11105 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
11106 | pi_clear_sn(vcpu_to_pi_desc(vcpu)); | |
11107 | } | |
11108 | ||
11109 | if (ret < 0) { | |
11110 | printk(KERN_INFO "%s: failed to update PI IRTE\n", | |
11111 | __func__); | |
11112 | goto out; | |
11113 | } | |
11114 | } | |
11115 | ||
11116 | ret = 0; | |
11117 | out: | |
11118 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
11119 | return ret; | |
11120 | } | |
11121 | ||
c45dcc71 AR |
11122 | static void vmx_setup_mce(struct kvm_vcpu *vcpu) |
11123 | { | |
11124 | if (vcpu->arch.mcg_cap & MCG_LMCE_P) | |
11125 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
11126 | FEATURE_CONTROL_LMCE; | |
11127 | else | |
11128 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
11129 | ~FEATURE_CONTROL_LMCE; | |
11130 | } | |
11131 | ||
404f6aac | 11132 | static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { |
6aa8b732 AK |
11133 | .cpu_has_kvm_support = cpu_has_kvm_support, |
11134 | .disabled_by_bios = vmx_disabled_by_bios, | |
11135 | .hardware_setup = hardware_setup, | |
11136 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 11137 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
11138 | .hardware_enable = hardware_enable, |
11139 | .hardware_disable = hardware_disable, | |
04547156 | 11140 | .cpu_has_accelerated_tpr = report_flexpriority, |
6d396b55 | 11141 | .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase, |
6aa8b732 AK |
11142 | |
11143 | .vcpu_create = vmx_create_vcpu, | |
11144 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 11145 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 11146 | |
04d2cc77 | 11147 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
11148 | .vcpu_load = vmx_vcpu_load, |
11149 | .vcpu_put = vmx_vcpu_put, | |
11150 | ||
a96036b8 | 11151 | .update_bp_intercept = update_exception_bitmap, |
6aa8b732 AK |
11152 | .get_msr = vmx_get_msr, |
11153 | .set_msr = vmx_set_msr, | |
11154 | .get_segment_base = vmx_get_segment_base, | |
11155 | .get_segment = vmx_get_segment, | |
11156 | .set_segment = vmx_set_segment, | |
2e4d2653 | 11157 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 11158 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 11159 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 11160 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 11161 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 11162 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
11163 | .set_cr3 = vmx_set_cr3, |
11164 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 11165 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
11166 | .get_idt = vmx_get_idt, |
11167 | .set_idt = vmx_set_idt, | |
11168 | .get_gdt = vmx_get_gdt, | |
11169 | .set_gdt = vmx_set_gdt, | |
73aaf249 JK |
11170 | .get_dr6 = vmx_get_dr6, |
11171 | .set_dr6 = vmx_set_dr6, | |
020df079 | 11172 | .set_dr7 = vmx_set_dr7, |
81908bf4 | 11173 | .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, |
5fdbf976 | 11174 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
11175 | .get_rflags = vmx_get_rflags, |
11176 | .set_rflags = vmx_set_rflags, | |
be94f6b7 HH |
11177 | |
11178 | .get_pkru = vmx_get_pkru, | |
11179 | ||
0fdd74f7 | 11180 | .fpu_activate = vmx_fpu_activate, |
02daab21 | 11181 | .fpu_deactivate = vmx_fpu_deactivate, |
6aa8b732 AK |
11182 | |
11183 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 11184 | |
6aa8b732 | 11185 | .run = vmx_vcpu_run, |
6062d012 | 11186 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 11187 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
11188 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
11189 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 11190 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 11191 | .set_irq = vmx_inject_irq, |
95ba8273 | 11192 | .set_nmi = vmx_inject_nmi, |
298101da | 11193 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 11194 | .cancel_injection = vmx_cancel_injection, |
78646121 | 11195 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 11196 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
11197 | .get_nmi_mask = vmx_get_nmi_mask, |
11198 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
11199 | .enable_nmi_window = enable_nmi_window, |
11200 | .enable_irq_window = enable_irq_window, | |
11201 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 11202 | .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode, |
38b99173 | 11203 | .set_apic_access_page_addr = vmx_set_apic_access_page_addr, |
d62caabb AS |
11204 | .get_enable_apicv = vmx_get_enable_apicv, |
11205 | .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, | |
c7c9c56c YZ |
11206 | .load_eoi_exitmap = vmx_load_eoi_exitmap, |
11207 | .hwapic_irr_update = vmx_hwapic_irr_update, | |
11208 | .hwapic_isr_update = vmx_hwapic_isr_update, | |
a20ed54d YZ |
11209 | .sync_pir_to_irr = vmx_sync_pir_to_irr, |
11210 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, | |
95ba8273 | 11211 | |
cbc94022 | 11212 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 11213 | .get_tdp_level = get_ept_level, |
4b12f0de | 11214 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 11215 | |
586f9607 | 11216 | .get_exit_info = vmx_get_exit_info, |
586f9607 | 11217 | |
17cc3935 | 11218 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
11219 | |
11220 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
11221 | |
11222 | .rdtscp_supported = vmx_rdtscp_supported, | |
ad756a16 | 11223 | .invpcid_supported = vmx_invpcid_supported, |
d4330ef2 JR |
11224 | |
11225 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
11226 | |
11227 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a ZA |
11228 | |
11229 | .write_tsc_offset = vmx_write_tsc_offset, | |
1c97f0a0 JR |
11230 | |
11231 | .set_tdp_cr3 = vmx_set_cr3, | |
8a76d7f2 JR |
11232 | |
11233 | .check_intercept = vmx_check_intercept, | |
a547c6db | 11234 | .handle_external_intr = vmx_handle_external_intr, |
da8999d3 | 11235 | .mpx_supported = vmx_mpx_supported, |
55412b2e | 11236 | .xsaves_supported = vmx_xsaves_supported, |
b6b8a145 JK |
11237 | |
11238 | .check_nested_events = vmx_check_nested_events, | |
ae97a3b8 RK |
11239 | |
11240 | .sched_in = vmx_sched_in, | |
843e4330 KH |
11241 | |
11242 | .slot_enable_log_dirty = vmx_slot_enable_log_dirty, | |
11243 | .slot_disable_log_dirty = vmx_slot_disable_log_dirty, | |
11244 | .flush_log_dirty = vmx_flush_log_dirty, | |
11245 | .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, | |
25462f7f | 11246 | |
bf9f6ac8 FW |
11247 | .pre_block = vmx_pre_block, |
11248 | .post_block = vmx_post_block, | |
11249 | ||
25462f7f | 11250 | .pmu_ops = &intel_pmu_ops, |
efc64404 FW |
11251 | |
11252 | .update_pi_irte = vmx_update_pi_irte, | |
64672c95 YJ |
11253 | |
11254 | #ifdef CONFIG_X86_64 | |
11255 | .set_hv_timer = vmx_set_hv_timer, | |
11256 | .cancel_hv_timer = vmx_cancel_hv_timer, | |
11257 | #endif | |
c45dcc71 AR |
11258 | |
11259 | .setup_mce = vmx_setup_mce, | |
6aa8b732 AK |
11260 | }; |
11261 | ||
11262 | static int __init vmx_init(void) | |
11263 | { | |
34a1cd60 TC |
11264 | int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
11265 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
fdef3ad1 | 11266 | if (r) |
34a1cd60 | 11267 | return r; |
25c5f225 | 11268 | |
2965faa5 | 11269 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
11270 | rcu_assign_pointer(crash_vmclear_loaded_vmcss, |
11271 | crash_vmclear_local_loaded_vmcss); | |
11272 | #endif | |
11273 | ||
fdef3ad1 | 11274 | return 0; |
6aa8b732 AK |
11275 | } |
11276 | ||
11277 | static void __exit vmx_exit(void) | |
11278 | { | |
2965faa5 | 11279 | #ifdef CONFIG_KEXEC_CORE |
3b63a43f | 11280 | RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); |
8f536b76 ZY |
11281 | synchronize_rcu(); |
11282 | #endif | |
11283 | ||
cb498ea2 | 11284 | kvm_exit(); |
6aa8b732 AK |
11285 | } |
11286 | ||
11287 | module_init(vmx_init) | |
11288 | module_exit(vmx_exit) |