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Update version for v2.8.0-rc1 release
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
b834b508 38#if defined(CONFIG_KVM)
ef8621b1 39#include <linux/kvm_para.h>
b834b508 40#endif
65dee380 41
9c17d615 42#include "sysemu/sysemu.h"
53a89e26 43#include "hw/qdev-properties.h"
5232d00a 44#include "hw/i386/topology.h"
bdeec802 45#ifndef CONFIG_USER_ONLY
2001d0cd 46#include "exec/address-spaces.h"
741da0d3 47#include "hw/hw.h"
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
14c985cf 60#define CPUID_2_L3_16MB_16WAY_64B 0x4d
5e891bf8
EH		 61
62
63/* CPUID Leaf 4 constants: */
64
65/* EAX: */
66#define CPUID_4_TYPE_DCACHE 1
67#define CPUID_4_TYPE_ICACHE 2
68#define CPUID_4_TYPE_UNIFIED 3
69
70#define CPUID_4_LEVEL(l) ((l) << 5)
71
72#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73#define CPUID_4_FULLY_ASSOC (1 << 9)
74
75/* EDX: */
76#define CPUID_4_NO_INVD_SHARING (1 << 0)
77#define CPUID_4_INCLUSIVE (1 << 1)
78#define CPUID_4_COMPLEX_IDX (1 << 2)
79
80#define ASSOC_FULL 0xFF
81
82/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
84 a == 2 ? 0x2 : \
85 a == 4 ? 0x4 : \
86 a == 8 ? 0x6 : \
87 a == 16 ? 0x8 : \
88 a == 32 ? 0xA : \
89 a == 48 ? 0xB : \
90 a == 64 ? 0xC : \
91 a == 96 ? 0xD : \
92 a == 128 ? 0xE : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
95
96
97/* Definitions of the hardcoded cache entries we expose: */
98
99/* L1 data cache: */
100#define L1D_LINE_SIZE 64
101#define L1D_ASSOCIATIVITY 8
102#define L1D_SETS 64
103#define L1D_PARTITIONS 1
104/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107#define L1D_LINES_PER_TAG 1
108#define L1D_SIZE_KB_AMD 64
109#define L1D_ASSOCIATIVITY_AMD 2
110
111/* L1 instruction cache: */
112#define L1I_LINE_SIZE 64
113#define L1I_ASSOCIATIVITY 8
114#define L1I_SETS 64
115#define L1I_PARTITIONS 1
116/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119#define L1I_LINES_PER_TAG 1
120#define L1I_SIZE_KB_AMD 64
121#define L1I_ASSOCIATIVITY_AMD 2
122
123/* Level 2 unified cache: */
124#define L2_LINE_SIZE 64
125#define L2_ASSOCIATIVITY 16
126#define L2_SETS 4096
127#define L2_PARTITIONS 1
128/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132#define L2_LINES_PER_TAG 1
133#define L2_SIZE_KB_AMD 512
134
14c985cf 135/* Level 3 unified cache: */
5e891bf8
EH		 136#define L3_SIZE_KB 0 /* disabled */
137#define L3_ASSOCIATIVITY 0 /* disabled */
138#define L3_LINES_PER_TAG 0 /* disabled */
139#define L3_LINE_SIZE 0 /* disabled */
14c985cf
LM		 140#define L3_N_LINE_SIZE 64
141#define L3_N_ASSOCIATIVITY 16
142#define L3_N_SETS 16384
143#define L3_N_PARTITIONS 1
144#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
145#define L3_N_LINES_PER_TAG 1
146#define L3_N_SIZE_KB_AMD 16384
5e891bf8
EH		 147
148/* TLB definitions: */
149
150#define L1_DTLB_2M_ASSOC 1
151#define L1_DTLB_2M_ENTRIES 255
152#define L1_DTLB_4K_ASSOC 1
153#define L1_DTLB_4K_ENTRIES 255
154
155#define L1_ITLB_2M_ASSOC 1
156#define L1_ITLB_2M_ENTRIES 255
157#define L1_ITLB_4K_ASSOC 1
158#define L1_ITLB_4K_ENTRIES 255
159
160#define L2_DTLB_2M_ASSOC 0 /* disabled */
161#define L2_DTLB_2M_ENTRIES 0 /* disabled */
162#define L2_DTLB_4K_ASSOC 4
163#define L2_DTLB_4K_ENTRIES 512
164
165#define L2_ITLB_2M_ASSOC 0 /* disabled */
166#define L2_ITLB_2M_ENTRIES 0 /* disabled */
167#define L2_ITLB_4K_ASSOC 4
168#define L2_ITLB_4K_ENTRIES 512
169
170
171
99b88a17
IM		 172static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
173 uint32_t vendor2, uint32_t vendor3)
174{
175 int i;
176 for (i = 0; i < 4; i++) {
177 dst[i] = vendor1 >> (8 * i);
178 dst[i + 4] = vendor2 >> (8 * i);
179 dst[i + 8] = vendor3 >> (8 * i);
180 }
181 dst[CPUID_VENDOR_SZ] = '\0';
182}
183
621626ce
EH		 184#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
185#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
186 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
187#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
188 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
189 CPUID_PSE36 | CPUID_FXSR)
190#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
191#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
192 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
193 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
194 CPUID_PAE | CPUID_SEP | CPUID_APIC)
195
196#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
197 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
198 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
199 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 200 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 201 /* partly implemented:
202 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
203 /* missing:
204 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
205#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
206 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
207 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 208 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 209 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
210 /* missing:
211 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
212 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
213 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 214 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
215 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 216
217#ifdef TARGET_X86_64
218#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
219#else
220#define TCG_EXT2_X86_64_FEATURES 0
221#endif
222
223#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
224 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
225 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
226 TCG_EXT2_X86_64_FEATURES)
227#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
228 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
229#define TCG_EXT4_FEATURES 0
230#define TCG_SVM_FEATURES 0
231#define TCG_KVM_FEATURES 0
232#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 233 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
234 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 235 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
236 CPUID_7_0_EBX_ERMS)
621626ce 237 /* missing:
07929f2a 238 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 239 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 240 CPUID_7_0_EBX_RDSEED */
0f70ed47 241#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
95ea69fb 242#define TCG_7_0_EDX_FEATURES 0
303752a9 243#define TCG_APM_FEATURES 0
28b8e4d0 244#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 245#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
246 /* missing:
247 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 248
5ef57876 249typedef struct FeatureWordInfo {
2d5312da
EH		 250 /* feature flags names are taken from "Intel Processor Identification and
251 * the CPUID Instruction" and AMD's "CPUID Specification".
252 * In cases of disagreement between feature naming conventions,
253 * aliases may be added.
254 */
255 const char *feat_names[32];
04d104b6
EH		 256 uint32_t cpuid_eax; /* Input EAX for CPUID */
257 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
258 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
259 int cpuid_reg; /* output register (R_* constant) */
37ce3522 260 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 261 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 262 uint32_t migratable_flags; /* Feature flags known to be migratable */
5ef57876
EH		 263} FeatureWordInfo;
264
265static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 266 [FEAT_1_EDX] = {
2d5312da
EH		 267 .feat_names = {
268 "fpu", "vme", "de", "pse",
269 "tsc", "msr", "pae", "mce",
270 "cx8", "apic", NULL, "sep",
271 "mtrr", "pge", "mca", "cmov",
272 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
273 NULL, "ds" /* Intel dts */, "acpi", "mmx",
274 "fxsr", "sse", "sse2", "ss",
275 "ht" /* Intel htt */, "tm", "ia64", "pbe",
276 },
bffd67b0 277 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 278 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 279 },
280 [FEAT_1_ECX] = {
2d5312da 281 .feat_names = {
16d2fcaa 282 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 283 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 284 "tm2", "ssse3", "cid", NULL,
285 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 286 NULL, "pcid", "dca", "sse4.1",
287 "sse4.2", "x2apic", "movbe", "popcnt",
2d5312da
EH		 288 "tsc-deadline", "aes", "xsave", "osxsave",
289 "avx", "f16c", "rdrand", "hypervisor",
290 },
bffd67b0 291 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 292 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 293 },
2d5312da
EH		 294 /* Feature names that are already defined on feature_name[] but
295 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
296 * names on feat_names below. They are copied automatically
297 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
298 */
bffd67b0 299 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 300 .feat_names = {
301 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
302 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
303 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
304 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
305 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 306 "nx", NULL, "mmxext", NULL /* mmx */,
307 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
308 NULL, "lm", "3dnowext", "3dnow",
2d5312da 309 },
bffd67b0 310 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 311 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 312 },
313 [FEAT_8000_0001_ECX] = {
2d5312da 314 .feat_names = {
fc7dfd20 315 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 316 "cr8legacy", "abm", "sse4a", "misalignsse",
317 "3dnowprefetch", "osvw", "ibs", "xop",
318 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 319 "fma4", "tce", NULL, "nodeid-msr",
320 NULL, "tbm", "topoext", "perfctr-core",
321 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 322 NULL, NULL, NULL, NULL,
323 },
bffd67b0 324 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 325 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 326 },
89e49c8b 327 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 328 .feat_names = {
329 NULL, NULL, "xstore", "xstore-en",
330 NULL, NULL, "xcrypt", "xcrypt-en",
331 "ace2", "ace2-en", "phe", "phe-en",
332 "pmm", "pmm-en", NULL, NULL,
333 NULL, NULL, NULL, NULL,
334 NULL, NULL, NULL, NULL,
335 NULL, NULL, NULL, NULL,
336 NULL, NULL, NULL, NULL,
337 },
89e49c8b 338 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 339 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 340 },
bffd67b0 341 [FEAT_KVM] = {
2d5312da 342 .feat_names = {
fc7dfd20
EH		 343 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
344 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
2d5312da
EH		 345 NULL, NULL, NULL, NULL,
346 NULL, NULL, NULL, NULL,
347 NULL, NULL, NULL, NULL,
348 NULL, NULL, NULL, NULL,
349 "kvmclock-stable-bit", NULL, NULL, NULL,
350 NULL, NULL, NULL, NULL,
351 },
bffd67b0 352 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 353 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 354 },
c35bd19a 355 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 356 .feat_names = {
357 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
358 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
359 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
360 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
361 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
362 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
363 NULL, NULL, NULL, NULL,
364 NULL, NULL, NULL, NULL,
365 NULL, NULL, NULL, NULL,
366 NULL, NULL, NULL, NULL,
367 NULL, NULL, NULL, NULL,
368 },
c35bd19a
EY		 369 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
370 },
371 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 372 .feat_names = {
373 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
374 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
375 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
376 NULL /* hv_create_port */, NULL /* hv_connect_port */,
377 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
378 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
379 NULL, NULL,
380 NULL, NULL, NULL, NULL,
381 NULL, NULL, NULL, NULL,
382 NULL, NULL, NULL, NULL,
383 NULL, NULL, NULL, NULL,
384 },
c35bd19a
EY		 385 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
386 },
387 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 388 .feat_names = {
389 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
390 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
391 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
392 NULL, NULL,
393 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
394 NULL, NULL, NULL, NULL,
395 NULL, NULL, NULL, NULL,
396 NULL, NULL, NULL, NULL,
397 NULL, NULL, NULL, NULL,
398 NULL, NULL, NULL, NULL,
399 },
c35bd19a
EY		 400 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
401 },
bffd67b0 402 [FEAT_SVM] = {
2d5312da 403 .feat_names = {
fc7dfd20
EH		 404 "npt", "lbrv", "svm-lock", "nrip-save",
405 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
406 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 407 "pfthreshold", NULL, NULL, NULL,
408 NULL, NULL, NULL, NULL,
409 NULL, NULL, NULL, NULL,
410 NULL, NULL, NULL, NULL,
411 NULL, NULL, NULL, NULL,
412 },
bffd67b0 413 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 414 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 415 },
416 [FEAT_7_0_EBX] = {
2d5312da 417 .feat_names = {
fc7dfd20 418 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 419 "hle", "avx2", NULL, "smep",
420 "bmi2", "erms", "invpcid", "rtm",
421 NULL, NULL, "mpx", NULL,
422 "avx512f", "avx512dq", "rdseed", "adx",
423 "smap", "avx512ifma", "pcommit", "clflushopt",
424 "clwb", NULL, "avx512pf", "avx512er",
425 "avx512cd", NULL, "avx512bw", "avx512vl",
426 },
04d104b6
EH		 427 .cpuid_eax = 7,
428 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
429 .cpuid_reg = R_EBX,
37ce3522 430 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 431 },
f74eefe0 432 [FEAT_7_0_ECX] = {
2d5312da
EH		 433 .feat_names = {
434 NULL, "avx512vbmi", "umip", "pku",
435 "ospke", NULL, NULL, NULL,
436 NULL, NULL, NULL, NULL,
437 NULL, NULL, NULL, NULL,
438 NULL, NULL, NULL, NULL,
439 NULL, NULL, "rdpid", NULL,
440 NULL, NULL, NULL, NULL,
441 NULL, NULL, NULL, NULL,
442 },
f74eefe0
HH		 443 .cpuid_eax = 7,
444 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
445 .cpuid_reg = R_ECX,
446 .tcg_features = TCG_7_0_ECX_FEATURES,
447 },
95ea69fb
LK		 448 [FEAT_7_0_EDX] = {
449 .feat_names = {
450 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
451 NULL, NULL, NULL, NULL,
452 NULL, NULL, NULL, NULL,
453 NULL, NULL, NULL, NULL,
454 NULL, NULL, NULL, NULL,
455 NULL, NULL, NULL, NULL,
456 NULL, NULL, NULL, NULL,
457 NULL, NULL, NULL, NULL,
458 },
459 .cpuid_eax = 7,
460 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
461 .cpuid_reg = R_EDX,
462 .tcg_features = TCG_7_0_EDX_FEATURES,
463 },
303752a9 464 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 465 .feat_names = {
466 NULL, NULL, NULL, NULL,
467 NULL, NULL, NULL, NULL,
468 "invtsc", NULL, NULL, NULL,
469 NULL, NULL, NULL, NULL,
470 NULL, NULL, NULL, NULL,
471 NULL, NULL, NULL, NULL,
472 NULL, NULL, NULL, NULL,
473 NULL, NULL, NULL, NULL,
474 },
303752a9
MT		 475 .cpuid_eax = 0x80000007,
476 .cpuid_reg = R_EDX,
477 .tcg_features = TCG_APM_FEATURES,
478 .unmigratable_flags = CPUID_APM_INVTSC,
479 },
0bb0b2d2 480 [FEAT_XSAVE] = {
2d5312da
EH		 481 .feat_names = {
482 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
483 NULL, NULL, NULL, NULL,
484 NULL, NULL, NULL, NULL,
485 NULL, NULL, NULL, NULL,
486 NULL, NULL, NULL, NULL,
487 NULL, NULL, NULL, NULL,
488 NULL, NULL, NULL, NULL,
489 NULL, NULL, NULL, NULL,
490 },
0bb0b2d2
PB		 491 .cpuid_eax = 0xd,
492 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
493 .cpuid_reg = R_EAX,
c9cfe8f9 494 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 495 },
28b8e4d0 496 [FEAT_6_EAX] = {
2d5312da
EH		 497 .feat_names = {
498 NULL, NULL, "arat", NULL,
499 NULL, NULL, NULL, NULL,
500 NULL, NULL, NULL, NULL,
501 NULL, NULL, NULL, NULL,
502 NULL, NULL, NULL, NULL,
503 NULL, NULL, NULL, NULL,
504 NULL, NULL, NULL, NULL,
505 NULL, NULL, NULL, NULL,
506 },
28b8e4d0
JK		 507 .cpuid_eax = 6, .cpuid_reg = R_EAX,
508 .tcg_features = TCG_6_EAX_FEATURES,
509 },
96193c22
EH		 510 [FEAT_XSAVE_COMP_LO] = {
511 .cpuid_eax = 0xD,
512 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
513 .cpuid_reg = R_EAX,
514 .tcg_features = ~0U,
6fb2fff7
EH		 515 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
516 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
517 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
518 XSTATE_PKRU_MASK,
96193c22
EH		 519 },
520 [FEAT_XSAVE_COMP_HI] = {
521 .cpuid_eax = 0xD,
522 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
523 .cpuid_reg = R_EDX,
524 .tcg_features = ~0U,
525 },
5ef57876
EH		 526};
527
8e8aba50
EH		 528typedef struct X86RegisterInfo32 {
529 /* Name of register */
530 const char *name;
531 /* QAPI enum value register */
532 X86CPURegister32 qapi_enum;
533} X86RegisterInfo32;
534
535#define REGISTER(reg) \
5d371f41 536 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 537static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 538 REGISTER(EAX),
539 REGISTER(ECX),
540 REGISTER(EDX),
541 REGISTER(EBX),
542 REGISTER(ESP),
543 REGISTER(EBP),
544 REGISTER(ESI),
545 REGISTER(EDI),
546};
547#undef REGISTER
548
3f32bd21
RH		 549typedef struct ExtSaveArea {
550 uint32_t feature, bits;
551 uint32_t offset, size;
552} ExtSaveArea;
553
554static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 555 [XSTATE_FP_BIT] = {
556 /* x87 FP state component is always enabled if XSAVE is supported */
557 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
558 /* x87 state is in the legacy region of the XSAVE area */
559 .offset = 0,
560 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
561 },
562 [XSTATE_SSE_BIT] = {
563 /* SSE state component is always enabled if XSAVE is supported */
564 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
565 /* SSE state is in the legacy region of the XSAVE area */
566 .offset = 0,
567 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
568 },
cfc3b074
PB		 569 [XSTATE_YMM_BIT] =
570 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 571 .offset = offsetof(X86XSaveArea, avx_state),
572 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 573 [XSTATE_BNDREGS_BIT] =
574 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 575 .offset = offsetof(X86XSaveArea, bndreg_state),
576 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 577 [XSTATE_BNDCSR_BIT] =
578 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 579 .offset = offsetof(X86XSaveArea, bndcsr_state),
580 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 581 [XSTATE_OPMASK_BIT] =
582 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 583 .offset = offsetof(X86XSaveArea, opmask_state),
584 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 585 [XSTATE_ZMM_Hi256_BIT] =
586 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 587 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
588 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 589 [XSTATE_Hi16_ZMM_BIT] =
590 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 591 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
592 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 593 [XSTATE_PKRU_BIT] =
594 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 595 .offset = offsetof(X86XSaveArea, pkru_state),
596 .size = sizeof(XSavePKRU) },
2560f19f 597};
8e8aba50 598
1fda6198
EH		 599static uint32_t xsave_area_size(uint64_t mask)
600{
601 int i;
e3c9022b 602 uint64_t ret = 0;
1fda6198 603
e3c9022b 604 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 605 const ExtSaveArea *esa = &x86_ext_save_areas[i];
606 if ((mask >> i) & 1) {
607 ret = MAX(ret, esa->offset + esa->size);
608 }
609 }
610 return ret;
611}
612
96193c22
EH		 613static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
614{
615 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
616 cpu->env.features[FEAT_XSAVE_COMP_LO];
617}
618
8b4beddc
EH		 619const char *get_register_name_32(unsigned int reg)
620{
31ccdde2 621 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 622 return NULL;
623 }
8e8aba50 624 return x86_reg_info_32[reg].name;
8b4beddc
EH		 625}
626
84f1b92f
EH		 627/*
628 * Returns the set of feature flags that are supported and migratable by
629 * QEMU, for a given FeatureWord.
630 */
631static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
632{
633 FeatureWordInfo *wi = &feature_word_info[w];
634 uint32_t r = 0;
635 int i;
636
637 for (i = 0; i < 32; i++) {
638 uint32_t f = 1U << i;
6fb2fff7
EH		 639
640 /* If the feature name is known, it is implicitly considered migratable,
641 * unless it is explicitly set in unmigratable_flags */
642 if ((wi->migratable_flags & f) ||
643 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
644 r |= f;
84f1b92f 645 }
84f1b92f
EH		 646 }
647 return r;
648}
649
bb44e0d1
JK		 650void host_cpuid(uint32_t function, uint32_t count,
651 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 652{
a1fd24af
AL		 653 uint32_t vec[4];
654
655#ifdef __x86_64__
656 asm volatile("cpuid"
657 : "=a"(vec[0]), "=b"(vec[1]),
658 "=c"(vec[2]), "=d"(vec[3])
659 : "0"(function), "c"(count) : "cc");
c1f41226 660#elif defined(__i386__)
a1fd24af
AL		 661 asm volatile("pusha \n\t"
662 "cpuid \n\t"
663 "mov %%eax, 0(%2) \n\t"
664 "mov %%ebx, 4(%2) \n\t"
665 "mov %%ecx, 8(%2) \n\t"
666 "mov %%edx, 12(%2) \n\t"
667 "popa"
668 : : "a"(function), "c"(count), "S"(vec)
669 : "memory", "cc");
c1f41226
EH		 670#else
671 abort();
a1fd24af
AL		 672#endif
673
bdde476a 674 if (eax)
a1fd24af 675 *eax = vec[0];
bdde476a 676 if (ebx)
a1fd24af 677 *ebx = vec[1];
bdde476a 678 if (ecx)
a1fd24af 679 *ecx = vec[2];
bdde476a 680 if (edx)
a1fd24af 681 *edx = vec[3];
bdde476a 682}
c6dc6f63 683
d940ee9b
EH		 684/* CPU class name definitions: */
685
686#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
687#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
688
689/* Return type name for a given CPU model name
690 * Caller is responsible for freeing the returned string.
691 */
692static char *x86_cpu_type_name(const char *model_name)
693{
694 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
695}
696
500050d1
AF		 697static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
698{
d940ee9b
EH		 699 ObjectClass *oc;
700 char *typename;
701
500050d1
AF		 702 if (cpu_model == NULL) {
703 return NULL;
704 }
705
d940ee9b
EH		 706 typename = x86_cpu_type_name(cpu_model);
707 oc = object_class_by_name(typename);
708 g_free(typename);
709 return oc;
500050d1
AF		 710}
711
104494ea
IM		 712static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
713{
714 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
715 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
716 return g_strndup(class_name,
717 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
718}
719
d940ee9b 720struct X86CPUDefinition {
c6dc6f63
AP		 721 const char *name;
722 uint32_t level;
90e4b0c3 723 uint32_t xlevel;
99b88a17
IM		 724 /* vendor is zero-terminated, 12 character ASCII string */
725 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 726 int family;
727 int model;
728 int stepping;
0514ef2f 729 FeatureWordArray features;
c6dc6f63 730 char model_id[48];
d940ee9b 731};
c6dc6f63 732
9576de75 733static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 734 {
735 .name = "qemu64",
3046bb5d 736 .level = 0xd,
99b88a17 737 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 738 .family = 6,
f8e6a11a 739 .model = 6,
c6dc6f63 740 .stepping = 3,
0514ef2f 741 .features[FEAT_1_EDX] =
27861ecc 742 PPRO_FEATURES |
c6dc6f63 743 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 744 CPUID_PSE36,
0514ef2f 745 .features[FEAT_1_ECX] =
6aa91e4a 746 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 747 .features[FEAT_8000_0001_EDX] =
c6dc6f63 748 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 749 .features[FEAT_8000_0001_ECX] =
71195672 750 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 751 .xlevel = 0x8000000A,
9cf2cc3d 752 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 753 },
754 {
755 .name = "phenom",
756 .level = 5,
99b88a17 757 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 758 .family = 16,
759 .model = 2,
760 .stepping = 3,
b9fc20bc 761 /* Missing: CPUID_HT */
0514ef2f 762 .features[FEAT_1_EDX] =
27861ecc 763 PPRO_FEATURES |
c6dc6f63 764 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 765 CPUID_PSE36 | CPUID_VME,
0514ef2f 766 .features[FEAT_1_ECX] =
27861ecc 767 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 768 CPUID_EXT_POPCNT,
0514ef2f 769 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 770 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
771 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 772 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 773 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
774 CPUID_EXT3_CR8LEG,
775 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
776 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 777 .features[FEAT_8000_0001_ECX] =
27861ecc 778 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 779 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 780 /* Missing: CPUID_SVM_LBRV */
0514ef2f 781 .features[FEAT_SVM] =
b9fc20bc 782 CPUID_SVM_NPT,
c6dc6f63
AP		 783 .xlevel = 0x8000001A,
784 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
785 },
786 {
787 .name = "core2duo",
788 .level = 10,
99b88a17 789 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 790 .family = 6,
791 .model = 15,
792 .stepping = 11,
b9fc20bc 793 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 794 .features[FEAT_1_EDX] =
27861ecc 795 PPRO_FEATURES |
c6dc6f63 796 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 797 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
798 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 799 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 800 .features[FEAT_1_ECX] =
27861ecc 801 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 802 CPUID_EXT_CX16,
0514ef2f 803 .features[FEAT_8000_0001_EDX] =
27861ecc 804 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 805 .features[FEAT_8000_0001_ECX] =
27861ecc 806 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 807 .xlevel = 0x80000008,
808 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
809 },
810 {
811 .name = "kvm64",
3046bb5d 812 .level = 0xd,
99b88a17 813 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 814 .family = 15,
815 .model = 6,
816 .stepping = 1,
b3a4f0b1 817 /* Missing: CPUID_HT */
0514ef2f 818 .features[FEAT_1_EDX] =
b3a4f0b1 819 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 820 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
821 CPUID_PSE36,
822 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 823 .features[FEAT_1_ECX] =
27861ecc 824 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 825 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 826 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 827 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
828 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
829 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
830 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
831 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 832 .features[FEAT_8000_0001_ECX] =
27861ecc 833 0,
c6dc6f63
AP		 834 .xlevel = 0x80000008,
835 .model_id = "Common KVM processor"
836 },
c6dc6f63
AP		 837 {
838 .name = "qemu32",
839 .level = 4,
99b88a17 840 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 841 .family = 6,
f8e6a11a 842 .model = 6,
c6dc6f63 843 .stepping = 3,
0514ef2f 844 .features[FEAT_1_EDX] =
27861ecc 845 PPRO_FEATURES,
0514ef2f 846 .features[FEAT_1_ECX] =
6aa91e4a 847 CPUID_EXT_SSE3,
58012d66 848 .xlevel = 0x80000004,
9cf2cc3d 849 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 850 },
eafaf1e5
AP		 851 {
852 .name = "kvm32",
853 .level = 5,
99b88a17 854 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 855 .family = 15,
856 .model = 6,
857 .stepping = 1,
0514ef2f 858 .features[FEAT_1_EDX] =
b3a4f0b1 859 PPRO_FEATURES | CPUID_VME |
eafaf1e5 860 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 861 .features[FEAT_1_ECX] =
27861ecc 862 CPUID_EXT_SSE3,
0514ef2f 863 .features[FEAT_8000_0001_ECX] =
27861ecc 864 0,
eafaf1e5
AP		 865 .xlevel = 0x80000008,
866 .model_id = "Common 32-bit KVM processor"
867 },
c6dc6f63
AP		 868 {
869 .name = "coreduo",
870 .level = 10,
99b88a17 871 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 872 .family = 6,
873 .model = 14,
874 .stepping = 8,
b9fc20bc 875 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 876 .features[FEAT_1_EDX] =
27861ecc 877 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 878 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
879 CPUID_SS,
880 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 881 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 882 .features[FEAT_1_ECX] =
e93abc14 883 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 884 .features[FEAT_8000_0001_EDX] =
27861ecc 885 CPUID_EXT2_NX,
c6dc6f63
AP		 886 .xlevel = 0x80000008,
887 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
888 },
889 {
890 .name = "486",
58012d66 891 .level = 1,
99b88a17 892 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 893 .family = 4,
b2a856d9 894 .model = 8,
c6dc6f63 895 .stepping = 0,
0514ef2f 896 .features[FEAT_1_EDX] =
27861ecc 897 I486_FEATURES,
c6dc6f63
AP		 898 .xlevel = 0,
899 },
900 {
901 .name = "pentium",
902 .level = 1,
99b88a17 903 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 904 .family = 5,
905 .model = 4,
906 .stepping = 3,
0514ef2f 907 .features[FEAT_1_EDX] =
27861ecc 908 PENTIUM_FEATURES,
c6dc6f63
AP		 909 .xlevel = 0,
910 },
911 {
912 .name = "pentium2",
913 .level = 2,
99b88a17 914 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 915 .family = 6,
916 .model = 5,
917 .stepping = 2,
0514ef2f 918 .features[FEAT_1_EDX] =
27861ecc 919 PENTIUM2_FEATURES,
c6dc6f63
AP		 920 .xlevel = 0,
921 },
922 {
923 .name = "pentium3",
3046bb5d 924 .level = 3,
99b88a17 925 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 926 .family = 6,
927 .model = 7,
928 .stepping = 3,
0514ef2f 929 .features[FEAT_1_EDX] =
27861ecc 930 PENTIUM3_FEATURES,
c6dc6f63
AP		 931 .xlevel = 0,
932 },
933 {
934 .name = "athlon",
935 .level = 2,
99b88a17 936 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 937 .family = 6,
938 .model = 2,
939 .stepping = 3,
0514ef2f 940 .features[FEAT_1_EDX] =
27861ecc 941 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 942 CPUID_MCA,
0514ef2f 943 .features[FEAT_8000_0001_EDX] =
60032ac0 944 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 945 .xlevel = 0x80000008,
9cf2cc3d 946 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 947 },
948 {
949 .name = "n270",
3046bb5d 950 .level = 10,
99b88a17 951 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 952 .family = 6,
953 .model = 28,
954 .stepping = 2,
b9fc20bc 955 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 956 .features[FEAT_1_EDX] =
27861ecc 957 PPRO_FEATURES |
b9fc20bc
EH		 958 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
959 CPUID_ACPI | CPUID_SS,
c6dc6f63 960 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 961 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
962 * CPUID_EXT_XTPR */
0514ef2f 963 .features[FEAT_1_ECX] =
27861ecc 964 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 965 CPUID_EXT_MOVBE,
0514ef2f 966 .features[FEAT_8000_0001_EDX] =
60032ac0 967 CPUID_EXT2_NX,
0514ef2f 968 .features[FEAT_8000_0001_ECX] =
27861ecc 969 CPUID_EXT3_LAHF_LM,
3046bb5d 970 .xlevel = 0x80000008,
c6dc6f63
AP		 971 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
972 },
3eca4642
EH		 973 {
974 .name = "Conroe",
3046bb5d 975 .level = 10,
99b88a17 976 .vendor = CPUID_VENDOR_INTEL,
3eca4642 977 .family = 6,
ffce9ebb 978 .model = 15,
3eca4642 979 .stepping = 3,
0514ef2f 980 .features[FEAT_1_EDX] =
b3a4f0b1 981 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 982 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
983 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
984 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
985 CPUID_DE | CPUID_FP87,
0514ef2f 986 .features[FEAT_1_ECX] =
27861ecc 987 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 988 .features[FEAT_8000_0001_EDX] =
27861ecc 989 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 990 .features[FEAT_8000_0001_ECX] =
27861ecc 991 CPUID_EXT3_LAHF_LM,
3046bb5d 992 .xlevel = 0x80000008,
3eca4642
EH		 993 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
994 },
995 {
996 .name = "Penryn",
3046bb5d 997 .level = 10,
99b88a17 998 .vendor = CPUID_VENDOR_INTEL,
3eca4642 999 .family = 6,
ffce9ebb 1000 .model = 23,
3eca4642 1001 .stepping = 3,
0514ef2f 1002 .features[FEAT_1_EDX] =
b3a4f0b1 1003 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1004 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1005 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1006 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1007 CPUID_DE | CPUID_FP87,
0514ef2f 1008 .features[FEAT_1_ECX] =
27861ecc 1009 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1010 CPUID_EXT_SSE3,
0514ef2f 1011 .features[FEAT_8000_0001_EDX] =
27861ecc 1012 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1013 .features[FEAT_8000_0001_ECX] =
27861ecc 1014 CPUID_EXT3_LAHF_LM,
3046bb5d 1015 .xlevel = 0x80000008,
3eca4642
EH		 1016 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1017 },
1018 {
1019 .name = "Nehalem",
3046bb5d 1020 .level = 11,
99b88a17 1021 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1022 .family = 6,
ffce9ebb 1023 .model = 26,
3eca4642 1024 .stepping = 3,
0514ef2f 1025 .features[FEAT_1_EDX] =
b3a4f0b1 1026 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1027 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1028 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1029 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1030 CPUID_DE | CPUID_FP87,
0514ef2f 1031 .features[FEAT_1_ECX] =
27861ecc 1032 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1033 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1034 .features[FEAT_8000_0001_EDX] =
27861ecc 1035 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1036 .features[FEAT_8000_0001_ECX] =
27861ecc 1037 CPUID_EXT3_LAHF_LM,
3046bb5d 1038 .xlevel = 0x80000008,
3eca4642
EH		 1039 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1040 },
1041 {
1042 .name = "Westmere",
1043 .level = 11,
99b88a17 1044 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1045 .family = 6,
1046 .model = 44,
1047 .stepping = 1,
0514ef2f 1048 .features[FEAT_1_EDX] =
b3a4f0b1 1049 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1050 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1051 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1052 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1053 CPUID_DE | CPUID_FP87,
0514ef2f 1054 .features[FEAT_1_ECX] =
27861ecc 1055 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1056 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1057 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1058 .features[FEAT_8000_0001_EDX] =
27861ecc 1059 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1060 .features[FEAT_8000_0001_ECX] =
27861ecc 1061 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1062 .features[FEAT_6_EAX] =
1063 CPUID_6_EAX_ARAT,
3046bb5d 1064 .xlevel = 0x80000008,
3eca4642
EH		 1065 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1066 },
1067 {
1068 .name = "SandyBridge",
1069 .level = 0xd,
99b88a17 1070 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1071 .family = 6,
1072 .model = 42,
1073 .stepping = 1,
0514ef2f 1074 .features[FEAT_1_EDX] =
b3a4f0b1 1075 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1076 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1077 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1078 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1079 CPUID_DE | CPUID_FP87,
0514ef2f 1080 .features[FEAT_1_ECX] =
27861ecc 1081 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1082 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1083 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1084 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1085 CPUID_EXT_SSE3,
0514ef2f 1086 .features[FEAT_8000_0001_EDX] =
27861ecc 1087 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1088 CPUID_EXT2_SYSCALL,
0514ef2f 1089 .features[FEAT_8000_0001_ECX] =
27861ecc 1090 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1091 .features[FEAT_XSAVE] =
1092 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1093 .features[FEAT_6_EAX] =
1094 CPUID_6_EAX_ARAT,
3046bb5d 1095 .xlevel = 0x80000008,
3eca4642
EH		 1096 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1097 },
2f9ac42a
PB		 1098 {
1099 .name = "IvyBridge",
1100 .level = 0xd,
1101 .vendor = CPUID_VENDOR_INTEL,
1102 .family = 6,
1103 .model = 58,
1104 .stepping = 9,
1105 .features[FEAT_1_EDX] =
1106 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1107 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1108 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1109 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1110 CPUID_DE | CPUID_FP87,
1111 .features[FEAT_1_ECX] =
1112 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1113 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1114 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1115 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1116 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1117 .features[FEAT_7_0_EBX] =
1118 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1119 CPUID_7_0_EBX_ERMS,
1120 .features[FEAT_8000_0001_EDX] =
1121 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1122 CPUID_EXT2_SYSCALL,
1123 .features[FEAT_8000_0001_ECX] =
1124 CPUID_EXT3_LAHF_LM,
1125 .features[FEAT_XSAVE] =
1126 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1127 .features[FEAT_6_EAX] =
1128 CPUID_6_EAX_ARAT,
3046bb5d 1129 .xlevel = 0x80000008,
2f9ac42a
PB		 1130 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1131 },
37507094 1132 {
a356850b
EH		 1133 .name = "Haswell-noTSX",
1134 .level = 0xd,
1135 .vendor = CPUID_VENDOR_INTEL,
1136 .family = 6,
1137 .model = 60,
1138 .stepping = 1,
1139 .features[FEAT_1_EDX] =
1140 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1141 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1142 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1143 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1144 CPUID_DE | CPUID_FP87,
1145 .features[FEAT_1_ECX] =
1146 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1147 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1148 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1149 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1150 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1151 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1152 .features[FEAT_8000_0001_EDX] =
1153 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1154 CPUID_EXT2_SYSCALL,
1155 .features[FEAT_8000_0001_ECX] =
becb6667 1156 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1157 .features[FEAT_7_0_EBX] =
1158 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1159 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1160 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1161 .features[FEAT_XSAVE] =
1162 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1163 .features[FEAT_6_EAX] =
1164 CPUID_6_EAX_ARAT,
3046bb5d 1165 .xlevel = 0x80000008,
a356850b
EH		 1166 .model_id = "Intel Core Processor (Haswell, no TSX)",
1167 }, {
37507094
EH		 1168 .name = "Haswell",
1169 .level = 0xd,
99b88a17 1170 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1171 .family = 6,
1172 .model = 60,
1173 .stepping = 1,
0514ef2f 1174 .features[FEAT_1_EDX] =
b3a4f0b1 1175 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1176 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1177 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1178 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1179 CPUID_DE | CPUID_FP87,
0514ef2f 1180 .features[FEAT_1_ECX] =
27861ecc 1181 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1182 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1183 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1184 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1185 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1186 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1187 .features[FEAT_8000_0001_EDX] =
27861ecc 1188 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1189 CPUID_EXT2_SYSCALL,
0514ef2f 1190 .features[FEAT_8000_0001_ECX] =
becb6667 1191 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1192 .features[FEAT_7_0_EBX] =
27861ecc 1193 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1194 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1195 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1196 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1197 .features[FEAT_XSAVE] =
1198 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1199 .features[FEAT_6_EAX] =
1200 CPUID_6_EAX_ARAT,
3046bb5d 1201 .xlevel = 0x80000008,
37507094
EH		 1202 .model_id = "Intel Core Processor (Haswell)",
1203 },
a356850b
EH		 1204 {
1205 .name = "Broadwell-noTSX",
1206 .level = 0xd,
1207 .vendor = CPUID_VENDOR_INTEL,
1208 .family = 6,
1209 .model = 61,
1210 .stepping = 2,
1211 .features[FEAT_1_EDX] =
1212 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1213 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1214 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1215 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1216 CPUID_DE | CPUID_FP87,
1217 .features[FEAT_1_ECX] =
1218 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1219 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1220 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1221 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1222 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1223 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1224 .features[FEAT_8000_0001_EDX] =
1225 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1226 CPUID_EXT2_SYSCALL,
1227 .features[FEAT_8000_0001_ECX] =
becb6667 1228 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1229 .features[FEAT_7_0_EBX] =
1230 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1231 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1232 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1233 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1234 CPUID_7_0_EBX_SMAP,
1235 .features[FEAT_XSAVE] =
1236 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1237 .features[FEAT_6_EAX] =
1238 CPUID_6_EAX_ARAT,
3046bb5d 1239 .xlevel = 0x80000008,
a356850b
EH		 1240 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1241 },
ece01354
EH		 1242 {
1243 .name = "Broadwell",
1244 .level = 0xd,
1245 .vendor = CPUID_VENDOR_INTEL,
1246 .family = 6,
1247 .model = 61,
1248 .stepping = 2,
1249 .features[FEAT_1_EDX] =
b3a4f0b1 1250 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1251 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1252 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1253 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1254 CPUID_DE | CPUID_FP87,
1255 .features[FEAT_1_ECX] =
1256 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1257 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1258 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1259 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1260 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1261 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1262 .features[FEAT_8000_0001_EDX] =
1263 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1264 CPUID_EXT2_SYSCALL,
1265 .features[FEAT_8000_0001_ECX] =
becb6667 1266 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1267 .features[FEAT_7_0_EBX] =
1268 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1269 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1270 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1271 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1272 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1273 .features[FEAT_XSAVE] =
1274 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1275 .features[FEAT_6_EAX] =
1276 CPUID_6_EAX_ARAT,
3046bb5d 1277 .xlevel = 0x80000008,
ece01354
EH		 1278 .model_id = "Intel Core Processor (Broadwell)",
1279 },
f6f949e9
EH		 1280 {
1281 .name = "Skylake-Client",
1282 .level = 0xd,
1283 .vendor = CPUID_VENDOR_INTEL,
1284 .family = 6,
1285 .model = 94,
1286 .stepping = 3,
1287 .features[FEAT_1_EDX] =
1288 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1289 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1290 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1291 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1292 CPUID_DE | CPUID_FP87,
1293 .features[FEAT_1_ECX] =
1294 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1295 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1296 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1297 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1298 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1299 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1300 .features[FEAT_8000_0001_EDX] =
1301 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1302 CPUID_EXT2_SYSCALL,
1303 .features[FEAT_8000_0001_ECX] =
1304 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1305 .features[FEAT_7_0_EBX] =
1306 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1307 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1308 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1309 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1310 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1311 /* Missing: XSAVES (not supported by some Linux versions,
1312 * including v4.1 to v4.6).
1313 * KVM doesn't yet expose any XSAVES state save component,
1314 * and the only one defined in Skylake (processor tracing)
1315 * probably will block migration anyway.
1316 */
1317 .features[FEAT_XSAVE] =
1318 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1319 CPUID_XSAVE_XGETBV1,
1320 .features[FEAT_6_EAX] =
1321 CPUID_6_EAX_ARAT,
1322 .xlevel = 0x80000008,
1323 .model_id = "Intel Core Processor (Skylake)",
1324 },
3eca4642
EH		 1325 {
1326 .name = "Opteron_G1",
1327 .level = 5,
99b88a17 1328 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1329 .family = 15,
1330 .model = 6,
1331 .stepping = 1,
0514ef2f 1332 .features[FEAT_1_EDX] =
b3a4f0b1 1333 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1334 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1335 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1336 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1337 CPUID_DE | CPUID_FP87,
0514ef2f 1338 .features[FEAT_1_ECX] =
27861ecc 1339 CPUID_EXT_SSE3,
0514ef2f 1340 .features[FEAT_8000_0001_EDX] =
27861ecc 1341 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1342 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1343 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1344 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1345 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1346 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1347 .xlevel = 0x80000008,
1348 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1349 },
1350 {
1351 .name = "Opteron_G2",
1352 .level = 5,
99b88a17 1353 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1354 .family = 15,
1355 .model = 6,
1356 .stepping = 1,
0514ef2f 1357 .features[FEAT_1_EDX] =
b3a4f0b1 1358 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1359 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1360 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1361 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1362 CPUID_DE | CPUID_FP87,
0514ef2f 1363 .features[FEAT_1_ECX] =
27861ecc 1364 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1365 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1366 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1367 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1368 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1369 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1370 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1371 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1372 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1373 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1374 .features[FEAT_8000_0001_ECX] =
27861ecc 1375 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1376 .xlevel = 0x80000008,
1377 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1378 },
1379 {
1380 .name = "Opteron_G3",
1381 .level = 5,
99b88a17 1382 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 1383 .family = 16,
1384 .model = 2,
1385 .stepping = 3,
0514ef2f 1386 .features[FEAT_1_EDX] =
b3a4f0b1 1387 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1388 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1389 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1390 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1391 CPUID_DE | CPUID_FP87,
0514ef2f 1392 .features[FEAT_1_ECX] =
27861ecc 1393 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1394 CPUID_EXT_SSE3,
33b5e8c0 1395 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1396 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1397 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1398 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1399 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1400 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1401 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1402 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1403 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1404 .features[FEAT_8000_0001_ECX] =
27861ecc 1405 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1406 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1407 .xlevel = 0x80000008,
1408 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1409 },
1410 {
1411 .name = "Opteron_G4",
1412 .level = 0xd,
99b88a17 1413 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1414 .family = 21,
1415 .model = 1,
1416 .stepping = 2,
0514ef2f 1417 .features[FEAT_1_EDX] =
b3a4f0b1 1418 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1419 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1420 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1421 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1422 CPUID_DE | CPUID_FP87,
0514ef2f 1423 .features[FEAT_1_ECX] =
27861ecc 1424 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1425 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1426 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1427 CPUID_EXT_SSE3,
33b5e8c0 1428 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1429 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1430 CPUID_EXT2_LM |
b3fb3a20
EH		 1431 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1432 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1433 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1434 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1435 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1436 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1437 .features[FEAT_8000_0001_ECX] =
27861ecc 1438 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1439 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1440 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1441 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1442 /* no xsaveopt! */
3eca4642
EH		 1443 .xlevel = 0x8000001A,
1444 .model_id = "AMD Opteron 62xx class CPU",
1445 },
021941b9
AP		 1446 {
1447 .name = "Opteron_G5",
1448 .level = 0xd,
99b88a17 1449 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1450 .family = 21,
1451 .model = 2,
1452 .stepping = 0,
0514ef2f 1453 .features[FEAT_1_EDX] =
b3a4f0b1 1454 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1455 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1456 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1457 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1458 CPUID_DE | CPUID_FP87,
0514ef2f 1459 .features[FEAT_1_ECX] =
27861ecc 1460 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1461 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1462 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1463 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1464 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1465 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1466 CPUID_EXT2_LM |
b3fb3a20
EH		 1467 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1468 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1469 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1470 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1471 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1472 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1473 .features[FEAT_8000_0001_ECX] =
27861ecc 1474 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1475 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1476 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1477 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1478 /* no xsaveopt! */
021941b9
AP		 1479 .xlevel = 0x8000001A,
1480 .model_id = "AMD Opteron 63xx class CPU",
1481 },
c6dc6f63
AP		 1482};
1483
5114e842
EH		 1484typedef struct PropValue {
1485 const char *prop, *value;
1486} PropValue;
1487
1488/* KVM-specific features that are automatically added/removed
1489 * from all CPU models when KVM is enabled.
1490 */
1491static PropValue kvm_default_props[] = {
1492 { "kvmclock", "on" },
1493 { "kvm-nopiodelay", "on" },
1494 { "kvm-asyncpf", "on" },
1495 { "kvm-steal-time", "on" },
1496 { "kvm-pv-eoi", "on" },
1497 { "kvmclock-stable-bit", "on" },
1498 { "x2apic", "on" },
1499 { "acpi", "off" },
1500 { "monitor", "off" },
1501 { "svm", "off" },
1502 { NULL, NULL },
1503};
1504
04d99c3c
EH		 1505/* TCG-specific defaults that override all CPU models when using TCG
1506 */
1507static PropValue tcg_default_props[] = {
1508 { "vme", "off" },
1509 { NULL, NULL },
1510};
1511
1512
5114e842
EH		 1513void x86_cpu_change_kvm_default(const char *prop, const char *value)
1514{
1515 PropValue *pv;
1516 for (pv = kvm_default_props; pv->prop; pv++) {
1517 if (!strcmp(pv->prop, prop)) {
1518 pv->value = value;
1519 break;
1520 }
1521 }
1522
1523 /* It is valid to call this function only for properties that
1524 * are already present in the kvm_default_props table.
1525 */
1526 assert(pv->prop);
1527}
1528
4d1b279b
EH		 1529static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1530 bool migratable_only);
1531
d940ee9b
EH		 1532#ifdef CONFIG_KVM
1533
40bfe48f
HZ		 1534static bool lmce_supported(void)
1535{
1536 uint64_t mce_cap;
1537
1538 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1539 return false;
1540 }
1541
1542 return !!(mce_cap & MCG_LMCE_P);
1543}
1544
c6dc6f63
AP		 1545static int cpu_x86_fill_model_id(char *str)
1546{
1547 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1548 int i;
1549
1550 for (i = 0; i < 3; i++) {
1551 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1552 memcpy(str + i * 16 + 0, &eax, 4);
1553 memcpy(str + i * 16 + 4, &ebx, 4);
1554 memcpy(str + i * 16 + 8, &ecx, 4);
1555 memcpy(str + i * 16 + 12, &edx, 4);
1556 }
1557 return 0;
1558}
1559
d940ee9b
EH		 1560static X86CPUDefinition host_cpudef;
1561
84f1b92f 1562static Property host_x86_cpu_properties[] = {
120eee7d 1563 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1564 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1565 DEFINE_PROP_END_OF_LIST()
1566};
1567
d940ee9b 1568/* class_init for the "host" CPU model
6e746f30 1569 *
d940ee9b 1570 * This function may be called before KVM is initialized.
6e746f30 1571 */
d940ee9b 1572static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1573{
84f1b92f 1574 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1575 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1576 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1577
d940ee9b 1578 xcc->kvm_required = true;
6e746f30 1579
c6dc6f63 1580 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1581 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1582
1583 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1584 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1585 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1586 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1587
d940ee9b 1588 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1589
d940ee9b 1590 xcc->cpu_def = &host_cpudef;
ee465a3e
EH		 1591 xcc->model_description =
1592 "KVM processor with all supported host features "
1593 "(only available in KVM mode)";
d940ee9b
EH		 1594
1595 /* level, xlevel, xlevel2, and the feature words are initialized on
1596 * instance_init, because they require KVM to be initialized.
1597 */
84f1b92f
EH		 1598
1599 dc->props = host_x86_cpu_properties;
4c315c27
MA		 1600 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1601 dc->cannot_destroy_with_object_finalize_yet = true;
d940ee9b
EH		 1602}
1603
1604static void host_x86_cpu_initfn(Object *obj)
1605{
1606 X86CPU *cpu = X86_CPU(obj);
1607 CPUX86State *env = &cpu->env;
1608 KVMState *s = kvm_state;
d940ee9b 1609
4d1b279b
EH		 1610 /* We can't fill the features array here because we don't know yet if
1611 * "migratable" is true or false.
1612 */
1613 cpu->host_features = true;
1614
104494ea 1615 /* If KVM is disabled, x86_cpu_realizefn() will report an error later */
e4356010 1616 if (kvm_enabled()) {
c39c0edf
EH		 1617 env->cpuid_min_level =
1618 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1619 env->cpuid_min_xlevel =
1620 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1621 env->cpuid_min_xlevel2 =
1622 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
40bfe48f
HZ		 1623
1624 if (lmce_supported()) {
1625 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1626 }
e4356010 1627 }
2a573259 1628
d940ee9b 1629 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1630}
1631
d940ee9b
EH		 1632static const TypeInfo host_x86_cpu_type_info = {
1633 .name = X86_CPU_TYPE_NAME("host"),
1634 .parent = TYPE_X86_CPU,
1635 .instance_init = host_x86_cpu_initfn,
1636 .class_init = host_x86_cpu_class_init,
1637};
1638
1639#endif
1640
8459e396 1641static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1642{
8459e396 1643 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1644 int i;
1645
857aee33 1646 for (i = 0; i < 32; ++i) {
72370dc1 1647 if ((1UL << i) & mask) {
bffd67b0 1648 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1649 assert(reg);
fefb41bf 1650 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1651 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1652 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1653 f->cpuid_eax, reg,
1654 f->feat_names[i] ? "." : "",
1655 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1656 }
857aee33 1657 }
c6dc6f63
AP		 1658}
1659
d7bce999
EB		 1660static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1661 const char *name, void *opaque,
1662 Error **errp)
95b8519d
AF		 1663{
1664 X86CPU *cpu = X86_CPU(obj);
1665 CPUX86State *env = &cpu->env;
1666 int64_t value;
1667
1668 value = (env->cpuid_version >> 8) & 0xf;
1669 if (value == 0xf) {
1670 value += (env->cpuid_version >> 20) & 0xff;
1671 }
51e72bc1 1672 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1673}
1674
d7bce999
EB		 1675static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1676 const char *name, void *opaque,
1677 Error **errp)
ed5e1ec3 1678{
71ad61d3
AF		 1679 X86CPU *cpu = X86_CPU(obj);
1680 CPUX86State *env = &cpu->env;
1681 const int64_t min = 0;
1682 const int64_t max = 0xff + 0xf;
65cd9064 1683 Error *local_err = NULL;
71ad61d3
AF		 1684 int64_t value;
1685
51e72bc1 1686 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1687 if (local_err) {
1688 error_propagate(errp, local_err);
71ad61d3
AF		 1689 return;
1690 }
1691 if (value < min || value > max) {
c6bd8c70
MA		 1692 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1693 name ? name : "null", value, min, max);
71ad61d3
AF		 1694 return;
1695 }
1696
ed5e1ec3 1697 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1698 if (value > 0x0f) {
1699 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1700 } else {
71ad61d3 1701 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1702 }
1703}
1704
d7bce999
EB		 1705static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1706 const char *name, void *opaque,
1707 Error **errp)
67e30c83
AF		 1708{
1709 X86CPU *cpu = X86_CPU(obj);
1710 CPUX86State *env = &cpu->env;
1711 int64_t value;
1712
1713 value = (env->cpuid_version >> 4) & 0xf;
1714 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1715 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1716}
1717
d7bce999
EB		 1718static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1719 const char *name, void *opaque,
1720 Error **errp)
b0704cbd 1721{
c5291a4f
AF		 1722 X86CPU *cpu = X86_CPU(obj);
1723 CPUX86State *env = &cpu->env;
1724 const int64_t min = 0;
1725 const int64_t max = 0xff;
65cd9064 1726 Error *local_err = NULL;
c5291a4f
AF		 1727 int64_t value;
1728
51e72bc1 1729 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1730 if (local_err) {
1731 error_propagate(errp, local_err);
c5291a4f
AF		 1732 return;
1733 }
1734 if (value < min || value > max) {
c6bd8c70
MA		 1735 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1736 name ? name : "null", value, min, max);
c5291a4f
AF		 1737 return;
1738 }
1739
b0704cbd 1740 env->cpuid_version &= ~0xf00f0;
c5291a4f 1741 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1742}
1743
35112e41 1744static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1745 const char *name, void *opaque,
35112e41
AF		 1746 Error **errp)
1747{
1748 X86CPU *cpu = X86_CPU(obj);
1749 CPUX86State *env = &cpu->env;
1750 int64_t value;
1751
1752 value = env->cpuid_version & 0xf;
51e72bc1 1753 visit_type_int(v, name, &value, errp);
35112e41
AF		 1754}
1755
036e2222 1756static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1757 const char *name, void *opaque,
036e2222 1758 Error **errp)
38c3dc46 1759{
036e2222
AF		 1760 X86CPU *cpu = X86_CPU(obj);
1761 CPUX86State *env = &cpu->env;
1762 const int64_t min = 0;
1763 const int64_t max = 0xf;
65cd9064 1764 Error *local_err = NULL;
036e2222
AF		 1765 int64_t value;
1766
51e72bc1 1767 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1768 if (local_err) {
1769 error_propagate(errp, local_err);
036e2222
AF		 1770 return;
1771 }
1772 if (value < min || value > max) {
c6bd8c70
MA		 1773 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1774 name ? name : "null", value, min, max);
036e2222
AF		 1775 return;
1776 }
1777
38c3dc46 1778 env->cpuid_version &= ~0xf;
036e2222 1779 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1780}
1781
d480e1af
AF		 1782static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1783{
1784 X86CPU *cpu = X86_CPU(obj);
1785 CPUX86State *env = &cpu->env;
1786 char *value;
d480e1af 1787
e42a92ae 1788 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1789 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1790 env->cpuid_vendor3);
d480e1af
AF		 1791 return value;
1792}
1793
1794static void x86_cpuid_set_vendor(Object *obj, const char *value,
1795 Error **errp)
1796{
1797 X86CPU *cpu = X86_CPU(obj);
1798 CPUX86State *env = &cpu->env;
1799 int i;
1800
9df694ee 1801 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1802 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1803 return;
1804 }
1805
1806 env->cpuid_vendor1 = 0;
1807 env->cpuid_vendor2 = 0;
1808 env->cpuid_vendor3 = 0;
1809 for (i = 0; i < 4; i++) {
1810 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1811 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1812 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1813 }
d480e1af
AF		 1814}
1815
63e886eb
AF		 1816static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1817{
1818 X86CPU *cpu = X86_CPU(obj);
1819 CPUX86State *env = &cpu->env;
1820 char *value;
1821 int i;
1822
1823 value = g_malloc(48 + 1);
1824 for (i = 0; i < 48; i++) {
1825 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1826 }
1827 value[48] = '\0';
1828 return value;
1829}
1830
938d4c25
AF		 1831static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1832 Error **errp)
dcce6675 1833{
938d4c25
AF		 1834 X86CPU *cpu = X86_CPU(obj);
1835 CPUX86State *env = &cpu->env;
dcce6675
AF		 1836 int c, len, i;
1837
1838 if (model_id == NULL) {
1839 model_id = "";
1840 }
1841 len = strlen(model_id);
d0a6acf4 1842 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1843 for (i = 0; i < 48; i++) {
1844 if (i >= len) {
1845 c = '\0';
1846 } else {
1847 c = (uint8_t)model_id[i];
1848 }
1849 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1850 }
1851}
1852
d7bce999
EB		 1853static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1854 void *opaque, Error **errp)
89e48965
AF		 1855{
1856 X86CPU *cpu = X86_CPU(obj);
1857 int64_t value;
1858
1859 value = cpu->env.tsc_khz * 1000;
51e72bc1 1860 visit_type_int(v, name, &value, errp);
89e48965
AF		 1861}
1862
d7bce999
EB		 1863static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1864 void *opaque, Error **errp)
89e48965
AF		 1865{
1866 X86CPU *cpu = X86_CPU(obj);
1867 const int64_t min = 0;
2e84849a 1868 const int64_t max = INT64_MAX;
65cd9064 1869 Error *local_err = NULL;
89e48965
AF		 1870 int64_t value;
1871
51e72bc1 1872 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1873 if (local_err) {
1874 error_propagate(errp, local_err);
89e48965
AF		 1875 return;
1876 }
1877 if (value < min || value > max) {
c6bd8c70
MA		 1878 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1879 name ? name : "null", value, min, max);
89e48965
AF		 1880 return;
1881 }
1882
36f96c4b 1883 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1884}
1885
7e5292b5 1886/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1887static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1888 const char *name, void *opaque,
1889 Error **errp)
8e8aba50 1890{
7e5292b5 1891 uint32_t *array = (uint32_t *)opaque;
8e8aba50 1892 FeatureWord w;
8e8aba50
EH		 1893 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1894 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1895 X86CPUFeatureWordInfoList *list = NULL;
1896
1897 for (w = 0; w < FEATURE_WORDS; w++) {
1898 FeatureWordInfo *wi = &feature_word_info[w];
1899 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1900 qwi->cpuid_input_eax = wi->cpuid_eax;
1901 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1902 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1903 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1904 qwi->features = array[w];
8e8aba50
EH		 1905
1906 /* List will be in reverse order, but order shouldn't matter */
1907 list_entries[w].next = list;
1908 list_entries[w].value = &word_infos[w];
1909 list = &list_entries[w];
1910 }
1911
6b62d961 1912 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 1913}
1914
d7bce999
EB		 1915static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1916 void *opaque, Error **errp)
c8f0f88e
IM		 1917{
1918 X86CPU *cpu = X86_CPU(obj);
1919 int64_t value = cpu->hyperv_spinlock_attempts;
1920
51e72bc1 1921 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1922}
1923
d7bce999
EB		 1924static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1925 void *opaque, Error **errp)
c8f0f88e
IM		 1926{
1927 const int64_t min = 0xFFF;
1928 const int64_t max = UINT_MAX;
1929 X86CPU *cpu = X86_CPU(obj);
1930 Error *err = NULL;
1931 int64_t value;
1932
51e72bc1 1933 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1934 if (err) {
1935 error_propagate(errp, err);
1936 return;
1937 }
1938
1939 if (value < min || value > max) {
1940 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1941 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1942 object_get_typename(obj), name ? name : "null",
1943 value, min, max);
c8f0f88e
IM		 1944 return;
1945 }
1946 cpu->hyperv_spinlock_attempts = value;
1947}
1948
1949static PropertyInfo qdev_prop_spinlocks = {
1950 .name = "int",
1951 .get = x86_get_hv_spinlocks,
1952 .set = x86_set_hv_spinlocks,
1953};
1954
72ac2e87
IM		 1955/* Convert all '_' in a feature string option name to '-', to make feature
1956 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1957 */
1958static inline void feat2prop(char *s)
1959{
1960 while ((s = strchr(s, '_'))) {
1961 *s = '-';
1962 }
1963}
1964
b54c9377
EH		 1965/* Return the feature property name for a feature flag bit */
1966static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
1967{
1968 /* XSAVE components are automatically enabled by other features,
1969 * so return the original feature name instead
1970 */
1971 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
1972 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
1973
1974 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
1975 x86_ext_save_areas[comp].bits) {
1976 w = x86_ext_save_areas[comp].feature;
1977 bitnr = ctz32(x86_ext_save_areas[comp].bits);
1978 }
1979 }
1980
1981 assert(bitnr < 32);
1982 assert(w < FEATURE_WORDS);
1983 return feature_word_info[w].feat_names[bitnr];
1984}
1985
dc15c051
IM		 1986/* Compatibily hack to maintain legacy +-feat semantic,
1987 * where +-feat overwrites any feature set by
1988 * feat=on|feat even if the later is parsed after +-feat
1989 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
1990 */
2fae0d96 1991static GList *plus_features, *minus_features;
dc15c051 1992
83a00f60
EH		 1993static gint compare_string(gconstpointer a, gconstpointer b)
1994{
1995 return g_strcmp0(a, b);
1996}
1997
8f961357
EH		 1998/* Parse "+feature,-feature,feature=foo" CPU feature string
1999 */
62a48a2a 2000static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 2001 Error **errp)
8f961357 2002{
8f961357 2003 char *featurestr; /* Single 'key=value" string being parsed */
94a444b2 2004 Error *local_err = NULL;
62a48a2a 2005 static bool cpu_globals_initialized;
83a00f60 2006 bool ambiguous = false;
62a48a2a
IM		 2007
2008 if (cpu_globals_initialized) {
2009 return;
2010 }
2011 cpu_globals_initialized = true;
8f961357 2012
f6750e95
EH		 2013 if (!features) {
2014 return;
2015 }
2016
2017 for (featurestr = strtok(features, ",");
2018 featurestr && !local_err;
2019 featurestr = strtok(NULL, ",")) {
2020 const char *name;
2021 const char *val = NULL;
2022 char *eq = NULL;
cf2887c9 2023 char num[32];
62a48a2a 2024 GlobalProperty *prop;
c6dc6f63 2025
f6750e95 2026 /* Compatibility syntax: */
c6dc6f63 2027 if (featurestr[0] == '+') {
2fae0d96
EH		 2028 plus_features = g_list_append(plus_features,
2029 g_strdup(featurestr + 1));
f6750e95 2030 continue;
c6dc6f63 2031 } else if (featurestr[0] == '-') {
2fae0d96
EH		 2032 minus_features = g_list_append(minus_features,
2033 g_strdup(featurestr + 1));
f6750e95
EH		 2034 continue;
2035 }
2036
2037 eq = strchr(featurestr, '=');
2038 if (eq) {
2039 *eq++ = 0;
2040 val = eq;
c6dc6f63 2041 } else {
f6750e95 2042 val = "on";
a91987c2 2043 }
f6750e95
EH		 2044
2045 feat2prop(featurestr);
2046 name = featurestr;
2047
83a00f60
EH		 2048 if (g_list_find_custom(plus_features, name, compare_string)) {
2049 error_report("warning: Ambiguous CPU model string. "
2050 "Don't mix both \"+%s\" and \"%s=%s\"",
2051 name, name, val);
2052 ambiguous = true;
2053 }
2054 if (g_list_find_custom(minus_features, name, compare_string)) {
2055 error_report("warning: Ambiguous CPU model string. "
2056 "Don't mix both \"-%s\" and \"%s=%s\"",
2057 name, name, val);
2058 ambiguous = true;
2059 }
2060
f6750e95
EH		 2061 /* Special case: */
2062 if (!strcmp(name, "tsc-freq")) {
2063 int64_t tsc_freq;
2064 char *err;
f6750e95
EH		 2065
2066 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
2067 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
2068 if (tsc_freq < 0 || *err) {
2069 error_setg(errp, "bad numerical value %s", val);
2070 return;
2071 }
2072 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2073 val = num;
2074 name = "tsc-frequency";
c6dc6f63 2075 }
f6750e95 2076
62a48a2a
IM		 2077 prop = g_new0(typeof(*prop), 1);
2078 prop->driver = typename;
2079 prop->property = g_strdup(name);
2080 prop->value = g_strdup(val);
2081 prop->errp = &error_fatal;
2082 qdev_prop_register_global(prop);
f6750e95
EH		 2083 }
2084
83a00f60
EH		 2085 if (ambiguous) {
2086 error_report("warning: Compatibility of ambiguous CPU model "
2087 "strings won't be kept on future QEMU versions");
2088 }
2089
f6750e95
EH		 2090 if (local_err) {
2091 error_propagate(errp, local_err);
c6dc6f63 2092 }
c6dc6f63
AP		 2093}
2094
b54c9377
EH		 2095static void x86_cpu_load_features(X86CPU *cpu, Error **errp);
2096static int x86_cpu_filter_features(X86CPU *cpu);
2097
2098/* Check for missing features that may prevent the CPU class from
2099 * running using the current machine and accelerator.
2100 */
2101static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
2102 strList **missing_feats)
2103{
2104 X86CPU *xc;
2105 FeatureWord w;
2106 Error *err = NULL;
2107 strList **next = missing_feats;
2108
2109 if (xcc->kvm_required && !kvm_enabled()) {
2110 strList *new = g_new0(strList, 1);
2111 new->value = g_strdup("kvm");;
2112 *missing_feats = new;
2113 return;
2114 }
2115
2116 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2117
2118 x86_cpu_load_features(xc, &err);
2119 if (err) {
2120 /* Errors at x86_cpu_load_features should never happen,
2121 * but in case it does, just report the model as not
2122 * runnable at all using the "type" property.
2123 */
2124 strList *new = g_new0(strList, 1);
2125 new->value = g_strdup("type");
2126 *next = new;
2127 next = &new->next;
2128 }
2129
2130 x86_cpu_filter_features(xc);
2131
2132 for (w = 0; w < FEATURE_WORDS; w++) {
2133 uint32_t filtered = xc->filtered_features[w];
2134 int i;
2135 for (i = 0; i < 32; i++) {
2136 if (filtered & (1UL << i)) {
2137 strList *new = g_new0(strList, 1);
2138 new->value = g_strdup(x86_cpu_feature_name(w, i));
2139 *next = new;
2140 next = &new->next;
2141 }
2142 }
2143 }
2144
2145 object_unref(OBJECT(xc));
2146}
2147
8c3329e5 2148/* Print all cpuid feature names in featureset
c6dc6f63 2149 */
8c3329e5 2150static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2151{
8c3329e5
EH		 2152 int bit;
2153 bool first = true;
2154
2155 for (bit = 0; bit < 32; bit++) {
2156 if (featureset[bit]) {
2157 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2158 first = false;
c6dc6f63 2159 }
8c3329e5 2160 }
c6dc6f63
AP		 2161}
2162
ee465a3e
EH		 2163/* Sort alphabetically by type name, listing kvm_required models last. */
2164static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
2165{
2166 ObjectClass *class_a = (ObjectClass *)a;
2167 ObjectClass *class_b = (ObjectClass *)b;
2168 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
2169 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
2170 const char *name_a, *name_b;
2171
2172 if (cc_a->kvm_required != cc_b->kvm_required) {
2173 /* kvm_required items go last */
2174 return cc_a->kvm_required ? 1 : -1;
2175 } else {
2176 name_a = object_class_get_name(class_a);
2177 name_b = object_class_get_name(class_b);
2178 return strcmp(name_a, name_b);
2179 }
2180}
2181
2182static GSList *get_sorted_cpu_model_list(void)
2183{
2184 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
2185 list = g_slist_sort(list, x86_cpu_list_compare);
2186 return list;
2187}
2188
2189static void x86_cpu_list_entry(gpointer data, gpointer user_data)
2190{
2191 ObjectClass *oc = data;
2192 X86CPUClass *cc = X86_CPU_CLASS(oc);
2193 CPUListState *s = user_data;
2194 char *name = x86_cpu_class_get_model_name(cc);
2195 const char *desc = cc->model_description;
2196 if (!desc) {
2197 desc = cc->cpu_def->model_id;
2198 }
2199
2200 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
2201 name, desc);
2202 g_free(name);
2203}
2204
2205/* list available CPU models and flags */
e916cbf8 2206void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2207{
7fc9b714 2208 int i;
ee465a3e
EH		 2209 CPUListState s = {
2210 .file = f,
2211 .cpu_fprintf = cpu_fprintf,
2212 };
2213 GSList *list;
c6dc6f63 2214
ee465a3e
EH		 2215 (*cpu_fprintf)(f, "Available CPUs:\n");
2216 list = get_sorted_cpu_model_list();
2217 g_slist_foreach(list, x86_cpu_list_entry, &s);
2218 g_slist_free(list);
21ad7789 2219
6cdf8854 2220 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2221 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2222 FeatureWordInfo *fw = &feature_word_info[i];
2223
8c3329e5
EH		 2224 (*cpu_fprintf)(f, " ");
2225 listflags(f, cpu_fprintf, fw->feat_names);
2226 (*cpu_fprintf)(f, "\n");
3af60be2 2227 }
c6dc6f63
AP		 2228}
2229
ee465a3e
EH		 2230static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
2231{
2232 ObjectClass *oc = data;
2233 X86CPUClass *cc = X86_CPU_CLASS(oc);
2234 CpuDefinitionInfoList **cpu_list = user_data;
2235 CpuDefinitionInfoList *entry;
2236 CpuDefinitionInfo *info;
2237
2238 info = g_malloc0(sizeof(*info));
2239 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 2240 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
2241 info->has_unavailable_features = true;
ee465a3e
EH		 2242
2243 entry = g_malloc0(sizeof(*entry));
2244 entry->value = info;
2245 entry->next = *cpu_list;
2246 *cpu_list = entry;
2247}
2248
76b64a7a 2249CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2250{
2251 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 2252 GSList *list = get_sorted_cpu_model_list();
2253 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
2254 g_slist_free(list);
e3966126
AL		 2255 return cpu_list;
2256}
2257
84f1b92f
EH		 2258static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2259 bool migratable_only)
27418adf
EH		 2260{
2261 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2262 uint32_t r;
27418adf 2263
fefb41bf 2264 if (kvm_enabled()) {
84f1b92f
EH		 2265 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2266 wi->cpuid_ecx,
2267 wi->cpuid_reg);
fefb41bf 2268 } else if (tcg_enabled()) {
84f1b92f 2269 r = wi->tcg_features;
fefb41bf
EH		 2270 } else {
2271 return ~0;
2272 }
84f1b92f
EH		 2273 if (migratable_only) {
2274 r &= x86_cpu_get_migratable_flags(w);
2275 }
2276 return r;
27418adf
EH		 2277}
2278
51f63aed
EH		 2279/*
2280 * Filters CPU feature words based on host availability of each feature.
2281 *
51f63aed
EH		 2282 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2283 */
27418adf 2284static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2285{
2286 CPUX86State *env = &cpu->env;
bd87d2a2 2287 FeatureWord w;
51f63aed
EH		 2288 int rv = 0;
2289
bd87d2a2 2290 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f 2291 uint32_t host_feat =
46c032f3 2292 x86_cpu_get_supported_feature_word(w, false);
034acf4a
EH		 2293 uint32_t requested_features = env->features[w];
2294 env->features[w] &= host_feat;
2295 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed 2296 if (cpu->filtered_features[w]) {
51f63aed
EH		 2297 rv = 1;
2298 }
bd87d2a2 2299 }
51f63aed
EH		 2300
2301 return rv;
bc74b7db 2302}
bc74b7db 2303
8ca30e86
EH		 2304static void x86_cpu_report_filtered_features(X86CPU *cpu)
2305{
2306 FeatureWord w;
2307
2308 for (w = 0; w < FEATURE_WORDS; w++) {
2309 report_unavailable_features(w, cpu->filtered_features[w]);
2310 }
2311}
2312
5114e842
EH		 2313static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2314{
2315 PropValue *pv;
2316 for (pv = props; pv->prop; pv++) {
2317 if (!pv->value) {
2318 continue;
2319 }
2320 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2321 &error_abort);
2322 }
2323}
2324
d940ee9b 2325/* Load data from X86CPUDefinition
c080e30e 2326 */
d940ee9b 2327static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2328{
61dcd775 2329 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2330 const char *vendor;
2331 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2332 FeatureWord w;
c6dc6f63 2333
c39c0edf
EH		 2334 /* CPU models only set _minimum_ values for level/xlevel: */
2335 object_property_set_int(OBJECT(cpu), def->level, "min-level", errp);
2336 object_property_set_int(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
2337
2d64255b
AF		 2338 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2339 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2340 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2341 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2342 for (w = 0; w < FEATURE_WORDS; w++) {
2343 env->features[w] = def->features[w];
2344 }
82beb536 2345
9576de75 2346 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2347 if (kvm_enabled()) {
492a4c94
LT		 2348 if (!kvm_irqchip_in_kernel()) {
2349 x86_cpu_change_kvm_default("x2apic", "off");
2350 }
2351
5114e842 2352 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 2353 } else if (tcg_enabled()) {
2354 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 2355 }
5fcca9ff 2356
82beb536 2357 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2358
2359 /* sysenter isn't supported in compatibility mode on AMD,
2360 * syscall isn't supported in compatibility mode on Intel.
2361 * Normally we advertise the actual CPU vendor, but you can
2362 * override this using the 'vendor' property if you want to use
2363 * KVM's sysenter/syscall emulation in compatibility mode and
2364 * when doing cross vendor migration
2365 */
74f54bc4 2366 vendor = def->vendor;
7c08db30
EH		 2367 if (kvm_enabled()) {
2368 uint32_t ebx = 0, ecx = 0, edx = 0;
2369 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2370 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2371 vendor = host_vendor;
2372 }
2373
2374 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2375
c6dc6f63
AP		 2376}
2377
0856579c 2378X86CPU *cpu_x86_init(const char *cpu_model)
7f833247 2379{
a57d0163 2380 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
5c3c6a68
AF		 2381}
2382
d940ee9b
EH		 2383static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2384{
2385 X86CPUDefinition *cpudef = data;
2386 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2387
2388 xcc->cpu_def = cpudef;
2389}
2390
2391static void x86_register_cpudef_type(X86CPUDefinition *def)
2392{
2393 char *typename = x86_cpu_type_name(def->name);
2394 TypeInfo ti = {
2395 .name = typename,
2396 .parent = TYPE_X86_CPU,
2397 .class_init = x86_cpu_cpudef_class_init,
2398 .class_data = def,
2399 };
2400
2401 type_register(&ti);
2402 g_free(typename);
2403}
2404
c6dc6f63 2405#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2406
0e26b7b8
BS		 2407void cpu_clear_apic_feature(CPUX86State *env)
2408{
0514ef2f 2409 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2410}
2411
c6dc6f63
AP		 2412#endif /* !CONFIG_USER_ONLY */
2413
c6dc6f63
AP		 2414void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2415 uint32_t *eax, uint32_t *ebx,
2416 uint32_t *ecx, uint32_t *edx)
2417{
a60f24b5
AF		 2418 X86CPU *cpu = x86_env_get_cpu(env);
2419 CPUState *cs = CPU(cpu);
14c985cf 2420 uint32_t pkg_offset;
a60f24b5 2421
c6dc6f63
AP		 2422 /* test if maximum index reached */
2423 if (index & 0x80000000) {
b3baa152
BW		 2424 if (index > env->cpuid_xlevel) {
2425 if (env->cpuid_xlevel2 > 0) {
2426 /* Handle the Centaur's CPUID instruction. */
2427 if (index > env->cpuid_xlevel2) {
2428 index = env->cpuid_xlevel2;
2429 } else if (index < 0xC0000000) {
2430 index = env->cpuid_xlevel;
2431 }
2432 } else {
57f26ae7
EH		 2433 /* Intel documentation states that invalid EAX input will
2434 * return the same information as EAX=cpuid_level
2435 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2436 */
2437 index = env->cpuid_level;
b3baa152
BW		 2438 }
2439 }
c6dc6f63
AP		 2440 } else {
2441 if (index > env->cpuid_level)
2442 index = env->cpuid_level;
2443 }
2444
2445 switch(index) {
2446 case 0:
2447 *eax = env->cpuid_level;
5eb2f7a4
EH		 2448 *ebx = env->cpuid_vendor1;
2449 *edx = env->cpuid_vendor2;
2450 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2451 break;
2452 case 1:
2453 *eax = env->cpuid_version;
7e72a45c
EH		 2454 *ebx = (cpu->apic_id << 24) |
2455 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2456 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2457 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2458 *ecx |= CPUID_EXT_OSXSAVE;
2459 }
0514ef2f 2460 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2461 if (cs->nr_cores * cs->nr_threads > 1) {
2462 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2463 *edx |= CPUID_HT;
c6dc6f63
AP		 2464 }
2465 break;
2466 case 2:
2467 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2468 if (cpu->cache_info_passthrough) {
2469 host_cpuid(index, 0, eax, ebx, ecx, edx);
2470 break;
2471 }
5e891bf8 2472 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 2473 *ebx = 0;
14c985cf
LM		 2474 if (!cpu->enable_l3_cache) {
2475 *ecx = 0;
2476 } else {
2477 *ecx = L3_N_DESCRIPTOR;
2478 }
5e891bf8
EH		 2479 *edx = (L1D_DESCRIPTOR << 16) | \
2480 (L1I_DESCRIPTOR << 8) | \
2481 (L2_DESCRIPTOR);
c6dc6f63
AP		 2482 break;
2483 case 4:
2484 /* cache info: needed for Core compatibility */
787aaf57
BC		 2485 if (cpu->cache_info_passthrough) {
2486 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2487 *eax &= ~0xFC000000;
c6dc6f63 2488 } else {
2f7a21c4 2489 *eax = 0;
76c2975a 2490 switch (count) {
c6dc6f63 2491 case 0: /* L1 dcache info */
5e891bf8
EH		 2492 *eax |= CPUID_4_TYPE_DCACHE | \
2493 CPUID_4_LEVEL(1) | \
2494 CPUID_4_SELF_INIT_LEVEL;
2495 *ebx = (L1D_LINE_SIZE - 1) | \
2496 ((L1D_PARTITIONS - 1) << 12) | \
2497 ((L1D_ASSOCIATIVITY - 1) << 22);
2498 *ecx = L1D_SETS - 1;
2499 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2500 break;
2501 case 1: /* L1 icache info */
5e891bf8
EH		 2502 *eax |= CPUID_4_TYPE_ICACHE | \
2503 CPUID_4_LEVEL(1) | \
2504 CPUID_4_SELF_INIT_LEVEL;
2505 *ebx = (L1I_LINE_SIZE - 1) | \
2506 ((L1I_PARTITIONS - 1) << 12) | \
2507 ((L1I_ASSOCIATIVITY - 1) << 22);
2508 *ecx = L1I_SETS - 1;
2509 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2510 break;
2511 case 2: /* L2 cache info */
5e891bf8
EH		 2512 *eax |= CPUID_4_TYPE_UNIFIED | \
2513 CPUID_4_LEVEL(2) | \
2514 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2515 if (cs->nr_threads > 1) {
2516 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2517 }
5e891bf8
EH		 2518 *ebx = (L2_LINE_SIZE - 1) | \
2519 ((L2_PARTITIONS - 1) << 12) | \
2520 ((L2_ASSOCIATIVITY - 1) << 22);
2521 *ecx = L2_SETS - 1;
2522 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63 2523 break;
14c985cf
LM		 2524 case 3: /* L3 cache info */
2525 if (!cpu->enable_l3_cache) {
2526 *eax = 0;
2527 *ebx = 0;
2528 *ecx = 0;
2529 *edx = 0;
2530 break;
2531 }
2532 *eax |= CPUID_4_TYPE_UNIFIED | \
2533 CPUID_4_LEVEL(3) | \
2534 CPUID_4_SELF_INIT_LEVEL;
2535 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2536 *eax |= ((1 << pkg_offset) - 1) << 14;
2537 *ebx = (L3_N_LINE_SIZE - 1) | \
2538 ((L3_N_PARTITIONS - 1) << 12) | \
2539 ((L3_N_ASSOCIATIVITY - 1) << 22);
2540 *ecx = L3_N_SETS - 1;
2541 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2542 break;
c6dc6f63
AP		 2543 default: /* end of info */
2544 *eax = 0;
2545 *ebx = 0;
2546 *ecx = 0;
2547 *edx = 0;
2548 break;
76c2975a
PB		 2549 }
2550 }
2551
2552 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2553 if ((*eax & 31) && cs->nr_cores > 1) {
2554 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2555 }
2556 break;
2557 case 5:
2558 /* mwait info: needed for Core compatibility */
2559 *eax = 0; /* Smallest monitor-line size in bytes */
2560 *ebx = 0; /* Largest monitor-line size in bytes */
2561 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2562 *edx = 0;
2563 break;
2564 case 6:
2565 /* Thermal and Power Leaf */
28b8e4d0 2566 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2567 *ebx = 0;
2568 *ecx = 0;
2569 *edx = 0;
2570 break;
f7911686 2571 case 7:
13526728
EH		 2572 /* Structured Extended Feature Flags Enumeration Leaf */
2573 if (count == 0) {
2574 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2575 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2576 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2577 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2578 *ecx |= CPUID_7_0_ECX_OSPKE;
2579 }
95ea69fb 2580 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 2581 } else {
2582 *eax = 0;
2583 *ebx = 0;
2584 *ecx = 0;
2585 *edx = 0;
2586 }
2587 break;
c6dc6f63
AP		 2588 case 9:
2589 /* Direct Cache Access Information Leaf */
2590 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2591 *ebx = 0;
2592 *ecx = 0;
2593 *edx = 0;
2594 break;
2595 case 0xA:
2596 /* Architectural Performance Monitoring Leaf */
9337e3b6 2597 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2598 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2599
2600 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2601 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2602 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2603 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2604 } else {
2605 *eax = 0;
2606 *ebx = 0;
2607 *ecx = 0;
2608 *edx = 0;
2609 }
c6dc6f63 2610 break;
5232d00a
RK		 2611 case 0xB:
2612 /* Extended Topology Enumeration Leaf */
2613 if (!cpu->enable_cpuid_0xb) {
2614 *eax = *ebx = *ecx = *edx = 0;
2615 break;
2616 }
2617
2618 *ecx = count & 0xff;
2619 *edx = cpu->apic_id;
2620
2621 switch (count) {
2622 case 0:
eab60fb9
MAL		 2623 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
2624 *ebx = cs->nr_threads;
5232d00a
RK		 2625 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2626 break;
2627 case 1:
eab60fb9
MAL		 2628 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2629 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 2630 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2631 break;
2632 default:
2633 *eax = 0;
2634 *ebx = 0;
2635 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2636 }
2637
2638 assert(!(*eax & ~0x1f));
2639 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2640 break;
2560f19f 2641 case 0xD: {
51e49430 2642 /* Processor Extended State */
2560f19f
PB		 2643 *eax = 0;
2644 *ebx = 0;
2645 *ecx = 0;
2646 *edx = 0;
19dc85db 2647 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2648 break;
2649 }
4928cd6d 2650
2560f19f 2651 if (count == 0) {
96193c22
EH		 2652 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
2653 *eax = env->features[FEAT_XSAVE_COMP_LO];
2654 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 2655 *ebx = *ecx;
2656 } else if (count == 1) {
0bb0b2d2 2657 *eax = env->features[FEAT_XSAVE];
f4f1110e 2658 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 2659 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
2660 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 2661 *eax = esa->size;
2662 *ebx = esa->offset;
2560f19f 2663 }
51e49430
SY		 2664 }
2665 break;
2560f19f 2666 }
c6dc6f63
AP		 2667 case 0x80000000:
2668 *eax = env->cpuid_xlevel;
2669 *ebx = env->cpuid_vendor1;
2670 *edx = env->cpuid_vendor2;
2671 *ecx = env->cpuid_vendor3;
2672 break;
2673 case 0x80000001:
2674 *eax = env->cpuid_version;
2675 *ebx = 0;
0514ef2f
EH		 2676 *ecx = env->features[FEAT_8000_0001_ECX];
2677 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2678
2679 /* The Linux kernel checks for the CMPLegacy bit and
2680 * discards multiple thread information if it is set.
cb8d4c8f 2681 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2682 */
ce3960eb 2683 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2684 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2685 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2686 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2687 *ecx |= 1 << 1; /* CmpLegacy bit */
2688 }
2689 }
c6dc6f63
AP		 2690 break;
2691 case 0x80000002:
2692 case 0x80000003:
2693 case 0x80000004:
2694 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2695 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2696 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2697 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2698 break;
2699 case 0x80000005:
2700 /* cache info (L1 cache) */
787aaf57
BC		 2701 if (cpu->cache_info_passthrough) {
2702 host_cpuid(index, 0, eax, ebx, ecx, edx);
2703 break;
2704 }
5e891bf8
EH		 2705 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2706 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2707 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2708 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2709 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2710 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2711 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2712 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2713 break;
2714 case 0x80000006:
2715 /* cache info (L2 cache) */
787aaf57
BC		 2716 if (cpu->cache_info_passthrough) {
2717 host_cpuid(index, 0, eax, ebx, ecx, edx);
2718 break;
2719 }
5e891bf8
EH		 2720 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2721 (L2_DTLB_2M_ENTRIES << 16) | \
2722 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2723 (L2_ITLB_2M_ENTRIES);
2724 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2725 (L2_DTLB_4K_ENTRIES << 16) | \
2726 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2727 (L2_ITLB_4K_ENTRIES);
2728 *ecx = (L2_SIZE_KB_AMD << 16) | \
2729 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2730 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
14c985cf
LM		 2731 if (!cpu->enable_l3_cache) {
2732 *edx = ((L3_SIZE_KB / 512) << 18) | \
2733 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2734 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2735 } else {
2736 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
2737 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
2738 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
2739 }
c6dc6f63 2740 break;
303752a9
MT		 2741 case 0x80000007:
2742 *eax = 0;
2743 *ebx = 0;
2744 *ecx = 0;
2745 *edx = env->features[FEAT_8000_0007_EDX];
2746 break;
c6dc6f63
AP		 2747 case 0x80000008:
2748 /* virtual & phys address size in low 2 bytes. */
0514ef2f 2749 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a
DDAG		 2750 /* 64 bit processor, 48 bits virtual, configurable
2751 * physical bits.
2752 */
2753 *eax = 0x00003000 + cpu->phys_bits;
c6dc6f63 2754 } else {
af45907a 2755 *eax = cpu->phys_bits;
c6dc6f63
AP		 2756 }
2757 *ebx = 0;
2758 *ecx = 0;
2759 *edx = 0;
ce3960eb
AF		 2760 if (cs->nr_cores * cs->nr_threads > 1) {
2761 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2762 }
2763 break;
2764 case 0x8000000A:
0514ef2f 2765 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2766 *eax = 0x00000001; /* SVM Revision */
2767 *ebx = 0x00000010; /* nr of ASIDs */
2768 *ecx = 0;
0514ef2f 2769 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2770 } else {
2771 *eax = 0;
2772 *ebx = 0;
2773 *ecx = 0;
2774 *edx = 0;
2775 }
c6dc6f63 2776 break;
b3baa152
BW		 2777 case 0xC0000000:
2778 *eax = env->cpuid_xlevel2;
2779 *ebx = 0;
2780 *ecx = 0;
2781 *edx = 0;
2782 break;
2783 case 0xC0000001:
2784 /* Support for VIA CPU's CPUID instruction */
2785 *eax = env->cpuid_version;
2786 *ebx = 0;
2787 *ecx = 0;
0514ef2f 2788 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2789 break;
2790 case 0xC0000002:
2791 case 0xC0000003:
2792 case 0xC0000004:
2793 /* Reserved for the future, and now filled with zero */
2794 *eax = 0;
2795 *ebx = 0;
2796 *ecx = 0;
2797 *edx = 0;
2798 break;
c6dc6f63
AP		 2799 default:
2800 /* reserved values: zero */
2801 *eax = 0;
2802 *ebx = 0;
2803 *ecx = 0;
2804 *edx = 0;
2805 break;
2806 }
2807}
5fd2087a
AF		 2808
2809/* CPUClass::reset() */
2810static void x86_cpu_reset(CPUState *s)
2811{
2812 X86CPU *cpu = X86_CPU(s);
2813 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2814 CPUX86State *env = &cpu->env;
a114d25d
RH		 2815 target_ulong cr4;
2816 uint64_t xcr0;
c1958aea
AF		 2817 int i;
2818
5fd2087a
AF		 2819 xcc->parent_reset(s);
2820
5e992a8e 2821 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 2822
00c8cb0a 2823 tlb_flush(s, 1);
c1958aea
AF		 2824
2825 env->old_exception = -1;
2826
2827 /* init to reset state */
2828
c1958aea
AF		 2829 env->hflags2 |= HF2_GIF_MASK;
2830
2831 cpu_x86_update_cr0(env, 0x60000010);
2832 env->a20_mask = ~0x0;
2833 env->smbase = 0x30000;
2834
2835 env->idt.limit = 0xffff;
2836 env->gdt.limit = 0xffff;
2837 env->ldt.limit = 0xffff;
2838 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2839 env->tr.limit = 0xffff;
2840 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2841
2842 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2843 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2844 DESC_R_MASK | DESC_A_MASK);
2845 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2846 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2847 DESC_A_MASK);
2848 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2849 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2850 DESC_A_MASK);
2851 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2852 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2853 DESC_A_MASK);
2854 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2855 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2856 DESC_A_MASK);
2857 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2858 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2859 DESC_A_MASK);
2860
2861 env->eip = 0xfff0;
2862 env->regs[R_EDX] = env->cpuid_version;
2863
2864 env->eflags = 0x2;
2865
2866 /* FPU init */
2867 for (i = 0; i < 8; i++) {
2868 env->fptags[i] = 1;
2869 }
5bde1407 2870 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2871
2872 env->mxcsr = 0x1f80;
a114d25d
RH		 2873 /* All units are in INIT state. */
2874 env->xstate_bv = 0;
c1958aea
AF		 2875
2876 env->pat = 0x0007040600070406ULL;
2877 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2878
2879 memset(env->dr, 0, sizeof(env->dr));
2880 env->dr[6] = DR6_FIXED_1;
2881 env->dr[7] = DR7_FIXED_1;
b3310ab3 2882 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2883 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2884
a114d25d 2885 cr4 = 0;
cfc3b074 2886 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 2887
2888#ifdef CONFIG_USER_ONLY
2889 /* Enable all the features for user-mode. */
2890 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 2891 xcr0 |= XSTATE_SSE_MASK;
a114d25d 2892 }
0f70ed47
PB		 2893 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2894 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 2895 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 2896 xcr0 |= 1ull << i;
2897 }
a114d25d 2898 }
0f70ed47 2899
a114d25d
RH		 2900 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2901 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2902 }
07929f2a
RH		 2903 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2904 cr4 |= CR4_FSGSBASE_MASK;
2905 }
a114d25d
RH		 2906#endif
2907
2908 env->xcr0 = xcr0;
2909 cpu_x86_update_cr4(env, cr4);
0522604b 2910
9db2efd9
AW		 2911 /*
2912 * SDM 11.11.5 requires:
2913 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2914 * - IA32_MTRR_PHYSMASKn.V = 0
2915 * All other bits are undefined. For simplification, zero it all.
2916 */
2917 env->mtrr_deftype = 0;
2918 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2919 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2920
dd673288
IM		 2921#if !defined(CONFIG_USER_ONLY)
2922 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2923 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2924
259186a7 2925 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2926
2927 if (kvm_enabled()) {
2928 kvm_arch_reset_vcpu(cpu);
2929 }
dd673288 2930#endif
5fd2087a
AF		 2931}
2932
dd673288
IM		 2933#ifndef CONFIG_USER_ONLY
2934bool cpu_is_bsp(X86CPU *cpu)
2935{
02e51483 2936 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2937}
65dee380
IM		 2938
2939/* TODO: remove me, when reset over QOM tree is implemented */
2940static void x86_cpu_machine_reset_cb(void *opaque)
2941{
2942 X86CPU *cpu = opaque;
2943 cpu_reset(CPU(cpu));
2944}
dd673288
IM		 2945#endif
2946
de024815
AF		 2947static void mce_init(X86CPU *cpu)
2948{
2949 CPUX86State *cenv = &cpu->env;
2950 unsigned int bank;
2951
2952 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2953 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 2954 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 2955 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
2956 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 2957 cenv->mcg_ctl = ~(uint64_t)0;
2958 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2959 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2960 }
2961 }
2962}
2963
bdeec802 2964#ifndef CONFIG_USER_ONLY
2f114315 2965APICCommonClass *apic_get_class(void)
bdeec802 2966{
bdeec802
IM		 2967 const char *apic_type = "apic";
2968
15eafc2e 2969 if (kvm_apic_in_kernel()) {
bdeec802
IM		 2970 apic_type = "kvm-apic";
2971 } else if (xen_enabled()) {
2972 apic_type = "xen-apic";
2973 }
2974
2f114315
RK		 2975 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
2976}
2977
2978static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2979{
2980 APICCommonState *apic;
2981 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
2982
2983 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 2984
6816b1b3
IM		 2985 object_property_add_child(OBJECT(cpu), "lapic",
2986 OBJECT(cpu->apic_state), &error_abort);
67e55caa 2987 object_unref(OBJECT(cpu->apic_state));
6816b1b3 2988
33d7a288 2989 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2990 /* TODO: convert to link<> */
02e51483 2991 apic = APIC_COMMON(cpu->apic_state);
60671e58 2992 apic->cpu = cpu;
8d42d2d3 2993 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 2994}
2995
2996static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2997{
8d42d2d3
CF		 2998 APICCommonState *apic;
2999 static bool apic_mmio_map_once;
3000
02e51483 3001 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 3002 return;
3003 }
6e8e2651
MA		 3004 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
3005 errp);
8d42d2d3
CF		 3006
3007 /* Map APIC MMIO area */
3008 apic = APIC_COMMON(cpu->apic_state);
3009 if (!apic_mmio_map_once) {
3010 memory_region_add_subregion_overlap(get_system_memory(),
3011 apic->apicbase &
3012 MSR_IA32_APICBASE_BASE,
3013 &apic->io_memory,
3014 0x1000);
3015 apic_mmio_map_once = true;
3016 }
bdeec802 3017}
f809c605
PB		 3018
3019static void x86_cpu_machine_done(Notifier *n, void *unused)
3020{
3021 X86CPU *cpu = container_of(n, X86CPU, machine_done);
3022 MemoryRegion *smram =
3023 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
3024
3025 if (smram) {
3026 cpu->smram = g_new(MemoryRegion, 1);
3027 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
3028 smram, 0, 1ull << 32);
3029 memory_region_set_enabled(cpu->smram, false);
3030 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
3031 }
3032}
d3c64d6a
IM		 3033#else
3034static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3035{
3036}
bdeec802
IM		 3037#endif
3038
11f6fee5
DDAG		 3039/* Note: Only safe for use on x86(-64) hosts */
3040static uint32_t x86_host_phys_bits(void)
3041{
3042 uint32_t eax;
3043 uint32_t host_phys_bits;
3044
3045 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
3046 if (eax >= 0x80000008) {
3047 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
3048 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3049 * at 23:16 that can specify a maximum physical address bits for
3050 * the guest that can override this value; but I've not seen
3051 * anything with that set.
3052 */
3053 host_phys_bits = eax & 0xff;
3054 } else {
3055 /* It's an odd 64 bit machine that doesn't have the leaf for
3056 * physical address bits; fall back to 36 that's most older
3057 * Intel.
3058 */
3059 host_phys_bits = 36;
3060 }
3061
3062 return host_phys_bits;
3063}
e48638fd 3064
c39c0edf
EH		 3065static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
3066{
3067 if (*min < value) {
3068 *min = value;
3069 }
3070}
3071
3072/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3073static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
3074{
3075 CPUX86State *env = &cpu->env;
3076 FeatureWordInfo *fi = &feature_word_info[w];
3077 uint32_t eax = fi->cpuid_eax;
3078 uint32_t region = eax & 0xF0000000;
3079
3080 if (!env->features[w]) {
3081 return;
3082 }
3083
3084 switch (region) {
3085 case 0x00000000:
3086 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
3087 break;
3088 case 0x80000000:
3089 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
3090 break;
3091 case 0xC0000000:
3092 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
3093 break;
3094 }
3095}
3096
2ca8a8be
EH		 3097/* Calculate XSAVE components based on the configured CPU feature flags */
3098static void x86_cpu_enable_xsave_components(X86CPU *cpu)
3099{
3100 CPUX86State *env = &cpu->env;
3101 int i;
96193c22 3102 uint64_t mask;
2ca8a8be
EH		 3103
3104 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
3105 return;
3106 }
3107
e3c9022b
EH		 3108 mask = 0;
3109 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 3110 const ExtSaveArea *esa = &x86_ext_save_areas[i];
3111 if (env->features[esa->feature] & esa->bits) {
96193c22 3112 mask |= (1ULL << i);
2ca8a8be
EH		 3113 }
3114 }
3115
96193c22
EH		 3116 env->features[FEAT_XSAVE_COMP_LO] = mask;
3117 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 3118}
3119
41f3d4d6
EH		 3120/* Load CPUID data based on configured features */
3121static void x86_cpu_load_features(X86CPU *cpu, Error **errp)
7a059953 3122{
b34d12d1 3123 CPUX86State *env = &cpu->env;
dc15c051 3124 FeatureWord w;
2fae0d96 3125 GList *l;
41f3d4d6 3126 Error *local_err = NULL;
9886e834 3127
dc15c051
IM		 3128 /*TODO: cpu->host_features incorrectly overwrites features
3129 * set using "feat=on|off". Once we fix this, we can convert
3130 * plus_features & minus_features to global properties
3131 * inside x86_cpu_parse_featurestr() too.
3132 */
3133 if (cpu->host_features) {
3134 for (w = 0; w < FEATURE_WORDS; w++) {
3135 env->features[w] =
3136 x86_cpu_get_supported_feature_word(w, cpu->migratable);
3137 }
3138 }
3139
2fae0d96
EH		 3140 for (l = plus_features; l; l = l->next) {
3141 const char *prop = l->data;
3142 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
3143 if (local_err) {
3144 goto out;
3145 }
3146 }
3147
3148 for (l = minus_features; l; l = l->next) {
3149 const char *prop = l->data;
3150 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
3151 if (local_err) {
3152 goto out;
3153 }
dc15c051
IM		 3154 }
3155
aec661de
EH		 3156 if (!kvm_enabled() || !cpu->expose_kvm) {
3157 env->features[FEAT_KVM] = 0;
3158 }
3159
2ca8a8be 3160 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 3161
3162 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3163 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
3164 if (cpu->full_cpuid_auto_level) {
3165 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
3166 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
3167 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
3168 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
3169 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
3170 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
3171 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
3172 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
3173 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
3174 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 3175 /* SVM requires CPUID[0x8000000A] */
3176 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
3177 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
3178 }
c39c0edf
EH		 3179 }
3180
3181 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3182 if (env->cpuid_level == UINT32_MAX) {
3183 env->cpuid_level = env->cpuid_min_level;
3184 }
3185 if (env->cpuid_xlevel == UINT32_MAX) {
3186 env->cpuid_xlevel = env->cpuid_min_xlevel;
3187 }
3188 if (env->cpuid_xlevel2 == UINT32_MAX) {
3189 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 3190 }
7a059953 3191
41f3d4d6
EH		 3192out:
3193 if (local_err != NULL) {
3194 error_propagate(errp, local_err);
3195 }
3196}
3197
3198#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3199 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3200 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3201#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3202 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3203 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
3204static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
3205{
3206 CPUState *cs = CPU(dev);
3207 X86CPU *cpu = X86_CPU(dev);
3208 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3209 CPUX86State *env = &cpu->env;
3210 Error *local_err = NULL;
3211 static bool ht_warned;
3212
3213 if (xcc->kvm_required && !kvm_enabled()) {
3214 char *name = x86_cpu_class_get_model_name(xcc);
3215 error_setg(&local_err, "CPU model '%s' requires KVM", name);
3216 g_free(name);
3217 goto out;
3218 }
3219
3220 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
3221 error_setg(errp, "apic-id property was not initialized properly");
3222 return;
3223 }
3224
3225 x86_cpu_load_features(cpu, &local_err);
3226 if (local_err) {
3227 goto out;
3228 }
3229
8ca30e86
EH		 3230 if (x86_cpu_filter_features(cpu) &&
3231 (cpu->check_cpuid || cpu->enforce_cpuid)) {
3232 x86_cpu_report_filtered_features(cpu);
3233 if (cpu->enforce_cpuid) {
3234 error_setg(&local_err,
3235 kvm_enabled() ?
3236 "Host doesn't support requested features" :
3237 "TCG doesn't support requested features");
3238 goto out;
3239 }
9997cf7b
EH		 3240 }
3241
9b15cd9e
IM		 3242 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3243 * CPUID[1].EDX.
3244 */
e48638fd 3245 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 3246 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3247 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 3248 & CPUID_EXT2_AMD_ALIASES);
3249 }
3250
11f6fee5
DDAG		 3251 /* For 64bit systems think about the number of physical bits to present.
3252 * ideally this should be the same as the host; anything other than matching
3253 * the host can cause incorrect guest behaviour.
3254 * QEMU used to pick the magic value of 40 bits that corresponds to
3255 * consumer AMD devices but nothing else.
3256 */
af45907a 3257 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a 3258 if (kvm_enabled()) {
11f6fee5
DDAG		 3259 uint32_t host_phys_bits = x86_host_phys_bits();
3260 static bool warned;
3261
3262 if (cpu->host_phys_bits) {
3263 /* The user asked for us to use the host physical bits */
3264 cpu->phys_bits = host_phys_bits;
3265 }
3266
3267 /* Print a warning if the user set it to a value that's not the
3268 * host value.
3269 */
3270 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3271 !warned) {
3272 error_report("Warning: Host physical bits (%u)"
3273 " does not match phys-bits property (%u)",
3274 host_phys_bits, cpu->phys_bits);
3275 warned = true;
3276 }
3277
3278 if (cpu->phys_bits &&
3279 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3280 cpu->phys_bits < 32)) {
af45907a
DDAG		 3281 error_setg(errp, "phys-bits should be between 32 and %u "
3282 " (but is %u)",
3283 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3284 return;
3285 }
3286 } else {
11f6fee5 3287 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 3288 error_setg(errp, "TCG only supports phys-bits=%u",
3289 TCG_PHYS_ADDR_BITS);
3290 return;
3291 }
3292 }
11f6fee5
DDAG		 3293 /* 0 means it was not explicitly set by the user (or by machine
3294 * compat_props or by the host code above). In this case, the default
3295 * is the value used by TCG (40).
3296 */
3297 if (cpu->phys_bits == 0) {
3298 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3299 }
af45907a
DDAG		 3300 } else {
3301 /* For 32 bit systems don't use the user set value, but keep
3302 * phys_bits consistent with what we tell the guest.
3303 */
3304 if (cpu->phys_bits != 0) {
3305 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3306 return;
3307 }
fefb41bf 3308
af45907a
DDAG		 3309 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3310 cpu->phys_bits = 36;
3311 } else {
3312 cpu->phys_bits = 32;
3313 }
3314 }
ce5b1bbf
LV		 3315 cpu_exec_realizefn(cs, &local_err);
3316 if (local_err != NULL) {
3317 error_propagate(errp, local_err);
3318 return;
3319 }
42ecabaa 3320
57f2453a
EH		 3321 if (tcg_enabled()) {
3322 tcg_x86_init();
3323 }
3324
65dee380
IM		 3325#ifndef CONFIG_USER_ONLY
3326 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 3327
0514ef2f 3328 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 3329 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 3330 if (local_err != NULL) {
4dc1f449 3331 goto out;
bdeec802
IM		 3332 }
3333 }
65dee380
IM		 3334#endif
3335
7a059953 3336 mce_init(cpu);
2001d0cd
PB		 3337
3338#ifndef CONFIG_USER_ONLY
3339 if (tcg_enabled()) {
56943e8c
PM		 3340 AddressSpace *newas = g_new(AddressSpace, 1);
3341
f809c605 3342 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 3343 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 3344
3345 /* Outer container... */
3346 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 3347 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 3348
3349 /* ... with two regions inside: normal system memory with low
3350 * priority, and...
3351 */
3352 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3353 get_system_memory(), 0, ~0ull);
3354 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3355 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 3356 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 3357 cs->num_ases = 1;
56943e8c 3358 cpu_address_space_init(cs, newas, 0);
f809c605
PB		 3359
3360 /* ... SMRAM with higher priority, linked from /machine/smram. */
3361 cpu->machine_done.notify = x86_cpu_machine_done;
3362 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 3363 }
3364#endif
3365
14a10fc3 3366 qemu_init_vcpu(cs);
d3c64d6a 3367
e48638fd
WH		 3368 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3369 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3370 * based on inputs (sockets,cores,threads), it is still better to gives
3371 * users a warning.
3372 *
3373 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3374 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3375 */
3376 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3377 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3378 " -smp options properly.");
3379 ht_warned = true;
3380 }
3381
d3c64d6a
IM		 3382 x86_cpu_apic_realize(cpu, &local_err);
3383 if (local_err != NULL) {
3384 goto out;
3385 }
14a10fc3 3386 cpu_reset(cs);
2b6f294c 3387
4dc1f449 3388 xcc->parent_realize(dev, &local_err);
2001d0cd 3389
4dc1f449
IM		 3390out:
3391 if (local_err != NULL) {
3392 error_propagate(errp, local_err);
3393 return;
3394 }
7a059953
AF		 3395}
3396
c884776e
IM		 3397static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3398{
3399 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 3400 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3401 Error *local_err = NULL;
c884776e
IM		 3402
3403#ifndef CONFIG_USER_ONLY
3404 cpu_remove_sync(CPU(dev));
3405 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3406#endif
3407
3408 if (cpu->apic_state) {
3409 object_unparent(OBJECT(cpu->apic_state));
3410 cpu->apic_state = NULL;
3411 }
7bbc124e
LV		 3412
3413 xcc->parent_unrealize(dev, &local_err);
3414 if (local_err != NULL) {
3415 error_propagate(errp, local_err);
3416 return;
3417 }
c884776e
IM		 3418}
3419
38e5c119
EH		 3420typedef struct BitProperty {
3421 uint32_t *ptr;
3422 uint32_t mask;
3423} BitProperty;
3424
d7bce999
EB		 3425static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3426 void *opaque, Error **errp)
38e5c119
EH		 3427{
3428 BitProperty *fp = opaque;
3429 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 3430 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3431}
3432
d7bce999
EB		 3433static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3434 void *opaque, Error **errp)
38e5c119
EH		 3435{
3436 DeviceState *dev = DEVICE(obj);
3437 BitProperty *fp = opaque;
3438 Error *local_err = NULL;
3439 bool value;
3440
3441 if (dev->realized) {
3442 qdev_prop_set_after_realize(dev, name, errp);
3443 return;
3444 }
3445
51e72bc1 3446 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3447 if (local_err) {
3448 error_propagate(errp, local_err);
3449 return;
3450 }
3451
3452 if (value) {
3453 *fp->ptr |= fp->mask;
3454 } else {
3455 *fp->ptr &= ~fp->mask;
3456 }
3457}
3458
3459static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3460 void *opaque)
3461{
3462 BitProperty *prop = opaque;
3463 g_free(prop);
3464}
3465
3466/* Register a boolean property to get/set a single bit in a uint32_t field.
3467 *
3468 * The same property name can be registered multiple times to make it affect
3469 * multiple bits in the same FeatureWord. In that case, the getter will return
3470 * true only if all bits are set.
3471 */
3472static void x86_cpu_register_bit_prop(X86CPU *cpu,
3473 const char *prop_name,
3474 uint32_t *field,
3475 int bitnr)
3476{
3477 BitProperty *fp;
3478 ObjectProperty *op;
3479 uint32_t mask = (1UL << bitnr);
3480
3481 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3482 if (op) {
3483 fp = op->opaque;
3484 assert(fp->ptr == field);
3485 fp->mask |= mask;
3486 } else {
3487 fp = g_new0(BitProperty, 1);
3488 fp->ptr = field;
3489 fp->mask = mask;
3490 object_property_add(OBJECT(cpu), prop_name, "bool",
3491 x86_cpu_get_bit_prop,
3492 x86_cpu_set_bit_prop,
3493 x86_cpu_release_bit_prop, fp, &error_abort);
3494 }
3495}
3496
3497static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3498 FeatureWord w,
3499 int bitnr)
3500{
38e5c119 3501 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 3502 const char *name = fi->feat_names[bitnr];
38e5c119 3503
16d2fcaa 3504 if (!name) {
38e5c119
EH		 3505 return;
3506 }
3507
fc7dfd20
EH		 3508 /* Property names should use "-" instead of "_".
3509 * Old names containing underscores are registered as aliases
3510 * using object_property_add_alias()
3511 */
16d2fcaa
EH		 3512 assert(!strchr(name, '_'));
3513 /* aliases don't use "|" delimiters anymore, they are registered
3514 * manually using object_property_add_alias() */
3515 assert(!strchr(name, '|'));
3516 x86_cpu_register_bit_prop(cpu, name, &cpu->env.features[w], bitnr);
38e5c119
EH		 3517}
3518
de024815
AF		 3519static void x86_cpu_initfn(Object *obj)
3520{
55e5c285 3521 CPUState *cs = CPU(obj);
de024815 3522 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3523 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3524 CPUX86State *env = &cpu->env;
38e5c119 3525 FeatureWord w;
de024815 3526
c05efcb1 3527 cs->env_ptr = env;
71ad61d3
AF		 3528
3529 object_property_add(obj, "family", "int",
95b8519d 3530 x86_cpuid_version_get_family,
71ad61d3 3531 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3532 object_property_add(obj, "model", "int",
67e30c83 3533 x86_cpuid_version_get_model,
c5291a4f 3534 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3535 object_property_add(obj, "stepping", "int",
35112e41 3536 x86_cpuid_version_get_stepping,
036e2222 3537 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3538 object_property_add_str(obj, "vendor",
3539 x86_cpuid_get_vendor,
3540 x86_cpuid_set_vendor, NULL);
938d4c25 3541 object_property_add_str(obj, "model-id",
63e886eb 3542 x86_cpuid_get_model_id,
938d4c25 3543 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3544 object_property_add(obj, "tsc-frequency", "int",
3545 x86_cpuid_get_tsc_freq,
3546 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 3547 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3548 x86_cpu_get_feature_words,
7e5292b5
EH		 3549 NULL, NULL, (void *)env->features, NULL);
3550 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3551 x86_cpu_get_feature_words,
3552 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3553
92067bf4 3554 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3555
38e5c119
EH		 3556 for (w = 0; w < FEATURE_WORDS; w++) {
3557 int bitnr;
3558
3559 for (bitnr = 0; bitnr < 32; bitnr++) {
3560 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3561 }
3562 }
3563
16d2fcaa
EH		 3564 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
3565 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
3566 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
3567 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
3568 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
3569 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
3570 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
3571
54b8dc7c
EH		 3572 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
3573 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
3574 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
3575 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
3576 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
3577 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
3578 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
3579 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
3580 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
3581 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
3582 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
3583 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
3584 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
3585 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
3586 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
3587 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
3588 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
3589 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
3590 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
3591 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
3592 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
3593
d940ee9b 3594 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
de024815
AF		 3595}
3596
997395d3
IM		 3597static int64_t x86_cpu_get_arch_id(CPUState *cs)
3598{
3599 X86CPU *cpu = X86_CPU(cs);
997395d3 3600
7e72a45c 3601 return cpu->apic_id;
997395d3
IM		 3602}
3603
444d5590
AF		 3604static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3605{
3606 X86CPU *cpu = X86_CPU(cs);
3607
3608 return cpu->env.cr[0] & CR0_PG_MASK;
3609}
3610
f45748f1
AF		 3611static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3612{
3613 X86CPU *cpu = X86_CPU(cs);
3614
3615 cpu->env.eip = value;
3616}
3617
bdf7ae5b
AF		 3618static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3619{
3620 X86CPU *cpu = X86_CPU(cs);
3621
3622 cpu->env.eip = tb->pc - tb->cs_base;
3623}
3624
8c2e1b00
AF		 3625static bool x86_cpu_has_work(CPUState *cs)
3626{
3627 X86CPU *cpu = X86_CPU(cs);
3628 CPUX86State *env = &cpu->env;
3629
6220e900
PD		 3630 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3631 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3632 (env->eflags & IF_MASK)) ||
3633 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3634 CPU_INTERRUPT_INIT |
3635 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3636 CPU_INTERRUPT_MCE)) ||
3637 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3638 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3639}
3640
9337e3b6 3641static Property x86_cpu_properties[] = {
2da00e31
IM		 3642#ifdef CONFIG_USER_ONLY
3643 /* apic_id = 0 by default for *-user, see commit 9886e834 */
3644 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 3645 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
3646 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
3647 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 3648#else
3649 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 3650 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
3651 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
3652 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 3653#endif
9337e3b6 3654 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3655 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3656 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3657 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3658 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3659 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3660 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3661 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3662 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3663 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3664 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3665 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3666 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3667 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 3668 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 3669 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 3670 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 3671 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
3672 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
3673 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
3674 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
3675 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
3676 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
3677 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 3678 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 3679 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 3680 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 3681 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
9337e3b6
EH		 3682 DEFINE_PROP_END_OF_LIST()
3683};
3684
5fd2087a
AF		 3685static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3686{
3687 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3688 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3689 DeviceClass *dc = DEVICE_CLASS(oc);
3690
3691 xcc->parent_realize = dc->realize;
7bbc124e 3692 xcc->parent_unrealize = dc->unrealize;
2b6f294c 3693 dc->realize = x86_cpu_realizefn;
c884776e 3694 dc->unrealize = x86_cpu_unrealizefn;
9337e3b6 3695 dc->props = x86_cpu_properties;
5fd2087a
AF		 3696
3697 xcc->parent_reset = cc->reset;
3698 cc->reset = x86_cpu_reset;
91b1df8c 3699 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3700
500050d1 3701 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3702 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3703 cc->has_work = x86_cpu_has_work;
97a8ea5a 3704 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3705 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3706 cc->dump_state = x86_cpu_dump_state;
f45748f1 3707 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3708 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3709 cc->gdb_read_register = x86_cpu_gdb_read_register;
3710 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3711 cc->get_arch_id = x86_cpu_get_arch_id;
3712 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3713#ifdef CONFIG_USER_ONLY
3714 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3715#else
a23bbfda 3716 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3717 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3718 cc->write_elf64_note = x86_cpu_write_elf64_note;
3719 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3720 cc->write_elf32_note = x86_cpu_write_elf32_note;
3721 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3722 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3723#endif
175cad36
DE		 3724 /* CPU_NB_REGS * 2 = general regs + xmm regs
3725 * 25 = eip, eflags, 6 seg regs, st[0-7], fctrl,...,fop, mxcsr.
3726 */
a0e372f0 3727 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3728#ifndef CONFIG_USER_ONLY
3729 cc->debug_excp_handler = breakpoint_handler;
3730#endif
374e0cd4
RH		 3731 cc->cpu_exec_enter = x86_cpu_exec_enter;
3732 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27 3733
edd12111 3734 dc->cannot_instantiate_with_device_add_yet = false;
5fd2087a
AF		 3735}
3736
3737static const TypeInfo x86_cpu_type_info = {
3738 .name = TYPE_X86_CPU,
3739 .parent = TYPE_CPU,
3740 .instance_size = sizeof(X86CPU),
de024815 3741 .instance_init = x86_cpu_initfn,
d940ee9b 3742 .abstract = true,
5fd2087a
AF		 3743 .class_size = sizeof(X86CPUClass),
3744 .class_init = x86_cpu_common_class_init,
3745};
3746
3747static void x86_cpu_register_types(void)
3748{
d940ee9b
EH		 3749 int i;
3750
5fd2087a 3751 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3752 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3753 x86_register_cpudef_type(&builtin_x86_defs[i]);
3754 }
3755#ifdef CONFIG_KVM
3756 type_register_static(&host_x86_cpu_type_info);
3757#endif
5fd2087a
AF		 3758}
3759
3760type_init(x86_cpu_register_types)
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