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KVM: nVMX: Fix posted intr delivery when vcpu is in guest mode
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
d62caabb 22#include "lapic.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732 25#include <linux/module.h>
9d8f549d 26#include <linux/kernel.h>
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27#include <linux/mm.h>
28#include <linux/highmem.h>
e8edc6e0 29#include <linux/sched.h>
c7addb90 30#include <linux/moduleparam.h>
e9bda3b3 31#include <linux/mod_devicetable.h>
af658dca 32#include <linux/trace_events.h>
5a0e3ad6 33#include <linux/slab.h>
cafd6659 34#include <linux/tboot.h>
f4124500 35#include <linux/hrtimer.h>
c207aee4 36#include <linux/frame.h>
5fdbf976 37#include "kvm_cache_regs.h"
35920a35 38#include "x86.h"
e495606d 39
28b835d6 40#include <asm/cpu.h>
6aa8b732 41#include <asm/io.h>
3b3be0d1 42#include <asm/desc.h>
13673a90 43#include <asm/vmx.h>
6210e37b 44#include <asm/virtext.h>
a0861c02 45#include <asm/mce.h>
952f07ec 46#include <asm/fpu/internal.h>
d7cd9796 47#include <asm/perf_event.h>
81908bf4 48#include <asm/debugreg.h>
8f536b76 49#include <asm/kexec.h>
dab2087d 50#include <asm/apic.h>
efc64404 51#include <asm/irq_remapping.h>
d6e41f11 52#include <asm/mmu_context.h>
6aa8b732 53
229456fc 54#include "trace.h"
25462f7f 55#include "pmu.h"
229456fc 56
4ecac3fd 57#define __ex(x) __kvm_handle_fault_on_reboot(x)
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58#define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 60
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61MODULE_AUTHOR("Qumranet");
62MODULE_LICENSE("GPL");
63
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64static const struct x86_cpu_id vmx_cpu_id[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX),
66 {}
67};
68MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
69
476bc001 70static bool __read_mostly enable_vpid = 1;
736caefe 71module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 72
476bc001 73static bool __read_mostly flexpriority_enabled = 1;
736caefe 74module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 75
476bc001 76static bool __read_mostly enable_ept = 1;
736caefe 77module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 78
476bc001 79static bool __read_mostly enable_unrestricted_guest = 1;
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80module_param_named(unrestricted_guest,
81 enable_unrestricted_guest, bool, S_IRUGO);
82
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83static bool __read_mostly enable_ept_ad_bits = 1;
84module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
85
a27685c3 86static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 87module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 88
476bc001 89static bool __read_mostly fasteoi = 1;
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90module_param(fasteoi, bool, S_IRUGO);
91
5a71785d 92static bool __read_mostly enable_apicv = 1;
01e439be 93module_param(enable_apicv, bool, S_IRUGO);
83d4c286 94
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95static bool __read_mostly enable_shadow_vmcs = 1;
96module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
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97/*
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
101 */
476bc001 102static bool __read_mostly nested = 0;
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103module_param(nested, bool, S_IRUGO);
104
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105static u64 __read_mostly host_xss;
106
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107static bool __read_mostly enable_pml = 1;
108module_param_named(pml, enable_pml, bool, S_IRUGO);
109
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110#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
111
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112/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
113static int __read_mostly cpu_preemption_timer_multi;
114static bool __read_mostly enable_preemption_timer = 1;
115#ifdef CONFIG_X86_64
116module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
117#endif
118
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119#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
120#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
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121#define KVM_VM_CR0_ALWAYS_ON \
122 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
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123#define KVM_CR4_GUEST_OWNED_BITS \
124 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 125 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 126
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127#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
128#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
129
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130#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
131
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132#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
133
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134/*
135 * Hyper-V requires all of these, so mark them as supported even though
136 * they are just treated the same as all-context.
137 */
138#define VMX_VPID_EXTENT_SUPPORTED_MASK \
139 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
140 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
143
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144/*
145 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
146 * ple_gap: upper bound on the amount of time between two successive
147 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 148 * According to test, this time is usually smaller than 128 cycles.
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149 * ple_window: upper bound on the amount of time a guest is allowed to execute
150 * in a PAUSE loop. Tests indicate that most spinlocks are held for
151 * less than 2^12 cycles
152 * Time is measured based on a counter that runs at the same rate as the TSC,
153 * refer SDM volume 3b section 21.6.13 & 22.1.3.
154 */
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155#define KVM_VMX_DEFAULT_PLE_GAP 128
156#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
157#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
158#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
159#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
160 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
161
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162static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
163module_param(ple_gap, int, S_IRUGO);
164
165static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
166module_param(ple_window, int, S_IRUGO);
167
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168/* Default doubles per-vcpu window every exit. */
169static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
170module_param(ple_window_grow, int, S_IRUGO);
171
172/* Default resets per-vcpu window every exit to ple_window. */
173static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
174module_param(ple_window_shrink, int, S_IRUGO);
175
176/* Default is to compute the maximum so we can never overflow. */
177static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
178static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179module_param(ple_window_max, int, S_IRUGO);
180
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181extern const ulong vmx_return;
182
8bf00a52 183#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 184#define VMCS02_POOL_SIZE 1
61d2ef2c 185
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186struct vmcs {
187 u32 revision_id;
188 u32 abort;
189 char data[0];
190};
191
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192/*
193 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
194 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
195 * loaded on this CPU (so we can clear them if the CPU goes down).
196 */
197struct loaded_vmcs {
198 struct vmcs *vmcs;
355f4fb1 199 struct vmcs *shadow_vmcs;
d462b819 200 int cpu;
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201 bool launched;
202 bool nmi_known_unmasked;
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203 struct list_head loaded_vmcss_on_cpu_link;
204};
205
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206struct shared_msr_entry {
207 unsigned index;
208 u64 data;
d5696725 209 u64 mask;
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210};
211
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212/*
213 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
214 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
215 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
216 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
217 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
218 * More than one of these structures may exist, if L1 runs multiple L2 guests.
219 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
220 * underlying hardware which will be used to run L2.
221 * This structure is packed to ensure that its layout is identical across
222 * machines (necessary for live migration).
223 * If there are changes in this struct, VMCS12_REVISION must be changed.
224 */
22bd0358 225typedef u64 natural_width;
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226struct __packed vmcs12 {
227 /* According to the Intel spec, a VMCS region must start with the
228 * following two fields. Then follow implementation-specific data.
229 */
230 u32 revision_id;
231 u32 abort;
22bd0358 232
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233 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
234 u32 padding[7]; /* room for future expansion */
235
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236 u64 io_bitmap_a;
237 u64 io_bitmap_b;
238 u64 msr_bitmap;
239 u64 vm_exit_msr_store_addr;
240 u64 vm_exit_msr_load_addr;
241 u64 vm_entry_msr_load_addr;
242 u64 tsc_offset;
243 u64 virtual_apic_page_addr;
244 u64 apic_access_addr;
705699a1 245 u64 posted_intr_desc_addr;
22bd0358 246 u64 ept_pointer;
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247 u64 eoi_exit_bitmap0;
248 u64 eoi_exit_bitmap1;
249 u64 eoi_exit_bitmap2;
250 u64 eoi_exit_bitmap3;
81dc01f7 251 u64 xss_exit_bitmap;
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252 u64 guest_physical_address;
253 u64 vmcs_link_pointer;
c5f983f6 254 u64 pml_address;
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255 u64 guest_ia32_debugctl;
256 u64 guest_ia32_pat;
257 u64 guest_ia32_efer;
258 u64 guest_ia32_perf_global_ctrl;
259 u64 guest_pdptr0;
260 u64 guest_pdptr1;
261 u64 guest_pdptr2;
262 u64 guest_pdptr3;
36be0b9d 263 u64 guest_bndcfgs;
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264 u64 host_ia32_pat;
265 u64 host_ia32_efer;
266 u64 host_ia32_perf_global_ctrl;
267 u64 padding64[8]; /* room for future expansion */
268 /*
269 * To allow migration of L1 (complete with its L2 guests) between
270 * machines of different natural widths (32 or 64 bit), we cannot have
271 * unsigned long fields with no explict size. We use u64 (aliased
272 * natural_width) instead. Luckily, x86 is little-endian.
273 */
274 natural_width cr0_guest_host_mask;
275 natural_width cr4_guest_host_mask;
276 natural_width cr0_read_shadow;
277 natural_width cr4_read_shadow;
278 natural_width cr3_target_value0;
279 natural_width cr3_target_value1;
280 natural_width cr3_target_value2;
281 natural_width cr3_target_value3;
282 natural_width exit_qualification;
283 natural_width guest_linear_address;
284 natural_width guest_cr0;
285 natural_width guest_cr3;
286 natural_width guest_cr4;
287 natural_width guest_es_base;
288 natural_width guest_cs_base;
289 natural_width guest_ss_base;
290 natural_width guest_ds_base;
291 natural_width guest_fs_base;
292 natural_width guest_gs_base;
293 natural_width guest_ldtr_base;
294 natural_width guest_tr_base;
295 natural_width guest_gdtr_base;
296 natural_width guest_idtr_base;
297 natural_width guest_dr7;
298 natural_width guest_rsp;
299 natural_width guest_rip;
300 natural_width guest_rflags;
301 natural_width guest_pending_dbg_exceptions;
302 natural_width guest_sysenter_esp;
303 natural_width guest_sysenter_eip;
304 natural_width host_cr0;
305 natural_width host_cr3;
306 natural_width host_cr4;
307 natural_width host_fs_base;
308 natural_width host_gs_base;
309 natural_width host_tr_base;
310 natural_width host_gdtr_base;
311 natural_width host_idtr_base;
312 natural_width host_ia32_sysenter_esp;
313 natural_width host_ia32_sysenter_eip;
314 natural_width host_rsp;
315 natural_width host_rip;
316 natural_width paddingl[8]; /* room for future expansion */
317 u32 pin_based_vm_exec_control;
318 u32 cpu_based_vm_exec_control;
319 u32 exception_bitmap;
320 u32 page_fault_error_code_mask;
321 u32 page_fault_error_code_match;
322 u32 cr3_target_count;
323 u32 vm_exit_controls;
324 u32 vm_exit_msr_store_count;
325 u32 vm_exit_msr_load_count;
326 u32 vm_entry_controls;
327 u32 vm_entry_msr_load_count;
328 u32 vm_entry_intr_info_field;
329 u32 vm_entry_exception_error_code;
330 u32 vm_entry_instruction_len;
331 u32 tpr_threshold;
332 u32 secondary_vm_exec_control;
333 u32 vm_instruction_error;
334 u32 vm_exit_reason;
335 u32 vm_exit_intr_info;
336 u32 vm_exit_intr_error_code;
337 u32 idt_vectoring_info_field;
338 u32 idt_vectoring_error_code;
339 u32 vm_exit_instruction_len;
340 u32 vmx_instruction_info;
341 u32 guest_es_limit;
342 u32 guest_cs_limit;
343 u32 guest_ss_limit;
344 u32 guest_ds_limit;
345 u32 guest_fs_limit;
346 u32 guest_gs_limit;
347 u32 guest_ldtr_limit;
348 u32 guest_tr_limit;
349 u32 guest_gdtr_limit;
350 u32 guest_idtr_limit;
351 u32 guest_es_ar_bytes;
352 u32 guest_cs_ar_bytes;
353 u32 guest_ss_ar_bytes;
354 u32 guest_ds_ar_bytes;
355 u32 guest_fs_ar_bytes;
356 u32 guest_gs_ar_bytes;
357 u32 guest_ldtr_ar_bytes;
358 u32 guest_tr_ar_bytes;
359 u32 guest_interruptibility_info;
360 u32 guest_activity_state;
361 u32 guest_sysenter_cs;
362 u32 host_ia32_sysenter_cs;
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363 u32 vmx_preemption_timer_value;
364 u32 padding32[7]; /* room for future expansion */
22bd0358 365 u16 virtual_processor_id;
705699a1 366 u16 posted_intr_nv;
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NHE
367 u16 guest_es_selector;
368 u16 guest_cs_selector;
369 u16 guest_ss_selector;
370 u16 guest_ds_selector;
371 u16 guest_fs_selector;
372 u16 guest_gs_selector;
373 u16 guest_ldtr_selector;
374 u16 guest_tr_selector;
608406e2 375 u16 guest_intr_status;
c5f983f6 376 u16 guest_pml_index;
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NHE
377 u16 host_es_selector;
378 u16 host_cs_selector;
379 u16 host_ss_selector;
380 u16 host_ds_selector;
381 u16 host_fs_selector;
382 u16 host_gs_selector;
383 u16 host_tr_selector;
a9d30f33
NHE
384};
385
386/*
387 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
388 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
389 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
390 */
391#define VMCS12_REVISION 0x11e57ed0
392
393/*
394 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
395 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
396 * current implementation, 4K are reserved to avoid future complications.
397 */
398#define VMCS12_SIZE 0x1000
399
ff2f6fe9
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400/* Used to remember the last vmcs02 used for some recently used vmcs12s */
401struct vmcs02_list {
402 struct list_head list;
403 gpa_t vmptr;
404 struct loaded_vmcs vmcs02;
405};
406
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NHE
407/*
408 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
409 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
410 */
411struct nested_vmx {
412 /* Has the level1 guest done vmxon? */
413 bool vmxon;
3573e22c 414 gpa_t vmxon_ptr;
c5f983f6 415 bool pml_full;
a9d30f33
NHE
416
417 /* The guest-physical address of the current VMCS L1 keeps for L2 */
418 gpa_t current_vmptr;
419 /* The host-usable pointer to the above */
420 struct page *current_vmcs12_page;
421 struct vmcs12 *current_vmcs12;
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DM
422 /*
423 * Cache of the guest's VMCS, existing outside of guest memory.
424 * Loaded from guest memory during VMPTRLD. Flushed to guest
425 * memory during VMXOFF, VMCLEAR, VMPTRLD.
426 */
427 struct vmcs12 *cached_vmcs12;
012f83cb
AG
428 /*
429 * Indicates if the shadow vmcs must be updated with the
430 * data hold by vmcs12
431 */
432 bool sync_shadow_vmcs;
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433
434 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
435 struct list_head vmcs02_pool;
436 int vmcs02_num;
dccbfcf5 437 bool change_vmcs01_virtual_x2apic_mode;
644d711a
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438 /* L2 must run next, and mustn't decide to exit to L1. */
439 bool nested_run_pending;
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NHE
440 /*
441 * Guest pages referred to in vmcs02 with host-physical pointers, so
442 * we must keep them pinned while L2 runs.
443 */
444 struct page *apic_access_page;
a7c0b07d 445 struct page *virtual_apic_page;
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WV
446 struct page *pi_desc_page;
447 struct pi_desc *pi_desc;
448 bool pi_pending;
449 u16 posted_intr_nv;
f4124500 450
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RK
451 unsigned long *msr_bitmap;
452
f4124500
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453 struct hrtimer preemption_timer;
454 bool preemption_timer_expired;
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455
456 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
457 u64 vmcs01_debugctl;
b9c237bb 458
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WL
459 u16 vpid02;
460 u16 last_vpid;
461
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DM
462 /*
463 * We only store the "true" versions of the VMX capability MSRs. We
464 * generate the "non-true" versions by setting the must-be-1 bits
465 * according to the SDM.
466 */
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467 u32 nested_vmx_procbased_ctls_low;
468 u32 nested_vmx_procbased_ctls_high;
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WV
469 u32 nested_vmx_secondary_ctls_low;
470 u32 nested_vmx_secondary_ctls_high;
471 u32 nested_vmx_pinbased_ctls_low;
472 u32 nested_vmx_pinbased_ctls_high;
473 u32 nested_vmx_exit_ctls_low;
474 u32 nested_vmx_exit_ctls_high;
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475 u32 nested_vmx_entry_ctls_low;
476 u32 nested_vmx_entry_ctls_high;
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WV
477 u32 nested_vmx_misc_low;
478 u32 nested_vmx_misc_high;
479 u32 nested_vmx_ept_caps;
99b83ac8 480 u32 nested_vmx_vpid_caps;
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DM
481 u64 nested_vmx_basic;
482 u64 nested_vmx_cr0_fixed0;
483 u64 nested_vmx_cr0_fixed1;
484 u64 nested_vmx_cr4_fixed0;
485 u64 nested_vmx_cr4_fixed1;
486 u64 nested_vmx_vmcs_enum;
ec378aee
NHE
487};
488
01e439be 489#define POSTED_INTR_ON 0
ebbfc765
FW
490#define POSTED_INTR_SN 1
491
01e439be
YZ
492/* Posted-Interrupt Descriptor */
493struct pi_desc {
494 u32 pir[8]; /* Posted interrupt requested */
6ef1522f
FW
495 union {
496 struct {
497 /* bit 256 - Outstanding Notification */
498 u16 on : 1,
499 /* bit 257 - Suppress Notification */
500 sn : 1,
501 /* bit 271:258 - Reserved */
502 rsvd_1 : 14;
503 /* bit 279:272 - Notification Vector */
504 u8 nv;
505 /* bit 287:280 - Reserved */
506 u8 rsvd_2;
507 /* bit 319:288 - Notification Destination */
508 u32 ndst;
509 };
510 u64 control;
511 };
512 u32 rsvd[6];
01e439be
YZ
513} __aligned(64);
514
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YZ
515static bool pi_test_and_set_on(struct pi_desc *pi_desc)
516{
517 return test_and_set_bit(POSTED_INTR_ON,
518 (unsigned long *)&pi_desc->control);
519}
520
521static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
522{
523 return test_and_clear_bit(POSTED_INTR_ON,
524 (unsigned long *)&pi_desc->control);
525}
526
527static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
528{
529 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
530}
531
ebbfc765
FW
532static inline void pi_clear_sn(struct pi_desc *pi_desc)
533{
534 return clear_bit(POSTED_INTR_SN,
535 (unsigned long *)&pi_desc->control);
536}
537
538static inline void pi_set_sn(struct pi_desc *pi_desc)
539{
540 return set_bit(POSTED_INTR_SN,
541 (unsigned long *)&pi_desc->control);
542}
543
ad361091
PB
544static inline void pi_clear_on(struct pi_desc *pi_desc)
545{
546 clear_bit(POSTED_INTR_ON,
547 (unsigned long *)&pi_desc->control);
548}
549
ebbfc765
FW
550static inline int pi_test_on(struct pi_desc *pi_desc)
551{
552 return test_bit(POSTED_INTR_ON,
553 (unsigned long *)&pi_desc->control);
554}
555
556static inline int pi_test_sn(struct pi_desc *pi_desc)
557{
558 return test_bit(POSTED_INTR_SN,
559 (unsigned long *)&pi_desc->control);
560}
561
a2fa3e9f 562struct vcpu_vmx {
fb3f0f51 563 struct kvm_vcpu vcpu;
313dbd49 564 unsigned long host_rsp;
29bd8a78 565 u8 fail;
51aa01d1 566 u32 exit_intr_info;
1155f76a 567 u32 idt_vectoring_info;
6de12732 568 ulong rflags;
26bb0981 569 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH
570 int nmsrs;
571 int save_nmsrs;
a547c6db 572 unsigned long host_idt_base;
a2fa3e9f 573#ifdef CONFIG_X86_64
44ea2b17
AK
574 u64 msr_host_kernel_gs_base;
575 u64 msr_guest_kernel_gs_base;
a2fa3e9f 576#endif
2961e876
GN
577 u32 vm_entry_controls_shadow;
578 u32 vm_exit_controls_shadow;
d462b819
NHE
579 /*
580 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
581 * non-nested (L1) guest, it always points to vmcs01. For a nested
582 * guest (L2), it points to a different VMCS.
583 */
584 struct loaded_vmcs vmcs01;
585 struct loaded_vmcs *loaded_vmcs;
586 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK
587 struct msr_autoload {
588 unsigned nr;
589 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
590 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
591 } msr_autoload;
a2fa3e9f
GH
592 struct {
593 int loaded;
594 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK
595#ifdef CONFIG_X86_64
596 u16 ds_sel, es_sel;
597#endif
152d3f2f
LV
598 int gs_ldt_reload_needed;
599 int fs_reload_needed;
da8999d3 600 u64 msr_host_bndcfgs;
d6e41f11 601 unsigned long vmcs_host_cr3; /* May not match real cr3 */
d974baa3 602 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 603 } host_state;
9c8cba37 604 struct {
7ffd92c5 605 int vm86_active;
78ac8b47 606 ulong save_rflags;
f5f7b2fe
AK
607 struct kvm_segment segs[8];
608 } rmode;
609 struct {
610 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK
611 struct kvm_save_segment {
612 u16 selector;
613 unsigned long base;
614 u32 limit;
615 u32 ar;
f5f7b2fe 616 } seg[8];
2fb92db1 617 } segment_cache;
2384d2b3 618 int vpid;
04fa4d32 619 bool emulation_required;
3b86cd99 620
a0861c02 621 u32 exit_reason;
4e47c7a6 622
01e439be
YZ
623 /* Posted interrupt descriptor */
624 struct pi_desc pi_desc;
625
ec378aee
NHE
626 /* Support for a guest hypervisor (nested VMX) */
627 struct nested_vmx nested;
a7653ecd
RK
628
629 /* Dynamic PLE window. */
630 int ple_window;
631 bool ple_window_dirty;
843e4330
KH
632
633 /* Support for PML */
634#define PML_ENTITY_NUM 512
635 struct page *pml_pg;
2680d6da 636
64672c95
YJ
637 /* apic deadline value in host tsc */
638 u64 hv_deadline_tsc;
639
2680d6da 640 u64 current_tsc_ratio;
1be0e61c
XG
641
642 bool guest_pkru_valid;
643 u32 guest_pkru;
644 u32 host_pkru;
3b84080b 645
37e4c997
HZ
646 /*
647 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
648 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
649 * in msr_ia32_feature_control_valid_bits.
650 */
3b84080b 651 u64 msr_ia32_feature_control;
37e4c997 652 u64 msr_ia32_feature_control_valid_bits;
a2fa3e9f
GH
653};
654
2fb92db1
AK
655enum segment_cache_field {
656 SEG_FIELD_SEL = 0,
657 SEG_FIELD_BASE = 1,
658 SEG_FIELD_LIMIT = 2,
659 SEG_FIELD_AR = 3,
660
661 SEG_FIELD_NR = 4
662};
663
a2fa3e9f
GH
664static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
665{
fb3f0f51 666 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH
667}
668
efc64404
FW
669static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
670{
671 return &(to_vmx(vcpu)->pi_desc);
672}
673
22bd0358
NHE
674#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
675#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
676#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
677 [number##_HIGH] = VMCS12_OFFSET(name)+4
678
4607c2d7 679
fe2b201b 680static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG
681 /*
682 * We do NOT shadow fields that are modified when L0
683 * traps and emulates any vmx instruction (e.g. VMPTRLD,
684 * VMXON...) executed by L1.
685 * For example, VM_INSTRUCTION_ERROR is read
686 * by L1 if a vmx instruction fails (part of the error path).
687 * Note the code assumes this logic. If for some reason
688 * we start shadowing these fields then we need to
689 * force a shadow sync when L0 emulates vmx instructions
690 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
691 * by nested_vmx_failValid)
692 */
693 VM_EXIT_REASON,
694 VM_EXIT_INTR_INFO,
695 VM_EXIT_INSTRUCTION_LEN,
696 IDT_VECTORING_INFO_FIELD,
697 IDT_VECTORING_ERROR_CODE,
698 VM_EXIT_INTR_ERROR_CODE,
699 EXIT_QUALIFICATION,
700 GUEST_LINEAR_ADDRESS,
701 GUEST_PHYSICAL_ADDRESS
702};
fe2b201b 703static int max_shadow_read_only_fields =
4607c2d7
AG
704 ARRAY_SIZE(shadow_read_only_fields);
705
fe2b201b 706static unsigned long shadow_read_write_fields[] = {
a7c0b07d 707 TPR_THRESHOLD,
4607c2d7
AG
708 GUEST_RIP,
709 GUEST_RSP,
710 GUEST_CR0,
711 GUEST_CR3,
712 GUEST_CR4,
713 GUEST_INTERRUPTIBILITY_INFO,
714 GUEST_RFLAGS,
715 GUEST_CS_SELECTOR,
716 GUEST_CS_AR_BYTES,
717 GUEST_CS_LIMIT,
718 GUEST_CS_BASE,
719 GUEST_ES_BASE,
36be0b9d 720 GUEST_BNDCFGS,
4607c2d7
AG
721 CR0_GUEST_HOST_MASK,
722 CR0_READ_SHADOW,
723 CR4_READ_SHADOW,
724 TSC_OFFSET,
725 EXCEPTION_BITMAP,
726 CPU_BASED_VM_EXEC_CONTROL,
727 VM_ENTRY_EXCEPTION_ERROR_CODE,
728 VM_ENTRY_INTR_INFO_FIELD,
729 VM_ENTRY_INSTRUCTION_LEN,
730 VM_ENTRY_EXCEPTION_ERROR_CODE,
731 HOST_FS_BASE,
732 HOST_GS_BASE,
733 HOST_FS_SELECTOR,
734 HOST_GS_SELECTOR
735};
fe2b201b 736static int max_shadow_read_write_fields =
4607c2d7
AG
737 ARRAY_SIZE(shadow_read_write_fields);
738
772e0318 739static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 740 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 741 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE
742 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
743 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
744 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
745 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
746 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
747 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
748 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
749 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 750 FIELD(GUEST_INTR_STATUS, guest_intr_status),
c5f983f6 751 FIELD(GUEST_PML_INDEX, guest_pml_index),
22bd0358
NHE
752 FIELD(HOST_ES_SELECTOR, host_es_selector),
753 FIELD(HOST_CS_SELECTOR, host_cs_selector),
754 FIELD(HOST_SS_SELECTOR, host_ss_selector),
755 FIELD(HOST_DS_SELECTOR, host_ds_selector),
756 FIELD(HOST_FS_SELECTOR, host_fs_selector),
757 FIELD(HOST_GS_SELECTOR, host_gs_selector),
758 FIELD(HOST_TR_SELECTOR, host_tr_selector),
759 FIELD64(IO_BITMAP_A, io_bitmap_a),
760 FIELD64(IO_BITMAP_B, io_bitmap_b),
761 FIELD64(MSR_BITMAP, msr_bitmap),
762 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
763 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
764 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
765 FIELD64(TSC_OFFSET, tsc_offset),
766 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
767 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 768 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 769 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV
770 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
771 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
772 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
773 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 774 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE
775 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
776 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
c5f983f6 777 FIELD64(PML_ADDRESS, pml_address),
22bd0358
NHE
778 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
779 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
780 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
781 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
782 FIELD64(GUEST_PDPTR0, guest_pdptr0),
783 FIELD64(GUEST_PDPTR1, guest_pdptr1),
784 FIELD64(GUEST_PDPTR2, guest_pdptr2),
785 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 786 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE
787 FIELD64(HOST_IA32_PAT, host_ia32_pat),
788 FIELD64(HOST_IA32_EFER, host_ia32_efer),
789 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
790 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
791 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
792 FIELD(EXCEPTION_BITMAP, exception_bitmap),
793 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
794 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
795 FIELD(CR3_TARGET_COUNT, cr3_target_count),
796 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
797 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
798 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
799 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
800 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
801 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
802 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
803 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
804 FIELD(TPR_THRESHOLD, tpr_threshold),
805 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
806 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
807 FIELD(VM_EXIT_REASON, vm_exit_reason),
808 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
809 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
810 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
811 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
812 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
813 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
814 FIELD(GUEST_ES_LIMIT, guest_es_limit),
815 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
816 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
817 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
818 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
819 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
820 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
821 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
822 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
823 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
824 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
825 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
826 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
827 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
828 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
829 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
830 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
831 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
832 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
833 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
834 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
835 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 836 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE
837 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
838 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
839 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
840 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
841 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
842 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
843 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
844 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
845 FIELD(EXIT_QUALIFICATION, exit_qualification),
846 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
847 FIELD(GUEST_CR0, guest_cr0),
848 FIELD(GUEST_CR3, guest_cr3),
849 FIELD(GUEST_CR4, guest_cr4),
850 FIELD(GUEST_ES_BASE, guest_es_base),
851 FIELD(GUEST_CS_BASE, guest_cs_base),
852 FIELD(GUEST_SS_BASE, guest_ss_base),
853 FIELD(GUEST_DS_BASE, guest_ds_base),
854 FIELD(GUEST_FS_BASE, guest_fs_base),
855 FIELD(GUEST_GS_BASE, guest_gs_base),
856 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
857 FIELD(GUEST_TR_BASE, guest_tr_base),
858 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
859 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
860 FIELD(GUEST_DR7, guest_dr7),
861 FIELD(GUEST_RSP, guest_rsp),
862 FIELD(GUEST_RIP, guest_rip),
863 FIELD(GUEST_RFLAGS, guest_rflags),
864 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
865 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
866 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
867 FIELD(HOST_CR0, host_cr0),
868 FIELD(HOST_CR3, host_cr3),
869 FIELD(HOST_CR4, host_cr4),
870 FIELD(HOST_FS_BASE, host_fs_base),
871 FIELD(HOST_GS_BASE, host_gs_base),
872 FIELD(HOST_TR_BASE, host_tr_base),
873 FIELD(HOST_GDTR_BASE, host_gdtr_base),
874 FIELD(HOST_IDTR_BASE, host_idtr_base),
875 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
876 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
877 FIELD(HOST_RSP, host_rsp),
878 FIELD(HOST_RIP, host_rip),
879};
22bd0358
NHE
880
881static inline short vmcs_field_to_offset(unsigned long field)
882{
a2ae9df7
PB
883 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
884
885 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
886 vmcs_field_to_offset_table[field] == 0)
887 return -ENOENT;
888
22bd0358
NHE
889 return vmcs_field_to_offset_table[field];
890}
891
a9d30f33
NHE
892static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
893{
4f2777bc 894 return to_vmx(vcpu)->nested.cached_vmcs12;
a9d30f33
NHE
895}
896
897static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
898{
54bf36aa 899 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 900 if (is_error_page(page))
a9d30f33 901 return NULL;
32cad84f 902
a9d30f33
NHE
903 return page;
904}
905
906static void nested_release_page(struct page *page)
907{
908 kvm_release_page_dirty(page);
909}
910
911static void nested_release_page_clean(struct page *page)
912{
913 kvm_release_page_clean(page);
914}
915
995f00a6 916static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
bfd0a56b 917static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
995f00a6 918static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
f53cd63c 919static bool vmx_xsaves_supported(void);
776e58ea 920static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW
921static void vmx_set_segment(struct kvm_vcpu *vcpu,
922 struct kvm_segment *var, int seg);
923static void vmx_get_segment(struct kvm_vcpu *vcpu,
924 struct kvm_segment *var, int seg);
d99e4152
GN
925static bool guest_state_valid(struct kvm_vcpu *vcpu);
926static u32 vmx_segment_access_rights(struct kvm_segment *var);
c3114420 927static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 928static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 929static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 930
6aa8b732
AK
931static DEFINE_PER_CPU(struct vmcs *, vmxarea);
932static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE
933/*
934 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
935 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
936 */
937static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 938
bf9f6ac8
FW
939/*
940 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
941 * can find which vCPU should be waken up.
942 */
943static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
944static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
945
23611332
RK
946enum {
947 VMX_IO_BITMAP_A,
948 VMX_IO_BITMAP_B,
949 VMX_MSR_BITMAP_LEGACY,
950 VMX_MSR_BITMAP_LONGMODE,
951 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
952 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
953 VMX_MSR_BITMAP_LEGACY_X2APIC,
954 VMX_MSR_BITMAP_LONGMODE_X2APIC,
955 VMX_VMREAD_BITMAP,
956 VMX_VMWRITE_BITMAP,
957 VMX_BITMAP_NR
958};
959
960static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
961
962#define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
963#define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
964#define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
965#define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
966#define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
967#define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
968#define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
969#define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
970#define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
971#define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
fdef3ad1 972
110312c8 973static bool cpu_has_load_ia32_efer;
8bf00a52 974static bool cpu_has_load_perf_global_ctrl;
110312c8 975
2384d2b3
SY
976static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
977static DEFINE_SPINLOCK(vmx_vpid_lock);
978
1c3d14fe 979static struct vmcs_config {
6aa8b732
AK
980 int size;
981 int order;
9ac7e3e8 982 u32 basic_cap;
6aa8b732 983 u32 revision_id;
1c3d14fe
YS
984 u32 pin_based_exec_ctrl;
985 u32 cpu_based_exec_ctrl;
f78e0e2e 986 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS
987 u32 vmexit_ctrl;
988 u32 vmentry_ctrl;
989} vmcs_config;
6aa8b732 990
efff9e53 991static struct vmx_capability {
d56f546d
SY
992 u32 ept;
993 u32 vpid;
994} vmx_capability;
995
6aa8b732
AK
996#define VMX_SEGMENT_FIELD(seg) \
997 [VCPU_SREG_##seg] = { \
998 .selector = GUEST_##seg##_SELECTOR, \
999 .base = GUEST_##seg##_BASE, \
1000 .limit = GUEST_##seg##_LIMIT, \
1001 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1002 }
1003
772e0318 1004static const struct kvm_vmx_segment_field {
6aa8b732
AK
1005 unsigned selector;
1006 unsigned base;
1007 unsigned limit;
1008 unsigned ar_bytes;
1009} kvm_vmx_segment_fields[] = {
1010 VMX_SEGMENT_FIELD(CS),
1011 VMX_SEGMENT_FIELD(DS),
1012 VMX_SEGMENT_FIELD(ES),
1013 VMX_SEGMENT_FIELD(FS),
1014 VMX_SEGMENT_FIELD(GS),
1015 VMX_SEGMENT_FIELD(SS),
1016 VMX_SEGMENT_FIELD(TR),
1017 VMX_SEGMENT_FIELD(LDTR),
1018};
1019
26bb0981
AK
1020static u64 host_efer;
1021
6de4f3ad
AK
1022static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1023
4d56c8a7 1024/*
8c06585d 1025 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK
1026 * away by decrementing the array size.
1027 */
6aa8b732 1028static const u32 vmx_msr_index[] = {
05b3e0c2 1029#ifdef CONFIG_X86_64
44ea2b17 1030 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 1031#endif
8c06585d 1032 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 1033};
6aa8b732 1034
5bb16016 1035static inline bool is_exception_n(u32 intr_info, u8 vector)
6aa8b732
AK
1036{
1037 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1038 INTR_INFO_VALID_MASK)) ==
5bb16016
JK
1039 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1040}
1041
6f05485d
JK
1042static inline bool is_debug(u32 intr_info)
1043{
1044 return is_exception_n(intr_info, DB_VECTOR);
1045}
1046
1047static inline bool is_breakpoint(u32 intr_info)
1048{
1049 return is_exception_n(intr_info, BP_VECTOR);
1050}
1051
5bb16016
JK
1052static inline bool is_page_fault(u32 intr_info)
1053{
1054 return is_exception_n(intr_info, PF_VECTOR);
6aa8b732
AK
1055}
1056
31299944 1057static inline bool is_no_device(u32 intr_info)
2ab455cc 1058{
5bb16016 1059 return is_exception_n(intr_info, NM_VECTOR);
2ab455cc
AL
1060}
1061
31299944 1062static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0 1063{
5bb16016 1064 return is_exception_n(intr_info, UD_VECTOR);
7aa81cc0
AL
1065}
1066
31299944 1067static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK
1068{
1069 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1070 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1071}
1072
31299944 1073static inline bool is_machine_check(u32 intr_info)
a0861c02
AK
1074{
1075 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1076 INTR_INFO_VALID_MASK)) ==
1077 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1078}
1079
31299944 1080static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 1081{
04547156 1082 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY
1083}
1084
31299944 1085static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 1086{
04547156 1087 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS
1088}
1089
35754c98 1090static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 1091{
35754c98 1092 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS
1093}
1094
31299944 1095static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 1096{
04547156
SY
1097 return vmcs_config.cpu_based_exec_ctrl &
1098 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY
1099}
1100
774ead3a 1101static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 1102{
04547156
SY
1103 return vmcs_config.cpu_based_2nd_exec_ctrl &
1104 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1105}
1106
8d14695f
YZ
1107static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1108{
1109 return vmcs_config.cpu_based_2nd_exec_ctrl &
1110 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1111}
1112
83d4c286
YZ
1113static inline bool cpu_has_vmx_apic_register_virt(void)
1114{
1115 return vmcs_config.cpu_based_2nd_exec_ctrl &
1116 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1117}
1118
c7c9c56c
YZ
1119static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1120{
1121 return vmcs_config.cpu_based_2nd_exec_ctrl &
1122 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1123}
1124
64672c95
YJ
1125/*
1126 * Comment's format: document - errata name - stepping - processor name.
1127 * Refer from
1128 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1129 */
1130static u32 vmx_preemption_cpu_tfms[] = {
1131/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
11320x000206E6,
1133/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1134/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1135/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
11360x00020652,
1137/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
11380x00020655,
1139/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1140/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1141/*
1142 * 320767.pdf - AAP86 - B1 -
1143 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1144 */
11450x000106E5,
1146/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
11470x000106A0,
1148/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
11490x000106A1,
1150/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
11510x000106A4,
1152 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1153 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1154 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
11550x000106A5,
1156};
1157
1158static inline bool cpu_has_broken_vmx_preemption_timer(void)
1159{
1160 u32 eax = cpuid_eax(0x00000001), i;
1161
1162 /* Clear the reserved bits */
1163 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 1164 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ
1165 if (eax == vmx_preemption_cpu_tfms[i])
1166 return true;
1167
1168 return false;
1169}
1170
1171static inline bool cpu_has_vmx_preemption_timer(void)
1172{
64672c95
YJ
1173 return vmcs_config.pin_based_exec_ctrl &
1174 PIN_BASED_VMX_PREEMPTION_TIMER;
1175}
1176
01e439be
YZ
1177static inline bool cpu_has_vmx_posted_intr(void)
1178{
d6a858d1
PB
1179 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1180 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ
1181}
1182
1183static inline bool cpu_has_vmx_apicv(void)
1184{
1185 return cpu_has_vmx_apic_register_virt() &&
1186 cpu_has_vmx_virtual_intr_delivery() &&
1187 cpu_has_vmx_posted_intr();
1188}
1189
04547156
SY
1190static inline bool cpu_has_vmx_flexpriority(void)
1191{
1192 return cpu_has_vmx_tpr_shadow() &&
1193 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY
1194}
1195
e799794e
MT
1196static inline bool cpu_has_vmx_ept_execute_only(void)
1197{
31299944 1198 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT
1199}
1200
e799794e
MT
1201static inline bool cpu_has_vmx_ept_2m_page(void)
1202{
31299944 1203 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT
1204}
1205
878403b7
SY
1206static inline bool cpu_has_vmx_ept_1g_page(void)
1207{
31299944 1208 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY
1209}
1210
4bc9b982
SY
1211static inline bool cpu_has_vmx_ept_4levels(void)
1212{
1213 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1214}
1215
83c3a331
XH
1216static inline bool cpu_has_vmx_ept_ad_bits(void)
1217{
1218 return vmx_capability.ept & VMX_EPT_AD_BIT;
1219}
1220
31299944 1221static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1222{
31299944 1223 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY
1224}
1225
31299944 1226static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1227{
31299944 1228 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY
1229}
1230
518c8aee
GJ
1231static inline bool cpu_has_vmx_invvpid_single(void)
1232{
1233 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1234}
1235
b9d762fa
GJ
1236static inline bool cpu_has_vmx_invvpid_global(void)
1237{
1238 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1239}
1240
08d839c4
WL
1241static inline bool cpu_has_vmx_invvpid(void)
1242{
1243 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1244}
1245
31299944 1246static inline bool cpu_has_vmx_ept(void)
d56f546d 1247{
04547156
SY
1248 return vmcs_config.cpu_based_2nd_exec_ctrl &
1249 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY
1250}
1251
31299944 1252static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK
1253{
1254 return vmcs_config.cpu_based_2nd_exec_ctrl &
1255 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1256}
1257
31299944 1258static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE
1259{
1260 return vmcs_config.cpu_based_2nd_exec_ctrl &
1261 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1262}
1263
9ac7e3e8
JD
1264static inline bool cpu_has_vmx_basic_inout(void)
1265{
1266 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1267}
1268
35754c98 1269static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1270{
35754c98 1271 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY
1272}
1273
31299944 1274static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1275{
04547156
SY
1276 return vmcs_config.cpu_based_2nd_exec_ctrl &
1277 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY
1278}
1279
31299944 1280static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY
1281{
1282 return vmcs_config.cpu_based_2nd_exec_ctrl &
1283 SECONDARY_EXEC_RDTSCP;
1284}
1285
ad756a16
MJ
1286static inline bool cpu_has_vmx_invpcid(void)
1287{
1288 return vmcs_config.cpu_based_2nd_exec_ctrl &
1289 SECONDARY_EXEC_ENABLE_INVPCID;
1290}
1291
f5f48ee1
SY
1292static inline bool cpu_has_vmx_wbinvd_exit(void)
1293{
1294 return vmcs_config.cpu_based_2nd_exec_ctrl &
1295 SECONDARY_EXEC_WBINVD_EXITING;
1296}
1297
abc4fc58
AG
1298static inline bool cpu_has_vmx_shadow_vmcs(void)
1299{
1300 u64 vmx_msr;
1301 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1302 /* check if the cpu supports writing r/o exit information fields */
1303 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1304 return false;
1305
1306 return vmcs_config.cpu_based_2nd_exec_ctrl &
1307 SECONDARY_EXEC_SHADOW_VMCS;
1308}
1309
843e4330
KH
1310static inline bool cpu_has_vmx_pml(void)
1311{
1312 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1313}
1314
64903d61
HZ
1315static inline bool cpu_has_vmx_tsc_scaling(void)
1316{
1317 return vmcs_config.cpu_based_2nd_exec_ctrl &
1318 SECONDARY_EXEC_TSC_SCALING;
1319}
1320
04547156
SY
1321static inline bool report_flexpriority(void)
1322{
1323 return flexpriority_enabled;
1324}
1325
c7c2c709
JM
1326static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1327{
1328 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1329}
1330
fe3ef05c
NHE
1331static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1332{
1333 return vmcs12->cpu_based_vm_exec_control & bit;
1334}
1335
1336static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1337{
1338 return (vmcs12->cpu_based_vm_exec_control &
1339 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1340 (vmcs12->secondary_vm_exec_control & bit);
1341}
1342
f5c4368f 1343static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE
1344{
1345 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1346}
1347
f4124500
JK
1348static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1349{
1350 return vmcs12->pin_based_vm_exec_control &
1351 PIN_BASED_VMX_PREEMPTION_TIMER;
1352}
1353
155a97a3
NHE
1354static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1355{
1356 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1357}
1358
81dc01f7
WL
1359static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1360{
1361 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1362 vmx_xsaves_supported();
1363}
1364
c5f983f6
BD
1365static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1366{
1367 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1368}
1369
f2b93280
WV
1370static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1371{
1372 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1373}
1374
5c614b35
WL
1375static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1376{
1377 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1378}
1379
82f0dd4b
WV
1380static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1381{
1382 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1383}
1384
608406e2
WV
1385static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1386{
1387 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1388}
1389
705699a1
WV
1390static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1391{
1392 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1393}
1394
ef85b673 1395static inline bool is_nmi(u32 intr_info)
644d711a
NHE
1396{
1397 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
ef85b673 1398 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
644d711a
NHE
1399}
1400
533558bc
JK
1401static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1402 u32 exit_intr_info,
1403 unsigned long exit_qualification);
7c177938
NHE
1404static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1405 struct vmcs12 *vmcs12,
1406 u32 reason, unsigned long qualification);
1407
8b9cf98c 1408static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK
1409{
1410 int i;
1411
a2fa3e9f 1412 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1413 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED
1414 return i;
1415 return -1;
1416}
1417
2384d2b3
SY
1418static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1419{
1420 struct {
1421 u64 vpid : 16;
1422 u64 rsvd : 48;
1423 u64 gva;
1424 } operand = { vpid, 0, gva };
1425
4ecac3fd 1426 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY
1427 /* CF==1 or ZF==1 --> rc = -1 */
1428 "; ja 1f ; ud2 ; 1:"
1429 : : "a"(&operand), "c"(ext) : "cc", "memory");
1430}
1431
1439442c
SY
1432static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1433{
1434 struct {
1435 u64 eptp, gpa;
1436 } operand = {eptp, gpa};
1437
4ecac3fd 1438 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY
1439 /* CF==1 or ZF==1 --> rc = -1 */
1440 "; ja 1f ; ud2 ; 1:\n"
1441 : : "a" (&operand), "c" (ext) : "cc", "memory");
1442}
1443
26bb0981 1444static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED
1445{
1446 int i;
1447
8b9cf98c 1448 i = __find_msr_index(vmx, msr);
a75beee6 1449 if (i >= 0)
a2fa3e9f 1450 return &vmx->guest_msrs[i];
8b6d44c7 1451 return NULL;
7725f0ba
AK
1452}
1453
6aa8b732
AK
1454static void vmcs_clear(struct vmcs *vmcs)
1455{
1456 u64 phys_addr = __pa(vmcs);
1457 u8 error;
1458
4ecac3fd 1459 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1460 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK
1461 : "cc", "memory");
1462 if (error)
1463 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1464 vmcs, phys_addr);
1465}
1466
d462b819
NHE
1467static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1468{
1469 vmcs_clear(loaded_vmcs->vmcs);
355f4fb1
JM
1470 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1471 vmcs_clear(loaded_vmcs->shadow_vmcs);
d462b819
NHE
1472 loaded_vmcs->cpu = -1;
1473 loaded_vmcs->launched = 0;
1474}
1475
7725b894
DX
1476static void vmcs_load(struct vmcs *vmcs)
1477{
1478 u64 phys_addr = __pa(vmcs);
1479 u8 error;
1480
1481 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1482 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX
1483 : "cc", "memory");
1484 if (error)
2844d849 1485 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX
1486 vmcs, phys_addr);
1487}
1488
2965faa5 1489#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY
1490/*
1491 * This bitmap is used to indicate whether the vmclear
1492 * operation is enabled on all cpus. All disabled by
1493 * default.
1494 */
1495static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1496
1497static inline void crash_enable_local_vmclear(int cpu)
1498{
1499 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1500}
1501
1502static inline void crash_disable_local_vmclear(int cpu)
1503{
1504 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1505}
1506
1507static inline int crash_local_vmclear_enabled(int cpu)
1508{
1509 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1510}
1511
1512static void crash_vmclear_local_loaded_vmcss(void)
1513{
1514 int cpu = raw_smp_processor_id();
1515 struct loaded_vmcs *v;
1516
1517 if (!crash_local_vmclear_enabled(cpu))
1518 return;
1519
1520 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1521 loaded_vmcss_on_cpu_link)
1522 vmcs_clear(v->vmcs);
1523}
1524#else
1525static inline void crash_enable_local_vmclear(int cpu) { }
1526static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1527#endif /* CONFIG_KEXEC_CORE */
8f536b76 1528
d462b819 1529static void __loaded_vmcs_clear(void *arg)
6aa8b732 1530{
d462b819 1531 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1532 int cpu = raw_smp_processor_id();
6aa8b732 1533
d462b819
NHE
1534 if (loaded_vmcs->cpu != cpu)
1535 return; /* vcpu migration can race with cpu offline */
1536 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1537 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1538 crash_disable_local_vmclear(cpu);
d462b819 1539 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG
1540
1541 /*
1542 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1543 * is before setting loaded_vmcs->vcpu to -1 which is done in
1544 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1545 * then adds the vmcs into percpu list before it is deleted.
1546 */
1547 smp_wmb();
1548
d462b819 1549 loaded_vmcs_init(loaded_vmcs);
8f536b76 1550 crash_enable_local_vmclear(cpu);
6aa8b732
AK
1551}
1552
d462b819 1553static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1554{
e6c7d321
XG
1555 int cpu = loaded_vmcs->cpu;
1556
1557 if (cpu != -1)
1558 smp_call_function_single(cpu,
1559 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK
1560}
1561
dd5f5341 1562static inline void vpid_sync_vcpu_single(int vpid)
2384d2b3 1563{
dd5f5341 1564 if (vpid == 0)
2384d2b3
SY
1565 return;
1566
518c8aee 1567 if (cpu_has_vmx_invvpid_single())
dd5f5341 1568 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
2384d2b3
SY
1569}
1570
b9d762fa
GJ
1571static inline void vpid_sync_vcpu_global(void)
1572{
1573 if (cpu_has_vmx_invvpid_global())
1574 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1575}
1576
dd5f5341 1577static inline void vpid_sync_context(int vpid)
b9d762fa
GJ
1578{
1579 if (cpu_has_vmx_invvpid_single())
dd5f5341 1580 vpid_sync_vcpu_single(vpid);
b9d762fa
GJ
1581 else
1582 vpid_sync_vcpu_global();
1583}
1584
1439442c
SY
1585static inline void ept_sync_global(void)
1586{
1587 if (cpu_has_vmx_invept_global())
1588 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1589}
1590
1591static inline void ept_sync_context(u64 eptp)
1592{
089d034e 1593 if (enable_ept) {
1439442c
SY
1594 if (cpu_has_vmx_invept_context())
1595 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1596 else
1597 ept_sync_global();
1598 }
1599}
1600
8a86aea9
PB
1601static __always_inline void vmcs_check16(unsigned long field)
1602{
1603 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1604 "16-bit accessor invalid for 64-bit field");
1605 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1606 "16-bit accessor invalid for 64-bit high field");
1607 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1608 "16-bit accessor invalid for 32-bit high field");
1609 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1610 "16-bit accessor invalid for natural width field");
1611}
1612
1613static __always_inline void vmcs_check32(unsigned long field)
1614{
1615 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1616 "32-bit accessor invalid for 16-bit field");
1617 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1618 "32-bit accessor invalid for natural width field");
1619}
1620
1621static __always_inline void vmcs_check64(unsigned long field)
1622{
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1624 "64-bit accessor invalid for 16-bit field");
1625 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1626 "64-bit accessor invalid for 64-bit high field");
1627 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1628 "64-bit accessor invalid for 32-bit field");
1629 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1630 "64-bit accessor invalid for natural width field");
1631}
1632
1633static __always_inline void vmcs_checkl(unsigned long field)
1634{
1635 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1636 "Natural width accessor invalid for 16-bit field");
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1638 "Natural width accessor invalid for 64-bit field");
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1640 "Natural width accessor invalid for 64-bit high field");
1641 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1642 "Natural width accessor invalid for 32-bit field");
1643}
1644
1645static __always_inline unsigned long __vmcs_readl(unsigned long field)
6aa8b732 1646{
5e520e62 1647 unsigned long value;
6aa8b732 1648
5e520e62
AK
1649 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1650 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK
1651 return value;
1652}
1653
96304217 1654static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732 1655{
8a86aea9
PB
1656 vmcs_check16(field);
1657 return __vmcs_readl(field);
6aa8b732
AK
1658}
1659
96304217 1660static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732 1661{
8a86aea9
PB
1662 vmcs_check32(field);
1663 return __vmcs_readl(field);
6aa8b732
AK
1664}
1665
96304217 1666static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1667{
8a86aea9 1668 vmcs_check64(field);
05b3e0c2 1669#ifdef CONFIG_X86_64
8a86aea9 1670 return __vmcs_readl(field);
6aa8b732 1671#else
8a86aea9 1672 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
6aa8b732
AK
1673#endif
1674}
1675
8a86aea9
PB
1676static __always_inline unsigned long vmcs_readl(unsigned long field)
1677{
1678 vmcs_checkl(field);
1679 return __vmcs_readl(field);
1680}
1681
e52de1b8
AK
1682static noinline void vmwrite_error(unsigned long field, unsigned long value)
1683{
1684 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1685 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1686 dump_stack();
1687}
1688
8a86aea9 1689static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
6aa8b732
AK
1690{
1691 u8 error;
1692
4ecac3fd 1693 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1694 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK
1695 if (unlikely(error))
1696 vmwrite_error(field, value);
6aa8b732
AK
1697}
1698
8a86aea9 1699static __always_inline void vmcs_write16(unsigned long field, u16 value)
6aa8b732 1700{
8a86aea9
PB
1701 vmcs_check16(field);
1702 __vmcs_writel(field, value);
6aa8b732
AK
1703}
1704
8a86aea9 1705static __always_inline void vmcs_write32(unsigned long field, u32 value)
6aa8b732 1706{
8a86aea9
PB
1707 vmcs_check32(field);
1708 __vmcs_writel(field, value);
6aa8b732
AK
1709}
1710
8a86aea9 1711static __always_inline void vmcs_write64(unsigned long field, u64 value)
6aa8b732 1712{
8a86aea9
PB
1713 vmcs_check64(field);
1714 __vmcs_writel(field, value);
7682f2d0 1715#ifndef CONFIG_X86_64
6aa8b732 1716 asm volatile ("");
8a86aea9 1717 __vmcs_writel(field+1, value >> 32);
6aa8b732
AK
1718#endif
1719}
1720
8a86aea9 1721static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2ab455cc 1722{
8a86aea9
PB
1723 vmcs_checkl(field);
1724 __vmcs_writel(field, value);
2ab455cc
AL
1725}
1726
8a86aea9 1727static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2ab455cc 1728{
8a86aea9
PB
1729 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1730 "vmcs_clear_bits does not support 64-bit fields");
1731 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2ab455cc
AL
1732}
1733
8a86aea9 1734static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2ab455cc 1735{
8a86aea9
PB
1736 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1737 "vmcs_set_bits does not support 64-bit fields");
1738 __vmcs_writel(field, __vmcs_readl(field) | mask);
2ab455cc
AL
1739}
1740
8391ce44
PB
1741static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1742{
1743 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1744}
1745
2961e876
GN
1746static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1747{
1748 vmcs_write32(VM_ENTRY_CONTROLS, val);
1749 vmx->vm_entry_controls_shadow = val;
1750}
1751
1752static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1753{
1754 if (vmx->vm_entry_controls_shadow != val)
1755 vm_entry_controls_init(vmx, val);
1756}
1757
1758static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1759{
1760 return vmx->vm_entry_controls_shadow;
1761}
1762
1763
1764static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1765{
1766 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1767}
1768
1769static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1770{
1771 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1772}
1773
8391ce44
PB
1774static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1775{
1776 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1777}
1778
2961e876
GN
1779static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1780{
1781 vmcs_write32(VM_EXIT_CONTROLS, val);
1782 vmx->vm_exit_controls_shadow = val;
1783}
1784
1785static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1786{
1787 if (vmx->vm_exit_controls_shadow != val)
1788 vm_exit_controls_init(vmx, val);
1789}
1790
1791static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1792{
1793 return vmx->vm_exit_controls_shadow;
1794}
1795
1796
1797static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1798{
1799 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1800}
1801
1802static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1803{
1804 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1805}
1806
2fb92db1
AK
1807static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1808{
1809 vmx->segment_cache.bitmask = 0;
1810}
1811
1812static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1813 unsigned field)
1814{
1815 bool ret;
1816 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1817
1818 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1819 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1820 vmx->segment_cache.bitmask = 0;
1821 }
1822 ret = vmx->segment_cache.bitmask & mask;
1823 vmx->segment_cache.bitmask |= mask;
1824 return ret;
1825}
1826
1827static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1828{
1829 u16 *p = &vmx->segment_cache.seg[seg].selector;
1830
1831 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1832 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1833 return *p;
1834}
1835
1836static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1837{
1838 ulong *p = &vmx->segment_cache.seg[seg].base;
1839
1840 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1841 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1842 return *p;
1843}
1844
1845static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1846{
1847 u32 *p = &vmx->segment_cache.seg[seg].limit;
1848
1849 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1850 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1851 return *p;
1852}
1853
1854static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1855{
1856 u32 *p = &vmx->segment_cache.seg[seg].ar;
1857
1858 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1859 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1860 return *p;
1861}
1862
abd3f2d6
AK
1863static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1864{
1865 u32 eb;
1866
fd7373cc 1867 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 1868 (1u << DB_VECTOR) | (1u << AC_VECTOR);
fd7373cc
JK
1869 if ((vcpu->guest_debug &
1870 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1871 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1872 eb |= 1u << BP_VECTOR;
7ffd92c5 1873 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1874 eb = ~0;
089d034e 1875 if (enable_ept)
1439442c 1876 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE
1877
1878 /* When we are running a nested L2 guest and L1 specified for it a
1879 * certain exception bitmap, we must trap the same exceptions and pass
1880 * them to L1. When running L2, we will only handle the exceptions
1881 * specified above if L1 did not want them.
1882 */
1883 if (is_guest_mode(vcpu))
1884 eb |= get_vmcs12(vcpu)->exception_bitmap;
1885
abd3f2d6
AK
1886 vmcs_write32(EXCEPTION_BITMAP, eb);
1887}
1888
2961e876
GN
1889static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1890 unsigned long entry, unsigned long exit)
8bf00a52 1891{
2961e876
GN
1892 vm_entry_controls_clearbit(vmx, entry);
1893 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN
1894}
1895
61d2ef2c
AK
1896static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1897{
1898 unsigned i;
1899 struct msr_autoload *m = &vmx->msr_autoload;
1900
8bf00a52
GN
1901 switch (msr) {
1902 case MSR_EFER:
1903 if (cpu_has_load_ia32_efer) {
2961e876
GN
1904 clear_atomic_switch_msr_special(vmx,
1905 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN
1906 VM_EXIT_LOAD_IA32_EFER);
1907 return;
1908 }
1909 break;
1910 case MSR_CORE_PERF_GLOBAL_CTRL:
1911 if (cpu_has_load_perf_global_ctrl) {
2961e876 1912 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN
1913 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1914 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1915 return;
1916 }
1917 break;
110312c8
AK
1918 }
1919
61d2ef2c
AK
1920 for (i = 0; i < m->nr; ++i)
1921 if (m->guest[i].index == msr)
1922 break;
1923
1924 if (i == m->nr)
1925 return;
1926 --m->nr;
1927 m->guest[i] = m->guest[m->nr];
1928 m->host[i] = m->host[m->nr];
1929 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1930 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1931}
1932
2961e876
GN
1933static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1934 unsigned long entry, unsigned long exit,
1935 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1936 u64 guest_val, u64 host_val)
8bf00a52
GN
1937{
1938 vmcs_write64(guest_val_vmcs, guest_val);
1939 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN
1940 vm_entry_controls_setbit(vmx, entry);
1941 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN
1942}
1943
61d2ef2c
AK
1944static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1945 u64 guest_val, u64 host_val)
1946{
1947 unsigned i;
1948 struct msr_autoload *m = &vmx->msr_autoload;
1949
8bf00a52
GN
1950 switch (msr) {
1951 case MSR_EFER:
1952 if (cpu_has_load_ia32_efer) {
2961e876
GN
1953 add_atomic_switch_msr_special(vmx,
1954 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN
1955 VM_EXIT_LOAD_IA32_EFER,
1956 GUEST_IA32_EFER,
1957 HOST_IA32_EFER,
1958 guest_val, host_val);
1959 return;
1960 }
1961 break;
1962 case MSR_CORE_PERF_GLOBAL_CTRL:
1963 if (cpu_has_load_perf_global_ctrl) {
2961e876 1964 add_atomic_switch_msr_special(vmx,
8bf00a52
GN
1965 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1966 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1967 GUEST_IA32_PERF_GLOBAL_CTRL,
1968 HOST_IA32_PERF_GLOBAL_CTRL,
1969 guest_val, host_val);
1970 return;
1971 }
1972 break;
7099e2e1
RK
1973 case MSR_IA32_PEBS_ENABLE:
1974 /* PEBS needs a quiescent period after being disabled (to write
1975 * a record). Disabling PEBS through VMX MSR swapping doesn't
1976 * provide that period, so a CPU could write host's record into
1977 * guest's memory.
1978 */
1979 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK
1980 }
1981
61d2ef2c
AK
1982 for (i = 0; i < m->nr; ++i)
1983 if (m->guest[i].index == msr)
1984 break;
1985
e7fc6f93 1986 if (i == NR_AUTOLOAD_MSRS) {
60266204 1987 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN
1988 "Can't add msr %x\n", msr);
1989 return;
1990 } else if (i == m->nr) {
61d2ef2c
AK
1991 ++m->nr;
1992 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1993 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1994 }
1995
1996 m->guest[i].index = msr;
1997 m->guest[i].value = guest_val;
1998 m->host[i].index = msr;
1999 m->host[i].value = host_val;
2000}
2001
92c0d900 2002static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 2003{
844a5fe2
PB
2004 u64 guest_efer = vmx->vcpu.arch.efer;
2005 u64 ignore_bits = 0;
2006
2007 if (!enable_ept) {
2008 /*
2009 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2010 * host CPUID is more efficient than testing guest CPUID
2011 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2012 */
2013 if (boot_cpu_has(X86_FEATURE_SMEP))
2014 guest_efer |= EFER_NX;
2015 else if (!(guest_efer & EFER_NX))
2016 ignore_bits |= EFER_NX;
2017 }
3a34a881 2018
51c6cf66 2019 /*
844a5fe2 2020 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 2021 */
844a5fe2 2022 ignore_bits |= EFER_SCE;
51c6cf66
AK
2023#ifdef CONFIG_X86_64
2024 ignore_bits |= EFER_LMA | EFER_LME;
2025 /* SCE is meaningful only in long mode on Intel */
2026 if (guest_efer & EFER_LMA)
2027 ignore_bits &= ~(u64)EFER_SCE;
2028#endif
84ad33ef
AK
2029
2030 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL
2031
2032 /*
2033 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2034 * On CPUs that support "load IA32_EFER", always switch EFER
2035 * atomically, since it's faster than switching it manually.
2036 */
2037 if (cpu_has_load_ia32_efer ||
2038 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK
2039 if (!(guest_efer & EFER_LMA))
2040 guest_efer &= ~EFER_LME;
54b98bff
AL
2041 if (guest_efer != host_efer)
2042 add_atomic_switch_msr(vmx, MSR_EFER,
2043 guest_efer, host_efer);
84ad33ef 2044 return false;
844a5fe2
PB
2045 } else {
2046 guest_efer &= ~ignore_bits;
2047 guest_efer |= host_efer & ignore_bits;
2048
2049 vmx->guest_msrs[efer_offset].data = guest_efer;
2050 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 2051
844a5fe2
PB
2052 return true;
2053 }
51c6cf66
AK
2054}
2055
e28baead
AL
2056#ifdef CONFIG_X86_32
2057/*
2058 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2059 * VMCS rather than the segment table. KVM uses this helper to figure
2060 * out the current bases to poke them into the VMCS before entry.
2061 */
2d49ec72
GN
2062static unsigned long segment_base(u16 selector)
2063{
8c2e41f7 2064 struct desc_struct *table;
2d49ec72
GN
2065 unsigned long v;
2066
8c2e41f7 2067 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN
2068 return 0;
2069
45fc8757 2070 table = get_current_gdt_ro();
2d49ec72 2071
8c2e41f7 2072 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN
2073 u16 ldt_selector = kvm_read_ldt();
2074
8c2e41f7 2075 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN
2076 return 0;
2077
8c2e41f7 2078 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 2079 }
8c2e41f7 2080 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN
2081 return v;
2082}
e28baead 2083#endif
2d49ec72 2084
04d2cc77 2085static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 2086{
04d2cc77 2087 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2088 int i;
04d2cc77 2089
a2fa3e9f 2090 if (vmx->host_state.loaded)
33ed6329
AK
2091 return;
2092
a2fa3e9f 2093 vmx->host_state.loaded = 1;
33ed6329
AK
2094 /*
2095 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2096 * allow segment selectors with cpl > 0 or ti == 1.
2097 */
d6e88aec 2098 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 2099 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 2100 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 2101 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 2102 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV
2103 vmx->host_state.fs_reload_needed = 0;
2104 } else {
33ed6329 2105 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 2106 vmx->host_state.fs_reload_needed = 1;
33ed6329 2107 }
9581d442 2108 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH
2109 if (!(vmx->host_state.gs_sel & 7))
2110 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK
2111 else {
2112 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 2113 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK
2114 }
2115
b2da15ac
AK
2116#ifdef CONFIG_X86_64
2117 savesegment(ds, vmx->host_state.ds_sel);
2118 savesegment(es, vmx->host_state.es_sel);
2119#endif
2120
33ed6329
AK
2121#ifdef CONFIG_X86_64
2122 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2123 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2124#else
a2fa3e9f
GH
2125 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2126 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 2127#endif
707c0874
AK
2128
2129#ifdef CONFIG_X86_64
c8770e7b
AK
2130 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2131 if (is_long_mode(&vmx->vcpu))
44ea2b17 2132 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 2133#endif
da8999d3
LJ
2134 if (boot_cpu_has(X86_FEATURE_MPX))
2135 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK
2136 for (i = 0; i < vmx->save_nmsrs; ++i)
2137 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK
2138 vmx->guest_msrs[i].data,
2139 vmx->guest_msrs[i].mask);
33ed6329
AK
2140}
2141
a9b21b62 2142static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 2143{
a2fa3e9f 2144 if (!vmx->host_state.loaded)
33ed6329
AK
2145 return;
2146
e1beb1d3 2147 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 2148 vmx->host_state.loaded = 0;
c8770e7b
AK
2149#ifdef CONFIG_X86_64
2150 if (is_long_mode(&vmx->vcpu))
2151 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2152#endif
152d3f2f 2153 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 2154 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 2155#ifdef CONFIG_X86_64
9581d442 2156 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK
2157#else
2158 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 2159#endif
33ed6329 2160 }
0a77fe4c
AK
2161 if (vmx->host_state.fs_reload_needed)
2162 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK
2163#ifdef CONFIG_X86_64
2164 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2165 loadsegment(ds, vmx->host_state.ds_sel);
2166 loadsegment(es, vmx->host_state.es_sel);
2167 }
b2da15ac 2168#endif
b7ffc44d 2169 invalidate_tss_limit();
44ea2b17 2170#ifdef CONFIG_X86_64
c8770e7b 2171 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 2172#endif
da8999d3
LJ
2173 if (vmx->host_state.msr_host_bndcfgs)
2174 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
45fc8757 2175 load_fixmap_gdt(raw_smp_processor_id());
33ed6329
AK
2176}
2177
a9b21b62
AK
2178static void vmx_load_host_state(struct vcpu_vmx *vmx)
2179{
2180 preempt_disable();
2181 __vmx_load_host_state(vmx);
2182 preempt_enable();
2183}
2184
28b835d6
FW
2185static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2186{
2187 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2188 struct pi_desc old, new;
2189 unsigned int dest;
2190
2191 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
2192 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2193 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW
2194 return;
2195
2196 do {
2197 old.control = new.control = pi_desc->control;
2198
2199 /*
2200 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2201 * are two possible cases:
2202 * 1. After running 'pre_block', context switch
2203 * happened. For this case, 'sn' was set in
2204 * vmx_vcpu_put(), so we need to clear it here.
2205 * 2. After running 'pre_block', we were blocked,
2206 * and woken up by some other guy. For this case,
2207 * we don't need to do anything, 'pi_post_block'
2208 * will do everything for us. However, we cannot
2209 * check whether it is case #1 or case #2 here
2210 * (maybe, not needed), so we also clear sn here,
2211 * I think it is not a big deal.
2212 */
2213 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2214 if (vcpu->cpu != cpu) {
2215 dest = cpu_physical_id(cpu);
2216
2217 if (x2apic_enabled())
2218 new.ndst = dest;
2219 else
2220 new.ndst = (dest << 8) & 0xFF00;
2221 }
2222
2223 /* set 'NV' to 'notification vector' */
2224 new.nv = POSTED_INTR_VECTOR;
2225 }
2226
2227 /* Allow posting non-urgent interrupts */
2228 new.sn = 0;
2229 } while (cmpxchg(&pi_desc->control, old.control,
2230 new.control) != old.control);
2231}
1be0e61c 2232
c95ba92a
PF
2233static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2234{
2235 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2236 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2237}
2238
6aa8b732
AK
2239/*
2240 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2241 * vcpu mutex is already taken.
2242 */
15ad7146 2243static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 2244{
a2fa3e9f 2245 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 2246 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 2247
b80c76ec 2248 if (!already_loaded) {
fe0e80be 2249 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 2250 local_irq_disable();
8f536b76 2251 crash_disable_local_vmclear(cpu);
5a560f8b
XG
2252
2253 /*
2254 * Read loaded_vmcs->cpu should be before fetching
2255 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2256 * See the comments in __loaded_vmcs_clear().
2257 */
2258 smp_rmb();
2259
d462b819
NHE
2260 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2261 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 2262 crash_enable_local_vmclear(cpu);
92fe13be 2263 local_irq_enable();
b80c76ec
JM
2264 }
2265
2266 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2267 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2268 vmcs_load(vmx->loaded_vmcs->vmcs);
2269 }
2270
2271 if (!already_loaded) {
59c58ceb 2272 void *gdt = get_current_gdt_ro();
b80c76ec
JM
2273 unsigned long sysenter_esp;
2274
2275 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 2276
6aa8b732
AK
2277 /*
2278 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 2279 * processors. See 22.2.4.
6aa8b732 2280 */
e0c23063
AL
2281 vmcs_writel(HOST_TR_BASE,
2282 (unsigned long)this_cpu_ptr(&cpu_tss));
59c58ceb 2283 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732 2284
b7ffc44d
AL
2285 /*
2286 * VM exits change the host TR limit to 0x67 after a VM
2287 * exit. This is okay, since 0x67 covers everything except
2288 * the IO bitmap and have have code to handle the IO bitmap
2289 * being lost after a VM exit.
2290 */
2291 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2292
6aa8b732
AK
2293 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2294 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 2295
d462b819 2296 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 2297 }
28b835d6 2298
2680d6da
OH
2299 /* Setup TSC multiplier */
2300 if (kvm_has_tsc_control &&
c95ba92a
PF
2301 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2302 decache_tsc_multiplier(vmx);
2680d6da 2303
28b835d6 2304 vmx_vcpu_pi_load(vcpu, cpu);
1be0e61c 2305 vmx->host_pkru = read_pkru();
28b835d6
FW
2306}
2307
2308static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2309{
2310 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2311
2312 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
2313 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2314 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW
2315 return;
2316
2317 /* Set SN when the vCPU is preempted */
2318 if (vcpu->preempted)
2319 pi_set_sn(pi_desc);
6aa8b732
AK
2320}
2321
2322static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2323{
28b835d6
FW
2324 vmx_vcpu_pi_put(vcpu);
2325
a9b21b62 2326 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK
2327}
2328
f244deed
WL
2329static bool emulation_required(struct kvm_vcpu *vcpu)
2330{
2331 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2332}
2333
edcafe3c
AK
2334static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2335
fe3ef05c
NHE
2336/*
2337 * Return the cr0 value that a nested guest would read. This is a combination
2338 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2339 * its hypervisor (cr0_read_shadow).
2340 */
2341static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2342{
2343 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2344 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2345}
2346static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2347{
2348 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2349 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2350}
2351
6aa8b732
AK
2352static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2353{
78ac8b47 2354 unsigned long rflags, save_rflags;
345dcaa8 2355
6de12732
AK
2356 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2357 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2358 rflags = vmcs_readl(GUEST_RFLAGS);
2359 if (to_vmx(vcpu)->rmode.vm86_active) {
2360 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2361 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2362 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2363 }
2364 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2365 }
6de12732 2366 return to_vmx(vcpu)->rflags;
6aa8b732
AK
2367}
2368
2369static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2370{
f244deed
WL
2371 unsigned long old_rflags = vmx_get_rflags(vcpu);
2372
6de12732
AK
2373 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2374 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK
2375 if (to_vmx(vcpu)->rmode.vm86_active) {
2376 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2377 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2378 }
6aa8b732 2379 vmcs_writel(GUEST_RFLAGS, rflags);
f244deed
WL
2380
2381 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2382 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
6aa8b732
AK
2383}
2384
be94f6b7
HH
2385static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2386{
2387 return to_vmx(vcpu)->guest_pkru;
2388}
2389
37ccdcbe 2390static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC
2391{
2392 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2393 int ret = 0;
2394
2395 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2396 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2397 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2398 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2399
37ccdcbe 2400 return ret;
2809f5d2
GC
2401}
2402
2403static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2404{
2405 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2406 u32 interruptibility = interruptibility_old;
2407
2408 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2409
48005f64 2410 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2411 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2412 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC
2413 interruptibility |= GUEST_INTR_STATE_STI;
2414
2415 if ((interruptibility != interruptibility_old))
2416 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2417}
2418
6aa8b732
AK
2419static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2420{
2421 unsigned long rip;
6aa8b732 2422
5fdbf976 2423 rip = kvm_rip_read(vcpu);
6aa8b732 2424 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2425 kvm_rip_write(vcpu, rip);
6aa8b732 2426
2809f5d2
GC
2427 /* skipping an emulated instruction also counts */
2428 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK
2429}
2430
0b6ac343
NHE
2431/*
2432 * KVM wants to inject page-faults which it got to the guest. This function
2433 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2434 */
adfe20fb 2435static int nested_vmx_check_exception(struct kvm_vcpu *vcpu)
0b6ac343
NHE
2436{
2437 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
adfe20fb 2438 unsigned int nr = vcpu->arch.exception.nr;
0b6ac343 2439
adfe20fb
WL
2440 if (!((vmcs12->exception_bitmap & (1u << nr)) ||
2441 (nr == PF_VECTOR && vcpu->arch.exception.nested_apf)))
0b6ac343
NHE
2442 return 0;
2443
adfe20fb
WL
2444 if (vcpu->arch.exception.nested_apf) {
2445 vmcs_write32(VM_EXIT_INTR_ERROR_CODE, vcpu->arch.exception.error_code);
2446 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
2447 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
2448 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
2449 vcpu->arch.apf.nested_apf_token);
2450 return 1;
2451 }
2452
d4912215 2453 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
533558bc
JK
2454 vmcs_read32(VM_EXIT_INTR_INFO),
2455 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE
2456 return 1;
2457}
2458
cfcd20e5 2459static void vmx_queue_exception(struct kvm_vcpu *vcpu)
298101da 2460{
77ab6db0 2461 struct vcpu_vmx *vmx = to_vmx(vcpu);
cfcd20e5
WL
2462 unsigned nr = vcpu->arch.exception.nr;
2463 bool has_error_code = vcpu->arch.exception.has_error_code;
2464 bool reinject = vcpu->arch.exception.reinject;
2465 u32 error_code = vcpu->arch.exception.error_code;
8ab2d2e2 2466 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2467
e011c663 2468 if (!reinject && is_guest_mode(vcpu) &&
adfe20fb 2469 nested_vmx_check_exception(vcpu))
0b6ac343
NHE
2470 return;
2471
8ab2d2e2 2472 if (has_error_code) {
77ab6db0 2473 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK
2474 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2475 }
77ab6db0 2476
7ffd92c5 2477 if (vmx->rmode.vm86_active) {
71f9833b
SH
2478 int inc_eip = 0;
2479 if (kvm_exception_is_soft(nr))
2480 inc_eip = vcpu->arch.event_exit_inst_len;
2481 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2482 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK
2483 return;
2484 }
2485
66fd3f7f
GN
2486 if (kvm_exception_is_soft(nr)) {
2487 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2488 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK
2489 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2490 } else
2491 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2492
2493 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK
2494}
2495
4e47c7a6
SY
2496static bool vmx_rdtscp_supported(void)
2497{
2498 return cpu_has_vmx_rdtscp();
2499}
2500
ad756a16
MJ
2501static bool vmx_invpcid_supported(void)
2502{
2503 return cpu_has_vmx_invpcid() && enable_ept;
2504}
2505
a75beee6
ED
2506/*
2507 * Swap MSR entry in host/guest MSR entry array.
2508 */
8b9cf98c 2509static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2510{
26bb0981 2511 struct shared_msr_entry tmp;
a2fa3e9f
GH
2512
2513 tmp = vmx->guest_msrs[to];
2514 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2515 vmx->guest_msrs[from] = tmp;
a75beee6
ED
2516}
2517
8d14695f
YZ
2518static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2519{
2520 unsigned long *msr_bitmap;
2521
670125bd 2522 if (is_guest_mode(vcpu))
d048c098 2523 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
3ce424e4
RK
2524 else if (cpu_has_secondary_exec_ctrls() &&
2525 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2526 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
f6e90f9e
WL
2527 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2528 if (is_long_mode(vcpu))
c63e4563 2529 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
f6e90f9e 2530 else
c63e4563 2531 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
f6e90f9e
WL
2532 } else {
2533 if (is_long_mode(vcpu))
c63e4563 2534 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
f6e90f9e 2535 else
c63e4563 2536 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
f6e90f9e 2537 }
8d14695f
YZ
2538 } else {
2539 if (is_long_mode(vcpu))
2540 msr_bitmap = vmx_msr_bitmap_longmode;
2541 else
2542 msr_bitmap = vmx_msr_bitmap_legacy;
2543 }
2544
2545 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2546}
2547
e38aea3e
AK
2548/*
2549 * Set up the vmcs to automatically save and restore system
2550 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2551 * mode, as fiddling with msrs is very expensive.
2552 */
8b9cf98c 2553static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2554{
26bb0981 2555 int save_nmsrs, index;
e38aea3e 2556
a75beee6
ED
2557 save_nmsrs = 0;
2558#ifdef CONFIG_X86_64
8b9cf98c 2559 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2560 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2561 if (index >= 0)
8b9cf98c
RR
2562 move_msr_up(vmx, index, save_nmsrs++);
2563 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2564 if (index >= 0)
8b9cf98c
RR
2565 move_msr_up(vmx, index, save_nmsrs++);
2566 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2567 if (index >= 0)
8b9cf98c 2568 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6 2569 index = __find_msr_index(vmx, MSR_TSC_AUX);
1cea0ce6 2570 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
4e47c7a6 2571 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2572 /*
8c06585d 2573 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED
2574 * if efer.sce is enabled.
2575 */
8c06585d 2576 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2577 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2578 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED
2579 }
2580#endif
92c0d900
AK
2581 index = __find_msr_index(vmx, MSR_EFER);
2582 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2583 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2584
26bb0981 2585 vmx->save_nmsrs = save_nmsrs;
5897297b 2586
8d14695f
YZ
2587 if (cpu_has_vmx_msr_bitmap())
2588 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK
2589}
2590
6aa8b732
AK
2591/*
2592 * reads and returns guest's timestamp counter "register"
be7b263e
HZ
2593 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2594 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
6aa8b732 2595 */
be7b263e 2596static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
6aa8b732
AK
2597{
2598 u64 host_tsc, tsc_offset;
2599
4ea1636b 2600 host_tsc = rdtsc();
6aa8b732 2601 tsc_offset = vmcs_read64(TSC_OFFSET);
be7b263e 2602 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
6aa8b732
AK
2603}
2604
2605/*
99e3e30a 2606 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2607 */
99e3e30a 2608static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2609{
27fc51b2 2610 if (is_guest_mode(vcpu)) {
7991825b 2611 /*
27fc51b2
NHE
2612 * We're here if L1 chose not to trap WRMSR to TSC. According
2613 * to the spec, this should set L1's TSC; The offset that L1
2614 * set for L2 remains unchanged, and still needs to be added
2615 * to the newly set TSC to get L2's TSC.
7991825b 2616 */
27fc51b2 2617 struct vmcs12 *vmcs12;
27fc51b2
NHE
2618 /* recalculate vmcs02.TSC_OFFSET: */
2619 vmcs12 = get_vmcs12(vcpu);
2620 vmcs_write64(TSC_OFFSET, offset +
2621 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2622 vmcs12->tsc_offset : 0));
2623 } else {
489223ed
YY
2624 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2625 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE
2626 vmcs_write64(TSC_OFFSET, offset);
2627 }
6aa8b732
AK
2628}
2629
801d3424
NHE
2630static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2631{
2632 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2633 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2634}
2635
2636/*
2637 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2638 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2639 * all guests if the "nested" module option is off, and can also be disabled
2640 * for a single guest by disabling its VMX cpuid bit.
2641 */
2642static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2643{
2644 return nested && guest_cpuid_has_vmx(vcpu);
2645}
2646
b87a51ae
NHE
2647/*
2648 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2649 * returned for the various VMX controls MSRs when nested VMX is enabled.
2650 * The same values should also be used to verify that vmcs12 control fields are
2651 * valid during nested entry from L1 to L2.
2652 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2653 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2654 * bit in the high half is on if the corresponding bit in the control field
2655 * may be on. See also vmx_control_verify().
b87a51ae 2656 */
b9c237bb 2657static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE
2658{
2659 /*
2660 * Note that as a general rule, the high half of the MSRs (bits in
2661 * the control fields which may be 1) should be initialized by the
2662 * intersection of the underlying hardware's MSR (i.e., features which
2663 * can be supported) and the list of features we want to expose -
2664 * because they are known to be properly supported in our code.
2665 * Also, usually, the low half of the MSRs (bits which must be 1) can
2666 * be set to 0, meaning that L1 may turn off any of these bits. The
2667 * reason is that if one of these bits is necessary, it will appear
2668 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2669 * fields of vmcs01 and vmcs02, will turn these bits off - and
2670 * nested_vmx_exit_handled() will not pass related exits to L1.
2671 * These rules have exceptions below.
2672 */
2673
2674 /* pin-based controls */
eabeaacc 2675 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV
2676 vmx->nested.nested_vmx_pinbased_ctls_low,
2677 vmx->nested.nested_vmx_pinbased_ctls_high);
2678 vmx->nested.nested_vmx_pinbased_ctls_low |=
2679 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2680 vmx->nested.nested_vmx_pinbased_ctls_high &=
2681 PIN_BASED_EXT_INTR_MASK |
2682 PIN_BASED_NMI_EXITING |
2683 PIN_BASED_VIRTUAL_NMIS;
2684 vmx->nested.nested_vmx_pinbased_ctls_high |=
2685 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2686 PIN_BASED_VMX_PREEMPTION_TIMER;
d62caabb 2687 if (kvm_vcpu_apicv_active(&vmx->vcpu))
705699a1
WV
2688 vmx->nested.nested_vmx_pinbased_ctls_high |=
2689 PIN_BASED_POSTED_INTR;
b87a51ae 2690
3dbcd8da 2691 /* exit controls */
c0dfee58 2692 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV
2693 vmx->nested.nested_vmx_exit_ctls_low,
2694 vmx->nested.nested_vmx_exit_ctls_high);
2695 vmx->nested.nested_vmx_exit_ctls_low =
2696 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2697
b9c237bb 2698 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2699#ifdef CONFIG_X86_64
c0dfee58 2700 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2701#endif
f4124500 2702 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV
2703 vmx->nested.nested_vmx_exit_ctls_high |=
2704 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2705 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD
2706 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2707
a87036ad 2708 if (kvm_mpx_supported())
b9c237bb 2709 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2710
2996fca0 2711 /* We support free control of debug control saving. */
0115f9cb 2712 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2996fca0 2713
b87a51ae
NHE
2714 /* entry controls */
2715 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV
2716 vmx->nested.nested_vmx_entry_ctls_low,
2717 vmx->nested.nested_vmx_entry_ctls_high);
2718 vmx->nested.nested_vmx_entry_ctls_low =
2719 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2720 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK
2721#ifdef CONFIG_X86_64
2722 VM_ENTRY_IA32E_MODE |
2723#endif
2724 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV
2725 vmx->nested.nested_vmx_entry_ctls_high |=
2726 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
a87036ad 2727 if (kvm_mpx_supported())
b9c237bb 2728 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2729
2996fca0 2730 /* We support free control of debug control loading. */
0115f9cb 2731 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2996fca0 2732
b87a51ae
NHE
2733 /* cpu-based controls */
2734 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV
2735 vmx->nested.nested_vmx_procbased_ctls_low,
2736 vmx->nested.nested_vmx_procbased_ctls_high);
2737 vmx->nested.nested_vmx_procbased_ctls_low =
2738 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2739 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK
2740 CPU_BASED_VIRTUAL_INTR_PENDING |
2741 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE
2742 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2743 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2744 CPU_BASED_CR3_STORE_EXITING |
2745#ifdef CONFIG_X86_64
2746 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2747#endif
2748 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD
2749 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2750 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2751 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2752 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE
2753 /*
2754 * We can allow some features even when not supported by the
2755 * hardware. For example, L1 can specify an MSR bitmap - and we
2756 * can use it to avoid exits to L1 - even when L0 runs L2
2757 * without MSR bitmaps.
2758 */
b9c237bb
WV
2759 vmx->nested.nested_vmx_procbased_ctls_high |=
2760 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2761 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2762
3dcdf3ec 2763 /* We support free control of CR3 access interception. */
0115f9cb 2764 vmx->nested.nested_vmx_procbased_ctls_low &=
3dcdf3ec
JK
2765 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2766
b87a51ae
NHE
2767 /* secondary cpu-based controls */
2768 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV
2769 vmx->nested.nested_vmx_secondary_ctls_low,
2770 vmx->nested.nested_vmx_secondary_ctls_high);
2771 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2772 vmx->nested.nested_vmx_secondary_ctls_high &=
a5f46457 2773 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
d6851fbe 2774 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2775 SECONDARY_EXEC_RDTSCP |
1b07304c 2776 SECONDARY_EXEC_DESC |
f2b93280 2777 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2778 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2779 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7 2780 SECONDARY_EXEC_WBINVD_EXITING |
dfa169bb 2781 SECONDARY_EXEC_XSAVES;
c18911a2 2782
afa61f75
NHE
2783 if (enable_ept) {
2784 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2785 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2786 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2787 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
7db74265 2788 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
02120c45
BD
2789 if (cpu_has_vmx_ept_execute_only())
2790 vmx->nested.nested_vmx_ept_caps |=
2791 VMX_EPT_EXECUTE_ONLY_BIT;
b9c237bb 2792 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
45e11817 2793 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
7db74265
PB
2794 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2795 VMX_EPT_1GB_PAGE_BIT;
03efce6f
BD
2796 if (enable_ept_ad_bits) {
2797 vmx->nested.nested_vmx_secondary_ctls_high |=
2798 SECONDARY_EXEC_ENABLE_PML;
7461fbc4 2799 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
03efce6f 2800 }
afa61f75 2801 } else
b9c237bb 2802 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2803
ef697a71
PB
2804 /*
2805 * Old versions of KVM use the single-context version without
2806 * checking for support, so declare that it is supported even
2807 * though it is treated as global context. The alternative is
2808 * not failing the single-context invvpid, and it is worse.
2809 */
63cb6d5f
WL
2810 if (enable_vpid) {
2811 vmx->nested.nested_vmx_secondary_ctls_high |=
2812 SECONDARY_EXEC_ENABLE_VPID;
089d7b6e 2813 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
bcdde302 2814 VMX_VPID_EXTENT_SUPPORTED_MASK;
63cb6d5f 2815 } else
089d7b6e 2816 vmx->nested.nested_vmx_vpid_caps = 0;
99b83ac8 2817
0790ec17
RK
2818 if (enable_unrestricted_guest)
2819 vmx->nested.nested_vmx_secondary_ctls_high |=
2820 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2821
c18911a2 2822 /* miscellaneous data */
b9c237bb
WV
2823 rdmsr(MSR_IA32_VMX_MISC,
2824 vmx->nested.nested_vmx_misc_low,
2825 vmx->nested.nested_vmx_misc_high);
2826 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2827 vmx->nested.nested_vmx_misc_low |=
2828 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2829 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2830 vmx->nested.nested_vmx_misc_high = 0;
62cc6b9d
DM
2831
2832 /*
2833 * This MSR reports some information about VMX support. We
2834 * should return information about the VMX we emulate for the
2835 * guest, and the VMCS structure we give it - not about the
2836 * VMX support of the underlying hardware.
2837 */
2838 vmx->nested.nested_vmx_basic =
2839 VMCS12_REVISION |
2840 VMX_BASIC_TRUE_CTLS |
2841 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2842 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2843
2844 if (cpu_has_vmx_basic_inout())
2845 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2846
2847 /*
8322ebbb 2848 * These MSRs specify bits which the guest must keep fixed on
62cc6b9d
DM
2849 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2850 * We picked the standard core2 setting.
2851 */
2852#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2853#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2854 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
62cc6b9d 2855 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
8322ebbb
DM
2856
2857 /* These MSRs specify bits which the guest must keep fixed off. */
2858 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2859 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
62cc6b9d
DM
2860
2861 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2862 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
b87a51ae
NHE
2863}
2864
3899152c
DM
2865/*
2866 * if fixed0[i] == 1: val[i] must be 1
2867 * if fixed1[i] == 0: val[i] must be 0
2868 */
2869static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2870{
2871 return ((val & fixed1) | fixed0) == val;
b87a51ae
NHE
2872}
2873
2874static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2875{
3899152c 2876 return fixed_bits_valid(control, low, high);
b87a51ae
NHE
2877}
2878
2879static inline u64 vmx_control_msr(u32 low, u32 high)
2880{
2881 return low | ((u64)high << 32);
2882}
2883
62cc6b9d
DM
2884static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2885{
2886 superset &= mask;
2887 subset &= mask;
2888
2889 return (superset | subset) == superset;
2890}
2891
2892static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2893{
2894 const u64 feature_and_reserved =
2895 /* feature (except bit 48; see below) */
2896 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2897 /* reserved */
2898 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2899 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2900
2901 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2902 return -EINVAL;
2903
2904 /*
2905 * KVM does not emulate a version of VMX that constrains physical
2906 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2907 */
2908 if (data & BIT_ULL(48))
2909 return -EINVAL;
2910
2911 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2912 vmx_basic_vmcs_revision_id(data))
2913 return -EINVAL;
2914
2915 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2916 return -EINVAL;
2917
2918 vmx->nested.nested_vmx_basic = data;
2919 return 0;
2920}
2921
2922static int
2923vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2924{
2925 u64 supported;
2926 u32 *lowp, *highp;
2927
2928 switch (msr_index) {
2929 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2930 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2931 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2932 break;
2933 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2934 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2935 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2936 break;
2937 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2938 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2939 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2940 break;
2941 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2942 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2943 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2944 break;
2945 case MSR_IA32_VMX_PROCBASED_CTLS2:
2946 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2947 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2948 break;
2949 default:
2950 BUG();
2951 }
2952
2953 supported = vmx_control_msr(*lowp, *highp);
2954
2955 /* Check must-be-1 bits are still 1. */
2956 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2957 return -EINVAL;
2958
2959 /* Check must-be-0 bits are still 0. */
2960 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2961 return -EINVAL;
2962
2963 *lowp = data;
2964 *highp = data >> 32;
2965 return 0;
2966}
2967
2968static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2969{
2970 const u64 feature_and_reserved_bits =
2971 /* feature */
2972 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2973 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2974 /* reserved */
2975 GENMASK_ULL(13, 9) | BIT_ULL(31);
2976 u64 vmx_misc;
2977
2978 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2979 vmx->nested.nested_vmx_misc_high);
2980
2981 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2982 return -EINVAL;
2983
2984 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2985 PIN_BASED_VMX_PREEMPTION_TIMER) &&
2986 vmx_misc_preemption_timer_rate(data) !=
2987 vmx_misc_preemption_timer_rate(vmx_misc))
2988 return -EINVAL;
2989
2990 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2991 return -EINVAL;
2992
2993 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2994 return -EINVAL;
2995
2996 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2997 return -EINVAL;
2998
2999 vmx->nested.nested_vmx_misc_low = data;
3000 vmx->nested.nested_vmx_misc_high = data >> 32;
3001 return 0;
3002}
3003
3004static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3005{
3006 u64 vmx_ept_vpid_cap;
3007
3008 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3009 vmx->nested.nested_vmx_vpid_caps);
3010
3011 /* Every bit is either reserved or a feature bit. */
3012 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3013 return -EINVAL;
3014
3015 vmx->nested.nested_vmx_ept_caps = data;
3016 vmx->nested.nested_vmx_vpid_caps = data >> 32;
3017 return 0;
3018}
3019
3020static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3021{
3022 u64 *msr;
3023
3024 switch (msr_index) {
3025 case MSR_IA32_VMX_CR0_FIXED0:
3026 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3027 break;
3028 case MSR_IA32_VMX_CR4_FIXED0:
3029 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3030 break;
3031 default:
3032 BUG();
3033 }
3034
3035 /*
3036 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3037 * must be 1 in the restored value.
3038 */
3039 if (!is_bitwise_subset(data, *msr, -1ULL))
3040 return -EINVAL;
3041
3042 *msr = data;
3043 return 0;
3044}
3045
3046/*
3047 * Called when userspace is restoring VMX MSRs.
3048 *
3049 * Returns 0 on success, non-0 otherwise.
3050 */
3051static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
b87a51ae 3052{
b9c237bb
WV
3053 struct vcpu_vmx *vmx = to_vmx(vcpu);
3054
b87a51ae 3055 switch (msr_index) {
b87a51ae 3056 case MSR_IA32_VMX_BASIC:
62cc6b9d
DM
3057 return vmx_restore_vmx_basic(vmx, data);
3058 case MSR_IA32_VMX_PINBASED_CTLS:
3059 case MSR_IA32_VMX_PROCBASED_CTLS:
3060 case MSR_IA32_VMX_EXIT_CTLS:
3061 case MSR_IA32_VMX_ENTRY_CTLS:
b87a51ae 3062 /*
62cc6b9d
DM
3063 * The "non-true" VMX capability MSRs are generated from the
3064 * "true" MSRs, so we do not support restoring them directly.
3065 *
3066 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3067 * should restore the "true" MSRs with the must-be-1 bits
3068 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3069 * DEFAULT SETTINGS".
b87a51ae 3070 */
62cc6b9d
DM
3071 return -EINVAL;
3072 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3073 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3074 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3075 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3076 case MSR_IA32_VMX_PROCBASED_CTLS2:
3077 return vmx_restore_control_msr(vmx, msr_index, data);
3078 case MSR_IA32_VMX_MISC:
3079 return vmx_restore_vmx_misc(vmx, data);
3080 case MSR_IA32_VMX_CR0_FIXED0:
3081 case MSR_IA32_VMX_CR4_FIXED0:
3082 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3083 case MSR_IA32_VMX_CR0_FIXED1:
3084 case MSR_IA32_VMX_CR4_FIXED1:
3085 /*
3086 * These MSRs are generated based on the vCPU's CPUID, so we
3087 * do not support restoring them directly.
3088 */
3089 return -EINVAL;
3090 case MSR_IA32_VMX_EPT_VPID_CAP:
3091 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3092 case MSR_IA32_VMX_VMCS_ENUM:
3093 vmx->nested.nested_vmx_vmcs_enum = data;
3094 return 0;
3095 default:
b87a51ae 3096 /*
62cc6b9d 3097 * The rest of the VMX capability MSRs do not support restore.
b87a51ae 3098 */
62cc6b9d
DM
3099 return -EINVAL;
3100 }
3101}
3102
3103/* Returns 0 on success, non-0 otherwise. */
3104static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3105{
3106 struct vcpu_vmx *vmx = to_vmx(vcpu);
3107
3108 switch (msr_index) {
3109 case MSR_IA32_VMX_BASIC:
3110 *pdata = vmx->nested.nested_vmx_basic;
b87a51ae
NHE
3111 break;
3112 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3113 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV
3114 *pdata = vmx_control_msr(
3115 vmx->nested.nested_vmx_pinbased_ctls_low,
3116 vmx->nested.nested_vmx_pinbased_ctls_high);
0115f9cb
DM
3117 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3118 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3119 break;
3120 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3121 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV
3122 *pdata = vmx_control_msr(
3123 vmx->nested.nested_vmx_procbased_ctls_low,
3124 vmx->nested.nested_vmx_procbased_ctls_high);
0115f9cb
DM
3125 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3126 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3127 break;
3128 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3129 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV
3130 *pdata = vmx_control_msr(
3131 vmx->nested.nested_vmx_exit_ctls_low,
3132 vmx->nested.nested_vmx_exit_ctls_high);
0115f9cb
DM
3133 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3134 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3135 break;
3136 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3137 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV
3138 *pdata = vmx_control_msr(
3139 vmx->nested.nested_vmx_entry_ctls_low,
3140 vmx->nested.nested_vmx_entry_ctls_high);
0115f9cb
DM
3141 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3142 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3143 break;
3144 case MSR_IA32_VMX_MISC:
b9c237bb
WV
3145 *pdata = vmx_control_msr(
3146 vmx->nested.nested_vmx_misc_low,
3147 vmx->nested.nested_vmx_misc_high);
b87a51ae 3148 break;
b87a51ae 3149 case MSR_IA32_VMX_CR0_FIXED0:
62cc6b9d 3150 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
b87a51ae
NHE
3151 break;
3152 case MSR_IA32_VMX_CR0_FIXED1:
62cc6b9d 3153 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
b87a51ae
NHE
3154 break;
3155 case MSR_IA32_VMX_CR4_FIXED0:
62cc6b9d 3156 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
b87a51ae
NHE
3157 break;
3158 case MSR_IA32_VMX_CR4_FIXED1:
62cc6b9d 3159 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
b87a51ae
NHE
3160 break;
3161 case MSR_IA32_VMX_VMCS_ENUM:
62cc6b9d 3162 *pdata = vmx->nested.nested_vmx_vmcs_enum;
b87a51ae
NHE
3163 break;
3164 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV
3165 *pdata = vmx_control_msr(
3166 vmx->nested.nested_vmx_secondary_ctls_low,
3167 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE
3168 break;
3169 case MSR_IA32_VMX_EPT_VPID_CAP:
089d7b6e
WL
3170 *pdata = vmx->nested.nested_vmx_ept_caps |
3171 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
b87a51ae
NHE
3172 break;
3173 default:
b87a51ae 3174 return 1;
b3897a49
NHE
3175 }
3176
b87a51ae
NHE
3177 return 0;
3178}
3179
37e4c997
HZ
3180static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3181 uint64_t val)
3182{
3183 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3184
3185 return !(val & ~valid_bits);
3186}
3187
6aa8b732
AK
3188/*
3189 * Reads an msr value (of 'msr_index') into 'pdata'.
3190 * Returns 0 on success, non-0 otherwise.
3191 * Assumes vcpu_load() was already called.
3192 */
609e36d3 3193static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 3194{
26bb0981 3195 struct shared_msr_entry *msr;
6aa8b732 3196
609e36d3 3197 switch (msr_info->index) {
05b3e0c2 3198#ifdef CONFIG_X86_64
6aa8b732 3199 case MSR_FS_BASE:
609e36d3 3200 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK
3201 break;
3202 case MSR_GS_BASE:
609e36d3 3203 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 3204 break;
44ea2b17
AK
3205 case MSR_KERNEL_GS_BASE:
3206 vmx_load_host_state(to_vmx(vcpu));
609e36d3 3207 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 3208 break;
26bb0981 3209#endif
6aa8b732 3210 case MSR_EFER:
609e36d3 3211 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 3212 case MSR_IA32_TSC:
be7b263e 3213 msr_info->data = guest_read_tsc(vcpu);
6aa8b732
AK
3214 break;
3215 case MSR_IA32_SYSENTER_CS:
609e36d3 3216 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK
3217 break;
3218 case MSR_IA32_SYSENTER_EIP:
609e36d3 3219 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK
3220 break;
3221 case MSR_IA32_SYSENTER_ESP:
609e36d3 3222 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 3223 break;
0dd376e7 3224 case MSR_IA32_BNDCFGS:
691bd434
HZ
3225 if (!kvm_mpx_supported() ||
3226 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
93c4adc7 3227 return 1;
609e36d3 3228 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 3229 break;
c45dcc71
AR
3230 case MSR_IA32_MCG_EXT_CTL:
3231 if (!msr_info->host_initiated &&
3232 !(to_vmx(vcpu)->msr_ia32_feature_control &
3233 FEATURE_CONTROL_LMCE))
cae50139 3234 return 1;
c45dcc71
AR
3235 msr_info->data = vcpu->arch.mcg_ext_ctl;
3236 break;
cae50139 3237 case MSR_IA32_FEATURE_CONTROL:
3b84080b 3238 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
cae50139
JK
3239 break;
3240 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3241 if (!nested_vmx_allowed(vcpu))
3242 return 1;
609e36d3 3243 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL
3244 case MSR_IA32_XSS:
3245 if (!vmx_xsaves_supported())
3246 return 1;
609e36d3 3247 msr_info->data = vcpu->arch.ia32_xss;
20300099 3248 break;
4e47c7a6 3249 case MSR_TSC_AUX:
81b1b9ca 3250 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
4e47c7a6
SY
3251 return 1;
3252 /* Otherwise falls through */
6aa8b732 3253 default:
609e36d3 3254 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 3255 if (msr) {
609e36d3 3256 msr_info->data = msr->data;
3bab1f5d 3257 break;
6aa8b732 3258 }
609e36d3 3259 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK
3260 }
3261
6aa8b732
AK
3262 return 0;
3263}
3264
cae50139
JK
3265static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3266
6aa8b732
AK
3267/*
3268 * Writes msr value into into the appropriate "register".
3269 * Returns 0 on success, non-0 otherwise.
3270 * Assumes vcpu_load() was already called.
3271 */
8fe8ab46 3272static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 3273{
a2fa3e9f 3274 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 3275 struct shared_msr_entry *msr;
2cc51560 3276 int ret = 0;
8fe8ab46
WA
3277 u32 msr_index = msr_info->index;
3278 u64 data = msr_info->data;
2cc51560 3279
6aa8b732 3280 switch (msr_index) {
3bab1f5d 3281 case MSR_EFER:
8fe8ab46 3282 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 3283 break;
16175a79 3284#ifdef CONFIG_X86_64
6aa8b732 3285 case MSR_FS_BASE:
2fb92db1 3286 vmx_segment_cache_clear(vmx);
6aa8b732
AK
3287 vmcs_writel(GUEST_FS_BASE, data);
3288 break;
3289 case MSR_GS_BASE:
2fb92db1 3290 vmx_segment_cache_clear(vmx);
6aa8b732
AK
3291 vmcs_writel(GUEST_GS_BASE, data);
3292 break;
44ea2b17
AK
3293 case MSR_KERNEL_GS_BASE:
3294 vmx_load_host_state(vmx);
3295 vmx->msr_guest_kernel_gs_base = data;
3296 break;
6aa8b732
AK
3297#endif
3298 case MSR_IA32_SYSENTER_CS:
3299 vmcs_write32(GUEST_SYSENTER_CS, data);
3300 break;
3301 case MSR_IA32_SYSENTER_EIP:
f5b42c33 3302 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK
3303 break;
3304 case MSR_IA32_SYSENTER_ESP:
f5b42c33 3305 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 3306 break;
0dd376e7 3307 case MSR_IA32_BNDCFGS:
691bd434
HZ
3308 if (!kvm_mpx_supported() ||
3309 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
93c4adc7 3310 return 1;
4531662d
JM
3311 if (is_noncanonical_address(data & PAGE_MASK) ||
3312 (data & MSR_IA32_BNDCFGS_RSVD))
93c4adc7 3313 return 1;
0dd376e7
LJ
3314 vmcs_write64(GUEST_BNDCFGS, data);
3315 break;
af24a4e4 3316 case MSR_IA32_TSC:
8fe8ab46 3317 kvm_write_tsc(vcpu, msr_info);
6aa8b732 3318 break;
468d472f
SY
3319 case MSR_IA32_CR_PAT:
3320 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA
3321 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3322 return 1;
468d472f
SY
3323 vmcs_write64(GUEST_IA32_PAT, data);
3324 vcpu->arch.pat = data;
3325 break;
3326 }
8fe8ab46 3327 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 3328 break;
ba904635
WA
3329 case MSR_IA32_TSC_ADJUST:
3330 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 3331 break;
c45dcc71
AR
3332 case MSR_IA32_MCG_EXT_CTL:
3333 if ((!msr_info->host_initiated &&
3334 !(to_vmx(vcpu)->msr_ia32_feature_control &
3335 FEATURE_CONTROL_LMCE)) ||
3336 (data & ~MCG_EXT_CTL_LMCE_EN))
3337 return 1;
3338 vcpu->arch.mcg_ext_ctl = data;
3339 break;
cae50139 3340 case MSR_IA32_FEATURE_CONTROL:
37e4c997 3341 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 3342 (to_vmx(vcpu)->msr_ia32_feature_control &
cae50139
JK
3343 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3344 return 1;
3b84080b 3345 vmx->msr_ia32_feature_control = data;
cae50139
JK
3346 if (msr_info->host_initiated && data == 0)
3347 vmx_leave_nested(vcpu);
3348 break;
3349 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM
3350 if (!msr_info->host_initiated)
3351 return 1; /* they are read-only */
3352 if (!nested_vmx_allowed(vcpu))
3353 return 1;
3354 return vmx_set_vmx_msr(vcpu, msr_index, data);
20300099
WL
3355 case MSR_IA32_XSS:
3356 if (!vmx_xsaves_supported())
3357 return 1;
3358 /*
3359 * The only supported bit as of Skylake is bit 8, but
3360 * it is not supported on KVM.
3361 */
3362 if (data != 0)
3363 return 1;
3364 vcpu->arch.ia32_xss = data;
3365 if (vcpu->arch.ia32_xss != host_xss)
3366 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3367 vcpu->arch.ia32_xss, host_xss);
3368 else
3369 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3370 break;
4e47c7a6 3371 case MSR_TSC_AUX:
81b1b9ca 3372 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
4e47c7a6
SY
3373 return 1;
3374 /* Check reserved bit, higher 32 bits should be zero */
3375 if ((data >> 32) != 0)
3376 return 1;
3377 /* Otherwise falls through */
6aa8b732 3378 default:
8b9cf98c 3379 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 3380 if (msr) {
8b3c3104 3381 u64 old_msr_data = msr->data;
3bab1f5d 3382 msr->data = data;
2225fd56
AK
3383 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3384 preempt_disable();
8b3c3104
AH
3385 ret = kvm_set_shared_msr(msr->index, msr->data,
3386 msr->mask);
2225fd56 3387 preempt_enable();
8b3c3104
AH
3388 if (ret)
3389 msr->data = old_msr_data;
2225fd56 3390 }
3bab1f5d 3391 break;
6aa8b732 3392 }
8fe8ab46 3393 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK
3394 }
3395
2cc51560 3396 return ret;
6aa8b732
AK
3397}
3398
5fdbf976 3399static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 3400{
5fdbf976
MT
3401 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3402 switch (reg) {
3403 case VCPU_REGS_RSP:
3404 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3405 break;
3406 case VCPU_REGS_RIP:
3407 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3408 break;
6de4f3ad
AK
3409 case VCPU_EXREG_PDPTR:
3410 if (enable_ept)
3411 ept_save_pdptrs(vcpu);
3412 break;
5fdbf976
MT
3413 default:
3414 break;
3415 }
6aa8b732
AK
3416}
3417
6aa8b732
AK
3418static __init int cpu_has_kvm_support(void)
3419{
6210e37b 3420 return cpu_has_vmx();
6aa8b732
AK
3421}
3422
3423static __init int vmx_disabled_by_bios(void)
3424{
3425 u64 msr;
3426
3427 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 3428 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 3429 /* launched w/ TXT and VMX disabled */
cafd6659
SW
3430 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3431 && tboot_enabled())
3432 return 1;
23f3e991 3433 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 3434 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 3435 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW
3436 && !tboot_enabled()) {
3437 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 3438 "activate TXT before enabling KVM\n");
cafd6659 3439 return 1;
f9335afe 3440 }
23f3e991
JC
3441 /* launched w/o TXT and VMX disabled */
3442 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3443 && !tboot_enabled())
3444 return 1;
cafd6659
SW
3445 }
3446
3447 return 0;
6aa8b732
AK
3448}
3449
7725b894
DX
3450static void kvm_cpu_vmxon(u64 addr)
3451{
fe0e80be 3452 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS
3453 intel_pt_handle_vmx(1);
3454
7725b894
DX
3455 asm volatile (ASM_VMX_VMXON_RAX
3456 : : "a"(&addr), "m"(addr)
3457 : "memory", "cc");
3458}
3459
13a34e06 3460static int hardware_enable(void)
6aa8b732
AK
3461{
3462 int cpu = raw_smp_processor_id();
3463 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 3464 u64 old, test_bits;
6aa8b732 3465
1e02ce4c 3466 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG
3467 return -EBUSY;
3468
d462b819 3469 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW
3470 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3471 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY
3472
3473 /*
3474 * Now we can enable the vmclear operation in kdump
3475 * since the loaded_vmcss_on_cpu list on this cpu
3476 * has been initialized.
3477 *
3478 * Though the cpu is not in VMX operation now, there
3479 * is no problem to enable the vmclear operation
3480 * for the loaded_vmcss_on_cpu list is empty!
3481 */
3482 crash_enable_local_vmclear(cpu);
3483
6aa8b732 3484 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW
3485
3486 test_bits = FEATURE_CONTROL_LOCKED;
3487 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3488 if (tboot_enabled())
3489 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3490
3491 if ((old & test_bits) != test_bits) {
6aa8b732 3492 /* enable and lock */
cafd6659
SW
3493 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3494 }
fe0e80be
DH
3495 kvm_cpu_vmxon(phys_addr);
3496 ept_sync_global();
10474ae8
AG
3497
3498 return 0;
6aa8b732
AK
3499}
3500
d462b819 3501static void vmclear_local_loaded_vmcss(void)
543e4243
AK
3502{
3503 int cpu = raw_smp_processor_id();
d462b819 3504 struct loaded_vmcs *v, *n;
543e4243 3505
d462b819
NHE
3506 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3507 loaded_vmcss_on_cpu_link)
3508 __loaded_vmcs_clear(v);
543e4243
AK
3509}
3510
710ff4a8
EH
3511
3512/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3513 * tricks.
3514 */
3515static void kvm_cpu_vmxoff(void)
6aa8b732 3516{
4ecac3fd 3517 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1c5ac21a
AS
3518
3519 intel_pt_handle_vmx(0);
fe0e80be 3520 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK
3521}
3522
13a34e06 3523static void hardware_disable(void)
710ff4a8 3524{
fe0e80be
DH
3525 vmclear_local_loaded_vmcss();
3526 kvm_cpu_vmxoff();
710ff4a8
EH
3527}
3528
1c3d14fe 3529static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 3530 u32 msr, u32 *result)
1c3d14fe
YS
3531{
3532 u32 vmx_msr_low, vmx_msr_high;
3533 u32 ctl = ctl_min | ctl_opt;
3534
3535 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3536
3537 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3538 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3539
3540 /* Ensure minimum (required) set of control bits are supported. */
3541 if (ctl_min & ~ctl)
002c7f7c 3542 return -EIO;
1c3d14fe
YS
3543
3544 *result = ctl;
3545 return 0;
3546}
3547
110312c8
AK
3548static __init bool allow_1_setting(u32 msr, u32 ctl)
3549{
3550 u32 vmx_msr_low, vmx_msr_high;
3551
3552 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3553 return vmx_msr_high & ctl;
3554}
3555
002c7f7c 3556static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK
3557{
3558 u32 vmx_msr_low, vmx_msr_high;
d56f546d 3559 u32 min, opt, min2, opt2;
1c3d14fe
YS
3560 u32 _pin_based_exec_control = 0;
3561 u32 _cpu_based_exec_control = 0;
f78e0e2e 3562 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS
3563 u32 _vmexit_control = 0;
3564 u32 _vmentry_control = 0;
3565
10166744 3566 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS
3567#ifdef CONFIG_X86_64
3568 CPU_BASED_CR8_LOAD_EXITING |
3569 CPU_BASED_CR8_STORE_EXITING |
3570#endif
d56f546d
SY
3571 CPU_BASED_CR3_LOAD_EXITING |
3572 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS
3573 CPU_BASED_USE_IO_BITMAPS |
3574 CPU_BASED_MOV_DR_EXITING |
a7052897 3575 CPU_BASED_USE_TSC_OFFSETING |
fee84b07
AK
3576 CPU_BASED_INVLPG_EXITING |
3577 CPU_BASED_RDPMC_EXITING;
443381a8 3578
668fffa3
MT
3579 if (!kvm_mwait_in_guest())
3580 min |= CPU_BASED_MWAIT_EXITING |
3581 CPU_BASED_MONITOR_EXITING;
3582
f78e0e2e 3583 opt = CPU_BASED_TPR_SHADOW |
25c5f225 3584 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 3585 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS
3586 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3587 &_cpu_based_exec_control) < 0)
002c7f7c 3588 return -EIO;
6e5d865c
YS
3589#ifdef CONFIG_X86_64
3590 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3591 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3592 ~CPU_BASED_CR8_STORE_EXITING;
3593#endif
f78e0e2e 3594 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY
3595 min2 = 0;
3596 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3597 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3598 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3599 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3600 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3601 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3602 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3603 SECONDARY_EXEC_RDTSCP |
83d4c286 3604 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3605 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3606 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3607 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 3608 SECONDARY_EXEC_XSAVES |
8b3e34e4 3609 SECONDARY_EXEC_ENABLE_PML |
64903d61 3610 SECONDARY_EXEC_TSC_SCALING;
d56f546d
SY
3611 if (adjust_vmx_controls(min2, opt2,
3612 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY
3613 &_cpu_based_2nd_exec_control) < 0)
3614 return -EIO;
3615 }
3616#ifndef CONFIG_X86_64
3617 if (!(_cpu_based_2nd_exec_control &
3618 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3619 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3620#endif
83d4c286
YZ
3621
3622 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3623 _cpu_based_2nd_exec_control &= ~(
8d14695f 3624 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ
3625 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3626 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3627
d56f546d 3628 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT
3629 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3630 enabled */
5fff7d27
GN
3631 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3632 CPU_BASED_CR3_STORE_EXITING |
3633 CPU_BASED_INVLPG_EXITING);
d56f546d
SY
3634 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3635 vmx_capability.ept, vmx_capability.vpid);
3636 }
1c3d14fe 3637
91fa0f8e 3638 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS
3639#ifdef CONFIG_X86_64
3640 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3641#endif
a547c6db 3642 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
91fa0f8e 3643 VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS
3644 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3645 &_vmexit_control) < 0)
002c7f7c 3646 return -EIO;
1c3d14fe 3647
2c82878b
PB
3648 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3649 PIN_BASED_VIRTUAL_NMIS;
3650 opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ
3651 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3652 &_pin_based_exec_control) < 0)
3653 return -EIO;
3654
1c17c3e6
PB
3655 if (cpu_has_broken_vmx_preemption_timer())
3656 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 3657 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 3658 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ
3659 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3660
c845f9c6 3661 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3662 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS
3663 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3664 &_vmentry_control) < 0)
002c7f7c 3665 return -EIO;
6aa8b732 3666
c68876fd 3667 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS
3668
3669 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3670 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3671 return -EIO;
1c3d14fe
YS
3672
3673#ifdef CONFIG_X86_64
3674 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3675 if (vmx_msr_high & (1u<<16))
002c7f7c 3676 return -EIO;
1c3d14fe
YS
3677#endif
3678
3679 /* Require Write-Back (WB) memory type for VMCS accesses. */
3680 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3681 return -EIO;
1c3d14fe 3682
002c7f7c 3683 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 3684 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 3685 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
002c7f7c 3686 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3687
002c7f7c
YS
3688 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3689 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3690 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS
3691 vmcs_conf->vmexit_ctrl = _vmexit_control;
3692 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3693
110312c8
AK
3694 cpu_has_load_ia32_efer =
3695 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3696 VM_ENTRY_LOAD_IA32_EFER)
3697 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3698 VM_EXIT_LOAD_IA32_EFER);
3699
8bf00a52
GN
3700 cpu_has_load_perf_global_ctrl =
3701 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3702 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3703 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3704 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3705
3706 /*
3707 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
bb3541f1 3708 * but due to errata below it can't be used. Workaround is to use
8bf00a52
GN
3709 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3710 *
3711 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3712 *
3713 * AAK155 (model 26)
3714 * AAP115 (model 30)
3715 * AAT100 (model 37)
3716 * BC86,AAY89,BD102 (model 44)
3717 * BA97 (model 46)
3718 *
3719 */
3720 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3721 switch (boot_cpu_data.x86_model) {
3722 case 26:
3723 case 30:
3724 case 37:
3725 case 44:
3726 case 46:
3727 cpu_has_load_perf_global_ctrl = false;
3728 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3729 "does not work properly. Using workaround\n");
3730 break;
3731 default:
3732 break;
3733 }
3734 }
3735
782511b0 3736 if (boot_cpu_has(X86_FEATURE_XSAVES))
20300099
WL
3737 rdmsrl(MSR_IA32_XSS, host_xss);
3738
1c3d14fe 3739 return 0;
c68876fd 3740}
6aa8b732
AK
3741
3742static struct vmcs *alloc_vmcs_cpu(int cpu)
3743{
3744 int node = cpu_to_node(cpu);
3745 struct page *pages;
3746 struct vmcs *vmcs;
3747
96db800f 3748 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK
3749 if (!pages)
3750 return NULL;
3751 vmcs = page_address(pages);
1c3d14fe
YS
3752 memset(vmcs, 0, vmcs_config.size);
3753 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK
3754 return vmcs;
3755}
3756
3757static struct vmcs *alloc_vmcs(void)
3758{
d3b2c338 3759 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK
3760}
3761
3762static void free_vmcs(struct vmcs *vmcs)
3763{
1c3d14fe 3764 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK
3765}
3766
d462b819
NHE
3767/*
3768 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3769 */
3770static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3771{
3772 if (!loaded_vmcs->vmcs)
3773 return;
3774 loaded_vmcs_clear(loaded_vmcs);
3775 free_vmcs(loaded_vmcs->vmcs);
3776 loaded_vmcs->vmcs = NULL;
355f4fb1 3777 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE
3778}
3779
39959588 3780static void free_kvm_area(void)
6aa8b732
AK
3781{
3782 int cpu;
3783
3230bb47 3784 for_each_possible_cpu(cpu) {
6aa8b732 3785 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA
3786 per_cpu(vmxarea, cpu) = NULL;
3787 }
6aa8b732
AK
3788}
3789
85fd514e
JM
3790enum vmcs_field_type {
3791 VMCS_FIELD_TYPE_U16 = 0,
3792 VMCS_FIELD_TYPE_U64 = 1,
3793 VMCS_FIELD_TYPE_U32 = 2,
3794 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3795};
3796
3797static inline int vmcs_field_type(unsigned long field)
3798{
3799 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
3800 return VMCS_FIELD_TYPE_U32;
3801 return (field >> 13) & 0x3 ;
3802}
3803
3804static inline int vmcs_field_readonly(unsigned long field)
3805{
3806 return (((field >> 10) & 0x3) == 1);
3807}
3808
fe2b201b
BD
3809static void init_vmcs_shadow_fields(void)
3810{
3811 int i, j;
3812
3813 /* No checks for read only fields yet */
3814
3815 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3816 switch (shadow_read_write_fields[i]) {
3817 case GUEST_BNDCFGS:
a87036ad 3818 if (!kvm_mpx_supported())
fe2b201b
BD
3819 continue;
3820 break;
3821 default:
3822 break;
3823 }
3824
3825 if (j < i)
3826 shadow_read_write_fields[j] =
3827 shadow_read_write_fields[i];
3828 j++;
3829 }
3830 max_shadow_read_write_fields = j;
3831
3832 /* shadowed fields guest access without vmexit */
3833 for (i = 0; i < max_shadow_read_write_fields; i++) {
85fd514e
JM
3834 unsigned long field = shadow_read_write_fields[i];
3835
3836 clear_bit(field, vmx_vmwrite_bitmap);
3837 clear_bit(field, vmx_vmread_bitmap);
3838 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
3839 clear_bit(field + 1, vmx_vmwrite_bitmap);
3840 clear_bit(field + 1, vmx_vmread_bitmap);
3841 }
3842 }
3843 for (i = 0; i < max_shadow_read_only_fields; i++) {
3844 unsigned long field = shadow_read_only_fields[i];
3845
3846 clear_bit(field, vmx_vmread_bitmap);
3847 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
3848 clear_bit(field + 1, vmx_vmread_bitmap);
fe2b201b 3849 }
fe2b201b
BD
3850}
3851
6aa8b732
AK
3852static __init int alloc_kvm_area(void)
3853{
3854 int cpu;
3855
3230bb47 3856 for_each_possible_cpu(cpu) {
6aa8b732
AK
3857 struct vmcs *vmcs;
3858
3859 vmcs = alloc_vmcs_cpu(cpu);
3860 if (!vmcs) {
3861 free_kvm_area();
3862 return -ENOMEM;
3863 }
3864
3865 per_cpu(vmxarea, cpu) = vmcs;
3866 }
3867 return 0;
3868}
3869
91b0aa2c 3870static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3871 struct kvm_segment *save)
6aa8b732 3872{
d99e4152
GN
3873 if (!emulate_invalid_guest_state) {
3874 /*
3875 * CS and SS RPL should be equal during guest entry according
3876 * to VMX spec, but in reality it is not always so. Since vcpu
3877 * is in the middle of the transition from real mode to
3878 * protected mode it is safe to assume that RPL 0 is a good
3879 * default value.
3880 */
3881 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA
3882 save->selector &= ~SEGMENT_RPL_MASK;
3883 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3884 save->s = 1;
6aa8b732 3885 }
d99e4152 3886 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK
3887}
3888
3889static void enter_pmode(struct kvm_vcpu *vcpu)
3890{
3891 unsigned long flags;
a89a8fb9 3892 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3893
d99e4152
GN
3894 /*
3895 * Update real mode segment cache. It may be not up-to-date if sement
3896 * register was written while vcpu was in a guest mode.
3897 */
3898 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3899 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3900 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3901 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3902 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3903 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3904
7ffd92c5 3905 vmx->rmode.vm86_active = 0;
6aa8b732 3906
2fb92db1
AK
3907 vmx_segment_cache_clear(vmx);
3908
f5f7b2fe 3909 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK
3910
3911 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK
3912 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3913 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK
3914 vmcs_writel(GUEST_RFLAGS, flags);
3915
66aee91a
RR
3916 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3917 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK
3918
3919 update_exception_bitmap(vcpu);
3920
91b0aa2c
GN
3921 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3922 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3923 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3924 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3925 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3926 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK
3927}
3928
f5f7b2fe 3929static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3930{
772e0318 3931 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN
3932 struct kvm_segment var = *save;
3933
3934 var.dpl = 0x3;
3935 if (seg == VCPU_SREG_CS)
3936 var.type = 0x3;
3937
3938 if (!emulate_invalid_guest_state) {
3939 var.selector = var.base >> 4;
3940 var.base = var.base & 0xffff0;
3941 var.limit = 0xffff;
3942 var.g = 0;
3943 var.db = 0;
3944 var.present = 1;
3945 var.s = 1;
3946 var.l = 0;
3947 var.unusable = 0;
3948 var.type = 0x3;
3949 var.avl = 0;
3950 if (save->base & 0xf)
3951 printk_once(KERN_WARNING "kvm: segment base is not "
3952 "paragraph aligned when entering "
3953 "protected mode (seg=%d)", seg);
3954 }
6aa8b732 3955
d99e4152 3956 vmcs_write16(sf->selector, var.selector);
96794e4e 3957 vmcs_writel(sf->base, var.base);
d99e4152
GN
3958 vmcs_write32(sf->limit, var.limit);
3959 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK
3960}
3961
3962static void enter_rmode(struct kvm_vcpu *vcpu)
3963{
3964 unsigned long flags;
a89a8fb9 3965 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3966
f5f7b2fe
AK
3967 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3968 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3969 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3970 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3971 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN
3972 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3973 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3974
7ffd92c5 3975 vmx->rmode.vm86_active = 1;
6aa8b732 3976
776e58ea
GN
3977 /*
3978 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3979 * vcpu. Warn the user that an update is overdue.
776e58ea 3980 */
4918c6ca 3981 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN
3982 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3983 "called before entering vcpu\n");
776e58ea 3984
2fb92db1
AK
3985 vmx_segment_cache_clear(vmx);
3986
4918c6ca 3987 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3988 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK
3989 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3990
3991 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3992 vmx->rmode.save_rflags = flags;
6aa8b732 3993
053de044 3994 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK
3995
3996 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3997 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK
3998 update_exception_bitmap(vcpu);
3999
d99e4152
GN
4000 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4001 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4002 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4003 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4004 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4005 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 4006
8668a3c4 4007 kvm_mmu_reset_context(vcpu);
6aa8b732
AK
4008}
4009
401d10de
AS
4010static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4011{
4012 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK
4013 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4014
4015 if (!msr)
4016 return;
401d10de 4017
44ea2b17
AK
4018 /*
4019 * Force kernel_gs_base reloading before EFER changes, as control
4020 * of this msr depends on is_long_mode().
4021 */
4022 vmx_load_host_state(to_vmx(vcpu));
f6801dff 4023 vcpu->arch.efer = efer;
401d10de 4024 if (efer & EFER_LMA) {
2961e876 4025 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS
4026 msr->data = efer;
4027 } else {
2961e876 4028 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS
4029
4030 msr->data = efer & ~EFER_LME;
4031 }
4032 setup_msrs(vmx);
4033}
4034
05b3e0c2 4035#ifdef CONFIG_X86_64
6aa8b732
AK
4036
4037static void enter_lmode(struct kvm_vcpu *vcpu)
4038{
4039 u32 guest_tr_ar;
4040
2fb92db1
AK
4041 vmx_segment_cache_clear(to_vmx(vcpu));
4042
6aa8b732 4043 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 4044 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK
4045 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4046 __func__);
6aa8b732 4047 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL
4048 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4049 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 4050 }
da38f438 4051 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK
4052}
4053
4054static void exit_lmode(struct kvm_vcpu *vcpu)
4055{
2961e876 4056 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 4057 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK
4058}
4059
4060#endif
4061
dd5f5341 4062static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
2384d2b3 4063{
dd180b3e
XG
4064 if (enable_ept) {
4065 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4066 return;
995f00a6 4067 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
f0b98c02
JM
4068 } else {
4069 vpid_sync_context(vpid);
dd180b3e 4070 }
2384d2b3
SY
4071}
4072
dd5f5341
WL
4073static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4074{
4075 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4076}
4077
fb6c8198
JM
4078static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4079{
4080 if (enable_ept)
4081 vmx_flush_tlb(vcpu);
4082}
4083
e8467fda
AK
4084static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4085{
4086 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4087
4088 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4089 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4090}
4091
aff48baa
AK
4092static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4093{
4094 if (enable_ept && is_paging(vcpu))
4095 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4096 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4097}
4098
25c4c276 4099static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 4100{
fc78f519
AK
4101 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4102
4103 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4104 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK
4105}
4106
1439442c
SY
4107static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4108{
d0d538b9
GN
4109 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4110
6de4f3ad
AK
4111 if (!test_bit(VCPU_EXREG_PDPTR,
4112 (unsigned long *)&vcpu->arch.regs_dirty))
4113 return;
4114
1439442c 4115 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN
4116 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4117 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4118 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4119 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY
4120 }
4121}
4122
8f5d549f
AK
4123static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4124{
d0d538b9
GN
4125 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4126
8f5d549f 4127 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN
4128 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4129 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4130 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4131 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 4132 }
6de4f3ad
AK
4133
4134 __set_bit(VCPU_EXREG_PDPTR,
4135 (unsigned long *)&vcpu->arch.regs_avail);
4136 __set_bit(VCPU_EXREG_PDPTR,
4137 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK
4138}
4139
3899152c
DM
4140static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4141{
4142 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4143 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4144 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4145
4146 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4147 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4148 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4149 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4150
4151 return fixed_bits_valid(val, fixed0, fixed1);
4152}
4153
4154static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4155{
4156 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4157 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4158
4159 return fixed_bits_valid(val, fixed0, fixed1);
4160}
4161
4162static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4163{
4164 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4165 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4166
4167 return fixed_bits_valid(val, fixed0, fixed1);
4168}
4169
4170/* No difference in the restrictions on guest and host CR4 in VMX operation. */
4171#define nested_guest_cr4_valid nested_cr4_valid
4172#define nested_host_cr4_valid nested_cr4_valid
4173
5e1746d6 4174static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY
4175
4176static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4177 unsigned long cr0,
4178 struct kvm_vcpu *vcpu)
4179{
5233dd51
MT
4180 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4181 vmx_decache_cr3(vcpu);
1439442c
SY
4182 if (!(cr0 & X86_CR0_PG)) {
4183 /* From paging/starting to nonpaging */
4184 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 4185 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY
4186 (CPU_BASED_CR3_LOAD_EXITING |
4187 CPU_BASED_CR3_STORE_EXITING));
4188 vcpu->arch.cr0 = cr0;
fc78f519 4189 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY
4190 } else if (!is_paging(vcpu)) {
4191 /* From nonpaging to paging */
4192 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 4193 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY
4194 ~(CPU_BASED_CR3_LOAD_EXITING |
4195 CPU_BASED_CR3_STORE_EXITING));
4196 vcpu->arch.cr0 = cr0;
fc78f519 4197 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 4198 }
95eb84a7
SY
4199
4200 if (!(cr0 & X86_CR0_WP))
4201 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY
4202}
4203
6aa8b732
AK
4204static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4205{
7ffd92c5 4206 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK
4207 unsigned long hw_cr0;
4208
5037878e 4209 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 4210 if (enable_unrestricted_guest)
5037878e 4211 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 4212 else {
5037878e 4213 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 4214
218e763f
GN
4215 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4216 enter_pmode(vcpu);
6aa8b732 4217
218e763f
GN
4218 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4219 enter_rmode(vcpu);
4220 }
6aa8b732 4221
05b3e0c2 4222#ifdef CONFIG_X86_64
f6801dff 4223 if (vcpu->arch.efer & EFER_LME) {
707d92fa 4224 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 4225 enter_lmode(vcpu);
707d92fa 4226 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK
4227 exit_lmode(vcpu);
4228 }
4229#endif
4230
089d034e 4231 if (enable_ept)
1439442c
SY
4232 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4233
6aa8b732 4234 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 4235 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 4236 vcpu->arch.cr0 = cr0;
14168786
GN
4237
4238 /* depends on vcpu->arch.cr0 to be set to a new value */
4239 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK
4240}
4241
995f00a6 4242static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
1439442c
SY
4243{
4244 u64 eptp;
4245
4246 /* TODO write the value reading from MSR */
4247 eptp = VMX_EPT_DEFAULT_MT |
4248 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
995f00a6
PF
4249 if (enable_ept_ad_bits &&
4250 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
b38f9934 4251 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY
4252 eptp |= (root_hpa & PAGE_MASK);
4253
4254 return eptp;
4255}
4256
6aa8b732
AK
4257static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4258{
1439442c
SY
4259 unsigned long guest_cr3;
4260 u64 eptp;
4261
4262 guest_cr3 = cr3;
089d034e 4263 if (enable_ept) {
995f00a6 4264 eptp = construct_eptp(vcpu, cr3);
1439442c 4265 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK
4266 if (is_paging(vcpu) || is_guest_mode(vcpu))
4267 guest_cr3 = kvm_read_cr3(vcpu);
4268 else
4269 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 4270 ept_load_pdptrs(vcpu);
1439442c
SY
4271 }
4272
2384d2b3 4273 vmx_flush_tlb(vcpu);
1439442c 4274 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK
4275}
4276
5e1746d6 4277static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 4278{
085e68ee
BS
4279 /*
4280 * Pass through host's Machine Check Enable value to hw_cr4, which
4281 * is in force while we are in guest mode. Do not let guests control
4282 * this bit, even if host CR4.MCE == 0.
4283 */
4284 unsigned long hw_cr4 =
4285 (cr4_read_shadow() & X86_CR4_MCE) |
4286 (cr4 & ~X86_CR4_MCE) |
4287 (to_vmx(vcpu)->rmode.vm86_active ?
4288 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 4289
5e1746d6
NHE
4290 if (cr4 & X86_CR4_VMXE) {
4291 /*
4292 * To use VMXON (and later other VMX instructions), a guest
4293 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4294 * So basically the check on whether to allow nested VMX
4295 * is here.
4296 */
4297 if (!nested_vmx_allowed(vcpu))
4298 return 1;
1a0d74e6 4299 }
3899152c
DM
4300
4301 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE
4302 return 1;
4303
ad312c7c 4304 vcpu->arch.cr4 = cr4;
bc23008b
AK
4305 if (enable_ept) {
4306 if (!is_paging(vcpu)) {
4307 hw_cr4 &= ~X86_CR4_PAE;
4308 hw_cr4 |= X86_CR4_PSE;
4309 } else if (!(cr4 & X86_CR4_PAE)) {
4310 hw_cr4 &= ~X86_CR4_PAE;
4311 }
4312 }
1439442c 4313
656ec4a4
RK
4314 if (!enable_unrestricted_guest && !is_paging(vcpu))
4315 /*
ddba2628
HH
4316 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4317 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4318 * to be manually disabled when guest switches to non-paging
4319 * mode.
4320 *
4321 * If !enable_unrestricted_guest, the CPU is always running
4322 * with CR0.PG=1 and CR4 needs to be modified.
4323 * If enable_unrestricted_guest, the CPU automatically
4324 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 4325 */
ddba2628 4326 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
656ec4a4 4327
1439442c
SY
4328 vmcs_writel(CR4_READ_SHADOW, cr4);
4329 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 4330 return 0;
6aa8b732
AK
4331}
4332
6aa8b732
AK
4333static void vmx_get_segment(struct kvm_vcpu *vcpu,
4334 struct kvm_segment *var, int seg)
4335{
a9179499 4336 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK
4337 u32 ar;
4338
c6ad1153 4339 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 4340 *var = vmx->rmode.segs[seg];
a9179499 4341 if (seg == VCPU_SREG_TR
2fb92db1 4342 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 4343 return;
1390a28b
AK
4344 var->base = vmx_read_guest_seg_base(vmx, seg);
4345 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4346 return;
a9179499 4347 }
2fb92db1
AK
4348 var->base = vmx_read_guest_seg_base(vmx, seg);
4349 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4350 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4351 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 4352 var->unusable = (ar >> 16) & 1;
6aa8b732
AK
4353 var->type = ar & 15;
4354 var->s = (ar >> 4) & 1;
4355 var->dpl = (ar >> 5) & 3;
03617c18
GN
4356 /*
4357 * Some userspaces do not preserve unusable property. Since usable
4358 * segment has to be present according to VMX spec we can use present
4359 * property to amend userspace bug by making unusable segment always
4360 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4361 * segment as unusable.
4362 */
4363 var->present = !var->unusable;
6aa8b732
AK
4364 var->avl = (ar >> 12) & 1;
4365 var->l = (ar >> 13) & 1;
4366 var->db = (ar >> 14) & 1;
4367 var->g = (ar >> 15) & 1;
6aa8b732
AK
4368}
4369
a9179499
AK
4370static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4371{
a9179499
AK
4372 struct kvm_segment s;
4373
4374 if (to_vmx(vcpu)->rmode.vm86_active) {
4375 vmx_get_segment(vcpu, &s, seg);
4376 return s.base;
4377 }
2fb92db1 4378 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK
4379}
4380
b09408d0 4381static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 4382{
b09408d0
MT
4383 struct vcpu_vmx *vmx = to_vmx(vcpu);
4384
ae9fedc7 4385 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 4386 return 0;
ae9fedc7
PB
4387 else {
4388 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 4389 return VMX_AR_DPL(ar);
69c73028 4390 }
69c73028
AK
4391}
4392
653e3108 4393static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 4394{
6aa8b732
AK
4395 u32 ar;
4396
f0495f9b 4397 if (var->unusable || !var->present)
6aa8b732
AK
4398 ar = 1 << 16;
4399 else {
4400 ar = var->type & 15;
4401 ar |= (var->s & 1) << 4;
4402 ar |= (var->dpl & 3) << 5;
4403 ar |= (var->present & 1) << 7;
4404 ar |= (var->avl & 1) << 12;
4405 ar |= (var->l & 1) << 13;
4406 ar |= (var->db & 1) << 14;
4407 ar |= (var->g & 1) << 15;
4408 }
653e3108
AK
4409
4410 return ar;
4411}
4412
4413static void vmx_set_segment(struct kvm_vcpu *vcpu,
4414 struct kvm_segment *var, int seg)
4415{
7ffd92c5 4416 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 4417 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 4418
2fb92db1
AK
4419 vmx_segment_cache_clear(vmx);
4420
1ecd50a9
GN
4421 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4422 vmx->rmode.segs[seg] = *var;
4423 if (seg == VCPU_SREG_TR)
4424 vmcs_write16(sf->selector, var->selector);
4425 else if (var->s)
4426 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 4427 goto out;
653e3108 4428 }
1ecd50a9 4429
653e3108
AK
4430 vmcs_writel(sf->base, var->base);
4431 vmcs_write32(sf->limit, var->limit);
4432 vmcs_write16(sf->selector, var->selector);
3a624e29
NK
4433
4434 /*
4435 * Fix the "Accessed" bit in AR field of segment registers for older
4436 * qemu binaries.
4437 * IA32 arch specifies that at the time of processor reset the
4438 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 4439 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK
4440 * state vmexit when "unrestricted guest" mode is turned on.
4441 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4442 * tree. Newer qemu binaries with that qemu fix would not need this
4443 * kvm hack.
4444 */
4445 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 4446 var->type |= 0x1; /* Accessed */
3a624e29 4447
f924d66d 4448 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN
4449
4450out:
98eb2f8b 4451 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK
4452}
4453
6aa8b732
AK
4454static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4455{
2fb92db1 4456 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK
4457
4458 *db = (ar >> 14) & 1;
4459 *l = (ar >> 13) & 1;
4460}
4461
89a27f4d 4462static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4463{
89a27f4d
GN
4464 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4465 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK
4466}
4467
89a27f4d 4468static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4469{
89a27f4d
GN
4470 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4471 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK
4472}
4473
89a27f4d 4474static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4475{
89a27f4d
GN
4476 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4477 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK
4478}
4479
89a27f4d 4480static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4481{
89a27f4d
GN
4482 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4483 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK
4484}
4485
648dfaa7
MG
4486static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4487{
4488 struct kvm_segment var;
4489 u32 ar;
4490
4491 vmx_get_segment(vcpu, &var, seg);
07f42f5f 4492 var.dpl = 0x3;
0647f4aa
GN
4493 if (seg == VCPU_SREG_CS)
4494 var.type = 0x3;
648dfaa7
MG
4495 ar = vmx_segment_access_rights(&var);
4496
4497 if (var.base != (var.selector << 4))
4498 return false;
89efbed0 4499 if (var.limit != 0xffff)
648dfaa7 4500 return false;
07f42f5f 4501 if (ar != 0xf3)
648dfaa7
MG
4502 return false;
4503
4504 return true;
4505}
4506
4507static bool code_segment_valid(struct kvm_vcpu *vcpu)
4508{
4509 struct kvm_segment cs;
4510 unsigned int cs_rpl;
4511
4512 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 4513 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 4514
1872a3f4
AK
4515 if (cs.unusable)
4516 return false;
4d283ec9 4517 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG
4518 return false;
4519 if (!cs.s)
4520 return false;
4d283ec9 4521 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG
4522 if (cs.dpl > cs_rpl)
4523 return false;
1872a3f4 4524 } else {
648dfaa7
MG
4525 if (cs.dpl != cs_rpl)
4526 return false;
4527 }
4528 if (!cs.present)
4529 return false;
4530
4531 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4532 return true;
4533}
4534
4535static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4536{
4537 struct kvm_segment ss;
4538 unsigned int ss_rpl;
4539
4540 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 4541 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 4542
1872a3f4
AK
4543 if (ss.unusable)
4544 return true;
4545 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG
4546 return false;
4547 if (!ss.s)
4548 return false;
4549 if (ss.dpl != ss_rpl) /* DPL != RPL */
4550 return false;
4551 if (!ss.present)
4552 return false;
4553
4554 return true;
4555}
4556
4557static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4558{
4559 struct kvm_segment var;
4560 unsigned int rpl;
4561
4562 vmx_get_segment(vcpu, &var, seg);
b32a9918 4563 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 4564
1872a3f4
AK
4565 if (var.unusable)
4566 return true;
648dfaa7
MG
4567 if (!var.s)
4568 return false;
4569 if (!var.present)
4570 return false;
4d283ec9 4571 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG
4572 if (var.dpl < rpl) /* DPL < RPL */
4573 return false;
4574 }
4575
4576 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4577 * rights flags
4578 */
4579 return true;
4580}
4581
4582static bool tr_valid(struct kvm_vcpu *vcpu)
4583{
4584 struct kvm_segment tr;
4585
4586 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4587
1872a3f4
AK
4588 if (tr.unusable)
4589 return false;
b32a9918 4590 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 4591 return false;
1872a3f4 4592 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG
4593 return false;
4594 if (!tr.present)
4595 return false;
4596
4597 return true;
4598}
4599
4600static bool ldtr_valid(struct kvm_vcpu *vcpu)
4601{
4602 struct kvm_segment ldtr;
4603
4604 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4605
1872a3f4
AK
4606 if (ldtr.unusable)
4607 return true;
b32a9918 4608 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG
4609 return false;
4610 if (ldtr.type != 2)
4611 return false;
4612 if (!ldtr.present)
4613 return false;
4614
4615 return true;
4616}
4617
4618static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4619{
4620 struct kvm_segment cs, ss;
4621
4622 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4623 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4624
b32a9918
NA
4625 return ((cs.selector & SEGMENT_RPL_MASK) ==
4626 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG
4627}
4628
4629/*
4630 * Check if guest state is valid. Returns true if valid, false if
4631 * not.
4632 * We assume that registers are always usable
4633 */
4634static bool guest_state_valid(struct kvm_vcpu *vcpu)
4635{
c5e97c80
GN
4636 if (enable_unrestricted_guest)
4637 return true;
4638
648dfaa7 4639 /* real mode guest state checks */
f13882d8 4640 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG
4641 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4642 return false;
4643 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4644 return false;
4645 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4646 return false;
4647 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4648 return false;
4649 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4650 return false;
4651 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4652 return false;
4653 } else {
4654 /* protected mode guest state checks */
4655 if (!cs_ss_rpl_check(vcpu))
4656 return false;
4657 if (!code_segment_valid(vcpu))
4658 return false;
4659 if (!stack_segment_valid(vcpu))
4660 return false;
4661 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4662 return false;
4663 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4664 return false;
4665 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4666 return false;
4667 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4668 return false;
4669 if (!tr_valid(vcpu))
4670 return false;
4671 if (!ldtr_valid(vcpu))
4672 return false;
4673 }
4674 /* TODO:
4675 * - Add checks on RIP
4676 * - Add checks on RFLAGS
4677 */
4678
4679 return true;
4680}
4681
5fa99cbe
JM
4682static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4683{
4684 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4685}
4686
d77c26fc 4687static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4688{
40dcaa9f 4689 gfn_t fn;
195aefde 4690 u16 data = 0;
1f755a82 4691 int idx, r;
6aa8b732 4692
40dcaa9f 4693 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4694 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE
4695 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4696 if (r < 0)
10589a46 4697 goto out;
195aefde 4698 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY
4699 r = kvm_write_guest_page(kvm, fn++, &data,
4700 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4701 if (r < 0)
10589a46 4702 goto out;
195aefde
IE
4703 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4704 if (r < 0)
10589a46 4705 goto out;
195aefde
IE
4706 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4707 if (r < 0)
10589a46 4708 goto out;
195aefde 4709 data = ~0;
10589a46
MT
4710 r = kvm_write_guest_page(kvm, fn, &data,
4711 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4712 sizeof(u8));
10589a46 4713out:
40dcaa9f 4714 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4715 return r;
6aa8b732
AK
4716}
4717
b7ebfb05
SY
4718static int init_rmode_identity_map(struct kvm *kvm)
4719{
f51770ed 4720 int i, idx, r = 0;
ba049e93 4721 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY
4722 u32 tmp;
4723
089d034e 4724 if (!enable_ept)
f51770ed 4725 return 0;
a255d479
TC
4726
4727 /* Protect kvm->arch.ept_identity_pagetable_done. */
4728 mutex_lock(&kvm->slots_lock);
4729
f51770ed 4730 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4731 goto out2;
a255d479 4732
b927a3ce 4733 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC
4734
4735 r = alloc_identity_pagetable(kvm);
f51770ed 4736 if (r < 0)
a255d479
TC
4737 goto out2;
4738
40dcaa9f 4739 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY
4740 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4741 if (r < 0)
4742 goto out;
4743 /* Set up identity-mapping pagetable for EPT in real mode */
4744 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4745 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4746 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4747 r = kvm_write_guest_page(kvm, identity_map_pfn,
4748 &tmp, i * sizeof(tmp), sizeof(tmp));
4749 if (r < 0)
4750 goto out;
4751 }
4752 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4753
b7ebfb05 4754out:
40dcaa9f 4755 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC
4756
4757out2:
4758 mutex_unlock(&kvm->slots_lock);
f51770ed 4759 return r;
b7ebfb05
SY
4760}
4761
6aa8b732
AK
4762static void seg_setup(int seg)
4763{
772e0318 4764 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4765 unsigned int ar;
6aa8b732
AK
4766
4767 vmcs_write16(sf->selector, 0);
4768 vmcs_writel(sf->base, 0);
4769 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN
4770 ar = 0x93;
4771 if (seg == VCPU_SREG_CS)
4772 ar |= 0x08; /* code segment */
3a624e29
NK
4773
4774 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK
4775}
4776
f78e0e2e
SY
4777static int alloc_apic_access_page(struct kvm *kvm)
4778{
4484141a 4779 struct page *page;
f78e0e2e
SY
4780 int r = 0;
4781
79fac95e 4782 mutex_lock(&kvm->slots_lock);
c24ae0dc 4783 if (kvm->arch.apic_access_page_done)
f78e0e2e 4784 goto out;
1d8007bd
PB
4785 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4786 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY
4787 if (r)
4788 goto out;
72dc67a6 4789
73a6d941 4790 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG
4791 if (is_error_page(page)) {
4792 r = -EFAULT;
4793 goto out;
4794 }
4795
c24ae0dc
TC
4796 /*
4797 * Do not pin the page in memory, so that memory hot-unplug
4798 * is able to migrate it.
4799 */
4800 put_page(page);
4801 kvm->arch.apic_access_page_done = true;
f78e0e2e 4802out:
79fac95e 4803 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY
4804 return r;
4805}
4806
b7ebfb05
SY
4807static int alloc_identity_pagetable(struct kvm *kvm)
4808{
a255d479
TC
4809 /* Called with kvm->slots_lock held. */
4810
b7ebfb05
SY
4811 int r = 0;
4812
a255d479
TC
4813 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4814
1d8007bd
PB
4815 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4816 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
b7ebfb05 4817
b7ebfb05
SY
4818 return r;
4819}
4820
991e7a0e 4821static int allocate_vpid(void)
2384d2b3
SY
4822{
4823 int vpid;
4824
919818ab 4825 if (!enable_vpid)
991e7a0e 4826 return 0;
2384d2b3
SY
4827 spin_lock(&vmx_vpid_lock);
4828 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 4829 if (vpid < VMX_NR_VPIDS)
2384d2b3 4830 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL
4831 else
4832 vpid = 0;
2384d2b3 4833 spin_unlock(&vmx_vpid_lock);
991e7a0e 4834 return vpid;
2384d2b3
SY
4835}
4836
991e7a0e 4837static void free_vpid(int vpid)
cdbecfc3 4838{
991e7a0e 4839 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ
4840 return;
4841 spin_lock(&vmx_vpid_lock);
991e7a0e 4842 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ
4843 spin_unlock(&vmx_vpid_lock);
4844}
4845
8d14695f
YZ
4846#define MSR_TYPE_R 1
4847#define MSR_TYPE_W 2
4848static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4849 u32 msr, int type)
25c5f225 4850{
3e7c73e9 4851 int f = sizeof(unsigned long);
25c5f225
SY
4852
4853 if (!cpu_has_vmx_msr_bitmap())
4854 return;
4855
4856 /*
4857 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4858 * have the write-low and read-high bitmap offsets the wrong way round.
4859 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4860 */
25c5f225 4861 if (msr <= 0x1fff) {
8d14695f
YZ
4862 if (type & MSR_TYPE_R)
4863 /* read-low */
4864 __clear_bit(msr, msr_bitmap + 0x000 / f);
4865
4866 if (type & MSR_TYPE_W)
4867 /* write-low */
4868 __clear_bit(msr, msr_bitmap + 0x800 / f);
4869
25c5f225
SY
4870 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4871 msr &= 0x1fff;
8d14695f
YZ
4872 if (type & MSR_TYPE_R)
4873 /* read-high */
4874 __clear_bit(msr, msr_bitmap + 0x400 / f);
4875
4876 if (type & MSR_TYPE_W)
4877 /* write-high */
4878 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4879
4880 }
4881}
4882
f2b93280
WV
4883/*
4884 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4885 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4886 */
4887static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4888 unsigned long *msr_bitmap_nested,
4889 u32 msr, int type)
4890{
4891 int f = sizeof(unsigned long);
4892
4893 if (!cpu_has_vmx_msr_bitmap()) {
4894 WARN_ON(1);
4895 return;
4896 }
4897
4898 /*
4899 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4900 * have the write-low and read-high bitmap offsets the wrong way round.
4901 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4902 */
4903 if (msr <= 0x1fff) {
4904 if (type & MSR_TYPE_R &&
4905 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4906 /* read-low */
4907 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4908
4909 if (type & MSR_TYPE_W &&
4910 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4911 /* write-low */
4912 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4913
4914 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4915 msr &= 0x1fff;
4916 if (type & MSR_TYPE_R &&
4917 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4918 /* read-high */
4919 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4920
4921 if (type & MSR_TYPE_W &&
4922 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4923 /* write-high */
4924 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4925
4926 }
4927}
4928
5897297b
AK
4929static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4930{
4931 if (!longmode_only)
8d14695f
YZ
4932 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4933 msr, MSR_TYPE_R | MSR_TYPE_W);
4934 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4935 msr, MSR_TYPE_R | MSR_TYPE_W);
4936}
4937
2e69f865 4938static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
8d14695f 4939{
f6e90f9e 4940 if (apicv_active) {
c63e4563 4941 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
2e69f865 4942 msr, type);
c63e4563 4943 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
2e69f865 4944 msr, type);
f6e90f9e 4945 } else {
f6e90f9e 4946 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
2e69f865 4947 msr, type);
f6e90f9e 4948 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
2e69f865 4949 msr, type);
f6e90f9e 4950 }
5897297b
AK
4951}
4952
d62caabb 4953static bool vmx_get_enable_apicv(void)
d50ab6c1 4954{
d62caabb 4955 return enable_apicv;
d50ab6c1
PB
4956}
4957
6342c50a 4958static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
705699a1
WV
4959{
4960 struct vcpu_vmx *vmx = to_vmx(vcpu);
4961 int max_irr;
4962 void *vapic_page;
4963 u16 status;
4964
4965 if (vmx->nested.pi_desc &&
4966 vmx->nested.pi_pending) {
4967 vmx->nested.pi_pending = false;
4968 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
6342c50a 4969 return;
705699a1
WV
4970
4971 max_irr = find_last_bit(
4972 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4973
4974 if (max_irr == 256)
6342c50a 4975 return;
705699a1
WV
4976
4977 vapic_page = kmap(vmx->nested.virtual_apic_page);
705699a1
WV
4978 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4979 kunmap(vmx->nested.virtual_apic_page);
4980
4981 status = vmcs_read16(GUEST_INTR_STATUS);
4982 if ((u8)max_irr > ((u8)status & 0xff)) {
4983 status &= ~0xff;
4984 status |= (u8)max_irr;
4985 vmcs_write16(GUEST_INTR_STATUS, status);
4986 }
4987 }
705699a1
WV
4988}
4989
06a5524f
WV
4990static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
4991 bool nested)
21bc8dc5
RK
4992{
4993#ifdef CONFIG_SMP
06a5524f
WV
4994 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
4995
21bc8dc5 4996 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6
FW
4997 struct vcpu_vmx *vmx = to_vmx(vcpu);
4998
4999 /*
5000 * Currently, we don't support urgent interrupt,
5001 * all interrupts are recognized as non-urgent
5002 * interrupt, so we cannot post interrupts when
5003 * 'SN' is set.
5004 *
5005 * If the vcpu is in guest mode, it means it is
5006 * running instead of being scheduled out and
5007 * waiting in the run queue, and that's the only
5008 * case when 'SN' is set currently, warning if
5009 * 'SN' is set.
5010 */
5011 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
5012
06a5524f 5013 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
21bc8dc5
RK
5014 return true;
5015 }
5016#endif
5017 return false;
5018}
5019
705699a1
WV
5020static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5021 int vector)
5022{
5023 struct vcpu_vmx *vmx = to_vmx(vcpu);
5024
5025 if (is_guest_mode(vcpu) &&
5026 vector == vmx->nested.posted_intr_nv) {
5027 /* the PIR and ON have been set by L1. */
06a5524f 5028 kvm_vcpu_trigger_posted_interrupt(vcpu, true);
705699a1
WV
5029 /*
5030 * If a posted intr is not recognized by hardware,
5031 * we will accomplish it in the next vmentry.
5032 */
5033 vmx->nested.pi_pending = true;
5034 kvm_make_request(KVM_REQ_EVENT, vcpu);
5035 return 0;
5036 }
5037 return -1;
5038}
a20ed54d
YZ
5039/*
5040 * Send interrupt to vcpu via posted interrupt way.
5041 * 1. If target vcpu is running(non-root mode), send posted interrupt
5042 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5043 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5044 * interrupt from PIR in next vmentry.
5045 */
5046static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5047{
5048 struct vcpu_vmx *vmx = to_vmx(vcpu);
5049 int r;
5050
705699a1
WV
5051 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5052 if (!r)
5053 return;
5054
a20ed54d
YZ
5055 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5056 return;
5057
b95234c8
PB
5058 /* If a previous notification has sent the IPI, nothing to do. */
5059 if (pi_test_and_set_on(&vmx->pi_desc))
5060 return;
5061
06a5524f 5062 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
a20ed54d
YZ
5063 kvm_vcpu_kick(vcpu);
5064}
5065
a3a8ff8e
NHE
5066/*
5067 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5068 * will not change in the lifetime of the guest.
5069 * Note that host-state that does change is set elsewhere. E.g., host-state
5070 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5071 */
a547c6db 5072static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE
5073{
5074 u32 low32, high32;
5075 unsigned long tmpl;
5076 struct desc_ptr dt;
d6e41f11 5077 unsigned long cr0, cr3, cr4;
a3a8ff8e 5078
04ac88ab
AL
5079 cr0 = read_cr0();
5080 WARN_ON(cr0 & X86_CR0_TS);
5081 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL
5082
5083 /*
5084 * Save the most likely value for this task's CR3 in the VMCS.
5085 * We can't use __get_current_cr3_fast() because we're not atomic.
5086 */
6c690ee1 5087 cr3 = __read_cr3();
d6e41f11
AL
5088 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5089 vmx->host_state.vmcs_host_cr3 = cr3;
a3a8ff8e 5090
d974baa3 5091 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 5092 cr4 = cr4_read_shadow();
d974baa3
AL
5093 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5094 vmx->host_state.vmcs_host_cr4 = cr4;
5095
a3a8ff8e 5096 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK
5097#ifdef CONFIG_X86_64
5098 /*
5099 * Load null selectors, so we can avoid reloading them in
5100 * __vmx_load_host_state(), in case userspace uses the null selectors
5101 * too (the expected case).
5102 */
5103 vmcs_write16(HOST_DS_SELECTOR, 0);
5104 vmcs_write16(HOST_ES_SELECTOR, 0);
5105#else
a3a8ff8e
NHE
5106 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5107 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 5108#endif
a3a8ff8e
NHE
5109 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5110 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5111
5112 native_store_idt(&dt);
5113 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 5114 vmx->host_idt_base = dt.address;
a3a8ff8e 5115
83287ea4 5116 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE
5117
5118 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5119 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5120 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5121 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5122
5123 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5124 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5125 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5126 }
5127}
5128
bf8179a0
NHE
5129static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5130{
5131 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5132 if (enable_ept)
5133 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE
5134 if (is_guest_mode(&vmx->vcpu))
5135 vmx->vcpu.arch.cr4_guest_owned_bits &=
5136 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE
5137 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5138}
5139
01e439be
YZ
5140static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5141{
5142 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5143
d62caabb 5144 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 5145 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
64672c95
YJ
5146 /* Enable the preemption timer dynamically */
5147 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ
5148 return pin_based_exec_ctrl;
5149}
5150
d62caabb
AS
5151static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5152{
5153 struct vcpu_vmx *vmx = to_vmx(vcpu);
5154
5155 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK
5156 if (cpu_has_secondary_exec_ctrls()) {
5157 if (kvm_vcpu_apicv_active(vcpu))
5158 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5159 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5160 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5161 else
5162 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5163 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5164 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5165 }
5166
5167 if (cpu_has_vmx_msr_bitmap())
5168 vmx_set_msr_bitmap(vcpu);
d62caabb
AS
5169}
5170
bf8179a0
NHE
5171static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5172{
5173 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB
5174
5175 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5176 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5177
35754c98 5178 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE
5179 exec_control &= ~CPU_BASED_TPR_SHADOW;
5180#ifdef CONFIG_X86_64
5181 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5182 CPU_BASED_CR8_LOAD_EXITING;
5183#endif
5184 }
5185 if (!enable_ept)
5186 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5187 CPU_BASED_CR3_LOAD_EXITING |
5188 CPU_BASED_INVLPG_EXITING;
5189 return exec_control;
5190}
5191
5192static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5193{
5194 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 5195 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE
5196 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5197 if (vmx->vpid == 0)
5198 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5199 if (!enable_ept) {
5200 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5201 enable_unrestricted_guest = 0;
ad756a16
MJ
5202 /* Enable INVPCID for non-ept guests may cause performance regression. */
5203 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE
5204 }
5205 if (!enable_unrestricted_guest)
5206 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5207 if (!ple_gap)
5208 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
d62caabb 5209 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
c7c9c56c
YZ
5210 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5211 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 5212 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG
5213 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5214 (handle_vmptrld).
5215 We can NOT enable shadow_vmcs here because we don't have yet
5216 a current VMCS12
5217 */
5218 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH
5219
5220 if (!enable_pml)
5221 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 5222
bf8179a0
NHE
5223 return exec_control;
5224}
5225
ce88decf
XG
5226static void ept_set_mmio_spte_mask(void)
5227{
5228 /*
5229 * EPT Misconfigurations can be generated if the value of bits 2:0
5230 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 5231 */
dcdca5fe
PF
5232 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5233 VMX_EPT_MISCONFIG_WX_VALUE);
ce88decf
XG
5234}
5235
f53cd63c 5236#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK
5237/*
5238 * Sets up the vmcs for emulated real mode.
5239 */
8b9cf98c 5240static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 5241{
2e4ce7f5 5242#ifdef CONFIG_X86_64
6aa8b732 5243 unsigned long a;
2e4ce7f5 5244#endif
6aa8b732 5245 int i;
6aa8b732 5246
6aa8b732 5247 /* I/O */
3e7c73e9
AK
5248 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5249 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 5250
4607c2d7
AG
5251 if (enable_shadow_vmcs) {
5252 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5253 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5254 }
25c5f225 5255 if (cpu_has_vmx_msr_bitmap())
5897297b 5256 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 5257
6aa8b732
AK
5258 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5259
6aa8b732 5260 /* Control */
01e439be 5261 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
64672c95 5262 vmx->hv_deadline_tsc = -1;
6e5d865c 5263
bf8179a0 5264 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 5265
dfa169bb 5266 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE
5267 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5268 vmx_secondary_exec_control(vmx));
dfa169bb 5269 }
f78e0e2e 5270
d62caabb 5271 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ
5272 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5273 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5274 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5275 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5276
5277 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 5278
0bcf261c 5279 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 5280 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ
5281 }
5282
4b8d54f9
ZE
5283 if (ple_gap) {
5284 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK
5285 vmx->ple_window = ple_window;
5286 vmx->ple_window_dirty = true;
4b8d54f9
ZE
5287 }
5288
c3707958
XG
5289 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5290 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK
5291 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5292
9581d442
AK
5293 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5294 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 5295 vmx_set_constant_host_state(vmx);
05b3e0c2 5296#ifdef CONFIG_X86_64
6aa8b732
AK
5297 rdmsrl(MSR_FS_BASE, a);
5298 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5299 rdmsrl(MSR_GS_BASE, a);
5300 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5301#else
5302 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5303 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5304#endif
5305
2cc51560
ED
5306 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5307 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 5308 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 5309 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 5310 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 5311
74545705
RK
5312 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5313 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 5314
03916db9 5315 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK
5316 u32 index = vmx_msr_index[i];
5317 u32 data_low, data_high;
a2fa3e9f 5318 int j = vmx->nmsrs;
6aa8b732
AK
5319
5320 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5321 continue;
432bd6cb
AK
5322 if (wrmsr_safe(index, data_low, data_high) < 0)
5323 continue;
26bb0981
AK
5324 vmx->guest_msrs[j].index = i;
5325 vmx->guest_msrs[j].data = 0;
d5696725 5326 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 5327 ++vmx->nmsrs;
6aa8b732 5328 }
6aa8b732 5329
2961e876
GN
5330
5331 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK
5332
5333 /* 22.2.1, 20.8.1 */
2961e876 5334 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 5335
bd7e5b08
PB
5336 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5337 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5338
bf8179a0 5339 set_cr4_guest_host_mask(vmx);
e00c8cf2 5340
f53cd63c
WL
5341 if (vmx_xsaves_supported())
5342 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5343
4e59516a
PF
5344 if (enable_pml) {
5345 ASSERT(vmx->pml_pg);
5346 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5347 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5348 }
5349
e00c8cf2
AK
5350 return 0;
5351}
5352
d28bc9dd 5353static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK
5354{
5355 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 5356 struct msr_data apic_base_msr;
d28bc9dd 5357 u64 cr0;
e00c8cf2 5358
7ffd92c5 5359 vmx->rmode.vm86_active = 0;
e00c8cf2 5360
ad312c7c 5361 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA
5362 kvm_set_cr8(vcpu, 0);
5363
5364 if (!init_event) {
5365 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5366 MSR_IA32_APICBASE_ENABLE;
5367 if (kvm_vcpu_is_reset_bsp(vcpu))
5368 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5369 apic_base_msr.host_initiated = true;
5370 kvm_set_apic_base(vcpu, &apic_base_msr);
5371 }
e00c8cf2 5372
2fb92db1
AK
5373 vmx_segment_cache_clear(vmx);
5374
5706be0d 5375 seg_setup(VCPU_SREG_CS);
66450a21 5376 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 5377 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK
5378
5379 seg_setup(VCPU_SREG_DS);
5380 seg_setup(VCPU_SREG_ES);
5381 seg_setup(VCPU_SREG_FS);
5382 seg_setup(VCPU_SREG_GS);
5383 seg_setup(VCPU_SREG_SS);
5384
5385 vmcs_write16(GUEST_TR_SELECTOR, 0);
5386 vmcs_writel(GUEST_TR_BASE, 0);
5387 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5388 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5389
5390 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5391 vmcs_writel(GUEST_LDTR_BASE, 0);
5392 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5393 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5394
d28bc9dd
NA
5395 if (!init_event) {
5396 vmcs_write32(GUEST_SYSENTER_CS, 0);
5397 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5398 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5399 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5400 }
e00c8cf2
AK
5401
5402 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 5403 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 5404
e00c8cf2
AK
5405 vmcs_writel(GUEST_GDTR_BASE, 0);
5406 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5407
5408 vmcs_writel(GUEST_IDTR_BASE, 0);
5409 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5410
443381a8 5411 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 5412 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 5413 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
e00c8cf2 5414
e00c8cf2
AK
5415 setup_msrs(vmx);
5416
6aa8b732
AK
5417 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5418
d28bc9dd 5419 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 5420 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 5421 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 5422 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 5423 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY
5424 vmcs_write32(TPR_THRESHOLD, 0);
5425 }
5426
a73896cb 5427 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 5428
d62caabb 5429 if (kvm_vcpu_apicv_active(vcpu))
01e439be
YZ
5430 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5431
2384d2b3
SY
5432 if (vmx->vpid != 0)
5433 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5434
d28bc9dd 5435 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 5436 vmx->vcpu.arch.cr0 = cr0;
f2463247 5437 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 5438 vmx_set_cr4(vcpu, 0);
5690891b 5439 vmx_set_efer(vcpu, 0);
bd7e5b08 5440
d28bc9dd 5441 update_exception_bitmap(vcpu);
6aa8b732 5442
dd5f5341 5443 vpid_sync_context(vmx->vpid);
6aa8b732
AK
5444}
5445
b6f1250e
NHE
5446/*
5447 * In nested virtualization, check if L1 asked to exit on external interrupts.
5448 * For most existing hypervisors, this will always return true.
5449 */
5450static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5451{
5452 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5453 PIN_BASED_EXT_INTR_MASK;
5454}
5455
77b0f5d6
BD
5456/*
5457 * In nested virtualization, check if L1 has set
5458 * VM_EXIT_ACK_INTR_ON_EXIT
5459 */
5460static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5461{
5462 return get_vmcs12(vcpu)->vm_exit_controls &
5463 VM_EXIT_ACK_INTR_ON_EXIT;
5464}
5465
ea8ceb83
JK
5466static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5467{
5468 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5469 PIN_BASED_NMI_EXITING;
5470}
5471
c9a7953f 5472static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 5473{
47c0152e
PB
5474 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5475 CPU_BASED_VIRTUAL_INTR_PENDING);
3b86cd99
JK
5476}
5477
c9a7953f 5478static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 5479{
2c82878b 5480 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK
5481 enable_irq_window(vcpu);
5482 return;
5483 }
3b86cd99 5484
47c0152e
PB
5485 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5486 CPU_BASED_VIRTUAL_NMI_PENDING);
3b86cd99
JK
5487}
5488
66fd3f7f 5489static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 5490{
9c8cba37 5491 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN
5492 uint32_t intr;
5493 int irq = vcpu->arch.interrupt.nr;
9c8cba37 5494
229456fc 5495 trace_kvm_inj_virq(irq);
2714d1d3 5496
fa89a817 5497 ++vcpu->stat.irq_injections;
7ffd92c5 5498 if (vmx->rmode.vm86_active) {
71f9833b
SH
5499 int inc_eip = 0;
5500 if (vcpu->arch.interrupt.soft)
5501 inc_eip = vcpu->arch.event_exit_inst_len;
5502 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 5503 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED
5504 return;
5505 }
66fd3f7f
GN
5506 intr = irq | INTR_INFO_VALID_MASK;
5507 if (vcpu->arch.interrupt.soft) {
5508 intr |= INTR_TYPE_SOFT_INTR;
5509 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5510 vmx->vcpu.arch.event_exit_inst_len);
5511 } else
5512 intr |= INTR_TYPE_EXT_INTR;
5513 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED
5514}
5515
f08864b4
SY
5516static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5517{
66a5a347
JK
5518 struct vcpu_vmx *vmx = to_vmx(vcpu);
5519
4c4a6f79
PB
5520 ++vcpu->stat.nmi_injections;
5521 vmx->loaded_vmcs->nmi_known_unmasked = false;
3b86cd99 5522
7ffd92c5 5523 if (vmx->rmode.vm86_active) {
71f9833b 5524 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 5525 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK
5526 return;
5527 }
c5a6d5f7 5528
f08864b4
SY
5529 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5530 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY
5531}
5532
3cfc3092
JK
5533static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5534{
4c4a6f79
PB
5535 struct vcpu_vmx *vmx = to_vmx(vcpu);
5536 bool masked;
5537
5538 if (vmx->loaded_vmcs->nmi_known_unmasked)
9d58b931 5539 return false;
4c4a6f79
PB
5540 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5541 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5542 return masked;
3cfc3092
JK
5543}
5544
5545static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5546{
5547 struct vcpu_vmx *vmx = to_vmx(vcpu);
5548
4c4a6f79 5549 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
2c82878b
PB
5550 if (masked)
5551 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5552 GUEST_INTR_STATE_NMI);
5553 else
5554 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5555 GUEST_INTR_STATE_NMI);
3cfc3092
JK
5556}
5557
2505dc9f
JK
5558static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5559{
b6b8a145
JK
5560 if (to_vmx(vcpu)->nested.nested_run_pending)
5561 return 0;
ea8ceb83 5562
2505dc9f
JK
5563 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5564 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5565 | GUEST_INTR_STATE_NMI));
5566}
5567
78646121
GN
5568static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5569{
b6b8a145
JK
5570 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5571 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN
5572 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5573 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN
5574}
5575
cbc94022
IE
5576static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5577{
5578 int ret;
cbc94022 5579
1d8007bd
PB
5580 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5581 PAGE_SIZE * 3);
cbc94022
IE
5582 if (ret)
5583 return ret;
bfc6d222 5584 kvm->arch.tss_addr = addr;
1f755a82 5585 return init_rmode_tss(kvm);
cbc94022
IE
5586}
5587
0ca1b4f4 5588static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 5589{
77ab6db0 5590 switch (vec) {
77ab6db0 5591 case BP_VECTOR:
c573cd22
JK
5592 /*
5593 * Update instruction length as we may reinject the exception
5594 * from user space while in guest debugging mode.
5595 */
5596 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5597 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 5598 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN
5599 return false;
5600 /* fall through */
5601 case DB_VECTOR:
5602 if (vcpu->guest_debug &
5603 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5604 return false;
d0bfb940
JK
5605 /* fall through */
5606 case DE_VECTOR:
77ab6db0
JK
5607 case OF_VECTOR:
5608 case BR_VECTOR:
5609 case UD_VECTOR:
5610 case DF_VECTOR:
5611 case SS_VECTOR:
5612 case GP_VECTOR:
5613 case MF_VECTOR:
0ca1b4f4
GN
5614 return true;
5615 break;
77ab6db0 5616 }
0ca1b4f4
GN
5617 return false;
5618}
5619
5620static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5621 int vec, u32 err_code)
5622{
5623 /*
5624 * Instruction with address size override prefix opcode 0x67
5625 * Cause the #SS fault with 0 error code in VM86 mode.
5626 */
5627 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5628 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5629 if (vcpu->arch.halt_request) {
5630 vcpu->arch.halt_request = 0;
5cb56059 5631 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN
5632 }
5633 return 1;
5634 }
5635 return 0;
5636 }
5637
5638 /*
5639 * Forward all other exceptions that are valid in real mode.
5640 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5641 * the required debugging infrastructure rework.
5642 */
5643 kvm_queue_exception(vcpu, vec);
5644 return 1;
6aa8b732
AK
5645}
5646
a0861c02
AK
5647/*
5648 * Trigger machine check on the host. We assume all the MSRs are already set up
5649 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5650 * We pass a fake environment to the machine check handler because we want
5651 * the guest to be always treated like user space, no matter what context
5652 * it used internally.
5653 */
5654static void kvm_machine_check(void)
5655{
5656#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5657 struct pt_regs regs = {
5658 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5659 .flags = X86_EFLAGS_IF,
5660 };
5661
5662 do_machine_check(&regs, 0);
5663#endif
5664}
5665
851ba692 5666static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK
5667{
5668 /* already handled by vcpu_run */
5669 return 1;
5670}
5671
851ba692 5672static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5673{
1155f76a 5674 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5675 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5676 u32 intr_info, ex_no, error_code;
42dbaa5a 5677 unsigned long cr2, rip, dr6;
6aa8b732
AK
5678 u32 vect_info;
5679 enum emulation_result er;
5680
1155f76a 5681 vect_info = vmx->idt_vectoring_info;
88786475 5682 intr_info = vmx->exit_intr_info;
6aa8b732 5683
a0861c02 5684 if (is_machine_check(intr_info))
851ba692 5685 return handle_machine_check(vcpu);
a0861c02 5686
ef85b673 5687 if (is_nmi(intr_info))
1b6269db 5688 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc 5689
7aa81cc0 5690 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK
5691 if (is_guest_mode(vcpu)) {
5692 kvm_queue_exception(vcpu, UD_VECTOR);
5693 return 1;
5694 }
51d8b661 5695 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5696 if (er != EMULATE_DONE)
7ee5d940 5697 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL
5698 return 1;
5699 }
5700
6aa8b732 5701 error_code = 0;
2e11384c 5702 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5703 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG
5704
5705 /*
5706 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5707 * MMIO, it is better to report an internal error.
5708 * See the comments in vmx_handle_exit.
5709 */
5710 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5711 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5712 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5713 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5714 vcpu->run->internal.ndata = 3;
bf4ca23e
XG
5715 vcpu->run->internal.data[0] = vect_info;
5716 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5717 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG
5718 return 0;
5719 }
5720
6aa8b732
AK
5721 if (is_page_fault(intr_info)) {
5722 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1261bfa3
WL
5723 /* EPT won't cause page fault directly */
5724 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
5725 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0,
5726 true);
6aa8b732
AK
5727 }
5728
d0bfb940 5729 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN
5730
5731 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5732 return handle_rmode_exception(vcpu, ex_no, error_code);
5733
42dbaa5a 5734 switch (ex_no) {
54a20552
EN
5735 case AC_VECTOR:
5736 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5737 return 1;
42dbaa5a
JK
5738 case DB_VECTOR:
5739 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5740 if (!(vcpu->guest_debug &
5741 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5742 vcpu->arch.dr6 &= ~15;
6f43ed01 5743 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD
5744 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5745 skip_emulated_instruction(vcpu);
5746
42dbaa5a
JK
5747 kvm_queue_exception(vcpu, DB_VECTOR);
5748 return 1;
5749 }
5750 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5751 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5752 /* fall through */
5753 case BP_VECTOR:
c573cd22
JK
5754 /*
5755 * Update instruction length as we may reinject #BP from
5756 * user space while in guest debugging mode. Reading it for
5757 * #DB as well causes no harm, it is not used in that case.
5758 */
5759 vmx->vcpu.arch.event_exit_inst_len =
5760 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5761 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5762 rip = kvm_rip_read(vcpu);
d0bfb940
JK
5763 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5764 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK
5765 break;
5766 default:
d0bfb940
JK
5767 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5768 kvm_run->ex.exception = ex_no;
5769 kvm_run->ex.error_code = error_code;
42dbaa5a 5770 break;
6aa8b732 5771 }
6aa8b732
AK
5772 return 0;
5773}
5774
851ba692 5775static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5776{
1165f5fe 5777 ++vcpu->stat.irq_exits;
6aa8b732
AK
5778 return 1;
5779}
5780
851ba692 5781static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5782{
851ba692 5783 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK
5784 return 0;
5785}
6aa8b732 5786
851ba692 5787static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5788{
bfdaab09 5789 unsigned long exit_qualification;
6affcbed 5790 int size, in, string, ret;
039576c0 5791 unsigned port;
6aa8b732 5792
bfdaab09 5793 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5794 string = (exit_qualification & 16) != 0;
cf8f70bf 5795 in = (exit_qualification & 8) != 0;
e70669ab 5796
cf8f70bf 5797 ++vcpu->stat.io_exits;
e70669ab 5798
cf8f70bf 5799 if (string || in)
51d8b661 5800 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5801
cf8f70bf
GN
5802 port = exit_qualification >> 16;
5803 size = (exit_qualification & 7) + 1;
cf8f70bf 5804
6affcbed
KH
5805 ret = kvm_skip_emulated_instruction(vcpu);
5806
5807 /*
5808 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5809 * KVM_EXIT_DEBUG here.
5810 */
5811 return kvm_fast_pio_out(vcpu, size, port) && ret;
6aa8b732
AK
5812}
5813
102d8325
IM
5814static void
5815vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5816{
5817 /*
5818 * Patch in the VMCALL instruction:
5819 */
5820 hypercall[0] = 0x0f;
5821 hypercall[1] = 0x01;
5822 hypercall[2] = 0xc1;
102d8325
IM
5823}
5824
0fa06071 5825/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE
5826static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5827{
eeadf9e7 5828 if (is_guest_mode(vcpu)) {
1a0d74e6
JK
5829 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5830 unsigned long orig_val = val;
5831
eeadf9e7
NHE
5832 /*
5833 * We get here when L2 changed cr0 in a way that did not change
5834 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK
5835 * but did change L0 shadowed bits. So we first calculate the
5836 * effective cr0 value that L1 would like to write into the
5837 * hardware. It consists of the L2-owned bits from the new
5838 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5839 */
1a0d74e6
JK
5840 val = (val & ~vmcs12->cr0_guest_host_mask) |
5841 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5842
3899152c 5843 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 5844 return 1;
1a0d74e6
JK
5845
5846 if (kvm_set_cr0(vcpu, val))
5847 return 1;
5848 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5849 return 0;
1a0d74e6
JK
5850 } else {
5851 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 5852 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 5853 return 1;
3899152c 5854
eeadf9e7 5855 return kvm_set_cr0(vcpu, val);
1a0d74e6 5856 }
eeadf9e7
NHE
5857}
5858
5859static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5860{
5861 if (is_guest_mode(vcpu)) {
1a0d74e6
JK
5862 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5863 unsigned long orig_val = val;
5864
5865 /* analogously to handle_set_cr0 */
5866 val = (val & ~vmcs12->cr4_guest_host_mask) |
5867 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5868 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5869 return 1;
1a0d74e6 5870 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE
5871 return 0;
5872 } else
5873 return kvm_set_cr4(vcpu, val);
5874}
5875
851ba692 5876static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5877{
229456fc 5878 unsigned long exit_qualification, val;
6aa8b732
AK
5879 int cr;
5880 int reg;
49a9b07e 5881 int err;
6affcbed 5882 int ret;
6aa8b732 5883
bfdaab09 5884 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK
5885 cr = exit_qualification & 15;
5886 reg = (exit_qualification >> 8) & 15;
5887 switch ((exit_qualification >> 4) & 3) {
5888 case 0: /* mov to cr */
1e32c079 5889 val = kvm_register_readl(vcpu, reg);
229456fc 5890 trace_kvm_cr_write(cr, val);
6aa8b732
AK
5891 switch (cr) {
5892 case 0:
eeadf9e7 5893 err = handle_set_cr0(vcpu, val);
6affcbed 5894 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 5895 case 3:
2390218b 5896 err = kvm_set_cr3(vcpu, val);
6affcbed 5897 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 5898 case 4:
eeadf9e7 5899 err = handle_set_cr4(vcpu, val);
6affcbed 5900 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN
5901 case 8: {
5902 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5903 u8 cr8 = (u8)val;
eea1cff9 5904 err = kvm_set_cr8(vcpu, cr8);
6affcbed 5905 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 5906 if (lapic_in_kernel(vcpu))
6affcbed 5907 return ret;
0a5fff19 5908 if (cr8_prev <= cr8)
6affcbed
KH
5909 return ret;
5910 /*
5911 * TODO: we might be squashing a
5912 * KVM_GUESTDBG_SINGLESTEP-triggered
5913 * KVM_EXIT_DEBUG here.
5914 */
851ba692 5915 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN
5916 return 0;
5917 }
4b8073e4 5918 }
6aa8b732 5919 break;
25c4c276 5920 case 2: /* clts */
bd7e5b08
PB
5921 WARN_ONCE(1, "Guest should always own CR0.TS");
5922 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 5923 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 5924 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5925 case 1: /*mov from cr*/
5926 switch (cr) {
5927 case 3:
9f8fe504
AK
5928 val = kvm_read_cr3(vcpu);
5929 kvm_register_write(vcpu, reg, val);
5930 trace_kvm_cr_read(cr, val);
6affcbed 5931 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 5932 case 8:
229456fc
MT
5933 val = kvm_get_cr8(vcpu);
5934 kvm_register_write(vcpu, reg, val);
5935 trace_kvm_cr_read(cr, val);
6affcbed 5936 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5937 }
5938 break;
5939 case 3: /* lmsw */
a1f83a74 5940 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5941 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5942 kvm_lmsw(vcpu, val);
6aa8b732 5943
6affcbed 5944 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5945 default:
5946 break;
5947 }
851ba692 5948 vcpu->run->exit_reason = 0;
a737f256 5949 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK
5950 (int)(exit_qualification >> 4) & 3, cr);
5951 return 0;
5952}
5953
851ba692 5954static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5955{
bfdaab09 5956 unsigned long exit_qualification;
16f8a6f9
NA
5957 int dr, dr7, reg;
5958
5959 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5960 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5961
5962 /* First, if DR does not exist, trigger UD */
5963 if (!kvm_require_dr(vcpu, dr))
5964 return 1;
6aa8b732 5965
f2483415 5966 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK
5967 if (!kvm_require_cpl(vcpu, 0))
5968 return 1;
16f8a6f9
NA
5969 dr7 = vmcs_readl(GUEST_DR7);
5970 if (dr7 & DR7_GD) {
42dbaa5a
JK
5971 /*
5972 * As the vm-exit takes precedence over the debug trap, we
5973 * need to emulate the latter, either for the host or the
5974 * guest debugging itself.
5975 */
5976 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5977 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5978 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5979 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK
5980 vcpu->run->debug.arch.exception = DB_VECTOR;
5981 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK
5982 return 0;
5983 } else {
7305eb5d 5984 vcpu->arch.dr6 &= ~15;
6f43ed01 5985 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK
5986 kvm_queue_exception(vcpu, DB_VECTOR);
5987 return 1;
5988 }
5989 }
5990
81908bf4 5991 if (vcpu->guest_debug == 0) {
8f22372f
PB
5992 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5993 CPU_BASED_MOV_DR_EXITING);
81908bf4
PB
5994
5995 /*
5996 * No more DR vmexits; force a reload of the debug registers
5997 * and reenter on this instruction. The next vmexit will
5998 * retrieve the full state of the debug registers.
5999 */
6000 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6001 return 1;
6002 }
6003
42dbaa5a
JK
6004 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6005 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 6006 unsigned long val;
4c4d563b
JK
6007
6008 if (kvm_get_dr(vcpu, dr, &val))
6009 return 1;
6010 kvm_register_write(vcpu, reg, val);
020df079 6011 } else
5777392e 6012 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK
6013 return 1;
6014
6affcbed 6015 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
6016}
6017
73aaf249
JK
6018static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6019{
6020 return vcpu->arch.dr6;
6021}
6022
6023static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6024{
6025}
6026
81908bf4
PB
6027static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6028{
81908bf4
PB
6029 get_debugreg(vcpu->arch.db[0], 0);
6030 get_debugreg(vcpu->arch.db[1], 1);
6031 get_debugreg(vcpu->arch.db[2], 2);
6032 get_debugreg(vcpu->arch.db[3], 3);
6033 get_debugreg(vcpu->arch.dr6, 6);
6034 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6035
6036 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
8f22372f 6037 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
81908bf4
PB
6038}
6039
020df079
GN
6040static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6041{
6042 vmcs_writel(GUEST_DR7, val);
6043}
6044
851ba692 6045static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 6046{
6a908b62 6047 return kvm_emulate_cpuid(vcpu);
6aa8b732
AK
6048}
6049
851ba692 6050static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 6051{
ad312c7c 6052 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 6053 struct msr_data msr_info;
6aa8b732 6054
609e36d3
PB
6055 msr_info.index = ecx;
6056 msr_info.host_initiated = false;
6057 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 6058 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 6059 kvm_inject_gp(vcpu, 0);
6aa8b732
AK
6060 return 1;
6061 }
6062
609e36d3 6063 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 6064
6aa8b732 6065 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB
6066 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6067 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6affcbed 6068 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
6069}
6070
851ba692 6071static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 6072{
8fe8ab46 6073 struct msr_data msr;
ad312c7c
ZX
6074 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6075 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6076 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 6077
8fe8ab46
WA
6078 msr.data = data;
6079 msr.index = ecx;
6080 msr.host_initiated = false;
854e8bb1 6081 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 6082 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 6083 kvm_inject_gp(vcpu, 0);
6aa8b732
AK
6084 return 1;
6085 }
6086
59200273 6087 trace_kvm_msr_write(ecx, data);
6affcbed 6088 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
6089}
6090
851ba692 6091static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 6092{
eb90f341 6093 kvm_apic_update_ppr(vcpu);
6e5d865c
YS
6094 return 1;
6095}
6096
851ba692 6097static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 6098{
47c0152e
PB
6099 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6100 CPU_BASED_VIRTUAL_INTR_PENDING);
2714d1d3 6101
3842d135
AK
6102 kvm_make_request(KVM_REQ_EVENT, vcpu);
6103
a26bf12a 6104 ++vcpu->stat.irq_window_exits;
6aa8b732
AK
6105 return 1;
6106}
6107
851ba692 6108static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 6109{
d3bef15f 6110 return kvm_emulate_halt(vcpu);
6aa8b732
AK
6111}
6112
851ba692 6113static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 6114{
0d9c055e 6115 return kvm_emulate_hypercall(vcpu);
c21415e8
IM
6116}
6117
ec25d5e6
GN
6118static int handle_invd(struct kvm_vcpu *vcpu)
6119{
51d8b661 6120 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN
6121}
6122
851ba692 6123static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 6124{
f9c617f6 6125 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT
6126
6127 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 6128 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT
6129}
6130
fee84b07
AK
6131static int handle_rdpmc(struct kvm_vcpu *vcpu)
6132{
6133 int err;
6134
6135 err = kvm_rdpmc(vcpu);
6affcbed 6136 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK
6137}
6138
851ba692 6139static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 6140{
6affcbed 6141 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED
6142}
6143
2acf923e
DC
6144static int handle_xsetbv(struct kvm_vcpu *vcpu)
6145{
6146 u64 new_bv = kvm_read_edx_eax(vcpu);
6147 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6148
6149 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 6150 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC
6151 return 1;
6152}
6153
f53cd63c
WL
6154static int handle_xsaves(struct kvm_vcpu *vcpu)
6155{
6affcbed 6156 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL
6157 WARN(1, "this should never happen\n");
6158 return 1;
6159}
6160
6161static int handle_xrstors(struct kvm_vcpu *vcpu)
6162{
6affcbed 6163 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL
6164 WARN(1, "this should never happen\n");
6165 return 1;
6166}
6167
851ba692 6168static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 6169{
58fbbf26
KT
6170 if (likely(fasteoi)) {
6171 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6172 int access_type, offset;
6173
6174 access_type = exit_qualification & APIC_ACCESS_TYPE;
6175 offset = exit_qualification & APIC_ACCESS_OFFSET;
6176 /*
6177 * Sane guest uses MOV to write EOI, with written value
6178 * not cared. So make a short-circuit here by avoiding
6179 * heavy instruction emulation.
6180 */
6181 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6182 (offset == APIC_EOI)) {
6183 kvm_lapic_set_eoi(vcpu);
6affcbed 6184 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT
6185 }
6186 }
51d8b661 6187 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY
6188}
6189
c7c9c56c
YZ
6190static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6191{
6192 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6193 int vector = exit_qualification & 0xff;
6194
6195 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6196 kvm_apic_set_eoi_accelerated(vcpu, vector);
6197 return 1;
6198}
6199
83d4c286
YZ
6200static int handle_apic_write(struct kvm_vcpu *vcpu)
6201{
6202 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6203 u32 offset = exit_qualification & 0xfff;
6204
6205 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6206 kvm_apic_write_nodecode(vcpu, offset);
6207 return 1;
6208}
6209
851ba692 6210static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 6211{
60637aac 6212 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 6213 unsigned long exit_qualification;
e269fb21
JK
6214 bool has_error_code = false;
6215 u32 error_code = 0;
37817f29 6216 u16 tss_selector;
7f3d35fd 6217 int reason, type, idt_v, idt_index;
64a7ec06
GN
6218
6219 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 6220 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 6221 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE
6222
6223 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6224
6225 reason = (u32)exit_qualification >> 30;
64a7ec06
GN
6226 if (reason == TASK_SWITCH_GATE && idt_v) {
6227 switch (type) {
6228 case INTR_TYPE_NMI_INTR:
6229 vcpu->arch.nmi_injected = false;
654f06fc 6230 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN
6231 break;
6232 case INTR_TYPE_EXT_INTR:
66fd3f7f 6233 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN
6234 kvm_clear_interrupt_queue(vcpu);
6235 break;
6236 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK
6237 if (vmx->idt_vectoring_info &
6238 VECTORING_INFO_DELIVER_CODE_MASK) {
6239 has_error_code = true;
6240 error_code =
6241 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6242 }
6243 /* fall through */
64a7ec06
GN
6244 case INTR_TYPE_SOFT_EXCEPTION:
6245 kvm_clear_exception_queue(vcpu);
6246 break;
6247 default:
6248 break;
6249 }
60637aac 6250 }
37817f29
IE
6251 tss_selector = exit_qualification;
6252
64a7ec06
GN
6253 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6254 type != INTR_TYPE_EXT_INTR &&
6255 type != INTR_TYPE_NMI_INTR))
6256 skip_emulated_instruction(vcpu);
6257
7f3d35fd
KW
6258 if (kvm_task_switch(vcpu, tss_selector,
6259 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6260 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN
6261 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6262 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6263 vcpu->run->internal.ndata = 0;
42dbaa5a 6264 return 0;
acb54517 6265 }
42dbaa5a 6266
42dbaa5a
JK
6267 /*
6268 * TODO: What about debug traps on tss switch?
6269 * Are we supposed to inject them and update dr6?
6270 */
6271
6272 return 1;
37817f29
IE
6273}
6274
851ba692 6275static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 6276{
f9c617f6 6277 unsigned long exit_qualification;
1439442c 6278 gpa_t gpa;
4f5982a5 6279 u32 error_code;
1439442c 6280
f9c617f6 6281 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 6282
0be9c7a8
GN
6283 /*
6284 * EPT violation happened while executing iret from NMI,
6285 * "blocked by NMI" bit has to be set before next VM entry.
6286 * There are errata that may cause this bit to not be set:
6287 * AAK134, BY25.
6288 */
bcd1c294 6289 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
bcd1c294 6290 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN
6291 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6292
1439442c 6293 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 6294 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 6295
27959a44 6296 /* Is it a read fault? */
ab22a473 6297 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS
6298 ? PFERR_USER_MASK : 0;
6299 /* Is it a write fault? */
ab22a473 6300 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS
6301 ? PFERR_WRITE_MASK : 0;
6302 /* Is it a fetch fault? */
ab22a473 6303 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS
6304 ? PFERR_FETCH_MASK : 0;
6305 /* ept page table entry is present? */
6306 error_code |= (exit_qualification &
6307 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6308 EPT_VIOLATION_EXECUTABLE))
6309 ? PFERR_PRESENT_MASK : 0;
4f5982a5 6310
db1c056c 6311 vcpu->arch.gpa_available = true;
25d92081
YZ
6312 vcpu->arch.exit_qualification = exit_qualification;
6313
4f5982a5 6314 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY
6315}
6316
851ba692 6317static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 6318{
f735d4af 6319 int ret;
68f89400
MT
6320 gpa_t gpa;
6321
6322 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 6323 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 6324 trace_kvm_fast_mmio(gpa);
6affcbed 6325 return kvm_skip_emulated_instruction(vcpu);
68c3b4d1 6326 }
68f89400 6327
450869d6 6328 ret = handle_mmio_page_fault(vcpu, gpa, true);
db1c056c 6329 vcpu->arch.gpa_available = true;
b37fbea6 6330 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG
6331 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6332 EMULATE_DONE;
f8f55942
XG
6333
6334 if (unlikely(ret == RET_MMIO_PF_INVALID))
6335 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6336
b37fbea6 6337 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG
6338 return 1;
6339
6340 /* It is the real ept misconfig */
f735d4af 6341 WARN_ON(1);
68f89400 6342
851ba692
AK
6343 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6344 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT
6345
6346 return 0;
6347}
6348
851ba692 6349static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 6350{
47c0152e
PB
6351 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6352 CPU_BASED_VIRTUAL_NMI_PENDING);
f08864b4 6353 ++vcpu->stat.nmi_window_exits;
3842d135 6354 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY
6355
6356 return 1;
6357}
6358
80ced186 6359static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 6360{
8b3079a5
AK
6361 struct vcpu_vmx *vmx = to_vmx(vcpu);
6362 enum emulation_result err = EMULATE_DONE;
80ced186 6363 int ret = 1;
49e9d557
AK
6364 u32 cpu_exec_ctrl;
6365 bool intr_window_requested;
b8405c18 6366 unsigned count = 130;
49e9d557
AK
6367
6368 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6369 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 6370
98eb2f8b 6371 while (vmx->emulation_required && count-- != 0) {
bdea48e3 6372 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK
6373 return handle_interrupt_window(&vmx->vcpu);
6374
72875d8a 6375 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK
6376 return 1;
6377
991eebf9 6378 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 6379
ac0a48c3 6380 if (err == EMULATE_USER_EXIT) {
94452b9e 6381 ++vcpu->stat.mmio_exits;
80ced186
MG
6382 ret = 0;
6383 goto out;
6384 }
1d5a4d9b 6385
de5f70e0
AK
6386 if (err != EMULATE_DONE) {
6387 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6388 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6389 vcpu->run->internal.ndata = 0;
6d77dbfc 6390 return 0;
de5f70e0 6391 }
ea953ef0 6392
8d76c49e
GN
6393 if (vcpu->arch.halt_request) {
6394 vcpu->arch.halt_request = 0;
5cb56059 6395 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN
6396 goto out;
6397 }
6398
ea953ef0 6399 if (signal_pending(current))
80ced186 6400 goto out;
ea953ef0
MG
6401 if (need_resched())
6402 schedule();
6403 }
6404
80ced186
MG
6405out:
6406 return ret;
ea953ef0
MG
6407}
6408
b4a2d31d
RK
6409static int __grow_ple_window(int val)
6410{
6411 if (ple_window_grow < 1)
6412 return ple_window;
6413
6414 val = min(val, ple_window_actual_max);
6415
6416 if (ple_window_grow < ple_window)
6417 val *= ple_window_grow;
6418 else
6419 val += ple_window_grow;
6420
6421 return val;
6422}
6423
6424static int __shrink_ple_window(int val, int modifier, int minimum)
6425{
6426 if (modifier < 1)
6427 return ple_window;
6428
6429 if (modifier < ple_window)
6430 val /= modifier;
6431 else
6432 val -= modifier;
6433
6434 return max(val, minimum);
6435}
6436
6437static void grow_ple_window(struct kvm_vcpu *vcpu)
6438{
6439 struct vcpu_vmx *vmx = to_vmx(vcpu);
6440 int old = vmx->ple_window;
6441
6442 vmx->ple_window = __grow_ple_window(old);
6443
6444 if (vmx->ple_window != old)
6445 vmx->ple_window_dirty = true;
7b46268d
RK
6446
6447 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK
6448}
6449
6450static void shrink_ple_window(struct kvm_vcpu *vcpu)
6451{
6452 struct vcpu_vmx *vmx = to_vmx(vcpu);
6453 int old = vmx->ple_window;
6454
6455 vmx->ple_window = __shrink_ple_window(old,
6456 ple_window_shrink, ple_window);
6457
6458 if (vmx->ple_window != old)
6459 vmx->ple_window_dirty = true;
7b46268d
RK
6460
6461 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK
6462}
6463
6464/*
6465 * ple_window_actual_max is computed to be one grow_ple_window() below
6466 * ple_window_max. (See __grow_ple_window for the reason.)
6467 * This prevents overflows, because ple_window_max is int.
6468 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6469 * this process.
6470 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6471 */
6472static void update_ple_window_actual_max(void)
6473{
6474 ple_window_actual_max =
6475 __shrink_ple_window(max(ple_window_max, ple_window),
6476 ple_window_grow, INT_MIN);
6477}
6478
bf9f6ac8
FW
6479/*
6480 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6481 */
6482static void wakeup_handler(void)
6483{
6484 struct kvm_vcpu *vcpu;
6485 int cpu = smp_processor_id();
6486
6487 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6488 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6489 blocked_vcpu_list) {
6490 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6491
6492 if (pi_test_on(pi_desc) == 1)
6493 kvm_vcpu_kick(vcpu);
6494 }
6495 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6496}
6497
f160c7b7
JS
6498void vmx_enable_tdp(void)
6499{
6500 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6501 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6502 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6503 0ull, VMX_EPT_EXECUTABLE_MASK,
6504 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
995f00a6 6505 VMX_EPT_RWX_MASK);
f160c7b7
JS
6506
6507 ept_set_mmio_spte_mask();
6508 kvm_enable_tdp();
6509}
6510
f2c7648d
TC
6511static __init int hardware_setup(void)
6512{
34a1cd60
TC
6513 int r = -ENOMEM, i, msr;
6514
6515 rdmsrl_safe(MSR_EFER, &host_efer);
6516
6517 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6518 kvm_define_shared_msr(i, vmx_msr_index[i]);
6519
23611332
RK
6520 for (i = 0; i < VMX_BITMAP_NR; i++) {
6521 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6522 if (!vmx_bitmap[i])
6523 goto out;
6524 }
34a1cd60
TC
6525
6526 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
34a1cd60
TC
6527 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6528 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6529
6530 /*
6531 * Allow direct access to the PC debug port (it is often used for I/O
6532 * delays, but the vmexits simply slow things down).
6533 */
6534 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6535 clear_bit(0x80, vmx_io_bitmap_a);
6536
6537 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6538
6539 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6540 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6541
34a1cd60
TC
6542 if (setup_vmcs_config(&vmcs_config) < 0) {
6543 r = -EIO;
23611332 6544 goto out;
baa03522 6545 }
f2c7648d
TC
6546
6547 if (boot_cpu_has(X86_FEATURE_NX))
6548 kvm_enable_efer_bits(EFER_NX);
6549
08d839c4
WL
6550 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6551 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
f2c7648d 6552 enable_vpid = 0;
08d839c4 6553
f2c7648d
TC
6554 if (!cpu_has_vmx_shadow_vmcs())
6555 enable_shadow_vmcs = 0;
6556 if (enable_shadow_vmcs)
6557 init_vmcs_shadow_fields();
6558
6559 if (!cpu_has_vmx_ept() ||
6560 !cpu_has_vmx_ept_4levels()) {
6561 enable_ept = 0;
6562 enable_unrestricted_guest = 0;
6563 enable_ept_ad_bits = 0;
6564 }
6565
fce6ac4c 6566 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
f2c7648d
TC
6567 enable_ept_ad_bits = 0;
6568
6569 if (!cpu_has_vmx_unrestricted_guest())
6570 enable_unrestricted_guest = 0;
6571
ad15a296 6572 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC
6573 flexpriority_enabled = 0;
6574
ad15a296
PB
6575 /*
6576 * set_apic_access_page_addr() is used to reload apic access
6577 * page upon invalidation. No need to do anything if not
6578 * using the APIC_ACCESS_ADDR VMCS field.
6579 */
6580 if (!flexpriority_enabled)
f2c7648d 6581 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC
6582
6583 if (!cpu_has_vmx_tpr_shadow())
6584 kvm_x86_ops->update_cr8_intercept = NULL;
6585
6586 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6587 kvm_disable_largepages();
6588
6589 if (!cpu_has_vmx_ple())
6590 ple_gap = 0;
6591
76dfafd5 6592 if (!cpu_has_vmx_apicv()) {
f2c7648d 6593 enable_apicv = 0;
76dfafd5
PB
6594 kvm_x86_ops->sync_pir_to_irr = NULL;
6595 }
f2c7648d 6596
64903d61
HZ
6597 if (cpu_has_vmx_tsc_scaling()) {
6598 kvm_has_tsc_control = true;
6599 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6600 kvm_tsc_scaling_ratio_frac_bits = 48;
6601 }
6602
baa03522
TC
6603 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6604 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6605 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6606 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6607 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6608 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
baa03522 6609
c63e4563 6610 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
baa03522 6611 vmx_msr_bitmap_legacy, PAGE_SIZE);
c63e4563 6612 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
baa03522 6613 vmx_msr_bitmap_longmode, PAGE_SIZE);
c63e4563 6614 memcpy(vmx_msr_bitmap_legacy_x2apic,
f6e90f9e 6615 vmx_msr_bitmap_legacy, PAGE_SIZE);
c63e4563 6616 memcpy(vmx_msr_bitmap_longmode_x2apic,
f6e90f9e 6617 vmx_msr_bitmap_longmode, PAGE_SIZE);
baa03522 6618
04bb92e4
WL
6619 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6620
40d8338d
RK
6621 for (msr = 0x800; msr <= 0x8ff; msr++) {
6622 if (msr == 0x839 /* TMCCT */)
6623 continue;
2e69f865 6624 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
40d8338d 6625 }
3ce424e4 6626
f6e90f9e 6627 /*
2e69f865
RK
6628 * TPR reads and writes can be virtualized even if virtual interrupt
6629 * delivery is not in use.
f6e90f9e 6630 */
2e69f865
RK
6631 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6632 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
3ce424e4 6633
3ce424e4 6634 /* EOI */
2e69f865 6635 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
3ce424e4 6636 /* SELF-IPI */
2e69f865 6637 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
baa03522 6638
f160c7b7
JS
6639 if (enable_ept)
6640 vmx_enable_tdp();
6641 else
baa03522
TC
6642 kvm_disable_tdp();
6643
6644 update_ple_window_actual_max();
6645
843e4330
KH
6646 /*
6647 * Only enable PML when hardware supports PML feature, and both EPT
6648 * and EPT A/D bit features are enabled -- PML depends on them to work.
6649 */
6650 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6651 enable_pml = 0;
6652
6653 if (!enable_pml) {
6654 kvm_x86_ops->slot_enable_log_dirty = NULL;
6655 kvm_x86_ops->slot_disable_log_dirty = NULL;
6656 kvm_x86_ops->flush_log_dirty = NULL;
6657 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6658 }
6659
64672c95
YJ
6660 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6661 u64 vmx_msr;
6662
6663 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6664 cpu_preemption_timer_multi =
6665 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6666 } else {
6667 kvm_x86_ops->set_hv_timer = NULL;
6668 kvm_x86_ops->cancel_hv_timer = NULL;
6669 }
6670
bf9f6ac8
FW
6671 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6672
c45dcc71
AR
6673 kvm_mce_cap_supported |= MCG_LMCE_P;
6674
f2c7648d 6675 return alloc_kvm_area();
34a1cd60 6676
34a1cd60 6677out:
23611332
RK
6678 for (i = 0; i < VMX_BITMAP_NR; i++)
6679 free_page((unsigned long)vmx_bitmap[i]);
34a1cd60
TC
6680
6681 return r;
f2c7648d
TC
6682}
6683
6684static __exit void hardware_unsetup(void)
6685{
23611332
RK
6686 int i;
6687
6688 for (i = 0; i < VMX_BITMAP_NR; i++)
6689 free_page((unsigned long)vmx_bitmap[i]);
34a1cd60 6690
f2c7648d
TC
6691 free_kvm_area();
6692}
6693
4b8d54f9
ZE
6694/*
6695 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6696 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6697 */
9fb41ba8 6698static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6699{
b4a2d31d
RK
6700 if (ple_gap)
6701 grow_ple_window(vcpu);
6702
4b8d54f9 6703 kvm_vcpu_on_spin(vcpu);
6affcbed 6704 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE
6705}
6706
87c00572 6707static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6708{
6affcbed 6709 return kvm_skip_emulated_instruction(vcpu);
59708670
SY
6710}
6711
87c00572
GS
6712static int handle_mwait(struct kvm_vcpu *vcpu)
6713{
6714 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6715 return handle_nop(vcpu);
6716}
6717
5f3d45e7
MD
6718static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6719{
6720 return 1;
6721}
6722
87c00572
GS
6723static int handle_monitor(struct kvm_vcpu *vcpu)
6724{
6725 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6726 return handle_nop(vcpu);
6727}
6728
ff2f6fe9
NHE
6729/*
6730 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6731 * We could reuse a single VMCS for all the L2 guests, but we also want the
6732 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6733 * allows keeping them loaded on the processor, and in the future will allow
6734 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6735 * every entry if they never change.
6736 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6737 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6738 *
6739 * The following functions allocate and free a vmcs02 in this pool.
6740 */
6741
6742/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6743static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6744{
6745 struct vmcs02_list *item;
6746 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6747 if (item->vmptr == vmx->nested.current_vmptr) {
6748 list_move(&item->list, &vmx->nested.vmcs02_pool);
6749 return &item->vmcs02;
6750 }
6751
6752 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6753 /* Recycle the least recently used VMCS. */
d74c0e6b
GT
6754 item = list_last_entry(&vmx->nested.vmcs02_pool,
6755 struct vmcs02_list, list);
ff2f6fe9
NHE
6756 item->vmptr = vmx->nested.current_vmptr;
6757 list_move(&item->list, &vmx->nested.vmcs02_pool);
6758 return &item->vmcs02;
6759 }
6760
6761 /* Create a new VMCS */
0fa24ce3 6762 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE
6763 if (!item)
6764 return NULL;
6765 item->vmcs02.vmcs = alloc_vmcs();
355f4fb1 6766 item->vmcs02.shadow_vmcs = NULL;
ff2f6fe9
NHE
6767 if (!item->vmcs02.vmcs) {
6768 kfree(item);
6769 return NULL;
6770 }
6771 loaded_vmcs_init(&item->vmcs02);
6772 item->vmptr = vmx->nested.current_vmptr;
6773 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6774 vmx->nested.vmcs02_num++;
6775 return &item->vmcs02;
6776}
6777
6778/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6779static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6780{
6781 struct vmcs02_list *item;
6782 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6783 if (item->vmptr == vmptr) {
6784 free_loaded_vmcs(&item->vmcs02);
6785 list_del(&item->list);
6786 kfree(item);
6787 vmx->nested.vmcs02_num--;
6788 return;
6789 }
6790}
6791
6792/*
6793 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB
6794 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6795 * must be &vmx->vmcs01.
ff2f6fe9
NHE
6796 */
6797static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6798{
6799 struct vmcs02_list *item, *n;
4fa7734c
PB
6800
6801 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6802 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB
6803 /*
6804 * Something will leak if the above WARN triggers. Better than
6805 * a use-after-free.
6806 */
6807 if (vmx->loaded_vmcs == &item->vmcs02)
6808 continue;
6809
6810 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE
6811 list_del(&item->list);
6812 kfree(item);
4fa7734c 6813 vmx->nested.vmcs02_num--;
ff2f6fe9 6814 }
ff2f6fe9
NHE
6815}
6816
0658fbaa
ACL
6817/*
6818 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6819 * set the success or error code of an emulated VMX instruction, as specified
6820 * by Vol 2B, VMX Instruction Reference, "Conventions".
6821 */
6822static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6823{
6824 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6825 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6826 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6827}
6828
6829static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6830{
6831 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6832 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6833 X86_EFLAGS_SF | X86_EFLAGS_OF))
6834 | X86_EFLAGS_CF);
6835}
6836
145c28dd 6837static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL
6838 u32 vm_instruction_error)
6839{
6840 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6841 /*
6842 * failValid writes the error number to the current VMCS, which
6843 * can't be done there isn't a current VMCS.
6844 */
6845 nested_vmx_failInvalid(vcpu);
6846 return;
6847 }
6848 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6849 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6850 X86_EFLAGS_SF | X86_EFLAGS_OF))
6851 | X86_EFLAGS_ZF);
6852 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6853 /*
6854 * We don't need to force a shadow sync because
6855 * VM_INSTRUCTION_ERROR is not shadowed
6856 */
6857}
145c28dd 6858
ff651cb6
WV
6859static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6860{
6861 /* TODO: not to reset guest simply here. */
6862 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
bbe41b95 6863 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
ff651cb6
WV
6864}
6865
f4124500
JK
6866static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6867{
6868 struct vcpu_vmx *vmx =
6869 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6870
6871 vmx->nested.preemption_timer_expired = true;
6872 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6873 kvm_vcpu_kick(&vmx->vcpu);
6874
6875 return HRTIMER_NORESTART;
6876}
6877
19677e32
BD
6878/*
6879 * Decode the memory-address operand of a vmx instruction, as recorded on an
6880 * exit caused by such an instruction (run by a guest hypervisor).
6881 * On success, returns 0. When the operand is invalid, returns 1 and throws
6882 * #UD or #GP.
6883 */
6884static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6885 unsigned long exit_qualification,
f9eb4af6 6886 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6887{
f9eb4af6
EK
6888 gva_t off;
6889 bool exn;
6890 struct kvm_segment s;
6891
19677e32
BD
6892 /*
6893 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6894 * Execution", on an exit, vmx_instruction_info holds most of the
6895 * addressing components of the operand. Only the displacement part
6896 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6897 * For how an actual address is calculated from all these components,
6898 * refer to Vol. 1, "Operand Addressing".
6899 */
6900 int scaling = vmx_instruction_info & 3;
6901 int addr_size = (vmx_instruction_info >> 7) & 7;
6902 bool is_reg = vmx_instruction_info & (1u << 10);
6903 int seg_reg = (vmx_instruction_info >> 15) & 7;
6904 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6905 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6906 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6907 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6908
6909 if (is_reg) {
6910 kvm_queue_exception(vcpu, UD_VECTOR);
6911 return 1;
6912 }
6913
6914 /* Addr = segment_base + offset */
6915 /* offset = base + [index * scale] + displacement */
f9eb4af6 6916 off = exit_qualification; /* holds the displacement */
19677e32 6917 if (base_is_valid)
f9eb4af6 6918 off += kvm_register_read(vcpu, base_reg);
19677e32 6919 if (index_is_valid)
f9eb4af6
EK
6920 off += kvm_register_read(vcpu, index_reg)<<scaling;
6921 vmx_get_segment(vcpu, &s, seg_reg);
6922 *ret = s.base + off;
19677e32
BD
6923
6924 if (addr_size == 1) /* 32 bit */
6925 *ret &= 0xffffffff;
6926
f9eb4af6
EK
6927 /* Checks for #GP/#SS exceptions. */
6928 exn = false;
ff30ef40
QC
6929 if (is_long_mode(vcpu)) {
6930 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6931 * non-canonical form. This is the only check on the memory
6932 * destination for long mode!
6933 */
6934 exn = is_noncanonical_address(*ret);
6935 } else if (is_protmode(vcpu)) {
f9eb4af6
EK
6936 /* Protected mode: apply checks for segment validity in the
6937 * following order:
6938 * - segment type check (#GP(0) may be thrown)
6939 * - usability check (#GP(0)/#SS(0))
6940 * - limit check (#GP(0)/#SS(0))
6941 */
6942 if (wr)
6943 /* #GP(0) if the destination operand is located in a
6944 * read-only data segment or any code segment.
6945 */
6946 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6947 else
6948 /* #GP(0) if the source operand is located in an
6949 * execute-only code segment
6950 */
6951 exn = ((s.type & 0xa) == 8);
ff30ef40
QC
6952 if (exn) {
6953 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6954 return 1;
6955 }
f9eb4af6
EK
6956 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6957 */
6958 exn = (s.unusable != 0);
6959 /* Protected mode: #GP(0)/#SS(0) if the memory
6960 * operand is outside the segment limit.
6961 */
6962 exn = exn || (off + sizeof(u64) > s.limit);
6963 }
6964 if (exn) {
6965 kvm_queue_exception_e(vcpu,
6966 seg_reg == VCPU_SREG_SS ?
6967 SS_VECTOR : GP_VECTOR,
6968 0);
6969 return 1;
6970 }
6971
19677e32
BD
6972 return 0;
6973}
6974
cbf71279 6975static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
3573e22c
BD
6976{
6977 gva_t gva;
3573e22c 6978 struct x86_exception e;
3573e22c
BD
6979
6980 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 6981 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD
6982 return 1;
6983
cbf71279
RK
6984 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
6985 sizeof(*vmpointer), &e)) {
3573e22c
BD
6986 kvm_inject_page_fault(vcpu, &e);
6987 return 1;
6988 }
6989
3573e22c
BD
6990 return 0;
6991}
6992
e29acc55
JM
6993static int enter_vmx_operation(struct kvm_vcpu *vcpu)
6994{
6995 struct vcpu_vmx *vmx = to_vmx(vcpu);
6996 struct vmcs *shadow_vmcs;
6997
6998 if (cpu_has_vmx_msr_bitmap()) {
6999 vmx->nested.msr_bitmap =
7000 (unsigned long *)__get_free_page(GFP_KERNEL);
7001 if (!vmx->nested.msr_bitmap)
7002 goto out_msr_bitmap;
7003 }
7004
7005 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7006 if (!vmx->nested.cached_vmcs12)
7007 goto out_cached_vmcs12;
7008
7009 if (enable_shadow_vmcs) {
7010 shadow_vmcs = alloc_vmcs();
7011 if (!shadow_vmcs)
7012 goto out_shadow_vmcs;
7013 /* mark vmcs as shadow */
7014 shadow_vmcs->revision_id |= (1u << 31);
7015 /* init shadow vmcs */
7016 vmcs_clear(shadow_vmcs);
7017 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7018 }
7019
7020 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7021 vmx->nested.vmcs02_num = 0;
7022
7023 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7024 HRTIMER_MODE_REL_PINNED);
7025 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7026
7027 vmx->nested.vmxon = true;
7028 return 0;
7029
7030out_shadow_vmcs:
7031 kfree(vmx->nested.cached_vmcs12);
7032
7033out_cached_vmcs12:
7034 free_page((unsigned long)vmx->nested.msr_bitmap);
7035
7036out_msr_bitmap:
7037 return -ENOMEM;
7038}
7039
ec378aee
NHE
7040/*
7041 * Emulate the VMXON instruction.
7042 * Currently, we just remember that VMX is active, and do not save or even
7043 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7044 * do not currently need to store anything in that guest-allocated memory
7045 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7046 * argument is different from the VMXON pointer (which the spec says they do).
7047 */
7048static int handle_vmon(struct kvm_vcpu *vcpu)
7049{
e29acc55 7050 int ret;
cbf71279
RK
7051 gpa_t vmptr;
7052 struct page *page;
ec378aee 7053 struct vcpu_vmx *vmx = to_vmx(vcpu);
b3897a49
NHE
7054 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7055 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee 7056
70f3aac9
JM
7057 /*
7058 * The Intel VMX Instruction Reference lists a bunch of bits that are
7059 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7060 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7061 * Otherwise, we should fail with #UD. But most faulting conditions
7062 * have already been checked by hardware, prior to the VM-exit for
7063 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7064 * that bit set to 1 in non-root mode.
ec378aee 7065 */
70f3aac9 7066 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
ec378aee
NHE
7067 kvm_queue_exception(vcpu, UD_VECTOR);
7068 return 1;
7069 }
7070
145c28dd
AG
7071 if (vmx->nested.vmxon) {
7072 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6affcbed 7073 return kvm_skip_emulated_instruction(vcpu);
145c28dd 7074 }
b3897a49 7075
3b84080b 7076 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
b3897a49
NHE
7077 != VMXON_NEEDED_FEATURES) {
7078 kvm_inject_gp(vcpu, 0);
7079 return 1;
7080 }
7081
cbf71279 7082 if (nested_vmx_get_vmptr(vcpu, &vmptr))
21e7fbe7 7083 return 1;
cbf71279
RK
7084
7085 /*
7086 * SDM 3: 24.11.5
7087 * The first 4 bytes of VMXON region contain the supported
7088 * VMCS revision identifier
7089 *
7090 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7091 * which replaces physical address width with 32
7092 */
7093 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7094 nested_vmx_failInvalid(vcpu);
7095 return kvm_skip_emulated_instruction(vcpu);
7096 }
7097
7098 page = nested_get_page(vcpu, vmptr);
7099 if (page == NULL) {
7100 nested_vmx_failInvalid(vcpu);
7101 return kvm_skip_emulated_instruction(vcpu);
7102 }
7103 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7104 kunmap(page);
7105 nested_release_page_clean(page);
7106 nested_vmx_failInvalid(vcpu);
7107 return kvm_skip_emulated_instruction(vcpu);
7108 }
7109 kunmap(page);
7110 nested_release_page_clean(page);
7111
7112 vmx->nested.vmxon_ptr = vmptr;
e29acc55
JM
7113 ret = enter_vmx_operation(vcpu);
7114 if (ret)
7115 return ret;
ec378aee 7116
a25eb114 7117 nested_vmx_succeed(vcpu);
6affcbed 7118 return kvm_skip_emulated_instruction(vcpu);
ec378aee
NHE
7119}
7120
7121/*
7122 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7123 * for running VMX instructions (except VMXON, whose prerequisites are
7124 * slightly different). It also specifies what exception to inject otherwise.
70f3aac9
JM
7125 * Note that many of these exceptions have priority over VM exits, so they
7126 * don't have to be checked again here.
ec378aee
NHE
7127 */
7128static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7129{
70f3aac9 7130 if (!to_vmx(vcpu)->nested.vmxon) {
ec378aee
NHE
7131 kvm_queue_exception(vcpu, UD_VECTOR);
7132 return 0;
7133 }
ec378aee
NHE
7134 return 1;
7135}
7136
e7953d7f
AG
7137static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7138{
9a2a05b9
PB
7139 if (vmx->nested.current_vmptr == -1ull)
7140 return;
7141
7142 /* current_vmptr and current_vmcs12 are always set/reset together */
7143 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7144 return;
7145
012f83cb 7146 if (enable_shadow_vmcs) {
9a2a05b9
PB
7147 /* copy to memory all shadowed fields in case
7148 they were modified */
7149 copy_shadow_to_vmcs12(vmx);
7150 vmx->nested.sync_shadow_vmcs = false;
7ec36296
XG
7151 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7152 SECONDARY_EXEC_SHADOW_VMCS);
9a2a05b9 7153 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 7154 }
705699a1 7155 vmx->nested.posted_intr_nv = -1;
4f2777bc
DM
7156
7157 /* Flush VMCS12 to guest memory */
7158 memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7159 VMCS12_SIZE);
7160
e7953d7f
AG
7161 kunmap(vmx->nested.current_vmcs12_page);
7162 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB
7163 vmx->nested.current_vmptr = -1ull;
7164 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG
7165}
7166
ec378aee
NHE
7167/*
7168 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7169 * just stops using VMX.
7170 */
7171static void free_nested(struct vcpu_vmx *vmx)
7172{
7173 if (!vmx->nested.vmxon)
7174 return;
9a2a05b9 7175
ec378aee 7176 vmx->nested.vmxon = false;
5c614b35 7177 free_vpid(vmx->nested.vpid02);
9a2a05b9 7178 nested_release_vmcs12(vmx);
d048c098
RK
7179 if (vmx->nested.msr_bitmap) {
7180 free_page((unsigned long)vmx->nested.msr_bitmap);
7181 vmx->nested.msr_bitmap = NULL;
7182 }
355f4fb1
JM
7183 if (enable_shadow_vmcs) {
7184 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7185 free_vmcs(vmx->vmcs01.shadow_vmcs);
7186 vmx->vmcs01.shadow_vmcs = NULL;
7187 }
4f2777bc 7188 kfree(vmx->nested.cached_vmcs12);
fe3ef05c
NHE
7189 /* Unpin physical memory we referred to in current vmcs02 */
7190 if (vmx->nested.apic_access_page) {
7191 nested_release_page(vmx->nested.apic_access_page);
48d89b92 7192 vmx->nested.apic_access_page = NULL;
fe3ef05c 7193 }
a7c0b07d
WL
7194 if (vmx->nested.virtual_apic_page) {
7195 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 7196 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 7197 }
705699a1
WV
7198 if (vmx->nested.pi_desc_page) {
7199 kunmap(vmx->nested.pi_desc_page);
7200 nested_release_page(vmx->nested.pi_desc_page);
7201 vmx->nested.pi_desc_page = NULL;
7202 vmx->nested.pi_desc = NULL;
7203 }
ff2f6fe9
NHE
7204
7205 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE
7206}
7207
7208/* Emulate the VMXOFF instruction */
7209static int handle_vmoff(struct kvm_vcpu *vcpu)
7210{
7211 if (!nested_vmx_check_permission(vcpu))
7212 return 1;
7213 free_nested(to_vmx(vcpu));
a25eb114 7214 nested_vmx_succeed(vcpu);
6affcbed 7215 return kvm_skip_emulated_instruction(vcpu);
ec378aee
NHE
7216}
7217
27d6c865
NHE
7218/* Emulate the VMCLEAR instruction */
7219static int handle_vmclear(struct kvm_vcpu *vcpu)
7220{
7221 struct vcpu_vmx *vmx = to_vmx(vcpu);
587d7e72 7222 u32 zero = 0;
27d6c865 7223 gpa_t vmptr;
27d6c865
NHE
7224
7225 if (!nested_vmx_check_permission(vcpu))
7226 return 1;
7227
cbf71279 7228 if (nested_vmx_get_vmptr(vcpu, &vmptr))
27d6c865 7229 return 1;
27d6c865 7230
cbf71279
RK
7231 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7232 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7233 return kvm_skip_emulated_instruction(vcpu);
7234 }
7235
7236 if (vmptr == vmx->nested.vmxon_ptr) {
7237 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7238 return kvm_skip_emulated_instruction(vcpu);
7239 }
7240
9a2a05b9 7241 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 7242 nested_release_vmcs12(vmx);
27d6c865 7243
587d7e72
JM
7244 kvm_vcpu_write_guest(vcpu,
7245 vmptr + offsetof(struct vmcs12, launch_state),
7246 &zero, sizeof(zero));
27d6c865
NHE
7247
7248 nested_free_vmcs02(vmx, vmptr);
7249
27d6c865 7250 nested_vmx_succeed(vcpu);
6affcbed 7251 return kvm_skip_emulated_instruction(vcpu);
27d6c865
NHE
7252}
7253
cd232ad0
NHE
7254static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7255
7256/* Emulate the VMLAUNCH instruction */
7257static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7258{
7259 return nested_vmx_run(vcpu, true);
7260}
7261
7262/* Emulate the VMRESUME instruction */
7263static int handle_vmresume(struct kvm_vcpu *vcpu)
7264{
7265
7266 return nested_vmx_run(vcpu, false);
7267}
7268
49f705c5
NHE
7269/*
7270 * Read a vmcs12 field. Since these can have varying lengths and we return
7271 * one type, we chose the biggest type (u64) and zero-extend the return value
7272 * to that size. Note that the caller, handle_vmread, might need to use only
7273 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7274 * 64-bit fields are to be returned).
7275 */
a2ae9df7
PB
7276static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7277 unsigned long field, u64 *ret)
49f705c5
NHE
7278{
7279 short offset = vmcs_field_to_offset(field);
7280 char *p;
7281
7282 if (offset < 0)
a2ae9df7 7283 return offset;
49f705c5
NHE
7284
7285 p = ((char *)(get_vmcs12(vcpu))) + offset;
7286
7287 switch (vmcs_field_type(field)) {
7288 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7289 *ret = *((natural_width *)p);
a2ae9df7 7290 return 0;
49f705c5
NHE
7291 case VMCS_FIELD_TYPE_U16:
7292 *ret = *((u16 *)p);
a2ae9df7 7293 return 0;
49f705c5
NHE
7294 case VMCS_FIELD_TYPE_U32:
7295 *ret = *((u32 *)p);
a2ae9df7 7296 return 0;
49f705c5
NHE
7297 case VMCS_FIELD_TYPE_U64:
7298 *ret = *((u64 *)p);
a2ae9df7 7299 return 0;
49f705c5 7300 default:
a2ae9df7
PB
7301 WARN_ON(1);
7302 return -ENOENT;
49f705c5
NHE
7303 }
7304}
7305
20b97fea 7306
a2ae9df7
PB
7307static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7308 unsigned long field, u64 field_value){
20b97fea
AG
7309 short offset = vmcs_field_to_offset(field);
7310 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7311 if (offset < 0)
a2ae9df7 7312 return offset;
20b97fea
AG
7313
7314 switch (vmcs_field_type(field)) {
7315 case VMCS_FIELD_TYPE_U16:
7316 *(u16 *)p = field_value;
a2ae9df7 7317 return 0;
20b97fea
AG
7318 case VMCS_FIELD_TYPE_U32:
7319 *(u32 *)p = field_value;
a2ae9df7 7320 return 0;
20b97fea
AG
7321 case VMCS_FIELD_TYPE_U64:
7322 *(u64 *)p = field_value;
a2ae9df7 7323 return 0;
20b97fea
AG
7324 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7325 *(natural_width *)p = field_value;
a2ae9df7 7326 return 0;
20b97fea 7327 default:
a2ae9df7
PB
7328 WARN_ON(1);
7329 return -ENOENT;
20b97fea
AG
7330 }
7331
7332}
7333
16f5b903
AG
7334static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7335{
7336 int i;
7337 unsigned long field;
7338 u64 field_value;
355f4fb1 7339 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
c2bae893
MK
7340 const unsigned long *fields = shadow_read_write_fields;
7341 const int num_fields = max_shadow_read_write_fields;
16f5b903 7342
282da870
JK
7343 preempt_disable();
7344
16f5b903
AG
7345 vmcs_load(shadow_vmcs);
7346
7347 for (i = 0; i < num_fields; i++) {
7348 field = fields[i];
7349 switch (vmcs_field_type(field)) {
7350 case VMCS_FIELD_TYPE_U16:
7351 field_value = vmcs_read16(field);
7352 break;
7353 case VMCS_FIELD_TYPE_U32:
7354 field_value = vmcs_read32(field);
7355 break;
7356 case VMCS_FIELD_TYPE_U64:
7357 field_value = vmcs_read64(field);
7358 break;
7359 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7360 field_value = vmcs_readl(field);
7361 break;
a2ae9df7
PB
7362 default:
7363 WARN_ON(1);
7364 continue;
16f5b903
AG
7365 }
7366 vmcs12_write_any(&vmx->vcpu, field, field_value);
7367 }
7368
7369 vmcs_clear(shadow_vmcs);
7370 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK
7371
7372 preempt_enable();
16f5b903
AG
7373}
7374
c3114420
AG
7375static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7376{
c2bae893
MK
7377 const unsigned long *fields[] = {
7378 shadow_read_write_fields,
7379 shadow_read_only_fields
c3114420 7380 };
c2bae893 7381 const int max_fields[] = {
c3114420
AG
7382 max_shadow_read_write_fields,
7383 max_shadow_read_only_fields
7384 };
7385 int i, q;
7386 unsigned long field;
7387 u64 field_value = 0;
355f4fb1 7388 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
c3114420
AG
7389
7390 vmcs_load(shadow_vmcs);
7391
c2bae893 7392 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG
7393 for (i = 0; i < max_fields[q]; i++) {
7394 field = fields[q][i];
7395 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7396
7397 switch (vmcs_field_type(field)) {
7398 case VMCS_FIELD_TYPE_U16:
7399 vmcs_write16(field, (u16)field_value);
7400 break;
7401 case VMCS_FIELD_TYPE_U32:
7402 vmcs_write32(field, (u32)field_value);
7403 break;
7404 case VMCS_FIELD_TYPE_U64:
7405 vmcs_write64(field, (u64)field_value);
7406 break;
7407 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7408 vmcs_writel(field, (long)field_value);
7409 break;
a2ae9df7
PB
7410 default:
7411 WARN_ON(1);
7412 break;
c3114420
AG
7413 }
7414 }
7415 }
7416
7417 vmcs_clear(shadow_vmcs);
7418 vmcs_load(vmx->loaded_vmcs->vmcs);
7419}
7420
49f705c5
NHE
7421/*
7422 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7423 * used before) all generate the same failure when it is missing.
7424 */
7425static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7426{
7427 struct vcpu_vmx *vmx = to_vmx(vcpu);
7428 if (vmx->nested.current_vmptr == -1ull) {
7429 nested_vmx_failInvalid(vcpu);
49f705c5
NHE
7430 return 0;
7431 }
7432 return 1;
7433}
7434
7435static int handle_vmread(struct kvm_vcpu *vcpu)
7436{
7437 unsigned long field;
7438 u64 field_value;
7439 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7440 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7441 gva_t gva = 0;
7442
eb277562 7443 if (!nested_vmx_check_permission(vcpu))
49f705c5
NHE
7444 return 1;
7445
6affcbed
KH
7446 if (!nested_vmx_check_vmcs12(vcpu))
7447 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7448
7449 /* Decode instruction info and find the field to read */
27e6fb5d 7450 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 7451 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 7452 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5 7453 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6affcbed 7454 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7455 }
7456 /*
7457 * Now copy part of this value to register or memory, as requested.
7458 * Note that the number of bits actually copied is 32 or 64 depending
7459 * on the guest's mode (32 or 64 bit), not on the given field's length.
7460 */
7461 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 7462 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE
7463 field_value);
7464 } else {
7465 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7466 vmx_instruction_info, true, &gva))
49f705c5 7467 return 1;
70f3aac9 7468 /* _system ok, as hardware has verified cpl=0 */
49f705c5
NHE
7469 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7470 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7471 }
7472
7473 nested_vmx_succeed(vcpu);
6affcbed 7474 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7475}
7476
7477
7478static int handle_vmwrite(struct kvm_vcpu *vcpu)
7479{
7480 unsigned long field;
7481 gva_t gva;
7482 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7483 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE
7484 /* The value to write might be 32 or 64 bits, depending on L1's long
7485 * mode, and eventually we need to write that into a field of several
7486 * possible lengths. The code below first zero-extends the value to 64
6a6256f9 7487 * bit (field_value), and then copies only the appropriate number of
49f705c5
NHE
7488 * bits into the vmcs12 field.
7489 */
7490 u64 field_value = 0;
7491 struct x86_exception e;
7492
eb277562 7493 if (!nested_vmx_check_permission(vcpu))
49f705c5
NHE
7494 return 1;
7495
6affcbed
KH
7496 if (!nested_vmx_check_vmcs12(vcpu))
7497 return kvm_skip_emulated_instruction(vcpu);
eb277562 7498
49f705c5 7499 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7500 field_value = kvm_register_readl(vcpu,
49f705c5
NHE
7501 (((vmx_instruction_info) >> 3) & 0xf));
7502 else {
7503 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7504 vmx_instruction_info, false, &gva))
49f705c5
NHE
7505 return 1;
7506 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7507 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE
7508 kvm_inject_page_fault(vcpu, &e);
7509 return 1;
7510 }
7511 }
7512
7513
27e6fb5d 7514 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE
7515 if (vmcs_field_readonly(field)) {
7516 nested_vmx_failValid(vcpu,
7517 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6affcbed 7518 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7519 }
7520
a2ae9df7 7521 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5 7522 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6affcbed 7523 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7524 }
7525
7526 nested_vmx_succeed(vcpu);
6affcbed 7527 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7528}
7529
a8bc284e
JM
7530static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7531{
7532 vmx->nested.current_vmptr = vmptr;
7533 if (enable_shadow_vmcs) {
7534 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7535 SECONDARY_EXEC_SHADOW_VMCS);
7536 vmcs_write64(VMCS_LINK_POINTER,
7537 __pa(vmx->vmcs01.shadow_vmcs));
7538 vmx->nested.sync_shadow_vmcs = true;
7539 }
7540}
7541
63846663
NHE
7542/* Emulate the VMPTRLD instruction */
7543static int handle_vmptrld(struct kvm_vcpu *vcpu)
7544{
7545 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7546 gpa_t vmptr;
63846663
NHE
7547
7548 if (!nested_vmx_check_permission(vcpu))
7549 return 1;
7550
cbf71279 7551 if (nested_vmx_get_vmptr(vcpu, &vmptr))
63846663 7552 return 1;
63846663 7553
cbf71279
RK
7554 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7555 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7556 return kvm_skip_emulated_instruction(vcpu);
7557 }
7558
7559 if (vmptr == vmx->nested.vmxon_ptr) {
7560 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7561 return kvm_skip_emulated_instruction(vcpu);
7562 }
7563
63846663
NHE
7564 if (vmx->nested.current_vmptr != vmptr) {
7565 struct vmcs12 *new_vmcs12;
7566 struct page *page;
7567 page = nested_get_page(vcpu, vmptr);
7568 if (page == NULL) {
7569 nested_vmx_failInvalid(vcpu);
6affcbed 7570 return kvm_skip_emulated_instruction(vcpu);
63846663
NHE
7571 }
7572 new_vmcs12 = kmap(page);
7573 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7574 kunmap(page);
7575 nested_release_page_clean(page);
7576 nested_vmx_failValid(vcpu,
7577 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6affcbed 7578 return kvm_skip_emulated_instruction(vcpu);
63846663 7579 }
63846663 7580
9a2a05b9 7581 nested_release_vmcs12(vmx);
63846663
NHE
7582 vmx->nested.current_vmcs12 = new_vmcs12;
7583 vmx->nested.current_vmcs12_page = page;
4f2777bc
DM
7584 /*
7585 * Load VMCS12 from guest memory since it is not already
7586 * cached.
7587 */
7588 memcpy(vmx->nested.cached_vmcs12,
7589 vmx->nested.current_vmcs12, VMCS12_SIZE);
a8bc284e 7590 set_current_vmptr(vmx, vmptr);
63846663
NHE
7591 }
7592
7593 nested_vmx_succeed(vcpu);
6affcbed 7594 return kvm_skip_emulated_instruction(vcpu);
63846663
NHE
7595}
7596
6a4d7550
NHE
7597/* Emulate the VMPTRST instruction */
7598static int handle_vmptrst(struct kvm_vcpu *vcpu)
7599{
7600 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7601 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7602 gva_t vmcs_gva;
7603 struct x86_exception e;
7604
7605 if (!nested_vmx_check_permission(vcpu))
7606 return 1;
7607
7608 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7609 vmx_instruction_info, true, &vmcs_gva))
6a4d7550 7610 return 1;
70f3aac9 7611 /* ok to use *_system, as hardware has verified cpl=0 */
6a4d7550
NHE
7612 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7613 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7614 sizeof(u64), &e)) {
7615 kvm_inject_page_fault(vcpu, &e);
7616 return 1;
7617 }
7618 nested_vmx_succeed(vcpu);
6affcbed 7619 return kvm_skip_emulated_instruction(vcpu);
6a4d7550
NHE
7620}
7621
bfd0a56b
NHE
7622/* Emulate the INVEPT instruction */
7623static int handle_invept(struct kvm_vcpu *vcpu)
7624{
b9c237bb 7625 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE
7626 u32 vmx_instruction_info, types;
7627 unsigned long type;
7628 gva_t gva;
7629 struct x86_exception e;
7630 struct {
7631 u64 eptp, gpa;
7632 } operand;
bfd0a56b 7633
b9c237bb
WV
7634 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7635 SECONDARY_EXEC_ENABLE_EPT) ||
7636 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE
7637 kvm_queue_exception(vcpu, UD_VECTOR);
7638 return 1;
7639 }
7640
7641 if (!nested_vmx_check_permission(vcpu))
7642 return 1;
7643
bfd0a56b 7644 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7645 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7646
b9c237bb 7647 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b 7648
85c856b3 7649 if (type >= 32 || !(types & (1 << type))) {
bfd0a56b
NHE
7650 nested_vmx_failValid(vcpu,
7651 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7652 return kvm_skip_emulated_instruction(vcpu);
bfd0a56b
NHE
7653 }
7654
7655 /* According to the Intel VMX instruction reference, the memory
7656 * operand is read even if it isn't needed (e.g., for type==global)
7657 */
7658 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7659 vmx_instruction_info, false, &gva))
bfd0a56b
NHE
7660 return 1;
7661 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7662 sizeof(operand), &e)) {
7663 kvm_inject_page_fault(vcpu, &e);
7664 return 1;
7665 }
7666
7667 switch (type) {
bfd0a56b 7668 case VMX_EPT_EXTENT_GLOBAL:
45e11817
BD
7669 /*
7670 * TODO: track mappings and invalidate
7671 * single context requests appropriately
7672 */
7673 case VMX_EPT_EXTENT_CONTEXT:
bfd0a56b 7674 kvm_mmu_sync_roots(vcpu);
77c3913b 7675 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE
7676 nested_vmx_succeed(vcpu);
7677 break;
7678 default:
7679 BUG_ON(1);
7680 break;
7681 }
7682
6affcbed 7683 return kvm_skip_emulated_instruction(vcpu);
bfd0a56b
NHE
7684}
7685
a642fc30
PM
7686static int handle_invvpid(struct kvm_vcpu *vcpu)
7687{
99b83ac8
WL
7688 struct vcpu_vmx *vmx = to_vmx(vcpu);
7689 u32 vmx_instruction_info;
7690 unsigned long type, types;
7691 gva_t gva;
7692 struct x86_exception e;
40352605
JM
7693 struct {
7694 u64 vpid;
7695 u64 gla;
7696 } operand;
99b83ac8
WL
7697
7698 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7699 SECONDARY_EXEC_ENABLE_VPID) ||
7700 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7701 kvm_queue_exception(vcpu, UD_VECTOR);
7702 return 1;
7703 }
7704
7705 if (!nested_vmx_check_permission(vcpu))
7706 return 1;
7707
7708 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7709 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7710
bcdde302
JD
7711 types = (vmx->nested.nested_vmx_vpid_caps &
7712 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
99b83ac8 7713
85c856b3 7714 if (type >= 32 || !(types & (1 << type))) {
99b83ac8
WL
7715 nested_vmx_failValid(vcpu,
7716 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7717 return kvm_skip_emulated_instruction(vcpu);
99b83ac8
WL
7718 }
7719
7720 /* according to the intel vmx instruction reference, the memory
7721 * operand is read even if it isn't needed (e.g., for type==global)
7722 */
7723 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7724 vmx_instruction_info, false, &gva))
7725 return 1;
40352605
JM
7726 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7727 sizeof(operand), &e)) {
99b83ac8
WL
7728 kvm_inject_page_fault(vcpu, &e);
7729 return 1;
7730 }
40352605
JM
7731 if (operand.vpid >> 16) {
7732 nested_vmx_failValid(vcpu,
7733 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7734 return kvm_skip_emulated_instruction(vcpu);
7735 }
99b83ac8
WL
7736
7737 switch (type) {
bcdde302 7738 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
40352605
JM
7739 if (is_noncanonical_address(operand.gla)) {
7740 nested_vmx_failValid(vcpu,
7741 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7742 return kvm_skip_emulated_instruction(vcpu);
7743 }
7744 /* fall through */
ef697a71 7745 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
bcdde302 7746 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
40352605 7747 if (!operand.vpid) {
bcdde302
JD
7748 nested_vmx_failValid(vcpu,
7749 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7750 return kvm_skip_emulated_instruction(vcpu);
bcdde302
JD
7751 }
7752 break;
99b83ac8 7753 case VMX_VPID_EXTENT_ALL_CONTEXT:
99b83ac8
WL
7754 break;
7755 default:
bcdde302 7756 WARN_ON_ONCE(1);
6affcbed 7757 return kvm_skip_emulated_instruction(vcpu);
99b83ac8
WL
7758 }
7759
bcdde302
JD
7760 __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7761 nested_vmx_succeed(vcpu);
7762
6affcbed 7763 return kvm_skip_emulated_instruction(vcpu);
a642fc30
PM
7764}
7765
843e4330
KH
7766static int handle_pml_full(struct kvm_vcpu *vcpu)
7767{
7768 unsigned long exit_qualification;
7769
7770 trace_kvm_pml_full(vcpu->vcpu_id);
7771
7772 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7773
7774 /*
7775 * PML buffer FULL happened while executing iret from NMI,
7776 * "blocked by NMI" bit has to be set before next VM entry.
7777 */
7778 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
843e4330
KH
7779 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7780 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7781 GUEST_INTR_STATE_NMI);
7782
7783 /*
7784 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7785 * here.., and there's no userspace involvement needed for PML.
7786 */
7787 return 1;
7788}
7789
64672c95
YJ
7790static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7791{
7792 kvm_lapic_expired_hv_timer(vcpu);
7793 return 1;
7794}
7795
6aa8b732
AK
7796/*
7797 * The exit handlers return 1 if the exit was handled fully and guest execution
7798 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7799 * to be done to userspace and return 0.
7800 */
772e0318 7801static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK
7802 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7803 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7804 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7805 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7806 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK
7807 [EXIT_REASON_CR_ACCESS] = handle_cr,
7808 [EXIT_REASON_DR_ACCESS] = handle_dr,
7809 [EXIT_REASON_CPUID] = handle_cpuid,
7810 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7811 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7812 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7813 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7814 [EXIT_REASON_INVD] = handle_invd,
a7052897 7815 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7816 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7817 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7818 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7819 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7820 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7821 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7822 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7823 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7824 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE
7825 [EXIT_REASON_VMOFF] = handle_vmoff,
7826 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY
7827 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7828 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7829 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7830 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7831 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7832 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7833 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7834 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT
7835 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7836 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7837 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7838 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7839 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7840 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7841 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7842 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL
7843 [EXIT_REASON_XSAVES] = handle_xsaves,
7844 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7845 [EXIT_REASON_PML_FULL] = handle_pml_full,
64672c95 7846 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
6aa8b732
AK
7847};
7848
7849static const int kvm_vmx_max_exit_handlers =
50a3485c 7850 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7851
908a7bdd
JK
7852static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7853 struct vmcs12 *vmcs12)
7854{
7855 unsigned long exit_qualification;
7856 gpa_t bitmap, last_bitmap;
7857 unsigned int port;
7858 int size;
7859 u8 b;
7860
908a7bdd 7861 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7862 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK
7863
7864 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7865
7866 port = exit_qualification >> 16;
7867 size = (exit_qualification & 7) + 1;
7868
7869 last_bitmap = (gpa_t)-1;
7870 b = -1;
7871
7872 while (size > 0) {
7873 if (port < 0x8000)
7874 bitmap = vmcs12->io_bitmap_a;
7875 else if (port < 0x10000)
7876 bitmap = vmcs12->io_bitmap_b;
7877 else
1d804d07 7878 return true;
908a7bdd
JK
7879 bitmap += (port & 0x7fff) / 8;
7880
7881 if (last_bitmap != bitmap)
54bf36aa 7882 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7883 return true;
908a7bdd 7884 if (b & (1 << (port & 7)))
1d804d07 7885 return true;
908a7bdd
JK
7886
7887 port++;
7888 size--;
7889 last_bitmap = bitmap;
7890 }
7891
1d804d07 7892 return false;
908a7bdd
JK
7893}
7894
644d711a
NHE
7895/*
7896 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7897 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7898 * disinterest in the current event (read or write a specific MSR) by using an
7899 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7900 */
7901static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7902 struct vmcs12 *vmcs12, u32 exit_reason)
7903{
7904 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7905 gpa_t bitmap;
7906
cbd29cb6 7907 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7908 return true;
644d711a
NHE
7909
7910 /*
7911 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7912 * for the four combinations of read/write and low/high MSR numbers.
7913 * First we need to figure out which of the four to use:
7914 */
7915 bitmap = vmcs12->msr_bitmap;
7916 if (exit_reason == EXIT_REASON_MSR_WRITE)
7917 bitmap += 2048;
7918 if (msr_index >= 0xc0000000) {
7919 msr_index -= 0xc0000000;
7920 bitmap += 1024;
7921 }
7922
7923 /* Then read the msr_index'th bit from this bitmap: */
7924 if (msr_index < 1024*8) {
7925 unsigned char b;
54bf36aa 7926 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7927 return true;
644d711a
NHE
7928 return 1 & (b >> (msr_index & 7));
7929 } else
1d804d07 7930 return true; /* let L1 handle the wrong parameter */
644d711a
NHE
7931}
7932
7933/*
7934 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7935 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7936 * intercept (via guest_host_mask etc.) the current event.
7937 */
7938static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7939 struct vmcs12 *vmcs12)
7940{
7941 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7942 int cr = exit_qualification & 15;
e1d39b17
JS
7943 int reg;
7944 unsigned long val;
644d711a
NHE
7945
7946 switch ((exit_qualification >> 4) & 3) {
7947 case 0: /* mov to cr */
e1d39b17
JS
7948 reg = (exit_qualification >> 8) & 15;
7949 val = kvm_register_readl(vcpu, reg);
644d711a
NHE
7950 switch (cr) {
7951 case 0:
7952 if (vmcs12->cr0_guest_host_mask &
7953 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7954 return true;
644d711a
NHE
7955 break;
7956 case 3:
7957 if ((vmcs12->cr3_target_count >= 1 &&
7958 vmcs12->cr3_target_value0 == val) ||
7959 (vmcs12->cr3_target_count >= 2 &&
7960 vmcs12->cr3_target_value1 == val) ||
7961 (vmcs12->cr3_target_count >= 3 &&
7962 vmcs12->cr3_target_value2 == val) ||
7963 (vmcs12->cr3_target_count >= 4 &&
7964 vmcs12->cr3_target_value3 == val))
1d804d07 7965 return false;
644d711a 7966 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7967 return true;
644d711a
NHE
7968 break;
7969 case 4:
7970 if (vmcs12->cr4_guest_host_mask &
7971 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7972 return true;
644d711a
NHE
7973 break;
7974 case 8:
7975 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7976 return true;
644d711a
NHE
7977 break;
7978 }
7979 break;
7980 case 2: /* clts */
7981 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7982 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7983 return true;
644d711a
NHE
7984 break;
7985 case 1: /* mov from cr */
7986 switch (cr) {
7987 case 3:
7988 if (vmcs12->cpu_based_vm_exec_control &
7989 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7990 return true;
644d711a
NHE
7991 break;
7992 case 8:
7993 if (vmcs12->cpu_based_vm_exec_control &
7994 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7995 return true;
644d711a
NHE
7996 break;
7997 }
7998 break;
7999 case 3: /* lmsw */
8000 /*
8001 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8002 * cr0. Other attempted changes are ignored, with no exit.
8003 */
e1d39b17 8004 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
644d711a
NHE
8005 if (vmcs12->cr0_guest_host_mask & 0xe &
8006 (val ^ vmcs12->cr0_read_shadow))
1d804d07 8007 return true;
644d711a
NHE
8008 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8009 !(vmcs12->cr0_read_shadow & 0x1) &&
8010 (val & 0x1))
1d804d07 8011 return true;
644d711a
NHE
8012 break;
8013 }
1d804d07 8014 return false;
644d711a
NHE
8015}
8016
8017/*
8018 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8019 * should handle it ourselves in L0 (and then continue L2). Only call this
8020 * when in is_guest_mode (L2).
8021 */
8022static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8023{
644d711a
NHE
8024 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8025 struct vcpu_vmx *vmx = to_vmx(vcpu);
8026 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 8027 u32 exit_reason = vmx->exit_reason;
644d711a 8028
542060ea
JK
8029 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8030 vmcs_readl(EXIT_QUALIFICATION),
8031 vmx->idt_vectoring_info,
8032 intr_info,
8033 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8034 KVM_ISA_VMX);
8035
644d711a 8036 if (vmx->nested.nested_run_pending)
1d804d07 8037 return false;
644d711a
NHE
8038
8039 if (unlikely(vmx->fail)) {
bd80158a
JK
8040 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8041 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 8042 return true;
644d711a
NHE
8043 }
8044
8045 switch (exit_reason) {
8046 case EXIT_REASON_EXCEPTION_NMI:
ef85b673 8047 if (is_nmi(intr_info))
1d804d07 8048 return false;
644d711a 8049 else if (is_page_fault(intr_info))
52a5c155 8050 return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
e504c909 8051 else if (is_no_device(intr_info) &&
ccf9844e 8052 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 8053 return false;
6f05485d
JK
8054 else if (is_debug(intr_info) &&
8055 vcpu->guest_debug &
8056 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8057 return false;
8058 else if (is_breakpoint(intr_info) &&
8059 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8060 return false;
644d711a
NHE
8061 return vmcs12->exception_bitmap &
8062 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8063 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 8064 return false;
644d711a 8065 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 8066 return true;
644d711a 8067 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 8068 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 8069 case EXIT_REASON_NMI_WINDOW:
3b656cf7 8070 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 8071 case EXIT_REASON_TASK_SWITCH:
1d804d07 8072 return true;
644d711a 8073 case EXIT_REASON_CPUID:
1d804d07 8074 return true;
644d711a
NHE
8075 case EXIT_REASON_HLT:
8076 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8077 case EXIT_REASON_INVD:
1d804d07 8078 return true;
644d711a
NHE
8079 case EXIT_REASON_INVLPG:
8080 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8081 case EXIT_REASON_RDPMC:
8082 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
a5f46457
PB
8083 case EXIT_REASON_RDRAND:
8084 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8085 case EXIT_REASON_RDSEED:
8086 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
b3a2a907 8087 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE
8088 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8089 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8090 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8091 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8092 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8093 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 8094 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE
8095 /*
8096 * VMX instructions trap unconditionally. This allows L1 to
8097 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8098 */
1d804d07 8099 return true;
644d711a
NHE
8100 case EXIT_REASON_CR_ACCESS:
8101 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8102 case EXIT_REASON_DR_ACCESS:
8103 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8104 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 8105 return nested_vmx_exit_handled_io(vcpu, vmcs12);
1b07304c
PB
8106 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8107 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
644d711a
NHE
8108 case EXIT_REASON_MSR_READ:
8109 case EXIT_REASON_MSR_WRITE:
8110 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8111 case EXIT_REASON_INVALID_STATE:
1d804d07 8112 return true;
644d711a
NHE
8113 case EXIT_REASON_MWAIT_INSTRUCTION:
8114 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD
8115 case EXIT_REASON_MONITOR_TRAP_FLAG:
8116 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE
8117 case EXIT_REASON_MONITOR_INSTRUCTION:
8118 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8119 case EXIT_REASON_PAUSE_INSTRUCTION:
8120 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8121 nested_cpu_has2(vmcs12,
8122 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8123 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 8124 return false;
644d711a 8125 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 8126 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE
8127 case EXIT_REASON_APIC_ACCESS:
8128 return nested_cpu_has2(vmcs12,
8129 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 8130 case EXIT_REASON_APIC_WRITE:
608406e2
WV
8131 case EXIT_REASON_EOI_INDUCED:
8132 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 8133 return true;
644d711a 8134 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE
8135 /*
8136 * L0 always deals with the EPT violation. If nested EPT is
8137 * used, and the nested mmu code discovers that the address is
8138 * missing in the guest EPT table (EPT12), the EPT violation
8139 * will be injected with nested_ept_inject_page_fault()
8140 */
1d804d07 8141 return false;
644d711a 8142 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE
8143 /*
8144 * L2 never uses directly L1's EPT, but rather L0's own EPT
8145 * table (shadow on EPT) or a merged EPT table that L0 built
8146 * (EPT on EPT). So any problems with the structure of the
8147 * table is L0's fault.
8148 */
1d804d07 8149 return false;
644d711a
NHE
8150 case EXIT_REASON_WBINVD:
8151 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8152 case EXIT_REASON_XSETBV:
1d804d07 8153 return true;
81dc01f7
WL
8154 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8155 /*
8156 * This should never happen, since it is not possible to
8157 * set XSS to a non-zero value---neither in L1 nor in L2.
8158 * If if it were, XSS would have to be checked against
8159 * the XSS exit bitmap in vmcs12.
8160 */
8161 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
55123e3c
WL
8162 case EXIT_REASON_PREEMPTION_TIMER:
8163 return false;
ab007cc9 8164 case EXIT_REASON_PML_FULL:
03efce6f 8165 /* We emulate PML support to L1. */
ab007cc9 8166 return false;
644d711a 8167 default:
1d804d07 8168 return true;
644d711a
NHE
8169 }
8170}
8171
586f9607
AK
8172static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8173{
8174 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8175 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8176}
8177
a3eaa864 8178static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
843e4330 8179{
a3eaa864
KH
8180 if (vmx->pml_pg) {
8181 __free_page(vmx->pml_pg);
8182 vmx->pml_pg = NULL;
8183 }
843e4330
KH
8184}
8185
54bf36aa 8186static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 8187{
54bf36aa 8188 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH
8189 u64 *pml_buf;
8190 u16 pml_idx;
8191
8192 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8193
8194 /* Do nothing if PML buffer is empty */
8195 if (pml_idx == (PML_ENTITY_NUM - 1))
8196 return;
8197
8198 /* PML index always points to next available PML buffer entity */
8199 if (pml_idx >= PML_ENTITY_NUM)
8200 pml_idx = 0;
8201 else
8202 pml_idx++;
8203
8204 pml_buf = page_address(vmx->pml_pg);
8205 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8206 u64 gpa;
8207
8208 gpa = pml_buf[pml_idx];
8209 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 8210 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH
8211 }
8212
8213 /* reset PML index */
8214 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8215}
8216
8217/*
8218 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8219 * Called before reporting dirty_bitmap to userspace.
8220 */
8221static void kvm_flush_pml_buffers(struct kvm *kvm)
8222{
8223 int i;
8224 struct kvm_vcpu *vcpu;
8225 /*
8226 * We only need to kick vcpu out of guest mode here, as PML buffer
8227 * is flushed at beginning of all VMEXITs, and it's obvious that only
8228 * vcpus running in guest are possible to have unflushed GPAs in PML
8229 * buffer.
8230 */
8231 kvm_for_each_vcpu(i, vcpu, kvm)
8232 kvm_vcpu_kick(vcpu);
8233}
8234
4eb64dce
PB
8235static void vmx_dump_sel(char *name, uint32_t sel)
8236{
8237 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
96794e4e 8238 name, vmcs_read16(sel),
4eb64dce
PB
8239 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8240 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8241 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8242}
8243
8244static void vmx_dump_dtsel(char *name, uint32_t limit)
8245{
8246 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8247 name, vmcs_read32(limit),
8248 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8249}
8250
8251static void dump_vmcs(void)
8252{
8253 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8254 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8255 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8256 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8257 u32 secondary_exec_control = 0;
8258 unsigned long cr4 = vmcs_readl(GUEST_CR4);
f3531054 8259 u64 efer = vmcs_read64(GUEST_IA32_EFER);
4eb64dce
PB
8260 int i, n;
8261
8262 if (cpu_has_secondary_exec_ctrls())
8263 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8264
8265 pr_err("*** Guest State ***\n");
8266 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8267 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8268 vmcs_readl(CR0_GUEST_HOST_MASK));
8269 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8270 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8271 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8272 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8273 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8274 {
845c5b40
PB
8275 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8276 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8277 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8278 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
4eb64dce
PB
8279 }
8280 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8281 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8282 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8283 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8284 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8285 vmcs_readl(GUEST_SYSENTER_ESP),
8286 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8287 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8288 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8289 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8290 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8291 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8292 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8293 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8294 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8295 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8296 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8297 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8298 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
845c5b40
PB
8299 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8300 efer, vmcs_read64(GUEST_IA32_PAT));
8301 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8302 vmcs_read64(GUEST_IA32_DEBUGCTL),
4eb64dce
PB
8303 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8304 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
845c5b40
PB
8305 pr_err("PerfGlobCtl = 0x%016llx\n",
8306 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
4eb64dce 8307 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
845c5b40 8308 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
4eb64dce
PB
8309 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8310 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8311 vmcs_read32(GUEST_ACTIVITY_STATE));
8312 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8313 pr_err("InterruptStatus = %04x\n",
8314 vmcs_read16(GUEST_INTR_STATUS));
8315
8316 pr_err("*** Host State ***\n");
8317 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8318 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8319 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8320 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8321 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8322 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8323 vmcs_read16(HOST_TR_SELECTOR));
8324 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8325 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8326 vmcs_readl(HOST_TR_BASE));
8327 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8328 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8329 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8330 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8331 vmcs_readl(HOST_CR4));
8332 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8333 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8334 vmcs_read32(HOST_IA32_SYSENTER_CS),
8335 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8336 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
845c5b40
PB
8337 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8338 vmcs_read64(HOST_IA32_EFER),
8339 vmcs_read64(HOST_IA32_PAT));
4eb64dce 8340 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
845c5b40
PB
8341 pr_err("PerfGlobCtl = 0x%016llx\n",
8342 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
4eb64dce
PB
8343
8344 pr_err("*** Control State ***\n");
8345 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8346 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8347 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8348 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8349 vmcs_read32(EXCEPTION_BITMAP),
8350 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8351 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8352 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8353 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8354 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8355 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8356 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8357 vmcs_read32(VM_EXIT_INTR_INFO),
8358 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8359 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8360 pr_err(" reason=%08x qualification=%016lx\n",
8361 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8362 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8363 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8364 vmcs_read32(IDT_VECTORING_ERROR_CODE));
845c5b40 8365 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8cfe9866 8366 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
845c5b40
PB
8367 pr_err("TSC Multiplier = 0x%016llx\n",
8368 vmcs_read64(TSC_MULTIPLIER));
4eb64dce
PB
8369 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8370 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8371 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8372 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8373 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
845c5b40 8374 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
4eb64dce
PB
8375 n = vmcs_read32(CR3_TARGET_COUNT);
8376 for (i = 0; i + 1 < n; i += 4)
8377 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8378 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8379 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8380 if (i < n)
8381 pr_err("CR3 target%u=%016lx\n",
8382 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8383 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8384 pr_err("PLE Gap=%08x Window=%08x\n",
8385 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8386 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8387 pr_err("Virtual processor ID = 0x%04x\n",
8388 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8389}
8390
6aa8b732
AK
8391/*
8392 * The guest has exited. See if we can fix it or if we need userspace
8393 * assistance.
8394 */
851ba692 8395static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 8396{
29bd8a78 8397 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 8398 u32 exit_reason = vmx->exit_reason;
1155f76a 8399 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 8400
8b89fe1f 8401 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
db1c056c 8402 vcpu->arch.gpa_available = false;
8b89fe1f 8403
843e4330
KH
8404 /*
8405 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8406 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8407 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8408 * mode as if vcpus is in root mode, the PML buffer must has been
8409 * flushed already.
8410 */
8411 if (enable_pml)
54bf36aa 8412 vmx_flush_pml_buffer(vcpu);
843e4330 8413
80ced186 8414 /* If guest state is invalid, start emulating */
14168786 8415 if (vmx->emulation_required)
80ced186 8416 return handle_invalid_guest_state(vcpu);
1d5a4d9b 8417
644d711a 8418 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK
8419 nested_vmx_vmexit(vcpu, exit_reason,
8420 vmcs_read32(VM_EXIT_INTR_INFO),
8421 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE
8422 return 1;
8423 }
8424
5120702e 8425 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 8426 dump_vmcs();
5120702e
MG
8427 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8428 vcpu->run->fail_entry.hardware_entry_failure_reason
8429 = exit_reason;
8430 return 0;
8431 }
8432
29bd8a78 8433 if (unlikely(vmx->fail)) {
851ba692
AK
8434 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8435 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK
8436 = vmcs_read32(VM_INSTRUCTION_ERROR);
8437 return 0;
8438 }
6aa8b732 8439
b9bf6882
XG
8440 /*
8441 * Note:
8442 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8443 * delivery event since it indicates guest is accessing MMIO.
8444 * The vm-exit can be triggered again after return to guest that
8445 * will cause infinite loop.
8446 */
d77c26fc 8447 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 8448 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 8449 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b244c9fc 8450 exit_reason != EXIT_REASON_PML_FULL &&
b9bf6882
XG
8451 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8452 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8453 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
70bcd708 8454 vcpu->run->internal.ndata = 3;
b9bf6882
XG
8455 vcpu->run->internal.data[0] = vectoring_info;
8456 vcpu->run->internal.data[1] = exit_reason;
70bcd708
PB
8457 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8458 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8459 vcpu->run->internal.ndata++;
8460 vcpu->run->internal.data[3] =
8461 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8462 }
b9bf6882
XG
8463 return 0;
8464 }
3b86cd99 8465
6aa8b732
AK
8466 if (exit_reason < kvm_vmx_max_exit_handlers
8467 && kvm_vmx_exit_handlers[exit_reason])
851ba692 8468 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 8469 else {
6c6c5e03
RK
8470 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8471 exit_reason);
2bc19dc3
MT
8472 kvm_queue_exception(vcpu, UD_VECTOR);
8473 return 1;
6aa8b732 8474 }
6aa8b732
AK
8475}
8476
95ba8273 8477static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 8478{
a7c0b07d
WL
8479 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8480
8481 if (is_guest_mode(vcpu) &&
8482 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8483 return;
8484
95ba8273 8485 if (irr == -1 || tpr < irr) {
6e5d865c
YS
8486 vmcs_write32(TPR_THRESHOLD, 0);
8487 return;
8488 }
8489
95ba8273 8490 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS
8491}
8492
8d14695f
YZ
8493static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8494{
8495 u32 sec_exec_control;
8496
dccbfcf5
RK
8497 /* Postpone execution until vmcs01 is the current VMCS. */
8498 if (is_guest_mode(vcpu)) {
8499 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8500 return;
8501 }
8502
f6e90f9e 8503 if (!cpu_has_vmx_virtualize_x2apic_mode())
8d14695f
YZ
8504 return;
8505
35754c98 8506 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ
8507 return;
8508
8509 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8510
8511 if (set) {
8512 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8513 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8514 } else {
8515 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8516 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
fb6c8198 8517 vmx_flush_tlb_ept_only(vcpu);
8d14695f
YZ
8518 }
8519 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8520
8521 vmx_set_msr_bitmap(vcpu);
8522}
8523
38b99173
TC
8524static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8525{
8526 struct vcpu_vmx *vmx = to_vmx(vcpu);
8527
8528 /*
8529 * Currently we do not handle the nested case where L2 has an
8530 * APIC access page of its own; that page is still pinned.
8531 * Hence, we skip the case where the VCPU is in guest mode _and_
8532 * L1 prepared an APIC access page for L2.
8533 *
8534 * For the case where L1 and L2 share the same APIC access page
8535 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8536 * in the vmcs12), this function will only update either the vmcs01
8537 * or the vmcs02. If the former, the vmcs02 will be updated by
8538 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8539 * the next L2->L1 exit.
8540 */
8541 if (!is_guest_mode(vcpu) ||
4f2777bc 8542 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
fb6c8198 8543 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
38b99173 8544 vmcs_write64(APIC_ACCESS_ADDR, hpa);
fb6c8198
JM
8545 vmx_flush_tlb_ept_only(vcpu);
8546 }
38b99173
TC
8547}
8548
67c9dddc 8549static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
c7c9c56c
YZ
8550{
8551 u16 status;
8552 u8 old;
8553
67c9dddc
PB
8554 if (max_isr == -1)
8555 max_isr = 0;
c7c9c56c
YZ
8556
8557 status = vmcs_read16(GUEST_INTR_STATUS);
8558 old = status >> 8;
67c9dddc 8559 if (max_isr != old) {
c7c9c56c 8560 status &= 0xff;
67c9dddc 8561 status |= max_isr << 8;
c7c9c56c
YZ
8562 vmcs_write16(GUEST_INTR_STATUS, status);
8563 }
8564}
8565
8566static void vmx_set_rvi(int vector)
8567{
8568 u16 status;
8569 u8 old;
8570
4114c27d
WW
8571 if (vector == -1)
8572 vector = 0;
8573
c7c9c56c
YZ
8574 status = vmcs_read16(GUEST_INTR_STATUS);
8575 old = (u8)status & 0xff;
8576 if ((u8)vector != old) {
8577 status &= ~0xff;
8578 status |= (u8)vector;
8579 vmcs_write16(GUEST_INTR_STATUS, status);
8580 }
8581}
8582
8583static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8584{
4114c27d
WW
8585 if (!is_guest_mode(vcpu)) {
8586 vmx_set_rvi(max_irr);
8587 return;
8588 }
8589
c7c9c56c
YZ
8590 if (max_irr == -1)
8591 return;
8592
963fee16 8593 /*
4114c27d
WW
8594 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8595 * handles it.
963fee16 8596 */
4114c27d 8597 if (nested_exit_on_intr(vcpu))
963fee16
WL
8598 return;
8599
963fee16 8600 /*
4114c27d 8601 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL
8602 * is run without virtual interrupt delivery.
8603 */
8604 if (!kvm_event_needs_reinjection(vcpu) &&
8605 vmx_interrupt_allowed(vcpu)) {
8606 kvm_queue_interrupt(vcpu, max_irr, false);
8607 vmx_inject_irq(vcpu);
8608 }
c7c9c56c
YZ
8609}
8610
76dfafd5 8611static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
810e6def
PB
8612{
8613 struct vcpu_vmx *vmx = to_vmx(vcpu);
76dfafd5 8614 int max_irr;
810e6def 8615
76dfafd5
PB
8616 WARN_ON(!vcpu->arch.apicv_active);
8617 if (pi_test_on(&vmx->pi_desc)) {
8618 pi_clear_on(&vmx->pi_desc);
8619 /*
8620 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8621 * But on x86 this is just a compiler barrier anyway.
8622 */
8623 smp_mb__after_atomic();
8624 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8625 } else {
8626 max_irr = kvm_lapic_find_highest_irr(vcpu);
8627 }
8628 vmx_hwapic_irr_update(vcpu, max_irr);
8629 return max_irr;
810e6def
PB
8630}
8631
6308630b 8632static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
c7c9c56c 8633{
d62caabb 8634 if (!kvm_vcpu_apicv_active(vcpu))
3d81bc7e
YZ
8635 return;
8636
c7c9c56c
YZ
8637 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8638 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8639 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8640 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8641}
8642
967235d3
PB
8643static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8644{
8645 struct vcpu_vmx *vmx = to_vmx(vcpu);
8646
8647 pi_clear_on(&vmx->pi_desc);
8648 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8649}
8650
51aa01d1 8651static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8652{
48ae0fb4
JM
8653 u32 exit_intr_info = 0;
8654 u16 basic_exit_reason = (u16)vmx->exit_reason;
00eba012 8655
48ae0fb4
JM
8656 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8657 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
00eba012
AK
8658 return;
8659
48ae0fb4
JM
8660 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
8661 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8662 vmx->exit_intr_info = exit_intr_info;
a0861c02 8663
1261bfa3
WL
8664 /* if exit due to PF check for async PF */
8665 if (is_page_fault(exit_intr_info))
8666 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
8667
a0861c02 8668 /* Handle machine checks before interrupts are enabled */
48ae0fb4
JM
8669 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
8670 is_machine_check(exit_intr_info))
a0861c02
AK
8671 kvm_machine_check();
8672
20f65983 8673 /* We need to handle NMIs before interrupts are enabled */
ef85b673 8674 if (is_nmi(exit_intr_info)) {
ff9d07a0 8675 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8676 asm("int $2");
ff9d07a0
ZY
8677 kvm_after_handle_nmi(&vmx->vcpu);
8678 }
51aa01d1 8679}
20f65983 8680
a547c6db
YZ
8681static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8682{
8683 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3f62de5f 8684 register void *__sp asm(_ASM_SP);
a547c6db 8685
a547c6db
YZ
8686 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8687 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8688 unsigned int vector;
8689 unsigned long entry;
8690 gate_desc *desc;
8691 struct vcpu_vmx *vmx = to_vmx(vcpu);
8692#ifdef CONFIG_X86_64
8693 unsigned long tmp;
8694#endif
8695
8696 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8697 desc = (gate_desc *)vmx->host_idt_base + vector;
8698 entry = gate_offset(*desc);
8699 asm volatile(
8700#ifdef CONFIG_X86_64
8701 "mov %%" _ASM_SP ", %[sp]\n\t"
8702 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8703 "push $%c[ss]\n\t"
8704 "push %[sp]\n\t"
8705#endif
8706 "pushf\n\t"
a547c6db
YZ
8707 __ASM_SIZE(push) " $%c[cs]\n\t"
8708 "call *%[entry]\n\t"
8709 :
8710#ifdef CONFIG_X86_64
3f62de5f 8711 [sp]"=&r"(tmp),
a547c6db 8712#endif
3f62de5f 8713 "+r"(__sp)
a547c6db
YZ
8714 :
8715 [entry]"r"(entry),
8716 [ss]"i"(__KERNEL_DS),
8717 [cs]"i"(__KERNEL_CS)
8718 );
f2485b3e 8719 }
a547c6db 8720}
c207aee4 8721STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
a547c6db 8722
6d396b55
PB
8723static bool vmx_has_high_real_mode_segbase(void)
8724{
8725 return enable_unrestricted_guest || emulate_invalid_guest_state;
8726}
8727
da8999d3
LJ
8728static bool vmx_mpx_supported(void)
8729{
8730 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8731 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8732}
8733
55412b2e
WL
8734static bool vmx_xsaves_supported(void)
8735{
8736 return vmcs_config.cpu_based_2nd_exec_ctrl &
8737 SECONDARY_EXEC_XSAVES;
8738}
8739
51aa01d1
AK
8740static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8741{
c5ca8e57 8742 u32 exit_intr_info;
51aa01d1
AK
8743 bool unblock_nmi;
8744 u8 vector;
8745 bool idtv_info_valid;
8746
8747 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8748
4c4a6f79 8749 if (vmx->loaded_vmcs->nmi_known_unmasked)
2c82878b
PB
8750 return;
8751 /*
8752 * Can't use vmx->exit_intr_info since we're not sure what
8753 * the exit reason is.
8754 */
8755 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8756 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8757 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8758 /*
8759 * SDM 3: 27.7.1.2 (September 2008)
8760 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8761 * a guest IRET fault.
8762 * SDM 3: 23.2.2 (September 2008)
8763 * Bit 12 is undefined in any of the following cases:
8764 * If the VM exit sets the valid bit in the IDT-vectoring
8765 * information field.
8766 * If the VM exit is due to a double fault.
8767 */
8768 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8769 vector != DF_VECTOR && !idtv_info_valid)
8770 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8771 GUEST_INTR_STATE_NMI);
8772 else
4c4a6f79 8773 vmx->loaded_vmcs->nmi_known_unmasked =
2c82878b
PB
8774 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8775 & GUEST_INTR_STATE_NMI);
51aa01d1
AK
8776}
8777
3ab66e8a 8778static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK
8779 u32 idt_vectoring_info,
8780 int instr_len_field,
8781 int error_code_field)
51aa01d1 8782{
51aa01d1
AK
8783 u8 vector;
8784 int type;
8785 bool idtv_info_valid;
8786
8787 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8788
3ab66e8a
JK
8789 vcpu->arch.nmi_injected = false;
8790 kvm_clear_exception_queue(vcpu);
8791 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN
8792
8793 if (!idtv_info_valid)
8794 return;
8795
3ab66e8a 8796 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8797
668f612f
AK
8798 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8799 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8800
64a7ec06 8801 switch (type) {
37b96e98 8802 case INTR_TYPE_NMI_INTR:
3ab66e8a 8803 vcpu->arch.nmi_injected = true;
668f612f 8804 /*
7b4a25cb 8805 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN
8806 * Clear bit "block by NMI" before VM entry if a NMI
8807 * delivery faulted.
668f612f 8808 */
3ab66e8a 8809 vmx_set_nmi_mask(vcpu, false);
37b96e98 8810 break;
37b96e98 8811 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8812 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN
8813 /* fall through */
8814 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8815 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8816 u32 err = vmcs_read32(error_code_field);
851eb667 8817 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8818 } else
851eb667 8819 kvm_requeue_exception(vcpu, vector);
37b96e98 8820 break;
66fd3f7f 8821 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8822 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8823 /* fall through */
37b96e98 8824 case INTR_TYPE_EXT_INTR:
3ab66e8a 8825 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN
8826 break;
8827 default:
8828 break;
f7d9238f 8829 }
cf393f75
AK
8830}
8831
83422e17
AK
8832static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8833{
3ab66e8a 8834 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK
8835 VM_EXIT_INSTRUCTION_LEN,
8836 IDT_VECTORING_ERROR_CODE);
8837}
8838
b463a6f7
AK
8839static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8840{
3ab66e8a 8841 __vmx_complete_interrupts(vcpu,
b463a6f7
AK
8842 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8843 VM_ENTRY_INSTRUCTION_LEN,
8844 VM_ENTRY_EXCEPTION_ERROR_CODE);
8845
8846 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8847}
8848
d7cd9796
GN
8849static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8850{
8851 int i, nr_msrs;
8852 struct perf_guest_switch_msr *msrs;
8853
8854 msrs = perf_guest_get_msrs(&nr_msrs);
8855
8856 if (!msrs)
8857 return;
8858
8859 for (i = 0; i < nr_msrs; i++)
8860 if (msrs[i].host == msrs[i].guest)
8861 clear_atomic_switch_msr(vmx, msrs[i].msr);
8862 else
8863 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8864 msrs[i].host);
8865}
8866
33365e7a 8867static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
64672c95
YJ
8868{
8869 struct vcpu_vmx *vmx = to_vmx(vcpu);
8870 u64 tscl;
8871 u32 delta_tsc;
8872
8873 if (vmx->hv_deadline_tsc == -1)
8874 return;
8875
8876 tscl = rdtsc();
8877 if (vmx->hv_deadline_tsc > tscl)
8878 /* sure to be 32 bit only because checked on set_hv_timer */
8879 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8880 cpu_preemption_timer_multi);
8881 else
8882 delta_tsc = 0;
8883
8884 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8885}
8886
a3b5ba49 8887static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8888{
a2fa3e9f 8889 struct vcpu_vmx *vmx = to_vmx(vcpu);
d6e41f11 8890 unsigned long debugctlmsr, cr3, cr4;
104f226b 8891
104f226b
AK
8892 /* Don't enter VMX if guest state is invalid, let the exit handler
8893 start emulation until we arrive back to a valid state */
14168786 8894 if (vmx->emulation_required)
104f226b
AK
8895 return;
8896
a7653ecd
RK
8897 if (vmx->ple_window_dirty) {
8898 vmx->ple_window_dirty = false;
8899 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8900 }
8901
012f83cb
AG
8902 if (vmx->nested.sync_shadow_vmcs) {
8903 copy_vmcs12_to_shadow(vmx);
8904 vmx->nested.sync_shadow_vmcs = false;
8905 }
8906
104f226b
AK
8907 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8908 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8909 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8910 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8911
d6e41f11
AL
8912 cr3 = __get_current_cr3_fast();
8913 if (unlikely(cr3 != vmx->host_state.vmcs_host_cr3)) {
8914 vmcs_writel(HOST_CR3, cr3);
8915 vmx->host_state.vmcs_host_cr3 = cr3;
8916 }
8917
1e02ce4c 8918 cr4 = cr4_read_shadow();
d974baa3
AL
8919 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8920 vmcs_writel(HOST_CR4, cr4);
8921 vmx->host_state.vmcs_host_cr4 = cr4;
8922 }
8923
104f226b
AK
8924 /* When single-stepping over STI and MOV SS, we must clear the
8925 * corresponding interruptibility bits in the guest state. Otherwise
8926 * vmentry fails as it then expects bit 14 (BS) in pending debug
8927 * exceptions being set, but that's not correct for the guest debugging
8928 * case. */
8929 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8930 vmx_set_interrupt_shadow(vcpu, 0);
8931
1be0e61c
XG
8932 if (vmx->guest_pkru_valid)
8933 __write_pkru(vmx->guest_pkru);
8934
d7cd9796 8935 atomic_switch_perf_msrs(vmx);
2a7921b7 8936 debugctlmsr = get_debugctlmsr();
d7cd9796 8937
64672c95
YJ
8938 vmx_arm_hv_timer(vcpu);
8939
d462b819 8940 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8941 asm(
6aa8b732 8942 /* Store host registers */
b188c81f
AK
8943 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8944 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8945 "push %%" _ASM_CX " \n\t"
8946 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8947 "je 1f \n\t"
b188c81f 8948 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8949 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8950 "1: \n\t"
d3edefc0 8951 /* Reload cr2 if changed */
b188c81f
AK
8952 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8953 "mov %%cr2, %%" _ASM_DX " \n\t"
8954 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8955 "je 2f \n\t"
b188c81f 8956 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8957 "2: \n\t"
6aa8b732 8958 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8959 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8960 /* Load guest registers. Don't clobber flags. */
b188c81f
AK
8961 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8962 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8963 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8964 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8965 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8966 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8967#ifdef CONFIG_X86_64
e08aa78a
AK
8968 "mov %c[r8](%0), %%r8 \n\t"
8969 "mov %c[r9](%0), %%r9 \n\t"
8970 "mov %c[r10](%0), %%r10 \n\t"
8971 "mov %c[r11](%0), %%r11 \n\t"
8972 "mov %c[r12](%0), %%r12 \n\t"
8973 "mov %c[r13](%0), %%r13 \n\t"
8974 "mov %c[r14](%0), %%r14 \n\t"
8975 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8976#endif
b188c81f 8977 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8978
6aa8b732 8979 /* Enter guest mode */
83287ea4 8980 "jne 1f \n\t"
4ecac3fd 8981 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK
8982 "jmp 2f \n\t"
8983 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8984 "2: "
6aa8b732 8985 /* Save guest registers, load host registers, keep flags */
b188c81f 8986 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8987 "pop %0 \n\t"
b188c81f
AK
8988 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8989 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8990 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8991 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8992 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8993 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8994 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8995#ifdef CONFIG_X86_64
e08aa78a
AK
8996 "mov %%r8, %c[r8](%0) \n\t"
8997 "mov %%r9, %c[r9](%0) \n\t"
8998 "mov %%r10, %c[r10](%0) \n\t"
8999 "mov %%r11, %c[r11](%0) \n\t"
9000 "mov %%r12, %c[r12](%0) \n\t"
9001 "mov %%r13, %c[r13](%0) \n\t"
9002 "mov %%r14, %c[r14](%0) \n\t"
9003 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 9004#endif
b188c81f
AK
9005 "mov %%cr2, %%" _ASM_AX " \n\t"
9006 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 9007
b188c81f 9008 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 9009 "setbe %c[fail](%0) \n\t"
83287ea4
AK
9010 ".pushsection .rodata \n\t"
9011 ".global vmx_return \n\t"
9012 "vmx_return: " _ASM_PTR " 2b \n\t"
9013 ".popsection"
e08aa78a 9014 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 9015 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 9016 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 9017 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX
9018 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9019 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9020 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9021 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9022 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9023 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9024 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 9025#ifdef CONFIG_X86_64
ad312c7c
ZX
9026 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9027 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9028 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9029 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9030 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9031 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9032 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9033 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 9034#endif
40712fae
AK
9035 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9036 [wordsize]"i"(sizeof(ulong))
c2036300
LV
9037 : "cc", "memory"
9038#ifdef CONFIG_X86_64
b188c81f 9039 , "rax", "rbx", "rdi", "rsi"
c2036300 9040 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK
9041#else
9042 , "eax", "ebx", "edi", "esi"
c2036300
LV
9043#endif
9044 );
6aa8b732 9045
2a7921b7
GN
9046 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9047 if (debugctlmsr)
9048 update_debugctlmsr(debugctlmsr);
9049
aa67f609
AK
9050#ifndef CONFIG_X86_64
9051 /*
9052 * The sysexit path does not restore ds/es, so we must set them to
9053 * a reasonable value ourselves.
9054 *
9055 * We can't defer this to vmx_load_host_state() since that function
9056 * may be executed in interrupt context, which saves and restore segments
9057 * around it, nullifying its effect.
9058 */
9059 loadsegment(ds, __USER_DS);
9060 loadsegment(es, __USER_DS);
9061#endif
9062
6de4f3ad 9063 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 9064 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 9065 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 9066 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 9067 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT
9068 vcpu->arch.regs_dirty = 0;
9069
1155f76a
AK
9070 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9071
d462b819 9072 vmx->loaded_vmcs->launched = 1;
1b6269db 9073
51aa01d1 9074 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1 9075
1be0e61c
XG
9076 /*
9077 * eager fpu is enabled if PKEY is supported and CR4 is switched
9078 * back on host, so it is safe to read guest PKRU from current
9079 * XSAVE.
9080 */
9081 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9082 vmx->guest_pkru = __read_pkru();
9083 if (vmx->guest_pkru != vmx->host_pkru) {
9084 vmx->guest_pkru_valid = true;
9085 __write_pkru(vmx->host_pkru);
9086 } else
9087 vmx->guest_pkru_valid = false;
9088 }
9089
e0b890d3
GN
9090 /*
9091 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9092 * we did not inject a still-pending event to L1 now because of
9093 * nested_run_pending, we need to re-enable this bit.
9094 */
9095 if (vmx->nested.nested_run_pending)
9096 kvm_make_request(KVM_REQ_EVENT, vcpu);
9097
9098 vmx->nested.nested_run_pending = 0;
9099
51aa01d1
AK
9100 vmx_complete_atomic_exit(vmx);
9101 vmx_recover_nmi_blocking(vmx);
cf393f75 9102 vmx_complete_interrupts(vmx);
6aa8b732 9103}
c207aee4 9104STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
6aa8b732 9105
1279a6b1 9106static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
4fa7734c
PB
9107{
9108 struct vcpu_vmx *vmx = to_vmx(vcpu);
9109 int cpu;
9110
1279a6b1 9111 if (vmx->loaded_vmcs == vmcs)
4fa7734c
PB
9112 return;
9113
9114 cpu = get_cpu();
1279a6b1 9115 vmx->loaded_vmcs = vmcs;
4fa7734c
PB
9116 vmx_vcpu_put(vcpu);
9117 vmx_vcpu_load(vcpu, cpu);
9118 vcpu->cpu = cpu;
9119 put_cpu();
9120}
9121
2f1fe811
JM
9122/*
9123 * Ensure that the current vmcs of the logical processor is the
9124 * vmcs01 of the vcpu before calling free_nested().
9125 */
9126static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9127{
9128 struct vcpu_vmx *vmx = to_vmx(vcpu);
9129 int r;
9130
9131 r = vcpu_load(vcpu);
9132 BUG_ON(r);
1279a6b1 9133 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
2f1fe811
JM
9134 free_nested(vmx);
9135 vcpu_put(vcpu);
9136}
9137
6aa8b732
AK
9138static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9139{
fb3f0f51
RR
9140 struct vcpu_vmx *vmx = to_vmx(vcpu);
9141
843e4330 9142 if (enable_pml)
a3eaa864 9143 vmx_destroy_pml_buffer(vmx);
991e7a0e 9144 free_vpid(vmx->vpid);
4fa7734c 9145 leave_guest_mode(vcpu);
2f1fe811 9146 vmx_free_vcpu_nested(vcpu);
4fa7734c 9147 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR
9148 kfree(vmx->guest_msrs);
9149 kvm_vcpu_uninit(vcpu);
a4770347 9150 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK
9151}
9152
fb3f0f51 9153static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 9154{
fb3f0f51 9155 int err;
c16f862d 9156 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 9157 int cpu;
6aa8b732 9158
a2fa3e9f 9159 if (!vmx)
fb3f0f51
RR
9160 return ERR_PTR(-ENOMEM);
9161
991e7a0e 9162 vmx->vpid = allocate_vpid();
2384d2b3 9163
fb3f0f51
RR
9164 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9165 if (err)
9166 goto free_vcpu;
965b58a5 9167
4e59516a
PF
9168 err = -ENOMEM;
9169
9170 /*
9171 * If PML is turned on, failure on enabling PML just results in failure
9172 * of creating the vcpu, therefore we can simplify PML logic (by
9173 * avoiding dealing with cases, such as enabling PML partially on vcpus
9174 * for the guest, etc.
9175 */
9176 if (enable_pml) {
9177 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9178 if (!vmx->pml_pg)
9179 goto uninit_vcpu;
9180 }
9181
a2fa3e9f 9182 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB
9183 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9184 > PAGE_SIZE);
0123be42 9185
4e59516a
PF
9186 if (!vmx->guest_msrs)
9187 goto free_pml;
965b58a5 9188
d462b819
NHE
9189 vmx->loaded_vmcs = &vmx->vmcs01;
9190 vmx->loaded_vmcs->vmcs = alloc_vmcs();
355f4fb1 9191 vmx->loaded_vmcs->shadow_vmcs = NULL;
d462b819 9192 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 9193 goto free_msrs;
d462b819 9194 loaded_vmcs_init(vmx->loaded_vmcs);
a2fa3e9f 9195
15ad7146
AK
9196 cpu = get_cpu();
9197 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 9198 vmx->vcpu.cpu = cpu;
8b9cf98c 9199 err = vmx_vcpu_setup(vmx);
fb3f0f51 9200 vmx_vcpu_put(&vmx->vcpu);
15ad7146 9201 put_cpu();
fb3f0f51
RR
9202 if (err)
9203 goto free_vmcs;
35754c98 9204 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK
9205 err = alloc_apic_access_page(kvm);
9206 if (err)
5e4a0b3c 9207 goto free_vmcs;
a63cb560 9208 }
fb3f0f51 9209
b927a3ce
SY
9210 if (enable_ept) {
9211 if (!kvm->arch.ept_identity_map_addr)
9212 kvm->arch.ept_identity_map_addr =
9213 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC
9214 err = init_rmode_identity_map(kvm);
9215 if (err)
93ea5388 9216 goto free_vmcs;
b927a3ce 9217 }
b7ebfb05 9218
5c614b35 9219 if (nested) {
b9c237bb 9220 nested_vmx_setup_ctls_msrs(vmx);
5c614b35
WL
9221 vmx->nested.vpid02 = allocate_vpid();
9222 }
b9c237bb 9223
705699a1 9224 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE
9225 vmx->nested.current_vmptr = -1ull;
9226 vmx->nested.current_vmcs12 = NULL;
9227
37e4c997
HZ
9228 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9229
fb3f0f51
RR
9230 return &vmx->vcpu;
9231
9232free_vmcs:
5c614b35 9233 free_vpid(vmx->nested.vpid02);
5f3fbc34 9234 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 9235free_msrs:
fb3f0f51 9236 kfree(vmx->guest_msrs);
4e59516a
PF
9237free_pml:
9238 vmx_destroy_pml_buffer(vmx);
fb3f0f51
RR
9239uninit_vcpu:
9240 kvm_vcpu_uninit(&vmx->vcpu);
9241free_vcpu:
991e7a0e 9242 free_vpid(vmx->vpid);
a4770347 9243 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 9244 return ERR_PTR(err);
6aa8b732
AK
9245}
9246
002c7f7c
YS
9247static void __init vmx_check_processor_compat(void *rtn)
9248{
9249 struct vmcs_config vmcs_conf;
9250
9251 *(int *)rtn = 0;
9252 if (setup_vmcs_config(&vmcs_conf) < 0)
9253 *(int *)rtn = -EIO;
9254 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9255 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9256 smp_processor_id());
9257 *(int *)rtn = -EIO;
9258 }
9259}
9260
67253af5
SY
9261static int get_ept_level(void)
9262{
9263 return VMX_EPT_DEFAULT_GAW + 1;
9264}
9265
4b12f0de 9266static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 9267{
b18d5431
XG
9268 u8 cache;
9269 u64 ipat = 0;
4b12f0de 9270
522c68c4 9271 /* For VT-d and EPT combination
606decd6 9272 * 1. MMIO: always map as UC
522c68c4
SY
9273 * 2. EPT with VT-d:
9274 * a. VT-d without snooping control feature: can't guarantee the
606decd6 9275 * result, try to trust guest.
522c68c4
SY
9276 * b. VT-d with snooping control feature: snooping control feature of
9277 * VT-d engine can guarantee the cache correctness. Just set it
9278 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 9279 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY
9280 * consistent with host MTRR
9281 */
606decd6
PB
9282 if (is_mmio) {
9283 cache = MTRR_TYPE_UNCACHABLE;
9284 goto exit;
9285 }
9286
9287 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG
9288 ipat = VMX_EPT_IPAT_BIT;
9289 cache = MTRR_TYPE_WRBACK;
9290 goto exit;
9291 }
9292
9293 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9294 ipat = VMX_EPT_IPAT_BIT;
0da029ed 9295 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG
9296 cache = MTRR_TYPE_WRBACK;
9297 else
9298 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG
9299 goto exit;
9300 }
9301
ff53604b 9302 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG
9303
9304exit:
9305 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY
9306}
9307
17cc3935 9308static int vmx_get_lpage_level(void)
344f414f 9309{
878403b7
SY
9310 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9311 return PT_DIRECTORY_LEVEL;
9312 else
9313 /* For shadow and EPT supported 1GB page */
9314 return PT_PDPE_LEVEL;
344f414f
JR
9315}
9316
feda805f
XG
9317static void vmcs_set_secondary_exec_control(u32 new_ctl)
9318{
9319 /*
9320 * These bits in the secondary execution controls field
9321 * are dynamic, the others are mostly based on the hypervisor
9322 * architecture and the guest's CPUID. Do not touch the
9323 * dynamic bits.
9324 */
9325 u32 mask =
9326 SECONDARY_EXEC_SHADOW_VMCS |
9327 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9328 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9329
9330 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9331
9332 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9333 (new_ctl & ~mask) | (cur_ctl & mask));
9334}
9335
8322ebbb
DM
9336/*
9337 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9338 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9339 */
9340static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9341{
9342 struct vcpu_vmx *vmx = to_vmx(vcpu);
9343 struct kvm_cpuid_entry2 *entry;
9344
9345 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9346 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9347
9348#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9349 if (entry && (entry->_reg & (_cpuid_mask))) \
9350 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9351} while (0)
9352
9353 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9354 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
9355 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
9356 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
9357 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
9358 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
9359 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
9360 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
9361 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
9362 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
9363 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9364 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
9365 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
9366 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
9367 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
9368
9369 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9370 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
9371 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
9372 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
9373 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
9374 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9375 cr4_fixed1_update(bit(11), ecx, bit(2));
9376
9377#undef cr4_fixed1_update
9378}
9379
0e851880
SY
9380static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9381{
4e47c7a6
SY
9382 struct kvm_cpuid_entry2 *best;
9383 struct vcpu_vmx *vmx = to_vmx(vcpu);
feda805f 9384 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
4e47c7a6 9385
4e47c7a6 9386 if (vmx_rdtscp_supported()) {
1cea0ce6
XG
9387 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9388 if (!rdtscp_enabled)
feda805f 9389 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
f36201e5 9390
8b97265a 9391 if (nested) {
1cea0ce6 9392 if (rdtscp_enabled)
8b97265a
PB
9393 vmx->nested.nested_vmx_secondary_ctls_high |=
9394 SECONDARY_EXEC_RDTSCP;
9395 else
9396 vmx->nested.nested_vmx_secondary_ctls_high &=
9397 ~SECONDARY_EXEC_RDTSCP;
9398 }
4e47c7a6 9399 }
ad756a16 9400
ad756a16
MJ
9401 /* Exposing INVPCID only when PCID is exposed */
9402 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9403 if (vmx_invpcid_supported() &&
29541bb8
XG
9404 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9405 !guest_cpuid_has_pcid(vcpu))) {
feda805f 9406 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
29541bb8 9407
ad756a16 9408 if (best)
4f977045 9409 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 9410 }
8b3e34e4 9411
45bdbcfd
HH
9412 if (cpu_has_secondary_exec_ctrls())
9413 vmcs_set_secondary_exec_control(secondary_exec_ctl);
feda805f 9414
37e4c997
HZ
9415 if (nested_vmx_allowed(vcpu))
9416 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9417 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9418 else
9419 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9420 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
8322ebbb
DM
9421
9422 if (nested_vmx_allowed(vcpu))
9423 nested_vmx_cr_fixed1_bits_update(vcpu);
0e851880
SY
9424}
9425
d4330ef2
JR
9426static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9427{
7b8050f5
NHE
9428 if (func == 1 && nested)
9429 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR
9430}
9431
25d92081
YZ
9432static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9433 struct x86_exception *fault)
9434{
533558bc 9435 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
c5f983f6 9436 struct vcpu_vmx *vmx = to_vmx(vcpu);
533558bc 9437 u32 exit_reason;
c5f983f6 9438 unsigned long exit_qualification = vcpu->arch.exit_qualification;
25d92081 9439
c5f983f6
BD
9440 if (vmx->nested.pml_full) {
9441 exit_reason = EXIT_REASON_PML_FULL;
9442 vmx->nested.pml_full = false;
9443 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9444 } else if (fault->error_code & PFERR_RSVD_MASK)
533558bc 9445 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 9446 else
533558bc 9447 exit_reason = EXIT_REASON_EPT_VIOLATION;
c5f983f6
BD
9448
9449 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
25d92081
YZ
9450 vmcs12->guest_physical_address = fault->address;
9451}
9452
995f00a6
PF
9453static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9454{
9455 return nested_ept_get_cr3(vcpu) & VMX_EPT_AD_ENABLE_BIT;
9456}
9457
155a97a3
NHE
9458/* Callbacks for nested_ept_init_mmu_context: */
9459
9460static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9461{
9462 /* return the page table to be shadowed - in our case, EPT12 */
9463 return get_vmcs12(vcpu)->ept_pointer;
9464}
9465
ae1e2d10 9466static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 9467{
995f00a6 9468 bool wants_ad;
ae1e2d10 9469
ad896af0 9470 WARN_ON(mmu_is_nested(vcpu));
995f00a6
PF
9471 wants_ad = nested_ept_ad_enabled(vcpu);
9472 if (wants_ad && !enable_ept_ad_bits)
ae1e2d10
PB
9473 return 1;
9474
9475 kvm_mmu_unload(vcpu);
ad896af0 9476 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb 9477 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
ae1e2d10 9478 VMX_EPT_EXECUTE_ONLY_BIT,
995f00a6 9479 wants_ad);
155a97a3
NHE
9480 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9481 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9482 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9483
9484 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
ae1e2d10 9485 return 0;
155a97a3
NHE
9486}
9487
9488static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9489{
9490 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9491}
9492
19d5f10b
EK
9493static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9494 u16 error_code)
9495{
9496 bool inequality, bit;
9497
9498 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9499 inequality =
9500 (error_code & vmcs12->page_fault_error_code_mask) !=
9501 vmcs12->page_fault_error_code_match;
9502 return inequality ^ bit;
9503}
9504
feaf0c7d
GN
9505static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9506 struct x86_exception *fault)
9507{
9508 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9509
9510 WARN_ON(!is_guest_mode(vcpu));
9511
19d5f10b 9512 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK
9513 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9514 vmcs_read32(VM_EXIT_INTR_INFO),
9515 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN
9516 else
9517 kvm_inject_page_fault(vcpu, fault);
9518}
9519
6beb7bd5
JM
9520static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9521 struct vmcs12 *vmcs12);
9522
9523static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
a2bcba50
WL
9524 struct vmcs12 *vmcs12)
9525{
9526 struct vcpu_vmx *vmx = to_vmx(vcpu);
6beb7bd5 9527 u64 hpa;
a2bcba50
WL
9528
9529 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a2bcba50
WL
9530 /*
9531 * Translate L1 physical address to host physical
9532 * address for vmcs02. Keep the page pinned, so this
9533 * physical address remains valid. We keep a reference
9534 * to it so we can release it later.
9535 */
9536 if (vmx->nested.apic_access_page) /* shouldn't happen */
9537 nested_release_page(vmx->nested.apic_access_page);
9538 vmx->nested.apic_access_page =
9539 nested_get_page(vcpu, vmcs12->apic_access_addr);
6beb7bd5
JM
9540 /*
9541 * If translation failed, no matter: This feature asks
9542 * to exit when accessing the given address, and if it
9543 * can never be accessed, this feature won't do
9544 * anything anyway.
9545 */
9546 if (vmx->nested.apic_access_page) {
9547 hpa = page_to_phys(vmx->nested.apic_access_page);
9548 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9549 } else {
9550 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9551 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9552 }
9553 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9554 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9555 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9556 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9557 kvm_vcpu_reload_apic_access_page(vcpu);
a2bcba50 9558 }
a7c0b07d
WL
9559
9560 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
a7c0b07d
WL
9561 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9562 nested_release_page(vmx->nested.virtual_apic_page);
9563 vmx->nested.virtual_apic_page =
9564 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9565
9566 /*
6beb7bd5
JM
9567 * If translation failed, VM entry will fail because
9568 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9569 * Failing the vm entry is _not_ what the processor
9570 * does but it's basically the only possibility we
9571 * have. We could still enter the guest if CR8 load
9572 * exits are enabled, CR8 store exits are enabled, and
9573 * virtualize APIC access is disabled; in this case
9574 * the processor would never use the TPR shadow and we
9575 * could simply clear the bit from the execution
9576 * control. But such a configuration is useless, so
9577 * let's keep the code simple.
a7c0b07d 9578 */
6beb7bd5
JM
9579 if (vmx->nested.virtual_apic_page) {
9580 hpa = page_to_phys(vmx->nested.virtual_apic_page);
9581 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9582 }
a7c0b07d
WL
9583 }
9584
705699a1 9585 if (nested_cpu_has_posted_intr(vmcs12)) {
705699a1
WV
9586 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9587 kunmap(vmx->nested.pi_desc_page);
9588 nested_release_page(vmx->nested.pi_desc_page);
9589 }
9590 vmx->nested.pi_desc_page =
9591 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
705699a1
WV
9592 vmx->nested.pi_desc =
9593 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9594 if (!vmx->nested.pi_desc) {
9595 nested_release_page_clean(vmx->nested.pi_desc_page);
6beb7bd5 9596 return;
705699a1
WV
9597 }
9598 vmx->nested.pi_desc =
9599 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9600 (unsigned long)(vmcs12->posted_intr_desc_addr &
9601 (PAGE_SIZE - 1)));
6beb7bd5
JM
9602 vmcs_write64(POSTED_INTR_DESC_ADDR,
9603 page_to_phys(vmx->nested.pi_desc_page) +
9604 (unsigned long)(vmcs12->posted_intr_desc_addr &
9605 (PAGE_SIZE - 1)));
705699a1 9606 }
6beb7bd5
JM
9607 if (cpu_has_vmx_msr_bitmap() &&
9608 nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9609 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9610 ;
9611 else
9612 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9613 CPU_BASED_USE_MSR_BITMAPS);
a2bcba50
WL
9614}
9615
f4124500
JK
9616static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9617{
9618 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9619 struct vcpu_vmx *vmx = to_vmx(vcpu);
9620
9621 if (vcpu->arch.virtual_tsc_khz == 0)
9622 return;
9623
9624 /* Make sure short timeouts reliably trigger an immediate vmexit.
9625 * hrtimer_start does not guarantee this. */
9626 if (preemption_timeout <= 1) {
9627 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9628 return;
9629 }
9630
9631 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9632 preemption_timeout *= 1000000;
9633 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9634 hrtimer_start(&vmx->nested.preemption_timer,
9635 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9636}
9637
56a20510
JM
9638static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
9639 struct vmcs12 *vmcs12)
9640{
9641 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9642 return 0;
9643
9644 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
9645 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
9646 return -EINVAL;
9647
9648 return 0;
9649}
9650
3af18d9c
WV
9651static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9652 struct vmcs12 *vmcs12)
9653{
3af18d9c
WV
9654 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9655 return 0;
9656
5fa99cbe 9657 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
3af18d9c
WV
9658 return -EINVAL;
9659
9660 return 0;
9661}
9662
9663/*
9664 * Merge L0's and L1's MSR bitmap, return false to indicate that
9665 * we do not use the hardware.
9666 */
9667static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9668 struct vmcs12 *vmcs12)
9669{
82f0dd4b 9670 int msr;
f2b93280 9671 struct page *page;
d048c098
RK
9672 unsigned long *msr_bitmap_l1;
9673 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
f2b93280 9674
d048c098 9675 /* This shortcut is ok because we support only x2APIC MSRs so far. */
f2b93280
WV
9676 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9677 return false;
9678
9679 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
05d8d346 9680 if (!page)
f2b93280 9681 return false;
d048c098 9682 msr_bitmap_l1 = (unsigned long *)kmap(page);
f2b93280 9683
d048c098
RK
9684 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9685
f2b93280 9686 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV
9687 if (nested_cpu_has_apic_reg_virt(vmcs12))
9688 for (msr = 0x800; msr <= 0x8ff; msr++)
9689 nested_vmx_disable_intercept_for_msr(
d048c098 9690 msr_bitmap_l1, msr_bitmap_l0,
82f0dd4b 9691 msr, MSR_TYPE_R);
d048c098
RK
9692
9693 nested_vmx_disable_intercept_for_msr(
9694 msr_bitmap_l1, msr_bitmap_l0,
f2b93280
WV
9695 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9696 MSR_TYPE_R | MSR_TYPE_W);
d048c098 9697
608406e2 9698 if (nested_cpu_has_vid(vmcs12)) {
608406e2 9699 nested_vmx_disable_intercept_for_msr(
d048c098 9700 msr_bitmap_l1, msr_bitmap_l0,
608406e2
WV
9701 APIC_BASE_MSR + (APIC_EOI >> 4),
9702 MSR_TYPE_W);
9703 nested_vmx_disable_intercept_for_msr(
d048c098 9704 msr_bitmap_l1, msr_bitmap_l0,
608406e2
WV
9705 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9706 MSR_TYPE_W);
9707 }
82f0dd4b 9708 }
f2b93280
WV
9709 kunmap(page);
9710 nested_release_page_clean(page);
9711
9712 return true;
9713}
9714
9715static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9716 struct vmcs12 *vmcs12)
9717{
82f0dd4b 9718 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 9719 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV
9720 !nested_cpu_has_vid(vmcs12) &&
9721 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV
9722 return 0;
9723
9724 /*
9725 * If virtualize x2apic mode is enabled,
9726 * virtualize apic access must be disabled.
9727 */
82f0dd4b
WV
9728 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9729 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV
9730 return -EINVAL;
9731
608406e2
WV
9732 /*
9733 * If virtual interrupt delivery is enabled,
9734 * we must exit on external interrupts.
9735 */
9736 if (nested_cpu_has_vid(vmcs12) &&
9737 !nested_exit_on_intr(vcpu))
9738 return -EINVAL;
9739
705699a1
WV
9740 /*
9741 * bits 15:8 should be zero in posted_intr_nv,
9742 * the descriptor address has been already checked
9743 * in nested_get_vmcs12_pages.
9744 */
9745 if (nested_cpu_has_posted_intr(vmcs12) &&
9746 (!nested_cpu_has_vid(vmcs12) ||
9747 !nested_exit_intr_ack_set(vcpu) ||
9748 vmcs12->posted_intr_nv & 0xff00))
9749 return -EINVAL;
9750
f2b93280
WV
9751 /* tpr shadow is needed by all apicv features. */
9752 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9753 return -EINVAL;
9754
9755 return 0;
3af18d9c
WV
9756}
9757
e9ac033e
EK
9758static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9759 unsigned long count_field,
92d71bc6 9760 unsigned long addr_field)
ff651cb6 9761{
92d71bc6 9762 int maxphyaddr;
e9ac033e
EK
9763 u64 count, addr;
9764
9765 if (vmcs12_read_any(vcpu, count_field, &count) ||
9766 vmcs12_read_any(vcpu, addr_field, &addr)) {
9767 WARN_ON(1);
9768 return -EINVAL;
9769 }
9770 if (count == 0)
9771 return 0;
92d71bc6 9772 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK
9773 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9774 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
bbe41b95 9775 pr_debug_ratelimited(
e9ac033e
EK
9776 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9777 addr_field, maxphyaddr, count, addr);
9778 return -EINVAL;
9779 }
9780 return 0;
9781}
9782
9783static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9784 struct vmcs12 *vmcs12)
9785{
e9ac033e
EK
9786 if (vmcs12->vm_exit_msr_load_count == 0 &&
9787 vmcs12->vm_exit_msr_store_count == 0 &&
9788 vmcs12->vm_entry_msr_load_count == 0)
9789 return 0; /* Fast path */
e9ac033e 9790 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9791 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9792 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9793 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9794 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9795 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK
9796 return -EINVAL;
9797 return 0;
9798}
9799
c5f983f6
BD
9800static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
9801 struct vmcs12 *vmcs12)
9802{
9803 u64 address = vmcs12->pml_address;
9804 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9805
9806 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
9807 if (!nested_cpu_has_ept(vmcs12) ||
9808 !IS_ALIGNED(address, 4096) ||
9809 address >> maxphyaddr)
9810 return -EINVAL;
9811 }
9812
9813 return 0;
9814}
9815
e9ac033e
EK
9816static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9817 struct vmx_msr_entry *e)
9818{
9819 /* x2APIC MSR accesses are not allowed */
8a9781f7 9820 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK
9821 return -EINVAL;
9822 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9823 e->index == MSR_IA32_UCODE_REV)
9824 return -EINVAL;
9825 if (e->reserved != 0)
ff651cb6
WV
9826 return -EINVAL;
9827 return 0;
9828}
9829
e9ac033e
EK
9830static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9831 struct vmx_msr_entry *e)
ff651cb6
WV
9832{
9833 if (e->index == MSR_FS_BASE ||
9834 e->index == MSR_GS_BASE ||
e9ac033e
EK
9835 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9836 nested_vmx_msr_check_common(vcpu, e))
9837 return -EINVAL;
9838 return 0;
9839}
9840
9841static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9842 struct vmx_msr_entry *e)
9843{
9844 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9845 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV
9846 return -EINVAL;
9847 return 0;
9848}
9849
9850/*
9851 * Load guest's/host's msr at nested entry/exit.
9852 * return 0 for success, entry index for failure.
9853 */
9854static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9855{
9856 u32 i;
9857 struct vmx_msr_entry e;
9858 struct msr_data msr;
9859
9860 msr.host_initiated = false;
9861 for (i = 0; i < count; i++) {
54bf36aa
PB
9862 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9863 &e, sizeof(e))) {
bbe41b95 9864 pr_debug_ratelimited(
e9ac033e
EK
9865 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9866 __func__, i, gpa + i * sizeof(e));
ff651cb6 9867 goto fail;
e9ac033e
EK
9868 }
9869 if (nested_vmx_load_msr_check(vcpu, &e)) {
bbe41b95 9870 pr_debug_ratelimited(
e9ac033e
EK
9871 "%s check failed (%u, 0x%x, 0x%x)\n",
9872 __func__, i, e.index, e.reserved);
9873 goto fail;
9874 }
ff651cb6
WV
9875 msr.index = e.index;
9876 msr.data = e.value;
e9ac033e 9877 if (kvm_set_msr(vcpu, &msr)) {
bbe41b95 9878 pr_debug_ratelimited(
e9ac033e
EK
9879 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9880 __func__, i, e.index, e.value);
ff651cb6 9881 goto fail;
e9ac033e 9882 }
ff651cb6
WV
9883 }
9884 return 0;
9885fail:
9886 return i + 1;
9887}
9888
9889static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9890{
9891 u32 i;
9892 struct vmx_msr_entry e;
9893
9894 for (i = 0; i < count; i++) {
609e36d3 9895 struct msr_data msr_info;
54bf36aa
PB
9896 if (kvm_vcpu_read_guest(vcpu,
9897 gpa + i * sizeof(e),
9898 &e, 2 * sizeof(u32))) {
bbe41b95 9899 pr_debug_ratelimited(
e9ac033e
EK
9900 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9901 __func__, i, gpa + i * sizeof(e));
ff651cb6 9902 return -EINVAL;
e9ac033e
EK
9903 }
9904 if (nested_vmx_store_msr_check(vcpu, &e)) {
bbe41b95 9905 pr_debug_ratelimited(
e9ac033e
EK
9906 "%s check failed (%u, 0x%x, 0x%x)\n",
9907 __func__, i, e.index, e.reserved);
ff651cb6 9908 return -EINVAL;
e9ac033e 9909 }
609e36d3
PB
9910 msr_info.host_initiated = false;
9911 msr_info.index = e.index;
9912 if (kvm_get_msr(vcpu, &msr_info)) {
bbe41b95 9913 pr_debug_ratelimited(
e9ac033e
EK
9914 "%s cannot read MSR (%u, 0x%x)\n",
9915 __func__, i, e.index);
9916 return -EINVAL;
9917 }
54bf36aa
PB
9918 if (kvm_vcpu_write_guest(vcpu,
9919 gpa + i * sizeof(e) +
9920 offsetof(struct vmx_msr_entry, value),
9921 &msr_info.data, sizeof(msr_info.data))) {
bbe41b95 9922 pr_debug_ratelimited(
e9ac033e 9923 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9924 __func__, i, e.index, msr_info.data);
e9ac033e
EK
9925 return -EINVAL;
9926 }
ff651cb6
WV
9927 }
9928 return 0;
9929}
9930
1dc35dac
LP
9931static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9932{
9933 unsigned long invalid_mask;
9934
9935 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9936 return (val & invalid_mask) == 0;
9937}
9938
9ed38ffa
LP
9939/*
9940 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9941 * emulating VM entry into a guest with EPT enabled.
9942 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9943 * is assigned to entry_failure_code on failure.
9944 */
9945static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
ca0bde28 9946 u32 *entry_failure_code)
9ed38ffa 9947{
9ed38ffa 9948 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
1dc35dac 9949 if (!nested_cr3_valid(vcpu, cr3)) {
9ed38ffa
LP
9950 *entry_failure_code = ENTRY_FAIL_DEFAULT;
9951 return 1;
9952 }
9953
9954 /*
9955 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9956 * must not be dereferenced.
9957 */
9958 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9959 !nested_ept) {
9960 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9961 *entry_failure_code = ENTRY_FAIL_PDPTE;
9962 return 1;
9963 }
9964 }
9965
9966 vcpu->arch.cr3 = cr3;
9967 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9968 }
9969
9970 kvm_mmu_reset_context(vcpu);
9971 return 0;
9972}
9973
fe3ef05c
NHE
9974/*
9975 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9976 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9977 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE
9978 * guest in a way that will both be appropriate to L1's requests, and our
9979 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9980 * function also has additional necessary side-effects, like setting various
9981 * vcpu->arch fields.
ee146c1c
LP
9982 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9983 * is assigned to entry_failure_code on failure.
fe3ef05c 9984 */
ee146c1c 9985static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
ca0bde28 9986 bool from_vmentry, u32 *entry_failure_code)
fe3ef05c
NHE
9987{
9988 struct vcpu_vmx *vmx = to_vmx(vcpu);
03efce6f 9989 u32 exec_control, vmcs12_exec_ctrl;
fe3ef05c
NHE
9990
9991 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9992 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9993 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9994 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9995 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9996 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9997 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9998 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9999 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10000 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10001 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10002 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10003 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10004 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10005 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10006 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10007 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10008 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10009 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10010 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10011 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10012 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10013 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10014 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10015 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10016 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10017 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10018 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10019 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10020 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10021 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10022 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10023 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10024 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10025 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10026 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10027
cf8b84f4
JM
10028 if (from_vmentry &&
10029 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
2996fca0
JK
10030 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10031 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10032 } else {
10033 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10034 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10035 }
cf8b84f4
JM
10036 if (from_vmentry) {
10037 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10038 vmcs12->vm_entry_intr_info_field);
10039 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10040 vmcs12->vm_entry_exception_error_code);
10041 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10042 vmcs12->vm_entry_instruction_len);
10043 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10044 vmcs12->guest_interruptibility_info);
10045 } else {
10046 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10047 }
fe3ef05c 10048 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 10049 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE
10050 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10051 vmcs12->guest_pending_dbg_exceptions);
10052 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10053 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10054
81dc01f7
WL
10055 if (nested_cpu_has_xsaves(vmcs12))
10056 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE
10057 vmcs_write64(VMCS_LINK_POINTER, -1ull);
10058
f4124500 10059 exec_control = vmcs12->pin_based_vm_exec_control;
9314006d
PB
10060
10061 /* Preemption timer setting is only taken from vmcs01. */
705699a1 10062 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9314006d
PB
10063 exec_control |= vmcs_config.pin_based_exec_ctrl;
10064 if (vmx->hv_deadline_tsc == -1)
10065 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
705699a1 10066
9314006d 10067 /* Posted interrupts setting is only taken from vmcs12. */
705699a1 10068 if (nested_cpu_has_posted_intr(vmcs12)) {
705699a1
WV
10069 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10070 vmx->nested.pi_pending = false;
06a5524f 10071 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
6beb7bd5 10072 } else {
705699a1 10073 exec_control &= ~PIN_BASED_POSTED_INTR;
6beb7bd5 10074 }
705699a1 10075
f4124500 10076 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 10077
f4124500
JK
10078 vmx->nested.preemption_timer_expired = false;
10079 if (nested_cpu_has_preemption_timer(vmcs12))
10080 vmx_start_preemption_timer(vcpu);
0238ea91 10081
fe3ef05c
NHE
10082 /*
10083 * Whether page-faults are trapped is determined by a combination of
10084 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10085 * If enable_ept, L0 doesn't care about page faults and we should
10086 * set all of these to L1's desires. However, if !enable_ept, L0 does
10087 * care about (at least some) page faults, and because it is not easy
10088 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10089 * to exit on each and every L2 page fault. This is done by setting
10090 * MASK=MATCH=0 and (see below) EB.PF=1.
10091 * Note that below we don't need special code to set EB.PF beyond the
10092 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10093 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10094 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10095 *
10096 * A problem with this approach (when !enable_ept) is that L1 may be
10097 * injected with more page faults than it asked for. This could have
10098 * caused problems, but in practice existing hypervisors don't care.
10099 * To fix this, we will need to emulate the PFEC checking (on the L1
10100 * page tables), using walk_addr(), when injecting PFs to L1.
10101 */
10102 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10103 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10104 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10105 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10106
10107 if (cpu_has_secondary_exec_ctrls()) {
f4124500 10108 exec_control = vmx_secondary_exec_control(vmx);
e2821620 10109
fe3ef05c 10110 /* Take the following fields only from vmcs12 */
696dfd95 10111 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 10112 SECONDARY_EXEC_RDTSCP |
696dfd95 10113 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
dfa169bb 10114 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c 10115 if (nested_cpu_has(vmcs12,
03efce6f
BD
10116 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10117 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10118 ~SECONDARY_EXEC_ENABLE_PML;
10119 exec_control |= vmcs12_exec_ctrl;
10120 }
fe3ef05c 10121
608406e2
WV
10122 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10123 vmcs_write64(EOI_EXIT_BITMAP0,
10124 vmcs12->eoi_exit_bitmap0);
10125 vmcs_write64(EOI_EXIT_BITMAP1,
10126 vmcs12->eoi_exit_bitmap1);
10127 vmcs_write64(EOI_EXIT_BITMAP2,
10128 vmcs12->eoi_exit_bitmap2);
10129 vmcs_write64(EOI_EXIT_BITMAP3,
10130 vmcs12->eoi_exit_bitmap3);
10131 vmcs_write16(GUEST_INTR_STATUS,
10132 vmcs12->guest_intr_status);
10133 }
10134
6beb7bd5
JM
10135 /*
10136 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10137 * nested_get_vmcs12_pages will either fix it up or
10138 * remove the VM execution control.
10139 */
10140 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10141 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10142
fe3ef05c
NHE
10143 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10144 }
10145
10146
10147 /*
10148 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10149 * Some constant fields are set here by vmx_set_constant_host_state().
10150 * Other fields are different per CPU, and will be set later when
10151 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10152 */
a547c6db 10153 vmx_set_constant_host_state(vmx);
fe3ef05c 10154
83bafef1
JM
10155 /*
10156 * Set the MSR load/store lists to match L0's settings.
10157 */
10158 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10159 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10160 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10161 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10162 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10163
fe3ef05c
NHE
10164 /*
10165 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10166 * entry, but only if the current (host) sp changed from the value
10167 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10168 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10169 * here we just force the write to happen on entry.
10170 */
10171 vmx->host_rsp = 0;
10172
10173 exec_control = vmx_exec_control(vmx); /* L0's desires */
10174 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10175 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10176 exec_control &= ~CPU_BASED_TPR_SHADOW;
10177 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d 10178
6beb7bd5
JM
10179 /*
10180 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10181 * nested_get_vmcs12_pages can't fix it up, the illegal value
10182 * will result in a VM entry failure.
10183 */
a7c0b07d 10184 if (exec_control & CPU_BASED_TPR_SHADOW) {
6beb7bd5 10185 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
a7c0b07d
WL
10186 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10187 }
10188
fe3ef05c 10189 /*
3af18d9c 10190 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE
10191 * Rather, exit every time.
10192 */
fe3ef05c
NHE
10193 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10194 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10195
10196 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10197
10198 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10199 * bitwise-or of what L1 wants to trap for L2, and what we want to
10200 * trap. Note that CR0.TS also needs updating - we do this later.
10201 */
10202 update_exception_bitmap(vcpu);
10203 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10204 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10205
8049d651
NHE
10206 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10207 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10208 * bits are further modified by vmx_set_efer() below.
10209 */
f4124500 10210 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE
10211
10212 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10213 * emulated by vmx_set_efer(), below.
10214 */
2961e876 10215 vm_entry_controls_init(vmx,
8049d651
NHE
10216 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10217 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE
10218 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10219
cf8b84f4
JM
10220 if (from_vmentry &&
10221 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
fe3ef05c 10222 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02 10223 vcpu->arch.pat = vmcs12->guest_ia32_pat;
cf8b84f4 10224 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 10225 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
cf8b84f4 10226 }
fe3ef05c
NHE
10227
10228 set_cr4_guest_host_mask(vmx);
10229
cf8b84f4
JM
10230 if (from_vmentry &&
10231 vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
36be0b9d
PB
10232 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10233
27fc51b2
NHE
10234 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10235 vmcs_write64(TSC_OFFSET,
ea26e4ec 10236 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
27fc51b2 10237 else
ea26e4ec 10238 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
c95ba92a
PF
10239 if (kvm_has_tsc_control)
10240 decache_tsc_multiplier(vmx);
fe3ef05c
NHE
10241
10242 if (enable_vpid) {
10243 /*
5c614b35
WL
10244 * There is no direct mapping between vpid02 and vpid12, the
10245 * vpid02 is per-vCPU for L0 and reused while the value of
10246 * vpid12 is changed w/ one invvpid during nested vmentry.
10247 * The vpid12 is allocated by L1 for L2, so it will not
10248 * influence global bitmap(for vpid01 and vpid02 allocation)
10249 * even if spawn a lot of nested vCPUs.
fe3ef05c 10250 */
5c614b35
WL
10251 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10252 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10253 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10254 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10255 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10256 }
10257 } else {
10258 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10259 vmx_flush_tlb(vcpu);
10260 }
10261
fe3ef05c
NHE
10262 }
10263
1fb883bb
LP
10264 if (enable_pml) {
10265 /*
10266 * Conceptually we want to copy the PML address and index from
10267 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10268 * since we always flush the log on each vmexit, this happens
10269 * to be equivalent to simply resetting the fields in vmcs02.
10270 */
10271 ASSERT(vmx->pml_pg);
10272 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10273 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10274 }
10275
155a97a3 10276 if (nested_cpu_has_ept(vmcs12)) {
ae1e2d10
PB
10277 if (nested_ept_init_mmu_context(vcpu)) {
10278 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10279 return 1;
10280 }
fb6c8198
JM
10281 } else if (nested_cpu_has2(vmcs12,
10282 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10283 vmx_flush_tlb_ept_only(vcpu);
155a97a3
NHE
10284 }
10285
fe3ef05c 10286 /*
bd7e5b08
PB
10287 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10288 * bits which we consider mandatory enabled.
fe3ef05c
NHE
10289 * The CR0_READ_SHADOW is what L2 should have expected to read given
10290 * the specifications by L1; It's not enough to take
10291 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10292 * have more bits than L1 expected.
10293 */
10294 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10295 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10296
10297 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10298 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10299
cf8b84f4
JM
10300 if (from_vmentry &&
10301 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
5a6a9748
DM
10302 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10303 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10304 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10305 else
10306 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10307 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10308 vmx_set_efer(vcpu, vcpu->arch.efer);
10309
9ed38ffa 10310 /* Shadow page tables on either EPT or shadow page tables. */
7ad658b6 10311 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
9ed38ffa
LP
10312 entry_failure_code))
10313 return 1;
7ca29de2 10314
feaf0c7d
GN
10315 if (!enable_ept)
10316 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10317
3633cfc3
NHE
10318 /*
10319 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10320 */
10321 if (enable_ept) {
10322 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10323 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10324 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10325 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10326 }
10327
fe3ef05c
NHE
10328 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10329 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
ee146c1c 10330 return 0;
fe3ef05c
NHE
10331}
10332
ca0bde28 10333static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
cd232ad0 10334{
cd232ad0 10335 struct vcpu_vmx *vmx = to_vmx(vcpu);
7c177938 10336
6dfacadd 10337 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
ca0bde28
JM
10338 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10339 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
26539bd0 10340
56a20510
JM
10341 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10342 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10343
ca0bde28
JM
10344 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10345 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
7c177938 10346
ca0bde28
JM
10347 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10348 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
f2b93280 10349
ca0bde28
JM
10350 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10351 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
e9ac033e 10352
c5f983f6
BD
10353 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10354 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10355
7c177938 10356 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
0115f9cb 10357 vmx->nested.nested_vmx_procbased_ctls_low,
b9c237bb 10358 vmx->nested.nested_vmx_procbased_ctls_high) ||
2e5b0bd9
JM
10359 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10360 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10361 vmx->nested.nested_vmx_secondary_ctls_low,
10362 vmx->nested.nested_vmx_secondary_ctls_high)) ||
7c177938 10363 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV
10364 vmx->nested.nested_vmx_pinbased_ctls_low,
10365 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 10366 !vmx_control_verify(vmcs12->vm_exit_controls,
0115f9cb 10367 vmx->nested.nested_vmx_exit_ctls_low,
b9c237bb 10368 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 10369 !vmx_control_verify(vmcs12->vm_entry_controls,
0115f9cb 10370 vmx->nested.nested_vmx_entry_ctls_low,
b9c237bb 10371 vmx->nested.nested_vmx_entry_ctls_high))
ca0bde28 10372 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
7c177938 10373
c7c2c709
JM
10374 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10375 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10376
3899152c 10377 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
1dc35dac 10378 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
ca0bde28
JM
10379 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10380 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10381
10382 return 0;
10383}
10384
10385static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10386 u32 *exit_qual)
10387{
10388 bool ia32e;
10389
10390 *exit_qual = ENTRY_FAIL_DEFAULT;
7c177938 10391
3899152c 10392 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
ca0bde28 10393 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
b428018a 10394 return 1;
ca0bde28
JM
10395
10396 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10397 vmcs12->vmcs_link_pointer != -1ull) {
10398 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
b428018a 10399 return 1;
7c177938
NHE
10400 }
10401
384bb783 10402 /*
cb0c8cda 10403 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK
10404 * are performed on the field for the IA32_EFER MSR:
10405 * - Bits reserved in the IA32_EFER MSR must be 0.
10406 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10407 * the IA-32e mode guest VM-exit control. It must also be identical
10408 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10409 * CR0.PG) is 1.
10410 */
ca0bde28
JM
10411 if (to_vmx(vcpu)->nested.nested_run_pending &&
10412 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
384bb783
JK
10413 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10414 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10415 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10416 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
ca0bde28 10417 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
b428018a 10418 return 1;
384bb783
JK
10419 }
10420
10421 /*
10422 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10423 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10424 * the values of the LMA and LME bits in the field must each be that of
10425 * the host address-space size VM-exit control.
10426 */
10427 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10428 ia32e = (vmcs12->vm_exit_controls &
10429 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10430 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10431 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
ca0bde28 10432 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
b428018a 10433 return 1;
ca0bde28
JM
10434 }
10435
10436 return 0;
10437}
10438
858e25c0
JM
10439static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10440{
10441 struct vcpu_vmx *vmx = to_vmx(vcpu);
10442 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10443 struct loaded_vmcs *vmcs02;
858e25c0
JM
10444 u32 msr_entry_idx;
10445 u32 exit_qual;
10446
10447 vmcs02 = nested_get_current_vmcs02(vmx);
10448 if (!vmcs02)
10449 return -ENOMEM;
10450
10451 enter_guest_mode(vcpu);
10452
10453 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10454 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10455
1279a6b1 10456 vmx_switch_vmcs(vcpu, vmcs02);
858e25c0
JM
10457 vmx_segment_cache_clear(vmx);
10458
10459 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10460 leave_guest_mode(vcpu);
1279a6b1 10461 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
858e25c0
JM
10462 nested_vmx_entry_failure(vcpu, vmcs12,
10463 EXIT_REASON_INVALID_STATE, exit_qual);
10464 return 1;
10465 }
10466
10467 nested_get_vmcs12_pages(vcpu, vmcs12);
10468
10469 msr_entry_idx = nested_vmx_load_msr(vcpu,
10470 vmcs12->vm_entry_msr_load_addr,
10471 vmcs12->vm_entry_msr_load_count);
10472 if (msr_entry_idx) {
10473 leave_guest_mode(vcpu);
1279a6b1 10474 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
858e25c0
JM
10475 nested_vmx_entry_failure(vcpu, vmcs12,
10476 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10477 return 1;
10478 }
10479
858e25c0
JM
10480 /*
10481 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10482 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10483 * returned as far as L1 is concerned. It will only return (and set
10484 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10485 */
10486 return 0;
10487}
10488
ca0bde28
JM
10489/*
10490 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10491 * for running an L2 nested guest.
10492 */
10493static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10494{
10495 struct vmcs12 *vmcs12;
10496 struct vcpu_vmx *vmx = to_vmx(vcpu);
b3f1dfb6 10497 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
ca0bde28
JM
10498 u32 exit_qual;
10499 int ret;
10500
10501 if (!nested_vmx_check_permission(vcpu))
10502 return 1;
10503
10504 if (!nested_vmx_check_vmcs12(vcpu))
10505 goto out;
10506
10507 vmcs12 = get_vmcs12(vcpu);
10508
10509 if (enable_shadow_vmcs)
10510 copy_shadow_to_vmcs12(vmx);
10511
10512 /*
10513 * The nested entry process starts with enforcing various prerequisites
10514 * on vmcs12 as required by the Intel SDM, and act appropriately when
10515 * they fail: As the SDM explains, some conditions should cause the
10516 * instruction to fail, while others will cause the instruction to seem
10517 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10518 * To speed up the normal (success) code path, we should avoid checking
10519 * for misconfigurations which will anyway be caught by the processor
10520 * when using the merged vmcs02.
10521 */
b3f1dfb6
JM
10522 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
10523 nested_vmx_failValid(vcpu,
10524 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
10525 goto out;
10526 }
10527
ca0bde28
JM
10528 if (vmcs12->launch_state == launch) {
10529 nested_vmx_failValid(vcpu,
10530 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10531 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10532 goto out;
10533 }
10534
10535 ret = check_vmentry_prereqs(vcpu, vmcs12);
10536 if (ret) {
10537 nested_vmx_failValid(vcpu, ret);
10538 goto out;
10539 }
10540
10541 /*
10542 * After this point, the trap flag no longer triggers a singlestep trap
10543 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10544 * This is not 100% correct; for performance reasons, we delegate most
10545 * of the checks on host state to the processor. If those fail,
10546 * the singlestep trap is missed.
10547 */
10548 skip_emulated_instruction(vcpu);
10549
10550 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10551 if (ret) {
10552 nested_vmx_entry_failure(vcpu, vmcs12,
10553 EXIT_REASON_INVALID_STATE, exit_qual);
10554 return 1;
384bb783
JK
10555 }
10556
7c177938
NHE
10557 /*
10558 * We're finally done with prerequisite checking, and can start with
10559 * the nested entry.
10560 */
10561
858e25c0
JM
10562 ret = enter_vmx_non_root_mode(vcpu, true);
10563 if (ret)
10564 return ret;
ff651cb6 10565
6dfacadd 10566 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 10567 return kvm_vcpu_halt(vcpu);
6dfacadd 10568
7af40ad3
JK
10569 vmx->nested.nested_run_pending = 1;
10570
cd232ad0 10571 return 1;
eb277562
KH
10572
10573out:
6affcbed 10574 return kvm_skip_emulated_instruction(vcpu);
cd232ad0
NHE
10575}
10576
4704d0be
NHE
10577/*
10578 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10579 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10580 * This function returns the new value we should put in vmcs12.guest_cr0.
10581 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10582 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10583 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10584 * didn't trap the bit, because if L1 did, so would L0).
10585 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10586 * been modified by L2, and L1 knows it. So just leave the old value of
10587 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10588 * isn't relevant, because if L0 traps this bit it can set it to anything.
10589 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10590 * changed these bits, and therefore they need to be updated, but L0
10591 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10592 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10593 */
10594static inline unsigned long
10595vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10596{
10597 return
10598 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10599 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10600 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10601 vcpu->arch.cr0_guest_owned_bits));
10602}
10603
10604static inline unsigned long
10605vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10606{
10607 return
10608 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10609 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10610 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10611 vcpu->arch.cr4_guest_owned_bits));
10612}
10613
5f3d5799
JK
10614static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10615 struct vmcs12 *vmcs12)
10616{
10617 u32 idt_vectoring;
10618 unsigned int nr;
10619
851eb667 10620 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK
10621 nr = vcpu->arch.exception.nr;
10622 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10623
10624 if (kvm_exception_is_soft(nr)) {
10625 vmcs12->vm_exit_instruction_len =
10626 vcpu->arch.event_exit_inst_len;
10627 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10628 } else
10629 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10630
10631 if (vcpu->arch.exception.has_error_code) {
10632 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10633 vmcs12->idt_vectoring_error_code =
10634 vcpu->arch.exception.error_code;
10635 }
10636
10637 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 10638 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK
10639 vmcs12->idt_vectoring_info_field =
10640 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10641 } else if (vcpu->arch.interrupt.pending) {
10642 nr = vcpu->arch.interrupt.nr;
10643 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10644
10645 if (vcpu->arch.interrupt.soft) {
10646 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10647 vmcs12->vm_entry_instruction_len =
10648 vcpu->arch.event_exit_inst_len;
10649 } else
10650 idt_vectoring |= INTR_TYPE_EXT_INTR;
10651
10652 vmcs12->idt_vectoring_info_field = idt_vectoring;
10653 }
10654}
10655
b6b8a145
JK
10656static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10657{
10658 struct vcpu_vmx *vmx = to_vmx(vcpu);
10659
acc9ab60
WL
10660 if (vcpu->arch.exception.pending ||
10661 vcpu->arch.nmi_injected ||
10662 vcpu->arch.interrupt.pending)
10663 return -EBUSY;
10664
f4124500
JK
10665 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10666 vmx->nested.preemption_timer_expired) {
10667 if (vmx->nested.nested_run_pending)
10668 return -EBUSY;
10669 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10670 return 0;
10671 }
10672
b6b8a145 10673 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
acc9ab60 10674 if (vmx->nested.nested_run_pending)
b6b8a145
JK
10675 return -EBUSY;
10676 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10677 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10678 INTR_INFO_VALID_MASK, 0);
10679 /*
10680 * The NMI-triggered VM exit counts as injection:
10681 * clear this one and block further NMIs.
10682 */
10683 vcpu->arch.nmi_pending = 0;
10684 vmx_set_nmi_mask(vcpu, true);
10685 return 0;
10686 }
10687
10688 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10689 nested_exit_on_intr(vcpu)) {
10690 if (vmx->nested.nested_run_pending)
10691 return -EBUSY;
10692 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 10693 return 0;
b6b8a145
JK
10694 }
10695
6342c50a
DH
10696 vmx_complete_nested_posted_interrupt(vcpu);
10697 return 0;
b6b8a145
JK
10698}
10699
f4124500
JK
10700static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10701{
10702 ktime_t remaining =
10703 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10704 u64 value;
10705
10706 if (ktime_to_ns(remaining) <= 0)
10707 return 0;
10708
10709 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10710 do_div(value, 1000000);
10711 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10712}
10713
4704d0be 10714/*
cf8b84f4
JM
10715 * Update the guest state fields of vmcs12 to reflect changes that
10716 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10717 * VM-entry controls is also updated, since this is really a guest
10718 * state bit.)
4704d0be 10719 */
cf8b84f4 10720static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be 10721{
4704d0be
NHE
10722 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10723 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10724
4704d0be
NHE
10725 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10726 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10727 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10728
10729 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10730 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10731 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10732 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10733 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10734 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10735 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10736 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10737 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10738 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10739 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10740 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10741 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10742 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10743 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10744 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10745 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10746 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10747 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10748 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10749 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10750 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10751 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10752 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10753 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10754 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10755 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10756 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10757 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10758 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10759 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10760 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10761 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10762 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10763 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10764 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10765
4704d0be
NHE
10766 vmcs12->guest_interruptibility_info =
10767 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10768 vmcs12->guest_pending_dbg_exceptions =
10769 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK
10770 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10771 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10772 else
10773 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 10774
f4124500
JK
10775 if (nested_cpu_has_preemption_timer(vmcs12)) {
10776 if (vmcs12->vm_exit_controls &
10777 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10778 vmcs12->vmx_preemption_timer_value =
10779 vmx_get_preemption_timer_value(vcpu);
10780 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10781 }
7854cbca 10782
3633cfc3
NHE
10783 /*
10784 * In some cases (usually, nested EPT), L2 is allowed to change its
10785 * own CR3 without exiting. If it has changed it, we must keep it.
10786 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10787 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10788 *
10789 * Additionally, restore L2's PDPTR to vmcs12.
10790 */
10791 if (enable_ept) {
f3531054 10792 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
3633cfc3
NHE
10793 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10794 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10795 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10796 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10797 }
10798
d281e13b 10799 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
119a9c01 10800
608406e2
WV
10801 if (nested_cpu_has_vid(vmcs12))
10802 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10803
c18911a2
JK
10804 vmcs12->vm_entry_controls =
10805 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 10806 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 10807
2996fca0
JK
10808 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10809 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10810 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10811 }
10812
4704d0be
NHE
10813 /* TODO: These cannot have changed unless we have MSR bitmaps and
10814 * the relevant bit asks not to trap the change */
b8c07d55 10815 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 10816 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK
10817 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10818 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE
10819 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10820 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10821 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
a87036ad 10822 if (kvm_mpx_supported())
36be0b9d 10823 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
cf8b84f4
JM
10824}
10825
10826/*
10827 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10828 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10829 * and this function updates it to reflect the changes to the guest state while
10830 * L2 was running (and perhaps made some exits which were handled directly by L0
10831 * without going back to L1), and to reflect the exit reason.
10832 * Note that we do not have to copy here all VMCS fields, just those that
10833 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10834 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10835 * which already writes to vmcs12 directly.
10836 */
10837static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10838 u32 exit_reason, u32 exit_intr_info,
10839 unsigned long exit_qualification)
10840{
10841 /* update guest state fields: */
10842 sync_vmcs12(vcpu, vmcs12);
4704d0be
NHE
10843
10844 /* update exit information fields: */
10845
533558bc
JK
10846 vmcs12->vm_exit_reason = exit_reason;
10847 vmcs12->exit_qualification = exit_qualification;
4704d0be 10848
533558bc 10849 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK
10850 if ((vmcs12->vm_exit_intr_info &
10851 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10852 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10853 vmcs12->vm_exit_intr_error_code =
10854 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 10855 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE
10856 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10857 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10858
5f3d5799 10859 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7cdc2d62
JM
10860 vmcs12->launch_state = 1;
10861
5f3d5799
JK
10862 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10863 * instead of reading the real value. */
4704d0be 10864 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK
10865
10866 /*
10867 * Transfer the event that L0 or L1 may wanted to inject into
10868 * L2 to IDT_VECTORING_INFO_FIELD.
10869 */
10870 vmcs12_save_pending_event(vcpu, vmcs12);
10871 }
10872
10873 /*
10874 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10875 * preserved above and would only end up incorrectly in L1.
10876 */
10877 vcpu->arch.nmi_injected = false;
10878 kvm_clear_exception_queue(vcpu);
10879 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE
10880}
10881
10882/*
10883 * A part of what we need to when the nested L2 guest exits and we want to
10884 * run its L1 parent, is to reset L1's guest state to the host state specified
10885 * in vmcs12.
10886 * This function is to be called not only on normal nested exit, but also on
10887 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10888 * Failures During or After Loading Guest State").
10889 * This function should be called when the active VMCS is L1's (vmcs01).
10890 */
733568f9
JK
10891static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10892 struct vmcs12 *vmcs12)
4704d0be 10893{
21feb4eb 10894 struct kvm_segment seg;
ca0bde28 10895 u32 entry_failure_code;
21feb4eb 10896
4704d0be
NHE
10897 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10898 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10899 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE
10900 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10901 else
10902 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10903 vmx_set_efer(vcpu, vcpu->arch.efer);
10904
10905 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10906 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10907 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE
10908 /*
10909 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
bd7e5b08
PB
10910 * actually changed, because vmx_set_cr0 refers to efer set above.
10911 *
10912 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10913 * (KVM doesn't change it);
4704d0be 10914 */
bd7e5b08 10915 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
9e3e4dbf 10916 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be 10917
bd7e5b08 10918 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
4704d0be
NHE
10919 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10920 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10921
29bf08f1 10922 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10923
1dc35dac
LP
10924 /*
10925 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10926 * couldn't have changed.
10927 */
10928 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10929 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
4704d0be 10930
feaf0c7d
GN
10931 if (!enable_ept)
10932 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10933
4704d0be
NHE
10934 if (enable_vpid) {
10935 /*
10936 * Trivially support vpid by letting L2s share their parent
10937 * L1's vpid. TODO: move to a more elaborate solution, giving
10938 * each L2 its own vpid and exposing the vpid feature to L1.
10939 */
10940 vmx_flush_tlb(vcpu);
10941 }
06a5524f
WV
10942 /* Restore posted intr vector. */
10943 if (nested_cpu_has_posted_intr(vmcs12))
10944 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4704d0be
NHE
10945
10946 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10947 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10948 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10949 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10950 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10951
36be0b9d
PB
10952 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10953 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10954 vmcs_write64(GUEST_BNDCFGS, 0);
10955
44811c02 10956 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10957 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK
10958 vcpu->arch.pat = vmcs12->host_ia32_pat;
10959 }
4704d0be
NHE
10960 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10961 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10962 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10963
21feb4eb
ACL
10964 /* Set L1 segment info according to Intel SDM
10965 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10966 seg = (struct kvm_segment) {
10967 .base = 0,
10968 .limit = 0xFFFFFFFF,
10969 .selector = vmcs12->host_cs_selector,
10970 .type = 11,
10971 .present = 1,
10972 .s = 1,
10973 .g = 1
10974 };
10975 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10976 seg.l = 1;
10977 else
10978 seg.db = 1;
10979 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10980 seg = (struct kvm_segment) {
10981 .base = 0,
10982 .limit = 0xFFFFFFFF,
10983 .type = 3,
10984 .present = 1,
10985 .s = 1,
10986 .db = 1,
10987 .g = 1
10988 };
10989 seg.selector = vmcs12->host_ds_selector;
10990 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10991 seg.selector = vmcs12->host_es_selector;
10992 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10993 seg.selector = vmcs12->host_ss_selector;
10994 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10995 seg.selector = vmcs12->host_fs_selector;
10996 seg.base = vmcs12->host_fs_base;
10997 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10998 seg.selector = vmcs12->host_gs_selector;
10999 seg.base = vmcs12->host_gs_base;
11000 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11001 seg = (struct kvm_segment) {
205befd9 11002 .base = vmcs12->host_tr_base,
21feb4eb
ACL
11003 .limit = 0x67,
11004 .selector = vmcs12->host_tr_selector,
11005 .type = 11,
11006 .present = 1
11007 };
11008 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11009
503cd0c5
JK
11010 kvm_set_dr(vcpu, 7, 0x400);
11011 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 11012
3af18d9c
WV
11013 if (cpu_has_vmx_msr_bitmap())
11014 vmx_set_msr_bitmap(vcpu);
11015
ff651cb6
WV
11016 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11017 vmcs12->vm_exit_msr_load_count))
11018 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE
11019}
11020
11021/*
11022 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11023 * and modify vmcs12 to make it see what it would expect to see there if
11024 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11025 */
533558bc
JK
11026static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11027 u32 exit_intr_info,
11028 unsigned long exit_qualification)
4704d0be
NHE
11029{
11030 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 11031 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
cf3215d9 11032 u32 vm_inst_error = 0;
4704d0be 11033
5f3d5799
JK
11034 /* trying to cancel vmlaunch/vmresume is a bug */
11035 WARN_ON_ONCE(vmx->nested.nested_run_pending);
11036
4704d0be 11037 leave_guest_mode(vcpu);
533558bc
JK
11038 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11039 exit_qualification);
4704d0be 11040
ff651cb6
WV
11041 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11042 vmcs12->vm_exit_msr_store_count))
11043 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11044
cf3215d9
JM
11045 if (unlikely(vmx->fail))
11046 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11047
1279a6b1 11048 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
f3380ca5 11049
77b0f5d6
BD
11050 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11051 && nested_exit_intr_ack_set(vcpu)) {
11052 int irq = kvm_cpu_get_interrupt(vcpu);
11053 WARN_ON(irq < 0);
11054 vmcs12->vm_exit_intr_info = irq |
11055 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11056 }
11057
542060ea
JK
11058 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11059 vmcs12->exit_qualification,
11060 vmcs12->idt_vectoring_info_field,
11061 vmcs12->vm_exit_intr_info,
11062 vmcs12->vm_exit_intr_error_code,
11063 KVM_ISA_VMX);
4704d0be 11064
8391ce44
PB
11065 vm_entry_controls_reset_shadow(vmx);
11066 vm_exit_controls_reset_shadow(vmx);
36c3cc42
JK
11067 vmx_segment_cache_clear(vmx);
11068
4704d0be
NHE
11069 /* if no vmcs02 cache requested, remove the one we used */
11070 if (VMCS02_POOL_SIZE == 0)
11071 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11072
11073 load_vmcs12_host_state(vcpu, vmcs12);
11074
9314006d 11075 /* Update any VMCS fields that might have changed while L2 ran */
83bafef1
JM
11076 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11077 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
ea26e4ec 11078 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
9314006d
PB
11079 if (vmx->hv_deadline_tsc == -1)
11080 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11081 PIN_BASED_VMX_PREEMPTION_TIMER);
11082 else
11083 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11084 PIN_BASED_VMX_PREEMPTION_TIMER);
c95ba92a
PF
11085 if (kvm_has_tsc_control)
11086 decache_tsc_multiplier(vmx);
4704d0be 11087
dccbfcf5
RK
11088 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11089 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11090 vmx_set_virtual_x2apic_mode(vcpu,
11091 vcpu->arch.apic_base & X2APIC_ENABLE);
fb6c8198
JM
11092 } else if (!nested_cpu_has_ept(vmcs12) &&
11093 nested_cpu_has2(vmcs12,
11094 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11095 vmx_flush_tlb_ept_only(vcpu);
dccbfcf5 11096 }
4704d0be
NHE
11097
11098 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11099 vmx->host_rsp = 0;
11100
11101 /* Unpin physical memory we referred to in vmcs02 */
11102 if (vmx->nested.apic_access_page) {
11103 nested_release_page(vmx->nested.apic_access_page);
48d89b92 11104 vmx->nested.apic_access_page = NULL;
4704d0be 11105 }
a7c0b07d
WL
11106 if (vmx->nested.virtual_apic_page) {
11107 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 11108 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 11109 }
705699a1
WV
11110 if (vmx->nested.pi_desc_page) {
11111 kunmap(vmx->nested.pi_desc_page);
11112 nested_release_page(vmx->nested.pi_desc_page);
11113 vmx->nested.pi_desc_page = NULL;
11114 vmx->nested.pi_desc = NULL;
11115 }
4704d0be 11116
38b99173
TC
11117 /*
11118 * We are now running in L2, mmu_notifier will force to reload the
11119 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11120 */
c83b6d15 11121 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
38b99173 11122
4704d0be
NHE
11123 /*
11124 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11125 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11126 * success or failure flag accordingly.
11127 */
11128 if (unlikely(vmx->fail)) {
11129 vmx->fail = 0;
cf3215d9 11130 nested_vmx_failValid(vcpu, vm_inst_error);
4704d0be
NHE
11131 } else
11132 nested_vmx_succeed(vcpu);
012f83cb
AG
11133 if (enable_shadow_vmcs)
11134 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK
11135
11136 /* in case we halted in L2 */
11137 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE
11138}
11139
42124925
JK
11140/*
11141 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11142 */
11143static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11144{
2f707d97
WL
11145 if (is_guest_mode(vcpu)) {
11146 to_vmx(vcpu)->nested.nested_run_pending = 0;
533558bc 11147 nested_vmx_vmexit(vcpu, -1, 0, 0);
2f707d97 11148 }
42124925
JK
11149 free_nested(to_vmx(vcpu));
11150}
11151
7c177938
NHE
11152/*
11153 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11154 * 23.7 "VM-entry failures during or after loading guest state" (this also
11155 * lists the acceptable exit-reason and exit-qualification parameters).
11156 * It should only be called before L2 actually succeeded to run, and when
11157 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11158 */
11159static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11160 struct vmcs12 *vmcs12,
11161 u32 reason, unsigned long qualification)
11162{
11163 load_vmcs12_host_state(vcpu, vmcs12);
11164 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11165 vmcs12->exit_qualification = qualification;
11166 nested_vmx_succeed(vcpu);
012f83cb
AG
11167 if (enable_shadow_vmcs)
11168 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE
11169}
11170
8a76d7f2
JR
11171static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11172 struct x86_instruction_info *info,
11173 enum x86_intercept_stage stage)
11174{
11175 return X86EMUL_CONTINUE;
11176}
11177
64672c95
YJ
11178#ifdef CONFIG_X86_64
11179/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11180static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11181 u64 divisor, u64 *result)
11182{
11183 u64 low = a << shift, high = a >> (64 - shift);
11184
11185 /* To avoid the overflow on divq */
11186 if (high >= divisor)
11187 return 1;
11188
11189 /* Low hold the result, high hold rem which is discarded */
11190 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11191 "rm" (divisor), "0" (low), "1" (high));
11192 *result = low;
11193
11194 return 0;
11195}
11196
11197static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11198{
11199 struct vcpu_vmx *vmx = to_vmx(vcpu);
9175d2e9
PB
11200 u64 tscl = rdtsc();
11201 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11202 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
64672c95
YJ
11203
11204 /* Convert to host delta tsc if tsc scaling is enabled */
11205 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11206 u64_shl_div_u64(delta_tsc,
11207 kvm_tsc_scaling_ratio_frac_bits,
11208 vcpu->arch.tsc_scaling_ratio,
11209 &delta_tsc))
11210 return -ERANGE;
11211
11212 /*
11213 * If the delta tsc can't fit in the 32 bit after the multi shift,
11214 * we can't use the preemption timer.
11215 * It's possible that it fits on later vmentries, but checking
11216 * on every vmentry is costly so we just use an hrtimer.
11217 */
11218 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11219 return -ERANGE;
11220
11221 vmx->hv_deadline_tsc = tscl + delta_tsc;
11222 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11223 PIN_BASED_VMX_PREEMPTION_TIMER);
c8533544
WL
11224
11225 return delta_tsc == 0;
64672c95
YJ
11226}
11227
11228static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11229{
11230 struct vcpu_vmx *vmx = to_vmx(vcpu);
11231 vmx->hv_deadline_tsc = -1;
11232 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11233 PIN_BASED_VMX_PREEMPTION_TIMER);
11234}
11235#endif
11236
48d89b92 11237static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 11238{
b4a2d31d
RK
11239 if (ple_gap)
11240 shrink_ple_window(vcpu);
ae97a3b8
RK
11241}
11242
843e4330
KH
11243static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11244 struct kvm_memory_slot *slot)
11245{
11246 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11247 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11248}
11249
11250static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11251 struct kvm_memory_slot *slot)
11252{
11253 kvm_mmu_slot_set_dirty(kvm, slot);
11254}
11255
11256static void vmx_flush_log_dirty(struct kvm *kvm)
11257{
11258 kvm_flush_pml_buffers(kvm);
11259}
11260
c5f983f6
BD
11261static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11262{
11263 struct vmcs12 *vmcs12;
11264 struct vcpu_vmx *vmx = to_vmx(vcpu);
11265 gpa_t gpa;
11266 struct page *page = NULL;
11267 u64 *pml_address;
11268
11269 if (is_guest_mode(vcpu)) {
11270 WARN_ON_ONCE(vmx->nested.pml_full);
11271
11272 /*
11273 * Check if PML is enabled for the nested guest.
11274 * Whether eptp bit 6 is set is already checked
11275 * as part of A/D emulation.
11276 */
11277 vmcs12 = get_vmcs12(vcpu);
11278 if (!nested_cpu_has_pml(vmcs12))
11279 return 0;
11280
4769886b 11281 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD
11282 vmx->nested.pml_full = true;
11283 return 1;
11284 }
11285
11286 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11287
11288 page = nested_get_page(vcpu, vmcs12->pml_address);
11289 if (!page)
11290 return 0;
11291
11292 pml_address = kmap(page);
11293 pml_address[vmcs12->guest_pml_index--] = gpa;
11294 kunmap(page);
11295 nested_release_page_clean(page);
11296 }
11297
11298 return 0;
11299}
11300
843e4330
KH
11301static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11302 struct kvm_memory_slot *memslot,
11303 gfn_t offset, unsigned long mask)
11304{
11305 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11306}
11307
bf9f6ac8
FW
11308/*
11309 * This routine does the following things for vCPU which is going
11310 * to be blocked if VT-d PI is enabled.
11311 * - Store the vCPU to the wakeup list, so when interrupts happen
11312 * we can find the right vCPU to wake up.
11313 * - Change the Posted-interrupt descriptor as below:
11314 * 'NDST' <-- vcpu->pre_pcpu
11315 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11316 * - If 'ON' is set during this process, which means at least one
11317 * interrupt is posted for this vCPU, we cannot block it, in
11318 * this case, return 1, otherwise, return 0.
11319 *
11320 */
bc22512b 11321static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8
FW
11322{
11323 unsigned long flags;
11324 unsigned int dest;
11325 struct pi_desc old, new;
11326 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11327
11328 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
11329 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11330 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW
11331 return 0;
11332
11333 vcpu->pre_pcpu = vcpu->cpu;
11334 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11335 vcpu->pre_pcpu), flags);
11336 list_add_tail(&vcpu->blocked_vcpu_list,
11337 &per_cpu(blocked_vcpu_on_cpu,
11338 vcpu->pre_pcpu));
11339 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11340 vcpu->pre_pcpu), flags);
11341
11342 do {
11343 old.control = new.control = pi_desc->control;
11344
11345 /*
11346 * We should not block the vCPU if
11347 * an interrupt is posted for it.
11348 */
11349 if (pi_test_on(pi_desc) == 1) {
11350 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11351 vcpu->pre_pcpu), flags);
11352 list_del(&vcpu->blocked_vcpu_list);
11353 spin_unlock_irqrestore(
11354 &per_cpu(blocked_vcpu_on_cpu_lock,
11355 vcpu->pre_pcpu), flags);
11356 vcpu->pre_pcpu = -1;
11357
11358 return 1;
11359 }
11360
11361 WARN((pi_desc->sn == 1),
11362 "Warning: SN field of posted-interrupts "
11363 "is set before blocking\n");
11364
11365 /*
11366 * Since vCPU can be preempted during this process,
11367 * vcpu->cpu could be different with pre_pcpu, we
11368 * need to set pre_pcpu as the destination of wakeup
11369 * notification event, then we can find the right vCPU
11370 * to wakeup in wakeup handler if interrupts happen
11371 * when the vCPU is in blocked state.
11372 */
11373 dest = cpu_physical_id(vcpu->pre_pcpu);
11374
11375 if (x2apic_enabled())
11376 new.ndst = dest;
11377 else
11378 new.ndst = (dest << 8) & 0xFF00;
11379
11380 /* set 'NV' to 'wakeup vector' */
11381 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11382 } while (cmpxchg(&pi_desc->control, old.control,
11383 new.control) != old.control);
11384
11385 return 0;
11386}
11387
bc22512b
YJ
11388static int vmx_pre_block(struct kvm_vcpu *vcpu)
11389{
11390 if (pi_pre_block(vcpu))
11391 return 1;
11392
64672c95
YJ
11393 if (kvm_lapic_hv_timer_in_use(vcpu))
11394 kvm_lapic_switch_to_sw_timer(vcpu);
11395
bc22512b
YJ
11396 return 0;
11397}
11398
11399static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8
FW
11400{
11401 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11402 struct pi_desc old, new;
11403 unsigned int dest;
11404 unsigned long flags;
11405
11406 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
11407 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11408 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW
11409 return;
11410
11411 do {
11412 old.control = new.control = pi_desc->control;
11413
11414 dest = cpu_physical_id(vcpu->cpu);
11415
11416 if (x2apic_enabled())
11417 new.ndst = dest;
11418 else
11419 new.ndst = (dest << 8) & 0xFF00;
11420
11421 /* Allow posting non-urgent interrupts */
11422 new.sn = 0;
11423
11424 /* set 'NV' to 'notification vector' */
11425 new.nv = POSTED_INTR_VECTOR;
11426 } while (cmpxchg(&pi_desc->control, old.control,
11427 new.control) != old.control);
11428
11429 if(vcpu->pre_pcpu != -1) {
11430 spin_lock_irqsave(
11431 &per_cpu(blocked_vcpu_on_cpu_lock,
11432 vcpu->pre_pcpu), flags);
11433 list_del(&vcpu->blocked_vcpu_list);
11434 spin_unlock_irqrestore(
11435 &per_cpu(blocked_vcpu_on_cpu_lock,
11436 vcpu->pre_pcpu), flags);
11437 vcpu->pre_pcpu = -1;
11438 }
11439}
11440
bc22512b
YJ
11441static void vmx_post_block(struct kvm_vcpu *vcpu)
11442{
64672c95
YJ
11443 if (kvm_x86_ops->set_hv_timer)
11444 kvm_lapic_switch_to_hv_timer(vcpu);
11445
bc22512b
YJ
11446 pi_post_block(vcpu);
11447}
11448
efc64404
FW
11449/*
11450 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11451 *
11452 * @kvm: kvm
11453 * @host_irq: host irq of the interrupt
11454 * @guest_irq: gsi of the interrupt
11455 * @set: set or unset PI
11456 * returns 0 on success, < 0 on failure
11457 */
11458static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11459 uint32_t guest_irq, bool set)
11460{
11461 struct kvm_kernel_irq_routing_entry *e;
11462 struct kvm_irq_routing_table *irq_rt;
11463 struct kvm_lapic_irq irq;
11464 struct kvm_vcpu *vcpu;
11465 struct vcpu_data vcpu_info;
11466 int idx, ret = -EINVAL;
11467
11468 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ
11469 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11470 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW
11471 return 0;
11472
11473 idx = srcu_read_lock(&kvm->irq_srcu);
11474 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11475 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11476
11477 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11478 if (e->type != KVM_IRQ_ROUTING_MSI)
11479 continue;
11480 /*
11481 * VT-d PI cannot support posting multicast/broadcast
11482 * interrupts to a vCPU, we still use interrupt remapping
11483 * for these kind of interrupts.
11484 *
11485 * For lowest-priority interrupts, we only support
11486 * those with single CPU as the destination, e.g. user
11487 * configures the interrupts via /proc/irq or uses
11488 * irqbalance to make the interrupts single-CPU.
11489 *
11490 * We will support full lowest-priority interrupt later.
11491 */
11492
37131313 11493 kvm_set_msi_irq(kvm, e, &irq);
23a1c257
FW
11494 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11495 /*
11496 * Make sure the IRTE is in remapped mode if
11497 * we don't handle it in posted mode.
11498 */
11499 ret = irq_set_vcpu_affinity(host_irq, NULL);
11500 if (ret < 0) {
11501 printk(KERN_INFO
11502 "failed to back to remapped mode, irq: %u\n",
11503 host_irq);
11504 goto out;
11505 }
11506
efc64404 11507 continue;
23a1c257 11508 }
efc64404
FW
11509
11510 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11511 vcpu_info.vector = irq.vector;
11512
b6ce9780 11513 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
efc64404
FW
11514 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11515
11516 if (set)
11517 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11518 else {
11519 /* suppress notification event before unposting */
11520 pi_set_sn(vcpu_to_pi_desc(vcpu));
11521 ret = irq_set_vcpu_affinity(host_irq, NULL);
11522 pi_clear_sn(vcpu_to_pi_desc(vcpu));
11523 }
11524
11525 if (ret < 0) {
11526 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11527 __func__);
11528 goto out;
11529 }
11530 }
11531
11532 ret = 0;
11533out:
11534 srcu_read_unlock(&kvm->irq_srcu, idx);
11535 return ret;
11536}
11537
c45dcc71
AR
11538static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11539{
11540 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11541 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11542 FEATURE_CONTROL_LMCE;
11543 else
11544 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11545 ~FEATURE_CONTROL_LMCE;
11546}
11547
404f6aac 11548static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK
11549 .cpu_has_kvm_support = cpu_has_kvm_support,
11550 .disabled_by_bios = vmx_disabled_by_bios,
11551 .hardware_setup = hardware_setup,
11552 .hardware_unsetup = hardware_unsetup,
002c7f7c 11553 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK
11554 .hardware_enable = hardware_enable,
11555 .hardware_disable = hardware_disable,
04547156 11556 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 11557 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK
11558
11559 .vcpu_create = vmx_create_vcpu,
11560 .vcpu_free = vmx_free_vcpu,
04d2cc77 11561 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 11562
04d2cc77 11563 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK
11564 .vcpu_load = vmx_vcpu_load,
11565 .vcpu_put = vmx_vcpu_put,
11566
a96036b8 11567 .update_bp_intercept = update_exception_bitmap,
6aa8b732
AK
11568 .get_msr = vmx_get_msr,
11569 .set_msr = vmx_set_msr,
11570 .get_segment_base = vmx_get_segment_base,
11571 .get_segment = vmx_get_segment,
11572 .set_segment = vmx_set_segment,
2e4d2653 11573 .get_cpl = vmx_get_cpl,
6aa8b732 11574 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 11575 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 11576 .decache_cr3 = vmx_decache_cr3,
25c4c276 11577 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 11578 .set_cr0 = vmx_set_cr0,
6aa8b732
AK
11579 .set_cr3 = vmx_set_cr3,
11580 .set_cr4 = vmx_set_cr4,
6aa8b732 11581 .set_efer = vmx_set_efer,
6aa8b732
AK
11582 .get_idt = vmx_get_idt,
11583 .set_idt = vmx_set_idt,
11584 .get_gdt = vmx_get_gdt,
11585 .set_gdt = vmx_set_gdt,
73aaf249
JK
11586 .get_dr6 = vmx_get_dr6,
11587 .set_dr6 = vmx_set_dr6,
020df079 11588 .set_dr7 = vmx_set_dr7,
81908bf4 11589 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 11590 .cache_reg = vmx_cache_reg,
6aa8b732
AK
11591 .get_rflags = vmx_get_rflags,
11592 .set_rflags = vmx_set_rflags,
be94f6b7
HH
11593
11594 .get_pkru = vmx_get_pkru,
11595
6aa8b732 11596 .tlb_flush = vmx_flush_tlb,
6aa8b732 11597
6aa8b732 11598 .run = vmx_vcpu_run,
6062d012 11599 .handle_exit = vmx_handle_exit,
6aa8b732 11600 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC
11601 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11602 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 11603 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 11604 .set_irq = vmx_inject_irq,
95ba8273 11605 .set_nmi = vmx_inject_nmi,
298101da 11606 .queue_exception = vmx_queue_exception,
b463a6f7 11607 .cancel_injection = vmx_cancel_injection,
78646121 11608 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 11609 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK
11610 .get_nmi_mask = vmx_get_nmi_mask,
11611 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN
11612 .enable_nmi_window = enable_nmi_window,
11613 .enable_irq_window = enable_irq_window,
11614 .update_cr8_intercept = update_cr8_intercept,
8d14695f 11615 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 11616 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb
AS
11617 .get_enable_apicv = vmx_get_enable_apicv,
11618 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 11619 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 11620 .apicv_post_state_restore = vmx_apicv_post_state_restore,
c7c9c56c
YZ
11621 .hwapic_irr_update = vmx_hwapic_irr_update,
11622 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ
11623 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11624 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 11625
cbc94022 11626 .set_tss_addr = vmx_set_tss_addr,
67253af5 11627 .get_tdp_level = get_ept_level,
4b12f0de 11628 .get_mt_mask = vmx_get_mt_mask,
229456fc 11629
586f9607 11630 .get_exit_info = vmx_get_exit_info,
586f9607 11631
17cc3935 11632 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY
11633
11634 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY
11635
11636 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 11637 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR
11638
11639 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY
11640
11641 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA
11642
11643 .write_tsc_offset = vmx_write_tsc_offset,
1c97f0a0
JR
11644
11645 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR
11646
11647 .check_intercept = vmx_check_intercept,
a547c6db 11648 .handle_external_intr = vmx_handle_external_intr,
da8999d3 11649 .mpx_supported = vmx_mpx_supported,
55412b2e 11650 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK
11651
11652 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK
11653
11654 .sched_in = vmx_sched_in,
843e4330
KH
11655
11656 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11657 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11658 .flush_log_dirty = vmx_flush_log_dirty,
11659 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 11660 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 11661
bf9f6ac8
FW
11662 .pre_block = vmx_pre_block,
11663 .post_block = vmx_post_block,
11664
25462f7f 11665 .pmu_ops = &intel_pmu_ops,
efc64404
FW
11666
11667 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ
11668
11669#ifdef CONFIG_X86_64
11670 .set_hv_timer = vmx_set_hv_timer,
11671 .cancel_hv_timer = vmx_cancel_hv_timer,
11672#endif
c45dcc71
AR
11673
11674 .setup_mce = vmx_setup_mce,
6aa8b732
AK
11675};
11676
11677static int __init vmx_init(void)
11678{
34a1cd60
TC
11679 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11680 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 11681 if (r)
34a1cd60 11682 return r;
25c5f225 11683
2965faa5 11684#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY
11685 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11686 crash_vmclear_local_loaded_vmcss);
11687#endif
11688
fdef3ad1 11689 return 0;
6aa8b732
AK
11690}
11691
11692static void __exit vmx_exit(void)
11693{
2965faa5 11694#ifdef CONFIG_KEXEC_CORE
3b63a43f 11695 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY
11696 synchronize_rcu();
11697#endif
11698
cb498ea2 11699 kvm_exit();
6aa8b732
AK
11700}
11701
11702module_init(vmx_init)
11703module_exit(vmx_exit)