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CommitLineData
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
d62caabb 22#include "lapic.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732 25#include <linux/module.h>
9d8f549d 26#include <linux/kernel.h>
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27#include <linux/mm.h>
28#include <linux/highmem.h>
e8edc6e0 29#include <linux/sched.h>
c7addb90 30#include <linux/moduleparam.h>
e9bda3b3 31#include <linux/mod_devicetable.h>
af658dca 32#include <linux/trace_events.h>
5a0e3ad6 33#include <linux/slab.h>
cafd6659 34#include <linux/tboot.h>
f4124500 35#include <linux/hrtimer.h>
c207aee4 36#include <linux/frame.h>
5fdbf976 37#include "kvm_cache_regs.h"
35920a35 38#include "x86.h"
e495606d 39
28b835d6 40#include <asm/cpu.h>
6aa8b732 41#include <asm/io.h>
3b3be0d1 42#include <asm/desc.h>
13673a90 43#include <asm/vmx.h>
6210e37b 44#include <asm/virtext.h>
a0861c02 45#include <asm/mce.h>
952f07ec 46#include <asm/fpu/internal.h>
d7cd9796 47#include <asm/perf_event.h>
81908bf4 48#include <asm/debugreg.h>
8f536b76 49#include <asm/kexec.h>
dab2087d 50#include <asm/apic.h>
efc64404 51#include <asm/irq_remapping.h>
d6e41f11 52#include <asm/mmu_context.h>
6aa8b732 53
229456fc 54#include "trace.h"
25462f7f 55#include "pmu.h"
229456fc 56
4ecac3fd 57#define __ex(x) __kvm_handle_fault_on_reboot(x)
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58#define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 60
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61MODULE_AUTHOR("Qumranet");
62MODULE_LICENSE("GPL");
63
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64static const struct x86_cpu_id vmx_cpu_id[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX),
66 {}
67};
68MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
69
476bc001 70static bool __read_mostly enable_vpid = 1;
736caefe 71module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 72
476bc001 73static bool __read_mostly flexpriority_enabled = 1;
736caefe 74module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 75
476bc001 76static bool __read_mostly enable_ept = 1;
736caefe 77module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 78
476bc001 79static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
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80module_param_named(unrestricted_guest,
81 enable_unrestricted_guest, bool, S_IRUGO);
82
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83static bool __read_mostly enable_ept_ad_bits = 1;
84module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
85
a27685c3 86static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 87module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 88
476bc001 89static bool __read_mostly fasteoi = 1;
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90module_param(fasteoi, bool, S_IRUGO);
91
5a71785d 92static bool __read_mostly enable_apicv = 1;
01e439be 93module_param(enable_apicv, bool, S_IRUGO);
83d4c286 94
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95static bool __read_mostly enable_shadow_vmcs = 1;
96module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
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97/*
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
101 */
476bc001 102static bool __read_mostly nested = 0;
801d3424
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103module_param(nested, bool, S_IRUGO);
104
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105static u64 __read_mostly host_xss;
106
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107static bool __read_mostly enable_pml = 1;
108module_param_named(pml, enable_pml, bool, S_IRUGO);
109
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110#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
111
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112/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
113static int __read_mostly cpu_preemption_timer_multi;
114static bool __read_mostly enable_preemption_timer = 1;
115#ifdef CONFIG_X86_64
116module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
117#endif
118
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119#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
120#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
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121#define KVM_VM_CR0_ALWAYS_ON \
122 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
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123#define KVM_CR4_GUEST_OWNED_BITS \
124 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 125 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 126
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127#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
128#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
129
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130#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
131
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132#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
133
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134/*
135 * Hyper-V requires all of these, so mark them as supported even though
136 * they are just treated the same as all-context.
137 */
138#define VMX_VPID_EXTENT_SUPPORTED_MASK \
139 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
140 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
143
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144/*
145 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
146 * ple_gap: upper bound on the amount of time between two successive
147 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 148 * According to test, this time is usually smaller than 128 cycles.
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149 * ple_window: upper bound on the amount of time a guest is allowed to execute
150 * in a PAUSE loop. Tests indicate that most spinlocks are held for
151 * less than 2^12 cycles
152 * Time is measured based on a counter that runs at the same rate as the TSC,
153 * refer SDM volume 3b section 21.6.13 & 22.1.3.
154 */
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155#define KVM_VMX_DEFAULT_PLE_GAP 128
156#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
157#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
158#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
159#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
160 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
161
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162static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
163module_param(ple_gap, int, S_IRUGO);
164
165static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
166module_param(ple_window, int, S_IRUGO);
167
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168/* Default doubles per-vcpu window every exit. */
169static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
170module_param(ple_window_grow, int, S_IRUGO);
171
172/* Default resets per-vcpu window every exit to ple_window. */
173static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
174module_param(ple_window_shrink, int, S_IRUGO);
175
176/* Default is to compute the maximum so we can never overflow. */
177static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
178static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179module_param(ple_window_max, int, S_IRUGO);
180
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181extern const ulong vmx_return;
182
8bf00a52 183#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 184#define VMCS02_POOL_SIZE 1
61d2ef2c 185
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186struct vmcs {
187 u32 revision_id;
188 u32 abort;
189 char data[0];
190};
191
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192/*
193 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
194 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
195 * loaded on this CPU (so we can clear them if the CPU goes down).
196 */
197struct loaded_vmcs {
198 struct vmcs *vmcs;
355f4fb1 199 struct vmcs *shadow_vmcs;
d462b819 200 int cpu;
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201 bool launched;
202 bool nmi_known_unmasked;
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203 struct list_head loaded_vmcss_on_cpu_link;
204};
205
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206struct shared_msr_entry {
207 unsigned index;
208 u64 data;
d5696725 209 u64 mask;
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210};
211
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212/*
213 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
214 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
215 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
216 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
217 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
218 * More than one of these structures may exist, if L1 runs multiple L2 guests.
219 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
220 * underlying hardware which will be used to run L2.
221 * This structure is packed to ensure that its layout is identical across
222 * machines (necessary for live migration).
223 * If there are changes in this struct, VMCS12_REVISION must be changed.
224 */
22bd0358 225typedef u64 natural_width;
a9d30f33
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226struct __packed vmcs12 {
227 /* According to the Intel spec, a VMCS region must start with the
228 * following two fields. Then follow implementation-specific data.
229 */
230 u32 revision_id;
231 u32 abort;
22bd0358 232
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233 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
234 u32 padding[7]; /* room for future expansion */
235
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236 u64 io_bitmap_a;
237 u64 io_bitmap_b;
238 u64 msr_bitmap;
239 u64 vm_exit_msr_store_addr;
240 u64 vm_exit_msr_load_addr;
241 u64 vm_entry_msr_load_addr;
242 u64 tsc_offset;
243 u64 virtual_apic_page_addr;
244 u64 apic_access_addr;
705699a1 245 u64 posted_intr_desc_addr;
22bd0358 246 u64 ept_pointer;
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247 u64 eoi_exit_bitmap0;
248 u64 eoi_exit_bitmap1;
249 u64 eoi_exit_bitmap2;
250 u64 eoi_exit_bitmap3;
81dc01f7 251 u64 xss_exit_bitmap;
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252 u64 guest_physical_address;
253 u64 vmcs_link_pointer;
c5f983f6 254 u64 pml_address;
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255 u64 guest_ia32_debugctl;
256 u64 guest_ia32_pat;
257 u64 guest_ia32_efer;
258 u64 guest_ia32_perf_global_ctrl;
259 u64 guest_pdptr0;
260 u64 guest_pdptr1;
261 u64 guest_pdptr2;
262 u64 guest_pdptr3;
36be0b9d 263 u64 guest_bndcfgs;
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264 u64 host_ia32_pat;
265 u64 host_ia32_efer;
266 u64 host_ia32_perf_global_ctrl;
267 u64 padding64[8]; /* room for future expansion */
268 /*
269 * To allow migration of L1 (complete with its L2 guests) between
270 * machines of different natural widths (32 or 64 bit), we cannot have
271 * unsigned long fields with no explict size. We use u64 (aliased
272 * natural_width) instead. Luckily, x86 is little-endian.
273 */
274 natural_width cr0_guest_host_mask;
275 natural_width cr4_guest_host_mask;
276 natural_width cr0_read_shadow;
277 natural_width cr4_read_shadow;
278 natural_width cr3_target_value0;
279 natural_width cr3_target_value1;
280 natural_width cr3_target_value2;
281 natural_width cr3_target_value3;
282 natural_width exit_qualification;
283 natural_width guest_linear_address;
284 natural_width guest_cr0;
285 natural_width guest_cr3;
286 natural_width guest_cr4;
287 natural_width guest_es_base;
288 natural_width guest_cs_base;
289 natural_width guest_ss_base;
290 natural_width guest_ds_base;
291 natural_width guest_fs_base;
292 natural_width guest_gs_base;
293 natural_width guest_ldtr_base;
294 natural_width guest_tr_base;
295 natural_width guest_gdtr_base;
296 natural_width guest_idtr_base;
297 natural_width guest_dr7;
298 natural_width guest_rsp;
299 natural_width guest_rip;
300 natural_width guest_rflags;
301 natural_width guest_pending_dbg_exceptions;
302 natural_width guest_sysenter_esp;
303 natural_width guest_sysenter_eip;
304 natural_width host_cr0;
305 natural_width host_cr3;
306 natural_width host_cr4;
307 natural_width host_fs_base;
308 natural_width host_gs_base;
309 natural_width host_tr_base;
310 natural_width host_gdtr_base;
311 natural_width host_idtr_base;
312 natural_width host_ia32_sysenter_esp;
313 natural_width host_ia32_sysenter_eip;
314 natural_width host_rsp;
315 natural_width host_rip;
316 natural_width paddingl[8]; /* room for future expansion */
317 u32 pin_based_vm_exec_control;
318 u32 cpu_based_vm_exec_control;
319 u32 exception_bitmap;
320 u32 page_fault_error_code_mask;
321 u32 page_fault_error_code_match;
322 u32 cr3_target_count;
323 u32 vm_exit_controls;
324 u32 vm_exit_msr_store_count;
325 u32 vm_exit_msr_load_count;
326 u32 vm_entry_controls;
327 u32 vm_entry_msr_load_count;
328 u32 vm_entry_intr_info_field;
329 u32 vm_entry_exception_error_code;
330 u32 vm_entry_instruction_len;
331 u32 tpr_threshold;
332 u32 secondary_vm_exec_control;
333 u32 vm_instruction_error;
334 u32 vm_exit_reason;
335 u32 vm_exit_intr_info;
336 u32 vm_exit_intr_error_code;
337 u32 idt_vectoring_info_field;
338 u32 idt_vectoring_error_code;
339 u32 vm_exit_instruction_len;
340 u32 vmx_instruction_info;
341 u32 guest_es_limit;
342 u32 guest_cs_limit;
343 u32 guest_ss_limit;
344 u32 guest_ds_limit;
345 u32 guest_fs_limit;
346 u32 guest_gs_limit;
347 u32 guest_ldtr_limit;
348 u32 guest_tr_limit;
349 u32 guest_gdtr_limit;
350 u32 guest_idtr_limit;
351 u32 guest_es_ar_bytes;
352 u32 guest_cs_ar_bytes;
353 u32 guest_ss_ar_bytes;
354 u32 guest_ds_ar_bytes;
355 u32 guest_fs_ar_bytes;
356 u32 guest_gs_ar_bytes;
357 u32 guest_ldtr_ar_bytes;
358 u32 guest_tr_ar_bytes;
359 u32 guest_interruptibility_info;
360 u32 guest_activity_state;
361 u32 guest_sysenter_cs;
362 u32 host_ia32_sysenter_cs;
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363 u32 vmx_preemption_timer_value;
364 u32 padding32[7]; /* room for future expansion */
22bd0358 365 u16 virtual_processor_id;
705699a1 366 u16 posted_intr_nv;
22bd0358
NHE
367 u16 guest_es_selector;
368 u16 guest_cs_selector;
369 u16 guest_ss_selector;
370 u16 guest_ds_selector;
371 u16 guest_fs_selector;
372 u16 guest_gs_selector;
373 u16 guest_ldtr_selector;
374 u16 guest_tr_selector;
608406e2 375 u16 guest_intr_status;
c5f983f6 376 u16 guest_pml_index;
22bd0358
NHE
377 u16 host_es_selector;
378 u16 host_cs_selector;
379 u16 host_ss_selector;
380 u16 host_ds_selector;
381 u16 host_fs_selector;
382 u16 host_gs_selector;
383 u16 host_tr_selector;
a9d30f33
NHE
384};
385
386/*
387 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
388 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
389 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
390 */
391#define VMCS12_REVISION 0x11e57ed0
392
393/*
394 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
395 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
396 * current implementation, 4K are reserved to avoid future complications.
397 */
398#define VMCS12_SIZE 0x1000
399
ff2f6fe9
NHE
400/* Used to remember the last vmcs02 used for some recently used vmcs12s */
401struct vmcs02_list {
402 struct list_head list;
403 gpa_t vmptr;
404 struct loaded_vmcs vmcs02;
405};
406
ec378aee
NHE
407/*
408 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
409 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
410 */
411struct nested_vmx {
412 /* Has the level1 guest done vmxon? */
413 bool vmxon;
3573e22c 414 gpa_t vmxon_ptr;
c5f983f6 415 bool pml_full;
a9d30f33
NHE
416
417 /* The guest-physical address of the current VMCS L1 keeps for L2 */
418 gpa_t current_vmptr;
419 /* The host-usable pointer to the above */
420 struct page *current_vmcs12_page;
421 struct vmcs12 *current_vmcs12;
4f2777bc
DM
422 /*
423 * Cache of the guest's VMCS, existing outside of guest memory.
424 * Loaded from guest memory during VMPTRLD. Flushed to guest
425 * memory during VMXOFF, VMCLEAR, VMPTRLD.
426 */
427 struct vmcs12 *cached_vmcs12;
012f83cb
AG
428 /*
429 * Indicates if the shadow vmcs must be updated with the
430 * data hold by vmcs12
431 */
432 bool sync_shadow_vmcs;
ff2f6fe9
NHE
433
434 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
435 struct list_head vmcs02_pool;
436 int vmcs02_num;
dccbfcf5 437 bool change_vmcs01_virtual_x2apic_mode;
644d711a
NHE
438 /* L2 must run next, and mustn't decide to exit to L1. */
439 bool nested_run_pending;
fe3ef05c
NHE
440 /*
441 * Guest pages referred to in vmcs02 with host-physical pointers, so
442 * we must keep them pinned while L2 runs.
443 */
444 struct page *apic_access_page;
a7c0b07d 445 struct page *virtual_apic_page;
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WV
446 struct page *pi_desc_page;
447 struct pi_desc *pi_desc;
448 bool pi_pending;
449 u16 posted_intr_nv;
f4124500 450
d048c098
RK
451 unsigned long *msr_bitmap;
452
f4124500
JK
453 struct hrtimer preemption_timer;
454 bool preemption_timer_expired;
2996fca0
JK
455
456 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
457 u64 vmcs01_debugctl;
b9c237bb 458
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WL
459 u16 vpid02;
460 u16 last_vpid;
461
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DM
462 /*
463 * We only store the "true" versions of the VMX capability MSRs. We
464 * generate the "non-true" versions by setting the must-be-1 bits
465 * according to the SDM.
466 */
b9c237bb
WV
467 u32 nested_vmx_procbased_ctls_low;
468 u32 nested_vmx_procbased_ctls_high;
b9c237bb
WV
469 u32 nested_vmx_secondary_ctls_low;
470 u32 nested_vmx_secondary_ctls_high;
471 u32 nested_vmx_pinbased_ctls_low;
472 u32 nested_vmx_pinbased_ctls_high;
473 u32 nested_vmx_exit_ctls_low;
474 u32 nested_vmx_exit_ctls_high;
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WV
475 u32 nested_vmx_entry_ctls_low;
476 u32 nested_vmx_entry_ctls_high;
b9c237bb
WV
477 u32 nested_vmx_misc_low;
478 u32 nested_vmx_misc_high;
479 u32 nested_vmx_ept_caps;
99b83ac8 480 u32 nested_vmx_vpid_caps;
62cc6b9d
DM
481 u64 nested_vmx_basic;
482 u64 nested_vmx_cr0_fixed0;
483 u64 nested_vmx_cr0_fixed1;
484 u64 nested_vmx_cr4_fixed0;
485 u64 nested_vmx_cr4_fixed1;
486 u64 nested_vmx_vmcs_enum;
ec378aee
NHE
487};
488
01e439be 489#define POSTED_INTR_ON 0
ebbfc765
FW
490#define POSTED_INTR_SN 1
491
01e439be
YZ
492/* Posted-Interrupt Descriptor */
493struct pi_desc {
494 u32 pir[8]; /* Posted interrupt requested */
6ef1522f
FW
495 union {
496 struct {
497 /* bit 256 - Outstanding Notification */
498 u16 on : 1,
499 /* bit 257 - Suppress Notification */
500 sn : 1,
501 /* bit 271:258 - Reserved */
502 rsvd_1 : 14;
503 /* bit 279:272 - Notification Vector */
504 u8 nv;
505 /* bit 287:280 - Reserved */
506 u8 rsvd_2;
507 /* bit 319:288 - Notification Destination */
508 u32 ndst;
509 };
510 u64 control;
511 };
512 u32 rsvd[6];
01e439be
YZ
513} __aligned(64);
514
a20ed54d
YZ
515static bool pi_test_and_set_on(struct pi_desc *pi_desc)
516{
517 return test_and_set_bit(POSTED_INTR_ON,
518 (unsigned long *)&pi_desc->control);
519}
520
521static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
522{
523 return test_and_clear_bit(POSTED_INTR_ON,
524 (unsigned long *)&pi_desc->control);
525}
526
527static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
528{
529 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
530}
531
ebbfc765
FW
532static inline void pi_clear_sn(struct pi_desc *pi_desc)
533{
534 return clear_bit(POSTED_INTR_SN,
535 (unsigned long *)&pi_desc->control);
536}
537
538static inline void pi_set_sn(struct pi_desc *pi_desc)
539{
540 return set_bit(POSTED_INTR_SN,
541 (unsigned long *)&pi_desc->control);
542}
543
ad361091
PB
544static inline void pi_clear_on(struct pi_desc *pi_desc)
545{
546 clear_bit(POSTED_INTR_ON,
547 (unsigned long *)&pi_desc->control);
548}
549
ebbfc765
FW
550static inline int pi_test_on(struct pi_desc *pi_desc)
551{
552 return test_bit(POSTED_INTR_ON,
553 (unsigned long *)&pi_desc->control);
554}
555
556static inline int pi_test_sn(struct pi_desc *pi_desc)
557{
558 return test_bit(POSTED_INTR_SN,
559 (unsigned long *)&pi_desc->control);
560}
561
a2fa3e9f 562struct vcpu_vmx {
fb3f0f51 563 struct kvm_vcpu vcpu;
313dbd49 564 unsigned long host_rsp;
29bd8a78 565 u8 fail;
51aa01d1 566 u32 exit_intr_info;
1155f76a 567 u32 idt_vectoring_info;
6de12732 568 ulong rflags;
26bb0981 569 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH
570 int nmsrs;
571 int save_nmsrs;
a547c6db 572 unsigned long host_idt_base;
a2fa3e9f 573#ifdef CONFIG_X86_64
44ea2b17
AK
574 u64 msr_host_kernel_gs_base;
575 u64 msr_guest_kernel_gs_base;
a2fa3e9f 576#endif
2961e876
GN
577 u32 vm_entry_controls_shadow;
578 u32 vm_exit_controls_shadow;
d462b819
NHE
579 /*
580 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
581 * non-nested (L1) guest, it always points to vmcs01. For a nested
582 * guest (L2), it points to a different VMCS.
583 */
584 struct loaded_vmcs vmcs01;
585 struct loaded_vmcs *loaded_vmcs;
586 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK
587 struct msr_autoload {
588 unsigned nr;
589 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
590 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
591 } msr_autoload;
a2fa3e9f
GH
592 struct {
593 int loaded;
594 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK
595#ifdef CONFIG_X86_64
596 u16 ds_sel, es_sel;
597#endif
152d3f2f
LV
598 int gs_ldt_reload_needed;
599 int fs_reload_needed;
da8999d3 600 u64 msr_host_bndcfgs;
d6e41f11 601 unsigned long vmcs_host_cr3; /* May not match real cr3 */
d974baa3 602 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 603 } host_state;
9c8cba37 604 struct {
7ffd92c5 605 int vm86_active;
78ac8b47 606 ulong save_rflags;
f5f7b2fe
AK
607 struct kvm_segment segs[8];
608 } rmode;
609 struct {
610 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK
611 struct kvm_save_segment {
612 u16 selector;
613 unsigned long base;
614 u32 limit;
615 u32 ar;
f5f7b2fe 616 } seg[8];
2fb92db1 617 } segment_cache;
2384d2b3 618 int vpid;
04fa4d32 619 bool emulation_required;
3b86cd99 620
a0861c02 621 u32 exit_reason;
4e47c7a6 622
01e439be
YZ
623 /* Posted interrupt descriptor */
624 struct pi_desc pi_desc;
625
ec378aee
NHE
626 /* Support for a guest hypervisor (nested VMX) */
627 struct nested_vmx nested;
a7653ecd
RK
628
629 /* Dynamic PLE window. */
630 int ple_window;
631 bool ple_window_dirty;
843e4330
KH
632
633 /* Support for PML */
634#define PML_ENTITY_NUM 512
635 struct page *pml_pg;
2680d6da 636
64672c95
YJ
637 /* apic deadline value in host tsc */
638 u64 hv_deadline_tsc;
639
2680d6da 640 u64 current_tsc_ratio;
1be0e61c
XG
641
642 bool guest_pkru_valid;
643 u32 guest_pkru;
644 u32 host_pkru;
3b84080b 645
37e4c997
HZ
646 /*
647 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
648 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
649 * in msr_ia32_feature_control_valid_bits.
650 */
3b84080b 651 u64 msr_ia32_feature_control;
37e4c997 652 u64 msr_ia32_feature_control_valid_bits;
a2fa3e9f
GH
653};
654
2fb92db1
AK
655enum segment_cache_field {
656 SEG_FIELD_SEL = 0,
657 SEG_FIELD_BASE = 1,
658 SEG_FIELD_LIMIT = 2,
659 SEG_FIELD_AR = 3,
660
661 SEG_FIELD_NR = 4
662};
663
a2fa3e9f
GH
664static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
665{
fb3f0f51 666 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH
667}
668
efc64404
FW
669static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
670{
671 return &(to_vmx(vcpu)->pi_desc);
672}
673
22bd0358
NHE
674#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
675#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
676#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
677 [number##_HIGH] = VMCS12_OFFSET(name)+4
678
4607c2d7 679
fe2b201b 680static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG
681 /*
682 * We do NOT shadow fields that are modified when L0
683 * traps and emulates any vmx instruction (e.g. VMPTRLD,
684 * VMXON...) executed by L1.
685 * For example, VM_INSTRUCTION_ERROR is read
686 * by L1 if a vmx instruction fails (part of the error path).
687 * Note the code assumes this logic. If for some reason
688 * we start shadowing these fields then we need to
689 * force a shadow sync when L0 emulates vmx instructions
690 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
691 * by nested_vmx_failValid)
692 */
693 VM_EXIT_REASON,
694 VM_EXIT_INTR_INFO,
695 VM_EXIT_INSTRUCTION_LEN,
696 IDT_VECTORING_INFO_FIELD,
697 IDT_VECTORING_ERROR_CODE,
698 VM_EXIT_INTR_ERROR_CODE,
699 EXIT_QUALIFICATION,
700 GUEST_LINEAR_ADDRESS,
701 GUEST_PHYSICAL_ADDRESS
702};
fe2b201b 703static int max_shadow_read_only_fields =
4607c2d7
AG
704 ARRAY_SIZE(shadow_read_only_fields);
705
fe2b201b 706static unsigned long shadow_read_write_fields[] = {
a7c0b07d 707 TPR_THRESHOLD,
4607c2d7
AG
708 GUEST_RIP,
709 GUEST_RSP,
710 GUEST_CR0,
711 GUEST_CR3,
712 GUEST_CR4,
713 GUEST_INTERRUPTIBILITY_INFO,
714 GUEST_RFLAGS,
715 GUEST_CS_SELECTOR,
716 GUEST_CS_AR_BYTES,
717 GUEST_CS_LIMIT,
718 GUEST_CS_BASE,
719 GUEST_ES_BASE,
36be0b9d 720 GUEST_BNDCFGS,
4607c2d7
AG
721 CR0_GUEST_HOST_MASK,
722 CR0_READ_SHADOW,
723 CR4_READ_SHADOW,
724 TSC_OFFSET,
725 EXCEPTION_BITMAP,
726 CPU_BASED_VM_EXEC_CONTROL,
727 VM_ENTRY_EXCEPTION_ERROR_CODE,
728 VM_ENTRY_INTR_INFO_FIELD,
729 VM_ENTRY_INSTRUCTION_LEN,
730 VM_ENTRY_EXCEPTION_ERROR_CODE,
731 HOST_FS_BASE,
732 HOST_GS_BASE,
733 HOST_FS_SELECTOR,
734 HOST_GS_SELECTOR
735};
fe2b201b 736static int max_shadow_read_write_fields =
4607c2d7
AG
737 ARRAY_SIZE(shadow_read_write_fields);
738
772e0318 739static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 740 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 741 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE
742 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
743 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
744 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
745 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
746 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
747 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
748 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
749 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 750 FIELD(GUEST_INTR_STATUS, guest_intr_status),
c5f983f6 751 FIELD(GUEST_PML_INDEX, guest_pml_index),
22bd0358
NHE
752 FIELD(HOST_ES_SELECTOR, host_es_selector),
753 FIELD(HOST_CS_SELECTOR, host_cs_selector),
754 FIELD(HOST_SS_SELECTOR, host_ss_selector),
755 FIELD(HOST_DS_SELECTOR, host_ds_selector),
756 FIELD(HOST_FS_SELECTOR, host_fs_selector),
757 FIELD(HOST_GS_SELECTOR, host_gs_selector),
758 FIELD(HOST_TR_SELECTOR, host_tr_selector),
759 FIELD64(IO_BITMAP_A, io_bitmap_a),
760 FIELD64(IO_BITMAP_B, io_bitmap_b),
761 FIELD64(MSR_BITMAP, msr_bitmap),
762 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
763 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
764 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
765 FIELD64(TSC_OFFSET, tsc_offset),
766 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
767 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 768 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 769 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV
770 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
771 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
772 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
773 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 774 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE
775 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
776 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
c5f983f6 777 FIELD64(PML_ADDRESS, pml_address),
22bd0358
NHE
778 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
779 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
780 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
781 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
782 FIELD64(GUEST_PDPTR0, guest_pdptr0),
783 FIELD64(GUEST_PDPTR1, guest_pdptr1),
784 FIELD64(GUEST_PDPTR2, guest_pdptr2),
785 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 786 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE
787 FIELD64(HOST_IA32_PAT, host_ia32_pat),
788 FIELD64(HOST_IA32_EFER, host_ia32_efer),
789 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
790 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
791 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
792 FIELD(EXCEPTION_BITMAP, exception_bitmap),
793 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
794 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
795 FIELD(CR3_TARGET_COUNT, cr3_target_count),
796 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
797 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
798 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
799 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
800 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
801 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
802 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
803 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
804 FIELD(TPR_THRESHOLD, tpr_threshold),
805 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
806 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
807 FIELD(VM_EXIT_REASON, vm_exit_reason),
808 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
809 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
810 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
811 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
812 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
813 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
814 FIELD(GUEST_ES_LIMIT, guest_es_limit),
815 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
816 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
817 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
818 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
819 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
820 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
821 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
822 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
823 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
824 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
825 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
826 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
827 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
828 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
829 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
830 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
831 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
832 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
833 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
834 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
835 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 836 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE
837 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
838 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
839 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
840 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
841 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
842 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
843 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
844 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
845 FIELD(EXIT_QUALIFICATION, exit_qualification),
846 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
847 FIELD(GUEST_CR0, guest_cr0),
848 FIELD(GUEST_CR3, guest_cr3),
849 FIELD(GUEST_CR4, guest_cr4),
850 FIELD(GUEST_ES_BASE, guest_es_base),
851 FIELD(GUEST_CS_BASE, guest_cs_base),
852 FIELD(GUEST_SS_BASE, guest_ss_base),
853 FIELD(GUEST_DS_BASE, guest_ds_base),
854 FIELD(GUEST_FS_BASE, guest_fs_base),
855 FIELD(GUEST_GS_BASE, guest_gs_base),
856 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
857 FIELD(GUEST_TR_BASE, guest_tr_base),
858 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
859 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
860 FIELD(GUEST_DR7, guest_dr7),
861 FIELD(GUEST_RSP, guest_rsp),
862 FIELD(GUEST_RIP, guest_rip),
863 FIELD(GUEST_RFLAGS, guest_rflags),
864 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
865 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
866 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
867 FIELD(HOST_CR0, host_cr0),
868 FIELD(HOST_CR3, host_cr3),
869 FIELD(HOST_CR4, host_cr4),
870 FIELD(HOST_FS_BASE, host_fs_base),
871 FIELD(HOST_GS_BASE, host_gs_base),
872 FIELD(HOST_TR_BASE, host_tr_base),
873 FIELD(HOST_GDTR_BASE, host_gdtr_base),
874 FIELD(HOST_IDTR_BASE, host_idtr_base),
875 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
876 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
877 FIELD(HOST_RSP, host_rsp),
878 FIELD(HOST_RIP, host_rip),
879};
22bd0358
NHE
880
881static inline short vmcs_field_to_offset(unsigned long field)
882{
a2ae9df7
PB
883 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
884
885 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
886 vmcs_field_to_offset_table[field] == 0)
887 return -ENOENT;
888
22bd0358
NHE
889 return vmcs_field_to_offset_table[field];
890}
891
a9d30f33
NHE
892static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
893{
4f2777bc 894 return to_vmx(vcpu)->nested.cached_vmcs12;
a9d30f33
NHE
895}
896
897static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
898{
54bf36aa 899 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 900 if (is_error_page(page))
a9d30f33 901 return NULL;
32cad84f 902
a9d30f33
NHE
903 return page;
904}
905
906static void nested_release_page(struct page *page)
907{
908 kvm_release_page_dirty(page);
909}
910
911static void nested_release_page_clean(struct page *page)
912{
913 kvm_release_page_clean(page);
914}
915
995f00a6 916static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
bfd0a56b 917static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
995f00a6 918static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
f53cd63c 919static bool vmx_xsaves_supported(void);
776e58ea 920static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW
921static void vmx_set_segment(struct kvm_vcpu *vcpu,
922 struct kvm_segment *var, int seg);
923static void vmx_get_segment(struct kvm_vcpu *vcpu,
924 struct kvm_segment *var, int seg);
d99e4152
GN
925static bool guest_state_valid(struct kvm_vcpu *vcpu);
926static u32 vmx_segment_access_rights(struct kvm_segment *var);
c3114420 927static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 928static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 929static int alloc_identity_pagetable(struct kvm *kvm);
b96fb439
PB
930static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
931static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
932static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
933 u16 error_code);
75880a01 934
6aa8b732
AK
935static DEFINE_PER_CPU(struct vmcs *, vmxarea);
936static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE
937/*
938 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
939 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
940 */
941static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 942
bf9f6ac8
FW
943/*
944 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
945 * can find which vCPU should be waken up.
946 */
947static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
948static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
949
23611332
RK
950enum {
951 VMX_IO_BITMAP_A,
952 VMX_IO_BITMAP_B,
953 VMX_MSR_BITMAP_LEGACY,
954 VMX_MSR_BITMAP_LONGMODE,
955 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
956 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
957 VMX_MSR_BITMAP_LEGACY_X2APIC,
958 VMX_MSR_BITMAP_LONGMODE_X2APIC,
959 VMX_VMREAD_BITMAP,
960 VMX_VMWRITE_BITMAP,
961 VMX_BITMAP_NR
962};
963
964static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
965
966#define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
967#define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
968#define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
969#define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
970#define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
971#define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
972#define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
973#define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
974#define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
975#define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
fdef3ad1 976
110312c8 977static bool cpu_has_load_ia32_efer;
8bf00a52 978static bool cpu_has_load_perf_global_ctrl;
110312c8 979
2384d2b3
SY
980static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
981static DEFINE_SPINLOCK(vmx_vpid_lock);
982
1c3d14fe 983static struct vmcs_config {
6aa8b732
AK
984 int size;
985 int order;
9ac7e3e8 986 u32 basic_cap;
6aa8b732 987 u32 revision_id;
1c3d14fe
YS
988 u32 pin_based_exec_ctrl;
989 u32 cpu_based_exec_ctrl;
f78e0e2e 990 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS
991 u32 vmexit_ctrl;
992 u32 vmentry_ctrl;
993} vmcs_config;
6aa8b732 994
efff9e53 995static struct vmx_capability {
d56f546d
SY
996 u32 ept;
997 u32 vpid;
998} vmx_capability;
999
6aa8b732
AK
1000#define VMX_SEGMENT_FIELD(seg) \
1001 [VCPU_SREG_##seg] = { \
1002 .selector = GUEST_##seg##_SELECTOR, \
1003 .base = GUEST_##seg##_BASE, \
1004 .limit = GUEST_##seg##_LIMIT, \
1005 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1006 }
1007
772e0318 1008static const struct kvm_vmx_segment_field {
6aa8b732
AK
1009 unsigned selector;
1010 unsigned base;
1011 unsigned limit;
1012 unsigned ar_bytes;
1013} kvm_vmx_segment_fields[] = {
1014 VMX_SEGMENT_FIELD(CS),
1015 VMX_SEGMENT_FIELD(DS),
1016 VMX_SEGMENT_FIELD(ES),
1017 VMX_SEGMENT_FIELD(FS),
1018 VMX_SEGMENT_FIELD(GS),
1019 VMX_SEGMENT_FIELD(SS),
1020 VMX_SEGMENT_FIELD(TR),
1021 VMX_SEGMENT_FIELD(LDTR),
1022};
1023
26bb0981
AK
1024static u64 host_efer;
1025
6de4f3ad
AK
1026static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1027
4d56c8a7 1028/*
8c06585d 1029 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK
1030 * away by decrementing the array size.
1031 */
6aa8b732 1032static const u32 vmx_msr_index[] = {
05b3e0c2 1033#ifdef CONFIG_X86_64
44ea2b17 1034 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 1035#endif
8c06585d 1036 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 1037};
6aa8b732 1038
5bb16016 1039static inline bool is_exception_n(u32 intr_info, u8 vector)
6aa8b732
AK
1040{
1041 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1042 INTR_INFO_VALID_MASK)) ==
5bb16016
JK
1043 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1044}
1045
6f05485d
JK
1046static inline bool is_debug(u32 intr_info)
1047{
1048 return is_exception_n(intr_info, DB_VECTOR);
1049}
1050
1051static inline bool is_breakpoint(u32 intr_info)
1052{
1053 return is_exception_n(intr_info, BP_VECTOR);
1054}
1055
5bb16016
JK
1056static inline bool is_page_fault(u32 intr_info)
1057{
1058 return is_exception_n(intr_info, PF_VECTOR);
6aa8b732
AK
1059}
1060
31299944 1061static inline bool is_no_device(u32 intr_info)
2ab455cc 1062{
5bb16016 1063 return is_exception_n(intr_info, NM_VECTOR);
2ab455cc
AL
1064}
1065
31299944 1066static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0 1067{
5bb16016 1068 return is_exception_n(intr_info, UD_VECTOR);
7aa81cc0
AL
1069}
1070
31299944 1071static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK
1072{
1073 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1074 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1075}
1076
31299944 1077static inline bool is_machine_check(u32 intr_info)
a0861c02
AK
1078{
1079 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1080 INTR_INFO_VALID_MASK)) ==
1081 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1082}
1083
31299944 1084static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 1085{
04547156 1086 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY
1087}
1088
31299944 1089static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 1090{
04547156 1091 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS
1092}
1093
35754c98 1094static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 1095{
35754c98 1096 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS
1097}
1098
31299944 1099static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 1100{
04547156
SY
1101 return vmcs_config.cpu_based_exec_ctrl &
1102 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY
1103}
1104
774ead3a 1105static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 1106{
04547156
SY
1107 return vmcs_config.cpu_based_2nd_exec_ctrl &
1108 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1109}
1110
8d14695f
YZ
1111static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1112{
1113 return vmcs_config.cpu_based_2nd_exec_ctrl &
1114 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1115}
1116
83d4c286
YZ
1117static inline bool cpu_has_vmx_apic_register_virt(void)
1118{
1119 return vmcs_config.cpu_based_2nd_exec_ctrl &
1120 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1121}
1122
c7c9c56c
YZ
1123static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1124{
1125 return vmcs_config.cpu_based_2nd_exec_ctrl &
1126 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1127}
1128
64672c95
YJ
1129/*
1130 * Comment's format: document - errata name - stepping - processor name.
1131 * Refer from
1132 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1133 */
1134static u32 vmx_preemption_cpu_tfms[] = {
1135/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
11360x000206E6,
1137/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1138/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1139/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
11400x00020652,
1141/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
11420x00020655,
1143/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1144/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1145/*
1146 * 320767.pdf - AAP86 - B1 -
1147 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1148 */
11490x000106E5,
1150/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
11510x000106A0,
1152/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
11530x000106A1,
1154/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
11550x000106A4,
1156 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1157 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1158 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
11590x000106A5,
1160};
1161
1162static inline bool cpu_has_broken_vmx_preemption_timer(void)
1163{
1164 u32 eax = cpuid_eax(0x00000001), i;
1165
1166 /* Clear the reserved bits */
1167 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 1168 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ
1169 if (eax == vmx_preemption_cpu_tfms[i])
1170 return true;
1171
1172 return false;
1173}
1174
1175static inline bool cpu_has_vmx_preemption_timer(void)
1176{
64672c95
YJ
1177 return vmcs_config.pin_based_exec_ctrl &
1178 PIN_BASED_VMX_PREEMPTION_TIMER;
1179}
1180
01e439be
YZ
1181static inline bool cpu_has_vmx_posted_intr(void)
1182{
d6a858d1
PB
1183 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1184 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ
1185}
1186
1187static inline bool cpu_has_vmx_apicv(void)
1188{
1189 return cpu_has_vmx_apic_register_virt() &&
1190 cpu_has_vmx_virtual_intr_delivery() &&
1191 cpu_has_vmx_posted_intr();
1192}
1193
04547156
SY
1194static inline bool cpu_has_vmx_flexpriority(void)
1195{
1196 return cpu_has_vmx_tpr_shadow() &&
1197 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY
1198}
1199
e799794e
MT
1200static inline bool cpu_has_vmx_ept_execute_only(void)
1201{
31299944 1202 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT
1203}
1204
e799794e
MT
1205static inline bool cpu_has_vmx_ept_2m_page(void)
1206{
31299944 1207 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT
1208}
1209
878403b7
SY
1210static inline bool cpu_has_vmx_ept_1g_page(void)
1211{
31299944 1212 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY
1213}
1214
4bc9b982
SY
1215static inline bool cpu_has_vmx_ept_4levels(void)
1216{
1217 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1218}
1219
83c3a331
XH
1220static inline bool cpu_has_vmx_ept_ad_bits(void)
1221{
1222 return vmx_capability.ept & VMX_EPT_AD_BIT;
1223}
1224
31299944 1225static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1226{
31299944 1227 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY
1228}
1229
31299944 1230static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1231{
31299944 1232 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY
1233}
1234
518c8aee
GJ
1235static inline bool cpu_has_vmx_invvpid_single(void)
1236{
1237 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1238}
1239
b9d762fa
GJ
1240static inline bool cpu_has_vmx_invvpid_global(void)
1241{
1242 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1243}
1244
08d839c4
WL
1245static inline bool cpu_has_vmx_invvpid(void)
1246{
1247 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1248}
1249
31299944 1250static inline bool cpu_has_vmx_ept(void)
d56f546d 1251{
04547156
SY
1252 return vmcs_config.cpu_based_2nd_exec_ctrl &
1253 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY
1254}
1255
31299944 1256static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK
1257{
1258 return vmcs_config.cpu_based_2nd_exec_ctrl &
1259 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1260}
1261
31299944 1262static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE
1263{
1264 return vmcs_config.cpu_based_2nd_exec_ctrl &
1265 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1266}
1267
9ac7e3e8
JD
1268static inline bool cpu_has_vmx_basic_inout(void)
1269{
1270 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1271}
1272
35754c98 1273static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1274{
35754c98 1275 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY
1276}
1277
31299944 1278static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1279{
04547156
SY
1280 return vmcs_config.cpu_based_2nd_exec_ctrl &
1281 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY
1282}
1283
31299944 1284static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY
1285{
1286 return vmcs_config.cpu_based_2nd_exec_ctrl &
1287 SECONDARY_EXEC_RDTSCP;
1288}
1289
ad756a16
MJ
1290static inline bool cpu_has_vmx_invpcid(void)
1291{
1292 return vmcs_config.cpu_based_2nd_exec_ctrl &
1293 SECONDARY_EXEC_ENABLE_INVPCID;
1294}
1295
f5f48ee1
SY
1296static inline bool cpu_has_vmx_wbinvd_exit(void)
1297{
1298 return vmcs_config.cpu_based_2nd_exec_ctrl &
1299 SECONDARY_EXEC_WBINVD_EXITING;
1300}
1301
abc4fc58
AG
1302static inline bool cpu_has_vmx_shadow_vmcs(void)
1303{
1304 u64 vmx_msr;
1305 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1306 /* check if the cpu supports writing r/o exit information fields */
1307 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1308 return false;
1309
1310 return vmcs_config.cpu_based_2nd_exec_ctrl &
1311 SECONDARY_EXEC_SHADOW_VMCS;
1312}
1313
843e4330
KH
1314static inline bool cpu_has_vmx_pml(void)
1315{
1316 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1317}
1318
64903d61
HZ
1319static inline bool cpu_has_vmx_tsc_scaling(void)
1320{
1321 return vmcs_config.cpu_based_2nd_exec_ctrl &
1322 SECONDARY_EXEC_TSC_SCALING;
1323}
1324
04547156
SY
1325static inline bool report_flexpriority(void)
1326{
1327 return flexpriority_enabled;
1328}
1329
c7c2c709
JM
1330static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1331{
1332 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1333}
1334
fe3ef05c
NHE
1335static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1336{
1337 return vmcs12->cpu_based_vm_exec_control & bit;
1338}
1339
1340static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1341{
1342 return (vmcs12->cpu_based_vm_exec_control &
1343 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1344 (vmcs12->secondary_vm_exec_control & bit);
1345}
1346
f5c4368f 1347static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE
1348{
1349 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1350}
1351
f4124500
JK
1352static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1353{
1354 return vmcs12->pin_based_vm_exec_control &
1355 PIN_BASED_VMX_PREEMPTION_TIMER;
1356}
1357
155a97a3
NHE
1358static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1359{
1360 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1361}
1362
81dc01f7
WL
1363static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1364{
1365 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1366 vmx_xsaves_supported();
1367}
1368
c5f983f6
BD
1369static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1370{
1371 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1372}
1373
f2b93280
WV
1374static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1375{
1376 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1377}
1378
5c614b35
WL
1379static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1380{
1381 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1382}
1383
82f0dd4b
WV
1384static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1385{
1386 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1387}
1388
608406e2
WV
1389static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1390{
1391 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1392}
1393
705699a1
WV
1394static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1395{
1396 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1397}
1398
ef85b673 1399static inline bool is_nmi(u32 intr_info)
644d711a
NHE
1400{
1401 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
ef85b673 1402 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
644d711a
NHE
1403}
1404
533558bc
JK
1405static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1406 u32 exit_intr_info,
1407 unsigned long exit_qualification);
7c177938
NHE
1408static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1409 struct vmcs12 *vmcs12,
1410 u32 reason, unsigned long qualification);
1411
8b9cf98c 1412static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK
1413{
1414 int i;
1415
a2fa3e9f 1416 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1417 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED
1418 return i;
1419 return -1;
1420}
1421
2384d2b3
SY
1422static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1423{
1424 struct {
1425 u64 vpid : 16;
1426 u64 rsvd : 48;
1427 u64 gva;
1428 } operand = { vpid, 0, gva };
1429
4ecac3fd 1430 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY
1431 /* CF==1 or ZF==1 --> rc = -1 */
1432 "; ja 1f ; ud2 ; 1:"
1433 : : "a"(&operand), "c"(ext) : "cc", "memory");
1434}
1435
1439442c
SY
1436static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1437{
1438 struct {
1439 u64 eptp, gpa;
1440 } operand = {eptp, gpa};
1441
4ecac3fd 1442 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY
1443 /* CF==1 or ZF==1 --> rc = -1 */
1444 "; ja 1f ; ud2 ; 1:\n"
1445 : : "a" (&operand), "c" (ext) : "cc", "memory");
1446}
1447
26bb0981 1448static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED
1449{
1450 int i;
1451
8b9cf98c 1452 i = __find_msr_index(vmx, msr);
a75beee6 1453 if (i >= 0)
a2fa3e9f 1454 return &vmx->guest_msrs[i];
8b6d44c7 1455 return NULL;
7725f0ba
AK
1456}
1457
6aa8b732
AK
1458static void vmcs_clear(struct vmcs *vmcs)
1459{
1460 u64 phys_addr = __pa(vmcs);
1461 u8 error;
1462
4ecac3fd 1463 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1464 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK
1465 : "cc", "memory");
1466 if (error)
1467 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1468 vmcs, phys_addr);
1469}
1470
d462b819
NHE
1471static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1472{
1473 vmcs_clear(loaded_vmcs->vmcs);
355f4fb1
JM
1474 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1475 vmcs_clear(loaded_vmcs->shadow_vmcs);
d462b819
NHE
1476 loaded_vmcs->cpu = -1;
1477 loaded_vmcs->launched = 0;
1478}
1479
7725b894
DX
1480static void vmcs_load(struct vmcs *vmcs)
1481{
1482 u64 phys_addr = __pa(vmcs);
1483 u8 error;
1484
1485 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1486 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX
1487 : "cc", "memory");
1488 if (error)
2844d849 1489 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX
1490 vmcs, phys_addr);
1491}
1492
2965faa5 1493#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY
1494/*
1495 * This bitmap is used to indicate whether the vmclear
1496 * operation is enabled on all cpus. All disabled by
1497 * default.
1498 */
1499static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1500
1501static inline void crash_enable_local_vmclear(int cpu)
1502{
1503 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1504}
1505
1506static inline void crash_disable_local_vmclear(int cpu)
1507{
1508 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1509}
1510
1511static inline int crash_local_vmclear_enabled(int cpu)
1512{
1513 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1514}
1515
1516static void crash_vmclear_local_loaded_vmcss(void)
1517{
1518 int cpu = raw_smp_processor_id();
1519 struct loaded_vmcs *v;
1520
1521 if (!crash_local_vmclear_enabled(cpu))
1522 return;
1523
1524 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1525 loaded_vmcss_on_cpu_link)
1526 vmcs_clear(v->vmcs);
1527}
1528#else
1529static inline void crash_enable_local_vmclear(int cpu) { }
1530static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1531#endif /* CONFIG_KEXEC_CORE */
8f536b76 1532
d462b819 1533static void __loaded_vmcs_clear(void *arg)
6aa8b732 1534{
d462b819 1535 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1536 int cpu = raw_smp_processor_id();
6aa8b732 1537
d462b819
NHE
1538 if (loaded_vmcs->cpu != cpu)
1539 return; /* vcpu migration can race with cpu offline */
1540 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1541 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1542 crash_disable_local_vmclear(cpu);
d462b819 1543 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG
1544
1545 /*
1546 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1547 * is before setting loaded_vmcs->vcpu to -1 which is done in
1548 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1549 * then adds the vmcs into percpu list before it is deleted.
1550 */
1551 smp_wmb();
1552
d462b819 1553 loaded_vmcs_init(loaded_vmcs);
8f536b76 1554 crash_enable_local_vmclear(cpu);
6aa8b732
AK
1555}
1556
d462b819 1557static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1558{
e6c7d321
XG
1559 int cpu = loaded_vmcs->cpu;
1560
1561 if (cpu != -1)
1562 smp_call_function_single(cpu,
1563 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK
1564}
1565
dd5f5341 1566static inline void vpid_sync_vcpu_single(int vpid)
2384d2b3 1567{
dd5f5341 1568 if (vpid == 0)
2384d2b3
SY
1569 return;
1570
518c8aee 1571 if (cpu_has_vmx_invvpid_single())
dd5f5341 1572 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
2384d2b3
SY
1573}
1574
b9d762fa
GJ
1575static inline void vpid_sync_vcpu_global(void)
1576{
1577 if (cpu_has_vmx_invvpid_global())
1578 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1579}
1580
dd5f5341 1581static inline void vpid_sync_context(int vpid)
b9d762fa
GJ
1582{
1583 if (cpu_has_vmx_invvpid_single())
dd5f5341 1584 vpid_sync_vcpu_single(vpid);
b9d762fa
GJ
1585 else
1586 vpid_sync_vcpu_global();
1587}
1588
1439442c
SY
1589static inline void ept_sync_global(void)
1590{
1591 if (cpu_has_vmx_invept_global())
1592 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1593}
1594
1595static inline void ept_sync_context(u64 eptp)
1596{
089d034e 1597 if (enable_ept) {
1439442c
SY
1598 if (cpu_has_vmx_invept_context())
1599 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1600 else
1601 ept_sync_global();
1602 }
1603}
1604
8a86aea9
PB
1605static __always_inline void vmcs_check16(unsigned long field)
1606{
1607 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1608 "16-bit accessor invalid for 64-bit field");
1609 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1610 "16-bit accessor invalid for 64-bit high field");
1611 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1612 "16-bit accessor invalid for 32-bit high field");
1613 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1614 "16-bit accessor invalid for natural width field");
1615}
1616
1617static __always_inline void vmcs_check32(unsigned long field)
1618{
1619 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1620 "32-bit accessor invalid for 16-bit field");
1621 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1622 "32-bit accessor invalid for natural width field");
1623}
1624
1625static __always_inline void vmcs_check64(unsigned long field)
1626{
1627 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1628 "64-bit accessor invalid for 16-bit field");
1629 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1630 "64-bit accessor invalid for 64-bit high field");
1631 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1632 "64-bit accessor invalid for 32-bit field");
1633 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1634 "64-bit accessor invalid for natural width field");
1635}
1636
1637static __always_inline void vmcs_checkl(unsigned long field)
1638{
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1640 "Natural width accessor invalid for 16-bit field");
1641 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1642 "Natural width accessor invalid for 64-bit field");
1643 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1644 "Natural width accessor invalid for 64-bit high field");
1645 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1646 "Natural width accessor invalid for 32-bit field");
1647}
1648
1649static __always_inline unsigned long __vmcs_readl(unsigned long field)
6aa8b732 1650{
5e520e62 1651 unsigned long value;
6aa8b732 1652
5e520e62
AK
1653 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1654 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK
1655 return value;
1656}
1657
96304217 1658static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732 1659{
8a86aea9
PB
1660 vmcs_check16(field);
1661 return __vmcs_readl(field);
6aa8b732
AK
1662}
1663
96304217 1664static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732 1665{
8a86aea9
PB
1666 vmcs_check32(field);
1667 return __vmcs_readl(field);
6aa8b732
AK
1668}
1669
96304217 1670static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1671{
8a86aea9 1672 vmcs_check64(field);
05b3e0c2 1673#ifdef CONFIG_X86_64
8a86aea9 1674 return __vmcs_readl(field);
6aa8b732 1675#else
8a86aea9 1676 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
6aa8b732
AK
1677#endif
1678}
1679
8a86aea9
PB
1680static __always_inline unsigned long vmcs_readl(unsigned long field)
1681{
1682 vmcs_checkl(field);
1683 return __vmcs_readl(field);
1684}
1685
e52de1b8
AK
1686static noinline void vmwrite_error(unsigned long field, unsigned long value)
1687{
1688 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1689 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1690 dump_stack();
1691}
1692
8a86aea9 1693static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
6aa8b732
AK
1694{
1695 u8 error;
1696
4ecac3fd 1697 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1698 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK
1699 if (unlikely(error))
1700 vmwrite_error(field, value);
6aa8b732
AK
1701}
1702
8a86aea9 1703static __always_inline void vmcs_write16(unsigned long field, u16 value)
6aa8b732 1704{
8a86aea9
PB
1705 vmcs_check16(field);
1706 __vmcs_writel(field, value);
6aa8b732
AK
1707}
1708
8a86aea9 1709static __always_inline void vmcs_write32(unsigned long field, u32 value)
6aa8b732 1710{
8a86aea9
PB
1711 vmcs_check32(field);
1712 __vmcs_writel(field, value);
6aa8b732
AK
1713}
1714
8a86aea9 1715static __always_inline void vmcs_write64(unsigned long field, u64 value)
6aa8b732 1716{
8a86aea9
PB
1717 vmcs_check64(field);
1718 __vmcs_writel(field, value);
7682f2d0 1719#ifndef CONFIG_X86_64
6aa8b732 1720 asm volatile ("");
8a86aea9 1721 __vmcs_writel(field+1, value >> 32);
6aa8b732
AK
1722#endif
1723}
1724
8a86aea9 1725static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2ab455cc 1726{
8a86aea9
PB
1727 vmcs_checkl(field);
1728 __vmcs_writel(field, value);
2ab455cc
AL
1729}
1730
8a86aea9 1731static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2ab455cc 1732{
8a86aea9
PB
1733 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1734 "vmcs_clear_bits does not support 64-bit fields");
1735 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2ab455cc
AL
1736}
1737
8a86aea9 1738static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2ab455cc 1739{
8a86aea9
PB
1740 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1741 "vmcs_set_bits does not support 64-bit fields");
1742 __vmcs_writel(field, __vmcs_readl(field) | mask);
2ab455cc
AL
1743}
1744
8391ce44
PB
1745static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1746{
1747 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1748}
1749
2961e876
GN
1750static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1751{
1752 vmcs_write32(VM_ENTRY_CONTROLS, val);
1753 vmx->vm_entry_controls_shadow = val;
1754}
1755
1756static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1757{
1758 if (vmx->vm_entry_controls_shadow != val)
1759 vm_entry_controls_init(vmx, val);
1760}
1761
1762static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1763{
1764 return vmx->vm_entry_controls_shadow;
1765}
1766
1767
1768static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1769{
1770 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1771}
1772
1773static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1774{
1775 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1776}
1777
8391ce44
PB
1778static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1779{
1780 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1781}
1782
2961e876
GN
1783static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1784{
1785 vmcs_write32(VM_EXIT_CONTROLS, val);
1786 vmx->vm_exit_controls_shadow = val;
1787}
1788
1789static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1790{
1791 if (vmx->vm_exit_controls_shadow != val)
1792 vm_exit_controls_init(vmx, val);
1793}
1794
1795static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1796{
1797 return vmx->vm_exit_controls_shadow;
1798}
1799
1800
1801static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1802{
1803 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1804}
1805
1806static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1807{
1808 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1809}
1810
2fb92db1
AK
1811static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1812{
1813 vmx->segment_cache.bitmask = 0;
1814}
1815
1816static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1817 unsigned field)
1818{
1819 bool ret;
1820 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1821
1822 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1823 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1824 vmx->segment_cache.bitmask = 0;
1825 }
1826 ret = vmx->segment_cache.bitmask & mask;
1827 vmx->segment_cache.bitmask |= mask;
1828 return ret;
1829}
1830
1831static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1832{
1833 u16 *p = &vmx->segment_cache.seg[seg].selector;
1834
1835 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1836 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1837 return *p;
1838}
1839
1840static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1841{
1842 ulong *p = &vmx->segment_cache.seg[seg].base;
1843
1844 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1845 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1846 return *p;
1847}
1848
1849static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1850{
1851 u32 *p = &vmx->segment_cache.seg[seg].limit;
1852
1853 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1854 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1855 return *p;
1856}
1857
1858static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1859{
1860 u32 *p = &vmx->segment_cache.seg[seg].ar;
1861
1862 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1863 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1864 return *p;
1865}
1866
abd3f2d6
AK
1867static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1868{
1869 u32 eb;
1870
fd7373cc 1871 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 1872 (1u << DB_VECTOR) | (1u << AC_VECTOR);
fd7373cc
JK
1873 if ((vcpu->guest_debug &
1874 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1875 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1876 eb |= 1u << BP_VECTOR;
7ffd92c5 1877 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1878 eb = ~0;
089d034e 1879 if (enable_ept)
1439442c 1880 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE
1881
1882 /* When we are running a nested L2 guest and L1 specified for it a
1883 * certain exception bitmap, we must trap the same exceptions and pass
1884 * them to L1. When running L2, we will only handle the exceptions
1885 * specified above if L1 did not want them.
1886 */
1887 if (is_guest_mode(vcpu))
1888 eb |= get_vmcs12(vcpu)->exception_bitmap;
1889
abd3f2d6
AK
1890 vmcs_write32(EXCEPTION_BITMAP, eb);
1891}
1892
2961e876
GN
1893static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1894 unsigned long entry, unsigned long exit)
8bf00a52 1895{
2961e876
GN
1896 vm_entry_controls_clearbit(vmx, entry);
1897 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN
1898}
1899
61d2ef2c
AK
1900static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1901{
1902 unsigned i;
1903 struct msr_autoload *m = &vmx->msr_autoload;
1904
8bf00a52
GN
1905 switch (msr) {
1906 case MSR_EFER:
1907 if (cpu_has_load_ia32_efer) {
2961e876
GN
1908 clear_atomic_switch_msr_special(vmx,
1909 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN
1910 VM_EXIT_LOAD_IA32_EFER);
1911 return;
1912 }
1913 break;
1914 case MSR_CORE_PERF_GLOBAL_CTRL:
1915 if (cpu_has_load_perf_global_ctrl) {
2961e876 1916 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN
1917 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1918 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1919 return;
1920 }
1921 break;
110312c8
AK
1922 }
1923
61d2ef2c
AK
1924 for (i = 0; i < m->nr; ++i)
1925 if (m->guest[i].index == msr)
1926 break;
1927
1928 if (i == m->nr)
1929 return;
1930 --m->nr;
1931 m->guest[i] = m->guest[m->nr];
1932 m->host[i] = m->host[m->nr];
1933 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1934 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1935}
1936
2961e876
GN
1937static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1938 unsigned long entry, unsigned long exit,
1939 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1940 u64 guest_val, u64 host_val)
8bf00a52
GN
1941{
1942 vmcs_write64(guest_val_vmcs, guest_val);
1943 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN
1944 vm_entry_controls_setbit(vmx, entry);
1945 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN
1946}
1947
61d2ef2c
AK
1948static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1949 u64 guest_val, u64 host_val)
1950{
1951 unsigned i;
1952 struct msr_autoload *m = &vmx->msr_autoload;
1953
8bf00a52
GN
1954 switch (msr) {
1955 case MSR_EFER:
1956 if (cpu_has_load_ia32_efer) {
2961e876
GN
1957 add_atomic_switch_msr_special(vmx,
1958 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN
1959 VM_EXIT_LOAD_IA32_EFER,
1960 GUEST_IA32_EFER,
1961 HOST_IA32_EFER,
1962 guest_val, host_val);
1963 return;
1964 }
1965 break;
1966 case MSR_CORE_PERF_GLOBAL_CTRL:
1967 if (cpu_has_load_perf_global_ctrl) {
2961e876 1968 add_atomic_switch_msr_special(vmx,
8bf00a52
GN
1969 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1970 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1971 GUEST_IA32_PERF_GLOBAL_CTRL,
1972 HOST_IA32_PERF_GLOBAL_CTRL,
1973 guest_val, host_val);
1974 return;
1975 }
1976 break;
7099e2e1
RK
1977 case MSR_IA32_PEBS_ENABLE:
1978 /* PEBS needs a quiescent period after being disabled (to write
1979 * a record). Disabling PEBS through VMX MSR swapping doesn't
1980 * provide that period, so a CPU could write host's record into
1981 * guest's memory.
1982 */
1983 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK
1984 }
1985
61d2ef2c
AK
1986 for (i = 0; i < m->nr; ++i)
1987 if (m->guest[i].index == msr)
1988 break;
1989
e7fc6f93 1990 if (i == NR_AUTOLOAD_MSRS) {
60266204 1991 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN
1992 "Can't add msr %x\n", msr);
1993 return;
1994 } else if (i == m->nr) {
61d2ef2c
AK
1995 ++m->nr;
1996 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1997 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1998 }
1999
2000 m->guest[i].index = msr;
2001 m->guest[i].value = guest_val;
2002 m->host[i].index = msr;
2003 m->host[i].value = host_val;
2004}
2005
92c0d900 2006static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 2007{
844a5fe2
PB
2008 u64 guest_efer = vmx->vcpu.arch.efer;
2009 u64 ignore_bits = 0;
2010
2011 if (!enable_ept) {
2012 /*
2013 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2014 * host CPUID is more efficient than testing guest CPUID
2015 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2016 */
2017 if (boot_cpu_has(X86_FEATURE_SMEP))
2018 guest_efer |= EFER_NX;
2019 else if (!(guest_efer & EFER_NX))
2020 ignore_bits |= EFER_NX;
2021 }
3a34a881 2022
51c6cf66 2023 /*
844a5fe2 2024 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 2025 */
844a5fe2 2026 ignore_bits |= EFER_SCE;
51c6cf66
AK
2027#ifdef CONFIG_X86_64
2028 ignore_bits |= EFER_LMA | EFER_LME;
2029 /* SCE is meaningful only in long mode on Intel */
2030 if (guest_efer & EFER_LMA)
2031 ignore_bits &= ~(u64)EFER_SCE;
2032#endif
84ad33ef
AK
2033
2034 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL
2035
2036 /*
2037 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2038 * On CPUs that support "load IA32_EFER", always switch EFER
2039 * atomically, since it's faster than switching it manually.
2040 */
2041 if (cpu_has_load_ia32_efer ||
2042 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK
2043 if (!(guest_efer & EFER_LMA))
2044 guest_efer &= ~EFER_LME;
54b98bff
AL
2045 if (guest_efer != host_efer)
2046 add_atomic_switch_msr(vmx, MSR_EFER,
2047 guest_efer, host_efer);
84ad33ef 2048 return false;
844a5fe2
PB
2049 } else {
2050 guest_efer &= ~ignore_bits;
2051 guest_efer |= host_efer & ignore_bits;
2052
2053 vmx->guest_msrs[efer_offset].data = guest_efer;
2054 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 2055
844a5fe2
PB
2056 return true;
2057 }
51c6cf66
AK
2058}
2059
e28baead
AL
2060#ifdef CONFIG_X86_32
2061/*
2062 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2063 * VMCS rather than the segment table. KVM uses this helper to figure
2064 * out the current bases to poke them into the VMCS before entry.
2065 */
2d49ec72
GN
2066static unsigned long segment_base(u16 selector)
2067{
8c2e41f7 2068 struct desc_struct *table;
2d49ec72
GN
2069 unsigned long v;
2070
8c2e41f7 2071 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN
2072 return 0;
2073
45fc8757 2074 table = get_current_gdt_ro();
2d49ec72 2075
8c2e41f7 2076 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN
2077 u16 ldt_selector = kvm_read_ldt();
2078
8c2e41f7 2079 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN
2080 return 0;
2081
8c2e41f7 2082 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 2083 }
8c2e41f7 2084 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN
2085 return v;
2086}
e28baead 2087#endif
2d49ec72 2088
04d2cc77 2089static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 2090{
04d2cc77 2091 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2092 int i;
04d2cc77 2093
a2fa3e9f 2094 if (vmx->host_state.loaded)
33ed6329
AK
2095 return;
2096
a2fa3e9f 2097 vmx->host_state.loaded = 1;
33ed6329
AK
2098 /*
2099 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2100 * allow segment selectors with cpl > 0 or ti == 1.
2101 */
d6e88aec 2102 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 2103 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 2104 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 2105 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 2106 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV
2107 vmx->host_state.fs_reload_needed = 0;
2108 } else {
33ed6329 2109 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 2110 vmx->host_state.fs_reload_needed = 1;
33ed6329 2111 }
9581d442 2112 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH
2113 if (!(vmx->host_state.gs_sel & 7))
2114 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK
2115 else {
2116 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 2117 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK
2118 }
2119
b2da15ac
AK
2120#ifdef CONFIG_X86_64
2121 savesegment(ds, vmx->host_state.ds_sel);
2122 savesegment(es, vmx->host_state.es_sel);
2123#endif
2124
33ed6329
AK
2125#ifdef CONFIG_X86_64
2126 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2127 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2128#else
a2fa3e9f
GH
2129 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2130 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 2131#endif
707c0874
AK
2132
2133#ifdef CONFIG_X86_64
c8770e7b
AK
2134 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2135 if (is_long_mode(&vmx->vcpu))
44ea2b17 2136 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 2137#endif
da8999d3
LJ
2138 if (boot_cpu_has(X86_FEATURE_MPX))
2139 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK
2140 for (i = 0; i < vmx->save_nmsrs; ++i)
2141 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK
2142 vmx->guest_msrs[i].data,
2143 vmx->guest_msrs[i].mask);
33ed6329
AK
2144}
2145
a9b21b62 2146static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 2147{
a2fa3e9f 2148 if (!vmx->host_state.loaded)
33ed6329
AK
2149 return;
2150
e1beb1d3 2151 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 2152 vmx->host_state.loaded = 0;
c8770e7b
AK
2153#ifdef CONFIG_X86_64
2154 if (is_long_mode(&vmx->vcpu))
2155 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2156#endif
152d3f2f 2157 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 2158 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 2159#ifdef CONFIG_X86_64
9581d442 2160 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK
2161#else
2162 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 2163#endif
33ed6329 2164 }
0a77fe4c
AK
2165 if (vmx->host_state.fs_reload_needed)
2166 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK
2167#ifdef CONFIG_X86_64
2168 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2169 loadsegment(ds, vmx->host_state.ds_sel);
2170 loadsegment(es, vmx->host_state.es_sel);
2171 }
b2da15ac 2172#endif
b7ffc44d 2173 invalidate_tss_limit();
44ea2b17 2174#ifdef CONFIG_X86_64
c8770e7b 2175 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 2176#endif
da8999d3
LJ
2177 if (vmx->host_state.msr_host_bndcfgs)
2178 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
45fc8757 2179 load_fixmap_gdt(raw_smp_processor_id());
33ed6329
AK
2180}
2181
a9b21b62
AK
2182static void vmx_load_host_state(struct vcpu_vmx *vmx)
2183{
2184 preempt_disable();
2185 __vmx_load_host_state(vmx);
2186 preempt_enable();
2187}
2188
28b835d6
FW
2189static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2190{
2191 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2192 struct pi_desc old, new;
2193 unsigned int dest;
2194
2195 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
2196 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2197 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW
2198 return;
2199
2200 do {
2201 old.control = new.control = pi_desc->control;
2202
2203 /*
2204 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2205 * are two possible cases:
2206 * 1. After running 'pre_block', context switch
2207 * happened. For this case, 'sn' was set in
2208 * vmx_vcpu_put(), so we need to clear it here.
2209 * 2. After running 'pre_block', we were blocked,
2210 * and woken up by some other guy. For this case,
2211 * we don't need to do anything, 'pi_post_block'
2212 * will do everything for us. However, we cannot
2213 * check whether it is case #1 or case #2 here
2214 * (maybe, not needed), so we also clear sn here,
2215 * I think it is not a big deal.
2216 */
2217 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2218 if (vcpu->cpu != cpu) {
2219 dest = cpu_physical_id(cpu);
2220
2221 if (x2apic_enabled())
2222 new.ndst = dest;
2223 else
2224 new.ndst = (dest << 8) & 0xFF00;
2225 }
2226
2227 /* set 'NV' to 'notification vector' */
2228 new.nv = POSTED_INTR_VECTOR;
2229 }
2230
2231 /* Allow posting non-urgent interrupts */
2232 new.sn = 0;
2233 } while (cmpxchg(&pi_desc->control, old.control,
2234 new.control) != old.control);
2235}
1be0e61c 2236
c95ba92a
PF
2237static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2238{
2239 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2240 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2241}
2242
6aa8b732
AK
2243/*
2244 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2245 * vcpu mutex is already taken.
2246 */
15ad7146 2247static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 2248{
a2fa3e9f 2249 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 2250 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 2251
b80c76ec 2252 if (!already_loaded) {
fe0e80be 2253 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 2254 local_irq_disable();
8f536b76 2255 crash_disable_local_vmclear(cpu);
5a560f8b
XG
2256
2257 /*
2258 * Read loaded_vmcs->cpu should be before fetching
2259 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2260 * See the comments in __loaded_vmcs_clear().
2261 */
2262 smp_rmb();
2263
d462b819
NHE
2264 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2265 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 2266 crash_enable_local_vmclear(cpu);
92fe13be 2267 local_irq_enable();
b80c76ec
JM
2268 }
2269
2270 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2271 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2272 vmcs_load(vmx->loaded_vmcs->vmcs);
2273 }
2274
2275 if (!already_loaded) {
59c58ceb 2276 void *gdt = get_current_gdt_ro();
b80c76ec
JM
2277 unsigned long sysenter_esp;
2278
2279 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 2280
6aa8b732
AK
2281 /*
2282 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 2283 * processors. See 22.2.4.
6aa8b732 2284 */
e0c23063
AL
2285 vmcs_writel(HOST_TR_BASE,
2286 (unsigned long)this_cpu_ptr(&cpu_tss));
59c58ceb 2287 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732 2288
b7ffc44d
AL
2289 /*
2290 * VM exits change the host TR limit to 0x67 after a VM
2291 * exit. This is okay, since 0x67 covers everything except
2292 * the IO bitmap and have have code to handle the IO bitmap
2293 * being lost after a VM exit.
2294 */
2295 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2296
6aa8b732
AK
2297 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2298 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 2299
d462b819 2300 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 2301 }
28b835d6 2302
2680d6da
OH
2303 /* Setup TSC multiplier */
2304 if (kvm_has_tsc_control &&
c95ba92a
PF
2305 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2306 decache_tsc_multiplier(vmx);
2680d6da 2307
28b835d6 2308 vmx_vcpu_pi_load(vcpu, cpu);
1be0e61c 2309 vmx->host_pkru = read_pkru();
28b835d6
FW
2310}
2311
2312static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2313{
2314 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2315
2316 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
2317 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2318 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW
2319 return;
2320
2321 /* Set SN when the vCPU is preempted */
2322 if (vcpu->preempted)
2323 pi_set_sn(pi_desc);
6aa8b732
AK
2324}
2325
2326static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2327{
28b835d6
FW
2328 vmx_vcpu_pi_put(vcpu);
2329
a9b21b62 2330 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK
2331}
2332
f244deed
WL
2333static bool emulation_required(struct kvm_vcpu *vcpu)
2334{
2335 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2336}
2337
edcafe3c
AK
2338static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2339
fe3ef05c
NHE
2340/*
2341 * Return the cr0 value that a nested guest would read. This is a combination
2342 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2343 * its hypervisor (cr0_read_shadow).
2344 */
2345static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2346{
2347 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2348 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2349}
2350static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2351{
2352 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2353 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2354}
2355
6aa8b732
AK
2356static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2357{
78ac8b47 2358 unsigned long rflags, save_rflags;
345dcaa8 2359
6de12732
AK
2360 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2361 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2362 rflags = vmcs_readl(GUEST_RFLAGS);
2363 if (to_vmx(vcpu)->rmode.vm86_active) {
2364 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2365 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2366 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2367 }
2368 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2369 }
6de12732 2370 return to_vmx(vcpu)->rflags;
6aa8b732
AK
2371}
2372
2373static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2374{
f244deed
WL
2375 unsigned long old_rflags = vmx_get_rflags(vcpu);
2376
6de12732
AK
2377 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2378 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK
2379 if (to_vmx(vcpu)->rmode.vm86_active) {
2380 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2381 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2382 }
6aa8b732 2383 vmcs_writel(GUEST_RFLAGS, rflags);
f244deed
WL
2384
2385 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2386 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
6aa8b732
AK
2387}
2388
be94f6b7
HH
2389static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2390{
2391 return to_vmx(vcpu)->guest_pkru;
2392}
2393
37ccdcbe 2394static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC
2395{
2396 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2397 int ret = 0;
2398
2399 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2400 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2401 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2402 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2403
37ccdcbe 2404 return ret;
2809f5d2
GC
2405}
2406
2407static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2408{
2409 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2410 u32 interruptibility = interruptibility_old;
2411
2412 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2413
48005f64 2414 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2415 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2416 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC
2417 interruptibility |= GUEST_INTR_STATE_STI;
2418
2419 if ((interruptibility != interruptibility_old))
2420 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2421}
2422
6aa8b732
AK
2423static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2424{
2425 unsigned long rip;
6aa8b732 2426
5fdbf976 2427 rip = kvm_rip_read(vcpu);
6aa8b732 2428 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2429 kvm_rip_write(vcpu, rip);
6aa8b732 2430
2809f5d2
GC
2431 /* skipping an emulated instruction also counts */
2432 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK
2433}
2434
b96fb439
PB
2435static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2436 unsigned long exit_qual)
2437{
2438 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2439 unsigned int nr = vcpu->arch.exception.nr;
2440 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2441
2442 if (vcpu->arch.exception.has_error_code) {
2443 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2444 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2445 }
2446
2447 if (kvm_exception_is_soft(nr))
2448 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2449 else
2450 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2451
2452 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2453 vmx_get_nmi_mask(vcpu))
2454 intr_info |= INTR_INFO_UNBLOCK_NMI;
2455
2456 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2457}
2458
0b6ac343
NHE
2459/*
2460 * KVM wants to inject page-faults which it got to the guest. This function
2461 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2462 */
adfe20fb 2463static int nested_vmx_check_exception(struct kvm_vcpu *vcpu)
0b6ac343
NHE
2464{
2465 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
adfe20fb 2466 unsigned int nr = vcpu->arch.exception.nr;
0b6ac343 2467
b96fb439
PB
2468 if (nr == PF_VECTOR) {
2469 if (vcpu->arch.exception.nested_apf) {
2470 nested_vmx_inject_exception_vmexit(vcpu,
2471 vcpu->arch.apf.nested_apf_token);
2472 return 1;
2473 }
2474 /*
2475 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2476 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2477 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2478 * can be written only when inject_pending_event runs. This should be
2479 * conditional on a new capability---if the capability is disabled,
2480 * kvm_multiple_exception would write the ancillary information to
2481 * CR2 or DR6, for backwards ABI-compatibility.
2482 */
2483 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2484 vcpu->arch.exception.error_code)) {
2485 nested_vmx_inject_exception_vmexit(vcpu, vcpu->arch.cr2);
2486 return 1;
2487 }
2488 } else {
2489 unsigned long exit_qual = 0;
2490 if (nr == DB_VECTOR)
2491 exit_qual = vcpu->arch.dr6;
0b6ac343 2492
b96fb439
PB
2493 if (vmcs12->exception_bitmap & (1u << nr)) {
2494 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
2495 return 1;
2496 }
adfe20fb
WL
2497 }
2498
b96fb439 2499 return 0;
0b6ac343
NHE
2500}
2501
cfcd20e5 2502static void vmx_queue_exception(struct kvm_vcpu *vcpu)
298101da 2503{
77ab6db0 2504 struct vcpu_vmx *vmx = to_vmx(vcpu);
cfcd20e5
WL
2505 unsigned nr = vcpu->arch.exception.nr;
2506 bool has_error_code = vcpu->arch.exception.has_error_code;
2507 bool reinject = vcpu->arch.exception.reinject;
2508 u32 error_code = vcpu->arch.exception.error_code;
8ab2d2e2 2509 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2510
e011c663 2511 if (!reinject && is_guest_mode(vcpu) &&
adfe20fb 2512 nested_vmx_check_exception(vcpu))
0b6ac343
NHE
2513 return;
2514
8ab2d2e2 2515 if (has_error_code) {
77ab6db0 2516 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK
2517 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2518 }
77ab6db0 2519
7ffd92c5 2520 if (vmx->rmode.vm86_active) {
71f9833b
SH
2521 int inc_eip = 0;
2522 if (kvm_exception_is_soft(nr))
2523 inc_eip = vcpu->arch.event_exit_inst_len;
2524 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2525 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK
2526 return;
2527 }
2528
66fd3f7f
GN
2529 if (kvm_exception_is_soft(nr)) {
2530 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2531 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK
2532 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2533 } else
2534 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2535
2536 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK
2537}
2538
4e47c7a6
SY
2539static bool vmx_rdtscp_supported(void)
2540{
2541 return cpu_has_vmx_rdtscp();
2542}
2543
ad756a16
MJ
2544static bool vmx_invpcid_supported(void)
2545{
2546 return cpu_has_vmx_invpcid() && enable_ept;
2547}
2548
a75beee6
ED
2549/*
2550 * Swap MSR entry in host/guest MSR entry array.
2551 */
8b9cf98c 2552static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2553{
26bb0981 2554 struct shared_msr_entry tmp;
a2fa3e9f
GH
2555
2556 tmp = vmx->guest_msrs[to];
2557 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2558 vmx->guest_msrs[from] = tmp;
a75beee6
ED
2559}
2560
8d14695f
YZ
2561static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2562{
2563 unsigned long *msr_bitmap;
2564
670125bd 2565 if (is_guest_mode(vcpu))
d048c098 2566 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
3ce424e4
RK
2567 else if (cpu_has_secondary_exec_ctrls() &&
2568 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2569 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
f6e90f9e
WL
2570 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2571 if (is_long_mode(vcpu))
c63e4563 2572 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
f6e90f9e 2573 else
c63e4563 2574 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
f6e90f9e
WL
2575 } else {
2576 if (is_long_mode(vcpu))
c63e4563 2577 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
f6e90f9e 2578 else
c63e4563 2579 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
f6e90f9e 2580 }
8d14695f
YZ
2581 } else {
2582 if (is_long_mode(vcpu))
2583 msr_bitmap = vmx_msr_bitmap_longmode;
2584 else
2585 msr_bitmap = vmx_msr_bitmap_legacy;
2586 }
2587
2588 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2589}
2590
e38aea3e
AK
2591/*
2592 * Set up the vmcs to automatically save and restore system
2593 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2594 * mode, as fiddling with msrs is very expensive.
2595 */
8b9cf98c 2596static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2597{
26bb0981 2598 int save_nmsrs, index;
e38aea3e 2599
a75beee6
ED
2600 save_nmsrs = 0;
2601#ifdef CONFIG_X86_64
8b9cf98c 2602 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2603 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2604 if (index >= 0)
8b9cf98c
RR
2605 move_msr_up(vmx, index, save_nmsrs++);
2606 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2607 if (index >= 0)
8b9cf98c
RR
2608 move_msr_up(vmx, index, save_nmsrs++);
2609 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2610 if (index >= 0)
8b9cf98c 2611 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6 2612 index = __find_msr_index(vmx, MSR_TSC_AUX);
1cea0ce6 2613 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
4e47c7a6 2614 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2615 /*
8c06585d 2616 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED
2617 * if efer.sce is enabled.
2618 */
8c06585d 2619 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2620 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2621 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED
2622 }
2623#endif
92c0d900
AK
2624 index = __find_msr_index(vmx, MSR_EFER);
2625 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2626 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2627
26bb0981 2628 vmx->save_nmsrs = save_nmsrs;
5897297b 2629
8d14695f
YZ
2630 if (cpu_has_vmx_msr_bitmap())
2631 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK
2632}
2633
6aa8b732
AK
2634/*
2635 * reads and returns guest's timestamp counter "register"
be7b263e
HZ
2636 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2637 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
6aa8b732 2638 */
be7b263e 2639static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
6aa8b732
AK
2640{
2641 u64 host_tsc, tsc_offset;
2642
4ea1636b 2643 host_tsc = rdtsc();
6aa8b732 2644 tsc_offset = vmcs_read64(TSC_OFFSET);
be7b263e 2645 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
6aa8b732
AK
2646}
2647
2648/*
99e3e30a 2649 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2650 */
99e3e30a 2651static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2652{
27fc51b2 2653 if (is_guest_mode(vcpu)) {
7991825b 2654 /*
27fc51b2
NHE
2655 * We're here if L1 chose not to trap WRMSR to TSC. According
2656 * to the spec, this should set L1's TSC; The offset that L1
2657 * set for L2 remains unchanged, and still needs to be added
2658 * to the newly set TSC to get L2's TSC.
7991825b 2659 */
27fc51b2 2660 struct vmcs12 *vmcs12;
27fc51b2
NHE
2661 /* recalculate vmcs02.TSC_OFFSET: */
2662 vmcs12 = get_vmcs12(vcpu);
2663 vmcs_write64(TSC_OFFSET, offset +
2664 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2665 vmcs12->tsc_offset : 0));
2666 } else {
489223ed
YY
2667 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2668 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE
2669 vmcs_write64(TSC_OFFSET, offset);
2670 }
6aa8b732
AK
2671}
2672
801d3424
NHE
2673static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2674{
2675 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2676 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2677}
2678
2679/*
2680 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2681 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2682 * all guests if the "nested" module option is off, and can also be disabled
2683 * for a single guest by disabling its VMX cpuid bit.
2684 */
2685static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2686{
2687 return nested && guest_cpuid_has_vmx(vcpu);
2688}
2689
b87a51ae
NHE
2690/*
2691 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2692 * returned for the various VMX controls MSRs when nested VMX is enabled.
2693 * The same values should also be used to verify that vmcs12 control fields are
2694 * valid during nested entry from L1 to L2.
2695 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2696 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2697 * bit in the high half is on if the corresponding bit in the control field
2698 * may be on. See also vmx_control_verify().
b87a51ae 2699 */
b9c237bb 2700static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE
2701{
2702 /*
2703 * Note that as a general rule, the high half of the MSRs (bits in
2704 * the control fields which may be 1) should be initialized by the
2705 * intersection of the underlying hardware's MSR (i.e., features which
2706 * can be supported) and the list of features we want to expose -
2707 * because they are known to be properly supported in our code.
2708 * Also, usually, the low half of the MSRs (bits which must be 1) can
2709 * be set to 0, meaning that L1 may turn off any of these bits. The
2710 * reason is that if one of these bits is necessary, it will appear
2711 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2712 * fields of vmcs01 and vmcs02, will turn these bits off - and
7313c698 2713 * nested_vmx_exit_reflected() will not pass related exits to L1.
b87a51ae
NHE
2714 * These rules have exceptions below.
2715 */
2716
2717 /* pin-based controls */
eabeaacc 2718 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV
2719 vmx->nested.nested_vmx_pinbased_ctls_low,
2720 vmx->nested.nested_vmx_pinbased_ctls_high);
2721 vmx->nested.nested_vmx_pinbased_ctls_low |=
2722 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2723 vmx->nested.nested_vmx_pinbased_ctls_high &=
2724 PIN_BASED_EXT_INTR_MASK |
2725 PIN_BASED_NMI_EXITING |
2726 PIN_BASED_VIRTUAL_NMIS;
2727 vmx->nested.nested_vmx_pinbased_ctls_high |=
2728 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2729 PIN_BASED_VMX_PREEMPTION_TIMER;
d62caabb 2730 if (kvm_vcpu_apicv_active(&vmx->vcpu))
705699a1
WV
2731 vmx->nested.nested_vmx_pinbased_ctls_high |=
2732 PIN_BASED_POSTED_INTR;
b87a51ae 2733
3dbcd8da 2734 /* exit controls */
c0dfee58 2735 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV
2736 vmx->nested.nested_vmx_exit_ctls_low,
2737 vmx->nested.nested_vmx_exit_ctls_high);
2738 vmx->nested.nested_vmx_exit_ctls_low =
2739 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2740
b9c237bb 2741 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2742#ifdef CONFIG_X86_64
c0dfee58 2743 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2744#endif
f4124500 2745 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV
2746 vmx->nested.nested_vmx_exit_ctls_high |=
2747 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2748 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD
2749 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2750
a87036ad 2751 if (kvm_mpx_supported())
b9c237bb 2752 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2753
2996fca0 2754 /* We support free control of debug control saving. */
0115f9cb 2755 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2996fca0 2756
b87a51ae
NHE
2757 /* entry controls */
2758 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV
2759 vmx->nested.nested_vmx_entry_ctls_low,
2760 vmx->nested.nested_vmx_entry_ctls_high);
2761 vmx->nested.nested_vmx_entry_ctls_low =
2762 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2763 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK
2764#ifdef CONFIG_X86_64
2765 VM_ENTRY_IA32E_MODE |
2766#endif
2767 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV
2768 vmx->nested.nested_vmx_entry_ctls_high |=
2769 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
a87036ad 2770 if (kvm_mpx_supported())
b9c237bb 2771 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2772
2996fca0 2773 /* We support free control of debug control loading. */
0115f9cb 2774 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2996fca0 2775
b87a51ae
NHE
2776 /* cpu-based controls */
2777 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV
2778 vmx->nested.nested_vmx_procbased_ctls_low,
2779 vmx->nested.nested_vmx_procbased_ctls_high);
2780 vmx->nested.nested_vmx_procbased_ctls_low =
2781 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2782 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK
2783 CPU_BASED_VIRTUAL_INTR_PENDING |
2784 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE
2785 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2786 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2787 CPU_BASED_CR3_STORE_EXITING |
2788#ifdef CONFIG_X86_64
2789 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2790#endif
2791 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD
2792 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2793 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2794 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2795 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE
2796 /*
2797 * We can allow some features even when not supported by the
2798 * hardware. For example, L1 can specify an MSR bitmap - and we
2799 * can use it to avoid exits to L1 - even when L0 runs L2
2800 * without MSR bitmaps.
2801 */
b9c237bb
WV
2802 vmx->nested.nested_vmx_procbased_ctls_high |=
2803 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2804 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2805
3dcdf3ec 2806 /* We support free control of CR3 access interception. */
0115f9cb 2807 vmx->nested.nested_vmx_procbased_ctls_low &=
3dcdf3ec
JK
2808 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2809
b87a51ae
NHE
2810 /* secondary cpu-based controls */
2811 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV
2812 vmx->nested.nested_vmx_secondary_ctls_low,
2813 vmx->nested.nested_vmx_secondary_ctls_high);
2814 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2815 vmx->nested.nested_vmx_secondary_ctls_high &=
a5f46457 2816 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
d6851fbe 2817 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2818 SECONDARY_EXEC_RDTSCP |
1b07304c 2819 SECONDARY_EXEC_DESC |
f2b93280 2820 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2821 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2822 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7 2823 SECONDARY_EXEC_WBINVD_EXITING |
dfa169bb 2824 SECONDARY_EXEC_XSAVES;
c18911a2 2825
afa61f75
NHE
2826 if (enable_ept) {
2827 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2828 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2829 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2830 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
7db74265 2831 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
02120c45
BD
2832 if (cpu_has_vmx_ept_execute_only())
2833 vmx->nested.nested_vmx_ept_caps |=
2834 VMX_EPT_EXECUTE_ONLY_BIT;
b9c237bb 2835 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
45e11817 2836 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
7db74265
PB
2837 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2838 VMX_EPT_1GB_PAGE_BIT;
03efce6f
BD
2839 if (enable_ept_ad_bits) {
2840 vmx->nested.nested_vmx_secondary_ctls_high |=
2841 SECONDARY_EXEC_ENABLE_PML;
7461fbc4 2842 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
03efce6f 2843 }
afa61f75 2844 } else
b9c237bb 2845 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2846
ef697a71
PB
2847 /*
2848 * Old versions of KVM use the single-context version without
2849 * checking for support, so declare that it is supported even
2850 * though it is treated as global context. The alternative is
2851 * not failing the single-context invvpid, and it is worse.
2852 */
63cb6d5f
WL
2853 if (enable_vpid) {
2854 vmx->nested.nested_vmx_secondary_ctls_high |=
2855 SECONDARY_EXEC_ENABLE_VPID;
089d7b6e 2856 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
bcdde302 2857 VMX_VPID_EXTENT_SUPPORTED_MASK;
63cb6d5f 2858 } else
089d7b6e 2859 vmx->nested.nested_vmx_vpid_caps = 0;
99b83ac8 2860
0790ec17
RK
2861 if (enable_unrestricted_guest)
2862 vmx->nested.nested_vmx_secondary_ctls_high |=
2863 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2864
c18911a2 2865 /* miscellaneous data */
b9c237bb
WV
2866 rdmsr(MSR_IA32_VMX_MISC,
2867 vmx->nested.nested_vmx_misc_low,
2868 vmx->nested.nested_vmx_misc_high);
2869 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2870 vmx->nested.nested_vmx_misc_low |=
2871 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2872 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2873 vmx->nested.nested_vmx_misc_high = 0;
62cc6b9d
DM
2874
2875 /*
2876 * This MSR reports some information about VMX support. We
2877 * should return information about the VMX we emulate for the
2878 * guest, and the VMCS structure we give it - not about the
2879 * VMX support of the underlying hardware.
2880 */
2881 vmx->nested.nested_vmx_basic =
2882 VMCS12_REVISION |
2883 VMX_BASIC_TRUE_CTLS |
2884 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2885 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2886
2887 if (cpu_has_vmx_basic_inout())
2888 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2889
2890 /*
8322ebbb 2891 * These MSRs specify bits which the guest must keep fixed on
62cc6b9d
DM
2892 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2893 * We picked the standard core2 setting.
2894 */
2895#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2896#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2897 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
62cc6b9d 2898 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
8322ebbb
DM
2899
2900 /* These MSRs specify bits which the guest must keep fixed off. */
2901 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2902 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
62cc6b9d
DM
2903
2904 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2905 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
b87a51ae
NHE
2906}
2907
3899152c
DM
2908/*
2909 * if fixed0[i] == 1: val[i] must be 1
2910 * if fixed1[i] == 0: val[i] must be 0
2911 */
2912static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2913{
2914 return ((val & fixed1) | fixed0) == val;
b87a51ae
NHE
2915}
2916
2917static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2918{
3899152c 2919 return fixed_bits_valid(control, low, high);
b87a51ae
NHE
2920}
2921
2922static inline u64 vmx_control_msr(u32 low, u32 high)
2923{
2924 return low | ((u64)high << 32);
2925}
2926
62cc6b9d
DM
2927static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2928{
2929 superset &= mask;
2930 subset &= mask;
2931
2932 return (superset | subset) == superset;
2933}
2934
2935static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2936{
2937 const u64 feature_and_reserved =
2938 /* feature (except bit 48; see below) */
2939 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2940 /* reserved */
2941 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2942 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2943
2944 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2945 return -EINVAL;
2946
2947 /*
2948 * KVM does not emulate a version of VMX that constrains physical
2949 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2950 */
2951 if (data & BIT_ULL(48))
2952 return -EINVAL;
2953
2954 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2955 vmx_basic_vmcs_revision_id(data))
2956 return -EINVAL;
2957
2958 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2959 return -EINVAL;
2960
2961 vmx->nested.nested_vmx_basic = data;
2962 return 0;
2963}
2964
2965static int
2966vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2967{
2968 u64 supported;
2969 u32 *lowp, *highp;
2970
2971 switch (msr_index) {
2972 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2973 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2974 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2975 break;
2976 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2977 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2978 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2979 break;
2980 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2981 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2982 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2983 break;
2984 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2985 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2986 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2987 break;
2988 case MSR_IA32_VMX_PROCBASED_CTLS2:
2989 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2990 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2991 break;
2992 default:
2993 BUG();
2994 }
2995
2996 supported = vmx_control_msr(*lowp, *highp);
2997
2998 /* Check must-be-1 bits are still 1. */
2999 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3000 return -EINVAL;
3001
3002 /* Check must-be-0 bits are still 0. */
3003 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3004 return -EINVAL;
3005
3006 *lowp = data;
3007 *highp = data >> 32;
3008 return 0;
3009}
3010
3011static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3012{
3013 const u64 feature_and_reserved_bits =
3014 /* feature */
3015 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3016 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3017 /* reserved */
3018 GENMASK_ULL(13, 9) | BIT_ULL(31);
3019 u64 vmx_misc;
3020
3021 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3022 vmx->nested.nested_vmx_misc_high);
3023
3024 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3025 return -EINVAL;
3026
3027 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3028 PIN_BASED_VMX_PREEMPTION_TIMER) &&
3029 vmx_misc_preemption_timer_rate(data) !=
3030 vmx_misc_preemption_timer_rate(vmx_misc))
3031 return -EINVAL;
3032
3033 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3034 return -EINVAL;
3035
3036 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3037 return -EINVAL;
3038
3039 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3040 return -EINVAL;
3041
3042 vmx->nested.nested_vmx_misc_low = data;
3043 vmx->nested.nested_vmx_misc_high = data >> 32;
3044 return 0;
3045}
3046
3047static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3048{
3049 u64 vmx_ept_vpid_cap;
3050
3051 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3052 vmx->nested.nested_vmx_vpid_caps);
3053
3054 /* Every bit is either reserved or a feature bit. */
3055 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3056 return -EINVAL;
3057
3058 vmx->nested.nested_vmx_ept_caps = data;
3059 vmx->nested.nested_vmx_vpid_caps = data >> 32;
3060 return 0;
3061}
3062
3063static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3064{
3065 u64 *msr;
3066
3067 switch (msr_index) {
3068 case MSR_IA32_VMX_CR0_FIXED0:
3069 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3070 break;
3071 case MSR_IA32_VMX_CR4_FIXED0:
3072 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3073 break;
3074 default:
3075 BUG();
3076 }
3077
3078 /*
3079 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3080 * must be 1 in the restored value.
3081 */
3082 if (!is_bitwise_subset(data, *msr, -1ULL))
3083 return -EINVAL;
3084
3085 *msr = data;
3086 return 0;
3087}
3088
3089/*
3090 * Called when userspace is restoring VMX MSRs.
3091 *
3092 * Returns 0 on success, non-0 otherwise.
3093 */
3094static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
b87a51ae 3095{
b9c237bb
WV
3096 struct vcpu_vmx *vmx = to_vmx(vcpu);
3097
b87a51ae 3098 switch (msr_index) {
b87a51ae 3099 case MSR_IA32_VMX_BASIC:
62cc6b9d
DM
3100 return vmx_restore_vmx_basic(vmx, data);
3101 case MSR_IA32_VMX_PINBASED_CTLS:
3102 case MSR_IA32_VMX_PROCBASED_CTLS:
3103 case MSR_IA32_VMX_EXIT_CTLS:
3104 case MSR_IA32_VMX_ENTRY_CTLS:
b87a51ae 3105 /*
62cc6b9d
DM
3106 * The "non-true" VMX capability MSRs are generated from the
3107 * "true" MSRs, so we do not support restoring them directly.
3108 *
3109 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3110 * should restore the "true" MSRs with the must-be-1 bits
3111 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3112 * DEFAULT SETTINGS".
b87a51ae 3113 */
62cc6b9d
DM
3114 return -EINVAL;
3115 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3116 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3117 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3118 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3119 case MSR_IA32_VMX_PROCBASED_CTLS2:
3120 return vmx_restore_control_msr(vmx, msr_index, data);
3121 case MSR_IA32_VMX_MISC:
3122 return vmx_restore_vmx_misc(vmx, data);
3123 case MSR_IA32_VMX_CR0_FIXED0:
3124 case MSR_IA32_VMX_CR4_FIXED0:
3125 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3126 case MSR_IA32_VMX_CR0_FIXED1:
3127 case MSR_IA32_VMX_CR4_FIXED1:
3128 /*
3129 * These MSRs are generated based on the vCPU's CPUID, so we
3130 * do not support restoring them directly.
3131 */
3132 return -EINVAL;
3133 case MSR_IA32_VMX_EPT_VPID_CAP:
3134 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3135 case MSR_IA32_VMX_VMCS_ENUM:
3136 vmx->nested.nested_vmx_vmcs_enum = data;
3137 return 0;
3138 default:
b87a51ae 3139 /*
62cc6b9d 3140 * The rest of the VMX capability MSRs do not support restore.
b87a51ae 3141 */
62cc6b9d
DM
3142 return -EINVAL;
3143 }
3144}
3145
3146/* Returns 0 on success, non-0 otherwise. */
3147static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3148{
3149 struct vcpu_vmx *vmx = to_vmx(vcpu);
3150
3151 switch (msr_index) {
3152 case MSR_IA32_VMX_BASIC:
3153 *pdata = vmx->nested.nested_vmx_basic;
b87a51ae
NHE
3154 break;
3155 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3156 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV
3157 *pdata = vmx_control_msr(
3158 vmx->nested.nested_vmx_pinbased_ctls_low,
3159 vmx->nested.nested_vmx_pinbased_ctls_high);
0115f9cb
DM
3160 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3161 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3162 break;
3163 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3164 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV
3165 *pdata = vmx_control_msr(
3166 vmx->nested.nested_vmx_procbased_ctls_low,
3167 vmx->nested.nested_vmx_procbased_ctls_high);
0115f9cb
DM
3168 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3169 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3170 break;
3171 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3172 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV
3173 *pdata = vmx_control_msr(
3174 vmx->nested.nested_vmx_exit_ctls_low,
3175 vmx->nested.nested_vmx_exit_ctls_high);
0115f9cb
DM
3176 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3177 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3178 break;
3179 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3180 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV
3181 *pdata = vmx_control_msr(
3182 vmx->nested.nested_vmx_entry_ctls_low,
3183 vmx->nested.nested_vmx_entry_ctls_high);
0115f9cb
DM
3184 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3185 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3186 break;
3187 case MSR_IA32_VMX_MISC:
b9c237bb
WV
3188 *pdata = vmx_control_msr(
3189 vmx->nested.nested_vmx_misc_low,
3190 vmx->nested.nested_vmx_misc_high);
b87a51ae 3191 break;
b87a51ae 3192 case MSR_IA32_VMX_CR0_FIXED0:
62cc6b9d 3193 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
b87a51ae
NHE
3194 break;
3195 case MSR_IA32_VMX_CR0_FIXED1:
62cc6b9d 3196 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
b87a51ae
NHE
3197 break;
3198 case MSR_IA32_VMX_CR4_FIXED0:
62cc6b9d 3199 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
b87a51ae
NHE
3200 break;
3201 case MSR_IA32_VMX_CR4_FIXED1:
62cc6b9d 3202 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
b87a51ae
NHE
3203 break;
3204 case MSR_IA32_VMX_VMCS_ENUM:
62cc6b9d 3205 *pdata = vmx->nested.nested_vmx_vmcs_enum;
b87a51ae
NHE
3206 break;
3207 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV
3208 *pdata = vmx_control_msr(
3209 vmx->nested.nested_vmx_secondary_ctls_low,
3210 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE
3211 break;
3212 case MSR_IA32_VMX_EPT_VPID_CAP:
089d7b6e
WL
3213 *pdata = vmx->nested.nested_vmx_ept_caps |
3214 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
b87a51ae
NHE
3215 break;
3216 default:
b87a51ae 3217 return 1;
b3897a49
NHE
3218 }
3219
b87a51ae
NHE
3220 return 0;
3221}
3222
37e4c997
HZ
3223static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3224 uint64_t val)
3225{
3226 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3227
3228 return !(val & ~valid_bits);
3229}
3230
6aa8b732
AK
3231/*
3232 * Reads an msr value (of 'msr_index') into 'pdata'.
3233 * Returns 0 on success, non-0 otherwise.
3234 * Assumes vcpu_load() was already called.
3235 */
609e36d3 3236static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 3237{
26bb0981 3238 struct shared_msr_entry *msr;
6aa8b732 3239
609e36d3 3240 switch (msr_info->index) {
05b3e0c2 3241#ifdef CONFIG_X86_64
6aa8b732 3242 case MSR_FS_BASE:
609e36d3 3243 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK
3244 break;
3245 case MSR_GS_BASE:
609e36d3 3246 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 3247 break;
44ea2b17
AK
3248 case MSR_KERNEL_GS_BASE:
3249 vmx_load_host_state(to_vmx(vcpu));
609e36d3 3250 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 3251 break;
26bb0981 3252#endif
6aa8b732 3253 case MSR_EFER:
609e36d3 3254 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 3255 case MSR_IA32_TSC:
be7b263e 3256 msr_info->data = guest_read_tsc(vcpu);
6aa8b732
AK
3257 break;
3258 case MSR_IA32_SYSENTER_CS:
609e36d3 3259 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK
3260 break;
3261 case MSR_IA32_SYSENTER_EIP:
609e36d3 3262 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK
3263 break;
3264 case MSR_IA32_SYSENTER_ESP:
609e36d3 3265 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 3266 break;
0dd376e7 3267 case MSR_IA32_BNDCFGS:
691bd434
HZ
3268 if (!kvm_mpx_supported() ||
3269 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
93c4adc7 3270 return 1;
609e36d3 3271 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 3272 break;
c45dcc71
AR
3273 case MSR_IA32_MCG_EXT_CTL:
3274 if (!msr_info->host_initiated &&
3275 !(to_vmx(vcpu)->msr_ia32_feature_control &
3276 FEATURE_CONTROL_LMCE))
cae50139 3277 return 1;
c45dcc71
AR
3278 msr_info->data = vcpu->arch.mcg_ext_ctl;
3279 break;
cae50139 3280 case MSR_IA32_FEATURE_CONTROL:
3b84080b 3281 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
cae50139
JK
3282 break;
3283 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3284 if (!nested_vmx_allowed(vcpu))
3285 return 1;
609e36d3 3286 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL
3287 case MSR_IA32_XSS:
3288 if (!vmx_xsaves_supported())
3289 return 1;
609e36d3 3290 msr_info->data = vcpu->arch.ia32_xss;
20300099 3291 break;
4e47c7a6 3292 case MSR_TSC_AUX:
81b1b9ca 3293 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
4e47c7a6
SY
3294 return 1;
3295 /* Otherwise falls through */
6aa8b732 3296 default:
609e36d3 3297 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 3298 if (msr) {
609e36d3 3299 msr_info->data = msr->data;
3bab1f5d 3300 break;
6aa8b732 3301 }
609e36d3 3302 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK
3303 }
3304
6aa8b732
AK
3305 return 0;
3306}
3307
cae50139
JK
3308static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3309
6aa8b732
AK
3310/*
3311 * Writes msr value into into the appropriate "register".
3312 * Returns 0 on success, non-0 otherwise.
3313 * Assumes vcpu_load() was already called.
3314 */
8fe8ab46 3315static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 3316{
a2fa3e9f 3317 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 3318 struct shared_msr_entry *msr;
2cc51560 3319 int ret = 0;
8fe8ab46
WA
3320 u32 msr_index = msr_info->index;
3321 u64 data = msr_info->data;
2cc51560 3322
6aa8b732 3323 switch (msr_index) {
3bab1f5d 3324 case MSR_EFER:
8fe8ab46 3325 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 3326 break;
16175a79 3327#ifdef CONFIG_X86_64
6aa8b732 3328 case MSR_FS_BASE:
2fb92db1 3329 vmx_segment_cache_clear(vmx);
6aa8b732
AK
3330 vmcs_writel(GUEST_FS_BASE, data);
3331 break;
3332 case MSR_GS_BASE:
2fb92db1 3333 vmx_segment_cache_clear(vmx);
6aa8b732
AK
3334 vmcs_writel(GUEST_GS_BASE, data);
3335 break;
44ea2b17
AK
3336 case MSR_KERNEL_GS_BASE:
3337 vmx_load_host_state(vmx);
3338 vmx->msr_guest_kernel_gs_base = data;
3339 break;
6aa8b732
AK
3340#endif
3341 case MSR_IA32_SYSENTER_CS:
3342 vmcs_write32(GUEST_SYSENTER_CS, data);
3343 break;
3344 case MSR_IA32_SYSENTER_EIP:
f5b42c33 3345 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK
3346 break;
3347 case MSR_IA32_SYSENTER_ESP:
f5b42c33 3348 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 3349 break;
0dd376e7 3350 case MSR_IA32_BNDCFGS:
691bd434
HZ
3351 if (!kvm_mpx_supported() ||
3352 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
93c4adc7 3353 return 1;
4531662d
JM
3354 if (is_noncanonical_address(data & PAGE_MASK) ||
3355 (data & MSR_IA32_BNDCFGS_RSVD))
93c4adc7 3356 return 1;
0dd376e7
LJ
3357 vmcs_write64(GUEST_BNDCFGS, data);
3358 break;
af24a4e4 3359 case MSR_IA32_TSC:
8fe8ab46 3360 kvm_write_tsc(vcpu, msr_info);
6aa8b732 3361 break;
468d472f
SY
3362 case MSR_IA32_CR_PAT:
3363 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA
3364 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3365 return 1;
468d472f
SY
3366 vmcs_write64(GUEST_IA32_PAT, data);
3367 vcpu->arch.pat = data;
3368 break;
3369 }
8fe8ab46 3370 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 3371 break;
ba904635
WA
3372 case MSR_IA32_TSC_ADJUST:
3373 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 3374 break;
c45dcc71
AR
3375 case MSR_IA32_MCG_EXT_CTL:
3376 if ((!msr_info->host_initiated &&
3377 !(to_vmx(vcpu)->msr_ia32_feature_control &
3378 FEATURE_CONTROL_LMCE)) ||
3379 (data & ~MCG_EXT_CTL_LMCE_EN))
3380 return 1;
3381 vcpu->arch.mcg_ext_ctl = data;
3382 break;
cae50139 3383 case MSR_IA32_FEATURE_CONTROL:
37e4c997 3384 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 3385 (to_vmx(vcpu)->msr_ia32_feature_control &
cae50139
JK
3386 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3387 return 1;
3b84080b 3388 vmx->msr_ia32_feature_control = data;
cae50139
JK
3389 if (msr_info->host_initiated && data == 0)
3390 vmx_leave_nested(vcpu);
3391 break;
3392 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM
3393 if (!msr_info->host_initiated)
3394 return 1; /* they are read-only */
3395 if (!nested_vmx_allowed(vcpu))
3396 return 1;
3397 return vmx_set_vmx_msr(vcpu, msr_index, data);
20300099
WL
3398 case MSR_IA32_XSS:
3399 if (!vmx_xsaves_supported())
3400 return 1;
3401 /*
3402 * The only supported bit as of Skylake is bit 8, but
3403 * it is not supported on KVM.
3404 */
3405 if (data != 0)
3406 return 1;
3407 vcpu->arch.ia32_xss = data;
3408 if (vcpu->arch.ia32_xss != host_xss)
3409 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3410 vcpu->arch.ia32_xss, host_xss);
3411 else
3412 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3413 break;
4e47c7a6 3414 case MSR_TSC_AUX:
81b1b9ca 3415 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
4e47c7a6
SY
3416 return 1;
3417 /* Check reserved bit, higher 32 bits should be zero */
3418 if ((data >> 32) != 0)
3419 return 1;
3420 /* Otherwise falls through */
6aa8b732 3421 default:
8b9cf98c 3422 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 3423 if (msr) {
8b3c3104 3424 u64 old_msr_data = msr->data;
3bab1f5d 3425 msr->data = data;
2225fd56
AK
3426 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3427 preempt_disable();
8b3c3104
AH
3428 ret = kvm_set_shared_msr(msr->index, msr->data,
3429 msr->mask);
2225fd56 3430 preempt_enable();
8b3c3104
AH
3431 if (ret)
3432 msr->data = old_msr_data;
2225fd56 3433 }
3bab1f5d 3434 break;
6aa8b732 3435 }
8fe8ab46 3436 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK
3437 }
3438
2cc51560 3439 return ret;
6aa8b732
AK
3440}
3441
5fdbf976 3442static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 3443{
5fdbf976
MT
3444 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3445 switch (reg) {
3446 case VCPU_REGS_RSP:
3447 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3448 break;
3449 case VCPU_REGS_RIP:
3450 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3451 break;
6de4f3ad
AK
3452 case VCPU_EXREG_PDPTR:
3453 if (enable_ept)
3454 ept_save_pdptrs(vcpu);
3455 break;
5fdbf976
MT
3456 default:
3457 break;
3458 }
6aa8b732
AK
3459}
3460
6aa8b732
AK
3461static __init int cpu_has_kvm_support(void)
3462{
6210e37b 3463 return cpu_has_vmx();
6aa8b732
AK
3464}
3465
3466static __init int vmx_disabled_by_bios(void)
3467{
3468 u64 msr;
3469
3470 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 3471 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 3472 /* launched w/ TXT and VMX disabled */
cafd6659
SW
3473 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3474 && tboot_enabled())
3475 return 1;
23f3e991 3476 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 3477 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 3478 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW
3479 && !tboot_enabled()) {
3480 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 3481 "activate TXT before enabling KVM\n");
cafd6659 3482 return 1;
f9335afe 3483 }
23f3e991
JC
3484 /* launched w/o TXT and VMX disabled */
3485 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3486 && !tboot_enabled())
3487 return 1;
cafd6659
SW
3488 }
3489
3490 return 0;
6aa8b732
AK
3491}
3492
7725b894
DX
3493static void kvm_cpu_vmxon(u64 addr)
3494{
fe0e80be 3495 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS
3496 intel_pt_handle_vmx(1);
3497
7725b894
DX
3498 asm volatile (ASM_VMX_VMXON_RAX
3499 : : "a"(&addr), "m"(addr)
3500 : "memory", "cc");
3501}
3502
13a34e06 3503static int hardware_enable(void)
6aa8b732
AK
3504{
3505 int cpu = raw_smp_processor_id();
3506 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 3507 u64 old, test_bits;
6aa8b732 3508
1e02ce4c 3509 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG
3510 return -EBUSY;
3511
d462b819 3512 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW
3513 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3514 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY
3515
3516 /*
3517 * Now we can enable the vmclear operation in kdump
3518 * since the loaded_vmcss_on_cpu list on this cpu
3519 * has been initialized.
3520 *
3521 * Though the cpu is not in VMX operation now, there
3522 * is no problem to enable the vmclear operation
3523 * for the loaded_vmcss_on_cpu list is empty!
3524 */
3525 crash_enable_local_vmclear(cpu);
3526
6aa8b732 3527 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW
3528
3529 test_bits = FEATURE_CONTROL_LOCKED;
3530 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3531 if (tboot_enabled())
3532 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3533
3534 if ((old & test_bits) != test_bits) {
6aa8b732 3535 /* enable and lock */
cafd6659
SW
3536 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3537 }
fe0e80be
DH
3538 kvm_cpu_vmxon(phys_addr);
3539 ept_sync_global();
10474ae8
AG
3540
3541 return 0;
6aa8b732
AK
3542}
3543
d462b819 3544static void vmclear_local_loaded_vmcss(void)
543e4243
AK
3545{
3546 int cpu = raw_smp_processor_id();
d462b819 3547 struct loaded_vmcs *v, *n;
543e4243 3548
d462b819
NHE
3549 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3550 loaded_vmcss_on_cpu_link)
3551 __loaded_vmcs_clear(v);
543e4243
AK
3552}
3553
710ff4a8
EH
3554
3555/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3556 * tricks.
3557 */
3558static void kvm_cpu_vmxoff(void)
6aa8b732 3559{
4ecac3fd 3560 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1c5ac21a
AS
3561
3562 intel_pt_handle_vmx(0);
fe0e80be 3563 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK
3564}
3565
13a34e06 3566static void hardware_disable(void)
710ff4a8 3567{
fe0e80be
DH
3568 vmclear_local_loaded_vmcss();
3569 kvm_cpu_vmxoff();
710ff4a8
EH
3570}
3571
1c3d14fe 3572static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 3573 u32 msr, u32 *result)
1c3d14fe
YS
3574{
3575 u32 vmx_msr_low, vmx_msr_high;
3576 u32 ctl = ctl_min | ctl_opt;
3577
3578 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3579
3580 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3581 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3582
3583 /* Ensure minimum (required) set of control bits are supported. */
3584 if (ctl_min & ~ctl)
002c7f7c 3585 return -EIO;
1c3d14fe
YS
3586
3587 *result = ctl;
3588 return 0;
3589}
3590
110312c8
AK
3591static __init bool allow_1_setting(u32 msr, u32 ctl)
3592{
3593 u32 vmx_msr_low, vmx_msr_high;
3594
3595 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3596 return vmx_msr_high & ctl;
3597}
3598
002c7f7c 3599static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK
3600{
3601 u32 vmx_msr_low, vmx_msr_high;
d56f546d 3602 u32 min, opt, min2, opt2;
1c3d14fe
YS
3603 u32 _pin_based_exec_control = 0;
3604 u32 _cpu_based_exec_control = 0;
f78e0e2e 3605 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS
3606 u32 _vmexit_control = 0;
3607 u32 _vmentry_control = 0;
3608
10166744 3609 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS
3610#ifdef CONFIG_X86_64
3611 CPU_BASED_CR8_LOAD_EXITING |
3612 CPU_BASED_CR8_STORE_EXITING |
3613#endif
d56f546d
SY
3614 CPU_BASED_CR3_LOAD_EXITING |
3615 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS
3616 CPU_BASED_USE_IO_BITMAPS |
3617 CPU_BASED_MOV_DR_EXITING |
a7052897 3618 CPU_BASED_USE_TSC_OFFSETING |
fee84b07
AK
3619 CPU_BASED_INVLPG_EXITING |
3620 CPU_BASED_RDPMC_EXITING;
443381a8 3621
668fffa3
MT
3622 if (!kvm_mwait_in_guest())
3623 min |= CPU_BASED_MWAIT_EXITING |
3624 CPU_BASED_MONITOR_EXITING;
3625
f78e0e2e 3626 opt = CPU_BASED_TPR_SHADOW |
25c5f225 3627 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 3628 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS
3629 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3630 &_cpu_based_exec_control) < 0)
002c7f7c 3631 return -EIO;
6e5d865c
YS
3632#ifdef CONFIG_X86_64
3633 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3634 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3635 ~CPU_BASED_CR8_STORE_EXITING;
3636#endif
f78e0e2e 3637 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY
3638 min2 = 0;
3639 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3640 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3641 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3642 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3643 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3644 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3645 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3646 SECONDARY_EXEC_RDTSCP |
83d4c286 3647 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3648 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3649 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3650 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 3651 SECONDARY_EXEC_XSAVES |
8b3e34e4 3652 SECONDARY_EXEC_ENABLE_PML |
64903d61 3653 SECONDARY_EXEC_TSC_SCALING;
d56f546d
SY
3654 if (adjust_vmx_controls(min2, opt2,
3655 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY
3656 &_cpu_based_2nd_exec_control) < 0)
3657 return -EIO;
3658 }
3659#ifndef CONFIG_X86_64
3660 if (!(_cpu_based_2nd_exec_control &
3661 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3662 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3663#endif
83d4c286
YZ
3664
3665 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3666 _cpu_based_2nd_exec_control &= ~(
8d14695f 3667 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ
3668 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3669 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3670
d56f546d 3671 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT
3672 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3673 enabled */
5fff7d27
GN
3674 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3675 CPU_BASED_CR3_STORE_EXITING |
3676 CPU_BASED_INVLPG_EXITING);
d56f546d
SY
3677 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3678 vmx_capability.ept, vmx_capability.vpid);
3679 }
1c3d14fe 3680
91fa0f8e 3681 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS
3682#ifdef CONFIG_X86_64
3683 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3684#endif
a547c6db 3685 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
91fa0f8e 3686 VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS
3687 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3688 &_vmexit_control) < 0)
002c7f7c 3689 return -EIO;
1c3d14fe 3690
2c82878b
PB
3691 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3692 PIN_BASED_VIRTUAL_NMIS;
3693 opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ
3694 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3695 &_pin_based_exec_control) < 0)
3696 return -EIO;
3697
1c17c3e6
PB
3698 if (cpu_has_broken_vmx_preemption_timer())
3699 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 3700 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 3701 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ
3702 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3703
c845f9c6 3704 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3705 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS
3706 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3707 &_vmentry_control) < 0)
002c7f7c 3708 return -EIO;
6aa8b732 3709
c68876fd 3710 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS
3711
3712 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3713 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3714 return -EIO;
1c3d14fe
YS
3715
3716#ifdef CONFIG_X86_64
3717 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3718 if (vmx_msr_high & (1u<<16))
002c7f7c 3719 return -EIO;
1c3d14fe
YS
3720#endif
3721
3722 /* Require Write-Back (WB) memory type for VMCS accesses. */
3723 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3724 return -EIO;
1c3d14fe 3725
002c7f7c 3726 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 3727 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 3728 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
002c7f7c 3729 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3730
002c7f7c
YS
3731 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3732 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3733 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS
3734 vmcs_conf->vmexit_ctrl = _vmexit_control;
3735 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3736
110312c8
AK
3737 cpu_has_load_ia32_efer =
3738 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3739 VM_ENTRY_LOAD_IA32_EFER)
3740 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3741 VM_EXIT_LOAD_IA32_EFER);
3742
8bf00a52
GN
3743 cpu_has_load_perf_global_ctrl =
3744 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3745 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3746 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3747 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3748
3749 /*
3750 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
bb3541f1 3751 * but due to errata below it can't be used. Workaround is to use
8bf00a52
GN
3752 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3753 *
3754 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3755 *
3756 * AAK155 (model 26)
3757 * AAP115 (model 30)
3758 * AAT100 (model 37)
3759 * BC86,AAY89,BD102 (model 44)
3760 * BA97 (model 46)
3761 *
3762 */
3763 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3764 switch (boot_cpu_data.x86_model) {
3765 case 26:
3766 case 30:
3767 case 37:
3768 case 44:
3769 case 46:
3770 cpu_has_load_perf_global_ctrl = false;
3771 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3772 "does not work properly. Using workaround\n");
3773 break;
3774 default:
3775 break;
3776 }
3777 }
3778
782511b0 3779 if (boot_cpu_has(X86_FEATURE_XSAVES))
20300099
WL
3780 rdmsrl(MSR_IA32_XSS, host_xss);
3781
1c3d14fe 3782 return 0;
c68876fd 3783}
6aa8b732
AK
3784
3785static struct vmcs *alloc_vmcs_cpu(int cpu)
3786{
3787 int node = cpu_to_node(cpu);
3788 struct page *pages;
3789 struct vmcs *vmcs;
3790
96db800f 3791 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK
3792 if (!pages)
3793 return NULL;
3794 vmcs = page_address(pages);
1c3d14fe
YS
3795 memset(vmcs, 0, vmcs_config.size);
3796 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK
3797 return vmcs;
3798}
3799
3800static struct vmcs *alloc_vmcs(void)
3801{
d3b2c338 3802 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK
3803}
3804
3805static void free_vmcs(struct vmcs *vmcs)
3806{
1c3d14fe 3807 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK
3808}
3809
d462b819
NHE
3810/*
3811 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3812 */
3813static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3814{
3815 if (!loaded_vmcs->vmcs)
3816 return;
3817 loaded_vmcs_clear(loaded_vmcs);
3818 free_vmcs(loaded_vmcs->vmcs);
3819 loaded_vmcs->vmcs = NULL;
355f4fb1 3820 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE
3821}
3822
39959588 3823static void free_kvm_area(void)
6aa8b732
AK
3824{
3825 int cpu;
3826
3230bb47 3827 for_each_possible_cpu(cpu) {
6aa8b732 3828 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA
3829 per_cpu(vmxarea, cpu) = NULL;
3830 }
6aa8b732
AK
3831}
3832
85fd514e
JM
3833enum vmcs_field_type {
3834 VMCS_FIELD_TYPE_U16 = 0,
3835 VMCS_FIELD_TYPE_U64 = 1,
3836 VMCS_FIELD_TYPE_U32 = 2,
3837 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3838};
3839
3840static inline int vmcs_field_type(unsigned long field)
3841{
3842 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
3843 return VMCS_FIELD_TYPE_U32;
3844 return (field >> 13) & 0x3 ;
3845}
3846
3847static inline int vmcs_field_readonly(unsigned long field)
3848{
3849 return (((field >> 10) & 0x3) == 1);
3850}
3851
fe2b201b
BD
3852static void init_vmcs_shadow_fields(void)
3853{
3854 int i, j;
3855
3856 /* No checks for read only fields yet */
3857
3858 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3859 switch (shadow_read_write_fields[i]) {
3860 case GUEST_BNDCFGS:
a87036ad 3861 if (!kvm_mpx_supported())
fe2b201b
BD
3862 continue;
3863 break;
3864 default:
3865 break;
3866 }
3867
3868 if (j < i)
3869 shadow_read_write_fields[j] =
3870 shadow_read_write_fields[i];
3871 j++;
3872 }
3873 max_shadow_read_write_fields = j;
3874
3875 /* shadowed fields guest access without vmexit */
3876 for (i = 0; i < max_shadow_read_write_fields; i++) {
85fd514e
JM
3877 unsigned long field = shadow_read_write_fields[i];
3878
3879 clear_bit(field, vmx_vmwrite_bitmap);
3880 clear_bit(field, vmx_vmread_bitmap);
3881 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
3882 clear_bit(field + 1, vmx_vmwrite_bitmap);
3883 clear_bit(field + 1, vmx_vmread_bitmap);
3884 }
3885 }
3886 for (i = 0; i < max_shadow_read_only_fields; i++) {
3887 unsigned long field = shadow_read_only_fields[i];
3888
3889 clear_bit(field, vmx_vmread_bitmap);
3890 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
3891 clear_bit(field + 1, vmx_vmread_bitmap);
fe2b201b 3892 }
fe2b201b
BD
3893}
3894
6aa8b732
AK
3895static __init int alloc_kvm_area(void)
3896{
3897 int cpu;
3898
3230bb47 3899 for_each_possible_cpu(cpu) {
6aa8b732
AK
3900 struct vmcs *vmcs;
3901
3902 vmcs = alloc_vmcs_cpu(cpu);
3903 if (!vmcs) {
3904 free_kvm_area();
3905 return -ENOMEM;
3906 }
3907
3908 per_cpu(vmxarea, cpu) = vmcs;
3909 }
3910 return 0;
3911}
3912
91b0aa2c 3913static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3914 struct kvm_segment *save)
6aa8b732 3915{
d99e4152
GN
3916 if (!emulate_invalid_guest_state) {
3917 /*
3918 * CS and SS RPL should be equal during guest entry according
3919 * to VMX spec, but in reality it is not always so. Since vcpu
3920 * is in the middle of the transition from real mode to
3921 * protected mode it is safe to assume that RPL 0 is a good
3922 * default value.
3923 */
3924 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA
3925 save->selector &= ~SEGMENT_RPL_MASK;
3926 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3927 save->s = 1;
6aa8b732 3928 }
d99e4152 3929 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK
3930}
3931
3932static void enter_pmode(struct kvm_vcpu *vcpu)
3933{
3934 unsigned long flags;
a89a8fb9 3935 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3936
d99e4152
GN
3937 /*
3938 * Update real mode segment cache. It may be not up-to-date if sement
3939 * register was written while vcpu was in a guest mode.
3940 */
3941 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3942 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3943 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3944 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3945 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3946 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3947
7ffd92c5 3948 vmx->rmode.vm86_active = 0;
6aa8b732 3949
2fb92db1
AK
3950 vmx_segment_cache_clear(vmx);
3951
f5f7b2fe 3952 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK
3953
3954 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK
3955 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3956 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK
3957 vmcs_writel(GUEST_RFLAGS, flags);
3958
66aee91a
RR
3959 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3960 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK
3961
3962 update_exception_bitmap(vcpu);
3963
91b0aa2c
GN
3964 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3965 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3966 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3967 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3968 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3969 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK
3970}
3971
f5f7b2fe 3972static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3973{
772e0318 3974 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN
3975 struct kvm_segment var = *save;
3976
3977 var.dpl = 0x3;
3978 if (seg == VCPU_SREG_CS)
3979 var.type = 0x3;
3980
3981 if (!emulate_invalid_guest_state) {
3982 var.selector = var.base >> 4;
3983 var.base = var.base & 0xffff0;
3984 var.limit = 0xffff;
3985 var.g = 0;
3986 var.db = 0;
3987 var.present = 1;
3988 var.s = 1;
3989 var.l = 0;
3990 var.unusable = 0;
3991 var.type = 0x3;
3992 var.avl = 0;
3993 if (save->base & 0xf)
3994 printk_once(KERN_WARNING "kvm: segment base is not "
3995 "paragraph aligned when entering "
3996 "protected mode (seg=%d)", seg);
3997 }
6aa8b732 3998
d99e4152 3999 vmcs_write16(sf->selector, var.selector);
96794e4e 4000 vmcs_writel(sf->base, var.base);
d99e4152
GN
4001 vmcs_write32(sf->limit, var.limit);
4002 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK
4003}
4004
4005static void enter_rmode(struct kvm_vcpu *vcpu)
4006{
4007 unsigned long flags;
a89a8fb9 4008 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 4009
f5f7b2fe
AK
4010 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4011 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4012 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4013 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4014 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN
4015 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4016 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 4017
7ffd92c5 4018 vmx->rmode.vm86_active = 1;
6aa8b732 4019
776e58ea
GN
4020 /*
4021 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 4022 * vcpu. Warn the user that an update is overdue.
776e58ea 4023 */
4918c6ca 4024 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN
4025 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4026 "called before entering vcpu\n");
776e58ea 4027
2fb92db1
AK
4028 vmx_segment_cache_clear(vmx);
4029
4918c6ca 4030 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 4031 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK
4032 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4033
4034 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 4035 vmx->rmode.save_rflags = flags;
6aa8b732 4036
053de044 4037 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK
4038
4039 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 4040 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK
4041 update_exception_bitmap(vcpu);
4042
d99e4152
GN
4043 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4044 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4045 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4046 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4047 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4048 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 4049
8668a3c4 4050 kvm_mmu_reset_context(vcpu);
6aa8b732
AK
4051}
4052
401d10de
AS
4053static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4054{
4055 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK
4056 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4057
4058 if (!msr)
4059 return;
401d10de 4060
44ea2b17
AK
4061 /*
4062 * Force kernel_gs_base reloading before EFER changes, as control
4063 * of this msr depends on is_long_mode().
4064 */
4065 vmx_load_host_state(to_vmx(vcpu));
f6801dff 4066 vcpu->arch.efer = efer;
401d10de 4067 if (efer & EFER_LMA) {
2961e876 4068 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS
4069 msr->data = efer;
4070 } else {
2961e876 4071 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS
4072
4073 msr->data = efer & ~EFER_LME;
4074 }
4075 setup_msrs(vmx);
4076}
4077
05b3e0c2 4078#ifdef CONFIG_X86_64
6aa8b732
AK
4079
4080static void enter_lmode(struct kvm_vcpu *vcpu)
4081{
4082 u32 guest_tr_ar;
4083
2fb92db1
AK
4084 vmx_segment_cache_clear(to_vmx(vcpu));
4085
6aa8b732 4086 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 4087 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK
4088 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4089 __func__);
6aa8b732 4090 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL
4091 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4092 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 4093 }
da38f438 4094 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK
4095}
4096
4097static void exit_lmode(struct kvm_vcpu *vcpu)
4098{
2961e876 4099 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 4100 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK
4101}
4102
4103#endif
4104
dd5f5341 4105static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
2384d2b3 4106{
dd180b3e
XG
4107 if (enable_ept) {
4108 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4109 return;
995f00a6 4110 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
f0b98c02
JM
4111 } else {
4112 vpid_sync_context(vpid);
dd180b3e 4113 }
2384d2b3
SY
4114}
4115
dd5f5341
WL
4116static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4117{
4118 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4119}
4120
fb6c8198
JM
4121static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4122{
4123 if (enable_ept)
4124 vmx_flush_tlb(vcpu);
4125}
4126
e8467fda
AK
4127static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4128{
4129 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4130
4131 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4132 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4133}
4134
aff48baa
AK
4135static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4136{
4137 if (enable_ept && is_paging(vcpu))
4138 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4139 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4140}
4141
25c4c276 4142static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 4143{
fc78f519
AK
4144 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4145
4146 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4147 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK
4148}
4149
1439442c
SY
4150static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4151{
d0d538b9
GN
4152 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4153
6de4f3ad
AK
4154 if (!test_bit(VCPU_EXREG_PDPTR,
4155 (unsigned long *)&vcpu->arch.regs_dirty))
4156 return;
4157
1439442c 4158 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN
4159 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4160 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4161 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4162 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY
4163 }
4164}
4165
8f5d549f
AK
4166static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4167{
d0d538b9
GN
4168 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4169
8f5d549f 4170 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN
4171 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4172 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4173 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4174 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 4175 }
6de4f3ad
AK
4176
4177 __set_bit(VCPU_EXREG_PDPTR,
4178 (unsigned long *)&vcpu->arch.regs_avail);
4179 __set_bit(VCPU_EXREG_PDPTR,
4180 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK
4181}
4182
3899152c
DM
4183static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4184{
4185 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4186 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4187 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4188
4189 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4190 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4191 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4192 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4193
4194 return fixed_bits_valid(val, fixed0, fixed1);
4195}
4196
4197static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4198{
4199 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4200 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4201
4202 return fixed_bits_valid(val, fixed0, fixed1);
4203}
4204
4205static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4206{
4207 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4208 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4209
4210 return fixed_bits_valid(val, fixed0, fixed1);
4211}
4212
4213/* No difference in the restrictions on guest and host CR4 in VMX operation. */
4214#define nested_guest_cr4_valid nested_cr4_valid
4215#define nested_host_cr4_valid nested_cr4_valid
4216
5e1746d6 4217static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY
4218
4219static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4220 unsigned long cr0,
4221 struct kvm_vcpu *vcpu)
4222{
5233dd51
MT
4223 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4224 vmx_decache_cr3(vcpu);
1439442c
SY
4225 if (!(cr0 & X86_CR0_PG)) {
4226 /* From paging/starting to nonpaging */
4227 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 4228 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY
4229 (CPU_BASED_CR3_LOAD_EXITING |
4230 CPU_BASED_CR3_STORE_EXITING));
4231 vcpu->arch.cr0 = cr0;
fc78f519 4232 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY
4233 } else if (!is_paging(vcpu)) {
4234 /* From nonpaging to paging */
4235 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 4236 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY
4237 ~(CPU_BASED_CR3_LOAD_EXITING |
4238 CPU_BASED_CR3_STORE_EXITING));
4239 vcpu->arch.cr0 = cr0;
fc78f519 4240 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 4241 }
95eb84a7
SY
4242
4243 if (!(cr0 & X86_CR0_WP))
4244 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY
4245}
4246
6aa8b732
AK
4247static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4248{
7ffd92c5 4249 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK
4250 unsigned long hw_cr0;
4251
5037878e 4252 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 4253 if (enable_unrestricted_guest)
5037878e 4254 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 4255 else {
5037878e 4256 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 4257
218e763f
GN
4258 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4259 enter_pmode(vcpu);
6aa8b732 4260
218e763f
GN
4261 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4262 enter_rmode(vcpu);
4263 }
6aa8b732 4264
05b3e0c2 4265#ifdef CONFIG_X86_64
f6801dff 4266 if (vcpu->arch.efer & EFER_LME) {
707d92fa 4267 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 4268 enter_lmode(vcpu);
707d92fa 4269 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK
4270 exit_lmode(vcpu);
4271 }
4272#endif
4273
089d034e 4274 if (enable_ept)
1439442c
SY
4275 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4276
6aa8b732 4277 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 4278 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 4279 vcpu->arch.cr0 = cr0;
14168786
GN
4280
4281 /* depends on vcpu->arch.cr0 to be set to a new value */
4282 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK
4283}
4284
995f00a6 4285static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
1439442c
SY
4286{
4287 u64 eptp;
4288
4289 /* TODO write the value reading from MSR */
4290 eptp = VMX_EPT_DEFAULT_MT |
4291 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
995f00a6
PF
4292 if (enable_ept_ad_bits &&
4293 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
b38f9934 4294 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY
4295 eptp |= (root_hpa & PAGE_MASK);
4296
4297 return eptp;
4298}
4299
6aa8b732
AK
4300static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4301{
1439442c
SY
4302 unsigned long guest_cr3;
4303 u64 eptp;
4304
4305 guest_cr3 = cr3;
089d034e 4306 if (enable_ept) {
995f00a6 4307 eptp = construct_eptp(vcpu, cr3);
1439442c 4308 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK
4309 if (is_paging(vcpu) || is_guest_mode(vcpu))
4310 guest_cr3 = kvm_read_cr3(vcpu);
4311 else
4312 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 4313 ept_load_pdptrs(vcpu);
1439442c
SY
4314 }
4315
2384d2b3 4316 vmx_flush_tlb(vcpu);
1439442c 4317 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK
4318}
4319
5e1746d6 4320static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 4321{
085e68ee
BS
4322 /*
4323 * Pass through host's Machine Check Enable value to hw_cr4, which
4324 * is in force while we are in guest mode. Do not let guests control
4325 * this bit, even if host CR4.MCE == 0.
4326 */
4327 unsigned long hw_cr4 =
4328 (cr4_read_shadow() & X86_CR4_MCE) |
4329 (cr4 & ~X86_CR4_MCE) |
4330 (to_vmx(vcpu)->rmode.vm86_active ?
4331 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 4332
5e1746d6
NHE
4333 if (cr4 & X86_CR4_VMXE) {
4334 /*
4335 * To use VMXON (and later other VMX instructions), a guest
4336 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4337 * So basically the check on whether to allow nested VMX
4338 * is here.
4339 */
4340 if (!nested_vmx_allowed(vcpu))
4341 return 1;
1a0d74e6 4342 }
3899152c
DM
4343
4344 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE
4345 return 1;
4346
ad312c7c 4347 vcpu->arch.cr4 = cr4;
bc23008b
AK
4348 if (enable_ept) {
4349 if (!is_paging(vcpu)) {
4350 hw_cr4 &= ~X86_CR4_PAE;
4351 hw_cr4 |= X86_CR4_PSE;
4352 } else if (!(cr4 & X86_CR4_PAE)) {
4353 hw_cr4 &= ~X86_CR4_PAE;
4354 }
4355 }
1439442c 4356
656ec4a4
RK
4357 if (!enable_unrestricted_guest && !is_paging(vcpu))
4358 /*
ddba2628
HH
4359 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4360 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4361 * to be manually disabled when guest switches to non-paging
4362 * mode.
4363 *
4364 * If !enable_unrestricted_guest, the CPU is always running
4365 * with CR0.PG=1 and CR4 needs to be modified.
4366 * If enable_unrestricted_guest, the CPU automatically
4367 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 4368 */
ddba2628 4369 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
656ec4a4 4370
1439442c
SY
4371 vmcs_writel(CR4_READ_SHADOW, cr4);
4372 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 4373 return 0;
6aa8b732
AK
4374}
4375
6aa8b732
AK
4376static void vmx_get_segment(struct kvm_vcpu *vcpu,
4377 struct kvm_segment *var, int seg)
4378{
a9179499 4379 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK
4380 u32 ar;
4381
c6ad1153 4382 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 4383 *var = vmx->rmode.segs[seg];
a9179499 4384 if (seg == VCPU_SREG_TR
2fb92db1 4385 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 4386 return;
1390a28b
AK
4387 var->base = vmx_read_guest_seg_base(vmx, seg);
4388 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4389 return;
a9179499 4390 }
2fb92db1
AK
4391 var->base = vmx_read_guest_seg_base(vmx, seg);
4392 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4393 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4394 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 4395 var->unusable = (ar >> 16) & 1;
6aa8b732
AK
4396 var->type = ar & 15;
4397 var->s = (ar >> 4) & 1;
4398 var->dpl = (ar >> 5) & 3;
03617c18
GN
4399 /*
4400 * Some userspaces do not preserve unusable property. Since usable
4401 * segment has to be present according to VMX spec we can use present
4402 * property to amend userspace bug by making unusable segment always
4403 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4404 * segment as unusable.
4405 */
4406 var->present = !var->unusable;
6aa8b732
AK
4407 var->avl = (ar >> 12) & 1;
4408 var->l = (ar >> 13) & 1;
4409 var->db = (ar >> 14) & 1;
4410 var->g = (ar >> 15) & 1;
6aa8b732
AK
4411}
4412
a9179499
AK
4413static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4414{
a9179499
AK
4415 struct kvm_segment s;
4416
4417 if (to_vmx(vcpu)->rmode.vm86_active) {
4418 vmx_get_segment(vcpu, &s, seg);
4419 return s.base;
4420 }
2fb92db1 4421 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK
4422}
4423
b09408d0 4424static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 4425{
b09408d0
MT
4426 struct vcpu_vmx *vmx = to_vmx(vcpu);
4427
ae9fedc7 4428 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 4429 return 0;
ae9fedc7
PB
4430 else {
4431 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 4432 return VMX_AR_DPL(ar);
69c73028 4433 }
69c73028
AK
4434}
4435
653e3108 4436static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 4437{
6aa8b732
AK
4438 u32 ar;
4439
f0495f9b 4440 if (var->unusable || !var->present)
6aa8b732
AK
4441 ar = 1 << 16;
4442 else {
4443 ar = var->type & 15;
4444 ar |= (var->s & 1) << 4;
4445 ar |= (var->dpl & 3) << 5;
4446 ar |= (var->present & 1) << 7;
4447 ar |= (var->avl & 1) << 12;
4448 ar |= (var->l & 1) << 13;
4449 ar |= (var->db & 1) << 14;
4450 ar |= (var->g & 1) << 15;
4451 }
653e3108
AK
4452
4453 return ar;
4454}
4455
4456static void vmx_set_segment(struct kvm_vcpu *vcpu,
4457 struct kvm_segment *var, int seg)
4458{
7ffd92c5 4459 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 4460 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 4461
2fb92db1
AK
4462 vmx_segment_cache_clear(vmx);
4463
1ecd50a9
GN
4464 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4465 vmx->rmode.segs[seg] = *var;
4466 if (seg == VCPU_SREG_TR)
4467 vmcs_write16(sf->selector, var->selector);
4468 else if (var->s)
4469 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 4470 goto out;
653e3108 4471 }
1ecd50a9 4472
653e3108
AK
4473 vmcs_writel(sf->base, var->base);
4474 vmcs_write32(sf->limit, var->limit);
4475 vmcs_write16(sf->selector, var->selector);
3a624e29
NK
4476
4477 /*
4478 * Fix the "Accessed" bit in AR field of segment registers for older
4479 * qemu binaries.
4480 * IA32 arch specifies that at the time of processor reset the
4481 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 4482 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK
4483 * state vmexit when "unrestricted guest" mode is turned on.
4484 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4485 * tree. Newer qemu binaries with that qemu fix would not need this
4486 * kvm hack.
4487 */
4488 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 4489 var->type |= 0x1; /* Accessed */
3a624e29 4490
f924d66d 4491 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN
4492
4493out:
98eb2f8b 4494 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK
4495}
4496
6aa8b732
AK
4497static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4498{
2fb92db1 4499 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK
4500
4501 *db = (ar >> 14) & 1;
4502 *l = (ar >> 13) & 1;
4503}
4504
89a27f4d 4505static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4506{
89a27f4d
GN
4507 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4508 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK
4509}
4510
89a27f4d 4511static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4512{
89a27f4d
GN
4513 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4514 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK
4515}
4516
89a27f4d 4517static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4518{
89a27f4d
GN
4519 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4520 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK
4521}
4522
89a27f4d 4523static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4524{
89a27f4d
GN
4525 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4526 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK
4527}
4528
648dfaa7
MG
4529static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4530{
4531 struct kvm_segment var;
4532 u32 ar;
4533
4534 vmx_get_segment(vcpu, &var, seg);
07f42f5f 4535 var.dpl = 0x3;
0647f4aa
GN
4536 if (seg == VCPU_SREG_CS)
4537 var.type = 0x3;
648dfaa7
MG
4538 ar = vmx_segment_access_rights(&var);
4539
4540 if (var.base != (var.selector << 4))
4541 return false;
89efbed0 4542 if (var.limit != 0xffff)
648dfaa7 4543 return false;
07f42f5f 4544 if (ar != 0xf3)
648dfaa7
MG
4545 return false;
4546
4547 return true;
4548}
4549
4550static bool code_segment_valid(struct kvm_vcpu *vcpu)
4551{
4552 struct kvm_segment cs;
4553 unsigned int cs_rpl;
4554
4555 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 4556 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 4557
1872a3f4
AK
4558 if (cs.unusable)
4559 return false;
4d283ec9 4560 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG
4561 return false;
4562 if (!cs.s)
4563 return false;
4d283ec9 4564 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG
4565 if (cs.dpl > cs_rpl)
4566 return false;
1872a3f4 4567 } else {
648dfaa7
MG
4568 if (cs.dpl != cs_rpl)
4569 return false;
4570 }
4571 if (!cs.present)
4572 return false;
4573
4574 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4575 return true;
4576}
4577
4578static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4579{
4580 struct kvm_segment ss;
4581 unsigned int ss_rpl;
4582
4583 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 4584 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 4585
1872a3f4
AK
4586 if (ss.unusable)
4587 return true;
4588 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG
4589 return false;
4590 if (!ss.s)
4591 return false;
4592 if (ss.dpl != ss_rpl) /* DPL != RPL */
4593 return false;
4594 if (!ss.present)
4595 return false;
4596
4597 return true;
4598}
4599
4600static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4601{
4602 struct kvm_segment var;
4603 unsigned int rpl;
4604
4605 vmx_get_segment(vcpu, &var, seg);
b32a9918 4606 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 4607
1872a3f4
AK
4608 if (var.unusable)
4609 return true;
648dfaa7
MG
4610 if (!var.s)
4611 return false;
4612 if (!var.present)
4613 return false;
4d283ec9 4614 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG
4615 if (var.dpl < rpl) /* DPL < RPL */
4616 return false;
4617 }
4618
4619 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4620 * rights flags
4621 */
4622 return true;
4623}
4624
4625static bool tr_valid(struct kvm_vcpu *vcpu)
4626{
4627 struct kvm_segment tr;
4628
4629 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4630
1872a3f4
AK
4631 if (tr.unusable)
4632 return false;
b32a9918 4633 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 4634 return false;
1872a3f4 4635 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG
4636 return false;
4637 if (!tr.present)
4638 return false;
4639
4640 return true;
4641}
4642
4643static bool ldtr_valid(struct kvm_vcpu *vcpu)
4644{
4645 struct kvm_segment ldtr;
4646
4647 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4648
1872a3f4
AK
4649 if (ldtr.unusable)
4650 return true;
b32a9918 4651 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG
4652 return false;
4653 if (ldtr.type != 2)
4654 return false;
4655 if (!ldtr.present)
4656 return false;
4657
4658 return true;
4659}
4660
4661static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4662{
4663 struct kvm_segment cs, ss;
4664
4665 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4666 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4667
b32a9918
NA
4668 return ((cs.selector & SEGMENT_RPL_MASK) ==
4669 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG
4670}
4671
4672/*
4673 * Check if guest state is valid. Returns true if valid, false if
4674 * not.
4675 * We assume that registers are always usable
4676 */
4677static bool guest_state_valid(struct kvm_vcpu *vcpu)
4678{
c5e97c80
GN
4679 if (enable_unrestricted_guest)
4680 return true;
4681
648dfaa7 4682 /* real mode guest state checks */
f13882d8 4683 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG
4684 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4685 return false;
4686 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4687 return false;
4688 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4689 return false;
4690 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4691 return false;
4692 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4693 return false;
4694 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4695 return false;
4696 } else {
4697 /* protected mode guest state checks */
4698 if (!cs_ss_rpl_check(vcpu))
4699 return false;
4700 if (!code_segment_valid(vcpu))
4701 return false;
4702 if (!stack_segment_valid(vcpu))
4703 return false;
4704 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4705 return false;
4706 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4707 return false;
4708 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4709 return false;
4710 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4711 return false;
4712 if (!tr_valid(vcpu))
4713 return false;
4714 if (!ldtr_valid(vcpu))
4715 return false;
4716 }
4717 /* TODO:
4718 * - Add checks on RIP
4719 * - Add checks on RFLAGS
4720 */
4721
4722 return true;
4723}
4724
5fa99cbe
JM
4725static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4726{
4727 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4728}
4729
d77c26fc 4730static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4731{
40dcaa9f 4732 gfn_t fn;
195aefde 4733 u16 data = 0;
1f755a82 4734 int idx, r;
6aa8b732 4735
40dcaa9f 4736 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4737 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE
4738 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4739 if (r < 0)
10589a46 4740 goto out;
195aefde 4741 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY
4742 r = kvm_write_guest_page(kvm, fn++, &data,
4743 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4744 if (r < 0)
10589a46 4745 goto out;
195aefde
IE
4746 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4747 if (r < 0)
10589a46 4748 goto out;
195aefde
IE
4749 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4750 if (r < 0)
10589a46 4751 goto out;
195aefde 4752 data = ~0;
10589a46
MT
4753 r = kvm_write_guest_page(kvm, fn, &data,
4754 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4755 sizeof(u8));
10589a46 4756out:
40dcaa9f 4757 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4758 return r;
6aa8b732
AK
4759}
4760
b7ebfb05
SY
4761static int init_rmode_identity_map(struct kvm *kvm)
4762{
f51770ed 4763 int i, idx, r = 0;
ba049e93 4764 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY
4765 u32 tmp;
4766
089d034e 4767 if (!enable_ept)
f51770ed 4768 return 0;
a255d479
TC
4769
4770 /* Protect kvm->arch.ept_identity_pagetable_done. */
4771 mutex_lock(&kvm->slots_lock);
4772
f51770ed 4773 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4774 goto out2;
a255d479 4775
b927a3ce 4776 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC
4777
4778 r = alloc_identity_pagetable(kvm);
f51770ed 4779 if (r < 0)
a255d479
TC
4780 goto out2;
4781
40dcaa9f 4782 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY
4783 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4784 if (r < 0)
4785 goto out;
4786 /* Set up identity-mapping pagetable for EPT in real mode */
4787 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4788 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4789 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4790 r = kvm_write_guest_page(kvm, identity_map_pfn,
4791 &tmp, i * sizeof(tmp), sizeof(tmp));
4792 if (r < 0)
4793 goto out;
4794 }
4795 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4796
b7ebfb05 4797out:
40dcaa9f 4798 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC
4799
4800out2:
4801 mutex_unlock(&kvm->slots_lock);
f51770ed 4802 return r;
b7ebfb05
SY
4803}
4804
6aa8b732
AK
4805static void seg_setup(int seg)
4806{
772e0318 4807 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4808 unsigned int ar;
6aa8b732
AK
4809
4810 vmcs_write16(sf->selector, 0);
4811 vmcs_writel(sf->base, 0);
4812 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN
4813 ar = 0x93;
4814 if (seg == VCPU_SREG_CS)
4815 ar |= 0x08; /* code segment */
3a624e29
NK
4816
4817 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK
4818}
4819
f78e0e2e
SY
4820static int alloc_apic_access_page(struct kvm *kvm)
4821{
4484141a 4822 struct page *page;
f78e0e2e
SY
4823 int r = 0;
4824
79fac95e 4825 mutex_lock(&kvm->slots_lock);
c24ae0dc 4826 if (kvm->arch.apic_access_page_done)
f78e0e2e 4827 goto out;
1d8007bd
PB
4828 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4829 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY
4830 if (r)
4831 goto out;
72dc67a6 4832
73a6d941 4833 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG
4834 if (is_error_page(page)) {
4835 r = -EFAULT;
4836 goto out;
4837 }
4838
c24ae0dc
TC
4839 /*
4840 * Do not pin the page in memory, so that memory hot-unplug
4841 * is able to migrate it.
4842 */
4843 put_page(page);
4844 kvm->arch.apic_access_page_done = true;
f78e0e2e 4845out:
79fac95e 4846 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY
4847 return r;
4848}
4849
b7ebfb05
SY
4850static int alloc_identity_pagetable(struct kvm *kvm)
4851{
a255d479
TC
4852 /* Called with kvm->slots_lock held. */
4853
b7ebfb05
SY
4854 int r = 0;
4855
a255d479
TC
4856 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4857
1d8007bd
PB
4858 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4859 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
b7ebfb05 4860
b7ebfb05
SY
4861 return r;
4862}
4863
991e7a0e 4864static int allocate_vpid(void)
2384d2b3
SY
4865{
4866 int vpid;
4867
919818ab 4868 if (!enable_vpid)
991e7a0e 4869 return 0;
2384d2b3
SY
4870 spin_lock(&vmx_vpid_lock);
4871 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 4872 if (vpid < VMX_NR_VPIDS)
2384d2b3 4873 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL
4874 else
4875 vpid = 0;
2384d2b3 4876 spin_unlock(&vmx_vpid_lock);
991e7a0e 4877 return vpid;
2384d2b3
SY
4878}
4879
991e7a0e 4880static void free_vpid(int vpid)
cdbecfc3 4881{
991e7a0e 4882 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ
4883 return;
4884 spin_lock(&vmx_vpid_lock);
991e7a0e 4885 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ
4886 spin_unlock(&vmx_vpid_lock);
4887}
4888
8d14695f
YZ
4889#define MSR_TYPE_R 1
4890#define MSR_TYPE_W 2
4891static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4892 u32 msr, int type)
25c5f225 4893{
3e7c73e9 4894 int f = sizeof(unsigned long);
25c5f225
SY
4895
4896 if (!cpu_has_vmx_msr_bitmap())
4897 return;
4898
4899 /*
4900 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4901 * have the write-low and read-high bitmap offsets the wrong way round.
4902 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4903 */
25c5f225 4904 if (msr <= 0x1fff) {
8d14695f
YZ
4905 if (type & MSR_TYPE_R)
4906 /* read-low */
4907 __clear_bit(msr, msr_bitmap + 0x000 / f);
4908
4909 if (type & MSR_TYPE_W)
4910 /* write-low */
4911 __clear_bit(msr, msr_bitmap + 0x800 / f);
4912
25c5f225
SY
4913 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4914 msr &= 0x1fff;
8d14695f
YZ
4915 if (type & MSR_TYPE_R)
4916 /* read-high */
4917 __clear_bit(msr, msr_bitmap + 0x400 / f);
4918
4919 if (type & MSR_TYPE_W)
4920 /* write-high */
4921 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4922
4923 }
4924}
4925
f2b93280
WV
4926/*
4927 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4928 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4929 */
4930static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4931 unsigned long *msr_bitmap_nested,
4932 u32 msr, int type)
4933{
4934 int f = sizeof(unsigned long);
4935
4936 if (!cpu_has_vmx_msr_bitmap()) {
4937 WARN_ON(1);
4938 return;
4939 }
4940
4941 /*
4942 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4943 * have the write-low and read-high bitmap offsets the wrong way round.
4944 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4945 */
4946 if (msr <= 0x1fff) {
4947 if (type & MSR_TYPE_R &&
4948 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4949 /* read-low */
4950 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4951
4952 if (type & MSR_TYPE_W &&
4953 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4954 /* write-low */
4955 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4956
4957 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4958 msr &= 0x1fff;
4959 if (type & MSR_TYPE_R &&
4960 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4961 /* read-high */
4962 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4963
4964 if (type & MSR_TYPE_W &&
4965 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4966 /* write-high */
4967 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4968
4969 }
4970}
4971
5897297b
AK
4972static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4973{
4974 if (!longmode_only)
8d14695f
YZ
4975 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4976 msr, MSR_TYPE_R | MSR_TYPE_W);
4977 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4978 msr, MSR_TYPE_R | MSR_TYPE_W);
4979}
4980
2e69f865 4981static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
8d14695f 4982{
f6e90f9e 4983 if (apicv_active) {
c63e4563 4984 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
2e69f865 4985 msr, type);
c63e4563 4986 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
2e69f865 4987 msr, type);
f6e90f9e 4988 } else {
f6e90f9e 4989 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
2e69f865 4990 msr, type);
f6e90f9e 4991 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
2e69f865 4992 msr, type);
f6e90f9e 4993 }
5897297b
AK
4994}
4995
d62caabb 4996static bool vmx_get_enable_apicv(void)
d50ab6c1 4997{
d62caabb 4998 return enable_apicv;
d50ab6c1
PB
4999}
5000
6342c50a 5001static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
705699a1
WV
5002{
5003 struct vcpu_vmx *vmx = to_vmx(vcpu);
5004 int max_irr;
5005 void *vapic_page;
5006 u16 status;
5007
5008 if (vmx->nested.pi_desc &&
5009 vmx->nested.pi_pending) {
5010 vmx->nested.pi_pending = false;
5011 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
6342c50a 5012 return;
705699a1
WV
5013
5014 max_irr = find_last_bit(
5015 (unsigned long *)vmx->nested.pi_desc->pir, 256);
5016
5017 if (max_irr == 256)
6342c50a 5018 return;
705699a1
WV
5019
5020 vapic_page = kmap(vmx->nested.virtual_apic_page);
705699a1
WV
5021 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
5022 kunmap(vmx->nested.virtual_apic_page);
5023
5024 status = vmcs_read16(GUEST_INTR_STATUS);
5025 if ((u8)max_irr > ((u8)status & 0xff)) {
5026 status &= ~0xff;
5027 status |= (u8)max_irr;
5028 vmcs_write16(GUEST_INTR_STATUS, status);
5029 }
5030 }
705699a1
WV
5031}
5032
06a5524f
WV
5033static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5034 bool nested)
21bc8dc5
RK
5035{
5036#ifdef CONFIG_SMP
06a5524f
WV
5037 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5038
21bc8dc5 5039 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6
FW
5040 struct vcpu_vmx *vmx = to_vmx(vcpu);
5041
5042 /*
5043 * Currently, we don't support urgent interrupt,
5044 * all interrupts are recognized as non-urgent
5045 * interrupt, so we cannot post interrupts when
5046 * 'SN' is set.
5047 *
5048 * If the vcpu is in guest mode, it means it is
5049 * running instead of being scheduled out and
5050 * waiting in the run queue, and that's the only
5051 * case when 'SN' is set currently, warning if
5052 * 'SN' is set.
5053 */
5054 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
5055
06a5524f 5056 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
21bc8dc5
RK
5057 return true;
5058 }
5059#endif
5060 return false;
5061}
5062
705699a1
WV
5063static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5064 int vector)
5065{
5066 struct vcpu_vmx *vmx = to_vmx(vcpu);
5067
5068 if (is_guest_mode(vcpu) &&
5069 vector == vmx->nested.posted_intr_nv) {
5070 /* the PIR and ON have been set by L1. */
06a5524f 5071 kvm_vcpu_trigger_posted_interrupt(vcpu, true);
705699a1
WV
5072 /*
5073 * If a posted intr is not recognized by hardware,
5074 * we will accomplish it in the next vmentry.
5075 */
5076 vmx->nested.pi_pending = true;
5077 kvm_make_request(KVM_REQ_EVENT, vcpu);
5078 return 0;
5079 }
5080 return -1;
5081}
a20ed54d
YZ
5082/*
5083 * Send interrupt to vcpu via posted interrupt way.
5084 * 1. If target vcpu is running(non-root mode), send posted interrupt
5085 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5086 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5087 * interrupt from PIR in next vmentry.
5088 */
5089static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5090{
5091 struct vcpu_vmx *vmx = to_vmx(vcpu);
5092 int r;
5093
705699a1
WV
5094 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5095 if (!r)
5096 return;
5097
a20ed54d
YZ
5098 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5099 return;
5100
b95234c8
PB
5101 /* If a previous notification has sent the IPI, nothing to do. */
5102 if (pi_test_and_set_on(&vmx->pi_desc))
5103 return;
5104
06a5524f 5105 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
a20ed54d
YZ
5106 kvm_vcpu_kick(vcpu);
5107}
5108
a3a8ff8e
NHE
5109/*
5110 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5111 * will not change in the lifetime of the guest.
5112 * Note that host-state that does change is set elsewhere. E.g., host-state
5113 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5114 */
a547c6db 5115static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE
5116{
5117 u32 low32, high32;
5118 unsigned long tmpl;
5119 struct desc_ptr dt;
d6e41f11 5120 unsigned long cr0, cr3, cr4;
a3a8ff8e 5121
04ac88ab
AL
5122 cr0 = read_cr0();
5123 WARN_ON(cr0 & X86_CR0_TS);
5124 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL
5125
5126 /*
5127 * Save the most likely value for this task's CR3 in the VMCS.
5128 * We can't use __get_current_cr3_fast() because we're not atomic.
5129 */
6c690ee1 5130 cr3 = __read_cr3();
d6e41f11
AL
5131 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5132 vmx->host_state.vmcs_host_cr3 = cr3;
a3a8ff8e 5133
d974baa3 5134 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 5135 cr4 = cr4_read_shadow();
d974baa3
AL
5136 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5137 vmx->host_state.vmcs_host_cr4 = cr4;
5138
a3a8ff8e 5139 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK
5140#ifdef CONFIG_X86_64
5141 /*
5142 * Load null selectors, so we can avoid reloading them in
5143 * __vmx_load_host_state(), in case userspace uses the null selectors
5144 * too (the expected case).
5145 */
5146 vmcs_write16(HOST_DS_SELECTOR, 0);
5147 vmcs_write16(HOST_ES_SELECTOR, 0);
5148#else
a3a8ff8e
NHE
5149 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5150 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 5151#endif
a3a8ff8e
NHE
5152 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5153 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5154
5155 native_store_idt(&dt);
5156 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 5157 vmx->host_idt_base = dt.address;
a3a8ff8e 5158
83287ea4 5159 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE
5160
5161 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5162 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5163 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5164 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5165
5166 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5167 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5168 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5169 }
5170}
5171
bf8179a0
NHE
5172static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5173{
5174 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5175 if (enable_ept)
5176 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE
5177 if (is_guest_mode(&vmx->vcpu))
5178 vmx->vcpu.arch.cr4_guest_owned_bits &=
5179 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE
5180 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5181}
5182
01e439be
YZ
5183static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5184{
5185 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5186
d62caabb 5187 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 5188 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
64672c95
YJ
5189 /* Enable the preemption timer dynamically */
5190 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ
5191 return pin_based_exec_ctrl;
5192}
5193
d62caabb
AS
5194static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5195{
5196 struct vcpu_vmx *vmx = to_vmx(vcpu);
5197
5198 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK
5199 if (cpu_has_secondary_exec_ctrls()) {
5200 if (kvm_vcpu_apicv_active(vcpu))
5201 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5202 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5203 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5204 else
5205 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5206 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5207 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5208 }
5209
5210 if (cpu_has_vmx_msr_bitmap())
5211 vmx_set_msr_bitmap(vcpu);
d62caabb
AS
5212}
5213
bf8179a0
NHE
5214static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5215{
5216 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB
5217
5218 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5219 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5220
35754c98 5221 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE
5222 exec_control &= ~CPU_BASED_TPR_SHADOW;
5223#ifdef CONFIG_X86_64
5224 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5225 CPU_BASED_CR8_LOAD_EXITING;
5226#endif
5227 }
5228 if (!enable_ept)
5229 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5230 CPU_BASED_CR3_LOAD_EXITING |
5231 CPU_BASED_INVLPG_EXITING;
5232 return exec_control;
5233}
5234
5235static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5236{
5237 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 5238 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE
5239 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5240 if (vmx->vpid == 0)
5241 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5242 if (!enable_ept) {
5243 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5244 enable_unrestricted_guest = 0;
ad756a16
MJ
5245 /* Enable INVPCID for non-ept guests may cause performance regression. */
5246 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE
5247 }
5248 if (!enable_unrestricted_guest)
5249 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5250 if (!ple_gap)
5251 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
d62caabb 5252 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
c7c9c56c
YZ
5253 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5254 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 5255 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG
5256 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5257 (handle_vmptrld).
5258 We can NOT enable shadow_vmcs here because we don't have yet
5259 a current VMCS12
5260 */
5261 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH
5262
5263 if (!enable_pml)
5264 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 5265
bf8179a0
NHE
5266 return exec_control;
5267}
5268
ce88decf
XG
5269static void ept_set_mmio_spte_mask(void)
5270{
5271 /*
5272 * EPT Misconfigurations can be generated if the value of bits 2:0
5273 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 5274 */
dcdca5fe
PF
5275 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5276 VMX_EPT_MISCONFIG_WX_VALUE);
ce88decf
XG
5277}
5278
f53cd63c 5279#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK
5280/*
5281 * Sets up the vmcs for emulated real mode.
5282 */
8b9cf98c 5283static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 5284{
2e4ce7f5 5285#ifdef CONFIG_X86_64
6aa8b732 5286 unsigned long a;
2e4ce7f5 5287#endif
6aa8b732 5288 int i;
6aa8b732 5289
6aa8b732 5290 /* I/O */
3e7c73e9
AK
5291 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5292 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 5293
4607c2d7
AG
5294 if (enable_shadow_vmcs) {
5295 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5296 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5297 }
25c5f225 5298 if (cpu_has_vmx_msr_bitmap())
5897297b 5299 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 5300
6aa8b732
AK
5301 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5302
6aa8b732 5303 /* Control */
01e439be 5304 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
64672c95 5305 vmx->hv_deadline_tsc = -1;
6e5d865c 5306
bf8179a0 5307 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 5308
dfa169bb 5309 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE
5310 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5311 vmx_secondary_exec_control(vmx));
dfa169bb 5312 }
f78e0e2e 5313
d62caabb 5314 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ
5315 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5316 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5317 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5318 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5319
5320 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 5321
0bcf261c 5322 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 5323 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ
5324 }
5325
4b8d54f9
ZE
5326 if (ple_gap) {
5327 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK
5328 vmx->ple_window = ple_window;
5329 vmx->ple_window_dirty = true;
4b8d54f9
ZE
5330 }
5331
c3707958
XG
5332 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5333 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK
5334 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5335
9581d442
AK
5336 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5337 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 5338 vmx_set_constant_host_state(vmx);
05b3e0c2 5339#ifdef CONFIG_X86_64
6aa8b732
AK
5340 rdmsrl(MSR_FS_BASE, a);
5341 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5342 rdmsrl(MSR_GS_BASE, a);
5343 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5344#else
5345 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5346 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5347#endif
5348
2cc51560
ED
5349 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5350 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 5351 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 5352 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 5353 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 5354
74545705
RK
5355 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5356 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 5357
03916db9 5358 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK
5359 u32 index = vmx_msr_index[i];
5360 u32 data_low, data_high;
a2fa3e9f 5361 int j = vmx->nmsrs;
6aa8b732
AK
5362
5363 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5364 continue;
432bd6cb
AK
5365 if (wrmsr_safe(index, data_low, data_high) < 0)
5366 continue;
26bb0981
AK
5367 vmx->guest_msrs[j].index = i;
5368 vmx->guest_msrs[j].data = 0;
d5696725 5369 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 5370 ++vmx->nmsrs;
6aa8b732 5371 }
6aa8b732 5372
2961e876
GN
5373
5374 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK
5375
5376 /* 22.2.1, 20.8.1 */
2961e876 5377 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 5378
bd7e5b08
PB
5379 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5380 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5381
bf8179a0 5382 set_cr4_guest_host_mask(vmx);
e00c8cf2 5383
f53cd63c
WL
5384 if (vmx_xsaves_supported())
5385 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5386
4e59516a
PF
5387 if (enable_pml) {
5388 ASSERT(vmx->pml_pg);
5389 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5390 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5391 }
5392
e00c8cf2
AK
5393 return 0;
5394}
5395
d28bc9dd 5396static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK
5397{
5398 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 5399 struct msr_data apic_base_msr;
d28bc9dd 5400 u64 cr0;
e00c8cf2 5401
7ffd92c5 5402 vmx->rmode.vm86_active = 0;
e00c8cf2 5403
ad312c7c 5404 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA
5405 kvm_set_cr8(vcpu, 0);
5406
5407 if (!init_event) {
5408 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5409 MSR_IA32_APICBASE_ENABLE;
5410 if (kvm_vcpu_is_reset_bsp(vcpu))
5411 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5412 apic_base_msr.host_initiated = true;
5413 kvm_set_apic_base(vcpu, &apic_base_msr);
5414 }
e00c8cf2 5415
2fb92db1
AK
5416 vmx_segment_cache_clear(vmx);
5417
5706be0d 5418 seg_setup(VCPU_SREG_CS);
66450a21 5419 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 5420 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK
5421
5422 seg_setup(VCPU_SREG_DS);
5423 seg_setup(VCPU_SREG_ES);
5424 seg_setup(VCPU_SREG_FS);
5425 seg_setup(VCPU_SREG_GS);
5426 seg_setup(VCPU_SREG_SS);
5427
5428 vmcs_write16(GUEST_TR_SELECTOR, 0);
5429 vmcs_writel(GUEST_TR_BASE, 0);
5430 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5431 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5432
5433 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5434 vmcs_writel(GUEST_LDTR_BASE, 0);
5435 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5436 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5437
d28bc9dd
NA
5438 if (!init_event) {
5439 vmcs_write32(GUEST_SYSENTER_CS, 0);
5440 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5441 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5442 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5443 }
e00c8cf2
AK
5444
5445 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 5446 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 5447
e00c8cf2
AK
5448 vmcs_writel(GUEST_GDTR_BASE, 0);
5449 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5450
5451 vmcs_writel(GUEST_IDTR_BASE, 0);
5452 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5453
443381a8 5454 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 5455 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 5456 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
e00c8cf2 5457
e00c8cf2
AK
5458 setup_msrs(vmx);
5459
6aa8b732
AK
5460 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5461
d28bc9dd 5462 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 5463 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 5464 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 5465 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 5466 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY
5467 vmcs_write32(TPR_THRESHOLD, 0);
5468 }
5469
a73896cb 5470 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 5471
d62caabb 5472 if (kvm_vcpu_apicv_active(vcpu))
01e439be
YZ
5473 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5474
2384d2b3
SY
5475 if (vmx->vpid != 0)
5476 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5477
d28bc9dd 5478 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 5479 vmx->vcpu.arch.cr0 = cr0;
f2463247 5480 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 5481 vmx_set_cr4(vcpu, 0);
5690891b 5482 vmx_set_efer(vcpu, 0);
bd7e5b08 5483
d28bc9dd 5484 update_exception_bitmap(vcpu);
6aa8b732 5485
dd5f5341 5486 vpid_sync_context(vmx->vpid);
6aa8b732
AK
5487}
5488
b6f1250e
NHE
5489/*
5490 * In nested virtualization, check if L1 asked to exit on external interrupts.
5491 * For most existing hypervisors, this will always return true.
5492 */
5493static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5494{
5495 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5496 PIN_BASED_EXT_INTR_MASK;
5497}
5498
77b0f5d6
BD
5499/*
5500 * In nested virtualization, check if L1 has set
5501 * VM_EXIT_ACK_INTR_ON_EXIT
5502 */
5503static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5504{
5505 return get_vmcs12(vcpu)->vm_exit_controls &
5506 VM_EXIT_ACK_INTR_ON_EXIT;
5507}
5508
ea8ceb83
JK
5509static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5510{
5511 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5512 PIN_BASED_NMI_EXITING;
5513}
5514
c9a7953f 5515static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 5516{
47c0152e
PB
5517 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5518 CPU_BASED_VIRTUAL_INTR_PENDING);
3b86cd99
JK
5519}
5520
c9a7953f 5521static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 5522{
2c82878b 5523 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK
5524 enable_irq_window(vcpu);
5525 return;
5526 }
3b86cd99 5527
47c0152e
PB
5528 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5529 CPU_BASED_VIRTUAL_NMI_PENDING);
3b86cd99
JK
5530}
5531
66fd3f7f 5532static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 5533{
9c8cba37 5534 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN
5535 uint32_t intr;
5536 int irq = vcpu->arch.interrupt.nr;
9c8cba37 5537
229456fc 5538 trace_kvm_inj_virq(irq);
2714d1d3 5539
fa89a817 5540 ++vcpu->stat.irq_injections;
7ffd92c5 5541 if (vmx->rmode.vm86_active) {
71f9833b
SH
5542 int inc_eip = 0;
5543 if (vcpu->arch.interrupt.soft)
5544 inc_eip = vcpu->arch.event_exit_inst_len;
5545 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 5546 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED
5547 return;
5548 }
66fd3f7f
GN
5549 intr = irq | INTR_INFO_VALID_MASK;
5550 if (vcpu->arch.interrupt.soft) {
5551 intr |= INTR_TYPE_SOFT_INTR;
5552 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5553 vmx->vcpu.arch.event_exit_inst_len);
5554 } else
5555 intr |= INTR_TYPE_EXT_INTR;
5556 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED
5557}
5558
f08864b4
SY
5559static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5560{
66a5a347
JK
5561 struct vcpu_vmx *vmx = to_vmx(vcpu);
5562
4c4a6f79
PB
5563 ++vcpu->stat.nmi_injections;
5564 vmx->loaded_vmcs->nmi_known_unmasked = false;
3b86cd99 5565
7ffd92c5 5566 if (vmx->rmode.vm86_active) {
71f9833b 5567 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 5568 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK
5569 return;
5570 }
c5a6d5f7 5571
f08864b4
SY
5572 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5573 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY
5574}
5575
3cfc3092
JK
5576static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5577{
4c4a6f79
PB
5578 struct vcpu_vmx *vmx = to_vmx(vcpu);
5579 bool masked;
5580
5581 if (vmx->loaded_vmcs->nmi_known_unmasked)
9d58b931 5582 return false;
4c4a6f79
PB
5583 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5584 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5585 return masked;
3cfc3092
JK
5586}
5587
5588static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5589{
5590 struct vcpu_vmx *vmx = to_vmx(vcpu);
5591
4c4a6f79 5592 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
2c82878b
PB
5593 if (masked)
5594 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5595 GUEST_INTR_STATE_NMI);
5596 else
5597 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5598 GUEST_INTR_STATE_NMI);
3cfc3092
JK
5599}
5600
2505dc9f
JK
5601static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5602{
b6b8a145
JK
5603 if (to_vmx(vcpu)->nested.nested_run_pending)
5604 return 0;
ea8ceb83 5605
2505dc9f
JK
5606 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5607 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5608 | GUEST_INTR_STATE_NMI));
5609}
5610
78646121
GN
5611static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5612{
b6b8a145
JK
5613 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5614 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN
5615 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5616 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN
5617}
5618
cbc94022
IE
5619static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5620{
5621 int ret;
cbc94022 5622
1d8007bd
PB
5623 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5624 PAGE_SIZE * 3);
cbc94022
IE
5625 if (ret)
5626 return ret;
bfc6d222 5627 kvm->arch.tss_addr = addr;
1f755a82 5628 return init_rmode_tss(kvm);
cbc94022
IE
5629}
5630
0ca1b4f4 5631static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 5632{
77ab6db0 5633 switch (vec) {
77ab6db0 5634 case BP_VECTOR:
c573cd22
JK
5635 /*
5636 * Update instruction length as we may reinject the exception
5637 * from user space while in guest debugging mode.
5638 */
5639 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5640 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 5641 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN
5642 return false;
5643 /* fall through */
5644 case DB_VECTOR:
5645 if (vcpu->guest_debug &
5646 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5647 return false;
d0bfb940
JK
5648 /* fall through */
5649 case DE_VECTOR:
77ab6db0
JK
5650 case OF_VECTOR:
5651 case BR_VECTOR:
5652 case UD_VECTOR:
5653 case DF_VECTOR:
5654 case SS_VECTOR:
5655 case GP_VECTOR:
5656 case MF_VECTOR:
0ca1b4f4
GN
5657 return true;
5658 break;
77ab6db0 5659 }
0ca1b4f4
GN
5660 return false;
5661}
5662
5663static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5664 int vec, u32 err_code)
5665{
5666 /*
5667 * Instruction with address size override prefix opcode 0x67
5668 * Cause the #SS fault with 0 error code in VM86 mode.
5669 */
5670 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5671 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5672 if (vcpu->arch.halt_request) {
5673 vcpu->arch.halt_request = 0;
5cb56059 5674 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN
5675 }
5676 return 1;
5677 }
5678 return 0;
5679 }
5680
5681 /*
5682 * Forward all other exceptions that are valid in real mode.
5683 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5684 * the required debugging infrastructure rework.
5685 */
5686 kvm_queue_exception(vcpu, vec);
5687 return 1;
6aa8b732
AK
5688}
5689
a0861c02
AK
5690/*
5691 * Trigger machine check on the host. We assume all the MSRs are already set up
5692 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5693 * We pass a fake environment to the machine check handler because we want
5694 * the guest to be always treated like user space, no matter what context
5695 * it used internally.
5696 */
5697static void kvm_machine_check(void)
5698{
5699#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5700 struct pt_regs regs = {
5701 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5702 .flags = X86_EFLAGS_IF,
5703 };
5704
5705 do_machine_check(&regs, 0);
5706#endif
5707}
5708
851ba692 5709static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK
5710{
5711 /* already handled by vcpu_run */
5712 return 1;
5713}
5714
851ba692 5715static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5716{
1155f76a 5717 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5718 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5719 u32 intr_info, ex_no, error_code;
42dbaa5a 5720 unsigned long cr2, rip, dr6;
6aa8b732
AK
5721 u32 vect_info;
5722 enum emulation_result er;
5723
1155f76a 5724 vect_info = vmx->idt_vectoring_info;
88786475 5725 intr_info = vmx->exit_intr_info;
6aa8b732 5726
a0861c02 5727 if (is_machine_check(intr_info))
851ba692 5728 return handle_machine_check(vcpu);
a0861c02 5729
ef85b673 5730 if (is_nmi(intr_info))
1b6269db 5731 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc 5732
7aa81cc0 5733 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK
5734 if (is_guest_mode(vcpu)) {
5735 kvm_queue_exception(vcpu, UD_VECTOR);
5736 return 1;
5737 }
51d8b661 5738 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5739 if (er != EMULATE_DONE)
7ee5d940 5740 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL
5741 return 1;
5742 }
5743
6aa8b732 5744 error_code = 0;
2e11384c 5745 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5746 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG
5747
5748 /*
5749 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5750 * MMIO, it is better to report an internal error.
5751 * See the comments in vmx_handle_exit.
5752 */
5753 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5754 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5755 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5756 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5757 vcpu->run->internal.ndata = 3;
bf4ca23e
XG
5758 vcpu->run->internal.data[0] = vect_info;
5759 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5760 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG
5761 return 0;
5762 }
5763
6aa8b732
AK
5764 if (is_page_fault(intr_info)) {
5765 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1261bfa3
WL
5766 /* EPT won't cause page fault directly */
5767 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
5768 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0,
5769 true);
6aa8b732
AK
5770 }
5771
d0bfb940 5772 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN
5773
5774 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5775 return handle_rmode_exception(vcpu, ex_no, error_code);
5776
42dbaa5a 5777 switch (ex_no) {
54a20552
EN
5778 case AC_VECTOR:
5779 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5780 return 1;
42dbaa5a
JK
5781 case DB_VECTOR:
5782 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5783 if (!(vcpu->guest_debug &
5784 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5785 vcpu->arch.dr6 &= ~15;
6f43ed01 5786 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD
5787 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5788 skip_emulated_instruction(vcpu);
5789
42dbaa5a
JK
5790 kvm_queue_exception(vcpu, DB_VECTOR);
5791 return 1;
5792 }
5793 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5794 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5795 /* fall through */
5796 case BP_VECTOR:
c573cd22
JK
5797 /*
5798 * Update instruction length as we may reinject #BP from
5799 * user space while in guest debugging mode. Reading it for
5800 * #DB as well causes no harm, it is not used in that case.
5801 */
5802 vmx->vcpu.arch.event_exit_inst_len =
5803 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5804 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5805 rip = kvm_rip_read(vcpu);
d0bfb940
JK
5806 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5807 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK
5808 break;
5809 default:
d0bfb940
JK
5810 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5811 kvm_run->ex.exception = ex_no;
5812 kvm_run->ex.error_code = error_code;
42dbaa5a 5813 break;
6aa8b732 5814 }
6aa8b732
AK
5815 return 0;
5816}
5817
851ba692 5818static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5819{
1165f5fe 5820 ++vcpu->stat.irq_exits;
6aa8b732
AK
5821 return 1;
5822}
5823
851ba692 5824static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5825{
851ba692 5826 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK
5827 return 0;
5828}
6aa8b732 5829
851ba692 5830static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5831{
bfdaab09 5832 unsigned long exit_qualification;
6affcbed 5833 int size, in, string, ret;
039576c0 5834 unsigned port;
6aa8b732 5835
bfdaab09 5836 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5837 string = (exit_qualification & 16) != 0;
cf8f70bf 5838 in = (exit_qualification & 8) != 0;
e70669ab 5839
cf8f70bf 5840 ++vcpu->stat.io_exits;
e70669ab 5841
cf8f70bf 5842 if (string || in)
51d8b661 5843 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5844
cf8f70bf
GN
5845 port = exit_qualification >> 16;
5846 size = (exit_qualification & 7) + 1;
cf8f70bf 5847
6affcbed
KH
5848 ret = kvm_skip_emulated_instruction(vcpu);
5849
5850 /*
5851 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5852 * KVM_EXIT_DEBUG here.
5853 */
5854 return kvm_fast_pio_out(vcpu, size, port) && ret;
6aa8b732
AK
5855}
5856
102d8325
IM
5857static void
5858vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5859{
5860 /*
5861 * Patch in the VMCALL instruction:
5862 */
5863 hypercall[0] = 0x0f;
5864 hypercall[1] = 0x01;
5865 hypercall[2] = 0xc1;
102d8325
IM
5866}
5867
0fa06071 5868/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE
5869static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5870{
eeadf9e7 5871 if (is_guest_mode(vcpu)) {
1a0d74e6
JK
5872 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5873 unsigned long orig_val = val;
5874
eeadf9e7
NHE
5875 /*
5876 * We get here when L2 changed cr0 in a way that did not change
5877 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK
5878 * but did change L0 shadowed bits. So we first calculate the
5879 * effective cr0 value that L1 would like to write into the
5880 * hardware. It consists of the L2-owned bits from the new
5881 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5882 */
1a0d74e6
JK
5883 val = (val & ~vmcs12->cr0_guest_host_mask) |
5884 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5885
3899152c 5886 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 5887 return 1;
1a0d74e6
JK
5888
5889 if (kvm_set_cr0(vcpu, val))
5890 return 1;
5891 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5892 return 0;
1a0d74e6
JK
5893 } else {
5894 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 5895 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 5896 return 1;
3899152c 5897
eeadf9e7 5898 return kvm_set_cr0(vcpu, val);
1a0d74e6 5899 }
eeadf9e7
NHE
5900}
5901
5902static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5903{
5904 if (is_guest_mode(vcpu)) {
1a0d74e6
JK
5905 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5906 unsigned long orig_val = val;
5907
5908 /* analogously to handle_set_cr0 */
5909 val = (val & ~vmcs12->cr4_guest_host_mask) |
5910 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5911 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5912 return 1;
1a0d74e6 5913 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE
5914 return 0;
5915 } else
5916 return kvm_set_cr4(vcpu, val);
5917}
5918
851ba692 5919static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5920{
229456fc 5921 unsigned long exit_qualification, val;
6aa8b732
AK
5922 int cr;
5923 int reg;
49a9b07e 5924 int err;
6affcbed 5925 int ret;
6aa8b732 5926
bfdaab09 5927 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK
5928 cr = exit_qualification & 15;
5929 reg = (exit_qualification >> 8) & 15;
5930 switch ((exit_qualification >> 4) & 3) {
5931 case 0: /* mov to cr */
1e32c079 5932 val = kvm_register_readl(vcpu, reg);
229456fc 5933 trace_kvm_cr_write(cr, val);
6aa8b732
AK
5934 switch (cr) {
5935 case 0:
eeadf9e7 5936 err = handle_set_cr0(vcpu, val);
6affcbed 5937 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 5938 case 3:
2390218b 5939 err = kvm_set_cr3(vcpu, val);
6affcbed 5940 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 5941 case 4:
eeadf9e7 5942 err = handle_set_cr4(vcpu, val);
6affcbed 5943 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN
5944 case 8: {
5945 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5946 u8 cr8 = (u8)val;
eea1cff9 5947 err = kvm_set_cr8(vcpu, cr8);
6affcbed 5948 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 5949 if (lapic_in_kernel(vcpu))
6affcbed 5950 return ret;
0a5fff19 5951 if (cr8_prev <= cr8)
6affcbed
KH
5952 return ret;
5953 /*
5954 * TODO: we might be squashing a
5955 * KVM_GUESTDBG_SINGLESTEP-triggered
5956 * KVM_EXIT_DEBUG here.
5957 */
851ba692 5958 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN
5959 return 0;
5960 }
4b8073e4 5961 }
6aa8b732 5962 break;
25c4c276 5963 case 2: /* clts */
bd7e5b08
PB
5964 WARN_ONCE(1, "Guest should always own CR0.TS");
5965 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 5966 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 5967 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5968 case 1: /*mov from cr*/
5969 switch (cr) {
5970 case 3:
9f8fe504
AK
5971 val = kvm_read_cr3(vcpu);
5972 kvm_register_write(vcpu, reg, val);
5973 trace_kvm_cr_read(cr, val);
6affcbed 5974 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 5975 case 8:
229456fc
MT
5976 val = kvm_get_cr8(vcpu);
5977 kvm_register_write(vcpu, reg, val);
5978 trace_kvm_cr_read(cr, val);
6affcbed 5979 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5980 }
5981 break;
5982 case 3: /* lmsw */
a1f83a74 5983 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5984 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5985 kvm_lmsw(vcpu, val);
6aa8b732 5986
6affcbed 5987 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5988 default:
5989 break;
5990 }
851ba692 5991 vcpu->run->exit_reason = 0;
a737f256 5992 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK
5993 (int)(exit_qualification >> 4) & 3, cr);
5994 return 0;
5995}
5996
851ba692 5997static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5998{
bfdaab09 5999 unsigned long exit_qualification;
16f8a6f9
NA
6000 int dr, dr7, reg;
6001
6002 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6003 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6004
6005 /* First, if DR does not exist, trigger UD */
6006 if (!kvm_require_dr(vcpu, dr))
6007 return 1;
6aa8b732 6008
f2483415 6009 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK
6010 if (!kvm_require_cpl(vcpu, 0))
6011 return 1;
16f8a6f9
NA
6012 dr7 = vmcs_readl(GUEST_DR7);
6013 if (dr7 & DR7_GD) {
42dbaa5a
JK
6014 /*
6015 * As the vm-exit takes precedence over the debug trap, we
6016 * need to emulate the latter, either for the host or the
6017 * guest debugging itself.
6018 */
6019 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 6020 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 6021 vcpu->run->debug.arch.dr7 = dr7;
82b32774 6022 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK
6023 vcpu->run->debug.arch.exception = DB_VECTOR;
6024 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK
6025 return 0;
6026 } else {
7305eb5d 6027 vcpu->arch.dr6 &= ~15;
6f43ed01 6028 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK
6029 kvm_queue_exception(vcpu, DB_VECTOR);
6030 return 1;
6031 }
6032 }
6033
81908bf4 6034 if (vcpu->guest_debug == 0) {
8f22372f
PB
6035 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6036 CPU_BASED_MOV_DR_EXITING);
81908bf4
PB
6037
6038 /*
6039 * No more DR vmexits; force a reload of the debug registers
6040 * and reenter on this instruction. The next vmexit will
6041 * retrieve the full state of the debug registers.
6042 */
6043 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6044 return 1;
6045 }
6046
42dbaa5a
JK
6047 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6048 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 6049 unsigned long val;
4c4d563b
JK
6050
6051 if (kvm_get_dr(vcpu, dr, &val))
6052 return 1;
6053 kvm_register_write(vcpu, reg, val);
020df079 6054 } else
5777392e 6055 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK
6056 return 1;
6057
6affcbed 6058 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
6059}
6060
73aaf249
JK
6061static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6062{
6063 return vcpu->arch.dr6;
6064}
6065
6066static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6067{
6068}
6069
81908bf4
PB
6070static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6071{
81908bf4
PB
6072 get_debugreg(vcpu->arch.db[0], 0);
6073 get_debugreg(vcpu->arch.db[1], 1);
6074 get_debugreg(vcpu->arch.db[2], 2);
6075 get_debugreg(vcpu->arch.db[3], 3);
6076 get_debugreg(vcpu->arch.dr6, 6);
6077 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6078
6079 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
8f22372f 6080 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
81908bf4
PB
6081}
6082
020df079
GN
6083static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6084{
6085 vmcs_writel(GUEST_DR7, val);
6086}
6087
851ba692 6088static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 6089{
6a908b62 6090 return kvm_emulate_cpuid(vcpu);
6aa8b732
AK
6091}
6092
851ba692 6093static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 6094{
ad312c7c 6095 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 6096 struct msr_data msr_info;
6aa8b732 6097
609e36d3
PB
6098 msr_info.index = ecx;
6099 msr_info.host_initiated = false;
6100 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 6101 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 6102 kvm_inject_gp(vcpu, 0);
6aa8b732
AK
6103 return 1;
6104 }
6105
609e36d3 6106 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 6107
6aa8b732 6108 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB
6109 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6110 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6affcbed 6111 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
6112}
6113
851ba692 6114static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 6115{
8fe8ab46 6116 struct msr_data msr;
ad312c7c
ZX
6117 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6118 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6119 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 6120
8fe8ab46
WA
6121 msr.data = data;
6122 msr.index = ecx;
6123 msr.host_initiated = false;
854e8bb1 6124 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 6125 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 6126 kvm_inject_gp(vcpu, 0);
6aa8b732
AK
6127 return 1;
6128 }
6129
59200273 6130 trace_kvm_msr_write(ecx, data);
6affcbed 6131 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
6132}
6133
851ba692 6134static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 6135{
eb90f341 6136 kvm_apic_update_ppr(vcpu);
6e5d865c
YS
6137 return 1;
6138}
6139
851ba692 6140static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 6141{
47c0152e
PB
6142 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6143 CPU_BASED_VIRTUAL_INTR_PENDING);
2714d1d3 6144
3842d135
AK
6145 kvm_make_request(KVM_REQ_EVENT, vcpu);
6146
a26bf12a 6147 ++vcpu->stat.irq_window_exits;
6aa8b732
AK
6148 return 1;
6149}
6150
851ba692 6151static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 6152{
d3bef15f 6153 return kvm_emulate_halt(vcpu);
6aa8b732
AK
6154}
6155
851ba692 6156static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 6157{
0d9c055e 6158 return kvm_emulate_hypercall(vcpu);
c21415e8
IM
6159}
6160
ec25d5e6
GN
6161static int handle_invd(struct kvm_vcpu *vcpu)
6162{
51d8b661 6163 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN
6164}
6165
851ba692 6166static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 6167{
f9c617f6 6168 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT
6169
6170 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 6171 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT
6172}
6173
fee84b07
AK
6174static int handle_rdpmc(struct kvm_vcpu *vcpu)
6175{
6176 int err;
6177
6178 err = kvm_rdpmc(vcpu);
6affcbed 6179 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK
6180}
6181
851ba692 6182static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 6183{
6affcbed 6184 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED
6185}
6186
2acf923e
DC
6187static int handle_xsetbv(struct kvm_vcpu *vcpu)
6188{
6189 u64 new_bv = kvm_read_edx_eax(vcpu);
6190 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6191
6192 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 6193 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC
6194 return 1;
6195}
6196
f53cd63c
WL
6197static int handle_xsaves(struct kvm_vcpu *vcpu)
6198{
6affcbed 6199 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL
6200 WARN(1, "this should never happen\n");
6201 return 1;
6202}
6203
6204static int handle_xrstors(struct kvm_vcpu *vcpu)
6205{
6affcbed 6206 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL
6207 WARN(1, "this should never happen\n");
6208 return 1;
6209}
6210
851ba692 6211static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 6212{
58fbbf26
KT
6213 if (likely(fasteoi)) {
6214 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6215 int access_type, offset;
6216
6217 access_type = exit_qualification & APIC_ACCESS_TYPE;
6218 offset = exit_qualification & APIC_ACCESS_OFFSET;
6219 /*
6220 * Sane guest uses MOV to write EOI, with written value
6221 * not cared. So make a short-circuit here by avoiding
6222 * heavy instruction emulation.
6223 */
6224 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6225 (offset == APIC_EOI)) {
6226 kvm_lapic_set_eoi(vcpu);
6affcbed 6227 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT
6228 }
6229 }
51d8b661 6230 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY
6231}
6232
c7c9c56c
YZ
6233static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6234{
6235 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6236 int vector = exit_qualification & 0xff;
6237
6238 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6239 kvm_apic_set_eoi_accelerated(vcpu, vector);
6240 return 1;
6241}
6242
83d4c286
YZ
6243static int handle_apic_write(struct kvm_vcpu *vcpu)
6244{
6245 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6246 u32 offset = exit_qualification & 0xfff;
6247
6248 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6249 kvm_apic_write_nodecode(vcpu, offset);
6250 return 1;
6251}
6252
851ba692 6253static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 6254{
60637aac 6255 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 6256 unsigned long exit_qualification;
e269fb21
JK
6257 bool has_error_code = false;
6258 u32 error_code = 0;
37817f29 6259 u16 tss_selector;
7f3d35fd 6260 int reason, type, idt_v, idt_index;
64a7ec06
GN
6261
6262 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 6263 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 6264 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE
6265
6266 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6267
6268 reason = (u32)exit_qualification >> 30;
64a7ec06
GN
6269 if (reason == TASK_SWITCH_GATE && idt_v) {
6270 switch (type) {
6271 case INTR_TYPE_NMI_INTR:
6272 vcpu->arch.nmi_injected = false;
654f06fc 6273 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN
6274 break;
6275 case INTR_TYPE_EXT_INTR:
66fd3f7f 6276 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN
6277 kvm_clear_interrupt_queue(vcpu);
6278 break;
6279 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK
6280 if (vmx->idt_vectoring_info &
6281 VECTORING_INFO_DELIVER_CODE_MASK) {
6282 has_error_code = true;
6283 error_code =
6284 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6285 }
6286 /* fall through */
64a7ec06
GN
6287 case INTR_TYPE_SOFT_EXCEPTION:
6288 kvm_clear_exception_queue(vcpu);
6289 break;
6290 default:
6291 break;
6292 }
60637aac 6293 }
37817f29
IE
6294 tss_selector = exit_qualification;
6295
64a7ec06
GN
6296 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6297 type != INTR_TYPE_EXT_INTR &&
6298 type != INTR_TYPE_NMI_INTR))
6299 skip_emulated_instruction(vcpu);
6300
7f3d35fd
KW
6301 if (kvm_task_switch(vcpu, tss_selector,
6302 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6303 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN
6304 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6305 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6306 vcpu->run->internal.ndata = 0;
42dbaa5a 6307 return 0;
acb54517 6308 }
42dbaa5a 6309
42dbaa5a
JK
6310 /*
6311 * TODO: What about debug traps on tss switch?
6312 * Are we supposed to inject them and update dr6?
6313 */
6314
6315 return 1;
37817f29
IE
6316}
6317
851ba692 6318static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 6319{
f9c617f6 6320 unsigned long exit_qualification;
1439442c 6321 gpa_t gpa;
4f5982a5 6322 u32 error_code;
1439442c 6323
f9c617f6 6324 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 6325
0be9c7a8
GN
6326 /*
6327 * EPT violation happened while executing iret from NMI,
6328 * "blocked by NMI" bit has to be set before next VM entry.
6329 * There are errata that may cause this bit to not be set:
6330 * AAK134, BY25.
6331 */
bcd1c294 6332 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
bcd1c294 6333 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN
6334 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6335
1439442c 6336 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 6337 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 6338
27959a44 6339 /* Is it a read fault? */
ab22a473 6340 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS
6341 ? PFERR_USER_MASK : 0;
6342 /* Is it a write fault? */
ab22a473 6343 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS
6344 ? PFERR_WRITE_MASK : 0;
6345 /* Is it a fetch fault? */
ab22a473 6346 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS
6347 ? PFERR_FETCH_MASK : 0;
6348 /* ept page table entry is present? */
6349 error_code |= (exit_qualification &
6350 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6351 EPT_VIOLATION_EXECUTABLE))
6352 ? PFERR_PRESENT_MASK : 0;
4f5982a5 6353
db1c056c 6354 vcpu->arch.gpa_available = true;
25d92081
YZ
6355 vcpu->arch.exit_qualification = exit_qualification;
6356
4f5982a5 6357 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY
6358}
6359
851ba692 6360static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 6361{
f735d4af 6362 int ret;
68f89400
MT
6363 gpa_t gpa;
6364
6365 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 6366 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 6367 trace_kvm_fast_mmio(gpa);
6affcbed 6368 return kvm_skip_emulated_instruction(vcpu);
68c3b4d1 6369 }
68f89400 6370
450869d6 6371 ret = handle_mmio_page_fault(vcpu, gpa, true);
db1c056c 6372 vcpu->arch.gpa_available = true;
b37fbea6 6373 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG
6374 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6375 EMULATE_DONE;
f8f55942
XG
6376
6377 if (unlikely(ret == RET_MMIO_PF_INVALID))
6378 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6379
b37fbea6 6380 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG
6381 return 1;
6382
6383 /* It is the real ept misconfig */
f735d4af 6384 WARN_ON(1);
68f89400 6385
851ba692
AK
6386 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6387 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT
6388
6389 return 0;
6390}
6391
851ba692 6392static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 6393{
47c0152e
PB
6394 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6395 CPU_BASED_VIRTUAL_NMI_PENDING);
f08864b4 6396 ++vcpu->stat.nmi_window_exits;
3842d135 6397 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY
6398
6399 return 1;
6400}
6401
80ced186 6402static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 6403{
8b3079a5
AK
6404 struct vcpu_vmx *vmx = to_vmx(vcpu);
6405 enum emulation_result err = EMULATE_DONE;
80ced186 6406 int ret = 1;
49e9d557
AK
6407 u32 cpu_exec_ctrl;
6408 bool intr_window_requested;
b8405c18 6409 unsigned count = 130;
49e9d557
AK
6410
6411 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6412 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 6413
98eb2f8b 6414 while (vmx->emulation_required && count-- != 0) {
bdea48e3 6415 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK
6416 return handle_interrupt_window(&vmx->vcpu);
6417
72875d8a 6418 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK
6419 return 1;
6420
991eebf9 6421 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 6422
ac0a48c3 6423 if (err == EMULATE_USER_EXIT) {
94452b9e 6424 ++vcpu->stat.mmio_exits;
80ced186
MG
6425 ret = 0;
6426 goto out;
6427 }
1d5a4d9b 6428
de5f70e0
AK
6429 if (err != EMULATE_DONE) {
6430 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6431 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6432 vcpu->run->internal.ndata = 0;
6d77dbfc 6433 return 0;
de5f70e0 6434 }
ea953ef0 6435
8d76c49e
GN
6436 if (vcpu->arch.halt_request) {
6437 vcpu->arch.halt_request = 0;
5cb56059 6438 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN
6439 goto out;
6440 }
6441
ea953ef0 6442 if (signal_pending(current))
80ced186 6443 goto out;
ea953ef0
MG
6444 if (need_resched())
6445 schedule();
6446 }
6447
80ced186
MG
6448out:
6449 return ret;
ea953ef0
MG
6450}
6451
b4a2d31d
RK
6452static int __grow_ple_window(int val)
6453{
6454 if (ple_window_grow < 1)
6455 return ple_window;
6456
6457 val = min(val, ple_window_actual_max);
6458
6459 if (ple_window_grow < ple_window)
6460 val *= ple_window_grow;
6461 else
6462 val += ple_window_grow;
6463
6464 return val;
6465}
6466
6467static int __shrink_ple_window(int val, int modifier, int minimum)
6468{
6469 if (modifier < 1)
6470 return ple_window;
6471
6472 if (modifier < ple_window)
6473 val /= modifier;
6474 else
6475 val -= modifier;
6476
6477 return max(val, minimum);
6478}
6479
6480static void grow_ple_window(struct kvm_vcpu *vcpu)
6481{
6482 struct vcpu_vmx *vmx = to_vmx(vcpu);
6483 int old = vmx->ple_window;
6484
6485 vmx->ple_window = __grow_ple_window(old);
6486
6487 if (vmx->ple_window != old)
6488 vmx->ple_window_dirty = true;
7b46268d
RK
6489
6490 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK
6491}
6492
6493static void shrink_ple_window(struct kvm_vcpu *vcpu)
6494{
6495 struct vcpu_vmx *vmx = to_vmx(vcpu);
6496 int old = vmx->ple_window;
6497
6498 vmx->ple_window = __shrink_ple_window(old,
6499 ple_window_shrink, ple_window);
6500
6501 if (vmx->ple_window != old)
6502 vmx->ple_window_dirty = true;
7b46268d
RK
6503
6504 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK
6505}
6506
6507/*
6508 * ple_window_actual_max is computed to be one grow_ple_window() below
6509 * ple_window_max. (See __grow_ple_window for the reason.)
6510 * This prevents overflows, because ple_window_max is int.
6511 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6512 * this process.
6513 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6514 */
6515static void update_ple_window_actual_max(void)
6516{
6517 ple_window_actual_max =
6518 __shrink_ple_window(max(ple_window_max, ple_window),
6519 ple_window_grow, INT_MIN);
6520}
6521
bf9f6ac8
FW
6522/*
6523 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6524 */
6525static void wakeup_handler(void)
6526{
6527 struct kvm_vcpu *vcpu;
6528 int cpu = smp_processor_id();
6529
6530 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6531 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6532 blocked_vcpu_list) {
6533 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6534
6535 if (pi_test_on(pi_desc) == 1)
6536 kvm_vcpu_kick(vcpu);
6537 }
6538 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6539}
6540
f160c7b7
JS
6541void vmx_enable_tdp(void)
6542{
6543 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6544 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6545 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6546 0ull, VMX_EPT_EXECUTABLE_MASK,
6547 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
995f00a6 6548 VMX_EPT_RWX_MASK);
f160c7b7
JS
6549
6550 ept_set_mmio_spte_mask();
6551 kvm_enable_tdp();
6552}
6553
f2c7648d
TC
6554static __init int hardware_setup(void)
6555{
34a1cd60
TC
6556 int r = -ENOMEM, i, msr;
6557
6558 rdmsrl_safe(MSR_EFER, &host_efer);
6559
6560 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6561 kvm_define_shared_msr(i, vmx_msr_index[i]);
6562
23611332
RK
6563 for (i = 0; i < VMX_BITMAP_NR; i++) {
6564 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6565 if (!vmx_bitmap[i])
6566 goto out;
6567 }
34a1cd60
TC
6568
6569 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
34a1cd60
TC
6570 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6571 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6572
6573 /*
6574 * Allow direct access to the PC debug port (it is often used for I/O
6575 * delays, but the vmexits simply slow things down).
6576 */
6577 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6578 clear_bit(0x80, vmx_io_bitmap_a);
6579
6580 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6581
6582 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6583 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6584
34a1cd60
TC
6585 if (setup_vmcs_config(&vmcs_config) < 0) {
6586 r = -EIO;
23611332 6587 goto out;
baa03522 6588 }
f2c7648d
TC
6589
6590 if (boot_cpu_has(X86_FEATURE_NX))
6591 kvm_enable_efer_bits(EFER_NX);
6592
08d839c4
WL
6593 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6594 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
f2c7648d 6595 enable_vpid = 0;
08d839c4 6596
f2c7648d
TC
6597 if (!cpu_has_vmx_shadow_vmcs())
6598 enable_shadow_vmcs = 0;
6599 if (enable_shadow_vmcs)
6600 init_vmcs_shadow_fields();
6601
6602 if (!cpu_has_vmx_ept() ||
6603 !cpu_has_vmx_ept_4levels()) {
6604 enable_ept = 0;
6605 enable_unrestricted_guest = 0;
6606 enable_ept_ad_bits = 0;
6607 }
6608
fce6ac4c 6609 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
f2c7648d
TC
6610 enable_ept_ad_bits = 0;
6611
6612 if (!cpu_has_vmx_unrestricted_guest())
6613 enable_unrestricted_guest = 0;
6614
ad15a296 6615 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC
6616 flexpriority_enabled = 0;
6617
ad15a296
PB
6618 /*
6619 * set_apic_access_page_addr() is used to reload apic access
6620 * page upon invalidation. No need to do anything if not
6621 * using the APIC_ACCESS_ADDR VMCS field.
6622 */
6623 if (!flexpriority_enabled)
f2c7648d 6624 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC
6625
6626 if (!cpu_has_vmx_tpr_shadow())
6627 kvm_x86_ops->update_cr8_intercept = NULL;
6628
6629 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6630 kvm_disable_largepages();
6631
6632 if (!cpu_has_vmx_ple())
6633 ple_gap = 0;
6634
76dfafd5 6635 if (!cpu_has_vmx_apicv()) {
f2c7648d 6636 enable_apicv = 0;
76dfafd5
PB
6637 kvm_x86_ops->sync_pir_to_irr = NULL;
6638 }
f2c7648d 6639
64903d61
HZ
6640 if (cpu_has_vmx_tsc_scaling()) {
6641 kvm_has_tsc_control = true;
6642 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6643 kvm_tsc_scaling_ratio_frac_bits = 48;
6644 }
6645
baa03522
TC
6646 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6647 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6648 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6649 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6650 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6651 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
baa03522 6652
c63e4563 6653 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
baa03522 6654 vmx_msr_bitmap_legacy, PAGE_SIZE);
c63e4563 6655 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
baa03522 6656 vmx_msr_bitmap_longmode, PAGE_SIZE);
c63e4563 6657 memcpy(vmx_msr_bitmap_legacy_x2apic,
f6e90f9e 6658 vmx_msr_bitmap_legacy, PAGE_SIZE);
c63e4563 6659 memcpy(vmx_msr_bitmap_longmode_x2apic,
f6e90f9e 6660 vmx_msr_bitmap_longmode, PAGE_SIZE);
baa03522 6661
04bb92e4
WL
6662 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6663
40d8338d
RK
6664 for (msr = 0x800; msr <= 0x8ff; msr++) {
6665 if (msr == 0x839 /* TMCCT */)
6666 continue;
2e69f865 6667 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
40d8338d 6668 }
3ce424e4 6669
f6e90f9e 6670 /*
2e69f865
RK
6671 * TPR reads and writes can be virtualized even if virtual interrupt
6672 * delivery is not in use.
f6e90f9e 6673 */
2e69f865
RK
6674 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6675 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
3ce424e4 6676
3ce424e4 6677 /* EOI */
2e69f865 6678 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
3ce424e4 6679 /* SELF-IPI */
2e69f865 6680 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
baa03522 6681
f160c7b7
JS
6682 if (enable_ept)
6683 vmx_enable_tdp();
6684 else
baa03522
TC
6685 kvm_disable_tdp();
6686
6687 update_ple_window_actual_max();
6688
843e4330
KH
6689 /*
6690 * Only enable PML when hardware supports PML feature, and both EPT
6691 * and EPT A/D bit features are enabled -- PML depends on them to work.
6692 */
6693 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6694 enable_pml = 0;
6695
6696 if (!enable_pml) {
6697 kvm_x86_ops->slot_enable_log_dirty = NULL;
6698 kvm_x86_ops->slot_disable_log_dirty = NULL;
6699 kvm_x86_ops->flush_log_dirty = NULL;
6700 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6701 }
6702
64672c95
YJ
6703 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6704 u64 vmx_msr;
6705
6706 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6707 cpu_preemption_timer_multi =
6708 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6709 } else {
6710 kvm_x86_ops->set_hv_timer = NULL;
6711 kvm_x86_ops->cancel_hv_timer = NULL;
6712 }
6713
bf9f6ac8
FW
6714 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6715
c45dcc71
AR
6716 kvm_mce_cap_supported |= MCG_LMCE_P;
6717
f2c7648d 6718 return alloc_kvm_area();
34a1cd60 6719
34a1cd60 6720out:
23611332
RK
6721 for (i = 0; i < VMX_BITMAP_NR; i++)
6722 free_page((unsigned long)vmx_bitmap[i]);
34a1cd60
TC
6723
6724 return r;
f2c7648d
TC
6725}
6726
6727static __exit void hardware_unsetup(void)
6728{
23611332
RK
6729 int i;
6730
6731 for (i = 0; i < VMX_BITMAP_NR; i++)
6732 free_page((unsigned long)vmx_bitmap[i]);
34a1cd60 6733
f2c7648d
TC
6734 free_kvm_area();
6735}
6736
4b8d54f9
ZE
6737/*
6738 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6739 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6740 */
9fb41ba8 6741static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6742{
b4a2d31d
RK
6743 if (ple_gap)
6744 grow_ple_window(vcpu);
6745
4b8d54f9 6746 kvm_vcpu_on_spin(vcpu);
6affcbed 6747 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE
6748}
6749
87c00572 6750static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6751{
6affcbed 6752 return kvm_skip_emulated_instruction(vcpu);
59708670
SY
6753}
6754
87c00572
GS
6755static int handle_mwait(struct kvm_vcpu *vcpu)
6756{
6757 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6758 return handle_nop(vcpu);
6759}
6760
5f3d45e7
MD
6761static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6762{
6763 return 1;
6764}
6765
87c00572
GS
6766static int handle_monitor(struct kvm_vcpu *vcpu)
6767{
6768 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6769 return handle_nop(vcpu);
6770}
6771
ff2f6fe9
NHE
6772/*
6773 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6774 * We could reuse a single VMCS for all the L2 guests, but we also want the
6775 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6776 * allows keeping them loaded on the processor, and in the future will allow
6777 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6778 * every entry if they never change.
6779 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6780 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6781 *
6782 * The following functions allocate and free a vmcs02 in this pool.
6783 */
6784
6785/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6786static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6787{
6788 struct vmcs02_list *item;
6789 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6790 if (item->vmptr == vmx->nested.current_vmptr) {
6791 list_move(&item->list, &vmx->nested.vmcs02_pool);
6792 return &item->vmcs02;
6793 }
6794
6795 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6796 /* Recycle the least recently used VMCS. */
d74c0e6b
GT
6797 item = list_last_entry(&vmx->nested.vmcs02_pool,
6798 struct vmcs02_list, list);
ff2f6fe9
NHE
6799 item->vmptr = vmx->nested.current_vmptr;
6800 list_move(&item->list, &vmx->nested.vmcs02_pool);
6801 return &item->vmcs02;
6802 }
6803
6804 /* Create a new VMCS */
0fa24ce3 6805 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE
6806 if (!item)
6807 return NULL;
6808 item->vmcs02.vmcs = alloc_vmcs();
355f4fb1 6809 item->vmcs02.shadow_vmcs = NULL;
ff2f6fe9
NHE
6810 if (!item->vmcs02.vmcs) {
6811 kfree(item);
6812 return NULL;
6813 }
6814 loaded_vmcs_init(&item->vmcs02);
6815 item->vmptr = vmx->nested.current_vmptr;
6816 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6817 vmx->nested.vmcs02_num++;
6818 return &item->vmcs02;
6819}
6820
6821/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6822static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6823{
6824 struct vmcs02_list *item;
6825 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6826 if (item->vmptr == vmptr) {
6827 free_loaded_vmcs(&item->vmcs02);
6828 list_del(&item->list);
6829 kfree(item);
6830 vmx->nested.vmcs02_num--;
6831 return;
6832 }
6833}
6834
6835/*
6836 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB
6837 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6838 * must be &vmx->vmcs01.
ff2f6fe9
NHE
6839 */
6840static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6841{
6842 struct vmcs02_list *item, *n;
4fa7734c
PB
6843
6844 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6845 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB
6846 /*
6847 * Something will leak if the above WARN triggers. Better than
6848 * a use-after-free.
6849 */
6850 if (vmx->loaded_vmcs == &item->vmcs02)
6851 continue;
6852
6853 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE
6854 list_del(&item->list);
6855 kfree(item);
4fa7734c 6856 vmx->nested.vmcs02_num--;
ff2f6fe9 6857 }
ff2f6fe9
NHE
6858}
6859
0658fbaa
ACL
6860/*
6861 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6862 * set the success or error code of an emulated VMX instruction, as specified
6863 * by Vol 2B, VMX Instruction Reference, "Conventions".
6864 */
6865static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6866{
6867 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6868 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6869 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6870}
6871
6872static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6873{
6874 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6875 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6876 X86_EFLAGS_SF | X86_EFLAGS_OF))
6877 | X86_EFLAGS_CF);
6878}
6879
145c28dd 6880static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL
6881 u32 vm_instruction_error)
6882{
6883 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6884 /*
6885 * failValid writes the error number to the current VMCS, which
6886 * can't be done there isn't a current VMCS.
6887 */
6888 nested_vmx_failInvalid(vcpu);
6889 return;
6890 }
6891 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6892 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6893 X86_EFLAGS_SF | X86_EFLAGS_OF))
6894 | X86_EFLAGS_ZF);
6895 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6896 /*
6897 * We don't need to force a shadow sync because
6898 * VM_INSTRUCTION_ERROR is not shadowed
6899 */
6900}
145c28dd 6901
ff651cb6
WV
6902static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6903{
6904 /* TODO: not to reset guest simply here. */
6905 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
bbe41b95 6906 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
ff651cb6
WV
6907}
6908
f4124500
JK
6909static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6910{
6911 struct vcpu_vmx *vmx =
6912 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6913
6914 vmx->nested.preemption_timer_expired = true;
6915 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6916 kvm_vcpu_kick(&vmx->vcpu);
6917
6918 return HRTIMER_NORESTART;
6919}
6920
19677e32
BD
6921/*
6922 * Decode the memory-address operand of a vmx instruction, as recorded on an
6923 * exit caused by such an instruction (run by a guest hypervisor).
6924 * On success, returns 0. When the operand is invalid, returns 1 and throws
6925 * #UD or #GP.
6926 */
6927static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6928 unsigned long exit_qualification,
f9eb4af6 6929 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6930{
f9eb4af6
EK
6931 gva_t off;
6932 bool exn;
6933 struct kvm_segment s;
6934
19677e32
BD
6935 /*
6936 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6937 * Execution", on an exit, vmx_instruction_info holds most of the
6938 * addressing components of the operand. Only the displacement part
6939 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6940 * For how an actual address is calculated from all these components,
6941 * refer to Vol. 1, "Operand Addressing".
6942 */
6943 int scaling = vmx_instruction_info & 3;
6944 int addr_size = (vmx_instruction_info >> 7) & 7;
6945 bool is_reg = vmx_instruction_info & (1u << 10);
6946 int seg_reg = (vmx_instruction_info >> 15) & 7;
6947 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6948 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6949 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6950 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6951
6952 if (is_reg) {
6953 kvm_queue_exception(vcpu, UD_VECTOR);
6954 return 1;
6955 }
6956
6957 /* Addr = segment_base + offset */
6958 /* offset = base + [index * scale] + displacement */
f9eb4af6 6959 off = exit_qualification; /* holds the displacement */
19677e32 6960 if (base_is_valid)
f9eb4af6 6961 off += kvm_register_read(vcpu, base_reg);
19677e32 6962 if (index_is_valid)
f9eb4af6
EK
6963 off += kvm_register_read(vcpu, index_reg)<<scaling;
6964 vmx_get_segment(vcpu, &s, seg_reg);
6965 *ret = s.base + off;
19677e32
BD
6966
6967 if (addr_size == 1) /* 32 bit */
6968 *ret &= 0xffffffff;
6969
f9eb4af6
EK
6970 /* Checks for #GP/#SS exceptions. */
6971 exn = false;
ff30ef40
QC
6972 if (is_long_mode(vcpu)) {
6973 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6974 * non-canonical form. This is the only check on the memory
6975 * destination for long mode!
6976 */
6977 exn = is_noncanonical_address(*ret);
6978 } else if (is_protmode(vcpu)) {
f9eb4af6
EK
6979 /* Protected mode: apply checks for segment validity in the
6980 * following order:
6981 * - segment type check (#GP(0) may be thrown)
6982 * - usability check (#GP(0)/#SS(0))
6983 * - limit check (#GP(0)/#SS(0))
6984 */
6985 if (wr)
6986 /* #GP(0) if the destination operand is located in a
6987 * read-only data segment or any code segment.
6988 */
6989 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6990 else
6991 /* #GP(0) if the source operand is located in an
6992 * execute-only code segment
6993 */
6994 exn = ((s.type & 0xa) == 8);
ff30ef40
QC
6995 if (exn) {
6996 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6997 return 1;
6998 }
f9eb4af6
EK
6999 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7000 */
7001 exn = (s.unusable != 0);
7002 /* Protected mode: #GP(0)/#SS(0) if the memory
7003 * operand is outside the segment limit.
7004 */
7005 exn = exn || (off + sizeof(u64) > s.limit);
7006 }
7007 if (exn) {
7008 kvm_queue_exception_e(vcpu,
7009 seg_reg == VCPU_SREG_SS ?
7010 SS_VECTOR : GP_VECTOR,
7011 0);
7012 return 1;
7013 }
7014
19677e32
BD
7015 return 0;
7016}
7017
cbf71279 7018static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
3573e22c
BD
7019{
7020 gva_t gva;
3573e22c 7021 struct x86_exception e;
3573e22c
BD
7022
7023 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7024 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD
7025 return 1;
7026
cbf71279
RK
7027 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
7028 sizeof(*vmpointer), &e)) {
3573e22c
BD
7029 kvm_inject_page_fault(vcpu, &e);
7030 return 1;
7031 }
7032
3573e22c
BD
7033 return 0;
7034}
7035
e29acc55
JM
7036static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7037{
7038 struct vcpu_vmx *vmx = to_vmx(vcpu);
7039 struct vmcs *shadow_vmcs;
7040
7041 if (cpu_has_vmx_msr_bitmap()) {
7042 vmx->nested.msr_bitmap =
7043 (unsigned long *)__get_free_page(GFP_KERNEL);
7044 if (!vmx->nested.msr_bitmap)
7045 goto out_msr_bitmap;
7046 }
7047
7048 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7049 if (!vmx->nested.cached_vmcs12)
7050 goto out_cached_vmcs12;
7051
7052 if (enable_shadow_vmcs) {
7053 shadow_vmcs = alloc_vmcs();
7054 if (!shadow_vmcs)
7055 goto out_shadow_vmcs;
7056 /* mark vmcs as shadow */
7057 shadow_vmcs->revision_id |= (1u << 31);
7058 /* init shadow vmcs */
7059 vmcs_clear(shadow_vmcs);
7060 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7061 }
7062
7063 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7064 vmx->nested.vmcs02_num = 0;
7065
7066 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7067 HRTIMER_MODE_REL_PINNED);
7068 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7069
7070 vmx->nested.vmxon = true;
7071 return 0;
7072
7073out_shadow_vmcs:
7074 kfree(vmx->nested.cached_vmcs12);
7075
7076out_cached_vmcs12:
7077 free_page((unsigned long)vmx->nested.msr_bitmap);
7078
7079out_msr_bitmap:
7080 return -ENOMEM;
7081}
7082
ec378aee
NHE
7083/*
7084 * Emulate the VMXON instruction.
7085 * Currently, we just remember that VMX is active, and do not save or even
7086 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7087 * do not currently need to store anything in that guest-allocated memory
7088 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7089 * argument is different from the VMXON pointer (which the spec says they do).
7090 */
7091static int handle_vmon(struct kvm_vcpu *vcpu)
7092{
e29acc55 7093 int ret;
cbf71279
RK
7094 gpa_t vmptr;
7095 struct page *page;
ec378aee 7096 struct vcpu_vmx *vmx = to_vmx(vcpu);
b3897a49
NHE
7097 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7098 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee 7099
70f3aac9
JM
7100 /*
7101 * The Intel VMX Instruction Reference lists a bunch of bits that are
7102 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7103 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7104 * Otherwise, we should fail with #UD. But most faulting conditions
7105 * have already been checked by hardware, prior to the VM-exit for
7106 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7107 * that bit set to 1 in non-root mode.
ec378aee 7108 */
70f3aac9 7109 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
ec378aee
NHE
7110 kvm_queue_exception(vcpu, UD_VECTOR);
7111 return 1;
7112 }
7113
145c28dd
AG
7114 if (vmx->nested.vmxon) {
7115 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6affcbed 7116 return kvm_skip_emulated_instruction(vcpu);
145c28dd 7117 }
b3897a49 7118
3b84080b 7119 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
b3897a49
NHE
7120 != VMXON_NEEDED_FEATURES) {
7121 kvm_inject_gp(vcpu, 0);
7122 return 1;
7123 }
7124
cbf71279 7125 if (nested_vmx_get_vmptr(vcpu, &vmptr))
21e7fbe7 7126 return 1;
cbf71279
RK
7127
7128 /*
7129 * SDM 3: 24.11.5
7130 * The first 4 bytes of VMXON region contain the supported
7131 * VMCS revision identifier
7132 *
7133 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7134 * which replaces physical address width with 32
7135 */
7136 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7137 nested_vmx_failInvalid(vcpu);
7138 return kvm_skip_emulated_instruction(vcpu);
7139 }
7140
7141 page = nested_get_page(vcpu, vmptr);
7142 if (page == NULL) {
7143 nested_vmx_failInvalid(vcpu);
7144 return kvm_skip_emulated_instruction(vcpu);
7145 }
7146 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7147 kunmap(page);
7148 nested_release_page_clean(page);
7149 nested_vmx_failInvalid(vcpu);
7150 return kvm_skip_emulated_instruction(vcpu);
7151 }
7152 kunmap(page);
7153 nested_release_page_clean(page);
7154
7155 vmx->nested.vmxon_ptr = vmptr;
e29acc55
JM
7156 ret = enter_vmx_operation(vcpu);
7157 if (ret)
7158 return ret;
ec378aee 7159
a25eb114 7160 nested_vmx_succeed(vcpu);
6affcbed 7161 return kvm_skip_emulated_instruction(vcpu);
ec378aee
NHE
7162}
7163
7164/*
7165 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7166 * for running VMX instructions (except VMXON, whose prerequisites are
7167 * slightly different). It also specifies what exception to inject otherwise.
70f3aac9
JM
7168 * Note that many of these exceptions have priority over VM exits, so they
7169 * don't have to be checked again here.
ec378aee
NHE
7170 */
7171static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7172{
70f3aac9 7173 if (!to_vmx(vcpu)->nested.vmxon) {
ec378aee
NHE
7174 kvm_queue_exception(vcpu, UD_VECTOR);
7175 return 0;
7176 }
ec378aee
NHE
7177 return 1;
7178}
7179
e7953d7f
AG
7180static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7181{
9a2a05b9
PB
7182 if (vmx->nested.current_vmptr == -1ull)
7183 return;
7184
7185 /* current_vmptr and current_vmcs12 are always set/reset together */
7186 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7187 return;
7188
012f83cb 7189 if (enable_shadow_vmcs) {
9a2a05b9
PB
7190 /* copy to memory all shadowed fields in case
7191 they were modified */
7192 copy_shadow_to_vmcs12(vmx);
7193 vmx->nested.sync_shadow_vmcs = false;
7ec36296
XG
7194 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7195 SECONDARY_EXEC_SHADOW_VMCS);
9a2a05b9 7196 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 7197 }
705699a1 7198 vmx->nested.posted_intr_nv = -1;
4f2777bc
DM
7199
7200 /* Flush VMCS12 to guest memory */
7201 memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7202 VMCS12_SIZE);
7203
e7953d7f
AG
7204 kunmap(vmx->nested.current_vmcs12_page);
7205 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB
7206 vmx->nested.current_vmptr = -1ull;
7207 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG
7208}
7209
ec378aee
NHE
7210/*
7211 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7212 * just stops using VMX.
7213 */
7214static void free_nested(struct vcpu_vmx *vmx)
7215{
7216 if (!vmx->nested.vmxon)
7217 return;
9a2a05b9 7218
ec378aee 7219 vmx->nested.vmxon = false;
5c614b35 7220 free_vpid(vmx->nested.vpid02);
9a2a05b9 7221 nested_release_vmcs12(vmx);
d048c098
RK
7222 if (vmx->nested.msr_bitmap) {
7223 free_page((unsigned long)vmx->nested.msr_bitmap);
7224 vmx->nested.msr_bitmap = NULL;
7225 }
355f4fb1
JM
7226 if (enable_shadow_vmcs) {
7227 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7228 free_vmcs(vmx->vmcs01.shadow_vmcs);
7229 vmx->vmcs01.shadow_vmcs = NULL;
7230 }
4f2777bc 7231 kfree(vmx->nested.cached_vmcs12);
fe3ef05c
NHE
7232 /* Unpin physical memory we referred to in current vmcs02 */
7233 if (vmx->nested.apic_access_page) {
7234 nested_release_page(vmx->nested.apic_access_page);
48d89b92 7235 vmx->nested.apic_access_page = NULL;
fe3ef05c 7236 }
a7c0b07d
WL
7237 if (vmx->nested.virtual_apic_page) {
7238 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 7239 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 7240 }
705699a1
WV
7241 if (vmx->nested.pi_desc_page) {
7242 kunmap(vmx->nested.pi_desc_page);
7243 nested_release_page(vmx->nested.pi_desc_page);
7244 vmx->nested.pi_desc_page = NULL;
7245 vmx->nested.pi_desc = NULL;
7246 }
ff2f6fe9
NHE
7247
7248 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE
7249}
7250
7251/* Emulate the VMXOFF instruction */
7252static int handle_vmoff(struct kvm_vcpu *vcpu)
7253{
7254 if (!nested_vmx_check_permission(vcpu))
7255 return 1;
7256 free_nested(to_vmx(vcpu));
a25eb114 7257 nested_vmx_succeed(vcpu);
6affcbed 7258 return kvm_skip_emulated_instruction(vcpu);
ec378aee
NHE
7259}
7260
27d6c865
NHE
7261/* Emulate the VMCLEAR instruction */
7262static int handle_vmclear(struct kvm_vcpu *vcpu)
7263{
7264 struct vcpu_vmx *vmx = to_vmx(vcpu);
587d7e72 7265 u32 zero = 0;
27d6c865 7266 gpa_t vmptr;
27d6c865
NHE
7267
7268 if (!nested_vmx_check_permission(vcpu))
7269 return 1;
7270
cbf71279 7271 if (nested_vmx_get_vmptr(vcpu, &vmptr))
27d6c865 7272 return 1;
27d6c865 7273
cbf71279
RK
7274 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7275 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7276 return kvm_skip_emulated_instruction(vcpu);
7277 }
7278
7279 if (vmptr == vmx->nested.vmxon_ptr) {
7280 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7281 return kvm_skip_emulated_instruction(vcpu);
7282 }
7283
9a2a05b9 7284 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 7285 nested_release_vmcs12(vmx);
27d6c865 7286
587d7e72
JM
7287 kvm_vcpu_write_guest(vcpu,
7288 vmptr + offsetof(struct vmcs12, launch_state),
7289 &zero, sizeof(zero));
27d6c865
NHE
7290
7291 nested_free_vmcs02(vmx, vmptr);
7292
27d6c865 7293 nested_vmx_succeed(vcpu);
6affcbed 7294 return kvm_skip_emulated_instruction(vcpu);
27d6c865
NHE
7295}
7296
cd232ad0
NHE
7297static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7298
7299/* Emulate the VMLAUNCH instruction */
7300static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7301{
7302 return nested_vmx_run(vcpu, true);
7303}
7304
7305/* Emulate the VMRESUME instruction */
7306static int handle_vmresume(struct kvm_vcpu *vcpu)
7307{
7308
7309 return nested_vmx_run(vcpu, false);
7310}
7311
49f705c5
NHE
7312/*
7313 * Read a vmcs12 field. Since these can have varying lengths and we return
7314 * one type, we chose the biggest type (u64) and zero-extend the return value
7315 * to that size. Note that the caller, handle_vmread, might need to use only
7316 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7317 * 64-bit fields are to be returned).
7318 */
a2ae9df7
PB
7319static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7320 unsigned long field, u64 *ret)
49f705c5
NHE
7321{
7322 short offset = vmcs_field_to_offset(field);
7323 char *p;
7324
7325 if (offset < 0)
a2ae9df7 7326 return offset;
49f705c5
NHE
7327
7328 p = ((char *)(get_vmcs12(vcpu))) + offset;
7329
7330 switch (vmcs_field_type(field)) {
7331 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7332 *ret = *((natural_width *)p);
a2ae9df7 7333 return 0;
49f705c5
NHE
7334 case VMCS_FIELD_TYPE_U16:
7335 *ret = *((u16 *)p);
a2ae9df7 7336 return 0;
49f705c5
NHE
7337 case VMCS_FIELD_TYPE_U32:
7338 *ret = *((u32 *)p);
a2ae9df7 7339 return 0;
49f705c5
NHE
7340 case VMCS_FIELD_TYPE_U64:
7341 *ret = *((u64 *)p);
a2ae9df7 7342 return 0;
49f705c5 7343 default:
a2ae9df7
PB
7344 WARN_ON(1);
7345 return -ENOENT;
49f705c5
NHE
7346 }
7347}
7348
20b97fea 7349
a2ae9df7
PB
7350static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7351 unsigned long field, u64 field_value){
20b97fea
AG
7352 short offset = vmcs_field_to_offset(field);
7353 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7354 if (offset < 0)
a2ae9df7 7355 return offset;
20b97fea
AG
7356
7357 switch (vmcs_field_type(field)) {
7358 case VMCS_FIELD_TYPE_U16:
7359 *(u16 *)p = field_value;
a2ae9df7 7360 return 0;
20b97fea
AG
7361 case VMCS_FIELD_TYPE_U32:
7362 *(u32 *)p = field_value;
a2ae9df7 7363 return 0;
20b97fea
AG
7364 case VMCS_FIELD_TYPE_U64:
7365 *(u64 *)p = field_value;
a2ae9df7 7366 return 0;
20b97fea
AG
7367 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7368 *(natural_width *)p = field_value;
a2ae9df7 7369 return 0;
20b97fea 7370 default:
a2ae9df7
PB
7371 WARN_ON(1);
7372 return -ENOENT;
20b97fea
AG
7373 }
7374
7375}
7376
16f5b903
AG
7377static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7378{
7379 int i;
7380 unsigned long field;
7381 u64 field_value;
355f4fb1 7382 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
c2bae893
MK
7383 const unsigned long *fields = shadow_read_write_fields;
7384 const int num_fields = max_shadow_read_write_fields;
16f5b903 7385
282da870
JK
7386 preempt_disable();
7387
16f5b903
AG
7388 vmcs_load(shadow_vmcs);
7389
7390 for (i = 0; i < num_fields; i++) {
7391 field = fields[i];
7392 switch (vmcs_field_type(field)) {
7393 case VMCS_FIELD_TYPE_U16:
7394 field_value = vmcs_read16(field);
7395 break;
7396 case VMCS_FIELD_TYPE_U32:
7397 field_value = vmcs_read32(field);
7398 break;
7399 case VMCS_FIELD_TYPE_U64:
7400 field_value = vmcs_read64(field);
7401 break;
7402 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7403 field_value = vmcs_readl(field);
7404 break;
a2ae9df7
PB
7405 default:
7406 WARN_ON(1);
7407 continue;
16f5b903
AG
7408 }
7409 vmcs12_write_any(&vmx->vcpu, field, field_value);
7410 }
7411
7412 vmcs_clear(shadow_vmcs);
7413 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK
7414
7415 preempt_enable();
16f5b903
AG
7416}
7417
c3114420
AG
7418static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7419{
c2bae893
MK
7420 const unsigned long *fields[] = {
7421 shadow_read_write_fields,
7422 shadow_read_only_fields
c3114420 7423 };
c2bae893 7424 const int max_fields[] = {
c3114420
AG
7425 max_shadow_read_write_fields,
7426 max_shadow_read_only_fields
7427 };
7428 int i, q;
7429 unsigned long field;
7430 u64 field_value = 0;
355f4fb1 7431 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
c3114420
AG
7432
7433 vmcs_load(shadow_vmcs);
7434
c2bae893 7435 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG
7436 for (i = 0; i < max_fields[q]; i++) {
7437 field = fields[q][i];
7438 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7439
7440 switch (vmcs_field_type(field)) {
7441 case VMCS_FIELD_TYPE_U16:
7442 vmcs_write16(field, (u16)field_value);
7443 break;
7444 case VMCS_FIELD_TYPE_U32:
7445 vmcs_write32(field, (u32)field_value);
7446 break;
7447 case VMCS_FIELD_TYPE_U64:
7448 vmcs_write64(field, (u64)field_value);
7449 break;
7450 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7451 vmcs_writel(field, (long)field_value);
7452 break;
a2ae9df7
PB
7453 default:
7454 WARN_ON(1);
7455 break;
c3114420
AG
7456 }
7457 }
7458 }
7459
7460 vmcs_clear(shadow_vmcs);
7461 vmcs_load(vmx->loaded_vmcs->vmcs);
7462}
7463
49f705c5
NHE
7464/*
7465 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7466 * used before) all generate the same failure when it is missing.
7467 */
7468static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7469{
7470 struct vcpu_vmx *vmx = to_vmx(vcpu);
7471 if (vmx->nested.current_vmptr == -1ull) {
7472 nested_vmx_failInvalid(vcpu);
49f705c5
NHE
7473 return 0;
7474 }
7475 return 1;
7476}
7477
7478static int handle_vmread(struct kvm_vcpu *vcpu)
7479{
7480 unsigned long field;
7481 u64 field_value;
7482 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7483 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7484 gva_t gva = 0;
7485
eb277562 7486 if (!nested_vmx_check_permission(vcpu))
49f705c5
NHE
7487 return 1;
7488
6affcbed
KH
7489 if (!nested_vmx_check_vmcs12(vcpu))
7490 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7491
7492 /* Decode instruction info and find the field to read */
27e6fb5d 7493 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 7494 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 7495 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5 7496 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6affcbed 7497 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7498 }
7499 /*
7500 * Now copy part of this value to register or memory, as requested.
7501 * Note that the number of bits actually copied is 32 or 64 depending
7502 * on the guest's mode (32 or 64 bit), not on the given field's length.
7503 */
7504 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 7505 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE
7506 field_value);
7507 } else {
7508 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7509 vmx_instruction_info, true, &gva))
49f705c5 7510 return 1;
70f3aac9 7511 /* _system ok, as hardware has verified cpl=0 */
49f705c5
NHE
7512 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7513 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7514 }
7515
7516 nested_vmx_succeed(vcpu);
6affcbed 7517 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7518}
7519
7520
7521static int handle_vmwrite(struct kvm_vcpu *vcpu)
7522{
7523 unsigned long field;
7524 gva_t gva;
7525 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7526 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE
7527 /* The value to write might be 32 or 64 bits, depending on L1's long
7528 * mode, and eventually we need to write that into a field of several
7529 * possible lengths. The code below first zero-extends the value to 64
6a6256f9 7530 * bit (field_value), and then copies only the appropriate number of
49f705c5
NHE
7531 * bits into the vmcs12 field.
7532 */
7533 u64 field_value = 0;
7534 struct x86_exception e;
7535
eb277562 7536 if (!nested_vmx_check_permission(vcpu))
49f705c5
NHE
7537 return 1;
7538
6affcbed
KH
7539 if (!nested_vmx_check_vmcs12(vcpu))
7540 return kvm_skip_emulated_instruction(vcpu);
eb277562 7541
49f705c5 7542 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7543 field_value = kvm_register_readl(vcpu,
49f705c5
NHE
7544 (((vmx_instruction_info) >> 3) & 0xf));
7545 else {
7546 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7547 vmx_instruction_info, false, &gva))
49f705c5
NHE
7548 return 1;
7549 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7550 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE
7551 kvm_inject_page_fault(vcpu, &e);
7552 return 1;
7553 }
7554 }
7555
7556
27e6fb5d 7557 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE
7558 if (vmcs_field_readonly(field)) {
7559 nested_vmx_failValid(vcpu,
7560 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6affcbed 7561 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7562 }
7563
a2ae9df7 7564 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5 7565 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6affcbed 7566 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7567 }
7568
7569 nested_vmx_succeed(vcpu);
6affcbed 7570 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7571}
7572
a8bc284e
JM
7573static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7574{
7575 vmx->nested.current_vmptr = vmptr;
7576 if (enable_shadow_vmcs) {
7577 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7578 SECONDARY_EXEC_SHADOW_VMCS);
7579 vmcs_write64(VMCS_LINK_POINTER,
7580 __pa(vmx->vmcs01.shadow_vmcs));
7581 vmx->nested.sync_shadow_vmcs = true;
7582 }
7583}
7584
63846663
NHE
7585/* Emulate the VMPTRLD instruction */
7586static int handle_vmptrld(struct kvm_vcpu *vcpu)
7587{
7588 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7589 gpa_t vmptr;
63846663
NHE
7590
7591 if (!nested_vmx_check_permission(vcpu))
7592 return 1;
7593
cbf71279 7594 if (nested_vmx_get_vmptr(vcpu, &vmptr))
63846663 7595 return 1;
63846663 7596
cbf71279
RK
7597 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7598 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7599 return kvm_skip_emulated_instruction(vcpu);
7600 }
7601
7602 if (vmptr == vmx->nested.vmxon_ptr) {
7603 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7604 return kvm_skip_emulated_instruction(vcpu);
7605 }
7606
63846663
NHE
7607 if (vmx->nested.current_vmptr != vmptr) {
7608 struct vmcs12 *new_vmcs12;
7609 struct page *page;
7610 page = nested_get_page(vcpu, vmptr);
7611 if (page == NULL) {
7612 nested_vmx_failInvalid(vcpu);
6affcbed 7613 return kvm_skip_emulated_instruction(vcpu);
63846663
NHE
7614 }
7615 new_vmcs12 = kmap(page);
7616 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7617 kunmap(page);
7618 nested_release_page_clean(page);
7619 nested_vmx_failValid(vcpu,
7620 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6affcbed 7621 return kvm_skip_emulated_instruction(vcpu);
63846663 7622 }
63846663 7623
9a2a05b9 7624 nested_release_vmcs12(vmx);
63846663
NHE
7625 vmx->nested.current_vmcs12 = new_vmcs12;
7626 vmx->nested.current_vmcs12_page = page;
4f2777bc
DM
7627 /*
7628 * Load VMCS12 from guest memory since it is not already
7629 * cached.
7630 */
7631 memcpy(vmx->nested.cached_vmcs12,
7632 vmx->nested.current_vmcs12, VMCS12_SIZE);
a8bc284e 7633 set_current_vmptr(vmx, vmptr);
63846663
NHE
7634 }
7635
7636 nested_vmx_succeed(vcpu);
6affcbed 7637 return kvm_skip_emulated_instruction(vcpu);
63846663
NHE
7638}
7639
6a4d7550
NHE
7640/* Emulate the VMPTRST instruction */
7641static int handle_vmptrst(struct kvm_vcpu *vcpu)
7642{
7643 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7644 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7645 gva_t vmcs_gva;
7646 struct x86_exception e;
7647
7648 if (!nested_vmx_check_permission(vcpu))
7649 return 1;
7650
7651 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7652 vmx_instruction_info, true, &vmcs_gva))
6a4d7550 7653 return 1;
70f3aac9 7654 /* ok to use *_system, as hardware has verified cpl=0 */
6a4d7550
NHE
7655 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7656 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7657 sizeof(u64), &e)) {
7658 kvm_inject_page_fault(vcpu, &e);
7659 return 1;
7660 }
7661 nested_vmx_succeed(vcpu);
6affcbed 7662 return kvm_skip_emulated_instruction(vcpu);
6a4d7550
NHE
7663}
7664
bfd0a56b
NHE
7665/* Emulate the INVEPT instruction */
7666static int handle_invept(struct kvm_vcpu *vcpu)
7667{
b9c237bb 7668 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE
7669 u32 vmx_instruction_info, types;
7670 unsigned long type;
7671 gva_t gva;
7672 struct x86_exception e;
7673 struct {
7674 u64 eptp, gpa;
7675 } operand;
bfd0a56b 7676
b9c237bb
WV
7677 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7678 SECONDARY_EXEC_ENABLE_EPT) ||
7679 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE
7680 kvm_queue_exception(vcpu, UD_VECTOR);
7681 return 1;
7682 }
7683
7684 if (!nested_vmx_check_permission(vcpu))
7685 return 1;
7686
bfd0a56b 7687 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7688 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7689
b9c237bb 7690 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b 7691
85c856b3 7692 if (type >= 32 || !(types & (1 << type))) {
bfd0a56b
NHE
7693 nested_vmx_failValid(vcpu,
7694 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7695 return kvm_skip_emulated_instruction(vcpu);
bfd0a56b
NHE
7696 }
7697
7698 /* According to the Intel VMX instruction reference, the memory
7699 * operand is read even if it isn't needed (e.g., for type==global)
7700 */
7701 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7702 vmx_instruction_info, false, &gva))
bfd0a56b
NHE
7703 return 1;
7704 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7705 sizeof(operand), &e)) {
7706 kvm_inject_page_fault(vcpu, &e);
7707 return 1;
7708 }
7709
7710 switch (type) {
bfd0a56b 7711 case VMX_EPT_EXTENT_GLOBAL:
45e11817
BD
7712 /*
7713 * TODO: track mappings and invalidate
7714 * single context requests appropriately
7715 */
7716 case VMX_EPT_EXTENT_CONTEXT:
bfd0a56b 7717 kvm_mmu_sync_roots(vcpu);
77c3913b 7718 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE
7719 nested_vmx_succeed(vcpu);
7720 break;
7721 default:
7722 BUG_ON(1);
7723 break;
7724 }
7725
6affcbed 7726 return kvm_skip_emulated_instruction(vcpu);
bfd0a56b
NHE
7727}
7728
a642fc30
PM
7729static int handle_invvpid(struct kvm_vcpu *vcpu)
7730{
99b83ac8
WL
7731 struct vcpu_vmx *vmx = to_vmx(vcpu);
7732 u32 vmx_instruction_info;
7733 unsigned long type, types;
7734 gva_t gva;
7735 struct x86_exception e;
40352605
JM
7736 struct {
7737 u64 vpid;
7738 u64 gla;
7739 } operand;
99b83ac8
WL
7740
7741 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7742 SECONDARY_EXEC_ENABLE_VPID) ||
7743 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7744 kvm_queue_exception(vcpu, UD_VECTOR);
7745 return 1;
7746 }
7747
7748 if (!nested_vmx_check_permission(vcpu))
7749 return 1;
7750
7751 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7752 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7753
bcdde302
JD
7754 types = (vmx->nested.nested_vmx_vpid_caps &
7755 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
99b83ac8 7756
85c856b3 7757 if (type >= 32 || !(types & (1 << type))) {
99b83ac8
WL
7758 nested_vmx_failValid(vcpu,
7759 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7760 return kvm_skip_emulated_instruction(vcpu);
99b83ac8
WL
7761 }
7762
7763 /* according to the intel vmx instruction reference, the memory
7764 * operand is read even if it isn't needed (e.g., for type==global)
7765 */
7766 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7767 vmx_instruction_info, false, &gva))
7768 return 1;
40352605
JM
7769 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7770 sizeof(operand), &e)) {
99b83ac8
WL
7771 kvm_inject_page_fault(vcpu, &e);
7772 return 1;
7773 }
40352605
JM
7774 if (operand.vpid >> 16) {
7775 nested_vmx_failValid(vcpu,
7776 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7777 return kvm_skip_emulated_instruction(vcpu);
7778 }
99b83ac8
WL
7779
7780 switch (type) {
bcdde302 7781 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
40352605
JM
7782 if (is_noncanonical_address(operand.gla)) {
7783 nested_vmx_failValid(vcpu,
7784 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7785 return kvm_skip_emulated_instruction(vcpu);
7786 }
7787 /* fall through */
ef697a71 7788 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
bcdde302 7789 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
40352605 7790 if (!operand.vpid) {
bcdde302
JD
7791 nested_vmx_failValid(vcpu,
7792 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7793 return kvm_skip_emulated_instruction(vcpu);
bcdde302
JD
7794 }
7795 break;
99b83ac8 7796 case VMX_VPID_EXTENT_ALL_CONTEXT:
99b83ac8
WL
7797 break;
7798 default:
bcdde302 7799 WARN_ON_ONCE(1);
6affcbed 7800 return kvm_skip_emulated_instruction(vcpu);
99b83ac8
WL
7801 }
7802
bcdde302
JD
7803 __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7804 nested_vmx_succeed(vcpu);
7805
6affcbed 7806 return kvm_skip_emulated_instruction(vcpu);
a642fc30
PM
7807}
7808
843e4330
KH
7809static int handle_pml_full(struct kvm_vcpu *vcpu)
7810{
7811 unsigned long exit_qualification;
7812
7813 trace_kvm_pml_full(vcpu->vcpu_id);
7814
7815 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7816
7817 /*
7818 * PML buffer FULL happened while executing iret from NMI,
7819 * "blocked by NMI" bit has to be set before next VM entry.
7820 */
7821 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
843e4330
KH
7822 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7823 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7824 GUEST_INTR_STATE_NMI);
7825
7826 /*
7827 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7828 * here.., and there's no userspace involvement needed for PML.
7829 */
7830 return 1;
7831}
7832
64672c95
YJ
7833static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7834{
7835 kvm_lapic_expired_hv_timer(vcpu);
7836 return 1;
7837}
7838
6aa8b732
AK
7839/*
7840 * The exit handlers return 1 if the exit was handled fully and guest execution
7841 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7842 * to be done to userspace and return 0.
7843 */
772e0318 7844static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK
7845 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7846 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7847 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7848 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7849 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK
7850 [EXIT_REASON_CR_ACCESS] = handle_cr,
7851 [EXIT_REASON_DR_ACCESS] = handle_dr,
7852 [EXIT_REASON_CPUID] = handle_cpuid,
7853 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7854 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7855 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7856 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7857 [EXIT_REASON_INVD] = handle_invd,
a7052897 7858 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7859 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7860 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7861 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7862 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7863 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7864 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7865 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7866 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7867 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE
7868 [EXIT_REASON_VMOFF] = handle_vmoff,
7869 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY
7870 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7871 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7872 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7873 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7874 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7875 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7876 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7877 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT
7878 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7879 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7880 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7881 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7882 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7883 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7884 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7885 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL
7886 [EXIT_REASON_XSAVES] = handle_xsaves,
7887 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7888 [EXIT_REASON_PML_FULL] = handle_pml_full,
64672c95 7889 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
6aa8b732
AK
7890};
7891
7892static const int kvm_vmx_max_exit_handlers =
50a3485c 7893 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7894
908a7bdd
JK
7895static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7896 struct vmcs12 *vmcs12)
7897{
7898 unsigned long exit_qualification;
7899 gpa_t bitmap, last_bitmap;
7900 unsigned int port;
7901 int size;
7902 u8 b;
7903
908a7bdd 7904 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7905 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK
7906
7907 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7908
7909 port = exit_qualification >> 16;
7910 size = (exit_qualification & 7) + 1;
7911
7912 last_bitmap = (gpa_t)-1;
7913 b = -1;
7914
7915 while (size > 0) {
7916 if (port < 0x8000)
7917 bitmap = vmcs12->io_bitmap_a;
7918 else if (port < 0x10000)
7919 bitmap = vmcs12->io_bitmap_b;
7920 else
1d804d07 7921 return true;
908a7bdd
JK
7922 bitmap += (port & 0x7fff) / 8;
7923
7924 if (last_bitmap != bitmap)
54bf36aa 7925 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7926 return true;
908a7bdd 7927 if (b & (1 << (port & 7)))
1d804d07 7928 return true;
908a7bdd
JK
7929
7930 port++;
7931 size--;
7932 last_bitmap = bitmap;
7933 }
7934
1d804d07 7935 return false;
908a7bdd
JK
7936}
7937
644d711a
NHE
7938/*
7939 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7940 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7941 * disinterest in the current event (read or write a specific MSR) by using an
7942 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7943 */
7944static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7945 struct vmcs12 *vmcs12, u32 exit_reason)
7946{
7947 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7948 gpa_t bitmap;
7949
cbd29cb6 7950 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7951 return true;
644d711a
NHE
7952
7953 /*
7954 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7955 * for the four combinations of read/write and low/high MSR numbers.
7956 * First we need to figure out which of the four to use:
7957 */
7958 bitmap = vmcs12->msr_bitmap;
7959 if (exit_reason == EXIT_REASON_MSR_WRITE)
7960 bitmap += 2048;
7961 if (msr_index >= 0xc0000000) {
7962 msr_index -= 0xc0000000;
7963 bitmap += 1024;
7964 }
7965
7966 /* Then read the msr_index'th bit from this bitmap: */
7967 if (msr_index < 1024*8) {
7968 unsigned char b;
54bf36aa 7969 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7970 return true;
644d711a
NHE
7971 return 1 & (b >> (msr_index & 7));
7972 } else
1d804d07 7973 return true; /* let L1 handle the wrong parameter */
644d711a
NHE
7974}
7975
7976/*
7977 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7978 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7979 * intercept (via guest_host_mask etc.) the current event.
7980 */
7981static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7982 struct vmcs12 *vmcs12)
7983{
7984 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7985 int cr = exit_qualification & 15;
e1d39b17
JS
7986 int reg;
7987 unsigned long val;
644d711a
NHE
7988
7989 switch ((exit_qualification >> 4) & 3) {
7990 case 0: /* mov to cr */
e1d39b17
JS
7991 reg = (exit_qualification >> 8) & 15;
7992 val = kvm_register_readl(vcpu, reg);
644d711a
NHE
7993 switch (cr) {
7994 case 0:
7995 if (vmcs12->cr0_guest_host_mask &
7996 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7997 return true;
644d711a
NHE
7998 break;
7999 case 3:
8000 if ((vmcs12->cr3_target_count >= 1 &&
8001 vmcs12->cr3_target_value0 == val) ||
8002 (vmcs12->cr3_target_count >= 2 &&
8003 vmcs12->cr3_target_value1 == val) ||
8004 (vmcs12->cr3_target_count >= 3 &&
8005 vmcs12->cr3_target_value2 == val) ||
8006 (vmcs12->cr3_target_count >= 4 &&
8007 vmcs12->cr3_target_value3 == val))
1d804d07 8008 return false;
644d711a 8009 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 8010 return true;
644d711a
NHE
8011 break;
8012 case 4:
8013 if (vmcs12->cr4_guest_host_mask &
8014 (vmcs12->cr4_read_shadow ^ val))
1d804d07 8015 return true;
644d711a
NHE
8016 break;
8017 case 8:
8018 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 8019 return true;
644d711a
NHE
8020 break;
8021 }
8022 break;
8023 case 2: /* clts */
8024 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8025 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 8026 return true;
644d711a
NHE
8027 break;
8028 case 1: /* mov from cr */
8029 switch (cr) {
8030 case 3:
8031 if (vmcs12->cpu_based_vm_exec_control &
8032 CPU_BASED_CR3_STORE_EXITING)
1d804d07 8033 return true;
644d711a
NHE
8034 break;
8035 case 8:
8036 if (vmcs12->cpu_based_vm_exec_control &
8037 CPU_BASED_CR8_STORE_EXITING)
1d804d07 8038 return true;
644d711a
NHE
8039 break;
8040 }
8041 break;
8042 case 3: /* lmsw */
8043 /*
8044 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8045 * cr0. Other attempted changes are ignored, with no exit.
8046 */
e1d39b17 8047 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
644d711a
NHE
8048 if (vmcs12->cr0_guest_host_mask & 0xe &
8049 (val ^ vmcs12->cr0_read_shadow))
1d804d07 8050 return true;
644d711a
NHE
8051 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8052 !(vmcs12->cr0_read_shadow & 0x1) &&
8053 (val & 0x1))
1d804d07 8054 return true;
644d711a
NHE
8055 break;
8056 }
1d804d07 8057 return false;
644d711a
NHE
8058}
8059
8060/*
8061 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8062 * should handle it ourselves in L0 (and then continue L2). Only call this
8063 * when in is_guest_mode (L2).
8064 */
7313c698 8065static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
644d711a 8066{
644d711a
NHE
8067 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8068 struct vcpu_vmx *vmx = to_vmx(vcpu);
8069 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8070
542060ea
JK
8071 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8072 vmcs_readl(EXIT_QUALIFICATION),
8073 vmx->idt_vectoring_info,
8074 intr_info,
8075 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8076 KVM_ISA_VMX);
8077
644d711a 8078 if (vmx->nested.nested_run_pending)
1d804d07 8079 return false;
644d711a
NHE
8080
8081 if (unlikely(vmx->fail)) {
bd80158a
JK
8082 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8083 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 8084 return true;
644d711a
NHE
8085 }
8086
8087 switch (exit_reason) {
8088 case EXIT_REASON_EXCEPTION_NMI:
ef85b673 8089 if (is_nmi(intr_info))
1d804d07 8090 return false;
644d711a 8091 else if (is_page_fault(intr_info))
52a5c155 8092 return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
e504c909 8093 else if (is_no_device(intr_info) &&
ccf9844e 8094 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 8095 return false;
6f05485d
JK
8096 else if (is_debug(intr_info) &&
8097 vcpu->guest_debug &
8098 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8099 return false;
8100 else if (is_breakpoint(intr_info) &&
8101 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8102 return false;
644d711a
NHE
8103 return vmcs12->exception_bitmap &
8104 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8105 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 8106 return false;
644d711a 8107 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 8108 return true;
644d711a 8109 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 8110 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 8111 case EXIT_REASON_NMI_WINDOW:
3b656cf7 8112 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 8113 case EXIT_REASON_TASK_SWITCH:
1d804d07 8114 return true;
644d711a 8115 case EXIT_REASON_CPUID:
1d804d07 8116 return true;
644d711a
NHE
8117 case EXIT_REASON_HLT:
8118 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8119 case EXIT_REASON_INVD:
1d804d07 8120 return true;
644d711a
NHE
8121 case EXIT_REASON_INVLPG:
8122 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8123 case EXIT_REASON_RDPMC:
8124 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
a5f46457
PB
8125 case EXIT_REASON_RDRAND:
8126 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8127 case EXIT_REASON_RDSEED:
8128 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
b3a2a907 8129 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE
8130 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8131 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8132 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8133 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8134 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8135 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 8136 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE
8137 /*
8138 * VMX instructions trap unconditionally. This allows L1 to
8139 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8140 */
1d804d07 8141 return true;
644d711a
NHE
8142 case EXIT_REASON_CR_ACCESS:
8143 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8144 case EXIT_REASON_DR_ACCESS:
8145 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8146 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 8147 return nested_vmx_exit_handled_io(vcpu, vmcs12);
1b07304c
PB
8148 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8149 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
644d711a
NHE
8150 case EXIT_REASON_MSR_READ:
8151 case EXIT_REASON_MSR_WRITE:
8152 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8153 case EXIT_REASON_INVALID_STATE:
1d804d07 8154 return true;
644d711a
NHE
8155 case EXIT_REASON_MWAIT_INSTRUCTION:
8156 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD
8157 case EXIT_REASON_MONITOR_TRAP_FLAG:
8158 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE
8159 case EXIT_REASON_MONITOR_INSTRUCTION:
8160 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8161 case EXIT_REASON_PAUSE_INSTRUCTION:
8162 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8163 nested_cpu_has2(vmcs12,
8164 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8165 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 8166 return false;
644d711a 8167 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 8168 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE
8169 case EXIT_REASON_APIC_ACCESS:
8170 return nested_cpu_has2(vmcs12,
8171 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 8172 case EXIT_REASON_APIC_WRITE:
608406e2
WV
8173 case EXIT_REASON_EOI_INDUCED:
8174 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 8175 return true;
644d711a 8176 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE
8177 /*
8178 * L0 always deals with the EPT violation. If nested EPT is
8179 * used, and the nested mmu code discovers that the address is
8180 * missing in the guest EPT table (EPT12), the EPT violation
8181 * will be injected with nested_ept_inject_page_fault()
8182 */
1d804d07 8183 return false;
644d711a 8184 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE
8185 /*
8186 * L2 never uses directly L1's EPT, but rather L0's own EPT
8187 * table (shadow on EPT) or a merged EPT table that L0 built
8188 * (EPT on EPT). So any problems with the structure of the
8189 * table is L0's fault.
8190 */
1d804d07 8191 return false;
644d711a
NHE
8192 case EXIT_REASON_WBINVD:
8193 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8194 case EXIT_REASON_XSETBV:
1d804d07 8195 return true;
81dc01f7
WL
8196 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8197 /*
8198 * This should never happen, since it is not possible to
8199 * set XSS to a non-zero value---neither in L1 nor in L2.
8200 * If if it were, XSS would have to be checked against
8201 * the XSS exit bitmap in vmcs12.
8202 */
8203 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
55123e3c
WL
8204 case EXIT_REASON_PREEMPTION_TIMER:
8205 return false;
ab007cc9 8206 case EXIT_REASON_PML_FULL:
03efce6f 8207 /* We emulate PML support to L1. */
ab007cc9 8208 return false;
644d711a 8209 default:
1d804d07 8210 return true;
644d711a
NHE
8211 }
8212}
8213
7313c698
PB
8214static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8215{
8216 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8217
8218 /*
8219 * At this point, the exit interruption info in exit_intr_info
8220 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8221 * we need to query the in-kernel LAPIC.
8222 */
8223 WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8224 if ((exit_intr_info &
8225 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8226 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8227 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8228 vmcs12->vm_exit_intr_error_code =
8229 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8230 }
8231
8232 nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8233 vmcs_readl(EXIT_QUALIFICATION));
8234 return 1;
8235}
8236
586f9607
AK
8237static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8238{
8239 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8240 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8241}
8242
a3eaa864 8243static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
843e4330 8244{
a3eaa864
KH
8245 if (vmx->pml_pg) {
8246 __free_page(vmx->pml_pg);
8247 vmx->pml_pg = NULL;
8248 }
843e4330
KH
8249}
8250
54bf36aa 8251static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 8252{
54bf36aa 8253 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH
8254 u64 *pml_buf;
8255 u16 pml_idx;
8256
8257 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8258
8259 /* Do nothing if PML buffer is empty */
8260 if (pml_idx == (PML_ENTITY_NUM - 1))
8261 return;
8262
8263 /* PML index always points to next available PML buffer entity */
8264 if (pml_idx >= PML_ENTITY_NUM)
8265 pml_idx = 0;
8266 else
8267 pml_idx++;
8268
8269 pml_buf = page_address(vmx->pml_pg);
8270 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8271 u64 gpa;
8272
8273 gpa = pml_buf[pml_idx];
8274 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 8275 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH
8276 }
8277
8278 /* reset PML index */
8279 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8280}
8281
8282/*
8283 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8284 * Called before reporting dirty_bitmap to userspace.
8285 */
8286static void kvm_flush_pml_buffers(struct kvm *kvm)
8287{
8288 int i;
8289 struct kvm_vcpu *vcpu;
8290 /*
8291 * We only need to kick vcpu out of guest mode here, as PML buffer
8292 * is flushed at beginning of all VMEXITs, and it's obvious that only
8293 * vcpus running in guest are possible to have unflushed GPAs in PML
8294 * buffer.
8295 */
8296 kvm_for_each_vcpu(i, vcpu, kvm)
8297 kvm_vcpu_kick(vcpu);
8298}
8299
4eb64dce
PB
8300static void vmx_dump_sel(char *name, uint32_t sel)
8301{
8302 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
96794e4e 8303 name, vmcs_read16(sel),
4eb64dce
PB
8304 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8305 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8306 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8307}
8308
8309static void vmx_dump_dtsel(char *name, uint32_t limit)
8310{
8311 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8312 name, vmcs_read32(limit),
8313 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8314}
8315
8316static void dump_vmcs(void)
8317{
8318 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8319 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8320 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8321 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8322 u32 secondary_exec_control = 0;
8323 unsigned long cr4 = vmcs_readl(GUEST_CR4);
f3531054 8324 u64 efer = vmcs_read64(GUEST_IA32_EFER);
4eb64dce
PB
8325 int i, n;
8326
8327 if (cpu_has_secondary_exec_ctrls())
8328 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8329
8330 pr_err("*** Guest State ***\n");
8331 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8332 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8333 vmcs_readl(CR0_GUEST_HOST_MASK));
8334 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8335 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8336 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8337 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8338 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8339 {
845c5b40
PB
8340 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8341 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8342 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8343 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
4eb64dce
PB
8344 }
8345 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8346 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8347 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8348 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8349 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8350 vmcs_readl(GUEST_SYSENTER_ESP),
8351 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8352 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8353 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8354 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8355 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8356 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8357 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8358 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8359 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8360 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8361 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8362 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8363 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
845c5b40
PB
8364 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8365 efer, vmcs_read64(GUEST_IA32_PAT));
8366 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8367 vmcs_read64(GUEST_IA32_DEBUGCTL),
4eb64dce
PB
8368 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8369 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
845c5b40
PB
8370 pr_err("PerfGlobCtl = 0x%016llx\n",
8371 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
4eb64dce 8372 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
845c5b40 8373 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
4eb64dce
PB
8374 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8375 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8376 vmcs_read32(GUEST_ACTIVITY_STATE));
8377 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8378 pr_err("InterruptStatus = %04x\n",
8379 vmcs_read16(GUEST_INTR_STATUS));
8380
8381 pr_err("*** Host State ***\n");
8382 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8383 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8384 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8385 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8386 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8387 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8388 vmcs_read16(HOST_TR_SELECTOR));
8389 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8390 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8391 vmcs_readl(HOST_TR_BASE));
8392 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8393 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8394 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8395 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8396 vmcs_readl(HOST_CR4));
8397 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8398 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8399 vmcs_read32(HOST_IA32_SYSENTER_CS),
8400 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8401 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
845c5b40
PB
8402 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8403 vmcs_read64(HOST_IA32_EFER),
8404 vmcs_read64(HOST_IA32_PAT));
4eb64dce 8405 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
845c5b40
PB
8406 pr_err("PerfGlobCtl = 0x%016llx\n",
8407 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
4eb64dce
PB
8408
8409 pr_err("*** Control State ***\n");
8410 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8411 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8412 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8413 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8414 vmcs_read32(EXCEPTION_BITMAP),
8415 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8416 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8417 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8418 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8419 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8420 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8421 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8422 vmcs_read32(VM_EXIT_INTR_INFO),
8423 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8424 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8425 pr_err(" reason=%08x qualification=%016lx\n",
8426 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8427 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8428 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8429 vmcs_read32(IDT_VECTORING_ERROR_CODE));
845c5b40 8430 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8cfe9866 8431 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
845c5b40
PB
8432 pr_err("TSC Multiplier = 0x%016llx\n",
8433 vmcs_read64(TSC_MULTIPLIER));
4eb64dce
PB
8434 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8435 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8436 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8437 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8438 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
845c5b40 8439 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
4eb64dce
PB
8440 n = vmcs_read32(CR3_TARGET_COUNT);
8441 for (i = 0; i + 1 < n; i += 4)
8442 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8443 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8444 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8445 if (i < n)
8446 pr_err("CR3 target%u=%016lx\n",
8447 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8448 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8449 pr_err("PLE Gap=%08x Window=%08x\n",
8450 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8451 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8452 pr_err("Virtual processor ID = 0x%04x\n",
8453 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8454}
8455
6aa8b732
AK
8456/*
8457 * The guest has exited. See if we can fix it or if we need userspace
8458 * assistance.
8459 */
851ba692 8460static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 8461{
29bd8a78 8462 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 8463 u32 exit_reason = vmx->exit_reason;
1155f76a 8464 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 8465
8b89fe1f 8466 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
db1c056c 8467 vcpu->arch.gpa_available = false;
8b89fe1f 8468
843e4330
KH
8469 /*
8470 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8471 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8472 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8473 * mode as if vcpus is in root mode, the PML buffer must has been
8474 * flushed already.
8475 */
8476 if (enable_pml)
54bf36aa 8477 vmx_flush_pml_buffer(vcpu);
843e4330 8478
80ced186 8479 /* If guest state is invalid, start emulating */
14168786 8480 if (vmx->emulation_required)
80ced186 8481 return handle_invalid_guest_state(vcpu);
1d5a4d9b 8482
7313c698
PB
8483 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
8484 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
644d711a 8485
5120702e 8486 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 8487 dump_vmcs();
5120702e
MG
8488 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8489 vcpu->run->fail_entry.hardware_entry_failure_reason
8490 = exit_reason;
8491 return 0;
8492 }
8493
29bd8a78 8494 if (unlikely(vmx->fail)) {
851ba692
AK
8495 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8496 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK
8497 = vmcs_read32(VM_INSTRUCTION_ERROR);
8498 return 0;
8499 }
6aa8b732 8500
b9bf6882
XG
8501 /*
8502 * Note:
8503 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8504 * delivery event since it indicates guest is accessing MMIO.
8505 * The vm-exit can be triggered again after return to guest that
8506 * will cause infinite loop.
8507 */
d77c26fc 8508 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 8509 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 8510 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b244c9fc 8511 exit_reason != EXIT_REASON_PML_FULL &&
b9bf6882
XG
8512 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8513 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8514 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
70bcd708 8515 vcpu->run->internal.ndata = 3;
b9bf6882
XG
8516 vcpu->run->internal.data[0] = vectoring_info;
8517 vcpu->run->internal.data[1] = exit_reason;
70bcd708
PB
8518 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8519 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8520 vcpu->run->internal.ndata++;
8521 vcpu->run->internal.data[3] =
8522 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8523 }
b9bf6882
XG
8524 return 0;
8525 }
3b86cd99 8526
6aa8b732
AK
8527 if (exit_reason < kvm_vmx_max_exit_handlers
8528 && kvm_vmx_exit_handlers[exit_reason])
851ba692 8529 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 8530 else {
6c6c5e03
RK
8531 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8532 exit_reason);
2bc19dc3
MT
8533 kvm_queue_exception(vcpu, UD_VECTOR);
8534 return 1;
6aa8b732 8535 }
6aa8b732
AK
8536}
8537
95ba8273 8538static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 8539{
a7c0b07d
WL
8540 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8541
8542 if (is_guest_mode(vcpu) &&
8543 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8544 return;
8545
95ba8273 8546 if (irr == -1 || tpr < irr) {
6e5d865c
YS
8547 vmcs_write32(TPR_THRESHOLD, 0);
8548 return;
8549 }
8550
95ba8273 8551 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS
8552}
8553
8d14695f
YZ
8554static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8555{
8556 u32 sec_exec_control;
8557
dccbfcf5
RK
8558 /* Postpone execution until vmcs01 is the current VMCS. */
8559 if (is_guest_mode(vcpu)) {
8560 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8561 return;
8562 }
8563
f6e90f9e 8564 if (!cpu_has_vmx_virtualize_x2apic_mode())
8d14695f
YZ
8565 return;
8566
35754c98 8567 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ
8568 return;
8569
8570 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8571
8572 if (set) {
8573 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8574 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8575 } else {
8576 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8577 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
fb6c8198 8578 vmx_flush_tlb_ept_only(vcpu);
8d14695f
YZ
8579 }
8580 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8581
8582 vmx_set_msr_bitmap(vcpu);
8583}
8584
38b99173
TC
8585static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8586{
8587 struct vcpu_vmx *vmx = to_vmx(vcpu);
8588
8589 /*
8590 * Currently we do not handle the nested case where L2 has an
8591 * APIC access page of its own; that page is still pinned.
8592 * Hence, we skip the case where the VCPU is in guest mode _and_
8593 * L1 prepared an APIC access page for L2.
8594 *
8595 * For the case where L1 and L2 share the same APIC access page
8596 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8597 * in the vmcs12), this function will only update either the vmcs01
8598 * or the vmcs02. If the former, the vmcs02 will be updated by
8599 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8600 * the next L2->L1 exit.
8601 */
8602 if (!is_guest_mode(vcpu) ||
4f2777bc 8603 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
fb6c8198 8604 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
38b99173 8605 vmcs_write64(APIC_ACCESS_ADDR, hpa);
fb6c8198
JM
8606 vmx_flush_tlb_ept_only(vcpu);
8607 }
38b99173
TC
8608}
8609
67c9dddc 8610static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
c7c9c56c
YZ
8611{
8612 u16 status;
8613 u8 old;
8614
67c9dddc
PB
8615 if (max_isr == -1)
8616 max_isr = 0;
c7c9c56c
YZ
8617
8618 status = vmcs_read16(GUEST_INTR_STATUS);
8619 old = status >> 8;
67c9dddc 8620 if (max_isr != old) {
c7c9c56c 8621 status &= 0xff;
67c9dddc 8622 status |= max_isr << 8;
c7c9c56c
YZ
8623 vmcs_write16(GUEST_INTR_STATUS, status);
8624 }
8625}
8626
8627static void vmx_set_rvi(int vector)
8628{
8629 u16 status;
8630 u8 old;
8631
4114c27d
WW
8632 if (vector == -1)
8633 vector = 0;
8634
c7c9c56c
YZ
8635 status = vmcs_read16(GUEST_INTR_STATUS);
8636 old = (u8)status & 0xff;
8637 if ((u8)vector != old) {
8638 status &= ~0xff;
8639 status |= (u8)vector;
8640 vmcs_write16(GUEST_INTR_STATUS, status);
8641 }
8642}
8643
8644static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8645{
4114c27d
WW
8646 if (!is_guest_mode(vcpu)) {
8647 vmx_set_rvi(max_irr);
8648 return;
8649 }
8650
c7c9c56c
YZ
8651 if (max_irr == -1)
8652 return;
8653
963fee16 8654 /*
4114c27d
WW
8655 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8656 * handles it.
963fee16 8657 */
4114c27d 8658 if (nested_exit_on_intr(vcpu))
963fee16
WL
8659 return;
8660
963fee16 8661 /*
4114c27d 8662 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL
8663 * is run without virtual interrupt delivery.
8664 */
8665 if (!kvm_event_needs_reinjection(vcpu) &&
8666 vmx_interrupt_allowed(vcpu)) {
8667 kvm_queue_interrupt(vcpu, max_irr, false);
8668 vmx_inject_irq(vcpu);
8669 }
c7c9c56c
YZ
8670}
8671
76dfafd5 8672static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
810e6def
PB
8673{
8674 struct vcpu_vmx *vmx = to_vmx(vcpu);
76dfafd5 8675 int max_irr;
810e6def 8676
76dfafd5
PB
8677 WARN_ON(!vcpu->arch.apicv_active);
8678 if (pi_test_on(&vmx->pi_desc)) {
8679 pi_clear_on(&vmx->pi_desc);
8680 /*
8681 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8682 * But on x86 this is just a compiler barrier anyway.
8683 */
8684 smp_mb__after_atomic();
8685 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8686 } else {
8687 max_irr = kvm_lapic_find_highest_irr(vcpu);
8688 }
8689 vmx_hwapic_irr_update(vcpu, max_irr);
8690 return max_irr;
810e6def
PB
8691}
8692
6308630b 8693static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
c7c9c56c 8694{
d62caabb 8695 if (!kvm_vcpu_apicv_active(vcpu))
3d81bc7e
YZ
8696 return;
8697
c7c9c56c
YZ
8698 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8699 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8700 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8701 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8702}
8703
967235d3
PB
8704static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8705{
8706 struct vcpu_vmx *vmx = to_vmx(vcpu);
8707
8708 pi_clear_on(&vmx->pi_desc);
8709 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8710}
8711
51aa01d1 8712static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8713{
48ae0fb4
JM
8714 u32 exit_intr_info = 0;
8715 u16 basic_exit_reason = (u16)vmx->exit_reason;
00eba012 8716
48ae0fb4
JM
8717 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8718 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
00eba012
AK
8719 return;
8720
48ae0fb4
JM
8721 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
8722 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8723 vmx->exit_intr_info = exit_intr_info;
a0861c02 8724
1261bfa3
WL
8725 /* if exit due to PF check for async PF */
8726 if (is_page_fault(exit_intr_info))
8727 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
8728
a0861c02 8729 /* Handle machine checks before interrupts are enabled */
48ae0fb4
JM
8730 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
8731 is_machine_check(exit_intr_info))
a0861c02
AK
8732 kvm_machine_check();
8733
20f65983 8734 /* We need to handle NMIs before interrupts are enabled */
ef85b673 8735 if (is_nmi(exit_intr_info)) {
ff9d07a0 8736 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8737 asm("int $2");
ff9d07a0
ZY
8738 kvm_after_handle_nmi(&vmx->vcpu);
8739 }
51aa01d1 8740}
20f65983 8741
a547c6db
YZ
8742static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8743{
8744 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3f62de5f 8745 register void *__sp asm(_ASM_SP);
a547c6db 8746
a547c6db
YZ
8747 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8748 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8749 unsigned int vector;
8750 unsigned long entry;
8751 gate_desc *desc;
8752 struct vcpu_vmx *vmx = to_vmx(vcpu);
8753#ifdef CONFIG_X86_64
8754 unsigned long tmp;
8755#endif
8756
8757 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8758 desc = (gate_desc *)vmx->host_idt_base + vector;
8759 entry = gate_offset(*desc);
8760 asm volatile(
8761#ifdef CONFIG_X86_64
8762 "mov %%" _ASM_SP ", %[sp]\n\t"
8763 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8764 "push $%c[ss]\n\t"
8765 "push %[sp]\n\t"
8766#endif
8767 "pushf\n\t"
a547c6db
YZ
8768 __ASM_SIZE(push) " $%c[cs]\n\t"
8769 "call *%[entry]\n\t"
8770 :
8771#ifdef CONFIG_X86_64
3f62de5f 8772 [sp]"=&r"(tmp),
a547c6db 8773#endif
3f62de5f 8774 "+r"(__sp)
a547c6db
YZ
8775 :
8776 [entry]"r"(entry),
8777 [ss]"i"(__KERNEL_DS),
8778 [cs]"i"(__KERNEL_CS)
8779 );
f2485b3e 8780 }
a547c6db 8781}
c207aee4 8782STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
a547c6db 8783
6d396b55
PB
8784static bool vmx_has_high_real_mode_segbase(void)
8785{
8786 return enable_unrestricted_guest || emulate_invalid_guest_state;
8787}
8788
da8999d3
LJ
8789static bool vmx_mpx_supported(void)
8790{
8791 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8792 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8793}
8794
55412b2e
WL
8795static bool vmx_xsaves_supported(void)
8796{
8797 return vmcs_config.cpu_based_2nd_exec_ctrl &
8798 SECONDARY_EXEC_XSAVES;
8799}
8800
51aa01d1
AK
8801static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8802{
c5ca8e57 8803 u32 exit_intr_info;
51aa01d1
AK
8804 bool unblock_nmi;
8805 u8 vector;
8806 bool idtv_info_valid;
8807
8808 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8809
4c4a6f79 8810 if (vmx->loaded_vmcs->nmi_known_unmasked)
2c82878b
PB
8811 return;
8812 /*
8813 * Can't use vmx->exit_intr_info since we're not sure what
8814 * the exit reason is.
8815 */
8816 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8817 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8818 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8819 /*
8820 * SDM 3: 27.7.1.2 (September 2008)
8821 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8822 * a guest IRET fault.
8823 * SDM 3: 23.2.2 (September 2008)
8824 * Bit 12 is undefined in any of the following cases:
8825 * If the VM exit sets the valid bit in the IDT-vectoring
8826 * information field.
8827 * If the VM exit is due to a double fault.
8828 */
8829 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8830 vector != DF_VECTOR && !idtv_info_valid)
8831 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8832 GUEST_INTR_STATE_NMI);
8833 else
4c4a6f79 8834 vmx->loaded_vmcs->nmi_known_unmasked =
2c82878b
PB
8835 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8836 & GUEST_INTR_STATE_NMI);
51aa01d1
AK
8837}
8838
3ab66e8a 8839static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK
8840 u32 idt_vectoring_info,
8841 int instr_len_field,
8842 int error_code_field)
51aa01d1 8843{
51aa01d1
AK
8844 u8 vector;
8845 int type;
8846 bool idtv_info_valid;
8847
8848 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8849
3ab66e8a
JK
8850 vcpu->arch.nmi_injected = false;
8851 kvm_clear_exception_queue(vcpu);
8852 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN
8853
8854 if (!idtv_info_valid)
8855 return;
8856
3ab66e8a 8857 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8858
668f612f
AK
8859 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8860 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8861
64a7ec06 8862 switch (type) {
37b96e98 8863 case INTR_TYPE_NMI_INTR:
3ab66e8a 8864 vcpu->arch.nmi_injected = true;
668f612f 8865 /*
7b4a25cb 8866 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN
8867 * Clear bit "block by NMI" before VM entry if a NMI
8868 * delivery faulted.
668f612f 8869 */
3ab66e8a 8870 vmx_set_nmi_mask(vcpu, false);
37b96e98 8871 break;
37b96e98 8872 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8873 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN
8874 /* fall through */
8875 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8876 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8877 u32 err = vmcs_read32(error_code_field);
851eb667 8878 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8879 } else
851eb667 8880 kvm_requeue_exception(vcpu, vector);
37b96e98 8881 break;
66fd3f7f 8882 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8883 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8884 /* fall through */
37b96e98 8885 case INTR_TYPE_EXT_INTR:
3ab66e8a 8886 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN
8887 break;
8888 default:
8889 break;
f7d9238f 8890 }
cf393f75
AK
8891}
8892
83422e17
AK
8893static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8894{
3ab66e8a 8895 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK
8896 VM_EXIT_INSTRUCTION_LEN,
8897 IDT_VECTORING_ERROR_CODE);
8898}
8899
b463a6f7
AK
8900static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8901{
3ab66e8a 8902 __vmx_complete_interrupts(vcpu,
b463a6f7
AK
8903 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8904 VM_ENTRY_INSTRUCTION_LEN,
8905 VM_ENTRY_EXCEPTION_ERROR_CODE);
8906
8907 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8908}
8909
d7cd9796
GN
8910static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8911{
8912 int i, nr_msrs;
8913 struct perf_guest_switch_msr *msrs;
8914
8915 msrs = perf_guest_get_msrs(&nr_msrs);
8916
8917 if (!msrs)
8918 return;
8919
8920 for (i = 0; i < nr_msrs; i++)
8921 if (msrs[i].host == msrs[i].guest)
8922 clear_atomic_switch_msr(vmx, msrs[i].msr);
8923 else
8924 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8925 msrs[i].host);
8926}
8927
33365e7a 8928static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
64672c95
YJ
8929{
8930 struct vcpu_vmx *vmx = to_vmx(vcpu);
8931 u64 tscl;
8932 u32 delta_tsc;
8933
8934 if (vmx->hv_deadline_tsc == -1)
8935 return;
8936
8937 tscl = rdtsc();
8938 if (vmx->hv_deadline_tsc > tscl)
8939 /* sure to be 32 bit only because checked on set_hv_timer */
8940 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8941 cpu_preemption_timer_multi);
8942 else
8943 delta_tsc = 0;
8944
8945 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8946}
8947
a3b5ba49 8948static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8949{
a2fa3e9f 8950 struct vcpu_vmx *vmx = to_vmx(vcpu);
d6e41f11 8951 unsigned long debugctlmsr, cr3, cr4;
104f226b 8952
104f226b
AK
8953 /* Don't enter VMX if guest state is invalid, let the exit handler
8954 start emulation until we arrive back to a valid state */
14168786 8955 if (vmx->emulation_required)
104f226b
AK
8956 return;
8957
a7653ecd
RK
8958 if (vmx->ple_window_dirty) {
8959 vmx->ple_window_dirty = false;
8960 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8961 }
8962
012f83cb
AG
8963 if (vmx->nested.sync_shadow_vmcs) {
8964 copy_vmcs12_to_shadow(vmx);
8965 vmx->nested.sync_shadow_vmcs = false;
8966 }
8967
104f226b
AK
8968 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8969 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8970 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8971 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8972
d6e41f11
AL
8973 cr3 = __get_current_cr3_fast();
8974 if (unlikely(cr3 != vmx->host_state.vmcs_host_cr3)) {
8975 vmcs_writel(HOST_CR3, cr3);
8976 vmx->host_state.vmcs_host_cr3 = cr3;
8977 }
8978
1e02ce4c 8979 cr4 = cr4_read_shadow();
d974baa3
AL
8980 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8981 vmcs_writel(HOST_CR4, cr4);
8982 vmx->host_state.vmcs_host_cr4 = cr4;
8983 }
8984
104f226b
AK
8985 /* When single-stepping over STI and MOV SS, we must clear the
8986 * corresponding interruptibility bits in the guest state. Otherwise
8987 * vmentry fails as it then expects bit 14 (BS) in pending debug
8988 * exceptions being set, but that's not correct for the guest debugging
8989 * case. */
8990 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8991 vmx_set_interrupt_shadow(vcpu, 0);
8992
1be0e61c
XG
8993 if (vmx->guest_pkru_valid)
8994 __write_pkru(vmx->guest_pkru);
8995
d7cd9796 8996 atomic_switch_perf_msrs(vmx);
2a7921b7 8997 debugctlmsr = get_debugctlmsr();
d7cd9796 8998
64672c95
YJ
8999 vmx_arm_hv_timer(vcpu);
9000
d462b819 9001 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 9002 asm(
6aa8b732 9003 /* Store host registers */
b188c81f
AK
9004 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9005 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9006 "push %%" _ASM_CX " \n\t"
9007 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 9008 "je 1f \n\t"
b188c81f 9009 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 9010 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 9011 "1: \n\t"
d3edefc0 9012 /* Reload cr2 if changed */
b188c81f
AK
9013 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9014 "mov %%cr2, %%" _ASM_DX " \n\t"
9015 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 9016 "je 2f \n\t"
b188c81f 9017 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 9018 "2: \n\t"
6aa8b732 9019 /* Check if vmlaunch of vmresume is needed */
e08aa78a 9020 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 9021 /* Load guest registers. Don't clobber flags. */
b188c81f
AK
9022 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9023 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9024 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9025 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9026 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9027 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 9028#ifdef CONFIG_X86_64
e08aa78a
AK
9029 "mov %c[r8](%0), %%r8 \n\t"
9030 "mov %c[r9](%0), %%r9 \n\t"
9031 "mov %c[r10](%0), %%r10 \n\t"
9032 "mov %c[r11](%0), %%r11 \n\t"
9033 "mov %c[r12](%0), %%r12 \n\t"
9034 "mov %c[r13](%0), %%r13 \n\t"
9035 "mov %c[r14](%0), %%r14 \n\t"
9036 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 9037#endif
b188c81f 9038 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 9039
6aa8b732 9040 /* Enter guest mode */
83287ea4 9041 "jne 1f \n\t"
4ecac3fd 9042 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK
9043 "jmp 2f \n\t"
9044 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9045 "2: "
6aa8b732 9046 /* Save guest registers, load host registers, keep flags */
b188c81f 9047 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 9048 "pop %0 \n\t"
b188c81f
AK
9049 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9050 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9051 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9052 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9053 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9054 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9055 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 9056#ifdef CONFIG_X86_64
e08aa78a
AK
9057 "mov %%r8, %c[r8](%0) \n\t"
9058 "mov %%r9, %c[r9](%0) \n\t"
9059 "mov %%r10, %c[r10](%0) \n\t"
9060 "mov %%r11, %c[r11](%0) \n\t"
9061 "mov %%r12, %c[r12](%0) \n\t"
9062 "mov %%r13, %c[r13](%0) \n\t"
9063 "mov %%r14, %c[r14](%0) \n\t"
9064 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 9065#endif
b188c81f
AK
9066 "mov %%cr2, %%" _ASM_AX " \n\t"
9067 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 9068
b188c81f 9069 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 9070 "setbe %c[fail](%0) \n\t"
83287ea4
AK
9071 ".pushsection .rodata \n\t"
9072 ".global vmx_return \n\t"
9073 "vmx_return: " _ASM_PTR " 2b \n\t"
9074 ".popsection"
e08aa78a 9075 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 9076 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 9077 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 9078 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX
9079 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9080 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9081 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9082 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9083 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9084 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9085 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 9086#ifdef CONFIG_X86_64
ad312c7c
ZX
9087 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9088 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9089 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9090 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9091 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9092 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9093 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9094 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 9095#endif
40712fae
AK
9096 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9097 [wordsize]"i"(sizeof(ulong))
c2036300
LV
9098 : "cc", "memory"
9099#ifdef CONFIG_X86_64
b188c81f 9100 , "rax", "rbx", "rdi", "rsi"
c2036300 9101 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK
9102#else
9103 , "eax", "ebx", "edi", "esi"
c2036300
LV
9104#endif
9105 );
6aa8b732 9106
2a7921b7
GN
9107 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9108 if (debugctlmsr)
9109 update_debugctlmsr(debugctlmsr);
9110
aa67f609
AK
9111#ifndef CONFIG_X86_64
9112 /*
9113 * The sysexit path does not restore ds/es, so we must set them to
9114 * a reasonable value ourselves.
9115 *
9116 * We can't defer this to vmx_load_host_state() since that function
9117 * may be executed in interrupt context, which saves and restore segments
9118 * around it, nullifying its effect.
9119 */
9120 loadsegment(ds, __USER_DS);
9121 loadsegment(es, __USER_DS);
9122#endif
9123
6de4f3ad 9124 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 9125 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 9126 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 9127 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 9128 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT
9129 vcpu->arch.regs_dirty = 0;
9130
1155f76a
AK
9131 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9132
d462b819 9133 vmx->loaded_vmcs->launched = 1;
1b6269db 9134
51aa01d1 9135 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1 9136
1be0e61c
XG
9137 /*
9138 * eager fpu is enabled if PKEY is supported and CR4 is switched
9139 * back on host, so it is safe to read guest PKRU from current
9140 * XSAVE.
9141 */
9142 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9143 vmx->guest_pkru = __read_pkru();
9144 if (vmx->guest_pkru != vmx->host_pkru) {
9145 vmx->guest_pkru_valid = true;
9146 __write_pkru(vmx->host_pkru);
9147 } else
9148 vmx->guest_pkru_valid = false;
9149 }
9150
e0b890d3
GN
9151 /*
9152 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9153 * we did not inject a still-pending event to L1 now because of
9154 * nested_run_pending, we need to re-enable this bit.
9155 */
9156 if (vmx->nested.nested_run_pending)
9157 kvm_make_request(KVM_REQ_EVENT, vcpu);
9158
9159 vmx->nested.nested_run_pending = 0;
9160
51aa01d1
AK
9161 vmx_complete_atomic_exit(vmx);
9162 vmx_recover_nmi_blocking(vmx);
cf393f75 9163 vmx_complete_interrupts(vmx);
6aa8b732 9164}
c207aee4 9165STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
6aa8b732 9166
1279a6b1 9167static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
4fa7734c
PB
9168{
9169 struct vcpu_vmx *vmx = to_vmx(vcpu);
9170 int cpu;
9171
1279a6b1 9172 if (vmx->loaded_vmcs == vmcs)
4fa7734c
PB
9173 return;
9174
9175 cpu = get_cpu();
1279a6b1 9176 vmx->loaded_vmcs = vmcs;
4fa7734c
PB
9177 vmx_vcpu_put(vcpu);
9178 vmx_vcpu_load(vcpu, cpu);
9179 vcpu->cpu = cpu;
9180 put_cpu();
9181}
9182
2f1fe811
JM
9183/*
9184 * Ensure that the current vmcs of the logical processor is the
9185 * vmcs01 of the vcpu before calling free_nested().
9186 */
9187static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9188{
9189 struct vcpu_vmx *vmx = to_vmx(vcpu);
9190 int r;
9191
9192 r = vcpu_load(vcpu);
9193 BUG_ON(r);
1279a6b1 9194 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
2f1fe811
JM
9195 free_nested(vmx);
9196 vcpu_put(vcpu);
9197}
9198
6aa8b732
AK
9199static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9200{
fb3f0f51
RR
9201 struct vcpu_vmx *vmx = to_vmx(vcpu);
9202
843e4330 9203 if (enable_pml)
a3eaa864 9204 vmx_destroy_pml_buffer(vmx);
991e7a0e 9205 free_vpid(vmx->vpid);
4fa7734c 9206 leave_guest_mode(vcpu);
2f1fe811 9207 vmx_free_vcpu_nested(vcpu);
4fa7734c 9208 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR
9209 kfree(vmx->guest_msrs);
9210 kvm_vcpu_uninit(vcpu);
a4770347 9211 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK
9212}
9213
fb3f0f51 9214static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 9215{
fb3f0f51 9216 int err;
c16f862d 9217 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 9218 int cpu;
6aa8b732 9219
a2fa3e9f 9220 if (!vmx)
fb3f0f51
RR
9221 return ERR_PTR(-ENOMEM);
9222
991e7a0e 9223 vmx->vpid = allocate_vpid();
2384d2b3 9224
fb3f0f51
RR
9225 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9226 if (err)
9227 goto free_vcpu;
965b58a5 9228
4e59516a
PF
9229 err = -ENOMEM;
9230
9231 /*
9232 * If PML is turned on, failure on enabling PML just results in failure
9233 * of creating the vcpu, therefore we can simplify PML logic (by
9234 * avoiding dealing with cases, such as enabling PML partially on vcpus
9235 * for the guest, etc.
9236 */
9237 if (enable_pml) {
9238 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9239 if (!vmx->pml_pg)
9240 goto uninit_vcpu;
9241 }
9242
a2fa3e9f 9243 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB
9244 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9245 > PAGE_SIZE);
0123be42 9246
4e59516a
PF
9247 if (!vmx->guest_msrs)
9248 goto free_pml;
965b58a5 9249
d462b819
NHE
9250 vmx->loaded_vmcs = &vmx->vmcs01;
9251 vmx->loaded_vmcs->vmcs = alloc_vmcs();
355f4fb1 9252 vmx->loaded_vmcs->shadow_vmcs = NULL;
d462b819 9253 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 9254 goto free_msrs;
d462b819 9255 loaded_vmcs_init(vmx->loaded_vmcs);
a2fa3e9f 9256
15ad7146
AK
9257 cpu = get_cpu();
9258 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 9259 vmx->vcpu.cpu = cpu;
8b9cf98c 9260 err = vmx_vcpu_setup(vmx);
fb3f0f51 9261 vmx_vcpu_put(&vmx->vcpu);
15ad7146 9262 put_cpu();
fb3f0f51
RR
9263 if (err)
9264 goto free_vmcs;
35754c98 9265 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK
9266 err = alloc_apic_access_page(kvm);
9267 if (err)
5e4a0b3c 9268 goto free_vmcs;
a63cb560 9269 }
fb3f0f51 9270
b927a3ce
SY
9271 if (enable_ept) {
9272 if (!kvm->arch.ept_identity_map_addr)
9273 kvm->arch.ept_identity_map_addr =
9274 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC
9275 err = init_rmode_identity_map(kvm);
9276 if (err)
93ea5388 9277 goto free_vmcs;
b927a3ce 9278 }
b7ebfb05 9279
5c614b35 9280 if (nested) {
b9c237bb 9281 nested_vmx_setup_ctls_msrs(vmx);
5c614b35
WL
9282 vmx->nested.vpid02 = allocate_vpid();
9283 }
b9c237bb 9284
705699a1 9285 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE
9286 vmx->nested.current_vmptr = -1ull;
9287 vmx->nested.current_vmcs12 = NULL;
9288
37e4c997
HZ
9289 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9290
fb3f0f51
RR
9291 return &vmx->vcpu;
9292
9293free_vmcs:
5c614b35 9294 free_vpid(vmx->nested.vpid02);
5f3fbc34 9295 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 9296free_msrs:
fb3f0f51 9297 kfree(vmx->guest_msrs);
4e59516a
PF
9298free_pml:
9299 vmx_destroy_pml_buffer(vmx);
fb3f0f51
RR
9300uninit_vcpu:
9301 kvm_vcpu_uninit(&vmx->vcpu);
9302free_vcpu:
991e7a0e 9303 free_vpid(vmx->vpid);
a4770347 9304 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 9305 return ERR_PTR(err);
6aa8b732
AK
9306}
9307
002c7f7c
YS
9308static void __init vmx_check_processor_compat(void *rtn)
9309{
9310 struct vmcs_config vmcs_conf;
9311
9312 *(int *)rtn = 0;
9313 if (setup_vmcs_config(&vmcs_conf) < 0)
9314 *(int *)rtn = -EIO;
9315 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9316 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9317 smp_processor_id());
9318 *(int *)rtn = -EIO;
9319 }
9320}
9321
67253af5
SY
9322static int get_ept_level(void)
9323{
9324 return VMX_EPT_DEFAULT_GAW + 1;
9325}
9326
4b12f0de 9327static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 9328{
b18d5431
XG
9329 u8 cache;
9330 u64 ipat = 0;
4b12f0de 9331
522c68c4 9332 /* For VT-d and EPT combination
606decd6 9333 * 1. MMIO: always map as UC
522c68c4
SY
9334 * 2. EPT with VT-d:
9335 * a. VT-d without snooping control feature: can't guarantee the
606decd6 9336 * result, try to trust guest.
522c68c4
SY
9337 * b. VT-d with snooping control feature: snooping control feature of
9338 * VT-d engine can guarantee the cache correctness. Just set it
9339 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 9340 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY
9341 * consistent with host MTRR
9342 */
606decd6
PB
9343 if (is_mmio) {
9344 cache = MTRR_TYPE_UNCACHABLE;
9345 goto exit;
9346 }
9347
9348 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG
9349 ipat = VMX_EPT_IPAT_BIT;
9350 cache = MTRR_TYPE_WRBACK;
9351 goto exit;
9352 }
9353
9354 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9355 ipat = VMX_EPT_IPAT_BIT;
0da029ed 9356 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG
9357 cache = MTRR_TYPE_WRBACK;
9358 else
9359 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG
9360 goto exit;
9361 }
9362
ff53604b 9363 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG
9364
9365exit:
9366 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY
9367}
9368
17cc3935 9369static int vmx_get_lpage_level(void)
344f414f 9370{
878403b7
SY
9371 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9372 return PT_DIRECTORY_LEVEL;
9373 else
9374 /* For shadow and EPT supported 1GB page */
9375 return PT_PDPE_LEVEL;
344f414f
JR
9376}
9377
feda805f
XG
9378static void vmcs_set_secondary_exec_control(u32 new_ctl)
9379{
9380 /*
9381 * These bits in the secondary execution controls field
9382 * are dynamic, the others are mostly based on the hypervisor
9383 * architecture and the guest's CPUID. Do not touch the
9384 * dynamic bits.
9385 */
9386 u32 mask =
9387 SECONDARY_EXEC_SHADOW_VMCS |
9388 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9389 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9390
9391 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9392
9393 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9394 (new_ctl & ~mask) | (cur_ctl & mask));
9395}
9396
8322ebbb
DM
9397/*
9398 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9399 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9400 */
9401static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9402{
9403 struct vcpu_vmx *vmx = to_vmx(vcpu);
9404 struct kvm_cpuid_entry2 *entry;
9405
9406 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9407 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9408
9409#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9410 if (entry && (entry->_reg & (_cpuid_mask))) \
9411 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9412} while (0)
9413
9414 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9415 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
9416 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
9417 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
9418 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
9419 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
9420 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
9421 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
9422 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
9423 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
9424 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9425 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
9426 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
9427 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
9428 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
9429
9430 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9431 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
9432 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
9433 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
9434 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
9435 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9436 cr4_fixed1_update(bit(11), ecx, bit(2));
9437
9438#undef cr4_fixed1_update
9439}
9440
0e851880
SY
9441static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9442{
4e47c7a6
SY
9443 struct kvm_cpuid_entry2 *best;
9444 struct vcpu_vmx *vmx = to_vmx(vcpu);
feda805f 9445 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
4e47c7a6 9446
4e47c7a6 9447 if (vmx_rdtscp_supported()) {
1cea0ce6
XG
9448 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9449 if (!rdtscp_enabled)
feda805f 9450 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
f36201e5 9451
8b97265a 9452 if (nested) {
1cea0ce6 9453 if (rdtscp_enabled)
8b97265a
PB
9454 vmx->nested.nested_vmx_secondary_ctls_high |=
9455 SECONDARY_EXEC_RDTSCP;
9456 else
9457 vmx->nested.nested_vmx_secondary_ctls_high &=
9458 ~SECONDARY_EXEC_RDTSCP;
9459 }
4e47c7a6 9460 }
ad756a16 9461
ad756a16
MJ
9462 /* Exposing INVPCID only when PCID is exposed */
9463 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9464 if (vmx_invpcid_supported() &&
29541bb8
XG
9465 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9466 !guest_cpuid_has_pcid(vcpu))) {
feda805f 9467 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
29541bb8 9468
ad756a16 9469 if (best)
4f977045 9470 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 9471 }
8b3e34e4 9472
45bdbcfd
HH
9473 if (cpu_has_secondary_exec_ctrls())
9474 vmcs_set_secondary_exec_control(secondary_exec_ctl);
feda805f 9475
37e4c997
HZ
9476 if (nested_vmx_allowed(vcpu))
9477 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9478 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9479 else
9480 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9481 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
8322ebbb
DM
9482
9483 if (nested_vmx_allowed(vcpu))
9484 nested_vmx_cr_fixed1_bits_update(vcpu);
0e851880
SY
9485}
9486
d4330ef2
JR
9487static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9488{
7b8050f5
NHE
9489 if (func == 1 && nested)
9490 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR
9491}
9492
25d92081
YZ
9493static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9494 struct x86_exception *fault)
9495{
533558bc 9496 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
c5f983f6 9497 struct vcpu_vmx *vmx = to_vmx(vcpu);
533558bc 9498 u32 exit_reason;
c5f983f6 9499 unsigned long exit_qualification = vcpu->arch.exit_qualification;
25d92081 9500
c5f983f6
BD
9501 if (vmx->nested.pml_full) {
9502 exit_reason = EXIT_REASON_PML_FULL;
9503 vmx->nested.pml_full = false;
9504 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9505 } else if (fault->error_code & PFERR_RSVD_MASK)
533558bc 9506 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 9507 else
533558bc 9508 exit_reason = EXIT_REASON_EPT_VIOLATION;
c5f983f6
BD
9509
9510 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
25d92081
YZ
9511 vmcs12->guest_physical_address = fault->address;
9512}
9513
995f00a6
PF
9514static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9515{
9516 return nested_ept_get_cr3(vcpu) & VMX_EPT_AD_ENABLE_BIT;
9517}
9518
155a97a3
NHE
9519/* Callbacks for nested_ept_init_mmu_context: */
9520
9521static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9522{
9523 /* return the page table to be shadowed - in our case, EPT12 */
9524 return get_vmcs12(vcpu)->ept_pointer;
9525}
9526
ae1e2d10 9527static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 9528{
995f00a6 9529 bool wants_ad;
ae1e2d10 9530
ad896af0 9531 WARN_ON(mmu_is_nested(vcpu));
995f00a6
PF
9532 wants_ad = nested_ept_ad_enabled(vcpu);
9533 if (wants_ad && !enable_ept_ad_bits)
ae1e2d10
PB
9534 return 1;
9535
9536 kvm_mmu_unload(vcpu);
ad896af0 9537 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb 9538 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
ae1e2d10 9539 VMX_EPT_EXECUTE_ONLY_BIT,
995f00a6 9540 wants_ad);
155a97a3
NHE
9541 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9542 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9543 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9544
9545 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
ae1e2d10 9546 return 0;
155a97a3
NHE
9547}
9548
9549static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9550{
9551 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9552}
9553
19d5f10b
EK
9554static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9555 u16 error_code)
9556{
9557 bool inequality, bit;
9558
9559 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9560 inequality =
9561 (error_code & vmcs12->page_fault_error_code_mask) !=
9562 vmcs12->page_fault_error_code_match;
9563 return inequality ^ bit;
9564}
9565
feaf0c7d
GN
9566static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9567 struct x86_exception *fault)
9568{
9569 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9570
9571 WARN_ON(!is_guest_mode(vcpu));
9572
7313c698 9573 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code)) {
b96fb439
PB
9574 vmcs12->vm_exit_intr_error_code = fault->error_code;
9575 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9576 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
9577 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
9578 fault->address);
7313c698 9579 } else {
feaf0c7d 9580 kvm_inject_page_fault(vcpu, fault);
7313c698 9581 }
feaf0c7d
GN
9582}
9583
6beb7bd5
JM
9584static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9585 struct vmcs12 *vmcs12);
9586
9587static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
a2bcba50
WL
9588 struct vmcs12 *vmcs12)
9589{
9590 struct vcpu_vmx *vmx = to_vmx(vcpu);
6beb7bd5 9591 u64 hpa;
a2bcba50
WL
9592
9593 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a2bcba50
WL
9594 /*
9595 * Translate L1 physical address to host physical
9596 * address for vmcs02. Keep the page pinned, so this
9597 * physical address remains valid. We keep a reference
9598 * to it so we can release it later.
9599 */
9600 if (vmx->nested.apic_access_page) /* shouldn't happen */
9601 nested_release_page(vmx->nested.apic_access_page);
9602 vmx->nested.apic_access_page =
9603 nested_get_page(vcpu, vmcs12->apic_access_addr);
6beb7bd5
JM
9604 /*
9605 * If translation failed, no matter: This feature asks
9606 * to exit when accessing the given address, and if it
9607 * can never be accessed, this feature won't do
9608 * anything anyway.
9609 */
9610 if (vmx->nested.apic_access_page) {
9611 hpa = page_to_phys(vmx->nested.apic_access_page);
9612 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9613 } else {
9614 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9615 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9616 }
9617 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9618 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9619 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9620 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9621 kvm_vcpu_reload_apic_access_page(vcpu);
a2bcba50 9622 }
a7c0b07d
WL
9623
9624 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
a7c0b07d
WL
9625 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9626 nested_release_page(vmx->nested.virtual_apic_page);
9627 vmx->nested.virtual_apic_page =
9628 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9629
9630 /*
6beb7bd5
JM
9631 * If translation failed, VM entry will fail because
9632 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9633 * Failing the vm entry is _not_ what the processor
9634 * does but it's basically the only possibility we
9635 * have. We could still enter the guest if CR8 load
9636 * exits are enabled, CR8 store exits are enabled, and
9637 * virtualize APIC access is disabled; in this case
9638 * the processor would never use the TPR shadow and we
9639 * could simply clear the bit from the execution
9640 * control. But such a configuration is useless, so
9641 * let's keep the code simple.
a7c0b07d 9642 */
6beb7bd5
JM
9643 if (vmx->nested.virtual_apic_page) {
9644 hpa = page_to_phys(vmx->nested.virtual_apic_page);
9645 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9646 }
a7c0b07d
WL
9647 }
9648
705699a1 9649 if (nested_cpu_has_posted_intr(vmcs12)) {
705699a1
WV
9650 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9651 kunmap(vmx->nested.pi_desc_page);
9652 nested_release_page(vmx->nested.pi_desc_page);
9653 }
9654 vmx->nested.pi_desc_page =
9655 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
705699a1
WV
9656 vmx->nested.pi_desc =
9657 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9658 if (!vmx->nested.pi_desc) {
9659 nested_release_page_clean(vmx->nested.pi_desc_page);
6beb7bd5 9660 return;
705699a1
WV
9661 }
9662 vmx->nested.pi_desc =
9663 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9664 (unsigned long)(vmcs12->posted_intr_desc_addr &
9665 (PAGE_SIZE - 1)));
6beb7bd5
JM
9666 vmcs_write64(POSTED_INTR_DESC_ADDR,
9667 page_to_phys(vmx->nested.pi_desc_page) +
9668 (unsigned long)(vmcs12->posted_intr_desc_addr &
9669 (PAGE_SIZE - 1)));
705699a1 9670 }
6beb7bd5
JM
9671 if (cpu_has_vmx_msr_bitmap() &&
9672 nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9673 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9674 ;
9675 else
9676 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9677 CPU_BASED_USE_MSR_BITMAPS);
a2bcba50
WL
9678}
9679
f4124500
JK
9680static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9681{
9682 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9683 struct vcpu_vmx *vmx = to_vmx(vcpu);
9684
9685 if (vcpu->arch.virtual_tsc_khz == 0)
9686 return;
9687
9688 /* Make sure short timeouts reliably trigger an immediate vmexit.
9689 * hrtimer_start does not guarantee this. */
9690 if (preemption_timeout <= 1) {
9691 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9692 return;
9693 }
9694
9695 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9696 preemption_timeout *= 1000000;
9697 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9698 hrtimer_start(&vmx->nested.preemption_timer,
9699 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9700}
9701
56a20510
JM
9702static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
9703 struct vmcs12 *vmcs12)
9704{
9705 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9706 return 0;
9707
9708 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
9709 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
9710 return -EINVAL;
9711
9712 return 0;
9713}
9714
3af18d9c
WV
9715static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9716 struct vmcs12 *vmcs12)
9717{
3af18d9c
WV
9718 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9719 return 0;
9720
5fa99cbe 9721 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
3af18d9c
WV
9722 return -EINVAL;
9723
9724 return 0;
9725}
9726
9727/*
9728 * Merge L0's and L1's MSR bitmap, return false to indicate that
9729 * we do not use the hardware.
9730 */
9731static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9732 struct vmcs12 *vmcs12)
9733{
82f0dd4b 9734 int msr;
f2b93280 9735 struct page *page;
d048c098
RK
9736 unsigned long *msr_bitmap_l1;
9737 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
f2b93280 9738
d048c098 9739 /* This shortcut is ok because we support only x2APIC MSRs so far. */
f2b93280
WV
9740 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9741 return false;
9742
9743 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
05d8d346 9744 if (!page)
f2b93280 9745 return false;
d048c098 9746 msr_bitmap_l1 = (unsigned long *)kmap(page);
f2b93280 9747
d048c098
RK
9748 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9749
f2b93280 9750 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV
9751 if (nested_cpu_has_apic_reg_virt(vmcs12))
9752 for (msr = 0x800; msr <= 0x8ff; msr++)
9753 nested_vmx_disable_intercept_for_msr(
d048c098 9754 msr_bitmap_l1, msr_bitmap_l0,
82f0dd4b 9755 msr, MSR_TYPE_R);
d048c098
RK
9756
9757 nested_vmx_disable_intercept_for_msr(
9758 msr_bitmap_l1, msr_bitmap_l0,
f2b93280
WV
9759 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9760 MSR_TYPE_R | MSR_TYPE_W);
d048c098 9761
608406e2 9762 if (nested_cpu_has_vid(vmcs12)) {
608406e2 9763 nested_vmx_disable_intercept_for_msr(
d048c098 9764 msr_bitmap_l1, msr_bitmap_l0,
608406e2
WV
9765 APIC_BASE_MSR + (APIC_EOI >> 4),
9766 MSR_TYPE_W);
9767 nested_vmx_disable_intercept_for_msr(
d048c098 9768 msr_bitmap_l1, msr_bitmap_l0,
608406e2
WV
9769 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9770 MSR_TYPE_W);
9771 }
82f0dd4b 9772 }
f2b93280
WV
9773 kunmap(page);
9774 nested_release_page_clean(page);
9775
9776 return true;
9777}
9778
9779static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9780 struct vmcs12 *vmcs12)
9781{
82f0dd4b 9782 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 9783 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV
9784 !nested_cpu_has_vid(vmcs12) &&
9785 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV
9786 return 0;
9787
9788 /*
9789 * If virtualize x2apic mode is enabled,
9790 * virtualize apic access must be disabled.
9791 */
82f0dd4b
WV
9792 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9793 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV
9794 return -EINVAL;
9795
608406e2
WV
9796 /*
9797 * If virtual interrupt delivery is enabled,
9798 * we must exit on external interrupts.
9799 */
9800 if (nested_cpu_has_vid(vmcs12) &&
9801 !nested_exit_on_intr(vcpu))
9802 return -EINVAL;
9803
705699a1
WV
9804 /*
9805 * bits 15:8 should be zero in posted_intr_nv,
9806 * the descriptor address has been already checked
9807 * in nested_get_vmcs12_pages.
9808 */
9809 if (nested_cpu_has_posted_intr(vmcs12) &&
9810 (!nested_cpu_has_vid(vmcs12) ||
9811 !nested_exit_intr_ack_set(vcpu) ||
9812 vmcs12->posted_intr_nv & 0xff00))
9813 return -EINVAL;
9814
f2b93280
WV
9815 /* tpr shadow is needed by all apicv features. */
9816 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9817 return -EINVAL;
9818
9819 return 0;
3af18d9c
WV
9820}
9821
e9ac033e
EK
9822static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9823 unsigned long count_field,
92d71bc6 9824 unsigned long addr_field)
ff651cb6 9825{
92d71bc6 9826 int maxphyaddr;
e9ac033e
EK
9827 u64 count, addr;
9828
9829 if (vmcs12_read_any(vcpu, count_field, &count) ||
9830 vmcs12_read_any(vcpu, addr_field, &addr)) {
9831 WARN_ON(1);
9832 return -EINVAL;
9833 }
9834 if (count == 0)
9835 return 0;
92d71bc6 9836 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK
9837 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9838 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
bbe41b95 9839 pr_debug_ratelimited(
e9ac033e
EK
9840 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9841 addr_field, maxphyaddr, count, addr);
9842 return -EINVAL;
9843 }
9844 return 0;
9845}
9846
9847static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9848 struct vmcs12 *vmcs12)
9849{
e9ac033e
EK
9850 if (vmcs12->vm_exit_msr_load_count == 0 &&
9851 vmcs12->vm_exit_msr_store_count == 0 &&
9852 vmcs12->vm_entry_msr_load_count == 0)
9853 return 0; /* Fast path */
e9ac033e 9854 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9855 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9856 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9857 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9858 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9859 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK
9860 return -EINVAL;
9861 return 0;
9862}
9863
c5f983f6
BD
9864static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
9865 struct vmcs12 *vmcs12)
9866{
9867 u64 address = vmcs12->pml_address;
9868 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9869
9870 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
9871 if (!nested_cpu_has_ept(vmcs12) ||
9872 !IS_ALIGNED(address, 4096) ||
9873 address >> maxphyaddr)
9874 return -EINVAL;
9875 }
9876
9877 return 0;
9878}
9879
e9ac033e
EK
9880static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9881 struct vmx_msr_entry *e)
9882{
9883 /* x2APIC MSR accesses are not allowed */
8a9781f7 9884 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK
9885 return -EINVAL;
9886 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9887 e->index == MSR_IA32_UCODE_REV)
9888 return -EINVAL;
9889 if (e->reserved != 0)
ff651cb6
WV
9890 return -EINVAL;
9891 return 0;
9892}
9893
e9ac033e
EK
9894static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9895 struct vmx_msr_entry *e)
ff651cb6
WV
9896{
9897 if (e->index == MSR_FS_BASE ||
9898 e->index == MSR_GS_BASE ||
e9ac033e
EK
9899 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9900 nested_vmx_msr_check_common(vcpu, e))
9901 return -EINVAL;
9902 return 0;
9903}
9904
9905static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9906 struct vmx_msr_entry *e)
9907{
9908 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9909 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV
9910 return -EINVAL;
9911 return 0;
9912}
9913
9914/*
9915 * Load guest's/host's msr at nested entry/exit.
9916 * return 0 for success, entry index for failure.
9917 */
9918static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9919{
9920 u32 i;
9921 struct vmx_msr_entry e;
9922 struct msr_data msr;
9923
9924 msr.host_initiated = false;
9925 for (i = 0; i < count; i++) {
54bf36aa
PB
9926 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9927 &e, sizeof(e))) {
bbe41b95 9928 pr_debug_ratelimited(
e9ac033e
EK
9929 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9930 __func__, i, gpa + i * sizeof(e));
ff651cb6 9931 goto fail;
e9ac033e
EK
9932 }
9933 if (nested_vmx_load_msr_check(vcpu, &e)) {
bbe41b95 9934 pr_debug_ratelimited(
e9ac033e
EK
9935 "%s check failed (%u, 0x%x, 0x%x)\n",
9936 __func__, i, e.index, e.reserved);
9937 goto fail;
9938 }
ff651cb6
WV
9939 msr.index = e.index;
9940 msr.data = e.value;
e9ac033e 9941 if (kvm_set_msr(vcpu, &msr)) {
bbe41b95 9942 pr_debug_ratelimited(
e9ac033e
EK
9943 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9944 __func__, i, e.index, e.value);
ff651cb6 9945 goto fail;
e9ac033e 9946 }
ff651cb6
WV
9947 }
9948 return 0;
9949fail:
9950 return i + 1;
9951}
9952
9953static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9954{
9955 u32 i;
9956 struct vmx_msr_entry e;
9957
9958 for (i = 0; i < count; i++) {
609e36d3 9959 struct msr_data msr_info;
54bf36aa
PB
9960 if (kvm_vcpu_read_guest(vcpu,
9961 gpa + i * sizeof(e),
9962 &e, 2 * sizeof(u32))) {
bbe41b95 9963 pr_debug_ratelimited(
e9ac033e
EK
9964 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9965 __func__, i, gpa + i * sizeof(e));
ff651cb6 9966 return -EINVAL;
e9ac033e
EK
9967 }
9968 if (nested_vmx_store_msr_check(vcpu, &e)) {
bbe41b95 9969 pr_debug_ratelimited(
e9ac033e
EK
9970 "%s check failed (%u, 0x%x, 0x%x)\n",
9971 __func__, i, e.index, e.reserved);
ff651cb6 9972 return -EINVAL;
e9ac033e 9973 }
609e36d3
PB
9974 msr_info.host_initiated = false;
9975 msr_info.index = e.index;
9976 if (kvm_get_msr(vcpu, &msr_info)) {
bbe41b95 9977 pr_debug_ratelimited(
e9ac033e
EK
9978 "%s cannot read MSR (%u, 0x%x)\n",
9979 __func__, i, e.index);
9980 return -EINVAL;
9981 }
54bf36aa
PB
9982 if (kvm_vcpu_write_guest(vcpu,
9983 gpa + i * sizeof(e) +
9984 offsetof(struct vmx_msr_entry, value),
9985 &msr_info.data, sizeof(msr_info.data))) {
bbe41b95 9986 pr_debug_ratelimited(
e9ac033e 9987 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9988 __func__, i, e.index, msr_info.data);
e9ac033e
EK
9989 return -EINVAL;
9990 }
ff651cb6
WV
9991 }
9992 return 0;
9993}
9994
1dc35dac
LP
9995static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9996{
9997 unsigned long invalid_mask;
9998
9999 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10000 return (val & invalid_mask) == 0;
10001}
10002
9ed38ffa
LP
10003/*
10004 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10005 * emulating VM entry into a guest with EPT enabled.
10006 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10007 * is assigned to entry_failure_code on failure.
10008 */
10009static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
ca0bde28 10010 u32 *entry_failure_code)
9ed38ffa 10011{
9ed38ffa 10012 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
1dc35dac 10013 if (!nested_cr3_valid(vcpu, cr3)) {
9ed38ffa
LP
10014 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10015 return 1;
10016 }
10017
10018 /*
10019 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10020 * must not be dereferenced.
10021 */
10022 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10023 !nested_ept) {
10024 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10025 *entry_failure_code = ENTRY_FAIL_PDPTE;
10026 return 1;
10027 }
10028 }
10029
10030 vcpu->arch.cr3 = cr3;
10031 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10032 }
10033
10034 kvm_mmu_reset_context(vcpu);
10035 return 0;
10036}
10037
fe3ef05c
NHE
10038/*
10039 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10040 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 10041 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE
10042 * guest in a way that will both be appropriate to L1's requests, and our
10043 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10044 * function also has additional necessary side-effects, like setting various
10045 * vcpu->arch fields.
ee146c1c
LP
10046 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10047 * is assigned to entry_failure_code on failure.
fe3ef05c 10048 */
ee146c1c 10049static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
ca0bde28 10050 bool from_vmentry, u32 *entry_failure_code)
fe3ef05c
NHE
10051{
10052 struct vcpu_vmx *vmx = to_vmx(vcpu);
03efce6f 10053 u32 exec_control, vmcs12_exec_ctrl;
fe3ef05c
NHE
10054
10055 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10056 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10057 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10058 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10059 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10060 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10061 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10062 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10063 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10064 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10065 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10066 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10067 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10068 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10069 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10070 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10071 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10072 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10073 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10074 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10075 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10076 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10077 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10078 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10079 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10080 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10081 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10082 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10083 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10084 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10085 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10086 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10087 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10088 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10089 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10090 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10091
cf8b84f4
JM
10092 if (from_vmentry &&
10093 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
2996fca0
JK
10094 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10095 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10096 } else {
10097 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10098 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10099 }
cf8b84f4
JM
10100 if (from_vmentry) {
10101 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10102 vmcs12->vm_entry_intr_info_field);
10103 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10104 vmcs12->vm_entry_exception_error_code);
10105 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10106 vmcs12->vm_entry_instruction_len);
10107 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10108 vmcs12->guest_interruptibility_info);
2d6144e3
WL
10109 vmx->loaded_vmcs->nmi_known_unmasked =
10110 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
cf8b84f4
JM
10111 } else {
10112 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10113 }
fe3ef05c 10114 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 10115 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE
10116 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10117 vmcs12->guest_pending_dbg_exceptions);
10118 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10119 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10120
81dc01f7
WL
10121 if (nested_cpu_has_xsaves(vmcs12))
10122 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE
10123 vmcs_write64(VMCS_LINK_POINTER, -1ull);
10124
f4124500 10125 exec_control = vmcs12->pin_based_vm_exec_control;
9314006d
PB
10126
10127 /* Preemption timer setting is only taken from vmcs01. */
705699a1 10128 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9314006d
PB
10129 exec_control |= vmcs_config.pin_based_exec_ctrl;
10130 if (vmx->hv_deadline_tsc == -1)
10131 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
705699a1 10132
9314006d 10133 /* Posted interrupts setting is only taken from vmcs12. */
705699a1 10134 if (nested_cpu_has_posted_intr(vmcs12)) {
705699a1
WV
10135 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10136 vmx->nested.pi_pending = false;
06a5524f 10137 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
6beb7bd5 10138 } else {
705699a1 10139 exec_control &= ~PIN_BASED_POSTED_INTR;
6beb7bd5 10140 }
705699a1 10141
f4124500 10142 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 10143
f4124500
JK
10144 vmx->nested.preemption_timer_expired = false;
10145 if (nested_cpu_has_preemption_timer(vmcs12))
10146 vmx_start_preemption_timer(vcpu);
0238ea91 10147
fe3ef05c
NHE
10148 /*
10149 * Whether page-faults are trapped is determined by a combination of
10150 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10151 * If enable_ept, L0 doesn't care about page faults and we should
10152 * set all of these to L1's desires. However, if !enable_ept, L0 does
10153 * care about (at least some) page faults, and because it is not easy
10154 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10155 * to exit on each and every L2 page fault. This is done by setting
10156 * MASK=MATCH=0 and (see below) EB.PF=1.
10157 * Note that below we don't need special code to set EB.PF beyond the
10158 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10159 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10160 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
fe3ef05c
NHE
10161 */
10162 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10163 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10164 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10165 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10166
10167 if (cpu_has_secondary_exec_ctrls()) {
f4124500 10168 exec_control = vmx_secondary_exec_control(vmx);
e2821620 10169
fe3ef05c 10170 /* Take the following fields only from vmcs12 */
696dfd95 10171 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 10172 SECONDARY_EXEC_RDTSCP |
696dfd95 10173 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
dfa169bb 10174 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c 10175 if (nested_cpu_has(vmcs12,
03efce6f
BD
10176 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10177 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10178 ~SECONDARY_EXEC_ENABLE_PML;
10179 exec_control |= vmcs12_exec_ctrl;
10180 }
fe3ef05c 10181
608406e2
WV
10182 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10183 vmcs_write64(EOI_EXIT_BITMAP0,
10184 vmcs12->eoi_exit_bitmap0);
10185 vmcs_write64(EOI_EXIT_BITMAP1,
10186 vmcs12->eoi_exit_bitmap1);
10187 vmcs_write64(EOI_EXIT_BITMAP2,
10188 vmcs12->eoi_exit_bitmap2);
10189 vmcs_write64(EOI_EXIT_BITMAP3,
10190 vmcs12->eoi_exit_bitmap3);
10191 vmcs_write16(GUEST_INTR_STATUS,
10192 vmcs12->guest_intr_status);
10193 }
10194
6beb7bd5
JM
10195 /*
10196 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10197 * nested_get_vmcs12_pages will either fix it up or
10198 * remove the VM execution control.
10199 */
10200 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10201 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10202
fe3ef05c
NHE
10203 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10204 }
10205
10206
10207 /*
10208 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10209 * Some constant fields are set here by vmx_set_constant_host_state().
10210 * Other fields are different per CPU, and will be set later when
10211 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10212 */
a547c6db 10213 vmx_set_constant_host_state(vmx);
fe3ef05c 10214
83bafef1
JM
10215 /*
10216 * Set the MSR load/store lists to match L0's settings.
10217 */
10218 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10219 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10220 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10221 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10222 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10223
fe3ef05c
NHE
10224 /*
10225 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10226 * entry, but only if the current (host) sp changed from the value
10227 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10228 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10229 * here we just force the write to happen on entry.
10230 */
10231 vmx->host_rsp = 0;
10232
10233 exec_control = vmx_exec_control(vmx); /* L0's desires */
10234 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10235 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10236 exec_control &= ~CPU_BASED_TPR_SHADOW;
10237 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d 10238
6beb7bd5
JM
10239 /*
10240 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10241 * nested_get_vmcs12_pages can't fix it up, the illegal value
10242 * will result in a VM entry failure.
10243 */
a7c0b07d 10244 if (exec_control & CPU_BASED_TPR_SHADOW) {
6beb7bd5 10245 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
a7c0b07d
WL
10246 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10247 }
10248
fe3ef05c 10249 /*
3af18d9c 10250 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE
10251 * Rather, exit every time.
10252 */
fe3ef05c
NHE
10253 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10254 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10255
10256 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10257
10258 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10259 * bitwise-or of what L1 wants to trap for L2, and what we want to
10260 * trap. Note that CR0.TS also needs updating - we do this later.
10261 */
10262 update_exception_bitmap(vcpu);
10263 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10264 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10265
8049d651
NHE
10266 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10267 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10268 * bits are further modified by vmx_set_efer() below.
10269 */
f4124500 10270 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE
10271
10272 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10273 * emulated by vmx_set_efer(), below.
10274 */
2961e876 10275 vm_entry_controls_init(vmx,
8049d651
NHE
10276 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10277 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE
10278 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10279
cf8b84f4
JM
10280 if (from_vmentry &&
10281 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
fe3ef05c 10282 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02 10283 vcpu->arch.pat = vmcs12->guest_ia32_pat;
cf8b84f4 10284 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 10285 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
cf8b84f4 10286 }
fe3ef05c
NHE
10287
10288 set_cr4_guest_host_mask(vmx);
10289
cf8b84f4
JM
10290 if (from_vmentry &&
10291 vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
36be0b9d
PB
10292 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10293
27fc51b2
NHE
10294 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10295 vmcs_write64(TSC_OFFSET,
ea26e4ec 10296 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
27fc51b2 10297 else
ea26e4ec 10298 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
c95ba92a
PF
10299 if (kvm_has_tsc_control)
10300 decache_tsc_multiplier(vmx);
fe3ef05c
NHE
10301
10302 if (enable_vpid) {
10303 /*
5c614b35
WL
10304 * There is no direct mapping between vpid02 and vpid12, the
10305 * vpid02 is per-vCPU for L0 and reused while the value of
10306 * vpid12 is changed w/ one invvpid during nested vmentry.
10307 * The vpid12 is allocated by L1 for L2, so it will not
10308 * influence global bitmap(for vpid01 and vpid02 allocation)
10309 * even if spawn a lot of nested vCPUs.
fe3ef05c 10310 */
5c614b35
WL
10311 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10312 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10313 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10314 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10315 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10316 }
10317 } else {
10318 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10319 vmx_flush_tlb(vcpu);
10320 }
10321
fe3ef05c
NHE
10322 }
10323
1fb883bb
LP
10324 if (enable_pml) {
10325 /*
10326 * Conceptually we want to copy the PML address and index from
10327 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10328 * since we always flush the log on each vmexit, this happens
10329 * to be equivalent to simply resetting the fields in vmcs02.
10330 */
10331 ASSERT(vmx->pml_pg);
10332 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10333 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10334 }
10335
155a97a3 10336 if (nested_cpu_has_ept(vmcs12)) {
ae1e2d10
PB
10337 if (nested_ept_init_mmu_context(vcpu)) {
10338 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10339 return 1;
10340 }
fb6c8198
JM
10341 } else if (nested_cpu_has2(vmcs12,
10342 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10343 vmx_flush_tlb_ept_only(vcpu);
155a97a3
NHE
10344 }
10345
fe3ef05c 10346 /*
bd7e5b08
PB
10347 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10348 * bits which we consider mandatory enabled.
fe3ef05c
NHE
10349 * The CR0_READ_SHADOW is what L2 should have expected to read given
10350 * the specifications by L1; It's not enough to take
10351 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10352 * have more bits than L1 expected.
10353 */
10354 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10355 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10356
10357 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10358 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10359
cf8b84f4
JM
10360 if (from_vmentry &&
10361 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
5a6a9748
DM
10362 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10363 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10364 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10365 else
10366 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10367 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10368 vmx_set_efer(vcpu, vcpu->arch.efer);
10369
9ed38ffa 10370 /* Shadow page tables on either EPT or shadow page tables. */
7ad658b6 10371 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
9ed38ffa
LP
10372 entry_failure_code))
10373 return 1;
7ca29de2 10374
feaf0c7d
GN
10375 if (!enable_ept)
10376 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10377
3633cfc3
NHE
10378 /*
10379 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10380 */
10381 if (enable_ept) {
10382 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10383 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10384 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10385 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10386 }
10387
fe3ef05c
NHE
10388 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10389 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
ee146c1c 10390 return 0;
fe3ef05c
NHE
10391}
10392
ca0bde28 10393static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
cd232ad0 10394{
cd232ad0 10395 struct vcpu_vmx *vmx = to_vmx(vcpu);
7c177938 10396
6dfacadd 10397 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
ca0bde28
JM
10398 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10399 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
26539bd0 10400
56a20510
JM
10401 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10402 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10403
ca0bde28
JM
10404 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10405 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
7c177938 10406
ca0bde28
JM
10407 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10408 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
f2b93280 10409
ca0bde28
JM
10410 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10411 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
e9ac033e 10412
c5f983f6
BD
10413 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10414 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10415
7c177938 10416 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
0115f9cb 10417 vmx->nested.nested_vmx_procbased_ctls_low,
b9c237bb 10418 vmx->nested.nested_vmx_procbased_ctls_high) ||
2e5b0bd9
JM
10419 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10420 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10421 vmx->nested.nested_vmx_secondary_ctls_low,
10422 vmx->nested.nested_vmx_secondary_ctls_high)) ||
7c177938 10423 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV
10424 vmx->nested.nested_vmx_pinbased_ctls_low,
10425 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 10426 !vmx_control_verify(vmcs12->vm_exit_controls,
0115f9cb 10427 vmx->nested.nested_vmx_exit_ctls_low,
b9c237bb 10428 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 10429 !vmx_control_verify(vmcs12->vm_entry_controls,
0115f9cb 10430 vmx->nested.nested_vmx_entry_ctls_low,
b9c237bb 10431 vmx->nested.nested_vmx_entry_ctls_high))
ca0bde28 10432 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
7c177938 10433
c7c2c709
JM
10434 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10435 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10436
3899152c 10437 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
1dc35dac 10438 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
ca0bde28
JM
10439 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10440 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10441
10442 return 0;
10443}
10444
10445static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10446 u32 *exit_qual)
10447{
10448 bool ia32e;
10449
10450 *exit_qual = ENTRY_FAIL_DEFAULT;
7c177938 10451
3899152c 10452 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
ca0bde28 10453 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
b428018a 10454 return 1;
ca0bde28
JM
10455
10456 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10457 vmcs12->vmcs_link_pointer != -1ull) {
10458 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
b428018a 10459 return 1;
7c177938
NHE
10460 }
10461
384bb783 10462 /*
cb0c8cda 10463 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK
10464 * are performed on the field for the IA32_EFER MSR:
10465 * - Bits reserved in the IA32_EFER MSR must be 0.
10466 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10467 * the IA-32e mode guest VM-exit control. It must also be identical
10468 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10469 * CR0.PG) is 1.
10470 */
ca0bde28
JM
10471 if (to_vmx(vcpu)->nested.nested_run_pending &&
10472 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
384bb783
JK
10473 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10474 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10475 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10476 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
ca0bde28 10477 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
b428018a 10478 return 1;
384bb783
JK
10479 }
10480
10481 /*
10482 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10483 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10484 * the values of the LMA and LME bits in the field must each be that of
10485 * the host address-space size VM-exit control.
10486 */
10487 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10488 ia32e = (vmcs12->vm_exit_controls &
10489 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10490 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10491 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
ca0bde28 10492 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
b428018a 10493 return 1;
ca0bde28
JM
10494 }
10495
10496 return 0;
10497}
10498
858e25c0
JM
10499static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10500{
10501 struct vcpu_vmx *vmx = to_vmx(vcpu);
10502 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10503 struct loaded_vmcs *vmcs02;
858e25c0
JM
10504 u32 msr_entry_idx;
10505 u32 exit_qual;
10506
10507 vmcs02 = nested_get_current_vmcs02(vmx);
10508 if (!vmcs02)
10509 return -ENOMEM;
10510
10511 enter_guest_mode(vcpu);
10512
10513 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10514 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10515
1279a6b1 10516 vmx_switch_vmcs(vcpu, vmcs02);
858e25c0
JM
10517 vmx_segment_cache_clear(vmx);
10518
10519 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10520 leave_guest_mode(vcpu);
1279a6b1 10521 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
858e25c0
JM
10522 nested_vmx_entry_failure(vcpu, vmcs12,
10523 EXIT_REASON_INVALID_STATE, exit_qual);
10524 return 1;
10525 }
10526
10527 nested_get_vmcs12_pages(vcpu, vmcs12);
10528
10529 msr_entry_idx = nested_vmx_load_msr(vcpu,
10530 vmcs12->vm_entry_msr_load_addr,
10531 vmcs12->vm_entry_msr_load_count);
10532 if (msr_entry_idx) {
10533 leave_guest_mode(vcpu);
1279a6b1 10534 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
858e25c0
JM
10535 nested_vmx_entry_failure(vcpu, vmcs12,
10536 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10537 return 1;
10538 }
10539
858e25c0
JM
10540 /*
10541 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10542 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10543 * returned as far as L1 is concerned. It will only return (and set
10544 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10545 */
10546 return 0;
10547}
10548
ca0bde28
JM
10549/*
10550 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10551 * for running an L2 nested guest.
10552 */
10553static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10554{
10555 struct vmcs12 *vmcs12;
10556 struct vcpu_vmx *vmx = to_vmx(vcpu);
b3f1dfb6 10557 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
ca0bde28
JM
10558 u32 exit_qual;
10559 int ret;
10560
10561 if (!nested_vmx_check_permission(vcpu))
10562 return 1;
10563
10564 if (!nested_vmx_check_vmcs12(vcpu))
10565 goto out;
10566
10567 vmcs12 = get_vmcs12(vcpu);
10568
10569 if (enable_shadow_vmcs)
10570 copy_shadow_to_vmcs12(vmx);
10571
10572 /*
10573 * The nested entry process starts with enforcing various prerequisites
10574 * on vmcs12 as required by the Intel SDM, and act appropriately when
10575 * they fail: As the SDM explains, some conditions should cause the
10576 * instruction to fail, while others will cause the instruction to seem
10577 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10578 * To speed up the normal (success) code path, we should avoid checking
10579 * for misconfigurations which will anyway be caught by the processor
10580 * when using the merged vmcs02.
10581 */
b3f1dfb6
JM
10582 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
10583 nested_vmx_failValid(vcpu,
10584 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
10585 goto out;
10586 }
10587
ca0bde28
JM
10588 if (vmcs12->launch_state == launch) {
10589 nested_vmx_failValid(vcpu,
10590 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10591 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10592 goto out;
10593 }
10594
10595 ret = check_vmentry_prereqs(vcpu, vmcs12);
10596 if (ret) {
10597 nested_vmx_failValid(vcpu, ret);
10598 goto out;
10599 }
10600
10601 /*
10602 * After this point, the trap flag no longer triggers a singlestep trap
10603 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10604 * This is not 100% correct; for performance reasons, we delegate most
10605 * of the checks on host state to the processor. If those fail,
10606 * the singlestep trap is missed.
10607 */
10608 skip_emulated_instruction(vcpu);
10609
10610 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10611 if (ret) {
10612 nested_vmx_entry_failure(vcpu, vmcs12,
10613 EXIT_REASON_INVALID_STATE, exit_qual);
10614 return 1;
384bb783
JK
10615 }
10616
7c177938
NHE
10617 /*
10618 * We're finally done with prerequisite checking, and can start with
10619 * the nested entry.
10620 */
10621
858e25c0
JM
10622 ret = enter_vmx_non_root_mode(vcpu, true);
10623 if (ret)
10624 return ret;
ff651cb6 10625
6dfacadd 10626 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 10627 return kvm_vcpu_halt(vcpu);
6dfacadd 10628
7af40ad3
JK
10629 vmx->nested.nested_run_pending = 1;
10630
cd232ad0 10631 return 1;
eb277562
KH
10632
10633out:
6affcbed 10634 return kvm_skip_emulated_instruction(vcpu);
cd232ad0
NHE
10635}
10636
4704d0be
NHE
10637/*
10638 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10639 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10640 * This function returns the new value we should put in vmcs12.guest_cr0.
10641 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10642 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10643 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10644 * didn't trap the bit, because if L1 did, so would L0).
10645 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10646 * been modified by L2, and L1 knows it. So just leave the old value of
10647 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10648 * isn't relevant, because if L0 traps this bit it can set it to anything.
10649 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10650 * changed these bits, and therefore they need to be updated, but L0
10651 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10652 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10653 */
10654static inline unsigned long
10655vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10656{
10657 return
10658 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10659 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10660 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10661 vcpu->arch.cr0_guest_owned_bits));
10662}
10663
10664static inline unsigned long
10665vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10666{
10667 return
10668 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10669 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10670 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10671 vcpu->arch.cr4_guest_owned_bits));
10672}
10673
5f3d5799
JK
10674static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10675 struct vmcs12 *vmcs12)
10676{
10677 u32 idt_vectoring;
10678 unsigned int nr;
10679
851eb667 10680 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK
10681 nr = vcpu->arch.exception.nr;
10682 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10683
10684 if (kvm_exception_is_soft(nr)) {
10685 vmcs12->vm_exit_instruction_len =
10686 vcpu->arch.event_exit_inst_len;
10687 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10688 } else
10689 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10690
10691 if (vcpu->arch.exception.has_error_code) {
10692 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10693 vmcs12->idt_vectoring_error_code =
10694 vcpu->arch.exception.error_code;
10695 }
10696
10697 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 10698 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK
10699 vmcs12->idt_vectoring_info_field =
10700 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10701 } else if (vcpu->arch.interrupt.pending) {
10702 nr = vcpu->arch.interrupt.nr;
10703 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10704
10705 if (vcpu->arch.interrupt.soft) {
10706 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10707 vmcs12->vm_entry_instruction_len =
10708 vcpu->arch.event_exit_inst_len;
10709 } else
10710 idt_vectoring |= INTR_TYPE_EXT_INTR;
10711
10712 vmcs12->idt_vectoring_info_field = idt_vectoring;
10713 }
10714}
10715
b6b8a145
JK
10716static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10717{
10718 struct vcpu_vmx *vmx = to_vmx(vcpu);
10719
acc9ab60
WL
10720 if (vcpu->arch.exception.pending ||
10721 vcpu->arch.nmi_injected ||
10722 vcpu->arch.interrupt.pending)
10723 return -EBUSY;
10724
f4124500
JK
10725 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10726 vmx->nested.preemption_timer_expired) {
10727 if (vmx->nested.nested_run_pending)
10728 return -EBUSY;
10729 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10730 return 0;
10731 }
10732
b6b8a145 10733 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
acc9ab60 10734 if (vmx->nested.nested_run_pending)
b6b8a145
JK
10735 return -EBUSY;
10736 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10737 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10738 INTR_INFO_VALID_MASK, 0);
10739 /*
10740 * The NMI-triggered VM exit counts as injection:
10741 * clear this one and block further NMIs.
10742 */
10743 vcpu->arch.nmi_pending = 0;
10744 vmx_set_nmi_mask(vcpu, true);
10745 return 0;
10746 }
10747
10748 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10749 nested_exit_on_intr(vcpu)) {
10750 if (vmx->nested.nested_run_pending)
10751 return -EBUSY;
10752 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 10753 return 0;
b6b8a145
JK
10754 }
10755
6342c50a
DH
10756 vmx_complete_nested_posted_interrupt(vcpu);
10757 return 0;
b6b8a145
JK
10758}
10759
f4124500
JK
10760static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10761{
10762 ktime_t remaining =
10763 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10764 u64 value;
10765
10766 if (ktime_to_ns(remaining) <= 0)
10767 return 0;
10768
10769 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10770 do_div(value, 1000000);
10771 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10772}
10773
4704d0be 10774/*
cf8b84f4
JM
10775 * Update the guest state fields of vmcs12 to reflect changes that
10776 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10777 * VM-entry controls is also updated, since this is really a guest
10778 * state bit.)
4704d0be 10779 */
cf8b84f4 10780static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be 10781{
4704d0be
NHE
10782 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10783 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10784
4704d0be
NHE
10785 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10786 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10787 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10788
10789 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10790 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10791 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10792 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10793 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10794 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10795 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10796 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10797 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10798 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10799 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10800 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10801 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10802 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10803 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10804 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10805 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10806 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10807 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10808 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10809 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10810 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10811 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10812 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10813 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10814 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10815 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10816 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10817 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10818 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10819 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10820 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10821 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10822 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10823 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10824 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10825
4704d0be
NHE
10826 vmcs12->guest_interruptibility_info =
10827 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10828 vmcs12->guest_pending_dbg_exceptions =
10829 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK
10830 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10831 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10832 else
10833 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 10834
f4124500
JK
10835 if (nested_cpu_has_preemption_timer(vmcs12)) {
10836 if (vmcs12->vm_exit_controls &
10837 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10838 vmcs12->vmx_preemption_timer_value =
10839 vmx_get_preemption_timer_value(vcpu);
10840 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10841 }
7854cbca 10842
3633cfc3
NHE
10843 /*
10844 * In some cases (usually, nested EPT), L2 is allowed to change its
10845 * own CR3 without exiting. If it has changed it, we must keep it.
10846 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10847 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10848 *
10849 * Additionally, restore L2's PDPTR to vmcs12.
10850 */
10851 if (enable_ept) {
f3531054 10852 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
3633cfc3
NHE
10853 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10854 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10855 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10856 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10857 }
10858
d281e13b 10859 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
119a9c01 10860
608406e2
WV
10861 if (nested_cpu_has_vid(vmcs12))
10862 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10863
c18911a2
JK
10864 vmcs12->vm_entry_controls =
10865 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 10866 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 10867
2996fca0
JK
10868 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10869 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10870 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10871 }
10872
4704d0be
NHE
10873 /* TODO: These cannot have changed unless we have MSR bitmaps and
10874 * the relevant bit asks not to trap the change */
b8c07d55 10875 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 10876 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK
10877 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10878 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE
10879 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10880 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10881 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
a87036ad 10882 if (kvm_mpx_supported())
36be0b9d 10883 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
cf8b84f4
JM
10884}
10885
10886/*
10887 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10888 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10889 * and this function updates it to reflect the changes to the guest state while
10890 * L2 was running (and perhaps made some exits which were handled directly by L0
10891 * without going back to L1), and to reflect the exit reason.
10892 * Note that we do not have to copy here all VMCS fields, just those that
10893 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10894 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10895 * which already writes to vmcs12 directly.
10896 */
10897static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10898 u32 exit_reason, u32 exit_intr_info,
10899 unsigned long exit_qualification)
10900{
10901 /* update guest state fields: */
10902 sync_vmcs12(vcpu, vmcs12);
4704d0be
NHE
10903
10904 /* update exit information fields: */
10905
533558bc
JK
10906 vmcs12->vm_exit_reason = exit_reason;
10907 vmcs12->exit_qualification = exit_qualification;
533558bc 10908 vmcs12->vm_exit_intr_info = exit_intr_info;
7313c698 10909
5f3d5799 10910 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE
10911 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10912 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10913
5f3d5799 10914 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7cdc2d62
JM
10915 vmcs12->launch_state = 1;
10916
5f3d5799
JK
10917 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10918 * instead of reading the real value. */
4704d0be 10919 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK
10920
10921 /*
10922 * Transfer the event that L0 or L1 may wanted to inject into
10923 * L2 to IDT_VECTORING_INFO_FIELD.
10924 */
10925 vmcs12_save_pending_event(vcpu, vmcs12);
10926 }
10927
10928 /*
10929 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10930 * preserved above and would only end up incorrectly in L1.
10931 */
10932 vcpu->arch.nmi_injected = false;
10933 kvm_clear_exception_queue(vcpu);
10934 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE
10935}
10936
10937/*
10938 * A part of what we need to when the nested L2 guest exits and we want to
10939 * run its L1 parent, is to reset L1's guest state to the host state specified
10940 * in vmcs12.
10941 * This function is to be called not only on normal nested exit, but also on
10942 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10943 * Failures During or After Loading Guest State").
10944 * This function should be called when the active VMCS is L1's (vmcs01).
10945 */
733568f9
JK
10946static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10947 struct vmcs12 *vmcs12)
4704d0be 10948{
21feb4eb 10949 struct kvm_segment seg;
ca0bde28 10950 u32 entry_failure_code;
21feb4eb 10951
4704d0be
NHE
10952 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10953 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10954 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE
10955 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10956 else
10957 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10958 vmx_set_efer(vcpu, vcpu->arch.efer);
10959
10960 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10961 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10962 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE
10963 /*
10964 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
bd7e5b08
PB
10965 * actually changed, because vmx_set_cr0 refers to efer set above.
10966 *
10967 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10968 * (KVM doesn't change it);
4704d0be 10969 */
bd7e5b08 10970 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
9e3e4dbf 10971 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be 10972
bd7e5b08 10973 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
4704d0be
NHE
10974 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10975 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10976
29bf08f1 10977 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10978
1dc35dac
LP
10979 /*
10980 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10981 * couldn't have changed.
10982 */
10983 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10984 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
4704d0be 10985
feaf0c7d
GN
10986 if (!enable_ept)
10987 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10988
4704d0be
NHE
10989 if (enable_vpid) {
10990 /*
10991 * Trivially support vpid by letting L2s share their parent
10992 * L1's vpid. TODO: move to a more elaborate solution, giving
10993 * each L2 its own vpid and exposing the vpid feature to L1.
10994 */
10995 vmx_flush_tlb(vcpu);
10996 }
06a5524f
WV
10997 /* Restore posted intr vector. */
10998 if (nested_cpu_has_posted_intr(vmcs12))
10999 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4704d0be
NHE
11000
11001 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11002 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11003 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11004 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11005 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 11006
36be0b9d
PB
11007 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11008 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11009 vmcs_write64(GUEST_BNDCFGS, 0);
11010
44811c02 11011 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 11012 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK
11013 vcpu->arch.pat = vmcs12->host_ia32_pat;
11014 }
4704d0be
NHE
11015 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11016 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11017 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 11018
21feb4eb
ACL
11019 /* Set L1 segment info according to Intel SDM
11020 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11021 seg = (struct kvm_segment) {
11022 .base = 0,
11023 .limit = 0xFFFFFFFF,
11024 .selector = vmcs12->host_cs_selector,
11025 .type = 11,
11026 .present = 1,
11027 .s = 1,
11028 .g = 1
11029 };
11030 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11031 seg.l = 1;
11032 else
11033 seg.db = 1;
11034 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11035 seg = (struct kvm_segment) {
11036 .base = 0,
11037 .limit = 0xFFFFFFFF,
11038 .type = 3,
11039 .present = 1,
11040 .s = 1,
11041 .db = 1,
11042 .g = 1
11043 };
11044 seg.selector = vmcs12->host_ds_selector;
11045 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11046 seg.selector = vmcs12->host_es_selector;
11047 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11048 seg.selector = vmcs12->host_ss_selector;
11049 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11050 seg.selector = vmcs12->host_fs_selector;
11051 seg.base = vmcs12->host_fs_base;
11052 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11053 seg.selector = vmcs12->host_gs_selector;
11054 seg.base = vmcs12->host_gs_base;
11055 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11056 seg = (struct kvm_segment) {
205befd9 11057 .base = vmcs12->host_tr_base,
21feb4eb
ACL
11058 .limit = 0x67,
11059 .selector = vmcs12->host_tr_selector,
11060 .type = 11,
11061 .present = 1
11062 };
11063 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11064
503cd0c5
JK
11065 kvm_set_dr(vcpu, 7, 0x400);
11066 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 11067
3af18d9c
WV
11068 if (cpu_has_vmx_msr_bitmap())
11069 vmx_set_msr_bitmap(vcpu);
11070
ff651cb6
WV
11071 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11072 vmcs12->vm_exit_msr_load_count))
11073 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE
11074}
11075
11076/*
11077 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11078 * and modify vmcs12 to make it see what it would expect to see there if
11079 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11080 */
533558bc
JK
11081static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11082 u32 exit_intr_info,
11083 unsigned long exit_qualification)
4704d0be
NHE
11084{
11085 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 11086 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
cf3215d9 11087 u32 vm_inst_error = 0;
4704d0be 11088
5f3d5799
JK
11089 /* trying to cancel vmlaunch/vmresume is a bug */
11090 WARN_ON_ONCE(vmx->nested.nested_run_pending);
11091
4704d0be 11092 leave_guest_mode(vcpu);
533558bc
JK
11093 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11094 exit_qualification);
4704d0be 11095
ff651cb6
WV
11096 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11097 vmcs12->vm_exit_msr_store_count))
11098 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11099
cf3215d9
JM
11100 if (unlikely(vmx->fail))
11101 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11102
1279a6b1 11103 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
f3380ca5 11104
77b0f5d6
BD
11105 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11106 && nested_exit_intr_ack_set(vcpu)) {
11107 int irq = kvm_cpu_get_interrupt(vcpu);
11108 WARN_ON(irq < 0);
11109 vmcs12->vm_exit_intr_info = irq |
11110 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11111 }
11112
542060ea
JK
11113 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11114 vmcs12->exit_qualification,
11115 vmcs12->idt_vectoring_info_field,
11116 vmcs12->vm_exit_intr_info,
11117 vmcs12->vm_exit_intr_error_code,
11118 KVM_ISA_VMX);
4704d0be 11119
8391ce44
PB
11120 vm_entry_controls_reset_shadow(vmx);
11121 vm_exit_controls_reset_shadow(vmx);
36c3cc42
JK
11122 vmx_segment_cache_clear(vmx);
11123
4704d0be
NHE
11124 /* if no vmcs02 cache requested, remove the one we used */
11125 if (VMCS02_POOL_SIZE == 0)
11126 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11127
11128 load_vmcs12_host_state(vcpu, vmcs12);
11129
9314006d 11130 /* Update any VMCS fields that might have changed while L2 ran */
83bafef1
JM
11131 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11132 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
ea26e4ec 11133 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
9314006d
PB
11134 if (vmx->hv_deadline_tsc == -1)
11135 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11136 PIN_BASED_VMX_PREEMPTION_TIMER);
11137 else
11138 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11139 PIN_BASED_VMX_PREEMPTION_TIMER);
c95ba92a
PF
11140 if (kvm_has_tsc_control)
11141 decache_tsc_multiplier(vmx);
4704d0be 11142
dccbfcf5
RK
11143 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11144 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11145 vmx_set_virtual_x2apic_mode(vcpu,
11146 vcpu->arch.apic_base & X2APIC_ENABLE);
fb6c8198
JM
11147 } else if (!nested_cpu_has_ept(vmcs12) &&
11148 nested_cpu_has2(vmcs12,
11149 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11150 vmx_flush_tlb_ept_only(vcpu);
dccbfcf5 11151 }
4704d0be
NHE
11152
11153 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11154 vmx->host_rsp = 0;
11155
11156 /* Unpin physical memory we referred to in vmcs02 */
11157 if (vmx->nested.apic_access_page) {
11158 nested_release_page(vmx->nested.apic_access_page);
48d89b92 11159 vmx->nested.apic_access_page = NULL;
4704d0be 11160 }
a7c0b07d
WL
11161 if (vmx->nested.virtual_apic_page) {
11162 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 11163 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 11164 }
705699a1
WV
11165 if (vmx->nested.pi_desc_page) {
11166 kunmap(vmx->nested.pi_desc_page);
11167 nested_release_page(vmx->nested.pi_desc_page);
11168 vmx->nested.pi_desc_page = NULL;
11169 vmx->nested.pi_desc = NULL;
11170 }
4704d0be 11171
38b99173
TC
11172 /*
11173 * We are now running in L2, mmu_notifier will force to reload the
11174 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11175 */
c83b6d15 11176 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
38b99173 11177
4704d0be
NHE
11178 /*
11179 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11180 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11181 * success or failure flag accordingly.
11182 */
11183 if (unlikely(vmx->fail)) {
11184 vmx->fail = 0;
cf3215d9 11185 nested_vmx_failValid(vcpu, vm_inst_error);
4704d0be
NHE
11186 } else
11187 nested_vmx_succeed(vcpu);
012f83cb
AG
11188 if (enable_shadow_vmcs)
11189 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK
11190
11191 /* in case we halted in L2 */
11192 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE
11193}
11194
42124925
JK
11195/*
11196 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11197 */
11198static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11199{
2f707d97
WL
11200 if (is_guest_mode(vcpu)) {
11201 to_vmx(vcpu)->nested.nested_run_pending = 0;
533558bc 11202 nested_vmx_vmexit(vcpu, -1, 0, 0);
2f707d97 11203 }
42124925
JK
11204 free_nested(to_vmx(vcpu));
11205}
11206
7c177938
NHE
11207/*
11208 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11209 * 23.7 "VM-entry failures during or after loading guest state" (this also
11210 * lists the acceptable exit-reason and exit-qualification parameters).
11211 * It should only be called before L2 actually succeeded to run, and when
11212 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11213 */
11214static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11215 struct vmcs12 *vmcs12,
11216 u32 reason, unsigned long qualification)
11217{
11218 load_vmcs12_host_state(vcpu, vmcs12);
11219 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11220 vmcs12->exit_qualification = qualification;
11221 nested_vmx_succeed(vcpu);
012f83cb
AG
11222 if (enable_shadow_vmcs)
11223 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE
11224}
11225
8a76d7f2
JR
11226static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11227 struct x86_instruction_info *info,
11228 enum x86_intercept_stage stage)
11229{
11230 return X86EMUL_CONTINUE;
11231}
11232
64672c95
YJ
11233#ifdef CONFIG_X86_64
11234/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11235static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11236 u64 divisor, u64 *result)
11237{
11238 u64 low = a << shift, high = a >> (64 - shift);
11239
11240 /* To avoid the overflow on divq */
11241 if (high >= divisor)
11242 return 1;
11243
11244 /* Low hold the result, high hold rem which is discarded */
11245 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11246 "rm" (divisor), "0" (low), "1" (high));
11247 *result = low;
11248
11249 return 0;
11250}
11251
11252static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11253{
11254 struct vcpu_vmx *vmx = to_vmx(vcpu);
9175d2e9
PB
11255 u64 tscl = rdtsc();
11256 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11257 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
64672c95
YJ
11258
11259 /* Convert to host delta tsc if tsc scaling is enabled */
11260 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11261 u64_shl_div_u64(delta_tsc,
11262 kvm_tsc_scaling_ratio_frac_bits,
11263 vcpu->arch.tsc_scaling_ratio,
11264 &delta_tsc))
11265 return -ERANGE;
11266
11267 /*
11268 * If the delta tsc can't fit in the 32 bit after the multi shift,
11269 * we can't use the preemption timer.
11270 * It's possible that it fits on later vmentries, but checking
11271 * on every vmentry is costly so we just use an hrtimer.
11272 */
11273 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11274 return -ERANGE;
11275
11276 vmx->hv_deadline_tsc = tscl + delta_tsc;
11277 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11278 PIN_BASED_VMX_PREEMPTION_TIMER);
c8533544
WL
11279
11280 return delta_tsc == 0;
64672c95
YJ
11281}
11282
11283static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11284{
11285 struct vcpu_vmx *vmx = to_vmx(vcpu);
11286 vmx->hv_deadline_tsc = -1;
11287 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11288 PIN_BASED_VMX_PREEMPTION_TIMER);
11289}
11290#endif
11291
48d89b92 11292static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 11293{
b4a2d31d
RK
11294 if (ple_gap)
11295 shrink_ple_window(vcpu);
ae97a3b8
RK
11296}
11297
843e4330
KH
11298static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11299 struct kvm_memory_slot *slot)
11300{
11301 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11302 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11303}
11304
11305static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11306 struct kvm_memory_slot *slot)
11307{
11308 kvm_mmu_slot_set_dirty(kvm, slot);
11309}
11310
11311static void vmx_flush_log_dirty(struct kvm *kvm)
11312{
11313 kvm_flush_pml_buffers(kvm);
11314}
11315
c5f983f6
BD
11316static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11317{
11318 struct vmcs12 *vmcs12;
11319 struct vcpu_vmx *vmx = to_vmx(vcpu);
11320 gpa_t gpa;
11321 struct page *page = NULL;
11322 u64 *pml_address;
11323
11324 if (is_guest_mode(vcpu)) {
11325 WARN_ON_ONCE(vmx->nested.pml_full);
11326
11327 /*
11328 * Check if PML is enabled for the nested guest.
11329 * Whether eptp bit 6 is set is already checked
11330 * as part of A/D emulation.
11331 */
11332 vmcs12 = get_vmcs12(vcpu);
11333 if (!nested_cpu_has_pml(vmcs12))
11334 return 0;
11335
4769886b 11336 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD
11337 vmx->nested.pml_full = true;
11338 return 1;
11339 }
11340
11341 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11342
11343 page = nested_get_page(vcpu, vmcs12->pml_address);
11344 if (!page)
11345 return 0;
11346
11347 pml_address = kmap(page);
11348 pml_address[vmcs12->guest_pml_index--] = gpa;
11349 kunmap(page);
11350 nested_release_page_clean(page);
11351 }
11352
11353 return 0;
11354}
11355
843e4330
KH
11356static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11357 struct kvm_memory_slot *memslot,
11358 gfn_t offset, unsigned long mask)
11359{
11360 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11361}
11362
bf9f6ac8
FW
11363/*
11364 * This routine does the following things for vCPU which is going
11365 * to be blocked if VT-d PI is enabled.
11366 * - Store the vCPU to the wakeup list, so when interrupts happen
11367 * we can find the right vCPU to wake up.
11368 * - Change the Posted-interrupt descriptor as below:
11369 * 'NDST' <-- vcpu->pre_pcpu
11370 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11371 * - If 'ON' is set during this process, which means at least one
11372 * interrupt is posted for this vCPU, we cannot block it, in
11373 * this case, return 1, otherwise, return 0.
11374 *
11375 */
bc22512b 11376static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8
FW
11377{
11378 unsigned long flags;
11379 unsigned int dest;
11380 struct pi_desc old, new;
11381 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11382
11383 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
11384 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11385 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW
11386 return 0;
11387
11388 vcpu->pre_pcpu = vcpu->cpu;
11389 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11390 vcpu->pre_pcpu), flags);
11391 list_add_tail(&vcpu->blocked_vcpu_list,
11392 &per_cpu(blocked_vcpu_on_cpu,
11393 vcpu->pre_pcpu));
11394 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11395 vcpu->pre_pcpu), flags);
11396
11397 do {
11398 old.control = new.control = pi_desc->control;
11399
11400 /*
11401 * We should not block the vCPU if
11402 * an interrupt is posted for it.
11403 */
11404 if (pi_test_on(pi_desc) == 1) {
11405 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11406 vcpu->pre_pcpu), flags);
11407 list_del(&vcpu->blocked_vcpu_list);
11408 spin_unlock_irqrestore(
11409 &per_cpu(blocked_vcpu_on_cpu_lock,
11410 vcpu->pre_pcpu), flags);
11411 vcpu->pre_pcpu = -1;
11412
11413 return 1;
11414 }
11415
11416 WARN((pi_desc->sn == 1),
11417 "Warning: SN field of posted-interrupts "
11418 "is set before blocking\n");
11419
11420 /*
11421 * Since vCPU can be preempted during this process,
11422 * vcpu->cpu could be different with pre_pcpu, we
11423 * need to set pre_pcpu as the destination of wakeup
11424 * notification event, then we can find the right vCPU
11425 * to wakeup in wakeup handler if interrupts happen
11426 * when the vCPU is in blocked state.
11427 */
11428 dest = cpu_physical_id(vcpu->pre_pcpu);
11429
11430 if (x2apic_enabled())
11431 new.ndst = dest;
11432 else
11433 new.ndst = (dest << 8) & 0xFF00;
11434
11435 /* set 'NV' to 'wakeup vector' */
11436 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11437 } while (cmpxchg(&pi_desc->control, old.control,
11438 new.control) != old.control);
11439
11440 return 0;
11441}
11442
bc22512b
YJ
11443static int vmx_pre_block(struct kvm_vcpu *vcpu)
11444{
11445 if (pi_pre_block(vcpu))
11446 return 1;
11447
64672c95
YJ
11448 if (kvm_lapic_hv_timer_in_use(vcpu))
11449 kvm_lapic_switch_to_sw_timer(vcpu);
11450
bc22512b
YJ
11451 return 0;
11452}
11453
11454static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8
FW
11455{
11456 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11457 struct pi_desc old, new;
11458 unsigned int dest;
11459 unsigned long flags;
11460
11461 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
11462 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11463 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW
11464 return;
11465
11466 do {
11467 old.control = new.control = pi_desc->control;
11468
11469 dest = cpu_physical_id(vcpu->cpu);
11470
11471 if (x2apic_enabled())
11472 new.ndst = dest;
11473 else
11474 new.ndst = (dest << 8) & 0xFF00;
11475
11476 /* Allow posting non-urgent interrupts */
11477 new.sn = 0;
11478
11479 /* set 'NV' to 'notification vector' */
11480 new.nv = POSTED_INTR_VECTOR;
11481 } while (cmpxchg(&pi_desc->control, old.control,
11482 new.control) != old.control);
11483
11484 if(vcpu->pre_pcpu != -1) {
11485 spin_lock_irqsave(
11486 &per_cpu(blocked_vcpu_on_cpu_lock,
11487 vcpu->pre_pcpu), flags);
11488 list_del(&vcpu->blocked_vcpu_list);
11489 spin_unlock_irqrestore(
11490 &per_cpu(blocked_vcpu_on_cpu_lock,
11491 vcpu->pre_pcpu), flags);
11492 vcpu->pre_pcpu = -1;
11493 }
11494}
11495
bc22512b
YJ
11496static void vmx_post_block(struct kvm_vcpu *vcpu)
11497{
64672c95
YJ
11498 if (kvm_x86_ops->set_hv_timer)
11499 kvm_lapic_switch_to_hv_timer(vcpu);
11500
bc22512b
YJ
11501 pi_post_block(vcpu);
11502}
11503
efc64404
FW
11504/*
11505 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11506 *
11507 * @kvm: kvm
11508 * @host_irq: host irq of the interrupt
11509 * @guest_irq: gsi of the interrupt
11510 * @set: set or unset PI
11511 * returns 0 on success, < 0 on failure
11512 */
11513static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11514 uint32_t guest_irq, bool set)
11515{
11516 struct kvm_kernel_irq_routing_entry *e;
11517 struct kvm_irq_routing_table *irq_rt;
11518 struct kvm_lapic_irq irq;
11519 struct kvm_vcpu *vcpu;
11520 struct vcpu_data vcpu_info;
11521 int idx, ret = -EINVAL;
11522
11523 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ
11524 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11525 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW
11526 return 0;
11527
11528 idx = srcu_read_lock(&kvm->irq_srcu);
11529 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11530 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11531
11532 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11533 if (e->type != KVM_IRQ_ROUTING_MSI)
11534 continue;
11535 /*
11536 * VT-d PI cannot support posting multicast/broadcast
11537 * interrupts to a vCPU, we still use interrupt remapping
11538 * for these kind of interrupts.
11539 *
11540 * For lowest-priority interrupts, we only support
11541 * those with single CPU as the destination, e.g. user
11542 * configures the interrupts via /proc/irq or uses
11543 * irqbalance to make the interrupts single-CPU.
11544 *
11545 * We will support full lowest-priority interrupt later.
11546 */
11547
37131313 11548 kvm_set_msi_irq(kvm, e, &irq);
23a1c257
FW
11549 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11550 /*
11551 * Make sure the IRTE is in remapped mode if
11552 * we don't handle it in posted mode.
11553 */
11554 ret = irq_set_vcpu_affinity(host_irq, NULL);
11555 if (ret < 0) {
11556 printk(KERN_INFO
11557 "failed to back to remapped mode, irq: %u\n",
11558 host_irq);
11559 goto out;
11560 }
11561
efc64404 11562 continue;
23a1c257 11563 }
efc64404
FW
11564
11565 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11566 vcpu_info.vector = irq.vector;
11567
b6ce9780 11568 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
efc64404
FW
11569 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11570
11571 if (set)
11572 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11573 else {
11574 /* suppress notification event before unposting */
11575 pi_set_sn(vcpu_to_pi_desc(vcpu));
11576 ret = irq_set_vcpu_affinity(host_irq, NULL);
11577 pi_clear_sn(vcpu_to_pi_desc(vcpu));
11578 }
11579
11580 if (ret < 0) {
11581 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11582 __func__);
11583 goto out;
11584 }
11585 }
11586
11587 ret = 0;
11588out:
11589 srcu_read_unlock(&kvm->irq_srcu, idx);
11590 return ret;
11591}
11592
c45dcc71
AR
11593static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11594{
11595 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11596 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11597 FEATURE_CONTROL_LMCE;
11598 else
11599 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11600 ~FEATURE_CONTROL_LMCE;
11601}
11602
404f6aac 11603static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK
11604 .cpu_has_kvm_support = cpu_has_kvm_support,
11605 .disabled_by_bios = vmx_disabled_by_bios,
11606 .hardware_setup = hardware_setup,
11607 .hardware_unsetup = hardware_unsetup,
002c7f7c 11608 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK
11609 .hardware_enable = hardware_enable,
11610 .hardware_disable = hardware_disable,
04547156 11611 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 11612 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK
11613
11614 .vcpu_create = vmx_create_vcpu,
11615 .vcpu_free = vmx_free_vcpu,
04d2cc77 11616 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 11617
04d2cc77 11618 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK
11619 .vcpu_load = vmx_vcpu_load,
11620 .vcpu_put = vmx_vcpu_put,
11621
a96036b8 11622 .update_bp_intercept = update_exception_bitmap,
6aa8b732
AK
11623 .get_msr = vmx_get_msr,
11624 .set_msr = vmx_set_msr,
11625 .get_segment_base = vmx_get_segment_base,
11626 .get_segment = vmx_get_segment,
11627 .set_segment = vmx_set_segment,
2e4d2653 11628 .get_cpl = vmx_get_cpl,
6aa8b732 11629 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 11630 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 11631 .decache_cr3 = vmx_decache_cr3,
25c4c276 11632 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 11633 .set_cr0 = vmx_set_cr0,
6aa8b732
AK
11634 .set_cr3 = vmx_set_cr3,
11635 .set_cr4 = vmx_set_cr4,
6aa8b732 11636 .set_efer = vmx_set_efer,
6aa8b732
AK
11637 .get_idt = vmx_get_idt,
11638 .set_idt = vmx_set_idt,
11639 .get_gdt = vmx_get_gdt,
11640 .set_gdt = vmx_set_gdt,
73aaf249
JK
11641 .get_dr6 = vmx_get_dr6,
11642 .set_dr6 = vmx_set_dr6,
020df079 11643 .set_dr7 = vmx_set_dr7,
81908bf4 11644 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 11645 .cache_reg = vmx_cache_reg,
6aa8b732
AK
11646 .get_rflags = vmx_get_rflags,
11647 .set_rflags = vmx_set_rflags,
be94f6b7
HH
11648
11649 .get_pkru = vmx_get_pkru,
11650
6aa8b732 11651 .tlb_flush = vmx_flush_tlb,
6aa8b732 11652
6aa8b732 11653 .run = vmx_vcpu_run,
6062d012 11654 .handle_exit = vmx_handle_exit,
6aa8b732 11655 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC
11656 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11657 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 11658 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 11659 .set_irq = vmx_inject_irq,
95ba8273 11660 .set_nmi = vmx_inject_nmi,
298101da 11661 .queue_exception = vmx_queue_exception,
b463a6f7 11662 .cancel_injection = vmx_cancel_injection,
78646121 11663 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 11664 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK
11665 .get_nmi_mask = vmx_get_nmi_mask,
11666 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN
11667 .enable_nmi_window = enable_nmi_window,
11668 .enable_irq_window = enable_irq_window,
11669 .update_cr8_intercept = update_cr8_intercept,
8d14695f 11670 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 11671 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb
AS
11672 .get_enable_apicv = vmx_get_enable_apicv,
11673 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 11674 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 11675 .apicv_post_state_restore = vmx_apicv_post_state_restore,
c7c9c56c
YZ
11676 .hwapic_irr_update = vmx_hwapic_irr_update,
11677 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ
11678 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11679 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 11680
cbc94022 11681 .set_tss_addr = vmx_set_tss_addr,
67253af5 11682 .get_tdp_level = get_ept_level,
4b12f0de 11683 .get_mt_mask = vmx_get_mt_mask,
229456fc 11684
586f9607 11685 .get_exit_info = vmx_get_exit_info,
586f9607 11686
17cc3935 11687 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY
11688
11689 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY
11690
11691 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 11692 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR
11693
11694 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY
11695
11696 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA
11697
11698 .write_tsc_offset = vmx_write_tsc_offset,
1c97f0a0
JR
11699
11700 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR
11701
11702 .check_intercept = vmx_check_intercept,
a547c6db 11703 .handle_external_intr = vmx_handle_external_intr,
da8999d3 11704 .mpx_supported = vmx_mpx_supported,
55412b2e 11705 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK
11706
11707 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK
11708
11709 .sched_in = vmx_sched_in,
843e4330
KH
11710
11711 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11712 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11713 .flush_log_dirty = vmx_flush_log_dirty,
11714 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 11715 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 11716
bf9f6ac8
FW
11717 .pre_block = vmx_pre_block,
11718 .post_block = vmx_post_block,
11719
25462f7f 11720 .pmu_ops = &intel_pmu_ops,
efc64404
FW
11721
11722 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ
11723
11724#ifdef CONFIG_X86_64
11725 .set_hv_timer = vmx_set_hv_timer,
11726 .cancel_hv_timer = vmx_cancel_hv_timer,
11727#endif
c45dcc71
AR
11728
11729 .setup_mce = vmx_setup_mce,
6aa8b732
AK
11730};
11731
11732static int __init vmx_init(void)
11733{
34a1cd60
TC
11734 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11735 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 11736 if (r)
34a1cd60 11737 return r;
25c5f225 11738
2965faa5 11739#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY
11740 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11741 crash_vmclear_local_loaded_vmcss);
11742#endif
11743
fdef3ad1 11744 return 0;
6aa8b732
AK
11745}
11746
11747static void __exit vmx_exit(void)
11748{
2965faa5 11749#ifdef CONFIG_KEXEC_CORE
3b63a43f 11750 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY
11751 synchronize_rcu();
11752#endif
11753
cb498ea2 11754 kvm_exit();
6aa8b732
AK
11755}
11756
11757module_init(vmx_init)
11758module_exit(vmx_exit)