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Merge branch 'sched/urgent' into x86/mm, to pick up dependent fix
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
d62caabb 22#include "lapic.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732 25#include <linux/module.h>
9d8f549d 26#include <linux/kernel.h>
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27#include <linux/mm.h>
28#include <linux/highmem.h>
e8edc6e0 29#include <linux/sched.h>
c7addb90 30#include <linux/moduleparam.h>
e9bda3b3 31#include <linux/mod_devicetable.h>
af658dca 32#include <linux/trace_events.h>
5a0e3ad6 33#include <linux/slab.h>
cafd6659 34#include <linux/tboot.h>
f4124500 35#include <linux/hrtimer.h>
5fdbf976 36#include "kvm_cache_regs.h"
35920a35 37#include "x86.h"
e495606d 38
28b835d6 39#include <asm/cpu.h>
6aa8b732 40#include <asm/io.h>
3b3be0d1 41#include <asm/desc.h>
13673a90 42#include <asm/vmx.h>
6210e37b 43#include <asm/virtext.h>
a0861c02 44#include <asm/mce.h>
952f07ec 45#include <asm/fpu/internal.h>
d7cd9796 46#include <asm/perf_event.h>
81908bf4 47#include <asm/debugreg.h>
8f536b76 48#include <asm/kexec.h>
dab2087d 49#include <asm/apic.h>
efc64404 50#include <asm/irq_remapping.h>
d6e41f11 51#include <asm/mmu_context.h>
6aa8b732 52
229456fc 53#include "trace.h"
25462f7f 54#include "pmu.h"
229456fc 55
4ecac3fd 56#define __ex(x) __kvm_handle_fault_on_reboot(x)
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57#define __ex_clear(x, reg) \
58 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 59
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60MODULE_AUTHOR("Qumranet");
61MODULE_LICENSE("GPL");
62
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63static const struct x86_cpu_id vmx_cpu_id[] = {
64 X86_FEATURE_MATCH(X86_FEATURE_VMX),
65 {}
66};
67MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
68
476bc001 69static bool __read_mostly enable_vpid = 1;
736caefe 70module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 71
476bc001 72static bool __read_mostly flexpriority_enabled = 1;
736caefe 73module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 74
476bc001 75static bool __read_mostly enable_ept = 1;
736caefe 76module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 77
476bc001 78static bool __read_mostly enable_unrestricted_guest = 1;
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79module_param_named(unrestricted_guest,
80 enable_unrestricted_guest, bool, S_IRUGO);
81
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82static bool __read_mostly enable_ept_ad_bits = 1;
83module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
84
a27685c3 85static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 86module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 87
476bc001 88static bool __read_mostly fasteoi = 1;
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89module_param(fasteoi, bool, S_IRUGO);
90
5a71785d 91static bool __read_mostly enable_apicv = 1;
01e439be 92module_param(enable_apicv, bool, S_IRUGO);
83d4c286 93
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94static bool __read_mostly enable_shadow_vmcs = 1;
95module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
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96/*
97 * If nested=1, nested virtualization is supported, i.e., guests may use
98 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
99 * use VMX instructions.
100 */
476bc001 101static bool __read_mostly nested = 0;
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102module_param(nested, bool, S_IRUGO);
103
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104static u64 __read_mostly host_xss;
105
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106static bool __read_mostly enable_pml = 1;
107module_param_named(pml, enable_pml, bool, S_IRUGO);
108
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109#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
110
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111/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
112static int __read_mostly cpu_preemption_timer_multi;
113static bool __read_mostly enable_preemption_timer = 1;
114#ifdef CONFIG_X86_64
115module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
116#endif
117
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118#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
119#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
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120#define KVM_VM_CR0_ALWAYS_ON \
121 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
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122#define KVM_CR4_GUEST_OWNED_BITS \
123 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 124 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 125
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126#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
127#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
128
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129#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
130
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131#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
132
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133/*
134 * Hyper-V requires all of these, so mark them as supported even though
135 * they are just treated the same as all-context.
136 */
137#define VMX_VPID_EXTENT_SUPPORTED_MASK \
138 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
139 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
140 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
142
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143/*
144 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
145 * ple_gap: upper bound on the amount of time between two successive
146 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 147 * According to test, this time is usually smaller than 128 cycles.
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148 * ple_window: upper bound on the amount of time a guest is allowed to execute
149 * in a PAUSE loop. Tests indicate that most spinlocks are held for
150 * less than 2^12 cycles
151 * Time is measured based on a counter that runs at the same rate as the TSC,
152 * refer SDM volume 3b section 21.6.13 & 22.1.3.
153 */
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154#define KVM_VMX_DEFAULT_PLE_GAP 128
155#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
156#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
157#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
158#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
159 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
160
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161static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
162module_param(ple_gap, int, S_IRUGO);
163
164static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
165module_param(ple_window, int, S_IRUGO);
166
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167/* Default doubles per-vcpu window every exit. */
168static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
169module_param(ple_window_grow, int, S_IRUGO);
170
171/* Default resets per-vcpu window every exit to ple_window. */
172static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
173module_param(ple_window_shrink, int, S_IRUGO);
174
175/* Default is to compute the maximum so we can never overflow. */
176static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
177static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
178module_param(ple_window_max, int, S_IRUGO);
179
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180extern const ulong vmx_return;
181
8bf00a52 182#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 183#define VMCS02_POOL_SIZE 1
61d2ef2c 184
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185struct vmcs {
186 u32 revision_id;
187 u32 abort;
188 char data[0];
189};
190
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191/*
192 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
193 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
194 * loaded on this CPU (so we can clear them if the CPU goes down).
195 */
196struct loaded_vmcs {
197 struct vmcs *vmcs;
355f4fb1 198 struct vmcs *shadow_vmcs;
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199 int cpu;
200 int launched;
201 struct list_head loaded_vmcss_on_cpu_link;
202};
203
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204struct shared_msr_entry {
205 unsigned index;
206 u64 data;
d5696725 207 u64 mask;
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208};
209
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210/*
211 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
212 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
213 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
214 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
215 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
216 * More than one of these structures may exist, if L1 runs multiple L2 guests.
217 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
218 * underlying hardware which will be used to run L2.
219 * This structure is packed to ensure that its layout is identical across
220 * machines (necessary for live migration).
221 * If there are changes in this struct, VMCS12_REVISION must be changed.
222 */
22bd0358 223typedef u64 natural_width;
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224struct __packed vmcs12 {
225 /* According to the Intel spec, a VMCS region must start with the
226 * following two fields. Then follow implementation-specific data.
227 */
228 u32 revision_id;
229 u32 abort;
22bd0358 230
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231 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
232 u32 padding[7]; /* room for future expansion */
233
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234 u64 io_bitmap_a;
235 u64 io_bitmap_b;
236 u64 msr_bitmap;
237 u64 vm_exit_msr_store_addr;
238 u64 vm_exit_msr_load_addr;
239 u64 vm_entry_msr_load_addr;
240 u64 tsc_offset;
241 u64 virtual_apic_page_addr;
242 u64 apic_access_addr;
705699a1 243 u64 posted_intr_desc_addr;
22bd0358 244 u64 ept_pointer;
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245 u64 eoi_exit_bitmap0;
246 u64 eoi_exit_bitmap1;
247 u64 eoi_exit_bitmap2;
248 u64 eoi_exit_bitmap3;
81dc01f7 249 u64 xss_exit_bitmap;
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250 u64 guest_physical_address;
251 u64 vmcs_link_pointer;
c5f983f6 252 u64 pml_address;
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253 u64 guest_ia32_debugctl;
254 u64 guest_ia32_pat;
255 u64 guest_ia32_efer;
256 u64 guest_ia32_perf_global_ctrl;
257 u64 guest_pdptr0;
258 u64 guest_pdptr1;
259 u64 guest_pdptr2;
260 u64 guest_pdptr3;
36be0b9d 261 u64 guest_bndcfgs;
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262 u64 host_ia32_pat;
263 u64 host_ia32_efer;
264 u64 host_ia32_perf_global_ctrl;
265 u64 padding64[8]; /* room for future expansion */
266 /*
267 * To allow migration of L1 (complete with its L2 guests) between
268 * machines of different natural widths (32 or 64 bit), we cannot have
269 * unsigned long fields with no explict size. We use u64 (aliased
270 * natural_width) instead. Luckily, x86 is little-endian.
271 */
272 natural_width cr0_guest_host_mask;
273 natural_width cr4_guest_host_mask;
274 natural_width cr0_read_shadow;
275 natural_width cr4_read_shadow;
276 natural_width cr3_target_value0;
277 natural_width cr3_target_value1;
278 natural_width cr3_target_value2;
279 natural_width cr3_target_value3;
280 natural_width exit_qualification;
281 natural_width guest_linear_address;
282 natural_width guest_cr0;
283 natural_width guest_cr3;
284 natural_width guest_cr4;
285 natural_width guest_es_base;
286 natural_width guest_cs_base;
287 natural_width guest_ss_base;
288 natural_width guest_ds_base;
289 natural_width guest_fs_base;
290 natural_width guest_gs_base;
291 natural_width guest_ldtr_base;
292 natural_width guest_tr_base;
293 natural_width guest_gdtr_base;
294 natural_width guest_idtr_base;
295 natural_width guest_dr7;
296 natural_width guest_rsp;
297 natural_width guest_rip;
298 natural_width guest_rflags;
299 natural_width guest_pending_dbg_exceptions;
300 natural_width guest_sysenter_esp;
301 natural_width guest_sysenter_eip;
302 natural_width host_cr0;
303 natural_width host_cr3;
304 natural_width host_cr4;
305 natural_width host_fs_base;
306 natural_width host_gs_base;
307 natural_width host_tr_base;
308 natural_width host_gdtr_base;
309 natural_width host_idtr_base;
310 natural_width host_ia32_sysenter_esp;
311 natural_width host_ia32_sysenter_eip;
312 natural_width host_rsp;
313 natural_width host_rip;
314 natural_width paddingl[8]; /* room for future expansion */
315 u32 pin_based_vm_exec_control;
316 u32 cpu_based_vm_exec_control;
317 u32 exception_bitmap;
318 u32 page_fault_error_code_mask;
319 u32 page_fault_error_code_match;
320 u32 cr3_target_count;
321 u32 vm_exit_controls;
322 u32 vm_exit_msr_store_count;
323 u32 vm_exit_msr_load_count;
324 u32 vm_entry_controls;
325 u32 vm_entry_msr_load_count;
326 u32 vm_entry_intr_info_field;
327 u32 vm_entry_exception_error_code;
328 u32 vm_entry_instruction_len;
329 u32 tpr_threshold;
330 u32 secondary_vm_exec_control;
331 u32 vm_instruction_error;
332 u32 vm_exit_reason;
333 u32 vm_exit_intr_info;
334 u32 vm_exit_intr_error_code;
335 u32 idt_vectoring_info_field;
336 u32 idt_vectoring_error_code;
337 u32 vm_exit_instruction_len;
338 u32 vmx_instruction_info;
339 u32 guest_es_limit;
340 u32 guest_cs_limit;
341 u32 guest_ss_limit;
342 u32 guest_ds_limit;
343 u32 guest_fs_limit;
344 u32 guest_gs_limit;
345 u32 guest_ldtr_limit;
346 u32 guest_tr_limit;
347 u32 guest_gdtr_limit;
348 u32 guest_idtr_limit;
349 u32 guest_es_ar_bytes;
350 u32 guest_cs_ar_bytes;
351 u32 guest_ss_ar_bytes;
352 u32 guest_ds_ar_bytes;
353 u32 guest_fs_ar_bytes;
354 u32 guest_gs_ar_bytes;
355 u32 guest_ldtr_ar_bytes;
356 u32 guest_tr_ar_bytes;
357 u32 guest_interruptibility_info;
358 u32 guest_activity_state;
359 u32 guest_sysenter_cs;
360 u32 host_ia32_sysenter_cs;
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361 u32 vmx_preemption_timer_value;
362 u32 padding32[7]; /* room for future expansion */
22bd0358 363 u16 virtual_processor_id;
705699a1 364 u16 posted_intr_nv;
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365 u16 guest_es_selector;
366 u16 guest_cs_selector;
367 u16 guest_ss_selector;
368 u16 guest_ds_selector;
369 u16 guest_fs_selector;
370 u16 guest_gs_selector;
371 u16 guest_ldtr_selector;
372 u16 guest_tr_selector;
608406e2 373 u16 guest_intr_status;
c5f983f6 374 u16 guest_pml_index;
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375 u16 host_es_selector;
376 u16 host_cs_selector;
377 u16 host_ss_selector;
378 u16 host_ds_selector;
379 u16 host_fs_selector;
380 u16 host_gs_selector;
381 u16 host_tr_selector;
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382};
383
384/*
385 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
386 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
387 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
388 */
389#define VMCS12_REVISION 0x11e57ed0
390
391/*
392 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
393 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
394 * current implementation, 4K are reserved to avoid future complications.
395 */
396#define VMCS12_SIZE 0x1000
397
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398/* Used to remember the last vmcs02 used for some recently used vmcs12s */
399struct vmcs02_list {
400 struct list_head list;
401 gpa_t vmptr;
402 struct loaded_vmcs vmcs02;
403};
404
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405/*
406 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
407 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
408 */
409struct nested_vmx {
410 /* Has the level1 guest done vmxon? */
411 bool vmxon;
3573e22c 412 gpa_t vmxon_ptr;
c5f983f6 413 bool pml_full;
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414
415 /* The guest-physical address of the current VMCS L1 keeps for L2 */
416 gpa_t current_vmptr;
417 /* The host-usable pointer to the above */
418 struct page *current_vmcs12_page;
419 struct vmcs12 *current_vmcs12;
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420 /*
421 * Cache of the guest's VMCS, existing outside of guest memory.
422 * Loaded from guest memory during VMPTRLD. Flushed to guest
423 * memory during VMXOFF, VMCLEAR, VMPTRLD.
424 */
425 struct vmcs12 *cached_vmcs12;
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426 /*
427 * Indicates if the shadow vmcs must be updated with the
428 * data hold by vmcs12
429 */
430 bool sync_shadow_vmcs;
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431
432 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
433 struct list_head vmcs02_pool;
434 int vmcs02_num;
dccbfcf5 435 bool change_vmcs01_virtual_x2apic_mode;
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436 /* L2 must run next, and mustn't decide to exit to L1. */
437 bool nested_run_pending;
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438 /*
439 * Guest pages referred to in vmcs02 with host-physical pointers, so
440 * we must keep them pinned while L2 runs.
441 */
442 struct page *apic_access_page;
a7c0b07d 443 struct page *virtual_apic_page;
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444 struct page *pi_desc_page;
445 struct pi_desc *pi_desc;
446 bool pi_pending;
447 u16 posted_intr_nv;
f4124500 448
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449 unsigned long *msr_bitmap;
450
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451 struct hrtimer preemption_timer;
452 bool preemption_timer_expired;
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453
454 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
455 u64 vmcs01_debugctl;
b9c237bb 456
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WL
457 u16 vpid02;
458 u16 last_vpid;
459
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DM
460 /*
461 * We only store the "true" versions of the VMX capability MSRs. We
462 * generate the "non-true" versions by setting the must-be-1 bits
463 * according to the SDM.
464 */
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465 u32 nested_vmx_procbased_ctls_low;
466 u32 nested_vmx_procbased_ctls_high;
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467 u32 nested_vmx_secondary_ctls_low;
468 u32 nested_vmx_secondary_ctls_high;
469 u32 nested_vmx_pinbased_ctls_low;
470 u32 nested_vmx_pinbased_ctls_high;
471 u32 nested_vmx_exit_ctls_low;
472 u32 nested_vmx_exit_ctls_high;
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473 u32 nested_vmx_entry_ctls_low;
474 u32 nested_vmx_entry_ctls_high;
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475 u32 nested_vmx_misc_low;
476 u32 nested_vmx_misc_high;
477 u32 nested_vmx_ept_caps;
99b83ac8 478 u32 nested_vmx_vpid_caps;
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DM
479 u64 nested_vmx_basic;
480 u64 nested_vmx_cr0_fixed0;
481 u64 nested_vmx_cr0_fixed1;
482 u64 nested_vmx_cr4_fixed0;
483 u64 nested_vmx_cr4_fixed1;
484 u64 nested_vmx_vmcs_enum;
ec378aee
NHE
485};
486
01e439be 487#define POSTED_INTR_ON 0
ebbfc765
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488#define POSTED_INTR_SN 1
489
01e439be
YZ
490/* Posted-Interrupt Descriptor */
491struct pi_desc {
492 u32 pir[8]; /* Posted interrupt requested */
6ef1522f
FW
493 union {
494 struct {
495 /* bit 256 - Outstanding Notification */
496 u16 on : 1,
497 /* bit 257 - Suppress Notification */
498 sn : 1,
499 /* bit 271:258 - Reserved */
500 rsvd_1 : 14;
501 /* bit 279:272 - Notification Vector */
502 u8 nv;
503 /* bit 287:280 - Reserved */
504 u8 rsvd_2;
505 /* bit 319:288 - Notification Destination */
506 u32 ndst;
507 };
508 u64 control;
509 };
510 u32 rsvd[6];
01e439be
YZ
511} __aligned(64);
512
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513static bool pi_test_and_set_on(struct pi_desc *pi_desc)
514{
515 return test_and_set_bit(POSTED_INTR_ON,
516 (unsigned long *)&pi_desc->control);
517}
518
519static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
520{
521 return test_and_clear_bit(POSTED_INTR_ON,
522 (unsigned long *)&pi_desc->control);
523}
524
525static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
526{
527 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
528}
529
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FW
530static inline void pi_clear_sn(struct pi_desc *pi_desc)
531{
532 return clear_bit(POSTED_INTR_SN,
533 (unsigned long *)&pi_desc->control);
534}
535
536static inline void pi_set_sn(struct pi_desc *pi_desc)
537{
538 return set_bit(POSTED_INTR_SN,
539 (unsigned long *)&pi_desc->control);
540}
541
ad361091
PB
542static inline void pi_clear_on(struct pi_desc *pi_desc)
543{
544 clear_bit(POSTED_INTR_ON,
545 (unsigned long *)&pi_desc->control);
546}
547
ebbfc765
FW
548static inline int pi_test_on(struct pi_desc *pi_desc)
549{
550 return test_bit(POSTED_INTR_ON,
551 (unsigned long *)&pi_desc->control);
552}
553
554static inline int pi_test_sn(struct pi_desc *pi_desc)
555{
556 return test_bit(POSTED_INTR_SN,
557 (unsigned long *)&pi_desc->control);
558}
559
a2fa3e9f 560struct vcpu_vmx {
fb3f0f51 561 struct kvm_vcpu vcpu;
313dbd49 562 unsigned long host_rsp;
29bd8a78 563 u8 fail;
9d58b931 564 bool nmi_known_unmasked;
51aa01d1 565 u32 exit_intr_info;
1155f76a 566 u32 idt_vectoring_info;
6de12732 567 ulong rflags;
26bb0981 568 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH
569 int nmsrs;
570 int save_nmsrs;
a547c6db 571 unsigned long host_idt_base;
a2fa3e9f 572#ifdef CONFIG_X86_64
44ea2b17
AK
573 u64 msr_host_kernel_gs_base;
574 u64 msr_guest_kernel_gs_base;
a2fa3e9f 575#endif
2961e876
GN
576 u32 vm_entry_controls_shadow;
577 u32 vm_exit_controls_shadow;
d462b819
NHE
578 /*
579 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
580 * non-nested (L1) guest, it always points to vmcs01. For a nested
581 * guest (L2), it points to a different VMCS.
582 */
583 struct loaded_vmcs vmcs01;
584 struct loaded_vmcs *loaded_vmcs;
585 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK
586 struct msr_autoload {
587 unsigned nr;
588 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
589 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
590 } msr_autoload;
a2fa3e9f
GH
591 struct {
592 int loaded;
593 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK
594#ifdef CONFIG_X86_64
595 u16 ds_sel, es_sel;
596#endif
152d3f2f
LV
597 int gs_ldt_reload_needed;
598 int fs_reload_needed;
da8999d3 599 u64 msr_host_bndcfgs;
d6e41f11 600 unsigned long vmcs_host_cr3; /* May not match real cr3 */
d974baa3 601 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 602 } host_state;
9c8cba37 603 struct {
7ffd92c5 604 int vm86_active;
78ac8b47 605 ulong save_rflags;
f5f7b2fe
AK
606 struct kvm_segment segs[8];
607 } rmode;
608 struct {
609 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK
610 struct kvm_save_segment {
611 u16 selector;
612 unsigned long base;
613 u32 limit;
614 u32 ar;
f5f7b2fe 615 } seg[8];
2fb92db1 616 } segment_cache;
2384d2b3 617 int vpid;
04fa4d32 618 bool emulation_required;
3b86cd99 619
a0861c02 620 u32 exit_reason;
4e47c7a6 621
01e439be
YZ
622 /* Posted interrupt descriptor */
623 struct pi_desc pi_desc;
624
ec378aee
NHE
625 /* Support for a guest hypervisor (nested VMX) */
626 struct nested_vmx nested;
a7653ecd
RK
627
628 /* Dynamic PLE window. */
629 int ple_window;
630 bool ple_window_dirty;
843e4330
KH
631
632 /* Support for PML */
633#define PML_ENTITY_NUM 512
634 struct page *pml_pg;
2680d6da 635
64672c95
YJ
636 /* apic deadline value in host tsc */
637 u64 hv_deadline_tsc;
638
2680d6da 639 u64 current_tsc_ratio;
1be0e61c
XG
640
641 bool guest_pkru_valid;
642 u32 guest_pkru;
643 u32 host_pkru;
3b84080b 644
37e4c997
HZ
645 /*
646 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
647 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
648 * in msr_ia32_feature_control_valid_bits.
649 */
3b84080b 650 u64 msr_ia32_feature_control;
37e4c997 651 u64 msr_ia32_feature_control_valid_bits;
a2fa3e9f
GH
652};
653
2fb92db1
AK
654enum segment_cache_field {
655 SEG_FIELD_SEL = 0,
656 SEG_FIELD_BASE = 1,
657 SEG_FIELD_LIMIT = 2,
658 SEG_FIELD_AR = 3,
659
660 SEG_FIELD_NR = 4
661};
662
a2fa3e9f
GH
663static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
664{
fb3f0f51 665 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH
666}
667
efc64404
FW
668static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
669{
670 return &(to_vmx(vcpu)->pi_desc);
671}
672
22bd0358
NHE
673#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
674#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
675#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
676 [number##_HIGH] = VMCS12_OFFSET(name)+4
677
4607c2d7 678
fe2b201b 679static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG
680 /*
681 * We do NOT shadow fields that are modified when L0
682 * traps and emulates any vmx instruction (e.g. VMPTRLD,
683 * VMXON...) executed by L1.
684 * For example, VM_INSTRUCTION_ERROR is read
685 * by L1 if a vmx instruction fails (part of the error path).
686 * Note the code assumes this logic. If for some reason
687 * we start shadowing these fields then we need to
688 * force a shadow sync when L0 emulates vmx instructions
689 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
690 * by nested_vmx_failValid)
691 */
692 VM_EXIT_REASON,
693 VM_EXIT_INTR_INFO,
694 VM_EXIT_INSTRUCTION_LEN,
695 IDT_VECTORING_INFO_FIELD,
696 IDT_VECTORING_ERROR_CODE,
697 VM_EXIT_INTR_ERROR_CODE,
698 EXIT_QUALIFICATION,
699 GUEST_LINEAR_ADDRESS,
700 GUEST_PHYSICAL_ADDRESS
701};
fe2b201b 702static int max_shadow_read_only_fields =
4607c2d7
AG
703 ARRAY_SIZE(shadow_read_only_fields);
704
fe2b201b 705static unsigned long shadow_read_write_fields[] = {
a7c0b07d 706 TPR_THRESHOLD,
4607c2d7
AG
707 GUEST_RIP,
708 GUEST_RSP,
709 GUEST_CR0,
710 GUEST_CR3,
711 GUEST_CR4,
712 GUEST_INTERRUPTIBILITY_INFO,
713 GUEST_RFLAGS,
714 GUEST_CS_SELECTOR,
715 GUEST_CS_AR_BYTES,
716 GUEST_CS_LIMIT,
717 GUEST_CS_BASE,
718 GUEST_ES_BASE,
36be0b9d 719 GUEST_BNDCFGS,
4607c2d7
AG
720 CR0_GUEST_HOST_MASK,
721 CR0_READ_SHADOW,
722 CR4_READ_SHADOW,
723 TSC_OFFSET,
724 EXCEPTION_BITMAP,
725 CPU_BASED_VM_EXEC_CONTROL,
726 VM_ENTRY_EXCEPTION_ERROR_CODE,
727 VM_ENTRY_INTR_INFO_FIELD,
728 VM_ENTRY_INSTRUCTION_LEN,
729 VM_ENTRY_EXCEPTION_ERROR_CODE,
730 HOST_FS_BASE,
731 HOST_GS_BASE,
732 HOST_FS_SELECTOR,
733 HOST_GS_SELECTOR
734};
fe2b201b 735static int max_shadow_read_write_fields =
4607c2d7
AG
736 ARRAY_SIZE(shadow_read_write_fields);
737
772e0318 738static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 739 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 740 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE
741 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
742 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
743 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
744 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
745 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
746 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
747 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
748 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 749 FIELD(GUEST_INTR_STATUS, guest_intr_status),
c5f983f6 750 FIELD(GUEST_PML_INDEX, guest_pml_index),
22bd0358
NHE
751 FIELD(HOST_ES_SELECTOR, host_es_selector),
752 FIELD(HOST_CS_SELECTOR, host_cs_selector),
753 FIELD(HOST_SS_SELECTOR, host_ss_selector),
754 FIELD(HOST_DS_SELECTOR, host_ds_selector),
755 FIELD(HOST_FS_SELECTOR, host_fs_selector),
756 FIELD(HOST_GS_SELECTOR, host_gs_selector),
757 FIELD(HOST_TR_SELECTOR, host_tr_selector),
758 FIELD64(IO_BITMAP_A, io_bitmap_a),
759 FIELD64(IO_BITMAP_B, io_bitmap_b),
760 FIELD64(MSR_BITMAP, msr_bitmap),
761 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
762 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
763 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
764 FIELD64(TSC_OFFSET, tsc_offset),
765 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
766 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 767 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 768 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV
769 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
770 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
771 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
772 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 773 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE
774 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
775 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
c5f983f6 776 FIELD64(PML_ADDRESS, pml_address),
22bd0358
NHE
777 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
778 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
779 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
780 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
781 FIELD64(GUEST_PDPTR0, guest_pdptr0),
782 FIELD64(GUEST_PDPTR1, guest_pdptr1),
783 FIELD64(GUEST_PDPTR2, guest_pdptr2),
784 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 785 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE
786 FIELD64(HOST_IA32_PAT, host_ia32_pat),
787 FIELD64(HOST_IA32_EFER, host_ia32_efer),
788 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
789 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
790 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
791 FIELD(EXCEPTION_BITMAP, exception_bitmap),
792 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
793 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
794 FIELD(CR3_TARGET_COUNT, cr3_target_count),
795 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
796 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
797 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
798 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
799 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
800 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
801 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
802 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
803 FIELD(TPR_THRESHOLD, tpr_threshold),
804 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
805 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
806 FIELD(VM_EXIT_REASON, vm_exit_reason),
807 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
808 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
809 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
810 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
811 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
812 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
813 FIELD(GUEST_ES_LIMIT, guest_es_limit),
814 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
815 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
816 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
817 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
818 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
819 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
820 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
821 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
822 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
823 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
824 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
825 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
826 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
827 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
828 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
829 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
830 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
831 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
832 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
833 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
834 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 835 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE
836 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
837 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
838 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
839 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
840 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
841 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
842 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
843 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
844 FIELD(EXIT_QUALIFICATION, exit_qualification),
845 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
846 FIELD(GUEST_CR0, guest_cr0),
847 FIELD(GUEST_CR3, guest_cr3),
848 FIELD(GUEST_CR4, guest_cr4),
849 FIELD(GUEST_ES_BASE, guest_es_base),
850 FIELD(GUEST_CS_BASE, guest_cs_base),
851 FIELD(GUEST_SS_BASE, guest_ss_base),
852 FIELD(GUEST_DS_BASE, guest_ds_base),
853 FIELD(GUEST_FS_BASE, guest_fs_base),
854 FIELD(GUEST_GS_BASE, guest_gs_base),
855 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
856 FIELD(GUEST_TR_BASE, guest_tr_base),
857 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
858 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
859 FIELD(GUEST_DR7, guest_dr7),
860 FIELD(GUEST_RSP, guest_rsp),
861 FIELD(GUEST_RIP, guest_rip),
862 FIELD(GUEST_RFLAGS, guest_rflags),
863 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
864 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
865 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
866 FIELD(HOST_CR0, host_cr0),
867 FIELD(HOST_CR3, host_cr3),
868 FIELD(HOST_CR4, host_cr4),
869 FIELD(HOST_FS_BASE, host_fs_base),
870 FIELD(HOST_GS_BASE, host_gs_base),
871 FIELD(HOST_TR_BASE, host_tr_base),
872 FIELD(HOST_GDTR_BASE, host_gdtr_base),
873 FIELD(HOST_IDTR_BASE, host_idtr_base),
874 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
875 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
876 FIELD(HOST_RSP, host_rsp),
877 FIELD(HOST_RIP, host_rip),
878};
22bd0358
NHE
879
880static inline short vmcs_field_to_offset(unsigned long field)
881{
a2ae9df7
PB
882 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
883
884 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
885 vmcs_field_to_offset_table[field] == 0)
886 return -ENOENT;
887
22bd0358
NHE
888 return vmcs_field_to_offset_table[field];
889}
890
a9d30f33
NHE
891static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
892{
4f2777bc 893 return to_vmx(vcpu)->nested.cached_vmcs12;
a9d30f33
NHE
894}
895
896static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
897{
54bf36aa 898 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 899 if (is_error_page(page))
a9d30f33 900 return NULL;
32cad84f 901
a9d30f33
NHE
902 return page;
903}
904
905static void nested_release_page(struct page *page)
906{
907 kvm_release_page_dirty(page);
908}
909
910static void nested_release_page_clean(struct page *page)
911{
912 kvm_release_page_clean(page);
913}
914
bfd0a56b 915static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 916static u64 construct_eptp(unsigned long root_hpa);
f53cd63c 917static bool vmx_xsaves_supported(void);
776e58ea 918static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW
919static void vmx_set_segment(struct kvm_vcpu *vcpu,
920 struct kvm_segment *var, int seg);
921static void vmx_get_segment(struct kvm_vcpu *vcpu,
922 struct kvm_segment *var, int seg);
d99e4152
GN
923static bool guest_state_valid(struct kvm_vcpu *vcpu);
924static u32 vmx_segment_access_rights(struct kvm_segment *var);
c3114420 925static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 926static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 927static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 928
6aa8b732
AK
929static DEFINE_PER_CPU(struct vmcs *, vmxarea);
930static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE
931/*
932 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
933 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
934 */
935static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 936
bf9f6ac8
FW
937/*
938 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
939 * can find which vCPU should be waken up.
940 */
941static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
942static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
943
23611332
RK
944enum {
945 VMX_IO_BITMAP_A,
946 VMX_IO_BITMAP_B,
947 VMX_MSR_BITMAP_LEGACY,
948 VMX_MSR_BITMAP_LONGMODE,
949 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
950 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
951 VMX_MSR_BITMAP_LEGACY_X2APIC,
952 VMX_MSR_BITMAP_LONGMODE_X2APIC,
953 VMX_VMREAD_BITMAP,
954 VMX_VMWRITE_BITMAP,
955 VMX_BITMAP_NR
956};
957
958static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
959
960#define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
961#define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
962#define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
963#define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
964#define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
965#define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
966#define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
967#define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
968#define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
969#define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
fdef3ad1 970
110312c8 971static bool cpu_has_load_ia32_efer;
8bf00a52 972static bool cpu_has_load_perf_global_ctrl;
110312c8 973
2384d2b3
SY
974static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
975static DEFINE_SPINLOCK(vmx_vpid_lock);
976
1c3d14fe 977static struct vmcs_config {
6aa8b732
AK
978 int size;
979 int order;
9ac7e3e8 980 u32 basic_cap;
6aa8b732 981 u32 revision_id;
1c3d14fe
YS
982 u32 pin_based_exec_ctrl;
983 u32 cpu_based_exec_ctrl;
f78e0e2e 984 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS
985 u32 vmexit_ctrl;
986 u32 vmentry_ctrl;
987} vmcs_config;
6aa8b732 988
efff9e53 989static struct vmx_capability {
d56f546d
SY
990 u32 ept;
991 u32 vpid;
992} vmx_capability;
993
6aa8b732
AK
994#define VMX_SEGMENT_FIELD(seg) \
995 [VCPU_SREG_##seg] = { \
996 .selector = GUEST_##seg##_SELECTOR, \
997 .base = GUEST_##seg##_BASE, \
998 .limit = GUEST_##seg##_LIMIT, \
999 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1000 }
1001
772e0318 1002static const struct kvm_vmx_segment_field {
6aa8b732
AK
1003 unsigned selector;
1004 unsigned base;
1005 unsigned limit;
1006 unsigned ar_bytes;
1007} kvm_vmx_segment_fields[] = {
1008 VMX_SEGMENT_FIELD(CS),
1009 VMX_SEGMENT_FIELD(DS),
1010 VMX_SEGMENT_FIELD(ES),
1011 VMX_SEGMENT_FIELD(FS),
1012 VMX_SEGMENT_FIELD(GS),
1013 VMX_SEGMENT_FIELD(SS),
1014 VMX_SEGMENT_FIELD(TR),
1015 VMX_SEGMENT_FIELD(LDTR),
1016};
1017
26bb0981
AK
1018static u64 host_efer;
1019
6de4f3ad
AK
1020static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1021
4d56c8a7 1022/*
8c06585d 1023 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK
1024 * away by decrementing the array size.
1025 */
6aa8b732 1026static const u32 vmx_msr_index[] = {
05b3e0c2 1027#ifdef CONFIG_X86_64
44ea2b17 1028 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 1029#endif
8c06585d 1030 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 1031};
6aa8b732 1032
5bb16016 1033static inline bool is_exception_n(u32 intr_info, u8 vector)
6aa8b732
AK
1034{
1035 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1036 INTR_INFO_VALID_MASK)) ==
5bb16016
JK
1037 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1038}
1039
6f05485d
JK
1040static inline bool is_debug(u32 intr_info)
1041{
1042 return is_exception_n(intr_info, DB_VECTOR);
1043}
1044
1045static inline bool is_breakpoint(u32 intr_info)
1046{
1047 return is_exception_n(intr_info, BP_VECTOR);
1048}
1049
5bb16016
JK
1050static inline bool is_page_fault(u32 intr_info)
1051{
1052 return is_exception_n(intr_info, PF_VECTOR);
6aa8b732
AK
1053}
1054
31299944 1055static inline bool is_no_device(u32 intr_info)
2ab455cc 1056{
5bb16016 1057 return is_exception_n(intr_info, NM_VECTOR);
2ab455cc
AL
1058}
1059
31299944 1060static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0 1061{
5bb16016 1062 return is_exception_n(intr_info, UD_VECTOR);
7aa81cc0
AL
1063}
1064
31299944 1065static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK
1066{
1067 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1068 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1069}
1070
31299944 1071static inline bool is_machine_check(u32 intr_info)
a0861c02
AK
1072{
1073 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1074 INTR_INFO_VALID_MASK)) ==
1075 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1076}
1077
31299944 1078static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 1079{
04547156 1080 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY
1081}
1082
31299944 1083static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 1084{
04547156 1085 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS
1086}
1087
35754c98 1088static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 1089{
35754c98 1090 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS
1091}
1092
31299944 1093static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 1094{
04547156
SY
1095 return vmcs_config.cpu_based_exec_ctrl &
1096 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY
1097}
1098
774ead3a 1099static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 1100{
04547156
SY
1101 return vmcs_config.cpu_based_2nd_exec_ctrl &
1102 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1103}
1104
8d14695f
YZ
1105static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1106{
1107 return vmcs_config.cpu_based_2nd_exec_ctrl &
1108 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1109}
1110
83d4c286
YZ
1111static inline bool cpu_has_vmx_apic_register_virt(void)
1112{
1113 return vmcs_config.cpu_based_2nd_exec_ctrl &
1114 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1115}
1116
c7c9c56c
YZ
1117static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1118{
1119 return vmcs_config.cpu_based_2nd_exec_ctrl &
1120 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1121}
1122
64672c95
YJ
1123/*
1124 * Comment's format: document - errata name - stepping - processor name.
1125 * Refer from
1126 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1127 */
1128static u32 vmx_preemption_cpu_tfms[] = {
1129/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
11300x000206E6,
1131/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1132/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1133/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
11340x00020652,
1135/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
11360x00020655,
1137/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1138/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1139/*
1140 * 320767.pdf - AAP86 - B1 -
1141 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1142 */
11430x000106E5,
1144/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
11450x000106A0,
1146/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
11470x000106A1,
1148/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
11490x000106A4,
1150 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1151 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1152 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
11530x000106A5,
1154};
1155
1156static inline bool cpu_has_broken_vmx_preemption_timer(void)
1157{
1158 u32 eax = cpuid_eax(0x00000001), i;
1159
1160 /* Clear the reserved bits */
1161 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 1162 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ
1163 if (eax == vmx_preemption_cpu_tfms[i])
1164 return true;
1165
1166 return false;
1167}
1168
1169static inline bool cpu_has_vmx_preemption_timer(void)
1170{
64672c95
YJ
1171 return vmcs_config.pin_based_exec_ctrl &
1172 PIN_BASED_VMX_PREEMPTION_TIMER;
1173}
1174
01e439be
YZ
1175static inline bool cpu_has_vmx_posted_intr(void)
1176{
d6a858d1
PB
1177 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1178 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ
1179}
1180
1181static inline bool cpu_has_vmx_apicv(void)
1182{
1183 return cpu_has_vmx_apic_register_virt() &&
1184 cpu_has_vmx_virtual_intr_delivery() &&
1185 cpu_has_vmx_posted_intr();
1186}
1187
04547156
SY
1188static inline bool cpu_has_vmx_flexpriority(void)
1189{
1190 return cpu_has_vmx_tpr_shadow() &&
1191 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY
1192}
1193
e799794e
MT
1194static inline bool cpu_has_vmx_ept_execute_only(void)
1195{
31299944 1196 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT
1197}
1198
e799794e
MT
1199static inline bool cpu_has_vmx_ept_2m_page(void)
1200{
31299944 1201 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT
1202}
1203
878403b7
SY
1204static inline bool cpu_has_vmx_ept_1g_page(void)
1205{
31299944 1206 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY
1207}
1208
4bc9b982
SY
1209static inline bool cpu_has_vmx_ept_4levels(void)
1210{
1211 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1212}
1213
83c3a331
XH
1214static inline bool cpu_has_vmx_ept_ad_bits(void)
1215{
1216 return vmx_capability.ept & VMX_EPT_AD_BIT;
1217}
1218
31299944 1219static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1220{
31299944 1221 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY
1222}
1223
31299944 1224static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1225{
31299944 1226 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY
1227}
1228
518c8aee
GJ
1229static inline bool cpu_has_vmx_invvpid_single(void)
1230{
1231 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1232}
1233
b9d762fa
GJ
1234static inline bool cpu_has_vmx_invvpid_global(void)
1235{
1236 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1237}
1238
08d839c4
WL
1239static inline bool cpu_has_vmx_invvpid(void)
1240{
1241 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1242}
1243
31299944 1244static inline bool cpu_has_vmx_ept(void)
d56f546d 1245{
04547156
SY
1246 return vmcs_config.cpu_based_2nd_exec_ctrl &
1247 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY
1248}
1249
31299944 1250static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK
1251{
1252 return vmcs_config.cpu_based_2nd_exec_ctrl &
1253 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1254}
1255
31299944 1256static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE
1257{
1258 return vmcs_config.cpu_based_2nd_exec_ctrl &
1259 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1260}
1261
9ac7e3e8
JD
1262static inline bool cpu_has_vmx_basic_inout(void)
1263{
1264 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1265}
1266
35754c98 1267static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1268{
35754c98 1269 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY
1270}
1271
31299944 1272static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1273{
04547156
SY
1274 return vmcs_config.cpu_based_2nd_exec_ctrl &
1275 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY
1276}
1277
31299944 1278static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY
1279{
1280 return vmcs_config.cpu_based_2nd_exec_ctrl &
1281 SECONDARY_EXEC_RDTSCP;
1282}
1283
ad756a16
MJ
1284static inline bool cpu_has_vmx_invpcid(void)
1285{
1286 return vmcs_config.cpu_based_2nd_exec_ctrl &
1287 SECONDARY_EXEC_ENABLE_INVPCID;
1288}
1289
f5f48ee1
SY
1290static inline bool cpu_has_vmx_wbinvd_exit(void)
1291{
1292 return vmcs_config.cpu_based_2nd_exec_ctrl &
1293 SECONDARY_EXEC_WBINVD_EXITING;
1294}
1295
abc4fc58
AG
1296static inline bool cpu_has_vmx_shadow_vmcs(void)
1297{
1298 u64 vmx_msr;
1299 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1300 /* check if the cpu supports writing r/o exit information fields */
1301 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1302 return false;
1303
1304 return vmcs_config.cpu_based_2nd_exec_ctrl &
1305 SECONDARY_EXEC_SHADOW_VMCS;
1306}
1307
843e4330
KH
1308static inline bool cpu_has_vmx_pml(void)
1309{
1310 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1311}
1312
64903d61
HZ
1313static inline bool cpu_has_vmx_tsc_scaling(void)
1314{
1315 return vmcs_config.cpu_based_2nd_exec_ctrl &
1316 SECONDARY_EXEC_TSC_SCALING;
1317}
1318
04547156
SY
1319static inline bool report_flexpriority(void)
1320{
1321 return flexpriority_enabled;
1322}
1323
c7c2c709
JM
1324static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1325{
1326 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1327}
1328
fe3ef05c
NHE
1329static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1330{
1331 return vmcs12->cpu_based_vm_exec_control & bit;
1332}
1333
1334static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1335{
1336 return (vmcs12->cpu_based_vm_exec_control &
1337 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1338 (vmcs12->secondary_vm_exec_control & bit);
1339}
1340
f5c4368f 1341static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE
1342{
1343 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1344}
1345
f4124500
JK
1346static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1347{
1348 return vmcs12->pin_based_vm_exec_control &
1349 PIN_BASED_VMX_PREEMPTION_TIMER;
1350}
1351
155a97a3
NHE
1352static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1353{
1354 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1355}
1356
81dc01f7
WL
1357static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1358{
1359 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1360 vmx_xsaves_supported();
1361}
1362
c5f983f6
BD
1363static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1364{
1365 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1366}
1367
f2b93280
WV
1368static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1369{
1370 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1371}
1372
5c614b35
WL
1373static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1374{
1375 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1376}
1377
82f0dd4b
WV
1378static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1379{
1380 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1381}
1382
608406e2
WV
1383static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1384{
1385 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1386}
1387
705699a1
WV
1388static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1389{
1390 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1391}
1392
ef85b673 1393static inline bool is_nmi(u32 intr_info)
644d711a
NHE
1394{
1395 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
ef85b673 1396 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
644d711a
NHE
1397}
1398
533558bc
JK
1399static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1400 u32 exit_intr_info,
1401 unsigned long exit_qualification);
7c177938
NHE
1402static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1403 struct vmcs12 *vmcs12,
1404 u32 reason, unsigned long qualification);
1405
8b9cf98c 1406static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK
1407{
1408 int i;
1409
a2fa3e9f 1410 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1411 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED
1412 return i;
1413 return -1;
1414}
1415
2384d2b3
SY
1416static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1417{
1418 struct {
1419 u64 vpid : 16;
1420 u64 rsvd : 48;
1421 u64 gva;
1422 } operand = { vpid, 0, gva };
1423
4ecac3fd 1424 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY
1425 /* CF==1 or ZF==1 --> rc = -1 */
1426 "; ja 1f ; ud2 ; 1:"
1427 : : "a"(&operand), "c"(ext) : "cc", "memory");
1428}
1429
1439442c
SY
1430static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1431{
1432 struct {
1433 u64 eptp, gpa;
1434 } operand = {eptp, gpa};
1435
4ecac3fd 1436 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY
1437 /* CF==1 or ZF==1 --> rc = -1 */
1438 "; ja 1f ; ud2 ; 1:\n"
1439 : : "a" (&operand), "c" (ext) : "cc", "memory");
1440}
1441
26bb0981 1442static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED
1443{
1444 int i;
1445
8b9cf98c 1446 i = __find_msr_index(vmx, msr);
a75beee6 1447 if (i >= 0)
a2fa3e9f 1448 return &vmx->guest_msrs[i];
8b6d44c7 1449 return NULL;
7725f0ba
AK
1450}
1451
6aa8b732
AK
1452static void vmcs_clear(struct vmcs *vmcs)
1453{
1454 u64 phys_addr = __pa(vmcs);
1455 u8 error;
1456
4ecac3fd 1457 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1458 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK
1459 : "cc", "memory");
1460 if (error)
1461 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1462 vmcs, phys_addr);
1463}
1464
d462b819
NHE
1465static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1466{
1467 vmcs_clear(loaded_vmcs->vmcs);
355f4fb1
JM
1468 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1469 vmcs_clear(loaded_vmcs->shadow_vmcs);
d462b819
NHE
1470 loaded_vmcs->cpu = -1;
1471 loaded_vmcs->launched = 0;
1472}
1473
7725b894
DX
1474static void vmcs_load(struct vmcs *vmcs)
1475{
1476 u64 phys_addr = __pa(vmcs);
1477 u8 error;
1478
1479 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1480 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX
1481 : "cc", "memory");
1482 if (error)
2844d849 1483 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX
1484 vmcs, phys_addr);
1485}
1486
2965faa5 1487#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY
1488/*
1489 * This bitmap is used to indicate whether the vmclear
1490 * operation is enabled on all cpus. All disabled by
1491 * default.
1492 */
1493static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1494
1495static inline void crash_enable_local_vmclear(int cpu)
1496{
1497 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1498}
1499
1500static inline void crash_disable_local_vmclear(int cpu)
1501{
1502 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1503}
1504
1505static inline int crash_local_vmclear_enabled(int cpu)
1506{
1507 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1508}
1509
1510static void crash_vmclear_local_loaded_vmcss(void)
1511{
1512 int cpu = raw_smp_processor_id();
1513 struct loaded_vmcs *v;
1514
1515 if (!crash_local_vmclear_enabled(cpu))
1516 return;
1517
1518 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1519 loaded_vmcss_on_cpu_link)
1520 vmcs_clear(v->vmcs);
1521}
1522#else
1523static inline void crash_enable_local_vmclear(int cpu) { }
1524static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1525#endif /* CONFIG_KEXEC_CORE */
8f536b76 1526
d462b819 1527static void __loaded_vmcs_clear(void *arg)
6aa8b732 1528{
d462b819 1529 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1530 int cpu = raw_smp_processor_id();
6aa8b732 1531
d462b819
NHE
1532 if (loaded_vmcs->cpu != cpu)
1533 return; /* vcpu migration can race with cpu offline */
1534 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1535 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1536 crash_disable_local_vmclear(cpu);
d462b819 1537 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG
1538
1539 /*
1540 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1541 * is before setting loaded_vmcs->vcpu to -1 which is done in
1542 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1543 * then adds the vmcs into percpu list before it is deleted.
1544 */
1545 smp_wmb();
1546
d462b819 1547 loaded_vmcs_init(loaded_vmcs);
8f536b76 1548 crash_enable_local_vmclear(cpu);
6aa8b732
AK
1549}
1550
d462b819 1551static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1552{
e6c7d321
XG
1553 int cpu = loaded_vmcs->cpu;
1554
1555 if (cpu != -1)
1556 smp_call_function_single(cpu,
1557 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK
1558}
1559
dd5f5341 1560static inline void vpid_sync_vcpu_single(int vpid)
2384d2b3 1561{
dd5f5341 1562 if (vpid == 0)
2384d2b3
SY
1563 return;
1564
518c8aee 1565 if (cpu_has_vmx_invvpid_single())
dd5f5341 1566 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
2384d2b3
SY
1567}
1568
b9d762fa
GJ
1569static inline void vpid_sync_vcpu_global(void)
1570{
1571 if (cpu_has_vmx_invvpid_global())
1572 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1573}
1574
dd5f5341 1575static inline void vpid_sync_context(int vpid)
b9d762fa
GJ
1576{
1577 if (cpu_has_vmx_invvpid_single())
dd5f5341 1578 vpid_sync_vcpu_single(vpid);
b9d762fa
GJ
1579 else
1580 vpid_sync_vcpu_global();
1581}
1582
1439442c
SY
1583static inline void ept_sync_global(void)
1584{
1585 if (cpu_has_vmx_invept_global())
1586 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1587}
1588
1589static inline void ept_sync_context(u64 eptp)
1590{
089d034e 1591 if (enable_ept) {
1439442c
SY
1592 if (cpu_has_vmx_invept_context())
1593 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1594 else
1595 ept_sync_global();
1596 }
1597}
1598
8a86aea9
PB
1599static __always_inline void vmcs_check16(unsigned long field)
1600{
1601 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1602 "16-bit accessor invalid for 64-bit field");
1603 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1604 "16-bit accessor invalid for 64-bit high field");
1605 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1606 "16-bit accessor invalid for 32-bit high field");
1607 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1608 "16-bit accessor invalid for natural width field");
1609}
1610
1611static __always_inline void vmcs_check32(unsigned long field)
1612{
1613 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1614 "32-bit accessor invalid for 16-bit field");
1615 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1616 "32-bit accessor invalid for natural width field");
1617}
1618
1619static __always_inline void vmcs_check64(unsigned long field)
1620{
1621 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1622 "64-bit accessor invalid for 16-bit field");
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1624 "64-bit accessor invalid for 64-bit high field");
1625 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1626 "64-bit accessor invalid for 32-bit field");
1627 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1628 "64-bit accessor invalid for natural width field");
1629}
1630
1631static __always_inline void vmcs_checkl(unsigned long field)
1632{
1633 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1634 "Natural width accessor invalid for 16-bit field");
1635 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1636 "Natural width accessor invalid for 64-bit field");
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1638 "Natural width accessor invalid for 64-bit high field");
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1640 "Natural width accessor invalid for 32-bit field");
1641}
1642
1643static __always_inline unsigned long __vmcs_readl(unsigned long field)
6aa8b732 1644{
5e520e62 1645 unsigned long value;
6aa8b732 1646
5e520e62
AK
1647 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1648 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK
1649 return value;
1650}
1651
96304217 1652static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732 1653{
8a86aea9
PB
1654 vmcs_check16(field);
1655 return __vmcs_readl(field);
6aa8b732
AK
1656}
1657
96304217 1658static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732 1659{
8a86aea9
PB
1660 vmcs_check32(field);
1661 return __vmcs_readl(field);
6aa8b732
AK
1662}
1663
96304217 1664static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1665{
8a86aea9 1666 vmcs_check64(field);
05b3e0c2 1667#ifdef CONFIG_X86_64
8a86aea9 1668 return __vmcs_readl(field);
6aa8b732 1669#else
8a86aea9 1670 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
6aa8b732
AK
1671#endif
1672}
1673
8a86aea9
PB
1674static __always_inline unsigned long vmcs_readl(unsigned long field)
1675{
1676 vmcs_checkl(field);
1677 return __vmcs_readl(field);
1678}
1679
e52de1b8
AK
1680static noinline void vmwrite_error(unsigned long field, unsigned long value)
1681{
1682 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1683 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1684 dump_stack();
1685}
1686
8a86aea9 1687static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
6aa8b732
AK
1688{
1689 u8 error;
1690
4ecac3fd 1691 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1692 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK
1693 if (unlikely(error))
1694 vmwrite_error(field, value);
6aa8b732
AK
1695}
1696
8a86aea9 1697static __always_inline void vmcs_write16(unsigned long field, u16 value)
6aa8b732 1698{
8a86aea9
PB
1699 vmcs_check16(field);
1700 __vmcs_writel(field, value);
6aa8b732
AK
1701}
1702
8a86aea9 1703static __always_inline void vmcs_write32(unsigned long field, u32 value)
6aa8b732 1704{
8a86aea9
PB
1705 vmcs_check32(field);
1706 __vmcs_writel(field, value);
6aa8b732
AK
1707}
1708
8a86aea9 1709static __always_inline void vmcs_write64(unsigned long field, u64 value)
6aa8b732 1710{
8a86aea9
PB
1711 vmcs_check64(field);
1712 __vmcs_writel(field, value);
7682f2d0 1713#ifndef CONFIG_X86_64
6aa8b732 1714 asm volatile ("");
8a86aea9 1715 __vmcs_writel(field+1, value >> 32);
6aa8b732
AK
1716#endif
1717}
1718
8a86aea9 1719static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2ab455cc 1720{
8a86aea9
PB
1721 vmcs_checkl(field);
1722 __vmcs_writel(field, value);
2ab455cc
AL
1723}
1724
8a86aea9 1725static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2ab455cc 1726{
8a86aea9
PB
1727 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1728 "vmcs_clear_bits does not support 64-bit fields");
1729 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2ab455cc
AL
1730}
1731
8a86aea9 1732static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2ab455cc 1733{
8a86aea9
PB
1734 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1735 "vmcs_set_bits does not support 64-bit fields");
1736 __vmcs_writel(field, __vmcs_readl(field) | mask);
2ab455cc
AL
1737}
1738
8391ce44
PB
1739static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1740{
1741 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1742}
1743
2961e876
GN
1744static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1745{
1746 vmcs_write32(VM_ENTRY_CONTROLS, val);
1747 vmx->vm_entry_controls_shadow = val;
1748}
1749
1750static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1751{
1752 if (vmx->vm_entry_controls_shadow != val)
1753 vm_entry_controls_init(vmx, val);
1754}
1755
1756static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1757{
1758 return vmx->vm_entry_controls_shadow;
1759}
1760
1761
1762static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1763{
1764 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1765}
1766
1767static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1768{
1769 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1770}
1771
8391ce44
PB
1772static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1773{
1774 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1775}
1776
2961e876
GN
1777static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1778{
1779 vmcs_write32(VM_EXIT_CONTROLS, val);
1780 vmx->vm_exit_controls_shadow = val;
1781}
1782
1783static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1784{
1785 if (vmx->vm_exit_controls_shadow != val)
1786 vm_exit_controls_init(vmx, val);
1787}
1788
1789static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1790{
1791 return vmx->vm_exit_controls_shadow;
1792}
1793
1794
1795static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1796{
1797 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1798}
1799
1800static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1801{
1802 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1803}
1804
2fb92db1
AK
1805static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1806{
1807 vmx->segment_cache.bitmask = 0;
1808}
1809
1810static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1811 unsigned field)
1812{
1813 bool ret;
1814 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1815
1816 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1817 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1818 vmx->segment_cache.bitmask = 0;
1819 }
1820 ret = vmx->segment_cache.bitmask & mask;
1821 vmx->segment_cache.bitmask |= mask;
1822 return ret;
1823}
1824
1825static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1826{
1827 u16 *p = &vmx->segment_cache.seg[seg].selector;
1828
1829 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1830 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1831 return *p;
1832}
1833
1834static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1835{
1836 ulong *p = &vmx->segment_cache.seg[seg].base;
1837
1838 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1839 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1840 return *p;
1841}
1842
1843static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1844{
1845 u32 *p = &vmx->segment_cache.seg[seg].limit;
1846
1847 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1848 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1849 return *p;
1850}
1851
1852static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1853{
1854 u32 *p = &vmx->segment_cache.seg[seg].ar;
1855
1856 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1857 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1858 return *p;
1859}
1860
abd3f2d6
AK
1861static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1862{
1863 u32 eb;
1864
fd7373cc 1865 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 1866 (1u << DB_VECTOR) | (1u << AC_VECTOR);
fd7373cc
JK
1867 if ((vcpu->guest_debug &
1868 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1869 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1870 eb |= 1u << BP_VECTOR;
7ffd92c5 1871 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1872 eb = ~0;
089d034e 1873 if (enable_ept)
1439442c 1874 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE
1875
1876 /* When we are running a nested L2 guest and L1 specified for it a
1877 * certain exception bitmap, we must trap the same exceptions and pass
1878 * them to L1. When running L2, we will only handle the exceptions
1879 * specified above if L1 did not want them.
1880 */
1881 if (is_guest_mode(vcpu))
1882 eb |= get_vmcs12(vcpu)->exception_bitmap;
1883
abd3f2d6
AK
1884 vmcs_write32(EXCEPTION_BITMAP, eb);
1885}
1886
2961e876
GN
1887static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1888 unsigned long entry, unsigned long exit)
8bf00a52 1889{
2961e876
GN
1890 vm_entry_controls_clearbit(vmx, entry);
1891 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN
1892}
1893
61d2ef2c
AK
1894static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1895{
1896 unsigned i;
1897 struct msr_autoload *m = &vmx->msr_autoload;
1898
8bf00a52
GN
1899 switch (msr) {
1900 case MSR_EFER:
1901 if (cpu_has_load_ia32_efer) {
2961e876
GN
1902 clear_atomic_switch_msr_special(vmx,
1903 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN
1904 VM_EXIT_LOAD_IA32_EFER);
1905 return;
1906 }
1907 break;
1908 case MSR_CORE_PERF_GLOBAL_CTRL:
1909 if (cpu_has_load_perf_global_ctrl) {
2961e876 1910 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN
1911 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1912 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1913 return;
1914 }
1915 break;
110312c8
AK
1916 }
1917
61d2ef2c
AK
1918 for (i = 0; i < m->nr; ++i)
1919 if (m->guest[i].index == msr)
1920 break;
1921
1922 if (i == m->nr)
1923 return;
1924 --m->nr;
1925 m->guest[i] = m->guest[m->nr];
1926 m->host[i] = m->host[m->nr];
1927 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1928 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1929}
1930
2961e876
GN
1931static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1932 unsigned long entry, unsigned long exit,
1933 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1934 u64 guest_val, u64 host_val)
8bf00a52
GN
1935{
1936 vmcs_write64(guest_val_vmcs, guest_val);
1937 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN
1938 vm_entry_controls_setbit(vmx, entry);
1939 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN
1940}
1941
61d2ef2c
AK
1942static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1943 u64 guest_val, u64 host_val)
1944{
1945 unsigned i;
1946 struct msr_autoload *m = &vmx->msr_autoload;
1947
8bf00a52
GN
1948 switch (msr) {
1949 case MSR_EFER:
1950 if (cpu_has_load_ia32_efer) {
2961e876
GN
1951 add_atomic_switch_msr_special(vmx,
1952 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN
1953 VM_EXIT_LOAD_IA32_EFER,
1954 GUEST_IA32_EFER,
1955 HOST_IA32_EFER,
1956 guest_val, host_val);
1957 return;
1958 }
1959 break;
1960 case MSR_CORE_PERF_GLOBAL_CTRL:
1961 if (cpu_has_load_perf_global_ctrl) {
2961e876 1962 add_atomic_switch_msr_special(vmx,
8bf00a52
GN
1963 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1964 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1965 GUEST_IA32_PERF_GLOBAL_CTRL,
1966 HOST_IA32_PERF_GLOBAL_CTRL,
1967 guest_val, host_val);
1968 return;
1969 }
1970 break;
7099e2e1
RK
1971 case MSR_IA32_PEBS_ENABLE:
1972 /* PEBS needs a quiescent period after being disabled (to write
1973 * a record). Disabling PEBS through VMX MSR swapping doesn't
1974 * provide that period, so a CPU could write host's record into
1975 * guest's memory.
1976 */
1977 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK
1978 }
1979
61d2ef2c
AK
1980 for (i = 0; i < m->nr; ++i)
1981 if (m->guest[i].index == msr)
1982 break;
1983
e7fc6f93 1984 if (i == NR_AUTOLOAD_MSRS) {
60266204 1985 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN
1986 "Can't add msr %x\n", msr);
1987 return;
1988 } else if (i == m->nr) {
61d2ef2c
AK
1989 ++m->nr;
1990 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1991 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1992 }
1993
1994 m->guest[i].index = msr;
1995 m->guest[i].value = guest_val;
1996 m->host[i].index = msr;
1997 m->host[i].value = host_val;
1998}
1999
92c0d900 2000static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 2001{
844a5fe2
PB
2002 u64 guest_efer = vmx->vcpu.arch.efer;
2003 u64 ignore_bits = 0;
2004
2005 if (!enable_ept) {
2006 /*
2007 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2008 * host CPUID is more efficient than testing guest CPUID
2009 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2010 */
2011 if (boot_cpu_has(X86_FEATURE_SMEP))
2012 guest_efer |= EFER_NX;
2013 else if (!(guest_efer & EFER_NX))
2014 ignore_bits |= EFER_NX;
2015 }
3a34a881 2016
51c6cf66 2017 /*
844a5fe2 2018 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 2019 */
844a5fe2 2020 ignore_bits |= EFER_SCE;
51c6cf66
AK
2021#ifdef CONFIG_X86_64
2022 ignore_bits |= EFER_LMA | EFER_LME;
2023 /* SCE is meaningful only in long mode on Intel */
2024 if (guest_efer & EFER_LMA)
2025 ignore_bits &= ~(u64)EFER_SCE;
2026#endif
84ad33ef
AK
2027
2028 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL
2029
2030 /*
2031 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2032 * On CPUs that support "load IA32_EFER", always switch EFER
2033 * atomically, since it's faster than switching it manually.
2034 */
2035 if (cpu_has_load_ia32_efer ||
2036 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK
2037 if (!(guest_efer & EFER_LMA))
2038 guest_efer &= ~EFER_LME;
54b98bff
AL
2039 if (guest_efer != host_efer)
2040 add_atomic_switch_msr(vmx, MSR_EFER,
2041 guest_efer, host_efer);
84ad33ef 2042 return false;
844a5fe2
PB
2043 } else {
2044 guest_efer &= ~ignore_bits;
2045 guest_efer |= host_efer & ignore_bits;
2046
2047 vmx->guest_msrs[efer_offset].data = guest_efer;
2048 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 2049
844a5fe2
PB
2050 return true;
2051 }
51c6cf66
AK
2052}
2053
e28baead
AL
2054#ifdef CONFIG_X86_32
2055/*
2056 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2057 * VMCS rather than the segment table. KVM uses this helper to figure
2058 * out the current bases to poke them into the VMCS before entry.
2059 */
2d49ec72
GN
2060static unsigned long segment_base(u16 selector)
2061{
8c2e41f7 2062 struct desc_struct *table;
2d49ec72
GN
2063 unsigned long v;
2064
8c2e41f7 2065 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN
2066 return 0;
2067
45fc8757 2068 table = get_current_gdt_ro();
2d49ec72 2069
8c2e41f7 2070 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN
2071 u16 ldt_selector = kvm_read_ldt();
2072
8c2e41f7 2073 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN
2074 return 0;
2075
8c2e41f7 2076 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 2077 }
8c2e41f7 2078 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN
2079 return v;
2080}
e28baead 2081#endif
2d49ec72 2082
04d2cc77 2083static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 2084{
04d2cc77 2085 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2086 int i;
04d2cc77 2087
a2fa3e9f 2088 if (vmx->host_state.loaded)
33ed6329
AK
2089 return;
2090
a2fa3e9f 2091 vmx->host_state.loaded = 1;
33ed6329
AK
2092 /*
2093 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2094 * allow segment selectors with cpl > 0 or ti == 1.
2095 */
d6e88aec 2096 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 2097 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 2098 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 2099 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 2100 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV
2101 vmx->host_state.fs_reload_needed = 0;
2102 } else {
33ed6329 2103 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 2104 vmx->host_state.fs_reload_needed = 1;
33ed6329 2105 }
9581d442 2106 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH
2107 if (!(vmx->host_state.gs_sel & 7))
2108 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK
2109 else {
2110 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 2111 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK
2112 }
2113
b2da15ac
AK
2114#ifdef CONFIG_X86_64
2115 savesegment(ds, vmx->host_state.ds_sel);
2116 savesegment(es, vmx->host_state.es_sel);
2117#endif
2118
33ed6329
AK
2119#ifdef CONFIG_X86_64
2120 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2121 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2122#else
a2fa3e9f
GH
2123 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2124 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 2125#endif
707c0874
AK
2126
2127#ifdef CONFIG_X86_64
c8770e7b
AK
2128 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2129 if (is_long_mode(&vmx->vcpu))
44ea2b17 2130 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 2131#endif
da8999d3
LJ
2132 if (boot_cpu_has(X86_FEATURE_MPX))
2133 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK
2134 for (i = 0; i < vmx->save_nmsrs; ++i)
2135 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK
2136 vmx->guest_msrs[i].data,
2137 vmx->guest_msrs[i].mask);
33ed6329
AK
2138}
2139
a9b21b62 2140static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 2141{
a2fa3e9f 2142 if (!vmx->host_state.loaded)
33ed6329
AK
2143 return;
2144
e1beb1d3 2145 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 2146 vmx->host_state.loaded = 0;
c8770e7b
AK
2147#ifdef CONFIG_X86_64
2148 if (is_long_mode(&vmx->vcpu))
2149 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2150#endif
152d3f2f 2151 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 2152 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 2153#ifdef CONFIG_X86_64
9581d442 2154 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK
2155#else
2156 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 2157#endif
33ed6329 2158 }
0a77fe4c
AK
2159 if (vmx->host_state.fs_reload_needed)
2160 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK
2161#ifdef CONFIG_X86_64
2162 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2163 loadsegment(ds, vmx->host_state.ds_sel);
2164 loadsegment(es, vmx->host_state.es_sel);
2165 }
b2da15ac 2166#endif
b7ffc44d 2167 invalidate_tss_limit();
44ea2b17 2168#ifdef CONFIG_X86_64
c8770e7b 2169 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 2170#endif
da8999d3
LJ
2171 if (vmx->host_state.msr_host_bndcfgs)
2172 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
45fc8757 2173 load_fixmap_gdt(raw_smp_processor_id());
33ed6329
AK
2174}
2175
a9b21b62
AK
2176static void vmx_load_host_state(struct vcpu_vmx *vmx)
2177{
2178 preempt_disable();
2179 __vmx_load_host_state(vmx);
2180 preempt_enable();
2181}
2182
28b835d6
FW
2183static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2184{
2185 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2186 struct pi_desc old, new;
2187 unsigned int dest;
2188
2189 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
2190 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2191 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW
2192 return;
2193
2194 do {
2195 old.control = new.control = pi_desc->control;
2196
2197 /*
2198 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2199 * are two possible cases:
2200 * 1. After running 'pre_block', context switch
2201 * happened. For this case, 'sn' was set in
2202 * vmx_vcpu_put(), so we need to clear it here.
2203 * 2. After running 'pre_block', we were blocked,
2204 * and woken up by some other guy. For this case,
2205 * we don't need to do anything, 'pi_post_block'
2206 * will do everything for us. However, we cannot
2207 * check whether it is case #1 or case #2 here
2208 * (maybe, not needed), so we also clear sn here,
2209 * I think it is not a big deal.
2210 */
2211 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2212 if (vcpu->cpu != cpu) {
2213 dest = cpu_physical_id(cpu);
2214
2215 if (x2apic_enabled())
2216 new.ndst = dest;
2217 else
2218 new.ndst = (dest << 8) & 0xFF00;
2219 }
2220
2221 /* set 'NV' to 'notification vector' */
2222 new.nv = POSTED_INTR_VECTOR;
2223 }
2224
2225 /* Allow posting non-urgent interrupts */
2226 new.sn = 0;
2227 } while (cmpxchg(&pi_desc->control, old.control,
2228 new.control) != old.control);
2229}
1be0e61c 2230
c95ba92a
PF
2231static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2232{
2233 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2234 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2235}
2236
6aa8b732
AK
2237/*
2238 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2239 * vcpu mutex is already taken.
2240 */
15ad7146 2241static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 2242{
a2fa3e9f 2243 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 2244 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 2245
b80c76ec 2246 if (!already_loaded) {
fe0e80be 2247 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 2248 local_irq_disable();
8f536b76 2249 crash_disable_local_vmclear(cpu);
5a560f8b
XG
2250
2251 /*
2252 * Read loaded_vmcs->cpu should be before fetching
2253 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2254 * See the comments in __loaded_vmcs_clear().
2255 */
2256 smp_rmb();
2257
d462b819
NHE
2258 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2259 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 2260 crash_enable_local_vmclear(cpu);
92fe13be 2261 local_irq_enable();
b80c76ec
JM
2262 }
2263
2264 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2265 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2266 vmcs_load(vmx->loaded_vmcs->vmcs);
2267 }
2268
2269 if (!already_loaded) {
59c58ceb 2270 void *gdt = get_current_gdt_ro();
b80c76ec
JM
2271 unsigned long sysenter_esp;
2272
2273 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 2274
6aa8b732
AK
2275 /*
2276 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 2277 * processors. See 22.2.4.
6aa8b732 2278 */
e0c23063
AL
2279 vmcs_writel(HOST_TR_BASE,
2280 (unsigned long)this_cpu_ptr(&cpu_tss));
59c58ceb 2281 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732 2282
b7ffc44d
AL
2283 /*
2284 * VM exits change the host TR limit to 0x67 after a VM
2285 * exit. This is okay, since 0x67 covers everything except
2286 * the IO bitmap and have have code to handle the IO bitmap
2287 * being lost after a VM exit.
2288 */
2289 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2290
6aa8b732
AK
2291 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2292 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 2293
d462b819 2294 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 2295 }
28b835d6 2296
2680d6da
OH
2297 /* Setup TSC multiplier */
2298 if (kvm_has_tsc_control &&
c95ba92a
PF
2299 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2300 decache_tsc_multiplier(vmx);
2680d6da 2301
28b835d6 2302 vmx_vcpu_pi_load(vcpu, cpu);
1be0e61c 2303 vmx->host_pkru = read_pkru();
28b835d6
FW
2304}
2305
2306static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2307{
2308 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2309
2310 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
2311 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2312 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW
2313 return;
2314
2315 /* Set SN when the vCPU is preempted */
2316 if (vcpu->preempted)
2317 pi_set_sn(pi_desc);
6aa8b732
AK
2318}
2319
2320static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2321{
28b835d6
FW
2322 vmx_vcpu_pi_put(vcpu);
2323
a9b21b62 2324 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK
2325}
2326
edcafe3c
AK
2327static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2328
fe3ef05c
NHE
2329/*
2330 * Return the cr0 value that a nested guest would read. This is a combination
2331 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2332 * its hypervisor (cr0_read_shadow).
2333 */
2334static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2335{
2336 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2337 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2338}
2339static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2340{
2341 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2342 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2343}
2344
6aa8b732
AK
2345static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2346{
78ac8b47 2347 unsigned long rflags, save_rflags;
345dcaa8 2348
6de12732
AK
2349 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2350 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2351 rflags = vmcs_readl(GUEST_RFLAGS);
2352 if (to_vmx(vcpu)->rmode.vm86_active) {
2353 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2354 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2355 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2356 }
2357 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2358 }
6de12732 2359 return to_vmx(vcpu)->rflags;
6aa8b732
AK
2360}
2361
2362static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2363{
6de12732
AK
2364 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2365 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK
2366 if (to_vmx(vcpu)->rmode.vm86_active) {
2367 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2368 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2369 }
6aa8b732
AK
2370 vmcs_writel(GUEST_RFLAGS, rflags);
2371}
2372
be94f6b7
HH
2373static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2374{
2375 return to_vmx(vcpu)->guest_pkru;
2376}
2377
37ccdcbe 2378static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC
2379{
2380 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2381 int ret = 0;
2382
2383 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2384 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2385 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2386 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2387
37ccdcbe 2388 return ret;
2809f5d2
GC
2389}
2390
2391static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2392{
2393 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2394 u32 interruptibility = interruptibility_old;
2395
2396 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2397
48005f64 2398 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2399 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2400 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC
2401 interruptibility |= GUEST_INTR_STATE_STI;
2402
2403 if ((interruptibility != interruptibility_old))
2404 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2405}
2406
6aa8b732
AK
2407static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2408{
2409 unsigned long rip;
6aa8b732 2410
5fdbf976 2411 rip = kvm_rip_read(vcpu);
6aa8b732 2412 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2413 kvm_rip_write(vcpu, rip);
6aa8b732 2414
2809f5d2
GC
2415 /* skipping an emulated instruction also counts */
2416 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK
2417}
2418
0b6ac343
NHE
2419/*
2420 * KVM wants to inject page-faults which it got to the guest. This function
2421 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2422 */
e011c663 2423static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE
2424{
2425 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2426
e011c663 2427 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE
2428 return 0;
2429
533558bc
JK
2430 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2431 vmcs_read32(VM_EXIT_INTR_INFO),
2432 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE
2433 return 1;
2434}
2435
298101da 2436static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR
2437 bool has_error_code, u32 error_code,
2438 bool reinject)
298101da 2439{
77ab6db0 2440 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2441 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2442
e011c663
GN
2443 if (!reinject && is_guest_mode(vcpu) &&
2444 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE
2445 return;
2446
8ab2d2e2 2447 if (has_error_code) {
77ab6db0 2448 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK
2449 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2450 }
77ab6db0 2451
7ffd92c5 2452 if (vmx->rmode.vm86_active) {
71f9833b
SH
2453 int inc_eip = 0;
2454 if (kvm_exception_is_soft(nr))
2455 inc_eip = vcpu->arch.event_exit_inst_len;
2456 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2457 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK
2458 return;
2459 }
2460
66fd3f7f
GN
2461 if (kvm_exception_is_soft(nr)) {
2462 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2463 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK
2464 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2465 } else
2466 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2467
2468 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK
2469}
2470
4e47c7a6
SY
2471static bool vmx_rdtscp_supported(void)
2472{
2473 return cpu_has_vmx_rdtscp();
2474}
2475
ad756a16
MJ
2476static bool vmx_invpcid_supported(void)
2477{
2478 return cpu_has_vmx_invpcid() && enable_ept;
2479}
2480
a75beee6
ED
2481/*
2482 * Swap MSR entry in host/guest MSR entry array.
2483 */
8b9cf98c 2484static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2485{
26bb0981 2486 struct shared_msr_entry tmp;
a2fa3e9f
GH
2487
2488 tmp = vmx->guest_msrs[to];
2489 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2490 vmx->guest_msrs[from] = tmp;
a75beee6
ED
2491}
2492
8d14695f
YZ
2493static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2494{
2495 unsigned long *msr_bitmap;
2496
670125bd 2497 if (is_guest_mode(vcpu))
d048c098 2498 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
3ce424e4
RK
2499 else if (cpu_has_secondary_exec_ctrls() &&
2500 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2501 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
f6e90f9e
WL
2502 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2503 if (is_long_mode(vcpu))
c63e4563 2504 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
f6e90f9e 2505 else
c63e4563 2506 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
f6e90f9e
WL
2507 } else {
2508 if (is_long_mode(vcpu))
c63e4563 2509 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
f6e90f9e 2510 else
c63e4563 2511 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
f6e90f9e 2512 }
8d14695f
YZ
2513 } else {
2514 if (is_long_mode(vcpu))
2515 msr_bitmap = vmx_msr_bitmap_longmode;
2516 else
2517 msr_bitmap = vmx_msr_bitmap_legacy;
2518 }
2519
2520 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2521}
2522
e38aea3e
AK
2523/*
2524 * Set up the vmcs to automatically save and restore system
2525 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2526 * mode, as fiddling with msrs is very expensive.
2527 */
8b9cf98c 2528static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2529{
26bb0981 2530 int save_nmsrs, index;
e38aea3e 2531
a75beee6
ED
2532 save_nmsrs = 0;
2533#ifdef CONFIG_X86_64
8b9cf98c 2534 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2535 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2536 if (index >= 0)
8b9cf98c
RR
2537 move_msr_up(vmx, index, save_nmsrs++);
2538 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2539 if (index >= 0)
8b9cf98c
RR
2540 move_msr_up(vmx, index, save_nmsrs++);
2541 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2542 if (index >= 0)
8b9cf98c 2543 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6 2544 index = __find_msr_index(vmx, MSR_TSC_AUX);
1cea0ce6 2545 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
4e47c7a6 2546 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2547 /*
8c06585d 2548 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED
2549 * if efer.sce is enabled.
2550 */
8c06585d 2551 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2552 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2553 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED
2554 }
2555#endif
92c0d900
AK
2556 index = __find_msr_index(vmx, MSR_EFER);
2557 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2558 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2559
26bb0981 2560 vmx->save_nmsrs = save_nmsrs;
5897297b 2561
8d14695f
YZ
2562 if (cpu_has_vmx_msr_bitmap())
2563 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK
2564}
2565
6aa8b732
AK
2566/*
2567 * reads and returns guest's timestamp counter "register"
be7b263e
HZ
2568 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2569 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
6aa8b732 2570 */
be7b263e 2571static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
6aa8b732
AK
2572{
2573 u64 host_tsc, tsc_offset;
2574
4ea1636b 2575 host_tsc = rdtsc();
6aa8b732 2576 tsc_offset = vmcs_read64(TSC_OFFSET);
be7b263e 2577 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
6aa8b732
AK
2578}
2579
2580/*
99e3e30a 2581 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2582 */
99e3e30a 2583static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2584{
27fc51b2 2585 if (is_guest_mode(vcpu)) {
7991825b 2586 /*
27fc51b2
NHE
2587 * We're here if L1 chose not to trap WRMSR to TSC. According
2588 * to the spec, this should set L1's TSC; The offset that L1
2589 * set for L2 remains unchanged, and still needs to be added
2590 * to the newly set TSC to get L2's TSC.
7991825b 2591 */
27fc51b2 2592 struct vmcs12 *vmcs12;
27fc51b2
NHE
2593 /* recalculate vmcs02.TSC_OFFSET: */
2594 vmcs12 = get_vmcs12(vcpu);
2595 vmcs_write64(TSC_OFFSET, offset +
2596 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2597 vmcs12->tsc_offset : 0));
2598 } else {
489223ed
YY
2599 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2600 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE
2601 vmcs_write64(TSC_OFFSET, offset);
2602 }
6aa8b732
AK
2603}
2604
801d3424
NHE
2605static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2606{
2607 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2608 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2609}
2610
2611/*
2612 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2613 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2614 * all guests if the "nested" module option is off, and can also be disabled
2615 * for a single guest by disabling its VMX cpuid bit.
2616 */
2617static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2618{
2619 return nested && guest_cpuid_has_vmx(vcpu);
2620}
2621
b87a51ae
NHE
2622/*
2623 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2624 * returned for the various VMX controls MSRs when nested VMX is enabled.
2625 * The same values should also be used to verify that vmcs12 control fields are
2626 * valid during nested entry from L1 to L2.
2627 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2628 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2629 * bit in the high half is on if the corresponding bit in the control field
2630 * may be on. See also vmx_control_verify().
b87a51ae 2631 */
b9c237bb 2632static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE
2633{
2634 /*
2635 * Note that as a general rule, the high half of the MSRs (bits in
2636 * the control fields which may be 1) should be initialized by the
2637 * intersection of the underlying hardware's MSR (i.e., features which
2638 * can be supported) and the list of features we want to expose -
2639 * because they are known to be properly supported in our code.
2640 * Also, usually, the low half of the MSRs (bits which must be 1) can
2641 * be set to 0, meaning that L1 may turn off any of these bits. The
2642 * reason is that if one of these bits is necessary, it will appear
2643 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2644 * fields of vmcs01 and vmcs02, will turn these bits off - and
2645 * nested_vmx_exit_handled() will not pass related exits to L1.
2646 * These rules have exceptions below.
2647 */
2648
2649 /* pin-based controls */
eabeaacc 2650 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV
2651 vmx->nested.nested_vmx_pinbased_ctls_low,
2652 vmx->nested.nested_vmx_pinbased_ctls_high);
2653 vmx->nested.nested_vmx_pinbased_ctls_low |=
2654 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2655 vmx->nested.nested_vmx_pinbased_ctls_high &=
2656 PIN_BASED_EXT_INTR_MASK |
2657 PIN_BASED_NMI_EXITING |
2658 PIN_BASED_VIRTUAL_NMIS;
2659 vmx->nested.nested_vmx_pinbased_ctls_high |=
2660 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2661 PIN_BASED_VMX_PREEMPTION_TIMER;
d62caabb 2662 if (kvm_vcpu_apicv_active(&vmx->vcpu))
705699a1
WV
2663 vmx->nested.nested_vmx_pinbased_ctls_high |=
2664 PIN_BASED_POSTED_INTR;
b87a51ae 2665
3dbcd8da 2666 /* exit controls */
c0dfee58 2667 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV
2668 vmx->nested.nested_vmx_exit_ctls_low,
2669 vmx->nested.nested_vmx_exit_ctls_high);
2670 vmx->nested.nested_vmx_exit_ctls_low =
2671 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2672
b9c237bb 2673 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2674#ifdef CONFIG_X86_64
c0dfee58 2675 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2676#endif
f4124500 2677 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV
2678 vmx->nested.nested_vmx_exit_ctls_high |=
2679 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2680 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD
2681 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2682
a87036ad 2683 if (kvm_mpx_supported())
b9c237bb 2684 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2685
2996fca0 2686 /* We support free control of debug control saving. */
0115f9cb 2687 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2996fca0 2688
b87a51ae
NHE
2689 /* entry controls */
2690 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV
2691 vmx->nested.nested_vmx_entry_ctls_low,
2692 vmx->nested.nested_vmx_entry_ctls_high);
2693 vmx->nested.nested_vmx_entry_ctls_low =
2694 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2695 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK
2696#ifdef CONFIG_X86_64
2697 VM_ENTRY_IA32E_MODE |
2698#endif
2699 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV
2700 vmx->nested.nested_vmx_entry_ctls_high |=
2701 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
a87036ad 2702 if (kvm_mpx_supported())
b9c237bb 2703 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2704
2996fca0 2705 /* We support free control of debug control loading. */
0115f9cb 2706 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2996fca0 2707
b87a51ae
NHE
2708 /* cpu-based controls */
2709 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV
2710 vmx->nested.nested_vmx_procbased_ctls_low,
2711 vmx->nested.nested_vmx_procbased_ctls_high);
2712 vmx->nested.nested_vmx_procbased_ctls_low =
2713 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2714 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK
2715 CPU_BASED_VIRTUAL_INTR_PENDING |
2716 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE
2717 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2718 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2719 CPU_BASED_CR3_STORE_EXITING |
2720#ifdef CONFIG_X86_64
2721 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2722#endif
2723 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD
2724 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2725 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2726 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2727 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE
2728 /*
2729 * We can allow some features even when not supported by the
2730 * hardware. For example, L1 can specify an MSR bitmap - and we
2731 * can use it to avoid exits to L1 - even when L0 runs L2
2732 * without MSR bitmaps.
2733 */
b9c237bb
WV
2734 vmx->nested.nested_vmx_procbased_ctls_high |=
2735 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2736 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2737
3dcdf3ec 2738 /* We support free control of CR3 access interception. */
0115f9cb 2739 vmx->nested.nested_vmx_procbased_ctls_low &=
3dcdf3ec
JK
2740 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2741
b87a51ae
NHE
2742 /* secondary cpu-based controls */
2743 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV
2744 vmx->nested.nested_vmx_secondary_ctls_low,
2745 vmx->nested.nested_vmx_secondary_ctls_high);
2746 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2747 vmx->nested.nested_vmx_secondary_ctls_high &=
a5f46457 2748 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
d6851fbe 2749 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2750 SECONDARY_EXEC_RDTSCP |
1b07304c 2751 SECONDARY_EXEC_DESC |
f2b93280 2752 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2753 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2754 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7 2755 SECONDARY_EXEC_WBINVD_EXITING |
dfa169bb 2756 SECONDARY_EXEC_XSAVES;
c18911a2 2757
afa61f75
NHE
2758 if (enable_ept) {
2759 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2760 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2761 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2762 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
7db74265 2763 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
02120c45
BD
2764 if (cpu_has_vmx_ept_execute_only())
2765 vmx->nested.nested_vmx_ept_caps |=
2766 VMX_EPT_EXECUTE_ONLY_BIT;
b9c237bb 2767 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
45e11817 2768 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
7db74265
PB
2769 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2770 VMX_EPT_1GB_PAGE_BIT;
03efce6f
BD
2771 if (enable_ept_ad_bits) {
2772 vmx->nested.nested_vmx_secondary_ctls_high |=
2773 SECONDARY_EXEC_ENABLE_PML;
ae1e2d10 2774 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
03efce6f 2775 }
afa61f75 2776 } else
b9c237bb 2777 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2778
ef697a71
PB
2779 /*
2780 * Old versions of KVM use the single-context version without
2781 * checking for support, so declare that it is supported even
2782 * though it is treated as global context. The alternative is
2783 * not failing the single-context invvpid, and it is worse.
2784 */
63cb6d5f
WL
2785 if (enable_vpid) {
2786 vmx->nested.nested_vmx_secondary_ctls_high |=
2787 SECONDARY_EXEC_ENABLE_VPID;
089d7b6e 2788 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
bcdde302 2789 VMX_VPID_EXTENT_SUPPORTED_MASK;
63cb6d5f 2790 } else
089d7b6e 2791 vmx->nested.nested_vmx_vpid_caps = 0;
99b83ac8 2792
0790ec17
RK
2793 if (enable_unrestricted_guest)
2794 vmx->nested.nested_vmx_secondary_ctls_high |=
2795 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2796
c18911a2 2797 /* miscellaneous data */
b9c237bb
WV
2798 rdmsr(MSR_IA32_VMX_MISC,
2799 vmx->nested.nested_vmx_misc_low,
2800 vmx->nested.nested_vmx_misc_high);
2801 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2802 vmx->nested.nested_vmx_misc_low |=
2803 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2804 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2805 vmx->nested.nested_vmx_misc_high = 0;
62cc6b9d
DM
2806
2807 /*
2808 * This MSR reports some information about VMX support. We
2809 * should return information about the VMX we emulate for the
2810 * guest, and the VMCS structure we give it - not about the
2811 * VMX support of the underlying hardware.
2812 */
2813 vmx->nested.nested_vmx_basic =
2814 VMCS12_REVISION |
2815 VMX_BASIC_TRUE_CTLS |
2816 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2817 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2818
2819 if (cpu_has_vmx_basic_inout())
2820 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2821
2822 /*
8322ebbb 2823 * These MSRs specify bits which the guest must keep fixed on
62cc6b9d
DM
2824 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2825 * We picked the standard core2 setting.
2826 */
2827#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2828#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2829 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
62cc6b9d 2830 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
8322ebbb
DM
2831
2832 /* These MSRs specify bits which the guest must keep fixed off. */
2833 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2834 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
62cc6b9d
DM
2835
2836 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2837 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
b87a51ae
NHE
2838}
2839
3899152c
DM
2840/*
2841 * if fixed0[i] == 1: val[i] must be 1
2842 * if fixed1[i] == 0: val[i] must be 0
2843 */
2844static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2845{
2846 return ((val & fixed1) | fixed0) == val;
b87a51ae
NHE
2847}
2848
2849static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2850{
3899152c 2851 return fixed_bits_valid(control, low, high);
b87a51ae
NHE
2852}
2853
2854static inline u64 vmx_control_msr(u32 low, u32 high)
2855{
2856 return low | ((u64)high << 32);
2857}
2858
62cc6b9d
DM
2859static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2860{
2861 superset &= mask;
2862 subset &= mask;
2863
2864 return (superset | subset) == superset;
2865}
2866
2867static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2868{
2869 const u64 feature_and_reserved =
2870 /* feature (except bit 48; see below) */
2871 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2872 /* reserved */
2873 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2874 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2875
2876 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2877 return -EINVAL;
2878
2879 /*
2880 * KVM does not emulate a version of VMX that constrains physical
2881 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2882 */
2883 if (data & BIT_ULL(48))
2884 return -EINVAL;
2885
2886 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2887 vmx_basic_vmcs_revision_id(data))
2888 return -EINVAL;
2889
2890 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2891 return -EINVAL;
2892
2893 vmx->nested.nested_vmx_basic = data;
2894 return 0;
2895}
2896
2897static int
2898vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2899{
2900 u64 supported;
2901 u32 *lowp, *highp;
2902
2903 switch (msr_index) {
2904 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2905 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2906 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2907 break;
2908 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2909 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2910 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2911 break;
2912 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2913 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2914 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2915 break;
2916 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2917 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2918 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2919 break;
2920 case MSR_IA32_VMX_PROCBASED_CTLS2:
2921 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2922 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2923 break;
2924 default:
2925 BUG();
2926 }
2927
2928 supported = vmx_control_msr(*lowp, *highp);
2929
2930 /* Check must-be-1 bits are still 1. */
2931 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2932 return -EINVAL;
2933
2934 /* Check must-be-0 bits are still 0. */
2935 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2936 return -EINVAL;
2937
2938 *lowp = data;
2939 *highp = data >> 32;
2940 return 0;
2941}
2942
2943static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2944{
2945 const u64 feature_and_reserved_bits =
2946 /* feature */
2947 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2948 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2949 /* reserved */
2950 GENMASK_ULL(13, 9) | BIT_ULL(31);
2951 u64 vmx_misc;
2952
2953 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2954 vmx->nested.nested_vmx_misc_high);
2955
2956 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2957 return -EINVAL;
2958
2959 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2960 PIN_BASED_VMX_PREEMPTION_TIMER) &&
2961 vmx_misc_preemption_timer_rate(data) !=
2962 vmx_misc_preemption_timer_rate(vmx_misc))
2963 return -EINVAL;
2964
2965 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2966 return -EINVAL;
2967
2968 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2969 return -EINVAL;
2970
2971 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2972 return -EINVAL;
2973
2974 vmx->nested.nested_vmx_misc_low = data;
2975 vmx->nested.nested_vmx_misc_high = data >> 32;
2976 return 0;
2977}
2978
2979static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2980{
2981 u64 vmx_ept_vpid_cap;
2982
2983 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2984 vmx->nested.nested_vmx_vpid_caps);
2985
2986 /* Every bit is either reserved or a feature bit. */
2987 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2988 return -EINVAL;
2989
2990 vmx->nested.nested_vmx_ept_caps = data;
2991 vmx->nested.nested_vmx_vpid_caps = data >> 32;
2992 return 0;
2993}
2994
2995static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2996{
2997 u64 *msr;
2998
2999 switch (msr_index) {
3000 case MSR_IA32_VMX_CR0_FIXED0:
3001 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3002 break;
3003 case MSR_IA32_VMX_CR4_FIXED0:
3004 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3005 break;
3006 default:
3007 BUG();
3008 }
3009
3010 /*
3011 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3012 * must be 1 in the restored value.
3013 */
3014 if (!is_bitwise_subset(data, *msr, -1ULL))
3015 return -EINVAL;
3016
3017 *msr = data;
3018 return 0;
3019}
3020
3021/*
3022 * Called when userspace is restoring VMX MSRs.
3023 *
3024 * Returns 0 on success, non-0 otherwise.
3025 */
3026static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
b87a51ae 3027{
b9c237bb
WV
3028 struct vcpu_vmx *vmx = to_vmx(vcpu);
3029
b87a51ae 3030 switch (msr_index) {
b87a51ae 3031 case MSR_IA32_VMX_BASIC:
62cc6b9d
DM
3032 return vmx_restore_vmx_basic(vmx, data);
3033 case MSR_IA32_VMX_PINBASED_CTLS:
3034 case MSR_IA32_VMX_PROCBASED_CTLS:
3035 case MSR_IA32_VMX_EXIT_CTLS:
3036 case MSR_IA32_VMX_ENTRY_CTLS:
b87a51ae 3037 /*
62cc6b9d
DM
3038 * The "non-true" VMX capability MSRs are generated from the
3039 * "true" MSRs, so we do not support restoring them directly.
3040 *
3041 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3042 * should restore the "true" MSRs with the must-be-1 bits
3043 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3044 * DEFAULT SETTINGS".
b87a51ae 3045 */
62cc6b9d
DM
3046 return -EINVAL;
3047 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3048 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3049 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3050 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3051 case MSR_IA32_VMX_PROCBASED_CTLS2:
3052 return vmx_restore_control_msr(vmx, msr_index, data);
3053 case MSR_IA32_VMX_MISC:
3054 return vmx_restore_vmx_misc(vmx, data);
3055 case MSR_IA32_VMX_CR0_FIXED0:
3056 case MSR_IA32_VMX_CR4_FIXED0:
3057 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3058 case MSR_IA32_VMX_CR0_FIXED1:
3059 case MSR_IA32_VMX_CR4_FIXED1:
3060 /*
3061 * These MSRs are generated based on the vCPU's CPUID, so we
3062 * do not support restoring them directly.
3063 */
3064 return -EINVAL;
3065 case MSR_IA32_VMX_EPT_VPID_CAP:
3066 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3067 case MSR_IA32_VMX_VMCS_ENUM:
3068 vmx->nested.nested_vmx_vmcs_enum = data;
3069 return 0;
3070 default:
b87a51ae 3071 /*
62cc6b9d 3072 * The rest of the VMX capability MSRs do not support restore.
b87a51ae 3073 */
62cc6b9d
DM
3074 return -EINVAL;
3075 }
3076}
3077
3078/* Returns 0 on success, non-0 otherwise. */
3079static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3080{
3081 struct vcpu_vmx *vmx = to_vmx(vcpu);
3082
3083 switch (msr_index) {
3084 case MSR_IA32_VMX_BASIC:
3085 *pdata = vmx->nested.nested_vmx_basic;
b87a51ae
NHE
3086 break;
3087 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3088 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV
3089 *pdata = vmx_control_msr(
3090 vmx->nested.nested_vmx_pinbased_ctls_low,
3091 vmx->nested.nested_vmx_pinbased_ctls_high);
0115f9cb
DM
3092 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3093 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3094 break;
3095 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3096 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV
3097 *pdata = vmx_control_msr(
3098 vmx->nested.nested_vmx_procbased_ctls_low,
3099 vmx->nested.nested_vmx_procbased_ctls_high);
0115f9cb
DM
3100 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3101 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3102 break;
3103 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3104 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV
3105 *pdata = vmx_control_msr(
3106 vmx->nested.nested_vmx_exit_ctls_low,
3107 vmx->nested.nested_vmx_exit_ctls_high);
0115f9cb
DM
3108 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3109 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3110 break;
3111 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3112 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV
3113 *pdata = vmx_control_msr(
3114 vmx->nested.nested_vmx_entry_ctls_low,
3115 vmx->nested.nested_vmx_entry_ctls_high);
0115f9cb
DM
3116 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3117 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3118 break;
3119 case MSR_IA32_VMX_MISC:
b9c237bb
WV
3120 *pdata = vmx_control_msr(
3121 vmx->nested.nested_vmx_misc_low,
3122 vmx->nested.nested_vmx_misc_high);
b87a51ae 3123 break;
b87a51ae 3124 case MSR_IA32_VMX_CR0_FIXED0:
62cc6b9d 3125 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
b87a51ae
NHE
3126 break;
3127 case MSR_IA32_VMX_CR0_FIXED1:
62cc6b9d 3128 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
b87a51ae
NHE
3129 break;
3130 case MSR_IA32_VMX_CR4_FIXED0:
62cc6b9d 3131 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
b87a51ae
NHE
3132 break;
3133 case MSR_IA32_VMX_CR4_FIXED1:
62cc6b9d 3134 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
b87a51ae
NHE
3135 break;
3136 case MSR_IA32_VMX_VMCS_ENUM:
62cc6b9d 3137 *pdata = vmx->nested.nested_vmx_vmcs_enum;
b87a51ae
NHE
3138 break;
3139 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV
3140 *pdata = vmx_control_msr(
3141 vmx->nested.nested_vmx_secondary_ctls_low,
3142 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE
3143 break;
3144 case MSR_IA32_VMX_EPT_VPID_CAP:
089d7b6e
WL
3145 *pdata = vmx->nested.nested_vmx_ept_caps |
3146 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
b87a51ae
NHE
3147 break;
3148 default:
b87a51ae 3149 return 1;
b3897a49
NHE
3150 }
3151
b87a51ae
NHE
3152 return 0;
3153}
3154
37e4c997
HZ
3155static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3156 uint64_t val)
3157{
3158 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3159
3160 return !(val & ~valid_bits);
3161}
3162
6aa8b732
AK
3163/*
3164 * Reads an msr value (of 'msr_index') into 'pdata'.
3165 * Returns 0 on success, non-0 otherwise.
3166 * Assumes vcpu_load() was already called.
3167 */
609e36d3 3168static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 3169{
26bb0981 3170 struct shared_msr_entry *msr;
6aa8b732 3171
609e36d3 3172 switch (msr_info->index) {
05b3e0c2 3173#ifdef CONFIG_X86_64
6aa8b732 3174 case MSR_FS_BASE:
609e36d3 3175 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK
3176 break;
3177 case MSR_GS_BASE:
609e36d3 3178 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 3179 break;
44ea2b17
AK
3180 case MSR_KERNEL_GS_BASE:
3181 vmx_load_host_state(to_vmx(vcpu));
609e36d3 3182 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 3183 break;
26bb0981 3184#endif
6aa8b732 3185 case MSR_EFER:
609e36d3 3186 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 3187 case MSR_IA32_TSC:
be7b263e 3188 msr_info->data = guest_read_tsc(vcpu);
6aa8b732
AK
3189 break;
3190 case MSR_IA32_SYSENTER_CS:
609e36d3 3191 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK
3192 break;
3193 case MSR_IA32_SYSENTER_EIP:
609e36d3 3194 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK
3195 break;
3196 case MSR_IA32_SYSENTER_ESP:
609e36d3 3197 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 3198 break;
0dd376e7 3199 case MSR_IA32_BNDCFGS:
a87036ad 3200 if (!kvm_mpx_supported())
93c4adc7 3201 return 1;
609e36d3 3202 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 3203 break;
c45dcc71
AR
3204 case MSR_IA32_MCG_EXT_CTL:
3205 if (!msr_info->host_initiated &&
3206 !(to_vmx(vcpu)->msr_ia32_feature_control &
3207 FEATURE_CONTROL_LMCE))
cae50139 3208 return 1;
c45dcc71
AR
3209 msr_info->data = vcpu->arch.mcg_ext_ctl;
3210 break;
cae50139 3211 case MSR_IA32_FEATURE_CONTROL:
3b84080b 3212 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
cae50139
JK
3213 break;
3214 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3215 if (!nested_vmx_allowed(vcpu))
3216 return 1;
609e36d3 3217 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL
3218 case MSR_IA32_XSS:
3219 if (!vmx_xsaves_supported())
3220 return 1;
609e36d3 3221 msr_info->data = vcpu->arch.ia32_xss;
20300099 3222 break;
4e47c7a6 3223 case MSR_TSC_AUX:
81b1b9ca 3224 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
4e47c7a6
SY
3225 return 1;
3226 /* Otherwise falls through */
6aa8b732 3227 default:
609e36d3 3228 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 3229 if (msr) {
609e36d3 3230 msr_info->data = msr->data;
3bab1f5d 3231 break;
6aa8b732 3232 }
609e36d3 3233 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK
3234 }
3235
6aa8b732
AK
3236 return 0;
3237}
3238
cae50139
JK
3239static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3240
6aa8b732
AK
3241/*
3242 * Writes msr value into into the appropriate "register".
3243 * Returns 0 on success, non-0 otherwise.
3244 * Assumes vcpu_load() was already called.
3245 */
8fe8ab46 3246static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 3247{
a2fa3e9f 3248 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 3249 struct shared_msr_entry *msr;
2cc51560 3250 int ret = 0;
8fe8ab46
WA
3251 u32 msr_index = msr_info->index;
3252 u64 data = msr_info->data;
2cc51560 3253
6aa8b732 3254 switch (msr_index) {
3bab1f5d 3255 case MSR_EFER:
8fe8ab46 3256 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 3257 break;
16175a79 3258#ifdef CONFIG_X86_64
6aa8b732 3259 case MSR_FS_BASE:
2fb92db1 3260 vmx_segment_cache_clear(vmx);
6aa8b732
AK
3261 vmcs_writel(GUEST_FS_BASE, data);
3262 break;
3263 case MSR_GS_BASE:
2fb92db1 3264 vmx_segment_cache_clear(vmx);
6aa8b732
AK
3265 vmcs_writel(GUEST_GS_BASE, data);
3266 break;
44ea2b17
AK
3267 case MSR_KERNEL_GS_BASE:
3268 vmx_load_host_state(vmx);
3269 vmx->msr_guest_kernel_gs_base = data;
3270 break;
6aa8b732
AK
3271#endif
3272 case MSR_IA32_SYSENTER_CS:
3273 vmcs_write32(GUEST_SYSENTER_CS, data);
3274 break;
3275 case MSR_IA32_SYSENTER_EIP:
f5b42c33 3276 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK
3277 break;
3278 case MSR_IA32_SYSENTER_ESP:
f5b42c33 3279 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 3280 break;
0dd376e7 3281 case MSR_IA32_BNDCFGS:
a87036ad 3282 if (!kvm_mpx_supported())
93c4adc7 3283 return 1;
0dd376e7
LJ
3284 vmcs_write64(GUEST_BNDCFGS, data);
3285 break;
af24a4e4 3286 case MSR_IA32_TSC:
8fe8ab46 3287 kvm_write_tsc(vcpu, msr_info);
6aa8b732 3288 break;
468d472f
SY
3289 case MSR_IA32_CR_PAT:
3290 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA
3291 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3292 return 1;
468d472f
SY
3293 vmcs_write64(GUEST_IA32_PAT, data);
3294 vcpu->arch.pat = data;
3295 break;
3296 }
8fe8ab46 3297 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 3298 break;
ba904635
WA
3299 case MSR_IA32_TSC_ADJUST:
3300 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 3301 break;
c45dcc71
AR
3302 case MSR_IA32_MCG_EXT_CTL:
3303 if ((!msr_info->host_initiated &&
3304 !(to_vmx(vcpu)->msr_ia32_feature_control &
3305 FEATURE_CONTROL_LMCE)) ||
3306 (data & ~MCG_EXT_CTL_LMCE_EN))
3307 return 1;
3308 vcpu->arch.mcg_ext_ctl = data;
3309 break;
cae50139 3310 case MSR_IA32_FEATURE_CONTROL:
37e4c997 3311 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 3312 (to_vmx(vcpu)->msr_ia32_feature_control &
cae50139
JK
3313 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3314 return 1;
3b84080b 3315 vmx->msr_ia32_feature_control = data;
cae50139
JK
3316 if (msr_info->host_initiated && data == 0)
3317 vmx_leave_nested(vcpu);
3318 break;
3319 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM
3320 if (!msr_info->host_initiated)
3321 return 1; /* they are read-only */
3322 if (!nested_vmx_allowed(vcpu))
3323 return 1;
3324 return vmx_set_vmx_msr(vcpu, msr_index, data);
20300099
WL
3325 case MSR_IA32_XSS:
3326 if (!vmx_xsaves_supported())
3327 return 1;
3328 /*
3329 * The only supported bit as of Skylake is bit 8, but
3330 * it is not supported on KVM.
3331 */
3332 if (data != 0)
3333 return 1;
3334 vcpu->arch.ia32_xss = data;
3335 if (vcpu->arch.ia32_xss != host_xss)
3336 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3337 vcpu->arch.ia32_xss, host_xss);
3338 else
3339 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3340 break;
4e47c7a6 3341 case MSR_TSC_AUX:
81b1b9ca 3342 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
4e47c7a6
SY
3343 return 1;
3344 /* Check reserved bit, higher 32 bits should be zero */
3345 if ((data >> 32) != 0)
3346 return 1;
3347 /* Otherwise falls through */
6aa8b732 3348 default:
8b9cf98c 3349 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 3350 if (msr) {
8b3c3104 3351 u64 old_msr_data = msr->data;
3bab1f5d 3352 msr->data = data;
2225fd56
AK
3353 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3354 preempt_disable();
8b3c3104
AH
3355 ret = kvm_set_shared_msr(msr->index, msr->data,
3356 msr->mask);
2225fd56 3357 preempt_enable();
8b3c3104
AH
3358 if (ret)
3359 msr->data = old_msr_data;
2225fd56 3360 }
3bab1f5d 3361 break;
6aa8b732 3362 }
8fe8ab46 3363 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK
3364 }
3365
2cc51560 3366 return ret;
6aa8b732
AK
3367}
3368
5fdbf976 3369static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 3370{
5fdbf976
MT
3371 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3372 switch (reg) {
3373 case VCPU_REGS_RSP:
3374 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3375 break;
3376 case VCPU_REGS_RIP:
3377 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3378 break;
6de4f3ad
AK
3379 case VCPU_EXREG_PDPTR:
3380 if (enable_ept)
3381 ept_save_pdptrs(vcpu);
3382 break;
5fdbf976
MT
3383 default:
3384 break;
3385 }
6aa8b732
AK
3386}
3387
6aa8b732
AK
3388static __init int cpu_has_kvm_support(void)
3389{
6210e37b 3390 return cpu_has_vmx();
6aa8b732
AK
3391}
3392
3393static __init int vmx_disabled_by_bios(void)
3394{
3395 u64 msr;
3396
3397 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 3398 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 3399 /* launched w/ TXT and VMX disabled */
cafd6659
SW
3400 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3401 && tboot_enabled())
3402 return 1;
23f3e991 3403 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 3404 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 3405 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW
3406 && !tboot_enabled()) {
3407 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 3408 "activate TXT before enabling KVM\n");
cafd6659 3409 return 1;
f9335afe 3410 }
23f3e991
JC
3411 /* launched w/o TXT and VMX disabled */
3412 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3413 && !tboot_enabled())
3414 return 1;
cafd6659
SW
3415 }
3416
3417 return 0;
6aa8b732
AK
3418}
3419
7725b894
DX
3420static void kvm_cpu_vmxon(u64 addr)
3421{
fe0e80be 3422 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS
3423 intel_pt_handle_vmx(1);
3424
7725b894
DX
3425 asm volatile (ASM_VMX_VMXON_RAX
3426 : : "a"(&addr), "m"(addr)
3427 : "memory", "cc");
3428}
3429
13a34e06 3430static int hardware_enable(void)
6aa8b732
AK
3431{
3432 int cpu = raw_smp_processor_id();
3433 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 3434 u64 old, test_bits;
6aa8b732 3435
1e02ce4c 3436 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG
3437 return -EBUSY;
3438
d462b819 3439 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW
3440 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3441 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY
3442
3443 /*
3444 * Now we can enable the vmclear operation in kdump
3445 * since the loaded_vmcss_on_cpu list on this cpu
3446 * has been initialized.
3447 *
3448 * Though the cpu is not in VMX operation now, there
3449 * is no problem to enable the vmclear operation
3450 * for the loaded_vmcss_on_cpu list is empty!
3451 */
3452 crash_enable_local_vmclear(cpu);
3453
6aa8b732 3454 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW
3455
3456 test_bits = FEATURE_CONTROL_LOCKED;
3457 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3458 if (tboot_enabled())
3459 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3460
3461 if ((old & test_bits) != test_bits) {
6aa8b732 3462 /* enable and lock */
cafd6659
SW
3463 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3464 }
fe0e80be
DH
3465 kvm_cpu_vmxon(phys_addr);
3466 ept_sync_global();
10474ae8
AG
3467
3468 return 0;
6aa8b732
AK
3469}
3470
d462b819 3471static void vmclear_local_loaded_vmcss(void)
543e4243
AK
3472{
3473 int cpu = raw_smp_processor_id();
d462b819 3474 struct loaded_vmcs *v, *n;
543e4243 3475
d462b819
NHE
3476 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3477 loaded_vmcss_on_cpu_link)
3478 __loaded_vmcs_clear(v);
543e4243
AK
3479}
3480
710ff4a8
EH
3481
3482/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3483 * tricks.
3484 */
3485static void kvm_cpu_vmxoff(void)
6aa8b732 3486{
4ecac3fd 3487 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1c5ac21a
AS
3488
3489 intel_pt_handle_vmx(0);
fe0e80be 3490 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK
3491}
3492
13a34e06 3493static void hardware_disable(void)
710ff4a8 3494{
fe0e80be
DH
3495 vmclear_local_loaded_vmcss();
3496 kvm_cpu_vmxoff();
710ff4a8
EH
3497}
3498
1c3d14fe 3499static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 3500 u32 msr, u32 *result)
1c3d14fe
YS
3501{
3502 u32 vmx_msr_low, vmx_msr_high;
3503 u32 ctl = ctl_min | ctl_opt;
3504
3505 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3506
3507 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3508 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3509
3510 /* Ensure minimum (required) set of control bits are supported. */
3511 if (ctl_min & ~ctl)
002c7f7c 3512 return -EIO;
1c3d14fe
YS
3513
3514 *result = ctl;
3515 return 0;
3516}
3517
110312c8
AK
3518static __init bool allow_1_setting(u32 msr, u32 ctl)
3519{
3520 u32 vmx_msr_low, vmx_msr_high;
3521
3522 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3523 return vmx_msr_high & ctl;
3524}
3525
002c7f7c 3526static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK
3527{
3528 u32 vmx_msr_low, vmx_msr_high;
d56f546d 3529 u32 min, opt, min2, opt2;
1c3d14fe
YS
3530 u32 _pin_based_exec_control = 0;
3531 u32 _cpu_based_exec_control = 0;
f78e0e2e 3532 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS
3533 u32 _vmexit_control = 0;
3534 u32 _vmentry_control = 0;
3535
10166744 3536 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS
3537#ifdef CONFIG_X86_64
3538 CPU_BASED_CR8_LOAD_EXITING |
3539 CPU_BASED_CR8_STORE_EXITING |
3540#endif
d56f546d
SY
3541 CPU_BASED_CR3_LOAD_EXITING |
3542 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS
3543 CPU_BASED_USE_IO_BITMAPS |
3544 CPU_BASED_MOV_DR_EXITING |
a7052897 3545 CPU_BASED_USE_TSC_OFFSETING |
fee84b07
AK
3546 CPU_BASED_INVLPG_EXITING |
3547 CPU_BASED_RDPMC_EXITING;
443381a8 3548
668fffa3
MT
3549 if (!kvm_mwait_in_guest())
3550 min |= CPU_BASED_MWAIT_EXITING |
3551 CPU_BASED_MONITOR_EXITING;
3552
f78e0e2e 3553 opt = CPU_BASED_TPR_SHADOW |
25c5f225 3554 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 3555 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS
3556 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3557 &_cpu_based_exec_control) < 0)
002c7f7c 3558 return -EIO;
6e5d865c
YS
3559#ifdef CONFIG_X86_64
3560 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3561 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3562 ~CPU_BASED_CR8_STORE_EXITING;
3563#endif
f78e0e2e 3564 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY
3565 min2 = 0;
3566 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3567 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3568 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3569 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3570 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3571 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3572 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3573 SECONDARY_EXEC_RDTSCP |
83d4c286 3574 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3575 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3576 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3577 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 3578 SECONDARY_EXEC_XSAVES |
8b3e34e4 3579 SECONDARY_EXEC_ENABLE_PML |
64903d61 3580 SECONDARY_EXEC_TSC_SCALING;
d56f546d
SY
3581 if (adjust_vmx_controls(min2, opt2,
3582 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY
3583 &_cpu_based_2nd_exec_control) < 0)
3584 return -EIO;
3585 }
3586#ifndef CONFIG_X86_64
3587 if (!(_cpu_based_2nd_exec_control &
3588 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3589 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3590#endif
83d4c286
YZ
3591
3592 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3593 _cpu_based_2nd_exec_control &= ~(
8d14695f 3594 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ
3595 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3596 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3597
d56f546d 3598 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT
3599 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3600 enabled */
5fff7d27
GN
3601 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3602 CPU_BASED_CR3_STORE_EXITING |
3603 CPU_BASED_INVLPG_EXITING);
d56f546d
SY
3604 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3605 vmx_capability.ept, vmx_capability.vpid);
3606 }
1c3d14fe 3607
91fa0f8e 3608 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS
3609#ifdef CONFIG_X86_64
3610 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3611#endif
a547c6db 3612 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
91fa0f8e 3613 VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS
3614 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3615 &_vmexit_control) < 0)
002c7f7c 3616 return -EIO;
1c3d14fe 3617
2c82878b
PB
3618 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3619 PIN_BASED_VIRTUAL_NMIS;
3620 opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ
3621 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3622 &_pin_based_exec_control) < 0)
3623 return -EIO;
3624
1c17c3e6
PB
3625 if (cpu_has_broken_vmx_preemption_timer())
3626 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 3627 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 3628 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ
3629 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3630
c845f9c6 3631 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3632 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS
3633 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3634 &_vmentry_control) < 0)
002c7f7c 3635 return -EIO;
6aa8b732 3636
c68876fd 3637 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS
3638
3639 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3640 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3641 return -EIO;
1c3d14fe
YS
3642
3643#ifdef CONFIG_X86_64
3644 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3645 if (vmx_msr_high & (1u<<16))
002c7f7c 3646 return -EIO;
1c3d14fe
YS
3647#endif
3648
3649 /* Require Write-Back (WB) memory type for VMCS accesses. */
3650 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3651 return -EIO;
1c3d14fe 3652
002c7f7c 3653 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 3654 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 3655 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
002c7f7c 3656 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3657
002c7f7c
YS
3658 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3659 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3660 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS
3661 vmcs_conf->vmexit_ctrl = _vmexit_control;
3662 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3663
110312c8
AK
3664 cpu_has_load_ia32_efer =
3665 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3666 VM_ENTRY_LOAD_IA32_EFER)
3667 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3668 VM_EXIT_LOAD_IA32_EFER);
3669
8bf00a52
GN
3670 cpu_has_load_perf_global_ctrl =
3671 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3672 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3673 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3674 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3675
3676 /*
3677 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
bb3541f1 3678 * but due to errata below it can't be used. Workaround is to use
8bf00a52
GN
3679 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3680 *
3681 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3682 *
3683 * AAK155 (model 26)
3684 * AAP115 (model 30)
3685 * AAT100 (model 37)
3686 * BC86,AAY89,BD102 (model 44)
3687 * BA97 (model 46)
3688 *
3689 */
3690 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3691 switch (boot_cpu_data.x86_model) {
3692 case 26:
3693 case 30:
3694 case 37:
3695 case 44:
3696 case 46:
3697 cpu_has_load_perf_global_ctrl = false;
3698 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3699 "does not work properly. Using workaround\n");
3700 break;
3701 default:
3702 break;
3703 }
3704 }
3705
782511b0 3706 if (boot_cpu_has(X86_FEATURE_XSAVES))
20300099
WL
3707 rdmsrl(MSR_IA32_XSS, host_xss);
3708
1c3d14fe 3709 return 0;
c68876fd 3710}
6aa8b732
AK
3711
3712static struct vmcs *alloc_vmcs_cpu(int cpu)
3713{
3714 int node = cpu_to_node(cpu);
3715 struct page *pages;
3716 struct vmcs *vmcs;
3717
96db800f 3718 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK
3719 if (!pages)
3720 return NULL;
3721 vmcs = page_address(pages);
1c3d14fe
YS
3722 memset(vmcs, 0, vmcs_config.size);
3723 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK
3724 return vmcs;
3725}
3726
3727static struct vmcs *alloc_vmcs(void)
3728{
d3b2c338 3729 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK
3730}
3731
3732static void free_vmcs(struct vmcs *vmcs)
3733{
1c3d14fe 3734 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK
3735}
3736
d462b819
NHE
3737/*
3738 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3739 */
3740static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3741{
3742 if (!loaded_vmcs->vmcs)
3743 return;
3744 loaded_vmcs_clear(loaded_vmcs);
3745 free_vmcs(loaded_vmcs->vmcs);
3746 loaded_vmcs->vmcs = NULL;
355f4fb1 3747 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE
3748}
3749
39959588 3750static void free_kvm_area(void)
6aa8b732
AK
3751{
3752 int cpu;
3753
3230bb47 3754 for_each_possible_cpu(cpu) {
6aa8b732 3755 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA
3756 per_cpu(vmxarea, cpu) = NULL;
3757 }
6aa8b732
AK
3758}
3759
fe2b201b
BD
3760static void init_vmcs_shadow_fields(void)
3761{
3762 int i, j;
3763
3764 /* No checks for read only fields yet */
3765
3766 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3767 switch (shadow_read_write_fields[i]) {
3768 case GUEST_BNDCFGS:
a87036ad 3769 if (!kvm_mpx_supported())
fe2b201b
BD
3770 continue;
3771 break;
3772 default:
3773 break;
3774 }
3775
3776 if (j < i)
3777 shadow_read_write_fields[j] =
3778 shadow_read_write_fields[i];
3779 j++;
3780 }
3781 max_shadow_read_write_fields = j;
3782
3783 /* shadowed fields guest access without vmexit */
3784 for (i = 0; i < max_shadow_read_write_fields; i++) {
3785 clear_bit(shadow_read_write_fields[i],
3786 vmx_vmwrite_bitmap);
3787 clear_bit(shadow_read_write_fields[i],
3788 vmx_vmread_bitmap);
3789 }
3790 for (i = 0; i < max_shadow_read_only_fields; i++)
3791 clear_bit(shadow_read_only_fields[i],
3792 vmx_vmread_bitmap);
3793}
3794
6aa8b732
AK
3795static __init int alloc_kvm_area(void)
3796{
3797 int cpu;
3798
3230bb47 3799 for_each_possible_cpu(cpu) {
6aa8b732
AK
3800 struct vmcs *vmcs;
3801
3802 vmcs = alloc_vmcs_cpu(cpu);
3803 if (!vmcs) {
3804 free_kvm_area();
3805 return -ENOMEM;
3806 }
3807
3808 per_cpu(vmxarea, cpu) = vmcs;
3809 }
3810 return 0;
3811}
3812
14168786
GN
3813static bool emulation_required(struct kvm_vcpu *vcpu)
3814{
3815 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3816}
3817
91b0aa2c 3818static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3819 struct kvm_segment *save)
6aa8b732 3820{
d99e4152
GN
3821 if (!emulate_invalid_guest_state) {
3822 /*
3823 * CS and SS RPL should be equal during guest entry according
3824 * to VMX spec, but in reality it is not always so. Since vcpu
3825 * is in the middle of the transition from real mode to
3826 * protected mode it is safe to assume that RPL 0 is a good
3827 * default value.
3828 */
3829 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA
3830 save->selector &= ~SEGMENT_RPL_MASK;
3831 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3832 save->s = 1;
6aa8b732 3833 }
d99e4152 3834 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK
3835}
3836
3837static void enter_pmode(struct kvm_vcpu *vcpu)
3838{
3839 unsigned long flags;
a89a8fb9 3840 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3841
d99e4152
GN
3842 /*
3843 * Update real mode segment cache. It may be not up-to-date if sement
3844 * register was written while vcpu was in a guest mode.
3845 */
3846 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3847 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3848 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3849 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3850 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3851 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3852
7ffd92c5 3853 vmx->rmode.vm86_active = 0;
6aa8b732 3854
2fb92db1
AK
3855 vmx_segment_cache_clear(vmx);
3856
f5f7b2fe 3857 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK
3858
3859 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK
3860 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3861 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK
3862 vmcs_writel(GUEST_RFLAGS, flags);
3863
66aee91a
RR
3864 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3865 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK
3866
3867 update_exception_bitmap(vcpu);
3868
91b0aa2c
GN
3869 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3870 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3871 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3872 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3873 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3874 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK
3875}
3876
f5f7b2fe 3877static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3878{
772e0318 3879 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN
3880 struct kvm_segment var = *save;
3881
3882 var.dpl = 0x3;
3883 if (seg == VCPU_SREG_CS)
3884 var.type = 0x3;
3885
3886 if (!emulate_invalid_guest_state) {
3887 var.selector = var.base >> 4;
3888 var.base = var.base & 0xffff0;
3889 var.limit = 0xffff;
3890 var.g = 0;
3891 var.db = 0;
3892 var.present = 1;
3893 var.s = 1;
3894 var.l = 0;
3895 var.unusable = 0;
3896 var.type = 0x3;
3897 var.avl = 0;
3898 if (save->base & 0xf)
3899 printk_once(KERN_WARNING "kvm: segment base is not "
3900 "paragraph aligned when entering "
3901 "protected mode (seg=%d)", seg);
3902 }
6aa8b732 3903
d99e4152 3904 vmcs_write16(sf->selector, var.selector);
96794e4e 3905 vmcs_writel(sf->base, var.base);
d99e4152
GN
3906 vmcs_write32(sf->limit, var.limit);
3907 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK
3908}
3909
3910static void enter_rmode(struct kvm_vcpu *vcpu)
3911{
3912 unsigned long flags;
a89a8fb9 3913 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3914
f5f7b2fe
AK
3915 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3916 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3917 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3918 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3919 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN
3920 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3921 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3922
7ffd92c5 3923 vmx->rmode.vm86_active = 1;
6aa8b732 3924
776e58ea
GN
3925 /*
3926 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3927 * vcpu. Warn the user that an update is overdue.
776e58ea 3928 */
4918c6ca 3929 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN
3930 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3931 "called before entering vcpu\n");
776e58ea 3932
2fb92db1
AK
3933 vmx_segment_cache_clear(vmx);
3934
4918c6ca 3935 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3936 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK
3937 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3938
3939 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3940 vmx->rmode.save_rflags = flags;
6aa8b732 3941
053de044 3942 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK
3943
3944 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3945 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK
3946 update_exception_bitmap(vcpu);
3947
d99e4152
GN
3948 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3949 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3950 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3951 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3952 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3953 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3954
8668a3c4 3955 kvm_mmu_reset_context(vcpu);
6aa8b732
AK
3956}
3957
401d10de
AS
3958static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3959{
3960 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK
3961 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3962
3963 if (!msr)
3964 return;
401d10de 3965
44ea2b17
AK
3966 /*
3967 * Force kernel_gs_base reloading before EFER changes, as control
3968 * of this msr depends on is_long_mode().
3969 */
3970 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3971 vcpu->arch.efer = efer;
401d10de 3972 if (efer & EFER_LMA) {
2961e876 3973 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS
3974 msr->data = efer;
3975 } else {
2961e876 3976 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS
3977
3978 msr->data = efer & ~EFER_LME;
3979 }
3980 setup_msrs(vmx);
3981}
3982
05b3e0c2 3983#ifdef CONFIG_X86_64
6aa8b732
AK
3984
3985static void enter_lmode(struct kvm_vcpu *vcpu)
3986{
3987 u32 guest_tr_ar;
3988
2fb92db1
AK
3989 vmx_segment_cache_clear(to_vmx(vcpu));
3990
6aa8b732 3991 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 3992 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK
3993 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3994 __func__);
6aa8b732 3995 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL
3996 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3997 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 3998 }
da38f438 3999 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK
4000}
4001
4002static void exit_lmode(struct kvm_vcpu *vcpu)
4003{
2961e876 4004 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 4005 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK
4006}
4007
4008#endif
4009
dd5f5341 4010static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
2384d2b3 4011{
dd180b3e
XG
4012 if (enable_ept) {
4013 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4014 return;
4e1096d2 4015 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
f0b98c02
JM
4016 } else {
4017 vpid_sync_context(vpid);
dd180b3e 4018 }
2384d2b3
SY
4019}
4020
dd5f5341
WL
4021static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4022{
4023 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4024}
4025
fb6c8198
JM
4026static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4027{
4028 if (enable_ept)
4029 vmx_flush_tlb(vcpu);
4030}
4031
e8467fda
AK
4032static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4033{
4034 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4035
4036 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4037 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4038}
4039
aff48baa
AK
4040static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4041{
4042 if (enable_ept && is_paging(vcpu))
4043 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4044 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4045}
4046
25c4c276 4047static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 4048{
fc78f519
AK
4049 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4050
4051 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4052 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK
4053}
4054
1439442c
SY
4055static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4056{
d0d538b9
GN
4057 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4058
6de4f3ad
AK
4059 if (!test_bit(VCPU_EXREG_PDPTR,
4060 (unsigned long *)&vcpu->arch.regs_dirty))
4061 return;
4062
1439442c 4063 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN
4064 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4065 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4066 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4067 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY
4068 }
4069}
4070
8f5d549f
AK
4071static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4072{
d0d538b9
GN
4073 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4074
8f5d549f 4075 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN
4076 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4077 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4078 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4079 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 4080 }
6de4f3ad
AK
4081
4082 __set_bit(VCPU_EXREG_PDPTR,
4083 (unsigned long *)&vcpu->arch.regs_avail);
4084 __set_bit(VCPU_EXREG_PDPTR,
4085 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK
4086}
4087
3899152c
DM
4088static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4089{
4090 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4091 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4092 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4093
4094 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4095 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4096 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4097 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4098
4099 return fixed_bits_valid(val, fixed0, fixed1);
4100}
4101
4102static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4103{
4104 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4105 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4106
4107 return fixed_bits_valid(val, fixed0, fixed1);
4108}
4109
4110static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4111{
4112 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4113 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4114
4115 return fixed_bits_valid(val, fixed0, fixed1);
4116}
4117
4118/* No difference in the restrictions on guest and host CR4 in VMX operation. */
4119#define nested_guest_cr4_valid nested_cr4_valid
4120#define nested_host_cr4_valid nested_cr4_valid
4121
5e1746d6 4122static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY
4123
4124static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4125 unsigned long cr0,
4126 struct kvm_vcpu *vcpu)
4127{
5233dd51
MT
4128 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4129 vmx_decache_cr3(vcpu);
1439442c
SY
4130 if (!(cr0 & X86_CR0_PG)) {
4131 /* From paging/starting to nonpaging */
4132 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 4133 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY
4134 (CPU_BASED_CR3_LOAD_EXITING |
4135 CPU_BASED_CR3_STORE_EXITING));
4136 vcpu->arch.cr0 = cr0;
fc78f519 4137 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY
4138 } else if (!is_paging(vcpu)) {
4139 /* From nonpaging to paging */
4140 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 4141 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY
4142 ~(CPU_BASED_CR3_LOAD_EXITING |
4143 CPU_BASED_CR3_STORE_EXITING));
4144 vcpu->arch.cr0 = cr0;
fc78f519 4145 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 4146 }
95eb84a7
SY
4147
4148 if (!(cr0 & X86_CR0_WP))
4149 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY
4150}
4151
6aa8b732
AK
4152static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4153{
7ffd92c5 4154 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK
4155 unsigned long hw_cr0;
4156
5037878e 4157 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 4158 if (enable_unrestricted_guest)
5037878e 4159 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 4160 else {
5037878e 4161 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 4162
218e763f
GN
4163 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4164 enter_pmode(vcpu);
6aa8b732 4165
218e763f
GN
4166 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4167 enter_rmode(vcpu);
4168 }
6aa8b732 4169
05b3e0c2 4170#ifdef CONFIG_X86_64
f6801dff 4171 if (vcpu->arch.efer & EFER_LME) {
707d92fa 4172 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 4173 enter_lmode(vcpu);
707d92fa 4174 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK
4175 exit_lmode(vcpu);
4176 }
4177#endif
4178
089d034e 4179 if (enable_ept)
1439442c
SY
4180 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4181
6aa8b732 4182 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 4183 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 4184 vcpu->arch.cr0 = cr0;
14168786
GN
4185
4186 /* depends on vcpu->arch.cr0 to be set to a new value */
4187 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK
4188}
4189
1439442c
SY
4190static u64 construct_eptp(unsigned long root_hpa)
4191{
4192 u64 eptp;
4193
4194 /* TODO write the value reading from MSR */
4195 eptp = VMX_EPT_DEFAULT_MT |
4196 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH
4197 if (enable_ept_ad_bits)
4198 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY
4199 eptp |= (root_hpa & PAGE_MASK);
4200
4201 return eptp;
4202}
4203
6aa8b732
AK
4204static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4205{
1439442c
SY
4206 unsigned long guest_cr3;
4207 u64 eptp;
4208
4209 guest_cr3 = cr3;
089d034e 4210 if (enable_ept) {
1439442c
SY
4211 eptp = construct_eptp(cr3);
4212 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK
4213 if (is_paging(vcpu) || is_guest_mode(vcpu))
4214 guest_cr3 = kvm_read_cr3(vcpu);
4215 else
4216 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 4217 ept_load_pdptrs(vcpu);
1439442c
SY
4218 }
4219
2384d2b3 4220 vmx_flush_tlb(vcpu);
1439442c 4221 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK
4222}
4223
5e1746d6 4224static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 4225{
085e68ee
BS
4226 /*
4227 * Pass through host's Machine Check Enable value to hw_cr4, which
4228 * is in force while we are in guest mode. Do not let guests control
4229 * this bit, even if host CR4.MCE == 0.
4230 */
4231 unsigned long hw_cr4 =
4232 (cr4_read_shadow() & X86_CR4_MCE) |
4233 (cr4 & ~X86_CR4_MCE) |
4234 (to_vmx(vcpu)->rmode.vm86_active ?
4235 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 4236
5e1746d6
NHE
4237 if (cr4 & X86_CR4_VMXE) {
4238 /*
4239 * To use VMXON (and later other VMX instructions), a guest
4240 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4241 * So basically the check on whether to allow nested VMX
4242 * is here.
4243 */
4244 if (!nested_vmx_allowed(vcpu))
4245 return 1;
1a0d74e6 4246 }
3899152c
DM
4247
4248 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE
4249 return 1;
4250
ad312c7c 4251 vcpu->arch.cr4 = cr4;
bc23008b
AK
4252 if (enable_ept) {
4253 if (!is_paging(vcpu)) {
4254 hw_cr4 &= ~X86_CR4_PAE;
4255 hw_cr4 |= X86_CR4_PSE;
4256 } else if (!(cr4 & X86_CR4_PAE)) {
4257 hw_cr4 &= ~X86_CR4_PAE;
4258 }
4259 }
1439442c 4260
656ec4a4
RK
4261 if (!enable_unrestricted_guest && !is_paging(vcpu))
4262 /*
ddba2628
HH
4263 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4264 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4265 * to be manually disabled when guest switches to non-paging
4266 * mode.
4267 *
4268 * If !enable_unrestricted_guest, the CPU is always running
4269 * with CR0.PG=1 and CR4 needs to be modified.
4270 * If enable_unrestricted_guest, the CPU automatically
4271 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 4272 */
ddba2628 4273 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
656ec4a4 4274
1439442c
SY
4275 vmcs_writel(CR4_READ_SHADOW, cr4);
4276 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 4277 return 0;
6aa8b732
AK
4278}
4279
6aa8b732
AK
4280static void vmx_get_segment(struct kvm_vcpu *vcpu,
4281 struct kvm_segment *var, int seg)
4282{
a9179499 4283 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK
4284 u32 ar;
4285
c6ad1153 4286 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 4287 *var = vmx->rmode.segs[seg];
a9179499 4288 if (seg == VCPU_SREG_TR
2fb92db1 4289 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 4290 return;
1390a28b
AK
4291 var->base = vmx_read_guest_seg_base(vmx, seg);
4292 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4293 return;
a9179499 4294 }
2fb92db1
AK
4295 var->base = vmx_read_guest_seg_base(vmx, seg);
4296 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4297 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4298 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 4299 var->unusable = (ar >> 16) & 1;
6aa8b732
AK
4300 var->type = ar & 15;
4301 var->s = (ar >> 4) & 1;
4302 var->dpl = (ar >> 5) & 3;
03617c18
GN
4303 /*
4304 * Some userspaces do not preserve unusable property. Since usable
4305 * segment has to be present according to VMX spec we can use present
4306 * property to amend userspace bug by making unusable segment always
4307 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4308 * segment as unusable.
4309 */
4310 var->present = !var->unusable;
6aa8b732
AK
4311 var->avl = (ar >> 12) & 1;
4312 var->l = (ar >> 13) & 1;
4313 var->db = (ar >> 14) & 1;
4314 var->g = (ar >> 15) & 1;
6aa8b732
AK
4315}
4316
a9179499
AK
4317static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4318{
a9179499
AK
4319 struct kvm_segment s;
4320
4321 if (to_vmx(vcpu)->rmode.vm86_active) {
4322 vmx_get_segment(vcpu, &s, seg);
4323 return s.base;
4324 }
2fb92db1 4325 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK
4326}
4327
b09408d0 4328static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 4329{
b09408d0
MT
4330 struct vcpu_vmx *vmx = to_vmx(vcpu);
4331
ae9fedc7 4332 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 4333 return 0;
ae9fedc7
PB
4334 else {
4335 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 4336 return VMX_AR_DPL(ar);
69c73028 4337 }
69c73028
AK
4338}
4339
653e3108 4340static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 4341{
6aa8b732
AK
4342 u32 ar;
4343
f0495f9b 4344 if (var->unusable || !var->present)
6aa8b732
AK
4345 ar = 1 << 16;
4346 else {
4347 ar = var->type & 15;
4348 ar |= (var->s & 1) << 4;
4349 ar |= (var->dpl & 3) << 5;
4350 ar |= (var->present & 1) << 7;
4351 ar |= (var->avl & 1) << 12;
4352 ar |= (var->l & 1) << 13;
4353 ar |= (var->db & 1) << 14;
4354 ar |= (var->g & 1) << 15;
4355 }
653e3108
AK
4356
4357 return ar;
4358}
4359
4360static void vmx_set_segment(struct kvm_vcpu *vcpu,
4361 struct kvm_segment *var, int seg)
4362{
7ffd92c5 4363 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 4364 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 4365
2fb92db1
AK
4366 vmx_segment_cache_clear(vmx);
4367
1ecd50a9
GN
4368 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4369 vmx->rmode.segs[seg] = *var;
4370 if (seg == VCPU_SREG_TR)
4371 vmcs_write16(sf->selector, var->selector);
4372 else if (var->s)
4373 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 4374 goto out;
653e3108 4375 }
1ecd50a9 4376
653e3108
AK
4377 vmcs_writel(sf->base, var->base);
4378 vmcs_write32(sf->limit, var->limit);
4379 vmcs_write16(sf->selector, var->selector);
3a624e29
NK
4380
4381 /*
4382 * Fix the "Accessed" bit in AR field of segment registers for older
4383 * qemu binaries.
4384 * IA32 arch specifies that at the time of processor reset the
4385 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 4386 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK
4387 * state vmexit when "unrestricted guest" mode is turned on.
4388 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4389 * tree. Newer qemu binaries with that qemu fix would not need this
4390 * kvm hack.
4391 */
4392 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 4393 var->type |= 0x1; /* Accessed */
3a624e29 4394
f924d66d 4395 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN
4396
4397out:
98eb2f8b 4398 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK
4399}
4400
6aa8b732
AK
4401static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4402{
2fb92db1 4403 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK
4404
4405 *db = (ar >> 14) & 1;
4406 *l = (ar >> 13) & 1;
4407}
4408
89a27f4d 4409static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4410{
89a27f4d
GN
4411 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4412 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK
4413}
4414
89a27f4d 4415static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4416{
89a27f4d
GN
4417 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4418 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK
4419}
4420
89a27f4d 4421static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4422{
89a27f4d
GN
4423 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4424 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK
4425}
4426
89a27f4d 4427static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4428{
89a27f4d
GN
4429 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4430 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK
4431}
4432
648dfaa7
MG
4433static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4434{
4435 struct kvm_segment var;
4436 u32 ar;
4437
4438 vmx_get_segment(vcpu, &var, seg);
07f42f5f 4439 var.dpl = 0x3;
0647f4aa
GN
4440 if (seg == VCPU_SREG_CS)
4441 var.type = 0x3;
648dfaa7
MG
4442 ar = vmx_segment_access_rights(&var);
4443
4444 if (var.base != (var.selector << 4))
4445 return false;
89efbed0 4446 if (var.limit != 0xffff)
648dfaa7 4447 return false;
07f42f5f 4448 if (ar != 0xf3)
648dfaa7
MG
4449 return false;
4450
4451 return true;
4452}
4453
4454static bool code_segment_valid(struct kvm_vcpu *vcpu)
4455{
4456 struct kvm_segment cs;
4457 unsigned int cs_rpl;
4458
4459 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 4460 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 4461
1872a3f4
AK
4462 if (cs.unusable)
4463 return false;
4d283ec9 4464 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG
4465 return false;
4466 if (!cs.s)
4467 return false;
4d283ec9 4468 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG
4469 if (cs.dpl > cs_rpl)
4470 return false;
1872a3f4 4471 } else {
648dfaa7
MG
4472 if (cs.dpl != cs_rpl)
4473 return false;
4474 }
4475 if (!cs.present)
4476 return false;
4477
4478 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4479 return true;
4480}
4481
4482static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4483{
4484 struct kvm_segment ss;
4485 unsigned int ss_rpl;
4486
4487 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 4488 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 4489
1872a3f4
AK
4490 if (ss.unusable)
4491 return true;
4492 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG
4493 return false;
4494 if (!ss.s)
4495 return false;
4496 if (ss.dpl != ss_rpl) /* DPL != RPL */
4497 return false;
4498 if (!ss.present)
4499 return false;
4500
4501 return true;
4502}
4503
4504static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4505{
4506 struct kvm_segment var;
4507 unsigned int rpl;
4508
4509 vmx_get_segment(vcpu, &var, seg);
b32a9918 4510 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 4511
1872a3f4
AK
4512 if (var.unusable)
4513 return true;
648dfaa7
MG
4514 if (!var.s)
4515 return false;
4516 if (!var.present)
4517 return false;
4d283ec9 4518 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG
4519 if (var.dpl < rpl) /* DPL < RPL */
4520 return false;
4521 }
4522
4523 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4524 * rights flags
4525 */
4526 return true;
4527}
4528
4529static bool tr_valid(struct kvm_vcpu *vcpu)
4530{
4531 struct kvm_segment tr;
4532
4533 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4534
1872a3f4
AK
4535 if (tr.unusable)
4536 return false;
b32a9918 4537 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 4538 return false;
1872a3f4 4539 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG
4540 return false;
4541 if (!tr.present)
4542 return false;
4543
4544 return true;
4545}
4546
4547static bool ldtr_valid(struct kvm_vcpu *vcpu)
4548{
4549 struct kvm_segment ldtr;
4550
4551 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4552
1872a3f4
AK
4553 if (ldtr.unusable)
4554 return true;
b32a9918 4555 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG
4556 return false;
4557 if (ldtr.type != 2)
4558 return false;
4559 if (!ldtr.present)
4560 return false;
4561
4562 return true;
4563}
4564
4565static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4566{
4567 struct kvm_segment cs, ss;
4568
4569 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4570 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4571
b32a9918
NA
4572 return ((cs.selector & SEGMENT_RPL_MASK) ==
4573 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG
4574}
4575
4576/*
4577 * Check if guest state is valid. Returns true if valid, false if
4578 * not.
4579 * We assume that registers are always usable
4580 */
4581static bool guest_state_valid(struct kvm_vcpu *vcpu)
4582{
c5e97c80
GN
4583 if (enable_unrestricted_guest)
4584 return true;
4585
648dfaa7 4586 /* real mode guest state checks */
f13882d8 4587 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG
4588 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4589 return false;
4590 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4591 return false;
4592 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4593 return false;
4594 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4595 return false;
4596 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4597 return false;
4598 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4599 return false;
4600 } else {
4601 /* protected mode guest state checks */
4602 if (!cs_ss_rpl_check(vcpu))
4603 return false;
4604 if (!code_segment_valid(vcpu))
4605 return false;
4606 if (!stack_segment_valid(vcpu))
4607 return false;
4608 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4609 return false;
4610 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4611 return false;
4612 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4613 return false;
4614 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4615 return false;
4616 if (!tr_valid(vcpu))
4617 return false;
4618 if (!ldtr_valid(vcpu))
4619 return false;
4620 }
4621 /* TODO:
4622 * - Add checks on RIP
4623 * - Add checks on RFLAGS
4624 */
4625
4626 return true;
4627}
4628
d77c26fc 4629static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4630{
40dcaa9f 4631 gfn_t fn;
195aefde 4632 u16 data = 0;
1f755a82 4633 int idx, r;
6aa8b732 4634
40dcaa9f 4635 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4636 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE
4637 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4638 if (r < 0)
10589a46 4639 goto out;
195aefde 4640 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY
4641 r = kvm_write_guest_page(kvm, fn++, &data,
4642 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4643 if (r < 0)
10589a46 4644 goto out;
195aefde
IE
4645 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4646 if (r < 0)
10589a46 4647 goto out;
195aefde
IE
4648 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4649 if (r < 0)
10589a46 4650 goto out;
195aefde 4651 data = ~0;
10589a46
MT
4652 r = kvm_write_guest_page(kvm, fn, &data,
4653 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4654 sizeof(u8));
10589a46 4655out:
40dcaa9f 4656 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4657 return r;
6aa8b732
AK
4658}
4659
b7ebfb05
SY
4660static int init_rmode_identity_map(struct kvm *kvm)
4661{
f51770ed 4662 int i, idx, r = 0;
ba049e93 4663 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY
4664 u32 tmp;
4665
089d034e 4666 if (!enable_ept)
f51770ed 4667 return 0;
a255d479
TC
4668
4669 /* Protect kvm->arch.ept_identity_pagetable_done. */
4670 mutex_lock(&kvm->slots_lock);
4671
f51770ed 4672 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4673 goto out2;
a255d479 4674
b927a3ce 4675 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC
4676
4677 r = alloc_identity_pagetable(kvm);
f51770ed 4678 if (r < 0)
a255d479
TC
4679 goto out2;
4680
40dcaa9f 4681 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY
4682 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4683 if (r < 0)
4684 goto out;
4685 /* Set up identity-mapping pagetable for EPT in real mode */
4686 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4687 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4688 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4689 r = kvm_write_guest_page(kvm, identity_map_pfn,
4690 &tmp, i * sizeof(tmp), sizeof(tmp));
4691 if (r < 0)
4692 goto out;
4693 }
4694 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4695
b7ebfb05 4696out:
40dcaa9f 4697 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC
4698
4699out2:
4700 mutex_unlock(&kvm->slots_lock);
f51770ed 4701 return r;
b7ebfb05
SY
4702}
4703
6aa8b732
AK
4704static void seg_setup(int seg)
4705{
772e0318 4706 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4707 unsigned int ar;
6aa8b732
AK
4708
4709 vmcs_write16(sf->selector, 0);
4710 vmcs_writel(sf->base, 0);
4711 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN
4712 ar = 0x93;
4713 if (seg == VCPU_SREG_CS)
4714 ar |= 0x08; /* code segment */
3a624e29
NK
4715
4716 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK
4717}
4718
f78e0e2e
SY
4719static int alloc_apic_access_page(struct kvm *kvm)
4720{
4484141a 4721 struct page *page;
f78e0e2e
SY
4722 int r = 0;
4723
79fac95e 4724 mutex_lock(&kvm->slots_lock);
c24ae0dc 4725 if (kvm->arch.apic_access_page_done)
f78e0e2e 4726 goto out;
1d8007bd
PB
4727 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4728 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY
4729 if (r)
4730 goto out;
72dc67a6 4731
73a6d941 4732 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG
4733 if (is_error_page(page)) {
4734 r = -EFAULT;
4735 goto out;
4736 }
4737
c24ae0dc
TC
4738 /*
4739 * Do not pin the page in memory, so that memory hot-unplug
4740 * is able to migrate it.
4741 */
4742 put_page(page);
4743 kvm->arch.apic_access_page_done = true;
f78e0e2e 4744out:
79fac95e 4745 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY
4746 return r;
4747}
4748
b7ebfb05
SY
4749static int alloc_identity_pagetable(struct kvm *kvm)
4750{
a255d479
TC
4751 /* Called with kvm->slots_lock held. */
4752
b7ebfb05
SY
4753 int r = 0;
4754
a255d479
TC
4755 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4756
1d8007bd
PB
4757 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4758 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
b7ebfb05 4759
b7ebfb05
SY
4760 return r;
4761}
4762
991e7a0e 4763static int allocate_vpid(void)
2384d2b3
SY
4764{
4765 int vpid;
4766
919818ab 4767 if (!enable_vpid)
991e7a0e 4768 return 0;
2384d2b3
SY
4769 spin_lock(&vmx_vpid_lock);
4770 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 4771 if (vpid < VMX_NR_VPIDS)
2384d2b3 4772 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL
4773 else
4774 vpid = 0;
2384d2b3 4775 spin_unlock(&vmx_vpid_lock);
991e7a0e 4776 return vpid;
2384d2b3
SY
4777}
4778
991e7a0e 4779static void free_vpid(int vpid)
cdbecfc3 4780{
991e7a0e 4781 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ
4782 return;
4783 spin_lock(&vmx_vpid_lock);
991e7a0e 4784 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ
4785 spin_unlock(&vmx_vpid_lock);
4786}
4787
8d14695f
YZ
4788#define MSR_TYPE_R 1
4789#define MSR_TYPE_W 2
4790static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4791 u32 msr, int type)
25c5f225 4792{
3e7c73e9 4793 int f = sizeof(unsigned long);
25c5f225
SY
4794
4795 if (!cpu_has_vmx_msr_bitmap())
4796 return;
4797
4798 /*
4799 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4800 * have the write-low and read-high bitmap offsets the wrong way round.
4801 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4802 */
25c5f225 4803 if (msr <= 0x1fff) {
8d14695f
YZ
4804 if (type & MSR_TYPE_R)
4805 /* read-low */
4806 __clear_bit(msr, msr_bitmap + 0x000 / f);
4807
4808 if (type & MSR_TYPE_W)
4809 /* write-low */
4810 __clear_bit(msr, msr_bitmap + 0x800 / f);
4811
25c5f225
SY
4812 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4813 msr &= 0x1fff;
8d14695f
YZ
4814 if (type & MSR_TYPE_R)
4815 /* read-high */
4816 __clear_bit(msr, msr_bitmap + 0x400 / f);
4817
4818 if (type & MSR_TYPE_W)
4819 /* write-high */
4820 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4821
4822 }
4823}
4824
f2b93280
WV
4825/*
4826 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4827 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4828 */
4829static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4830 unsigned long *msr_bitmap_nested,
4831 u32 msr, int type)
4832{
4833 int f = sizeof(unsigned long);
4834
4835 if (!cpu_has_vmx_msr_bitmap()) {
4836 WARN_ON(1);
4837 return;
4838 }
4839
4840 /*
4841 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4842 * have the write-low and read-high bitmap offsets the wrong way round.
4843 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4844 */
4845 if (msr <= 0x1fff) {
4846 if (type & MSR_TYPE_R &&
4847 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4848 /* read-low */
4849 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4850
4851 if (type & MSR_TYPE_W &&
4852 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4853 /* write-low */
4854 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4855
4856 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4857 msr &= 0x1fff;
4858 if (type & MSR_TYPE_R &&
4859 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4860 /* read-high */
4861 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4862
4863 if (type & MSR_TYPE_W &&
4864 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4865 /* write-high */
4866 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4867
4868 }
4869}
4870
5897297b
AK
4871static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4872{
4873 if (!longmode_only)
8d14695f
YZ
4874 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4875 msr, MSR_TYPE_R | MSR_TYPE_W);
4876 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4877 msr, MSR_TYPE_R | MSR_TYPE_W);
4878}
4879
2e69f865 4880static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
8d14695f 4881{
f6e90f9e 4882 if (apicv_active) {
c63e4563 4883 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
2e69f865 4884 msr, type);
c63e4563 4885 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
2e69f865 4886 msr, type);
f6e90f9e 4887 } else {
f6e90f9e 4888 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
2e69f865 4889 msr, type);
f6e90f9e 4890 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
2e69f865 4891 msr, type);
f6e90f9e 4892 }
5897297b
AK
4893}
4894
d62caabb 4895static bool vmx_get_enable_apicv(void)
d50ab6c1 4896{
d62caabb 4897 return enable_apicv;
d50ab6c1
PB
4898}
4899
6342c50a 4900static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
705699a1
WV
4901{
4902 struct vcpu_vmx *vmx = to_vmx(vcpu);
4903 int max_irr;
4904 void *vapic_page;
4905 u16 status;
4906
4907 if (vmx->nested.pi_desc &&
4908 vmx->nested.pi_pending) {
4909 vmx->nested.pi_pending = false;
4910 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
6342c50a 4911 return;
705699a1
WV
4912
4913 max_irr = find_last_bit(
4914 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4915
4916 if (max_irr == 256)
6342c50a 4917 return;
705699a1
WV
4918
4919 vapic_page = kmap(vmx->nested.virtual_apic_page);
705699a1
WV
4920 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4921 kunmap(vmx->nested.virtual_apic_page);
4922
4923 status = vmcs_read16(GUEST_INTR_STATUS);
4924 if ((u8)max_irr > ((u8)status & 0xff)) {
4925 status &= ~0xff;
4926 status |= (u8)max_irr;
4927 vmcs_write16(GUEST_INTR_STATUS, status);
4928 }
4929 }
705699a1
WV
4930}
4931
21bc8dc5
RK
4932static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4933{
4934#ifdef CONFIG_SMP
4935 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6
FW
4936 struct vcpu_vmx *vmx = to_vmx(vcpu);
4937
4938 /*
4939 * Currently, we don't support urgent interrupt,
4940 * all interrupts are recognized as non-urgent
4941 * interrupt, so we cannot post interrupts when
4942 * 'SN' is set.
4943 *
4944 * If the vcpu is in guest mode, it means it is
4945 * running instead of being scheduled out and
4946 * waiting in the run queue, and that's the only
4947 * case when 'SN' is set currently, warning if
4948 * 'SN' is set.
4949 */
4950 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4951
21bc8dc5
RK
4952 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4953 POSTED_INTR_VECTOR);
4954 return true;
4955 }
4956#endif
4957 return false;
4958}
4959
705699a1
WV
4960static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4961 int vector)
4962{
4963 struct vcpu_vmx *vmx = to_vmx(vcpu);
4964
4965 if (is_guest_mode(vcpu) &&
4966 vector == vmx->nested.posted_intr_nv) {
4967 /* the PIR and ON have been set by L1. */
21bc8dc5 4968 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV
4969 /*
4970 * If a posted intr is not recognized by hardware,
4971 * we will accomplish it in the next vmentry.
4972 */
4973 vmx->nested.pi_pending = true;
4974 kvm_make_request(KVM_REQ_EVENT, vcpu);
4975 return 0;
4976 }
4977 return -1;
4978}
a20ed54d
YZ
4979/*
4980 * Send interrupt to vcpu via posted interrupt way.
4981 * 1. If target vcpu is running(non-root mode), send posted interrupt
4982 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4983 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4984 * interrupt from PIR in next vmentry.
4985 */
4986static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4987{
4988 struct vcpu_vmx *vmx = to_vmx(vcpu);
4989 int r;
4990
705699a1
WV
4991 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4992 if (!r)
4993 return;
4994
a20ed54d
YZ
4995 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4996 return;
4997
b95234c8
PB
4998 /* If a previous notification has sent the IPI, nothing to do. */
4999 if (pi_test_and_set_on(&vmx->pi_desc))
5000 return;
5001
5002 if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ
5003 kvm_vcpu_kick(vcpu);
5004}
5005
a3a8ff8e
NHE
5006/*
5007 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5008 * will not change in the lifetime of the guest.
5009 * Note that host-state that does change is set elsewhere. E.g., host-state
5010 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5011 */
a547c6db 5012static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE
5013{
5014 u32 low32, high32;
5015 unsigned long tmpl;
5016 struct desc_ptr dt;
d6e41f11 5017 unsigned long cr0, cr3, cr4;
a3a8ff8e 5018
04ac88ab
AL
5019 cr0 = read_cr0();
5020 WARN_ON(cr0 & X86_CR0_TS);
5021 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL
5022
5023 /*
5024 * Save the most likely value for this task's CR3 in the VMCS.
5025 * We can't use __get_current_cr3_fast() because we're not atomic.
5026 */
5027 cr3 = read_cr3();
5028 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5029 vmx->host_state.vmcs_host_cr3 = cr3;
a3a8ff8e 5030
d974baa3 5031 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 5032 cr4 = cr4_read_shadow();
d974baa3
AL
5033 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5034 vmx->host_state.vmcs_host_cr4 = cr4;
5035
a3a8ff8e 5036 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK
5037#ifdef CONFIG_X86_64
5038 /*
5039 * Load null selectors, so we can avoid reloading them in
5040 * __vmx_load_host_state(), in case userspace uses the null selectors
5041 * too (the expected case).
5042 */
5043 vmcs_write16(HOST_DS_SELECTOR, 0);
5044 vmcs_write16(HOST_ES_SELECTOR, 0);
5045#else
a3a8ff8e
NHE
5046 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5047 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 5048#endif
a3a8ff8e
NHE
5049 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5050 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5051
5052 native_store_idt(&dt);
5053 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 5054 vmx->host_idt_base = dt.address;
a3a8ff8e 5055
83287ea4 5056 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE
5057
5058 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5059 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5060 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5061 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5062
5063 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5064 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5065 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5066 }
5067}
5068
bf8179a0
NHE
5069static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5070{
5071 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5072 if (enable_ept)
5073 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE
5074 if (is_guest_mode(&vmx->vcpu))
5075 vmx->vcpu.arch.cr4_guest_owned_bits &=
5076 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE
5077 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5078}
5079
01e439be
YZ
5080static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5081{
5082 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5083
d62caabb 5084 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 5085 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
64672c95
YJ
5086 /* Enable the preemption timer dynamically */
5087 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ
5088 return pin_based_exec_ctrl;
5089}
5090
d62caabb
AS
5091static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5092{
5093 struct vcpu_vmx *vmx = to_vmx(vcpu);
5094
5095 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK
5096 if (cpu_has_secondary_exec_ctrls()) {
5097 if (kvm_vcpu_apicv_active(vcpu))
5098 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5099 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5100 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5101 else
5102 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5103 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5104 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5105 }
5106
5107 if (cpu_has_vmx_msr_bitmap())
5108 vmx_set_msr_bitmap(vcpu);
d62caabb
AS
5109}
5110
bf8179a0
NHE
5111static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5112{
5113 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB
5114
5115 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5116 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5117
35754c98 5118 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE
5119 exec_control &= ~CPU_BASED_TPR_SHADOW;
5120#ifdef CONFIG_X86_64
5121 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5122 CPU_BASED_CR8_LOAD_EXITING;
5123#endif
5124 }
5125 if (!enable_ept)
5126 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5127 CPU_BASED_CR3_LOAD_EXITING |
5128 CPU_BASED_INVLPG_EXITING;
5129 return exec_control;
5130}
5131
5132static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5133{
5134 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 5135 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE
5136 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5137 if (vmx->vpid == 0)
5138 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5139 if (!enable_ept) {
5140 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5141 enable_unrestricted_guest = 0;
ad756a16
MJ
5142 /* Enable INVPCID for non-ept guests may cause performance regression. */
5143 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE
5144 }
5145 if (!enable_unrestricted_guest)
5146 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5147 if (!ple_gap)
5148 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
d62caabb 5149 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
c7c9c56c
YZ
5150 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5151 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 5152 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG
5153 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5154 (handle_vmptrld).
5155 We can NOT enable shadow_vmcs here because we don't have yet
5156 a current VMCS12
5157 */
5158 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH
5159
5160 if (!enable_pml)
5161 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 5162
bf8179a0
NHE
5163 return exec_control;
5164}
5165
ce88decf
XG
5166static void ept_set_mmio_spte_mask(void)
5167{
5168 /*
5169 * EPT Misconfigurations can be generated if the value of bits 2:0
5170 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 5171 */
312b616b 5172 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
ce88decf
XG
5173}
5174
f53cd63c 5175#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK
5176/*
5177 * Sets up the vmcs for emulated real mode.
5178 */
8b9cf98c 5179static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 5180{
2e4ce7f5 5181#ifdef CONFIG_X86_64
6aa8b732 5182 unsigned long a;
2e4ce7f5 5183#endif
6aa8b732 5184 int i;
6aa8b732 5185
6aa8b732 5186 /* I/O */
3e7c73e9
AK
5187 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5188 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 5189
4607c2d7
AG
5190 if (enable_shadow_vmcs) {
5191 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5192 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5193 }
25c5f225 5194 if (cpu_has_vmx_msr_bitmap())
5897297b 5195 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 5196
6aa8b732
AK
5197 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5198
6aa8b732 5199 /* Control */
01e439be 5200 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
64672c95 5201 vmx->hv_deadline_tsc = -1;
6e5d865c 5202
bf8179a0 5203 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 5204
dfa169bb 5205 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE
5206 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5207 vmx_secondary_exec_control(vmx));
dfa169bb 5208 }
f78e0e2e 5209
d62caabb 5210 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ
5211 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5212 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5213 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5214 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5215
5216 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 5217
0bcf261c 5218 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 5219 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ
5220 }
5221
4b8d54f9
ZE
5222 if (ple_gap) {
5223 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK
5224 vmx->ple_window = ple_window;
5225 vmx->ple_window_dirty = true;
4b8d54f9
ZE
5226 }
5227
c3707958
XG
5228 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5229 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK
5230 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5231
9581d442
AK
5232 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5233 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 5234 vmx_set_constant_host_state(vmx);
05b3e0c2 5235#ifdef CONFIG_X86_64
6aa8b732
AK
5236 rdmsrl(MSR_FS_BASE, a);
5237 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5238 rdmsrl(MSR_GS_BASE, a);
5239 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5240#else
5241 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5242 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5243#endif
5244
2cc51560
ED
5245 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5246 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 5247 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 5248 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 5249 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 5250
74545705
RK
5251 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5252 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 5253
03916db9 5254 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK
5255 u32 index = vmx_msr_index[i];
5256 u32 data_low, data_high;
a2fa3e9f 5257 int j = vmx->nmsrs;
6aa8b732
AK
5258
5259 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5260 continue;
432bd6cb
AK
5261 if (wrmsr_safe(index, data_low, data_high) < 0)
5262 continue;
26bb0981
AK
5263 vmx->guest_msrs[j].index = i;
5264 vmx->guest_msrs[j].data = 0;
d5696725 5265 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 5266 ++vmx->nmsrs;
6aa8b732 5267 }
6aa8b732 5268
2961e876
GN
5269
5270 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK
5271
5272 /* 22.2.1, 20.8.1 */
2961e876 5273 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 5274
bd7e5b08
PB
5275 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5276 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5277
bf8179a0 5278 set_cr4_guest_host_mask(vmx);
e00c8cf2 5279
f53cd63c
WL
5280 if (vmx_xsaves_supported())
5281 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5282
4e59516a
PF
5283 if (enable_pml) {
5284 ASSERT(vmx->pml_pg);
5285 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5286 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5287 }
5288
e00c8cf2
AK
5289 return 0;
5290}
5291
d28bc9dd 5292static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK
5293{
5294 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 5295 struct msr_data apic_base_msr;
d28bc9dd 5296 u64 cr0;
e00c8cf2 5297
7ffd92c5 5298 vmx->rmode.vm86_active = 0;
e00c8cf2 5299
ad312c7c 5300 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA
5301 kvm_set_cr8(vcpu, 0);
5302
5303 if (!init_event) {
5304 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5305 MSR_IA32_APICBASE_ENABLE;
5306 if (kvm_vcpu_is_reset_bsp(vcpu))
5307 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5308 apic_base_msr.host_initiated = true;
5309 kvm_set_apic_base(vcpu, &apic_base_msr);
5310 }
e00c8cf2 5311
2fb92db1
AK
5312 vmx_segment_cache_clear(vmx);
5313
5706be0d 5314 seg_setup(VCPU_SREG_CS);
66450a21 5315 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 5316 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK
5317
5318 seg_setup(VCPU_SREG_DS);
5319 seg_setup(VCPU_SREG_ES);
5320 seg_setup(VCPU_SREG_FS);
5321 seg_setup(VCPU_SREG_GS);
5322 seg_setup(VCPU_SREG_SS);
5323
5324 vmcs_write16(GUEST_TR_SELECTOR, 0);
5325 vmcs_writel(GUEST_TR_BASE, 0);
5326 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5327 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5328
5329 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5330 vmcs_writel(GUEST_LDTR_BASE, 0);
5331 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5332 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5333
d28bc9dd
NA
5334 if (!init_event) {
5335 vmcs_write32(GUEST_SYSENTER_CS, 0);
5336 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5337 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5338 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5339 }
e00c8cf2
AK
5340
5341 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 5342 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 5343
e00c8cf2
AK
5344 vmcs_writel(GUEST_GDTR_BASE, 0);
5345 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5346
5347 vmcs_writel(GUEST_IDTR_BASE, 0);
5348 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5349
443381a8 5350 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 5351 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 5352 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
e00c8cf2 5353
e00c8cf2
AK
5354 setup_msrs(vmx);
5355
6aa8b732
AK
5356 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5357
d28bc9dd 5358 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 5359 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 5360 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 5361 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 5362 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY
5363 vmcs_write32(TPR_THRESHOLD, 0);
5364 }
5365
a73896cb 5366 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 5367
d62caabb 5368 if (kvm_vcpu_apicv_active(vcpu))
01e439be
YZ
5369 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5370
2384d2b3
SY
5371 if (vmx->vpid != 0)
5372 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5373
d28bc9dd 5374 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 5375 vmx->vcpu.arch.cr0 = cr0;
f2463247 5376 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 5377 vmx_set_cr4(vcpu, 0);
5690891b 5378 vmx_set_efer(vcpu, 0);
bd7e5b08 5379
d28bc9dd 5380 update_exception_bitmap(vcpu);
6aa8b732 5381
dd5f5341 5382 vpid_sync_context(vmx->vpid);
6aa8b732
AK
5383}
5384
b6f1250e
NHE
5385/*
5386 * In nested virtualization, check if L1 asked to exit on external interrupts.
5387 * For most existing hypervisors, this will always return true.
5388 */
5389static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5390{
5391 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5392 PIN_BASED_EXT_INTR_MASK;
5393}
5394
77b0f5d6
BD
5395/*
5396 * In nested virtualization, check if L1 has set
5397 * VM_EXIT_ACK_INTR_ON_EXIT
5398 */
5399static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5400{
5401 return get_vmcs12(vcpu)->vm_exit_controls &
5402 VM_EXIT_ACK_INTR_ON_EXIT;
5403}
5404
ea8ceb83
JK
5405static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5406{
5407 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5408 PIN_BASED_NMI_EXITING;
5409}
5410
c9a7953f 5411static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 5412{
47c0152e
PB
5413 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5414 CPU_BASED_VIRTUAL_INTR_PENDING);
3b86cd99
JK
5415}
5416
c9a7953f 5417static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 5418{
2c82878b 5419 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK
5420 enable_irq_window(vcpu);
5421 return;
5422 }
3b86cd99 5423
47c0152e
PB
5424 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5425 CPU_BASED_VIRTUAL_NMI_PENDING);
3b86cd99
JK
5426}
5427
66fd3f7f 5428static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 5429{
9c8cba37 5430 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN
5431 uint32_t intr;
5432 int irq = vcpu->arch.interrupt.nr;
9c8cba37 5433
229456fc 5434 trace_kvm_inj_virq(irq);
2714d1d3 5435
fa89a817 5436 ++vcpu->stat.irq_injections;
7ffd92c5 5437 if (vmx->rmode.vm86_active) {
71f9833b
SH
5438 int inc_eip = 0;
5439 if (vcpu->arch.interrupt.soft)
5440 inc_eip = vcpu->arch.event_exit_inst_len;
5441 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 5442 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED
5443 return;
5444 }
66fd3f7f
GN
5445 intr = irq | INTR_INFO_VALID_MASK;
5446 if (vcpu->arch.interrupt.soft) {
5447 intr |= INTR_TYPE_SOFT_INTR;
5448 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5449 vmx->vcpu.arch.event_exit_inst_len);
5450 } else
5451 intr |= INTR_TYPE_EXT_INTR;
5452 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED
5453}
5454
f08864b4
SY
5455static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5456{
66a5a347
JK
5457 struct vcpu_vmx *vmx = to_vmx(vcpu);
5458
c5a6d5f7 5459 if (!is_guest_mode(vcpu)) {
c5a6d5f7
WL
5460 ++vcpu->stat.nmi_injections;
5461 vmx->nmi_known_unmasked = false;
3b86cd99
JK
5462 }
5463
7ffd92c5 5464 if (vmx->rmode.vm86_active) {
71f9833b 5465 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 5466 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK
5467 return;
5468 }
c5a6d5f7 5469
f08864b4
SY
5470 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5471 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY
5472}
5473
3cfc3092
JK
5474static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5475{
9d58b931
AK
5476 if (to_vmx(vcpu)->nmi_known_unmasked)
5477 return false;
c332c83a 5478 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK
5479}
5480
5481static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5482{
5483 struct vcpu_vmx *vmx = to_vmx(vcpu);
5484
2c82878b
PB
5485 vmx->nmi_known_unmasked = !masked;
5486 if (masked)
5487 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5488 GUEST_INTR_STATE_NMI);
5489 else
5490 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5491 GUEST_INTR_STATE_NMI);
3cfc3092
JK
5492}
5493
2505dc9f
JK
5494static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5495{
b6b8a145
JK
5496 if (to_vmx(vcpu)->nested.nested_run_pending)
5497 return 0;
ea8ceb83 5498
2505dc9f
JK
5499 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5500 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5501 | GUEST_INTR_STATE_NMI));
5502}
5503
78646121
GN
5504static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5505{
b6b8a145
JK
5506 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5507 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN
5508 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5509 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN
5510}
5511
cbc94022
IE
5512static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5513{
5514 int ret;
cbc94022 5515
1d8007bd
PB
5516 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5517 PAGE_SIZE * 3);
cbc94022
IE
5518 if (ret)
5519 return ret;
bfc6d222 5520 kvm->arch.tss_addr = addr;
1f755a82 5521 return init_rmode_tss(kvm);
cbc94022
IE
5522}
5523
0ca1b4f4 5524static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 5525{
77ab6db0 5526 switch (vec) {
77ab6db0 5527 case BP_VECTOR:
c573cd22
JK
5528 /*
5529 * Update instruction length as we may reinject the exception
5530 * from user space while in guest debugging mode.
5531 */
5532 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5533 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 5534 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN
5535 return false;
5536 /* fall through */
5537 case DB_VECTOR:
5538 if (vcpu->guest_debug &
5539 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5540 return false;
d0bfb940
JK
5541 /* fall through */
5542 case DE_VECTOR:
77ab6db0
JK
5543 case OF_VECTOR:
5544 case BR_VECTOR:
5545 case UD_VECTOR:
5546 case DF_VECTOR:
5547 case SS_VECTOR:
5548 case GP_VECTOR:
5549 case MF_VECTOR:
0ca1b4f4
GN
5550 return true;
5551 break;
77ab6db0 5552 }
0ca1b4f4
GN
5553 return false;
5554}
5555
5556static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5557 int vec, u32 err_code)
5558{
5559 /*
5560 * Instruction with address size override prefix opcode 0x67
5561 * Cause the #SS fault with 0 error code in VM86 mode.
5562 */
5563 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5564 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5565 if (vcpu->arch.halt_request) {
5566 vcpu->arch.halt_request = 0;
5cb56059 5567 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN
5568 }
5569 return 1;
5570 }
5571 return 0;
5572 }
5573
5574 /*
5575 * Forward all other exceptions that are valid in real mode.
5576 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5577 * the required debugging infrastructure rework.
5578 */
5579 kvm_queue_exception(vcpu, vec);
5580 return 1;
6aa8b732
AK
5581}
5582
a0861c02
AK
5583/*
5584 * Trigger machine check on the host. We assume all the MSRs are already set up
5585 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5586 * We pass a fake environment to the machine check handler because we want
5587 * the guest to be always treated like user space, no matter what context
5588 * it used internally.
5589 */
5590static void kvm_machine_check(void)
5591{
5592#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5593 struct pt_regs regs = {
5594 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5595 .flags = X86_EFLAGS_IF,
5596 };
5597
5598 do_machine_check(&regs, 0);
5599#endif
5600}
5601
851ba692 5602static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK
5603{
5604 /* already handled by vcpu_run */
5605 return 1;
5606}
5607
851ba692 5608static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5609{
1155f76a 5610 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5611 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5612 u32 intr_info, ex_no, error_code;
42dbaa5a 5613 unsigned long cr2, rip, dr6;
6aa8b732
AK
5614 u32 vect_info;
5615 enum emulation_result er;
5616
1155f76a 5617 vect_info = vmx->idt_vectoring_info;
88786475 5618 intr_info = vmx->exit_intr_info;
6aa8b732 5619
a0861c02 5620 if (is_machine_check(intr_info))
851ba692 5621 return handle_machine_check(vcpu);
a0861c02 5622
ef85b673 5623 if (is_nmi(intr_info))
1b6269db 5624 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc 5625
7aa81cc0 5626 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK
5627 if (is_guest_mode(vcpu)) {
5628 kvm_queue_exception(vcpu, UD_VECTOR);
5629 return 1;
5630 }
51d8b661 5631 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5632 if (er != EMULATE_DONE)
7ee5d940 5633 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL
5634 return 1;
5635 }
5636
6aa8b732 5637 error_code = 0;
2e11384c 5638 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5639 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG
5640
5641 /*
5642 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5643 * MMIO, it is better to report an internal error.
5644 * See the comments in vmx_handle_exit.
5645 */
5646 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5647 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5648 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5649 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5650 vcpu->run->internal.ndata = 3;
bf4ca23e
XG
5651 vcpu->run->internal.data[0] = vect_info;
5652 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5653 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG
5654 return 0;
5655 }
5656
6aa8b732 5657 if (is_page_fault(intr_info)) {
1439442c 5658 /* EPT won't cause page fault directly */
cf3ace79 5659 BUG_ON(enable_ept);
6aa8b732 5660 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT
5661 trace_kvm_page_fault(cr2, error_code);
5662
3298b75c 5663 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5664 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5665 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK
5666 }
5667
d0bfb940 5668 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN
5669
5670 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5671 return handle_rmode_exception(vcpu, ex_no, error_code);
5672
42dbaa5a 5673 switch (ex_no) {
54a20552
EN
5674 case AC_VECTOR:
5675 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5676 return 1;
42dbaa5a
JK
5677 case DB_VECTOR:
5678 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5679 if (!(vcpu->guest_debug &
5680 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5681 vcpu->arch.dr6 &= ~15;
6f43ed01 5682 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD
5683 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5684 skip_emulated_instruction(vcpu);
5685
42dbaa5a
JK
5686 kvm_queue_exception(vcpu, DB_VECTOR);
5687 return 1;
5688 }
5689 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5690 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5691 /* fall through */
5692 case BP_VECTOR:
c573cd22
JK
5693 /*
5694 * Update instruction length as we may reinject #BP from
5695 * user space while in guest debugging mode. Reading it for
5696 * #DB as well causes no harm, it is not used in that case.
5697 */
5698 vmx->vcpu.arch.event_exit_inst_len =
5699 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5700 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5701 rip = kvm_rip_read(vcpu);
d0bfb940
JK
5702 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5703 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK
5704 break;
5705 default:
d0bfb940
JK
5706 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5707 kvm_run->ex.exception = ex_no;
5708 kvm_run->ex.error_code = error_code;
42dbaa5a 5709 break;
6aa8b732 5710 }
6aa8b732
AK
5711 return 0;
5712}
5713
851ba692 5714static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5715{
1165f5fe 5716 ++vcpu->stat.irq_exits;
6aa8b732
AK
5717 return 1;
5718}
5719
851ba692 5720static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5721{
851ba692 5722 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK
5723 return 0;
5724}
6aa8b732 5725
851ba692 5726static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5727{
bfdaab09 5728 unsigned long exit_qualification;
6affcbed 5729 int size, in, string, ret;
039576c0 5730 unsigned port;
6aa8b732 5731
bfdaab09 5732 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5733 string = (exit_qualification & 16) != 0;
cf8f70bf 5734 in = (exit_qualification & 8) != 0;
e70669ab 5735
cf8f70bf 5736 ++vcpu->stat.io_exits;
e70669ab 5737
cf8f70bf 5738 if (string || in)
51d8b661 5739 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5740
cf8f70bf
GN
5741 port = exit_qualification >> 16;
5742 size = (exit_qualification & 7) + 1;
cf8f70bf 5743
6affcbed
KH
5744 ret = kvm_skip_emulated_instruction(vcpu);
5745
5746 /*
5747 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5748 * KVM_EXIT_DEBUG here.
5749 */
5750 return kvm_fast_pio_out(vcpu, size, port) && ret;
6aa8b732
AK
5751}
5752
102d8325
IM
5753static void
5754vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5755{
5756 /*
5757 * Patch in the VMCALL instruction:
5758 */
5759 hypercall[0] = 0x0f;
5760 hypercall[1] = 0x01;
5761 hypercall[2] = 0xc1;
102d8325
IM
5762}
5763
0fa06071 5764/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE
5765static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5766{
eeadf9e7 5767 if (is_guest_mode(vcpu)) {
1a0d74e6
JK
5768 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5769 unsigned long orig_val = val;
5770
eeadf9e7
NHE
5771 /*
5772 * We get here when L2 changed cr0 in a way that did not change
5773 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK
5774 * but did change L0 shadowed bits. So we first calculate the
5775 * effective cr0 value that L1 would like to write into the
5776 * hardware. It consists of the L2-owned bits from the new
5777 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5778 */
1a0d74e6
JK
5779 val = (val & ~vmcs12->cr0_guest_host_mask) |
5780 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5781
3899152c 5782 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 5783 return 1;
1a0d74e6
JK
5784
5785 if (kvm_set_cr0(vcpu, val))
5786 return 1;
5787 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5788 return 0;
1a0d74e6
JK
5789 } else {
5790 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 5791 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 5792 return 1;
3899152c 5793
eeadf9e7 5794 return kvm_set_cr0(vcpu, val);
1a0d74e6 5795 }
eeadf9e7
NHE
5796}
5797
5798static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5799{
5800 if (is_guest_mode(vcpu)) {
1a0d74e6
JK
5801 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5802 unsigned long orig_val = val;
5803
5804 /* analogously to handle_set_cr0 */
5805 val = (val & ~vmcs12->cr4_guest_host_mask) |
5806 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5807 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5808 return 1;
1a0d74e6 5809 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE
5810 return 0;
5811 } else
5812 return kvm_set_cr4(vcpu, val);
5813}
5814
851ba692 5815static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5816{
229456fc 5817 unsigned long exit_qualification, val;
6aa8b732
AK
5818 int cr;
5819 int reg;
49a9b07e 5820 int err;
6affcbed 5821 int ret;
6aa8b732 5822
bfdaab09 5823 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK
5824 cr = exit_qualification & 15;
5825 reg = (exit_qualification >> 8) & 15;
5826 switch ((exit_qualification >> 4) & 3) {
5827 case 0: /* mov to cr */
1e32c079 5828 val = kvm_register_readl(vcpu, reg);
229456fc 5829 trace_kvm_cr_write(cr, val);
6aa8b732
AK
5830 switch (cr) {
5831 case 0:
eeadf9e7 5832 err = handle_set_cr0(vcpu, val);
6affcbed 5833 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 5834 case 3:
2390218b 5835 err = kvm_set_cr3(vcpu, val);
6affcbed 5836 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 5837 case 4:
eeadf9e7 5838 err = handle_set_cr4(vcpu, val);
6affcbed 5839 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN
5840 case 8: {
5841 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5842 u8 cr8 = (u8)val;
eea1cff9 5843 err = kvm_set_cr8(vcpu, cr8);
6affcbed 5844 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 5845 if (lapic_in_kernel(vcpu))
6affcbed 5846 return ret;
0a5fff19 5847 if (cr8_prev <= cr8)
6affcbed
KH
5848 return ret;
5849 /*
5850 * TODO: we might be squashing a
5851 * KVM_GUESTDBG_SINGLESTEP-triggered
5852 * KVM_EXIT_DEBUG here.
5853 */
851ba692 5854 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN
5855 return 0;
5856 }
4b8073e4 5857 }
6aa8b732 5858 break;
25c4c276 5859 case 2: /* clts */
bd7e5b08
PB
5860 WARN_ONCE(1, "Guest should always own CR0.TS");
5861 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 5862 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 5863 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5864 case 1: /*mov from cr*/
5865 switch (cr) {
5866 case 3:
9f8fe504
AK
5867 val = kvm_read_cr3(vcpu);
5868 kvm_register_write(vcpu, reg, val);
5869 trace_kvm_cr_read(cr, val);
6affcbed 5870 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 5871 case 8:
229456fc
MT
5872 val = kvm_get_cr8(vcpu);
5873 kvm_register_write(vcpu, reg, val);
5874 trace_kvm_cr_read(cr, val);
6affcbed 5875 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5876 }
5877 break;
5878 case 3: /* lmsw */
a1f83a74 5879 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5880 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5881 kvm_lmsw(vcpu, val);
6aa8b732 5882
6affcbed 5883 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5884 default:
5885 break;
5886 }
851ba692 5887 vcpu->run->exit_reason = 0;
a737f256 5888 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK
5889 (int)(exit_qualification >> 4) & 3, cr);
5890 return 0;
5891}
5892
851ba692 5893static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5894{
bfdaab09 5895 unsigned long exit_qualification;
16f8a6f9
NA
5896 int dr, dr7, reg;
5897
5898 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5899 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5900
5901 /* First, if DR does not exist, trigger UD */
5902 if (!kvm_require_dr(vcpu, dr))
5903 return 1;
6aa8b732 5904
f2483415 5905 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK
5906 if (!kvm_require_cpl(vcpu, 0))
5907 return 1;
16f8a6f9
NA
5908 dr7 = vmcs_readl(GUEST_DR7);
5909 if (dr7 & DR7_GD) {
42dbaa5a
JK
5910 /*
5911 * As the vm-exit takes precedence over the debug trap, we
5912 * need to emulate the latter, either for the host or the
5913 * guest debugging itself.
5914 */
5915 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5916 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5917 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5918 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK
5919 vcpu->run->debug.arch.exception = DB_VECTOR;
5920 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK
5921 return 0;
5922 } else {
7305eb5d 5923 vcpu->arch.dr6 &= ~15;
6f43ed01 5924 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK
5925 kvm_queue_exception(vcpu, DB_VECTOR);
5926 return 1;
5927 }
5928 }
5929
81908bf4 5930 if (vcpu->guest_debug == 0) {
8f22372f
PB
5931 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5932 CPU_BASED_MOV_DR_EXITING);
81908bf4
PB
5933
5934 /*
5935 * No more DR vmexits; force a reload of the debug registers
5936 * and reenter on this instruction. The next vmexit will
5937 * retrieve the full state of the debug registers.
5938 */
5939 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5940 return 1;
5941 }
5942
42dbaa5a
JK
5943 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5944 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5945 unsigned long val;
4c4d563b
JK
5946
5947 if (kvm_get_dr(vcpu, dr, &val))
5948 return 1;
5949 kvm_register_write(vcpu, reg, val);
020df079 5950 } else
5777392e 5951 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK
5952 return 1;
5953
6affcbed 5954 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5955}
5956
73aaf249
JK
5957static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5958{
5959 return vcpu->arch.dr6;
5960}
5961
5962static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5963{
5964}
5965
81908bf4
PB
5966static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5967{
81908bf4
PB
5968 get_debugreg(vcpu->arch.db[0], 0);
5969 get_debugreg(vcpu->arch.db[1], 1);
5970 get_debugreg(vcpu->arch.db[2], 2);
5971 get_debugreg(vcpu->arch.db[3], 3);
5972 get_debugreg(vcpu->arch.dr6, 6);
5973 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5974
5975 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
8f22372f 5976 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
81908bf4
PB
5977}
5978
020df079
GN
5979static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5980{
5981 vmcs_writel(GUEST_DR7, val);
5982}
5983
851ba692 5984static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5985{
6a908b62 5986 return kvm_emulate_cpuid(vcpu);
6aa8b732
AK
5987}
5988
851ba692 5989static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5990{
ad312c7c 5991 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 5992 struct msr_data msr_info;
6aa8b732 5993
609e36d3
PB
5994 msr_info.index = ecx;
5995 msr_info.host_initiated = false;
5996 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 5997 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5998 kvm_inject_gp(vcpu, 0);
6aa8b732
AK
5999 return 1;
6000 }
6001
609e36d3 6002 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 6003
6aa8b732 6004 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB
6005 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6006 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6affcbed 6007 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
6008}
6009
851ba692 6010static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 6011{
8fe8ab46 6012 struct msr_data msr;
ad312c7c
ZX
6013 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6014 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6015 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 6016
8fe8ab46
WA
6017 msr.data = data;
6018 msr.index = ecx;
6019 msr.host_initiated = false;
854e8bb1 6020 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 6021 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 6022 kvm_inject_gp(vcpu, 0);
6aa8b732
AK
6023 return 1;
6024 }
6025
59200273 6026 trace_kvm_msr_write(ecx, data);
6affcbed 6027 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
6028}
6029
851ba692 6030static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 6031{
eb90f341 6032 kvm_apic_update_ppr(vcpu);
6e5d865c
YS
6033 return 1;
6034}
6035
851ba692 6036static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 6037{
47c0152e
PB
6038 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6039 CPU_BASED_VIRTUAL_INTR_PENDING);
2714d1d3 6040
3842d135
AK
6041 kvm_make_request(KVM_REQ_EVENT, vcpu);
6042
a26bf12a 6043 ++vcpu->stat.irq_window_exits;
6aa8b732
AK
6044 return 1;
6045}
6046
851ba692 6047static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 6048{
d3bef15f 6049 return kvm_emulate_halt(vcpu);
6aa8b732
AK
6050}
6051
851ba692 6052static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 6053{
0d9c055e 6054 return kvm_emulate_hypercall(vcpu);
c21415e8
IM
6055}
6056
ec25d5e6
GN
6057static int handle_invd(struct kvm_vcpu *vcpu)
6058{
51d8b661 6059 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN
6060}
6061
851ba692 6062static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 6063{
f9c617f6 6064 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT
6065
6066 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 6067 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT
6068}
6069
fee84b07
AK
6070static int handle_rdpmc(struct kvm_vcpu *vcpu)
6071{
6072 int err;
6073
6074 err = kvm_rdpmc(vcpu);
6affcbed 6075 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK
6076}
6077
851ba692 6078static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 6079{
6affcbed 6080 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED
6081}
6082
2acf923e
DC
6083static int handle_xsetbv(struct kvm_vcpu *vcpu)
6084{
6085 u64 new_bv = kvm_read_edx_eax(vcpu);
6086 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6087
6088 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 6089 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC
6090 return 1;
6091}
6092
f53cd63c
WL
6093static int handle_xsaves(struct kvm_vcpu *vcpu)
6094{
6affcbed 6095 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL
6096 WARN(1, "this should never happen\n");
6097 return 1;
6098}
6099
6100static int handle_xrstors(struct kvm_vcpu *vcpu)
6101{
6affcbed 6102 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL
6103 WARN(1, "this should never happen\n");
6104 return 1;
6105}
6106
851ba692 6107static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 6108{
58fbbf26
KT
6109 if (likely(fasteoi)) {
6110 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6111 int access_type, offset;
6112
6113 access_type = exit_qualification & APIC_ACCESS_TYPE;
6114 offset = exit_qualification & APIC_ACCESS_OFFSET;
6115 /*
6116 * Sane guest uses MOV to write EOI, with written value
6117 * not cared. So make a short-circuit here by avoiding
6118 * heavy instruction emulation.
6119 */
6120 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6121 (offset == APIC_EOI)) {
6122 kvm_lapic_set_eoi(vcpu);
6affcbed 6123 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT
6124 }
6125 }
51d8b661 6126 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY
6127}
6128
c7c9c56c
YZ
6129static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6130{
6131 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6132 int vector = exit_qualification & 0xff;
6133
6134 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6135 kvm_apic_set_eoi_accelerated(vcpu, vector);
6136 return 1;
6137}
6138
83d4c286
YZ
6139static int handle_apic_write(struct kvm_vcpu *vcpu)
6140{
6141 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6142 u32 offset = exit_qualification & 0xfff;
6143
6144 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6145 kvm_apic_write_nodecode(vcpu, offset);
6146 return 1;
6147}
6148
851ba692 6149static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 6150{
60637aac 6151 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 6152 unsigned long exit_qualification;
e269fb21
JK
6153 bool has_error_code = false;
6154 u32 error_code = 0;
37817f29 6155 u16 tss_selector;
7f3d35fd 6156 int reason, type, idt_v, idt_index;
64a7ec06
GN
6157
6158 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 6159 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 6160 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE
6161
6162 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6163
6164 reason = (u32)exit_qualification >> 30;
64a7ec06
GN
6165 if (reason == TASK_SWITCH_GATE && idt_v) {
6166 switch (type) {
6167 case INTR_TYPE_NMI_INTR:
6168 vcpu->arch.nmi_injected = false;
654f06fc 6169 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN
6170 break;
6171 case INTR_TYPE_EXT_INTR:
66fd3f7f 6172 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN
6173 kvm_clear_interrupt_queue(vcpu);
6174 break;
6175 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK
6176 if (vmx->idt_vectoring_info &
6177 VECTORING_INFO_DELIVER_CODE_MASK) {
6178 has_error_code = true;
6179 error_code =
6180 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6181 }
6182 /* fall through */
64a7ec06
GN
6183 case INTR_TYPE_SOFT_EXCEPTION:
6184 kvm_clear_exception_queue(vcpu);
6185 break;
6186 default:
6187 break;
6188 }
60637aac 6189 }
37817f29
IE
6190 tss_selector = exit_qualification;
6191
64a7ec06
GN
6192 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6193 type != INTR_TYPE_EXT_INTR &&
6194 type != INTR_TYPE_NMI_INTR))
6195 skip_emulated_instruction(vcpu);
6196
7f3d35fd
KW
6197 if (kvm_task_switch(vcpu, tss_selector,
6198 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6199 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN
6200 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6201 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6202 vcpu->run->internal.ndata = 0;
42dbaa5a 6203 return 0;
acb54517 6204 }
42dbaa5a 6205
42dbaa5a
JK
6206 /*
6207 * TODO: What about debug traps on tss switch?
6208 * Are we supposed to inject them and update dr6?
6209 */
6210
6211 return 1;
37817f29
IE
6212}
6213
851ba692 6214static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 6215{
f9c617f6 6216 unsigned long exit_qualification;
1439442c 6217 gpa_t gpa;
4f5982a5 6218 u32 error_code;
1439442c 6219
f9c617f6 6220 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 6221
ae1e2d10
PB
6222 if (is_guest_mode(vcpu)
6223 && !(exit_qualification & EPT_VIOLATION_GVA_TRANSLATED)) {
6224 /*
6225 * Fix up exit_qualification according to whether guest
6226 * page table accesses are reads or writes.
6227 */
6228 u64 eptp = nested_ept_get_cr3(vcpu);
33251870 6229 if (!(eptp & VMX_EPT_AD_ENABLE_BIT))
ae1e2d10 6230 exit_qualification &= ~EPT_VIOLATION_ACC_WRITE;
1439442c
SY
6231 }
6232
0be9c7a8
GN
6233 /*
6234 * EPT violation happened while executing iret from NMI,
6235 * "blocked by NMI" bit has to be set before next VM entry.
6236 * There are errata that may cause this bit to not be set:
6237 * AAK134, BY25.
6238 */
bcd1c294 6239 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
bcd1c294 6240 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN
6241 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6242
1439442c 6243 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 6244 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 6245
27959a44 6246 /* Is it a read fault? */
ab22a473 6247 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS
6248 ? PFERR_USER_MASK : 0;
6249 /* Is it a write fault? */
ab22a473 6250 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS
6251 ? PFERR_WRITE_MASK : 0;
6252 /* Is it a fetch fault? */
ab22a473 6253 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS
6254 ? PFERR_FETCH_MASK : 0;
6255 /* ept page table entry is present? */
6256 error_code |= (exit_qualification &
6257 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6258 EPT_VIOLATION_EXECUTABLE))
6259 ? PFERR_PRESENT_MASK : 0;
4f5982a5 6260
db1c056c 6261 vcpu->arch.gpa_available = true;
25d92081
YZ
6262 vcpu->arch.exit_qualification = exit_qualification;
6263
4f5982a5 6264 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY
6265}
6266
851ba692 6267static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 6268{
f735d4af 6269 int ret;
68f89400
MT
6270 gpa_t gpa;
6271
6272 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 6273 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 6274 trace_kvm_fast_mmio(gpa);
6affcbed 6275 return kvm_skip_emulated_instruction(vcpu);
68c3b4d1 6276 }
68f89400 6277
450869d6 6278 ret = handle_mmio_page_fault(vcpu, gpa, true);
db1c056c 6279 vcpu->arch.gpa_available = true;
b37fbea6 6280 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG
6281 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6282 EMULATE_DONE;
f8f55942
XG
6283
6284 if (unlikely(ret == RET_MMIO_PF_INVALID))
6285 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6286
b37fbea6 6287 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG
6288 return 1;
6289
6290 /* It is the real ept misconfig */
f735d4af 6291 WARN_ON(1);
68f89400 6292
851ba692
AK
6293 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6294 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT
6295
6296 return 0;
6297}
6298
851ba692 6299static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 6300{
47c0152e
PB
6301 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6302 CPU_BASED_VIRTUAL_NMI_PENDING);
f08864b4 6303 ++vcpu->stat.nmi_window_exits;
3842d135 6304 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY
6305
6306 return 1;
6307}
6308
80ced186 6309static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 6310{
8b3079a5
AK
6311 struct vcpu_vmx *vmx = to_vmx(vcpu);
6312 enum emulation_result err = EMULATE_DONE;
80ced186 6313 int ret = 1;
49e9d557
AK
6314 u32 cpu_exec_ctrl;
6315 bool intr_window_requested;
b8405c18 6316 unsigned count = 130;
49e9d557
AK
6317
6318 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6319 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 6320
98eb2f8b 6321 while (vmx->emulation_required && count-- != 0) {
bdea48e3 6322 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK
6323 return handle_interrupt_window(&vmx->vcpu);
6324
72875d8a 6325 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK
6326 return 1;
6327
991eebf9 6328 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 6329
ac0a48c3 6330 if (err == EMULATE_USER_EXIT) {
94452b9e 6331 ++vcpu->stat.mmio_exits;
80ced186
MG
6332 ret = 0;
6333 goto out;
6334 }
1d5a4d9b 6335
de5f70e0
AK
6336 if (err != EMULATE_DONE) {
6337 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6338 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6339 vcpu->run->internal.ndata = 0;
6d77dbfc 6340 return 0;
de5f70e0 6341 }
ea953ef0 6342
8d76c49e
GN
6343 if (vcpu->arch.halt_request) {
6344 vcpu->arch.halt_request = 0;
5cb56059 6345 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN
6346 goto out;
6347 }
6348
ea953ef0 6349 if (signal_pending(current))
80ced186 6350 goto out;
ea953ef0
MG
6351 if (need_resched())
6352 schedule();
6353 }
6354
80ced186
MG
6355out:
6356 return ret;
ea953ef0
MG
6357}
6358
b4a2d31d
RK
6359static int __grow_ple_window(int val)
6360{
6361 if (ple_window_grow < 1)
6362 return ple_window;
6363
6364 val = min(val, ple_window_actual_max);
6365
6366 if (ple_window_grow < ple_window)
6367 val *= ple_window_grow;
6368 else
6369 val += ple_window_grow;
6370
6371 return val;
6372}
6373
6374static int __shrink_ple_window(int val, int modifier, int minimum)
6375{
6376 if (modifier < 1)
6377 return ple_window;
6378
6379 if (modifier < ple_window)
6380 val /= modifier;
6381 else
6382 val -= modifier;
6383
6384 return max(val, minimum);
6385}
6386
6387static void grow_ple_window(struct kvm_vcpu *vcpu)
6388{
6389 struct vcpu_vmx *vmx = to_vmx(vcpu);
6390 int old = vmx->ple_window;
6391
6392 vmx->ple_window = __grow_ple_window(old);
6393
6394 if (vmx->ple_window != old)
6395 vmx->ple_window_dirty = true;
7b46268d
RK
6396
6397 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK
6398}
6399
6400static void shrink_ple_window(struct kvm_vcpu *vcpu)
6401{
6402 struct vcpu_vmx *vmx = to_vmx(vcpu);
6403 int old = vmx->ple_window;
6404
6405 vmx->ple_window = __shrink_ple_window(old,
6406 ple_window_shrink, ple_window);
6407
6408 if (vmx->ple_window != old)
6409 vmx->ple_window_dirty = true;
7b46268d
RK
6410
6411 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK
6412}
6413
6414/*
6415 * ple_window_actual_max is computed to be one grow_ple_window() below
6416 * ple_window_max. (See __grow_ple_window for the reason.)
6417 * This prevents overflows, because ple_window_max is int.
6418 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6419 * this process.
6420 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6421 */
6422static void update_ple_window_actual_max(void)
6423{
6424 ple_window_actual_max =
6425 __shrink_ple_window(max(ple_window_max, ple_window),
6426 ple_window_grow, INT_MIN);
6427}
6428
bf9f6ac8
FW
6429/*
6430 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6431 */
6432static void wakeup_handler(void)
6433{
6434 struct kvm_vcpu *vcpu;
6435 int cpu = smp_processor_id();
6436
6437 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6438 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6439 blocked_vcpu_list) {
6440 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6441
6442 if (pi_test_on(pi_desc) == 1)
6443 kvm_vcpu_kick(vcpu);
6444 }
6445 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6446}
6447
f160c7b7
JS
6448void vmx_enable_tdp(void)
6449{
6450 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6451 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6452 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6453 0ull, VMX_EPT_EXECUTABLE_MASK,
6454 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
312b616b 6455 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
f160c7b7
JS
6456
6457 ept_set_mmio_spte_mask();
6458 kvm_enable_tdp();
6459}
6460
f2c7648d
TC
6461static __init int hardware_setup(void)
6462{
34a1cd60
TC
6463 int r = -ENOMEM, i, msr;
6464
6465 rdmsrl_safe(MSR_EFER, &host_efer);
6466
6467 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6468 kvm_define_shared_msr(i, vmx_msr_index[i]);
6469
23611332
RK
6470 for (i = 0; i < VMX_BITMAP_NR; i++) {
6471 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6472 if (!vmx_bitmap[i])
6473 goto out;
6474 }
34a1cd60
TC
6475
6476 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
34a1cd60
TC
6477 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6478 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6479
6480 /*
6481 * Allow direct access to the PC debug port (it is often used for I/O
6482 * delays, but the vmexits simply slow things down).
6483 */
6484 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6485 clear_bit(0x80, vmx_io_bitmap_a);
6486
6487 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6488
6489 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6490 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6491
34a1cd60
TC
6492 if (setup_vmcs_config(&vmcs_config) < 0) {
6493 r = -EIO;
23611332 6494 goto out;
baa03522 6495 }
f2c7648d
TC
6496
6497 if (boot_cpu_has(X86_FEATURE_NX))
6498 kvm_enable_efer_bits(EFER_NX);
6499
08d839c4
WL
6500 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6501 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
f2c7648d 6502 enable_vpid = 0;
08d839c4 6503
f2c7648d
TC
6504 if (!cpu_has_vmx_shadow_vmcs())
6505 enable_shadow_vmcs = 0;
6506 if (enable_shadow_vmcs)
6507 init_vmcs_shadow_fields();
6508
6509 if (!cpu_has_vmx_ept() ||
6510 !cpu_has_vmx_ept_4levels()) {
6511 enable_ept = 0;
6512 enable_unrestricted_guest = 0;
6513 enable_ept_ad_bits = 0;
6514 }
6515
fce6ac4c 6516 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
f2c7648d
TC
6517 enable_ept_ad_bits = 0;
6518
6519 if (!cpu_has_vmx_unrestricted_guest())
6520 enable_unrestricted_guest = 0;
6521
ad15a296 6522 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC
6523 flexpriority_enabled = 0;
6524
ad15a296
PB
6525 /*
6526 * set_apic_access_page_addr() is used to reload apic access
6527 * page upon invalidation. No need to do anything if not
6528 * using the APIC_ACCESS_ADDR VMCS field.
6529 */
6530 if (!flexpriority_enabled)
f2c7648d 6531 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC
6532
6533 if (!cpu_has_vmx_tpr_shadow())
6534 kvm_x86_ops->update_cr8_intercept = NULL;
6535
6536 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6537 kvm_disable_largepages();
6538
6539 if (!cpu_has_vmx_ple())
6540 ple_gap = 0;
6541
76dfafd5 6542 if (!cpu_has_vmx_apicv()) {
f2c7648d 6543 enable_apicv = 0;
76dfafd5
PB
6544 kvm_x86_ops->sync_pir_to_irr = NULL;
6545 }
f2c7648d 6546
64903d61
HZ
6547 if (cpu_has_vmx_tsc_scaling()) {
6548 kvm_has_tsc_control = true;
6549 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6550 kvm_tsc_scaling_ratio_frac_bits = 48;
6551 }
6552
baa03522
TC
6553 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6554 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6555 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6556 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6557 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6558 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6559 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6560
c63e4563 6561 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
baa03522 6562 vmx_msr_bitmap_legacy, PAGE_SIZE);
c63e4563 6563 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
baa03522 6564 vmx_msr_bitmap_longmode, PAGE_SIZE);
c63e4563 6565 memcpy(vmx_msr_bitmap_legacy_x2apic,
f6e90f9e 6566 vmx_msr_bitmap_legacy, PAGE_SIZE);
c63e4563 6567 memcpy(vmx_msr_bitmap_longmode_x2apic,
f6e90f9e 6568 vmx_msr_bitmap_longmode, PAGE_SIZE);
baa03522 6569
04bb92e4
WL
6570 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6571
40d8338d
RK
6572 for (msr = 0x800; msr <= 0x8ff; msr++) {
6573 if (msr == 0x839 /* TMCCT */)
6574 continue;
2e69f865 6575 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
40d8338d 6576 }
3ce424e4 6577
f6e90f9e 6578 /*
2e69f865
RK
6579 * TPR reads and writes can be virtualized even if virtual interrupt
6580 * delivery is not in use.
f6e90f9e 6581 */
2e69f865
RK
6582 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6583 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
3ce424e4 6584
3ce424e4 6585 /* EOI */
2e69f865 6586 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
3ce424e4 6587 /* SELF-IPI */
2e69f865 6588 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
baa03522 6589
f160c7b7
JS
6590 if (enable_ept)
6591 vmx_enable_tdp();
6592 else
baa03522
TC
6593 kvm_disable_tdp();
6594
6595 update_ple_window_actual_max();
6596
843e4330
KH
6597 /*
6598 * Only enable PML when hardware supports PML feature, and both EPT
6599 * and EPT A/D bit features are enabled -- PML depends on them to work.
6600 */
6601 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6602 enable_pml = 0;
6603
6604 if (!enable_pml) {
6605 kvm_x86_ops->slot_enable_log_dirty = NULL;
6606 kvm_x86_ops->slot_disable_log_dirty = NULL;
6607 kvm_x86_ops->flush_log_dirty = NULL;
6608 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6609 }
6610
64672c95
YJ
6611 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6612 u64 vmx_msr;
6613
6614 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6615 cpu_preemption_timer_multi =
6616 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6617 } else {
6618 kvm_x86_ops->set_hv_timer = NULL;
6619 kvm_x86_ops->cancel_hv_timer = NULL;
6620 }
6621
bf9f6ac8
FW
6622 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6623
c45dcc71
AR
6624 kvm_mce_cap_supported |= MCG_LMCE_P;
6625
f2c7648d 6626 return alloc_kvm_area();
34a1cd60 6627
34a1cd60 6628out:
23611332
RK
6629 for (i = 0; i < VMX_BITMAP_NR; i++)
6630 free_page((unsigned long)vmx_bitmap[i]);
34a1cd60
TC
6631
6632 return r;
f2c7648d
TC
6633}
6634
6635static __exit void hardware_unsetup(void)
6636{
23611332
RK
6637 int i;
6638
6639 for (i = 0; i < VMX_BITMAP_NR; i++)
6640 free_page((unsigned long)vmx_bitmap[i]);
34a1cd60 6641
f2c7648d
TC
6642 free_kvm_area();
6643}
6644
4b8d54f9
ZE
6645/*
6646 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6647 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6648 */
9fb41ba8 6649static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6650{
b4a2d31d
RK
6651 if (ple_gap)
6652 grow_ple_window(vcpu);
6653
4b8d54f9 6654 kvm_vcpu_on_spin(vcpu);
6affcbed 6655 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE
6656}
6657
87c00572 6658static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6659{
6affcbed 6660 return kvm_skip_emulated_instruction(vcpu);
59708670
SY
6661}
6662
87c00572
GS
6663static int handle_mwait(struct kvm_vcpu *vcpu)
6664{
6665 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6666 return handle_nop(vcpu);
6667}
6668
5f3d45e7
MD
6669static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6670{
6671 return 1;
6672}
6673
87c00572
GS
6674static int handle_monitor(struct kvm_vcpu *vcpu)
6675{
6676 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6677 return handle_nop(vcpu);
6678}
6679
ff2f6fe9
NHE
6680/*
6681 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6682 * We could reuse a single VMCS for all the L2 guests, but we also want the
6683 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6684 * allows keeping them loaded on the processor, and in the future will allow
6685 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6686 * every entry if they never change.
6687 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6688 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6689 *
6690 * The following functions allocate and free a vmcs02 in this pool.
6691 */
6692
6693/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6694static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6695{
6696 struct vmcs02_list *item;
6697 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6698 if (item->vmptr == vmx->nested.current_vmptr) {
6699 list_move(&item->list, &vmx->nested.vmcs02_pool);
6700 return &item->vmcs02;
6701 }
6702
6703 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6704 /* Recycle the least recently used VMCS. */
d74c0e6b
GT
6705 item = list_last_entry(&vmx->nested.vmcs02_pool,
6706 struct vmcs02_list, list);
ff2f6fe9
NHE
6707 item->vmptr = vmx->nested.current_vmptr;
6708 list_move(&item->list, &vmx->nested.vmcs02_pool);
6709 return &item->vmcs02;
6710 }
6711
6712 /* Create a new VMCS */
0fa24ce3 6713 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE
6714 if (!item)
6715 return NULL;
6716 item->vmcs02.vmcs = alloc_vmcs();
355f4fb1 6717 item->vmcs02.shadow_vmcs = NULL;
ff2f6fe9
NHE
6718 if (!item->vmcs02.vmcs) {
6719 kfree(item);
6720 return NULL;
6721 }
6722 loaded_vmcs_init(&item->vmcs02);
6723 item->vmptr = vmx->nested.current_vmptr;
6724 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6725 vmx->nested.vmcs02_num++;
6726 return &item->vmcs02;
6727}
6728
6729/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6730static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6731{
6732 struct vmcs02_list *item;
6733 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6734 if (item->vmptr == vmptr) {
6735 free_loaded_vmcs(&item->vmcs02);
6736 list_del(&item->list);
6737 kfree(item);
6738 vmx->nested.vmcs02_num--;
6739 return;
6740 }
6741}
6742
6743/*
6744 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB
6745 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6746 * must be &vmx->vmcs01.
ff2f6fe9
NHE
6747 */
6748static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6749{
6750 struct vmcs02_list *item, *n;
4fa7734c
PB
6751
6752 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6753 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB
6754 /*
6755 * Something will leak if the above WARN triggers. Better than
6756 * a use-after-free.
6757 */
6758 if (vmx->loaded_vmcs == &item->vmcs02)
6759 continue;
6760
6761 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE
6762 list_del(&item->list);
6763 kfree(item);
4fa7734c 6764 vmx->nested.vmcs02_num--;
ff2f6fe9 6765 }
ff2f6fe9
NHE
6766}
6767
0658fbaa
ACL
6768/*
6769 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6770 * set the success or error code of an emulated VMX instruction, as specified
6771 * by Vol 2B, VMX Instruction Reference, "Conventions".
6772 */
6773static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6774{
6775 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6776 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6777 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6778}
6779
6780static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6781{
6782 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6783 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6784 X86_EFLAGS_SF | X86_EFLAGS_OF))
6785 | X86_EFLAGS_CF);
6786}
6787
145c28dd 6788static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL
6789 u32 vm_instruction_error)
6790{
6791 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6792 /*
6793 * failValid writes the error number to the current VMCS, which
6794 * can't be done there isn't a current VMCS.
6795 */
6796 nested_vmx_failInvalid(vcpu);
6797 return;
6798 }
6799 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6800 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6801 X86_EFLAGS_SF | X86_EFLAGS_OF))
6802 | X86_EFLAGS_ZF);
6803 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6804 /*
6805 * We don't need to force a shadow sync because
6806 * VM_INSTRUCTION_ERROR is not shadowed
6807 */
6808}
145c28dd 6809
ff651cb6
WV
6810static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6811{
6812 /* TODO: not to reset guest simply here. */
6813 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
bbe41b95 6814 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
ff651cb6
WV
6815}
6816
f4124500
JK
6817static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6818{
6819 struct vcpu_vmx *vmx =
6820 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6821
6822 vmx->nested.preemption_timer_expired = true;
6823 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6824 kvm_vcpu_kick(&vmx->vcpu);
6825
6826 return HRTIMER_NORESTART;
6827}
6828
19677e32
BD
6829/*
6830 * Decode the memory-address operand of a vmx instruction, as recorded on an
6831 * exit caused by such an instruction (run by a guest hypervisor).
6832 * On success, returns 0. When the operand is invalid, returns 1 and throws
6833 * #UD or #GP.
6834 */
6835static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6836 unsigned long exit_qualification,
f9eb4af6 6837 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6838{
f9eb4af6
EK
6839 gva_t off;
6840 bool exn;
6841 struct kvm_segment s;
6842
19677e32
BD
6843 /*
6844 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6845 * Execution", on an exit, vmx_instruction_info holds most of the
6846 * addressing components of the operand. Only the displacement part
6847 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6848 * For how an actual address is calculated from all these components,
6849 * refer to Vol. 1, "Operand Addressing".
6850 */
6851 int scaling = vmx_instruction_info & 3;
6852 int addr_size = (vmx_instruction_info >> 7) & 7;
6853 bool is_reg = vmx_instruction_info & (1u << 10);
6854 int seg_reg = (vmx_instruction_info >> 15) & 7;
6855 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6856 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6857 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6858 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6859
6860 if (is_reg) {
6861 kvm_queue_exception(vcpu, UD_VECTOR);
6862 return 1;
6863 }
6864
6865 /* Addr = segment_base + offset */
6866 /* offset = base + [index * scale] + displacement */
f9eb4af6 6867 off = exit_qualification; /* holds the displacement */
19677e32 6868 if (base_is_valid)
f9eb4af6 6869 off += kvm_register_read(vcpu, base_reg);
19677e32 6870 if (index_is_valid)
f9eb4af6
EK
6871 off += kvm_register_read(vcpu, index_reg)<<scaling;
6872 vmx_get_segment(vcpu, &s, seg_reg);
6873 *ret = s.base + off;
19677e32
BD
6874
6875 if (addr_size == 1) /* 32 bit */
6876 *ret &= 0xffffffff;
6877
f9eb4af6
EK
6878 /* Checks for #GP/#SS exceptions. */
6879 exn = false;
ff30ef40
QC
6880 if (is_long_mode(vcpu)) {
6881 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6882 * non-canonical form. This is the only check on the memory
6883 * destination for long mode!
6884 */
6885 exn = is_noncanonical_address(*ret);
6886 } else if (is_protmode(vcpu)) {
f9eb4af6
EK
6887 /* Protected mode: apply checks for segment validity in the
6888 * following order:
6889 * - segment type check (#GP(0) may be thrown)
6890 * - usability check (#GP(0)/#SS(0))
6891 * - limit check (#GP(0)/#SS(0))
6892 */
6893 if (wr)
6894 /* #GP(0) if the destination operand is located in a
6895 * read-only data segment or any code segment.
6896 */
6897 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6898 else
6899 /* #GP(0) if the source operand is located in an
6900 * execute-only code segment
6901 */
6902 exn = ((s.type & 0xa) == 8);
ff30ef40
QC
6903 if (exn) {
6904 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6905 return 1;
6906 }
f9eb4af6
EK
6907 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6908 */
6909 exn = (s.unusable != 0);
6910 /* Protected mode: #GP(0)/#SS(0) if the memory
6911 * operand is outside the segment limit.
6912 */
6913 exn = exn || (off + sizeof(u64) > s.limit);
6914 }
6915 if (exn) {
6916 kvm_queue_exception_e(vcpu,
6917 seg_reg == VCPU_SREG_SS ?
6918 SS_VECTOR : GP_VECTOR,
6919 0);
6920 return 1;
6921 }
6922
19677e32
BD
6923 return 0;
6924}
6925
cbf71279 6926static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
3573e22c
BD
6927{
6928 gva_t gva;
3573e22c 6929 struct x86_exception e;
3573e22c
BD
6930
6931 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 6932 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD
6933 return 1;
6934
cbf71279
RK
6935 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
6936 sizeof(*vmpointer), &e)) {
3573e22c
BD
6937 kvm_inject_page_fault(vcpu, &e);
6938 return 1;
6939 }
6940
3573e22c
BD
6941 return 0;
6942}
6943
e29acc55
JM
6944static int enter_vmx_operation(struct kvm_vcpu *vcpu)
6945{
6946 struct vcpu_vmx *vmx = to_vmx(vcpu);
6947 struct vmcs *shadow_vmcs;
6948
6949 if (cpu_has_vmx_msr_bitmap()) {
6950 vmx->nested.msr_bitmap =
6951 (unsigned long *)__get_free_page(GFP_KERNEL);
6952 if (!vmx->nested.msr_bitmap)
6953 goto out_msr_bitmap;
6954 }
6955
6956 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
6957 if (!vmx->nested.cached_vmcs12)
6958 goto out_cached_vmcs12;
6959
6960 if (enable_shadow_vmcs) {
6961 shadow_vmcs = alloc_vmcs();
6962 if (!shadow_vmcs)
6963 goto out_shadow_vmcs;
6964 /* mark vmcs as shadow */
6965 shadow_vmcs->revision_id |= (1u << 31);
6966 /* init shadow vmcs */
6967 vmcs_clear(shadow_vmcs);
6968 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
6969 }
6970
6971 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6972 vmx->nested.vmcs02_num = 0;
6973
6974 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6975 HRTIMER_MODE_REL_PINNED);
6976 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6977
6978 vmx->nested.vmxon = true;
6979 return 0;
6980
6981out_shadow_vmcs:
6982 kfree(vmx->nested.cached_vmcs12);
6983
6984out_cached_vmcs12:
6985 free_page((unsigned long)vmx->nested.msr_bitmap);
6986
6987out_msr_bitmap:
6988 return -ENOMEM;
6989}
6990
ec378aee
NHE
6991/*
6992 * Emulate the VMXON instruction.
6993 * Currently, we just remember that VMX is active, and do not save or even
6994 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6995 * do not currently need to store anything in that guest-allocated memory
6996 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6997 * argument is different from the VMXON pointer (which the spec says they do).
6998 */
6999static int handle_vmon(struct kvm_vcpu *vcpu)
7000{
e29acc55 7001 int ret;
cbf71279
RK
7002 gpa_t vmptr;
7003 struct page *page;
ec378aee 7004 struct vcpu_vmx *vmx = to_vmx(vcpu);
b3897a49
NHE
7005 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7006 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee 7007
70f3aac9
JM
7008 /*
7009 * The Intel VMX Instruction Reference lists a bunch of bits that are
7010 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7011 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7012 * Otherwise, we should fail with #UD. But most faulting conditions
7013 * have already been checked by hardware, prior to the VM-exit for
7014 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7015 * that bit set to 1 in non-root mode.
ec378aee 7016 */
70f3aac9 7017 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
ec378aee
NHE
7018 kvm_queue_exception(vcpu, UD_VECTOR);
7019 return 1;
7020 }
7021
145c28dd
AG
7022 if (vmx->nested.vmxon) {
7023 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6affcbed 7024 return kvm_skip_emulated_instruction(vcpu);
145c28dd 7025 }
b3897a49 7026
3b84080b 7027 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
b3897a49
NHE
7028 != VMXON_NEEDED_FEATURES) {
7029 kvm_inject_gp(vcpu, 0);
7030 return 1;
7031 }
7032
cbf71279 7033 if (nested_vmx_get_vmptr(vcpu, &vmptr))
21e7fbe7 7034 return 1;
cbf71279
RK
7035
7036 /*
7037 * SDM 3: 24.11.5
7038 * The first 4 bytes of VMXON region contain the supported
7039 * VMCS revision identifier
7040 *
7041 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7042 * which replaces physical address width with 32
7043 */
7044 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7045 nested_vmx_failInvalid(vcpu);
7046 return kvm_skip_emulated_instruction(vcpu);
7047 }
7048
7049 page = nested_get_page(vcpu, vmptr);
7050 if (page == NULL) {
7051 nested_vmx_failInvalid(vcpu);
7052 return kvm_skip_emulated_instruction(vcpu);
7053 }
7054 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7055 kunmap(page);
7056 nested_release_page_clean(page);
7057 nested_vmx_failInvalid(vcpu);
7058 return kvm_skip_emulated_instruction(vcpu);
7059 }
7060 kunmap(page);
7061 nested_release_page_clean(page);
7062
7063 vmx->nested.vmxon_ptr = vmptr;
e29acc55
JM
7064 ret = enter_vmx_operation(vcpu);
7065 if (ret)
7066 return ret;
ec378aee 7067
a25eb114 7068 nested_vmx_succeed(vcpu);
6affcbed 7069 return kvm_skip_emulated_instruction(vcpu);
ec378aee
NHE
7070}
7071
7072/*
7073 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7074 * for running VMX instructions (except VMXON, whose prerequisites are
7075 * slightly different). It also specifies what exception to inject otherwise.
70f3aac9
JM
7076 * Note that many of these exceptions have priority over VM exits, so they
7077 * don't have to be checked again here.
ec378aee
NHE
7078 */
7079static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7080{
70f3aac9 7081 if (!to_vmx(vcpu)->nested.vmxon) {
ec378aee
NHE
7082 kvm_queue_exception(vcpu, UD_VECTOR);
7083 return 0;
7084 }
ec378aee
NHE
7085 return 1;
7086}
7087
e7953d7f
AG
7088static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7089{
9a2a05b9
PB
7090 if (vmx->nested.current_vmptr == -1ull)
7091 return;
7092
7093 /* current_vmptr and current_vmcs12 are always set/reset together */
7094 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7095 return;
7096
012f83cb 7097 if (enable_shadow_vmcs) {
9a2a05b9
PB
7098 /* copy to memory all shadowed fields in case
7099 they were modified */
7100 copy_shadow_to_vmcs12(vmx);
7101 vmx->nested.sync_shadow_vmcs = false;
7ec36296
XG
7102 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7103 SECONDARY_EXEC_SHADOW_VMCS);
9a2a05b9 7104 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 7105 }
705699a1 7106 vmx->nested.posted_intr_nv = -1;
4f2777bc
DM
7107
7108 /* Flush VMCS12 to guest memory */
7109 memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7110 VMCS12_SIZE);
7111
e7953d7f
AG
7112 kunmap(vmx->nested.current_vmcs12_page);
7113 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB
7114 vmx->nested.current_vmptr = -1ull;
7115 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG
7116}
7117
ec378aee
NHE
7118/*
7119 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7120 * just stops using VMX.
7121 */
7122static void free_nested(struct vcpu_vmx *vmx)
7123{
7124 if (!vmx->nested.vmxon)
7125 return;
9a2a05b9 7126
ec378aee 7127 vmx->nested.vmxon = false;
5c614b35 7128 free_vpid(vmx->nested.vpid02);
9a2a05b9 7129 nested_release_vmcs12(vmx);
d048c098
RK
7130 if (vmx->nested.msr_bitmap) {
7131 free_page((unsigned long)vmx->nested.msr_bitmap);
7132 vmx->nested.msr_bitmap = NULL;
7133 }
355f4fb1
JM
7134 if (enable_shadow_vmcs) {
7135 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7136 free_vmcs(vmx->vmcs01.shadow_vmcs);
7137 vmx->vmcs01.shadow_vmcs = NULL;
7138 }
4f2777bc 7139 kfree(vmx->nested.cached_vmcs12);
fe3ef05c
NHE
7140 /* Unpin physical memory we referred to in current vmcs02 */
7141 if (vmx->nested.apic_access_page) {
7142 nested_release_page(vmx->nested.apic_access_page);
48d89b92 7143 vmx->nested.apic_access_page = NULL;
fe3ef05c 7144 }
a7c0b07d
WL
7145 if (vmx->nested.virtual_apic_page) {
7146 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 7147 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 7148 }
705699a1
WV
7149 if (vmx->nested.pi_desc_page) {
7150 kunmap(vmx->nested.pi_desc_page);
7151 nested_release_page(vmx->nested.pi_desc_page);
7152 vmx->nested.pi_desc_page = NULL;
7153 vmx->nested.pi_desc = NULL;
7154 }
ff2f6fe9
NHE
7155
7156 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE
7157}
7158
7159/* Emulate the VMXOFF instruction */
7160static int handle_vmoff(struct kvm_vcpu *vcpu)
7161{
7162 if (!nested_vmx_check_permission(vcpu))
7163 return 1;
7164 free_nested(to_vmx(vcpu));
a25eb114 7165 nested_vmx_succeed(vcpu);
6affcbed 7166 return kvm_skip_emulated_instruction(vcpu);
ec378aee
NHE
7167}
7168
27d6c865
NHE
7169/* Emulate the VMCLEAR instruction */
7170static int handle_vmclear(struct kvm_vcpu *vcpu)
7171{
7172 struct vcpu_vmx *vmx = to_vmx(vcpu);
587d7e72 7173 u32 zero = 0;
27d6c865 7174 gpa_t vmptr;
27d6c865
NHE
7175
7176 if (!nested_vmx_check_permission(vcpu))
7177 return 1;
7178
cbf71279 7179 if (nested_vmx_get_vmptr(vcpu, &vmptr))
27d6c865 7180 return 1;
27d6c865 7181
cbf71279
RK
7182 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7183 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7184 return kvm_skip_emulated_instruction(vcpu);
7185 }
7186
7187 if (vmptr == vmx->nested.vmxon_ptr) {
7188 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7189 return kvm_skip_emulated_instruction(vcpu);
7190 }
7191
9a2a05b9 7192 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 7193 nested_release_vmcs12(vmx);
27d6c865 7194
587d7e72
JM
7195 kvm_vcpu_write_guest(vcpu,
7196 vmptr + offsetof(struct vmcs12, launch_state),
7197 &zero, sizeof(zero));
27d6c865
NHE
7198
7199 nested_free_vmcs02(vmx, vmptr);
7200
27d6c865 7201 nested_vmx_succeed(vcpu);
6affcbed 7202 return kvm_skip_emulated_instruction(vcpu);
27d6c865
NHE
7203}
7204
cd232ad0
NHE
7205static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7206
7207/* Emulate the VMLAUNCH instruction */
7208static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7209{
7210 return nested_vmx_run(vcpu, true);
7211}
7212
7213/* Emulate the VMRESUME instruction */
7214static int handle_vmresume(struct kvm_vcpu *vcpu)
7215{
7216
7217 return nested_vmx_run(vcpu, false);
7218}
7219
49f705c5
NHE
7220enum vmcs_field_type {
7221 VMCS_FIELD_TYPE_U16 = 0,
7222 VMCS_FIELD_TYPE_U64 = 1,
7223 VMCS_FIELD_TYPE_U32 = 2,
7224 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7225};
7226
7227static inline int vmcs_field_type(unsigned long field)
7228{
7229 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
7230 return VMCS_FIELD_TYPE_U32;
7231 return (field >> 13) & 0x3 ;
7232}
7233
7234static inline int vmcs_field_readonly(unsigned long field)
7235{
7236 return (((field >> 10) & 0x3) == 1);
7237}
7238
7239/*
7240 * Read a vmcs12 field. Since these can have varying lengths and we return
7241 * one type, we chose the biggest type (u64) and zero-extend the return value
7242 * to that size. Note that the caller, handle_vmread, might need to use only
7243 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7244 * 64-bit fields are to be returned).
7245 */
a2ae9df7
PB
7246static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7247 unsigned long field, u64 *ret)
49f705c5
NHE
7248{
7249 short offset = vmcs_field_to_offset(field);
7250 char *p;
7251
7252 if (offset < 0)
a2ae9df7 7253 return offset;
49f705c5
NHE
7254
7255 p = ((char *)(get_vmcs12(vcpu))) + offset;
7256
7257 switch (vmcs_field_type(field)) {
7258 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7259 *ret = *((natural_width *)p);
a2ae9df7 7260 return 0;
49f705c5
NHE
7261 case VMCS_FIELD_TYPE_U16:
7262 *ret = *((u16 *)p);
a2ae9df7 7263 return 0;
49f705c5
NHE
7264 case VMCS_FIELD_TYPE_U32:
7265 *ret = *((u32 *)p);
a2ae9df7 7266 return 0;
49f705c5
NHE
7267 case VMCS_FIELD_TYPE_U64:
7268 *ret = *((u64 *)p);
a2ae9df7 7269 return 0;
49f705c5 7270 default:
a2ae9df7
PB
7271 WARN_ON(1);
7272 return -ENOENT;
49f705c5
NHE
7273 }
7274}
7275
20b97fea 7276
a2ae9df7
PB
7277static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7278 unsigned long field, u64 field_value){
20b97fea
AG
7279 short offset = vmcs_field_to_offset(field);
7280 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7281 if (offset < 0)
a2ae9df7 7282 return offset;
20b97fea
AG
7283
7284 switch (vmcs_field_type(field)) {
7285 case VMCS_FIELD_TYPE_U16:
7286 *(u16 *)p = field_value;
a2ae9df7 7287 return 0;
20b97fea
AG
7288 case VMCS_FIELD_TYPE_U32:
7289 *(u32 *)p = field_value;
a2ae9df7 7290 return 0;
20b97fea
AG
7291 case VMCS_FIELD_TYPE_U64:
7292 *(u64 *)p = field_value;
a2ae9df7 7293 return 0;
20b97fea
AG
7294 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7295 *(natural_width *)p = field_value;
a2ae9df7 7296 return 0;
20b97fea 7297 default:
a2ae9df7
PB
7298 WARN_ON(1);
7299 return -ENOENT;
20b97fea
AG
7300 }
7301
7302}
7303
16f5b903
AG
7304static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7305{
7306 int i;
7307 unsigned long field;
7308 u64 field_value;
355f4fb1 7309 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
c2bae893
MK
7310 const unsigned long *fields = shadow_read_write_fields;
7311 const int num_fields = max_shadow_read_write_fields;
16f5b903 7312
282da870
JK
7313 preempt_disable();
7314
16f5b903
AG
7315 vmcs_load(shadow_vmcs);
7316
7317 for (i = 0; i < num_fields; i++) {
7318 field = fields[i];
7319 switch (vmcs_field_type(field)) {
7320 case VMCS_FIELD_TYPE_U16:
7321 field_value = vmcs_read16(field);
7322 break;
7323 case VMCS_FIELD_TYPE_U32:
7324 field_value = vmcs_read32(field);
7325 break;
7326 case VMCS_FIELD_TYPE_U64:
7327 field_value = vmcs_read64(field);
7328 break;
7329 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7330 field_value = vmcs_readl(field);
7331 break;
a2ae9df7
PB
7332 default:
7333 WARN_ON(1);
7334 continue;
16f5b903
AG
7335 }
7336 vmcs12_write_any(&vmx->vcpu, field, field_value);
7337 }
7338
7339 vmcs_clear(shadow_vmcs);
7340 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK
7341
7342 preempt_enable();
16f5b903
AG
7343}
7344
c3114420
AG
7345static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7346{
c2bae893
MK
7347 const unsigned long *fields[] = {
7348 shadow_read_write_fields,
7349 shadow_read_only_fields
c3114420 7350 };
c2bae893 7351 const int max_fields[] = {
c3114420
AG
7352 max_shadow_read_write_fields,
7353 max_shadow_read_only_fields
7354 };
7355 int i, q;
7356 unsigned long field;
7357 u64 field_value = 0;
355f4fb1 7358 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
c3114420
AG
7359
7360 vmcs_load(shadow_vmcs);
7361
c2bae893 7362 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG
7363 for (i = 0; i < max_fields[q]; i++) {
7364 field = fields[q][i];
7365 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7366
7367 switch (vmcs_field_type(field)) {
7368 case VMCS_FIELD_TYPE_U16:
7369 vmcs_write16(field, (u16)field_value);
7370 break;
7371 case VMCS_FIELD_TYPE_U32:
7372 vmcs_write32(field, (u32)field_value);
7373 break;
7374 case VMCS_FIELD_TYPE_U64:
7375 vmcs_write64(field, (u64)field_value);
7376 break;
7377 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7378 vmcs_writel(field, (long)field_value);
7379 break;
a2ae9df7
PB
7380 default:
7381 WARN_ON(1);
7382 break;
c3114420
AG
7383 }
7384 }
7385 }
7386
7387 vmcs_clear(shadow_vmcs);
7388 vmcs_load(vmx->loaded_vmcs->vmcs);
7389}
7390
49f705c5
NHE
7391/*
7392 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7393 * used before) all generate the same failure when it is missing.
7394 */
7395static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7396{
7397 struct vcpu_vmx *vmx = to_vmx(vcpu);
7398 if (vmx->nested.current_vmptr == -1ull) {
7399 nested_vmx_failInvalid(vcpu);
49f705c5
NHE
7400 return 0;
7401 }
7402 return 1;
7403}
7404
7405static int handle_vmread(struct kvm_vcpu *vcpu)
7406{
7407 unsigned long field;
7408 u64 field_value;
7409 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7410 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7411 gva_t gva = 0;
7412
eb277562 7413 if (!nested_vmx_check_permission(vcpu))
49f705c5
NHE
7414 return 1;
7415
6affcbed
KH
7416 if (!nested_vmx_check_vmcs12(vcpu))
7417 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7418
7419 /* Decode instruction info and find the field to read */
27e6fb5d 7420 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 7421 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 7422 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5 7423 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6affcbed 7424 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7425 }
7426 /*
7427 * Now copy part of this value to register or memory, as requested.
7428 * Note that the number of bits actually copied is 32 or 64 depending
7429 * on the guest's mode (32 or 64 bit), not on the given field's length.
7430 */
7431 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 7432 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE
7433 field_value);
7434 } else {
7435 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7436 vmx_instruction_info, true, &gva))
49f705c5 7437 return 1;
70f3aac9 7438 /* _system ok, as hardware has verified cpl=0 */
49f705c5
NHE
7439 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7440 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7441 }
7442
7443 nested_vmx_succeed(vcpu);
6affcbed 7444 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7445}
7446
7447
7448static int handle_vmwrite(struct kvm_vcpu *vcpu)
7449{
7450 unsigned long field;
7451 gva_t gva;
7452 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7453 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE
7454 /* The value to write might be 32 or 64 bits, depending on L1's long
7455 * mode, and eventually we need to write that into a field of several
7456 * possible lengths. The code below first zero-extends the value to 64
6a6256f9 7457 * bit (field_value), and then copies only the appropriate number of
49f705c5
NHE
7458 * bits into the vmcs12 field.
7459 */
7460 u64 field_value = 0;
7461 struct x86_exception e;
7462
eb277562 7463 if (!nested_vmx_check_permission(vcpu))
49f705c5
NHE
7464 return 1;
7465
6affcbed
KH
7466 if (!nested_vmx_check_vmcs12(vcpu))
7467 return kvm_skip_emulated_instruction(vcpu);
eb277562 7468
49f705c5 7469 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7470 field_value = kvm_register_readl(vcpu,
49f705c5
NHE
7471 (((vmx_instruction_info) >> 3) & 0xf));
7472 else {
7473 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7474 vmx_instruction_info, false, &gva))
49f705c5
NHE
7475 return 1;
7476 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7477 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE
7478 kvm_inject_page_fault(vcpu, &e);
7479 return 1;
7480 }
7481 }
7482
7483
27e6fb5d 7484 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE
7485 if (vmcs_field_readonly(field)) {
7486 nested_vmx_failValid(vcpu,
7487 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6affcbed 7488 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7489 }
7490
a2ae9df7 7491 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5 7492 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6affcbed 7493 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7494 }
7495
7496 nested_vmx_succeed(vcpu);
6affcbed 7497 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7498}
7499
a8bc284e
JM
7500static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7501{
7502 vmx->nested.current_vmptr = vmptr;
7503 if (enable_shadow_vmcs) {
7504 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7505 SECONDARY_EXEC_SHADOW_VMCS);
7506 vmcs_write64(VMCS_LINK_POINTER,
7507 __pa(vmx->vmcs01.shadow_vmcs));
7508 vmx->nested.sync_shadow_vmcs = true;
7509 }
7510}
7511
63846663
NHE
7512/* Emulate the VMPTRLD instruction */
7513static int handle_vmptrld(struct kvm_vcpu *vcpu)
7514{
7515 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7516 gpa_t vmptr;
63846663
NHE
7517
7518 if (!nested_vmx_check_permission(vcpu))
7519 return 1;
7520
cbf71279 7521 if (nested_vmx_get_vmptr(vcpu, &vmptr))
63846663 7522 return 1;
63846663 7523
cbf71279
RK
7524 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7525 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7526 return kvm_skip_emulated_instruction(vcpu);
7527 }
7528
7529 if (vmptr == vmx->nested.vmxon_ptr) {
7530 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7531 return kvm_skip_emulated_instruction(vcpu);
7532 }
7533
63846663
NHE
7534 if (vmx->nested.current_vmptr != vmptr) {
7535 struct vmcs12 *new_vmcs12;
7536 struct page *page;
7537 page = nested_get_page(vcpu, vmptr);
7538 if (page == NULL) {
7539 nested_vmx_failInvalid(vcpu);
6affcbed 7540 return kvm_skip_emulated_instruction(vcpu);
63846663
NHE
7541 }
7542 new_vmcs12 = kmap(page);
7543 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7544 kunmap(page);
7545 nested_release_page_clean(page);
7546 nested_vmx_failValid(vcpu,
7547 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6affcbed 7548 return kvm_skip_emulated_instruction(vcpu);
63846663 7549 }
63846663 7550
9a2a05b9 7551 nested_release_vmcs12(vmx);
63846663
NHE
7552 vmx->nested.current_vmcs12 = new_vmcs12;
7553 vmx->nested.current_vmcs12_page = page;
4f2777bc
DM
7554 /*
7555 * Load VMCS12 from guest memory since it is not already
7556 * cached.
7557 */
7558 memcpy(vmx->nested.cached_vmcs12,
7559 vmx->nested.current_vmcs12, VMCS12_SIZE);
a8bc284e 7560 set_current_vmptr(vmx, vmptr);
63846663
NHE
7561 }
7562
7563 nested_vmx_succeed(vcpu);
6affcbed 7564 return kvm_skip_emulated_instruction(vcpu);
63846663
NHE
7565}
7566
6a4d7550
NHE
7567/* Emulate the VMPTRST instruction */
7568static int handle_vmptrst(struct kvm_vcpu *vcpu)
7569{
7570 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7571 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7572 gva_t vmcs_gva;
7573 struct x86_exception e;
7574
7575 if (!nested_vmx_check_permission(vcpu))
7576 return 1;
7577
7578 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7579 vmx_instruction_info, true, &vmcs_gva))
6a4d7550 7580 return 1;
70f3aac9 7581 /* ok to use *_system, as hardware has verified cpl=0 */
6a4d7550
NHE
7582 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7583 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7584 sizeof(u64), &e)) {
7585 kvm_inject_page_fault(vcpu, &e);
7586 return 1;
7587 }
7588 nested_vmx_succeed(vcpu);
6affcbed 7589 return kvm_skip_emulated_instruction(vcpu);
6a4d7550
NHE
7590}
7591
bfd0a56b
NHE
7592/* Emulate the INVEPT instruction */
7593static int handle_invept(struct kvm_vcpu *vcpu)
7594{
b9c237bb 7595 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE
7596 u32 vmx_instruction_info, types;
7597 unsigned long type;
7598 gva_t gva;
7599 struct x86_exception e;
7600 struct {
7601 u64 eptp, gpa;
7602 } operand;
bfd0a56b 7603
b9c237bb
WV
7604 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7605 SECONDARY_EXEC_ENABLE_EPT) ||
7606 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE
7607 kvm_queue_exception(vcpu, UD_VECTOR);
7608 return 1;
7609 }
7610
7611 if (!nested_vmx_check_permission(vcpu))
7612 return 1;
7613
bfd0a56b 7614 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7615 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7616
b9c237bb 7617 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b 7618
85c856b3 7619 if (type >= 32 || !(types & (1 << type))) {
bfd0a56b
NHE
7620 nested_vmx_failValid(vcpu,
7621 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7622 return kvm_skip_emulated_instruction(vcpu);
bfd0a56b
NHE
7623 }
7624
7625 /* According to the Intel VMX instruction reference, the memory
7626 * operand is read even if it isn't needed (e.g., for type==global)
7627 */
7628 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7629 vmx_instruction_info, false, &gva))
bfd0a56b
NHE
7630 return 1;
7631 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7632 sizeof(operand), &e)) {
7633 kvm_inject_page_fault(vcpu, &e);
7634 return 1;
7635 }
7636
7637 switch (type) {
bfd0a56b 7638 case VMX_EPT_EXTENT_GLOBAL:
45e11817
BD
7639 /*
7640 * TODO: track mappings and invalidate
7641 * single context requests appropriately
7642 */
7643 case VMX_EPT_EXTENT_CONTEXT:
bfd0a56b 7644 kvm_mmu_sync_roots(vcpu);
77c3913b 7645 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE
7646 nested_vmx_succeed(vcpu);
7647 break;
7648 default:
7649 BUG_ON(1);
7650 break;
7651 }
7652
6affcbed 7653 return kvm_skip_emulated_instruction(vcpu);
bfd0a56b
NHE
7654}
7655
a642fc30
PM
7656static int handle_invvpid(struct kvm_vcpu *vcpu)
7657{
99b83ac8
WL
7658 struct vcpu_vmx *vmx = to_vmx(vcpu);
7659 u32 vmx_instruction_info;
7660 unsigned long type, types;
7661 gva_t gva;
7662 struct x86_exception e;
7663 int vpid;
7664
7665 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7666 SECONDARY_EXEC_ENABLE_VPID) ||
7667 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7668 kvm_queue_exception(vcpu, UD_VECTOR);
7669 return 1;
7670 }
7671
7672 if (!nested_vmx_check_permission(vcpu))
7673 return 1;
7674
7675 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7676 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7677
bcdde302
JD
7678 types = (vmx->nested.nested_vmx_vpid_caps &
7679 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
99b83ac8 7680
85c856b3 7681 if (type >= 32 || !(types & (1 << type))) {
99b83ac8
WL
7682 nested_vmx_failValid(vcpu,
7683 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7684 return kvm_skip_emulated_instruction(vcpu);
99b83ac8
WL
7685 }
7686
7687 /* according to the intel vmx instruction reference, the memory
7688 * operand is read even if it isn't needed (e.g., for type==global)
7689 */
7690 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7691 vmx_instruction_info, false, &gva))
7692 return 1;
7693 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7694 sizeof(u32), &e)) {
7695 kvm_inject_page_fault(vcpu, &e);
7696 return 1;
7697 }
7698
7699 switch (type) {
bcdde302 7700 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
ef697a71 7701 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
bcdde302
JD
7702 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7703 if (!vpid) {
7704 nested_vmx_failValid(vcpu,
7705 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7706 return kvm_skip_emulated_instruction(vcpu);
bcdde302
JD
7707 }
7708 break;
99b83ac8 7709 case VMX_VPID_EXTENT_ALL_CONTEXT:
99b83ac8
WL
7710 break;
7711 default:
bcdde302 7712 WARN_ON_ONCE(1);
6affcbed 7713 return kvm_skip_emulated_instruction(vcpu);
99b83ac8
WL
7714 }
7715
bcdde302
JD
7716 __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7717 nested_vmx_succeed(vcpu);
7718
6affcbed 7719 return kvm_skip_emulated_instruction(vcpu);
a642fc30
PM
7720}
7721
843e4330
KH
7722static int handle_pml_full(struct kvm_vcpu *vcpu)
7723{
7724 unsigned long exit_qualification;
7725
7726 trace_kvm_pml_full(vcpu->vcpu_id);
7727
7728 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7729
7730 /*
7731 * PML buffer FULL happened while executing iret from NMI,
7732 * "blocked by NMI" bit has to be set before next VM entry.
7733 */
7734 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
843e4330
KH
7735 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7736 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7737 GUEST_INTR_STATE_NMI);
7738
7739 /*
7740 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7741 * here.., and there's no userspace involvement needed for PML.
7742 */
7743 return 1;
7744}
7745
64672c95
YJ
7746static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7747{
7748 kvm_lapic_expired_hv_timer(vcpu);
7749 return 1;
7750}
7751
6aa8b732
AK
7752/*
7753 * The exit handlers return 1 if the exit was handled fully and guest execution
7754 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7755 * to be done to userspace and return 0.
7756 */
772e0318 7757static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK
7758 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7759 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7760 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7761 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7762 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK
7763 [EXIT_REASON_CR_ACCESS] = handle_cr,
7764 [EXIT_REASON_DR_ACCESS] = handle_dr,
7765 [EXIT_REASON_CPUID] = handle_cpuid,
7766 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7767 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7768 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7769 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7770 [EXIT_REASON_INVD] = handle_invd,
a7052897 7771 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7772 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7773 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7774 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7775 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7776 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7777 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7778 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7779 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7780 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE
7781 [EXIT_REASON_VMOFF] = handle_vmoff,
7782 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY
7783 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7784 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7785 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7786 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7787 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7788 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7789 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7790 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT
7791 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7792 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7793 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7794 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7795 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7796 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7797 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7798 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL
7799 [EXIT_REASON_XSAVES] = handle_xsaves,
7800 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7801 [EXIT_REASON_PML_FULL] = handle_pml_full,
64672c95 7802 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
6aa8b732
AK
7803};
7804
7805static const int kvm_vmx_max_exit_handlers =
50a3485c 7806 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7807
908a7bdd
JK
7808static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7809 struct vmcs12 *vmcs12)
7810{
7811 unsigned long exit_qualification;
7812 gpa_t bitmap, last_bitmap;
7813 unsigned int port;
7814 int size;
7815 u8 b;
7816
908a7bdd 7817 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7818 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK
7819
7820 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7821
7822 port = exit_qualification >> 16;
7823 size = (exit_qualification & 7) + 1;
7824
7825 last_bitmap = (gpa_t)-1;
7826 b = -1;
7827
7828 while (size > 0) {
7829 if (port < 0x8000)
7830 bitmap = vmcs12->io_bitmap_a;
7831 else if (port < 0x10000)
7832 bitmap = vmcs12->io_bitmap_b;
7833 else
1d804d07 7834 return true;
908a7bdd
JK
7835 bitmap += (port & 0x7fff) / 8;
7836
7837 if (last_bitmap != bitmap)
54bf36aa 7838 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7839 return true;
908a7bdd 7840 if (b & (1 << (port & 7)))
1d804d07 7841 return true;
908a7bdd
JK
7842
7843 port++;
7844 size--;
7845 last_bitmap = bitmap;
7846 }
7847
1d804d07 7848 return false;
908a7bdd
JK
7849}
7850
644d711a
NHE
7851/*
7852 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7853 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7854 * disinterest in the current event (read or write a specific MSR) by using an
7855 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7856 */
7857static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7858 struct vmcs12 *vmcs12, u32 exit_reason)
7859{
7860 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7861 gpa_t bitmap;
7862
cbd29cb6 7863 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7864 return true;
644d711a
NHE
7865
7866 /*
7867 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7868 * for the four combinations of read/write and low/high MSR numbers.
7869 * First we need to figure out which of the four to use:
7870 */
7871 bitmap = vmcs12->msr_bitmap;
7872 if (exit_reason == EXIT_REASON_MSR_WRITE)
7873 bitmap += 2048;
7874 if (msr_index >= 0xc0000000) {
7875 msr_index -= 0xc0000000;
7876 bitmap += 1024;
7877 }
7878
7879 /* Then read the msr_index'th bit from this bitmap: */
7880 if (msr_index < 1024*8) {
7881 unsigned char b;
54bf36aa 7882 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7883 return true;
644d711a
NHE
7884 return 1 & (b >> (msr_index & 7));
7885 } else
1d804d07 7886 return true; /* let L1 handle the wrong parameter */
644d711a
NHE
7887}
7888
7889/*
7890 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7891 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7892 * intercept (via guest_host_mask etc.) the current event.
7893 */
7894static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7895 struct vmcs12 *vmcs12)
7896{
7897 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7898 int cr = exit_qualification & 15;
e1d39b17
JS
7899 int reg;
7900 unsigned long val;
644d711a
NHE
7901
7902 switch ((exit_qualification >> 4) & 3) {
7903 case 0: /* mov to cr */
e1d39b17
JS
7904 reg = (exit_qualification >> 8) & 15;
7905 val = kvm_register_readl(vcpu, reg);
644d711a
NHE
7906 switch (cr) {
7907 case 0:
7908 if (vmcs12->cr0_guest_host_mask &
7909 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7910 return true;
644d711a
NHE
7911 break;
7912 case 3:
7913 if ((vmcs12->cr3_target_count >= 1 &&
7914 vmcs12->cr3_target_value0 == val) ||
7915 (vmcs12->cr3_target_count >= 2 &&
7916 vmcs12->cr3_target_value1 == val) ||
7917 (vmcs12->cr3_target_count >= 3 &&
7918 vmcs12->cr3_target_value2 == val) ||
7919 (vmcs12->cr3_target_count >= 4 &&
7920 vmcs12->cr3_target_value3 == val))
1d804d07 7921 return false;
644d711a 7922 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7923 return true;
644d711a
NHE
7924 break;
7925 case 4:
7926 if (vmcs12->cr4_guest_host_mask &
7927 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7928 return true;
644d711a
NHE
7929 break;
7930 case 8:
7931 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7932 return true;
644d711a
NHE
7933 break;
7934 }
7935 break;
7936 case 2: /* clts */
7937 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7938 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7939 return true;
644d711a
NHE
7940 break;
7941 case 1: /* mov from cr */
7942 switch (cr) {
7943 case 3:
7944 if (vmcs12->cpu_based_vm_exec_control &
7945 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7946 return true;
644d711a
NHE
7947 break;
7948 case 8:
7949 if (vmcs12->cpu_based_vm_exec_control &
7950 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7951 return true;
644d711a
NHE
7952 break;
7953 }
7954 break;
7955 case 3: /* lmsw */
7956 /*
7957 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7958 * cr0. Other attempted changes are ignored, with no exit.
7959 */
e1d39b17 7960 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
644d711a
NHE
7961 if (vmcs12->cr0_guest_host_mask & 0xe &
7962 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7963 return true;
644d711a
NHE
7964 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7965 !(vmcs12->cr0_read_shadow & 0x1) &&
7966 (val & 0x1))
1d804d07 7967 return true;
644d711a
NHE
7968 break;
7969 }
1d804d07 7970 return false;
644d711a
NHE
7971}
7972
7973/*
7974 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7975 * should handle it ourselves in L0 (and then continue L2). Only call this
7976 * when in is_guest_mode (L2).
7977 */
7978static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7979{
644d711a
NHE
7980 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7981 struct vcpu_vmx *vmx = to_vmx(vcpu);
7982 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7983 u32 exit_reason = vmx->exit_reason;
644d711a 7984
542060ea
JK
7985 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7986 vmcs_readl(EXIT_QUALIFICATION),
7987 vmx->idt_vectoring_info,
7988 intr_info,
7989 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7990 KVM_ISA_VMX);
7991
644d711a 7992 if (vmx->nested.nested_run_pending)
1d804d07 7993 return false;
644d711a
NHE
7994
7995 if (unlikely(vmx->fail)) {
bd80158a
JK
7996 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7997 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 7998 return true;
644d711a
NHE
7999 }
8000
8001 switch (exit_reason) {
8002 case EXIT_REASON_EXCEPTION_NMI:
ef85b673 8003 if (is_nmi(intr_info))
1d804d07 8004 return false;
644d711a
NHE
8005 else if (is_page_fault(intr_info))
8006 return enable_ept;
e504c909 8007 else if (is_no_device(intr_info) &&
ccf9844e 8008 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 8009 return false;
6f05485d
JK
8010 else if (is_debug(intr_info) &&
8011 vcpu->guest_debug &
8012 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8013 return false;
8014 else if (is_breakpoint(intr_info) &&
8015 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8016 return false;
644d711a
NHE
8017 return vmcs12->exception_bitmap &
8018 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8019 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 8020 return false;
644d711a 8021 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 8022 return true;
644d711a 8023 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 8024 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 8025 case EXIT_REASON_NMI_WINDOW:
3b656cf7 8026 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 8027 case EXIT_REASON_TASK_SWITCH:
1d804d07 8028 return true;
644d711a 8029 case EXIT_REASON_CPUID:
1d804d07 8030 return true;
644d711a
NHE
8031 case EXIT_REASON_HLT:
8032 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8033 case EXIT_REASON_INVD:
1d804d07 8034 return true;
644d711a
NHE
8035 case EXIT_REASON_INVLPG:
8036 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8037 case EXIT_REASON_RDPMC:
8038 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
a5f46457
PB
8039 case EXIT_REASON_RDRAND:
8040 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8041 case EXIT_REASON_RDSEED:
8042 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
b3a2a907 8043 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE
8044 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8045 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8046 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8047 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8048 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8049 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 8050 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE
8051 /*
8052 * VMX instructions trap unconditionally. This allows L1 to
8053 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8054 */
1d804d07 8055 return true;
644d711a
NHE
8056 case EXIT_REASON_CR_ACCESS:
8057 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8058 case EXIT_REASON_DR_ACCESS:
8059 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8060 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 8061 return nested_vmx_exit_handled_io(vcpu, vmcs12);
1b07304c
PB
8062 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8063 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
644d711a
NHE
8064 case EXIT_REASON_MSR_READ:
8065 case EXIT_REASON_MSR_WRITE:
8066 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8067 case EXIT_REASON_INVALID_STATE:
1d804d07 8068 return true;
644d711a
NHE
8069 case EXIT_REASON_MWAIT_INSTRUCTION:
8070 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD
8071 case EXIT_REASON_MONITOR_TRAP_FLAG:
8072 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE
8073 case EXIT_REASON_MONITOR_INSTRUCTION:
8074 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8075 case EXIT_REASON_PAUSE_INSTRUCTION:
8076 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8077 nested_cpu_has2(vmcs12,
8078 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8079 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 8080 return false;
644d711a 8081 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 8082 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE
8083 case EXIT_REASON_APIC_ACCESS:
8084 return nested_cpu_has2(vmcs12,
8085 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 8086 case EXIT_REASON_APIC_WRITE:
608406e2
WV
8087 case EXIT_REASON_EOI_INDUCED:
8088 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 8089 return true;
644d711a 8090 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE
8091 /*
8092 * L0 always deals with the EPT violation. If nested EPT is
8093 * used, and the nested mmu code discovers that the address is
8094 * missing in the guest EPT table (EPT12), the EPT violation
8095 * will be injected with nested_ept_inject_page_fault()
8096 */
1d804d07 8097 return false;
644d711a 8098 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE
8099 /*
8100 * L2 never uses directly L1's EPT, but rather L0's own EPT
8101 * table (shadow on EPT) or a merged EPT table that L0 built
8102 * (EPT on EPT). So any problems with the structure of the
8103 * table is L0's fault.
8104 */
1d804d07 8105 return false;
644d711a
NHE
8106 case EXIT_REASON_WBINVD:
8107 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8108 case EXIT_REASON_XSETBV:
1d804d07 8109 return true;
81dc01f7
WL
8110 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8111 /*
8112 * This should never happen, since it is not possible to
8113 * set XSS to a non-zero value---neither in L1 nor in L2.
8114 * If if it were, XSS would have to be checked against
8115 * the XSS exit bitmap in vmcs12.
8116 */
8117 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
55123e3c
WL
8118 case EXIT_REASON_PREEMPTION_TIMER:
8119 return false;
ab007cc9 8120 case EXIT_REASON_PML_FULL:
03efce6f 8121 /* We emulate PML support to L1. */
ab007cc9 8122 return false;
644d711a 8123 default:
1d804d07 8124 return true;
644d711a
NHE
8125 }
8126}
8127
586f9607
AK
8128static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8129{
8130 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8131 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8132}
8133
a3eaa864 8134static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
843e4330 8135{
a3eaa864
KH
8136 if (vmx->pml_pg) {
8137 __free_page(vmx->pml_pg);
8138 vmx->pml_pg = NULL;
8139 }
843e4330
KH
8140}
8141
54bf36aa 8142static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 8143{
54bf36aa 8144 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH
8145 u64 *pml_buf;
8146 u16 pml_idx;
8147
8148 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8149
8150 /* Do nothing if PML buffer is empty */
8151 if (pml_idx == (PML_ENTITY_NUM - 1))
8152 return;
8153
8154 /* PML index always points to next available PML buffer entity */
8155 if (pml_idx >= PML_ENTITY_NUM)
8156 pml_idx = 0;
8157 else
8158 pml_idx++;
8159
8160 pml_buf = page_address(vmx->pml_pg);
8161 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8162 u64 gpa;
8163
8164 gpa = pml_buf[pml_idx];
8165 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 8166 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH
8167 }
8168
8169 /* reset PML index */
8170 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8171}
8172
8173/*
8174 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8175 * Called before reporting dirty_bitmap to userspace.
8176 */
8177static void kvm_flush_pml_buffers(struct kvm *kvm)
8178{
8179 int i;
8180 struct kvm_vcpu *vcpu;
8181 /*
8182 * We only need to kick vcpu out of guest mode here, as PML buffer
8183 * is flushed at beginning of all VMEXITs, and it's obvious that only
8184 * vcpus running in guest are possible to have unflushed GPAs in PML
8185 * buffer.
8186 */
8187 kvm_for_each_vcpu(i, vcpu, kvm)
8188 kvm_vcpu_kick(vcpu);
8189}
8190
4eb64dce
PB
8191static void vmx_dump_sel(char *name, uint32_t sel)
8192{
8193 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
96794e4e 8194 name, vmcs_read16(sel),
4eb64dce
PB
8195 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8196 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8197 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8198}
8199
8200static void vmx_dump_dtsel(char *name, uint32_t limit)
8201{
8202 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8203 name, vmcs_read32(limit),
8204 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8205}
8206
8207static void dump_vmcs(void)
8208{
8209 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8210 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8211 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8212 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8213 u32 secondary_exec_control = 0;
8214 unsigned long cr4 = vmcs_readl(GUEST_CR4);
f3531054 8215 u64 efer = vmcs_read64(GUEST_IA32_EFER);
4eb64dce
PB
8216 int i, n;
8217
8218 if (cpu_has_secondary_exec_ctrls())
8219 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8220
8221 pr_err("*** Guest State ***\n");
8222 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8223 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8224 vmcs_readl(CR0_GUEST_HOST_MASK));
8225 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8226 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8227 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8228 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8229 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8230 {
845c5b40
PB
8231 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8232 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8233 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8234 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
4eb64dce
PB
8235 }
8236 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8237 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8238 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8239 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8240 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8241 vmcs_readl(GUEST_SYSENTER_ESP),
8242 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8243 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8244 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8245 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8246 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8247 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8248 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8249 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8250 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8251 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8252 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8253 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8254 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
845c5b40
PB
8255 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8256 efer, vmcs_read64(GUEST_IA32_PAT));
8257 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8258 vmcs_read64(GUEST_IA32_DEBUGCTL),
4eb64dce
PB
8259 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8260 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
845c5b40
PB
8261 pr_err("PerfGlobCtl = 0x%016llx\n",
8262 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
4eb64dce 8263 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
845c5b40 8264 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
4eb64dce
PB
8265 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8266 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8267 vmcs_read32(GUEST_ACTIVITY_STATE));
8268 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8269 pr_err("InterruptStatus = %04x\n",
8270 vmcs_read16(GUEST_INTR_STATUS));
8271
8272 pr_err("*** Host State ***\n");
8273 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8274 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8275 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8276 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8277 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8278 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8279 vmcs_read16(HOST_TR_SELECTOR));
8280 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8281 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8282 vmcs_readl(HOST_TR_BASE));
8283 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8284 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8285 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8286 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8287 vmcs_readl(HOST_CR4));
8288 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8289 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8290 vmcs_read32(HOST_IA32_SYSENTER_CS),
8291 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8292 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
845c5b40
PB
8293 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8294 vmcs_read64(HOST_IA32_EFER),
8295 vmcs_read64(HOST_IA32_PAT));
4eb64dce 8296 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
845c5b40
PB
8297 pr_err("PerfGlobCtl = 0x%016llx\n",
8298 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
4eb64dce
PB
8299
8300 pr_err("*** Control State ***\n");
8301 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8302 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8303 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8304 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8305 vmcs_read32(EXCEPTION_BITMAP),
8306 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8307 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8308 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8309 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8310 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8311 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8312 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8313 vmcs_read32(VM_EXIT_INTR_INFO),
8314 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8315 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8316 pr_err(" reason=%08x qualification=%016lx\n",
8317 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8318 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8319 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8320 vmcs_read32(IDT_VECTORING_ERROR_CODE));
845c5b40 8321 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8cfe9866 8322 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
845c5b40
PB
8323 pr_err("TSC Multiplier = 0x%016llx\n",
8324 vmcs_read64(TSC_MULTIPLIER));
4eb64dce
PB
8325 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8326 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8327 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8328 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8329 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
845c5b40 8330 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
4eb64dce
PB
8331 n = vmcs_read32(CR3_TARGET_COUNT);
8332 for (i = 0; i + 1 < n; i += 4)
8333 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8334 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8335 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8336 if (i < n)
8337 pr_err("CR3 target%u=%016lx\n",
8338 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8339 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8340 pr_err("PLE Gap=%08x Window=%08x\n",
8341 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8342 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8343 pr_err("Virtual processor ID = 0x%04x\n",
8344 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8345}
8346
6aa8b732
AK
8347/*
8348 * The guest has exited. See if we can fix it or if we need userspace
8349 * assistance.
8350 */
851ba692 8351static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 8352{
29bd8a78 8353 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 8354 u32 exit_reason = vmx->exit_reason;
1155f76a 8355 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 8356
8b89fe1f 8357 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
db1c056c 8358 vcpu->arch.gpa_available = false;
8b89fe1f 8359
843e4330
KH
8360 /*
8361 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8362 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8363 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8364 * mode as if vcpus is in root mode, the PML buffer must has been
8365 * flushed already.
8366 */
8367 if (enable_pml)
54bf36aa 8368 vmx_flush_pml_buffer(vcpu);
843e4330 8369
80ced186 8370 /* If guest state is invalid, start emulating */
14168786 8371 if (vmx->emulation_required)
80ced186 8372 return handle_invalid_guest_state(vcpu);
1d5a4d9b 8373
644d711a 8374 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK
8375 nested_vmx_vmexit(vcpu, exit_reason,
8376 vmcs_read32(VM_EXIT_INTR_INFO),
8377 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE
8378 return 1;
8379 }
8380
5120702e 8381 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 8382 dump_vmcs();
5120702e
MG
8383 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8384 vcpu->run->fail_entry.hardware_entry_failure_reason
8385 = exit_reason;
8386 return 0;
8387 }
8388
29bd8a78 8389 if (unlikely(vmx->fail)) {
851ba692
AK
8390 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8391 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK
8392 = vmcs_read32(VM_INSTRUCTION_ERROR);
8393 return 0;
8394 }
6aa8b732 8395
b9bf6882
XG
8396 /*
8397 * Note:
8398 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8399 * delivery event since it indicates guest is accessing MMIO.
8400 * The vm-exit can be triggered again after return to guest that
8401 * will cause infinite loop.
8402 */
d77c26fc 8403 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 8404 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 8405 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b244c9fc 8406 exit_reason != EXIT_REASON_PML_FULL &&
b9bf6882
XG
8407 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8408 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8409 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8410 vcpu->run->internal.ndata = 2;
8411 vcpu->run->internal.data[0] = vectoring_info;
8412 vcpu->run->internal.data[1] = exit_reason;
8413 return 0;
8414 }
3b86cd99 8415
6aa8b732
AK
8416 if (exit_reason < kvm_vmx_max_exit_handlers
8417 && kvm_vmx_exit_handlers[exit_reason])
851ba692 8418 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 8419 else {
6c6c5e03
RK
8420 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8421 exit_reason);
2bc19dc3
MT
8422 kvm_queue_exception(vcpu, UD_VECTOR);
8423 return 1;
6aa8b732 8424 }
6aa8b732
AK
8425}
8426
95ba8273 8427static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 8428{
a7c0b07d
WL
8429 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8430
8431 if (is_guest_mode(vcpu) &&
8432 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8433 return;
8434
95ba8273 8435 if (irr == -1 || tpr < irr) {
6e5d865c
YS
8436 vmcs_write32(TPR_THRESHOLD, 0);
8437 return;
8438 }
8439
95ba8273 8440 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS
8441}
8442
8d14695f
YZ
8443static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8444{
8445 u32 sec_exec_control;
8446
dccbfcf5
RK
8447 /* Postpone execution until vmcs01 is the current VMCS. */
8448 if (is_guest_mode(vcpu)) {
8449 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8450 return;
8451 }
8452
f6e90f9e 8453 if (!cpu_has_vmx_virtualize_x2apic_mode())
8d14695f
YZ
8454 return;
8455
35754c98 8456 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ
8457 return;
8458
8459 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8460
8461 if (set) {
8462 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8463 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8464 } else {
8465 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8466 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
fb6c8198 8467 vmx_flush_tlb_ept_only(vcpu);
8d14695f
YZ
8468 }
8469 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8470
8471 vmx_set_msr_bitmap(vcpu);
8472}
8473
38b99173
TC
8474static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8475{
8476 struct vcpu_vmx *vmx = to_vmx(vcpu);
8477
8478 /*
8479 * Currently we do not handle the nested case where L2 has an
8480 * APIC access page of its own; that page is still pinned.
8481 * Hence, we skip the case where the VCPU is in guest mode _and_
8482 * L1 prepared an APIC access page for L2.
8483 *
8484 * For the case where L1 and L2 share the same APIC access page
8485 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8486 * in the vmcs12), this function will only update either the vmcs01
8487 * or the vmcs02. If the former, the vmcs02 will be updated by
8488 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8489 * the next L2->L1 exit.
8490 */
8491 if (!is_guest_mode(vcpu) ||
4f2777bc 8492 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
fb6c8198 8493 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
38b99173 8494 vmcs_write64(APIC_ACCESS_ADDR, hpa);
fb6c8198
JM
8495 vmx_flush_tlb_ept_only(vcpu);
8496 }
38b99173
TC
8497}
8498
67c9dddc 8499static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
c7c9c56c
YZ
8500{
8501 u16 status;
8502 u8 old;
8503
67c9dddc
PB
8504 if (max_isr == -1)
8505 max_isr = 0;
c7c9c56c
YZ
8506
8507 status = vmcs_read16(GUEST_INTR_STATUS);
8508 old = status >> 8;
67c9dddc 8509 if (max_isr != old) {
c7c9c56c 8510 status &= 0xff;
67c9dddc 8511 status |= max_isr << 8;
c7c9c56c
YZ
8512 vmcs_write16(GUEST_INTR_STATUS, status);
8513 }
8514}
8515
8516static void vmx_set_rvi(int vector)
8517{
8518 u16 status;
8519 u8 old;
8520
4114c27d
WW
8521 if (vector == -1)
8522 vector = 0;
8523
c7c9c56c
YZ
8524 status = vmcs_read16(GUEST_INTR_STATUS);
8525 old = (u8)status & 0xff;
8526 if ((u8)vector != old) {
8527 status &= ~0xff;
8528 status |= (u8)vector;
8529 vmcs_write16(GUEST_INTR_STATUS, status);
8530 }
8531}
8532
8533static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8534{
4114c27d
WW
8535 if (!is_guest_mode(vcpu)) {
8536 vmx_set_rvi(max_irr);
8537 return;
8538 }
8539
c7c9c56c
YZ
8540 if (max_irr == -1)
8541 return;
8542
963fee16 8543 /*
4114c27d
WW
8544 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8545 * handles it.
963fee16 8546 */
4114c27d 8547 if (nested_exit_on_intr(vcpu))
963fee16
WL
8548 return;
8549
963fee16 8550 /*
4114c27d 8551 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL
8552 * is run without virtual interrupt delivery.
8553 */
8554 if (!kvm_event_needs_reinjection(vcpu) &&
8555 vmx_interrupt_allowed(vcpu)) {
8556 kvm_queue_interrupt(vcpu, max_irr, false);
8557 vmx_inject_irq(vcpu);
8558 }
c7c9c56c
YZ
8559}
8560
76dfafd5 8561static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
810e6def
PB
8562{
8563 struct vcpu_vmx *vmx = to_vmx(vcpu);
76dfafd5 8564 int max_irr;
810e6def 8565
76dfafd5
PB
8566 WARN_ON(!vcpu->arch.apicv_active);
8567 if (pi_test_on(&vmx->pi_desc)) {
8568 pi_clear_on(&vmx->pi_desc);
8569 /*
8570 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8571 * But on x86 this is just a compiler barrier anyway.
8572 */
8573 smp_mb__after_atomic();
8574 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8575 } else {
8576 max_irr = kvm_lapic_find_highest_irr(vcpu);
8577 }
8578 vmx_hwapic_irr_update(vcpu, max_irr);
8579 return max_irr;
810e6def
PB
8580}
8581
6308630b 8582static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
c7c9c56c 8583{
d62caabb 8584 if (!kvm_vcpu_apicv_active(vcpu))
3d81bc7e
YZ
8585 return;
8586
c7c9c56c
YZ
8587 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8588 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8589 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8590 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8591}
8592
967235d3
PB
8593static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8594{
8595 struct vcpu_vmx *vmx = to_vmx(vcpu);
8596
8597 pi_clear_on(&vmx->pi_desc);
8598 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8599}
8600
51aa01d1 8601static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8602{
00eba012
AK
8603 u32 exit_intr_info;
8604
8605 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8606 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8607 return;
8608
c5ca8e57 8609 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 8610 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK
8611
8612 /* Handle machine checks before interrupts are enabled */
00eba012 8613 if (is_machine_check(exit_intr_info))
a0861c02
AK
8614 kvm_machine_check();
8615
20f65983 8616 /* We need to handle NMIs before interrupts are enabled */
ef85b673 8617 if (is_nmi(exit_intr_info)) {
ff9d07a0 8618 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8619 asm("int $2");
ff9d07a0
ZY
8620 kvm_after_handle_nmi(&vmx->vcpu);
8621 }
51aa01d1 8622}
20f65983 8623
a547c6db
YZ
8624static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8625{
8626 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3f62de5f 8627 register void *__sp asm(_ASM_SP);
a547c6db 8628
a547c6db
YZ
8629 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8630 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8631 unsigned int vector;
8632 unsigned long entry;
8633 gate_desc *desc;
8634 struct vcpu_vmx *vmx = to_vmx(vcpu);
8635#ifdef CONFIG_X86_64
8636 unsigned long tmp;
8637#endif
8638
8639 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8640 desc = (gate_desc *)vmx->host_idt_base + vector;
8641 entry = gate_offset(*desc);
8642 asm volatile(
8643#ifdef CONFIG_X86_64
8644 "mov %%" _ASM_SP ", %[sp]\n\t"
8645 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8646 "push $%c[ss]\n\t"
8647 "push %[sp]\n\t"
8648#endif
8649 "pushf\n\t"
a547c6db
YZ
8650 __ASM_SIZE(push) " $%c[cs]\n\t"
8651 "call *%[entry]\n\t"
8652 :
8653#ifdef CONFIG_X86_64
3f62de5f 8654 [sp]"=&r"(tmp),
a547c6db 8655#endif
3f62de5f 8656 "+r"(__sp)
a547c6db
YZ
8657 :
8658 [entry]"r"(entry),
8659 [ss]"i"(__KERNEL_DS),
8660 [cs]"i"(__KERNEL_CS)
8661 );
f2485b3e 8662 }
a547c6db
YZ
8663}
8664
6d396b55
PB
8665static bool vmx_has_high_real_mode_segbase(void)
8666{
8667 return enable_unrestricted_guest || emulate_invalid_guest_state;
8668}
8669
da8999d3
LJ
8670static bool vmx_mpx_supported(void)
8671{
8672 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8673 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8674}
8675
55412b2e
WL
8676static bool vmx_xsaves_supported(void)
8677{
8678 return vmcs_config.cpu_based_2nd_exec_ctrl &
8679 SECONDARY_EXEC_XSAVES;
8680}
8681
51aa01d1
AK
8682static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8683{
c5ca8e57 8684 u32 exit_intr_info;
51aa01d1
AK
8685 bool unblock_nmi;
8686 u8 vector;
8687 bool idtv_info_valid;
8688
8689 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8690
2c82878b
PB
8691 if (vmx->nmi_known_unmasked)
8692 return;
8693 /*
8694 * Can't use vmx->exit_intr_info since we're not sure what
8695 * the exit reason is.
8696 */
8697 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8698 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8699 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8700 /*
8701 * SDM 3: 27.7.1.2 (September 2008)
8702 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8703 * a guest IRET fault.
8704 * SDM 3: 23.2.2 (September 2008)
8705 * Bit 12 is undefined in any of the following cases:
8706 * If the VM exit sets the valid bit in the IDT-vectoring
8707 * information field.
8708 * If the VM exit is due to a double fault.
8709 */
8710 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8711 vector != DF_VECTOR && !idtv_info_valid)
8712 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8713 GUEST_INTR_STATE_NMI);
8714 else
8715 vmx->nmi_known_unmasked =
8716 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8717 & GUEST_INTR_STATE_NMI);
51aa01d1
AK
8718}
8719
3ab66e8a 8720static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK
8721 u32 idt_vectoring_info,
8722 int instr_len_field,
8723 int error_code_field)
51aa01d1 8724{
51aa01d1
AK
8725 u8 vector;
8726 int type;
8727 bool idtv_info_valid;
8728
8729 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8730
3ab66e8a
JK
8731 vcpu->arch.nmi_injected = false;
8732 kvm_clear_exception_queue(vcpu);
8733 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN
8734
8735 if (!idtv_info_valid)
8736 return;
8737
3ab66e8a 8738 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8739
668f612f
AK
8740 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8741 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8742
64a7ec06 8743 switch (type) {
37b96e98 8744 case INTR_TYPE_NMI_INTR:
3ab66e8a 8745 vcpu->arch.nmi_injected = true;
668f612f 8746 /*
7b4a25cb 8747 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN
8748 * Clear bit "block by NMI" before VM entry if a NMI
8749 * delivery faulted.
668f612f 8750 */
3ab66e8a 8751 vmx_set_nmi_mask(vcpu, false);
37b96e98 8752 break;
37b96e98 8753 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8754 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN
8755 /* fall through */
8756 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8757 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8758 u32 err = vmcs_read32(error_code_field);
851eb667 8759 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8760 } else
851eb667 8761 kvm_requeue_exception(vcpu, vector);
37b96e98 8762 break;
66fd3f7f 8763 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8764 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8765 /* fall through */
37b96e98 8766 case INTR_TYPE_EXT_INTR:
3ab66e8a 8767 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN
8768 break;
8769 default:
8770 break;
f7d9238f 8771 }
cf393f75
AK
8772}
8773
83422e17
AK
8774static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8775{
3ab66e8a 8776 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK
8777 VM_EXIT_INSTRUCTION_LEN,
8778 IDT_VECTORING_ERROR_CODE);
8779}
8780
b463a6f7
AK
8781static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8782{
3ab66e8a 8783 __vmx_complete_interrupts(vcpu,
b463a6f7
AK
8784 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8785 VM_ENTRY_INSTRUCTION_LEN,
8786 VM_ENTRY_EXCEPTION_ERROR_CODE);
8787
8788 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8789}
8790
d7cd9796
GN
8791static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8792{
8793 int i, nr_msrs;
8794 struct perf_guest_switch_msr *msrs;
8795
8796 msrs = perf_guest_get_msrs(&nr_msrs);
8797
8798 if (!msrs)
8799 return;
8800
8801 for (i = 0; i < nr_msrs; i++)
8802 if (msrs[i].host == msrs[i].guest)
8803 clear_atomic_switch_msr(vmx, msrs[i].msr);
8804 else
8805 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8806 msrs[i].host);
8807}
8808
33365e7a 8809static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
64672c95
YJ
8810{
8811 struct vcpu_vmx *vmx = to_vmx(vcpu);
8812 u64 tscl;
8813 u32 delta_tsc;
8814
8815 if (vmx->hv_deadline_tsc == -1)
8816 return;
8817
8818 tscl = rdtsc();
8819 if (vmx->hv_deadline_tsc > tscl)
8820 /* sure to be 32 bit only because checked on set_hv_timer */
8821 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8822 cpu_preemption_timer_multi);
8823 else
8824 delta_tsc = 0;
8825
8826 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8827}
8828
a3b5ba49 8829static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8830{
a2fa3e9f 8831 struct vcpu_vmx *vmx = to_vmx(vcpu);
d6e41f11 8832 unsigned long debugctlmsr, cr3, cr4;
104f226b 8833
104f226b
AK
8834 /* Don't enter VMX if guest state is invalid, let the exit handler
8835 start emulation until we arrive back to a valid state */
14168786 8836 if (vmx->emulation_required)
104f226b
AK
8837 return;
8838
a7653ecd
RK
8839 if (vmx->ple_window_dirty) {
8840 vmx->ple_window_dirty = false;
8841 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8842 }
8843
012f83cb
AG
8844 if (vmx->nested.sync_shadow_vmcs) {
8845 copy_vmcs12_to_shadow(vmx);
8846 vmx->nested.sync_shadow_vmcs = false;
8847 }
8848
104f226b
AK
8849 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8850 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8851 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8852 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8853
d6e41f11
AL
8854 cr3 = __get_current_cr3_fast();
8855 if (unlikely(cr3 != vmx->host_state.vmcs_host_cr3)) {
8856 vmcs_writel(HOST_CR3, cr3);
8857 vmx->host_state.vmcs_host_cr3 = cr3;
8858 }
8859
1e02ce4c 8860 cr4 = cr4_read_shadow();
d974baa3
AL
8861 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8862 vmcs_writel(HOST_CR4, cr4);
8863 vmx->host_state.vmcs_host_cr4 = cr4;
8864 }
8865
104f226b
AK
8866 /* When single-stepping over STI and MOV SS, we must clear the
8867 * corresponding interruptibility bits in the guest state. Otherwise
8868 * vmentry fails as it then expects bit 14 (BS) in pending debug
8869 * exceptions being set, but that's not correct for the guest debugging
8870 * case. */
8871 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8872 vmx_set_interrupt_shadow(vcpu, 0);
8873
1be0e61c
XG
8874 if (vmx->guest_pkru_valid)
8875 __write_pkru(vmx->guest_pkru);
8876
d7cd9796 8877 atomic_switch_perf_msrs(vmx);
2a7921b7 8878 debugctlmsr = get_debugctlmsr();
d7cd9796 8879
64672c95
YJ
8880 vmx_arm_hv_timer(vcpu);
8881
d462b819 8882 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8883 asm(
6aa8b732 8884 /* Store host registers */
b188c81f
AK
8885 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8886 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8887 "push %%" _ASM_CX " \n\t"
8888 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8889 "je 1f \n\t"
b188c81f 8890 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8891 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8892 "1: \n\t"
d3edefc0 8893 /* Reload cr2 if changed */
b188c81f
AK
8894 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8895 "mov %%cr2, %%" _ASM_DX " \n\t"
8896 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8897 "je 2f \n\t"
b188c81f 8898 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8899 "2: \n\t"
6aa8b732 8900 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8901 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8902 /* Load guest registers. Don't clobber flags. */
b188c81f
AK
8903 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8904 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8905 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8906 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8907 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8908 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8909#ifdef CONFIG_X86_64
e08aa78a
AK
8910 "mov %c[r8](%0), %%r8 \n\t"
8911 "mov %c[r9](%0), %%r9 \n\t"
8912 "mov %c[r10](%0), %%r10 \n\t"
8913 "mov %c[r11](%0), %%r11 \n\t"
8914 "mov %c[r12](%0), %%r12 \n\t"
8915 "mov %c[r13](%0), %%r13 \n\t"
8916 "mov %c[r14](%0), %%r14 \n\t"
8917 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8918#endif
b188c81f 8919 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8920
6aa8b732 8921 /* Enter guest mode */
83287ea4 8922 "jne 1f \n\t"
4ecac3fd 8923 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK
8924 "jmp 2f \n\t"
8925 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8926 "2: "
6aa8b732 8927 /* Save guest registers, load host registers, keep flags */
b188c81f 8928 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8929 "pop %0 \n\t"
b188c81f
AK
8930 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8931 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8932 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8933 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8934 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8935 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8936 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8937#ifdef CONFIG_X86_64
e08aa78a
AK
8938 "mov %%r8, %c[r8](%0) \n\t"
8939 "mov %%r9, %c[r9](%0) \n\t"
8940 "mov %%r10, %c[r10](%0) \n\t"
8941 "mov %%r11, %c[r11](%0) \n\t"
8942 "mov %%r12, %c[r12](%0) \n\t"
8943 "mov %%r13, %c[r13](%0) \n\t"
8944 "mov %%r14, %c[r14](%0) \n\t"
8945 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8946#endif
b188c81f
AK
8947 "mov %%cr2, %%" _ASM_AX " \n\t"
8948 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8949
b188c81f 8950 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8951 "setbe %c[fail](%0) \n\t"
83287ea4
AK
8952 ".pushsection .rodata \n\t"
8953 ".global vmx_return \n\t"
8954 "vmx_return: " _ASM_PTR " 2b \n\t"
8955 ".popsection"
e08aa78a 8956 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8957 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8958 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8959 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX
8960 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8961 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8962 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8963 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8964 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8965 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8966 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8967#ifdef CONFIG_X86_64
ad312c7c
ZX
8968 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8969 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8970 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8971 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8972 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8973 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8974 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8975 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8976#endif
40712fae
AK
8977 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8978 [wordsize]"i"(sizeof(ulong))
c2036300
LV
8979 : "cc", "memory"
8980#ifdef CONFIG_X86_64
b188c81f 8981 , "rax", "rbx", "rdi", "rsi"
c2036300 8982 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK
8983#else
8984 , "eax", "ebx", "edi", "esi"
c2036300
LV
8985#endif
8986 );
6aa8b732 8987
2a7921b7
GN
8988 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8989 if (debugctlmsr)
8990 update_debugctlmsr(debugctlmsr);
8991
aa67f609
AK
8992#ifndef CONFIG_X86_64
8993 /*
8994 * The sysexit path does not restore ds/es, so we must set them to
8995 * a reasonable value ourselves.
8996 *
8997 * We can't defer this to vmx_load_host_state() since that function
8998 * may be executed in interrupt context, which saves and restore segments
8999 * around it, nullifying its effect.
9000 */
9001 loadsegment(ds, __USER_DS);
9002 loadsegment(es, __USER_DS);
9003#endif
9004
6de4f3ad 9005 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 9006 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 9007 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 9008 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 9009 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT
9010 vcpu->arch.regs_dirty = 0;
9011
1155f76a
AK
9012 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9013
d462b819 9014 vmx->loaded_vmcs->launched = 1;
1b6269db 9015
51aa01d1 9016 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1 9017
1be0e61c
XG
9018 /*
9019 * eager fpu is enabled if PKEY is supported and CR4 is switched
9020 * back on host, so it is safe to read guest PKRU from current
9021 * XSAVE.
9022 */
9023 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9024 vmx->guest_pkru = __read_pkru();
9025 if (vmx->guest_pkru != vmx->host_pkru) {
9026 vmx->guest_pkru_valid = true;
9027 __write_pkru(vmx->host_pkru);
9028 } else
9029 vmx->guest_pkru_valid = false;
9030 }
9031
e0b890d3
GN
9032 /*
9033 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9034 * we did not inject a still-pending event to L1 now because of
9035 * nested_run_pending, we need to re-enable this bit.
9036 */
9037 if (vmx->nested.nested_run_pending)
9038 kvm_make_request(KVM_REQ_EVENT, vcpu);
9039
9040 vmx->nested.nested_run_pending = 0;
9041
51aa01d1
AK
9042 vmx_complete_atomic_exit(vmx);
9043 vmx_recover_nmi_blocking(vmx);
cf393f75 9044 vmx_complete_interrupts(vmx);
6aa8b732
AK
9045}
9046
1279a6b1 9047static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
4fa7734c
PB
9048{
9049 struct vcpu_vmx *vmx = to_vmx(vcpu);
9050 int cpu;
9051
1279a6b1 9052 if (vmx->loaded_vmcs == vmcs)
4fa7734c
PB
9053 return;
9054
9055 cpu = get_cpu();
1279a6b1 9056 vmx->loaded_vmcs = vmcs;
4fa7734c
PB
9057 vmx_vcpu_put(vcpu);
9058 vmx_vcpu_load(vcpu, cpu);
9059 vcpu->cpu = cpu;
9060 put_cpu();
9061}
9062
2f1fe811
JM
9063/*
9064 * Ensure that the current vmcs of the logical processor is the
9065 * vmcs01 of the vcpu before calling free_nested().
9066 */
9067static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9068{
9069 struct vcpu_vmx *vmx = to_vmx(vcpu);
9070 int r;
9071
9072 r = vcpu_load(vcpu);
9073 BUG_ON(r);
1279a6b1 9074 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
2f1fe811
JM
9075 free_nested(vmx);
9076 vcpu_put(vcpu);
9077}
9078
6aa8b732
AK
9079static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9080{
fb3f0f51
RR
9081 struct vcpu_vmx *vmx = to_vmx(vcpu);
9082
843e4330 9083 if (enable_pml)
a3eaa864 9084 vmx_destroy_pml_buffer(vmx);
991e7a0e 9085 free_vpid(vmx->vpid);
4fa7734c 9086 leave_guest_mode(vcpu);
2f1fe811 9087 vmx_free_vcpu_nested(vcpu);
4fa7734c 9088 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR
9089 kfree(vmx->guest_msrs);
9090 kvm_vcpu_uninit(vcpu);
a4770347 9091 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK
9092}
9093
fb3f0f51 9094static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 9095{
fb3f0f51 9096 int err;
c16f862d 9097 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 9098 int cpu;
6aa8b732 9099
a2fa3e9f 9100 if (!vmx)
fb3f0f51
RR
9101 return ERR_PTR(-ENOMEM);
9102
991e7a0e 9103 vmx->vpid = allocate_vpid();
2384d2b3 9104
fb3f0f51
RR
9105 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9106 if (err)
9107 goto free_vcpu;
965b58a5 9108
4e59516a
PF
9109 err = -ENOMEM;
9110
9111 /*
9112 * If PML is turned on, failure on enabling PML just results in failure
9113 * of creating the vcpu, therefore we can simplify PML logic (by
9114 * avoiding dealing with cases, such as enabling PML partially on vcpus
9115 * for the guest, etc.
9116 */
9117 if (enable_pml) {
9118 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9119 if (!vmx->pml_pg)
9120 goto uninit_vcpu;
9121 }
9122
a2fa3e9f 9123 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB
9124 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9125 > PAGE_SIZE);
0123be42 9126
4e59516a
PF
9127 if (!vmx->guest_msrs)
9128 goto free_pml;
965b58a5 9129
d462b819
NHE
9130 vmx->loaded_vmcs = &vmx->vmcs01;
9131 vmx->loaded_vmcs->vmcs = alloc_vmcs();
355f4fb1 9132 vmx->loaded_vmcs->shadow_vmcs = NULL;
d462b819 9133 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 9134 goto free_msrs;
d462b819 9135 loaded_vmcs_init(vmx->loaded_vmcs);
a2fa3e9f 9136
15ad7146
AK
9137 cpu = get_cpu();
9138 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 9139 vmx->vcpu.cpu = cpu;
8b9cf98c 9140 err = vmx_vcpu_setup(vmx);
fb3f0f51 9141 vmx_vcpu_put(&vmx->vcpu);
15ad7146 9142 put_cpu();
fb3f0f51
RR
9143 if (err)
9144 goto free_vmcs;
35754c98 9145 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK
9146 err = alloc_apic_access_page(kvm);
9147 if (err)
5e4a0b3c 9148 goto free_vmcs;
a63cb560 9149 }
fb3f0f51 9150
b927a3ce
SY
9151 if (enable_ept) {
9152 if (!kvm->arch.ept_identity_map_addr)
9153 kvm->arch.ept_identity_map_addr =
9154 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC
9155 err = init_rmode_identity_map(kvm);
9156 if (err)
93ea5388 9157 goto free_vmcs;
b927a3ce 9158 }
b7ebfb05 9159
5c614b35 9160 if (nested) {
b9c237bb 9161 nested_vmx_setup_ctls_msrs(vmx);
5c614b35
WL
9162 vmx->nested.vpid02 = allocate_vpid();
9163 }
b9c237bb 9164
705699a1 9165 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE
9166 vmx->nested.current_vmptr = -1ull;
9167 vmx->nested.current_vmcs12 = NULL;
9168
37e4c997
HZ
9169 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9170
fb3f0f51
RR
9171 return &vmx->vcpu;
9172
9173free_vmcs:
5c614b35 9174 free_vpid(vmx->nested.vpid02);
5f3fbc34 9175 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 9176free_msrs:
fb3f0f51 9177 kfree(vmx->guest_msrs);
4e59516a
PF
9178free_pml:
9179 vmx_destroy_pml_buffer(vmx);
fb3f0f51
RR
9180uninit_vcpu:
9181 kvm_vcpu_uninit(&vmx->vcpu);
9182free_vcpu:
991e7a0e 9183 free_vpid(vmx->vpid);
a4770347 9184 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 9185 return ERR_PTR(err);
6aa8b732
AK
9186}
9187
002c7f7c
YS
9188static void __init vmx_check_processor_compat(void *rtn)
9189{
9190 struct vmcs_config vmcs_conf;
9191
9192 *(int *)rtn = 0;
9193 if (setup_vmcs_config(&vmcs_conf) < 0)
9194 *(int *)rtn = -EIO;
9195 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9196 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9197 smp_processor_id());
9198 *(int *)rtn = -EIO;
9199 }
9200}
9201
67253af5
SY
9202static int get_ept_level(void)
9203{
9204 return VMX_EPT_DEFAULT_GAW + 1;
9205}
9206
4b12f0de 9207static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 9208{
b18d5431
XG
9209 u8 cache;
9210 u64 ipat = 0;
4b12f0de 9211
522c68c4 9212 /* For VT-d and EPT combination
606decd6 9213 * 1. MMIO: always map as UC
522c68c4
SY
9214 * 2. EPT with VT-d:
9215 * a. VT-d without snooping control feature: can't guarantee the
606decd6 9216 * result, try to trust guest.
522c68c4
SY
9217 * b. VT-d with snooping control feature: snooping control feature of
9218 * VT-d engine can guarantee the cache correctness. Just set it
9219 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 9220 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY
9221 * consistent with host MTRR
9222 */
606decd6
PB
9223 if (is_mmio) {
9224 cache = MTRR_TYPE_UNCACHABLE;
9225 goto exit;
9226 }
9227
9228 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG
9229 ipat = VMX_EPT_IPAT_BIT;
9230 cache = MTRR_TYPE_WRBACK;
9231 goto exit;
9232 }
9233
9234 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9235 ipat = VMX_EPT_IPAT_BIT;
0da029ed 9236 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG
9237 cache = MTRR_TYPE_WRBACK;
9238 else
9239 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG
9240 goto exit;
9241 }
9242
ff53604b 9243 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG
9244
9245exit:
9246 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY
9247}
9248
17cc3935 9249static int vmx_get_lpage_level(void)
344f414f 9250{
878403b7
SY
9251 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9252 return PT_DIRECTORY_LEVEL;
9253 else
9254 /* For shadow and EPT supported 1GB page */
9255 return PT_PDPE_LEVEL;
344f414f
JR
9256}
9257
feda805f
XG
9258static void vmcs_set_secondary_exec_control(u32 new_ctl)
9259{
9260 /*
9261 * These bits in the secondary execution controls field
9262 * are dynamic, the others are mostly based on the hypervisor
9263 * architecture and the guest's CPUID. Do not touch the
9264 * dynamic bits.
9265 */
9266 u32 mask =
9267 SECONDARY_EXEC_SHADOW_VMCS |
9268 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9269 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9270
9271 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9272
9273 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9274 (new_ctl & ~mask) | (cur_ctl & mask));
9275}
9276
8322ebbb
DM
9277/*
9278 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9279 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9280 */
9281static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9282{
9283 struct vcpu_vmx *vmx = to_vmx(vcpu);
9284 struct kvm_cpuid_entry2 *entry;
9285
9286 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9287 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9288
9289#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9290 if (entry && (entry->_reg & (_cpuid_mask))) \
9291 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9292} while (0)
9293
9294 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9295 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
9296 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
9297 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
9298 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
9299 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
9300 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
9301 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
9302 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
9303 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
9304 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9305 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
9306 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
9307 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
9308 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
9309
9310 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9311 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
9312 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
9313 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
9314 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
9315 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9316 cr4_fixed1_update(bit(11), ecx, bit(2));
9317
9318#undef cr4_fixed1_update
9319}
9320
0e851880
SY
9321static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9322{
4e47c7a6
SY
9323 struct kvm_cpuid_entry2 *best;
9324 struct vcpu_vmx *vmx = to_vmx(vcpu);
feda805f 9325 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
4e47c7a6 9326
4e47c7a6 9327 if (vmx_rdtscp_supported()) {
1cea0ce6
XG
9328 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9329 if (!rdtscp_enabled)
feda805f 9330 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
f36201e5 9331
8b97265a 9332 if (nested) {
1cea0ce6 9333 if (rdtscp_enabled)
8b97265a
PB
9334 vmx->nested.nested_vmx_secondary_ctls_high |=
9335 SECONDARY_EXEC_RDTSCP;
9336 else
9337 vmx->nested.nested_vmx_secondary_ctls_high &=
9338 ~SECONDARY_EXEC_RDTSCP;
9339 }
4e47c7a6 9340 }
ad756a16 9341
ad756a16
MJ
9342 /* Exposing INVPCID only when PCID is exposed */
9343 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9344 if (vmx_invpcid_supported() &&
29541bb8
XG
9345 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9346 !guest_cpuid_has_pcid(vcpu))) {
feda805f 9347 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
29541bb8 9348
ad756a16 9349 if (best)
4f977045 9350 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 9351 }
8b3e34e4 9352
45bdbcfd
HH
9353 if (cpu_has_secondary_exec_ctrls())
9354 vmcs_set_secondary_exec_control(secondary_exec_ctl);
feda805f 9355
37e4c997
HZ
9356 if (nested_vmx_allowed(vcpu))
9357 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9358 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9359 else
9360 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9361 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
8322ebbb
DM
9362
9363 if (nested_vmx_allowed(vcpu))
9364 nested_vmx_cr_fixed1_bits_update(vcpu);
0e851880
SY
9365}
9366
d4330ef2
JR
9367static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9368{
7b8050f5
NHE
9369 if (func == 1 && nested)
9370 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR
9371}
9372
25d92081
YZ
9373static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9374 struct x86_exception *fault)
9375{
533558bc 9376 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
c5f983f6 9377 struct vcpu_vmx *vmx = to_vmx(vcpu);
533558bc 9378 u32 exit_reason;
c5f983f6 9379 unsigned long exit_qualification = vcpu->arch.exit_qualification;
25d92081 9380
c5f983f6
BD
9381 if (vmx->nested.pml_full) {
9382 exit_reason = EXIT_REASON_PML_FULL;
9383 vmx->nested.pml_full = false;
9384 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9385 } else if (fault->error_code & PFERR_RSVD_MASK)
533558bc 9386 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 9387 else
533558bc 9388 exit_reason = EXIT_REASON_EPT_VIOLATION;
c5f983f6
BD
9389
9390 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
25d92081
YZ
9391 vmcs12->guest_physical_address = fault->address;
9392}
9393
155a97a3
NHE
9394/* Callbacks for nested_ept_init_mmu_context: */
9395
9396static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9397{
9398 /* return the page table to be shadowed - in our case, EPT12 */
9399 return get_vmcs12(vcpu)->ept_pointer;
9400}
9401
ae1e2d10 9402static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 9403{
ae1e2d10
PB
9404 u64 eptp;
9405
ad896af0 9406 WARN_ON(mmu_is_nested(vcpu));
ae1e2d10
PB
9407 eptp = nested_ept_get_cr3(vcpu);
9408 if ((eptp & VMX_EPT_AD_ENABLE_BIT) && !enable_ept_ad_bits)
9409 return 1;
9410
9411 kvm_mmu_unload(vcpu);
ad896af0 9412 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb 9413 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
ae1e2d10
PB
9414 VMX_EPT_EXECUTE_ONLY_BIT,
9415 eptp & VMX_EPT_AD_ENABLE_BIT);
155a97a3
NHE
9416 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9417 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9418 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9419
9420 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
ae1e2d10 9421 return 0;
155a97a3
NHE
9422}
9423
9424static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9425{
9426 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9427}
9428
19d5f10b
EK
9429static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9430 u16 error_code)
9431{
9432 bool inequality, bit;
9433
9434 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9435 inequality =
9436 (error_code & vmcs12->page_fault_error_code_mask) !=
9437 vmcs12->page_fault_error_code_match;
9438 return inequality ^ bit;
9439}
9440
feaf0c7d
GN
9441static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9442 struct x86_exception *fault)
9443{
9444 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9445
9446 WARN_ON(!is_guest_mode(vcpu));
9447
19d5f10b 9448 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK
9449 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9450 vmcs_read32(VM_EXIT_INTR_INFO),
9451 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN
9452 else
9453 kvm_inject_page_fault(vcpu, fault);
9454}
9455
6beb7bd5
JM
9456static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9457 struct vmcs12 *vmcs12);
9458
9459static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
a2bcba50
WL
9460 struct vmcs12 *vmcs12)
9461{
9462 struct vcpu_vmx *vmx = to_vmx(vcpu);
6beb7bd5 9463 u64 hpa;
a2bcba50
WL
9464
9465 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a2bcba50
WL
9466 /*
9467 * Translate L1 physical address to host physical
9468 * address for vmcs02. Keep the page pinned, so this
9469 * physical address remains valid. We keep a reference
9470 * to it so we can release it later.
9471 */
9472 if (vmx->nested.apic_access_page) /* shouldn't happen */
9473 nested_release_page(vmx->nested.apic_access_page);
9474 vmx->nested.apic_access_page =
9475 nested_get_page(vcpu, vmcs12->apic_access_addr);
6beb7bd5
JM
9476 /*
9477 * If translation failed, no matter: This feature asks
9478 * to exit when accessing the given address, and if it
9479 * can never be accessed, this feature won't do
9480 * anything anyway.
9481 */
9482 if (vmx->nested.apic_access_page) {
9483 hpa = page_to_phys(vmx->nested.apic_access_page);
9484 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9485 } else {
9486 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9487 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9488 }
9489 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9490 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9491 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9492 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9493 kvm_vcpu_reload_apic_access_page(vcpu);
a2bcba50 9494 }
a7c0b07d
WL
9495
9496 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
a7c0b07d
WL
9497 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9498 nested_release_page(vmx->nested.virtual_apic_page);
9499 vmx->nested.virtual_apic_page =
9500 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9501
9502 /*
6beb7bd5
JM
9503 * If translation failed, VM entry will fail because
9504 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9505 * Failing the vm entry is _not_ what the processor
9506 * does but it's basically the only possibility we
9507 * have. We could still enter the guest if CR8 load
9508 * exits are enabled, CR8 store exits are enabled, and
9509 * virtualize APIC access is disabled; in this case
9510 * the processor would never use the TPR shadow and we
9511 * could simply clear the bit from the execution
9512 * control. But such a configuration is useless, so
9513 * let's keep the code simple.
a7c0b07d 9514 */
6beb7bd5
JM
9515 if (vmx->nested.virtual_apic_page) {
9516 hpa = page_to_phys(vmx->nested.virtual_apic_page);
9517 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9518 }
a7c0b07d
WL
9519 }
9520
705699a1 9521 if (nested_cpu_has_posted_intr(vmcs12)) {
705699a1
WV
9522 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9523 kunmap(vmx->nested.pi_desc_page);
9524 nested_release_page(vmx->nested.pi_desc_page);
9525 }
9526 vmx->nested.pi_desc_page =
9527 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
705699a1
WV
9528 vmx->nested.pi_desc =
9529 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9530 if (!vmx->nested.pi_desc) {
9531 nested_release_page_clean(vmx->nested.pi_desc_page);
6beb7bd5 9532 return;
705699a1
WV
9533 }
9534 vmx->nested.pi_desc =
9535 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9536 (unsigned long)(vmcs12->posted_intr_desc_addr &
9537 (PAGE_SIZE - 1)));
6beb7bd5
JM
9538 vmcs_write64(POSTED_INTR_DESC_ADDR,
9539 page_to_phys(vmx->nested.pi_desc_page) +
9540 (unsigned long)(vmcs12->posted_intr_desc_addr &
9541 (PAGE_SIZE - 1)));
705699a1 9542 }
6beb7bd5
JM
9543 if (cpu_has_vmx_msr_bitmap() &&
9544 nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9545 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9546 ;
9547 else
9548 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9549 CPU_BASED_USE_MSR_BITMAPS);
a2bcba50
WL
9550}
9551
f4124500
JK
9552static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9553{
9554 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9555 struct vcpu_vmx *vmx = to_vmx(vcpu);
9556
9557 if (vcpu->arch.virtual_tsc_khz == 0)
9558 return;
9559
9560 /* Make sure short timeouts reliably trigger an immediate vmexit.
9561 * hrtimer_start does not guarantee this. */
9562 if (preemption_timeout <= 1) {
9563 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9564 return;
9565 }
9566
9567 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9568 preemption_timeout *= 1000000;
9569 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9570 hrtimer_start(&vmx->nested.preemption_timer,
9571 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9572}
9573
3af18d9c
WV
9574static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9575 struct vmcs12 *vmcs12)
9576{
9577 int maxphyaddr;
9578 u64 addr;
9579
9580 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9581 return 0;
9582
9583 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9584 WARN_ON(1);
9585 return -EINVAL;
9586 }
9587 maxphyaddr = cpuid_maxphyaddr(vcpu);
9588
9589 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9590 ((addr + PAGE_SIZE) >> maxphyaddr))
9591 return -EINVAL;
9592
9593 return 0;
9594}
9595
9596/*
9597 * Merge L0's and L1's MSR bitmap, return false to indicate that
9598 * we do not use the hardware.
9599 */
9600static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9601 struct vmcs12 *vmcs12)
9602{
82f0dd4b 9603 int msr;
f2b93280 9604 struct page *page;
d048c098
RK
9605 unsigned long *msr_bitmap_l1;
9606 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
f2b93280 9607
d048c098 9608 /* This shortcut is ok because we support only x2APIC MSRs so far. */
f2b93280
WV
9609 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9610 return false;
9611
9612 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
05d8d346 9613 if (!page)
f2b93280 9614 return false;
d048c098 9615 msr_bitmap_l1 = (unsigned long *)kmap(page);
f2b93280 9616
d048c098
RK
9617 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9618
f2b93280 9619 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV
9620 if (nested_cpu_has_apic_reg_virt(vmcs12))
9621 for (msr = 0x800; msr <= 0x8ff; msr++)
9622 nested_vmx_disable_intercept_for_msr(
d048c098 9623 msr_bitmap_l1, msr_bitmap_l0,
82f0dd4b 9624 msr, MSR_TYPE_R);
d048c098
RK
9625
9626 nested_vmx_disable_intercept_for_msr(
9627 msr_bitmap_l1, msr_bitmap_l0,
f2b93280
WV
9628 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9629 MSR_TYPE_R | MSR_TYPE_W);
d048c098 9630
608406e2 9631 if (nested_cpu_has_vid(vmcs12)) {
608406e2 9632 nested_vmx_disable_intercept_for_msr(
d048c098 9633 msr_bitmap_l1, msr_bitmap_l0,
608406e2
WV
9634 APIC_BASE_MSR + (APIC_EOI >> 4),
9635 MSR_TYPE_W);
9636 nested_vmx_disable_intercept_for_msr(
d048c098 9637 msr_bitmap_l1, msr_bitmap_l0,
608406e2
WV
9638 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9639 MSR_TYPE_W);
9640 }
82f0dd4b 9641 }
f2b93280
WV
9642 kunmap(page);
9643 nested_release_page_clean(page);
9644
9645 return true;
9646}
9647
9648static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9649 struct vmcs12 *vmcs12)
9650{
82f0dd4b 9651 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 9652 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV
9653 !nested_cpu_has_vid(vmcs12) &&
9654 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV
9655 return 0;
9656
9657 /*
9658 * If virtualize x2apic mode is enabled,
9659 * virtualize apic access must be disabled.
9660 */
82f0dd4b
WV
9661 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9662 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV
9663 return -EINVAL;
9664
608406e2
WV
9665 /*
9666 * If virtual interrupt delivery is enabled,
9667 * we must exit on external interrupts.
9668 */
9669 if (nested_cpu_has_vid(vmcs12) &&
9670 !nested_exit_on_intr(vcpu))
9671 return -EINVAL;
9672
705699a1
WV
9673 /*
9674 * bits 15:8 should be zero in posted_intr_nv,
9675 * the descriptor address has been already checked
9676 * in nested_get_vmcs12_pages.
9677 */
9678 if (nested_cpu_has_posted_intr(vmcs12) &&
9679 (!nested_cpu_has_vid(vmcs12) ||
9680 !nested_exit_intr_ack_set(vcpu) ||
9681 vmcs12->posted_intr_nv & 0xff00))
9682 return -EINVAL;
9683
f2b93280
WV
9684 /* tpr shadow is needed by all apicv features. */
9685 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9686 return -EINVAL;
9687
9688 return 0;
3af18d9c
WV
9689}
9690
e9ac033e
EK
9691static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9692 unsigned long count_field,
92d71bc6 9693 unsigned long addr_field)
ff651cb6 9694{
92d71bc6 9695 int maxphyaddr;
e9ac033e
EK
9696 u64 count, addr;
9697
9698 if (vmcs12_read_any(vcpu, count_field, &count) ||
9699 vmcs12_read_any(vcpu, addr_field, &addr)) {
9700 WARN_ON(1);
9701 return -EINVAL;
9702 }
9703 if (count == 0)
9704 return 0;
92d71bc6 9705 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK
9706 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9707 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
bbe41b95 9708 pr_debug_ratelimited(
e9ac033e
EK
9709 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9710 addr_field, maxphyaddr, count, addr);
9711 return -EINVAL;
9712 }
9713 return 0;
9714}
9715
9716static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9717 struct vmcs12 *vmcs12)
9718{
e9ac033e
EK
9719 if (vmcs12->vm_exit_msr_load_count == 0 &&
9720 vmcs12->vm_exit_msr_store_count == 0 &&
9721 vmcs12->vm_entry_msr_load_count == 0)
9722 return 0; /* Fast path */
e9ac033e 9723 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9724 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9725 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9726 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9727 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9728 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK
9729 return -EINVAL;
9730 return 0;
9731}
9732
c5f983f6
BD
9733static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
9734 struct vmcs12 *vmcs12)
9735{
9736 u64 address = vmcs12->pml_address;
9737 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9738
9739 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
9740 if (!nested_cpu_has_ept(vmcs12) ||
9741 !IS_ALIGNED(address, 4096) ||
9742 address >> maxphyaddr)
9743 return -EINVAL;
9744 }
9745
9746 return 0;
9747}
9748
e9ac033e
EK
9749static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9750 struct vmx_msr_entry *e)
9751{
9752 /* x2APIC MSR accesses are not allowed */
8a9781f7 9753 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK
9754 return -EINVAL;
9755 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9756 e->index == MSR_IA32_UCODE_REV)
9757 return -EINVAL;
9758 if (e->reserved != 0)
ff651cb6
WV
9759 return -EINVAL;
9760 return 0;
9761}
9762
e9ac033e
EK
9763static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9764 struct vmx_msr_entry *e)
ff651cb6
WV
9765{
9766 if (e->index == MSR_FS_BASE ||
9767 e->index == MSR_GS_BASE ||
e9ac033e
EK
9768 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9769 nested_vmx_msr_check_common(vcpu, e))
9770 return -EINVAL;
9771 return 0;
9772}
9773
9774static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9775 struct vmx_msr_entry *e)
9776{
9777 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9778 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV
9779 return -EINVAL;
9780 return 0;
9781}
9782
9783/*
9784 * Load guest's/host's msr at nested entry/exit.
9785 * return 0 for success, entry index for failure.
9786 */
9787static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9788{
9789 u32 i;
9790 struct vmx_msr_entry e;
9791 struct msr_data msr;
9792
9793 msr.host_initiated = false;
9794 for (i = 0; i < count; i++) {
54bf36aa
PB
9795 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9796 &e, sizeof(e))) {
bbe41b95 9797 pr_debug_ratelimited(
e9ac033e
EK
9798 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9799 __func__, i, gpa + i * sizeof(e));
ff651cb6 9800 goto fail;
e9ac033e
EK
9801 }
9802 if (nested_vmx_load_msr_check(vcpu, &e)) {
bbe41b95 9803 pr_debug_ratelimited(
e9ac033e
EK
9804 "%s check failed (%u, 0x%x, 0x%x)\n",
9805 __func__, i, e.index, e.reserved);
9806 goto fail;
9807 }
ff651cb6
WV
9808 msr.index = e.index;
9809 msr.data = e.value;
e9ac033e 9810 if (kvm_set_msr(vcpu, &msr)) {
bbe41b95 9811 pr_debug_ratelimited(
e9ac033e
EK
9812 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9813 __func__, i, e.index, e.value);
ff651cb6 9814 goto fail;
e9ac033e 9815 }
ff651cb6
WV
9816 }
9817 return 0;
9818fail:
9819 return i + 1;
9820}
9821
9822static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9823{
9824 u32 i;
9825 struct vmx_msr_entry e;
9826
9827 for (i = 0; i < count; i++) {
609e36d3 9828 struct msr_data msr_info;
54bf36aa
PB
9829 if (kvm_vcpu_read_guest(vcpu,
9830 gpa + i * sizeof(e),
9831 &e, 2 * sizeof(u32))) {
bbe41b95 9832 pr_debug_ratelimited(
e9ac033e
EK
9833 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9834 __func__, i, gpa + i * sizeof(e));
ff651cb6 9835 return -EINVAL;
e9ac033e
EK
9836 }
9837 if (nested_vmx_store_msr_check(vcpu, &e)) {
bbe41b95 9838 pr_debug_ratelimited(
e9ac033e
EK
9839 "%s check failed (%u, 0x%x, 0x%x)\n",
9840 __func__, i, e.index, e.reserved);
ff651cb6 9841 return -EINVAL;
e9ac033e 9842 }
609e36d3
PB
9843 msr_info.host_initiated = false;
9844 msr_info.index = e.index;
9845 if (kvm_get_msr(vcpu, &msr_info)) {
bbe41b95 9846 pr_debug_ratelimited(
e9ac033e
EK
9847 "%s cannot read MSR (%u, 0x%x)\n",
9848 __func__, i, e.index);
9849 return -EINVAL;
9850 }
54bf36aa
PB
9851 if (kvm_vcpu_write_guest(vcpu,
9852 gpa + i * sizeof(e) +
9853 offsetof(struct vmx_msr_entry, value),
9854 &msr_info.data, sizeof(msr_info.data))) {
bbe41b95 9855 pr_debug_ratelimited(
e9ac033e 9856 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9857 __func__, i, e.index, msr_info.data);
e9ac033e
EK
9858 return -EINVAL;
9859 }
ff651cb6
WV
9860 }
9861 return 0;
9862}
9863
1dc35dac
LP
9864static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9865{
9866 unsigned long invalid_mask;
9867
9868 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9869 return (val & invalid_mask) == 0;
9870}
9871
9ed38ffa
LP
9872/*
9873 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9874 * emulating VM entry into a guest with EPT enabled.
9875 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9876 * is assigned to entry_failure_code on failure.
9877 */
9878static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
ca0bde28 9879 u32 *entry_failure_code)
9ed38ffa 9880{
9ed38ffa 9881 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
1dc35dac 9882 if (!nested_cr3_valid(vcpu, cr3)) {
9ed38ffa
LP
9883 *entry_failure_code = ENTRY_FAIL_DEFAULT;
9884 return 1;
9885 }
9886
9887 /*
9888 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9889 * must not be dereferenced.
9890 */
9891 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9892 !nested_ept) {
9893 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9894 *entry_failure_code = ENTRY_FAIL_PDPTE;
9895 return 1;
9896 }
9897 }
9898
9899 vcpu->arch.cr3 = cr3;
9900 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9901 }
9902
9903 kvm_mmu_reset_context(vcpu);
9904 return 0;
9905}
9906
fe3ef05c
NHE
9907/*
9908 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9909 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9910 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE
9911 * guest in a way that will both be appropriate to L1's requests, and our
9912 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9913 * function also has additional necessary side-effects, like setting various
9914 * vcpu->arch fields.
ee146c1c
LP
9915 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9916 * is assigned to entry_failure_code on failure.
fe3ef05c 9917 */
ee146c1c 9918static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
ca0bde28 9919 bool from_vmentry, u32 *entry_failure_code)
fe3ef05c
NHE
9920{
9921 struct vcpu_vmx *vmx = to_vmx(vcpu);
03efce6f 9922 u32 exec_control, vmcs12_exec_ctrl;
fe3ef05c
NHE
9923
9924 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9925 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9926 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9927 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9928 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9929 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9930 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9931 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9932 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9933 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9934 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9935 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9936 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9937 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9938 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9939 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9940 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9941 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9942 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9943 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9944 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9945 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9946 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9947 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9948 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9949 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9950 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9951 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9952 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9953 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9954 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9955 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9956 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9957 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9958 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9959 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9960
cf8b84f4
JM
9961 if (from_vmentry &&
9962 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
2996fca0
JK
9963 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9964 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9965 } else {
9966 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9967 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9968 }
cf8b84f4
JM
9969 if (from_vmentry) {
9970 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9971 vmcs12->vm_entry_intr_info_field);
9972 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9973 vmcs12->vm_entry_exception_error_code);
9974 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9975 vmcs12->vm_entry_instruction_len);
9976 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9977 vmcs12->guest_interruptibility_info);
9978 } else {
9979 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9980 }
fe3ef05c 9981 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9982 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE
9983 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9984 vmcs12->guest_pending_dbg_exceptions);
9985 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9986 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9987
81dc01f7
WL
9988 if (nested_cpu_has_xsaves(vmcs12))
9989 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE
9990 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9991
f4124500 9992 exec_control = vmcs12->pin_based_vm_exec_control;
9314006d
PB
9993
9994 /* Preemption timer setting is only taken from vmcs01. */
705699a1 9995 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9314006d
PB
9996 exec_control |= vmcs_config.pin_based_exec_ctrl;
9997 if (vmx->hv_deadline_tsc == -1)
9998 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
705699a1 9999
9314006d 10000 /* Posted interrupts setting is only taken from vmcs12. */
705699a1
WV
10001 if (nested_cpu_has_posted_intr(vmcs12)) {
10002 /*
10003 * Note that we use L0's vector here and in
10004 * vmx_deliver_nested_posted_interrupt.
10005 */
10006 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10007 vmx->nested.pi_pending = false;
0bcf261c 10008 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6beb7bd5 10009 } else {
705699a1 10010 exec_control &= ~PIN_BASED_POSTED_INTR;
6beb7bd5 10011 }
705699a1 10012
f4124500 10013 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 10014
f4124500
JK
10015 vmx->nested.preemption_timer_expired = false;
10016 if (nested_cpu_has_preemption_timer(vmcs12))
10017 vmx_start_preemption_timer(vcpu);
0238ea91 10018
fe3ef05c
NHE
10019 /*
10020 * Whether page-faults are trapped is determined by a combination of
10021 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10022 * If enable_ept, L0 doesn't care about page faults and we should
10023 * set all of these to L1's desires. However, if !enable_ept, L0 does
10024 * care about (at least some) page faults, and because it is not easy
10025 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10026 * to exit on each and every L2 page fault. This is done by setting
10027 * MASK=MATCH=0 and (see below) EB.PF=1.
10028 * Note that below we don't need special code to set EB.PF beyond the
10029 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10030 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10031 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10032 *
10033 * A problem with this approach (when !enable_ept) is that L1 may be
10034 * injected with more page faults than it asked for. This could have
10035 * caused problems, but in practice existing hypervisors don't care.
10036 * To fix this, we will need to emulate the PFEC checking (on the L1
10037 * page tables), using walk_addr(), when injecting PFs to L1.
10038 */
10039 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10040 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10041 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10042 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10043
10044 if (cpu_has_secondary_exec_ctrls()) {
f4124500 10045 exec_control = vmx_secondary_exec_control(vmx);
e2821620 10046
fe3ef05c 10047 /* Take the following fields only from vmcs12 */
696dfd95 10048 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 10049 SECONDARY_EXEC_RDTSCP |
696dfd95 10050 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
dfa169bb 10051 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c 10052 if (nested_cpu_has(vmcs12,
03efce6f
BD
10053 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10054 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10055 ~SECONDARY_EXEC_ENABLE_PML;
10056 exec_control |= vmcs12_exec_ctrl;
10057 }
fe3ef05c 10058
608406e2
WV
10059 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10060 vmcs_write64(EOI_EXIT_BITMAP0,
10061 vmcs12->eoi_exit_bitmap0);
10062 vmcs_write64(EOI_EXIT_BITMAP1,
10063 vmcs12->eoi_exit_bitmap1);
10064 vmcs_write64(EOI_EXIT_BITMAP2,
10065 vmcs12->eoi_exit_bitmap2);
10066 vmcs_write64(EOI_EXIT_BITMAP3,
10067 vmcs12->eoi_exit_bitmap3);
10068 vmcs_write16(GUEST_INTR_STATUS,
10069 vmcs12->guest_intr_status);
10070 }
10071
6beb7bd5
JM
10072 /*
10073 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10074 * nested_get_vmcs12_pages will either fix it up or
10075 * remove the VM execution control.
10076 */
10077 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10078 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10079
fe3ef05c
NHE
10080 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10081 }
10082
10083
10084 /*
10085 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10086 * Some constant fields are set here by vmx_set_constant_host_state().
10087 * Other fields are different per CPU, and will be set later when
10088 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10089 */
a547c6db 10090 vmx_set_constant_host_state(vmx);
fe3ef05c 10091
83bafef1
JM
10092 /*
10093 * Set the MSR load/store lists to match L0's settings.
10094 */
10095 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10096 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10097 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10098 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10099 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10100
fe3ef05c
NHE
10101 /*
10102 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10103 * entry, but only if the current (host) sp changed from the value
10104 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10105 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10106 * here we just force the write to happen on entry.
10107 */
10108 vmx->host_rsp = 0;
10109
10110 exec_control = vmx_exec_control(vmx); /* L0's desires */
10111 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10112 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10113 exec_control &= ~CPU_BASED_TPR_SHADOW;
10114 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d 10115
6beb7bd5
JM
10116 /*
10117 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10118 * nested_get_vmcs12_pages can't fix it up, the illegal value
10119 * will result in a VM entry failure.
10120 */
a7c0b07d 10121 if (exec_control & CPU_BASED_TPR_SHADOW) {
6beb7bd5 10122 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
a7c0b07d
WL
10123 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10124 }
10125
fe3ef05c 10126 /*
3af18d9c 10127 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE
10128 * Rather, exit every time.
10129 */
fe3ef05c
NHE
10130 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10131 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10132
10133 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10134
10135 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10136 * bitwise-or of what L1 wants to trap for L2, and what we want to
10137 * trap. Note that CR0.TS also needs updating - we do this later.
10138 */
10139 update_exception_bitmap(vcpu);
10140 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10141 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10142
8049d651
NHE
10143 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10144 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10145 * bits are further modified by vmx_set_efer() below.
10146 */
f4124500 10147 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE
10148
10149 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10150 * emulated by vmx_set_efer(), below.
10151 */
2961e876 10152 vm_entry_controls_init(vmx,
8049d651
NHE
10153 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10154 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE
10155 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10156
cf8b84f4
JM
10157 if (from_vmentry &&
10158 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
fe3ef05c 10159 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02 10160 vcpu->arch.pat = vmcs12->guest_ia32_pat;
cf8b84f4 10161 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 10162 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
cf8b84f4 10163 }
fe3ef05c
NHE
10164
10165 set_cr4_guest_host_mask(vmx);
10166
cf8b84f4
JM
10167 if (from_vmentry &&
10168 vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
36be0b9d
PB
10169 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10170
27fc51b2
NHE
10171 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10172 vmcs_write64(TSC_OFFSET,
ea26e4ec 10173 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
27fc51b2 10174 else
ea26e4ec 10175 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
c95ba92a
PF
10176 if (kvm_has_tsc_control)
10177 decache_tsc_multiplier(vmx);
fe3ef05c
NHE
10178
10179 if (enable_vpid) {
10180 /*
5c614b35
WL
10181 * There is no direct mapping between vpid02 and vpid12, the
10182 * vpid02 is per-vCPU for L0 and reused while the value of
10183 * vpid12 is changed w/ one invvpid during nested vmentry.
10184 * The vpid12 is allocated by L1 for L2, so it will not
10185 * influence global bitmap(for vpid01 and vpid02 allocation)
10186 * even if spawn a lot of nested vCPUs.
fe3ef05c 10187 */
5c614b35
WL
10188 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10189 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10190 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10191 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10192 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10193 }
10194 } else {
10195 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10196 vmx_flush_tlb(vcpu);
10197 }
10198
fe3ef05c
NHE
10199 }
10200
1fb883bb
LP
10201 if (enable_pml) {
10202 /*
10203 * Conceptually we want to copy the PML address and index from
10204 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10205 * since we always flush the log on each vmexit, this happens
10206 * to be equivalent to simply resetting the fields in vmcs02.
10207 */
10208 ASSERT(vmx->pml_pg);
10209 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10210 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10211 }
10212
155a97a3 10213 if (nested_cpu_has_ept(vmcs12)) {
ae1e2d10
PB
10214 if (nested_ept_init_mmu_context(vcpu)) {
10215 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10216 return 1;
10217 }
fb6c8198
JM
10218 } else if (nested_cpu_has2(vmcs12,
10219 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10220 vmx_flush_tlb_ept_only(vcpu);
155a97a3
NHE
10221 }
10222
fe3ef05c 10223 /*
bd7e5b08
PB
10224 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10225 * bits which we consider mandatory enabled.
fe3ef05c
NHE
10226 * The CR0_READ_SHADOW is what L2 should have expected to read given
10227 * the specifications by L1; It's not enough to take
10228 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10229 * have more bits than L1 expected.
10230 */
10231 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10232 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10233
10234 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10235 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10236
cf8b84f4
JM
10237 if (from_vmentry &&
10238 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
5a6a9748
DM
10239 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10240 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10241 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10242 else
10243 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10244 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10245 vmx_set_efer(vcpu, vcpu->arch.efer);
10246
9ed38ffa 10247 /* Shadow page tables on either EPT or shadow page tables. */
7ad658b6 10248 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
9ed38ffa
LP
10249 entry_failure_code))
10250 return 1;
7ca29de2 10251
feaf0c7d
GN
10252 if (!enable_ept)
10253 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10254
3633cfc3
NHE
10255 /*
10256 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10257 */
10258 if (enable_ept) {
10259 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10260 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10261 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10262 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10263 }
10264
fe3ef05c
NHE
10265 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10266 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
ee146c1c 10267 return 0;
fe3ef05c
NHE
10268}
10269
ca0bde28 10270static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
cd232ad0 10271{
cd232ad0 10272 struct vcpu_vmx *vmx = to_vmx(vcpu);
7c177938 10273
6dfacadd 10274 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
ca0bde28
JM
10275 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10276 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
26539bd0 10277
ca0bde28
JM
10278 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10279 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
7c177938 10280
ca0bde28
JM
10281 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10282 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
f2b93280 10283
ca0bde28
JM
10284 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10285 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
e9ac033e 10286
c5f983f6
BD
10287 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10288 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10289
7c177938 10290 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
0115f9cb 10291 vmx->nested.nested_vmx_procbased_ctls_low,
b9c237bb 10292 vmx->nested.nested_vmx_procbased_ctls_high) ||
2e5b0bd9
JM
10293 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10294 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10295 vmx->nested.nested_vmx_secondary_ctls_low,
10296 vmx->nested.nested_vmx_secondary_ctls_high)) ||
7c177938 10297 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV
10298 vmx->nested.nested_vmx_pinbased_ctls_low,
10299 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 10300 !vmx_control_verify(vmcs12->vm_exit_controls,
0115f9cb 10301 vmx->nested.nested_vmx_exit_ctls_low,
b9c237bb 10302 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 10303 !vmx_control_verify(vmcs12->vm_entry_controls,
0115f9cb 10304 vmx->nested.nested_vmx_entry_ctls_low,
b9c237bb 10305 vmx->nested.nested_vmx_entry_ctls_high))
ca0bde28 10306 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
7c177938 10307
c7c2c709
JM
10308 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10309 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10310
3899152c 10311 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
1dc35dac 10312 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
ca0bde28
JM
10313 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10314 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10315
10316 return 0;
10317}
10318
10319static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10320 u32 *exit_qual)
10321{
10322 bool ia32e;
10323
10324 *exit_qual = ENTRY_FAIL_DEFAULT;
7c177938 10325
3899152c 10326 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
ca0bde28 10327 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
b428018a 10328 return 1;
ca0bde28
JM
10329
10330 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10331 vmcs12->vmcs_link_pointer != -1ull) {
10332 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
b428018a 10333 return 1;
7c177938
NHE
10334 }
10335
384bb783 10336 /*
cb0c8cda 10337 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK
10338 * are performed on the field for the IA32_EFER MSR:
10339 * - Bits reserved in the IA32_EFER MSR must be 0.
10340 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10341 * the IA-32e mode guest VM-exit control. It must also be identical
10342 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10343 * CR0.PG) is 1.
10344 */
ca0bde28
JM
10345 if (to_vmx(vcpu)->nested.nested_run_pending &&
10346 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
384bb783
JK
10347 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10348 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10349 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10350 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
ca0bde28 10351 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
b428018a 10352 return 1;
384bb783
JK
10353 }
10354
10355 /*
10356 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10357 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10358 * the values of the LMA and LME bits in the field must each be that of
10359 * the host address-space size VM-exit control.
10360 */
10361 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10362 ia32e = (vmcs12->vm_exit_controls &
10363 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10364 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10365 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
ca0bde28 10366 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
b428018a 10367 return 1;
ca0bde28
JM
10368 }
10369
10370 return 0;
10371}
10372
858e25c0
JM
10373static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10374{
10375 struct vcpu_vmx *vmx = to_vmx(vcpu);
10376 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10377 struct loaded_vmcs *vmcs02;
858e25c0
JM
10378 u32 msr_entry_idx;
10379 u32 exit_qual;
10380
10381 vmcs02 = nested_get_current_vmcs02(vmx);
10382 if (!vmcs02)
10383 return -ENOMEM;
10384
10385 enter_guest_mode(vcpu);
10386
10387 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10388 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10389
1279a6b1 10390 vmx_switch_vmcs(vcpu, vmcs02);
858e25c0
JM
10391 vmx_segment_cache_clear(vmx);
10392
10393 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10394 leave_guest_mode(vcpu);
1279a6b1 10395 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
858e25c0
JM
10396 nested_vmx_entry_failure(vcpu, vmcs12,
10397 EXIT_REASON_INVALID_STATE, exit_qual);
10398 return 1;
10399 }
10400
10401 nested_get_vmcs12_pages(vcpu, vmcs12);
10402
10403 msr_entry_idx = nested_vmx_load_msr(vcpu,
10404 vmcs12->vm_entry_msr_load_addr,
10405 vmcs12->vm_entry_msr_load_count);
10406 if (msr_entry_idx) {
10407 leave_guest_mode(vcpu);
1279a6b1 10408 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
858e25c0
JM
10409 nested_vmx_entry_failure(vcpu, vmcs12,
10410 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10411 return 1;
10412 }
10413
10414 vmcs12->launch_state = 1;
10415
10416 /*
10417 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10418 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10419 * returned as far as L1 is concerned. It will only return (and set
10420 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10421 */
10422 return 0;
10423}
10424
ca0bde28
JM
10425/*
10426 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10427 * for running an L2 nested guest.
10428 */
10429static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10430{
10431 struct vmcs12 *vmcs12;
10432 struct vcpu_vmx *vmx = to_vmx(vcpu);
ca0bde28
JM
10433 u32 exit_qual;
10434 int ret;
10435
10436 if (!nested_vmx_check_permission(vcpu))
10437 return 1;
10438
10439 if (!nested_vmx_check_vmcs12(vcpu))
10440 goto out;
10441
10442 vmcs12 = get_vmcs12(vcpu);
10443
10444 if (enable_shadow_vmcs)
10445 copy_shadow_to_vmcs12(vmx);
10446
10447 /*
10448 * The nested entry process starts with enforcing various prerequisites
10449 * on vmcs12 as required by the Intel SDM, and act appropriately when
10450 * they fail: As the SDM explains, some conditions should cause the
10451 * instruction to fail, while others will cause the instruction to seem
10452 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10453 * To speed up the normal (success) code path, we should avoid checking
10454 * for misconfigurations which will anyway be caught by the processor
10455 * when using the merged vmcs02.
10456 */
10457 if (vmcs12->launch_state == launch) {
10458 nested_vmx_failValid(vcpu,
10459 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10460 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10461 goto out;
10462 }
10463
10464 ret = check_vmentry_prereqs(vcpu, vmcs12);
10465 if (ret) {
10466 nested_vmx_failValid(vcpu, ret);
10467 goto out;
10468 }
10469
10470 /*
10471 * After this point, the trap flag no longer triggers a singlestep trap
10472 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10473 * This is not 100% correct; for performance reasons, we delegate most
10474 * of the checks on host state to the processor. If those fail,
10475 * the singlestep trap is missed.
10476 */
10477 skip_emulated_instruction(vcpu);
10478
10479 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10480 if (ret) {
10481 nested_vmx_entry_failure(vcpu, vmcs12,
10482 EXIT_REASON_INVALID_STATE, exit_qual);
10483 return 1;
384bb783
JK
10484 }
10485
7c177938
NHE
10486 /*
10487 * We're finally done with prerequisite checking, and can start with
10488 * the nested entry.
10489 */
10490
858e25c0
JM
10491 ret = enter_vmx_non_root_mode(vcpu, true);
10492 if (ret)
10493 return ret;
ff651cb6 10494
6dfacadd 10495 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 10496 return kvm_vcpu_halt(vcpu);
6dfacadd 10497
7af40ad3
JK
10498 vmx->nested.nested_run_pending = 1;
10499
cd232ad0 10500 return 1;
eb277562
KH
10501
10502out:
6affcbed 10503 return kvm_skip_emulated_instruction(vcpu);
cd232ad0
NHE
10504}
10505
4704d0be
NHE
10506/*
10507 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10508 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10509 * This function returns the new value we should put in vmcs12.guest_cr0.
10510 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10511 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10512 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10513 * didn't trap the bit, because if L1 did, so would L0).
10514 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10515 * been modified by L2, and L1 knows it. So just leave the old value of
10516 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10517 * isn't relevant, because if L0 traps this bit it can set it to anything.
10518 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10519 * changed these bits, and therefore they need to be updated, but L0
10520 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10521 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10522 */
10523static inline unsigned long
10524vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10525{
10526 return
10527 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10528 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10529 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10530 vcpu->arch.cr0_guest_owned_bits));
10531}
10532
10533static inline unsigned long
10534vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10535{
10536 return
10537 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10538 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10539 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10540 vcpu->arch.cr4_guest_owned_bits));
10541}
10542
5f3d5799
JK
10543static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10544 struct vmcs12 *vmcs12)
10545{
10546 u32 idt_vectoring;
10547 unsigned int nr;
10548
851eb667 10549 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK
10550 nr = vcpu->arch.exception.nr;
10551 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10552
10553 if (kvm_exception_is_soft(nr)) {
10554 vmcs12->vm_exit_instruction_len =
10555 vcpu->arch.event_exit_inst_len;
10556 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10557 } else
10558 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10559
10560 if (vcpu->arch.exception.has_error_code) {
10561 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10562 vmcs12->idt_vectoring_error_code =
10563 vcpu->arch.exception.error_code;
10564 }
10565
10566 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 10567 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK
10568 vmcs12->idt_vectoring_info_field =
10569 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10570 } else if (vcpu->arch.interrupt.pending) {
10571 nr = vcpu->arch.interrupt.nr;
10572 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10573
10574 if (vcpu->arch.interrupt.soft) {
10575 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10576 vmcs12->vm_entry_instruction_len =
10577 vcpu->arch.event_exit_inst_len;
10578 } else
10579 idt_vectoring |= INTR_TYPE_EXT_INTR;
10580
10581 vmcs12->idt_vectoring_info_field = idt_vectoring;
10582 }
10583}
10584
b6b8a145
JK
10585static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10586{
10587 struct vcpu_vmx *vmx = to_vmx(vcpu);
10588
acc9ab60
WL
10589 if (vcpu->arch.exception.pending ||
10590 vcpu->arch.nmi_injected ||
10591 vcpu->arch.interrupt.pending)
10592 return -EBUSY;
10593
f4124500
JK
10594 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10595 vmx->nested.preemption_timer_expired) {
10596 if (vmx->nested.nested_run_pending)
10597 return -EBUSY;
10598 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10599 return 0;
10600 }
10601
b6b8a145 10602 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
acc9ab60 10603 if (vmx->nested.nested_run_pending)
b6b8a145
JK
10604 return -EBUSY;
10605 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10606 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10607 INTR_INFO_VALID_MASK, 0);
10608 /*
10609 * The NMI-triggered VM exit counts as injection:
10610 * clear this one and block further NMIs.
10611 */
10612 vcpu->arch.nmi_pending = 0;
10613 vmx_set_nmi_mask(vcpu, true);
10614 return 0;
10615 }
10616
10617 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10618 nested_exit_on_intr(vcpu)) {
10619 if (vmx->nested.nested_run_pending)
10620 return -EBUSY;
10621 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 10622 return 0;
b6b8a145
JK
10623 }
10624
6342c50a
DH
10625 vmx_complete_nested_posted_interrupt(vcpu);
10626 return 0;
b6b8a145
JK
10627}
10628
f4124500
JK
10629static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10630{
10631 ktime_t remaining =
10632 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10633 u64 value;
10634
10635 if (ktime_to_ns(remaining) <= 0)
10636 return 0;
10637
10638 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10639 do_div(value, 1000000);
10640 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10641}
10642
4704d0be 10643/*
cf8b84f4
JM
10644 * Update the guest state fields of vmcs12 to reflect changes that
10645 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10646 * VM-entry controls is also updated, since this is really a guest
10647 * state bit.)
4704d0be 10648 */
cf8b84f4 10649static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be 10650{
4704d0be
NHE
10651 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10652 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10653
4704d0be
NHE
10654 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10655 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10656 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10657
10658 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10659 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10660 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10661 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10662 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10663 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10664 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10665 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10666 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10667 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10668 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10669 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10670 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10671 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10672 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10673 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10674 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10675 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10676 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10677 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10678 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10679 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10680 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10681 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10682 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10683 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10684 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10685 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10686 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10687 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10688 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10689 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10690 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10691 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10692 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10693 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10694
4704d0be
NHE
10695 vmcs12->guest_interruptibility_info =
10696 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10697 vmcs12->guest_pending_dbg_exceptions =
10698 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK
10699 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10700 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10701 else
10702 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 10703
f4124500
JK
10704 if (nested_cpu_has_preemption_timer(vmcs12)) {
10705 if (vmcs12->vm_exit_controls &
10706 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10707 vmcs12->vmx_preemption_timer_value =
10708 vmx_get_preemption_timer_value(vcpu);
10709 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10710 }
7854cbca 10711
3633cfc3
NHE
10712 /*
10713 * In some cases (usually, nested EPT), L2 is allowed to change its
10714 * own CR3 without exiting. If it has changed it, we must keep it.
10715 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10716 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10717 *
10718 * Additionally, restore L2's PDPTR to vmcs12.
10719 */
10720 if (enable_ept) {
f3531054 10721 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
3633cfc3
NHE
10722 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10723 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10724 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10725 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10726 }
10727
119a9c01
JD
10728 if (nested_cpu_has_ept(vmcs12))
10729 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10730
608406e2
WV
10731 if (nested_cpu_has_vid(vmcs12))
10732 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10733
c18911a2
JK
10734 vmcs12->vm_entry_controls =
10735 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 10736 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 10737
2996fca0
JK
10738 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10739 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10740 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10741 }
10742
4704d0be
NHE
10743 /* TODO: These cannot have changed unless we have MSR bitmaps and
10744 * the relevant bit asks not to trap the change */
b8c07d55 10745 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 10746 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK
10747 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10748 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE
10749 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10750 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10751 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
a87036ad 10752 if (kvm_mpx_supported())
36be0b9d 10753 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL
10754 if (nested_cpu_has_xsaves(vmcs12))
10755 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
cf8b84f4
JM
10756}
10757
10758/*
10759 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10760 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10761 * and this function updates it to reflect the changes to the guest state while
10762 * L2 was running (and perhaps made some exits which were handled directly by L0
10763 * without going back to L1), and to reflect the exit reason.
10764 * Note that we do not have to copy here all VMCS fields, just those that
10765 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10766 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10767 * which already writes to vmcs12 directly.
10768 */
10769static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10770 u32 exit_reason, u32 exit_intr_info,
10771 unsigned long exit_qualification)
10772{
10773 /* update guest state fields: */
10774 sync_vmcs12(vcpu, vmcs12);
4704d0be
NHE
10775
10776 /* update exit information fields: */
10777
533558bc
JK
10778 vmcs12->vm_exit_reason = exit_reason;
10779 vmcs12->exit_qualification = exit_qualification;
4704d0be 10780
533558bc 10781 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK
10782 if ((vmcs12->vm_exit_intr_info &
10783 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10784 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10785 vmcs12->vm_exit_intr_error_code =
10786 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 10787 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE
10788 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10789 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10790
5f3d5799
JK
10791 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10792 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10793 * instead of reading the real value. */
4704d0be 10794 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK
10795
10796 /*
10797 * Transfer the event that L0 or L1 may wanted to inject into
10798 * L2 to IDT_VECTORING_INFO_FIELD.
10799 */
10800 vmcs12_save_pending_event(vcpu, vmcs12);
10801 }
10802
10803 /*
10804 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10805 * preserved above and would only end up incorrectly in L1.
10806 */
10807 vcpu->arch.nmi_injected = false;
10808 kvm_clear_exception_queue(vcpu);
10809 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE
10810}
10811
10812/*
10813 * A part of what we need to when the nested L2 guest exits and we want to
10814 * run its L1 parent, is to reset L1's guest state to the host state specified
10815 * in vmcs12.
10816 * This function is to be called not only on normal nested exit, but also on
10817 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10818 * Failures During or After Loading Guest State").
10819 * This function should be called when the active VMCS is L1's (vmcs01).
10820 */
733568f9
JK
10821static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10822 struct vmcs12 *vmcs12)
4704d0be 10823{
21feb4eb 10824 struct kvm_segment seg;
ca0bde28 10825 u32 entry_failure_code;
21feb4eb 10826
4704d0be
NHE
10827 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10828 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10829 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE
10830 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10831 else
10832 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10833 vmx_set_efer(vcpu, vcpu->arch.efer);
10834
10835 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10836 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10837 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE
10838 /*
10839 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
bd7e5b08
PB
10840 * actually changed, because vmx_set_cr0 refers to efer set above.
10841 *
10842 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10843 * (KVM doesn't change it);
4704d0be 10844 */
bd7e5b08 10845 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
9e3e4dbf 10846 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be 10847
bd7e5b08 10848 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
4704d0be
NHE
10849 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10850 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10851
29bf08f1 10852 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10853
1dc35dac
LP
10854 /*
10855 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10856 * couldn't have changed.
10857 */
10858 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10859 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
4704d0be 10860
feaf0c7d
GN
10861 if (!enable_ept)
10862 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10863
4704d0be
NHE
10864 if (enable_vpid) {
10865 /*
10866 * Trivially support vpid by letting L2s share their parent
10867 * L1's vpid. TODO: move to a more elaborate solution, giving
10868 * each L2 its own vpid and exposing the vpid feature to L1.
10869 */
10870 vmx_flush_tlb(vcpu);
10871 }
10872
10873
10874 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10875 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10876 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10877 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10878 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10879
36be0b9d
PB
10880 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10881 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10882 vmcs_write64(GUEST_BNDCFGS, 0);
10883
44811c02 10884 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10885 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK
10886 vcpu->arch.pat = vmcs12->host_ia32_pat;
10887 }
4704d0be
NHE
10888 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10889 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10890 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10891
21feb4eb
ACL
10892 /* Set L1 segment info according to Intel SDM
10893 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10894 seg = (struct kvm_segment) {
10895 .base = 0,
10896 .limit = 0xFFFFFFFF,
10897 .selector = vmcs12->host_cs_selector,
10898 .type = 11,
10899 .present = 1,
10900 .s = 1,
10901 .g = 1
10902 };
10903 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10904 seg.l = 1;
10905 else
10906 seg.db = 1;
10907 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10908 seg = (struct kvm_segment) {
10909 .base = 0,
10910 .limit = 0xFFFFFFFF,
10911 .type = 3,
10912 .present = 1,
10913 .s = 1,
10914 .db = 1,
10915 .g = 1
10916 };
10917 seg.selector = vmcs12->host_ds_selector;
10918 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10919 seg.selector = vmcs12->host_es_selector;
10920 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10921 seg.selector = vmcs12->host_ss_selector;
10922 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10923 seg.selector = vmcs12->host_fs_selector;
10924 seg.base = vmcs12->host_fs_base;
10925 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10926 seg.selector = vmcs12->host_gs_selector;
10927 seg.base = vmcs12->host_gs_base;
10928 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10929 seg = (struct kvm_segment) {
205befd9 10930 .base = vmcs12->host_tr_base,
21feb4eb
ACL
10931 .limit = 0x67,
10932 .selector = vmcs12->host_tr_selector,
10933 .type = 11,
10934 .present = 1
10935 };
10936 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10937
503cd0c5
JK
10938 kvm_set_dr(vcpu, 7, 0x400);
10939 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 10940
3af18d9c
WV
10941 if (cpu_has_vmx_msr_bitmap())
10942 vmx_set_msr_bitmap(vcpu);
10943
ff651cb6
WV
10944 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10945 vmcs12->vm_exit_msr_load_count))
10946 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE
10947}
10948
10949/*
10950 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10951 * and modify vmcs12 to make it see what it would expect to see there if
10952 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10953 */
533558bc
JK
10954static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10955 u32 exit_intr_info,
10956 unsigned long exit_qualification)
4704d0be
NHE
10957{
10958 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 10959 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
cf3215d9 10960 u32 vm_inst_error = 0;
4704d0be 10961
5f3d5799
JK
10962 /* trying to cancel vmlaunch/vmresume is a bug */
10963 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10964
4704d0be 10965 leave_guest_mode(vcpu);
533558bc
JK
10966 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10967 exit_qualification);
4704d0be 10968
ff651cb6
WV
10969 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10970 vmcs12->vm_exit_msr_store_count))
10971 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10972
cf3215d9
JM
10973 if (unlikely(vmx->fail))
10974 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
10975
1279a6b1 10976 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
f3380ca5 10977
77b0f5d6
BD
10978 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10979 && nested_exit_intr_ack_set(vcpu)) {
10980 int irq = kvm_cpu_get_interrupt(vcpu);
10981 WARN_ON(irq < 0);
10982 vmcs12->vm_exit_intr_info = irq |
10983 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10984 }
10985
542060ea
JK
10986 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10987 vmcs12->exit_qualification,
10988 vmcs12->idt_vectoring_info_field,
10989 vmcs12->vm_exit_intr_info,
10990 vmcs12->vm_exit_intr_error_code,
10991 KVM_ISA_VMX);
4704d0be 10992
8391ce44
PB
10993 vm_entry_controls_reset_shadow(vmx);
10994 vm_exit_controls_reset_shadow(vmx);
36c3cc42
JK
10995 vmx_segment_cache_clear(vmx);
10996
4704d0be
NHE
10997 /* if no vmcs02 cache requested, remove the one we used */
10998 if (VMCS02_POOL_SIZE == 0)
10999 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11000
11001 load_vmcs12_host_state(vcpu, vmcs12);
11002
9314006d 11003 /* Update any VMCS fields that might have changed while L2 ran */
83bafef1
JM
11004 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11005 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
ea26e4ec 11006 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
9314006d
PB
11007 if (vmx->hv_deadline_tsc == -1)
11008 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11009 PIN_BASED_VMX_PREEMPTION_TIMER);
11010 else
11011 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11012 PIN_BASED_VMX_PREEMPTION_TIMER);
c95ba92a
PF
11013 if (kvm_has_tsc_control)
11014 decache_tsc_multiplier(vmx);
4704d0be 11015
dccbfcf5
RK
11016 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11017 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11018 vmx_set_virtual_x2apic_mode(vcpu,
11019 vcpu->arch.apic_base & X2APIC_ENABLE);
fb6c8198
JM
11020 } else if (!nested_cpu_has_ept(vmcs12) &&
11021 nested_cpu_has2(vmcs12,
11022 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11023 vmx_flush_tlb_ept_only(vcpu);
dccbfcf5 11024 }
4704d0be
NHE
11025
11026 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11027 vmx->host_rsp = 0;
11028
11029 /* Unpin physical memory we referred to in vmcs02 */
11030 if (vmx->nested.apic_access_page) {
11031 nested_release_page(vmx->nested.apic_access_page);
48d89b92 11032 vmx->nested.apic_access_page = NULL;
4704d0be 11033 }
a7c0b07d
WL
11034 if (vmx->nested.virtual_apic_page) {
11035 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 11036 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 11037 }
705699a1
WV
11038 if (vmx->nested.pi_desc_page) {
11039 kunmap(vmx->nested.pi_desc_page);
11040 nested_release_page(vmx->nested.pi_desc_page);
11041 vmx->nested.pi_desc_page = NULL;
11042 vmx->nested.pi_desc = NULL;
11043 }
4704d0be 11044
38b99173
TC
11045 /*
11046 * We are now running in L2, mmu_notifier will force to reload the
11047 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11048 */
c83b6d15 11049 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
38b99173 11050
4704d0be
NHE
11051 /*
11052 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11053 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11054 * success or failure flag accordingly.
11055 */
11056 if (unlikely(vmx->fail)) {
11057 vmx->fail = 0;
cf3215d9 11058 nested_vmx_failValid(vcpu, vm_inst_error);
4704d0be
NHE
11059 } else
11060 nested_vmx_succeed(vcpu);
012f83cb
AG
11061 if (enable_shadow_vmcs)
11062 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK
11063
11064 /* in case we halted in L2 */
11065 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE
11066}
11067
42124925
JK
11068/*
11069 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11070 */
11071static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11072{
2f707d97
WL
11073 if (is_guest_mode(vcpu)) {
11074 to_vmx(vcpu)->nested.nested_run_pending = 0;
533558bc 11075 nested_vmx_vmexit(vcpu, -1, 0, 0);
2f707d97 11076 }
42124925
JK
11077 free_nested(to_vmx(vcpu));
11078}
11079
7c177938
NHE
11080/*
11081 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11082 * 23.7 "VM-entry failures during or after loading guest state" (this also
11083 * lists the acceptable exit-reason and exit-qualification parameters).
11084 * It should only be called before L2 actually succeeded to run, and when
11085 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11086 */
11087static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11088 struct vmcs12 *vmcs12,
11089 u32 reason, unsigned long qualification)
11090{
11091 load_vmcs12_host_state(vcpu, vmcs12);
11092 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11093 vmcs12->exit_qualification = qualification;
11094 nested_vmx_succeed(vcpu);
012f83cb
AG
11095 if (enable_shadow_vmcs)
11096 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE
11097}
11098
8a76d7f2
JR
11099static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11100 struct x86_instruction_info *info,
11101 enum x86_intercept_stage stage)
11102{
11103 return X86EMUL_CONTINUE;
11104}
11105
64672c95
YJ
11106#ifdef CONFIG_X86_64
11107/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11108static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11109 u64 divisor, u64 *result)
11110{
11111 u64 low = a << shift, high = a >> (64 - shift);
11112
11113 /* To avoid the overflow on divq */
11114 if (high >= divisor)
11115 return 1;
11116
11117 /* Low hold the result, high hold rem which is discarded */
11118 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11119 "rm" (divisor), "0" (low), "1" (high));
11120 *result = low;
11121
11122 return 0;
11123}
11124
11125static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11126{
11127 struct vcpu_vmx *vmx = to_vmx(vcpu);
9175d2e9
PB
11128 u64 tscl = rdtsc();
11129 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11130 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
64672c95
YJ
11131
11132 /* Convert to host delta tsc if tsc scaling is enabled */
11133 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11134 u64_shl_div_u64(delta_tsc,
11135 kvm_tsc_scaling_ratio_frac_bits,
11136 vcpu->arch.tsc_scaling_ratio,
11137 &delta_tsc))
11138 return -ERANGE;
11139
11140 /*
11141 * If the delta tsc can't fit in the 32 bit after the multi shift,
11142 * we can't use the preemption timer.
11143 * It's possible that it fits on later vmentries, but checking
11144 * on every vmentry is costly so we just use an hrtimer.
11145 */
11146 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11147 return -ERANGE;
11148
11149 vmx->hv_deadline_tsc = tscl + delta_tsc;
11150 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11151 PIN_BASED_VMX_PREEMPTION_TIMER);
11152 return 0;
11153}
11154
11155static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11156{
11157 struct vcpu_vmx *vmx = to_vmx(vcpu);
11158 vmx->hv_deadline_tsc = -1;
11159 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11160 PIN_BASED_VMX_PREEMPTION_TIMER);
11161}
11162#endif
11163
48d89b92 11164static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 11165{
b4a2d31d
RK
11166 if (ple_gap)
11167 shrink_ple_window(vcpu);
ae97a3b8
RK
11168}
11169
843e4330
KH
11170static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11171 struct kvm_memory_slot *slot)
11172{
11173 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11174 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11175}
11176
11177static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11178 struct kvm_memory_slot *slot)
11179{
11180 kvm_mmu_slot_set_dirty(kvm, slot);
11181}
11182
11183static void vmx_flush_log_dirty(struct kvm *kvm)
11184{
11185 kvm_flush_pml_buffers(kvm);
11186}
11187
c5f983f6
BD
11188static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11189{
11190 struct vmcs12 *vmcs12;
11191 struct vcpu_vmx *vmx = to_vmx(vcpu);
11192 gpa_t gpa;
11193 struct page *page = NULL;
11194 u64 *pml_address;
11195
11196 if (is_guest_mode(vcpu)) {
11197 WARN_ON_ONCE(vmx->nested.pml_full);
11198
11199 /*
11200 * Check if PML is enabled for the nested guest.
11201 * Whether eptp bit 6 is set is already checked
11202 * as part of A/D emulation.
11203 */
11204 vmcs12 = get_vmcs12(vcpu);
11205 if (!nested_cpu_has_pml(vmcs12))
11206 return 0;
11207
4769886b 11208 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD
11209 vmx->nested.pml_full = true;
11210 return 1;
11211 }
11212
11213 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11214
11215 page = nested_get_page(vcpu, vmcs12->pml_address);
11216 if (!page)
11217 return 0;
11218
11219 pml_address = kmap(page);
11220 pml_address[vmcs12->guest_pml_index--] = gpa;
11221 kunmap(page);
11222 nested_release_page_clean(page);
11223 }
11224
11225 return 0;
11226}
11227
843e4330
KH
11228static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11229 struct kvm_memory_slot *memslot,
11230 gfn_t offset, unsigned long mask)
11231{
11232 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11233}
11234
bf9f6ac8
FW
11235/*
11236 * This routine does the following things for vCPU which is going
11237 * to be blocked if VT-d PI is enabled.
11238 * - Store the vCPU to the wakeup list, so when interrupts happen
11239 * we can find the right vCPU to wake up.
11240 * - Change the Posted-interrupt descriptor as below:
11241 * 'NDST' <-- vcpu->pre_pcpu
11242 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11243 * - If 'ON' is set during this process, which means at least one
11244 * interrupt is posted for this vCPU, we cannot block it, in
11245 * this case, return 1, otherwise, return 0.
11246 *
11247 */
bc22512b 11248static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8
FW
11249{
11250 unsigned long flags;
11251 unsigned int dest;
11252 struct pi_desc old, new;
11253 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11254
11255 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
11256 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11257 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW
11258 return 0;
11259
11260 vcpu->pre_pcpu = vcpu->cpu;
11261 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11262 vcpu->pre_pcpu), flags);
11263 list_add_tail(&vcpu->blocked_vcpu_list,
11264 &per_cpu(blocked_vcpu_on_cpu,
11265 vcpu->pre_pcpu));
11266 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11267 vcpu->pre_pcpu), flags);
11268
11269 do {
11270 old.control = new.control = pi_desc->control;
11271
11272 /*
11273 * We should not block the vCPU if
11274 * an interrupt is posted for it.
11275 */
11276 if (pi_test_on(pi_desc) == 1) {
11277 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11278 vcpu->pre_pcpu), flags);
11279 list_del(&vcpu->blocked_vcpu_list);
11280 spin_unlock_irqrestore(
11281 &per_cpu(blocked_vcpu_on_cpu_lock,
11282 vcpu->pre_pcpu), flags);
11283 vcpu->pre_pcpu = -1;
11284
11285 return 1;
11286 }
11287
11288 WARN((pi_desc->sn == 1),
11289 "Warning: SN field of posted-interrupts "
11290 "is set before blocking\n");
11291
11292 /*
11293 * Since vCPU can be preempted during this process,
11294 * vcpu->cpu could be different with pre_pcpu, we
11295 * need to set pre_pcpu as the destination of wakeup
11296 * notification event, then we can find the right vCPU
11297 * to wakeup in wakeup handler if interrupts happen
11298 * when the vCPU is in blocked state.
11299 */
11300 dest = cpu_physical_id(vcpu->pre_pcpu);
11301
11302 if (x2apic_enabled())
11303 new.ndst = dest;
11304 else
11305 new.ndst = (dest << 8) & 0xFF00;
11306
11307 /* set 'NV' to 'wakeup vector' */
11308 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11309 } while (cmpxchg(&pi_desc->control, old.control,
11310 new.control) != old.control);
11311
11312 return 0;
11313}
11314
bc22512b
YJ
11315static int vmx_pre_block(struct kvm_vcpu *vcpu)
11316{
11317 if (pi_pre_block(vcpu))
11318 return 1;
11319
64672c95
YJ
11320 if (kvm_lapic_hv_timer_in_use(vcpu))
11321 kvm_lapic_switch_to_sw_timer(vcpu);
11322
bc22512b
YJ
11323 return 0;
11324}
11325
11326static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8
FW
11327{
11328 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11329 struct pi_desc old, new;
11330 unsigned int dest;
11331 unsigned long flags;
11332
11333 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
11334 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11335 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW
11336 return;
11337
11338 do {
11339 old.control = new.control = pi_desc->control;
11340
11341 dest = cpu_physical_id(vcpu->cpu);
11342
11343 if (x2apic_enabled())
11344 new.ndst = dest;
11345 else
11346 new.ndst = (dest << 8) & 0xFF00;
11347
11348 /* Allow posting non-urgent interrupts */
11349 new.sn = 0;
11350
11351 /* set 'NV' to 'notification vector' */
11352 new.nv = POSTED_INTR_VECTOR;
11353 } while (cmpxchg(&pi_desc->control, old.control,
11354 new.control) != old.control);
11355
11356 if(vcpu->pre_pcpu != -1) {
11357 spin_lock_irqsave(
11358 &per_cpu(blocked_vcpu_on_cpu_lock,
11359 vcpu->pre_pcpu), flags);
11360 list_del(&vcpu->blocked_vcpu_list);
11361 spin_unlock_irqrestore(
11362 &per_cpu(blocked_vcpu_on_cpu_lock,
11363 vcpu->pre_pcpu), flags);
11364 vcpu->pre_pcpu = -1;
11365 }
11366}
11367
bc22512b
YJ
11368static void vmx_post_block(struct kvm_vcpu *vcpu)
11369{
64672c95
YJ
11370 if (kvm_x86_ops->set_hv_timer)
11371 kvm_lapic_switch_to_hv_timer(vcpu);
11372
bc22512b
YJ
11373 pi_post_block(vcpu);
11374}
11375
efc64404
FW
11376/*
11377 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11378 *
11379 * @kvm: kvm
11380 * @host_irq: host irq of the interrupt
11381 * @guest_irq: gsi of the interrupt
11382 * @set: set or unset PI
11383 * returns 0 on success, < 0 on failure
11384 */
11385static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11386 uint32_t guest_irq, bool set)
11387{
11388 struct kvm_kernel_irq_routing_entry *e;
11389 struct kvm_irq_routing_table *irq_rt;
11390 struct kvm_lapic_irq irq;
11391 struct kvm_vcpu *vcpu;
11392 struct vcpu_data vcpu_info;
11393 int idx, ret = -EINVAL;
11394
11395 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ
11396 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11397 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW
11398 return 0;
11399
11400 idx = srcu_read_lock(&kvm->irq_srcu);
11401 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11402 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11403
11404 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11405 if (e->type != KVM_IRQ_ROUTING_MSI)
11406 continue;
11407 /*
11408 * VT-d PI cannot support posting multicast/broadcast
11409 * interrupts to a vCPU, we still use interrupt remapping
11410 * for these kind of interrupts.
11411 *
11412 * For lowest-priority interrupts, we only support
11413 * those with single CPU as the destination, e.g. user
11414 * configures the interrupts via /proc/irq or uses
11415 * irqbalance to make the interrupts single-CPU.
11416 *
11417 * We will support full lowest-priority interrupt later.
11418 */
11419
37131313 11420 kvm_set_msi_irq(kvm, e, &irq);
23a1c257
FW
11421 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11422 /*
11423 * Make sure the IRTE is in remapped mode if
11424 * we don't handle it in posted mode.
11425 */
11426 ret = irq_set_vcpu_affinity(host_irq, NULL);
11427 if (ret < 0) {
11428 printk(KERN_INFO
11429 "failed to back to remapped mode, irq: %u\n",
11430 host_irq);
11431 goto out;
11432 }
11433
efc64404 11434 continue;
23a1c257 11435 }
efc64404
FW
11436
11437 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11438 vcpu_info.vector = irq.vector;
11439
b6ce9780 11440 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
efc64404
FW
11441 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11442
11443 if (set)
11444 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11445 else {
11446 /* suppress notification event before unposting */
11447 pi_set_sn(vcpu_to_pi_desc(vcpu));
11448 ret = irq_set_vcpu_affinity(host_irq, NULL);
11449 pi_clear_sn(vcpu_to_pi_desc(vcpu));
11450 }
11451
11452 if (ret < 0) {
11453 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11454 __func__);
11455 goto out;
11456 }
11457 }
11458
11459 ret = 0;
11460out:
11461 srcu_read_unlock(&kvm->irq_srcu, idx);
11462 return ret;
11463}
11464
c45dcc71
AR
11465static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11466{
11467 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11468 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11469 FEATURE_CONTROL_LMCE;
11470 else
11471 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11472 ~FEATURE_CONTROL_LMCE;
11473}
11474
404f6aac 11475static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK
11476 .cpu_has_kvm_support = cpu_has_kvm_support,
11477 .disabled_by_bios = vmx_disabled_by_bios,
11478 .hardware_setup = hardware_setup,
11479 .hardware_unsetup = hardware_unsetup,
002c7f7c 11480 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK
11481 .hardware_enable = hardware_enable,
11482 .hardware_disable = hardware_disable,
04547156 11483 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 11484 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK
11485
11486 .vcpu_create = vmx_create_vcpu,
11487 .vcpu_free = vmx_free_vcpu,
04d2cc77 11488 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 11489
04d2cc77 11490 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK
11491 .vcpu_load = vmx_vcpu_load,
11492 .vcpu_put = vmx_vcpu_put,
11493
a96036b8 11494 .update_bp_intercept = update_exception_bitmap,
6aa8b732
AK
11495 .get_msr = vmx_get_msr,
11496 .set_msr = vmx_set_msr,
11497 .get_segment_base = vmx_get_segment_base,
11498 .get_segment = vmx_get_segment,
11499 .set_segment = vmx_set_segment,
2e4d2653 11500 .get_cpl = vmx_get_cpl,
6aa8b732 11501 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 11502 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 11503 .decache_cr3 = vmx_decache_cr3,
25c4c276 11504 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 11505 .set_cr0 = vmx_set_cr0,
6aa8b732
AK
11506 .set_cr3 = vmx_set_cr3,
11507 .set_cr4 = vmx_set_cr4,
6aa8b732 11508 .set_efer = vmx_set_efer,
6aa8b732
AK
11509 .get_idt = vmx_get_idt,
11510 .set_idt = vmx_set_idt,
11511 .get_gdt = vmx_get_gdt,
11512 .set_gdt = vmx_set_gdt,
73aaf249
JK
11513 .get_dr6 = vmx_get_dr6,
11514 .set_dr6 = vmx_set_dr6,
020df079 11515 .set_dr7 = vmx_set_dr7,
81908bf4 11516 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 11517 .cache_reg = vmx_cache_reg,
6aa8b732
AK
11518 .get_rflags = vmx_get_rflags,
11519 .set_rflags = vmx_set_rflags,
be94f6b7
HH
11520
11521 .get_pkru = vmx_get_pkru,
11522
6aa8b732 11523 .tlb_flush = vmx_flush_tlb,
6aa8b732 11524
6aa8b732 11525 .run = vmx_vcpu_run,
6062d012 11526 .handle_exit = vmx_handle_exit,
6aa8b732 11527 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC
11528 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11529 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 11530 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 11531 .set_irq = vmx_inject_irq,
95ba8273 11532 .set_nmi = vmx_inject_nmi,
298101da 11533 .queue_exception = vmx_queue_exception,
b463a6f7 11534 .cancel_injection = vmx_cancel_injection,
78646121 11535 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 11536 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK
11537 .get_nmi_mask = vmx_get_nmi_mask,
11538 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN
11539 .enable_nmi_window = enable_nmi_window,
11540 .enable_irq_window = enable_irq_window,
11541 .update_cr8_intercept = update_cr8_intercept,
8d14695f 11542 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 11543 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb
AS
11544 .get_enable_apicv = vmx_get_enable_apicv,
11545 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 11546 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 11547 .apicv_post_state_restore = vmx_apicv_post_state_restore,
c7c9c56c
YZ
11548 .hwapic_irr_update = vmx_hwapic_irr_update,
11549 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ
11550 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11551 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 11552
cbc94022 11553 .set_tss_addr = vmx_set_tss_addr,
67253af5 11554 .get_tdp_level = get_ept_level,
4b12f0de 11555 .get_mt_mask = vmx_get_mt_mask,
229456fc 11556
586f9607 11557 .get_exit_info = vmx_get_exit_info,
586f9607 11558
17cc3935 11559 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY
11560
11561 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY
11562
11563 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 11564 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR
11565
11566 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY
11567
11568 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA
11569
11570 .write_tsc_offset = vmx_write_tsc_offset,
1c97f0a0
JR
11571
11572 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR
11573
11574 .check_intercept = vmx_check_intercept,
a547c6db 11575 .handle_external_intr = vmx_handle_external_intr,
da8999d3 11576 .mpx_supported = vmx_mpx_supported,
55412b2e 11577 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK
11578
11579 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK
11580
11581 .sched_in = vmx_sched_in,
843e4330
KH
11582
11583 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11584 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11585 .flush_log_dirty = vmx_flush_log_dirty,
11586 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 11587 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 11588
bf9f6ac8
FW
11589 .pre_block = vmx_pre_block,
11590 .post_block = vmx_post_block,
11591
25462f7f 11592 .pmu_ops = &intel_pmu_ops,
efc64404
FW
11593
11594 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ
11595
11596#ifdef CONFIG_X86_64
11597 .set_hv_timer = vmx_set_hv_timer,
11598 .cancel_hv_timer = vmx_cancel_hv_timer,
11599#endif
c45dcc71
AR
11600
11601 .setup_mce = vmx_setup_mce,
6aa8b732
AK
11602};
11603
11604static int __init vmx_init(void)
11605{
34a1cd60
TC
11606 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11607 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 11608 if (r)
34a1cd60 11609 return r;
25c5f225 11610
2965faa5 11611#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY
11612 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11613 crash_vmclear_local_loaded_vmcss);
11614#endif
11615
fdef3ad1 11616 return 0;
6aa8b732
AK
11617}
11618
11619static void __exit vmx_exit(void)
11620{
2965faa5 11621#ifdef CONFIG_KEXEC_CORE
3b63a43f 11622 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY
11623 synchronize_rcu();
11624#endif
11625
cb498ea2 11626 kvm_exit();
6aa8b732
AK
11627}
11628
11629module_init(vmx_init)
11630module_exit(vmx_exit)