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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
d62caabb 22#include "lapic.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732 25#include <linux/module.h>
9d8f549d 26#include <linux/kernel.h>
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27#include <linux/mm.h>
28#include <linux/highmem.h>
e8edc6e0 29#include <linux/sched.h>
c7addb90 30#include <linux/moduleparam.h>
e9bda3b3 31#include <linux/mod_devicetable.h>
af658dca 32#include <linux/trace_events.h>
5a0e3ad6 33#include <linux/slab.h>
cafd6659 34#include <linux/tboot.h>
f4124500 35#include <linux/hrtimer.h>
5fdbf976 36#include "kvm_cache_regs.h"
35920a35 37#include "x86.h"
e495606d 38
28b835d6 39#include <asm/cpu.h>
6aa8b732 40#include <asm/io.h>
3b3be0d1 41#include <asm/desc.h>
13673a90 42#include <asm/vmx.h>
6210e37b 43#include <asm/virtext.h>
a0861c02 44#include <asm/mce.h>
952f07ec 45#include <asm/fpu/internal.h>
d7cd9796 46#include <asm/perf_event.h>
81908bf4 47#include <asm/debugreg.h>
8f536b76 48#include <asm/kexec.h>
dab2087d 49#include <asm/apic.h>
efc64404 50#include <asm/irq_remapping.h>
6aa8b732 51
229456fc 52#include "trace.h"
25462f7f 53#include "pmu.h"
229456fc 54
4ecac3fd 55#define __ex(x) __kvm_handle_fault_on_reboot(x)
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56#define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 58
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59MODULE_AUTHOR("Qumranet");
60MODULE_LICENSE("GPL");
61
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62static const struct x86_cpu_id vmx_cpu_id[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX),
64 {}
65};
66MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
67
476bc001 68static bool __read_mostly enable_vpid = 1;
736caefe 69module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 70
476bc001 71static bool __read_mostly flexpriority_enabled = 1;
736caefe 72module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 73
476bc001 74static bool __read_mostly enable_ept = 1;
736caefe 75module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 76
476bc001 77static bool __read_mostly enable_unrestricted_guest = 1;
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78module_param_named(unrestricted_guest,
79 enable_unrestricted_guest, bool, S_IRUGO);
80
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81static bool __read_mostly enable_ept_ad_bits = 1;
82module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
83
a27685c3 84static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 85module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 86
476bc001 87static bool __read_mostly fasteoi = 1;
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88module_param(fasteoi, bool, S_IRUGO);
89
5a71785d 90static bool __read_mostly enable_apicv = 1;
01e439be 91module_param(enable_apicv, bool, S_IRUGO);
83d4c286 92
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93static bool __read_mostly enable_shadow_vmcs = 1;
94module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
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95/*
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
99 */
476bc001 100static bool __read_mostly nested = 0;
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101module_param(nested, bool, S_IRUGO);
102
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103static u64 __read_mostly host_xss;
104
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105static bool __read_mostly enable_pml = 1;
106module_param_named(pml, enable_pml, bool, S_IRUGO);
107
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108#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
109
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110/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
111static int __read_mostly cpu_preemption_timer_multi;
112static bool __read_mostly enable_preemption_timer = 1;
113#ifdef CONFIG_X86_64
114module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
115#endif
116
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117#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
118#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
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119#define KVM_VM_CR0_ALWAYS_ON \
120 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
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121#define KVM_CR4_GUEST_OWNED_BITS \
122 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 123 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 124
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125#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
126#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
127
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128#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
129
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130#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
131
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132/*
133 * Hyper-V requires all of these, so mark them as supported even though
134 * they are just treated the same as all-context.
135 */
136#define VMX_VPID_EXTENT_SUPPORTED_MASK \
137 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
138 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
139 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
140 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
141
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142/*
143 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
144 * ple_gap: upper bound on the amount of time between two successive
145 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 146 * According to test, this time is usually smaller than 128 cycles.
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147 * ple_window: upper bound on the amount of time a guest is allowed to execute
148 * in a PAUSE loop. Tests indicate that most spinlocks are held for
149 * less than 2^12 cycles
150 * Time is measured based on a counter that runs at the same rate as the TSC,
151 * refer SDM volume 3b section 21.6.13 & 22.1.3.
152 */
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153#define KVM_VMX_DEFAULT_PLE_GAP 128
154#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
155#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
156#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
157#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
158 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
159
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160static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
161module_param(ple_gap, int, S_IRUGO);
162
163static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
164module_param(ple_window, int, S_IRUGO);
165
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166/* Default doubles per-vcpu window every exit. */
167static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
168module_param(ple_window_grow, int, S_IRUGO);
169
170/* Default resets per-vcpu window every exit to ple_window. */
171static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
172module_param(ple_window_shrink, int, S_IRUGO);
173
174/* Default is to compute the maximum so we can never overflow. */
175static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
176static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
177module_param(ple_window_max, int, S_IRUGO);
178
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179extern const ulong vmx_return;
180
8bf00a52 181#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 182#define VMCS02_POOL_SIZE 1
61d2ef2c 183
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184struct vmcs {
185 u32 revision_id;
186 u32 abort;
187 char data[0];
188};
189
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190/*
191 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
192 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
193 * loaded on this CPU (so we can clear them if the CPU goes down).
194 */
195struct loaded_vmcs {
196 struct vmcs *vmcs;
355f4fb1 197 struct vmcs *shadow_vmcs;
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198 int cpu;
199 int launched;
200 struct list_head loaded_vmcss_on_cpu_link;
201};
202
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203struct shared_msr_entry {
204 unsigned index;
205 u64 data;
d5696725 206 u64 mask;
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207};
208
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209/*
210 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
211 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
212 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
213 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
214 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
215 * More than one of these structures may exist, if L1 runs multiple L2 guests.
216 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
217 * underlying hardware which will be used to run L2.
218 * This structure is packed to ensure that its layout is identical across
219 * machines (necessary for live migration).
220 * If there are changes in this struct, VMCS12_REVISION must be changed.
221 */
22bd0358 222typedef u64 natural_width;
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223struct __packed vmcs12 {
224 /* According to the Intel spec, a VMCS region must start with the
225 * following two fields. Then follow implementation-specific data.
226 */
227 u32 revision_id;
228 u32 abort;
22bd0358 229
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230 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
231 u32 padding[7]; /* room for future expansion */
232
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233 u64 io_bitmap_a;
234 u64 io_bitmap_b;
235 u64 msr_bitmap;
236 u64 vm_exit_msr_store_addr;
237 u64 vm_exit_msr_load_addr;
238 u64 vm_entry_msr_load_addr;
239 u64 tsc_offset;
240 u64 virtual_apic_page_addr;
241 u64 apic_access_addr;
705699a1 242 u64 posted_intr_desc_addr;
22bd0358 243 u64 ept_pointer;
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244 u64 eoi_exit_bitmap0;
245 u64 eoi_exit_bitmap1;
246 u64 eoi_exit_bitmap2;
247 u64 eoi_exit_bitmap3;
81dc01f7 248 u64 xss_exit_bitmap;
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249 u64 guest_physical_address;
250 u64 vmcs_link_pointer;
c5f983f6 251 u64 pml_address;
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252 u64 guest_ia32_debugctl;
253 u64 guest_ia32_pat;
254 u64 guest_ia32_efer;
255 u64 guest_ia32_perf_global_ctrl;
256 u64 guest_pdptr0;
257 u64 guest_pdptr1;
258 u64 guest_pdptr2;
259 u64 guest_pdptr3;
36be0b9d 260 u64 guest_bndcfgs;
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261 u64 host_ia32_pat;
262 u64 host_ia32_efer;
263 u64 host_ia32_perf_global_ctrl;
264 u64 padding64[8]; /* room for future expansion */
265 /*
266 * To allow migration of L1 (complete with its L2 guests) between
267 * machines of different natural widths (32 or 64 bit), we cannot have
268 * unsigned long fields with no explict size. We use u64 (aliased
269 * natural_width) instead. Luckily, x86 is little-endian.
270 */
271 natural_width cr0_guest_host_mask;
272 natural_width cr4_guest_host_mask;
273 natural_width cr0_read_shadow;
274 natural_width cr4_read_shadow;
275 natural_width cr3_target_value0;
276 natural_width cr3_target_value1;
277 natural_width cr3_target_value2;
278 natural_width cr3_target_value3;
279 natural_width exit_qualification;
280 natural_width guest_linear_address;
281 natural_width guest_cr0;
282 natural_width guest_cr3;
283 natural_width guest_cr4;
284 natural_width guest_es_base;
285 natural_width guest_cs_base;
286 natural_width guest_ss_base;
287 natural_width guest_ds_base;
288 natural_width guest_fs_base;
289 natural_width guest_gs_base;
290 natural_width guest_ldtr_base;
291 natural_width guest_tr_base;
292 natural_width guest_gdtr_base;
293 natural_width guest_idtr_base;
294 natural_width guest_dr7;
295 natural_width guest_rsp;
296 natural_width guest_rip;
297 natural_width guest_rflags;
298 natural_width guest_pending_dbg_exceptions;
299 natural_width guest_sysenter_esp;
300 natural_width guest_sysenter_eip;
301 natural_width host_cr0;
302 natural_width host_cr3;
303 natural_width host_cr4;
304 natural_width host_fs_base;
305 natural_width host_gs_base;
306 natural_width host_tr_base;
307 natural_width host_gdtr_base;
308 natural_width host_idtr_base;
309 natural_width host_ia32_sysenter_esp;
310 natural_width host_ia32_sysenter_eip;
311 natural_width host_rsp;
312 natural_width host_rip;
313 natural_width paddingl[8]; /* room for future expansion */
314 u32 pin_based_vm_exec_control;
315 u32 cpu_based_vm_exec_control;
316 u32 exception_bitmap;
317 u32 page_fault_error_code_mask;
318 u32 page_fault_error_code_match;
319 u32 cr3_target_count;
320 u32 vm_exit_controls;
321 u32 vm_exit_msr_store_count;
322 u32 vm_exit_msr_load_count;
323 u32 vm_entry_controls;
324 u32 vm_entry_msr_load_count;
325 u32 vm_entry_intr_info_field;
326 u32 vm_entry_exception_error_code;
327 u32 vm_entry_instruction_len;
328 u32 tpr_threshold;
329 u32 secondary_vm_exec_control;
330 u32 vm_instruction_error;
331 u32 vm_exit_reason;
332 u32 vm_exit_intr_info;
333 u32 vm_exit_intr_error_code;
334 u32 idt_vectoring_info_field;
335 u32 idt_vectoring_error_code;
336 u32 vm_exit_instruction_len;
337 u32 vmx_instruction_info;
338 u32 guest_es_limit;
339 u32 guest_cs_limit;
340 u32 guest_ss_limit;
341 u32 guest_ds_limit;
342 u32 guest_fs_limit;
343 u32 guest_gs_limit;
344 u32 guest_ldtr_limit;
345 u32 guest_tr_limit;
346 u32 guest_gdtr_limit;
347 u32 guest_idtr_limit;
348 u32 guest_es_ar_bytes;
349 u32 guest_cs_ar_bytes;
350 u32 guest_ss_ar_bytes;
351 u32 guest_ds_ar_bytes;
352 u32 guest_fs_ar_bytes;
353 u32 guest_gs_ar_bytes;
354 u32 guest_ldtr_ar_bytes;
355 u32 guest_tr_ar_bytes;
356 u32 guest_interruptibility_info;
357 u32 guest_activity_state;
358 u32 guest_sysenter_cs;
359 u32 host_ia32_sysenter_cs;
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360 u32 vmx_preemption_timer_value;
361 u32 padding32[7]; /* room for future expansion */
22bd0358 362 u16 virtual_processor_id;
705699a1 363 u16 posted_intr_nv;
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364 u16 guest_es_selector;
365 u16 guest_cs_selector;
366 u16 guest_ss_selector;
367 u16 guest_ds_selector;
368 u16 guest_fs_selector;
369 u16 guest_gs_selector;
370 u16 guest_ldtr_selector;
371 u16 guest_tr_selector;
608406e2 372 u16 guest_intr_status;
c5f983f6 373 u16 guest_pml_index;
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NHE
374 u16 host_es_selector;
375 u16 host_cs_selector;
376 u16 host_ss_selector;
377 u16 host_ds_selector;
378 u16 host_fs_selector;
379 u16 host_gs_selector;
380 u16 host_tr_selector;
a9d30f33
NHE
381};
382
383/*
384 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
385 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
386 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
387 */
388#define VMCS12_REVISION 0x11e57ed0
389
390/*
391 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
392 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
393 * current implementation, 4K are reserved to avoid future complications.
394 */
395#define VMCS12_SIZE 0x1000
396
ff2f6fe9
NHE
397/* Used to remember the last vmcs02 used for some recently used vmcs12s */
398struct vmcs02_list {
399 struct list_head list;
400 gpa_t vmptr;
401 struct loaded_vmcs vmcs02;
402};
403
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NHE
404/*
405 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
406 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
407 */
408struct nested_vmx {
409 /* Has the level1 guest done vmxon? */
410 bool vmxon;
3573e22c 411 gpa_t vmxon_ptr;
c5f983f6 412 bool pml_full;
a9d30f33
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413
414 /* The guest-physical address of the current VMCS L1 keeps for L2 */
415 gpa_t current_vmptr;
416 /* The host-usable pointer to the above */
417 struct page *current_vmcs12_page;
418 struct vmcs12 *current_vmcs12;
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DM
419 /*
420 * Cache of the guest's VMCS, existing outside of guest memory.
421 * Loaded from guest memory during VMPTRLD. Flushed to guest
422 * memory during VMXOFF, VMCLEAR, VMPTRLD.
423 */
424 struct vmcs12 *cached_vmcs12;
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AG
425 /*
426 * Indicates if the shadow vmcs must be updated with the
427 * data hold by vmcs12
428 */
429 bool sync_shadow_vmcs;
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430
431 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
432 struct list_head vmcs02_pool;
433 int vmcs02_num;
dccbfcf5 434 bool change_vmcs01_virtual_x2apic_mode;
644d711a
NHE
435 /* L2 must run next, and mustn't decide to exit to L1. */
436 bool nested_run_pending;
fe3ef05c
NHE
437 /*
438 * Guest pages referred to in vmcs02 with host-physical pointers, so
439 * we must keep them pinned while L2 runs.
440 */
441 struct page *apic_access_page;
a7c0b07d 442 struct page *virtual_apic_page;
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443 struct page *pi_desc_page;
444 struct pi_desc *pi_desc;
445 bool pi_pending;
446 u16 posted_intr_nv;
f4124500 447
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448 unsigned long *msr_bitmap;
449
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450 struct hrtimer preemption_timer;
451 bool preemption_timer_expired;
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452
453 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
454 u64 vmcs01_debugctl;
b9c237bb 455
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WL
456 u16 vpid02;
457 u16 last_vpid;
458
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DM
459 /*
460 * We only store the "true" versions of the VMX capability MSRs. We
461 * generate the "non-true" versions by setting the must-be-1 bits
462 * according to the SDM.
463 */
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WV
464 u32 nested_vmx_procbased_ctls_low;
465 u32 nested_vmx_procbased_ctls_high;
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466 u32 nested_vmx_secondary_ctls_low;
467 u32 nested_vmx_secondary_ctls_high;
468 u32 nested_vmx_pinbased_ctls_low;
469 u32 nested_vmx_pinbased_ctls_high;
470 u32 nested_vmx_exit_ctls_low;
471 u32 nested_vmx_exit_ctls_high;
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472 u32 nested_vmx_entry_ctls_low;
473 u32 nested_vmx_entry_ctls_high;
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474 u32 nested_vmx_misc_low;
475 u32 nested_vmx_misc_high;
476 u32 nested_vmx_ept_caps;
99b83ac8 477 u32 nested_vmx_vpid_caps;
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DM
478 u64 nested_vmx_basic;
479 u64 nested_vmx_cr0_fixed0;
480 u64 nested_vmx_cr0_fixed1;
481 u64 nested_vmx_cr4_fixed0;
482 u64 nested_vmx_cr4_fixed1;
483 u64 nested_vmx_vmcs_enum;
ec378aee
NHE
484};
485
01e439be 486#define POSTED_INTR_ON 0
ebbfc765
FW
487#define POSTED_INTR_SN 1
488
01e439be
YZ
489/* Posted-Interrupt Descriptor */
490struct pi_desc {
491 u32 pir[8]; /* Posted interrupt requested */
6ef1522f
FW
492 union {
493 struct {
494 /* bit 256 - Outstanding Notification */
495 u16 on : 1,
496 /* bit 257 - Suppress Notification */
497 sn : 1,
498 /* bit 271:258 - Reserved */
499 rsvd_1 : 14;
500 /* bit 279:272 - Notification Vector */
501 u8 nv;
502 /* bit 287:280 - Reserved */
503 u8 rsvd_2;
504 /* bit 319:288 - Notification Destination */
505 u32 ndst;
506 };
507 u64 control;
508 };
509 u32 rsvd[6];
01e439be
YZ
510} __aligned(64);
511
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YZ
512static bool pi_test_and_set_on(struct pi_desc *pi_desc)
513{
514 return test_and_set_bit(POSTED_INTR_ON,
515 (unsigned long *)&pi_desc->control);
516}
517
518static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
519{
520 return test_and_clear_bit(POSTED_INTR_ON,
521 (unsigned long *)&pi_desc->control);
522}
523
524static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
525{
526 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
527}
528
ebbfc765
FW
529static inline void pi_clear_sn(struct pi_desc *pi_desc)
530{
531 return clear_bit(POSTED_INTR_SN,
532 (unsigned long *)&pi_desc->control);
533}
534
535static inline void pi_set_sn(struct pi_desc *pi_desc)
536{
537 return set_bit(POSTED_INTR_SN,
538 (unsigned long *)&pi_desc->control);
539}
540
ad361091
PB
541static inline void pi_clear_on(struct pi_desc *pi_desc)
542{
543 clear_bit(POSTED_INTR_ON,
544 (unsigned long *)&pi_desc->control);
545}
546
ebbfc765
FW
547static inline int pi_test_on(struct pi_desc *pi_desc)
548{
549 return test_bit(POSTED_INTR_ON,
550 (unsigned long *)&pi_desc->control);
551}
552
553static inline int pi_test_sn(struct pi_desc *pi_desc)
554{
555 return test_bit(POSTED_INTR_SN,
556 (unsigned long *)&pi_desc->control);
557}
558
a2fa3e9f 559struct vcpu_vmx {
fb3f0f51 560 struct kvm_vcpu vcpu;
313dbd49 561 unsigned long host_rsp;
29bd8a78 562 u8 fail;
9d58b931 563 bool nmi_known_unmasked;
51aa01d1 564 u32 exit_intr_info;
1155f76a 565 u32 idt_vectoring_info;
6de12732 566 ulong rflags;
26bb0981 567 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH
568 int nmsrs;
569 int save_nmsrs;
a547c6db 570 unsigned long host_idt_base;
a2fa3e9f 571#ifdef CONFIG_X86_64
44ea2b17
AK
572 u64 msr_host_kernel_gs_base;
573 u64 msr_guest_kernel_gs_base;
a2fa3e9f 574#endif
2961e876
GN
575 u32 vm_entry_controls_shadow;
576 u32 vm_exit_controls_shadow;
d462b819
NHE
577 /*
578 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
579 * non-nested (L1) guest, it always points to vmcs01. For a nested
580 * guest (L2), it points to a different VMCS.
581 */
582 struct loaded_vmcs vmcs01;
583 struct loaded_vmcs *loaded_vmcs;
584 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK
585 struct msr_autoload {
586 unsigned nr;
587 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
588 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
589 } msr_autoload;
a2fa3e9f
GH
590 struct {
591 int loaded;
592 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK
593#ifdef CONFIG_X86_64
594 u16 ds_sel, es_sel;
595#endif
152d3f2f
LV
596 int gs_ldt_reload_needed;
597 int fs_reload_needed;
da8999d3 598 u64 msr_host_bndcfgs;
d974baa3 599 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 600 } host_state;
9c8cba37 601 struct {
7ffd92c5 602 int vm86_active;
78ac8b47 603 ulong save_rflags;
f5f7b2fe
AK
604 struct kvm_segment segs[8];
605 } rmode;
606 struct {
607 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK
608 struct kvm_save_segment {
609 u16 selector;
610 unsigned long base;
611 u32 limit;
612 u32 ar;
f5f7b2fe 613 } seg[8];
2fb92db1 614 } segment_cache;
2384d2b3 615 int vpid;
04fa4d32 616 bool emulation_required;
3b86cd99 617
a0861c02 618 u32 exit_reason;
4e47c7a6 619
01e439be
YZ
620 /* Posted interrupt descriptor */
621 struct pi_desc pi_desc;
622
ec378aee
NHE
623 /* Support for a guest hypervisor (nested VMX) */
624 struct nested_vmx nested;
a7653ecd
RK
625
626 /* Dynamic PLE window. */
627 int ple_window;
628 bool ple_window_dirty;
843e4330
KH
629
630 /* Support for PML */
631#define PML_ENTITY_NUM 512
632 struct page *pml_pg;
2680d6da 633
64672c95
YJ
634 /* apic deadline value in host tsc */
635 u64 hv_deadline_tsc;
636
2680d6da 637 u64 current_tsc_ratio;
1be0e61c
XG
638
639 bool guest_pkru_valid;
640 u32 guest_pkru;
641 u32 host_pkru;
3b84080b 642
37e4c997
HZ
643 /*
644 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
645 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
646 * in msr_ia32_feature_control_valid_bits.
647 */
3b84080b 648 u64 msr_ia32_feature_control;
37e4c997 649 u64 msr_ia32_feature_control_valid_bits;
a2fa3e9f
GH
650};
651
2fb92db1
AK
652enum segment_cache_field {
653 SEG_FIELD_SEL = 0,
654 SEG_FIELD_BASE = 1,
655 SEG_FIELD_LIMIT = 2,
656 SEG_FIELD_AR = 3,
657
658 SEG_FIELD_NR = 4
659};
660
a2fa3e9f
GH
661static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
662{
fb3f0f51 663 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH
664}
665
efc64404
FW
666static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
667{
668 return &(to_vmx(vcpu)->pi_desc);
669}
670
22bd0358
NHE
671#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
672#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
673#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
674 [number##_HIGH] = VMCS12_OFFSET(name)+4
675
4607c2d7 676
fe2b201b 677static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG
678 /*
679 * We do NOT shadow fields that are modified when L0
680 * traps and emulates any vmx instruction (e.g. VMPTRLD,
681 * VMXON...) executed by L1.
682 * For example, VM_INSTRUCTION_ERROR is read
683 * by L1 if a vmx instruction fails (part of the error path).
684 * Note the code assumes this logic. If for some reason
685 * we start shadowing these fields then we need to
686 * force a shadow sync when L0 emulates vmx instructions
687 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
688 * by nested_vmx_failValid)
689 */
690 VM_EXIT_REASON,
691 VM_EXIT_INTR_INFO,
692 VM_EXIT_INSTRUCTION_LEN,
693 IDT_VECTORING_INFO_FIELD,
694 IDT_VECTORING_ERROR_CODE,
695 VM_EXIT_INTR_ERROR_CODE,
696 EXIT_QUALIFICATION,
697 GUEST_LINEAR_ADDRESS,
698 GUEST_PHYSICAL_ADDRESS
699};
fe2b201b 700static int max_shadow_read_only_fields =
4607c2d7
AG
701 ARRAY_SIZE(shadow_read_only_fields);
702
fe2b201b 703static unsigned long shadow_read_write_fields[] = {
a7c0b07d 704 TPR_THRESHOLD,
4607c2d7
AG
705 GUEST_RIP,
706 GUEST_RSP,
707 GUEST_CR0,
708 GUEST_CR3,
709 GUEST_CR4,
710 GUEST_INTERRUPTIBILITY_INFO,
711 GUEST_RFLAGS,
712 GUEST_CS_SELECTOR,
713 GUEST_CS_AR_BYTES,
714 GUEST_CS_LIMIT,
715 GUEST_CS_BASE,
716 GUEST_ES_BASE,
36be0b9d 717 GUEST_BNDCFGS,
4607c2d7
AG
718 CR0_GUEST_HOST_MASK,
719 CR0_READ_SHADOW,
720 CR4_READ_SHADOW,
721 TSC_OFFSET,
722 EXCEPTION_BITMAP,
723 CPU_BASED_VM_EXEC_CONTROL,
724 VM_ENTRY_EXCEPTION_ERROR_CODE,
725 VM_ENTRY_INTR_INFO_FIELD,
726 VM_ENTRY_INSTRUCTION_LEN,
727 VM_ENTRY_EXCEPTION_ERROR_CODE,
728 HOST_FS_BASE,
729 HOST_GS_BASE,
730 HOST_FS_SELECTOR,
731 HOST_GS_SELECTOR
732};
fe2b201b 733static int max_shadow_read_write_fields =
4607c2d7
AG
734 ARRAY_SIZE(shadow_read_write_fields);
735
772e0318 736static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 737 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 738 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE
739 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
740 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
741 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
742 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
743 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
744 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
745 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
746 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 747 FIELD(GUEST_INTR_STATUS, guest_intr_status),
c5f983f6 748 FIELD(GUEST_PML_INDEX, guest_pml_index),
22bd0358
NHE
749 FIELD(HOST_ES_SELECTOR, host_es_selector),
750 FIELD(HOST_CS_SELECTOR, host_cs_selector),
751 FIELD(HOST_SS_SELECTOR, host_ss_selector),
752 FIELD(HOST_DS_SELECTOR, host_ds_selector),
753 FIELD(HOST_FS_SELECTOR, host_fs_selector),
754 FIELD(HOST_GS_SELECTOR, host_gs_selector),
755 FIELD(HOST_TR_SELECTOR, host_tr_selector),
756 FIELD64(IO_BITMAP_A, io_bitmap_a),
757 FIELD64(IO_BITMAP_B, io_bitmap_b),
758 FIELD64(MSR_BITMAP, msr_bitmap),
759 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
760 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
761 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
762 FIELD64(TSC_OFFSET, tsc_offset),
763 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
764 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 765 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 766 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV
767 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
768 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
769 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
770 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 771 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE
772 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
773 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
c5f983f6 774 FIELD64(PML_ADDRESS, pml_address),
22bd0358
NHE
775 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
776 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
777 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
778 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
779 FIELD64(GUEST_PDPTR0, guest_pdptr0),
780 FIELD64(GUEST_PDPTR1, guest_pdptr1),
781 FIELD64(GUEST_PDPTR2, guest_pdptr2),
782 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 783 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE
784 FIELD64(HOST_IA32_PAT, host_ia32_pat),
785 FIELD64(HOST_IA32_EFER, host_ia32_efer),
786 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
787 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
788 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
789 FIELD(EXCEPTION_BITMAP, exception_bitmap),
790 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
791 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
792 FIELD(CR3_TARGET_COUNT, cr3_target_count),
793 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
794 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
795 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
796 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
797 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
798 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
799 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
800 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
801 FIELD(TPR_THRESHOLD, tpr_threshold),
802 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
803 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
804 FIELD(VM_EXIT_REASON, vm_exit_reason),
805 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
806 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
807 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
808 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
809 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
810 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
811 FIELD(GUEST_ES_LIMIT, guest_es_limit),
812 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
813 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
814 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
815 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
816 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
817 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
818 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
819 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
820 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
821 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
822 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
823 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
824 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
825 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
826 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
827 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
828 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
829 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
830 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
831 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
832 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 833 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE
834 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
835 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
836 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
837 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
838 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
839 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
840 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
841 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
842 FIELD(EXIT_QUALIFICATION, exit_qualification),
843 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
844 FIELD(GUEST_CR0, guest_cr0),
845 FIELD(GUEST_CR3, guest_cr3),
846 FIELD(GUEST_CR4, guest_cr4),
847 FIELD(GUEST_ES_BASE, guest_es_base),
848 FIELD(GUEST_CS_BASE, guest_cs_base),
849 FIELD(GUEST_SS_BASE, guest_ss_base),
850 FIELD(GUEST_DS_BASE, guest_ds_base),
851 FIELD(GUEST_FS_BASE, guest_fs_base),
852 FIELD(GUEST_GS_BASE, guest_gs_base),
853 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
854 FIELD(GUEST_TR_BASE, guest_tr_base),
855 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
856 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
857 FIELD(GUEST_DR7, guest_dr7),
858 FIELD(GUEST_RSP, guest_rsp),
859 FIELD(GUEST_RIP, guest_rip),
860 FIELD(GUEST_RFLAGS, guest_rflags),
861 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
862 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
863 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
864 FIELD(HOST_CR0, host_cr0),
865 FIELD(HOST_CR3, host_cr3),
866 FIELD(HOST_CR4, host_cr4),
867 FIELD(HOST_FS_BASE, host_fs_base),
868 FIELD(HOST_GS_BASE, host_gs_base),
869 FIELD(HOST_TR_BASE, host_tr_base),
870 FIELD(HOST_GDTR_BASE, host_gdtr_base),
871 FIELD(HOST_IDTR_BASE, host_idtr_base),
872 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
873 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
874 FIELD(HOST_RSP, host_rsp),
875 FIELD(HOST_RIP, host_rip),
876};
22bd0358
NHE
877
878static inline short vmcs_field_to_offset(unsigned long field)
879{
a2ae9df7
PB
880 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
881
882 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
883 vmcs_field_to_offset_table[field] == 0)
884 return -ENOENT;
885
22bd0358
NHE
886 return vmcs_field_to_offset_table[field];
887}
888
a9d30f33
NHE
889static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
890{
4f2777bc 891 return to_vmx(vcpu)->nested.cached_vmcs12;
a9d30f33
NHE
892}
893
894static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
895{
54bf36aa 896 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 897 if (is_error_page(page))
a9d30f33 898 return NULL;
32cad84f 899
a9d30f33
NHE
900 return page;
901}
902
903static void nested_release_page(struct page *page)
904{
905 kvm_release_page_dirty(page);
906}
907
908static void nested_release_page_clean(struct page *page)
909{
910 kvm_release_page_clean(page);
911}
912
bfd0a56b 913static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 914static u64 construct_eptp(unsigned long root_hpa);
f53cd63c 915static bool vmx_xsaves_supported(void);
776e58ea 916static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW
917static void vmx_set_segment(struct kvm_vcpu *vcpu,
918 struct kvm_segment *var, int seg);
919static void vmx_get_segment(struct kvm_vcpu *vcpu,
920 struct kvm_segment *var, int seg);
d99e4152
GN
921static bool guest_state_valid(struct kvm_vcpu *vcpu);
922static u32 vmx_segment_access_rights(struct kvm_segment *var);
c3114420 923static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 924static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 925static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 926
6aa8b732
AK
927static DEFINE_PER_CPU(struct vmcs *, vmxarea);
928static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE
929/*
930 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
931 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
932 */
933static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 934
bf9f6ac8
FW
935/*
936 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
937 * can find which vCPU should be waken up.
938 */
939static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
940static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
941
23611332
RK
942enum {
943 VMX_IO_BITMAP_A,
944 VMX_IO_BITMAP_B,
945 VMX_MSR_BITMAP_LEGACY,
946 VMX_MSR_BITMAP_LONGMODE,
947 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
948 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
949 VMX_MSR_BITMAP_LEGACY_X2APIC,
950 VMX_MSR_BITMAP_LONGMODE_X2APIC,
951 VMX_VMREAD_BITMAP,
952 VMX_VMWRITE_BITMAP,
953 VMX_BITMAP_NR
954};
955
956static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
957
958#define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
959#define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
960#define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
961#define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
962#define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
963#define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
964#define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
965#define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
966#define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
967#define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
fdef3ad1 968
110312c8 969static bool cpu_has_load_ia32_efer;
8bf00a52 970static bool cpu_has_load_perf_global_ctrl;
110312c8 971
2384d2b3
SY
972static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
973static DEFINE_SPINLOCK(vmx_vpid_lock);
974
1c3d14fe 975static struct vmcs_config {
6aa8b732
AK
976 int size;
977 int order;
9ac7e3e8 978 u32 basic_cap;
6aa8b732 979 u32 revision_id;
1c3d14fe
YS
980 u32 pin_based_exec_ctrl;
981 u32 cpu_based_exec_ctrl;
f78e0e2e 982 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS
983 u32 vmexit_ctrl;
984 u32 vmentry_ctrl;
985} vmcs_config;
6aa8b732 986
efff9e53 987static struct vmx_capability {
d56f546d
SY
988 u32 ept;
989 u32 vpid;
990} vmx_capability;
991
6aa8b732
AK
992#define VMX_SEGMENT_FIELD(seg) \
993 [VCPU_SREG_##seg] = { \
994 .selector = GUEST_##seg##_SELECTOR, \
995 .base = GUEST_##seg##_BASE, \
996 .limit = GUEST_##seg##_LIMIT, \
997 .ar_bytes = GUEST_##seg##_AR_BYTES, \
998 }
999
772e0318 1000static const struct kvm_vmx_segment_field {
6aa8b732
AK
1001 unsigned selector;
1002 unsigned base;
1003 unsigned limit;
1004 unsigned ar_bytes;
1005} kvm_vmx_segment_fields[] = {
1006 VMX_SEGMENT_FIELD(CS),
1007 VMX_SEGMENT_FIELD(DS),
1008 VMX_SEGMENT_FIELD(ES),
1009 VMX_SEGMENT_FIELD(FS),
1010 VMX_SEGMENT_FIELD(GS),
1011 VMX_SEGMENT_FIELD(SS),
1012 VMX_SEGMENT_FIELD(TR),
1013 VMX_SEGMENT_FIELD(LDTR),
1014};
1015
26bb0981
AK
1016static u64 host_efer;
1017
6de4f3ad
AK
1018static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1019
4d56c8a7 1020/*
8c06585d 1021 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK
1022 * away by decrementing the array size.
1023 */
6aa8b732 1024static const u32 vmx_msr_index[] = {
05b3e0c2 1025#ifdef CONFIG_X86_64
44ea2b17 1026 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 1027#endif
8c06585d 1028 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 1029};
6aa8b732 1030
5bb16016 1031static inline bool is_exception_n(u32 intr_info, u8 vector)
6aa8b732
AK
1032{
1033 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1034 INTR_INFO_VALID_MASK)) ==
5bb16016
JK
1035 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1036}
1037
6f05485d
JK
1038static inline bool is_debug(u32 intr_info)
1039{
1040 return is_exception_n(intr_info, DB_VECTOR);
1041}
1042
1043static inline bool is_breakpoint(u32 intr_info)
1044{
1045 return is_exception_n(intr_info, BP_VECTOR);
1046}
1047
5bb16016
JK
1048static inline bool is_page_fault(u32 intr_info)
1049{
1050 return is_exception_n(intr_info, PF_VECTOR);
6aa8b732
AK
1051}
1052
31299944 1053static inline bool is_no_device(u32 intr_info)
2ab455cc 1054{
5bb16016 1055 return is_exception_n(intr_info, NM_VECTOR);
2ab455cc
AL
1056}
1057
31299944 1058static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0 1059{
5bb16016 1060 return is_exception_n(intr_info, UD_VECTOR);
7aa81cc0
AL
1061}
1062
31299944 1063static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK
1064{
1065 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1066 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1067}
1068
31299944 1069static inline bool is_machine_check(u32 intr_info)
a0861c02
AK
1070{
1071 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1072 INTR_INFO_VALID_MASK)) ==
1073 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1074}
1075
31299944 1076static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 1077{
04547156 1078 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY
1079}
1080
31299944 1081static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 1082{
04547156 1083 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS
1084}
1085
35754c98 1086static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 1087{
35754c98 1088 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS
1089}
1090
31299944 1091static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 1092{
04547156
SY
1093 return vmcs_config.cpu_based_exec_ctrl &
1094 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY
1095}
1096
774ead3a 1097static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 1098{
04547156
SY
1099 return vmcs_config.cpu_based_2nd_exec_ctrl &
1100 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1101}
1102
8d14695f
YZ
1103static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1104{
1105 return vmcs_config.cpu_based_2nd_exec_ctrl &
1106 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1107}
1108
83d4c286
YZ
1109static inline bool cpu_has_vmx_apic_register_virt(void)
1110{
1111 return vmcs_config.cpu_based_2nd_exec_ctrl &
1112 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1113}
1114
c7c9c56c
YZ
1115static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1116{
1117 return vmcs_config.cpu_based_2nd_exec_ctrl &
1118 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1119}
1120
64672c95
YJ
1121/*
1122 * Comment's format: document - errata name - stepping - processor name.
1123 * Refer from
1124 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1125 */
1126static u32 vmx_preemption_cpu_tfms[] = {
1127/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
11280x000206E6,
1129/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1130/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1131/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
11320x00020652,
1133/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
11340x00020655,
1135/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1136/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1137/*
1138 * 320767.pdf - AAP86 - B1 -
1139 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1140 */
11410x000106E5,
1142/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
11430x000106A0,
1144/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
11450x000106A1,
1146/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
11470x000106A4,
1148 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1149 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1150 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
11510x000106A5,
1152};
1153
1154static inline bool cpu_has_broken_vmx_preemption_timer(void)
1155{
1156 u32 eax = cpuid_eax(0x00000001), i;
1157
1158 /* Clear the reserved bits */
1159 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 1160 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ
1161 if (eax == vmx_preemption_cpu_tfms[i])
1162 return true;
1163
1164 return false;
1165}
1166
1167static inline bool cpu_has_vmx_preemption_timer(void)
1168{
64672c95
YJ
1169 return vmcs_config.pin_based_exec_ctrl &
1170 PIN_BASED_VMX_PREEMPTION_TIMER;
1171}
1172
01e439be
YZ
1173static inline bool cpu_has_vmx_posted_intr(void)
1174{
d6a858d1
PB
1175 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1176 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ
1177}
1178
1179static inline bool cpu_has_vmx_apicv(void)
1180{
1181 return cpu_has_vmx_apic_register_virt() &&
1182 cpu_has_vmx_virtual_intr_delivery() &&
1183 cpu_has_vmx_posted_intr();
1184}
1185
04547156
SY
1186static inline bool cpu_has_vmx_flexpriority(void)
1187{
1188 return cpu_has_vmx_tpr_shadow() &&
1189 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY
1190}
1191
e799794e
MT
1192static inline bool cpu_has_vmx_ept_execute_only(void)
1193{
31299944 1194 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT
1195}
1196
e799794e
MT
1197static inline bool cpu_has_vmx_ept_2m_page(void)
1198{
31299944 1199 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT
1200}
1201
878403b7
SY
1202static inline bool cpu_has_vmx_ept_1g_page(void)
1203{
31299944 1204 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY
1205}
1206
4bc9b982
SY
1207static inline bool cpu_has_vmx_ept_4levels(void)
1208{
1209 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1210}
1211
83c3a331
XH
1212static inline bool cpu_has_vmx_ept_ad_bits(void)
1213{
1214 return vmx_capability.ept & VMX_EPT_AD_BIT;
1215}
1216
31299944 1217static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1218{
31299944 1219 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY
1220}
1221
31299944 1222static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1223{
31299944 1224 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY
1225}
1226
518c8aee
GJ
1227static inline bool cpu_has_vmx_invvpid_single(void)
1228{
1229 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1230}
1231
b9d762fa
GJ
1232static inline bool cpu_has_vmx_invvpid_global(void)
1233{
1234 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1235}
1236
08d839c4
WL
1237static inline bool cpu_has_vmx_invvpid(void)
1238{
1239 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1240}
1241
31299944 1242static inline bool cpu_has_vmx_ept(void)
d56f546d 1243{
04547156
SY
1244 return vmcs_config.cpu_based_2nd_exec_ctrl &
1245 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY
1246}
1247
31299944 1248static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK
1249{
1250 return vmcs_config.cpu_based_2nd_exec_ctrl &
1251 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1252}
1253
31299944 1254static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE
1255{
1256 return vmcs_config.cpu_based_2nd_exec_ctrl &
1257 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1258}
1259
9ac7e3e8
JD
1260static inline bool cpu_has_vmx_basic_inout(void)
1261{
1262 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1263}
1264
35754c98 1265static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1266{
35754c98 1267 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY
1268}
1269
31299944 1270static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1271{
04547156
SY
1272 return vmcs_config.cpu_based_2nd_exec_ctrl &
1273 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY
1274}
1275
31299944 1276static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY
1277{
1278 return vmcs_config.cpu_based_2nd_exec_ctrl &
1279 SECONDARY_EXEC_RDTSCP;
1280}
1281
ad756a16
MJ
1282static inline bool cpu_has_vmx_invpcid(void)
1283{
1284 return vmcs_config.cpu_based_2nd_exec_ctrl &
1285 SECONDARY_EXEC_ENABLE_INVPCID;
1286}
1287
f5f48ee1
SY
1288static inline bool cpu_has_vmx_wbinvd_exit(void)
1289{
1290 return vmcs_config.cpu_based_2nd_exec_ctrl &
1291 SECONDARY_EXEC_WBINVD_EXITING;
1292}
1293
abc4fc58
AG
1294static inline bool cpu_has_vmx_shadow_vmcs(void)
1295{
1296 u64 vmx_msr;
1297 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1298 /* check if the cpu supports writing r/o exit information fields */
1299 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1300 return false;
1301
1302 return vmcs_config.cpu_based_2nd_exec_ctrl &
1303 SECONDARY_EXEC_SHADOW_VMCS;
1304}
1305
843e4330
KH
1306static inline bool cpu_has_vmx_pml(void)
1307{
1308 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1309}
1310
64903d61
HZ
1311static inline bool cpu_has_vmx_tsc_scaling(void)
1312{
1313 return vmcs_config.cpu_based_2nd_exec_ctrl &
1314 SECONDARY_EXEC_TSC_SCALING;
1315}
1316
04547156
SY
1317static inline bool report_flexpriority(void)
1318{
1319 return flexpriority_enabled;
1320}
1321
c7c2c709
JM
1322static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1323{
1324 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1325}
1326
fe3ef05c
NHE
1327static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1328{
1329 return vmcs12->cpu_based_vm_exec_control & bit;
1330}
1331
1332static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1333{
1334 return (vmcs12->cpu_based_vm_exec_control &
1335 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1336 (vmcs12->secondary_vm_exec_control & bit);
1337}
1338
f5c4368f 1339static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE
1340{
1341 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1342}
1343
f4124500
JK
1344static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1345{
1346 return vmcs12->pin_based_vm_exec_control &
1347 PIN_BASED_VMX_PREEMPTION_TIMER;
1348}
1349
155a97a3
NHE
1350static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1351{
1352 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1353}
1354
81dc01f7
WL
1355static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1356{
1357 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1358 vmx_xsaves_supported();
1359}
1360
c5f983f6
BD
1361static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1362{
1363 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1364}
1365
f2b93280
WV
1366static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1367{
1368 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1369}
1370
5c614b35
WL
1371static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1372{
1373 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1374}
1375
82f0dd4b
WV
1376static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1377{
1378 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1379}
1380
608406e2
WV
1381static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1382{
1383 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1384}
1385
705699a1
WV
1386static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1387{
1388 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1389}
1390
ef85b673 1391static inline bool is_nmi(u32 intr_info)
644d711a
NHE
1392{
1393 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
ef85b673 1394 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
644d711a
NHE
1395}
1396
533558bc
JK
1397static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1398 u32 exit_intr_info,
1399 unsigned long exit_qualification);
7c177938
NHE
1400static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1401 struct vmcs12 *vmcs12,
1402 u32 reason, unsigned long qualification);
1403
8b9cf98c 1404static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK
1405{
1406 int i;
1407
a2fa3e9f 1408 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1409 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED
1410 return i;
1411 return -1;
1412}
1413
2384d2b3
SY
1414static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1415{
1416 struct {
1417 u64 vpid : 16;
1418 u64 rsvd : 48;
1419 u64 gva;
1420 } operand = { vpid, 0, gva };
1421
4ecac3fd 1422 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY
1423 /* CF==1 or ZF==1 --> rc = -1 */
1424 "; ja 1f ; ud2 ; 1:"
1425 : : "a"(&operand), "c"(ext) : "cc", "memory");
1426}
1427
1439442c
SY
1428static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1429{
1430 struct {
1431 u64 eptp, gpa;
1432 } operand = {eptp, gpa};
1433
4ecac3fd 1434 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY
1435 /* CF==1 or ZF==1 --> rc = -1 */
1436 "; ja 1f ; ud2 ; 1:\n"
1437 : : "a" (&operand), "c" (ext) : "cc", "memory");
1438}
1439
26bb0981 1440static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED
1441{
1442 int i;
1443
8b9cf98c 1444 i = __find_msr_index(vmx, msr);
a75beee6 1445 if (i >= 0)
a2fa3e9f 1446 return &vmx->guest_msrs[i];
8b6d44c7 1447 return NULL;
7725f0ba
AK
1448}
1449
6aa8b732
AK
1450static void vmcs_clear(struct vmcs *vmcs)
1451{
1452 u64 phys_addr = __pa(vmcs);
1453 u8 error;
1454
4ecac3fd 1455 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1456 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK
1457 : "cc", "memory");
1458 if (error)
1459 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1460 vmcs, phys_addr);
1461}
1462
d462b819
NHE
1463static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1464{
1465 vmcs_clear(loaded_vmcs->vmcs);
355f4fb1
JM
1466 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1467 vmcs_clear(loaded_vmcs->shadow_vmcs);
d462b819
NHE
1468 loaded_vmcs->cpu = -1;
1469 loaded_vmcs->launched = 0;
1470}
1471
7725b894
DX
1472static void vmcs_load(struct vmcs *vmcs)
1473{
1474 u64 phys_addr = __pa(vmcs);
1475 u8 error;
1476
1477 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1478 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX
1479 : "cc", "memory");
1480 if (error)
2844d849 1481 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX
1482 vmcs, phys_addr);
1483}
1484
2965faa5 1485#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY
1486/*
1487 * This bitmap is used to indicate whether the vmclear
1488 * operation is enabled on all cpus. All disabled by
1489 * default.
1490 */
1491static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1492
1493static inline void crash_enable_local_vmclear(int cpu)
1494{
1495 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1496}
1497
1498static inline void crash_disable_local_vmclear(int cpu)
1499{
1500 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1501}
1502
1503static inline int crash_local_vmclear_enabled(int cpu)
1504{
1505 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1506}
1507
1508static void crash_vmclear_local_loaded_vmcss(void)
1509{
1510 int cpu = raw_smp_processor_id();
1511 struct loaded_vmcs *v;
1512
1513 if (!crash_local_vmclear_enabled(cpu))
1514 return;
1515
1516 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1517 loaded_vmcss_on_cpu_link)
1518 vmcs_clear(v->vmcs);
1519}
1520#else
1521static inline void crash_enable_local_vmclear(int cpu) { }
1522static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1523#endif /* CONFIG_KEXEC_CORE */
8f536b76 1524
d462b819 1525static void __loaded_vmcs_clear(void *arg)
6aa8b732 1526{
d462b819 1527 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1528 int cpu = raw_smp_processor_id();
6aa8b732 1529
d462b819
NHE
1530 if (loaded_vmcs->cpu != cpu)
1531 return; /* vcpu migration can race with cpu offline */
1532 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1533 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1534 crash_disable_local_vmclear(cpu);
d462b819 1535 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG
1536
1537 /*
1538 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1539 * is before setting loaded_vmcs->vcpu to -1 which is done in
1540 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1541 * then adds the vmcs into percpu list before it is deleted.
1542 */
1543 smp_wmb();
1544
d462b819 1545 loaded_vmcs_init(loaded_vmcs);
8f536b76 1546 crash_enable_local_vmclear(cpu);
6aa8b732
AK
1547}
1548
d462b819 1549static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1550{
e6c7d321
XG
1551 int cpu = loaded_vmcs->cpu;
1552
1553 if (cpu != -1)
1554 smp_call_function_single(cpu,
1555 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK
1556}
1557
dd5f5341 1558static inline void vpid_sync_vcpu_single(int vpid)
2384d2b3 1559{
dd5f5341 1560 if (vpid == 0)
2384d2b3
SY
1561 return;
1562
518c8aee 1563 if (cpu_has_vmx_invvpid_single())
dd5f5341 1564 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
2384d2b3
SY
1565}
1566
b9d762fa
GJ
1567static inline void vpid_sync_vcpu_global(void)
1568{
1569 if (cpu_has_vmx_invvpid_global())
1570 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1571}
1572
dd5f5341 1573static inline void vpid_sync_context(int vpid)
b9d762fa
GJ
1574{
1575 if (cpu_has_vmx_invvpid_single())
dd5f5341 1576 vpid_sync_vcpu_single(vpid);
b9d762fa
GJ
1577 else
1578 vpid_sync_vcpu_global();
1579}
1580
1439442c
SY
1581static inline void ept_sync_global(void)
1582{
1583 if (cpu_has_vmx_invept_global())
1584 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1585}
1586
1587static inline void ept_sync_context(u64 eptp)
1588{
089d034e 1589 if (enable_ept) {
1439442c
SY
1590 if (cpu_has_vmx_invept_context())
1591 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1592 else
1593 ept_sync_global();
1594 }
1595}
1596
8a86aea9
PB
1597static __always_inline void vmcs_check16(unsigned long field)
1598{
1599 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1600 "16-bit accessor invalid for 64-bit field");
1601 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1602 "16-bit accessor invalid for 64-bit high field");
1603 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1604 "16-bit accessor invalid for 32-bit high field");
1605 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1606 "16-bit accessor invalid for natural width field");
1607}
1608
1609static __always_inline void vmcs_check32(unsigned long field)
1610{
1611 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1612 "32-bit accessor invalid for 16-bit field");
1613 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1614 "32-bit accessor invalid for natural width field");
1615}
1616
1617static __always_inline void vmcs_check64(unsigned long field)
1618{
1619 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1620 "64-bit accessor invalid for 16-bit field");
1621 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1622 "64-bit accessor invalid for 64-bit high field");
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1624 "64-bit accessor invalid for 32-bit field");
1625 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1626 "64-bit accessor invalid for natural width field");
1627}
1628
1629static __always_inline void vmcs_checkl(unsigned long field)
1630{
1631 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1632 "Natural width accessor invalid for 16-bit field");
1633 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1634 "Natural width accessor invalid for 64-bit field");
1635 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1636 "Natural width accessor invalid for 64-bit high field");
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1638 "Natural width accessor invalid for 32-bit field");
1639}
1640
1641static __always_inline unsigned long __vmcs_readl(unsigned long field)
6aa8b732 1642{
5e520e62 1643 unsigned long value;
6aa8b732 1644
5e520e62
AK
1645 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1646 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK
1647 return value;
1648}
1649
96304217 1650static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732 1651{
8a86aea9
PB
1652 vmcs_check16(field);
1653 return __vmcs_readl(field);
6aa8b732
AK
1654}
1655
96304217 1656static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732 1657{
8a86aea9
PB
1658 vmcs_check32(field);
1659 return __vmcs_readl(field);
6aa8b732
AK
1660}
1661
96304217 1662static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1663{
8a86aea9 1664 vmcs_check64(field);
05b3e0c2 1665#ifdef CONFIG_X86_64
8a86aea9 1666 return __vmcs_readl(field);
6aa8b732 1667#else
8a86aea9 1668 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
6aa8b732
AK
1669#endif
1670}
1671
8a86aea9
PB
1672static __always_inline unsigned long vmcs_readl(unsigned long field)
1673{
1674 vmcs_checkl(field);
1675 return __vmcs_readl(field);
1676}
1677
e52de1b8
AK
1678static noinline void vmwrite_error(unsigned long field, unsigned long value)
1679{
1680 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1681 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1682 dump_stack();
1683}
1684
8a86aea9 1685static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
6aa8b732
AK
1686{
1687 u8 error;
1688
4ecac3fd 1689 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1690 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK
1691 if (unlikely(error))
1692 vmwrite_error(field, value);
6aa8b732
AK
1693}
1694
8a86aea9 1695static __always_inline void vmcs_write16(unsigned long field, u16 value)
6aa8b732 1696{
8a86aea9
PB
1697 vmcs_check16(field);
1698 __vmcs_writel(field, value);
6aa8b732
AK
1699}
1700
8a86aea9 1701static __always_inline void vmcs_write32(unsigned long field, u32 value)
6aa8b732 1702{
8a86aea9
PB
1703 vmcs_check32(field);
1704 __vmcs_writel(field, value);
6aa8b732
AK
1705}
1706
8a86aea9 1707static __always_inline void vmcs_write64(unsigned long field, u64 value)
6aa8b732 1708{
8a86aea9
PB
1709 vmcs_check64(field);
1710 __vmcs_writel(field, value);
7682f2d0 1711#ifndef CONFIG_X86_64
6aa8b732 1712 asm volatile ("");
8a86aea9 1713 __vmcs_writel(field+1, value >> 32);
6aa8b732
AK
1714#endif
1715}
1716
8a86aea9 1717static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2ab455cc 1718{
8a86aea9
PB
1719 vmcs_checkl(field);
1720 __vmcs_writel(field, value);
2ab455cc
AL
1721}
1722
8a86aea9 1723static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2ab455cc 1724{
8a86aea9
PB
1725 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1726 "vmcs_clear_bits does not support 64-bit fields");
1727 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2ab455cc
AL
1728}
1729
8a86aea9 1730static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2ab455cc 1731{
8a86aea9
PB
1732 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1733 "vmcs_set_bits does not support 64-bit fields");
1734 __vmcs_writel(field, __vmcs_readl(field) | mask);
2ab455cc
AL
1735}
1736
8391ce44
PB
1737static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1738{
1739 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1740}
1741
2961e876
GN
1742static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1743{
1744 vmcs_write32(VM_ENTRY_CONTROLS, val);
1745 vmx->vm_entry_controls_shadow = val;
1746}
1747
1748static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1749{
1750 if (vmx->vm_entry_controls_shadow != val)
1751 vm_entry_controls_init(vmx, val);
1752}
1753
1754static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1755{
1756 return vmx->vm_entry_controls_shadow;
1757}
1758
1759
1760static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1761{
1762 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1763}
1764
1765static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1766{
1767 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1768}
1769
8391ce44
PB
1770static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1771{
1772 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1773}
1774
2961e876
GN
1775static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1776{
1777 vmcs_write32(VM_EXIT_CONTROLS, val);
1778 vmx->vm_exit_controls_shadow = val;
1779}
1780
1781static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1782{
1783 if (vmx->vm_exit_controls_shadow != val)
1784 vm_exit_controls_init(vmx, val);
1785}
1786
1787static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1788{
1789 return vmx->vm_exit_controls_shadow;
1790}
1791
1792
1793static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1794{
1795 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1796}
1797
1798static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1799{
1800 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1801}
1802
2fb92db1
AK
1803static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1804{
1805 vmx->segment_cache.bitmask = 0;
1806}
1807
1808static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1809 unsigned field)
1810{
1811 bool ret;
1812 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1813
1814 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1815 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1816 vmx->segment_cache.bitmask = 0;
1817 }
1818 ret = vmx->segment_cache.bitmask & mask;
1819 vmx->segment_cache.bitmask |= mask;
1820 return ret;
1821}
1822
1823static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1824{
1825 u16 *p = &vmx->segment_cache.seg[seg].selector;
1826
1827 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1828 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1829 return *p;
1830}
1831
1832static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1833{
1834 ulong *p = &vmx->segment_cache.seg[seg].base;
1835
1836 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1837 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1838 return *p;
1839}
1840
1841static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1842{
1843 u32 *p = &vmx->segment_cache.seg[seg].limit;
1844
1845 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1846 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1847 return *p;
1848}
1849
1850static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1851{
1852 u32 *p = &vmx->segment_cache.seg[seg].ar;
1853
1854 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1855 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1856 return *p;
1857}
1858
abd3f2d6
AK
1859static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1860{
1861 u32 eb;
1862
fd7373cc 1863 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 1864 (1u << DB_VECTOR) | (1u << AC_VECTOR);
fd7373cc
JK
1865 if ((vcpu->guest_debug &
1866 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1867 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1868 eb |= 1u << BP_VECTOR;
7ffd92c5 1869 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1870 eb = ~0;
089d034e 1871 if (enable_ept)
1439442c 1872 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE
1873
1874 /* When we are running a nested L2 guest and L1 specified for it a
1875 * certain exception bitmap, we must trap the same exceptions and pass
1876 * them to L1. When running L2, we will only handle the exceptions
1877 * specified above if L1 did not want them.
1878 */
1879 if (is_guest_mode(vcpu))
1880 eb |= get_vmcs12(vcpu)->exception_bitmap;
1881
abd3f2d6
AK
1882 vmcs_write32(EXCEPTION_BITMAP, eb);
1883}
1884
2961e876
GN
1885static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1886 unsigned long entry, unsigned long exit)
8bf00a52 1887{
2961e876
GN
1888 vm_entry_controls_clearbit(vmx, entry);
1889 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN
1890}
1891
61d2ef2c
AK
1892static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1893{
1894 unsigned i;
1895 struct msr_autoload *m = &vmx->msr_autoload;
1896
8bf00a52
GN
1897 switch (msr) {
1898 case MSR_EFER:
1899 if (cpu_has_load_ia32_efer) {
2961e876
GN
1900 clear_atomic_switch_msr_special(vmx,
1901 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN
1902 VM_EXIT_LOAD_IA32_EFER);
1903 return;
1904 }
1905 break;
1906 case MSR_CORE_PERF_GLOBAL_CTRL:
1907 if (cpu_has_load_perf_global_ctrl) {
2961e876 1908 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN
1909 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1910 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1911 return;
1912 }
1913 break;
110312c8
AK
1914 }
1915
61d2ef2c
AK
1916 for (i = 0; i < m->nr; ++i)
1917 if (m->guest[i].index == msr)
1918 break;
1919
1920 if (i == m->nr)
1921 return;
1922 --m->nr;
1923 m->guest[i] = m->guest[m->nr];
1924 m->host[i] = m->host[m->nr];
1925 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1926 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1927}
1928
2961e876
GN
1929static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1930 unsigned long entry, unsigned long exit,
1931 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1932 u64 guest_val, u64 host_val)
8bf00a52
GN
1933{
1934 vmcs_write64(guest_val_vmcs, guest_val);
1935 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN
1936 vm_entry_controls_setbit(vmx, entry);
1937 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN
1938}
1939
61d2ef2c
AK
1940static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1941 u64 guest_val, u64 host_val)
1942{
1943 unsigned i;
1944 struct msr_autoload *m = &vmx->msr_autoload;
1945
8bf00a52
GN
1946 switch (msr) {
1947 case MSR_EFER:
1948 if (cpu_has_load_ia32_efer) {
2961e876
GN
1949 add_atomic_switch_msr_special(vmx,
1950 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN
1951 VM_EXIT_LOAD_IA32_EFER,
1952 GUEST_IA32_EFER,
1953 HOST_IA32_EFER,
1954 guest_val, host_val);
1955 return;
1956 }
1957 break;
1958 case MSR_CORE_PERF_GLOBAL_CTRL:
1959 if (cpu_has_load_perf_global_ctrl) {
2961e876 1960 add_atomic_switch_msr_special(vmx,
8bf00a52
GN
1961 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1962 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1963 GUEST_IA32_PERF_GLOBAL_CTRL,
1964 HOST_IA32_PERF_GLOBAL_CTRL,
1965 guest_val, host_val);
1966 return;
1967 }
1968 break;
7099e2e1
RK
1969 case MSR_IA32_PEBS_ENABLE:
1970 /* PEBS needs a quiescent period after being disabled (to write
1971 * a record). Disabling PEBS through VMX MSR swapping doesn't
1972 * provide that period, so a CPU could write host's record into
1973 * guest's memory.
1974 */
1975 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK
1976 }
1977
61d2ef2c
AK
1978 for (i = 0; i < m->nr; ++i)
1979 if (m->guest[i].index == msr)
1980 break;
1981
e7fc6f93 1982 if (i == NR_AUTOLOAD_MSRS) {
60266204 1983 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN
1984 "Can't add msr %x\n", msr);
1985 return;
1986 } else if (i == m->nr) {
61d2ef2c
AK
1987 ++m->nr;
1988 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1989 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1990 }
1991
1992 m->guest[i].index = msr;
1993 m->guest[i].value = guest_val;
1994 m->host[i].index = msr;
1995 m->host[i].value = host_val;
1996}
1997
92c0d900 1998static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1999{
844a5fe2
PB
2000 u64 guest_efer = vmx->vcpu.arch.efer;
2001 u64 ignore_bits = 0;
2002
2003 if (!enable_ept) {
2004 /*
2005 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2006 * host CPUID is more efficient than testing guest CPUID
2007 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2008 */
2009 if (boot_cpu_has(X86_FEATURE_SMEP))
2010 guest_efer |= EFER_NX;
2011 else if (!(guest_efer & EFER_NX))
2012 ignore_bits |= EFER_NX;
2013 }
3a34a881 2014
51c6cf66 2015 /*
844a5fe2 2016 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 2017 */
844a5fe2 2018 ignore_bits |= EFER_SCE;
51c6cf66
AK
2019#ifdef CONFIG_X86_64
2020 ignore_bits |= EFER_LMA | EFER_LME;
2021 /* SCE is meaningful only in long mode on Intel */
2022 if (guest_efer & EFER_LMA)
2023 ignore_bits &= ~(u64)EFER_SCE;
2024#endif
84ad33ef
AK
2025
2026 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL
2027
2028 /*
2029 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2030 * On CPUs that support "load IA32_EFER", always switch EFER
2031 * atomically, since it's faster than switching it manually.
2032 */
2033 if (cpu_has_load_ia32_efer ||
2034 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK
2035 if (!(guest_efer & EFER_LMA))
2036 guest_efer &= ~EFER_LME;
54b98bff
AL
2037 if (guest_efer != host_efer)
2038 add_atomic_switch_msr(vmx, MSR_EFER,
2039 guest_efer, host_efer);
84ad33ef 2040 return false;
844a5fe2
PB
2041 } else {
2042 guest_efer &= ~ignore_bits;
2043 guest_efer |= host_efer & ignore_bits;
2044
2045 vmx->guest_msrs[efer_offset].data = guest_efer;
2046 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 2047
844a5fe2
PB
2048 return true;
2049 }
51c6cf66
AK
2050}
2051
e28baead
AL
2052#ifdef CONFIG_X86_32
2053/*
2054 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2055 * VMCS rather than the segment table. KVM uses this helper to figure
2056 * out the current bases to poke them into the VMCS before entry.
2057 */
2d49ec72
GN
2058static unsigned long segment_base(u16 selector)
2059{
8c2e41f7 2060 struct desc_struct *table;
2d49ec72
GN
2061 unsigned long v;
2062
8c2e41f7 2063 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN
2064 return 0;
2065
45fc8757 2066 table = get_current_gdt_ro();
2d49ec72 2067
8c2e41f7 2068 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN
2069 u16 ldt_selector = kvm_read_ldt();
2070
8c2e41f7 2071 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN
2072 return 0;
2073
8c2e41f7 2074 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 2075 }
8c2e41f7 2076 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN
2077 return v;
2078}
e28baead 2079#endif
2d49ec72 2080
04d2cc77 2081static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 2082{
04d2cc77 2083 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2084 int i;
04d2cc77 2085
a2fa3e9f 2086 if (vmx->host_state.loaded)
33ed6329
AK
2087 return;
2088
a2fa3e9f 2089 vmx->host_state.loaded = 1;
33ed6329
AK
2090 /*
2091 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2092 * allow segment selectors with cpl > 0 or ti == 1.
2093 */
d6e88aec 2094 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 2095 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 2096 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 2097 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 2098 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV
2099 vmx->host_state.fs_reload_needed = 0;
2100 } else {
33ed6329 2101 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 2102 vmx->host_state.fs_reload_needed = 1;
33ed6329 2103 }
9581d442 2104 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH
2105 if (!(vmx->host_state.gs_sel & 7))
2106 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK
2107 else {
2108 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 2109 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK
2110 }
2111
b2da15ac
AK
2112#ifdef CONFIG_X86_64
2113 savesegment(ds, vmx->host_state.ds_sel);
2114 savesegment(es, vmx->host_state.es_sel);
2115#endif
2116
33ed6329
AK
2117#ifdef CONFIG_X86_64
2118 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2119 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2120#else
a2fa3e9f
GH
2121 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2122 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 2123#endif
707c0874
AK
2124
2125#ifdef CONFIG_X86_64
c8770e7b
AK
2126 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2127 if (is_long_mode(&vmx->vcpu))
44ea2b17 2128 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 2129#endif
da8999d3
LJ
2130 if (boot_cpu_has(X86_FEATURE_MPX))
2131 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK
2132 for (i = 0; i < vmx->save_nmsrs; ++i)
2133 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK
2134 vmx->guest_msrs[i].data,
2135 vmx->guest_msrs[i].mask);
33ed6329
AK
2136}
2137
a9b21b62 2138static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 2139{
a2fa3e9f 2140 if (!vmx->host_state.loaded)
33ed6329
AK
2141 return;
2142
e1beb1d3 2143 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 2144 vmx->host_state.loaded = 0;
c8770e7b
AK
2145#ifdef CONFIG_X86_64
2146 if (is_long_mode(&vmx->vcpu))
2147 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2148#endif
152d3f2f 2149 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 2150 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 2151#ifdef CONFIG_X86_64
9581d442 2152 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK
2153#else
2154 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 2155#endif
33ed6329 2156 }
0a77fe4c
AK
2157 if (vmx->host_state.fs_reload_needed)
2158 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK
2159#ifdef CONFIG_X86_64
2160 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2161 loadsegment(ds, vmx->host_state.ds_sel);
2162 loadsegment(es, vmx->host_state.es_sel);
2163 }
b2da15ac 2164#endif
b7ffc44d 2165 invalidate_tss_limit();
44ea2b17 2166#ifdef CONFIG_X86_64
c8770e7b 2167 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 2168#endif
da8999d3
LJ
2169 if (vmx->host_state.msr_host_bndcfgs)
2170 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
45fc8757 2171 load_fixmap_gdt(raw_smp_processor_id());
33ed6329
AK
2172}
2173
a9b21b62
AK
2174static void vmx_load_host_state(struct vcpu_vmx *vmx)
2175{
2176 preempt_disable();
2177 __vmx_load_host_state(vmx);
2178 preempt_enable();
2179}
2180
28b835d6
FW
2181static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2182{
2183 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2184 struct pi_desc old, new;
2185 unsigned int dest;
2186
2187 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
2188 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2189 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW
2190 return;
2191
2192 do {
2193 old.control = new.control = pi_desc->control;
2194
2195 /*
2196 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2197 * are two possible cases:
2198 * 1. After running 'pre_block', context switch
2199 * happened. For this case, 'sn' was set in
2200 * vmx_vcpu_put(), so we need to clear it here.
2201 * 2. After running 'pre_block', we were blocked,
2202 * and woken up by some other guy. For this case,
2203 * we don't need to do anything, 'pi_post_block'
2204 * will do everything for us. However, we cannot
2205 * check whether it is case #1 or case #2 here
2206 * (maybe, not needed), so we also clear sn here,
2207 * I think it is not a big deal.
2208 */
2209 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2210 if (vcpu->cpu != cpu) {
2211 dest = cpu_physical_id(cpu);
2212
2213 if (x2apic_enabled())
2214 new.ndst = dest;
2215 else
2216 new.ndst = (dest << 8) & 0xFF00;
2217 }
2218
2219 /* set 'NV' to 'notification vector' */
2220 new.nv = POSTED_INTR_VECTOR;
2221 }
2222
2223 /* Allow posting non-urgent interrupts */
2224 new.sn = 0;
2225 } while (cmpxchg(&pi_desc->control, old.control,
2226 new.control) != old.control);
2227}
1be0e61c 2228
c95ba92a
PF
2229static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2230{
2231 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2232 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2233}
2234
6aa8b732
AK
2235/*
2236 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2237 * vcpu mutex is already taken.
2238 */
15ad7146 2239static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 2240{
a2fa3e9f 2241 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 2242 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 2243
b80c76ec 2244 if (!already_loaded) {
fe0e80be 2245 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 2246 local_irq_disable();
8f536b76 2247 crash_disable_local_vmclear(cpu);
5a560f8b
XG
2248
2249 /*
2250 * Read loaded_vmcs->cpu should be before fetching
2251 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2252 * See the comments in __loaded_vmcs_clear().
2253 */
2254 smp_rmb();
2255
d462b819
NHE
2256 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2257 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 2258 crash_enable_local_vmclear(cpu);
92fe13be 2259 local_irq_enable();
b80c76ec
JM
2260 }
2261
2262 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2263 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2264 vmcs_load(vmx->loaded_vmcs->vmcs);
2265 }
2266
2267 if (!already_loaded) {
59c58ceb 2268 void *gdt = get_current_gdt_ro();
b80c76ec
JM
2269 unsigned long sysenter_esp;
2270
2271 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 2272
6aa8b732
AK
2273 /*
2274 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 2275 * processors. See 22.2.4.
6aa8b732 2276 */
e0c23063
AL
2277 vmcs_writel(HOST_TR_BASE,
2278 (unsigned long)this_cpu_ptr(&cpu_tss));
59c58ceb 2279 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732 2280
b7ffc44d
AL
2281 /*
2282 * VM exits change the host TR limit to 0x67 after a VM
2283 * exit. This is okay, since 0x67 covers everything except
2284 * the IO bitmap and have have code to handle the IO bitmap
2285 * being lost after a VM exit.
2286 */
2287 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2288
6aa8b732
AK
2289 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2290 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 2291
d462b819 2292 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 2293 }
28b835d6 2294
2680d6da
OH
2295 /* Setup TSC multiplier */
2296 if (kvm_has_tsc_control &&
c95ba92a
PF
2297 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2298 decache_tsc_multiplier(vmx);
2680d6da 2299
28b835d6 2300 vmx_vcpu_pi_load(vcpu, cpu);
1be0e61c 2301 vmx->host_pkru = read_pkru();
28b835d6
FW
2302}
2303
2304static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2305{
2306 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2307
2308 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
2309 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2310 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW
2311 return;
2312
2313 /* Set SN when the vCPU is preempted */
2314 if (vcpu->preempted)
2315 pi_set_sn(pi_desc);
6aa8b732
AK
2316}
2317
2318static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2319{
28b835d6
FW
2320 vmx_vcpu_pi_put(vcpu);
2321
a9b21b62 2322 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK
2323}
2324
edcafe3c
AK
2325static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2326
fe3ef05c
NHE
2327/*
2328 * Return the cr0 value that a nested guest would read. This is a combination
2329 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2330 * its hypervisor (cr0_read_shadow).
2331 */
2332static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2333{
2334 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2335 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2336}
2337static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2338{
2339 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2340 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2341}
2342
6aa8b732
AK
2343static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2344{
78ac8b47 2345 unsigned long rflags, save_rflags;
345dcaa8 2346
6de12732
AK
2347 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2348 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2349 rflags = vmcs_readl(GUEST_RFLAGS);
2350 if (to_vmx(vcpu)->rmode.vm86_active) {
2351 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2352 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2353 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2354 }
2355 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2356 }
6de12732 2357 return to_vmx(vcpu)->rflags;
6aa8b732
AK
2358}
2359
2360static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2361{
6de12732
AK
2362 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2363 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK
2364 if (to_vmx(vcpu)->rmode.vm86_active) {
2365 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2366 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2367 }
6aa8b732
AK
2368 vmcs_writel(GUEST_RFLAGS, rflags);
2369}
2370
be94f6b7
HH
2371static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2372{
2373 return to_vmx(vcpu)->guest_pkru;
2374}
2375
37ccdcbe 2376static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC
2377{
2378 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2379 int ret = 0;
2380
2381 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2382 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2383 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2384 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2385
37ccdcbe 2386 return ret;
2809f5d2
GC
2387}
2388
2389static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2390{
2391 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2392 u32 interruptibility = interruptibility_old;
2393
2394 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2395
48005f64 2396 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2397 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2398 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC
2399 interruptibility |= GUEST_INTR_STATE_STI;
2400
2401 if ((interruptibility != interruptibility_old))
2402 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2403}
2404
6aa8b732
AK
2405static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2406{
2407 unsigned long rip;
6aa8b732 2408
5fdbf976 2409 rip = kvm_rip_read(vcpu);
6aa8b732 2410 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2411 kvm_rip_write(vcpu, rip);
6aa8b732 2412
2809f5d2
GC
2413 /* skipping an emulated instruction also counts */
2414 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK
2415}
2416
0b6ac343
NHE
2417/*
2418 * KVM wants to inject page-faults which it got to the guest. This function
2419 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2420 */
e011c663 2421static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE
2422{
2423 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2424
e011c663 2425 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE
2426 return 0;
2427
533558bc
JK
2428 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2429 vmcs_read32(VM_EXIT_INTR_INFO),
2430 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE
2431 return 1;
2432}
2433
298101da 2434static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR
2435 bool has_error_code, u32 error_code,
2436 bool reinject)
298101da 2437{
77ab6db0 2438 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2439 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2440
e011c663
GN
2441 if (!reinject && is_guest_mode(vcpu) &&
2442 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE
2443 return;
2444
8ab2d2e2 2445 if (has_error_code) {
77ab6db0 2446 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK
2447 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2448 }
77ab6db0 2449
7ffd92c5 2450 if (vmx->rmode.vm86_active) {
71f9833b
SH
2451 int inc_eip = 0;
2452 if (kvm_exception_is_soft(nr))
2453 inc_eip = vcpu->arch.event_exit_inst_len;
2454 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2455 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK
2456 return;
2457 }
2458
66fd3f7f
GN
2459 if (kvm_exception_is_soft(nr)) {
2460 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2461 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK
2462 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2463 } else
2464 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2465
2466 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK
2467}
2468
4e47c7a6
SY
2469static bool vmx_rdtscp_supported(void)
2470{
2471 return cpu_has_vmx_rdtscp();
2472}
2473
ad756a16
MJ
2474static bool vmx_invpcid_supported(void)
2475{
2476 return cpu_has_vmx_invpcid() && enable_ept;
2477}
2478
a75beee6
ED
2479/*
2480 * Swap MSR entry in host/guest MSR entry array.
2481 */
8b9cf98c 2482static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2483{
26bb0981 2484 struct shared_msr_entry tmp;
a2fa3e9f
GH
2485
2486 tmp = vmx->guest_msrs[to];
2487 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2488 vmx->guest_msrs[from] = tmp;
a75beee6
ED
2489}
2490
8d14695f
YZ
2491static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2492{
2493 unsigned long *msr_bitmap;
2494
670125bd 2495 if (is_guest_mode(vcpu))
d048c098 2496 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
3ce424e4
RK
2497 else if (cpu_has_secondary_exec_ctrls() &&
2498 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2499 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
f6e90f9e
WL
2500 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2501 if (is_long_mode(vcpu))
c63e4563 2502 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
f6e90f9e 2503 else
c63e4563 2504 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
f6e90f9e
WL
2505 } else {
2506 if (is_long_mode(vcpu))
c63e4563 2507 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
f6e90f9e 2508 else
c63e4563 2509 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
f6e90f9e 2510 }
8d14695f
YZ
2511 } else {
2512 if (is_long_mode(vcpu))
2513 msr_bitmap = vmx_msr_bitmap_longmode;
2514 else
2515 msr_bitmap = vmx_msr_bitmap_legacy;
2516 }
2517
2518 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2519}
2520
e38aea3e
AK
2521/*
2522 * Set up the vmcs to automatically save and restore system
2523 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2524 * mode, as fiddling with msrs is very expensive.
2525 */
8b9cf98c 2526static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2527{
26bb0981 2528 int save_nmsrs, index;
e38aea3e 2529
a75beee6
ED
2530 save_nmsrs = 0;
2531#ifdef CONFIG_X86_64
8b9cf98c 2532 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2533 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2534 if (index >= 0)
8b9cf98c
RR
2535 move_msr_up(vmx, index, save_nmsrs++);
2536 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2537 if (index >= 0)
8b9cf98c
RR
2538 move_msr_up(vmx, index, save_nmsrs++);
2539 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2540 if (index >= 0)
8b9cf98c 2541 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6 2542 index = __find_msr_index(vmx, MSR_TSC_AUX);
1cea0ce6 2543 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
4e47c7a6 2544 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2545 /*
8c06585d 2546 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED
2547 * if efer.sce is enabled.
2548 */
8c06585d 2549 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2550 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2551 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED
2552 }
2553#endif
92c0d900
AK
2554 index = __find_msr_index(vmx, MSR_EFER);
2555 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2556 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2557
26bb0981 2558 vmx->save_nmsrs = save_nmsrs;
5897297b 2559
8d14695f
YZ
2560 if (cpu_has_vmx_msr_bitmap())
2561 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK
2562}
2563
6aa8b732
AK
2564/*
2565 * reads and returns guest's timestamp counter "register"
be7b263e
HZ
2566 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2567 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
6aa8b732 2568 */
be7b263e 2569static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
6aa8b732
AK
2570{
2571 u64 host_tsc, tsc_offset;
2572
4ea1636b 2573 host_tsc = rdtsc();
6aa8b732 2574 tsc_offset = vmcs_read64(TSC_OFFSET);
be7b263e 2575 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
6aa8b732
AK
2576}
2577
2578/*
99e3e30a 2579 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2580 */
99e3e30a 2581static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2582{
27fc51b2 2583 if (is_guest_mode(vcpu)) {
7991825b 2584 /*
27fc51b2
NHE
2585 * We're here if L1 chose not to trap WRMSR to TSC. According
2586 * to the spec, this should set L1's TSC; The offset that L1
2587 * set for L2 remains unchanged, and still needs to be added
2588 * to the newly set TSC to get L2's TSC.
7991825b 2589 */
27fc51b2 2590 struct vmcs12 *vmcs12;
27fc51b2
NHE
2591 /* recalculate vmcs02.TSC_OFFSET: */
2592 vmcs12 = get_vmcs12(vcpu);
2593 vmcs_write64(TSC_OFFSET, offset +
2594 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2595 vmcs12->tsc_offset : 0));
2596 } else {
489223ed
YY
2597 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2598 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE
2599 vmcs_write64(TSC_OFFSET, offset);
2600 }
6aa8b732
AK
2601}
2602
801d3424
NHE
2603static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2604{
2605 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2606 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2607}
2608
2609/*
2610 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2611 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2612 * all guests if the "nested" module option is off, and can also be disabled
2613 * for a single guest by disabling its VMX cpuid bit.
2614 */
2615static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2616{
2617 return nested && guest_cpuid_has_vmx(vcpu);
2618}
2619
b87a51ae
NHE
2620/*
2621 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2622 * returned for the various VMX controls MSRs when nested VMX is enabled.
2623 * The same values should also be used to verify that vmcs12 control fields are
2624 * valid during nested entry from L1 to L2.
2625 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2626 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2627 * bit in the high half is on if the corresponding bit in the control field
2628 * may be on. See also vmx_control_verify().
b87a51ae 2629 */
b9c237bb 2630static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE
2631{
2632 /*
2633 * Note that as a general rule, the high half of the MSRs (bits in
2634 * the control fields which may be 1) should be initialized by the
2635 * intersection of the underlying hardware's MSR (i.e., features which
2636 * can be supported) and the list of features we want to expose -
2637 * because they are known to be properly supported in our code.
2638 * Also, usually, the low half of the MSRs (bits which must be 1) can
2639 * be set to 0, meaning that L1 may turn off any of these bits. The
2640 * reason is that if one of these bits is necessary, it will appear
2641 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2642 * fields of vmcs01 and vmcs02, will turn these bits off - and
2643 * nested_vmx_exit_handled() will not pass related exits to L1.
2644 * These rules have exceptions below.
2645 */
2646
2647 /* pin-based controls */
eabeaacc 2648 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV
2649 vmx->nested.nested_vmx_pinbased_ctls_low,
2650 vmx->nested.nested_vmx_pinbased_ctls_high);
2651 vmx->nested.nested_vmx_pinbased_ctls_low |=
2652 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2653 vmx->nested.nested_vmx_pinbased_ctls_high &=
2654 PIN_BASED_EXT_INTR_MASK |
2655 PIN_BASED_NMI_EXITING |
2656 PIN_BASED_VIRTUAL_NMIS;
2657 vmx->nested.nested_vmx_pinbased_ctls_high |=
2658 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2659 PIN_BASED_VMX_PREEMPTION_TIMER;
d62caabb 2660 if (kvm_vcpu_apicv_active(&vmx->vcpu))
705699a1
WV
2661 vmx->nested.nested_vmx_pinbased_ctls_high |=
2662 PIN_BASED_POSTED_INTR;
b87a51ae 2663
3dbcd8da 2664 /* exit controls */
c0dfee58 2665 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV
2666 vmx->nested.nested_vmx_exit_ctls_low,
2667 vmx->nested.nested_vmx_exit_ctls_high);
2668 vmx->nested.nested_vmx_exit_ctls_low =
2669 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2670
b9c237bb 2671 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2672#ifdef CONFIG_X86_64
c0dfee58 2673 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2674#endif
f4124500 2675 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV
2676 vmx->nested.nested_vmx_exit_ctls_high |=
2677 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2678 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD
2679 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2680
a87036ad 2681 if (kvm_mpx_supported())
b9c237bb 2682 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2683
2996fca0 2684 /* We support free control of debug control saving. */
0115f9cb 2685 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2996fca0 2686
b87a51ae
NHE
2687 /* entry controls */
2688 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV
2689 vmx->nested.nested_vmx_entry_ctls_low,
2690 vmx->nested.nested_vmx_entry_ctls_high);
2691 vmx->nested.nested_vmx_entry_ctls_low =
2692 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2693 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK
2694#ifdef CONFIG_X86_64
2695 VM_ENTRY_IA32E_MODE |
2696#endif
2697 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV
2698 vmx->nested.nested_vmx_entry_ctls_high |=
2699 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
a87036ad 2700 if (kvm_mpx_supported())
b9c237bb 2701 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2702
2996fca0 2703 /* We support free control of debug control loading. */
0115f9cb 2704 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2996fca0 2705
b87a51ae
NHE
2706 /* cpu-based controls */
2707 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV
2708 vmx->nested.nested_vmx_procbased_ctls_low,
2709 vmx->nested.nested_vmx_procbased_ctls_high);
2710 vmx->nested.nested_vmx_procbased_ctls_low =
2711 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2712 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK
2713 CPU_BASED_VIRTUAL_INTR_PENDING |
2714 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE
2715 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2716 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2717 CPU_BASED_CR3_STORE_EXITING |
2718#ifdef CONFIG_X86_64
2719 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2720#endif
2721 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD
2722 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2723 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2724 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2725 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE
2726 /*
2727 * We can allow some features even when not supported by the
2728 * hardware. For example, L1 can specify an MSR bitmap - and we
2729 * can use it to avoid exits to L1 - even when L0 runs L2
2730 * without MSR bitmaps.
2731 */
b9c237bb
WV
2732 vmx->nested.nested_vmx_procbased_ctls_high |=
2733 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2734 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2735
3dcdf3ec 2736 /* We support free control of CR3 access interception. */
0115f9cb 2737 vmx->nested.nested_vmx_procbased_ctls_low &=
3dcdf3ec
JK
2738 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2739
b87a51ae
NHE
2740 /* secondary cpu-based controls */
2741 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV
2742 vmx->nested.nested_vmx_secondary_ctls_low,
2743 vmx->nested.nested_vmx_secondary_ctls_high);
2744 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2745 vmx->nested.nested_vmx_secondary_ctls_high &=
a5f46457 2746 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
d6851fbe 2747 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2748 SECONDARY_EXEC_RDTSCP |
1b07304c 2749 SECONDARY_EXEC_DESC |
f2b93280 2750 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2751 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2752 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7 2753 SECONDARY_EXEC_WBINVD_EXITING |
dfa169bb 2754 SECONDARY_EXEC_XSAVES;
c18911a2 2755
afa61f75
NHE
2756 if (enable_ept) {
2757 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2758 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2759 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2760 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
7db74265 2761 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
02120c45
BD
2762 if (cpu_has_vmx_ept_execute_only())
2763 vmx->nested.nested_vmx_ept_caps |=
2764 VMX_EPT_EXECUTE_ONLY_BIT;
b9c237bb 2765 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
45e11817 2766 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
7db74265
PB
2767 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2768 VMX_EPT_1GB_PAGE_BIT;
03efce6f
BD
2769 if (enable_ept_ad_bits) {
2770 vmx->nested.nested_vmx_secondary_ctls_high |=
2771 SECONDARY_EXEC_ENABLE_PML;
7461fbc4 2772 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
03efce6f 2773 }
afa61f75 2774 } else
b9c237bb 2775 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2776
ef697a71
PB
2777 /*
2778 * Old versions of KVM use the single-context version without
2779 * checking for support, so declare that it is supported even
2780 * though it is treated as global context. The alternative is
2781 * not failing the single-context invvpid, and it is worse.
2782 */
63cb6d5f
WL
2783 if (enable_vpid) {
2784 vmx->nested.nested_vmx_secondary_ctls_high |=
2785 SECONDARY_EXEC_ENABLE_VPID;
089d7b6e 2786 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
bcdde302 2787 VMX_VPID_EXTENT_SUPPORTED_MASK;
63cb6d5f 2788 } else
089d7b6e 2789 vmx->nested.nested_vmx_vpid_caps = 0;
99b83ac8 2790
0790ec17
RK
2791 if (enable_unrestricted_guest)
2792 vmx->nested.nested_vmx_secondary_ctls_high |=
2793 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2794
c18911a2 2795 /* miscellaneous data */
b9c237bb
WV
2796 rdmsr(MSR_IA32_VMX_MISC,
2797 vmx->nested.nested_vmx_misc_low,
2798 vmx->nested.nested_vmx_misc_high);
2799 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2800 vmx->nested.nested_vmx_misc_low |=
2801 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2802 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2803 vmx->nested.nested_vmx_misc_high = 0;
62cc6b9d
DM
2804
2805 /*
2806 * This MSR reports some information about VMX support. We
2807 * should return information about the VMX we emulate for the
2808 * guest, and the VMCS structure we give it - not about the
2809 * VMX support of the underlying hardware.
2810 */
2811 vmx->nested.nested_vmx_basic =
2812 VMCS12_REVISION |
2813 VMX_BASIC_TRUE_CTLS |
2814 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2815 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2816
2817 if (cpu_has_vmx_basic_inout())
2818 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2819
2820 /*
8322ebbb 2821 * These MSRs specify bits which the guest must keep fixed on
62cc6b9d
DM
2822 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2823 * We picked the standard core2 setting.
2824 */
2825#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2826#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2827 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
62cc6b9d 2828 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
8322ebbb
DM
2829
2830 /* These MSRs specify bits which the guest must keep fixed off. */
2831 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2832 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
62cc6b9d
DM
2833
2834 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2835 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
b87a51ae
NHE
2836}
2837
3899152c
DM
2838/*
2839 * if fixed0[i] == 1: val[i] must be 1
2840 * if fixed1[i] == 0: val[i] must be 0
2841 */
2842static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2843{
2844 return ((val & fixed1) | fixed0) == val;
b87a51ae
NHE
2845}
2846
2847static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2848{
3899152c 2849 return fixed_bits_valid(control, low, high);
b87a51ae
NHE
2850}
2851
2852static inline u64 vmx_control_msr(u32 low, u32 high)
2853{
2854 return low | ((u64)high << 32);
2855}
2856
62cc6b9d
DM
2857static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2858{
2859 superset &= mask;
2860 subset &= mask;
2861
2862 return (superset | subset) == superset;
2863}
2864
2865static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2866{
2867 const u64 feature_and_reserved =
2868 /* feature (except bit 48; see below) */
2869 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2870 /* reserved */
2871 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2872 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2873
2874 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2875 return -EINVAL;
2876
2877 /*
2878 * KVM does not emulate a version of VMX that constrains physical
2879 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2880 */
2881 if (data & BIT_ULL(48))
2882 return -EINVAL;
2883
2884 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2885 vmx_basic_vmcs_revision_id(data))
2886 return -EINVAL;
2887
2888 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2889 return -EINVAL;
2890
2891 vmx->nested.nested_vmx_basic = data;
2892 return 0;
2893}
2894
2895static int
2896vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2897{
2898 u64 supported;
2899 u32 *lowp, *highp;
2900
2901 switch (msr_index) {
2902 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2903 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2904 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2905 break;
2906 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2907 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2908 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2909 break;
2910 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2911 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2912 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2913 break;
2914 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2915 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2916 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2917 break;
2918 case MSR_IA32_VMX_PROCBASED_CTLS2:
2919 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2920 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2921 break;
2922 default:
2923 BUG();
2924 }
2925
2926 supported = vmx_control_msr(*lowp, *highp);
2927
2928 /* Check must-be-1 bits are still 1. */
2929 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2930 return -EINVAL;
2931
2932 /* Check must-be-0 bits are still 0. */
2933 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2934 return -EINVAL;
2935
2936 *lowp = data;
2937 *highp = data >> 32;
2938 return 0;
2939}
2940
2941static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2942{
2943 const u64 feature_and_reserved_bits =
2944 /* feature */
2945 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2946 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2947 /* reserved */
2948 GENMASK_ULL(13, 9) | BIT_ULL(31);
2949 u64 vmx_misc;
2950
2951 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2952 vmx->nested.nested_vmx_misc_high);
2953
2954 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2955 return -EINVAL;
2956
2957 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2958 PIN_BASED_VMX_PREEMPTION_TIMER) &&
2959 vmx_misc_preemption_timer_rate(data) !=
2960 vmx_misc_preemption_timer_rate(vmx_misc))
2961 return -EINVAL;
2962
2963 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2964 return -EINVAL;
2965
2966 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2967 return -EINVAL;
2968
2969 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2970 return -EINVAL;
2971
2972 vmx->nested.nested_vmx_misc_low = data;
2973 vmx->nested.nested_vmx_misc_high = data >> 32;
2974 return 0;
2975}
2976
2977static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2978{
2979 u64 vmx_ept_vpid_cap;
2980
2981 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2982 vmx->nested.nested_vmx_vpid_caps);
2983
2984 /* Every bit is either reserved or a feature bit. */
2985 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2986 return -EINVAL;
2987
2988 vmx->nested.nested_vmx_ept_caps = data;
2989 vmx->nested.nested_vmx_vpid_caps = data >> 32;
2990 return 0;
2991}
2992
2993static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2994{
2995 u64 *msr;
2996
2997 switch (msr_index) {
2998 case MSR_IA32_VMX_CR0_FIXED0:
2999 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3000 break;
3001 case MSR_IA32_VMX_CR4_FIXED0:
3002 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3003 break;
3004 default:
3005 BUG();
3006 }
3007
3008 /*
3009 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3010 * must be 1 in the restored value.
3011 */
3012 if (!is_bitwise_subset(data, *msr, -1ULL))
3013 return -EINVAL;
3014
3015 *msr = data;
3016 return 0;
3017}
3018
3019/*
3020 * Called when userspace is restoring VMX MSRs.
3021 *
3022 * Returns 0 on success, non-0 otherwise.
3023 */
3024static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
b87a51ae 3025{
b9c237bb
WV
3026 struct vcpu_vmx *vmx = to_vmx(vcpu);
3027
b87a51ae 3028 switch (msr_index) {
b87a51ae 3029 case MSR_IA32_VMX_BASIC:
62cc6b9d
DM
3030 return vmx_restore_vmx_basic(vmx, data);
3031 case MSR_IA32_VMX_PINBASED_CTLS:
3032 case MSR_IA32_VMX_PROCBASED_CTLS:
3033 case MSR_IA32_VMX_EXIT_CTLS:
3034 case MSR_IA32_VMX_ENTRY_CTLS:
b87a51ae 3035 /*
62cc6b9d
DM
3036 * The "non-true" VMX capability MSRs are generated from the
3037 * "true" MSRs, so we do not support restoring them directly.
3038 *
3039 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3040 * should restore the "true" MSRs with the must-be-1 bits
3041 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3042 * DEFAULT SETTINGS".
b87a51ae 3043 */
62cc6b9d
DM
3044 return -EINVAL;
3045 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3046 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3047 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3048 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3049 case MSR_IA32_VMX_PROCBASED_CTLS2:
3050 return vmx_restore_control_msr(vmx, msr_index, data);
3051 case MSR_IA32_VMX_MISC:
3052 return vmx_restore_vmx_misc(vmx, data);
3053 case MSR_IA32_VMX_CR0_FIXED0:
3054 case MSR_IA32_VMX_CR4_FIXED0:
3055 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3056 case MSR_IA32_VMX_CR0_FIXED1:
3057 case MSR_IA32_VMX_CR4_FIXED1:
3058 /*
3059 * These MSRs are generated based on the vCPU's CPUID, so we
3060 * do not support restoring them directly.
3061 */
3062 return -EINVAL;
3063 case MSR_IA32_VMX_EPT_VPID_CAP:
3064 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3065 case MSR_IA32_VMX_VMCS_ENUM:
3066 vmx->nested.nested_vmx_vmcs_enum = data;
3067 return 0;
3068 default:
b87a51ae 3069 /*
62cc6b9d 3070 * The rest of the VMX capability MSRs do not support restore.
b87a51ae 3071 */
62cc6b9d
DM
3072 return -EINVAL;
3073 }
3074}
3075
3076/* Returns 0 on success, non-0 otherwise. */
3077static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3078{
3079 struct vcpu_vmx *vmx = to_vmx(vcpu);
3080
3081 switch (msr_index) {
3082 case MSR_IA32_VMX_BASIC:
3083 *pdata = vmx->nested.nested_vmx_basic;
b87a51ae
NHE
3084 break;
3085 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3086 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV
3087 *pdata = vmx_control_msr(
3088 vmx->nested.nested_vmx_pinbased_ctls_low,
3089 vmx->nested.nested_vmx_pinbased_ctls_high);
0115f9cb
DM
3090 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3091 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3092 break;
3093 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3094 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV
3095 *pdata = vmx_control_msr(
3096 vmx->nested.nested_vmx_procbased_ctls_low,
3097 vmx->nested.nested_vmx_procbased_ctls_high);
0115f9cb
DM
3098 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3099 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3100 break;
3101 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3102 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV
3103 *pdata = vmx_control_msr(
3104 vmx->nested.nested_vmx_exit_ctls_low,
3105 vmx->nested.nested_vmx_exit_ctls_high);
0115f9cb
DM
3106 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3107 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3108 break;
3109 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3110 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV
3111 *pdata = vmx_control_msr(
3112 vmx->nested.nested_vmx_entry_ctls_low,
3113 vmx->nested.nested_vmx_entry_ctls_high);
0115f9cb
DM
3114 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3115 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3116 break;
3117 case MSR_IA32_VMX_MISC:
b9c237bb
WV
3118 *pdata = vmx_control_msr(
3119 vmx->nested.nested_vmx_misc_low,
3120 vmx->nested.nested_vmx_misc_high);
b87a51ae 3121 break;
b87a51ae 3122 case MSR_IA32_VMX_CR0_FIXED0:
62cc6b9d 3123 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
b87a51ae
NHE
3124 break;
3125 case MSR_IA32_VMX_CR0_FIXED1:
62cc6b9d 3126 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
b87a51ae
NHE
3127 break;
3128 case MSR_IA32_VMX_CR4_FIXED0:
62cc6b9d 3129 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
b87a51ae
NHE
3130 break;
3131 case MSR_IA32_VMX_CR4_FIXED1:
62cc6b9d 3132 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
b87a51ae
NHE
3133 break;
3134 case MSR_IA32_VMX_VMCS_ENUM:
62cc6b9d 3135 *pdata = vmx->nested.nested_vmx_vmcs_enum;
b87a51ae
NHE
3136 break;
3137 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV
3138 *pdata = vmx_control_msr(
3139 vmx->nested.nested_vmx_secondary_ctls_low,
3140 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE
3141 break;
3142 case MSR_IA32_VMX_EPT_VPID_CAP:
089d7b6e
WL
3143 *pdata = vmx->nested.nested_vmx_ept_caps |
3144 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
b87a51ae
NHE
3145 break;
3146 default:
b87a51ae 3147 return 1;
b3897a49
NHE
3148 }
3149
b87a51ae
NHE
3150 return 0;
3151}
3152
37e4c997
HZ
3153static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3154 uint64_t val)
3155{
3156 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3157
3158 return !(val & ~valid_bits);
3159}
3160
6aa8b732
AK
3161/*
3162 * Reads an msr value (of 'msr_index') into 'pdata'.
3163 * Returns 0 on success, non-0 otherwise.
3164 * Assumes vcpu_load() was already called.
3165 */
609e36d3 3166static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 3167{
26bb0981 3168 struct shared_msr_entry *msr;
6aa8b732 3169
609e36d3 3170 switch (msr_info->index) {
05b3e0c2 3171#ifdef CONFIG_X86_64
6aa8b732 3172 case MSR_FS_BASE:
609e36d3 3173 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK
3174 break;
3175 case MSR_GS_BASE:
609e36d3 3176 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 3177 break;
44ea2b17
AK
3178 case MSR_KERNEL_GS_BASE:
3179 vmx_load_host_state(to_vmx(vcpu));
609e36d3 3180 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 3181 break;
26bb0981 3182#endif
6aa8b732 3183 case MSR_EFER:
609e36d3 3184 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 3185 case MSR_IA32_TSC:
be7b263e 3186 msr_info->data = guest_read_tsc(vcpu);
6aa8b732
AK
3187 break;
3188 case MSR_IA32_SYSENTER_CS:
609e36d3 3189 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK
3190 break;
3191 case MSR_IA32_SYSENTER_EIP:
609e36d3 3192 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK
3193 break;
3194 case MSR_IA32_SYSENTER_ESP:
609e36d3 3195 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 3196 break;
0dd376e7 3197 case MSR_IA32_BNDCFGS:
4439af9f 3198 if (!kvm_mpx_supported() || !guest_cpuid_has_mpx(vcpu))
93c4adc7 3199 return 1;
609e36d3 3200 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 3201 break;
c45dcc71
AR
3202 case MSR_IA32_MCG_EXT_CTL:
3203 if (!msr_info->host_initiated &&
3204 !(to_vmx(vcpu)->msr_ia32_feature_control &
3205 FEATURE_CONTROL_LMCE))
cae50139 3206 return 1;
c45dcc71
AR
3207 msr_info->data = vcpu->arch.mcg_ext_ctl;
3208 break;
cae50139 3209 case MSR_IA32_FEATURE_CONTROL:
3b84080b 3210 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
cae50139
JK
3211 break;
3212 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3213 if (!nested_vmx_allowed(vcpu))
3214 return 1;
609e36d3 3215 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL
3216 case MSR_IA32_XSS:
3217 if (!vmx_xsaves_supported())
3218 return 1;
609e36d3 3219 msr_info->data = vcpu->arch.ia32_xss;
20300099 3220 break;
4e47c7a6 3221 case MSR_TSC_AUX:
81b1b9ca 3222 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
4e47c7a6
SY
3223 return 1;
3224 /* Otherwise falls through */
6aa8b732 3225 default:
609e36d3 3226 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 3227 if (msr) {
609e36d3 3228 msr_info->data = msr->data;
3bab1f5d 3229 break;
6aa8b732 3230 }
609e36d3 3231 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK
3232 }
3233
6aa8b732
AK
3234 return 0;
3235}
3236
cae50139
JK
3237static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3238
6aa8b732
AK
3239/*
3240 * Writes msr value into into the appropriate "register".
3241 * Returns 0 on success, non-0 otherwise.
3242 * Assumes vcpu_load() was already called.
3243 */
8fe8ab46 3244static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 3245{
a2fa3e9f 3246 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 3247 struct shared_msr_entry *msr;
2cc51560 3248 int ret = 0;
8fe8ab46
WA
3249 u32 msr_index = msr_info->index;
3250 u64 data = msr_info->data;
2cc51560 3251
6aa8b732 3252 switch (msr_index) {
3bab1f5d 3253 case MSR_EFER:
8fe8ab46 3254 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 3255 break;
16175a79 3256#ifdef CONFIG_X86_64
6aa8b732 3257 case MSR_FS_BASE:
2fb92db1 3258 vmx_segment_cache_clear(vmx);
6aa8b732
AK
3259 vmcs_writel(GUEST_FS_BASE, data);
3260 break;
3261 case MSR_GS_BASE:
2fb92db1 3262 vmx_segment_cache_clear(vmx);
6aa8b732
AK
3263 vmcs_writel(GUEST_GS_BASE, data);
3264 break;
44ea2b17
AK
3265 case MSR_KERNEL_GS_BASE:
3266 vmx_load_host_state(vmx);
3267 vmx->msr_guest_kernel_gs_base = data;
3268 break;
6aa8b732
AK
3269#endif
3270 case MSR_IA32_SYSENTER_CS:
3271 vmcs_write32(GUEST_SYSENTER_CS, data);
3272 break;
3273 case MSR_IA32_SYSENTER_EIP:
f5b42c33 3274 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK
3275 break;
3276 case MSR_IA32_SYSENTER_ESP:
f5b42c33 3277 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 3278 break;
0dd376e7 3279 case MSR_IA32_BNDCFGS:
4439af9f 3280 if (!kvm_mpx_supported() || !guest_cpuid_has_mpx(vcpu))
93c4adc7 3281 return 1;
4531662d
JM
3282 if (is_noncanonical_address(data & PAGE_MASK) ||
3283 (data & MSR_IA32_BNDCFGS_RSVD))
3284 return 1;
0dd376e7
LJ
3285 vmcs_write64(GUEST_BNDCFGS, data);
3286 break;
af24a4e4 3287 case MSR_IA32_TSC:
8fe8ab46 3288 kvm_write_tsc(vcpu, msr_info);
6aa8b732 3289 break;
468d472f
SY
3290 case MSR_IA32_CR_PAT:
3291 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA
3292 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3293 return 1;
468d472f
SY
3294 vmcs_write64(GUEST_IA32_PAT, data);
3295 vcpu->arch.pat = data;
3296 break;
3297 }
8fe8ab46 3298 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 3299 break;
ba904635
WA
3300 case MSR_IA32_TSC_ADJUST:
3301 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 3302 break;
c45dcc71
AR
3303 case MSR_IA32_MCG_EXT_CTL:
3304 if ((!msr_info->host_initiated &&
3305 !(to_vmx(vcpu)->msr_ia32_feature_control &
3306 FEATURE_CONTROL_LMCE)) ||
3307 (data & ~MCG_EXT_CTL_LMCE_EN))
3308 return 1;
3309 vcpu->arch.mcg_ext_ctl = data;
3310 break;
cae50139 3311 case MSR_IA32_FEATURE_CONTROL:
37e4c997 3312 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 3313 (to_vmx(vcpu)->msr_ia32_feature_control &
cae50139
JK
3314 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3315 return 1;
3b84080b 3316 vmx->msr_ia32_feature_control = data;
cae50139
JK
3317 if (msr_info->host_initiated && data == 0)
3318 vmx_leave_nested(vcpu);
3319 break;
3320 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM
3321 if (!msr_info->host_initiated)
3322 return 1; /* they are read-only */
3323 if (!nested_vmx_allowed(vcpu))
3324 return 1;
3325 return vmx_set_vmx_msr(vcpu, msr_index, data);
20300099
WL
3326 case MSR_IA32_XSS:
3327 if (!vmx_xsaves_supported())
3328 return 1;
3329 /*
3330 * The only supported bit as of Skylake is bit 8, but
3331 * it is not supported on KVM.
3332 */
3333 if (data != 0)
3334 return 1;
3335 vcpu->arch.ia32_xss = data;
3336 if (vcpu->arch.ia32_xss != host_xss)
3337 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3338 vcpu->arch.ia32_xss, host_xss);
3339 else
3340 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3341 break;
4e47c7a6 3342 case MSR_TSC_AUX:
81b1b9ca 3343 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
4e47c7a6
SY
3344 return 1;
3345 /* Check reserved bit, higher 32 bits should be zero */
3346 if ((data >> 32) != 0)
3347 return 1;
3348 /* Otherwise falls through */
6aa8b732 3349 default:
8b9cf98c 3350 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 3351 if (msr) {
8b3c3104 3352 u64 old_msr_data = msr->data;
3bab1f5d 3353 msr->data = data;
2225fd56
AK
3354 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3355 preempt_disable();
8b3c3104
AH
3356 ret = kvm_set_shared_msr(msr->index, msr->data,
3357 msr->mask);
2225fd56 3358 preempt_enable();
8b3c3104
AH
3359 if (ret)
3360 msr->data = old_msr_data;
2225fd56 3361 }
3bab1f5d 3362 break;
6aa8b732 3363 }
8fe8ab46 3364 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK
3365 }
3366
2cc51560 3367 return ret;
6aa8b732
AK
3368}
3369
5fdbf976 3370static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 3371{
5fdbf976
MT
3372 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3373 switch (reg) {
3374 case VCPU_REGS_RSP:
3375 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3376 break;
3377 case VCPU_REGS_RIP:
3378 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3379 break;
6de4f3ad
AK
3380 case VCPU_EXREG_PDPTR:
3381 if (enable_ept)
3382 ept_save_pdptrs(vcpu);
3383 break;
5fdbf976
MT
3384 default:
3385 break;
3386 }
6aa8b732
AK
3387}
3388
6aa8b732
AK
3389static __init int cpu_has_kvm_support(void)
3390{
6210e37b 3391 return cpu_has_vmx();
6aa8b732
AK
3392}
3393
3394static __init int vmx_disabled_by_bios(void)
3395{
3396 u64 msr;
3397
3398 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 3399 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 3400 /* launched w/ TXT and VMX disabled */
cafd6659
SW
3401 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3402 && tboot_enabled())
3403 return 1;
23f3e991 3404 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 3405 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 3406 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW
3407 && !tboot_enabled()) {
3408 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 3409 "activate TXT before enabling KVM\n");
cafd6659 3410 return 1;
f9335afe 3411 }
23f3e991
JC
3412 /* launched w/o TXT and VMX disabled */
3413 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3414 && !tboot_enabled())
3415 return 1;
cafd6659
SW
3416 }
3417
3418 return 0;
6aa8b732
AK
3419}
3420
7725b894
DX
3421static void kvm_cpu_vmxon(u64 addr)
3422{
fe0e80be 3423 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS
3424 intel_pt_handle_vmx(1);
3425
7725b894
DX
3426 asm volatile (ASM_VMX_VMXON_RAX
3427 : : "a"(&addr), "m"(addr)
3428 : "memory", "cc");
3429}
3430
13a34e06 3431static int hardware_enable(void)
6aa8b732
AK
3432{
3433 int cpu = raw_smp_processor_id();
3434 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 3435 u64 old, test_bits;
6aa8b732 3436
1e02ce4c 3437 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG
3438 return -EBUSY;
3439
d462b819 3440 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW
3441 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3442 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY
3443
3444 /*
3445 * Now we can enable the vmclear operation in kdump
3446 * since the loaded_vmcss_on_cpu list on this cpu
3447 * has been initialized.
3448 *
3449 * Though the cpu is not in VMX operation now, there
3450 * is no problem to enable the vmclear operation
3451 * for the loaded_vmcss_on_cpu list is empty!
3452 */
3453 crash_enable_local_vmclear(cpu);
3454
6aa8b732 3455 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW
3456
3457 test_bits = FEATURE_CONTROL_LOCKED;
3458 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3459 if (tboot_enabled())
3460 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3461
3462 if ((old & test_bits) != test_bits) {
6aa8b732 3463 /* enable and lock */
cafd6659
SW
3464 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3465 }
fe0e80be
DH
3466 kvm_cpu_vmxon(phys_addr);
3467 ept_sync_global();
10474ae8
AG
3468
3469 return 0;
6aa8b732
AK
3470}
3471
d462b819 3472static void vmclear_local_loaded_vmcss(void)
543e4243
AK
3473{
3474 int cpu = raw_smp_processor_id();
d462b819 3475 struct loaded_vmcs *v, *n;
543e4243 3476
d462b819
NHE
3477 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3478 loaded_vmcss_on_cpu_link)
3479 __loaded_vmcs_clear(v);
543e4243
AK
3480}
3481
710ff4a8
EH
3482
3483/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3484 * tricks.
3485 */
3486static void kvm_cpu_vmxoff(void)
6aa8b732 3487{
4ecac3fd 3488 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1c5ac21a
AS
3489
3490 intel_pt_handle_vmx(0);
fe0e80be 3491 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK
3492}
3493
13a34e06 3494static void hardware_disable(void)
710ff4a8 3495{
fe0e80be
DH
3496 vmclear_local_loaded_vmcss();
3497 kvm_cpu_vmxoff();
710ff4a8
EH
3498}
3499
1c3d14fe 3500static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 3501 u32 msr, u32 *result)
1c3d14fe
YS
3502{
3503 u32 vmx_msr_low, vmx_msr_high;
3504 u32 ctl = ctl_min | ctl_opt;
3505
3506 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3507
3508 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3509 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3510
3511 /* Ensure minimum (required) set of control bits are supported. */
3512 if (ctl_min & ~ctl)
002c7f7c 3513 return -EIO;
1c3d14fe
YS
3514
3515 *result = ctl;
3516 return 0;
3517}
3518
110312c8
AK
3519static __init bool allow_1_setting(u32 msr, u32 ctl)
3520{
3521 u32 vmx_msr_low, vmx_msr_high;
3522
3523 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3524 return vmx_msr_high & ctl;
3525}
3526
002c7f7c 3527static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK
3528{
3529 u32 vmx_msr_low, vmx_msr_high;
d56f546d 3530 u32 min, opt, min2, opt2;
1c3d14fe
YS
3531 u32 _pin_based_exec_control = 0;
3532 u32 _cpu_based_exec_control = 0;
f78e0e2e 3533 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS
3534 u32 _vmexit_control = 0;
3535 u32 _vmentry_control = 0;
3536
10166744 3537 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS
3538#ifdef CONFIG_X86_64
3539 CPU_BASED_CR8_LOAD_EXITING |
3540 CPU_BASED_CR8_STORE_EXITING |
3541#endif
d56f546d
SY
3542 CPU_BASED_CR3_LOAD_EXITING |
3543 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS
3544 CPU_BASED_USE_IO_BITMAPS |
3545 CPU_BASED_MOV_DR_EXITING |
a7052897 3546 CPU_BASED_USE_TSC_OFFSETING |
fee84b07
AK
3547 CPU_BASED_INVLPG_EXITING |
3548 CPU_BASED_RDPMC_EXITING;
443381a8 3549
668fffa3
MT
3550 if (!kvm_mwait_in_guest())
3551 min |= CPU_BASED_MWAIT_EXITING |
3552 CPU_BASED_MONITOR_EXITING;
3553
f78e0e2e 3554 opt = CPU_BASED_TPR_SHADOW |
25c5f225 3555 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 3556 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS
3557 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3558 &_cpu_based_exec_control) < 0)
002c7f7c 3559 return -EIO;
6e5d865c
YS
3560#ifdef CONFIG_X86_64
3561 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3562 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3563 ~CPU_BASED_CR8_STORE_EXITING;
3564#endif
f78e0e2e 3565 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY
3566 min2 = 0;
3567 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3568 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3569 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3570 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3571 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3572 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3573 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3574 SECONDARY_EXEC_RDTSCP |
83d4c286 3575 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3576 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3577 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3578 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 3579 SECONDARY_EXEC_XSAVES |
8b3e34e4 3580 SECONDARY_EXEC_ENABLE_PML |
64903d61 3581 SECONDARY_EXEC_TSC_SCALING;
d56f546d
SY
3582 if (adjust_vmx_controls(min2, opt2,
3583 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY
3584 &_cpu_based_2nd_exec_control) < 0)
3585 return -EIO;
3586 }
3587#ifndef CONFIG_X86_64
3588 if (!(_cpu_based_2nd_exec_control &
3589 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3590 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3591#endif
83d4c286
YZ
3592
3593 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3594 _cpu_based_2nd_exec_control &= ~(
8d14695f 3595 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ
3596 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3597 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3598
d56f546d 3599 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT
3600 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3601 enabled */
5fff7d27
GN
3602 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3603 CPU_BASED_CR3_STORE_EXITING |
3604 CPU_BASED_INVLPG_EXITING);
d56f546d
SY
3605 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3606 vmx_capability.ept, vmx_capability.vpid);
3607 }
1c3d14fe 3608
91fa0f8e 3609 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS
3610#ifdef CONFIG_X86_64
3611 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3612#endif
a547c6db 3613 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
91fa0f8e 3614 VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS
3615 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3616 &_vmexit_control) < 0)
002c7f7c 3617 return -EIO;
1c3d14fe 3618
2c82878b
PB
3619 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3620 PIN_BASED_VIRTUAL_NMIS;
3621 opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ
3622 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3623 &_pin_based_exec_control) < 0)
3624 return -EIO;
3625
1c17c3e6
PB
3626 if (cpu_has_broken_vmx_preemption_timer())
3627 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 3628 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 3629 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ
3630 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3631
c845f9c6 3632 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3633 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS
3634 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3635 &_vmentry_control) < 0)
002c7f7c 3636 return -EIO;
6aa8b732 3637
c68876fd 3638 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS
3639
3640 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3641 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3642 return -EIO;
1c3d14fe
YS
3643
3644#ifdef CONFIG_X86_64
3645 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3646 if (vmx_msr_high & (1u<<16))
002c7f7c 3647 return -EIO;
1c3d14fe
YS
3648#endif
3649
3650 /* Require Write-Back (WB) memory type for VMCS accesses. */
3651 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3652 return -EIO;
1c3d14fe 3653
002c7f7c 3654 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 3655 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 3656 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
002c7f7c 3657 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3658
002c7f7c
YS
3659 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3660 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3661 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS
3662 vmcs_conf->vmexit_ctrl = _vmexit_control;
3663 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3664
110312c8
AK
3665 cpu_has_load_ia32_efer =
3666 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3667 VM_ENTRY_LOAD_IA32_EFER)
3668 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3669 VM_EXIT_LOAD_IA32_EFER);
3670
8bf00a52
GN
3671 cpu_has_load_perf_global_ctrl =
3672 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3673 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3674 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3675 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3676
3677 /*
3678 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
bb3541f1 3679 * but due to errata below it can't be used. Workaround is to use
8bf00a52
GN
3680 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3681 *
3682 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3683 *
3684 * AAK155 (model 26)
3685 * AAP115 (model 30)
3686 * AAT100 (model 37)
3687 * BC86,AAY89,BD102 (model 44)
3688 * BA97 (model 46)
3689 *
3690 */
3691 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3692 switch (boot_cpu_data.x86_model) {
3693 case 26:
3694 case 30:
3695 case 37:
3696 case 44:
3697 case 46:
3698 cpu_has_load_perf_global_ctrl = false;
3699 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3700 "does not work properly. Using workaround\n");
3701 break;
3702 default:
3703 break;
3704 }
3705 }
3706
782511b0 3707 if (boot_cpu_has(X86_FEATURE_XSAVES))
20300099
WL
3708 rdmsrl(MSR_IA32_XSS, host_xss);
3709
1c3d14fe 3710 return 0;
c68876fd 3711}
6aa8b732
AK
3712
3713static struct vmcs *alloc_vmcs_cpu(int cpu)
3714{
3715 int node = cpu_to_node(cpu);
3716 struct page *pages;
3717 struct vmcs *vmcs;
3718
96db800f 3719 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK
3720 if (!pages)
3721 return NULL;
3722 vmcs = page_address(pages);
1c3d14fe
YS
3723 memset(vmcs, 0, vmcs_config.size);
3724 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK
3725 return vmcs;
3726}
3727
3728static struct vmcs *alloc_vmcs(void)
3729{
d3b2c338 3730 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK
3731}
3732
3733static void free_vmcs(struct vmcs *vmcs)
3734{
1c3d14fe 3735 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK
3736}
3737
d462b819
NHE
3738/*
3739 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3740 */
3741static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3742{
3743 if (!loaded_vmcs->vmcs)
3744 return;
3745 loaded_vmcs_clear(loaded_vmcs);
3746 free_vmcs(loaded_vmcs->vmcs);
3747 loaded_vmcs->vmcs = NULL;
355f4fb1 3748 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE
3749}
3750
39959588 3751static void free_kvm_area(void)
6aa8b732
AK
3752{
3753 int cpu;
3754
3230bb47 3755 for_each_possible_cpu(cpu) {
6aa8b732 3756 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA
3757 per_cpu(vmxarea, cpu) = NULL;
3758 }
6aa8b732
AK
3759}
3760
fe2b201b
BD
3761static void init_vmcs_shadow_fields(void)
3762{
3763 int i, j;
3764
3765 /* No checks for read only fields yet */
3766
3767 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3768 switch (shadow_read_write_fields[i]) {
3769 case GUEST_BNDCFGS:
a87036ad 3770 if (!kvm_mpx_supported())
fe2b201b
BD
3771 continue;
3772 break;
3773 default:
3774 break;
3775 }
3776
3777 if (j < i)
3778 shadow_read_write_fields[j] =
3779 shadow_read_write_fields[i];
3780 j++;
3781 }
3782 max_shadow_read_write_fields = j;
3783
3784 /* shadowed fields guest access without vmexit */
3785 for (i = 0; i < max_shadow_read_write_fields; i++) {
3786 clear_bit(shadow_read_write_fields[i],
3787 vmx_vmwrite_bitmap);
3788 clear_bit(shadow_read_write_fields[i],
3789 vmx_vmread_bitmap);
3790 }
3791 for (i = 0; i < max_shadow_read_only_fields; i++)
3792 clear_bit(shadow_read_only_fields[i],
3793 vmx_vmread_bitmap);
3794}
3795
6aa8b732
AK
3796static __init int alloc_kvm_area(void)
3797{
3798 int cpu;
3799
3230bb47 3800 for_each_possible_cpu(cpu) {
6aa8b732
AK
3801 struct vmcs *vmcs;
3802
3803 vmcs = alloc_vmcs_cpu(cpu);
3804 if (!vmcs) {
3805 free_kvm_area();
3806 return -ENOMEM;
3807 }
3808
3809 per_cpu(vmxarea, cpu) = vmcs;
3810 }
3811 return 0;
3812}
3813
14168786
GN
3814static bool emulation_required(struct kvm_vcpu *vcpu)
3815{
3816 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3817}
3818
91b0aa2c 3819static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3820 struct kvm_segment *save)
6aa8b732 3821{
d99e4152
GN
3822 if (!emulate_invalid_guest_state) {
3823 /*
3824 * CS and SS RPL should be equal during guest entry according
3825 * to VMX spec, but in reality it is not always so. Since vcpu
3826 * is in the middle of the transition from real mode to
3827 * protected mode it is safe to assume that RPL 0 is a good
3828 * default value.
3829 */
3830 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA
3831 save->selector &= ~SEGMENT_RPL_MASK;
3832 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3833 save->s = 1;
6aa8b732 3834 }
d99e4152 3835 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK
3836}
3837
3838static void enter_pmode(struct kvm_vcpu *vcpu)
3839{
3840 unsigned long flags;
a89a8fb9 3841 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3842
d99e4152
GN
3843 /*
3844 * Update real mode segment cache. It may be not up-to-date if sement
3845 * register was written while vcpu was in a guest mode.
3846 */
3847 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3848 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3849 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3850 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3851 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3852 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3853
7ffd92c5 3854 vmx->rmode.vm86_active = 0;
6aa8b732 3855
2fb92db1
AK
3856 vmx_segment_cache_clear(vmx);
3857
f5f7b2fe 3858 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK
3859
3860 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK
3861 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3862 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK
3863 vmcs_writel(GUEST_RFLAGS, flags);
3864
66aee91a
RR
3865 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3866 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK
3867
3868 update_exception_bitmap(vcpu);
3869
91b0aa2c
GN
3870 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3871 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3872 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3873 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3874 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3875 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK
3876}
3877
f5f7b2fe 3878static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3879{
772e0318 3880 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN
3881 struct kvm_segment var = *save;
3882
3883 var.dpl = 0x3;
3884 if (seg == VCPU_SREG_CS)
3885 var.type = 0x3;
3886
3887 if (!emulate_invalid_guest_state) {
3888 var.selector = var.base >> 4;
3889 var.base = var.base & 0xffff0;
3890 var.limit = 0xffff;
3891 var.g = 0;
3892 var.db = 0;
3893 var.present = 1;
3894 var.s = 1;
3895 var.l = 0;
3896 var.unusable = 0;
3897 var.type = 0x3;
3898 var.avl = 0;
3899 if (save->base & 0xf)
3900 printk_once(KERN_WARNING "kvm: segment base is not "
3901 "paragraph aligned when entering "
3902 "protected mode (seg=%d)", seg);
3903 }
6aa8b732 3904
d99e4152 3905 vmcs_write16(sf->selector, var.selector);
96794e4e 3906 vmcs_writel(sf->base, var.base);
d99e4152
GN
3907 vmcs_write32(sf->limit, var.limit);
3908 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK
3909}
3910
3911static void enter_rmode(struct kvm_vcpu *vcpu)
3912{
3913 unsigned long flags;
a89a8fb9 3914 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3915
f5f7b2fe
AK
3916 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3917 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3918 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3919 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3920 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN
3921 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3922 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3923
7ffd92c5 3924 vmx->rmode.vm86_active = 1;
6aa8b732 3925
776e58ea
GN
3926 /*
3927 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3928 * vcpu. Warn the user that an update is overdue.
776e58ea 3929 */
4918c6ca 3930 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN
3931 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3932 "called before entering vcpu\n");
776e58ea 3933
2fb92db1
AK
3934 vmx_segment_cache_clear(vmx);
3935
4918c6ca 3936 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3937 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK
3938 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3939
3940 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3941 vmx->rmode.save_rflags = flags;
6aa8b732 3942
053de044 3943 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK
3944
3945 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3946 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK
3947 update_exception_bitmap(vcpu);
3948
d99e4152
GN
3949 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3950 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3951 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3952 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3953 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3954 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3955
8668a3c4 3956 kvm_mmu_reset_context(vcpu);
6aa8b732
AK
3957}
3958
401d10de
AS
3959static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3960{
3961 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK
3962 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3963
3964 if (!msr)
3965 return;
401d10de 3966
44ea2b17
AK
3967 /*
3968 * Force kernel_gs_base reloading before EFER changes, as control
3969 * of this msr depends on is_long_mode().
3970 */
3971 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3972 vcpu->arch.efer = efer;
401d10de 3973 if (efer & EFER_LMA) {
2961e876 3974 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS
3975 msr->data = efer;
3976 } else {
2961e876 3977 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS
3978
3979 msr->data = efer & ~EFER_LME;
3980 }
3981 setup_msrs(vmx);
3982}
3983
05b3e0c2 3984#ifdef CONFIG_X86_64
6aa8b732
AK
3985
3986static void enter_lmode(struct kvm_vcpu *vcpu)
3987{
3988 u32 guest_tr_ar;
3989
2fb92db1
AK
3990 vmx_segment_cache_clear(to_vmx(vcpu));
3991
6aa8b732 3992 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 3993 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK
3994 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3995 __func__);
6aa8b732 3996 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL
3997 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3998 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 3999 }
da38f438 4000 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK
4001}
4002
4003static void exit_lmode(struct kvm_vcpu *vcpu)
4004{
2961e876 4005 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 4006 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK
4007}
4008
4009#endif
4010
dd5f5341 4011static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
2384d2b3 4012{
dd180b3e
XG
4013 if (enable_ept) {
4014 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4015 return;
4e1096d2 4016 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
f0b98c02
JM
4017 } else {
4018 vpid_sync_context(vpid);
dd180b3e 4019 }
2384d2b3
SY
4020}
4021
dd5f5341
WL
4022static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4023{
4024 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4025}
4026
fb6c8198
JM
4027static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4028{
4029 if (enable_ept)
4030 vmx_flush_tlb(vcpu);
4031}
4032
e8467fda
AK
4033static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4034{
4035 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4036
4037 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4038 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4039}
4040
aff48baa
AK
4041static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4042{
4043 if (enable_ept && is_paging(vcpu))
4044 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4045 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4046}
4047
25c4c276 4048static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 4049{
fc78f519
AK
4050 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4051
4052 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4053 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK
4054}
4055
1439442c
SY
4056static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4057{
d0d538b9
GN
4058 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4059
6de4f3ad
AK
4060 if (!test_bit(VCPU_EXREG_PDPTR,
4061 (unsigned long *)&vcpu->arch.regs_dirty))
4062 return;
4063
1439442c 4064 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN
4065 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4066 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4067 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4068 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY
4069 }
4070}
4071
8f5d549f
AK
4072static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4073{
d0d538b9
GN
4074 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4075
8f5d549f 4076 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN
4077 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4078 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4079 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4080 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 4081 }
6de4f3ad
AK
4082
4083 __set_bit(VCPU_EXREG_PDPTR,
4084 (unsigned long *)&vcpu->arch.regs_avail);
4085 __set_bit(VCPU_EXREG_PDPTR,
4086 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK
4087}
4088
3899152c
DM
4089static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4090{
4091 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4092 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4093 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4094
4095 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4096 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4097 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4098 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4099
4100 return fixed_bits_valid(val, fixed0, fixed1);
4101}
4102
4103static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4104{
4105 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4106 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4107
4108 return fixed_bits_valid(val, fixed0, fixed1);
4109}
4110
4111static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4112{
4113 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4114 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4115
4116 return fixed_bits_valid(val, fixed0, fixed1);
4117}
4118
4119/* No difference in the restrictions on guest and host CR4 in VMX operation. */
4120#define nested_guest_cr4_valid nested_cr4_valid
4121#define nested_host_cr4_valid nested_cr4_valid
4122
5e1746d6 4123static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY
4124
4125static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4126 unsigned long cr0,
4127 struct kvm_vcpu *vcpu)
4128{
5233dd51
MT
4129 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4130 vmx_decache_cr3(vcpu);
1439442c
SY
4131 if (!(cr0 & X86_CR0_PG)) {
4132 /* From paging/starting to nonpaging */
4133 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 4134 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY
4135 (CPU_BASED_CR3_LOAD_EXITING |
4136 CPU_BASED_CR3_STORE_EXITING));
4137 vcpu->arch.cr0 = cr0;
fc78f519 4138 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY
4139 } else if (!is_paging(vcpu)) {
4140 /* From nonpaging to paging */
4141 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 4142 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY
4143 ~(CPU_BASED_CR3_LOAD_EXITING |
4144 CPU_BASED_CR3_STORE_EXITING));
4145 vcpu->arch.cr0 = cr0;
fc78f519 4146 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 4147 }
95eb84a7
SY
4148
4149 if (!(cr0 & X86_CR0_WP))
4150 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY
4151}
4152
6aa8b732
AK
4153static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4154{
7ffd92c5 4155 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK
4156 unsigned long hw_cr0;
4157
5037878e 4158 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 4159 if (enable_unrestricted_guest)
5037878e 4160 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 4161 else {
5037878e 4162 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 4163
218e763f
GN
4164 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4165 enter_pmode(vcpu);
6aa8b732 4166
218e763f
GN
4167 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4168 enter_rmode(vcpu);
4169 }
6aa8b732 4170
05b3e0c2 4171#ifdef CONFIG_X86_64
f6801dff 4172 if (vcpu->arch.efer & EFER_LME) {
707d92fa 4173 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 4174 enter_lmode(vcpu);
707d92fa 4175 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK
4176 exit_lmode(vcpu);
4177 }
4178#endif
4179
089d034e 4180 if (enable_ept)
1439442c
SY
4181 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4182
6aa8b732 4183 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 4184 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 4185 vcpu->arch.cr0 = cr0;
14168786
GN
4186
4187 /* depends on vcpu->arch.cr0 to be set to a new value */
4188 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK
4189}
4190
1439442c
SY
4191static u64 construct_eptp(unsigned long root_hpa)
4192{
4193 u64 eptp;
4194
4195 /* TODO write the value reading from MSR */
4196 eptp = VMX_EPT_DEFAULT_MT |
4197 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH
4198 if (enable_ept_ad_bits)
4199 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY
4200 eptp |= (root_hpa & PAGE_MASK);
4201
4202 return eptp;
4203}
4204
6aa8b732
AK
4205static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4206{
1439442c
SY
4207 unsigned long guest_cr3;
4208 u64 eptp;
4209
4210 guest_cr3 = cr3;
089d034e 4211 if (enable_ept) {
1439442c
SY
4212 eptp = construct_eptp(cr3);
4213 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK
4214 if (is_paging(vcpu) || is_guest_mode(vcpu))
4215 guest_cr3 = kvm_read_cr3(vcpu);
4216 else
4217 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 4218 ept_load_pdptrs(vcpu);
1439442c
SY
4219 }
4220
2384d2b3 4221 vmx_flush_tlb(vcpu);
1439442c 4222 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK
4223}
4224
5e1746d6 4225static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 4226{
085e68ee
BS
4227 /*
4228 * Pass through host's Machine Check Enable value to hw_cr4, which
4229 * is in force while we are in guest mode. Do not let guests control
4230 * this bit, even if host CR4.MCE == 0.
4231 */
4232 unsigned long hw_cr4 =
4233 (cr4_read_shadow() & X86_CR4_MCE) |
4234 (cr4 & ~X86_CR4_MCE) |
4235 (to_vmx(vcpu)->rmode.vm86_active ?
4236 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 4237
5e1746d6
NHE
4238 if (cr4 & X86_CR4_VMXE) {
4239 /*
4240 * To use VMXON (and later other VMX instructions), a guest
4241 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4242 * So basically the check on whether to allow nested VMX
4243 * is here.
4244 */
4245 if (!nested_vmx_allowed(vcpu))
4246 return 1;
1a0d74e6 4247 }
3899152c
DM
4248
4249 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE
4250 return 1;
4251
ad312c7c 4252 vcpu->arch.cr4 = cr4;
bc23008b
AK
4253 if (enable_ept) {
4254 if (!is_paging(vcpu)) {
4255 hw_cr4 &= ~X86_CR4_PAE;
4256 hw_cr4 |= X86_CR4_PSE;
4257 } else if (!(cr4 & X86_CR4_PAE)) {
4258 hw_cr4 &= ~X86_CR4_PAE;
4259 }
4260 }
1439442c 4261
656ec4a4
RK
4262 if (!enable_unrestricted_guest && !is_paging(vcpu))
4263 /*
ddba2628
HH
4264 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4265 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4266 * to be manually disabled when guest switches to non-paging
4267 * mode.
4268 *
4269 * If !enable_unrestricted_guest, the CPU is always running
4270 * with CR0.PG=1 and CR4 needs to be modified.
4271 * If enable_unrestricted_guest, the CPU automatically
4272 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 4273 */
ddba2628 4274 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
656ec4a4 4275
1439442c
SY
4276 vmcs_writel(CR4_READ_SHADOW, cr4);
4277 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 4278 return 0;
6aa8b732
AK
4279}
4280
6aa8b732
AK
4281static void vmx_get_segment(struct kvm_vcpu *vcpu,
4282 struct kvm_segment *var, int seg)
4283{
a9179499 4284 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK
4285 u32 ar;
4286
c6ad1153 4287 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 4288 *var = vmx->rmode.segs[seg];
a9179499 4289 if (seg == VCPU_SREG_TR
2fb92db1 4290 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 4291 return;
1390a28b
AK
4292 var->base = vmx_read_guest_seg_base(vmx, seg);
4293 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4294 return;
a9179499 4295 }
2fb92db1
AK
4296 var->base = vmx_read_guest_seg_base(vmx, seg);
4297 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4298 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4299 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 4300 var->unusable = (ar >> 16) & 1;
6aa8b732
AK
4301 var->type = ar & 15;
4302 var->s = (ar >> 4) & 1;
4303 var->dpl = (ar >> 5) & 3;
03617c18
GN
4304 /*
4305 * Some userspaces do not preserve unusable property. Since usable
4306 * segment has to be present according to VMX spec we can use present
4307 * property to amend userspace bug by making unusable segment always
4308 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4309 * segment as unusable.
4310 */
4311 var->present = !var->unusable;
6aa8b732
AK
4312 var->avl = (ar >> 12) & 1;
4313 var->l = (ar >> 13) & 1;
4314 var->db = (ar >> 14) & 1;
4315 var->g = (ar >> 15) & 1;
6aa8b732
AK
4316}
4317
a9179499
AK
4318static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4319{
a9179499
AK
4320 struct kvm_segment s;
4321
4322 if (to_vmx(vcpu)->rmode.vm86_active) {
4323 vmx_get_segment(vcpu, &s, seg);
4324 return s.base;
4325 }
2fb92db1 4326 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK
4327}
4328
b09408d0 4329static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 4330{
b09408d0
MT
4331 struct vcpu_vmx *vmx = to_vmx(vcpu);
4332
ae9fedc7 4333 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 4334 return 0;
ae9fedc7
PB
4335 else {
4336 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 4337 return VMX_AR_DPL(ar);
69c73028 4338 }
69c73028
AK
4339}
4340
653e3108 4341static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 4342{
6aa8b732
AK
4343 u32 ar;
4344
f0495f9b 4345 if (var->unusable || !var->present)
6aa8b732
AK
4346 ar = 1 << 16;
4347 else {
4348 ar = var->type & 15;
4349 ar |= (var->s & 1) << 4;
4350 ar |= (var->dpl & 3) << 5;
4351 ar |= (var->present & 1) << 7;
4352 ar |= (var->avl & 1) << 12;
4353 ar |= (var->l & 1) << 13;
4354 ar |= (var->db & 1) << 14;
4355 ar |= (var->g & 1) << 15;
4356 }
653e3108
AK
4357
4358 return ar;
4359}
4360
4361static void vmx_set_segment(struct kvm_vcpu *vcpu,
4362 struct kvm_segment *var, int seg)
4363{
7ffd92c5 4364 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 4365 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 4366
2fb92db1
AK
4367 vmx_segment_cache_clear(vmx);
4368
1ecd50a9
GN
4369 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4370 vmx->rmode.segs[seg] = *var;
4371 if (seg == VCPU_SREG_TR)
4372 vmcs_write16(sf->selector, var->selector);
4373 else if (var->s)
4374 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 4375 goto out;
653e3108 4376 }
1ecd50a9 4377
653e3108
AK
4378 vmcs_writel(sf->base, var->base);
4379 vmcs_write32(sf->limit, var->limit);
4380 vmcs_write16(sf->selector, var->selector);
3a624e29
NK
4381
4382 /*
4383 * Fix the "Accessed" bit in AR field of segment registers for older
4384 * qemu binaries.
4385 * IA32 arch specifies that at the time of processor reset the
4386 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 4387 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK
4388 * state vmexit when "unrestricted guest" mode is turned on.
4389 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4390 * tree. Newer qemu binaries with that qemu fix would not need this
4391 * kvm hack.
4392 */
4393 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 4394 var->type |= 0x1; /* Accessed */
3a624e29 4395
f924d66d 4396 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN
4397
4398out:
98eb2f8b 4399 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK
4400}
4401
6aa8b732
AK
4402static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4403{
2fb92db1 4404 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK
4405
4406 *db = (ar >> 14) & 1;
4407 *l = (ar >> 13) & 1;
4408}
4409
89a27f4d 4410static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4411{
89a27f4d
GN
4412 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4413 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK
4414}
4415
89a27f4d 4416static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4417{
89a27f4d
GN
4418 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4419 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK
4420}
4421
89a27f4d 4422static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4423{
89a27f4d
GN
4424 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4425 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK
4426}
4427
89a27f4d 4428static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4429{
89a27f4d
GN
4430 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4431 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK
4432}
4433
648dfaa7
MG
4434static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4435{
4436 struct kvm_segment var;
4437 u32 ar;
4438
4439 vmx_get_segment(vcpu, &var, seg);
07f42f5f 4440 var.dpl = 0x3;
0647f4aa
GN
4441 if (seg == VCPU_SREG_CS)
4442 var.type = 0x3;
648dfaa7
MG
4443 ar = vmx_segment_access_rights(&var);
4444
4445 if (var.base != (var.selector << 4))
4446 return false;
89efbed0 4447 if (var.limit != 0xffff)
648dfaa7 4448 return false;
07f42f5f 4449 if (ar != 0xf3)
648dfaa7
MG
4450 return false;
4451
4452 return true;
4453}
4454
4455static bool code_segment_valid(struct kvm_vcpu *vcpu)
4456{
4457 struct kvm_segment cs;
4458 unsigned int cs_rpl;
4459
4460 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 4461 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 4462
1872a3f4
AK
4463 if (cs.unusable)
4464 return false;
4d283ec9 4465 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG
4466 return false;
4467 if (!cs.s)
4468 return false;
4d283ec9 4469 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG
4470 if (cs.dpl > cs_rpl)
4471 return false;
1872a3f4 4472 } else {
648dfaa7
MG
4473 if (cs.dpl != cs_rpl)
4474 return false;
4475 }
4476 if (!cs.present)
4477 return false;
4478
4479 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4480 return true;
4481}
4482
4483static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4484{
4485 struct kvm_segment ss;
4486 unsigned int ss_rpl;
4487
4488 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 4489 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 4490
1872a3f4
AK
4491 if (ss.unusable)
4492 return true;
4493 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG
4494 return false;
4495 if (!ss.s)
4496 return false;
4497 if (ss.dpl != ss_rpl) /* DPL != RPL */
4498 return false;
4499 if (!ss.present)
4500 return false;
4501
4502 return true;
4503}
4504
4505static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4506{
4507 struct kvm_segment var;
4508 unsigned int rpl;
4509
4510 vmx_get_segment(vcpu, &var, seg);
b32a9918 4511 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 4512
1872a3f4
AK
4513 if (var.unusable)
4514 return true;
648dfaa7
MG
4515 if (!var.s)
4516 return false;
4517 if (!var.present)
4518 return false;
4d283ec9 4519 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG
4520 if (var.dpl < rpl) /* DPL < RPL */
4521 return false;
4522 }
4523
4524 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4525 * rights flags
4526 */
4527 return true;
4528}
4529
4530static bool tr_valid(struct kvm_vcpu *vcpu)
4531{
4532 struct kvm_segment tr;
4533
4534 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4535
1872a3f4
AK
4536 if (tr.unusable)
4537 return false;
b32a9918 4538 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 4539 return false;
1872a3f4 4540 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG
4541 return false;
4542 if (!tr.present)
4543 return false;
4544
4545 return true;
4546}
4547
4548static bool ldtr_valid(struct kvm_vcpu *vcpu)
4549{
4550 struct kvm_segment ldtr;
4551
4552 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4553
1872a3f4
AK
4554 if (ldtr.unusable)
4555 return true;
b32a9918 4556 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG
4557 return false;
4558 if (ldtr.type != 2)
4559 return false;
4560 if (!ldtr.present)
4561 return false;
4562
4563 return true;
4564}
4565
4566static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4567{
4568 struct kvm_segment cs, ss;
4569
4570 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4571 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4572
b32a9918
NA
4573 return ((cs.selector & SEGMENT_RPL_MASK) ==
4574 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG
4575}
4576
4577/*
4578 * Check if guest state is valid. Returns true if valid, false if
4579 * not.
4580 * We assume that registers are always usable
4581 */
4582static bool guest_state_valid(struct kvm_vcpu *vcpu)
4583{
c5e97c80
GN
4584 if (enable_unrestricted_guest)
4585 return true;
4586
648dfaa7 4587 /* real mode guest state checks */
f13882d8 4588 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG
4589 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4590 return false;
4591 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4592 return false;
4593 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4594 return false;
4595 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4596 return false;
4597 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4598 return false;
4599 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4600 return false;
4601 } else {
4602 /* protected mode guest state checks */
4603 if (!cs_ss_rpl_check(vcpu))
4604 return false;
4605 if (!code_segment_valid(vcpu))
4606 return false;
4607 if (!stack_segment_valid(vcpu))
4608 return false;
4609 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4610 return false;
4611 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4612 return false;
4613 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4614 return false;
4615 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4616 return false;
4617 if (!tr_valid(vcpu))
4618 return false;
4619 if (!ldtr_valid(vcpu))
4620 return false;
4621 }
4622 /* TODO:
4623 * - Add checks on RIP
4624 * - Add checks on RFLAGS
4625 */
4626
4627 return true;
4628}
4629
d77c26fc 4630static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4631{
40dcaa9f 4632 gfn_t fn;
195aefde 4633 u16 data = 0;
1f755a82 4634 int idx, r;
6aa8b732 4635
40dcaa9f 4636 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4637 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE
4638 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4639 if (r < 0)
10589a46 4640 goto out;
195aefde 4641 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY
4642 r = kvm_write_guest_page(kvm, fn++, &data,
4643 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4644 if (r < 0)
10589a46 4645 goto out;
195aefde
IE
4646 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4647 if (r < 0)
10589a46 4648 goto out;
195aefde
IE
4649 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4650 if (r < 0)
10589a46 4651 goto out;
195aefde 4652 data = ~0;
10589a46
MT
4653 r = kvm_write_guest_page(kvm, fn, &data,
4654 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4655 sizeof(u8));
10589a46 4656out:
40dcaa9f 4657 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4658 return r;
6aa8b732
AK
4659}
4660
b7ebfb05
SY
4661static int init_rmode_identity_map(struct kvm *kvm)
4662{
f51770ed 4663 int i, idx, r = 0;
ba049e93 4664 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY
4665 u32 tmp;
4666
089d034e 4667 if (!enable_ept)
f51770ed 4668 return 0;
a255d479
TC
4669
4670 /* Protect kvm->arch.ept_identity_pagetable_done. */
4671 mutex_lock(&kvm->slots_lock);
4672
f51770ed 4673 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4674 goto out2;
a255d479 4675
b927a3ce 4676 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC
4677
4678 r = alloc_identity_pagetable(kvm);
f51770ed 4679 if (r < 0)
a255d479
TC
4680 goto out2;
4681
40dcaa9f 4682 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY
4683 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4684 if (r < 0)
4685 goto out;
4686 /* Set up identity-mapping pagetable for EPT in real mode */
4687 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4688 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4689 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4690 r = kvm_write_guest_page(kvm, identity_map_pfn,
4691 &tmp, i * sizeof(tmp), sizeof(tmp));
4692 if (r < 0)
4693 goto out;
4694 }
4695 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4696
b7ebfb05 4697out:
40dcaa9f 4698 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC
4699
4700out2:
4701 mutex_unlock(&kvm->slots_lock);
f51770ed 4702 return r;
b7ebfb05
SY
4703}
4704
6aa8b732
AK
4705static void seg_setup(int seg)
4706{
772e0318 4707 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4708 unsigned int ar;
6aa8b732
AK
4709
4710 vmcs_write16(sf->selector, 0);
4711 vmcs_writel(sf->base, 0);
4712 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN
4713 ar = 0x93;
4714 if (seg == VCPU_SREG_CS)
4715 ar |= 0x08; /* code segment */
3a624e29
NK
4716
4717 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK
4718}
4719
f78e0e2e
SY
4720static int alloc_apic_access_page(struct kvm *kvm)
4721{
4484141a 4722 struct page *page;
f78e0e2e
SY
4723 int r = 0;
4724
79fac95e 4725 mutex_lock(&kvm->slots_lock);
c24ae0dc 4726 if (kvm->arch.apic_access_page_done)
f78e0e2e 4727 goto out;
1d8007bd
PB
4728 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4729 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY
4730 if (r)
4731 goto out;
72dc67a6 4732
73a6d941 4733 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG
4734 if (is_error_page(page)) {
4735 r = -EFAULT;
4736 goto out;
4737 }
4738
c24ae0dc
TC
4739 /*
4740 * Do not pin the page in memory, so that memory hot-unplug
4741 * is able to migrate it.
4742 */
4743 put_page(page);
4744 kvm->arch.apic_access_page_done = true;
f78e0e2e 4745out:
79fac95e 4746 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY
4747 return r;
4748}
4749
b7ebfb05
SY
4750static int alloc_identity_pagetable(struct kvm *kvm)
4751{
a255d479
TC
4752 /* Called with kvm->slots_lock held. */
4753
b7ebfb05
SY
4754 int r = 0;
4755
a255d479
TC
4756 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4757
1d8007bd
PB
4758 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4759 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
b7ebfb05 4760
b7ebfb05
SY
4761 return r;
4762}
4763
991e7a0e 4764static int allocate_vpid(void)
2384d2b3
SY
4765{
4766 int vpid;
4767
919818ab 4768 if (!enable_vpid)
991e7a0e 4769 return 0;
2384d2b3
SY
4770 spin_lock(&vmx_vpid_lock);
4771 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 4772 if (vpid < VMX_NR_VPIDS)
2384d2b3 4773 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL
4774 else
4775 vpid = 0;
2384d2b3 4776 spin_unlock(&vmx_vpid_lock);
991e7a0e 4777 return vpid;
2384d2b3
SY
4778}
4779
991e7a0e 4780static void free_vpid(int vpid)
cdbecfc3 4781{
991e7a0e 4782 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ
4783 return;
4784 spin_lock(&vmx_vpid_lock);
991e7a0e 4785 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ
4786 spin_unlock(&vmx_vpid_lock);
4787}
4788
8d14695f
YZ
4789#define MSR_TYPE_R 1
4790#define MSR_TYPE_W 2
4791static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4792 u32 msr, int type)
25c5f225 4793{
3e7c73e9 4794 int f = sizeof(unsigned long);
25c5f225
SY
4795
4796 if (!cpu_has_vmx_msr_bitmap())
4797 return;
4798
4799 /*
4800 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4801 * have the write-low and read-high bitmap offsets the wrong way round.
4802 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4803 */
25c5f225 4804 if (msr <= 0x1fff) {
8d14695f
YZ
4805 if (type & MSR_TYPE_R)
4806 /* read-low */
4807 __clear_bit(msr, msr_bitmap + 0x000 / f);
4808
4809 if (type & MSR_TYPE_W)
4810 /* write-low */
4811 __clear_bit(msr, msr_bitmap + 0x800 / f);
4812
25c5f225
SY
4813 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4814 msr &= 0x1fff;
8d14695f
YZ
4815 if (type & MSR_TYPE_R)
4816 /* read-high */
4817 __clear_bit(msr, msr_bitmap + 0x400 / f);
4818
4819 if (type & MSR_TYPE_W)
4820 /* write-high */
4821 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4822
4823 }
4824}
4825
f2b93280
WV
4826/*
4827 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4828 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4829 */
4830static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4831 unsigned long *msr_bitmap_nested,
4832 u32 msr, int type)
4833{
4834 int f = sizeof(unsigned long);
4835
4836 if (!cpu_has_vmx_msr_bitmap()) {
4837 WARN_ON(1);
4838 return;
4839 }
4840
4841 /*
4842 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4843 * have the write-low and read-high bitmap offsets the wrong way round.
4844 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4845 */
4846 if (msr <= 0x1fff) {
4847 if (type & MSR_TYPE_R &&
4848 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4849 /* read-low */
4850 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4851
4852 if (type & MSR_TYPE_W &&
4853 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4854 /* write-low */
4855 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4856
4857 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4858 msr &= 0x1fff;
4859 if (type & MSR_TYPE_R &&
4860 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4861 /* read-high */
4862 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4863
4864 if (type & MSR_TYPE_W &&
4865 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4866 /* write-high */
4867 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4868
4869 }
4870}
4871
5897297b
AK
4872static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4873{
4874 if (!longmode_only)
8d14695f
YZ
4875 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4876 msr, MSR_TYPE_R | MSR_TYPE_W);
4877 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4878 msr, MSR_TYPE_R | MSR_TYPE_W);
4879}
4880
2e69f865 4881static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
8d14695f 4882{
f6e90f9e 4883 if (apicv_active) {
c63e4563 4884 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
2e69f865 4885 msr, type);
c63e4563 4886 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
2e69f865 4887 msr, type);
f6e90f9e 4888 } else {
f6e90f9e 4889 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
2e69f865 4890 msr, type);
f6e90f9e 4891 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
2e69f865 4892 msr, type);
f6e90f9e 4893 }
5897297b
AK
4894}
4895
d62caabb 4896static bool vmx_get_enable_apicv(void)
d50ab6c1 4897{
d62caabb 4898 return enable_apicv;
d50ab6c1
PB
4899}
4900
6342c50a 4901static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
705699a1
WV
4902{
4903 struct vcpu_vmx *vmx = to_vmx(vcpu);
4904 int max_irr;
4905 void *vapic_page;
4906 u16 status;
4907
4908 if (vmx->nested.pi_desc &&
4909 vmx->nested.pi_pending) {
4910 vmx->nested.pi_pending = false;
4911 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
6342c50a 4912 return;
705699a1
WV
4913
4914 max_irr = find_last_bit(
4915 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4916
4917 if (max_irr == 256)
6342c50a 4918 return;
705699a1
WV
4919
4920 vapic_page = kmap(vmx->nested.virtual_apic_page);
705699a1
WV
4921 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4922 kunmap(vmx->nested.virtual_apic_page);
4923
4924 status = vmcs_read16(GUEST_INTR_STATUS);
4925 if ((u8)max_irr > ((u8)status & 0xff)) {
4926 status &= ~0xff;
4927 status |= (u8)max_irr;
4928 vmcs_write16(GUEST_INTR_STATUS, status);
4929 }
4930 }
705699a1
WV
4931}
4932
21bc8dc5
RK
4933static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4934{
4935#ifdef CONFIG_SMP
4936 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6
FW
4937 struct vcpu_vmx *vmx = to_vmx(vcpu);
4938
4939 /*
4940 * Currently, we don't support urgent interrupt,
4941 * all interrupts are recognized as non-urgent
4942 * interrupt, so we cannot post interrupts when
4943 * 'SN' is set.
4944 *
4945 * If the vcpu is in guest mode, it means it is
4946 * running instead of being scheduled out and
4947 * waiting in the run queue, and that's the only
4948 * case when 'SN' is set currently, warning if
4949 * 'SN' is set.
4950 */
4951 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4952
21bc8dc5
RK
4953 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4954 POSTED_INTR_VECTOR);
4955 return true;
4956 }
4957#endif
4958 return false;
4959}
4960
705699a1
WV
4961static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4962 int vector)
4963{
4964 struct vcpu_vmx *vmx = to_vmx(vcpu);
4965
4966 if (is_guest_mode(vcpu) &&
4967 vector == vmx->nested.posted_intr_nv) {
4968 /* the PIR and ON have been set by L1. */
21bc8dc5 4969 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV
4970 /*
4971 * If a posted intr is not recognized by hardware,
4972 * we will accomplish it in the next vmentry.
4973 */
4974 vmx->nested.pi_pending = true;
4975 kvm_make_request(KVM_REQ_EVENT, vcpu);
4976 return 0;
4977 }
4978 return -1;
4979}
a20ed54d
YZ
4980/*
4981 * Send interrupt to vcpu via posted interrupt way.
4982 * 1. If target vcpu is running(non-root mode), send posted interrupt
4983 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4984 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4985 * interrupt from PIR in next vmentry.
4986 */
4987static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4988{
4989 struct vcpu_vmx *vmx = to_vmx(vcpu);
4990 int r;
4991
705699a1
WV
4992 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4993 if (!r)
4994 return;
4995
a20ed54d
YZ
4996 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4997 return;
4998
b95234c8
PB
4999 /* If a previous notification has sent the IPI, nothing to do. */
5000 if (pi_test_and_set_on(&vmx->pi_desc))
5001 return;
5002
5003 if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ
5004 kvm_vcpu_kick(vcpu);
5005}
5006
a3a8ff8e
NHE
5007/*
5008 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5009 * will not change in the lifetime of the guest.
5010 * Note that host-state that does change is set elsewhere. E.g., host-state
5011 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5012 */
a547c6db 5013static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE
5014{
5015 u32 low32, high32;
5016 unsigned long tmpl;
5017 struct desc_ptr dt;
04ac88ab 5018 unsigned long cr0, cr4;
a3a8ff8e 5019
04ac88ab
AL
5020 cr0 = read_cr0();
5021 WARN_ON(cr0 & X86_CR0_TS);
5022 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
a3a8ff8e
NHE
5023 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
5024
d974baa3 5025 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 5026 cr4 = cr4_read_shadow();
d974baa3
AL
5027 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5028 vmx->host_state.vmcs_host_cr4 = cr4;
5029
a3a8ff8e 5030 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK
5031#ifdef CONFIG_X86_64
5032 /*
5033 * Load null selectors, so we can avoid reloading them in
5034 * __vmx_load_host_state(), in case userspace uses the null selectors
5035 * too (the expected case).
5036 */
5037 vmcs_write16(HOST_DS_SELECTOR, 0);
5038 vmcs_write16(HOST_ES_SELECTOR, 0);
5039#else
a3a8ff8e
NHE
5040 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5041 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 5042#endif
a3a8ff8e
NHE
5043 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5044 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5045
5046 native_store_idt(&dt);
5047 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 5048 vmx->host_idt_base = dt.address;
a3a8ff8e 5049
83287ea4 5050 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE
5051
5052 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5053 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5054 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5055 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5056
5057 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5058 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5059 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5060 }
5061}
5062
bf8179a0
NHE
5063static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5064{
5065 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5066 if (enable_ept)
5067 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE
5068 if (is_guest_mode(&vmx->vcpu))
5069 vmx->vcpu.arch.cr4_guest_owned_bits &=
5070 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE
5071 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5072}
5073
01e439be
YZ
5074static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5075{
5076 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5077
d62caabb 5078 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 5079 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
64672c95
YJ
5080 /* Enable the preemption timer dynamically */
5081 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ
5082 return pin_based_exec_ctrl;
5083}
5084
d62caabb
AS
5085static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5086{
5087 struct vcpu_vmx *vmx = to_vmx(vcpu);
5088
5089 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK
5090 if (cpu_has_secondary_exec_ctrls()) {
5091 if (kvm_vcpu_apicv_active(vcpu))
5092 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5093 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5094 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5095 else
5096 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5097 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5098 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5099 }
5100
5101 if (cpu_has_vmx_msr_bitmap())
5102 vmx_set_msr_bitmap(vcpu);
d62caabb
AS
5103}
5104
bf8179a0
NHE
5105static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5106{
5107 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB
5108
5109 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5110 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5111
35754c98 5112 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE
5113 exec_control &= ~CPU_BASED_TPR_SHADOW;
5114#ifdef CONFIG_X86_64
5115 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5116 CPU_BASED_CR8_LOAD_EXITING;
5117#endif
5118 }
5119 if (!enable_ept)
5120 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5121 CPU_BASED_CR3_LOAD_EXITING |
5122 CPU_BASED_INVLPG_EXITING;
5123 return exec_control;
5124}
5125
5126static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5127{
5128 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 5129 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE
5130 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5131 if (vmx->vpid == 0)
5132 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5133 if (!enable_ept) {
5134 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5135 enable_unrestricted_guest = 0;
ad756a16
MJ
5136 /* Enable INVPCID for non-ept guests may cause performance regression. */
5137 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE
5138 }
5139 if (!enable_unrestricted_guest)
5140 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5141 if (!ple_gap)
5142 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
d62caabb 5143 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
c7c9c56c
YZ
5144 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5145 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 5146 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG
5147 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5148 (handle_vmptrld).
5149 We can NOT enable shadow_vmcs here because we don't have yet
5150 a current VMCS12
5151 */
5152 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH
5153
5154 if (!enable_pml)
5155 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 5156
bf8179a0
NHE
5157 return exec_control;
5158}
5159
ce88decf
XG
5160static void ept_set_mmio_spte_mask(void)
5161{
5162 /*
5163 * EPT Misconfigurations can be generated if the value of bits 2:0
5164 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 5165 */
312b616b 5166 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
ce88decf
XG
5167}
5168
f53cd63c 5169#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK
5170/*
5171 * Sets up the vmcs for emulated real mode.
5172 */
8b9cf98c 5173static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 5174{
2e4ce7f5 5175#ifdef CONFIG_X86_64
6aa8b732 5176 unsigned long a;
2e4ce7f5 5177#endif
6aa8b732 5178 int i;
6aa8b732 5179
6aa8b732 5180 /* I/O */
3e7c73e9
AK
5181 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5182 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 5183
4607c2d7
AG
5184 if (enable_shadow_vmcs) {
5185 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5186 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5187 }
25c5f225 5188 if (cpu_has_vmx_msr_bitmap())
5897297b 5189 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 5190
6aa8b732
AK
5191 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5192
6aa8b732 5193 /* Control */
01e439be 5194 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
64672c95 5195 vmx->hv_deadline_tsc = -1;
6e5d865c 5196
bf8179a0 5197 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 5198
dfa169bb 5199 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE
5200 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5201 vmx_secondary_exec_control(vmx));
dfa169bb 5202 }
f78e0e2e 5203
d62caabb 5204 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ
5205 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5206 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5207 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5208 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5209
5210 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 5211
0bcf261c 5212 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 5213 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ
5214 }
5215
4b8d54f9
ZE
5216 if (ple_gap) {
5217 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK
5218 vmx->ple_window = ple_window;
5219 vmx->ple_window_dirty = true;
4b8d54f9
ZE
5220 }
5221
c3707958
XG
5222 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5223 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK
5224 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5225
9581d442
AK
5226 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5227 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 5228 vmx_set_constant_host_state(vmx);
05b3e0c2 5229#ifdef CONFIG_X86_64
6aa8b732
AK
5230 rdmsrl(MSR_FS_BASE, a);
5231 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5232 rdmsrl(MSR_GS_BASE, a);
5233 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5234#else
5235 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5236 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5237#endif
5238
2cc51560
ED
5239 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5240 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 5241 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 5242 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 5243 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 5244
74545705
RK
5245 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5246 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 5247
03916db9 5248 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK
5249 u32 index = vmx_msr_index[i];
5250 u32 data_low, data_high;
a2fa3e9f 5251 int j = vmx->nmsrs;
6aa8b732
AK
5252
5253 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5254 continue;
432bd6cb
AK
5255 if (wrmsr_safe(index, data_low, data_high) < 0)
5256 continue;
26bb0981
AK
5257 vmx->guest_msrs[j].index = i;
5258 vmx->guest_msrs[j].data = 0;
d5696725 5259 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 5260 ++vmx->nmsrs;
6aa8b732 5261 }
6aa8b732 5262
2961e876
GN
5263
5264 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK
5265
5266 /* 22.2.1, 20.8.1 */
2961e876 5267 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 5268
bd7e5b08
PB
5269 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5270 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5271
bf8179a0 5272 set_cr4_guest_host_mask(vmx);
e00c8cf2 5273
f53cd63c
WL
5274 if (vmx_xsaves_supported())
5275 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5276
4e59516a
PF
5277 if (enable_pml) {
5278 ASSERT(vmx->pml_pg);
5279 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5280 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5281 }
5282
e00c8cf2
AK
5283 return 0;
5284}
5285
d28bc9dd 5286static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK
5287{
5288 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 5289 struct msr_data apic_base_msr;
d28bc9dd 5290 u64 cr0;
e00c8cf2 5291
7ffd92c5 5292 vmx->rmode.vm86_active = 0;
e00c8cf2 5293
ad312c7c 5294 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA
5295 kvm_set_cr8(vcpu, 0);
5296
5297 if (!init_event) {
5298 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5299 MSR_IA32_APICBASE_ENABLE;
5300 if (kvm_vcpu_is_reset_bsp(vcpu))
5301 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5302 apic_base_msr.host_initiated = true;
5303 kvm_set_apic_base(vcpu, &apic_base_msr);
5304 }
e00c8cf2 5305
2fb92db1
AK
5306 vmx_segment_cache_clear(vmx);
5307
5706be0d 5308 seg_setup(VCPU_SREG_CS);
66450a21 5309 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 5310 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK
5311
5312 seg_setup(VCPU_SREG_DS);
5313 seg_setup(VCPU_SREG_ES);
5314 seg_setup(VCPU_SREG_FS);
5315 seg_setup(VCPU_SREG_GS);
5316 seg_setup(VCPU_SREG_SS);
5317
5318 vmcs_write16(GUEST_TR_SELECTOR, 0);
5319 vmcs_writel(GUEST_TR_BASE, 0);
5320 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5321 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5322
5323 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5324 vmcs_writel(GUEST_LDTR_BASE, 0);
5325 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5326 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5327
d28bc9dd
NA
5328 if (!init_event) {
5329 vmcs_write32(GUEST_SYSENTER_CS, 0);
5330 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5331 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5332 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5333 }
e00c8cf2
AK
5334
5335 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 5336 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 5337
e00c8cf2
AK
5338 vmcs_writel(GUEST_GDTR_BASE, 0);
5339 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5340
5341 vmcs_writel(GUEST_IDTR_BASE, 0);
5342 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5343
443381a8 5344 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 5345 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 5346 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
e00c8cf2 5347
e00c8cf2
AK
5348 setup_msrs(vmx);
5349
6aa8b732
AK
5350 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5351
d28bc9dd 5352 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 5353 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 5354 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 5355 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 5356 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY
5357 vmcs_write32(TPR_THRESHOLD, 0);
5358 }
5359
a73896cb 5360 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 5361
d62caabb 5362 if (kvm_vcpu_apicv_active(vcpu))
01e439be
YZ
5363 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5364
2384d2b3
SY
5365 if (vmx->vpid != 0)
5366 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5367
d28bc9dd 5368 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 5369 vmx->vcpu.arch.cr0 = cr0;
f2463247 5370 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 5371 vmx_set_cr4(vcpu, 0);
5690891b 5372 vmx_set_efer(vcpu, 0);
bd7e5b08 5373
d28bc9dd 5374 update_exception_bitmap(vcpu);
6aa8b732 5375
dd5f5341 5376 vpid_sync_context(vmx->vpid);
6aa8b732
AK
5377}
5378
b6f1250e
NHE
5379/*
5380 * In nested virtualization, check if L1 asked to exit on external interrupts.
5381 * For most existing hypervisors, this will always return true.
5382 */
5383static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5384{
5385 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5386 PIN_BASED_EXT_INTR_MASK;
5387}
5388
77b0f5d6
BD
5389/*
5390 * In nested virtualization, check if L1 has set
5391 * VM_EXIT_ACK_INTR_ON_EXIT
5392 */
5393static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5394{
5395 return get_vmcs12(vcpu)->vm_exit_controls &
5396 VM_EXIT_ACK_INTR_ON_EXIT;
5397}
5398
ea8ceb83
JK
5399static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5400{
5401 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5402 PIN_BASED_NMI_EXITING;
5403}
5404
c9a7953f 5405static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 5406{
47c0152e
PB
5407 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5408 CPU_BASED_VIRTUAL_INTR_PENDING);
3b86cd99
JK
5409}
5410
c9a7953f 5411static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 5412{
2c82878b 5413 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK
5414 enable_irq_window(vcpu);
5415 return;
5416 }
3b86cd99 5417
47c0152e
PB
5418 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5419 CPU_BASED_VIRTUAL_NMI_PENDING);
3b86cd99
JK
5420}
5421
66fd3f7f 5422static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 5423{
9c8cba37 5424 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN
5425 uint32_t intr;
5426 int irq = vcpu->arch.interrupt.nr;
9c8cba37 5427
229456fc 5428 trace_kvm_inj_virq(irq);
2714d1d3 5429
fa89a817 5430 ++vcpu->stat.irq_injections;
7ffd92c5 5431 if (vmx->rmode.vm86_active) {
71f9833b
SH
5432 int inc_eip = 0;
5433 if (vcpu->arch.interrupt.soft)
5434 inc_eip = vcpu->arch.event_exit_inst_len;
5435 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 5436 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED
5437 return;
5438 }
66fd3f7f
GN
5439 intr = irq | INTR_INFO_VALID_MASK;
5440 if (vcpu->arch.interrupt.soft) {
5441 intr |= INTR_TYPE_SOFT_INTR;
5442 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5443 vmx->vcpu.arch.event_exit_inst_len);
5444 } else
5445 intr |= INTR_TYPE_EXT_INTR;
5446 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED
5447}
5448
f08864b4
SY
5449static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5450{
66a5a347
JK
5451 struct vcpu_vmx *vmx = to_vmx(vcpu);
5452
c5a6d5f7 5453 if (!is_guest_mode(vcpu)) {
c5a6d5f7
WL
5454 ++vcpu->stat.nmi_injections;
5455 vmx->nmi_known_unmasked = false;
3b86cd99
JK
5456 }
5457
7ffd92c5 5458 if (vmx->rmode.vm86_active) {
71f9833b 5459 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 5460 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK
5461 return;
5462 }
c5a6d5f7 5463
f08864b4
SY
5464 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5465 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY
5466}
5467
3cfc3092
JK
5468static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5469{
9d58b931
AK
5470 if (to_vmx(vcpu)->nmi_known_unmasked)
5471 return false;
c332c83a 5472 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK
5473}
5474
5475static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5476{
5477 struct vcpu_vmx *vmx = to_vmx(vcpu);
5478
2c82878b
PB
5479 vmx->nmi_known_unmasked = !masked;
5480 if (masked)
5481 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5482 GUEST_INTR_STATE_NMI);
5483 else
5484 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5485 GUEST_INTR_STATE_NMI);
3cfc3092
JK
5486}
5487
2505dc9f
JK
5488static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5489{
b6b8a145
JK
5490 if (to_vmx(vcpu)->nested.nested_run_pending)
5491 return 0;
ea8ceb83 5492
2505dc9f
JK
5493 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5494 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5495 | GUEST_INTR_STATE_NMI));
5496}
5497
78646121
GN
5498static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5499{
b6b8a145
JK
5500 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5501 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN
5502 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5503 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN
5504}
5505
cbc94022
IE
5506static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5507{
5508 int ret;
cbc94022 5509
1d8007bd
PB
5510 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5511 PAGE_SIZE * 3);
cbc94022
IE
5512 if (ret)
5513 return ret;
bfc6d222 5514 kvm->arch.tss_addr = addr;
1f755a82 5515 return init_rmode_tss(kvm);
cbc94022
IE
5516}
5517
0ca1b4f4 5518static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 5519{
77ab6db0 5520 switch (vec) {
77ab6db0 5521 case BP_VECTOR:
c573cd22
JK
5522 /*
5523 * Update instruction length as we may reinject the exception
5524 * from user space while in guest debugging mode.
5525 */
5526 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5527 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 5528 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN
5529 return false;
5530 /* fall through */
5531 case DB_VECTOR:
5532 if (vcpu->guest_debug &
5533 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5534 return false;
d0bfb940
JK
5535 /* fall through */
5536 case DE_VECTOR:
77ab6db0
JK
5537 case OF_VECTOR:
5538 case BR_VECTOR:
5539 case UD_VECTOR:
5540 case DF_VECTOR:
5541 case SS_VECTOR:
5542 case GP_VECTOR:
5543 case MF_VECTOR:
0ca1b4f4
GN
5544 return true;
5545 break;
77ab6db0 5546 }
0ca1b4f4
GN
5547 return false;
5548}
5549
5550static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5551 int vec, u32 err_code)
5552{
5553 /*
5554 * Instruction with address size override prefix opcode 0x67
5555 * Cause the #SS fault with 0 error code in VM86 mode.
5556 */
5557 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5558 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5559 if (vcpu->arch.halt_request) {
5560 vcpu->arch.halt_request = 0;
5cb56059 5561 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN
5562 }
5563 return 1;
5564 }
5565 return 0;
5566 }
5567
5568 /*
5569 * Forward all other exceptions that are valid in real mode.
5570 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5571 * the required debugging infrastructure rework.
5572 */
5573 kvm_queue_exception(vcpu, vec);
5574 return 1;
6aa8b732
AK
5575}
5576
a0861c02
AK
5577/*
5578 * Trigger machine check on the host. We assume all the MSRs are already set up
5579 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5580 * We pass a fake environment to the machine check handler because we want
5581 * the guest to be always treated like user space, no matter what context
5582 * it used internally.
5583 */
5584static void kvm_machine_check(void)
5585{
5586#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5587 struct pt_regs regs = {
5588 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5589 .flags = X86_EFLAGS_IF,
5590 };
5591
5592 do_machine_check(&regs, 0);
5593#endif
5594}
5595
851ba692 5596static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK
5597{
5598 /* already handled by vcpu_run */
5599 return 1;
5600}
5601
851ba692 5602static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5603{
1155f76a 5604 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5605 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5606 u32 intr_info, ex_no, error_code;
42dbaa5a 5607 unsigned long cr2, rip, dr6;
6aa8b732
AK
5608 u32 vect_info;
5609 enum emulation_result er;
5610
1155f76a 5611 vect_info = vmx->idt_vectoring_info;
88786475 5612 intr_info = vmx->exit_intr_info;
6aa8b732 5613
a0861c02 5614 if (is_machine_check(intr_info))
851ba692 5615 return handle_machine_check(vcpu);
a0861c02 5616
ef85b673 5617 if (is_nmi(intr_info))
1b6269db 5618 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc 5619
7aa81cc0 5620 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK
5621 if (is_guest_mode(vcpu)) {
5622 kvm_queue_exception(vcpu, UD_VECTOR);
5623 return 1;
5624 }
51d8b661 5625 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5626 if (er != EMULATE_DONE)
7ee5d940 5627 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL
5628 return 1;
5629 }
5630
6aa8b732 5631 error_code = 0;
2e11384c 5632 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5633 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG
5634
5635 /*
5636 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5637 * MMIO, it is better to report an internal error.
5638 * See the comments in vmx_handle_exit.
5639 */
5640 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5641 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5642 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5643 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5644 vcpu->run->internal.ndata = 3;
bf4ca23e
XG
5645 vcpu->run->internal.data[0] = vect_info;
5646 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5647 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG
5648 return 0;
5649 }
5650
6aa8b732 5651 if (is_page_fault(intr_info)) {
1439442c 5652 /* EPT won't cause page fault directly */
cf3ace79 5653 BUG_ON(enable_ept);
6aa8b732 5654 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT
5655 trace_kvm_page_fault(cr2, error_code);
5656
3298b75c 5657 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5658 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5659 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK
5660 }
5661
d0bfb940 5662 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN
5663
5664 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5665 return handle_rmode_exception(vcpu, ex_no, error_code);
5666
42dbaa5a 5667 switch (ex_no) {
54a20552
EN
5668 case AC_VECTOR:
5669 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5670 return 1;
42dbaa5a
JK
5671 case DB_VECTOR:
5672 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5673 if (!(vcpu->guest_debug &
5674 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5675 vcpu->arch.dr6 &= ~15;
6f43ed01 5676 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD
5677 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5678 skip_emulated_instruction(vcpu);
5679
42dbaa5a
JK
5680 kvm_queue_exception(vcpu, DB_VECTOR);
5681 return 1;
5682 }
5683 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5684 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5685 /* fall through */
5686 case BP_VECTOR:
c573cd22
JK
5687 /*
5688 * Update instruction length as we may reinject #BP from
5689 * user space while in guest debugging mode. Reading it for
5690 * #DB as well causes no harm, it is not used in that case.
5691 */
5692 vmx->vcpu.arch.event_exit_inst_len =
5693 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5694 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5695 rip = kvm_rip_read(vcpu);
d0bfb940
JK
5696 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5697 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK
5698 break;
5699 default:
d0bfb940
JK
5700 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5701 kvm_run->ex.exception = ex_no;
5702 kvm_run->ex.error_code = error_code;
42dbaa5a 5703 break;
6aa8b732 5704 }
6aa8b732
AK
5705 return 0;
5706}
5707
851ba692 5708static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5709{
1165f5fe 5710 ++vcpu->stat.irq_exits;
6aa8b732
AK
5711 return 1;
5712}
5713
851ba692 5714static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5715{
851ba692 5716 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK
5717 return 0;
5718}
6aa8b732 5719
851ba692 5720static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5721{
bfdaab09 5722 unsigned long exit_qualification;
6affcbed 5723 int size, in, string, ret;
039576c0 5724 unsigned port;
6aa8b732 5725
bfdaab09 5726 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5727 string = (exit_qualification & 16) != 0;
cf8f70bf 5728 in = (exit_qualification & 8) != 0;
e70669ab 5729
cf8f70bf 5730 ++vcpu->stat.io_exits;
e70669ab 5731
cf8f70bf 5732 if (string || in)
51d8b661 5733 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5734
cf8f70bf
GN
5735 port = exit_qualification >> 16;
5736 size = (exit_qualification & 7) + 1;
cf8f70bf 5737
6affcbed
KH
5738 ret = kvm_skip_emulated_instruction(vcpu);
5739
5740 /*
5741 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5742 * KVM_EXIT_DEBUG here.
5743 */
5744 return kvm_fast_pio_out(vcpu, size, port) && ret;
6aa8b732
AK
5745}
5746
102d8325
IM
5747static void
5748vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5749{
5750 /*
5751 * Patch in the VMCALL instruction:
5752 */
5753 hypercall[0] = 0x0f;
5754 hypercall[1] = 0x01;
5755 hypercall[2] = 0xc1;
102d8325
IM
5756}
5757
0fa06071 5758/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE
5759static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5760{
eeadf9e7 5761 if (is_guest_mode(vcpu)) {
1a0d74e6
JK
5762 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5763 unsigned long orig_val = val;
5764
eeadf9e7
NHE
5765 /*
5766 * We get here when L2 changed cr0 in a way that did not change
5767 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK
5768 * but did change L0 shadowed bits. So we first calculate the
5769 * effective cr0 value that L1 would like to write into the
5770 * hardware. It consists of the L2-owned bits from the new
5771 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5772 */
1a0d74e6
JK
5773 val = (val & ~vmcs12->cr0_guest_host_mask) |
5774 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5775
3899152c 5776 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 5777 return 1;
1a0d74e6
JK
5778
5779 if (kvm_set_cr0(vcpu, val))
5780 return 1;
5781 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5782 return 0;
1a0d74e6
JK
5783 } else {
5784 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 5785 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 5786 return 1;
3899152c 5787
eeadf9e7 5788 return kvm_set_cr0(vcpu, val);
1a0d74e6 5789 }
eeadf9e7
NHE
5790}
5791
5792static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5793{
5794 if (is_guest_mode(vcpu)) {
1a0d74e6
JK
5795 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5796 unsigned long orig_val = val;
5797
5798 /* analogously to handle_set_cr0 */
5799 val = (val & ~vmcs12->cr4_guest_host_mask) |
5800 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5801 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5802 return 1;
1a0d74e6 5803 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE
5804 return 0;
5805 } else
5806 return kvm_set_cr4(vcpu, val);
5807}
5808
851ba692 5809static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5810{
229456fc 5811 unsigned long exit_qualification, val;
6aa8b732
AK
5812 int cr;
5813 int reg;
49a9b07e 5814 int err;
6affcbed 5815 int ret;
6aa8b732 5816
bfdaab09 5817 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK
5818 cr = exit_qualification & 15;
5819 reg = (exit_qualification >> 8) & 15;
5820 switch ((exit_qualification >> 4) & 3) {
5821 case 0: /* mov to cr */
1e32c079 5822 val = kvm_register_readl(vcpu, reg);
229456fc 5823 trace_kvm_cr_write(cr, val);
6aa8b732
AK
5824 switch (cr) {
5825 case 0:
eeadf9e7 5826 err = handle_set_cr0(vcpu, val);
6affcbed 5827 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 5828 case 3:
2390218b 5829 err = kvm_set_cr3(vcpu, val);
6affcbed 5830 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 5831 case 4:
eeadf9e7 5832 err = handle_set_cr4(vcpu, val);
6affcbed 5833 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN
5834 case 8: {
5835 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5836 u8 cr8 = (u8)val;
eea1cff9 5837 err = kvm_set_cr8(vcpu, cr8);
6affcbed 5838 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 5839 if (lapic_in_kernel(vcpu))
6affcbed 5840 return ret;
0a5fff19 5841 if (cr8_prev <= cr8)
6affcbed
KH
5842 return ret;
5843 /*
5844 * TODO: we might be squashing a
5845 * KVM_GUESTDBG_SINGLESTEP-triggered
5846 * KVM_EXIT_DEBUG here.
5847 */
851ba692 5848 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN
5849 return 0;
5850 }
4b8073e4 5851 }
6aa8b732 5852 break;
25c4c276 5853 case 2: /* clts */
bd7e5b08
PB
5854 WARN_ONCE(1, "Guest should always own CR0.TS");
5855 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 5856 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 5857 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5858 case 1: /*mov from cr*/
5859 switch (cr) {
5860 case 3:
9f8fe504
AK
5861 val = kvm_read_cr3(vcpu);
5862 kvm_register_write(vcpu, reg, val);
5863 trace_kvm_cr_read(cr, val);
6affcbed 5864 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 5865 case 8:
229456fc
MT
5866 val = kvm_get_cr8(vcpu);
5867 kvm_register_write(vcpu, reg, val);
5868 trace_kvm_cr_read(cr, val);
6affcbed 5869 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5870 }
5871 break;
5872 case 3: /* lmsw */
a1f83a74 5873 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5874 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5875 kvm_lmsw(vcpu, val);
6aa8b732 5876
6affcbed 5877 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5878 default:
5879 break;
5880 }
851ba692 5881 vcpu->run->exit_reason = 0;
a737f256 5882 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK
5883 (int)(exit_qualification >> 4) & 3, cr);
5884 return 0;
5885}
5886
851ba692 5887static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5888{
bfdaab09 5889 unsigned long exit_qualification;
16f8a6f9
NA
5890 int dr, dr7, reg;
5891
5892 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5893 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5894
5895 /* First, if DR does not exist, trigger UD */
5896 if (!kvm_require_dr(vcpu, dr))
5897 return 1;
6aa8b732 5898
f2483415 5899 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK
5900 if (!kvm_require_cpl(vcpu, 0))
5901 return 1;
16f8a6f9
NA
5902 dr7 = vmcs_readl(GUEST_DR7);
5903 if (dr7 & DR7_GD) {
42dbaa5a
JK
5904 /*
5905 * As the vm-exit takes precedence over the debug trap, we
5906 * need to emulate the latter, either for the host or the
5907 * guest debugging itself.
5908 */
5909 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5910 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5911 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5912 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK
5913 vcpu->run->debug.arch.exception = DB_VECTOR;
5914 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK
5915 return 0;
5916 } else {
7305eb5d 5917 vcpu->arch.dr6 &= ~15;
6f43ed01 5918 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK
5919 kvm_queue_exception(vcpu, DB_VECTOR);
5920 return 1;
5921 }
5922 }
5923
81908bf4 5924 if (vcpu->guest_debug == 0) {
8f22372f
PB
5925 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5926 CPU_BASED_MOV_DR_EXITING);
81908bf4
PB
5927
5928 /*
5929 * No more DR vmexits; force a reload of the debug registers
5930 * and reenter on this instruction. The next vmexit will
5931 * retrieve the full state of the debug registers.
5932 */
5933 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5934 return 1;
5935 }
5936
42dbaa5a
JK
5937 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5938 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5939 unsigned long val;
4c4d563b
JK
5940
5941 if (kvm_get_dr(vcpu, dr, &val))
5942 return 1;
5943 kvm_register_write(vcpu, reg, val);
020df079 5944 } else
5777392e 5945 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK
5946 return 1;
5947
6affcbed 5948 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5949}
5950
73aaf249
JK
5951static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5952{
5953 return vcpu->arch.dr6;
5954}
5955
5956static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5957{
5958}
5959
81908bf4
PB
5960static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5961{
81908bf4
PB
5962 get_debugreg(vcpu->arch.db[0], 0);
5963 get_debugreg(vcpu->arch.db[1], 1);
5964 get_debugreg(vcpu->arch.db[2], 2);
5965 get_debugreg(vcpu->arch.db[3], 3);
5966 get_debugreg(vcpu->arch.dr6, 6);
5967 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5968
5969 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
8f22372f 5970 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
81908bf4
PB
5971}
5972
020df079
GN
5973static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5974{
5975 vmcs_writel(GUEST_DR7, val);
5976}
5977
851ba692 5978static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5979{
6a908b62 5980 return kvm_emulate_cpuid(vcpu);
6aa8b732
AK
5981}
5982
851ba692 5983static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5984{
ad312c7c 5985 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 5986 struct msr_data msr_info;
6aa8b732 5987
609e36d3
PB
5988 msr_info.index = ecx;
5989 msr_info.host_initiated = false;
5990 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 5991 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5992 kvm_inject_gp(vcpu, 0);
6aa8b732
AK
5993 return 1;
5994 }
5995
609e36d3 5996 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 5997
6aa8b732 5998 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB
5999 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6000 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6affcbed 6001 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
6002}
6003
851ba692 6004static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 6005{
8fe8ab46 6006 struct msr_data msr;
ad312c7c
ZX
6007 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6008 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6009 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 6010
8fe8ab46
WA
6011 msr.data = data;
6012 msr.index = ecx;
6013 msr.host_initiated = false;
854e8bb1 6014 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 6015 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 6016 kvm_inject_gp(vcpu, 0);
6aa8b732
AK
6017 return 1;
6018 }
6019
59200273 6020 trace_kvm_msr_write(ecx, data);
6affcbed 6021 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
6022}
6023
851ba692 6024static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 6025{
eb90f341 6026 kvm_apic_update_ppr(vcpu);
6e5d865c
YS
6027 return 1;
6028}
6029
851ba692 6030static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 6031{
47c0152e
PB
6032 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6033 CPU_BASED_VIRTUAL_INTR_PENDING);
2714d1d3 6034
3842d135
AK
6035 kvm_make_request(KVM_REQ_EVENT, vcpu);
6036
a26bf12a 6037 ++vcpu->stat.irq_window_exits;
6aa8b732
AK
6038 return 1;
6039}
6040
851ba692 6041static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 6042{
d3bef15f 6043 return kvm_emulate_halt(vcpu);
6aa8b732
AK
6044}
6045
851ba692 6046static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 6047{
0d9c055e 6048 return kvm_emulate_hypercall(vcpu);
c21415e8
IM
6049}
6050
ec25d5e6
GN
6051static int handle_invd(struct kvm_vcpu *vcpu)
6052{
51d8b661 6053 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN
6054}
6055
851ba692 6056static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 6057{
f9c617f6 6058 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT
6059
6060 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 6061 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT
6062}
6063
fee84b07
AK
6064static int handle_rdpmc(struct kvm_vcpu *vcpu)
6065{
6066 int err;
6067
6068 err = kvm_rdpmc(vcpu);
6affcbed 6069 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK
6070}
6071
851ba692 6072static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 6073{
6affcbed 6074 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED
6075}
6076
2acf923e
DC
6077static int handle_xsetbv(struct kvm_vcpu *vcpu)
6078{
6079 u64 new_bv = kvm_read_edx_eax(vcpu);
6080 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6081
6082 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 6083 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC
6084 return 1;
6085}
6086
f53cd63c
WL
6087static int handle_xsaves(struct kvm_vcpu *vcpu)
6088{
6affcbed 6089 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL
6090 WARN(1, "this should never happen\n");
6091 return 1;
6092}
6093
6094static int handle_xrstors(struct kvm_vcpu *vcpu)
6095{
6affcbed 6096 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL
6097 WARN(1, "this should never happen\n");
6098 return 1;
6099}
6100
851ba692 6101static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 6102{
58fbbf26
KT
6103 if (likely(fasteoi)) {
6104 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6105 int access_type, offset;
6106
6107 access_type = exit_qualification & APIC_ACCESS_TYPE;
6108 offset = exit_qualification & APIC_ACCESS_OFFSET;
6109 /*
6110 * Sane guest uses MOV to write EOI, with written value
6111 * not cared. So make a short-circuit here by avoiding
6112 * heavy instruction emulation.
6113 */
6114 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6115 (offset == APIC_EOI)) {
6116 kvm_lapic_set_eoi(vcpu);
6affcbed 6117 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT
6118 }
6119 }
51d8b661 6120 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY
6121}
6122
c7c9c56c
YZ
6123static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6124{
6125 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6126 int vector = exit_qualification & 0xff;
6127
6128 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6129 kvm_apic_set_eoi_accelerated(vcpu, vector);
6130 return 1;
6131}
6132
83d4c286
YZ
6133static int handle_apic_write(struct kvm_vcpu *vcpu)
6134{
6135 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6136 u32 offset = exit_qualification & 0xfff;
6137
6138 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6139 kvm_apic_write_nodecode(vcpu, offset);
6140 return 1;
6141}
6142
851ba692 6143static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 6144{
60637aac 6145 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 6146 unsigned long exit_qualification;
e269fb21
JK
6147 bool has_error_code = false;
6148 u32 error_code = 0;
37817f29 6149 u16 tss_selector;
7f3d35fd 6150 int reason, type, idt_v, idt_index;
64a7ec06
GN
6151
6152 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 6153 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 6154 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE
6155
6156 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6157
6158 reason = (u32)exit_qualification >> 30;
64a7ec06
GN
6159 if (reason == TASK_SWITCH_GATE && idt_v) {
6160 switch (type) {
6161 case INTR_TYPE_NMI_INTR:
6162 vcpu->arch.nmi_injected = false;
654f06fc 6163 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN
6164 break;
6165 case INTR_TYPE_EXT_INTR:
66fd3f7f 6166 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN
6167 kvm_clear_interrupt_queue(vcpu);
6168 break;
6169 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK
6170 if (vmx->idt_vectoring_info &
6171 VECTORING_INFO_DELIVER_CODE_MASK) {
6172 has_error_code = true;
6173 error_code =
6174 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6175 }
6176 /* fall through */
64a7ec06
GN
6177 case INTR_TYPE_SOFT_EXCEPTION:
6178 kvm_clear_exception_queue(vcpu);
6179 break;
6180 default:
6181 break;
6182 }
60637aac 6183 }
37817f29
IE
6184 tss_selector = exit_qualification;
6185
64a7ec06
GN
6186 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6187 type != INTR_TYPE_EXT_INTR &&
6188 type != INTR_TYPE_NMI_INTR))
6189 skip_emulated_instruction(vcpu);
6190
7f3d35fd
KW
6191 if (kvm_task_switch(vcpu, tss_selector,
6192 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6193 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN
6194 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6195 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6196 vcpu->run->internal.ndata = 0;
42dbaa5a 6197 return 0;
acb54517 6198 }
42dbaa5a 6199
42dbaa5a
JK
6200 /*
6201 * TODO: What about debug traps on tss switch?
6202 * Are we supposed to inject them and update dr6?
6203 */
6204
6205 return 1;
37817f29
IE
6206}
6207
851ba692 6208static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 6209{
f9c617f6 6210 unsigned long exit_qualification;
1439442c 6211 gpa_t gpa;
4f5982a5 6212 u32 error_code;
1439442c 6213
f9c617f6 6214 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 6215
ae1e2d10
PB
6216 if (is_guest_mode(vcpu)
6217 && !(exit_qualification & EPT_VIOLATION_GVA_TRANSLATED)) {
6218 /*
6219 * Fix up exit_qualification according to whether guest
6220 * page table accesses are reads or writes.
6221 */
6222 u64 eptp = nested_ept_get_cr3(vcpu);
33251870 6223 if (!(eptp & VMX_EPT_AD_ENABLE_BIT))
ae1e2d10 6224 exit_qualification &= ~EPT_VIOLATION_ACC_WRITE;
1439442c
SY
6225 }
6226
0be9c7a8
GN
6227 /*
6228 * EPT violation happened while executing iret from NMI,
6229 * "blocked by NMI" bit has to be set before next VM entry.
6230 * There are errata that may cause this bit to not be set:
6231 * AAK134, BY25.
6232 */
bcd1c294 6233 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
bcd1c294 6234 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN
6235 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6236
1439442c 6237 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 6238 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 6239
27959a44 6240 /* Is it a read fault? */
ab22a473 6241 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS
6242 ? PFERR_USER_MASK : 0;
6243 /* Is it a write fault? */
ab22a473 6244 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS
6245 ? PFERR_WRITE_MASK : 0;
6246 /* Is it a fetch fault? */
ab22a473 6247 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS
6248 ? PFERR_FETCH_MASK : 0;
6249 /* ept page table entry is present? */
6250 error_code |= (exit_qualification &
6251 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6252 EPT_VIOLATION_EXECUTABLE))
6253 ? PFERR_PRESENT_MASK : 0;
4f5982a5 6254
db1c056c 6255 vcpu->arch.gpa_available = true;
25d92081
YZ
6256 vcpu->arch.exit_qualification = exit_qualification;
6257
4f5982a5 6258 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY
6259}
6260
851ba692 6261static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 6262{
f735d4af 6263 int ret;
68f89400
MT
6264 gpa_t gpa;
6265
6266 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 6267 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 6268 trace_kvm_fast_mmio(gpa);
6affcbed 6269 return kvm_skip_emulated_instruction(vcpu);
68c3b4d1 6270 }
68f89400 6271
450869d6 6272 ret = handle_mmio_page_fault(vcpu, gpa, true);
db1c056c 6273 vcpu->arch.gpa_available = true;
b37fbea6 6274 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG
6275 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6276 EMULATE_DONE;
f8f55942
XG
6277
6278 if (unlikely(ret == RET_MMIO_PF_INVALID))
6279 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6280
b37fbea6 6281 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG
6282 return 1;
6283
6284 /* It is the real ept misconfig */
f735d4af 6285 WARN_ON(1);
68f89400 6286
851ba692
AK
6287 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6288 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT
6289
6290 return 0;
6291}
6292
851ba692 6293static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 6294{
47c0152e
PB
6295 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6296 CPU_BASED_VIRTUAL_NMI_PENDING);
f08864b4 6297 ++vcpu->stat.nmi_window_exits;
3842d135 6298 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY
6299
6300 return 1;
6301}
6302
80ced186 6303static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 6304{
8b3079a5
AK
6305 struct vcpu_vmx *vmx = to_vmx(vcpu);
6306 enum emulation_result err = EMULATE_DONE;
80ced186 6307 int ret = 1;
49e9d557
AK
6308 u32 cpu_exec_ctrl;
6309 bool intr_window_requested;
b8405c18 6310 unsigned count = 130;
49e9d557
AK
6311
6312 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6313 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 6314
98eb2f8b 6315 while (vmx->emulation_required && count-- != 0) {
bdea48e3 6316 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK
6317 return handle_interrupt_window(&vmx->vcpu);
6318
72875d8a 6319 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK
6320 return 1;
6321
991eebf9 6322 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 6323
ac0a48c3 6324 if (err == EMULATE_USER_EXIT) {
94452b9e 6325 ++vcpu->stat.mmio_exits;
80ced186
MG
6326 ret = 0;
6327 goto out;
6328 }
1d5a4d9b 6329
de5f70e0
AK
6330 if (err != EMULATE_DONE) {
6331 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6332 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6333 vcpu->run->internal.ndata = 0;
6d77dbfc 6334 return 0;
de5f70e0 6335 }
ea953ef0 6336
8d76c49e
GN
6337 if (vcpu->arch.halt_request) {
6338 vcpu->arch.halt_request = 0;
5cb56059 6339 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN
6340 goto out;
6341 }
6342
ea953ef0 6343 if (signal_pending(current))
80ced186 6344 goto out;
ea953ef0
MG
6345 if (need_resched())
6346 schedule();
6347 }
6348
80ced186
MG
6349out:
6350 return ret;
ea953ef0
MG
6351}
6352
b4a2d31d
RK
6353static int __grow_ple_window(int val)
6354{
6355 if (ple_window_grow < 1)
6356 return ple_window;
6357
6358 val = min(val, ple_window_actual_max);
6359
6360 if (ple_window_grow < ple_window)
6361 val *= ple_window_grow;
6362 else
6363 val += ple_window_grow;
6364
6365 return val;
6366}
6367
6368static int __shrink_ple_window(int val, int modifier, int minimum)
6369{
6370 if (modifier < 1)
6371 return ple_window;
6372
6373 if (modifier < ple_window)
6374 val /= modifier;
6375 else
6376 val -= modifier;
6377
6378 return max(val, minimum);
6379}
6380
6381static void grow_ple_window(struct kvm_vcpu *vcpu)
6382{
6383 struct vcpu_vmx *vmx = to_vmx(vcpu);
6384 int old = vmx->ple_window;
6385
6386 vmx->ple_window = __grow_ple_window(old);
6387
6388 if (vmx->ple_window != old)
6389 vmx->ple_window_dirty = true;
7b46268d
RK
6390
6391 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK
6392}
6393
6394static void shrink_ple_window(struct kvm_vcpu *vcpu)
6395{
6396 struct vcpu_vmx *vmx = to_vmx(vcpu);
6397 int old = vmx->ple_window;
6398
6399 vmx->ple_window = __shrink_ple_window(old,
6400 ple_window_shrink, ple_window);
6401
6402 if (vmx->ple_window != old)
6403 vmx->ple_window_dirty = true;
7b46268d
RK
6404
6405 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK
6406}
6407
6408/*
6409 * ple_window_actual_max is computed to be one grow_ple_window() below
6410 * ple_window_max. (See __grow_ple_window for the reason.)
6411 * This prevents overflows, because ple_window_max is int.
6412 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6413 * this process.
6414 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6415 */
6416static void update_ple_window_actual_max(void)
6417{
6418 ple_window_actual_max =
6419 __shrink_ple_window(max(ple_window_max, ple_window),
6420 ple_window_grow, INT_MIN);
6421}
6422
bf9f6ac8
FW
6423/*
6424 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6425 */
6426static void wakeup_handler(void)
6427{
6428 struct kvm_vcpu *vcpu;
6429 int cpu = smp_processor_id();
6430
6431 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6432 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6433 blocked_vcpu_list) {
6434 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6435
6436 if (pi_test_on(pi_desc) == 1)
6437 kvm_vcpu_kick(vcpu);
6438 }
6439 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6440}
6441
f160c7b7
JS
6442void vmx_enable_tdp(void)
6443{
6444 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6445 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6446 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6447 0ull, VMX_EPT_EXECUTABLE_MASK,
6448 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
312b616b 6449 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
f160c7b7
JS
6450
6451 ept_set_mmio_spte_mask();
6452 kvm_enable_tdp();
6453}
6454
f2c7648d
TC
6455static __init int hardware_setup(void)
6456{
34a1cd60
TC
6457 int r = -ENOMEM, i, msr;
6458
6459 rdmsrl_safe(MSR_EFER, &host_efer);
6460
6461 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6462 kvm_define_shared_msr(i, vmx_msr_index[i]);
6463
23611332
RK
6464 for (i = 0; i < VMX_BITMAP_NR; i++) {
6465 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6466 if (!vmx_bitmap[i])
6467 goto out;
6468 }
34a1cd60
TC
6469
6470 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
34a1cd60
TC
6471 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6472 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6473
6474 /*
6475 * Allow direct access to the PC debug port (it is often used for I/O
6476 * delays, but the vmexits simply slow things down).
6477 */
6478 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6479 clear_bit(0x80, vmx_io_bitmap_a);
6480
6481 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6482
6483 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6484 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6485
34a1cd60
TC
6486 if (setup_vmcs_config(&vmcs_config) < 0) {
6487 r = -EIO;
23611332 6488 goto out;
baa03522 6489 }
f2c7648d
TC
6490
6491 if (boot_cpu_has(X86_FEATURE_NX))
6492 kvm_enable_efer_bits(EFER_NX);
6493
08d839c4
WL
6494 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6495 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
f2c7648d 6496 enable_vpid = 0;
08d839c4 6497
f2c7648d
TC
6498 if (!cpu_has_vmx_shadow_vmcs())
6499 enable_shadow_vmcs = 0;
6500 if (enable_shadow_vmcs)
6501 init_vmcs_shadow_fields();
6502
6503 if (!cpu_has_vmx_ept() ||
6504 !cpu_has_vmx_ept_4levels()) {
6505 enable_ept = 0;
6506 enable_unrestricted_guest = 0;
6507 enable_ept_ad_bits = 0;
6508 }
6509
fce6ac4c 6510 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
f2c7648d
TC
6511 enable_ept_ad_bits = 0;
6512
6513 if (!cpu_has_vmx_unrestricted_guest())
6514 enable_unrestricted_guest = 0;
6515
ad15a296 6516 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC
6517 flexpriority_enabled = 0;
6518
ad15a296
PB
6519 /*
6520 * set_apic_access_page_addr() is used to reload apic access
6521 * page upon invalidation. No need to do anything if not
6522 * using the APIC_ACCESS_ADDR VMCS field.
6523 */
6524 if (!flexpriority_enabled)
f2c7648d 6525 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC
6526
6527 if (!cpu_has_vmx_tpr_shadow())
6528 kvm_x86_ops->update_cr8_intercept = NULL;
6529
6530 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6531 kvm_disable_largepages();
6532
6533 if (!cpu_has_vmx_ple())
6534 ple_gap = 0;
6535
76dfafd5 6536 if (!cpu_has_vmx_apicv()) {
f2c7648d 6537 enable_apicv = 0;
76dfafd5
PB
6538 kvm_x86_ops->sync_pir_to_irr = NULL;
6539 }
f2c7648d 6540
64903d61
HZ
6541 if (cpu_has_vmx_tsc_scaling()) {
6542 kvm_has_tsc_control = true;
6543 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6544 kvm_tsc_scaling_ratio_frac_bits = 48;
6545 }
6546
baa03522
TC
6547 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6548 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6549 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6550 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6551 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6552 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
baa03522 6553
c63e4563 6554 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
baa03522 6555 vmx_msr_bitmap_legacy, PAGE_SIZE);
c63e4563 6556 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
baa03522 6557 vmx_msr_bitmap_longmode, PAGE_SIZE);
c63e4563 6558 memcpy(vmx_msr_bitmap_legacy_x2apic,
f6e90f9e 6559 vmx_msr_bitmap_legacy, PAGE_SIZE);
c63e4563 6560 memcpy(vmx_msr_bitmap_longmode_x2apic,
f6e90f9e 6561 vmx_msr_bitmap_longmode, PAGE_SIZE);
baa03522 6562
04bb92e4
WL
6563 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6564
40d8338d
RK
6565 for (msr = 0x800; msr <= 0x8ff; msr++) {
6566 if (msr == 0x839 /* TMCCT */)
6567 continue;
2e69f865 6568 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
40d8338d 6569 }
3ce424e4 6570
f6e90f9e 6571 /*
2e69f865
RK
6572 * TPR reads and writes can be virtualized even if virtual interrupt
6573 * delivery is not in use.
f6e90f9e 6574 */
2e69f865
RK
6575 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6576 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
3ce424e4 6577
3ce424e4 6578 /* EOI */
2e69f865 6579 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
3ce424e4 6580 /* SELF-IPI */
2e69f865 6581 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
baa03522 6582
f160c7b7
JS
6583 if (enable_ept)
6584 vmx_enable_tdp();
6585 else
baa03522
TC
6586 kvm_disable_tdp();
6587
6588 update_ple_window_actual_max();
6589
843e4330
KH
6590 /*
6591 * Only enable PML when hardware supports PML feature, and both EPT
6592 * and EPT A/D bit features are enabled -- PML depends on them to work.
6593 */
6594 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6595 enable_pml = 0;
6596
6597 if (!enable_pml) {
6598 kvm_x86_ops->slot_enable_log_dirty = NULL;
6599 kvm_x86_ops->slot_disable_log_dirty = NULL;
6600 kvm_x86_ops->flush_log_dirty = NULL;
6601 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6602 }
6603
64672c95
YJ
6604 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6605 u64 vmx_msr;
6606
6607 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6608 cpu_preemption_timer_multi =
6609 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6610 } else {
6611 kvm_x86_ops->set_hv_timer = NULL;
6612 kvm_x86_ops->cancel_hv_timer = NULL;
6613 }
6614
bf9f6ac8
FW
6615 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6616
c45dcc71
AR
6617 kvm_mce_cap_supported |= MCG_LMCE_P;
6618
f2c7648d 6619 return alloc_kvm_area();
34a1cd60 6620
34a1cd60 6621out:
23611332
RK
6622 for (i = 0; i < VMX_BITMAP_NR; i++)
6623 free_page((unsigned long)vmx_bitmap[i]);
34a1cd60
TC
6624
6625 return r;
f2c7648d
TC
6626}
6627
6628static __exit void hardware_unsetup(void)
6629{
23611332
RK
6630 int i;
6631
6632 for (i = 0; i < VMX_BITMAP_NR; i++)
6633 free_page((unsigned long)vmx_bitmap[i]);
34a1cd60 6634
f2c7648d
TC
6635 free_kvm_area();
6636}
6637
4b8d54f9
ZE
6638/*
6639 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6640 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6641 */
9fb41ba8 6642static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6643{
b4a2d31d
RK
6644 if (ple_gap)
6645 grow_ple_window(vcpu);
6646
4b8d54f9 6647 kvm_vcpu_on_spin(vcpu);
6affcbed 6648 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE
6649}
6650
87c00572 6651static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6652{
6affcbed 6653 return kvm_skip_emulated_instruction(vcpu);
59708670
SY
6654}
6655
87c00572
GS
6656static int handle_mwait(struct kvm_vcpu *vcpu)
6657{
6658 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6659 return handle_nop(vcpu);
6660}
6661
5f3d45e7
MD
6662static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6663{
6664 return 1;
6665}
6666
87c00572
GS
6667static int handle_monitor(struct kvm_vcpu *vcpu)
6668{
6669 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6670 return handle_nop(vcpu);
6671}
6672
ff2f6fe9
NHE
6673/*
6674 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6675 * We could reuse a single VMCS for all the L2 guests, but we also want the
6676 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6677 * allows keeping them loaded on the processor, and in the future will allow
6678 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6679 * every entry if they never change.
6680 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6681 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6682 *
6683 * The following functions allocate and free a vmcs02 in this pool.
6684 */
6685
6686/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6687static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6688{
6689 struct vmcs02_list *item;
6690 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6691 if (item->vmptr == vmx->nested.current_vmptr) {
6692 list_move(&item->list, &vmx->nested.vmcs02_pool);
6693 return &item->vmcs02;
6694 }
6695
6696 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6697 /* Recycle the least recently used VMCS. */
d74c0e6b
GT
6698 item = list_last_entry(&vmx->nested.vmcs02_pool,
6699 struct vmcs02_list, list);
ff2f6fe9
NHE
6700 item->vmptr = vmx->nested.current_vmptr;
6701 list_move(&item->list, &vmx->nested.vmcs02_pool);
6702 return &item->vmcs02;
6703 }
6704
6705 /* Create a new VMCS */
0fa24ce3 6706 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE
6707 if (!item)
6708 return NULL;
6709 item->vmcs02.vmcs = alloc_vmcs();
355f4fb1 6710 item->vmcs02.shadow_vmcs = NULL;
ff2f6fe9
NHE
6711 if (!item->vmcs02.vmcs) {
6712 kfree(item);
6713 return NULL;
6714 }
6715 loaded_vmcs_init(&item->vmcs02);
6716 item->vmptr = vmx->nested.current_vmptr;
6717 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6718 vmx->nested.vmcs02_num++;
6719 return &item->vmcs02;
6720}
6721
6722/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6723static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6724{
6725 struct vmcs02_list *item;
6726 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6727 if (item->vmptr == vmptr) {
6728 free_loaded_vmcs(&item->vmcs02);
6729 list_del(&item->list);
6730 kfree(item);
6731 vmx->nested.vmcs02_num--;
6732 return;
6733 }
6734}
6735
6736/*
6737 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB
6738 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6739 * must be &vmx->vmcs01.
ff2f6fe9
NHE
6740 */
6741static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6742{
6743 struct vmcs02_list *item, *n;
4fa7734c
PB
6744
6745 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6746 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB
6747 /*
6748 * Something will leak if the above WARN triggers. Better than
6749 * a use-after-free.
6750 */
6751 if (vmx->loaded_vmcs == &item->vmcs02)
6752 continue;
6753
6754 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE
6755 list_del(&item->list);
6756 kfree(item);
4fa7734c 6757 vmx->nested.vmcs02_num--;
ff2f6fe9 6758 }
ff2f6fe9
NHE
6759}
6760
0658fbaa
ACL
6761/*
6762 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6763 * set the success or error code of an emulated VMX instruction, as specified
6764 * by Vol 2B, VMX Instruction Reference, "Conventions".
6765 */
6766static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6767{
6768 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6769 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6770 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6771}
6772
6773static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6774{
6775 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6776 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6777 X86_EFLAGS_SF | X86_EFLAGS_OF))
6778 | X86_EFLAGS_CF);
6779}
6780
145c28dd 6781static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL
6782 u32 vm_instruction_error)
6783{
6784 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6785 /*
6786 * failValid writes the error number to the current VMCS, which
6787 * can't be done there isn't a current VMCS.
6788 */
6789 nested_vmx_failInvalid(vcpu);
6790 return;
6791 }
6792 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6793 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6794 X86_EFLAGS_SF | X86_EFLAGS_OF))
6795 | X86_EFLAGS_ZF);
6796 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6797 /*
6798 * We don't need to force a shadow sync because
6799 * VM_INSTRUCTION_ERROR is not shadowed
6800 */
6801}
145c28dd 6802
ff651cb6
WV
6803static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6804{
6805 /* TODO: not to reset guest simply here. */
6806 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
bbe41b95 6807 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
ff651cb6
WV
6808}
6809
f4124500
JK
6810static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6811{
6812 struct vcpu_vmx *vmx =
6813 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6814
6815 vmx->nested.preemption_timer_expired = true;
6816 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6817 kvm_vcpu_kick(&vmx->vcpu);
6818
6819 return HRTIMER_NORESTART;
6820}
6821
19677e32
BD
6822/*
6823 * Decode the memory-address operand of a vmx instruction, as recorded on an
6824 * exit caused by such an instruction (run by a guest hypervisor).
6825 * On success, returns 0. When the operand is invalid, returns 1 and throws
6826 * #UD or #GP.
6827 */
6828static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6829 unsigned long exit_qualification,
f9eb4af6 6830 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6831{
f9eb4af6
EK
6832 gva_t off;
6833 bool exn;
6834 struct kvm_segment s;
6835
19677e32
BD
6836 /*
6837 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6838 * Execution", on an exit, vmx_instruction_info holds most of the
6839 * addressing components of the operand. Only the displacement part
6840 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6841 * For how an actual address is calculated from all these components,
6842 * refer to Vol. 1, "Operand Addressing".
6843 */
6844 int scaling = vmx_instruction_info & 3;
6845 int addr_size = (vmx_instruction_info >> 7) & 7;
6846 bool is_reg = vmx_instruction_info & (1u << 10);
6847 int seg_reg = (vmx_instruction_info >> 15) & 7;
6848 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6849 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6850 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6851 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6852
6853 if (is_reg) {
6854 kvm_queue_exception(vcpu, UD_VECTOR);
6855 return 1;
6856 }
6857
6858 /* Addr = segment_base + offset */
6859 /* offset = base + [index * scale] + displacement */
f9eb4af6 6860 off = exit_qualification; /* holds the displacement */
19677e32 6861 if (base_is_valid)
f9eb4af6 6862 off += kvm_register_read(vcpu, base_reg);
19677e32 6863 if (index_is_valid)
f9eb4af6
EK
6864 off += kvm_register_read(vcpu, index_reg)<<scaling;
6865 vmx_get_segment(vcpu, &s, seg_reg);
6866 *ret = s.base + off;
19677e32
BD
6867
6868 if (addr_size == 1) /* 32 bit */
6869 *ret &= 0xffffffff;
6870
f9eb4af6
EK
6871 /* Checks for #GP/#SS exceptions. */
6872 exn = false;
ff30ef40
QC
6873 if (is_long_mode(vcpu)) {
6874 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6875 * non-canonical form. This is the only check on the memory
6876 * destination for long mode!
6877 */
6878 exn = is_noncanonical_address(*ret);
6879 } else if (is_protmode(vcpu)) {
f9eb4af6
EK
6880 /* Protected mode: apply checks for segment validity in the
6881 * following order:
6882 * - segment type check (#GP(0) may be thrown)
6883 * - usability check (#GP(0)/#SS(0))
6884 * - limit check (#GP(0)/#SS(0))
6885 */
6886 if (wr)
6887 /* #GP(0) if the destination operand is located in a
6888 * read-only data segment or any code segment.
6889 */
6890 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6891 else
6892 /* #GP(0) if the source operand is located in an
6893 * execute-only code segment
6894 */
6895 exn = ((s.type & 0xa) == 8);
ff30ef40
QC
6896 if (exn) {
6897 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6898 return 1;
6899 }
f9eb4af6
EK
6900 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6901 */
6902 exn = (s.unusable != 0);
6903 /* Protected mode: #GP(0)/#SS(0) if the memory
6904 * operand is outside the segment limit.
6905 */
6906 exn = exn || (off + sizeof(u64) > s.limit);
6907 }
6908 if (exn) {
6909 kvm_queue_exception_e(vcpu,
6910 seg_reg == VCPU_SREG_SS ?
6911 SS_VECTOR : GP_VECTOR,
6912 0);
6913 return 1;
6914 }
6915
19677e32
BD
6916 return 0;
6917}
6918
cbf71279 6919static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
3573e22c
BD
6920{
6921 gva_t gva;
3573e22c 6922 struct x86_exception e;
3573e22c
BD
6923
6924 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 6925 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD
6926 return 1;
6927
cbf71279
RK
6928 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
6929 sizeof(*vmpointer), &e)) {
3573e22c
BD
6930 kvm_inject_page_fault(vcpu, &e);
6931 return 1;
6932 }
6933
3573e22c
BD
6934 return 0;
6935}
6936
e29acc55
JM
6937static int enter_vmx_operation(struct kvm_vcpu *vcpu)
6938{
6939 struct vcpu_vmx *vmx = to_vmx(vcpu);
6940 struct vmcs *shadow_vmcs;
6941
6942 if (cpu_has_vmx_msr_bitmap()) {
6943 vmx->nested.msr_bitmap =
6944 (unsigned long *)__get_free_page(GFP_KERNEL);
6945 if (!vmx->nested.msr_bitmap)
6946 goto out_msr_bitmap;
6947 }
6948
6949 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
6950 if (!vmx->nested.cached_vmcs12)
6951 goto out_cached_vmcs12;
6952
6953 if (enable_shadow_vmcs) {
6954 shadow_vmcs = alloc_vmcs();
6955 if (!shadow_vmcs)
6956 goto out_shadow_vmcs;
6957 /* mark vmcs as shadow */
6958 shadow_vmcs->revision_id |= (1u << 31);
6959 /* init shadow vmcs */
6960 vmcs_clear(shadow_vmcs);
6961 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
6962 }
6963
6964 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6965 vmx->nested.vmcs02_num = 0;
6966
6967 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6968 HRTIMER_MODE_REL_PINNED);
6969 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6970
6971 vmx->nested.vmxon = true;
6972 return 0;
6973
6974out_shadow_vmcs:
6975 kfree(vmx->nested.cached_vmcs12);
6976
6977out_cached_vmcs12:
6978 free_page((unsigned long)vmx->nested.msr_bitmap);
6979
6980out_msr_bitmap:
6981 return -ENOMEM;
6982}
6983
ec378aee
NHE
6984/*
6985 * Emulate the VMXON instruction.
6986 * Currently, we just remember that VMX is active, and do not save or even
6987 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6988 * do not currently need to store anything in that guest-allocated memory
6989 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6990 * argument is different from the VMXON pointer (which the spec says they do).
6991 */
6992static int handle_vmon(struct kvm_vcpu *vcpu)
6993{
e29acc55 6994 int ret;
cbf71279
RK
6995 gpa_t vmptr;
6996 struct page *page;
ec378aee 6997 struct vcpu_vmx *vmx = to_vmx(vcpu);
b3897a49
NHE
6998 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6999 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee 7000
70f3aac9
JM
7001 /*
7002 * The Intel VMX Instruction Reference lists a bunch of bits that are
7003 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7004 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7005 * Otherwise, we should fail with #UD. But most faulting conditions
7006 * have already been checked by hardware, prior to the VM-exit for
7007 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7008 * that bit set to 1 in non-root mode.
ec378aee 7009 */
70f3aac9 7010 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
ec378aee
NHE
7011 kvm_queue_exception(vcpu, UD_VECTOR);
7012 return 1;
7013 }
7014
145c28dd
AG
7015 if (vmx->nested.vmxon) {
7016 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6affcbed 7017 return kvm_skip_emulated_instruction(vcpu);
145c28dd 7018 }
b3897a49 7019
3b84080b 7020 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
b3897a49
NHE
7021 != VMXON_NEEDED_FEATURES) {
7022 kvm_inject_gp(vcpu, 0);
7023 return 1;
7024 }
7025
cbf71279 7026 if (nested_vmx_get_vmptr(vcpu, &vmptr))
21e7fbe7 7027 return 1;
cbf71279
RK
7028
7029 /*
7030 * SDM 3: 24.11.5
7031 * The first 4 bytes of VMXON region contain the supported
7032 * VMCS revision identifier
7033 *
7034 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7035 * which replaces physical address width with 32
7036 */
7037 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7038 nested_vmx_failInvalid(vcpu);
7039 return kvm_skip_emulated_instruction(vcpu);
7040 }
7041
7042 page = nested_get_page(vcpu, vmptr);
7043 if (page == NULL) {
7044 nested_vmx_failInvalid(vcpu);
7045 return kvm_skip_emulated_instruction(vcpu);
7046 }
7047 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7048 kunmap(page);
7049 nested_release_page_clean(page);
7050 nested_vmx_failInvalid(vcpu);
7051 return kvm_skip_emulated_instruction(vcpu);
7052 }
7053 kunmap(page);
7054 nested_release_page_clean(page);
7055
7056 vmx->nested.vmxon_ptr = vmptr;
e29acc55
JM
7057 ret = enter_vmx_operation(vcpu);
7058 if (ret)
7059 return ret;
ec378aee 7060
a25eb114 7061 nested_vmx_succeed(vcpu);
6affcbed 7062 return kvm_skip_emulated_instruction(vcpu);
ec378aee
NHE
7063}
7064
7065/*
7066 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7067 * for running VMX instructions (except VMXON, whose prerequisites are
7068 * slightly different). It also specifies what exception to inject otherwise.
70f3aac9
JM
7069 * Note that many of these exceptions have priority over VM exits, so they
7070 * don't have to be checked again here.
ec378aee
NHE
7071 */
7072static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7073{
70f3aac9 7074 if (!to_vmx(vcpu)->nested.vmxon) {
ec378aee
NHE
7075 kvm_queue_exception(vcpu, UD_VECTOR);
7076 return 0;
7077 }
ec378aee
NHE
7078 return 1;
7079}
7080
e7953d7f
AG
7081static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7082{
9a2a05b9
PB
7083 if (vmx->nested.current_vmptr == -1ull)
7084 return;
7085
7086 /* current_vmptr and current_vmcs12 are always set/reset together */
7087 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7088 return;
7089
012f83cb 7090 if (enable_shadow_vmcs) {
9a2a05b9
PB
7091 /* copy to memory all shadowed fields in case
7092 they were modified */
7093 copy_shadow_to_vmcs12(vmx);
7094 vmx->nested.sync_shadow_vmcs = false;
7ec36296
XG
7095 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7096 SECONDARY_EXEC_SHADOW_VMCS);
9a2a05b9 7097 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 7098 }
705699a1 7099 vmx->nested.posted_intr_nv = -1;
4f2777bc
DM
7100
7101 /* Flush VMCS12 to guest memory */
7102 memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7103 VMCS12_SIZE);
7104
e7953d7f
AG
7105 kunmap(vmx->nested.current_vmcs12_page);
7106 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB
7107 vmx->nested.current_vmptr = -1ull;
7108 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG
7109}
7110
ec378aee
NHE
7111/*
7112 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7113 * just stops using VMX.
7114 */
7115static void free_nested(struct vcpu_vmx *vmx)
7116{
7117 if (!vmx->nested.vmxon)
7118 return;
9a2a05b9 7119
ec378aee 7120 vmx->nested.vmxon = false;
5c614b35 7121 free_vpid(vmx->nested.vpid02);
9a2a05b9 7122 nested_release_vmcs12(vmx);
d048c098
RK
7123 if (vmx->nested.msr_bitmap) {
7124 free_page((unsigned long)vmx->nested.msr_bitmap);
7125 vmx->nested.msr_bitmap = NULL;
7126 }
355f4fb1
JM
7127 if (enable_shadow_vmcs) {
7128 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7129 free_vmcs(vmx->vmcs01.shadow_vmcs);
7130 vmx->vmcs01.shadow_vmcs = NULL;
7131 }
4f2777bc 7132 kfree(vmx->nested.cached_vmcs12);
fe3ef05c
NHE
7133 /* Unpin physical memory we referred to in current vmcs02 */
7134 if (vmx->nested.apic_access_page) {
7135 nested_release_page(vmx->nested.apic_access_page);
48d89b92 7136 vmx->nested.apic_access_page = NULL;
fe3ef05c 7137 }
a7c0b07d
WL
7138 if (vmx->nested.virtual_apic_page) {
7139 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 7140 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 7141 }
705699a1
WV
7142 if (vmx->nested.pi_desc_page) {
7143 kunmap(vmx->nested.pi_desc_page);
7144 nested_release_page(vmx->nested.pi_desc_page);
7145 vmx->nested.pi_desc_page = NULL;
7146 vmx->nested.pi_desc = NULL;
7147 }
ff2f6fe9
NHE
7148
7149 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE
7150}
7151
7152/* Emulate the VMXOFF instruction */
7153static int handle_vmoff(struct kvm_vcpu *vcpu)
7154{
7155 if (!nested_vmx_check_permission(vcpu))
7156 return 1;
7157 free_nested(to_vmx(vcpu));
a25eb114 7158 nested_vmx_succeed(vcpu);
6affcbed 7159 return kvm_skip_emulated_instruction(vcpu);
ec378aee
NHE
7160}
7161
27d6c865
NHE
7162/* Emulate the VMCLEAR instruction */
7163static int handle_vmclear(struct kvm_vcpu *vcpu)
7164{
7165 struct vcpu_vmx *vmx = to_vmx(vcpu);
587d7e72 7166 u32 zero = 0;
27d6c865 7167 gpa_t vmptr;
27d6c865
NHE
7168
7169 if (!nested_vmx_check_permission(vcpu))
7170 return 1;
7171
cbf71279 7172 if (nested_vmx_get_vmptr(vcpu, &vmptr))
27d6c865 7173 return 1;
27d6c865 7174
cbf71279
RK
7175 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7176 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7177 return kvm_skip_emulated_instruction(vcpu);
7178 }
7179
7180 if (vmptr == vmx->nested.vmxon_ptr) {
7181 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7182 return kvm_skip_emulated_instruction(vcpu);
7183 }
7184
9a2a05b9 7185 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 7186 nested_release_vmcs12(vmx);
27d6c865 7187
587d7e72
JM
7188 kvm_vcpu_write_guest(vcpu,
7189 vmptr + offsetof(struct vmcs12, launch_state),
7190 &zero, sizeof(zero));
27d6c865
NHE
7191
7192 nested_free_vmcs02(vmx, vmptr);
7193
27d6c865 7194 nested_vmx_succeed(vcpu);
6affcbed 7195 return kvm_skip_emulated_instruction(vcpu);
27d6c865
NHE
7196}
7197
cd232ad0
NHE
7198static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7199
7200/* Emulate the VMLAUNCH instruction */
7201static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7202{
7203 return nested_vmx_run(vcpu, true);
7204}
7205
7206/* Emulate the VMRESUME instruction */
7207static int handle_vmresume(struct kvm_vcpu *vcpu)
7208{
7209
7210 return nested_vmx_run(vcpu, false);
7211}
7212
49f705c5
NHE
7213enum vmcs_field_type {
7214 VMCS_FIELD_TYPE_U16 = 0,
7215 VMCS_FIELD_TYPE_U64 = 1,
7216 VMCS_FIELD_TYPE_U32 = 2,
7217 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7218};
7219
7220static inline int vmcs_field_type(unsigned long field)
7221{
7222 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
7223 return VMCS_FIELD_TYPE_U32;
7224 return (field >> 13) & 0x3 ;
7225}
7226
7227static inline int vmcs_field_readonly(unsigned long field)
7228{
7229 return (((field >> 10) & 0x3) == 1);
7230}
7231
7232/*
7233 * Read a vmcs12 field. Since these can have varying lengths and we return
7234 * one type, we chose the biggest type (u64) and zero-extend the return value
7235 * to that size. Note that the caller, handle_vmread, might need to use only
7236 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7237 * 64-bit fields are to be returned).
7238 */
a2ae9df7
PB
7239static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7240 unsigned long field, u64 *ret)
49f705c5
NHE
7241{
7242 short offset = vmcs_field_to_offset(field);
7243 char *p;
7244
7245 if (offset < 0)
a2ae9df7 7246 return offset;
49f705c5
NHE
7247
7248 p = ((char *)(get_vmcs12(vcpu))) + offset;
7249
7250 switch (vmcs_field_type(field)) {
7251 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7252 *ret = *((natural_width *)p);
a2ae9df7 7253 return 0;
49f705c5
NHE
7254 case VMCS_FIELD_TYPE_U16:
7255 *ret = *((u16 *)p);
a2ae9df7 7256 return 0;
49f705c5
NHE
7257 case VMCS_FIELD_TYPE_U32:
7258 *ret = *((u32 *)p);
a2ae9df7 7259 return 0;
49f705c5
NHE
7260 case VMCS_FIELD_TYPE_U64:
7261 *ret = *((u64 *)p);
a2ae9df7 7262 return 0;
49f705c5 7263 default:
a2ae9df7
PB
7264 WARN_ON(1);
7265 return -ENOENT;
49f705c5
NHE
7266 }
7267}
7268
20b97fea 7269
a2ae9df7
PB
7270static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7271 unsigned long field, u64 field_value){
20b97fea
AG
7272 short offset = vmcs_field_to_offset(field);
7273 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7274 if (offset < 0)
a2ae9df7 7275 return offset;
20b97fea
AG
7276
7277 switch (vmcs_field_type(field)) {
7278 case VMCS_FIELD_TYPE_U16:
7279 *(u16 *)p = field_value;
a2ae9df7 7280 return 0;
20b97fea
AG
7281 case VMCS_FIELD_TYPE_U32:
7282 *(u32 *)p = field_value;
a2ae9df7 7283 return 0;
20b97fea
AG
7284 case VMCS_FIELD_TYPE_U64:
7285 *(u64 *)p = field_value;
a2ae9df7 7286 return 0;
20b97fea
AG
7287 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7288 *(natural_width *)p = field_value;
a2ae9df7 7289 return 0;
20b97fea 7290 default:
a2ae9df7
PB
7291 WARN_ON(1);
7292 return -ENOENT;
20b97fea
AG
7293 }
7294
7295}
7296
16f5b903
AG
7297static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7298{
7299 int i;
7300 unsigned long field;
7301 u64 field_value;
355f4fb1 7302 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
c2bae893
MK
7303 const unsigned long *fields = shadow_read_write_fields;
7304 const int num_fields = max_shadow_read_write_fields;
16f5b903 7305
282da870
JK
7306 preempt_disable();
7307
16f5b903
AG
7308 vmcs_load(shadow_vmcs);
7309
7310 for (i = 0; i < num_fields; i++) {
7311 field = fields[i];
7312 switch (vmcs_field_type(field)) {
7313 case VMCS_FIELD_TYPE_U16:
7314 field_value = vmcs_read16(field);
7315 break;
7316 case VMCS_FIELD_TYPE_U32:
7317 field_value = vmcs_read32(field);
7318 break;
7319 case VMCS_FIELD_TYPE_U64:
7320 field_value = vmcs_read64(field);
7321 break;
7322 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7323 field_value = vmcs_readl(field);
7324 break;
a2ae9df7
PB
7325 default:
7326 WARN_ON(1);
7327 continue;
16f5b903
AG
7328 }
7329 vmcs12_write_any(&vmx->vcpu, field, field_value);
7330 }
7331
7332 vmcs_clear(shadow_vmcs);
7333 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK
7334
7335 preempt_enable();
16f5b903
AG
7336}
7337
c3114420
AG
7338static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7339{
c2bae893
MK
7340 const unsigned long *fields[] = {
7341 shadow_read_write_fields,
7342 shadow_read_only_fields
c3114420 7343 };
c2bae893 7344 const int max_fields[] = {
c3114420
AG
7345 max_shadow_read_write_fields,
7346 max_shadow_read_only_fields
7347 };
7348 int i, q;
7349 unsigned long field;
7350 u64 field_value = 0;
355f4fb1 7351 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
c3114420
AG
7352
7353 vmcs_load(shadow_vmcs);
7354
c2bae893 7355 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG
7356 for (i = 0; i < max_fields[q]; i++) {
7357 field = fields[q][i];
7358 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7359
7360 switch (vmcs_field_type(field)) {
7361 case VMCS_FIELD_TYPE_U16:
7362 vmcs_write16(field, (u16)field_value);
7363 break;
7364 case VMCS_FIELD_TYPE_U32:
7365 vmcs_write32(field, (u32)field_value);
7366 break;
7367 case VMCS_FIELD_TYPE_U64:
7368 vmcs_write64(field, (u64)field_value);
7369 break;
7370 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7371 vmcs_writel(field, (long)field_value);
7372 break;
a2ae9df7
PB
7373 default:
7374 WARN_ON(1);
7375 break;
c3114420
AG
7376 }
7377 }
7378 }
7379
7380 vmcs_clear(shadow_vmcs);
7381 vmcs_load(vmx->loaded_vmcs->vmcs);
7382}
7383
49f705c5
NHE
7384/*
7385 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7386 * used before) all generate the same failure when it is missing.
7387 */
7388static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7389{
7390 struct vcpu_vmx *vmx = to_vmx(vcpu);
7391 if (vmx->nested.current_vmptr == -1ull) {
7392 nested_vmx_failInvalid(vcpu);
49f705c5
NHE
7393 return 0;
7394 }
7395 return 1;
7396}
7397
7398static int handle_vmread(struct kvm_vcpu *vcpu)
7399{
7400 unsigned long field;
7401 u64 field_value;
7402 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7403 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7404 gva_t gva = 0;
7405
eb277562 7406 if (!nested_vmx_check_permission(vcpu))
49f705c5
NHE
7407 return 1;
7408
6affcbed
KH
7409 if (!nested_vmx_check_vmcs12(vcpu))
7410 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7411
7412 /* Decode instruction info and find the field to read */
27e6fb5d 7413 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 7414 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 7415 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5 7416 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6affcbed 7417 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7418 }
7419 /*
7420 * Now copy part of this value to register or memory, as requested.
7421 * Note that the number of bits actually copied is 32 or 64 depending
7422 * on the guest's mode (32 or 64 bit), not on the given field's length.
7423 */
7424 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 7425 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE
7426 field_value);
7427 } else {
7428 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7429 vmx_instruction_info, true, &gva))
49f705c5 7430 return 1;
70f3aac9 7431 /* _system ok, as hardware has verified cpl=0 */
49f705c5
NHE
7432 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7433 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7434 }
7435
7436 nested_vmx_succeed(vcpu);
6affcbed 7437 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7438}
7439
7440
7441static int handle_vmwrite(struct kvm_vcpu *vcpu)
7442{
7443 unsigned long field;
7444 gva_t gva;
7445 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7446 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE
7447 /* The value to write might be 32 or 64 bits, depending on L1's long
7448 * mode, and eventually we need to write that into a field of several
7449 * possible lengths. The code below first zero-extends the value to 64
6a6256f9 7450 * bit (field_value), and then copies only the appropriate number of
49f705c5
NHE
7451 * bits into the vmcs12 field.
7452 */
7453 u64 field_value = 0;
7454 struct x86_exception e;
7455
eb277562 7456 if (!nested_vmx_check_permission(vcpu))
49f705c5
NHE
7457 return 1;
7458
6affcbed
KH
7459 if (!nested_vmx_check_vmcs12(vcpu))
7460 return kvm_skip_emulated_instruction(vcpu);
eb277562 7461
49f705c5 7462 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7463 field_value = kvm_register_readl(vcpu,
49f705c5
NHE
7464 (((vmx_instruction_info) >> 3) & 0xf));
7465 else {
7466 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7467 vmx_instruction_info, false, &gva))
49f705c5
NHE
7468 return 1;
7469 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7470 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE
7471 kvm_inject_page_fault(vcpu, &e);
7472 return 1;
7473 }
7474 }
7475
7476
27e6fb5d 7477 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE
7478 if (vmcs_field_readonly(field)) {
7479 nested_vmx_failValid(vcpu,
7480 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6affcbed 7481 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7482 }
7483
a2ae9df7 7484 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5 7485 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6affcbed 7486 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7487 }
7488
7489 nested_vmx_succeed(vcpu);
6affcbed 7490 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7491}
7492
a8bc284e
JM
7493static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7494{
7495 vmx->nested.current_vmptr = vmptr;
7496 if (enable_shadow_vmcs) {
7497 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7498 SECONDARY_EXEC_SHADOW_VMCS);
7499 vmcs_write64(VMCS_LINK_POINTER,
7500 __pa(vmx->vmcs01.shadow_vmcs));
7501 vmx->nested.sync_shadow_vmcs = true;
7502 }
7503}
7504
63846663
NHE
7505/* Emulate the VMPTRLD instruction */
7506static int handle_vmptrld(struct kvm_vcpu *vcpu)
7507{
7508 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7509 gpa_t vmptr;
63846663
NHE
7510
7511 if (!nested_vmx_check_permission(vcpu))
7512 return 1;
7513
cbf71279 7514 if (nested_vmx_get_vmptr(vcpu, &vmptr))
63846663 7515 return 1;
63846663 7516
cbf71279
RK
7517 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7518 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7519 return kvm_skip_emulated_instruction(vcpu);
7520 }
7521
7522 if (vmptr == vmx->nested.vmxon_ptr) {
7523 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7524 return kvm_skip_emulated_instruction(vcpu);
7525 }
7526
63846663
NHE
7527 if (vmx->nested.current_vmptr != vmptr) {
7528 struct vmcs12 *new_vmcs12;
7529 struct page *page;
7530 page = nested_get_page(vcpu, vmptr);
7531 if (page == NULL) {
7532 nested_vmx_failInvalid(vcpu);
6affcbed 7533 return kvm_skip_emulated_instruction(vcpu);
63846663
NHE
7534 }
7535 new_vmcs12 = kmap(page);
7536 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7537 kunmap(page);
7538 nested_release_page_clean(page);
7539 nested_vmx_failValid(vcpu,
7540 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6affcbed 7541 return kvm_skip_emulated_instruction(vcpu);
63846663 7542 }
63846663 7543
9a2a05b9 7544 nested_release_vmcs12(vmx);
63846663
NHE
7545 vmx->nested.current_vmcs12 = new_vmcs12;
7546 vmx->nested.current_vmcs12_page = page;
4f2777bc
DM
7547 /*
7548 * Load VMCS12 from guest memory since it is not already
7549 * cached.
7550 */
7551 memcpy(vmx->nested.cached_vmcs12,
7552 vmx->nested.current_vmcs12, VMCS12_SIZE);
a8bc284e 7553 set_current_vmptr(vmx, vmptr);
63846663
NHE
7554 }
7555
7556 nested_vmx_succeed(vcpu);
6affcbed 7557 return kvm_skip_emulated_instruction(vcpu);
63846663
NHE
7558}
7559
6a4d7550
NHE
7560/* Emulate the VMPTRST instruction */
7561static int handle_vmptrst(struct kvm_vcpu *vcpu)
7562{
7563 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7564 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7565 gva_t vmcs_gva;
7566 struct x86_exception e;
7567
7568 if (!nested_vmx_check_permission(vcpu))
7569 return 1;
7570
7571 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7572 vmx_instruction_info, true, &vmcs_gva))
6a4d7550 7573 return 1;
70f3aac9 7574 /* ok to use *_system, as hardware has verified cpl=0 */
6a4d7550
NHE
7575 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7576 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7577 sizeof(u64), &e)) {
7578 kvm_inject_page_fault(vcpu, &e);
7579 return 1;
7580 }
7581 nested_vmx_succeed(vcpu);
6affcbed 7582 return kvm_skip_emulated_instruction(vcpu);
6a4d7550
NHE
7583}
7584
bfd0a56b
NHE
7585/* Emulate the INVEPT instruction */
7586static int handle_invept(struct kvm_vcpu *vcpu)
7587{
b9c237bb 7588 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE
7589 u32 vmx_instruction_info, types;
7590 unsigned long type;
7591 gva_t gva;
7592 struct x86_exception e;
7593 struct {
7594 u64 eptp, gpa;
7595 } operand;
bfd0a56b 7596
b9c237bb
WV
7597 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7598 SECONDARY_EXEC_ENABLE_EPT) ||
7599 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE
7600 kvm_queue_exception(vcpu, UD_VECTOR);
7601 return 1;
7602 }
7603
7604 if (!nested_vmx_check_permission(vcpu))
7605 return 1;
7606
bfd0a56b 7607 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7608 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7609
b9c237bb 7610 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b 7611
85c856b3 7612 if (type >= 32 || !(types & (1 << type))) {
bfd0a56b
NHE
7613 nested_vmx_failValid(vcpu,
7614 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7615 return kvm_skip_emulated_instruction(vcpu);
bfd0a56b
NHE
7616 }
7617
7618 /* According to the Intel VMX instruction reference, the memory
7619 * operand is read even if it isn't needed (e.g., for type==global)
7620 */
7621 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7622 vmx_instruction_info, false, &gva))
bfd0a56b
NHE
7623 return 1;
7624 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7625 sizeof(operand), &e)) {
7626 kvm_inject_page_fault(vcpu, &e);
7627 return 1;
7628 }
7629
7630 switch (type) {
bfd0a56b 7631 case VMX_EPT_EXTENT_GLOBAL:
45e11817
BD
7632 /*
7633 * TODO: track mappings and invalidate
7634 * single context requests appropriately
7635 */
7636 case VMX_EPT_EXTENT_CONTEXT:
bfd0a56b 7637 kvm_mmu_sync_roots(vcpu);
77c3913b 7638 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE
7639 nested_vmx_succeed(vcpu);
7640 break;
7641 default:
7642 BUG_ON(1);
7643 break;
7644 }
7645
6affcbed 7646 return kvm_skip_emulated_instruction(vcpu);
bfd0a56b
NHE
7647}
7648
a642fc30
PM
7649static int handle_invvpid(struct kvm_vcpu *vcpu)
7650{
99b83ac8
WL
7651 struct vcpu_vmx *vmx = to_vmx(vcpu);
7652 u32 vmx_instruction_info;
7653 unsigned long type, types;
7654 gva_t gva;
7655 struct x86_exception e;
7656 int vpid;
7657
7658 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7659 SECONDARY_EXEC_ENABLE_VPID) ||
7660 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7661 kvm_queue_exception(vcpu, UD_VECTOR);
7662 return 1;
7663 }
7664
7665 if (!nested_vmx_check_permission(vcpu))
7666 return 1;
7667
7668 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7669 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7670
bcdde302
JD
7671 types = (vmx->nested.nested_vmx_vpid_caps &
7672 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
99b83ac8 7673
85c856b3 7674 if (type >= 32 || !(types & (1 << type))) {
99b83ac8
WL
7675 nested_vmx_failValid(vcpu,
7676 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7677 return kvm_skip_emulated_instruction(vcpu);
99b83ac8
WL
7678 }
7679
7680 /* according to the intel vmx instruction reference, the memory
7681 * operand is read even if it isn't needed (e.g., for type==global)
7682 */
7683 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7684 vmx_instruction_info, false, &gva))
7685 return 1;
7686 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7687 sizeof(u32), &e)) {
7688 kvm_inject_page_fault(vcpu, &e);
7689 return 1;
7690 }
7691
7692 switch (type) {
bcdde302 7693 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
ef697a71 7694 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
bcdde302
JD
7695 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7696 if (!vpid) {
7697 nested_vmx_failValid(vcpu,
7698 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7699 return kvm_skip_emulated_instruction(vcpu);
bcdde302
JD
7700 }
7701 break;
99b83ac8 7702 case VMX_VPID_EXTENT_ALL_CONTEXT:
99b83ac8
WL
7703 break;
7704 default:
bcdde302 7705 WARN_ON_ONCE(1);
6affcbed 7706 return kvm_skip_emulated_instruction(vcpu);
99b83ac8
WL
7707 }
7708
bcdde302
JD
7709 __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7710 nested_vmx_succeed(vcpu);
7711
6affcbed 7712 return kvm_skip_emulated_instruction(vcpu);
a642fc30
PM
7713}
7714
843e4330
KH
7715static int handle_pml_full(struct kvm_vcpu *vcpu)
7716{
7717 unsigned long exit_qualification;
7718
7719 trace_kvm_pml_full(vcpu->vcpu_id);
7720
7721 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7722
7723 /*
7724 * PML buffer FULL happened while executing iret from NMI,
7725 * "blocked by NMI" bit has to be set before next VM entry.
7726 */
7727 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
843e4330
KH
7728 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7729 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7730 GUEST_INTR_STATE_NMI);
7731
7732 /*
7733 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7734 * here.., and there's no userspace involvement needed for PML.
7735 */
7736 return 1;
7737}
7738
64672c95
YJ
7739static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7740{
7741 kvm_lapic_expired_hv_timer(vcpu);
7742 return 1;
7743}
7744
6aa8b732
AK
7745/*
7746 * The exit handlers return 1 if the exit was handled fully and guest execution
7747 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7748 * to be done to userspace and return 0.
7749 */
772e0318 7750static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK
7751 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7752 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7753 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7754 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7755 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK
7756 [EXIT_REASON_CR_ACCESS] = handle_cr,
7757 [EXIT_REASON_DR_ACCESS] = handle_dr,
7758 [EXIT_REASON_CPUID] = handle_cpuid,
7759 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7760 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7761 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7762 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7763 [EXIT_REASON_INVD] = handle_invd,
a7052897 7764 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7765 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7766 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7767 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7768 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7769 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7770 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7771 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7772 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7773 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE
7774 [EXIT_REASON_VMOFF] = handle_vmoff,
7775 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY
7776 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7777 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7778 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7779 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7780 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7781 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7782 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7783 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT
7784 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7785 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7786 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7787 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7788 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7789 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7790 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7791 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL
7792 [EXIT_REASON_XSAVES] = handle_xsaves,
7793 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7794 [EXIT_REASON_PML_FULL] = handle_pml_full,
64672c95 7795 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
6aa8b732
AK
7796};
7797
7798static const int kvm_vmx_max_exit_handlers =
50a3485c 7799 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7800
908a7bdd
JK
7801static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7802 struct vmcs12 *vmcs12)
7803{
7804 unsigned long exit_qualification;
7805 gpa_t bitmap, last_bitmap;
7806 unsigned int port;
7807 int size;
7808 u8 b;
7809
908a7bdd 7810 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7811 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK
7812
7813 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7814
7815 port = exit_qualification >> 16;
7816 size = (exit_qualification & 7) + 1;
7817
7818 last_bitmap = (gpa_t)-1;
7819 b = -1;
7820
7821 while (size > 0) {
7822 if (port < 0x8000)
7823 bitmap = vmcs12->io_bitmap_a;
7824 else if (port < 0x10000)
7825 bitmap = vmcs12->io_bitmap_b;
7826 else
1d804d07 7827 return true;
908a7bdd
JK
7828 bitmap += (port & 0x7fff) / 8;
7829
7830 if (last_bitmap != bitmap)
54bf36aa 7831 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7832 return true;
908a7bdd 7833 if (b & (1 << (port & 7)))
1d804d07 7834 return true;
908a7bdd
JK
7835
7836 port++;
7837 size--;
7838 last_bitmap = bitmap;
7839 }
7840
1d804d07 7841 return false;
908a7bdd
JK
7842}
7843
644d711a
NHE
7844/*
7845 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7846 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7847 * disinterest in the current event (read or write a specific MSR) by using an
7848 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7849 */
7850static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7851 struct vmcs12 *vmcs12, u32 exit_reason)
7852{
7853 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7854 gpa_t bitmap;
7855
cbd29cb6 7856 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7857 return true;
644d711a
NHE
7858
7859 /*
7860 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7861 * for the four combinations of read/write and low/high MSR numbers.
7862 * First we need to figure out which of the four to use:
7863 */
7864 bitmap = vmcs12->msr_bitmap;
7865 if (exit_reason == EXIT_REASON_MSR_WRITE)
7866 bitmap += 2048;
7867 if (msr_index >= 0xc0000000) {
7868 msr_index -= 0xc0000000;
7869 bitmap += 1024;
7870 }
7871
7872 /* Then read the msr_index'th bit from this bitmap: */
7873 if (msr_index < 1024*8) {
7874 unsigned char b;
54bf36aa 7875 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7876 return true;
644d711a
NHE
7877 return 1 & (b >> (msr_index & 7));
7878 } else
1d804d07 7879 return true; /* let L1 handle the wrong parameter */
644d711a
NHE
7880}
7881
7882/*
7883 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7884 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7885 * intercept (via guest_host_mask etc.) the current event.
7886 */
7887static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7888 struct vmcs12 *vmcs12)
7889{
7890 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7891 int cr = exit_qualification & 15;
e1d39b17
JS
7892 int reg;
7893 unsigned long val;
644d711a
NHE
7894
7895 switch ((exit_qualification >> 4) & 3) {
7896 case 0: /* mov to cr */
e1d39b17
JS
7897 reg = (exit_qualification >> 8) & 15;
7898 val = kvm_register_readl(vcpu, reg);
644d711a
NHE
7899 switch (cr) {
7900 case 0:
7901 if (vmcs12->cr0_guest_host_mask &
7902 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7903 return true;
644d711a
NHE
7904 break;
7905 case 3:
7906 if ((vmcs12->cr3_target_count >= 1 &&
7907 vmcs12->cr3_target_value0 == val) ||
7908 (vmcs12->cr3_target_count >= 2 &&
7909 vmcs12->cr3_target_value1 == val) ||
7910 (vmcs12->cr3_target_count >= 3 &&
7911 vmcs12->cr3_target_value2 == val) ||
7912 (vmcs12->cr3_target_count >= 4 &&
7913 vmcs12->cr3_target_value3 == val))
1d804d07 7914 return false;
644d711a 7915 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7916 return true;
644d711a
NHE
7917 break;
7918 case 4:
7919 if (vmcs12->cr4_guest_host_mask &
7920 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7921 return true;
644d711a
NHE
7922 break;
7923 case 8:
7924 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7925 return true;
644d711a
NHE
7926 break;
7927 }
7928 break;
7929 case 2: /* clts */
7930 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7931 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7932 return true;
644d711a
NHE
7933 break;
7934 case 1: /* mov from cr */
7935 switch (cr) {
7936 case 3:
7937 if (vmcs12->cpu_based_vm_exec_control &
7938 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7939 return true;
644d711a
NHE
7940 break;
7941 case 8:
7942 if (vmcs12->cpu_based_vm_exec_control &
7943 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7944 return true;
644d711a
NHE
7945 break;
7946 }
7947 break;
7948 case 3: /* lmsw */
7949 /*
7950 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7951 * cr0. Other attempted changes are ignored, with no exit.
7952 */
e1d39b17 7953 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
644d711a
NHE
7954 if (vmcs12->cr0_guest_host_mask & 0xe &
7955 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7956 return true;
644d711a
NHE
7957 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7958 !(vmcs12->cr0_read_shadow & 0x1) &&
7959 (val & 0x1))
1d804d07 7960 return true;
644d711a
NHE
7961 break;
7962 }
1d804d07 7963 return false;
644d711a
NHE
7964}
7965
7966/*
7967 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7968 * should handle it ourselves in L0 (and then continue L2). Only call this
7969 * when in is_guest_mode (L2).
7970 */
7971static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7972{
644d711a
NHE
7973 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7974 struct vcpu_vmx *vmx = to_vmx(vcpu);
7975 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7976 u32 exit_reason = vmx->exit_reason;
644d711a 7977
542060ea
JK
7978 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7979 vmcs_readl(EXIT_QUALIFICATION),
7980 vmx->idt_vectoring_info,
7981 intr_info,
7982 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7983 KVM_ISA_VMX);
7984
644d711a 7985 if (vmx->nested.nested_run_pending)
1d804d07 7986 return false;
644d711a
NHE
7987
7988 if (unlikely(vmx->fail)) {
bd80158a
JK
7989 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7990 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 7991 return true;
644d711a
NHE
7992 }
7993
7994 switch (exit_reason) {
7995 case EXIT_REASON_EXCEPTION_NMI:
ef85b673 7996 if (is_nmi(intr_info))
1d804d07 7997 return false;
644d711a
NHE
7998 else if (is_page_fault(intr_info))
7999 return enable_ept;
e504c909 8000 else if (is_no_device(intr_info) &&
ccf9844e 8001 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 8002 return false;
6f05485d
JK
8003 else if (is_debug(intr_info) &&
8004 vcpu->guest_debug &
8005 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8006 return false;
8007 else if (is_breakpoint(intr_info) &&
8008 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8009 return false;
644d711a
NHE
8010 return vmcs12->exception_bitmap &
8011 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8012 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 8013 return false;
644d711a 8014 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 8015 return true;
644d711a 8016 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 8017 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 8018 case EXIT_REASON_NMI_WINDOW:
3b656cf7 8019 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 8020 case EXIT_REASON_TASK_SWITCH:
1d804d07 8021 return true;
644d711a 8022 case EXIT_REASON_CPUID:
1d804d07 8023 return true;
644d711a
NHE
8024 case EXIT_REASON_HLT:
8025 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8026 case EXIT_REASON_INVD:
1d804d07 8027 return true;
644d711a
NHE
8028 case EXIT_REASON_INVLPG:
8029 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8030 case EXIT_REASON_RDPMC:
8031 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
a5f46457
PB
8032 case EXIT_REASON_RDRAND:
8033 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8034 case EXIT_REASON_RDSEED:
8035 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
b3a2a907 8036 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE
8037 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8038 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8039 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8040 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8041 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8042 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 8043 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE
8044 /*
8045 * VMX instructions trap unconditionally. This allows L1 to
8046 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8047 */
1d804d07 8048 return true;
644d711a
NHE
8049 case EXIT_REASON_CR_ACCESS:
8050 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8051 case EXIT_REASON_DR_ACCESS:
8052 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8053 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 8054 return nested_vmx_exit_handled_io(vcpu, vmcs12);
1b07304c
PB
8055 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8056 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
644d711a
NHE
8057 case EXIT_REASON_MSR_READ:
8058 case EXIT_REASON_MSR_WRITE:
8059 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8060 case EXIT_REASON_INVALID_STATE:
1d804d07 8061 return true;
644d711a
NHE
8062 case EXIT_REASON_MWAIT_INSTRUCTION:
8063 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD
8064 case EXIT_REASON_MONITOR_TRAP_FLAG:
8065 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE
8066 case EXIT_REASON_MONITOR_INSTRUCTION:
8067 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8068 case EXIT_REASON_PAUSE_INSTRUCTION:
8069 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8070 nested_cpu_has2(vmcs12,
8071 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8072 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 8073 return false;
644d711a 8074 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 8075 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE
8076 case EXIT_REASON_APIC_ACCESS:
8077 return nested_cpu_has2(vmcs12,
8078 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 8079 case EXIT_REASON_APIC_WRITE:
608406e2
WV
8080 case EXIT_REASON_EOI_INDUCED:
8081 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 8082 return true;
644d711a 8083 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE
8084 /*
8085 * L0 always deals with the EPT violation. If nested EPT is
8086 * used, and the nested mmu code discovers that the address is
8087 * missing in the guest EPT table (EPT12), the EPT violation
8088 * will be injected with nested_ept_inject_page_fault()
8089 */
1d804d07 8090 return false;
644d711a 8091 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE
8092 /*
8093 * L2 never uses directly L1's EPT, but rather L0's own EPT
8094 * table (shadow on EPT) or a merged EPT table that L0 built
8095 * (EPT on EPT). So any problems with the structure of the
8096 * table is L0's fault.
8097 */
1d804d07 8098 return false;
644d711a
NHE
8099 case EXIT_REASON_WBINVD:
8100 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8101 case EXIT_REASON_XSETBV:
1d804d07 8102 return true;
81dc01f7
WL
8103 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8104 /*
8105 * This should never happen, since it is not possible to
8106 * set XSS to a non-zero value---neither in L1 nor in L2.
8107 * If if it were, XSS would have to be checked against
8108 * the XSS exit bitmap in vmcs12.
8109 */
8110 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
55123e3c
WL
8111 case EXIT_REASON_PREEMPTION_TIMER:
8112 return false;
ab007cc9 8113 case EXIT_REASON_PML_FULL:
03efce6f 8114 /* We emulate PML support to L1. */
ab007cc9 8115 return false;
644d711a 8116 default:
1d804d07 8117 return true;
644d711a
NHE
8118 }
8119}
8120
586f9607
AK
8121static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8122{
8123 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8124 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8125}
8126
a3eaa864 8127static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
843e4330 8128{
a3eaa864
KH
8129 if (vmx->pml_pg) {
8130 __free_page(vmx->pml_pg);
8131 vmx->pml_pg = NULL;
8132 }
843e4330
KH
8133}
8134
54bf36aa 8135static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 8136{
54bf36aa 8137 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH
8138 u64 *pml_buf;
8139 u16 pml_idx;
8140
8141 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8142
8143 /* Do nothing if PML buffer is empty */
8144 if (pml_idx == (PML_ENTITY_NUM - 1))
8145 return;
8146
8147 /* PML index always points to next available PML buffer entity */
8148 if (pml_idx >= PML_ENTITY_NUM)
8149 pml_idx = 0;
8150 else
8151 pml_idx++;
8152
8153 pml_buf = page_address(vmx->pml_pg);
8154 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8155 u64 gpa;
8156
8157 gpa = pml_buf[pml_idx];
8158 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 8159 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH
8160 }
8161
8162 /* reset PML index */
8163 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8164}
8165
8166/*
8167 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8168 * Called before reporting dirty_bitmap to userspace.
8169 */
8170static void kvm_flush_pml_buffers(struct kvm *kvm)
8171{
8172 int i;
8173 struct kvm_vcpu *vcpu;
8174 /*
8175 * We only need to kick vcpu out of guest mode here, as PML buffer
8176 * is flushed at beginning of all VMEXITs, and it's obvious that only
8177 * vcpus running in guest are possible to have unflushed GPAs in PML
8178 * buffer.
8179 */
8180 kvm_for_each_vcpu(i, vcpu, kvm)
8181 kvm_vcpu_kick(vcpu);
8182}
8183
4eb64dce
PB
8184static void vmx_dump_sel(char *name, uint32_t sel)
8185{
8186 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
96794e4e 8187 name, vmcs_read16(sel),
4eb64dce
PB
8188 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8189 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8190 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8191}
8192
8193static void vmx_dump_dtsel(char *name, uint32_t limit)
8194{
8195 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8196 name, vmcs_read32(limit),
8197 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8198}
8199
8200static void dump_vmcs(void)
8201{
8202 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8203 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8204 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8205 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8206 u32 secondary_exec_control = 0;
8207 unsigned long cr4 = vmcs_readl(GUEST_CR4);
f3531054 8208 u64 efer = vmcs_read64(GUEST_IA32_EFER);
4eb64dce
PB
8209 int i, n;
8210
8211 if (cpu_has_secondary_exec_ctrls())
8212 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8213
8214 pr_err("*** Guest State ***\n");
8215 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8216 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8217 vmcs_readl(CR0_GUEST_HOST_MASK));
8218 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8219 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8220 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8221 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8222 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8223 {
845c5b40
PB
8224 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8225 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8226 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8227 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
4eb64dce
PB
8228 }
8229 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8230 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8231 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8232 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8233 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8234 vmcs_readl(GUEST_SYSENTER_ESP),
8235 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8236 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8237 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8238 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8239 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8240 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8241 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8242 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8243 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8244 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8245 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8246 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8247 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
845c5b40
PB
8248 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8249 efer, vmcs_read64(GUEST_IA32_PAT));
8250 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8251 vmcs_read64(GUEST_IA32_DEBUGCTL),
4eb64dce
PB
8252 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8253 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
845c5b40
PB
8254 pr_err("PerfGlobCtl = 0x%016llx\n",
8255 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
4eb64dce 8256 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
845c5b40 8257 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
4eb64dce
PB
8258 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8259 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8260 vmcs_read32(GUEST_ACTIVITY_STATE));
8261 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8262 pr_err("InterruptStatus = %04x\n",
8263 vmcs_read16(GUEST_INTR_STATUS));
8264
8265 pr_err("*** Host State ***\n");
8266 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8267 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8268 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8269 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8270 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8271 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8272 vmcs_read16(HOST_TR_SELECTOR));
8273 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8274 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8275 vmcs_readl(HOST_TR_BASE));
8276 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8277 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8278 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8279 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8280 vmcs_readl(HOST_CR4));
8281 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8282 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8283 vmcs_read32(HOST_IA32_SYSENTER_CS),
8284 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8285 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
845c5b40
PB
8286 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8287 vmcs_read64(HOST_IA32_EFER),
8288 vmcs_read64(HOST_IA32_PAT));
4eb64dce 8289 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
845c5b40
PB
8290 pr_err("PerfGlobCtl = 0x%016llx\n",
8291 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
4eb64dce
PB
8292
8293 pr_err("*** Control State ***\n");
8294 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8295 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8296 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8297 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8298 vmcs_read32(EXCEPTION_BITMAP),
8299 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8300 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8301 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8302 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8303 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8304 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8305 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8306 vmcs_read32(VM_EXIT_INTR_INFO),
8307 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8308 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8309 pr_err(" reason=%08x qualification=%016lx\n",
8310 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8311 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8312 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8313 vmcs_read32(IDT_VECTORING_ERROR_CODE));
845c5b40 8314 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8cfe9866 8315 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
845c5b40
PB
8316 pr_err("TSC Multiplier = 0x%016llx\n",
8317 vmcs_read64(TSC_MULTIPLIER));
4eb64dce
PB
8318 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8319 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8320 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8321 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8322 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
845c5b40 8323 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
4eb64dce
PB
8324 n = vmcs_read32(CR3_TARGET_COUNT);
8325 for (i = 0; i + 1 < n; i += 4)
8326 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8327 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8328 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8329 if (i < n)
8330 pr_err("CR3 target%u=%016lx\n",
8331 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8332 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8333 pr_err("PLE Gap=%08x Window=%08x\n",
8334 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8335 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8336 pr_err("Virtual processor ID = 0x%04x\n",
8337 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8338}
8339
6aa8b732
AK
8340/*
8341 * The guest has exited. See if we can fix it or if we need userspace
8342 * assistance.
8343 */
851ba692 8344static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 8345{
29bd8a78 8346 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 8347 u32 exit_reason = vmx->exit_reason;
1155f76a 8348 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 8349
8b89fe1f 8350 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
db1c056c 8351 vcpu->arch.gpa_available = false;
8b89fe1f 8352
843e4330
KH
8353 /*
8354 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8355 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8356 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8357 * mode as if vcpus is in root mode, the PML buffer must has been
8358 * flushed already.
8359 */
8360 if (enable_pml)
54bf36aa 8361 vmx_flush_pml_buffer(vcpu);
843e4330 8362
80ced186 8363 /* If guest state is invalid, start emulating */
14168786 8364 if (vmx->emulation_required)
80ced186 8365 return handle_invalid_guest_state(vcpu);
1d5a4d9b 8366
644d711a 8367 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK
8368 nested_vmx_vmexit(vcpu, exit_reason,
8369 vmcs_read32(VM_EXIT_INTR_INFO),
8370 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE
8371 return 1;
8372 }
8373
5120702e 8374 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 8375 dump_vmcs();
5120702e
MG
8376 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8377 vcpu->run->fail_entry.hardware_entry_failure_reason
8378 = exit_reason;
8379 return 0;
8380 }
8381
29bd8a78 8382 if (unlikely(vmx->fail)) {
851ba692
AK
8383 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8384 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK
8385 = vmcs_read32(VM_INSTRUCTION_ERROR);
8386 return 0;
8387 }
6aa8b732 8388
b9bf6882
XG
8389 /*
8390 * Note:
8391 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8392 * delivery event since it indicates guest is accessing MMIO.
8393 * The vm-exit can be triggered again after return to guest that
8394 * will cause infinite loop.
8395 */
d77c26fc 8396 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 8397 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 8398 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b244c9fc 8399 exit_reason != EXIT_REASON_PML_FULL &&
b9bf6882
XG
8400 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8401 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8402 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8403 vcpu->run->internal.ndata = 2;
8404 vcpu->run->internal.data[0] = vectoring_info;
8405 vcpu->run->internal.data[1] = exit_reason;
8406 return 0;
8407 }
3b86cd99 8408
6aa8b732
AK
8409 if (exit_reason < kvm_vmx_max_exit_handlers
8410 && kvm_vmx_exit_handlers[exit_reason])
851ba692 8411 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 8412 else {
6c6c5e03
RK
8413 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8414 exit_reason);
2bc19dc3
MT
8415 kvm_queue_exception(vcpu, UD_VECTOR);
8416 return 1;
6aa8b732 8417 }
6aa8b732
AK
8418}
8419
95ba8273 8420static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 8421{
a7c0b07d
WL
8422 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8423
8424 if (is_guest_mode(vcpu) &&
8425 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8426 return;
8427
95ba8273 8428 if (irr == -1 || tpr < irr) {
6e5d865c
YS
8429 vmcs_write32(TPR_THRESHOLD, 0);
8430 return;
8431 }
8432
95ba8273 8433 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS
8434}
8435
8d14695f
YZ
8436static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8437{
8438 u32 sec_exec_control;
8439
dccbfcf5
RK
8440 /* Postpone execution until vmcs01 is the current VMCS. */
8441 if (is_guest_mode(vcpu)) {
8442 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8443 return;
8444 }
8445
f6e90f9e 8446 if (!cpu_has_vmx_virtualize_x2apic_mode())
8d14695f
YZ
8447 return;
8448
35754c98 8449 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ
8450 return;
8451
8452 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8453
8454 if (set) {
8455 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8456 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8457 } else {
8458 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8459 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
fb6c8198 8460 vmx_flush_tlb_ept_only(vcpu);
8d14695f
YZ
8461 }
8462 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8463
8464 vmx_set_msr_bitmap(vcpu);
8465}
8466
38b99173
TC
8467static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8468{
8469 struct vcpu_vmx *vmx = to_vmx(vcpu);
8470
8471 /*
8472 * Currently we do not handle the nested case where L2 has an
8473 * APIC access page of its own; that page is still pinned.
8474 * Hence, we skip the case where the VCPU is in guest mode _and_
8475 * L1 prepared an APIC access page for L2.
8476 *
8477 * For the case where L1 and L2 share the same APIC access page
8478 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8479 * in the vmcs12), this function will only update either the vmcs01
8480 * or the vmcs02. If the former, the vmcs02 will be updated by
8481 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8482 * the next L2->L1 exit.
8483 */
8484 if (!is_guest_mode(vcpu) ||
4f2777bc 8485 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
fb6c8198 8486 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
38b99173 8487 vmcs_write64(APIC_ACCESS_ADDR, hpa);
fb6c8198
JM
8488 vmx_flush_tlb_ept_only(vcpu);
8489 }
38b99173
TC
8490}
8491
67c9dddc 8492static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
c7c9c56c
YZ
8493{
8494 u16 status;
8495 u8 old;
8496
67c9dddc
PB
8497 if (max_isr == -1)
8498 max_isr = 0;
c7c9c56c
YZ
8499
8500 status = vmcs_read16(GUEST_INTR_STATUS);
8501 old = status >> 8;
67c9dddc 8502 if (max_isr != old) {
c7c9c56c 8503 status &= 0xff;
67c9dddc 8504 status |= max_isr << 8;
c7c9c56c
YZ
8505 vmcs_write16(GUEST_INTR_STATUS, status);
8506 }
8507}
8508
8509static void vmx_set_rvi(int vector)
8510{
8511 u16 status;
8512 u8 old;
8513
4114c27d
WW
8514 if (vector == -1)
8515 vector = 0;
8516
c7c9c56c
YZ
8517 status = vmcs_read16(GUEST_INTR_STATUS);
8518 old = (u8)status & 0xff;
8519 if ((u8)vector != old) {
8520 status &= ~0xff;
8521 status |= (u8)vector;
8522 vmcs_write16(GUEST_INTR_STATUS, status);
8523 }
8524}
8525
8526static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8527{
4114c27d
WW
8528 if (!is_guest_mode(vcpu)) {
8529 vmx_set_rvi(max_irr);
8530 return;
8531 }
8532
c7c9c56c
YZ
8533 if (max_irr == -1)
8534 return;
8535
963fee16 8536 /*
4114c27d
WW
8537 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8538 * handles it.
963fee16 8539 */
4114c27d 8540 if (nested_exit_on_intr(vcpu))
963fee16
WL
8541 return;
8542
963fee16 8543 /*
4114c27d 8544 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL
8545 * is run without virtual interrupt delivery.
8546 */
8547 if (!kvm_event_needs_reinjection(vcpu) &&
8548 vmx_interrupt_allowed(vcpu)) {
8549 kvm_queue_interrupt(vcpu, max_irr, false);
8550 vmx_inject_irq(vcpu);
8551 }
c7c9c56c
YZ
8552}
8553
76dfafd5 8554static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
810e6def
PB
8555{
8556 struct vcpu_vmx *vmx = to_vmx(vcpu);
76dfafd5 8557 int max_irr;
810e6def 8558
76dfafd5
PB
8559 WARN_ON(!vcpu->arch.apicv_active);
8560 if (pi_test_on(&vmx->pi_desc)) {
8561 pi_clear_on(&vmx->pi_desc);
8562 /*
8563 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8564 * But on x86 this is just a compiler barrier anyway.
8565 */
8566 smp_mb__after_atomic();
8567 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8568 } else {
8569 max_irr = kvm_lapic_find_highest_irr(vcpu);
8570 }
8571 vmx_hwapic_irr_update(vcpu, max_irr);
8572 return max_irr;
810e6def
PB
8573}
8574
6308630b 8575static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
c7c9c56c 8576{
d62caabb 8577 if (!kvm_vcpu_apicv_active(vcpu))
3d81bc7e
YZ
8578 return;
8579
c7c9c56c
YZ
8580 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8581 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8582 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8583 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8584}
8585
967235d3
PB
8586static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8587{
8588 struct vcpu_vmx *vmx = to_vmx(vcpu);
8589
8590 pi_clear_on(&vmx->pi_desc);
8591 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8592}
8593
51aa01d1 8594static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8595{
00eba012
AK
8596 u32 exit_intr_info;
8597
8598 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8599 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8600 return;
8601
c5ca8e57 8602 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 8603 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK
8604
8605 /* Handle machine checks before interrupts are enabled */
00eba012 8606 if (is_machine_check(exit_intr_info))
a0861c02
AK
8607 kvm_machine_check();
8608
20f65983 8609 /* We need to handle NMIs before interrupts are enabled */
ef85b673 8610 if (is_nmi(exit_intr_info)) {
ff9d07a0 8611 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8612 asm("int $2");
ff9d07a0
ZY
8613 kvm_after_handle_nmi(&vmx->vcpu);
8614 }
51aa01d1 8615}
20f65983 8616
a547c6db
YZ
8617static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8618{
8619 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3f62de5f 8620 register void *__sp asm(_ASM_SP);
a547c6db 8621
a547c6db
YZ
8622 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8623 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8624 unsigned int vector;
8625 unsigned long entry;
8626 gate_desc *desc;
8627 struct vcpu_vmx *vmx = to_vmx(vcpu);
8628#ifdef CONFIG_X86_64
8629 unsigned long tmp;
8630#endif
8631
8632 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8633 desc = (gate_desc *)vmx->host_idt_base + vector;
8634 entry = gate_offset(*desc);
8635 asm volatile(
8636#ifdef CONFIG_X86_64
8637 "mov %%" _ASM_SP ", %[sp]\n\t"
8638 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8639 "push $%c[ss]\n\t"
8640 "push %[sp]\n\t"
8641#endif
8642 "pushf\n\t"
a547c6db
YZ
8643 __ASM_SIZE(push) " $%c[cs]\n\t"
8644 "call *%[entry]\n\t"
8645 :
8646#ifdef CONFIG_X86_64
3f62de5f 8647 [sp]"=&r"(tmp),
a547c6db 8648#endif
3f62de5f 8649 "+r"(__sp)
a547c6db
YZ
8650 :
8651 [entry]"r"(entry),
8652 [ss]"i"(__KERNEL_DS),
8653 [cs]"i"(__KERNEL_CS)
8654 );
f2485b3e 8655 }
a547c6db
YZ
8656}
8657
6d396b55
PB
8658static bool vmx_has_high_real_mode_segbase(void)
8659{
8660 return enable_unrestricted_guest || emulate_invalid_guest_state;
8661}
8662
da8999d3
LJ
8663static bool vmx_mpx_supported(void)
8664{
8665 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8666 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8667}
8668
55412b2e
WL
8669static bool vmx_xsaves_supported(void)
8670{
8671 return vmcs_config.cpu_based_2nd_exec_ctrl &
8672 SECONDARY_EXEC_XSAVES;
8673}
8674
51aa01d1
AK
8675static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8676{
c5ca8e57 8677 u32 exit_intr_info;
51aa01d1
AK
8678 bool unblock_nmi;
8679 u8 vector;
8680 bool idtv_info_valid;
8681
8682 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8683
2c82878b
PB
8684 if (vmx->nmi_known_unmasked)
8685 return;
8686 /*
8687 * Can't use vmx->exit_intr_info since we're not sure what
8688 * the exit reason is.
8689 */
8690 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8691 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8692 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8693 /*
8694 * SDM 3: 27.7.1.2 (September 2008)
8695 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8696 * a guest IRET fault.
8697 * SDM 3: 23.2.2 (September 2008)
8698 * Bit 12 is undefined in any of the following cases:
8699 * If the VM exit sets the valid bit in the IDT-vectoring
8700 * information field.
8701 * If the VM exit is due to a double fault.
8702 */
8703 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8704 vector != DF_VECTOR && !idtv_info_valid)
8705 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8706 GUEST_INTR_STATE_NMI);
8707 else
8708 vmx->nmi_known_unmasked =
8709 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8710 & GUEST_INTR_STATE_NMI);
51aa01d1
AK
8711}
8712
3ab66e8a 8713static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK
8714 u32 idt_vectoring_info,
8715 int instr_len_field,
8716 int error_code_field)
51aa01d1 8717{
51aa01d1
AK
8718 u8 vector;
8719 int type;
8720 bool idtv_info_valid;
8721
8722 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8723
3ab66e8a
JK
8724 vcpu->arch.nmi_injected = false;
8725 kvm_clear_exception_queue(vcpu);
8726 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN
8727
8728 if (!idtv_info_valid)
8729 return;
8730
3ab66e8a 8731 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8732
668f612f
AK
8733 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8734 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8735
64a7ec06 8736 switch (type) {
37b96e98 8737 case INTR_TYPE_NMI_INTR:
3ab66e8a 8738 vcpu->arch.nmi_injected = true;
668f612f 8739 /*
7b4a25cb 8740 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN
8741 * Clear bit "block by NMI" before VM entry if a NMI
8742 * delivery faulted.
668f612f 8743 */
3ab66e8a 8744 vmx_set_nmi_mask(vcpu, false);
37b96e98 8745 break;
37b96e98 8746 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8747 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN
8748 /* fall through */
8749 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8750 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8751 u32 err = vmcs_read32(error_code_field);
851eb667 8752 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8753 } else
851eb667 8754 kvm_requeue_exception(vcpu, vector);
37b96e98 8755 break;
66fd3f7f 8756 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8757 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8758 /* fall through */
37b96e98 8759 case INTR_TYPE_EXT_INTR:
3ab66e8a 8760 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN
8761 break;
8762 default:
8763 break;
f7d9238f 8764 }
cf393f75
AK
8765}
8766
83422e17
AK
8767static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8768{
3ab66e8a 8769 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK
8770 VM_EXIT_INSTRUCTION_LEN,
8771 IDT_VECTORING_ERROR_CODE);
8772}
8773
b463a6f7
AK
8774static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8775{
3ab66e8a 8776 __vmx_complete_interrupts(vcpu,
b463a6f7
AK
8777 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8778 VM_ENTRY_INSTRUCTION_LEN,
8779 VM_ENTRY_EXCEPTION_ERROR_CODE);
8780
8781 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8782}
8783
d7cd9796
GN
8784static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8785{
8786 int i, nr_msrs;
8787 struct perf_guest_switch_msr *msrs;
8788
8789 msrs = perf_guest_get_msrs(&nr_msrs);
8790
8791 if (!msrs)
8792 return;
8793
8794 for (i = 0; i < nr_msrs; i++)
8795 if (msrs[i].host == msrs[i].guest)
8796 clear_atomic_switch_msr(vmx, msrs[i].msr);
8797 else
8798 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8799 msrs[i].host);
8800}
8801
33365e7a 8802static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
64672c95
YJ
8803{
8804 struct vcpu_vmx *vmx = to_vmx(vcpu);
8805 u64 tscl;
8806 u32 delta_tsc;
8807
8808 if (vmx->hv_deadline_tsc == -1)
8809 return;
8810
8811 tscl = rdtsc();
8812 if (vmx->hv_deadline_tsc > tscl)
8813 /* sure to be 32 bit only because checked on set_hv_timer */
8814 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8815 cpu_preemption_timer_multi);
8816 else
8817 delta_tsc = 0;
8818
8819 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8820}
8821
a3b5ba49 8822static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8823{
a2fa3e9f 8824 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8825 unsigned long debugctlmsr, cr4;
104f226b 8826
104f226b
AK
8827 /* Don't enter VMX if guest state is invalid, let the exit handler
8828 start emulation until we arrive back to a valid state */
14168786 8829 if (vmx->emulation_required)
104f226b
AK
8830 return;
8831
a7653ecd
RK
8832 if (vmx->ple_window_dirty) {
8833 vmx->ple_window_dirty = false;
8834 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8835 }
8836
012f83cb
AG
8837 if (vmx->nested.sync_shadow_vmcs) {
8838 copy_vmcs12_to_shadow(vmx);
8839 vmx->nested.sync_shadow_vmcs = false;
8840 }
8841
104f226b
AK
8842 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8843 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8844 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8845 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8846
1e02ce4c 8847 cr4 = cr4_read_shadow();
d974baa3
AL
8848 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8849 vmcs_writel(HOST_CR4, cr4);
8850 vmx->host_state.vmcs_host_cr4 = cr4;
8851 }
8852
104f226b
AK
8853 /* When single-stepping over STI and MOV SS, we must clear the
8854 * corresponding interruptibility bits in the guest state. Otherwise
8855 * vmentry fails as it then expects bit 14 (BS) in pending debug
8856 * exceptions being set, but that's not correct for the guest debugging
8857 * case. */
8858 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8859 vmx_set_interrupt_shadow(vcpu, 0);
8860
1be0e61c
XG
8861 if (vmx->guest_pkru_valid)
8862 __write_pkru(vmx->guest_pkru);
8863
d7cd9796 8864 atomic_switch_perf_msrs(vmx);
2a7921b7 8865 debugctlmsr = get_debugctlmsr();
d7cd9796 8866
64672c95
YJ
8867 vmx_arm_hv_timer(vcpu);
8868
d462b819 8869 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8870 asm(
6aa8b732 8871 /* Store host registers */
b188c81f
AK
8872 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8873 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8874 "push %%" _ASM_CX " \n\t"
8875 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8876 "je 1f \n\t"
b188c81f 8877 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8878 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8879 "1: \n\t"
d3edefc0 8880 /* Reload cr2 if changed */
b188c81f
AK
8881 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8882 "mov %%cr2, %%" _ASM_DX " \n\t"
8883 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8884 "je 2f \n\t"
b188c81f 8885 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8886 "2: \n\t"
6aa8b732 8887 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8888 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8889 /* Load guest registers. Don't clobber flags. */
b188c81f
AK
8890 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8891 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8892 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8893 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8894 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8895 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8896#ifdef CONFIG_X86_64
e08aa78a
AK
8897 "mov %c[r8](%0), %%r8 \n\t"
8898 "mov %c[r9](%0), %%r9 \n\t"
8899 "mov %c[r10](%0), %%r10 \n\t"
8900 "mov %c[r11](%0), %%r11 \n\t"
8901 "mov %c[r12](%0), %%r12 \n\t"
8902 "mov %c[r13](%0), %%r13 \n\t"
8903 "mov %c[r14](%0), %%r14 \n\t"
8904 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8905#endif
b188c81f 8906 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8907
6aa8b732 8908 /* Enter guest mode */
83287ea4 8909 "jne 1f \n\t"
4ecac3fd 8910 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK
8911 "jmp 2f \n\t"
8912 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8913 "2: "
6aa8b732 8914 /* Save guest registers, load host registers, keep flags */
b188c81f 8915 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8916 "pop %0 \n\t"
b188c81f
AK
8917 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8918 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8919 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8920 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8921 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8922 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8923 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8924#ifdef CONFIG_X86_64
e08aa78a
AK
8925 "mov %%r8, %c[r8](%0) \n\t"
8926 "mov %%r9, %c[r9](%0) \n\t"
8927 "mov %%r10, %c[r10](%0) \n\t"
8928 "mov %%r11, %c[r11](%0) \n\t"
8929 "mov %%r12, %c[r12](%0) \n\t"
8930 "mov %%r13, %c[r13](%0) \n\t"
8931 "mov %%r14, %c[r14](%0) \n\t"
8932 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8933#endif
b188c81f
AK
8934 "mov %%cr2, %%" _ASM_AX " \n\t"
8935 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8936
b188c81f 8937 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8938 "setbe %c[fail](%0) \n\t"
83287ea4
AK
8939 ".pushsection .rodata \n\t"
8940 ".global vmx_return \n\t"
8941 "vmx_return: " _ASM_PTR " 2b \n\t"
8942 ".popsection"
e08aa78a 8943 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8944 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8945 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8946 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX
8947 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8948 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8949 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8950 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8951 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8952 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8953 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8954#ifdef CONFIG_X86_64
ad312c7c
ZX
8955 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8956 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8957 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8958 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8959 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8960 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8961 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8962 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8963#endif
40712fae
AK
8964 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8965 [wordsize]"i"(sizeof(ulong))
c2036300
LV
8966 : "cc", "memory"
8967#ifdef CONFIG_X86_64
b188c81f 8968 , "rax", "rbx", "rdi", "rsi"
c2036300 8969 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK
8970#else
8971 , "eax", "ebx", "edi", "esi"
c2036300
LV
8972#endif
8973 );
6aa8b732 8974
2a7921b7
GN
8975 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8976 if (debugctlmsr)
8977 update_debugctlmsr(debugctlmsr);
8978
aa67f609
AK
8979#ifndef CONFIG_X86_64
8980 /*
8981 * The sysexit path does not restore ds/es, so we must set them to
8982 * a reasonable value ourselves.
8983 *
8984 * We can't defer this to vmx_load_host_state() since that function
8985 * may be executed in interrupt context, which saves and restore segments
8986 * around it, nullifying its effect.
8987 */
8988 loadsegment(ds, __USER_DS);
8989 loadsegment(es, __USER_DS);
8990#endif
8991
6de4f3ad 8992 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8993 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8994 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8995 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8996 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT
8997 vcpu->arch.regs_dirty = 0;
8998
1155f76a
AK
8999 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9000
d462b819 9001 vmx->loaded_vmcs->launched = 1;
1b6269db 9002
51aa01d1 9003 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1 9004
1be0e61c
XG
9005 /*
9006 * eager fpu is enabled if PKEY is supported and CR4 is switched
9007 * back on host, so it is safe to read guest PKRU from current
9008 * XSAVE.
9009 */
9010 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9011 vmx->guest_pkru = __read_pkru();
9012 if (vmx->guest_pkru != vmx->host_pkru) {
9013 vmx->guest_pkru_valid = true;
9014 __write_pkru(vmx->host_pkru);
9015 } else
9016 vmx->guest_pkru_valid = false;
9017 }
9018
e0b890d3
GN
9019 /*
9020 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9021 * we did not inject a still-pending event to L1 now because of
9022 * nested_run_pending, we need to re-enable this bit.
9023 */
9024 if (vmx->nested.nested_run_pending)
9025 kvm_make_request(KVM_REQ_EVENT, vcpu);
9026
9027 vmx->nested.nested_run_pending = 0;
9028
51aa01d1
AK
9029 vmx_complete_atomic_exit(vmx);
9030 vmx_recover_nmi_blocking(vmx);
cf393f75 9031 vmx_complete_interrupts(vmx);
6aa8b732
AK
9032}
9033
1279a6b1 9034static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
4fa7734c
PB
9035{
9036 struct vcpu_vmx *vmx = to_vmx(vcpu);
9037 int cpu;
9038
1279a6b1 9039 if (vmx->loaded_vmcs == vmcs)
4fa7734c
PB
9040 return;
9041
9042 cpu = get_cpu();
1279a6b1 9043 vmx->loaded_vmcs = vmcs;
4fa7734c
PB
9044 vmx_vcpu_put(vcpu);
9045 vmx_vcpu_load(vcpu, cpu);
9046 vcpu->cpu = cpu;
9047 put_cpu();
9048}
9049
2f1fe811
JM
9050/*
9051 * Ensure that the current vmcs of the logical processor is the
9052 * vmcs01 of the vcpu before calling free_nested().
9053 */
9054static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9055{
9056 struct vcpu_vmx *vmx = to_vmx(vcpu);
9057 int r;
9058
9059 r = vcpu_load(vcpu);
9060 BUG_ON(r);
1279a6b1 9061 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
2f1fe811
JM
9062 free_nested(vmx);
9063 vcpu_put(vcpu);
9064}
9065
6aa8b732
AK
9066static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9067{
fb3f0f51
RR
9068 struct vcpu_vmx *vmx = to_vmx(vcpu);
9069
843e4330 9070 if (enable_pml)
a3eaa864 9071 vmx_destroy_pml_buffer(vmx);
991e7a0e 9072 free_vpid(vmx->vpid);
4fa7734c 9073 leave_guest_mode(vcpu);
2f1fe811 9074 vmx_free_vcpu_nested(vcpu);
4fa7734c 9075 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR
9076 kfree(vmx->guest_msrs);
9077 kvm_vcpu_uninit(vcpu);
a4770347 9078 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK
9079}
9080
fb3f0f51 9081static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 9082{
fb3f0f51 9083 int err;
c16f862d 9084 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 9085 int cpu;
6aa8b732 9086
a2fa3e9f 9087 if (!vmx)
fb3f0f51
RR
9088 return ERR_PTR(-ENOMEM);
9089
991e7a0e 9090 vmx->vpid = allocate_vpid();
2384d2b3 9091
fb3f0f51
RR
9092 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9093 if (err)
9094 goto free_vcpu;
965b58a5 9095
4e59516a
PF
9096 err = -ENOMEM;
9097
9098 /*
9099 * If PML is turned on, failure on enabling PML just results in failure
9100 * of creating the vcpu, therefore we can simplify PML logic (by
9101 * avoiding dealing with cases, such as enabling PML partially on vcpus
9102 * for the guest, etc.
9103 */
9104 if (enable_pml) {
9105 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9106 if (!vmx->pml_pg)
9107 goto uninit_vcpu;
9108 }
9109
a2fa3e9f 9110 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB
9111 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9112 > PAGE_SIZE);
0123be42 9113
4e59516a
PF
9114 if (!vmx->guest_msrs)
9115 goto free_pml;
965b58a5 9116
d462b819
NHE
9117 vmx->loaded_vmcs = &vmx->vmcs01;
9118 vmx->loaded_vmcs->vmcs = alloc_vmcs();
355f4fb1 9119 vmx->loaded_vmcs->shadow_vmcs = NULL;
d462b819 9120 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 9121 goto free_msrs;
d462b819 9122 loaded_vmcs_init(vmx->loaded_vmcs);
a2fa3e9f 9123
15ad7146
AK
9124 cpu = get_cpu();
9125 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 9126 vmx->vcpu.cpu = cpu;
8b9cf98c 9127 err = vmx_vcpu_setup(vmx);
fb3f0f51 9128 vmx_vcpu_put(&vmx->vcpu);
15ad7146 9129 put_cpu();
fb3f0f51
RR
9130 if (err)
9131 goto free_vmcs;
35754c98 9132 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK
9133 err = alloc_apic_access_page(kvm);
9134 if (err)
5e4a0b3c 9135 goto free_vmcs;
a63cb560 9136 }
fb3f0f51 9137
b927a3ce
SY
9138 if (enable_ept) {
9139 if (!kvm->arch.ept_identity_map_addr)
9140 kvm->arch.ept_identity_map_addr =
9141 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC
9142 err = init_rmode_identity_map(kvm);
9143 if (err)
93ea5388 9144 goto free_vmcs;
b927a3ce 9145 }
b7ebfb05 9146
5c614b35 9147 if (nested) {
b9c237bb 9148 nested_vmx_setup_ctls_msrs(vmx);
5c614b35
WL
9149 vmx->nested.vpid02 = allocate_vpid();
9150 }
b9c237bb 9151
705699a1 9152 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE
9153 vmx->nested.current_vmptr = -1ull;
9154 vmx->nested.current_vmcs12 = NULL;
9155
37e4c997
HZ
9156 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9157
fb3f0f51
RR
9158 return &vmx->vcpu;
9159
9160free_vmcs:
5c614b35 9161 free_vpid(vmx->nested.vpid02);
5f3fbc34 9162 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 9163free_msrs:
fb3f0f51 9164 kfree(vmx->guest_msrs);
4e59516a
PF
9165free_pml:
9166 vmx_destroy_pml_buffer(vmx);
fb3f0f51
RR
9167uninit_vcpu:
9168 kvm_vcpu_uninit(&vmx->vcpu);
9169free_vcpu:
991e7a0e 9170 free_vpid(vmx->vpid);
a4770347 9171 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 9172 return ERR_PTR(err);
6aa8b732
AK
9173}
9174
002c7f7c
YS
9175static void __init vmx_check_processor_compat(void *rtn)
9176{
9177 struct vmcs_config vmcs_conf;
9178
9179 *(int *)rtn = 0;
9180 if (setup_vmcs_config(&vmcs_conf) < 0)
9181 *(int *)rtn = -EIO;
9182 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9183 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9184 smp_processor_id());
9185 *(int *)rtn = -EIO;
9186 }
9187}
9188
67253af5
SY
9189static int get_ept_level(void)
9190{
9191 return VMX_EPT_DEFAULT_GAW + 1;
9192}
9193
4b12f0de 9194static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 9195{
b18d5431
XG
9196 u8 cache;
9197 u64 ipat = 0;
4b12f0de 9198
522c68c4 9199 /* For VT-d and EPT combination
606decd6 9200 * 1. MMIO: always map as UC
522c68c4
SY
9201 * 2. EPT with VT-d:
9202 * a. VT-d without snooping control feature: can't guarantee the
606decd6 9203 * result, try to trust guest.
522c68c4
SY
9204 * b. VT-d with snooping control feature: snooping control feature of
9205 * VT-d engine can guarantee the cache correctness. Just set it
9206 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 9207 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY
9208 * consistent with host MTRR
9209 */
606decd6
PB
9210 if (is_mmio) {
9211 cache = MTRR_TYPE_UNCACHABLE;
9212 goto exit;
9213 }
9214
9215 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG
9216 ipat = VMX_EPT_IPAT_BIT;
9217 cache = MTRR_TYPE_WRBACK;
9218 goto exit;
9219 }
9220
9221 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9222 ipat = VMX_EPT_IPAT_BIT;
0da029ed 9223 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG
9224 cache = MTRR_TYPE_WRBACK;
9225 else
9226 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG
9227 goto exit;
9228 }
9229
ff53604b 9230 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG
9231
9232exit:
9233 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY
9234}
9235
17cc3935 9236static int vmx_get_lpage_level(void)
344f414f 9237{
878403b7
SY
9238 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9239 return PT_DIRECTORY_LEVEL;
9240 else
9241 /* For shadow and EPT supported 1GB page */
9242 return PT_PDPE_LEVEL;
344f414f
JR
9243}
9244
feda805f
XG
9245static void vmcs_set_secondary_exec_control(u32 new_ctl)
9246{
9247 /*
9248 * These bits in the secondary execution controls field
9249 * are dynamic, the others are mostly based on the hypervisor
9250 * architecture and the guest's CPUID. Do not touch the
9251 * dynamic bits.
9252 */
9253 u32 mask =
9254 SECONDARY_EXEC_SHADOW_VMCS |
9255 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9256 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9257
9258 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9259
9260 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9261 (new_ctl & ~mask) | (cur_ctl & mask));
9262}
9263
8322ebbb
DM
9264/*
9265 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9266 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9267 */
9268static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9269{
9270 struct vcpu_vmx *vmx = to_vmx(vcpu);
9271 struct kvm_cpuid_entry2 *entry;
9272
9273 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9274 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9275
9276#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9277 if (entry && (entry->_reg & (_cpuid_mask))) \
9278 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9279} while (0)
9280
9281 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9282 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
9283 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
9284 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
9285 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
9286 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
9287 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
9288 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
9289 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
9290 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
9291 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9292 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
9293 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
9294 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
9295 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
9296
9297 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9298 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
9299 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
9300 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
9301 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
9302 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9303 cr4_fixed1_update(bit(11), ecx, bit(2));
9304
9305#undef cr4_fixed1_update
9306}
9307
0e851880
SY
9308static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9309{
4e47c7a6
SY
9310 struct kvm_cpuid_entry2 *best;
9311 struct vcpu_vmx *vmx = to_vmx(vcpu);
feda805f 9312 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
4e47c7a6 9313
4e47c7a6 9314 if (vmx_rdtscp_supported()) {
1cea0ce6
XG
9315 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9316 if (!rdtscp_enabled)
feda805f 9317 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
f36201e5 9318
8b97265a 9319 if (nested) {
1cea0ce6 9320 if (rdtscp_enabled)
8b97265a
PB
9321 vmx->nested.nested_vmx_secondary_ctls_high |=
9322 SECONDARY_EXEC_RDTSCP;
9323 else
9324 vmx->nested.nested_vmx_secondary_ctls_high &=
9325 ~SECONDARY_EXEC_RDTSCP;
9326 }
4e47c7a6 9327 }
ad756a16 9328
ad756a16
MJ
9329 /* Exposing INVPCID only when PCID is exposed */
9330 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9331 if (vmx_invpcid_supported() &&
29541bb8
XG
9332 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9333 !guest_cpuid_has_pcid(vcpu))) {
feda805f 9334 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
29541bb8 9335
ad756a16 9336 if (best)
4f977045 9337 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 9338 }
8b3e34e4 9339
45bdbcfd
HH
9340 if (cpu_has_secondary_exec_ctrls())
9341 vmcs_set_secondary_exec_control(secondary_exec_ctl);
feda805f 9342
37e4c997
HZ
9343 if (nested_vmx_allowed(vcpu))
9344 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9345 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9346 else
9347 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9348 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
8322ebbb
DM
9349
9350 if (nested_vmx_allowed(vcpu))
9351 nested_vmx_cr_fixed1_bits_update(vcpu);
0e851880
SY
9352}
9353
d4330ef2
JR
9354static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9355{
7b8050f5
NHE
9356 if (func == 1 && nested)
9357 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR
9358}
9359
25d92081
YZ
9360static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9361 struct x86_exception *fault)
9362{
533558bc 9363 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
c5f983f6 9364 struct vcpu_vmx *vmx = to_vmx(vcpu);
533558bc 9365 u32 exit_reason;
c5f983f6 9366 unsigned long exit_qualification = vcpu->arch.exit_qualification;
25d92081 9367
c5f983f6
BD
9368 if (vmx->nested.pml_full) {
9369 exit_reason = EXIT_REASON_PML_FULL;
9370 vmx->nested.pml_full = false;
9371 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9372 } else if (fault->error_code & PFERR_RSVD_MASK)
533558bc 9373 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 9374 else
533558bc 9375 exit_reason = EXIT_REASON_EPT_VIOLATION;
c5f983f6
BD
9376
9377 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
25d92081
YZ
9378 vmcs12->guest_physical_address = fault->address;
9379}
9380
155a97a3
NHE
9381/* Callbacks for nested_ept_init_mmu_context: */
9382
9383static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9384{
9385 /* return the page table to be shadowed - in our case, EPT12 */
9386 return get_vmcs12(vcpu)->ept_pointer;
9387}
9388
ae1e2d10 9389static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 9390{
ae1e2d10
PB
9391 u64 eptp;
9392
ad896af0 9393 WARN_ON(mmu_is_nested(vcpu));
ae1e2d10
PB
9394 eptp = nested_ept_get_cr3(vcpu);
9395 if ((eptp & VMX_EPT_AD_ENABLE_BIT) && !enable_ept_ad_bits)
9396 return 1;
9397
9398 kvm_mmu_unload(vcpu);
ad896af0 9399 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb 9400 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
ae1e2d10
PB
9401 VMX_EPT_EXECUTE_ONLY_BIT,
9402 eptp & VMX_EPT_AD_ENABLE_BIT);
155a97a3
NHE
9403 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9404 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9405 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9406
9407 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
ae1e2d10 9408 return 0;
155a97a3
NHE
9409}
9410
9411static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9412{
9413 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9414}
9415
19d5f10b
EK
9416static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9417 u16 error_code)
9418{
9419 bool inequality, bit;
9420
9421 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9422 inequality =
9423 (error_code & vmcs12->page_fault_error_code_mask) !=
9424 vmcs12->page_fault_error_code_match;
9425 return inequality ^ bit;
9426}
9427
feaf0c7d
GN
9428static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9429 struct x86_exception *fault)
9430{
9431 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9432
9433 WARN_ON(!is_guest_mode(vcpu));
9434
19d5f10b 9435 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK
9436 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9437 vmcs_read32(VM_EXIT_INTR_INFO),
9438 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN
9439 else
9440 kvm_inject_page_fault(vcpu, fault);
9441}
9442
6beb7bd5
JM
9443static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9444 struct vmcs12 *vmcs12);
9445
9446static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
a2bcba50
WL
9447 struct vmcs12 *vmcs12)
9448{
9449 struct vcpu_vmx *vmx = to_vmx(vcpu);
6beb7bd5 9450 u64 hpa;
a2bcba50
WL
9451
9452 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a2bcba50
WL
9453 /*
9454 * Translate L1 physical address to host physical
9455 * address for vmcs02. Keep the page pinned, so this
9456 * physical address remains valid. We keep a reference
9457 * to it so we can release it later.
9458 */
9459 if (vmx->nested.apic_access_page) /* shouldn't happen */
9460 nested_release_page(vmx->nested.apic_access_page);
9461 vmx->nested.apic_access_page =
9462 nested_get_page(vcpu, vmcs12->apic_access_addr);
6beb7bd5
JM
9463 /*
9464 * If translation failed, no matter: This feature asks
9465 * to exit when accessing the given address, and if it
9466 * can never be accessed, this feature won't do
9467 * anything anyway.
9468 */
9469 if (vmx->nested.apic_access_page) {
9470 hpa = page_to_phys(vmx->nested.apic_access_page);
9471 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9472 } else {
9473 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9474 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9475 }
9476 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9477 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9478 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9479 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9480 kvm_vcpu_reload_apic_access_page(vcpu);
a2bcba50 9481 }
a7c0b07d
WL
9482
9483 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
a7c0b07d
WL
9484 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9485 nested_release_page(vmx->nested.virtual_apic_page);
9486 vmx->nested.virtual_apic_page =
9487 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9488
9489 /*
6beb7bd5
JM
9490 * If translation failed, VM entry will fail because
9491 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9492 * Failing the vm entry is _not_ what the processor
9493 * does but it's basically the only possibility we
9494 * have. We could still enter the guest if CR8 load
9495 * exits are enabled, CR8 store exits are enabled, and
9496 * virtualize APIC access is disabled; in this case
9497 * the processor would never use the TPR shadow and we
9498 * could simply clear the bit from the execution
9499 * control. But such a configuration is useless, so
9500 * let's keep the code simple.
a7c0b07d 9501 */
6beb7bd5
JM
9502 if (vmx->nested.virtual_apic_page) {
9503 hpa = page_to_phys(vmx->nested.virtual_apic_page);
9504 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9505 }
a7c0b07d
WL
9506 }
9507
705699a1 9508 if (nested_cpu_has_posted_intr(vmcs12)) {
705699a1
WV
9509 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9510 kunmap(vmx->nested.pi_desc_page);
9511 nested_release_page(vmx->nested.pi_desc_page);
9512 }
9513 vmx->nested.pi_desc_page =
9514 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
705699a1
WV
9515 vmx->nested.pi_desc =
9516 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9517 if (!vmx->nested.pi_desc) {
9518 nested_release_page_clean(vmx->nested.pi_desc_page);
6beb7bd5 9519 return;
705699a1
WV
9520 }
9521 vmx->nested.pi_desc =
9522 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9523 (unsigned long)(vmcs12->posted_intr_desc_addr &
9524 (PAGE_SIZE - 1)));
6beb7bd5
JM
9525 vmcs_write64(POSTED_INTR_DESC_ADDR,
9526 page_to_phys(vmx->nested.pi_desc_page) +
9527 (unsigned long)(vmcs12->posted_intr_desc_addr &
9528 (PAGE_SIZE - 1)));
705699a1 9529 }
6beb7bd5
JM
9530 if (cpu_has_vmx_msr_bitmap() &&
9531 nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9532 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9533 ;
9534 else
9535 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9536 CPU_BASED_USE_MSR_BITMAPS);
a2bcba50
WL
9537}
9538
f4124500
JK
9539static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9540{
9541 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9542 struct vcpu_vmx *vmx = to_vmx(vcpu);
9543
9544 if (vcpu->arch.virtual_tsc_khz == 0)
9545 return;
9546
9547 /* Make sure short timeouts reliably trigger an immediate vmexit.
9548 * hrtimer_start does not guarantee this. */
9549 if (preemption_timeout <= 1) {
9550 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9551 return;
9552 }
9553
9554 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9555 preemption_timeout *= 1000000;
9556 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9557 hrtimer_start(&vmx->nested.preemption_timer,
9558 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9559}
9560
3af18d9c
WV
9561static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9562 struct vmcs12 *vmcs12)
9563{
9564 int maxphyaddr;
9565 u64 addr;
9566
9567 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9568 return 0;
9569
9570 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9571 WARN_ON(1);
9572 return -EINVAL;
9573 }
9574 maxphyaddr = cpuid_maxphyaddr(vcpu);
9575
9576 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9577 ((addr + PAGE_SIZE) >> maxphyaddr))
9578 return -EINVAL;
9579
9580 return 0;
9581}
9582
9583/*
9584 * Merge L0's and L1's MSR bitmap, return false to indicate that
9585 * we do not use the hardware.
9586 */
9587static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9588 struct vmcs12 *vmcs12)
9589{
82f0dd4b 9590 int msr;
f2b93280 9591 struct page *page;
d048c098
RK
9592 unsigned long *msr_bitmap_l1;
9593 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
f2b93280 9594
d048c098 9595 /* This shortcut is ok because we support only x2APIC MSRs so far. */
f2b93280
WV
9596 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9597 return false;
9598
9599 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
05d8d346 9600 if (!page)
f2b93280 9601 return false;
d048c098 9602 msr_bitmap_l1 = (unsigned long *)kmap(page);
f2b93280 9603
d048c098
RK
9604 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9605
f2b93280 9606 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV
9607 if (nested_cpu_has_apic_reg_virt(vmcs12))
9608 for (msr = 0x800; msr <= 0x8ff; msr++)
9609 nested_vmx_disable_intercept_for_msr(
d048c098 9610 msr_bitmap_l1, msr_bitmap_l0,
82f0dd4b 9611 msr, MSR_TYPE_R);
d048c098
RK
9612
9613 nested_vmx_disable_intercept_for_msr(
9614 msr_bitmap_l1, msr_bitmap_l0,
f2b93280
WV
9615 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9616 MSR_TYPE_R | MSR_TYPE_W);
d048c098 9617
608406e2 9618 if (nested_cpu_has_vid(vmcs12)) {
608406e2 9619 nested_vmx_disable_intercept_for_msr(
d048c098 9620 msr_bitmap_l1, msr_bitmap_l0,
608406e2
WV
9621 APIC_BASE_MSR + (APIC_EOI >> 4),
9622 MSR_TYPE_W);
9623 nested_vmx_disable_intercept_for_msr(
d048c098 9624 msr_bitmap_l1, msr_bitmap_l0,
608406e2
WV
9625 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9626 MSR_TYPE_W);
9627 }
82f0dd4b 9628 }
f2b93280
WV
9629 kunmap(page);
9630 nested_release_page_clean(page);
9631
9632 return true;
9633}
9634
9635static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9636 struct vmcs12 *vmcs12)
9637{
82f0dd4b 9638 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 9639 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV
9640 !nested_cpu_has_vid(vmcs12) &&
9641 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV
9642 return 0;
9643
9644 /*
9645 * If virtualize x2apic mode is enabled,
9646 * virtualize apic access must be disabled.
9647 */
82f0dd4b
WV
9648 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9649 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV
9650 return -EINVAL;
9651
608406e2
WV
9652 /*
9653 * If virtual interrupt delivery is enabled,
9654 * we must exit on external interrupts.
9655 */
9656 if (nested_cpu_has_vid(vmcs12) &&
9657 !nested_exit_on_intr(vcpu))
9658 return -EINVAL;
9659
705699a1
WV
9660 /*
9661 * bits 15:8 should be zero in posted_intr_nv,
9662 * the descriptor address has been already checked
9663 * in nested_get_vmcs12_pages.
9664 */
9665 if (nested_cpu_has_posted_intr(vmcs12) &&
9666 (!nested_cpu_has_vid(vmcs12) ||
9667 !nested_exit_intr_ack_set(vcpu) ||
9668 vmcs12->posted_intr_nv & 0xff00))
9669 return -EINVAL;
9670
f2b93280
WV
9671 /* tpr shadow is needed by all apicv features. */
9672 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9673 return -EINVAL;
9674
9675 return 0;
3af18d9c
WV
9676}
9677
e9ac033e
EK
9678static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9679 unsigned long count_field,
92d71bc6 9680 unsigned long addr_field)
ff651cb6 9681{
92d71bc6 9682 int maxphyaddr;
e9ac033e
EK
9683 u64 count, addr;
9684
9685 if (vmcs12_read_any(vcpu, count_field, &count) ||
9686 vmcs12_read_any(vcpu, addr_field, &addr)) {
9687 WARN_ON(1);
9688 return -EINVAL;
9689 }
9690 if (count == 0)
9691 return 0;
92d71bc6 9692 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK
9693 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9694 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
bbe41b95 9695 pr_debug_ratelimited(
e9ac033e
EK
9696 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9697 addr_field, maxphyaddr, count, addr);
9698 return -EINVAL;
9699 }
9700 return 0;
9701}
9702
9703static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9704 struct vmcs12 *vmcs12)
9705{
e9ac033e
EK
9706 if (vmcs12->vm_exit_msr_load_count == 0 &&
9707 vmcs12->vm_exit_msr_store_count == 0 &&
9708 vmcs12->vm_entry_msr_load_count == 0)
9709 return 0; /* Fast path */
e9ac033e 9710 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9711 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9712 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9713 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9714 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9715 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK
9716 return -EINVAL;
9717 return 0;
9718}
9719
c5f983f6
BD
9720static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
9721 struct vmcs12 *vmcs12)
9722{
9723 u64 address = vmcs12->pml_address;
9724 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9725
9726 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
9727 if (!nested_cpu_has_ept(vmcs12) ||
9728 !IS_ALIGNED(address, 4096) ||
9729 address >> maxphyaddr)
9730 return -EINVAL;
9731 }
9732
9733 return 0;
9734}
9735
e9ac033e
EK
9736static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9737 struct vmx_msr_entry *e)
9738{
9739 /* x2APIC MSR accesses are not allowed */
8a9781f7 9740 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK
9741 return -EINVAL;
9742 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9743 e->index == MSR_IA32_UCODE_REV)
9744 return -EINVAL;
9745 if (e->reserved != 0)
ff651cb6
WV
9746 return -EINVAL;
9747 return 0;
9748}
9749
e9ac033e
EK
9750static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9751 struct vmx_msr_entry *e)
ff651cb6
WV
9752{
9753 if (e->index == MSR_FS_BASE ||
9754 e->index == MSR_GS_BASE ||
e9ac033e
EK
9755 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9756 nested_vmx_msr_check_common(vcpu, e))
9757 return -EINVAL;
9758 return 0;
9759}
9760
9761static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9762 struct vmx_msr_entry *e)
9763{
9764 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9765 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV
9766 return -EINVAL;
9767 return 0;
9768}
9769
9770/*
9771 * Load guest's/host's msr at nested entry/exit.
9772 * return 0 for success, entry index for failure.
9773 */
9774static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9775{
9776 u32 i;
9777 struct vmx_msr_entry e;
9778 struct msr_data msr;
9779
9780 msr.host_initiated = false;
9781 for (i = 0; i < count; i++) {
54bf36aa
PB
9782 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9783 &e, sizeof(e))) {
bbe41b95 9784 pr_debug_ratelimited(
e9ac033e
EK
9785 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9786 __func__, i, gpa + i * sizeof(e));
ff651cb6 9787 goto fail;
e9ac033e
EK
9788 }
9789 if (nested_vmx_load_msr_check(vcpu, &e)) {
bbe41b95 9790 pr_debug_ratelimited(
e9ac033e
EK
9791 "%s check failed (%u, 0x%x, 0x%x)\n",
9792 __func__, i, e.index, e.reserved);
9793 goto fail;
9794 }
ff651cb6
WV
9795 msr.index = e.index;
9796 msr.data = e.value;
e9ac033e 9797 if (kvm_set_msr(vcpu, &msr)) {
bbe41b95 9798 pr_debug_ratelimited(
e9ac033e
EK
9799 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9800 __func__, i, e.index, e.value);
ff651cb6 9801 goto fail;
e9ac033e 9802 }
ff651cb6
WV
9803 }
9804 return 0;
9805fail:
9806 return i + 1;
9807}
9808
9809static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9810{
9811 u32 i;
9812 struct vmx_msr_entry e;
9813
9814 for (i = 0; i < count; i++) {
609e36d3 9815 struct msr_data msr_info;
54bf36aa
PB
9816 if (kvm_vcpu_read_guest(vcpu,
9817 gpa + i * sizeof(e),
9818 &e, 2 * sizeof(u32))) {
bbe41b95 9819 pr_debug_ratelimited(
e9ac033e
EK
9820 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9821 __func__, i, gpa + i * sizeof(e));
ff651cb6 9822 return -EINVAL;
e9ac033e
EK
9823 }
9824 if (nested_vmx_store_msr_check(vcpu, &e)) {
bbe41b95 9825 pr_debug_ratelimited(
e9ac033e
EK
9826 "%s check failed (%u, 0x%x, 0x%x)\n",
9827 __func__, i, e.index, e.reserved);
ff651cb6 9828 return -EINVAL;
e9ac033e 9829 }
609e36d3
PB
9830 msr_info.host_initiated = false;
9831 msr_info.index = e.index;
9832 if (kvm_get_msr(vcpu, &msr_info)) {
bbe41b95 9833 pr_debug_ratelimited(
e9ac033e
EK
9834 "%s cannot read MSR (%u, 0x%x)\n",
9835 __func__, i, e.index);
9836 return -EINVAL;
9837 }
54bf36aa
PB
9838 if (kvm_vcpu_write_guest(vcpu,
9839 gpa + i * sizeof(e) +
9840 offsetof(struct vmx_msr_entry, value),
9841 &msr_info.data, sizeof(msr_info.data))) {
bbe41b95 9842 pr_debug_ratelimited(
e9ac033e 9843 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9844 __func__, i, e.index, msr_info.data);
e9ac033e
EK
9845 return -EINVAL;
9846 }
ff651cb6
WV
9847 }
9848 return 0;
9849}
9850
1dc35dac
LP
9851static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9852{
9853 unsigned long invalid_mask;
9854
9855 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9856 return (val & invalid_mask) == 0;
9857}
9858
9ed38ffa
LP
9859/*
9860 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9861 * emulating VM entry into a guest with EPT enabled.
9862 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9863 * is assigned to entry_failure_code on failure.
9864 */
9865static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
ca0bde28 9866 u32 *entry_failure_code)
9ed38ffa 9867{
9ed38ffa 9868 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
1dc35dac 9869 if (!nested_cr3_valid(vcpu, cr3)) {
9ed38ffa
LP
9870 *entry_failure_code = ENTRY_FAIL_DEFAULT;
9871 return 1;
9872 }
9873
9874 /*
9875 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9876 * must not be dereferenced.
9877 */
9878 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9879 !nested_ept) {
9880 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9881 *entry_failure_code = ENTRY_FAIL_PDPTE;
9882 return 1;
9883 }
9884 }
9885
9886 vcpu->arch.cr3 = cr3;
9887 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9888 }
9889
9890 kvm_mmu_reset_context(vcpu);
9891 return 0;
9892}
9893
fe3ef05c
NHE
9894/*
9895 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9896 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9897 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE
9898 * guest in a way that will both be appropriate to L1's requests, and our
9899 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9900 * function also has additional necessary side-effects, like setting various
9901 * vcpu->arch fields.
ee146c1c
LP
9902 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9903 * is assigned to entry_failure_code on failure.
fe3ef05c 9904 */
ee146c1c 9905static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
ca0bde28 9906 bool from_vmentry, u32 *entry_failure_code)
fe3ef05c
NHE
9907{
9908 struct vcpu_vmx *vmx = to_vmx(vcpu);
03efce6f 9909 u32 exec_control, vmcs12_exec_ctrl;
fe3ef05c
NHE
9910
9911 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9912 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9913 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9914 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9915 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9916 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9917 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9918 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9919 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9920 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9921 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9922 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9923 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9924 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9925 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9926 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9927 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9928 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9929 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9930 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9931 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9932 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9933 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9934 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9935 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9936 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9937 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9938 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9939 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9940 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9941 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9942 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9943 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9944 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9945 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9946 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9947
cf8b84f4
JM
9948 if (from_vmentry &&
9949 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
2996fca0
JK
9950 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9951 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9952 } else {
9953 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9954 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9955 }
cf8b84f4
JM
9956 if (from_vmentry) {
9957 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9958 vmcs12->vm_entry_intr_info_field);
9959 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9960 vmcs12->vm_entry_exception_error_code);
9961 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9962 vmcs12->vm_entry_instruction_len);
9963 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9964 vmcs12->guest_interruptibility_info);
9965 } else {
9966 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9967 }
fe3ef05c 9968 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9969 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE
9970 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9971 vmcs12->guest_pending_dbg_exceptions);
9972 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9973 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9974
81dc01f7
WL
9975 if (nested_cpu_has_xsaves(vmcs12))
9976 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE
9977 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9978
f4124500 9979 exec_control = vmcs12->pin_based_vm_exec_control;
9314006d
PB
9980
9981 /* Preemption timer setting is only taken from vmcs01. */
705699a1 9982 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9314006d
PB
9983 exec_control |= vmcs_config.pin_based_exec_ctrl;
9984 if (vmx->hv_deadline_tsc == -1)
9985 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
705699a1 9986
9314006d 9987 /* Posted interrupts setting is only taken from vmcs12. */
705699a1
WV
9988 if (nested_cpu_has_posted_intr(vmcs12)) {
9989 /*
9990 * Note that we use L0's vector here and in
9991 * vmx_deliver_nested_posted_interrupt.
9992 */
9993 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9994 vmx->nested.pi_pending = false;
0bcf261c 9995 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6beb7bd5 9996 } else {
705699a1 9997 exec_control &= ~PIN_BASED_POSTED_INTR;
6beb7bd5 9998 }
705699a1 9999
f4124500 10000 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 10001
f4124500
JK
10002 vmx->nested.preemption_timer_expired = false;
10003 if (nested_cpu_has_preemption_timer(vmcs12))
10004 vmx_start_preemption_timer(vcpu);
0238ea91 10005
fe3ef05c
NHE
10006 /*
10007 * Whether page-faults are trapped is determined by a combination of
10008 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10009 * If enable_ept, L0 doesn't care about page faults and we should
10010 * set all of these to L1's desires. However, if !enable_ept, L0 does
10011 * care about (at least some) page faults, and because it is not easy
10012 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10013 * to exit on each and every L2 page fault. This is done by setting
10014 * MASK=MATCH=0 and (see below) EB.PF=1.
10015 * Note that below we don't need special code to set EB.PF beyond the
10016 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10017 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10018 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10019 *
10020 * A problem with this approach (when !enable_ept) is that L1 may be
10021 * injected with more page faults than it asked for. This could have
10022 * caused problems, but in practice existing hypervisors don't care.
10023 * To fix this, we will need to emulate the PFEC checking (on the L1
10024 * page tables), using walk_addr(), when injecting PFs to L1.
10025 */
10026 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10027 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10028 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10029 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10030
10031 if (cpu_has_secondary_exec_ctrls()) {
f4124500 10032 exec_control = vmx_secondary_exec_control(vmx);
e2821620 10033
fe3ef05c 10034 /* Take the following fields only from vmcs12 */
696dfd95 10035 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 10036 SECONDARY_EXEC_RDTSCP |
696dfd95 10037 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
dfa169bb 10038 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c 10039 if (nested_cpu_has(vmcs12,
03efce6f
BD
10040 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10041 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10042 ~SECONDARY_EXEC_ENABLE_PML;
10043 exec_control |= vmcs12_exec_ctrl;
10044 }
fe3ef05c 10045
608406e2
WV
10046 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10047 vmcs_write64(EOI_EXIT_BITMAP0,
10048 vmcs12->eoi_exit_bitmap0);
10049 vmcs_write64(EOI_EXIT_BITMAP1,
10050 vmcs12->eoi_exit_bitmap1);
10051 vmcs_write64(EOI_EXIT_BITMAP2,
10052 vmcs12->eoi_exit_bitmap2);
10053 vmcs_write64(EOI_EXIT_BITMAP3,
10054 vmcs12->eoi_exit_bitmap3);
10055 vmcs_write16(GUEST_INTR_STATUS,
10056 vmcs12->guest_intr_status);
10057 }
10058
6beb7bd5
JM
10059 /*
10060 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10061 * nested_get_vmcs12_pages will either fix it up or
10062 * remove the VM execution control.
10063 */
10064 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10065 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10066
fe3ef05c
NHE
10067 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10068 }
10069
10070
10071 /*
10072 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10073 * Some constant fields are set here by vmx_set_constant_host_state().
10074 * Other fields are different per CPU, and will be set later when
10075 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10076 */
a547c6db 10077 vmx_set_constant_host_state(vmx);
fe3ef05c 10078
83bafef1
JM
10079 /*
10080 * Set the MSR load/store lists to match L0's settings.
10081 */
10082 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10083 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10084 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10085 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10086 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10087
fe3ef05c
NHE
10088 /*
10089 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10090 * entry, but only if the current (host) sp changed from the value
10091 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10092 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10093 * here we just force the write to happen on entry.
10094 */
10095 vmx->host_rsp = 0;
10096
10097 exec_control = vmx_exec_control(vmx); /* L0's desires */
10098 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10099 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10100 exec_control &= ~CPU_BASED_TPR_SHADOW;
10101 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d 10102
6beb7bd5
JM
10103 /*
10104 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10105 * nested_get_vmcs12_pages can't fix it up, the illegal value
10106 * will result in a VM entry failure.
10107 */
a7c0b07d 10108 if (exec_control & CPU_BASED_TPR_SHADOW) {
6beb7bd5 10109 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
a7c0b07d
WL
10110 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10111 }
10112
fe3ef05c 10113 /*
3af18d9c 10114 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE
10115 * Rather, exit every time.
10116 */
fe3ef05c
NHE
10117 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10118 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10119
10120 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10121
10122 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10123 * bitwise-or of what L1 wants to trap for L2, and what we want to
10124 * trap. Note that CR0.TS also needs updating - we do this later.
10125 */
10126 update_exception_bitmap(vcpu);
10127 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10128 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10129
8049d651
NHE
10130 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10131 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10132 * bits are further modified by vmx_set_efer() below.
10133 */
f4124500 10134 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE
10135
10136 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10137 * emulated by vmx_set_efer(), below.
10138 */
2961e876 10139 vm_entry_controls_init(vmx,
8049d651
NHE
10140 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10141 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE
10142 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10143
cf8b84f4
JM
10144 if (from_vmentry &&
10145 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
fe3ef05c 10146 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02 10147 vcpu->arch.pat = vmcs12->guest_ia32_pat;
cf8b84f4 10148 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 10149 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
cf8b84f4 10150 }
fe3ef05c
NHE
10151
10152 set_cr4_guest_host_mask(vmx);
10153
cf8b84f4
JM
10154 if (from_vmentry &&
10155 vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
36be0b9d
PB
10156 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10157
27fc51b2
NHE
10158 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10159 vmcs_write64(TSC_OFFSET,
ea26e4ec 10160 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
27fc51b2 10161 else
ea26e4ec 10162 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
c95ba92a
PF
10163 if (kvm_has_tsc_control)
10164 decache_tsc_multiplier(vmx);
fe3ef05c
NHE
10165
10166 if (enable_vpid) {
10167 /*
5c614b35
WL
10168 * There is no direct mapping between vpid02 and vpid12, the
10169 * vpid02 is per-vCPU for L0 and reused while the value of
10170 * vpid12 is changed w/ one invvpid during nested vmentry.
10171 * The vpid12 is allocated by L1 for L2, so it will not
10172 * influence global bitmap(for vpid01 and vpid02 allocation)
10173 * even if spawn a lot of nested vCPUs.
fe3ef05c 10174 */
5c614b35
WL
10175 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10176 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10177 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10178 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10179 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10180 }
10181 } else {
10182 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10183 vmx_flush_tlb(vcpu);
10184 }
10185
fe3ef05c
NHE
10186 }
10187
1fb883bb
LP
10188 if (enable_pml) {
10189 /*
10190 * Conceptually we want to copy the PML address and index from
10191 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10192 * since we always flush the log on each vmexit, this happens
10193 * to be equivalent to simply resetting the fields in vmcs02.
10194 */
10195 ASSERT(vmx->pml_pg);
10196 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10197 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10198 }
10199
155a97a3 10200 if (nested_cpu_has_ept(vmcs12)) {
ae1e2d10
PB
10201 if (nested_ept_init_mmu_context(vcpu)) {
10202 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10203 return 1;
10204 }
fb6c8198
JM
10205 } else if (nested_cpu_has2(vmcs12,
10206 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10207 vmx_flush_tlb_ept_only(vcpu);
155a97a3
NHE
10208 }
10209
fe3ef05c 10210 /*
bd7e5b08
PB
10211 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10212 * bits which we consider mandatory enabled.
fe3ef05c
NHE
10213 * The CR0_READ_SHADOW is what L2 should have expected to read given
10214 * the specifications by L1; It's not enough to take
10215 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10216 * have more bits than L1 expected.
10217 */
10218 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10219 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10220
10221 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10222 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10223
cf8b84f4
JM
10224 if (from_vmentry &&
10225 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
5a6a9748
DM
10226 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10227 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10228 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10229 else
10230 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10231 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10232 vmx_set_efer(vcpu, vcpu->arch.efer);
10233
9ed38ffa 10234 /* Shadow page tables on either EPT or shadow page tables. */
7ad658b6 10235 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
9ed38ffa
LP
10236 entry_failure_code))
10237 return 1;
7ca29de2 10238
feaf0c7d
GN
10239 if (!enable_ept)
10240 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10241
3633cfc3
NHE
10242 /*
10243 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10244 */
10245 if (enable_ept) {
10246 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10247 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10248 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10249 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10250 }
10251
fe3ef05c
NHE
10252 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10253 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
ee146c1c 10254 return 0;
fe3ef05c
NHE
10255}
10256
ca0bde28 10257static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
cd232ad0 10258{
cd232ad0 10259 struct vcpu_vmx *vmx = to_vmx(vcpu);
7c177938 10260
6dfacadd 10261 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
ca0bde28
JM
10262 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10263 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
26539bd0 10264
ca0bde28
JM
10265 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10266 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
7c177938 10267
ca0bde28
JM
10268 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10269 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
f2b93280 10270
ca0bde28
JM
10271 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10272 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
e9ac033e 10273
c5f983f6
BD
10274 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10275 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10276
7c177938 10277 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
0115f9cb 10278 vmx->nested.nested_vmx_procbased_ctls_low,
b9c237bb 10279 vmx->nested.nested_vmx_procbased_ctls_high) ||
2e5b0bd9
JM
10280 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10281 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10282 vmx->nested.nested_vmx_secondary_ctls_low,
10283 vmx->nested.nested_vmx_secondary_ctls_high)) ||
7c177938 10284 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV
10285 vmx->nested.nested_vmx_pinbased_ctls_low,
10286 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 10287 !vmx_control_verify(vmcs12->vm_exit_controls,
0115f9cb 10288 vmx->nested.nested_vmx_exit_ctls_low,
b9c237bb 10289 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 10290 !vmx_control_verify(vmcs12->vm_entry_controls,
0115f9cb 10291 vmx->nested.nested_vmx_entry_ctls_low,
b9c237bb 10292 vmx->nested.nested_vmx_entry_ctls_high))
ca0bde28 10293 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
7c177938 10294
c7c2c709
JM
10295 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10296 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10297
3899152c 10298 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
1dc35dac 10299 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
ca0bde28
JM
10300 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10301 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10302
10303 return 0;
10304}
10305
10306static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10307 u32 *exit_qual)
10308{
10309 bool ia32e;
10310
10311 *exit_qual = ENTRY_FAIL_DEFAULT;
7c177938 10312
3899152c 10313 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
ca0bde28 10314 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
b428018a 10315 return 1;
ca0bde28
JM
10316
10317 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10318 vmcs12->vmcs_link_pointer != -1ull) {
10319 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
b428018a 10320 return 1;
7c177938
NHE
10321 }
10322
384bb783 10323 /*
cb0c8cda 10324 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK
10325 * are performed on the field for the IA32_EFER MSR:
10326 * - Bits reserved in the IA32_EFER MSR must be 0.
10327 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10328 * the IA-32e mode guest VM-exit control. It must also be identical
10329 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10330 * CR0.PG) is 1.
10331 */
ca0bde28
JM
10332 if (to_vmx(vcpu)->nested.nested_run_pending &&
10333 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
384bb783
JK
10334 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10335 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10336 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10337 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
ca0bde28 10338 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
b428018a 10339 return 1;
384bb783
JK
10340 }
10341
10342 /*
10343 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10344 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10345 * the values of the LMA and LME bits in the field must each be that of
10346 * the host address-space size VM-exit control.
10347 */
10348 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10349 ia32e = (vmcs12->vm_exit_controls &
10350 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10351 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10352 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
ca0bde28 10353 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
b428018a 10354 return 1;
ca0bde28
JM
10355 }
10356
10357 return 0;
10358}
10359
858e25c0
JM
10360static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10361{
10362 struct vcpu_vmx *vmx = to_vmx(vcpu);
10363 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10364 struct loaded_vmcs *vmcs02;
858e25c0
JM
10365 u32 msr_entry_idx;
10366 u32 exit_qual;
10367
10368 vmcs02 = nested_get_current_vmcs02(vmx);
10369 if (!vmcs02)
10370 return -ENOMEM;
10371
10372 enter_guest_mode(vcpu);
10373
10374 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10375 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10376
1279a6b1 10377 vmx_switch_vmcs(vcpu, vmcs02);
858e25c0
JM
10378 vmx_segment_cache_clear(vmx);
10379
10380 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10381 leave_guest_mode(vcpu);
1279a6b1 10382 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
858e25c0
JM
10383 nested_vmx_entry_failure(vcpu, vmcs12,
10384 EXIT_REASON_INVALID_STATE, exit_qual);
10385 return 1;
10386 }
10387
10388 nested_get_vmcs12_pages(vcpu, vmcs12);
10389
10390 msr_entry_idx = nested_vmx_load_msr(vcpu,
10391 vmcs12->vm_entry_msr_load_addr,
10392 vmcs12->vm_entry_msr_load_count);
10393 if (msr_entry_idx) {
10394 leave_guest_mode(vcpu);
1279a6b1 10395 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
858e25c0
JM
10396 nested_vmx_entry_failure(vcpu, vmcs12,
10397 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10398 return 1;
10399 }
10400
10401 vmcs12->launch_state = 1;
10402
10403 /*
10404 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10405 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10406 * returned as far as L1 is concerned. It will only return (and set
10407 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10408 */
10409 return 0;
10410}
10411
ca0bde28
JM
10412/*
10413 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10414 * for running an L2 nested guest.
10415 */
10416static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10417{
10418 struct vmcs12 *vmcs12;
10419 struct vcpu_vmx *vmx = to_vmx(vcpu);
ca0bde28
JM
10420 u32 exit_qual;
10421 int ret;
10422
10423 if (!nested_vmx_check_permission(vcpu))
10424 return 1;
10425
10426 if (!nested_vmx_check_vmcs12(vcpu))
10427 goto out;
10428
10429 vmcs12 = get_vmcs12(vcpu);
10430
10431 if (enable_shadow_vmcs)
10432 copy_shadow_to_vmcs12(vmx);
10433
10434 /*
10435 * The nested entry process starts with enforcing various prerequisites
10436 * on vmcs12 as required by the Intel SDM, and act appropriately when
10437 * they fail: As the SDM explains, some conditions should cause the
10438 * instruction to fail, while others will cause the instruction to seem
10439 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10440 * To speed up the normal (success) code path, we should avoid checking
10441 * for misconfigurations which will anyway be caught by the processor
10442 * when using the merged vmcs02.
10443 */
10444 if (vmcs12->launch_state == launch) {
10445 nested_vmx_failValid(vcpu,
10446 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10447 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10448 goto out;
10449 }
10450
10451 ret = check_vmentry_prereqs(vcpu, vmcs12);
10452 if (ret) {
10453 nested_vmx_failValid(vcpu, ret);
10454 goto out;
10455 }
10456
10457 /*
10458 * After this point, the trap flag no longer triggers a singlestep trap
10459 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10460 * This is not 100% correct; for performance reasons, we delegate most
10461 * of the checks on host state to the processor. If those fail,
10462 * the singlestep trap is missed.
10463 */
10464 skip_emulated_instruction(vcpu);
10465
10466 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10467 if (ret) {
10468 nested_vmx_entry_failure(vcpu, vmcs12,
10469 EXIT_REASON_INVALID_STATE, exit_qual);
10470 return 1;
384bb783
JK
10471 }
10472
7c177938
NHE
10473 /*
10474 * We're finally done with prerequisite checking, and can start with
10475 * the nested entry.
10476 */
10477
858e25c0
JM
10478 ret = enter_vmx_non_root_mode(vcpu, true);
10479 if (ret)
10480 return ret;
ff651cb6 10481
6dfacadd 10482 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 10483 return kvm_vcpu_halt(vcpu);
6dfacadd 10484
7af40ad3
JK
10485 vmx->nested.nested_run_pending = 1;
10486
cd232ad0 10487 return 1;
eb277562
KH
10488
10489out:
6affcbed 10490 return kvm_skip_emulated_instruction(vcpu);
cd232ad0
NHE
10491}
10492
4704d0be
NHE
10493/*
10494 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10495 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10496 * This function returns the new value we should put in vmcs12.guest_cr0.
10497 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10498 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10499 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10500 * didn't trap the bit, because if L1 did, so would L0).
10501 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10502 * been modified by L2, and L1 knows it. So just leave the old value of
10503 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10504 * isn't relevant, because if L0 traps this bit it can set it to anything.
10505 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10506 * changed these bits, and therefore they need to be updated, but L0
10507 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10508 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10509 */
10510static inline unsigned long
10511vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10512{
10513 return
10514 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10515 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10516 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10517 vcpu->arch.cr0_guest_owned_bits));
10518}
10519
10520static inline unsigned long
10521vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10522{
10523 return
10524 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10525 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10526 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10527 vcpu->arch.cr4_guest_owned_bits));
10528}
10529
5f3d5799
JK
10530static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10531 struct vmcs12 *vmcs12)
10532{
10533 u32 idt_vectoring;
10534 unsigned int nr;
10535
851eb667 10536 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK
10537 nr = vcpu->arch.exception.nr;
10538 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10539
10540 if (kvm_exception_is_soft(nr)) {
10541 vmcs12->vm_exit_instruction_len =
10542 vcpu->arch.event_exit_inst_len;
10543 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10544 } else
10545 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10546
10547 if (vcpu->arch.exception.has_error_code) {
10548 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10549 vmcs12->idt_vectoring_error_code =
10550 vcpu->arch.exception.error_code;
10551 }
10552
10553 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 10554 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK
10555 vmcs12->idt_vectoring_info_field =
10556 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10557 } else if (vcpu->arch.interrupt.pending) {
10558 nr = vcpu->arch.interrupt.nr;
10559 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10560
10561 if (vcpu->arch.interrupt.soft) {
10562 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10563 vmcs12->vm_entry_instruction_len =
10564 vcpu->arch.event_exit_inst_len;
10565 } else
10566 idt_vectoring |= INTR_TYPE_EXT_INTR;
10567
10568 vmcs12->idt_vectoring_info_field = idt_vectoring;
10569 }
10570}
10571
b6b8a145
JK
10572static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10573{
10574 struct vcpu_vmx *vmx = to_vmx(vcpu);
10575
acc9ab60
WL
10576 if (vcpu->arch.exception.pending ||
10577 vcpu->arch.nmi_injected ||
10578 vcpu->arch.interrupt.pending)
10579 return -EBUSY;
10580
f4124500
JK
10581 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10582 vmx->nested.preemption_timer_expired) {
10583 if (vmx->nested.nested_run_pending)
10584 return -EBUSY;
10585 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10586 return 0;
10587 }
10588
b6b8a145 10589 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
acc9ab60 10590 if (vmx->nested.nested_run_pending)
b6b8a145
JK
10591 return -EBUSY;
10592 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10593 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10594 INTR_INFO_VALID_MASK, 0);
10595 /*
10596 * The NMI-triggered VM exit counts as injection:
10597 * clear this one and block further NMIs.
10598 */
10599 vcpu->arch.nmi_pending = 0;
10600 vmx_set_nmi_mask(vcpu, true);
10601 return 0;
10602 }
10603
10604 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10605 nested_exit_on_intr(vcpu)) {
10606 if (vmx->nested.nested_run_pending)
10607 return -EBUSY;
10608 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 10609 return 0;
b6b8a145
JK
10610 }
10611
6342c50a
DH
10612 vmx_complete_nested_posted_interrupt(vcpu);
10613 return 0;
b6b8a145
JK
10614}
10615
f4124500
JK
10616static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10617{
10618 ktime_t remaining =
10619 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10620 u64 value;
10621
10622 if (ktime_to_ns(remaining) <= 0)
10623 return 0;
10624
10625 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10626 do_div(value, 1000000);
10627 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10628}
10629
4704d0be 10630/*
cf8b84f4
JM
10631 * Update the guest state fields of vmcs12 to reflect changes that
10632 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10633 * VM-entry controls is also updated, since this is really a guest
10634 * state bit.)
4704d0be 10635 */
cf8b84f4 10636static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be 10637{
4704d0be
NHE
10638 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10639 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10640
4704d0be
NHE
10641 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10642 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10643 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10644
10645 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10646 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10647 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10648 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10649 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10650 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10651 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10652 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10653 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10654 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10655 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10656 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10657 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10658 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10659 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10660 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10661 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10662 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10663 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10664 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10665 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10666 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10667 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10668 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10669 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10670 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10671 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10672 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10673 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10674 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10675 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10676 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10677 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10678 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10679 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10680 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10681
4704d0be
NHE
10682 vmcs12->guest_interruptibility_info =
10683 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10684 vmcs12->guest_pending_dbg_exceptions =
10685 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK
10686 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10687 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10688 else
10689 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 10690
f4124500
JK
10691 if (nested_cpu_has_preemption_timer(vmcs12)) {
10692 if (vmcs12->vm_exit_controls &
10693 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10694 vmcs12->vmx_preemption_timer_value =
10695 vmx_get_preemption_timer_value(vcpu);
10696 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10697 }
7854cbca 10698
3633cfc3
NHE
10699 /*
10700 * In some cases (usually, nested EPT), L2 is allowed to change its
10701 * own CR3 without exiting. If it has changed it, we must keep it.
10702 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10703 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10704 *
10705 * Additionally, restore L2's PDPTR to vmcs12.
10706 */
10707 if (enable_ept) {
f3531054 10708 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
3633cfc3
NHE
10709 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10710 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10711 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10712 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10713 }
10714
d281e13b 10715 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
119a9c01 10716
608406e2
WV
10717 if (nested_cpu_has_vid(vmcs12))
10718 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10719
c18911a2
JK
10720 vmcs12->vm_entry_controls =
10721 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 10722 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 10723
2996fca0
JK
10724 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10725 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10726 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10727 }
10728
4704d0be
NHE
10729 /* TODO: These cannot have changed unless we have MSR bitmaps and
10730 * the relevant bit asks not to trap the change */
b8c07d55 10731 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 10732 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK
10733 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10734 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE
10735 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10736 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10737 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
a87036ad 10738 if (kvm_mpx_supported())
36be0b9d 10739 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
cf8b84f4
JM
10740}
10741
10742/*
10743 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10744 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10745 * and this function updates it to reflect the changes to the guest state while
10746 * L2 was running (and perhaps made some exits which were handled directly by L0
10747 * without going back to L1), and to reflect the exit reason.
10748 * Note that we do not have to copy here all VMCS fields, just those that
10749 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10750 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10751 * which already writes to vmcs12 directly.
10752 */
10753static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10754 u32 exit_reason, u32 exit_intr_info,
10755 unsigned long exit_qualification)
10756{
10757 /* update guest state fields: */
10758 sync_vmcs12(vcpu, vmcs12);
4704d0be
NHE
10759
10760 /* update exit information fields: */
10761
533558bc
JK
10762 vmcs12->vm_exit_reason = exit_reason;
10763 vmcs12->exit_qualification = exit_qualification;
4704d0be 10764
533558bc 10765 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK
10766 if ((vmcs12->vm_exit_intr_info &
10767 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10768 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10769 vmcs12->vm_exit_intr_error_code =
10770 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 10771 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE
10772 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10773 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10774
5f3d5799
JK
10775 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10776 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10777 * instead of reading the real value. */
4704d0be 10778 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK
10779
10780 /*
10781 * Transfer the event that L0 or L1 may wanted to inject into
10782 * L2 to IDT_VECTORING_INFO_FIELD.
10783 */
10784 vmcs12_save_pending_event(vcpu, vmcs12);
10785 }
10786
10787 /*
10788 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10789 * preserved above and would only end up incorrectly in L1.
10790 */
10791 vcpu->arch.nmi_injected = false;
10792 kvm_clear_exception_queue(vcpu);
10793 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE
10794}
10795
10796/*
10797 * A part of what we need to when the nested L2 guest exits and we want to
10798 * run its L1 parent, is to reset L1's guest state to the host state specified
10799 * in vmcs12.
10800 * This function is to be called not only on normal nested exit, but also on
10801 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10802 * Failures During or After Loading Guest State").
10803 * This function should be called when the active VMCS is L1's (vmcs01).
10804 */
733568f9
JK
10805static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10806 struct vmcs12 *vmcs12)
4704d0be 10807{
21feb4eb 10808 struct kvm_segment seg;
ca0bde28 10809 u32 entry_failure_code;
21feb4eb 10810
4704d0be
NHE
10811 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10812 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10813 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE
10814 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10815 else
10816 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10817 vmx_set_efer(vcpu, vcpu->arch.efer);
10818
10819 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10820 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10821 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE
10822 /*
10823 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
bd7e5b08
PB
10824 * actually changed, because vmx_set_cr0 refers to efer set above.
10825 *
10826 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10827 * (KVM doesn't change it);
4704d0be 10828 */
bd7e5b08 10829 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
9e3e4dbf 10830 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be 10831
bd7e5b08 10832 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
4704d0be
NHE
10833 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10834 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10835
29bf08f1 10836 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10837
1dc35dac
LP
10838 /*
10839 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10840 * couldn't have changed.
10841 */
10842 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10843 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
4704d0be 10844
feaf0c7d
GN
10845 if (!enable_ept)
10846 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10847
4704d0be
NHE
10848 if (enable_vpid) {
10849 /*
10850 * Trivially support vpid by letting L2s share their parent
10851 * L1's vpid. TODO: move to a more elaborate solution, giving
10852 * each L2 its own vpid and exposing the vpid feature to L1.
10853 */
10854 vmx_flush_tlb(vcpu);
10855 }
10856
10857
10858 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10859 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10860 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10861 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10862 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10863
36be0b9d
PB
10864 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10865 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10866 vmcs_write64(GUEST_BNDCFGS, 0);
10867
44811c02 10868 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10869 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK
10870 vcpu->arch.pat = vmcs12->host_ia32_pat;
10871 }
4704d0be
NHE
10872 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10873 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10874 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10875
21feb4eb
ACL
10876 /* Set L1 segment info according to Intel SDM
10877 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10878 seg = (struct kvm_segment) {
10879 .base = 0,
10880 .limit = 0xFFFFFFFF,
10881 .selector = vmcs12->host_cs_selector,
10882 .type = 11,
10883 .present = 1,
10884 .s = 1,
10885 .g = 1
10886 };
10887 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10888 seg.l = 1;
10889 else
10890 seg.db = 1;
10891 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10892 seg = (struct kvm_segment) {
10893 .base = 0,
10894 .limit = 0xFFFFFFFF,
10895 .type = 3,
10896 .present = 1,
10897 .s = 1,
10898 .db = 1,
10899 .g = 1
10900 };
10901 seg.selector = vmcs12->host_ds_selector;
10902 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10903 seg.selector = vmcs12->host_es_selector;
10904 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10905 seg.selector = vmcs12->host_ss_selector;
10906 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10907 seg.selector = vmcs12->host_fs_selector;
10908 seg.base = vmcs12->host_fs_base;
10909 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10910 seg.selector = vmcs12->host_gs_selector;
10911 seg.base = vmcs12->host_gs_base;
10912 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10913 seg = (struct kvm_segment) {
205befd9 10914 .base = vmcs12->host_tr_base,
21feb4eb
ACL
10915 .limit = 0x67,
10916 .selector = vmcs12->host_tr_selector,
10917 .type = 11,
10918 .present = 1
10919 };
10920 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10921
503cd0c5
JK
10922 kvm_set_dr(vcpu, 7, 0x400);
10923 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 10924
3af18d9c
WV
10925 if (cpu_has_vmx_msr_bitmap())
10926 vmx_set_msr_bitmap(vcpu);
10927
ff651cb6
WV
10928 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10929 vmcs12->vm_exit_msr_load_count))
10930 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE
10931}
10932
10933/*
10934 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10935 * and modify vmcs12 to make it see what it would expect to see there if
10936 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10937 */
533558bc
JK
10938static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10939 u32 exit_intr_info,
10940 unsigned long exit_qualification)
4704d0be
NHE
10941{
10942 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 10943 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
cf3215d9 10944 u32 vm_inst_error = 0;
4704d0be 10945
5f3d5799
JK
10946 /* trying to cancel vmlaunch/vmresume is a bug */
10947 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10948
4704d0be 10949 leave_guest_mode(vcpu);
533558bc
JK
10950 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10951 exit_qualification);
4704d0be 10952
ff651cb6
WV
10953 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10954 vmcs12->vm_exit_msr_store_count))
10955 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10956
cf3215d9
JM
10957 if (unlikely(vmx->fail))
10958 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
10959
1279a6b1 10960 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
f3380ca5 10961
77b0f5d6
BD
10962 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10963 && nested_exit_intr_ack_set(vcpu)) {
10964 int irq = kvm_cpu_get_interrupt(vcpu);
10965 WARN_ON(irq < 0);
10966 vmcs12->vm_exit_intr_info = irq |
10967 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10968 }
10969
542060ea
JK
10970 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10971 vmcs12->exit_qualification,
10972 vmcs12->idt_vectoring_info_field,
10973 vmcs12->vm_exit_intr_info,
10974 vmcs12->vm_exit_intr_error_code,
10975 KVM_ISA_VMX);
4704d0be 10976
8391ce44
PB
10977 vm_entry_controls_reset_shadow(vmx);
10978 vm_exit_controls_reset_shadow(vmx);
36c3cc42
JK
10979 vmx_segment_cache_clear(vmx);
10980
4704d0be
NHE
10981 /* if no vmcs02 cache requested, remove the one we used */
10982 if (VMCS02_POOL_SIZE == 0)
10983 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10984
10985 load_vmcs12_host_state(vcpu, vmcs12);
10986
9314006d 10987 /* Update any VMCS fields that might have changed while L2 ran */
83bafef1
JM
10988 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10989 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
ea26e4ec 10990 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
9314006d
PB
10991 if (vmx->hv_deadline_tsc == -1)
10992 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10993 PIN_BASED_VMX_PREEMPTION_TIMER);
10994 else
10995 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10996 PIN_BASED_VMX_PREEMPTION_TIMER);
c95ba92a
PF
10997 if (kvm_has_tsc_control)
10998 decache_tsc_multiplier(vmx);
4704d0be 10999
dccbfcf5
RK
11000 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11001 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11002 vmx_set_virtual_x2apic_mode(vcpu,
11003 vcpu->arch.apic_base & X2APIC_ENABLE);
fb6c8198
JM
11004 } else if (!nested_cpu_has_ept(vmcs12) &&
11005 nested_cpu_has2(vmcs12,
11006 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11007 vmx_flush_tlb_ept_only(vcpu);
dccbfcf5 11008 }
4704d0be
NHE
11009
11010 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11011 vmx->host_rsp = 0;
11012
11013 /* Unpin physical memory we referred to in vmcs02 */
11014 if (vmx->nested.apic_access_page) {
11015 nested_release_page(vmx->nested.apic_access_page);
48d89b92 11016 vmx->nested.apic_access_page = NULL;
4704d0be 11017 }
a7c0b07d
WL
11018 if (vmx->nested.virtual_apic_page) {
11019 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 11020 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 11021 }
705699a1
WV
11022 if (vmx->nested.pi_desc_page) {
11023 kunmap(vmx->nested.pi_desc_page);
11024 nested_release_page(vmx->nested.pi_desc_page);
11025 vmx->nested.pi_desc_page = NULL;
11026 vmx->nested.pi_desc = NULL;
11027 }
4704d0be 11028
38b99173
TC
11029 /*
11030 * We are now running in L2, mmu_notifier will force to reload the
11031 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11032 */
c83b6d15 11033 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
38b99173 11034
4704d0be
NHE
11035 /*
11036 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11037 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11038 * success or failure flag accordingly.
11039 */
11040 if (unlikely(vmx->fail)) {
11041 vmx->fail = 0;
cf3215d9 11042 nested_vmx_failValid(vcpu, vm_inst_error);
4704d0be
NHE
11043 } else
11044 nested_vmx_succeed(vcpu);
012f83cb
AG
11045 if (enable_shadow_vmcs)
11046 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK
11047
11048 /* in case we halted in L2 */
11049 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE
11050}
11051
42124925
JK
11052/*
11053 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11054 */
11055static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11056{
2f707d97
WL
11057 if (is_guest_mode(vcpu)) {
11058 to_vmx(vcpu)->nested.nested_run_pending = 0;
533558bc 11059 nested_vmx_vmexit(vcpu, -1, 0, 0);
2f707d97 11060 }
42124925
JK
11061 free_nested(to_vmx(vcpu));
11062}
11063
7c177938
NHE
11064/*
11065 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11066 * 23.7 "VM-entry failures during or after loading guest state" (this also
11067 * lists the acceptable exit-reason and exit-qualification parameters).
11068 * It should only be called before L2 actually succeeded to run, and when
11069 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11070 */
11071static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11072 struct vmcs12 *vmcs12,
11073 u32 reason, unsigned long qualification)
11074{
11075 load_vmcs12_host_state(vcpu, vmcs12);
11076 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11077 vmcs12->exit_qualification = qualification;
11078 nested_vmx_succeed(vcpu);
012f83cb
AG
11079 if (enable_shadow_vmcs)
11080 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE
11081}
11082
8a76d7f2
JR
11083static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11084 struct x86_instruction_info *info,
11085 enum x86_intercept_stage stage)
11086{
11087 return X86EMUL_CONTINUE;
11088}
11089
64672c95
YJ
11090#ifdef CONFIG_X86_64
11091/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11092static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11093 u64 divisor, u64 *result)
11094{
11095 u64 low = a << shift, high = a >> (64 - shift);
11096
11097 /* To avoid the overflow on divq */
11098 if (high >= divisor)
11099 return 1;
11100
11101 /* Low hold the result, high hold rem which is discarded */
11102 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11103 "rm" (divisor), "0" (low), "1" (high));
11104 *result = low;
11105
11106 return 0;
11107}
11108
11109static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11110{
11111 struct vcpu_vmx *vmx = to_vmx(vcpu);
9175d2e9
PB
11112 u64 tscl = rdtsc();
11113 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11114 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
64672c95
YJ
11115
11116 /* Convert to host delta tsc if tsc scaling is enabled */
11117 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11118 u64_shl_div_u64(delta_tsc,
11119 kvm_tsc_scaling_ratio_frac_bits,
11120 vcpu->arch.tsc_scaling_ratio,
11121 &delta_tsc))
11122 return -ERANGE;
11123
11124 /*
11125 * If the delta tsc can't fit in the 32 bit after the multi shift,
11126 * we can't use the preemption timer.
11127 * It's possible that it fits on later vmentries, but checking
11128 * on every vmentry is costly so we just use an hrtimer.
11129 */
11130 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11131 return -ERANGE;
11132
11133 vmx->hv_deadline_tsc = tscl + delta_tsc;
11134 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11135 PIN_BASED_VMX_PREEMPTION_TIMER);
11136 return 0;
11137}
11138
11139static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11140{
11141 struct vcpu_vmx *vmx = to_vmx(vcpu);
11142 vmx->hv_deadline_tsc = -1;
11143 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11144 PIN_BASED_VMX_PREEMPTION_TIMER);
11145}
11146#endif
11147
48d89b92 11148static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 11149{
b4a2d31d
RK
11150 if (ple_gap)
11151 shrink_ple_window(vcpu);
ae97a3b8
RK
11152}
11153
843e4330
KH
11154static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11155 struct kvm_memory_slot *slot)
11156{
11157 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11158 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11159}
11160
11161static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11162 struct kvm_memory_slot *slot)
11163{
11164 kvm_mmu_slot_set_dirty(kvm, slot);
11165}
11166
11167static void vmx_flush_log_dirty(struct kvm *kvm)
11168{
11169 kvm_flush_pml_buffers(kvm);
11170}
11171
c5f983f6
BD
11172static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11173{
11174 struct vmcs12 *vmcs12;
11175 struct vcpu_vmx *vmx = to_vmx(vcpu);
11176 gpa_t gpa;
11177 struct page *page = NULL;
11178 u64 *pml_address;
11179
11180 if (is_guest_mode(vcpu)) {
11181 WARN_ON_ONCE(vmx->nested.pml_full);
11182
11183 /*
11184 * Check if PML is enabled for the nested guest.
11185 * Whether eptp bit 6 is set is already checked
11186 * as part of A/D emulation.
11187 */
11188 vmcs12 = get_vmcs12(vcpu);
11189 if (!nested_cpu_has_pml(vmcs12))
11190 return 0;
11191
4769886b 11192 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD
11193 vmx->nested.pml_full = true;
11194 return 1;
11195 }
11196
11197 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11198
11199 page = nested_get_page(vcpu, vmcs12->pml_address);
11200 if (!page)
11201 return 0;
11202
11203 pml_address = kmap(page);
11204 pml_address[vmcs12->guest_pml_index--] = gpa;
11205 kunmap(page);
11206 nested_release_page_clean(page);
11207 }
11208
11209 return 0;
11210}
11211
843e4330
KH
11212static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11213 struct kvm_memory_slot *memslot,
11214 gfn_t offset, unsigned long mask)
11215{
11216 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11217}
11218
bf9f6ac8
FW
11219/*
11220 * This routine does the following things for vCPU which is going
11221 * to be blocked if VT-d PI is enabled.
11222 * - Store the vCPU to the wakeup list, so when interrupts happen
11223 * we can find the right vCPU to wake up.
11224 * - Change the Posted-interrupt descriptor as below:
11225 * 'NDST' <-- vcpu->pre_pcpu
11226 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11227 * - If 'ON' is set during this process, which means at least one
11228 * interrupt is posted for this vCPU, we cannot block it, in
11229 * this case, return 1, otherwise, return 0.
11230 *
11231 */
bc22512b 11232static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8
FW
11233{
11234 unsigned long flags;
11235 unsigned int dest;
11236 struct pi_desc old, new;
11237 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11238
11239 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
11240 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11241 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW
11242 return 0;
11243
11244 vcpu->pre_pcpu = vcpu->cpu;
11245 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11246 vcpu->pre_pcpu), flags);
11247 list_add_tail(&vcpu->blocked_vcpu_list,
11248 &per_cpu(blocked_vcpu_on_cpu,
11249 vcpu->pre_pcpu));
11250 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11251 vcpu->pre_pcpu), flags);
11252
11253 do {
11254 old.control = new.control = pi_desc->control;
11255
11256 /*
11257 * We should not block the vCPU if
11258 * an interrupt is posted for it.
11259 */
11260 if (pi_test_on(pi_desc) == 1) {
11261 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11262 vcpu->pre_pcpu), flags);
11263 list_del(&vcpu->blocked_vcpu_list);
11264 spin_unlock_irqrestore(
11265 &per_cpu(blocked_vcpu_on_cpu_lock,
11266 vcpu->pre_pcpu), flags);
11267 vcpu->pre_pcpu = -1;
11268
11269 return 1;
11270 }
11271
11272 WARN((pi_desc->sn == 1),
11273 "Warning: SN field of posted-interrupts "
11274 "is set before blocking\n");
11275
11276 /*
11277 * Since vCPU can be preempted during this process,
11278 * vcpu->cpu could be different with pre_pcpu, we
11279 * need to set pre_pcpu as the destination of wakeup
11280 * notification event, then we can find the right vCPU
11281 * to wakeup in wakeup handler if interrupts happen
11282 * when the vCPU is in blocked state.
11283 */
11284 dest = cpu_physical_id(vcpu->pre_pcpu);
11285
11286 if (x2apic_enabled())
11287 new.ndst = dest;
11288 else
11289 new.ndst = (dest << 8) & 0xFF00;
11290
11291 /* set 'NV' to 'wakeup vector' */
11292 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11293 } while (cmpxchg(&pi_desc->control, old.control,
11294 new.control) != old.control);
11295
11296 return 0;
11297}
11298
bc22512b
YJ
11299static int vmx_pre_block(struct kvm_vcpu *vcpu)
11300{
11301 if (pi_pre_block(vcpu))
11302 return 1;
11303
64672c95
YJ
11304 if (kvm_lapic_hv_timer_in_use(vcpu))
11305 kvm_lapic_switch_to_sw_timer(vcpu);
11306
bc22512b
YJ
11307 return 0;
11308}
11309
11310static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8
FW
11311{
11312 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11313 struct pi_desc old, new;
11314 unsigned int dest;
11315 unsigned long flags;
11316
11317 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
11318 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11319 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW
11320 return;
11321
11322 do {
11323 old.control = new.control = pi_desc->control;
11324
11325 dest = cpu_physical_id(vcpu->cpu);
11326
11327 if (x2apic_enabled())
11328 new.ndst = dest;
11329 else
11330 new.ndst = (dest << 8) & 0xFF00;
11331
11332 /* Allow posting non-urgent interrupts */
11333 new.sn = 0;
11334
11335 /* set 'NV' to 'notification vector' */
11336 new.nv = POSTED_INTR_VECTOR;
11337 } while (cmpxchg(&pi_desc->control, old.control,
11338 new.control) != old.control);
11339
11340 if(vcpu->pre_pcpu != -1) {
11341 spin_lock_irqsave(
11342 &per_cpu(blocked_vcpu_on_cpu_lock,
11343 vcpu->pre_pcpu), flags);
11344 list_del(&vcpu->blocked_vcpu_list);
11345 spin_unlock_irqrestore(
11346 &per_cpu(blocked_vcpu_on_cpu_lock,
11347 vcpu->pre_pcpu), flags);
11348 vcpu->pre_pcpu = -1;
11349 }
11350}
11351
bc22512b
YJ
11352static void vmx_post_block(struct kvm_vcpu *vcpu)
11353{
64672c95
YJ
11354 if (kvm_x86_ops->set_hv_timer)
11355 kvm_lapic_switch_to_hv_timer(vcpu);
11356
bc22512b
YJ
11357 pi_post_block(vcpu);
11358}
11359
efc64404
FW
11360/*
11361 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11362 *
11363 * @kvm: kvm
11364 * @host_irq: host irq of the interrupt
11365 * @guest_irq: gsi of the interrupt
11366 * @set: set or unset PI
11367 * returns 0 on success, < 0 on failure
11368 */
11369static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11370 uint32_t guest_irq, bool set)
11371{
11372 struct kvm_kernel_irq_routing_entry *e;
11373 struct kvm_irq_routing_table *irq_rt;
11374 struct kvm_lapic_irq irq;
11375 struct kvm_vcpu *vcpu;
11376 struct vcpu_data vcpu_info;
11377 int idx, ret = -EINVAL;
11378
11379 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ
11380 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11381 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW
11382 return 0;
11383
11384 idx = srcu_read_lock(&kvm->irq_srcu);
11385 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11386 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11387
11388 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11389 if (e->type != KVM_IRQ_ROUTING_MSI)
11390 continue;
11391 /*
11392 * VT-d PI cannot support posting multicast/broadcast
11393 * interrupts to a vCPU, we still use interrupt remapping
11394 * for these kind of interrupts.
11395 *
11396 * For lowest-priority interrupts, we only support
11397 * those with single CPU as the destination, e.g. user
11398 * configures the interrupts via /proc/irq or uses
11399 * irqbalance to make the interrupts single-CPU.
11400 *
11401 * We will support full lowest-priority interrupt later.
11402 */
11403
37131313 11404 kvm_set_msi_irq(kvm, e, &irq);
23a1c257
FW
11405 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11406 /*
11407 * Make sure the IRTE is in remapped mode if
11408 * we don't handle it in posted mode.
11409 */
11410 ret = irq_set_vcpu_affinity(host_irq, NULL);
11411 if (ret < 0) {
11412 printk(KERN_INFO
11413 "failed to back to remapped mode, irq: %u\n",
11414 host_irq);
11415 goto out;
11416 }
11417
efc64404 11418 continue;
23a1c257 11419 }
efc64404
FW
11420
11421 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11422 vcpu_info.vector = irq.vector;
11423
b6ce9780 11424 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
efc64404
FW
11425 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11426
11427 if (set)
11428 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11429 else {
11430 /* suppress notification event before unposting */
11431 pi_set_sn(vcpu_to_pi_desc(vcpu));
11432 ret = irq_set_vcpu_affinity(host_irq, NULL);
11433 pi_clear_sn(vcpu_to_pi_desc(vcpu));
11434 }
11435
11436 if (ret < 0) {
11437 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11438 __func__);
11439 goto out;
11440 }
11441 }
11442
11443 ret = 0;
11444out:
11445 srcu_read_unlock(&kvm->irq_srcu, idx);
11446 return ret;
11447}
11448
c45dcc71
AR
11449static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11450{
11451 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11452 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11453 FEATURE_CONTROL_LMCE;
11454 else
11455 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11456 ~FEATURE_CONTROL_LMCE;
11457}
11458
404f6aac 11459static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK
11460 .cpu_has_kvm_support = cpu_has_kvm_support,
11461 .disabled_by_bios = vmx_disabled_by_bios,
11462 .hardware_setup = hardware_setup,
11463 .hardware_unsetup = hardware_unsetup,
002c7f7c 11464 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK
11465 .hardware_enable = hardware_enable,
11466 .hardware_disable = hardware_disable,
04547156 11467 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 11468 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK
11469
11470 .vcpu_create = vmx_create_vcpu,
11471 .vcpu_free = vmx_free_vcpu,
04d2cc77 11472 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 11473
04d2cc77 11474 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK
11475 .vcpu_load = vmx_vcpu_load,
11476 .vcpu_put = vmx_vcpu_put,
11477
a96036b8 11478 .update_bp_intercept = update_exception_bitmap,
6aa8b732
AK
11479 .get_msr = vmx_get_msr,
11480 .set_msr = vmx_set_msr,
11481 .get_segment_base = vmx_get_segment_base,
11482 .get_segment = vmx_get_segment,
11483 .set_segment = vmx_set_segment,
2e4d2653 11484 .get_cpl = vmx_get_cpl,
6aa8b732 11485 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 11486 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 11487 .decache_cr3 = vmx_decache_cr3,
25c4c276 11488 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 11489 .set_cr0 = vmx_set_cr0,
6aa8b732
AK
11490 .set_cr3 = vmx_set_cr3,
11491 .set_cr4 = vmx_set_cr4,
6aa8b732 11492 .set_efer = vmx_set_efer,
6aa8b732
AK
11493 .get_idt = vmx_get_idt,
11494 .set_idt = vmx_set_idt,
11495 .get_gdt = vmx_get_gdt,
11496 .set_gdt = vmx_set_gdt,
73aaf249
JK
11497 .get_dr6 = vmx_get_dr6,
11498 .set_dr6 = vmx_set_dr6,
020df079 11499 .set_dr7 = vmx_set_dr7,
81908bf4 11500 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 11501 .cache_reg = vmx_cache_reg,
6aa8b732
AK
11502 .get_rflags = vmx_get_rflags,
11503 .set_rflags = vmx_set_rflags,
be94f6b7
HH
11504
11505 .get_pkru = vmx_get_pkru,
11506
6aa8b732 11507 .tlb_flush = vmx_flush_tlb,
6aa8b732 11508
6aa8b732 11509 .run = vmx_vcpu_run,
6062d012 11510 .handle_exit = vmx_handle_exit,
6aa8b732 11511 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC
11512 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11513 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 11514 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 11515 .set_irq = vmx_inject_irq,
95ba8273 11516 .set_nmi = vmx_inject_nmi,
298101da 11517 .queue_exception = vmx_queue_exception,
b463a6f7 11518 .cancel_injection = vmx_cancel_injection,
78646121 11519 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 11520 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK
11521 .get_nmi_mask = vmx_get_nmi_mask,
11522 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN
11523 .enable_nmi_window = enable_nmi_window,
11524 .enable_irq_window = enable_irq_window,
11525 .update_cr8_intercept = update_cr8_intercept,
8d14695f 11526 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 11527 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb
AS
11528 .get_enable_apicv = vmx_get_enable_apicv,
11529 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 11530 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 11531 .apicv_post_state_restore = vmx_apicv_post_state_restore,
c7c9c56c
YZ
11532 .hwapic_irr_update = vmx_hwapic_irr_update,
11533 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ
11534 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11535 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 11536
cbc94022 11537 .set_tss_addr = vmx_set_tss_addr,
67253af5 11538 .get_tdp_level = get_ept_level,
4b12f0de 11539 .get_mt_mask = vmx_get_mt_mask,
229456fc 11540
586f9607 11541 .get_exit_info = vmx_get_exit_info,
586f9607 11542
17cc3935 11543 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY
11544
11545 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY
11546
11547 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 11548 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR
11549
11550 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY
11551
11552 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA
11553
11554 .write_tsc_offset = vmx_write_tsc_offset,
1c97f0a0
JR
11555
11556 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR
11557
11558 .check_intercept = vmx_check_intercept,
a547c6db 11559 .handle_external_intr = vmx_handle_external_intr,
da8999d3 11560 .mpx_supported = vmx_mpx_supported,
55412b2e 11561 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK
11562
11563 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK
11564
11565 .sched_in = vmx_sched_in,
843e4330
KH
11566
11567 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11568 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11569 .flush_log_dirty = vmx_flush_log_dirty,
11570 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 11571 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 11572
bf9f6ac8
FW
11573 .pre_block = vmx_pre_block,
11574 .post_block = vmx_post_block,
11575
25462f7f 11576 .pmu_ops = &intel_pmu_ops,
efc64404
FW
11577
11578 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ
11579
11580#ifdef CONFIG_X86_64
11581 .set_hv_timer = vmx_set_hv_timer,
11582 .cancel_hv_timer = vmx_cancel_hv_timer,
11583#endif
c45dcc71
AR
11584
11585 .setup_mce = vmx_setup_mce,
6aa8b732
AK
11586};
11587
11588static int __init vmx_init(void)
11589{
34a1cd60
TC
11590 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11591 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 11592 if (r)
34a1cd60 11593 return r;
25c5f225 11594
2965faa5 11595#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY
11596 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11597 crash_vmclear_local_loaded_vmcss);
11598#endif
11599
fdef3ad1 11600 return 0;
6aa8b732
AK
11601}
11602
11603static void __exit vmx_exit(void)
11604{
2965faa5 11605#ifdef CONFIG_KEXEC_CORE
3b63a43f 11606 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY
11607 synchronize_rcu();
11608#endif
11609
cb498ea2 11610 kvm_exit();
6aa8b732
AK
11611}
11612
11613module_init(vmx_init)
11614module_exit(vmx_exit)