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kvm: nVMX: Fix nested_vmx_check_msr_bitmap_controls
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
d62caabb 22#include "lapic.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732 25#include <linux/module.h>
9d8f549d 26#include <linux/kernel.h>
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27#include <linux/mm.h>
28#include <linux/highmem.h>
e8edc6e0 29#include <linux/sched.h>
c7addb90 30#include <linux/moduleparam.h>
e9bda3b3 31#include <linux/mod_devicetable.h>
af658dca 32#include <linux/trace_events.h>
5a0e3ad6 33#include <linux/slab.h>
cafd6659 34#include <linux/tboot.h>
f4124500 35#include <linux/hrtimer.h>
c207aee4 36#include <linux/frame.h>
5fdbf976 37#include "kvm_cache_regs.h"
35920a35 38#include "x86.h"
e495606d 39
28b835d6 40#include <asm/cpu.h>
6aa8b732 41#include <asm/io.h>
3b3be0d1 42#include <asm/desc.h>
13673a90 43#include <asm/vmx.h>
6210e37b 44#include <asm/virtext.h>
a0861c02 45#include <asm/mce.h>
952f07ec 46#include <asm/fpu/internal.h>
d7cd9796 47#include <asm/perf_event.h>
81908bf4 48#include <asm/debugreg.h>
8f536b76 49#include <asm/kexec.h>
dab2087d 50#include <asm/apic.h>
efc64404 51#include <asm/irq_remapping.h>
d6e41f11 52#include <asm/mmu_context.h>
6aa8b732 53
229456fc 54#include "trace.h"
25462f7f 55#include "pmu.h"
229456fc 56
4ecac3fd 57#define __ex(x) __kvm_handle_fault_on_reboot(x)
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58#define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 60
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61MODULE_AUTHOR("Qumranet");
62MODULE_LICENSE("GPL");
63
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64static const struct x86_cpu_id vmx_cpu_id[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX),
66 {}
67};
68MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
69
476bc001 70static bool __read_mostly enable_vpid = 1;
736caefe 71module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 72
476bc001 73static bool __read_mostly flexpriority_enabled = 1;
736caefe 74module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 75
476bc001 76static bool __read_mostly enable_ept = 1;
736caefe 77module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 78
476bc001 79static bool __read_mostly enable_unrestricted_guest = 1;
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80module_param_named(unrestricted_guest,
81 enable_unrestricted_guest, bool, S_IRUGO);
82
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83static bool __read_mostly enable_ept_ad_bits = 1;
84module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
85
a27685c3 86static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 87module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 88
476bc001 89static bool __read_mostly fasteoi = 1;
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90module_param(fasteoi, bool, S_IRUGO);
91
5a71785d 92static bool __read_mostly enable_apicv = 1;
01e439be 93module_param(enable_apicv, bool, S_IRUGO);
83d4c286 94
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95static bool __read_mostly enable_shadow_vmcs = 1;
96module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
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97/*
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
101 */
476bc001 102static bool __read_mostly nested = 0;
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103module_param(nested, bool, S_IRUGO);
104
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105static u64 __read_mostly host_xss;
106
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107static bool __read_mostly enable_pml = 1;
108module_param_named(pml, enable_pml, bool, S_IRUGO);
109
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110#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
111
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112/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
113static int __read_mostly cpu_preemption_timer_multi;
114static bool __read_mostly enable_preemption_timer = 1;
115#ifdef CONFIG_X86_64
116module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
117#endif
118
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119#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
120#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
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121#define KVM_VM_CR0_ALWAYS_ON \
122 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
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123#define KVM_CR4_GUEST_OWNED_BITS \
124 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 125 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 126
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127#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
128#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
129
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130#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
131
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132#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
133
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134/*
135 * Hyper-V requires all of these, so mark them as supported even though
136 * they are just treated the same as all-context.
137 */
138#define VMX_VPID_EXTENT_SUPPORTED_MASK \
139 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
140 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
143
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144/*
145 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
146 * ple_gap: upper bound on the amount of time between two successive
147 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 148 * According to test, this time is usually smaller than 128 cycles.
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149 * ple_window: upper bound on the amount of time a guest is allowed to execute
150 * in a PAUSE loop. Tests indicate that most spinlocks are held for
151 * less than 2^12 cycles
152 * Time is measured based on a counter that runs at the same rate as the TSC,
153 * refer SDM volume 3b section 21.6.13 & 22.1.3.
154 */
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155#define KVM_VMX_DEFAULT_PLE_GAP 128
156#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
157#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
158#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
159#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
160 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
161
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162static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
163module_param(ple_gap, int, S_IRUGO);
164
165static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
166module_param(ple_window, int, S_IRUGO);
167
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168/* Default doubles per-vcpu window every exit. */
169static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
170module_param(ple_window_grow, int, S_IRUGO);
171
172/* Default resets per-vcpu window every exit to ple_window. */
173static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
174module_param(ple_window_shrink, int, S_IRUGO);
175
176/* Default is to compute the maximum so we can never overflow. */
177static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
178static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179module_param(ple_window_max, int, S_IRUGO);
180
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181extern const ulong vmx_return;
182
8bf00a52 183#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 184#define VMCS02_POOL_SIZE 1
61d2ef2c 185
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186struct vmcs {
187 u32 revision_id;
188 u32 abort;
189 char data[0];
190};
191
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192/*
193 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
194 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
195 * loaded on this CPU (so we can clear them if the CPU goes down).
196 */
197struct loaded_vmcs {
198 struct vmcs *vmcs;
355f4fb1 199 struct vmcs *shadow_vmcs;
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200 int cpu;
201 int launched;
202 struct list_head loaded_vmcss_on_cpu_link;
203};
204
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205struct shared_msr_entry {
206 unsigned index;
207 u64 data;
d5696725 208 u64 mask;
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209};
210
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211/*
212 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
213 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
214 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
215 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
216 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
217 * More than one of these structures may exist, if L1 runs multiple L2 guests.
218 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
219 * underlying hardware which will be used to run L2.
220 * This structure is packed to ensure that its layout is identical across
221 * machines (necessary for live migration).
222 * If there are changes in this struct, VMCS12_REVISION must be changed.
223 */
22bd0358 224typedef u64 natural_width;
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225struct __packed vmcs12 {
226 /* According to the Intel spec, a VMCS region must start with the
227 * following two fields. Then follow implementation-specific data.
228 */
229 u32 revision_id;
230 u32 abort;
22bd0358 231
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232 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
233 u32 padding[7]; /* room for future expansion */
234
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235 u64 io_bitmap_a;
236 u64 io_bitmap_b;
237 u64 msr_bitmap;
238 u64 vm_exit_msr_store_addr;
239 u64 vm_exit_msr_load_addr;
240 u64 vm_entry_msr_load_addr;
241 u64 tsc_offset;
242 u64 virtual_apic_page_addr;
243 u64 apic_access_addr;
705699a1 244 u64 posted_intr_desc_addr;
22bd0358 245 u64 ept_pointer;
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246 u64 eoi_exit_bitmap0;
247 u64 eoi_exit_bitmap1;
248 u64 eoi_exit_bitmap2;
249 u64 eoi_exit_bitmap3;
81dc01f7 250 u64 xss_exit_bitmap;
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251 u64 guest_physical_address;
252 u64 vmcs_link_pointer;
c5f983f6 253 u64 pml_address;
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254 u64 guest_ia32_debugctl;
255 u64 guest_ia32_pat;
256 u64 guest_ia32_efer;
257 u64 guest_ia32_perf_global_ctrl;
258 u64 guest_pdptr0;
259 u64 guest_pdptr1;
260 u64 guest_pdptr2;
261 u64 guest_pdptr3;
36be0b9d 262 u64 guest_bndcfgs;
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263 u64 host_ia32_pat;
264 u64 host_ia32_efer;
265 u64 host_ia32_perf_global_ctrl;
266 u64 padding64[8]; /* room for future expansion */
267 /*
268 * To allow migration of L1 (complete with its L2 guests) between
269 * machines of different natural widths (32 or 64 bit), we cannot have
270 * unsigned long fields with no explict size. We use u64 (aliased
271 * natural_width) instead. Luckily, x86 is little-endian.
272 */
273 natural_width cr0_guest_host_mask;
274 natural_width cr4_guest_host_mask;
275 natural_width cr0_read_shadow;
276 natural_width cr4_read_shadow;
277 natural_width cr3_target_value0;
278 natural_width cr3_target_value1;
279 natural_width cr3_target_value2;
280 natural_width cr3_target_value3;
281 natural_width exit_qualification;
282 natural_width guest_linear_address;
283 natural_width guest_cr0;
284 natural_width guest_cr3;
285 natural_width guest_cr4;
286 natural_width guest_es_base;
287 natural_width guest_cs_base;
288 natural_width guest_ss_base;
289 natural_width guest_ds_base;
290 natural_width guest_fs_base;
291 natural_width guest_gs_base;
292 natural_width guest_ldtr_base;
293 natural_width guest_tr_base;
294 natural_width guest_gdtr_base;
295 natural_width guest_idtr_base;
296 natural_width guest_dr7;
297 natural_width guest_rsp;
298 natural_width guest_rip;
299 natural_width guest_rflags;
300 natural_width guest_pending_dbg_exceptions;
301 natural_width guest_sysenter_esp;
302 natural_width guest_sysenter_eip;
303 natural_width host_cr0;
304 natural_width host_cr3;
305 natural_width host_cr4;
306 natural_width host_fs_base;
307 natural_width host_gs_base;
308 natural_width host_tr_base;
309 natural_width host_gdtr_base;
310 natural_width host_idtr_base;
311 natural_width host_ia32_sysenter_esp;
312 natural_width host_ia32_sysenter_eip;
313 natural_width host_rsp;
314 natural_width host_rip;
315 natural_width paddingl[8]; /* room for future expansion */
316 u32 pin_based_vm_exec_control;
317 u32 cpu_based_vm_exec_control;
318 u32 exception_bitmap;
319 u32 page_fault_error_code_mask;
320 u32 page_fault_error_code_match;
321 u32 cr3_target_count;
322 u32 vm_exit_controls;
323 u32 vm_exit_msr_store_count;
324 u32 vm_exit_msr_load_count;
325 u32 vm_entry_controls;
326 u32 vm_entry_msr_load_count;
327 u32 vm_entry_intr_info_field;
328 u32 vm_entry_exception_error_code;
329 u32 vm_entry_instruction_len;
330 u32 tpr_threshold;
331 u32 secondary_vm_exec_control;
332 u32 vm_instruction_error;
333 u32 vm_exit_reason;
334 u32 vm_exit_intr_info;
335 u32 vm_exit_intr_error_code;
336 u32 idt_vectoring_info_field;
337 u32 idt_vectoring_error_code;
338 u32 vm_exit_instruction_len;
339 u32 vmx_instruction_info;
340 u32 guest_es_limit;
341 u32 guest_cs_limit;
342 u32 guest_ss_limit;
343 u32 guest_ds_limit;
344 u32 guest_fs_limit;
345 u32 guest_gs_limit;
346 u32 guest_ldtr_limit;
347 u32 guest_tr_limit;
348 u32 guest_gdtr_limit;
349 u32 guest_idtr_limit;
350 u32 guest_es_ar_bytes;
351 u32 guest_cs_ar_bytes;
352 u32 guest_ss_ar_bytes;
353 u32 guest_ds_ar_bytes;
354 u32 guest_fs_ar_bytes;
355 u32 guest_gs_ar_bytes;
356 u32 guest_ldtr_ar_bytes;
357 u32 guest_tr_ar_bytes;
358 u32 guest_interruptibility_info;
359 u32 guest_activity_state;
360 u32 guest_sysenter_cs;
361 u32 host_ia32_sysenter_cs;
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362 u32 vmx_preemption_timer_value;
363 u32 padding32[7]; /* room for future expansion */
22bd0358 364 u16 virtual_processor_id;
705699a1 365 u16 posted_intr_nv;
22bd0358
NHE
366 u16 guest_es_selector;
367 u16 guest_cs_selector;
368 u16 guest_ss_selector;
369 u16 guest_ds_selector;
370 u16 guest_fs_selector;
371 u16 guest_gs_selector;
372 u16 guest_ldtr_selector;
373 u16 guest_tr_selector;
608406e2 374 u16 guest_intr_status;
c5f983f6 375 u16 guest_pml_index;
22bd0358
NHE
376 u16 host_es_selector;
377 u16 host_cs_selector;
378 u16 host_ss_selector;
379 u16 host_ds_selector;
380 u16 host_fs_selector;
381 u16 host_gs_selector;
382 u16 host_tr_selector;
a9d30f33
NHE
383};
384
385/*
386 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
387 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
388 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
389 */
390#define VMCS12_REVISION 0x11e57ed0
391
392/*
393 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
394 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
395 * current implementation, 4K are reserved to avoid future complications.
396 */
397#define VMCS12_SIZE 0x1000
398
ff2f6fe9
NHE
399/* Used to remember the last vmcs02 used for some recently used vmcs12s */
400struct vmcs02_list {
401 struct list_head list;
402 gpa_t vmptr;
403 struct loaded_vmcs vmcs02;
404};
405
ec378aee
NHE
406/*
407 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
408 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
409 */
410struct nested_vmx {
411 /* Has the level1 guest done vmxon? */
412 bool vmxon;
3573e22c 413 gpa_t vmxon_ptr;
c5f983f6 414 bool pml_full;
a9d30f33
NHE
415
416 /* The guest-physical address of the current VMCS L1 keeps for L2 */
417 gpa_t current_vmptr;
418 /* The host-usable pointer to the above */
419 struct page *current_vmcs12_page;
420 struct vmcs12 *current_vmcs12;
4f2777bc
DM
421 /*
422 * Cache of the guest's VMCS, existing outside of guest memory.
423 * Loaded from guest memory during VMPTRLD. Flushed to guest
424 * memory during VMXOFF, VMCLEAR, VMPTRLD.
425 */
426 struct vmcs12 *cached_vmcs12;
012f83cb
AG
427 /*
428 * Indicates if the shadow vmcs must be updated with the
429 * data hold by vmcs12
430 */
431 bool sync_shadow_vmcs;
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432
433 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
434 struct list_head vmcs02_pool;
435 int vmcs02_num;
dccbfcf5 436 bool change_vmcs01_virtual_x2apic_mode;
644d711a
NHE
437 /* L2 must run next, and mustn't decide to exit to L1. */
438 bool nested_run_pending;
fe3ef05c
NHE
439 /*
440 * Guest pages referred to in vmcs02 with host-physical pointers, so
441 * we must keep them pinned while L2 runs.
442 */
443 struct page *apic_access_page;
a7c0b07d 444 struct page *virtual_apic_page;
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WV
445 struct page *pi_desc_page;
446 struct pi_desc *pi_desc;
447 bool pi_pending;
448 u16 posted_intr_nv;
f4124500 449
d048c098
RK
450 unsigned long *msr_bitmap;
451
f4124500
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452 struct hrtimer preemption_timer;
453 bool preemption_timer_expired;
2996fca0
JK
454
455 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
456 u64 vmcs01_debugctl;
b9c237bb 457
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WL
458 u16 vpid02;
459 u16 last_vpid;
460
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DM
461 /*
462 * We only store the "true" versions of the VMX capability MSRs. We
463 * generate the "non-true" versions by setting the must-be-1 bits
464 * according to the SDM.
465 */
b9c237bb
WV
466 u32 nested_vmx_procbased_ctls_low;
467 u32 nested_vmx_procbased_ctls_high;
b9c237bb
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468 u32 nested_vmx_secondary_ctls_low;
469 u32 nested_vmx_secondary_ctls_high;
470 u32 nested_vmx_pinbased_ctls_low;
471 u32 nested_vmx_pinbased_ctls_high;
472 u32 nested_vmx_exit_ctls_low;
473 u32 nested_vmx_exit_ctls_high;
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WV
474 u32 nested_vmx_entry_ctls_low;
475 u32 nested_vmx_entry_ctls_high;
b9c237bb
WV
476 u32 nested_vmx_misc_low;
477 u32 nested_vmx_misc_high;
478 u32 nested_vmx_ept_caps;
99b83ac8 479 u32 nested_vmx_vpid_caps;
62cc6b9d
DM
480 u64 nested_vmx_basic;
481 u64 nested_vmx_cr0_fixed0;
482 u64 nested_vmx_cr0_fixed1;
483 u64 nested_vmx_cr4_fixed0;
484 u64 nested_vmx_cr4_fixed1;
485 u64 nested_vmx_vmcs_enum;
ec378aee
NHE
486};
487
01e439be 488#define POSTED_INTR_ON 0
ebbfc765
FW
489#define POSTED_INTR_SN 1
490
01e439be
YZ
491/* Posted-Interrupt Descriptor */
492struct pi_desc {
493 u32 pir[8]; /* Posted interrupt requested */
6ef1522f
FW
494 union {
495 struct {
496 /* bit 256 - Outstanding Notification */
497 u16 on : 1,
498 /* bit 257 - Suppress Notification */
499 sn : 1,
500 /* bit 271:258 - Reserved */
501 rsvd_1 : 14;
502 /* bit 279:272 - Notification Vector */
503 u8 nv;
504 /* bit 287:280 - Reserved */
505 u8 rsvd_2;
506 /* bit 319:288 - Notification Destination */
507 u32 ndst;
508 };
509 u64 control;
510 };
511 u32 rsvd[6];
01e439be
YZ
512} __aligned(64);
513
a20ed54d
YZ
514static bool pi_test_and_set_on(struct pi_desc *pi_desc)
515{
516 return test_and_set_bit(POSTED_INTR_ON,
517 (unsigned long *)&pi_desc->control);
518}
519
520static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
521{
522 return test_and_clear_bit(POSTED_INTR_ON,
523 (unsigned long *)&pi_desc->control);
524}
525
526static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
527{
528 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
529}
530
ebbfc765
FW
531static inline void pi_clear_sn(struct pi_desc *pi_desc)
532{
533 return clear_bit(POSTED_INTR_SN,
534 (unsigned long *)&pi_desc->control);
535}
536
537static inline void pi_set_sn(struct pi_desc *pi_desc)
538{
539 return set_bit(POSTED_INTR_SN,
540 (unsigned long *)&pi_desc->control);
541}
542
ad361091
PB
543static inline void pi_clear_on(struct pi_desc *pi_desc)
544{
545 clear_bit(POSTED_INTR_ON,
546 (unsigned long *)&pi_desc->control);
547}
548
ebbfc765
FW
549static inline int pi_test_on(struct pi_desc *pi_desc)
550{
551 return test_bit(POSTED_INTR_ON,
552 (unsigned long *)&pi_desc->control);
553}
554
555static inline int pi_test_sn(struct pi_desc *pi_desc)
556{
557 return test_bit(POSTED_INTR_SN,
558 (unsigned long *)&pi_desc->control);
559}
560
a2fa3e9f 561struct vcpu_vmx {
fb3f0f51 562 struct kvm_vcpu vcpu;
313dbd49 563 unsigned long host_rsp;
29bd8a78 564 u8 fail;
9d58b931 565 bool nmi_known_unmasked;
51aa01d1 566 u32 exit_intr_info;
1155f76a 567 u32 idt_vectoring_info;
6de12732 568 ulong rflags;
26bb0981 569 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH
570 int nmsrs;
571 int save_nmsrs;
a547c6db 572 unsigned long host_idt_base;
a2fa3e9f 573#ifdef CONFIG_X86_64
44ea2b17
AK
574 u64 msr_host_kernel_gs_base;
575 u64 msr_guest_kernel_gs_base;
a2fa3e9f 576#endif
2961e876
GN
577 u32 vm_entry_controls_shadow;
578 u32 vm_exit_controls_shadow;
d462b819
NHE
579 /*
580 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
581 * non-nested (L1) guest, it always points to vmcs01. For a nested
582 * guest (L2), it points to a different VMCS.
583 */
584 struct loaded_vmcs vmcs01;
585 struct loaded_vmcs *loaded_vmcs;
586 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK
587 struct msr_autoload {
588 unsigned nr;
589 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
590 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
591 } msr_autoload;
a2fa3e9f
GH
592 struct {
593 int loaded;
594 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK
595#ifdef CONFIG_X86_64
596 u16 ds_sel, es_sel;
597#endif
152d3f2f
LV
598 int gs_ldt_reload_needed;
599 int fs_reload_needed;
da8999d3 600 u64 msr_host_bndcfgs;
d6e41f11 601 unsigned long vmcs_host_cr3; /* May not match real cr3 */
d974baa3 602 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 603 } host_state;
9c8cba37 604 struct {
7ffd92c5 605 int vm86_active;
78ac8b47 606 ulong save_rflags;
f5f7b2fe
AK
607 struct kvm_segment segs[8];
608 } rmode;
609 struct {
610 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK
611 struct kvm_save_segment {
612 u16 selector;
613 unsigned long base;
614 u32 limit;
615 u32 ar;
f5f7b2fe 616 } seg[8];
2fb92db1 617 } segment_cache;
2384d2b3 618 int vpid;
04fa4d32 619 bool emulation_required;
3b86cd99 620
a0861c02 621 u32 exit_reason;
4e47c7a6 622
01e439be
YZ
623 /* Posted interrupt descriptor */
624 struct pi_desc pi_desc;
625
ec378aee
NHE
626 /* Support for a guest hypervisor (nested VMX) */
627 struct nested_vmx nested;
a7653ecd
RK
628
629 /* Dynamic PLE window. */
630 int ple_window;
631 bool ple_window_dirty;
843e4330
KH
632
633 /* Support for PML */
634#define PML_ENTITY_NUM 512
635 struct page *pml_pg;
2680d6da 636
64672c95
YJ
637 /* apic deadline value in host tsc */
638 u64 hv_deadline_tsc;
639
2680d6da 640 u64 current_tsc_ratio;
1be0e61c
XG
641
642 bool guest_pkru_valid;
643 u32 guest_pkru;
644 u32 host_pkru;
3b84080b 645
37e4c997
HZ
646 /*
647 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
648 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
649 * in msr_ia32_feature_control_valid_bits.
650 */
3b84080b 651 u64 msr_ia32_feature_control;
37e4c997 652 u64 msr_ia32_feature_control_valid_bits;
a2fa3e9f
GH
653};
654
2fb92db1
AK
655enum segment_cache_field {
656 SEG_FIELD_SEL = 0,
657 SEG_FIELD_BASE = 1,
658 SEG_FIELD_LIMIT = 2,
659 SEG_FIELD_AR = 3,
660
661 SEG_FIELD_NR = 4
662};
663
a2fa3e9f
GH
664static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
665{
fb3f0f51 666 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH
667}
668
efc64404
FW
669static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
670{
671 return &(to_vmx(vcpu)->pi_desc);
672}
673
22bd0358
NHE
674#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
675#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
676#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
677 [number##_HIGH] = VMCS12_OFFSET(name)+4
678
4607c2d7 679
fe2b201b 680static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG
681 /*
682 * We do NOT shadow fields that are modified when L0
683 * traps and emulates any vmx instruction (e.g. VMPTRLD,
684 * VMXON...) executed by L1.
685 * For example, VM_INSTRUCTION_ERROR is read
686 * by L1 if a vmx instruction fails (part of the error path).
687 * Note the code assumes this logic. If for some reason
688 * we start shadowing these fields then we need to
689 * force a shadow sync when L0 emulates vmx instructions
690 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
691 * by nested_vmx_failValid)
692 */
693 VM_EXIT_REASON,
694 VM_EXIT_INTR_INFO,
695 VM_EXIT_INSTRUCTION_LEN,
696 IDT_VECTORING_INFO_FIELD,
697 IDT_VECTORING_ERROR_CODE,
698 VM_EXIT_INTR_ERROR_CODE,
699 EXIT_QUALIFICATION,
700 GUEST_LINEAR_ADDRESS,
701 GUEST_PHYSICAL_ADDRESS
702};
fe2b201b 703static int max_shadow_read_only_fields =
4607c2d7
AG
704 ARRAY_SIZE(shadow_read_only_fields);
705
fe2b201b 706static unsigned long shadow_read_write_fields[] = {
a7c0b07d 707 TPR_THRESHOLD,
4607c2d7
AG
708 GUEST_RIP,
709 GUEST_RSP,
710 GUEST_CR0,
711 GUEST_CR3,
712 GUEST_CR4,
713 GUEST_INTERRUPTIBILITY_INFO,
714 GUEST_RFLAGS,
715 GUEST_CS_SELECTOR,
716 GUEST_CS_AR_BYTES,
717 GUEST_CS_LIMIT,
718 GUEST_CS_BASE,
719 GUEST_ES_BASE,
36be0b9d 720 GUEST_BNDCFGS,
4607c2d7
AG
721 CR0_GUEST_HOST_MASK,
722 CR0_READ_SHADOW,
723 CR4_READ_SHADOW,
724 TSC_OFFSET,
725 EXCEPTION_BITMAP,
726 CPU_BASED_VM_EXEC_CONTROL,
727 VM_ENTRY_EXCEPTION_ERROR_CODE,
728 VM_ENTRY_INTR_INFO_FIELD,
729 VM_ENTRY_INSTRUCTION_LEN,
730 VM_ENTRY_EXCEPTION_ERROR_CODE,
731 HOST_FS_BASE,
732 HOST_GS_BASE,
733 HOST_FS_SELECTOR,
734 HOST_GS_SELECTOR
735};
fe2b201b 736static int max_shadow_read_write_fields =
4607c2d7
AG
737 ARRAY_SIZE(shadow_read_write_fields);
738
772e0318 739static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 740 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 741 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE
742 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
743 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
744 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
745 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
746 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
747 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
748 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
749 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 750 FIELD(GUEST_INTR_STATUS, guest_intr_status),
c5f983f6 751 FIELD(GUEST_PML_INDEX, guest_pml_index),
22bd0358
NHE
752 FIELD(HOST_ES_SELECTOR, host_es_selector),
753 FIELD(HOST_CS_SELECTOR, host_cs_selector),
754 FIELD(HOST_SS_SELECTOR, host_ss_selector),
755 FIELD(HOST_DS_SELECTOR, host_ds_selector),
756 FIELD(HOST_FS_SELECTOR, host_fs_selector),
757 FIELD(HOST_GS_SELECTOR, host_gs_selector),
758 FIELD(HOST_TR_SELECTOR, host_tr_selector),
759 FIELD64(IO_BITMAP_A, io_bitmap_a),
760 FIELD64(IO_BITMAP_B, io_bitmap_b),
761 FIELD64(MSR_BITMAP, msr_bitmap),
762 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
763 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
764 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
765 FIELD64(TSC_OFFSET, tsc_offset),
766 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
767 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 768 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 769 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV
770 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
771 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
772 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
773 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 774 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE
775 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
776 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
c5f983f6 777 FIELD64(PML_ADDRESS, pml_address),
22bd0358
NHE
778 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
779 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
780 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
781 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
782 FIELD64(GUEST_PDPTR0, guest_pdptr0),
783 FIELD64(GUEST_PDPTR1, guest_pdptr1),
784 FIELD64(GUEST_PDPTR2, guest_pdptr2),
785 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 786 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE
787 FIELD64(HOST_IA32_PAT, host_ia32_pat),
788 FIELD64(HOST_IA32_EFER, host_ia32_efer),
789 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
790 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
791 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
792 FIELD(EXCEPTION_BITMAP, exception_bitmap),
793 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
794 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
795 FIELD(CR3_TARGET_COUNT, cr3_target_count),
796 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
797 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
798 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
799 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
800 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
801 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
802 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
803 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
804 FIELD(TPR_THRESHOLD, tpr_threshold),
805 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
806 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
807 FIELD(VM_EXIT_REASON, vm_exit_reason),
808 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
809 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
810 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
811 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
812 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
813 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
814 FIELD(GUEST_ES_LIMIT, guest_es_limit),
815 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
816 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
817 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
818 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
819 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
820 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
821 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
822 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
823 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
824 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
825 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
826 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
827 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
828 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
829 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
830 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
831 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
832 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
833 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
834 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
835 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 836 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE
837 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
838 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
839 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
840 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
841 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
842 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
843 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
844 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
845 FIELD(EXIT_QUALIFICATION, exit_qualification),
846 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
847 FIELD(GUEST_CR0, guest_cr0),
848 FIELD(GUEST_CR3, guest_cr3),
849 FIELD(GUEST_CR4, guest_cr4),
850 FIELD(GUEST_ES_BASE, guest_es_base),
851 FIELD(GUEST_CS_BASE, guest_cs_base),
852 FIELD(GUEST_SS_BASE, guest_ss_base),
853 FIELD(GUEST_DS_BASE, guest_ds_base),
854 FIELD(GUEST_FS_BASE, guest_fs_base),
855 FIELD(GUEST_GS_BASE, guest_gs_base),
856 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
857 FIELD(GUEST_TR_BASE, guest_tr_base),
858 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
859 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
860 FIELD(GUEST_DR7, guest_dr7),
861 FIELD(GUEST_RSP, guest_rsp),
862 FIELD(GUEST_RIP, guest_rip),
863 FIELD(GUEST_RFLAGS, guest_rflags),
864 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
865 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
866 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
867 FIELD(HOST_CR0, host_cr0),
868 FIELD(HOST_CR3, host_cr3),
869 FIELD(HOST_CR4, host_cr4),
870 FIELD(HOST_FS_BASE, host_fs_base),
871 FIELD(HOST_GS_BASE, host_gs_base),
872 FIELD(HOST_TR_BASE, host_tr_base),
873 FIELD(HOST_GDTR_BASE, host_gdtr_base),
874 FIELD(HOST_IDTR_BASE, host_idtr_base),
875 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
876 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
877 FIELD(HOST_RSP, host_rsp),
878 FIELD(HOST_RIP, host_rip),
879};
22bd0358
NHE
880
881static inline short vmcs_field_to_offset(unsigned long field)
882{
a2ae9df7
PB
883 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
884
885 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
886 vmcs_field_to_offset_table[field] == 0)
887 return -ENOENT;
888
22bd0358
NHE
889 return vmcs_field_to_offset_table[field];
890}
891
a9d30f33
NHE
892static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
893{
4f2777bc 894 return to_vmx(vcpu)->nested.cached_vmcs12;
a9d30f33
NHE
895}
896
897static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
898{
54bf36aa 899 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 900 if (is_error_page(page))
a9d30f33 901 return NULL;
32cad84f 902
a9d30f33
NHE
903 return page;
904}
905
906static void nested_release_page(struct page *page)
907{
908 kvm_release_page_dirty(page);
909}
910
911static void nested_release_page_clean(struct page *page)
912{
913 kvm_release_page_clean(page);
914}
915
995f00a6 916static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
bfd0a56b 917static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
995f00a6 918static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
f53cd63c 919static bool vmx_xsaves_supported(void);
776e58ea 920static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW
921static void vmx_set_segment(struct kvm_vcpu *vcpu,
922 struct kvm_segment *var, int seg);
923static void vmx_get_segment(struct kvm_vcpu *vcpu,
924 struct kvm_segment *var, int seg);
d99e4152
GN
925static bool guest_state_valid(struct kvm_vcpu *vcpu);
926static u32 vmx_segment_access_rights(struct kvm_segment *var);
c3114420 927static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 928static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 929static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 930
6aa8b732
AK
931static DEFINE_PER_CPU(struct vmcs *, vmxarea);
932static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE
933/*
934 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
935 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
936 */
937static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 938
bf9f6ac8
FW
939/*
940 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
941 * can find which vCPU should be waken up.
942 */
943static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
944static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
945
23611332
RK
946enum {
947 VMX_IO_BITMAP_A,
948 VMX_IO_BITMAP_B,
949 VMX_MSR_BITMAP_LEGACY,
950 VMX_MSR_BITMAP_LONGMODE,
951 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
952 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
953 VMX_MSR_BITMAP_LEGACY_X2APIC,
954 VMX_MSR_BITMAP_LONGMODE_X2APIC,
955 VMX_VMREAD_BITMAP,
956 VMX_VMWRITE_BITMAP,
957 VMX_BITMAP_NR
958};
959
960static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
961
962#define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
963#define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
964#define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
965#define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
966#define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
967#define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
968#define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
969#define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
970#define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
971#define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
fdef3ad1 972
110312c8 973static bool cpu_has_load_ia32_efer;
8bf00a52 974static bool cpu_has_load_perf_global_ctrl;
110312c8 975
2384d2b3
SY
976static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
977static DEFINE_SPINLOCK(vmx_vpid_lock);
978
1c3d14fe 979static struct vmcs_config {
6aa8b732
AK
980 int size;
981 int order;
9ac7e3e8 982 u32 basic_cap;
6aa8b732 983 u32 revision_id;
1c3d14fe
YS
984 u32 pin_based_exec_ctrl;
985 u32 cpu_based_exec_ctrl;
f78e0e2e 986 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS
987 u32 vmexit_ctrl;
988 u32 vmentry_ctrl;
989} vmcs_config;
6aa8b732 990
efff9e53 991static struct vmx_capability {
d56f546d
SY
992 u32 ept;
993 u32 vpid;
994} vmx_capability;
995
6aa8b732
AK
996#define VMX_SEGMENT_FIELD(seg) \
997 [VCPU_SREG_##seg] = { \
998 .selector = GUEST_##seg##_SELECTOR, \
999 .base = GUEST_##seg##_BASE, \
1000 .limit = GUEST_##seg##_LIMIT, \
1001 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1002 }
1003
772e0318 1004static const struct kvm_vmx_segment_field {
6aa8b732
AK
1005 unsigned selector;
1006 unsigned base;
1007 unsigned limit;
1008 unsigned ar_bytes;
1009} kvm_vmx_segment_fields[] = {
1010 VMX_SEGMENT_FIELD(CS),
1011 VMX_SEGMENT_FIELD(DS),
1012 VMX_SEGMENT_FIELD(ES),
1013 VMX_SEGMENT_FIELD(FS),
1014 VMX_SEGMENT_FIELD(GS),
1015 VMX_SEGMENT_FIELD(SS),
1016 VMX_SEGMENT_FIELD(TR),
1017 VMX_SEGMENT_FIELD(LDTR),
1018};
1019
26bb0981
AK
1020static u64 host_efer;
1021
6de4f3ad
AK
1022static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1023
4d56c8a7 1024/*
8c06585d 1025 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK
1026 * away by decrementing the array size.
1027 */
6aa8b732 1028static const u32 vmx_msr_index[] = {
05b3e0c2 1029#ifdef CONFIG_X86_64
44ea2b17 1030 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 1031#endif
8c06585d 1032 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 1033};
6aa8b732 1034
5bb16016 1035static inline bool is_exception_n(u32 intr_info, u8 vector)
6aa8b732
AK
1036{
1037 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1038 INTR_INFO_VALID_MASK)) ==
5bb16016
JK
1039 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1040}
1041
6f05485d
JK
1042static inline bool is_debug(u32 intr_info)
1043{
1044 return is_exception_n(intr_info, DB_VECTOR);
1045}
1046
1047static inline bool is_breakpoint(u32 intr_info)
1048{
1049 return is_exception_n(intr_info, BP_VECTOR);
1050}
1051
5bb16016
JK
1052static inline bool is_page_fault(u32 intr_info)
1053{
1054 return is_exception_n(intr_info, PF_VECTOR);
6aa8b732
AK
1055}
1056
31299944 1057static inline bool is_no_device(u32 intr_info)
2ab455cc 1058{
5bb16016 1059 return is_exception_n(intr_info, NM_VECTOR);
2ab455cc
AL
1060}
1061
31299944 1062static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0 1063{
5bb16016 1064 return is_exception_n(intr_info, UD_VECTOR);
7aa81cc0
AL
1065}
1066
31299944 1067static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK
1068{
1069 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1070 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1071}
1072
31299944 1073static inline bool is_machine_check(u32 intr_info)
a0861c02
AK
1074{
1075 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1076 INTR_INFO_VALID_MASK)) ==
1077 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1078}
1079
31299944 1080static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 1081{
04547156 1082 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY
1083}
1084
31299944 1085static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 1086{
04547156 1087 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS
1088}
1089
35754c98 1090static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 1091{
35754c98 1092 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS
1093}
1094
31299944 1095static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 1096{
04547156
SY
1097 return vmcs_config.cpu_based_exec_ctrl &
1098 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY
1099}
1100
774ead3a 1101static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 1102{
04547156
SY
1103 return vmcs_config.cpu_based_2nd_exec_ctrl &
1104 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1105}
1106
8d14695f
YZ
1107static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1108{
1109 return vmcs_config.cpu_based_2nd_exec_ctrl &
1110 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1111}
1112
83d4c286
YZ
1113static inline bool cpu_has_vmx_apic_register_virt(void)
1114{
1115 return vmcs_config.cpu_based_2nd_exec_ctrl &
1116 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1117}
1118
c7c9c56c
YZ
1119static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1120{
1121 return vmcs_config.cpu_based_2nd_exec_ctrl &
1122 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1123}
1124
64672c95
YJ
1125/*
1126 * Comment's format: document - errata name - stepping - processor name.
1127 * Refer from
1128 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1129 */
1130static u32 vmx_preemption_cpu_tfms[] = {
1131/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
11320x000206E6,
1133/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1134/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1135/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
11360x00020652,
1137/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
11380x00020655,
1139/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1140/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1141/*
1142 * 320767.pdf - AAP86 - B1 -
1143 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1144 */
11450x000106E5,
1146/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
11470x000106A0,
1148/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
11490x000106A1,
1150/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
11510x000106A4,
1152 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1153 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1154 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
11550x000106A5,
1156};
1157
1158static inline bool cpu_has_broken_vmx_preemption_timer(void)
1159{
1160 u32 eax = cpuid_eax(0x00000001), i;
1161
1162 /* Clear the reserved bits */
1163 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 1164 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ
1165 if (eax == vmx_preemption_cpu_tfms[i])
1166 return true;
1167
1168 return false;
1169}
1170
1171static inline bool cpu_has_vmx_preemption_timer(void)
1172{
64672c95
YJ
1173 return vmcs_config.pin_based_exec_ctrl &
1174 PIN_BASED_VMX_PREEMPTION_TIMER;
1175}
1176
01e439be
YZ
1177static inline bool cpu_has_vmx_posted_intr(void)
1178{
d6a858d1
PB
1179 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1180 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ
1181}
1182
1183static inline bool cpu_has_vmx_apicv(void)
1184{
1185 return cpu_has_vmx_apic_register_virt() &&
1186 cpu_has_vmx_virtual_intr_delivery() &&
1187 cpu_has_vmx_posted_intr();
1188}
1189
04547156
SY
1190static inline bool cpu_has_vmx_flexpriority(void)
1191{
1192 return cpu_has_vmx_tpr_shadow() &&
1193 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY
1194}
1195
e799794e
MT
1196static inline bool cpu_has_vmx_ept_execute_only(void)
1197{
31299944 1198 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT
1199}
1200
e799794e
MT
1201static inline bool cpu_has_vmx_ept_2m_page(void)
1202{
31299944 1203 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT
1204}
1205
878403b7
SY
1206static inline bool cpu_has_vmx_ept_1g_page(void)
1207{
31299944 1208 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY
1209}
1210
4bc9b982
SY
1211static inline bool cpu_has_vmx_ept_4levels(void)
1212{
1213 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1214}
1215
83c3a331
XH
1216static inline bool cpu_has_vmx_ept_ad_bits(void)
1217{
1218 return vmx_capability.ept & VMX_EPT_AD_BIT;
1219}
1220
31299944 1221static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1222{
31299944 1223 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY
1224}
1225
31299944 1226static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1227{
31299944 1228 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY
1229}
1230
518c8aee
GJ
1231static inline bool cpu_has_vmx_invvpid_single(void)
1232{
1233 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1234}
1235
b9d762fa
GJ
1236static inline bool cpu_has_vmx_invvpid_global(void)
1237{
1238 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1239}
1240
08d839c4
WL
1241static inline bool cpu_has_vmx_invvpid(void)
1242{
1243 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1244}
1245
31299944 1246static inline bool cpu_has_vmx_ept(void)
d56f546d 1247{
04547156
SY
1248 return vmcs_config.cpu_based_2nd_exec_ctrl &
1249 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY
1250}
1251
31299944 1252static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK
1253{
1254 return vmcs_config.cpu_based_2nd_exec_ctrl &
1255 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1256}
1257
31299944 1258static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE
1259{
1260 return vmcs_config.cpu_based_2nd_exec_ctrl &
1261 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1262}
1263
9ac7e3e8
JD
1264static inline bool cpu_has_vmx_basic_inout(void)
1265{
1266 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1267}
1268
35754c98 1269static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1270{
35754c98 1271 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY
1272}
1273
31299944 1274static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1275{
04547156
SY
1276 return vmcs_config.cpu_based_2nd_exec_ctrl &
1277 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY
1278}
1279
31299944 1280static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY
1281{
1282 return vmcs_config.cpu_based_2nd_exec_ctrl &
1283 SECONDARY_EXEC_RDTSCP;
1284}
1285
ad756a16
MJ
1286static inline bool cpu_has_vmx_invpcid(void)
1287{
1288 return vmcs_config.cpu_based_2nd_exec_ctrl &
1289 SECONDARY_EXEC_ENABLE_INVPCID;
1290}
1291
f5f48ee1
SY
1292static inline bool cpu_has_vmx_wbinvd_exit(void)
1293{
1294 return vmcs_config.cpu_based_2nd_exec_ctrl &
1295 SECONDARY_EXEC_WBINVD_EXITING;
1296}
1297
abc4fc58
AG
1298static inline bool cpu_has_vmx_shadow_vmcs(void)
1299{
1300 u64 vmx_msr;
1301 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1302 /* check if the cpu supports writing r/o exit information fields */
1303 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1304 return false;
1305
1306 return vmcs_config.cpu_based_2nd_exec_ctrl &
1307 SECONDARY_EXEC_SHADOW_VMCS;
1308}
1309
843e4330
KH
1310static inline bool cpu_has_vmx_pml(void)
1311{
1312 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1313}
1314
64903d61
HZ
1315static inline bool cpu_has_vmx_tsc_scaling(void)
1316{
1317 return vmcs_config.cpu_based_2nd_exec_ctrl &
1318 SECONDARY_EXEC_TSC_SCALING;
1319}
1320
04547156
SY
1321static inline bool report_flexpriority(void)
1322{
1323 return flexpriority_enabled;
1324}
1325
c7c2c709
JM
1326static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1327{
1328 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1329}
1330
fe3ef05c
NHE
1331static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1332{
1333 return vmcs12->cpu_based_vm_exec_control & bit;
1334}
1335
1336static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1337{
1338 return (vmcs12->cpu_based_vm_exec_control &
1339 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1340 (vmcs12->secondary_vm_exec_control & bit);
1341}
1342
f5c4368f 1343static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE
1344{
1345 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1346}
1347
f4124500
JK
1348static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1349{
1350 return vmcs12->pin_based_vm_exec_control &
1351 PIN_BASED_VMX_PREEMPTION_TIMER;
1352}
1353
155a97a3
NHE
1354static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1355{
1356 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1357}
1358
81dc01f7
WL
1359static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1360{
1361 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1362 vmx_xsaves_supported();
1363}
1364
c5f983f6
BD
1365static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1366{
1367 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1368}
1369
f2b93280
WV
1370static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1371{
1372 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1373}
1374
5c614b35
WL
1375static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1376{
1377 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1378}
1379
82f0dd4b
WV
1380static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1381{
1382 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1383}
1384
608406e2
WV
1385static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1386{
1387 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1388}
1389
705699a1
WV
1390static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1391{
1392 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1393}
1394
ef85b673 1395static inline bool is_nmi(u32 intr_info)
644d711a
NHE
1396{
1397 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
ef85b673 1398 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
644d711a
NHE
1399}
1400
533558bc
JK
1401static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1402 u32 exit_intr_info,
1403 unsigned long exit_qualification);
7c177938
NHE
1404static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1405 struct vmcs12 *vmcs12,
1406 u32 reason, unsigned long qualification);
1407
8b9cf98c 1408static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK
1409{
1410 int i;
1411
a2fa3e9f 1412 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1413 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED
1414 return i;
1415 return -1;
1416}
1417
2384d2b3
SY
1418static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1419{
1420 struct {
1421 u64 vpid : 16;
1422 u64 rsvd : 48;
1423 u64 gva;
1424 } operand = { vpid, 0, gva };
1425
4ecac3fd 1426 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY
1427 /* CF==1 or ZF==1 --> rc = -1 */
1428 "; ja 1f ; ud2 ; 1:"
1429 : : "a"(&operand), "c"(ext) : "cc", "memory");
1430}
1431
1439442c
SY
1432static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1433{
1434 struct {
1435 u64 eptp, gpa;
1436 } operand = {eptp, gpa};
1437
4ecac3fd 1438 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY
1439 /* CF==1 or ZF==1 --> rc = -1 */
1440 "; ja 1f ; ud2 ; 1:\n"
1441 : : "a" (&operand), "c" (ext) : "cc", "memory");
1442}
1443
26bb0981 1444static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED
1445{
1446 int i;
1447
8b9cf98c 1448 i = __find_msr_index(vmx, msr);
a75beee6 1449 if (i >= 0)
a2fa3e9f 1450 return &vmx->guest_msrs[i];
8b6d44c7 1451 return NULL;
7725f0ba
AK
1452}
1453
6aa8b732
AK
1454static void vmcs_clear(struct vmcs *vmcs)
1455{
1456 u64 phys_addr = __pa(vmcs);
1457 u8 error;
1458
4ecac3fd 1459 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1460 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK
1461 : "cc", "memory");
1462 if (error)
1463 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1464 vmcs, phys_addr);
1465}
1466
d462b819
NHE
1467static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1468{
1469 vmcs_clear(loaded_vmcs->vmcs);
355f4fb1
JM
1470 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1471 vmcs_clear(loaded_vmcs->shadow_vmcs);
d462b819
NHE
1472 loaded_vmcs->cpu = -1;
1473 loaded_vmcs->launched = 0;
1474}
1475
7725b894
DX
1476static void vmcs_load(struct vmcs *vmcs)
1477{
1478 u64 phys_addr = __pa(vmcs);
1479 u8 error;
1480
1481 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1482 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX
1483 : "cc", "memory");
1484 if (error)
2844d849 1485 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX
1486 vmcs, phys_addr);
1487}
1488
2965faa5 1489#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY
1490/*
1491 * This bitmap is used to indicate whether the vmclear
1492 * operation is enabled on all cpus. All disabled by
1493 * default.
1494 */
1495static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1496
1497static inline void crash_enable_local_vmclear(int cpu)
1498{
1499 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1500}
1501
1502static inline void crash_disable_local_vmclear(int cpu)
1503{
1504 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1505}
1506
1507static inline int crash_local_vmclear_enabled(int cpu)
1508{
1509 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1510}
1511
1512static void crash_vmclear_local_loaded_vmcss(void)
1513{
1514 int cpu = raw_smp_processor_id();
1515 struct loaded_vmcs *v;
1516
1517 if (!crash_local_vmclear_enabled(cpu))
1518 return;
1519
1520 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1521 loaded_vmcss_on_cpu_link)
1522 vmcs_clear(v->vmcs);
1523}
1524#else
1525static inline void crash_enable_local_vmclear(int cpu) { }
1526static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1527#endif /* CONFIG_KEXEC_CORE */
8f536b76 1528
d462b819 1529static void __loaded_vmcs_clear(void *arg)
6aa8b732 1530{
d462b819 1531 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1532 int cpu = raw_smp_processor_id();
6aa8b732 1533
d462b819
NHE
1534 if (loaded_vmcs->cpu != cpu)
1535 return; /* vcpu migration can race with cpu offline */
1536 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1537 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1538 crash_disable_local_vmclear(cpu);
d462b819 1539 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG
1540
1541 /*
1542 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1543 * is before setting loaded_vmcs->vcpu to -1 which is done in
1544 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1545 * then adds the vmcs into percpu list before it is deleted.
1546 */
1547 smp_wmb();
1548
d462b819 1549 loaded_vmcs_init(loaded_vmcs);
8f536b76 1550 crash_enable_local_vmclear(cpu);
6aa8b732
AK
1551}
1552
d462b819 1553static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1554{
e6c7d321
XG
1555 int cpu = loaded_vmcs->cpu;
1556
1557 if (cpu != -1)
1558 smp_call_function_single(cpu,
1559 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK
1560}
1561
dd5f5341 1562static inline void vpid_sync_vcpu_single(int vpid)
2384d2b3 1563{
dd5f5341 1564 if (vpid == 0)
2384d2b3
SY
1565 return;
1566
518c8aee 1567 if (cpu_has_vmx_invvpid_single())
dd5f5341 1568 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
2384d2b3
SY
1569}
1570
b9d762fa
GJ
1571static inline void vpid_sync_vcpu_global(void)
1572{
1573 if (cpu_has_vmx_invvpid_global())
1574 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1575}
1576
dd5f5341 1577static inline void vpid_sync_context(int vpid)
b9d762fa
GJ
1578{
1579 if (cpu_has_vmx_invvpid_single())
dd5f5341 1580 vpid_sync_vcpu_single(vpid);
b9d762fa
GJ
1581 else
1582 vpid_sync_vcpu_global();
1583}
1584
1439442c
SY
1585static inline void ept_sync_global(void)
1586{
1587 if (cpu_has_vmx_invept_global())
1588 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1589}
1590
1591static inline void ept_sync_context(u64 eptp)
1592{
089d034e 1593 if (enable_ept) {
1439442c
SY
1594 if (cpu_has_vmx_invept_context())
1595 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1596 else
1597 ept_sync_global();
1598 }
1599}
1600
8a86aea9
PB
1601static __always_inline void vmcs_check16(unsigned long field)
1602{
1603 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1604 "16-bit accessor invalid for 64-bit field");
1605 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1606 "16-bit accessor invalid for 64-bit high field");
1607 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1608 "16-bit accessor invalid for 32-bit high field");
1609 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1610 "16-bit accessor invalid for natural width field");
1611}
1612
1613static __always_inline void vmcs_check32(unsigned long field)
1614{
1615 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1616 "32-bit accessor invalid for 16-bit field");
1617 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1618 "32-bit accessor invalid for natural width field");
1619}
1620
1621static __always_inline void vmcs_check64(unsigned long field)
1622{
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1624 "64-bit accessor invalid for 16-bit field");
1625 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1626 "64-bit accessor invalid for 64-bit high field");
1627 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1628 "64-bit accessor invalid for 32-bit field");
1629 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1630 "64-bit accessor invalid for natural width field");
1631}
1632
1633static __always_inline void vmcs_checkl(unsigned long field)
1634{
1635 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1636 "Natural width accessor invalid for 16-bit field");
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1638 "Natural width accessor invalid for 64-bit field");
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1640 "Natural width accessor invalid for 64-bit high field");
1641 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1642 "Natural width accessor invalid for 32-bit field");
1643}
1644
1645static __always_inline unsigned long __vmcs_readl(unsigned long field)
6aa8b732 1646{
5e520e62 1647 unsigned long value;
6aa8b732 1648
5e520e62
AK
1649 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1650 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK
1651 return value;
1652}
1653
96304217 1654static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732 1655{
8a86aea9
PB
1656 vmcs_check16(field);
1657 return __vmcs_readl(field);
6aa8b732
AK
1658}
1659
96304217 1660static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732 1661{
8a86aea9
PB
1662 vmcs_check32(field);
1663 return __vmcs_readl(field);
6aa8b732
AK
1664}
1665
96304217 1666static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1667{
8a86aea9 1668 vmcs_check64(field);
05b3e0c2 1669#ifdef CONFIG_X86_64
8a86aea9 1670 return __vmcs_readl(field);
6aa8b732 1671#else
8a86aea9 1672 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
6aa8b732
AK
1673#endif
1674}
1675
8a86aea9
PB
1676static __always_inline unsigned long vmcs_readl(unsigned long field)
1677{
1678 vmcs_checkl(field);
1679 return __vmcs_readl(field);
1680}
1681
e52de1b8
AK
1682static noinline void vmwrite_error(unsigned long field, unsigned long value)
1683{
1684 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1685 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1686 dump_stack();
1687}
1688
8a86aea9 1689static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
6aa8b732
AK
1690{
1691 u8 error;
1692
4ecac3fd 1693 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1694 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK
1695 if (unlikely(error))
1696 vmwrite_error(field, value);
6aa8b732
AK
1697}
1698
8a86aea9 1699static __always_inline void vmcs_write16(unsigned long field, u16 value)
6aa8b732 1700{
8a86aea9
PB
1701 vmcs_check16(field);
1702 __vmcs_writel(field, value);
6aa8b732
AK
1703}
1704
8a86aea9 1705static __always_inline void vmcs_write32(unsigned long field, u32 value)
6aa8b732 1706{
8a86aea9
PB
1707 vmcs_check32(field);
1708 __vmcs_writel(field, value);
6aa8b732
AK
1709}
1710
8a86aea9 1711static __always_inline void vmcs_write64(unsigned long field, u64 value)
6aa8b732 1712{
8a86aea9
PB
1713 vmcs_check64(field);
1714 __vmcs_writel(field, value);
7682f2d0 1715#ifndef CONFIG_X86_64
6aa8b732 1716 asm volatile ("");
8a86aea9 1717 __vmcs_writel(field+1, value >> 32);
6aa8b732
AK
1718#endif
1719}
1720
8a86aea9 1721static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2ab455cc 1722{
8a86aea9
PB
1723 vmcs_checkl(field);
1724 __vmcs_writel(field, value);
2ab455cc
AL
1725}
1726
8a86aea9 1727static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2ab455cc 1728{
8a86aea9
PB
1729 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1730 "vmcs_clear_bits does not support 64-bit fields");
1731 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2ab455cc
AL
1732}
1733
8a86aea9 1734static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2ab455cc 1735{
8a86aea9
PB
1736 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1737 "vmcs_set_bits does not support 64-bit fields");
1738 __vmcs_writel(field, __vmcs_readl(field) | mask);
2ab455cc
AL
1739}
1740
8391ce44
PB
1741static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1742{
1743 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1744}
1745
2961e876
GN
1746static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1747{
1748 vmcs_write32(VM_ENTRY_CONTROLS, val);
1749 vmx->vm_entry_controls_shadow = val;
1750}
1751
1752static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1753{
1754 if (vmx->vm_entry_controls_shadow != val)
1755 vm_entry_controls_init(vmx, val);
1756}
1757
1758static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1759{
1760 return vmx->vm_entry_controls_shadow;
1761}
1762
1763
1764static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1765{
1766 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1767}
1768
1769static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1770{
1771 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1772}
1773
8391ce44
PB
1774static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1775{
1776 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1777}
1778
2961e876
GN
1779static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1780{
1781 vmcs_write32(VM_EXIT_CONTROLS, val);
1782 vmx->vm_exit_controls_shadow = val;
1783}
1784
1785static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1786{
1787 if (vmx->vm_exit_controls_shadow != val)
1788 vm_exit_controls_init(vmx, val);
1789}
1790
1791static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1792{
1793 return vmx->vm_exit_controls_shadow;
1794}
1795
1796
1797static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1798{
1799 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1800}
1801
1802static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1803{
1804 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1805}
1806
2fb92db1
AK
1807static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1808{
1809 vmx->segment_cache.bitmask = 0;
1810}
1811
1812static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1813 unsigned field)
1814{
1815 bool ret;
1816 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1817
1818 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1819 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1820 vmx->segment_cache.bitmask = 0;
1821 }
1822 ret = vmx->segment_cache.bitmask & mask;
1823 vmx->segment_cache.bitmask |= mask;
1824 return ret;
1825}
1826
1827static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1828{
1829 u16 *p = &vmx->segment_cache.seg[seg].selector;
1830
1831 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1832 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1833 return *p;
1834}
1835
1836static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1837{
1838 ulong *p = &vmx->segment_cache.seg[seg].base;
1839
1840 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1841 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1842 return *p;
1843}
1844
1845static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1846{
1847 u32 *p = &vmx->segment_cache.seg[seg].limit;
1848
1849 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1850 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1851 return *p;
1852}
1853
1854static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1855{
1856 u32 *p = &vmx->segment_cache.seg[seg].ar;
1857
1858 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1859 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1860 return *p;
1861}
1862
abd3f2d6
AK
1863static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1864{
1865 u32 eb;
1866
fd7373cc 1867 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 1868 (1u << DB_VECTOR) | (1u << AC_VECTOR);
fd7373cc
JK
1869 if ((vcpu->guest_debug &
1870 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1871 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1872 eb |= 1u << BP_VECTOR;
7ffd92c5 1873 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1874 eb = ~0;
089d034e 1875 if (enable_ept)
1439442c 1876 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE
1877
1878 /* When we are running a nested L2 guest and L1 specified for it a
1879 * certain exception bitmap, we must trap the same exceptions and pass
1880 * them to L1. When running L2, we will only handle the exceptions
1881 * specified above if L1 did not want them.
1882 */
1883 if (is_guest_mode(vcpu))
1884 eb |= get_vmcs12(vcpu)->exception_bitmap;
1885
abd3f2d6
AK
1886 vmcs_write32(EXCEPTION_BITMAP, eb);
1887}
1888
2961e876
GN
1889static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1890 unsigned long entry, unsigned long exit)
8bf00a52 1891{
2961e876
GN
1892 vm_entry_controls_clearbit(vmx, entry);
1893 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN
1894}
1895
61d2ef2c
AK
1896static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1897{
1898 unsigned i;
1899 struct msr_autoload *m = &vmx->msr_autoload;
1900
8bf00a52
GN
1901 switch (msr) {
1902 case MSR_EFER:
1903 if (cpu_has_load_ia32_efer) {
2961e876
GN
1904 clear_atomic_switch_msr_special(vmx,
1905 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN
1906 VM_EXIT_LOAD_IA32_EFER);
1907 return;
1908 }
1909 break;
1910 case MSR_CORE_PERF_GLOBAL_CTRL:
1911 if (cpu_has_load_perf_global_ctrl) {
2961e876 1912 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN
1913 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1914 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1915 return;
1916 }
1917 break;
110312c8
AK
1918 }
1919
61d2ef2c
AK
1920 for (i = 0; i < m->nr; ++i)
1921 if (m->guest[i].index == msr)
1922 break;
1923
1924 if (i == m->nr)
1925 return;
1926 --m->nr;
1927 m->guest[i] = m->guest[m->nr];
1928 m->host[i] = m->host[m->nr];
1929 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1930 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1931}
1932
2961e876
GN
1933static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1934 unsigned long entry, unsigned long exit,
1935 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1936 u64 guest_val, u64 host_val)
8bf00a52
GN
1937{
1938 vmcs_write64(guest_val_vmcs, guest_val);
1939 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN
1940 vm_entry_controls_setbit(vmx, entry);
1941 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN
1942}
1943
61d2ef2c
AK
1944static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1945 u64 guest_val, u64 host_val)
1946{
1947 unsigned i;
1948 struct msr_autoload *m = &vmx->msr_autoload;
1949
8bf00a52
GN
1950 switch (msr) {
1951 case MSR_EFER:
1952 if (cpu_has_load_ia32_efer) {
2961e876
GN
1953 add_atomic_switch_msr_special(vmx,
1954 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN
1955 VM_EXIT_LOAD_IA32_EFER,
1956 GUEST_IA32_EFER,
1957 HOST_IA32_EFER,
1958 guest_val, host_val);
1959 return;
1960 }
1961 break;
1962 case MSR_CORE_PERF_GLOBAL_CTRL:
1963 if (cpu_has_load_perf_global_ctrl) {
2961e876 1964 add_atomic_switch_msr_special(vmx,
8bf00a52
GN
1965 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1966 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1967 GUEST_IA32_PERF_GLOBAL_CTRL,
1968 HOST_IA32_PERF_GLOBAL_CTRL,
1969 guest_val, host_val);
1970 return;
1971 }
1972 break;
7099e2e1
RK
1973 case MSR_IA32_PEBS_ENABLE:
1974 /* PEBS needs a quiescent period after being disabled (to write
1975 * a record). Disabling PEBS through VMX MSR swapping doesn't
1976 * provide that period, so a CPU could write host's record into
1977 * guest's memory.
1978 */
1979 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK
1980 }
1981
61d2ef2c
AK
1982 for (i = 0; i < m->nr; ++i)
1983 if (m->guest[i].index == msr)
1984 break;
1985
e7fc6f93 1986 if (i == NR_AUTOLOAD_MSRS) {
60266204 1987 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN
1988 "Can't add msr %x\n", msr);
1989 return;
1990 } else if (i == m->nr) {
61d2ef2c
AK
1991 ++m->nr;
1992 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1993 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1994 }
1995
1996 m->guest[i].index = msr;
1997 m->guest[i].value = guest_val;
1998 m->host[i].index = msr;
1999 m->host[i].value = host_val;
2000}
2001
92c0d900 2002static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 2003{
844a5fe2
PB
2004 u64 guest_efer = vmx->vcpu.arch.efer;
2005 u64 ignore_bits = 0;
2006
2007 if (!enable_ept) {
2008 /*
2009 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2010 * host CPUID is more efficient than testing guest CPUID
2011 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2012 */
2013 if (boot_cpu_has(X86_FEATURE_SMEP))
2014 guest_efer |= EFER_NX;
2015 else if (!(guest_efer & EFER_NX))
2016 ignore_bits |= EFER_NX;
2017 }
3a34a881 2018
51c6cf66 2019 /*
844a5fe2 2020 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 2021 */
844a5fe2 2022 ignore_bits |= EFER_SCE;
51c6cf66
AK
2023#ifdef CONFIG_X86_64
2024 ignore_bits |= EFER_LMA | EFER_LME;
2025 /* SCE is meaningful only in long mode on Intel */
2026 if (guest_efer & EFER_LMA)
2027 ignore_bits &= ~(u64)EFER_SCE;
2028#endif
84ad33ef
AK
2029
2030 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL
2031
2032 /*
2033 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2034 * On CPUs that support "load IA32_EFER", always switch EFER
2035 * atomically, since it's faster than switching it manually.
2036 */
2037 if (cpu_has_load_ia32_efer ||
2038 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK
2039 if (!(guest_efer & EFER_LMA))
2040 guest_efer &= ~EFER_LME;
54b98bff
AL
2041 if (guest_efer != host_efer)
2042 add_atomic_switch_msr(vmx, MSR_EFER,
2043 guest_efer, host_efer);
84ad33ef 2044 return false;
844a5fe2
PB
2045 } else {
2046 guest_efer &= ~ignore_bits;
2047 guest_efer |= host_efer & ignore_bits;
2048
2049 vmx->guest_msrs[efer_offset].data = guest_efer;
2050 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 2051
844a5fe2
PB
2052 return true;
2053 }
51c6cf66
AK
2054}
2055
e28baead
AL
2056#ifdef CONFIG_X86_32
2057/*
2058 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2059 * VMCS rather than the segment table. KVM uses this helper to figure
2060 * out the current bases to poke them into the VMCS before entry.
2061 */
2d49ec72
GN
2062static unsigned long segment_base(u16 selector)
2063{
8c2e41f7 2064 struct desc_struct *table;
2d49ec72
GN
2065 unsigned long v;
2066
8c2e41f7 2067 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN
2068 return 0;
2069
45fc8757 2070 table = get_current_gdt_ro();
2d49ec72 2071
8c2e41f7 2072 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN
2073 u16 ldt_selector = kvm_read_ldt();
2074
8c2e41f7 2075 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN
2076 return 0;
2077
8c2e41f7 2078 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 2079 }
8c2e41f7 2080 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN
2081 return v;
2082}
e28baead 2083#endif
2d49ec72 2084
04d2cc77 2085static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 2086{
04d2cc77 2087 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2088 int i;
04d2cc77 2089
a2fa3e9f 2090 if (vmx->host_state.loaded)
33ed6329
AK
2091 return;
2092
a2fa3e9f 2093 vmx->host_state.loaded = 1;
33ed6329
AK
2094 /*
2095 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2096 * allow segment selectors with cpl > 0 or ti == 1.
2097 */
d6e88aec 2098 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 2099 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 2100 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 2101 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 2102 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV
2103 vmx->host_state.fs_reload_needed = 0;
2104 } else {
33ed6329 2105 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 2106 vmx->host_state.fs_reload_needed = 1;
33ed6329 2107 }
9581d442 2108 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH
2109 if (!(vmx->host_state.gs_sel & 7))
2110 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK
2111 else {
2112 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 2113 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK
2114 }
2115
b2da15ac
AK
2116#ifdef CONFIG_X86_64
2117 savesegment(ds, vmx->host_state.ds_sel);
2118 savesegment(es, vmx->host_state.es_sel);
2119#endif
2120
33ed6329
AK
2121#ifdef CONFIG_X86_64
2122 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2123 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2124#else
a2fa3e9f
GH
2125 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2126 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 2127#endif
707c0874
AK
2128
2129#ifdef CONFIG_X86_64
c8770e7b
AK
2130 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2131 if (is_long_mode(&vmx->vcpu))
44ea2b17 2132 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 2133#endif
da8999d3
LJ
2134 if (boot_cpu_has(X86_FEATURE_MPX))
2135 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK
2136 for (i = 0; i < vmx->save_nmsrs; ++i)
2137 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK
2138 vmx->guest_msrs[i].data,
2139 vmx->guest_msrs[i].mask);
33ed6329
AK
2140}
2141
a9b21b62 2142static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 2143{
a2fa3e9f 2144 if (!vmx->host_state.loaded)
33ed6329
AK
2145 return;
2146
e1beb1d3 2147 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 2148 vmx->host_state.loaded = 0;
c8770e7b
AK
2149#ifdef CONFIG_X86_64
2150 if (is_long_mode(&vmx->vcpu))
2151 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2152#endif
152d3f2f 2153 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 2154 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 2155#ifdef CONFIG_X86_64
9581d442 2156 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK
2157#else
2158 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 2159#endif
33ed6329 2160 }
0a77fe4c
AK
2161 if (vmx->host_state.fs_reload_needed)
2162 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK
2163#ifdef CONFIG_X86_64
2164 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2165 loadsegment(ds, vmx->host_state.ds_sel);
2166 loadsegment(es, vmx->host_state.es_sel);
2167 }
b2da15ac 2168#endif
b7ffc44d 2169 invalidate_tss_limit();
44ea2b17 2170#ifdef CONFIG_X86_64
c8770e7b 2171 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 2172#endif
da8999d3
LJ
2173 if (vmx->host_state.msr_host_bndcfgs)
2174 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
45fc8757 2175 load_fixmap_gdt(raw_smp_processor_id());
33ed6329
AK
2176}
2177
a9b21b62
AK
2178static void vmx_load_host_state(struct vcpu_vmx *vmx)
2179{
2180 preempt_disable();
2181 __vmx_load_host_state(vmx);
2182 preempt_enable();
2183}
2184
28b835d6
FW
2185static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2186{
2187 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2188 struct pi_desc old, new;
2189 unsigned int dest;
2190
2191 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
2192 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2193 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW
2194 return;
2195
2196 do {
2197 old.control = new.control = pi_desc->control;
2198
2199 /*
2200 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2201 * are two possible cases:
2202 * 1. After running 'pre_block', context switch
2203 * happened. For this case, 'sn' was set in
2204 * vmx_vcpu_put(), so we need to clear it here.
2205 * 2. After running 'pre_block', we were blocked,
2206 * and woken up by some other guy. For this case,
2207 * we don't need to do anything, 'pi_post_block'
2208 * will do everything for us. However, we cannot
2209 * check whether it is case #1 or case #2 here
2210 * (maybe, not needed), so we also clear sn here,
2211 * I think it is not a big deal.
2212 */
2213 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2214 if (vcpu->cpu != cpu) {
2215 dest = cpu_physical_id(cpu);
2216
2217 if (x2apic_enabled())
2218 new.ndst = dest;
2219 else
2220 new.ndst = (dest << 8) & 0xFF00;
2221 }
2222
2223 /* set 'NV' to 'notification vector' */
2224 new.nv = POSTED_INTR_VECTOR;
2225 }
2226
2227 /* Allow posting non-urgent interrupts */
2228 new.sn = 0;
2229 } while (cmpxchg(&pi_desc->control, old.control,
2230 new.control) != old.control);
2231}
1be0e61c 2232
c95ba92a
PF
2233static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2234{
2235 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2236 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2237}
2238
6aa8b732
AK
2239/*
2240 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2241 * vcpu mutex is already taken.
2242 */
15ad7146 2243static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 2244{
a2fa3e9f 2245 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 2246 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 2247
b80c76ec 2248 if (!already_loaded) {
fe0e80be 2249 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 2250 local_irq_disable();
8f536b76 2251 crash_disable_local_vmclear(cpu);
5a560f8b
XG
2252
2253 /*
2254 * Read loaded_vmcs->cpu should be before fetching
2255 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2256 * See the comments in __loaded_vmcs_clear().
2257 */
2258 smp_rmb();
2259
d462b819
NHE
2260 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2261 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 2262 crash_enable_local_vmclear(cpu);
92fe13be 2263 local_irq_enable();
b80c76ec
JM
2264 }
2265
2266 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2267 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2268 vmcs_load(vmx->loaded_vmcs->vmcs);
2269 }
2270
2271 if (!already_loaded) {
59c58ceb 2272 void *gdt = get_current_gdt_ro();
b80c76ec
JM
2273 unsigned long sysenter_esp;
2274
2275 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 2276
6aa8b732
AK
2277 /*
2278 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 2279 * processors. See 22.2.4.
6aa8b732 2280 */
e0c23063
AL
2281 vmcs_writel(HOST_TR_BASE,
2282 (unsigned long)this_cpu_ptr(&cpu_tss));
59c58ceb 2283 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732 2284
b7ffc44d
AL
2285 /*
2286 * VM exits change the host TR limit to 0x67 after a VM
2287 * exit. This is okay, since 0x67 covers everything except
2288 * the IO bitmap and have have code to handle the IO bitmap
2289 * being lost after a VM exit.
2290 */
2291 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2292
6aa8b732
AK
2293 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2294 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 2295
d462b819 2296 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 2297 }
28b835d6 2298
2680d6da
OH
2299 /* Setup TSC multiplier */
2300 if (kvm_has_tsc_control &&
c95ba92a
PF
2301 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2302 decache_tsc_multiplier(vmx);
2680d6da 2303
28b835d6 2304 vmx_vcpu_pi_load(vcpu, cpu);
1be0e61c 2305 vmx->host_pkru = read_pkru();
28b835d6
FW
2306}
2307
2308static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2309{
2310 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2311
2312 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
2313 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2314 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW
2315 return;
2316
2317 /* Set SN when the vCPU is preempted */
2318 if (vcpu->preempted)
2319 pi_set_sn(pi_desc);
6aa8b732
AK
2320}
2321
2322static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2323{
28b835d6
FW
2324 vmx_vcpu_pi_put(vcpu);
2325
a9b21b62 2326 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK
2327}
2328
edcafe3c
AK
2329static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2330
fe3ef05c
NHE
2331/*
2332 * Return the cr0 value that a nested guest would read. This is a combination
2333 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2334 * its hypervisor (cr0_read_shadow).
2335 */
2336static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2337{
2338 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2339 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2340}
2341static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2342{
2343 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2344 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2345}
2346
6aa8b732
AK
2347static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2348{
78ac8b47 2349 unsigned long rflags, save_rflags;
345dcaa8 2350
6de12732
AK
2351 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2352 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2353 rflags = vmcs_readl(GUEST_RFLAGS);
2354 if (to_vmx(vcpu)->rmode.vm86_active) {
2355 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2356 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2357 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2358 }
2359 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2360 }
6de12732 2361 return to_vmx(vcpu)->rflags;
6aa8b732
AK
2362}
2363
2364static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2365{
6de12732
AK
2366 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2367 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK
2368 if (to_vmx(vcpu)->rmode.vm86_active) {
2369 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2370 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2371 }
6aa8b732
AK
2372 vmcs_writel(GUEST_RFLAGS, rflags);
2373}
2374
be94f6b7
HH
2375static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2376{
2377 return to_vmx(vcpu)->guest_pkru;
2378}
2379
37ccdcbe 2380static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC
2381{
2382 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2383 int ret = 0;
2384
2385 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2386 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2387 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2388 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2389
37ccdcbe 2390 return ret;
2809f5d2
GC
2391}
2392
2393static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2394{
2395 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2396 u32 interruptibility = interruptibility_old;
2397
2398 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2399
48005f64 2400 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2401 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2402 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC
2403 interruptibility |= GUEST_INTR_STATE_STI;
2404
2405 if ((interruptibility != interruptibility_old))
2406 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2407}
2408
6aa8b732
AK
2409static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2410{
2411 unsigned long rip;
6aa8b732 2412
5fdbf976 2413 rip = kvm_rip_read(vcpu);
6aa8b732 2414 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2415 kvm_rip_write(vcpu, rip);
6aa8b732 2416
2809f5d2
GC
2417 /* skipping an emulated instruction also counts */
2418 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK
2419}
2420
0b6ac343
NHE
2421/*
2422 * KVM wants to inject page-faults which it got to the guest. This function
2423 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2424 */
e011c663 2425static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE
2426{
2427 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2428
e011c663 2429 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE
2430 return 0;
2431
d4912215 2432 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
533558bc
JK
2433 vmcs_read32(VM_EXIT_INTR_INFO),
2434 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE
2435 return 1;
2436}
2437
298101da 2438static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR
2439 bool has_error_code, u32 error_code,
2440 bool reinject)
298101da 2441{
77ab6db0 2442 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2443 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2444
e011c663
GN
2445 if (!reinject && is_guest_mode(vcpu) &&
2446 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE
2447 return;
2448
8ab2d2e2 2449 if (has_error_code) {
77ab6db0 2450 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK
2451 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2452 }
77ab6db0 2453
7ffd92c5 2454 if (vmx->rmode.vm86_active) {
71f9833b
SH
2455 int inc_eip = 0;
2456 if (kvm_exception_is_soft(nr))
2457 inc_eip = vcpu->arch.event_exit_inst_len;
2458 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2459 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK
2460 return;
2461 }
2462
66fd3f7f
GN
2463 if (kvm_exception_is_soft(nr)) {
2464 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2465 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK
2466 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2467 } else
2468 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2469
2470 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK
2471}
2472
4e47c7a6
SY
2473static bool vmx_rdtscp_supported(void)
2474{
2475 return cpu_has_vmx_rdtscp();
2476}
2477
ad756a16
MJ
2478static bool vmx_invpcid_supported(void)
2479{
2480 return cpu_has_vmx_invpcid() && enable_ept;
2481}
2482
a75beee6
ED
2483/*
2484 * Swap MSR entry in host/guest MSR entry array.
2485 */
8b9cf98c 2486static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2487{
26bb0981 2488 struct shared_msr_entry tmp;
a2fa3e9f
GH
2489
2490 tmp = vmx->guest_msrs[to];
2491 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2492 vmx->guest_msrs[from] = tmp;
a75beee6
ED
2493}
2494
8d14695f
YZ
2495static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2496{
2497 unsigned long *msr_bitmap;
2498
670125bd 2499 if (is_guest_mode(vcpu))
d048c098 2500 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
3ce424e4
RK
2501 else if (cpu_has_secondary_exec_ctrls() &&
2502 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2503 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
f6e90f9e
WL
2504 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2505 if (is_long_mode(vcpu))
c63e4563 2506 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
f6e90f9e 2507 else
c63e4563 2508 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
f6e90f9e
WL
2509 } else {
2510 if (is_long_mode(vcpu))
c63e4563 2511 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
f6e90f9e 2512 else
c63e4563 2513 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
f6e90f9e 2514 }
8d14695f
YZ
2515 } else {
2516 if (is_long_mode(vcpu))
2517 msr_bitmap = vmx_msr_bitmap_longmode;
2518 else
2519 msr_bitmap = vmx_msr_bitmap_legacy;
2520 }
2521
2522 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2523}
2524
e38aea3e
AK
2525/*
2526 * Set up the vmcs to automatically save and restore system
2527 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2528 * mode, as fiddling with msrs is very expensive.
2529 */
8b9cf98c 2530static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2531{
26bb0981 2532 int save_nmsrs, index;
e38aea3e 2533
a75beee6
ED
2534 save_nmsrs = 0;
2535#ifdef CONFIG_X86_64
8b9cf98c 2536 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2537 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2538 if (index >= 0)
8b9cf98c
RR
2539 move_msr_up(vmx, index, save_nmsrs++);
2540 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2541 if (index >= 0)
8b9cf98c
RR
2542 move_msr_up(vmx, index, save_nmsrs++);
2543 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2544 if (index >= 0)
8b9cf98c 2545 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6 2546 index = __find_msr_index(vmx, MSR_TSC_AUX);
1cea0ce6 2547 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
4e47c7a6 2548 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2549 /*
8c06585d 2550 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED
2551 * if efer.sce is enabled.
2552 */
8c06585d 2553 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2554 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2555 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED
2556 }
2557#endif
92c0d900
AK
2558 index = __find_msr_index(vmx, MSR_EFER);
2559 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2560 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2561
26bb0981 2562 vmx->save_nmsrs = save_nmsrs;
5897297b 2563
8d14695f
YZ
2564 if (cpu_has_vmx_msr_bitmap())
2565 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK
2566}
2567
6aa8b732
AK
2568/*
2569 * reads and returns guest's timestamp counter "register"
be7b263e
HZ
2570 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2571 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
6aa8b732 2572 */
be7b263e 2573static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
6aa8b732
AK
2574{
2575 u64 host_tsc, tsc_offset;
2576
4ea1636b 2577 host_tsc = rdtsc();
6aa8b732 2578 tsc_offset = vmcs_read64(TSC_OFFSET);
be7b263e 2579 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
6aa8b732
AK
2580}
2581
2582/*
99e3e30a 2583 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2584 */
99e3e30a 2585static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2586{
27fc51b2 2587 if (is_guest_mode(vcpu)) {
7991825b 2588 /*
27fc51b2
NHE
2589 * We're here if L1 chose not to trap WRMSR to TSC. According
2590 * to the spec, this should set L1's TSC; The offset that L1
2591 * set for L2 remains unchanged, and still needs to be added
2592 * to the newly set TSC to get L2's TSC.
7991825b 2593 */
27fc51b2 2594 struct vmcs12 *vmcs12;
27fc51b2
NHE
2595 /* recalculate vmcs02.TSC_OFFSET: */
2596 vmcs12 = get_vmcs12(vcpu);
2597 vmcs_write64(TSC_OFFSET, offset +
2598 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2599 vmcs12->tsc_offset : 0));
2600 } else {
489223ed
YY
2601 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2602 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE
2603 vmcs_write64(TSC_OFFSET, offset);
2604 }
6aa8b732
AK
2605}
2606
801d3424
NHE
2607static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2608{
2609 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2610 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2611}
2612
2613/*
2614 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2615 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2616 * all guests if the "nested" module option is off, and can also be disabled
2617 * for a single guest by disabling its VMX cpuid bit.
2618 */
2619static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2620{
2621 return nested && guest_cpuid_has_vmx(vcpu);
2622}
2623
b87a51ae
NHE
2624/*
2625 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2626 * returned for the various VMX controls MSRs when nested VMX is enabled.
2627 * The same values should also be used to verify that vmcs12 control fields are
2628 * valid during nested entry from L1 to L2.
2629 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2630 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2631 * bit in the high half is on if the corresponding bit in the control field
2632 * may be on. See also vmx_control_verify().
b87a51ae 2633 */
b9c237bb 2634static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE
2635{
2636 /*
2637 * Note that as a general rule, the high half of the MSRs (bits in
2638 * the control fields which may be 1) should be initialized by the
2639 * intersection of the underlying hardware's MSR (i.e., features which
2640 * can be supported) and the list of features we want to expose -
2641 * because they are known to be properly supported in our code.
2642 * Also, usually, the low half of the MSRs (bits which must be 1) can
2643 * be set to 0, meaning that L1 may turn off any of these bits. The
2644 * reason is that if one of these bits is necessary, it will appear
2645 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2646 * fields of vmcs01 and vmcs02, will turn these bits off - and
2647 * nested_vmx_exit_handled() will not pass related exits to L1.
2648 * These rules have exceptions below.
2649 */
2650
2651 /* pin-based controls */
eabeaacc 2652 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV
2653 vmx->nested.nested_vmx_pinbased_ctls_low,
2654 vmx->nested.nested_vmx_pinbased_ctls_high);
2655 vmx->nested.nested_vmx_pinbased_ctls_low |=
2656 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2657 vmx->nested.nested_vmx_pinbased_ctls_high &=
2658 PIN_BASED_EXT_INTR_MASK |
2659 PIN_BASED_NMI_EXITING |
2660 PIN_BASED_VIRTUAL_NMIS;
2661 vmx->nested.nested_vmx_pinbased_ctls_high |=
2662 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2663 PIN_BASED_VMX_PREEMPTION_TIMER;
d62caabb 2664 if (kvm_vcpu_apicv_active(&vmx->vcpu))
705699a1
WV
2665 vmx->nested.nested_vmx_pinbased_ctls_high |=
2666 PIN_BASED_POSTED_INTR;
b87a51ae 2667
3dbcd8da 2668 /* exit controls */
c0dfee58 2669 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV
2670 vmx->nested.nested_vmx_exit_ctls_low,
2671 vmx->nested.nested_vmx_exit_ctls_high);
2672 vmx->nested.nested_vmx_exit_ctls_low =
2673 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2674
b9c237bb 2675 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2676#ifdef CONFIG_X86_64
c0dfee58 2677 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2678#endif
f4124500 2679 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV
2680 vmx->nested.nested_vmx_exit_ctls_high |=
2681 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2682 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD
2683 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2684
a87036ad 2685 if (kvm_mpx_supported())
b9c237bb 2686 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2687
2996fca0 2688 /* We support free control of debug control saving. */
0115f9cb 2689 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2996fca0 2690
b87a51ae
NHE
2691 /* entry controls */
2692 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV
2693 vmx->nested.nested_vmx_entry_ctls_low,
2694 vmx->nested.nested_vmx_entry_ctls_high);
2695 vmx->nested.nested_vmx_entry_ctls_low =
2696 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2697 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK
2698#ifdef CONFIG_X86_64
2699 VM_ENTRY_IA32E_MODE |
2700#endif
2701 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV
2702 vmx->nested.nested_vmx_entry_ctls_high |=
2703 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
a87036ad 2704 if (kvm_mpx_supported())
b9c237bb 2705 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2706
2996fca0 2707 /* We support free control of debug control loading. */
0115f9cb 2708 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2996fca0 2709
b87a51ae
NHE
2710 /* cpu-based controls */
2711 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV
2712 vmx->nested.nested_vmx_procbased_ctls_low,
2713 vmx->nested.nested_vmx_procbased_ctls_high);
2714 vmx->nested.nested_vmx_procbased_ctls_low =
2715 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2716 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK
2717 CPU_BASED_VIRTUAL_INTR_PENDING |
2718 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE
2719 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2720 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2721 CPU_BASED_CR3_STORE_EXITING |
2722#ifdef CONFIG_X86_64
2723 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2724#endif
2725 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD
2726 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2727 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2728 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2729 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE
2730 /*
2731 * We can allow some features even when not supported by the
2732 * hardware. For example, L1 can specify an MSR bitmap - and we
2733 * can use it to avoid exits to L1 - even when L0 runs L2
2734 * without MSR bitmaps.
2735 */
b9c237bb
WV
2736 vmx->nested.nested_vmx_procbased_ctls_high |=
2737 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2738 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2739
3dcdf3ec 2740 /* We support free control of CR3 access interception. */
0115f9cb 2741 vmx->nested.nested_vmx_procbased_ctls_low &=
3dcdf3ec
JK
2742 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2743
b87a51ae
NHE
2744 /* secondary cpu-based controls */
2745 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV
2746 vmx->nested.nested_vmx_secondary_ctls_low,
2747 vmx->nested.nested_vmx_secondary_ctls_high);
2748 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2749 vmx->nested.nested_vmx_secondary_ctls_high &=
a5f46457 2750 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
d6851fbe 2751 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2752 SECONDARY_EXEC_RDTSCP |
1b07304c 2753 SECONDARY_EXEC_DESC |
f2b93280 2754 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2755 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2756 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7 2757 SECONDARY_EXEC_WBINVD_EXITING |
dfa169bb 2758 SECONDARY_EXEC_XSAVES;
c18911a2 2759
afa61f75
NHE
2760 if (enable_ept) {
2761 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2762 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2763 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2764 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
7db74265 2765 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
02120c45
BD
2766 if (cpu_has_vmx_ept_execute_only())
2767 vmx->nested.nested_vmx_ept_caps |=
2768 VMX_EPT_EXECUTE_ONLY_BIT;
b9c237bb 2769 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
45e11817 2770 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
7db74265
PB
2771 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2772 VMX_EPT_1GB_PAGE_BIT;
03efce6f
BD
2773 if (enable_ept_ad_bits) {
2774 vmx->nested.nested_vmx_secondary_ctls_high |=
2775 SECONDARY_EXEC_ENABLE_PML;
7461fbc4 2776 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
03efce6f 2777 }
afa61f75 2778 } else
b9c237bb 2779 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2780
ef697a71
PB
2781 /*
2782 * Old versions of KVM use the single-context version without
2783 * checking for support, so declare that it is supported even
2784 * though it is treated as global context. The alternative is
2785 * not failing the single-context invvpid, and it is worse.
2786 */
63cb6d5f
WL
2787 if (enable_vpid) {
2788 vmx->nested.nested_vmx_secondary_ctls_high |=
2789 SECONDARY_EXEC_ENABLE_VPID;
089d7b6e 2790 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
bcdde302 2791 VMX_VPID_EXTENT_SUPPORTED_MASK;
63cb6d5f 2792 } else
089d7b6e 2793 vmx->nested.nested_vmx_vpid_caps = 0;
99b83ac8 2794
0790ec17
RK
2795 if (enable_unrestricted_guest)
2796 vmx->nested.nested_vmx_secondary_ctls_high |=
2797 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2798
c18911a2 2799 /* miscellaneous data */
b9c237bb
WV
2800 rdmsr(MSR_IA32_VMX_MISC,
2801 vmx->nested.nested_vmx_misc_low,
2802 vmx->nested.nested_vmx_misc_high);
2803 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2804 vmx->nested.nested_vmx_misc_low |=
2805 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2806 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2807 vmx->nested.nested_vmx_misc_high = 0;
62cc6b9d
DM
2808
2809 /*
2810 * This MSR reports some information about VMX support. We
2811 * should return information about the VMX we emulate for the
2812 * guest, and the VMCS structure we give it - not about the
2813 * VMX support of the underlying hardware.
2814 */
2815 vmx->nested.nested_vmx_basic =
2816 VMCS12_REVISION |
2817 VMX_BASIC_TRUE_CTLS |
2818 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2819 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2820
2821 if (cpu_has_vmx_basic_inout())
2822 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2823
2824 /*
8322ebbb 2825 * These MSRs specify bits which the guest must keep fixed on
62cc6b9d
DM
2826 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2827 * We picked the standard core2 setting.
2828 */
2829#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2830#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2831 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
62cc6b9d 2832 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
8322ebbb
DM
2833
2834 /* These MSRs specify bits which the guest must keep fixed off. */
2835 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2836 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
62cc6b9d
DM
2837
2838 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2839 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
b87a51ae
NHE
2840}
2841
3899152c
DM
2842/*
2843 * if fixed0[i] == 1: val[i] must be 1
2844 * if fixed1[i] == 0: val[i] must be 0
2845 */
2846static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2847{
2848 return ((val & fixed1) | fixed0) == val;
b87a51ae
NHE
2849}
2850
2851static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2852{
3899152c 2853 return fixed_bits_valid(control, low, high);
b87a51ae
NHE
2854}
2855
2856static inline u64 vmx_control_msr(u32 low, u32 high)
2857{
2858 return low | ((u64)high << 32);
2859}
2860
62cc6b9d
DM
2861static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2862{
2863 superset &= mask;
2864 subset &= mask;
2865
2866 return (superset | subset) == superset;
2867}
2868
2869static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2870{
2871 const u64 feature_and_reserved =
2872 /* feature (except bit 48; see below) */
2873 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2874 /* reserved */
2875 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2876 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2877
2878 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2879 return -EINVAL;
2880
2881 /*
2882 * KVM does not emulate a version of VMX that constrains physical
2883 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2884 */
2885 if (data & BIT_ULL(48))
2886 return -EINVAL;
2887
2888 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2889 vmx_basic_vmcs_revision_id(data))
2890 return -EINVAL;
2891
2892 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2893 return -EINVAL;
2894
2895 vmx->nested.nested_vmx_basic = data;
2896 return 0;
2897}
2898
2899static int
2900vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2901{
2902 u64 supported;
2903 u32 *lowp, *highp;
2904
2905 switch (msr_index) {
2906 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2907 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2908 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2909 break;
2910 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2911 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2912 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2913 break;
2914 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2915 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2916 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2917 break;
2918 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2919 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2920 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2921 break;
2922 case MSR_IA32_VMX_PROCBASED_CTLS2:
2923 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2924 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2925 break;
2926 default:
2927 BUG();
2928 }
2929
2930 supported = vmx_control_msr(*lowp, *highp);
2931
2932 /* Check must-be-1 bits are still 1. */
2933 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2934 return -EINVAL;
2935
2936 /* Check must-be-0 bits are still 0. */
2937 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2938 return -EINVAL;
2939
2940 *lowp = data;
2941 *highp = data >> 32;
2942 return 0;
2943}
2944
2945static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2946{
2947 const u64 feature_and_reserved_bits =
2948 /* feature */
2949 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2950 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2951 /* reserved */
2952 GENMASK_ULL(13, 9) | BIT_ULL(31);
2953 u64 vmx_misc;
2954
2955 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2956 vmx->nested.nested_vmx_misc_high);
2957
2958 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2959 return -EINVAL;
2960
2961 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2962 PIN_BASED_VMX_PREEMPTION_TIMER) &&
2963 vmx_misc_preemption_timer_rate(data) !=
2964 vmx_misc_preemption_timer_rate(vmx_misc))
2965 return -EINVAL;
2966
2967 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2968 return -EINVAL;
2969
2970 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2971 return -EINVAL;
2972
2973 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2974 return -EINVAL;
2975
2976 vmx->nested.nested_vmx_misc_low = data;
2977 vmx->nested.nested_vmx_misc_high = data >> 32;
2978 return 0;
2979}
2980
2981static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2982{
2983 u64 vmx_ept_vpid_cap;
2984
2985 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2986 vmx->nested.nested_vmx_vpid_caps);
2987
2988 /* Every bit is either reserved or a feature bit. */
2989 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2990 return -EINVAL;
2991
2992 vmx->nested.nested_vmx_ept_caps = data;
2993 vmx->nested.nested_vmx_vpid_caps = data >> 32;
2994 return 0;
2995}
2996
2997static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2998{
2999 u64 *msr;
3000
3001 switch (msr_index) {
3002 case MSR_IA32_VMX_CR0_FIXED0:
3003 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3004 break;
3005 case MSR_IA32_VMX_CR4_FIXED0:
3006 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3007 break;
3008 default:
3009 BUG();
3010 }
3011
3012 /*
3013 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3014 * must be 1 in the restored value.
3015 */
3016 if (!is_bitwise_subset(data, *msr, -1ULL))
3017 return -EINVAL;
3018
3019 *msr = data;
3020 return 0;
3021}
3022
3023/*
3024 * Called when userspace is restoring VMX MSRs.
3025 *
3026 * Returns 0 on success, non-0 otherwise.
3027 */
3028static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
b87a51ae 3029{
b9c237bb
WV
3030 struct vcpu_vmx *vmx = to_vmx(vcpu);
3031
b87a51ae 3032 switch (msr_index) {
b87a51ae 3033 case MSR_IA32_VMX_BASIC:
62cc6b9d
DM
3034 return vmx_restore_vmx_basic(vmx, data);
3035 case MSR_IA32_VMX_PINBASED_CTLS:
3036 case MSR_IA32_VMX_PROCBASED_CTLS:
3037 case MSR_IA32_VMX_EXIT_CTLS:
3038 case MSR_IA32_VMX_ENTRY_CTLS:
b87a51ae 3039 /*
62cc6b9d
DM
3040 * The "non-true" VMX capability MSRs are generated from the
3041 * "true" MSRs, so we do not support restoring them directly.
3042 *
3043 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3044 * should restore the "true" MSRs with the must-be-1 bits
3045 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3046 * DEFAULT SETTINGS".
b87a51ae 3047 */
62cc6b9d
DM
3048 return -EINVAL;
3049 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3050 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3051 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3052 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3053 case MSR_IA32_VMX_PROCBASED_CTLS2:
3054 return vmx_restore_control_msr(vmx, msr_index, data);
3055 case MSR_IA32_VMX_MISC:
3056 return vmx_restore_vmx_misc(vmx, data);
3057 case MSR_IA32_VMX_CR0_FIXED0:
3058 case MSR_IA32_VMX_CR4_FIXED0:
3059 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3060 case MSR_IA32_VMX_CR0_FIXED1:
3061 case MSR_IA32_VMX_CR4_FIXED1:
3062 /*
3063 * These MSRs are generated based on the vCPU's CPUID, so we
3064 * do not support restoring them directly.
3065 */
3066 return -EINVAL;
3067 case MSR_IA32_VMX_EPT_VPID_CAP:
3068 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3069 case MSR_IA32_VMX_VMCS_ENUM:
3070 vmx->nested.nested_vmx_vmcs_enum = data;
3071 return 0;
3072 default:
b87a51ae 3073 /*
62cc6b9d 3074 * The rest of the VMX capability MSRs do not support restore.
b87a51ae 3075 */
62cc6b9d
DM
3076 return -EINVAL;
3077 }
3078}
3079
3080/* Returns 0 on success, non-0 otherwise. */
3081static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3082{
3083 struct vcpu_vmx *vmx = to_vmx(vcpu);
3084
3085 switch (msr_index) {
3086 case MSR_IA32_VMX_BASIC:
3087 *pdata = vmx->nested.nested_vmx_basic;
b87a51ae
NHE
3088 break;
3089 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3090 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV
3091 *pdata = vmx_control_msr(
3092 vmx->nested.nested_vmx_pinbased_ctls_low,
3093 vmx->nested.nested_vmx_pinbased_ctls_high);
0115f9cb
DM
3094 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3095 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3096 break;
3097 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3098 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV
3099 *pdata = vmx_control_msr(
3100 vmx->nested.nested_vmx_procbased_ctls_low,
3101 vmx->nested.nested_vmx_procbased_ctls_high);
0115f9cb
DM
3102 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3103 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3104 break;
3105 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3106 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV
3107 *pdata = vmx_control_msr(
3108 vmx->nested.nested_vmx_exit_ctls_low,
3109 vmx->nested.nested_vmx_exit_ctls_high);
0115f9cb
DM
3110 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3111 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3112 break;
3113 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3114 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV
3115 *pdata = vmx_control_msr(
3116 vmx->nested.nested_vmx_entry_ctls_low,
3117 vmx->nested.nested_vmx_entry_ctls_high);
0115f9cb
DM
3118 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3119 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3120 break;
3121 case MSR_IA32_VMX_MISC:
b9c237bb
WV
3122 *pdata = vmx_control_msr(
3123 vmx->nested.nested_vmx_misc_low,
3124 vmx->nested.nested_vmx_misc_high);
b87a51ae 3125 break;
b87a51ae 3126 case MSR_IA32_VMX_CR0_FIXED0:
62cc6b9d 3127 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
b87a51ae
NHE
3128 break;
3129 case MSR_IA32_VMX_CR0_FIXED1:
62cc6b9d 3130 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
b87a51ae
NHE
3131 break;
3132 case MSR_IA32_VMX_CR4_FIXED0:
62cc6b9d 3133 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
b87a51ae
NHE
3134 break;
3135 case MSR_IA32_VMX_CR4_FIXED1:
62cc6b9d 3136 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
b87a51ae
NHE
3137 break;
3138 case MSR_IA32_VMX_VMCS_ENUM:
62cc6b9d 3139 *pdata = vmx->nested.nested_vmx_vmcs_enum;
b87a51ae
NHE
3140 break;
3141 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV
3142 *pdata = vmx_control_msr(
3143 vmx->nested.nested_vmx_secondary_ctls_low,
3144 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE
3145 break;
3146 case MSR_IA32_VMX_EPT_VPID_CAP:
089d7b6e
WL
3147 *pdata = vmx->nested.nested_vmx_ept_caps |
3148 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
b87a51ae
NHE
3149 break;
3150 default:
b87a51ae 3151 return 1;
b3897a49
NHE
3152 }
3153
b87a51ae
NHE
3154 return 0;
3155}
3156
37e4c997
HZ
3157static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3158 uint64_t val)
3159{
3160 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3161
3162 return !(val & ~valid_bits);
3163}
3164
6aa8b732
AK
3165/*
3166 * Reads an msr value (of 'msr_index') into 'pdata'.
3167 * Returns 0 on success, non-0 otherwise.
3168 * Assumes vcpu_load() was already called.
3169 */
609e36d3 3170static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 3171{
26bb0981 3172 struct shared_msr_entry *msr;
6aa8b732 3173
609e36d3 3174 switch (msr_info->index) {
05b3e0c2 3175#ifdef CONFIG_X86_64
6aa8b732 3176 case MSR_FS_BASE:
609e36d3 3177 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK
3178 break;
3179 case MSR_GS_BASE:
609e36d3 3180 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 3181 break;
44ea2b17
AK
3182 case MSR_KERNEL_GS_BASE:
3183 vmx_load_host_state(to_vmx(vcpu));
609e36d3 3184 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 3185 break;
26bb0981 3186#endif
6aa8b732 3187 case MSR_EFER:
609e36d3 3188 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 3189 case MSR_IA32_TSC:
be7b263e 3190 msr_info->data = guest_read_tsc(vcpu);
6aa8b732
AK
3191 break;
3192 case MSR_IA32_SYSENTER_CS:
609e36d3 3193 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK
3194 break;
3195 case MSR_IA32_SYSENTER_EIP:
609e36d3 3196 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK
3197 break;
3198 case MSR_IA32_SYSENTER_ESP:
609e36d3 3199 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 3200 break;
0dd376e7 3201 case MSR_IA32_BNDCFGS:
691bd434
HZ
3202 if (!kvm_mpx_supported() ||
3203 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
93c4adc7 3204 return 1;
609e36d3 3205 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 3206 break;
c45dcc71
AR
3207 case MSR_IA32_MCG_EXT_CTL:
3208 if (!msr_info->host_initiated &&
3209 !(to_vmx(vcpu)->msr_ia32_feature_control &
3210 FEATURE_CONTROL_LMCE))
cae50139 3211 return 1;
c45dcc71
AR
3212 msr_info->data = vcpu->arch.mcg_ext_ctl;
3213 break;
cae50139 3214 case MSR_IA32_FEATURE_CONTROL:
3b84080b 3215 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
cae50139
JK
3216 break;
3217 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3218 if (!nested_vmx_allowed(vcpu))
3219 return 1;
609e36d3 3220 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL
3221 case MSR_IA32_XSS:
3222 if (!vmx_xsaves_supported())
3223 return 1;
609e36d3 3224 msr_info->data = vcpu->arch.ia32_xss;
20300099 3225 break;
4e47c7a6 3226 case MSR_TSC_AUX:
81b1b9ca 3227 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
4e47c7a6
SY
3228 return 1;
3229 /* Otherwise falls through */
6aa8b732 3230 default:
609e36d3 3231 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 3232 if (msr) {
609e36d3 3233 msr_info->data = msr->data;
3bab1f5d 3234 break;
6aa8b732 3235 }
609e36d3 3236 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK
3237 }
3238
6aa8b732
AK
3239 return 0;
3240}
3241
cae50139
JK
3242static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3243
6aa8b732
AK
3244/*
3245 * Writes msr value into into the appropriate "register".
3246 * Returns 0 on success, non-0 otherwise.
3247 * Assumes vcpu_load() was already called.
3248 */
8fe8ab46 3249static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 3250{
a2fa3e9f 3251 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 3252 struct shared_msr_entry *msr;
2cc51560 3253 int ret = 0;
8fe8ab46
WA
3254 u32 msr_index = msr_info->index;
3255 u64 data = msr_info->data;
2cc51560 3256
6aa8b732 3257 switch (msr_index) {
3bab1f5d 3258 case MSR_EFER:
8fe8ab46 3259 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 3260 break;
16175a79 3261#ifdef CONFIG_X86_64
6aa8b732 3262 case MSR_FS_BASE:
2fb92db1 3263 vmx_segment_cache_clear(vmx);
6aa8b732
AK
3264 vmcs_writel(GUEST_FS_BASE, data);
3265 break;
3266 case MSR_GS_BASE:
2fb92db1 3267 vmx_segment_cache_clear(vmx);
6aa8b732
AK
3268 vmcs_writel(GUEST_GS_BASE, data);
3269 break;
44ea2b17
AK
3270 case MSR_KERNEL_GS_BASE:
3271 vmx_load_host_state(vmx);
3272 vmx->msr_guest_kernel_gs_base = data;
3273 break;
6aa8b732
AK
3274#endif
3275 case MSR_IA32_SYSENTER_CS:
3276 vmcs_write32(GUEST_SYSENTER_CS, data);
3277 break;
3278 case MSR_IA32_SYSENTER_EIP:
f5b42c33 3279 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK
3280 break;
3281 case MSR_IA32_SYSENTER_ESP:
f5b42c33 3282 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 3283 break;
0dd376e7 3284 case MSR_IA32_BNDCFGS:
691bd434
HZ
3285 if (!kvm_mpx_supported() ||
3286 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
93c4adc7 3287 return 1;
4531662d
JM
3288 if (is_noncanonical_address(data & PAGE_MASK) ||
3289 (data & MSR_IA32_BNDCFGS_RSVD))
93c4adc7 3290 return 1;
0dd376e7
LJ
3291 vmcs_write64(GUEST_BNDCFGS, data);
3292 break;
af24a4e4 3293 case MSR_IA32_TSC:
8fe8ab46 3294 kvm_write_tsc(vcpu, msr_info);
6aa8b732 3295 break;
468d472f
SY
3296 case MSR_IA32_CR_PAT:
3297 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA
3298 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3299 return 1;
468d472f
SY
3300 vmcs_write64(GUEST_IA32_PAT, data);
3301 vcpu->arch.pat = data;
3302 break;
3303 }
8fe8ab46 3304 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 3305 break;
ba904635
WA
3306 case MSR_IA32_TSC_ADJUST:
3307 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 3308 break;
c45dcc71
AR
3309 case MSR_IA32_MCG_EXT_CTL:
3310 if ((!msr_info->host_initiated &&
3311 !(to_vmx(vcpu)->msr_ia32_feature_control &
3312 FEATURE_CONTROL_LMCE)) ||
3313 (data & ~MCG_EXT_CTL_LMCE_EN))
3314 return 1;
3315 vcpu->arch.mcg_ext_ctl = data;
3316 break;
cae50139 3317 case MSR_IA32_FEATURE_CONTROL:
37e4c997 3318 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 3319 (to_vmx(vcpu)->msr_ia32_feature_control &
cae50139
JK
3320 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3321 return 1;
3b84080b 3322 vmx->msr_ia32_feature_control = data;
cae50139
JK
3323 if (msr_info->host_initiated && data == 0)
3324 vmx_leave_nested(vcpu);
3325 break;
3326 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM
3327 if (!msr_info->host_initiated)
3328 return 1; /* they are read-only */
3329 if (!nested_vmx_allowed(vcpu))
3330 return 1;
3331 return vmx_set_vmx_msr(vcpu, msr_index, data);
20300099
WL
3332 case MSR_IA32_XSS:
3333 if (!vmx_xsaves_supported())
3334 return 1;
3335 /*
3336 * The only supported bit as of Skylake is bit 8, but
3337 * it is not supported on KVM.
3338 */
3339 if (data != 0)
3340 return 1;
3341 vcpu->arch.ia32_xss = data;
3342 if (vcpu->arch.ia32_xss != host_xss)
3343 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3344 vcpu->arch.ia32_xss, host_xss);
3345 else
3346 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3347 break;
4e47c7a6 3348 case MSR_TSC_AUX:
81b1b9ca 3349 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
4e47c7a6
SY
3350 return 1;
3351 /* Check reserved bit, higher 32 bits should be zero */
3352 if ((data >> 32) != 0)
3353 return 1;
3354 /* Otherwise falls through */
6aa8b732 3355 default:
8b9cf98c 3356 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 3357 if (msr) {
8b3c3104 3358 u64 old_msr_data = msr->data;
3bab1f5d 3359 msr->data = data;
2225fd56
AK
3360 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3361 preempt_disable();
8b3c3104
AH
3362 ret = kvm_set_shared_msr(msr->index, msr->data,
3363 msr->mask);
2225fd56 3364 preempt_enable();
8b3c3104
AH
3365 if (ret)
3366 msr->data = old_msr_data;
2225fd56 3367 }
3bab1f5d 3368 break;
6aa8b732 3369 }
8fe8ab46 3370 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK
3371 }
3372
2cc51560 3373 return ret;
6aa8b732
AK
3374}
3375
5fdbf976 3376static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 3377{
5fdbf976
MT
3378 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3379 switch (reg) {
3380 case VCPU_REGS_RSP:
3381 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3382 break;
3383 case VCPU_REGS_RIP:
3384 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3385 break;
6de4f3ad
AK
3386 case VCPU_EXREG_PDPTR:
3387 if (enable_ept)
3388 ept_save_pdptrs(vcpu);
3389 break;
5fdbf976
MT
3390 default:
3391 break;
3392 }
6aa8b732
AK
3393}
3394
6aa8b732
AK
3395static __init int cpu_has_kvm_support(void)
3396{
6210e37b 3397 return cpu_has_vmx();
6aa8b732
AK
3398}
3399
3400static __init int vmx_disabled_by_bios(void)
3401{
3402 u64 msr;
3403
3404 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 3405 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 3406 /* launched w/ TXT and VMX disabled */
cafd6659
SW
3407 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3408 && tboot_enabled())
3409 return 1;
23f3e991 3410 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 3411 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 3412 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW
3413 && !tboot_enabled()) {
3414 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 3415 "activate TXT before enabling KVM\n");
cafd6659 3416 return 1;
f9335afe 3417 }
23f3e991
JC
3418 /* launched w/o TXT and VMX disabled */
3419 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3420 && !tboot_enabled())
3421 return 1;
cafd6659
SW
3422 }
3423
3424 return 0;
6aa8b732
AK
3425}
3426
7725b894
DX
3427static void kvm_cpu_vmxon(u64 addr)
3428{
fe0e80be 3429 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS
3430 intel_pt_handle_vmx(1);
3431
7725b894
DX
3432 asm volatile (ASM_VMX_VMXON_RAX
3433 : : "a"(&addr), "m"(addr)
3434 : "memory", "cc");
3435}
3436
13a34e06 3437static int hardware_enable(void)
6aa8b732
AK
3438{
3439 int cpu = raw_smp_processor_id();
3440 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 3441 u64 old, test_bits;
6aa8b732 3442
1e02ce4c 3443 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG
3444 return -EBUSY;
3445
d462b819 3446 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW
3447 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3448 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY
3449
3450 /*
3451 * Now we can enable the vmclear operation in kdump
3452 * since the loaded_vmcss_on_cpu list on this cpu
3453 * has been initialized.
3454 *
3455 * Though the cpu is not in VMX operation now, there
3456 * is no problem to enable the vmclear operation
3457 * for the loaded_vmcss_on_cpu list is empty!
3458 */
3459 crash_enable_local_vmclear(cpu);
3460
6aa8b732 3461 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW
3462
3463 test_bits = FEATURE_CONTROL_LOCKED;
3464 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3465 if (tboot_enabled())
3466 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3467
3468 if ((old & test_bits) != test_bits) {
6aa8b732 3469 /* enable and lock */
cafd6659
SW
3470 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3471 }
fe0e80be
DH
3472 kvm_cpu_vmxon(phys_addr);
3473 ept_sync_global();
10474ae8
AG
3474
3475 return 0;
6aa8b732
AK
3476}
3477
d462b819 3478static void vmclear_local_loaded_vmcss(void)
543e4243
AK
3479{
3480 int cpu = raw_smp_processor_id();
d462b819 3481 struct loaded_vmcs *v, *n;
543e4243 3482
d462b819
NHE
3483 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3484 loaded_vmcss_on_cpu_link)
3485 __loaded_vmcs_clear(v);
543e4243
AK
3486}
3487
710ff4a8
EH
3488
3489/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3490 * tricks.
3491 */
3492static void kvm_cpu_vmxoff(void)
6aa8b732 3493{
4ecac3fd 3494 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1c5ac21a
AS
3495
3496 intel_pt_handle_vmx(0);
fe0e80be 3497 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK
3498}
3499
13a34e06 3500static void hardware_disable(void)
710ff4a8 3501{
fe0e80be
DH
3502 vmclear_local_loaded_vmcss();
3503 kvm_cpu_vmxoff();
710ff4a8
EH
3504}
3505
1c3d14fe 3506static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 3507 u32 msr, u32 *result)
1c3d14fe
YS
3508{
3509 u32 vmx_msr_low, vmx_msr_high;
3510 u32 ctl = ctl_min | ctl_opt;
3511
3512 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3513
3514 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3515 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3516
3517 /* Ensure minimum (required) set of control bits are supported. */
3518 if (ctl_min & ~ctl)
002c7f7c 3519 return -EIO;
1c3d14fe
YS
3520
3521 *result = ctl;
3522 return 0;
3523}
3524
110312c8
AK
3525static __init bool allow_1_setting(u32 msr, u32 ctl)
3526{
3527 u32 vmx_msr_low, vmx_msr_high;
3528
3529 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3530 return vmx_msr_high & ctl;
3531}
3532
002c7f7c 3533static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK
3534{
3535 u32 vmx_msr_low, vmx_msr_high;
d56f546d 3536 u32 min, opt, min2, opt2;
1c3d14fe
YS
3537 u32 _pin_based_exec_control = 0;
3538 u32 _cpu_based_exec_control = 0;
f78e0e2e 3539 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS
3540 u32 _vmexit_control = 0;
3541 u32 _vmentry_control = 0;
3542
10166744 3543 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS
3544#ifdef CONFIG_X86_64
3545 CPU_BASED_CR8_LOAD_EXITING |
3546 CPU_BASED_CR8_STORE_EXITING |
3547#endif
d56f546d
SY
3548 CPU_BASED_CR3_LOAD_EXITING |
3549 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS
3550 CPU_BASED_USE_IO_BITMAPS |
3551 CPU_BASED_MOV_DR_EXITING |
a7052897 3552 CPU_BASED_USE_TSC_OFFSETING |
fee84b07
AK
3553 CPU_BASED_INVLPG_EXITING |
3554 CPU_BASED_RDPMC_EXITING;
443381a8 3555
668fffa3
MT
3556 if (!kvm_mwait_in_guest())
3557 min |= CPU_BASED_MWAIT_EXITING |
3558 CPU_BASED_MONITOR_EXITING;
3559
f78e0e2e 3560 opt = CPU_BASED_TPR_SHADOW |
25c5f225 3561 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 3562 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS
3563 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3564 &_cpu_based_exec_control) < 0)
002c7f7c 3565 return -EIO;
6e5d865c
YS
3566#ifdef CONFIG_X86_64
3567 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3568 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3569 ~CPU_BASED_CR8_STORE_EXITING;
3570#endif
f78e0e2e 3571 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY
3572 min2 = 0;
3573 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3574 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3575 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3576 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3577 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3578 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3579 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3580 SECONDARY_EXEC_RDTSCP |
83d4c286 3581 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3582 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3583 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3584 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 3585 SECONDARY_EXEC_XSAVES |
8b3e34e4 3586 SECONDARY_EXEC_ENABLE_PML |
64903d61 3587 SECONDARY_EXEC_TSC_SCALING;
d56f546d
SY
3588 if (adjust_vmx_controls(min2, opt2,
3589 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY
3590 &_cpu_based_2nd_exec_control) < 0)
3591 return -EIO;
3592 }
3593#ifndef CONFIG_X86_64
3594 if (!(_cpu_based_2nd_exec_control &
3595 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3596 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3597#endif
83d4c286
YZ
3598
3599 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3600 _cpu_based_2nd_exec_control &= ~(
8d14695f 3601 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ
3602 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3603 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3604
d56f546d 3605 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT
3606 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3607 enabled */
5fff7d27
GN
3608 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3609 CPU_BASED_CR3_STORE_EXITING |
3610 CPU_BASED_INVLPG_EXITING);
d56f546d
SY
3611 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3612 vmx_capability.ept, vmx_capability.vpid);
3613 }
1c3d14fe 3614
91fa0f8e 3615 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS
3616#ifdef CONFIG_X86_64
3617 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3618#endif
a547c6db 3619 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
91fa0f8e 3620 VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS
3621 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3622 &_vmexit_control) < 0)
002c7f7c 3623 return -EIO;
1c3d14fe 3624
2c82878b
PB
3625 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3626 PIN_BASED_VIRTUAL_NMIS;
3627 opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ
3628 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3629 &_pin_based_exec_control) < 0)
3630 return -EIO;
3631
1c17c3e6
PB
3632 if (cpu_has_broken_vmx_preemption_timer())
3633 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 3634 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 3635 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ
3636 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3637
c845f9c6 3638 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3639 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS
3640 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3641 &_vmentry_control) < 0)
002c7f7c 3642 return -EIO;
6aa8b732 3643
c68876fd 3644 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS
3645
3646 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3647 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3648 return -EIO;
1c3d14fe
YS
3649
3650#ifdef CONFIG_X86_64
3651 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3652 if (vmx_msr_high & (1u<<16))
002c7f7c 3653 return -EIO;
1c3d14fe
YS
3654#endif
3655
3656 /* Require Write-Back (WB) memory type for VMCS accesses. */
3657 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3658 return -EIO;
1c3d14fe 3659
002c7f7c 3660 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 3661 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 3662 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
002c7f7c 3663 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3664
002c7f7c
YS
3665 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3666 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3667 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS
3668 vmcs_conf->vmexit_ctrl = _vmexit_control;
3669 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3670
110312c8
AK
3671 cpu_has_load_ia32_efer =
3672 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3673 VM_ENTRY_LOAD_IA32_EFER)
3674 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3675 VM_EXIT_LOAD_IA32_EFER);
3676
8bf00a52
GN
3677 cpu_has_load_perf_global_ctrl =
3678 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3679 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3680 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3681 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3682
3683 /*
3684 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
bb3541f1 3685 * but due to errata below it can't be used. Workaround is to use
8bf00a52
GN
3686 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3687 *
3688 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3689 *
3690 * AAK155 (model 26)
3691 * AAP115 (model 30)
3692 * AAT100 (model 37)
3693 * BC86,AAY89,BD102 (model 44)
3694 * BA97 (model 46)
3695 *
3696 */
3697 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3698 switch (boot_cpu_data.x86_model) {
3699 case 26:
3700 case 30:
3701 case 37:
3702 case 44:
3703 case 46:
3704 cpu_has_load_perf_global_ctrl = false;
3705 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3706 "does not work properly. Using workaround\n");
3707 break;
3708 default:
3709 break;
3710 }
3711 }
3712
782511b0 3713 if (boot_cpu_has(X86_FEATURE_XSAVES))
20300099
WL
3714 rdmsrl(MSR_IA32_XSS, host_xss);
3715
1c3d14fe 3716 return 0;
c68876fd 3717}
6aa8b732
AK
3718
3719static struct vmcs *alloc_vmcs_cpu(int cpu)
3720{
3721 int node = cpu_to_node(cpu);
3722 struct page *pages;
3723 struct vmcs *vmcs;
3724
96db800f 3725 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK
3726 if (!pages)
3727 return NULL;
3728 vmcs = page_address(pages);
1c3d14fe
YS
3729 memset(vmcs, 0, vmcs_config.size);
3730 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK
3731 return vmcs;
3732}
3733
3734static struct vmcs *alloc_vmcs(void)
3735{
d3b2c338 3736 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK
3737}
3738
3739static void free_vmcs(struct vmcs *vmcs)
3740{
1c3d14fe 3741 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK
3742}
3743
d462b819
NHE
3744/*
3745 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3746 */
3747static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3748{
3749 if (!loaded_vmcs->vmcs)
3750 return;
3751 loaded_vmcs_clear(loaded_vmcs);
3752 free_vmcs(loaded_vmcs->vmcs);
3753 loaded_vmcs->vmcs = NULL;
355f4fb1 3754 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE
3755}
3756
39959588 3757static void free_kvm_area(void)
6aa8b732
AK
3758{
3759 int cpu;
3760
3230bb47 3761 for_each_possible_cpu(cpu) {
6aa8b732 3762 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA
3763 per_cpu(vmxarea, cpu) = NULL;
3764 }
6aa8b732
AK
3765}
3766
fe2b201b
BD
3767static void init_vmcs_shadow_fields(void)
3768{
3769 int i, j;
3770
3771 /* No checks for read only fields yet */
3772
3773 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3774 switch (shadow_read_write_fields[i]) {
3775 case GUEST_BNDCFGS:
a87036ad 3776 if (!kvm_mpx_supported())
fe2b201b
BD
3777 continue;
3778 break;
3779 default:
3780 break;
3781 }
3782
3783 if (j < i)
3784 shadow_read_write_fields[j] =
3785 shadow_read_write_fields[i];
3786 j++;
3787 }
3788 max_shadow_read_write_fields = j;
3789
3790 /* shadowed fields guest access without vmexit */
3791 for (i = 0; i < max_shadow_read_write_fields; i++) {
3792 clear_bit(shadow_read_write_fields[i],
3793 vmx_vmwrite_bitmap);
3794 clear_bit(shadow_read_write_fields[i],
3795 vmx_vmread_bitmap);
3796 }
3797 for (i = 0; i < max_shadow_read_only_fields; i++)
3798 clear_bit(shadow_read_only_fields[i],
3799 vmx_vmread_bitmap);
3800}
3801
6aa8b732
AK
3802static __init int alloc_kvm_area(void)
3803{
3804 int cpu;
3805
3230bb47 3806 for_each_possible_cpu(cpu) {
6aa8b732
AK
3807 struct vmcs *vmcs;
3808
3809 vmcs = alloc_vmcs_cpu(cpu);
3810 if (!vmcs) {
3811 free_kvm_area();
3812 return -ENOMEM;
3813 }
3814
3815 per_cpu(vmxarea, cpu) = vmcs;
3816 }
3817 return 0;
3818}
3819
14168786
GN
3820static bool emulation_required(struct kvm_vcpu *vcpu)
3821{
3822 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3823}
3824
91b0aa2c 3825static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3826 struct kvm_segment *save)
6aa8b732 3827{
d99e4152
GN
3828 if (!emulate_invalid_guest_state) {
3829 /*
3830 * CS and SS RPL should be equal during guest entry according
3831 * to VMX spec, but in reality it is not always so. Since vcpu
3832 * is in the middle of the transition from real mode to
3833 * protected mode it is safe to assume that RPL 0 is a good
3834 * default value.
3835 */
3836 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA
3837 save->selector &= ~SEGMENT_RPL_MASK;
3838 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3839 save->s = 1;
6aa8b732 3840 }
d99e4152 3841 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK
3842}
3843
3844static void enter_pmode(struct kvm_vcpu *vcpu)
3845{
3846 unsigned long flags;
a89a8fb9 3847 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3848
d99e4152
GN
3849 /*
3850 * Update real mode segment cache. It may be not up-to-date if sement
3851 * register was written while vcpu was in a guest mode.
3852 */
3853 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3854 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3855 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3856 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3857 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3858 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3859
7ffd92c5 3860 vmx->rmode.vm86_active = 0;
6aa8b732 3861
2fb92db1
AK
3862 vmx_segment_cache_clear(vmx);
3863
f5f7b2fe 3864 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK
3865
3866 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK
3867 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3868 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK
3869 vmcs_writel(GUEST_RFLAGS, flags);
3870
66aee91a
RR
3871 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3872 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK
3873
3874 update_exception_bitmap(vcpu);
3875
91b0aa2c
GN
3876 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3877 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3878 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3879 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3880 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3881 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK
3882}
3883
f5f7b2fe 3884static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3885{
772e0318 3886 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN
3887 struct kvm_segment var = *save;
3888
3889 var.dpl = 0x3;
3890 if (seg == VCPU_SREG_CS)
3891 var.type = 0x3;
3892
3893 if (!emulate_invalid_guest_state) {
3894 var.selector = var.base >> 4;
3895 var.base = var.base & 0xffff0;
3896 var.limit = 0xffff;
3897 var.g = 0;
3898 var.db = 0;
3899 var.present = 1;
3900 var.s = 1;
3901 var.l = 0;
3902 var.unusable = 0;
3903 var.type = 0x3;
3904 var.avl = 0;
3905 if (save->base & 0xf)
3906 printk_once(KERN_WARNING "kvm: segment base is not "
3907 "paragraph aligned when entering "
3908 "protected mode (seg=%d)", seg);
3909 }
6aa8b732 3910
d99e4152 3911 vmcs_write16(sf->selector, var.selector);
96794e4e 3912 vmcs_writel(sf->base, var.base);
d99e4152
GN
3913 vmcs_write32(sf->limit, var.limit);
3914 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK
3915}
3916
3917static void enter_rmode(struct kvm_vcpu *vcpu)
3918{
3919 unsigned long flags;
a89a8fb9 3920 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3921
f5f7b2fe
AK
3922 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3923 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3924 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3925 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3926 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN
3927 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3928 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3929
7ffd92c5 3930 vmx->rmode.vm86_active = 1;
6aa8b732 3931
776e58ea
GN
3932 /*
3933 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3934 * vcpu. Warn the user that an update is overdue.
776e58ea 3935 */
4918c6ca 3936 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN
3937 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3938 "called before entering vcpu\n");
776e58ea 3939
2fb92db1
AK
3940 vmx_segment_cache_clear(vmx);
3941
4918c6ca 3942 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3943 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK
3944 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3945
3946 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3947 vmx->rmode.save_rflags = flags;
6aa8b732 3948
053de044 3949 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK
3950
3951 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3952 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK
3953 update_exception_bitmap(vcpu);
3954
d99e4152
GN
3955 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3956 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3957 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3958 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3959 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3960 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3961
8668a3c4 3962 kvm_mmu_reset_context(vcpu);
6aa8b732
AK
3963}
3964
401d10de
AS
3965static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3966{
3967 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK
3968 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3969
3970 if (!msr)
3971 return;
401d10de 3972
44ea2b17
AK
3973 /*
3974 * Force kernel_gs_base reloading before EFER changes, as control
3975 * of this msr depends on is_long_mode().
3976 */
3977 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3978 vcpu->arch.efer = efer;
401d10de 3979 if (efer & EFER_LMA) {
2961e876 3980 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS
3981 msr->data = efer;
3982 } else {
2961e876 3983 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS
3984
3985 msr->data = efer & ~EFER_LME;
3986 }
3987 setup_msrs(vmx);
3988}
3989
05b3e0c2 3990#ifdef CONFIG_X86_64
6aa8b732
AK
3991
3992static void enter_lmode(struct kvm_vcpu *vcpu)
3993{
3994 u32 guest_tr_ar;
3995
2fb92db1
AK
3996 vmx_segment_cache_clear(to_vmx(vcpu));
3997
6aa8b732 3998 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 3999 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK
4000 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4001 __func__);
6aa8b732 4002 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL
4003 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4004 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 4005 }
da38f438 4006 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK
4007}
4008
4009static void exit_lmode(struct kvm_vcpu *vcpu)
4010{
2961e876 4011 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 4012 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK
4013}
4014
4015#endif
4016
dd5f5341 4017static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
2384d2b3 4018{
dd180b3e
XG
4019 if (enable_ept) {
4020 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4021 return;
995f00a6 4022 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
f0b98c02
JM
4023 } else {
4024 vpid_sync_context(vpid);
dd180b3e 4025 }
2384d2b3
SY
4026}
4027
dd5f5341
WL
4028static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4029{
4030 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4031}
4032
fb6c8198
JM
4033static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4034{
4035 if (enable_ept)
4036 vmx_flush_tlb(vcpu);
4037}
4038
e8467fda
AK
4039static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4040{
4041 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4042
4043 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4044 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4045}
4046
aff48baa
AK
4047static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4048{
4049 if (enable_ept && is_paging(vcpu))
4050 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4051 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4052}
4053
25c4c276 4054static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 4055{
fc78f519
AK
4056 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4057
4058 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4059 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK
4060}
4061
1439442c
SY
4062static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4063{
d0d538b9
GN
4064 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4065
6de4f3ad
AK
4066 if (!test_bit(VCPU_EXREG_PDPTR,
4067 (unsigned long *)&vcpu->arch.regs_dirty))
4068 return;
4069
1439442c 4070 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN
4071 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4072 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4073 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4074 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY
4075 }
4076}
4077
8f5d549f
AK
4078static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4079{
d0d538b9
GN
4080 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4081
8f5d549f 4082 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN
4083 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4084 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4085 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4086 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 4087 }
6de4f3ad
AK
4088
4089 __set_bit(VCPU_EXREG_PDPTR,
4090 (unsigned long *)&vcpu->arch.regs_avail);
4091 __set_bit(VCPU_EXREG_PDPTR,
4092 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK
4093}
4094
3899152c
DM
4095static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4096{
4097 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4098 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4099 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4100
4101 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4102 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4103 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4104 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4105
4106 return fixed_bits_valid(val, fixed0, fixed1);
4107}
4108
4109static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4110{
4111 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4112 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4113
4114 return fixed_bits_valid(val, fixed0, fixed1);
4115}
4116
4117static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4118{
4119 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4120 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4121
4122 return fixed_bits_valid(val, fixed0, fixed1);
4123}
4124
4125/* No difference in the restrictions on guest and host CR4 in VMX operation. */
4126#define nested_guest_cr4_valid nested_cr4_valid
4127#define nested_host_cr4_valid nested_cr4_valid
4128
5e1746d6 4129static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY
4130
4131static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4132 unsigned long cr0,
4133 struct kvm_vcpu *vcpu)
4134{
5233dd51
MT
4135 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4136 vmx_decache_cr3(vcpu);
1439442c
SY
4137 if (!(cr0 & X86_CR0_PG)) {
4138 /* From paging/starting to nonpaging */
4139 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 4140 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY
4141 (CPU_BASED_CR3_LOAD_EXITING |
4142 CPU_BASED_CR3_STORE_EXITING));
4143 vcpu->arch.cr0 = cr0;
fc78f519 4144 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY
4145 } else if (!is_paging(vcpu)) {
4146 /* From nonpaging to paging */
4147 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 4148 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY
4149 ~(CPU_BASED_CR3_LOAD_EXITING |
4150 CPU_BASED_CR3_STORE_EXITING));
4151 vcpu->arch.cr0 = cr0;
fc78f519 4152 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 4153 }
95eb84a7
SY
4154
4155 if (!(cr0 & X86_CR0_WP))
4156 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY
4157}
4158
6aa8b732
AK
4159static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4160{
7ffd92c5 4161 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK
4162 unsigned long hw_cr0;
4163
5037878e 4164 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 4165 if (enable_unrestricted_guest)
5037878e 4166 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 4167 else {
5037878e 4168 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 4169
218e763f
GN
4170 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4171 enter_pmode(vcpu);
6aa8b732 4172
218e763f
GN
4173 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4174 enter_rmode(vcpu);
4175 }
6aa8b732 4176
05b3e0c2 4177#ifdef CONFIG_X86_64
f6801dff 4178 if (vcpu->arch.efer & EFER_LME) {
707d92fa 4179 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 4180 enter_lmode(vcpu);
707d92fa 4181 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK
4182 exit_lmode(vcpu);
4183 }
4184#endif
4185
089d034e 4186 if (enable_ept)
1439442c
SY
4187 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4188
6aa8b732 4189 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 4190 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 4191 vcpu->arch.cr0 = cr0;
14168786
GN
4192
4193 /* depends on vcpu->arch.cr0 to be set to a new value */
4194 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK
4195}
4196
995f00a6 4197static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
1439442c
SY
4198{
4199 u64 eptp;
4200
4201 /* TODO write the value reading from MSR */
4202 eptp = VMX_EPT_DEFAULT_MT |
4203 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
995f00a6
PF
4204 if (enable_ept_ad_bits &&
4205 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
b38f9934 4206 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY
4207 eptp |= (root_hpa & PAGE_MASK);
4208
4209 return eptp;
4210}
4211
6aa8b732
AK
4212static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4213{
1439442c
SY
4214 unsigned long guest_cr3;
4215 u64 eptp;
4216
4217 guest_cr3 = cr3;
089d034e 4218 if (enable_ept) {
995f00a6 4219 eptp = construct_eptp(vcpu, cr3);
1439442c 4220 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK
4221 if (is_paging(vcpu) || is_guest_mode(vcpu))
4222 guest_cr3 = kvm_read_cr3(vcpu);
4223 else
4224 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 4225 ept_load_pdptrs(vcpu);
1439442c
SY
4226 }
4227
2384d2b3 4228 vmx_flush_tlb(vcpu);
1439442c 4229 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK
4230}
4231
5e1746d6 4232static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 4233{
085e68ee
BS
4234 /*
4235 * Pass through host's Machine Check Enable value to hw_cr4, which
4236 * is in force while we are in guest mode. Do not let guests control
4237 * this bit, even if host CR4.MCE == 0.
4238 */
4239 unsigned long hw_cr4 =
4240 (cr4_read_shadow() & X86_CR4_MCE) |
4241 (cr4 & ~X86_CR4_MCE) |
4242 (to_vmx(vcpu)->rmode.vm86_active ?
4243 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 4244
5e1746d6
NHE
4245 if (cr4 & X86_CR4_VMXE) {
4246 /*
4247 * To use VMXON (and later other VMX instructions), a guest
4248 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4249 * So basically the check on whether to allow nested VMX
4250 * is here.
4251 */
4252 if (!nested_vmx_allowed(vcpu))
4253 return 1;
1a0d74e6 4254 }
3899152c
DM
4255
4256 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE
4257 return 1;
4258
ad312c7c 4259 vcpu->arch.cr4 = cr4;
bc23008b
AK
4260 if (enable_ept) {
4261 if (!is_paging(vcpu)) {
4262 hw_cr4 &= ~X86_CR4_PAE;
4263 hw_cr4 |= X86_CR4_PSE;
4264 } else if (!(cr4 & X86_CR4_PAE)) {
4265 hw_cr4 &= ~X86_CR4_PAE;
4266 }
4267 }
1439442c 4268
656ec4a4
RK
4269 if (!enable_unrestricted_guest && !is_paging(vcpu))
4270 /*
ddba2628
HH
4271 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4272 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4273 * to be manually disabled when guest switches to non-paging
4274 * mode.
4275 *
4276 * If !enable_unrestricted_guest, the CPU is always running
4277 * with CR0.PG=1 and CR4 needs to be modified.
4278 * If enable_unrestricted_guest, the CPU automatically
4279 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 4280 */
ddba2628 4281 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
656ec4a4 4282
1439442c
SY
4283 vmcs_writel(CR4_READ_SHADOW, cr4);
4284 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 4285 return 0;
6aa8b732
AK
4286}
4287
6aa8b732
AK
4288static void vmx_get_segment(struct kvm_vcpu *vcpu,
4289 struct kvm_segment *var, int seg)
4290{
a9179499 4291 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK
4292 u32 ar;
4293
c6ad1153 4294 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 4295 *var = vmx->rmode.segs[seg];
a9179499 4296 if (seg == VCPU_SREG_TR
2fb92db1 4297 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 4298 return;
1390a28b
AK
4299 var->base = vmx_read_guest_seg_base(vmx, seg);
4300 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4301 return;
a9179499 4302 }
2fb92db1
AK
4303 var->base = vmx_read_guest_seg_base(vmx, seg);
4304 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4305 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4306 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 4307 var->unusable = (ar >> 16) & 1;
6aa8b732
AK
4308 var->type = ar & 15;
4309 var->s = (ar >> 4) & 1;
4310 var->dpl = (ar >> 5) & 3;
03617c18
GN
4311 /*
4312 * Some userspaces do not preserve unusable property. Since usable
4313 * segment has to be present according to VMX spec we can use present
4314 * property to amend userspace bug by making unusable segment always
4315 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4316 * segment as unusable.
4317 */
4318 var->present = !var->unusable;
6aa8b732
AK
4319 var->avl = (ar >> 12) & 1;
4320 var->l = (ar >> 13) & 1;
4321 var->db = (ar >> 14) & 1;
4322 var->g = (ar >> 15) & 1;
6aa8b732
AK
4323}
4324
a9179499
AK
4325static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4326{
a9179499
AK
4327 struct kvm_segment s;
4328
4329 if (to_vmx(vcpu)->rmode.vm86_active) {
4330 vmx_get_segment(vcpu, &s, seg);
4331 return s.base;
4332 }
2fb92db1 4333 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK
4334}
4335
b09408d0 4336static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 4337{
b09408d0
MT
4338 struct vcpu_vmx *vmx = to_vmx(vcpu);
4339
ae9fedc7 4340 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 4341 return 0;
ae9fedc7
PB
4342 else {
4343 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 4344 return VMX_AR_DPL(ar);
69c73028 4345 }
69c73028
AK
4346}
4347
653e3108 4348static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 4349{
6aa8b732
AK
4350 u32 ar;
4351
f0495f9b 4352 if (var->unusable || !var->present)
6aa8b732
AK
4353 ar = 1 << 16;
4354 else {
4355 ar = var->type & 15;
4356 ar |= (var->s & 1) << 4;
4357 ar |= (var->dpl & 3) << 5;
4358 ar |= (var->present & 1) << 7;
4359 ar |= (var->avl & 1) << 12;
4360 ar |= (var->l & 1) << 13;
4361 ar |= (var->db & 1) << 14;
4362 ar |= (var->g & 1) << 15;
4363 }
653e3108
AK
4364
4365 return ar;
4366}
4367
4368static void vmx_set_segment(struct kvm_vcpu *vcpu,
4369 struct kvm_segment *var, int seg)
4370{
7ffd92c5 4371 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 4372 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 4373
2fb92db1
AK
4374 vmx_segment_cache_clear(vmx);
4375
1ecd50a9
GN
4376 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4377 vmx->rmode.segs[seg] = *var;
4378 if (seg == VCPU_SREG_TR)
4379 vmcs_write16(sf->selector, var->selector);
4380 else if (var->s)
4381 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 4382 goto out;
653e3108 4383 }
1ecd50a9 4384
653e3108
AK
4385 vmcs_writel(sf->base, var->base);
4386 vmcs_write32(sf->limit, var->limit);
4387 vmcs_write16(sf->selector, var->selector);
3a624e29
NK
4388
4389 /*
4390 * Fix the "Accessed" bit in AR field of segment registers for older
4391 * qemu binaries.
4392 * IA32 arch specifies that at the time of processor reset the
4393 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 4394 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK
4395 * state vmexit when "unrestricted guest" mode is turned on.
4396 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4397 * tree. Newer qemu binaries with that qemu fix would not need this
4398 * kvm hack.
4399 */
4400 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 4401 var->type |= 0x1; /* Accessed */
3a624e29 4402
f924d66d 4403 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN
4404
4405out:
98eb2f8b 4406 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK
4407}
4408
6aa8b732
AK
4409static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4410{
2fb92db1 4411 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK
4412
4413 *db = (ar >> 14) & 1;
4414 *l = (ar >> 13) & 1;
4415}
4416
89a27f4d 4417static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4418{
89a27f4d
GN
4419 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4420 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK
4421}
4422
89a27f4d 4423static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4424{
89a27f4d
GN
4425 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4426 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK
4427}
4428
89a27f4d 4429static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4430{
89a27f4d
GN
4431 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4432 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK
4433}
4434
89a27f4d 4435static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4436{
89a27f4d
GN
4437 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4438 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK
4439}
4440
648dfaa7
MG
4441static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4442{
4443 struct kvm_segment var;
4444 u32 ar;
4445
4446 vmx_get_segment(vcpu, &var, seg);
07f42f5f 4447 var.dpl = 0x3;
0647f4aa
GN
4448 if (seg == VCPU_SREG_CS)
4449 var.type = 0x3;
648dfaa7
MG
4450 ar = vmx_segment_access_rights(&var);
4451
4452 if (var.base != (var.selector << 4))
4453 return false;
89efbed0 4454 if (var.limit != 0xffff)
648dfaa7 4455 return false;
07f42f5f 4456 if (ar != 0xf3)
648dfaa7
MG
4457 return false;
4458
4459 return true;
4460}
4461
4462static bool code_segment_valid(struct kvm_vcpu *vcpu)
4463{
4464 struct kvm_segment cs;
4465 unsigned int cs_rpl;
4466
4467 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 4468 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 4469
1872a3f4
AK
4470 if (cs.unusable)
4471 return false;
4d283ec9 4472 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG
4473 return false;
4474 if (!cs.s)
4475 return false;
4d283ec9 4476 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG
4477 if (cs.dpl > cs_rpl)
4478 return false;
1872a3f4 4479 } else {
648dfaa7
MG
4480 if (cs.dpl != cs_rpl)
4481 return false;
4482 }
4483 if (!cs.present)
4484 return false;
4485
4486 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4487 return true;
4488}
4489
4490static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4491{
4492 struct kvm_segment ss;
4493 unsigned int ss_rpl;
4494
4495 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 4496 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 4497
1872a3f4
AK
4498 if (ss.unusable)
4499 return true;
4500 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG
4501 return false;
4502 if (!ss.s)
4503 return false;
4504 if (ss.dpl != ss_rpl) /* DPL != RPL */
4505 return false;
4506 if (!ss.present)
4507 return false;
4508
4509 return true;
4510}
4511
4512static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4513{
4514 struct kvm_segment var;
4515 unsigned int rpl;
4516
4517 vmx_get_segment(vcpu, &var, seg);
b32a9918 4518 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 4519
1872a3f4
AK
4520 if (var.unusable)
4521 return true;
648dfaa7
MG
4522 if (!var.s)
4523 return false;
4524 if (!var.present)
4525 return false;
4d283ec9 4526 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG
4527 if (var.dpl < rpl) /* DPL < RPL */
4528 return false;
4529 }
4530
4531 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4532 * rights flags
4533 */
4534 return true;
4535}
4536
4537static bool tr_valid(struct kvm_vcpu *vcpu)
4538{
4539 struct kvm_segment tr;
4540
4541 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4542
1872a3f4
AK
4543 if (tr.unusable)
4544 return false;
b32a9918 4545 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 4546 return false;
1872a3f4 4547 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG
4548 return false;
4549 if (!tr.present)
4550 return false;
4551
4552 return true;
4553}
4554
4555static bool ldtr_valid(struct kvm_vcpu *vcpu)
4556{
4557 struct kvm_segment ldtr;
4558
4559 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4560
1872a3f4
AK
4561 if (ldtr.unusable)
4562 return true;
b32a9918 4563 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG
4564 return false;
4565 if (ldtr.type != 2)
4566 return false;
4567 if (!ldtr.present)
4568 return false;
4569
4570 return true;
4571}
4572
4573static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4574{
4575 struct kvm_segment cs, ss;
4576
4577 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4578 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4579
b32a9918
NA
4580 return ((cs.selector & SEGMENT_RPL_MASK) ==
4581 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG
4582}
4583
4584/*
4585 * Check if guest state is valid. Returns true if valid, false if
4586 * not.
4587 * We assume that registers are always usable
4588 */
4589static bool guest_state_valid(struct kvm_vcpu *vcpu)
4590{
c5e97c80
GN
4591 if (enable_unrestricted_guest)
4592 return true;
4593
648dfaa7 4594 /* real mode guest state checks */
f13882d8 4595 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG
4596 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4597 return false;
4598 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4599 return false;
4600 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4601 return false;
4602 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4603 return false;
4604 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4605 return false;
4606 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4607 return false;
4608 } else {
4609 /* protected mode guest state checks */
4610 if (!cs_ss_rpl_check(vcpu))
4611 return false;
4612 if (!code_segment_valid(vcpu))
4613 return false;
4614 if (!stack_segment_valid(vcpu))
4615 return false;
4616 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4617 return false;
4618 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4619 return false;
4620 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4621 return false;
4622 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4623 return false;
4624 if (!tr_valid(vcpu))
4625 return false;
4626 if (!ldtr_valid(vcpu))
4627 return false;
4628 }
4629 /* TODO:
4630 * - Add checks on RIP
4631 * - Add checks on RFLAGS
4632 */
4633
4634 return true;
4635}
4636
5fa99cbe
JM
4637static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4638{
4639 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4640}
4641
d77c26fc 4642static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4643{
40dcaa9f 4644 gfn_t fn;
195aefde 4645 u16 data = 0;
1f755a82 4646 int idx, r;
6aa8b732 4647
40dcaa9f 4648 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4649 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE
4650 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4651 if (r < 0)
10589a46 4652 goto out;
195aefde 4653 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY
4654 r = kvm_write_guest_page(kvm, fn++, &data,
4655 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4656 if (r < 0)
10589a46 4657 goto out;
195aefde
IE
4658 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4659 if (r < 0)
10589a46 4660 goto out;
195aefde
IE
4661 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4662 if (r < 0)
10589a46 4663 goto out;
195aefde 4664 data = ~0;
10589a46
MT
4665 r = kvm_write_guest_page(kvm, fn, &data,
4666 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4667 sizeof(u8));
10589a46 4668out:
40dcaa9f 4669 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4670 return r;
6aa8b732
AK
4671}
4672
b7ebfb05
SY
4673static int init_rmode_identity_map(struct kvm *kvm)
4674{
f51770ed 4675 int i, idx, r = 0;
ba049e93 4676 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY
4677 u32 tmp;
4678
089d034e 4679 if (!enable_ept)
f51770ed 4680 return 0;
a255d479
TC
4681
4682 /* Protect kvm->arch.ept_identity_pagetable_done. */
4683 mutex_lock(&kvm->slots_lock);
4684
f51770ed 4685 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4686 goto out2;
a255d479 4687
b927a3ce 4688 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC
4689
4690 r = alloc_identity_pagetable(kvm);
f51770ed 4691 if (r < 0)
a255d479
TC
4692 goto out2;
4693
40dcaa9f 4694 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY
4695 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4696 if (r < 0)
4697 goto out;
4698 /* Set up identity-mapping pagetable for EPT in real mode */
4699 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4700 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4701 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4702 r = kvm_write_guest_page(kvm, identity_map_pfn,
4703 &tmp, i * sizeof(tmp), sizeof(tmp));
4704 if (r < 0)
4705 goto out;
4706 }
4707 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4708
b7ebfb05 4709out:
40dcaa9f 4710 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC
4711
4712out2:
4713 mutex_unlock(&kvm->slots_lock);
f51770ed 4714 return r;
b7ebfb05
SY
4715}
4716
6aa8b732
AK
4717static void seg_setup(int seg)
4718{
772e0318 4719 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4720 unsigned int ar;
6aa8b732
AK
4721
4722 vmcs_write16(sf->selector, 0);
4723 vmcs_writel(sf->base, 0);
4724 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN
4725 ar = 0x93;
4726 if (seg == VCPU_SREG_CS)
4727 ar |= 0x08; /* code segment */
3a624e29
NK
4728
4729 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK
4730}
4731
f78e0e2e
SY
4732static int alloc_apic_access_page(struct kvm *kvm)
4733{
4484141a 4734 struct page *page;
f78e0e2e
SY
4735 int r = 0;
4736
79fac95e 4737 mutex_lock(&kvm->slots_lock);
c24ae0dc 4738 if (kvm->arch.apic_access_page_done)
f78e0e2e 4739 goto out;
1d8007bd
PB
4740 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4741 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY
4742 if (r)
4743 goto out;
72dc67a6 4744
73a6d941 4745 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG
4746 if (is_error_page(page)) {
4747 r = -EFAULT;
4748 goto out;
4749 }
4750
c24ae0dc
TC
4751 /*
4752 * Do not pin the page in memory, so that memory hot-unplug
4753 * is able to migrate it.
4754 */
4755 put_page(page);
4756 kvm->arch.apic_access_page_done = true;
f78e0e2e 4757out:
79fac95e 4758 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY
4759 return r;
4760}
4761
b7ebfb05
SY
4762static int alloc_identity_pagetable(struct kvm *kvm)
4763{
a255d479
TC
4764 /* Called with kvm->slots_lock held. */
4765
b7ebfb05
SY
4766 int r = 0;
4767
a255d479
TC
4768 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4769
1d8007bd
PB
4770 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4771 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
b7ebfb05 4772
b7ebfb05
SY
4773 return r;
4774}
4775
991e7a0e 4776static int allocate_vpid(void)
2384d2b3
SY
4777{
4778 int vpid;
4779
919818ab 4780 if (!enable_vpid)
991e7a0e 4781 return 0;
2384d2b3
SY
4782 spin_lock(&vmx_vpid_lock);
4783 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 4784 if (vpid < VMX_NR_VPIDS)
2384d2b3 4785 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL
4786 else
4787 vpid = 0;
2384d2b3 4788 spin_unlock(&vmx_vpid_lock);
991e7a0e 4789 return vpid;
2384d2b3
SY
4790}
4791
991e7a0e 4792static void free_vpid(int vpid)
cdbecfc3 4793{
991e7a0e 4794 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ
4795 return;
4796 spin_lock(&vmx_vpid_lock);
991e7a0e 4797 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ
4798 spin_unlock(&vmx_vpid_lock);
4799}
4800
8d14695f
YZ
4801#define MSR_TYPE_R 1
4802#define MSR_TYPE_W 2
4803static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4804 u32 msr, int type)
25c5f225 4805{
3e7c73e9 4806 int f = sizeof(unsigned long);
25c5f225
SY
4807
4808 if (!cpu_has_vmx_msr_bitmap())
4809 return;
4810
4811 /*
4812 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4813 * have the write-low and read-high bitmap offsets the wrong way round.
4814 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4815 */
25c5f225 4816 if (msr <= 0x1fff) {
8d14695f
YZ
4817 if (type & MSR_TYPE_R)
4818 /* read-low */
4819 __clear_bit(msr, msr_bitmap + 0x000 / f);
4820
4821 if (type & MSR_TYPE_W)
4822 /* write-low */
4823 __clear_bit(msr, msr_bitmap + 0x800 / f);
4824
25c5f225
SY
4825 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4826 msr &= 0x1fff;
8d14695f
YZ
4827 if (type & MSR_TYPE_R)
4828 /* read-high */
4829 __clear_bit(msr, msr_bitmap + 0x400 / f);
4830
4831 if (type & MSR_TYPE_W)
4832 /* write-high */
4833 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4834
4835 }
4836}
4837
f2b93280
WV
4838/*
4839 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4840 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4841 */
4842static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4843 unsigned long *msr_bitmap_nested,
4844 u32 msr, int type)
4845{
4846 int f = sizeof(unsigned long);
4847
4848 if (!cpu_has_vmx_msr_bitmap()) {
4849 WARN_ON(1);
4850 return;
4851 }
4852
4853 /*
4854 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4855 * have the write-low and read-high bitmap offsets the wrong way round.
4856 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4857 */
4858 if (msr <= 0x1fff) {
4859 if (type & MSR_TYPE_R &&
4860 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4861 /* read-low */
4862 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4863
4864 if (type & MSR_TYPE_W &&
4865 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4866 /* write-low */
4867 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4868
4869 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4870 msr &= 0x1fff;
4871 if (type & MSR_TYPE_R &&
4872 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4873 /* read-high */
4874 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4875
4876 if (type & MSR_TYPE_W &&
4877 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4878 /* write-high */
4879 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4880
4881 }
4882}
4883
5897297b
AK
4884static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4885{
4886 if (!longmode_only)
8d14695f
YZ
4887 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4888 msr, MSR_TYPE_R | MSR_TYPE_W);
4889 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4890 msr, MSR_TYPE_R | MSR_TYPE_W);
4891}
4892
2e69f865 4893static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
8d14695f 4894{
f6e90f9e 4895 if (apicv_active) {
c63e4563 4896 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
2e69f865 4897 msr, type);
c63e4563 4898 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
2e69f865 4899 msr, type);
f6e90f9e 4900 } else {
f6e90f9e 4901 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
2e69f865 4902 msr, type);
f6e90f9e 4903 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
2e69f865 4904 msr, type);
f6e90f9e 4905 }
5897297b
AK
4906}
4907
d62caabb 4908static bool vmx_get_enable_apicv(void)
d50ab6c1 4909{
d62caabb 4910 return enable_apicv;
d50ab6c1
PB
4911}
4912
6342c50a 4913static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
705699a1
WV
4914{
4915 struct vcpu_vmx *vmx = to_vmx(vcpu);
4916 int max_irr;
4917 void *vapic_page;
4918 u16 status;
4919
4920 if (vmx->nested.pi_desc &&
4921 vmx->nested.pi_pending) {
4922 vmx->nested.pi_pending = false;
4923 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
6342c50a 4924 return;
705699a1
WV
4925
4926 max_irr = find_last_bit(
4927 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4928
4929 if (max_irr == 256)
6342c50a 4930 return;
705699a1
WV
4931
4932 vapic_page = kmap(vmx->nested.virtual_apic_page);
705699a1
WV
4933 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4934 kunmap(vmx->nested.virtual_apic_page);
4935
4936 status = vmcs_read16(GUEST_INTR_STATUS);
4937 if ((u8)max_irr > ((u8)status & 0xff)) {
4938 status &= ~0xff;
4939 status |= (u8)max_irr;
4940 vmcs_write16(GUEST_INTR_STATUS, status);
4941 }
4942 }
705699a1
WV
4943}
4944
21bc8dc5
RK
4945static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4946{
4947#ifdef CONFIG_SMP
4948 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6
FW
4949 struct vcpu_vmx *vmx = to_vmx(vcpu);
4950
4951 /*
4952 * Currently, we don't support urgent interrupt,
4953 * all interrupts are recognized as non-urgent
4954 * interrupt, so we cannot post interrupts when
4955 * 'SN' is set.
4956 *
4957 * If the vcpu is in guest mode, it means it is
4958 * running instead of being scheduled out and
4959 * waiting in the run queue, and that's the only
4960 * case when 'SN' is set currently, warning if
4961 * 'SN' is set.
4962 */
4963 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4964
21bc8dc5
RK
4965 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4966 POSTED_INTR_VECTOR);
4967 return true;
4968 }
4969#endif
4970 return false;
4971}
4972
705699a1
WV
4973static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4974 int vector)
4975{
4976 struct vcpu_vmx *vmx = to_vmx(vcpu);
4977
4978 if (is_guest_mode(vcpu) &&
4979 vector == vmx->nested.posted_intr_nv) {
4980 /* the PIR and ON have been set by L1. */
21bc8dc5 4981 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV
4982 /*
4983 * If a posted intr is not recognized by hardware,
4984 * we will accomplish it in the next vmentry.
4985 */
4986 vmx->nested.pi_pending = true;
4987 kvm_make_request(KVM_REQ_EVENT, vcpu);
4988 return 0;
4989 }
4990 return -1;
4991}
a20ed54d
YZ
4992/*
4993 * Send interrupt to vcpu via posted interrupt way.
4994 * 1. If target vcpu is running(non-root mode), send posted interrupt
4995 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4996 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4997 * interrupt from PIR in next vmentry.
4998 */
4999static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5000{
5001 struct vcpu_vmx *vmx = to_vmx(vcpu);
5002 int r;
5003
705699a1
WV
5004 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5005 if (!r)
5006 return;
5007
a20ed54d
YZ
5008 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5009 return;
5010
b95234c8
PB
5011 /* If a previous notification has sent the IPI, nothing to do. */
5012 if (pi_test_and_set_on(&vmx->pi_desc))
5013 return;
5014
5015 if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ
5016 kvm_vcpu_kick(vcpu);
5017}
5018
a3a8ff8e
NHE
5019/*
5020 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5021 * will not change in the lifetime of the guest.
5022 * Note that host-state that does change is set elsewhere. E.g., host-state
5023 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5024 */
a547c6db 5025static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE
5026{
5027 u32 low32, high32;
5028 unsigned long tmpl;
5029 struct desc_ptr dt;
d6e41f11 5030 unsigned long cr0, cr3, cr4;
a3a8ff8e 5031
04ac88ab
AL
5032 cr0 = read_cr0();
5033 WARN_ON(cr0 & X86_CR0_TS);
5034 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL
5035
5036 /*
5037 * Save the most likely value for this task's CR3 in the VMCS.
5038 * We can't use __get_current_cr3_fast() because we're not atomic.
5039 */
6c690ee1 5040 cr3 = __read_cr3();
d6e41f11
AL
5041 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5042 vmx->host_state.vmcs_host_cr3 = cr3;
a3a8ff8e 5043
d974baa3 5044 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 5045 cr4 = cr4_read_shadow();
d974baa3
AL
5046 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5047 vmx->host_state.vmcs_host_cr4 = cr4;
5048
a3a8ff8e 5049 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK
5050#ifdef CONFIG_X86_64
5051 /*
5052 * Load null selectors, so we can avoid reloading them in
5053 * __vmx_load_host_state(), in case userspace uses the null selectors
5054 * too (the expected case).
5055 */
5056 vmcs_write16(HOST_DS_SELECTOR, 0);
5057 vmcs_write16(HOST_ES_SELECTOR, 0);
5058#else
a3a8ff8e
NHE
5059 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5060 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 5061#endif
a3a8ff8e
NHE
5062 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5063 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5064
5065 native_store_idt(&dt);
5066 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 5067 vmx->host_idt_base = dt.address;
a3a8ff8e 5068
83287ea4 5069 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE
5070
5071 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5072 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5073 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5074 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5075
5076 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5077 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5078 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5079 }
5080}
5081
bf8179a0
NHE
5082static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5083{
5084 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5085 if (enable_ept)
5086 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE
5087 if (is_guest_mode(&vmx->vcpu))
5088 vmx->vcpu.arch.cr4_guest_owned_bits &=
5089 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE
5090 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5091}
5092
01e439be
YZ
5093static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5094{
5095 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5096
d62caabb 5097 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 5098 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
64672c95
YJ
5099 /* Enable the preemption timer dynamically */
5100 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ
5101 return pin_based_exec_ctrl;
5102}
5103
d62caabb
AS
5104static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5105{
5106 struct vcpu_vmx *vmx = to_vmx(vcpu);
5107
5108 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK
5109 if (cpu_has_secondary_exec_ctrls()) {
5110 if (kvm_vcpu_apicv_active(vcpu))
5111 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5112 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5113 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5114 else
5115 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5116 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5117 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5118 }
5119
5120 if (cpu_has_vmx_msr_bitmap())
5121 vmx_set_msr_bitmap(vcpu);
d62caabb
AS
5122}
5123
bf8179a0
NHE
5124static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5125{
5126 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB
5127
5128 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5129 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5130
35754c98 5131 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE
5132 exec_control &= ~CPU_BASED_TPR_SHADOW;
5133#ifdef CONFIG_X86_64
5134 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5135 CPU_BASED_CR8_LOAD_EXITING;
5136#endif
5137 }
5138 if (!enable_ept)
5139 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5140 CPU_BASED_CR3_LOAD_EXITING |
5141 CPU_BASED_INVLPG_EXITING;
5142 return exec_control;
5143}
5144
5145static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5146{
5147 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 5148 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE
5149 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5150 if (vmx->vpid == 0)
5151 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5152 if (!enable_ept) {
5153 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5154 enable_unrestricted_guest = 0;
ad756a16
MJ
5155 /* Enable INVPCID for non-ept guests may cause performance regression. */
5156 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE
5157 }
5158 if (!enable_unrestricted_guest)
5159 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5160 if (!ple_gap)
5161 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
d62caabb 5162 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
c7c9c56c
YZ
5163 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5164 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 5165 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG
5166 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5167 (handle_vmptrld).
5168 We can NOT enable shadow_vmcs here because we don't have yet
5169 a current VMCS12
5170 */
5171 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH
5172
5173 if (!enable_pml)
5174 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 5175
bf8179a0
NHE
5176 return exec_control;
5177}
5178
ce88decf
XG
5179static void ept_set_mmio_spte_mask(void)
5180{
5181 /*
5182 * EPT Misconfigurations can be generated if the value of bits 2:0
5183 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 5184 */
dcdca5fe
PF
5185 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5186 VMX_EPT_MISCONFIG_WX_VALUE);
ce88decf
XG
5187}
5188
f53cd63c 5189#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK
5190/*
5191 * Sets up the vmcs for emulated real mode.
5192 */
8b9cf98c 5193static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 5194{
2e4ce7f5 5195#ifdef CONFIG_X86_64
6aa8b732 5196 unsigned long a;
2e4ce7f5 5197#endif
6aa8b732 5198 int i;
6aa8b732 5199
6aa8b732 5200 /* I/O */
3e7c73e9
AK
5201 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5202 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 5203
4607c2d7
AG
5204 if (enable_shadow_vmcs) {
5205 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5206 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5207 }
25c5f225 5208 if (cpu_has_vmx_msr_bitmap())
5897297b 5209 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 5210
6aa8b732
AK
5211 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5212
6aa8b732 5213 /* Control */
01e439be 5214 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
64672c95 5215 vmx->hv_deadline_tsc = -1;
6e5d865c 5216
bf8179a0 5217 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 5218
dfa169bb 5219 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE
5220 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5221 vmx_secondary_exec_control(vmx));
dfa169bb 5222 }
f78e0e2e 5223
d62caabb 5224 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ
5225 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5226 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5227 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5228 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5229
5230 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 5231
0bcf261c 5232 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 5233 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ
5234 }
5235
4b8d54f9
ZE
5236 if (ple_gap) {
5237 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK
5238 vmx->ple_window = ple_window;
5239 vmx->ple_window_dirty = true;
4b8d54f9
ZE
5240 }
5241
c3707958
XG
5242 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5243 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK
5244 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5245
9581d442
AK
5246 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5247 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 5248 vmx_set_constant_host_state(vmx);
05b3e0c2 5249#ifdef CONFIG_X86_64
6aa8b732
AK
5250 rdmsrl(MSR_FS_BASE, a);
5251 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5252 rdmsrl(MSR_GS_BASE, a);
5253 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5254#else
5255 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5256 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5257#endif
5258
2cc51560
ED
5259 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5260 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 5261 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 5262 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 5263 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 5264
74545705
RK
5265 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5266 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 5267
03916db9 5268 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK
5269 u32 index = vmx_msr_index[i];
5270 u32 data_low, data_high;
a2fa3e9f 5271 int j = vmx->nmsrs;
6aa8b732
AK
5272
5273 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5274 continue;
432bd6cb
AK
5275 if (wrmsr_safe(index, data_low, data_high) < 0)
5276 continue;
26bb0981
AK
5277 vmx->guest_msrs[j].index = i;
5278 vmx->guest_msrs[j].data = 0;
d5696725 5279 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 5280 ++vmx->nmsrs;
6aa8b732 5281 }
6aa8b732 5282
2961e876
GN
5283
5284 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK
5285
5286 /* 22.2.1, 20.8.1 */
2961e876 5287 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 5288
bd7e5b08
PB
5289 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5290 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5291
bf8179a0 5292 set_cr4_guest_host_mask(vmx);
e00c8cf2 5293
f53cd63c
WL
5294 if (vmx_xsaves_supported())
5295 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5296
4e59516a
PF
5297 if (enable_pml) {
5298 ASSERT(vmx->pml_pg);
5299 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5300 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5301 }
5302
e00c8cf2
AK
5303 return 0;
5304}
5305
d28bc9dd 5306static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK
5307{
5308 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 5309 struct msr_data apic_base_msr;
d28bc9dd 5310 u64 cr0;
e00c8cf2 5311
7ffd92c5 5312 vmx->rmode.vm86_active = 0;
e00c8cf2 5313
ad312c7c 5314 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA
5315 kvm_set_cr8(vcpu, 0);
5316
5317 if (!init_event) {
5318 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5319 MSR_IA32_APICBASE_ENABLE;
5320 if (kvm_vcpu_is_reset_bsp(vcpu))
5321 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5322 apic_base_msr.host_initiated = true;
5323 kvm_set_apic_base(vcpu, &apic_base_msr);
5324 }
e00c8cf2 5325
2fb92db1
AK
5326 vmx_segment_cache_clear(vmx);
5327
5706be0d 5328 seg_setup(VCPU_SREG_CS);
66450a21 5329 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 5330 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK
5331
5332 seg_setup(VCPU_SREG_DS);
5333 seg_setup(VCPU_SREG_ES);
5334 seg_setup(VCPU_SREG_FS);
5335 seg_setup(VCPU_SREG_GS);
5336 seg_setup(VCPU_SREG_SS);
5337
5338 vmcs_write16(GUEST_TR_SELECTOR, 0);
5339 vmcs_writel(GUEST_TR_BASE, 0);
5340 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5341 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5342
5343 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5344 vmcs_writel(GUEST_LDTR_BASE, 0);
5345 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5346 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5347
d28bc9dd
NA
5348 if (!init_event) {
5349 vmcs_write32(GUEST_SYSENTER_CS, 0);
5350 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5351 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5352 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5353 }
e00c8cf2
AK
5354
5355 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 5356 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 5357
e00c8cf2
AK
5358 vmcs_writel(GUEST_GDTR_BASE, 0);
5359 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5360
5361 vmcs_writel(GUEST_IDTR_BASE, 0);
5362 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5363
443381a8 5364 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 5365 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 5366 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
e00c8cf2 5367
e00c8cf2
AK
5368 setup_msrs(vmx);
5369
6aa8b732
AK
5370 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5371
d28bc9dd 5372 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 5373 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 5374 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 5375 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 5376 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY
5377 vmcs_write32(TPR_THRESHOLD, 0);
5378 }
5379
a73896cb 5380 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 5381
d62caabb 5382 if (kvm_vcpu_apicv_active(vcpu))
01e439be
YZ
5383 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5384
2384d2b3
SY
5385 if (vmx->vpid != 0)
5386 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5387
d28bc9dd 5388 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 5389 vmx->vcpu.arch.cr0 = cr0;
f2463247 5390 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 5391 vmx_set_cr4(vcpu, 0);
5690891b 5392 vmx_set_efer(vcpu, 0);
bd7e5b08 5393
d28bc9dd 5394 update_exception_bitmap(vcpu);
6aa8b732 5395
dd5f5341 5396 vpid_sync_context(vmx->vpid);
6aa8b732
AK
5397}
5398
b6f1250e
NHE
5399/*
5400 * In nested virtualization, check if L1 asked to exit on external interrupts.
5401 * For most existing hypervisors, this will always return true.
5402 */
5403static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5404{
5405 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5406 PIN_BASED_EXT_INTR_MASK;
5407}
5408
77b0f5d6
BD
5409/*
5410 * In nested virtualization, check if L1 has set
5411 * VM_EXIT_ACK_INTR_ON_EXIT
5412 */
5413static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5414{
5415 return get_vmcs12(vcpu)->vm_exit_controls &
5416 VM_EXIT_ACK_INTR_ON_EXIT;
5417}
5418
ea8ceb83
JK
5419static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5420{
5421 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5422 PIN_BASED_NMI_EXITING;
5423}
5424
c9a7953f 5425static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 5426{
47c0152e
PB
5427 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5428 CPU_BASED_VIRTUAL_INTR_PENDING);
3b86cd99
JK
5429}
5430
c9a7953f 5431static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 5432{
2c82878b 5433 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK
5434 enable_irq_window(vcpu);
5435 return;
5436 }
3b86cd99 5437
47c0152e
PB
5438 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5439 CPU_BASED_VIRTUAL_NMI_PENDING);
3b86cd99
JK
5440}
5441
66fd3f7f 5442static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 5443{
9c8cba37 5444 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN
5445 uint32_t intr;
5446 int irq = vcpu->arch.interrupt.nr;
9c8cba37 5447
229456fc 5448 trace_kvm_inj_virq(irq);
2714d1d3 5449
fa89a817 5450 ++vcpu->stat.irq_injections;
7ffd92c5 5451 if (vmx->rmode.vm86_active) {
71f9833b
SH
5452 int inc_eip = 0;
5453 if (vcpu->arch.interrupt.soft)
5454 inc_eip = vcpu->arch.event_exit_inst_len;
5455 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 5456 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED
5457 return;
5458 }
66fd3f7f
GN
5459 intr = irq | INTR_INFO_VALID_MASK;
5460 if (vcpu->arch.interrupt.soft) {
5461 intr |= INTR_TYPE_SOFT_INTR;
5462 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5463 vmx->vcpu.arch.event_exit_inst_len);
5464 } else
5465 intr |= INTR_TYPE_EXT_INTR;
5466 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED
5467}
5468
f08864b4
SY
5469static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5470{
66a5a347
JK
5471 struct vcpu_vmx *vmx = to_vmx(vcpu);
5472
c5a6d5f7 5473 if (!is_guest_mode(vcpu)) {
c5a6d5f7
WL
5474 ++vcpu->stat.nmi_injections;
5475 vmx->nmi_known_unmasked = false;
3b86cd99
JK
5476 }
5477
7ffd92c5 5478 if (vmx->rmode.vm86_active) {
71f9833b 5479 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 5480 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK
5481 return;
5482 }
c5a6d5f7 5483
f08864b4
SY
5484 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5485 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY
5486}
5487
3cfc3092
JK
5488static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5489{
9d58b931
AK
5490 if (to_vmx(vcpu)->nmi_known_unmasked)
5491 return false;
c332c83a 5492 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK
5493}
5494
5495static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5496{
5497 struct vcpu_vmx *vmx = to_vmx(vcpu);
5498
2c82878b
PB
5499 vmx->nmi_known_unmasked = !masked;
5500 if (masked)
5501 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5502 GUEST_INTR_STATE_NMI);
5503 else
5504 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5505 GUEST_INTR_STATE_NMI);
3cfc3092
JK
5506}
5507
2505dc9f
JK
5508static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5509{
b6b8a145
JK
5510 if (to_vmx(vcpu)->nested.nested_run_pending)
5511 return 0;
ea8ceb83 5512
2505dc9f
JK
5513 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5514 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5515 | GUEST_INTR_STATE_NMI));
5516}
5517
78646121
GN
5518static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5519{
b6b8a145
JK
5520 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5521 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN
5522 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5523 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN
5524}
5525
cbc94022
IE
5526static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5527{
5528 int ret;
cbc94022 5529
1d8007bd
PB
5530 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5531 PAGE_SIZE * 3);
cbc94022
IE
5532 if (ret)
5533 return ret;
bfc6d222 5534 kvm->arch.tss_addr = addr;
1f755a82 5535 return init_rmode_tss(kvm);
cbc94022
IE
5536}
5537
0ca1b4f4 5538static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 5539{
77ab6db0 5540 switch (vec) {
77ab6db0 5541 case BP_VECTOR:
c573cd22
JK
5542 /*
5543 * Update instruction length as we may reinject the exception
5544 * from user space while in guest debugging mode.
5545 */
5546 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5547 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 5548 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN
5549 return false;
5550 /* fall through */
5551 case DB_VECTOR:
5552 if (vcpu->guest_debug &
5553 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5554 return false;
d0bfb940
JK
5555 /* fall through */
5556 case DE_VECTOR:
77ab6db0
JK
5557 case OF_VECTOR:
5558 case BR_VECTOR:
5559 case UD_VECTOR:
5560 case DF_VECTOR:
5561 case SS_VECTOR:
5562 case GP_VECTOR:
5563 case MF_VECTOR:
0ca1b4f4
GN
5564 return true;
5565 break;
77ab6db0 5566 }
0ca1b4f4
GN
5567 return false;
5568}
5569
5570static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5571 int vec, u32 err_code)
5572{
5573 /*
5574 * Instruction with address size override prefix opcode 0x67
5575 * Cause the #SS fault with 0 error code in VM86 mode.
5576 */
5577 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5578 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5579 if (vcpu->arch.halt_request) {
5580 vcpu->arch.halt_request = 0;
5cb56059 5581 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN
5582 }
5583 return 1;
5584 }
5585 return 0;
5586 }
5587
5588 /*
5589 * Forward all other exceptions that are valid in real mode.
5590 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5591 * the required debugging infrastructure rework.
5592 */
5593 kvm_queue_exception(vcpu, vec);
5594 return 1;
6aa8b732
AK
5595}
5596
a0861c02
AK
5597/*
5598 * Trigger machine check on the host. We assume all the MSRs are already set up
5599 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5600 * We pass a fake environment to the machine check handler because we want
5601 * the guest to be always treated like user space, no matter what context
5602 * it used internally.
5603 */
5604static void kvm_machine_check(void)
5605{
5606#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5607 struct pt_regs regs = {
5608 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5609 .flags = X86_EFLAGS_IF,
5610 };
5611
5612 do_machine_check(&regs, 0);
5613#endif
5614}
5615
851ba692 5616static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK
5617{
5618 /* already handled by vcpu_run */
5619 return 1;
5620}
5621
851ba692 5622static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5623{
1155f76a 5624 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5625 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5626 u32 intr_info, ex_no, error_code;
42dbaa5a 5627 unsigned long cr2, rip, dr6;
6aa8b732
AK
5628 u32 vect_info;
5629 enum emulation_result er;
5630
1155f76a 5631 vect_info = vmx->idt_vectoring_info;
88786475 5632 intr_info = vmx->exit_intr_info;
6aa8b732 5633
a0861c02 5634 if (is_machine_check(intr_info))
851ba692 5635 return handle_machine_check(vcpu);
a0861c02 5636
ef85b673 5637 if (is_nmi(intr_info))
1b6269db 5638 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc 5639
7aa81cc0 5640 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK
5641 if (is_guest_mode(vcpu)) {
5642 kvm_queue_exception(vcpu, UD_VECTOR);
5643 return 1;
5644 }
51d8b661 5645 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5646 if (er != EMULATE_DONE)
7ee5d940 5647 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL
5648 return 1;
5649 }
5650
6aa8b732 5651 error_code = 0;
2e11384c 5652 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5653 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG
5654
5655 /*
5656 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5657 * MMIO, it is better to report an internal error.
5658 * See the comments in vmx_handle_exit.
5659 */
5660 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5661 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5662 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5663 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5664 vcpu->run->internal.ndata = 3;
bf4ca23e
XG
5665 vcpu->run->internal.data[0] = vect_info;
5666 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5667 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG
5668 return 0;
5669 }
5670
6aa8b732 5671 if (is_page_fault(intr_info)) {
1439442c 5672 /* EPT won't cause page fault directly */
cf3ace79 5673 BUG_ON(enable_ept);
6aa8b732 5674 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT
5675 trace_kvm_page_fault(cr2, error_code);
5676
3298b75c 5677 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5678 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5679 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK
5680 }
5681
d0bfb940 5682 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN
5683
5684 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5685 return handle_rmode_exception(vcpu, ex_no, error_code);
5686
42dbaa5a 5687 switch (ex_no) {
54a20552
EN
5688 case AC_VECTOR:
5689 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5690 return 1;
42dbaa5a
JK
5691 case DB_VECTOR:
5692 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5693 if (!(vcpu->guest_debug &
5694 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5695 vcpu->arch.dr6 &= ~15;
6f43ed01 5696 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD
5697 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5698 skip_emulated_instruction(vcpu);
5699
42dbaa5a
JK
5700 kvm_queue_exception(vcpu, DB_VECTOR);
5701 return 1;
5702 }
5703 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5704 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5705 /* fall through */
5706 case BP_VECTOR:
c573cd22
JK
5707 /*
5708 * Update instruction length as we may reinject #BP from
5709 * user space while in guest debugging mode. Reading it for
5710 * #DB as well causes no harm, it is not used in that case.
5711 */
5712 vmx->vcpu.arch.event_exit_inst_len =
5713 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5714 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5715 rip = kvm_rip_read(vcpu);
d0bfb940
JK
5716 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5717 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK
5718 break;
5719 default:
d0bfb940
JK
5720 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5721 kvm_run->ex.exception = ex_no;
5722 kvm_run->ex.error_code = error_code;
42dbaa5a 5723 break;
6aa8b732 5724 }
6aa8b732
AK
5725 return 0;
5726}
5727
851ba692 5728static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5729{
1165f5fe 5730 ++vcpu->stat.irq_exits;
6aa8b732
AK
5731 return 1;
5732}
5733
851ba692 5734static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5735{
851ba692 5736 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK
5737 return 0;
5738}
6aa8b732 5739
851ba692 5740static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5741{
bfdaab09 5742 unsigned long exit_qualification;
6affcbed 5743 int size, in, string, ret;
039576c0 5744 unsigned port;
6aa8b732 5745
bfdaab09 5746 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5747 string = (exit_qualification & 16) != 0;
cf8f70bf 5748 in = (exit_qualification & 8) != 0;
e70669ab 5749
cf8f70bf 5750 ++vcpu->stat.io_exits;
e70669ab 5751
cf8f70bf 5752 if (string || in)
51d8b661 5753 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5754
cf8f70bf
GN
5755 port = exit_qualification >> 16;
5756 size = (exit_qualification & 7) + 1;
cf8f70bf 5757
6affcbed
KH
5758 ret = kvm_skip_emulated_instruction(vcpu);
5759
5760 /*
5761 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5762 * KVM_EXIT_DEBUG here.
5763 */
5764 return kvm_fast_pio_out(vcpu, size, port) && ret;
6aa8b732
AK
5765}
5766
102d8325
IM
5767static void
5768vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5769{
5770 /*
5771 * Patch in the VMCALL instruction:
5772 */
5773 hypercall[0] = 0x0f;
5774 hypercall[1] = 0x01;
5775 hypercall[2] = 0xc1;
102d8325
IM
5776}
5777
0fa06071 5778/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE
5779static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5780{
eeadf9e7 5781 if (is_guest_mode(vcpu)) {
1a0d74e6
JK
5782 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5783 unsigned long orig_val = val;
5784
eeadf9e7
NHE
5785 /*
5786 * We get here when L2 changed cr0 in a way that did not change
5787 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK
5788 * but did change L0 shadowed bits. So we first calculate the
5789 * effective cr0 value that L1 would like to write into the
5790 * hardware. It consists of the L2-owned bits from the new
5791 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5792 */
1a0d74e6
JK
5793 val = (val & ~vmcs12->cr0_guest_host_mask) |
5794 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5795
3899152c 5796 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 5797 return 1;
1a0d74e6
JK
5798
5799 if (kvm_set_cr0(vcpu, val))
5800 return 1;
5801 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5802 return 0;
1a0d74e6
JK
5803 } else {
5804 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 5805 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 5806 return 1;
3899152c 5807
eeadf9e7 5808 return kvm_set_cr0(vcpu, val);
1a0d74e6 5809 }
eeadf9e7
NHE
5810}
5811
5812static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5813{
5814 if (is_guest_mode(vcpu)) {
1a0d74e6
JK
5815 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5816 unsigned long orig_val = val;
5817
5818 /* analogously to handle_set_cr0 */
5819 val = (val & ~vmcs12->cr4_guest_host_mask) |
5820 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5821 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5822 return 1;
1a0d74e6 5823 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE
5824 return 0;
5825 } else
5826 return kvm_set_cr4(vcpu, val);
5827}
5828
851ba692 5829static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5830{
229456fc 5831 unsigned long exit_qualification, val;
6aa8b732
AK
5832 int cr;
5833 int reg;
49a9b07e 5834 int err;
6affcbed 5835 int ret;
6aa8b732 5836
bfdaab09 5837 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK
5838 cr = exit_qualification & 15;
5839 reg = (exit_qualification >> 8) & 15;
5840 switch ((exit_qualification >> 4) & 3) {
5841 case 0: /* mov to cr */
1e32c079 5842 val = kvm_register_readl(vcpu, reg);
229456fc 5843 trace_kvm_cr_write(cr, val);
6aa8b732
AK
5844 switch (cr) {
5845 case 0:
eeadf9e7 5846 err = handle_set_cr0(vcpu, val);
6affcbed 5847 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 5848 case 3:
2390218b 5849 err = kvm_set_cr3(vcpu, val);
6affcbed 5850 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 5851 case 4:
eeadf9e7 5852 err = handle_set_cr4(vcpu, val);
6affcbed 5853 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN
5854 case 8: {
5855 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5856 u8 cr8 = (u8)val;
eea1cff9 5857 err = kvm_set_cr8(vcpu, cr8);
6affcbed 5858 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 5859 if (lapic_in_kernel(vcpu))
6affcbed 5860 return ret;
0a5fff19 5861 if (cr8_prev <= cr8)
6affcbed
KH
5862 return ret;
5863 /*
5864 * TODO: we might be squashing a
5865 * KVM_GUESTDBG_SINGLESTEP-triggered
5866 * KVM_EXIT_DEBUG here.
5867 */
851ba692 5868 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN
5869 return 0;
5870 }
4b8073e4 5871 }
6aa8b732 5872 break;
25c4c276 5873 case 2: /* clts */
bd7e5b08
PB
5874 WARN_ONCE(1, "Guest should always own CR0.TS");
5875 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 5876 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 5877 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5878 case 1: /*mov from cr*/
5879 switch (cr) {
5880 case 3:
9f8fe504
AK
5881 val = kvm_read_cr3(vcpu);
5882 kvm_register_write(vcpu, reg, val);
5883 trace_kvm_cr_read(cr, val);
6affcbed 5884 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 5885 case 8:
229456fc
MT
5886 val = kvm_get_cr8(vcpu);
5887 kvm_register_write(vcpu, reg, val);
5888 trace_kvm_cr_read(cr, val);
6affcbed 5889 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5890 }
5891 break;
5892 case 3: /* lmsw */
a1f83a74 5893 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5894 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5895 kvm_lmsw(vcpu, val);
6aa8b732 5896
6affcbed 5897 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5898 default:
5899 break;
5900 }
851ba692 5901 vcpu->run->exit_reason = 0;
a737f256 5902 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK
5903 (int)(exit_qualification >> 4) & 3, cr);
5904 return 0;
5905}
5906
851ba692 5907static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5908{
bfdaab09 5909 unsigned long exit_qualification;
16f8a6f9
NA
5910 int dr, dr7, reg;
5911
5912 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5913 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5914
5915 /* First, if DR does not exist, trigger UD */
5916 if (!kvm_require_dr(vcpu, dr))
5917 return 1;
6aa8b732 5918
f2483415 5919 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK
5920 if (!kvm_require_cpl(vcpu, 0))
5921 return 1;
16f8a6f9
NA
5922 dr7 = vmcs_readl(GUEST_DR7);
5923 if (dr7 & DR7_GD) {
42dbaa5a
JK
5924 /*
5925 * As the vm-exit takes precedence over the debug trap, we
5926 * need to emulate the latter, either for the host or the
5927 * guest debugging itself.
5928 */
5929 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5930 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5931 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5932 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK
5933 vcpu->run->debug.arch.exception = DB_VECTOR;
5934 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK
5935 return 0;
5936 } else {
7305eb5d 5937 vcpu->arch.dr6 &= ~15;
6f43ed01 5938 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK
5939 kvm_queue_exception(vcpu, DB_VECTOR);
5940 return 1;
5941 }
5942 }
5943
81908bf4 5944 if (vcpu->guest_debug == 0) {
8f22372f
PB
5945 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5946 CPU_BASED_MOV_DR_EXITING);
81908bf4
PB
5947
5948 /*
5949 * No more DR vmexits; force a reload of the debug registers
5950 * and reenter on this instruction. The next vmexit will
5951 * retrieve the full state of the debug registers.
5952 */
5953 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5954 return 1;
5955 }
5956
42dbaa5a
JK
5957 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5958 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5959 unsigned long val;
4c4d563b
JK
5960
5961 if (kvm_get_dr(vcpu, dr, &val))
5962 return 1;
5963 kvm_register_write(vcpu, reg, val);
020df079 5964 } else
5777392e 5965 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK
5966 return 1;
5967
6affcbed 5968 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5969}
5970
73aaf249
JK
5971static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5972{
5973 return vcpu->arch.dr6;
5974}
5975
5976static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5977{
5978}
5979
81908bf4
PB
5980static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5981{
81908bf4
PB
5982 get_debugreg(vcpu->arch.db[0], 0);
5983 get_debugreg(vcpu->arch.db[1], 1);
5984 get_debugreg(vcpu->arch.db[2], 2);
5985 get_debugreg(vcpu->arch.db[3], 3);
5986 get_debugreg(vcpu->arch.dr6, 6);
5987 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5988
5989 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
8f22372f 5990 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
81908bf4
PB
5991}
5992
020df079
GN
5993static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5994{
5995 vmcs_writel(GUEST_DR7, val);
5996}
5997
851ba692 5998static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5999{
6a908b62 6000 return kvm_emulate_cpuid(vcpu);
6aa8b732
AK
6001}
6002
851ba692 6003static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 6004{
ad312c7c 6005 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 6006 struct msr_data msr_info;
6aa8b732 6007
609e36d3
PB
6008 msr_info.index = ecx;
6009 msr_info.host_initiated = false;
6010 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 6011 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 6012 kvm_inject_gp(vcpu, 0);
6aa8b732
AK
6013 return 1;
6014 }
6015
609e36d3 6016 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 6017
6aa8b732 6018 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB
6019 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6020 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6affcbed 6021 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
6022}
6023
851ba692 6024static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 6025{
8fe8ab46 6026 struct msr_data msr;
ad312c7c
ZX
6027 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6028 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6029 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 6030
8fe8ab46
WA
6031 msr.data = data;
6032 msr.index = ecx;
6033 msr.host_initiated = false;
854e8bb1 6034 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 6035 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 6036 kvm_inject_gp(vcpu, 0);
6aa8b732
AK
6037 return 1;
6038 }
6039
59200273 6040 trace_kvm_msr_write(ecx, data);
6affcbed 6041 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
6042}
6043
851ba692 6044static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 6045{
eb90f341 6046 kvm_apic_update_ppr(vcpu);
6e5d865c
YS
6047 return 1;
6048}
6049
851ba692 6050static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 6051{
47c0152e
PB
6052 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6053 CPU_BASED_VIRTUAL_INTR_PENDING);
2714d1d3 6054
3842d135
AK
6055 kvm_make_request(KVM_REQ_EVENT, vcpu);
6056
a26bf12a 6057 ++vcpu->stat.irq_window_exits;
6aa8b732
AK
6058 return 1;
6059}
6060
851ba692 6061static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 6062{
d3bef15f 6063 return kvm_emulate_halt(vcpu);
6aa8b732
AK
6064}
6065
851ba692 6066static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 6067{
0d9c055e 6068 return kvm_emulate_hypercall(vcpu);
c21415e8
IM
6069}
6070
ec25d5e6
GN
6071static int handle_invd(struct kvm_vcpu *vcpu)
6072{
51d8b661 6073 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN
6074}
6075
851ba692 6076static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 6077{
f9c617f6 6078 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT
6079
6080 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 6081 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT
6082}
6083
fee84b07
AK
6084static int handle_rdpmc(struct kvm_vcpu *vcpu)
6085{
6086 int err;
6087
6088 err = kvm_rdpmc(vcpu);
6affcbed 6089 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK
6090}
6091
851ba692 6092static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 6093{
6affcbed 6094 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED
6095}
6096
2acf923e
DC
6097static int handle_xsetbv(struct kvm_vcpu *vcpu)
6098{
6099 u64 new_bv = kvm_read_edx_eax(vcpu);
6100 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6101
6102 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 6103 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC
6104 return 1;
6105}
6106
f53cd63c
WL
6107static int handle_xsaves(struct kvm_vcpu *vcpu)
6108{
6affcbed 6109 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL
6110 WARN(1, "this should never happen\n");
6111 return 1;
6112}
6113
6114static int handle_xrstors(struct kvm_vcpu *vcpu)
6115{
6affcbed 6116 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL
6117 WARN(1, "this should never happen\n");
6118 return 1;
6119}
6120
851ba692 6121static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 6122{
58fbbf26
KT
6123 if (likely(fasteoi)) {
6124 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6125 int access_type, offset;
6126
6127 access_type = exit_qualification & APIC_ACCESS_TYPE;
6128 offset = exit_qualification & APIC_ACCESS_OFFSET;
6129 /*
6130 * Sane guest uses MOV to write EOI, with written value
6131 * not cared. So make a short-circuit here by avoiding
6132 * heavy instruction emulation.
6133 */
6134 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6135 (offset == APIC_EOI)) {
6136 kvm_lapic_set_eoi(vcpu);
6affcbed 6137 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT
6138 }
6139 }
51d8b661 6140 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY
6141}
6142
c7c9c56c
YZ
6143static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6144{
6145 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6146 int vector = exit_qualification & 0xff;
6147
6148 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6149 kvm_apic_set_eoi_accelerated(vcpu, vector);
6150 return 1;
6151}
6152
83d4c286
YZ
6153static int handle_apic_write(struct kvm_vcpu *vcpu)
6154{
6155 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6156 u32 offset = exit_qualification & 0xfff;
6157
6158 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6159 kvm_apic_write_nodecode(vcpu, offset);
6160 return 1;
6161}
6162
851ba692 6163static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 6164{
60637aac 6165 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 6166 unsigned long exit_qualification;
e269fb21
JK
6167 bool has_error_code = false;
6168 u32 error_code = 0;
37817f29 6169 u16 tss_selector;
7f3d35fd 6170 int reason, type, idt_v, idt_index;
64a7ec06
GN
6171
6172 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 6173 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 6174 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE
6175
6176 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6177
6178 reason = (u32)exit_qualification >> 30;
64a7ec06
GN
6179 if (reason == TASK_SWITCH_GATE && idt_v) {
6180 switch (type) {
6181 case INTR_TYPE_NMI_INTR:
6182 vcpu->arch.nmi_injected = false;
654f06fc 6183 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN
6184 break;
6185 case INTR_TYPE_EXT_INTR:
66fd3f7f 6186 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN
6187 kvm_clear_interrupt_queue(vcpu);
6188 break;
6189 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK
6190 if (vmx->idt_vectoring_info &
6191 VECTORING_INFO_DELIVER_CODE_MASK) {
6192 has_error_code = true;
6193 error_code =
6194 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6195 }
6196 /* fall through */
64a7ec06
GN
6197 case INTR_TYPE_SOFT_EXCEPTION:
6198 kvm_clear_exception_queue(vcpu);
6199 break;
6200 default:
6201 break;
6202 }
60637aac 6203 }
37817f29
IE
6204 tss_selector = exit_qualification;
6205
64a7ec06
GN
6206 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6207 type != INTR_TYPE_EXT_INTR &&
6208 type != INTR_TYPE_NMI_INTR))
6209 skip_emulated_instruction(vcpu);
6210
7f3d35fd
KW
6211 if (kvm_task_switch(vcpu, tss_selector,
6212 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6213 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN
6214 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6215 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6216 vcpu->run->internal.ndata = 0;
42dbaa5a 6217 return 0;
acb54517 6218 }
42dbaa5a 6219
42dbaa5a
JK
6220 /*
6221 * TODO: What about debug traps on tss switch?
6222 * Are we supposed to inject them and update dr6?
6223 */
6224
6225 return 1;
37817f29
IE
6226}
6227
851ba692 6228static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 6229{
f9c617f6 6230 unsigned long exit_qualification;
1439442c 6231 gpa_t gpa;
4f5982a5 6232 u32 error_code;
1439442c 6233
f9c617f6 6234 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 6235
0be9c7a8
GN
6236 /*
6237 * EPT violation happened while executing iret from NMI,
6238 * "blocked by NMI" bit has to be set before next VM entry.
6239 * There are errata that may cause this bit to not be set:
6240 * AAK134, BY25.
6241 */
bcd1c294 6242 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
bcd1c294 6243 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN
6244 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6245
1439442c 6246 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 6247 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 6248
27959a44 6249 /* Is it a read fault? */
ab22a473 6250 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS
6251 ? PFERR_USER_MASK : 0;
6252 /* Is it a write fault? */
ab22a473 6253 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS
6254 ? PFERR_WRITE_MASK : 0;
6255 /* Is it a fetch fault? */
ab22a473 6256 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS
6257 ? PFERR_FETCH_MASK : 0;
6258 /* ept page table entry is present? */
6259 error_code |= (exit_qualification &
6260 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6261 EPT_VIOLATION_EXECUTABLE))
6262 ? PFERR_PRESENT_MASK : 0;
4f5982a5 6263
db1c056c 6264 vcpu->arch.gpa_available = true;
25d92081
YZ
6265 vcpu->arch.exit_qualification = exit_qualification;
6266
4f5982a5 6267 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY
6268}
6269
851ba692 6270static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 6271{
f735d4af 6272 int ret;
68f89400
MT
6273 gpa_t gpa;
6274
6275 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 6276 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 6277 trace_kvm_fast_mmio(gpa);
6affcbed 6278 return kvm_skip_emulated_instruction(vcpu);
68c3b4d1 6279 }
68f89400 6280
450869d6 6281 ret = handle_mmio_page_fault(vcpu, gpa, true);
db1c056c 6282 vcpu->arch.gpa_available = true;
b37fbea6 6283 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG
6284 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6285 EMULATE_DONE;
f8f55942
XG
6286
6287 if (unlikely(ret == RET_MMIO_PF_INVALID))
6288 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6289
b37fbea6 6290 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG
6291 return 1;
6292
6293 /* It is the real ept misconfig */
f735d4af 6294 WARN_ON(1);
68f89400 6295
851ba692
AK
6296 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6297 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT
6298
6299 return 0;
6300}
6301
851ba692 6302static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 6303{
47c0152e
PB
6304 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6305 CPU_BASED_VIRTUAL_NMI_PENDING);
f08864b4 6306 ++vcpu->stat.nmi_window_exits;
3842d135 6307 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY
6308
6309 return 1;
6310}
6311
80ced186 6312static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 6313{
8b3079a5
AK
6314 struct vcpu_vmx *vmx = to_vmx(vcpu);
6315 enum emulation_result err = EMULATE_DONE;
80ced186 6316 int ret = 1;
49e9d557
AK
6317 u32 cpu_exec_ctrl;
6318 bool intr_window_requested;
b8405c18 6319 unsigned count = 130;
49e9d557
AK
6320
6321 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6322 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 6323
98eb2f8b 6324 while (vmx->emulation_required && count-- != 0) {
bdea48e3 6325 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK
6326 return handle_interrupt_window(&vmx->vcpu);
6327
72875d8a 6328 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK
6329 return 1;
6330
991eebf9 6331 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 6332
ac0a48c3 6333 if (err == EMULATE_USER_EXIT) {
94452b9e 6334 ++vcpu->stat.mmio_exits;
80ced186
MG
6335 ret = 0;
6336 goto out;
6337 }
1d5a4d9b 6338
de5f70e0
AK
6339 if (err != EMULATE_DONE) {
6340 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6341 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6342 vcpu->run->internal.ndata = 0;
6d77dbfc 6343 return 0;
de5f70e0 6344 }
ea953ef0 6345
8d76c49e
GN
6346 if (vcpu->arch.halt_request) {
6347 vcpu->arch.halt_request = 0;
5cb56059 6348 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN
6349 goto out;
6350 }
6351
ea953ef0 6352 if (signal_pending(current))
80ced186 6353 goto out;
ea953ef0
MG
6354 if (need_resched())
6355 schedule();
6356 }
6357
80ced186
MG
6358out:
6359 return ret;
ea953ef0
MG
6360}
6361
b4a2d31d
RK
6362static int __grow_ple_window(int val)
6363{
6364 if (ple_window_grow < 1)
6365 return ple_window;
6366
6367 val = min(val, ple_window_actual_max);
6368
6369 if (ple_window_grow < ple_window)
6370 val *= ple_window_grow;
6371 else
6372 val += ple_window_grow;
6373
6374 return val;
6375}
6376
6377static int __shrink_ple_window(int val, int modifier, int minimum)
6378{
6379 if (modifier < 1)
6380 return ple_window;
6381
6382 if (modifier < ple_window)
6383 val /= modifier;
6384 else
6385 val -= modifier;
6386
6387 return max(val, minimum);
6388}
6389
6390static void grow_ple_window(struct kvm_vcpu *vcpu)
6391{
6392 struct vcpu_vmx *vmx = to_vmx(vcpu);
6393 int old = vmx->ple_window;
6394
6395 vmx->ple_window = __grow_ple_window(old);
6396
6397 if (vmx->ple_window != old)
6398 vmx->ple_window_dirty = true;
7b46268d
RK
6399
6400 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK
6401}
6402
6403static void shrink_ple_window(struct kvm_vcpu *vcpu)
6404{
6405 struct vcpu_vmx *vmx = to_vmx(vcpu);
6406 int old = vmx->ple_window;
6407
6408 vmx->ple_window = __shrink_ple_window(old,
6409 ple_window_shrink, ple_window);
6410
6411 if (vmx->ple_window != old)
6412 vmx->ple_window_dirty = true;
7b46268d
RK
6413
6414 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK
6415}
6416
6417/*
6418 * ple_window_actual_max is computed to be one grow_ple_window() below
6419 * ple_window_max. (See __grow_ple_window for the reason.)
6420 * This prevents overflows, because ple_window_max is int.
6421 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6422 * this process.
6423 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6424 */
6425static void update_ple_window_actual_max(void)
6426{
6427 ple_window_actual_max =
6428 __shrink_ple_window(max(ple_window_max, ple_window),
6429 ple_window_grow, INT_MIN);
6430}
6431
bf9f6ac8
FW
6432/*
6433 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6434 */
6435static void wakeup_handler(void)
6436{
6437 struct kvm_vcpu *vcpu;
6438 int cpu = smp_processor_id();
6439
6440 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6441 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6442 blocked_vcpu_list) {
6443 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6444
6445 if (pi_test_on(pi_desc) == 1)
6446 kvm_vcpu_kick(vcpu);
6447 }
6448 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6449}
6450
f160c7b7
JS
6451void vmx_enable_tdp(void)
6452{
6453 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6454 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6455 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6456 0ull, VMX_EPT_EXECUTABLE_MASK,
6457 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
995f00a6 6458 VMX_EPT_RWX_MASK);
f160c7b7
JS
6459
6460 ept_set_mmio_spte_mask();
6461 kvm_enable_tdp();
6462}
6463
f2c7648d
TC
6464static __init int hardware_setup(void)
6465{
34a1cd60
TC
6466 int r = -ENOMEM, i, msr;
6467
6468 rdmsrl_safe(MSR_EFER, &host_efer);
6469
6470 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6471 kvm_define_shared_msr(i, vmx_msr_index[i]);
6472
23611332
RK
6473 for (i = 0; i < VMX_BITMAP_NR; i++) {
6474 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6475 if (!vmx_bitmap[i])
6476 goto out;
6477 }
34a1cd60
TC
6478
6479 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
34a1cd60
TC
6480 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6481 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6482
6483 /*
6484 * Allow direct access to the PC debug port (it is often used for I/O
6485 * delays, but the vmexits simply slow things down).
6486 */
6487 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6488 clear_bit(0x80, vmx_io_bitmap_a);
6489
6490 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6491
6492 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6493 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6494
34a1cd60
TC
6495 if (setup_vmcs_config(&vmcs_config) < 0) {
6496 r = -EIO;
23611332 6497 goto out;
baa03522 6498 }
f2c7648d
TC
6499
6500 if (boot_cpu_has(X86_FEATURE_NX))
6501 kvm_enable_efer_bits(EFER_NX);
6502
08d839c4
WL
6503 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6504 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
f2c7648d 6505 enable_vpid = 0;
08d839c4 6506
f2c7648d
TC
6507 if (!cpu_has_vmx_shadow_vmcs())
6508 enable_shadow_vmcs = 0;
6509 if (enable_shadow_vmcs)
6510 init_vmcs_shadow_fields();
6511
6512 if (!cpu_has_vmx_ept() ||
6513 !cpu_has_vmx_ept_4levels()) {
6514 enable_ept = 0;
6515 enable_unrestricted_guest = 0;
6516 enable_ept_ad_bits = 0;
6517 }
6518
fce6ac4c 6519 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
f2c7648d
TC
6520 enable_ept_ad_bits = 0;
6521
6522 if (!cpu_has_vmx_unrestricted_guest())
6523 enable_unrestricted_guest = 0;
6524
ad15a296 6525 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC
6526 flexpriority_enabled = 0;
6527
ad15a296
PB
6528 /*
6529 * set_apic_access_page_addr() is used to reload apic access
6530 * page upon invalidation. No need to do anything if not
6531 * using the APIC_ACCESS_ADDR VMCS field.
6532 */
6533 if (!flexpriority_enabled)
f2c7648d 6534 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC
6535
6536 if (!cpu_has_vmx_tpr_shadow())
6537 kvm_x86_ops->update_cr8_intercept = NULL;
6538
6539 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6540 kvm_disable_largepages();
6541
6542 if (!cpu_has_vmx_ple())
6543 ple_gap = 0;
6544
76dfafd5 6545 if (!cpu_has_vmx_apicv()) {
f2c7648d 6546 enable_apicv = 0;
76dfafd5
PB
6547 kvm_x86_ops->sync_pir_to_irr = NULL;
6548 }
f2c7648d 6549
64903d61
HZ
6550 if (cpu_has_vmx_tsc_scaling()) {
6551 kvm_has_tsc_control = true;
6552 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6553 kvm_tsc_scaling_ratio_frac_bits = 48;
6554 }
6555
baa03522
TC
6556 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6557 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6558 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6559 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6560 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6561 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
baa03522 6562
c63e4563 6563 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
baa03522 6564 vmx_msr_bitmap_legacy, PAGE_SIZE);
c63e4563 6565 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
baa03522 6566 vmx_msr_bitmap_longmode, PAGE_SIZE);
c63e4563 6567 memcpy(vmx_msr_bitmap_legacy_x2apic,
f6e90f9e 6568 vmx_msr_bitmap_legacy, PAGE_SIZE);
c63e4563 6569 memcpy(vmx_msr_bitmap_longmode_x2apic,
f6e90f9e 6570 vmx_msr_bitmap_longmode, PAGE_SIZE);
baa03522 6571
04bb92e4
WL
6572 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6573
40d8338d
RK
6574 for (msr = 0x800; msr <= 0x8ff; msr++) {
6575 if (msr == 0x839 /* TMCCT */)
6576 continue;
2e69f865 6577 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
40d8338d 6578 }
3ce424e4 6579
f6e90f9e 6580 /*
2e69f865
RK
6581 * TPR reads and writes can be virtualized even if virtual interrupt
6582 * delivery is not in use.
f6e90f9e 6583 */
2e69f865
RK
6584 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6585 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
3ce424e4 6586
3ce424e4 6587 /* EOI */
2e69f865 6588 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
3ce424e4 6589 /* SELF-IPI */
2e69f865 6590 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
baa03522 6591
f160c7b7
JS
6592 if (enable_ept)
6593 vmx_enable_tdp();
6594 else
baa03522
TC
6595 kvm_disable_tdp();
6596
6597 update_ple_window_actual_max();
6598
843e4330
KH
6599 /*
6600 * Only enable PML when hardware supports PML feature, and both EPT
6601 * and EPT A/D bit features are enabled -- PML depends on them to work.
6602 */
6603 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6604 enable_pml = 0;
6605
6606 if (!enable_pml) {
6607 kvm_x86_ops->slot_enable_log_dirty = NULL;
6608 kvm_x86_ops->slot_disable_log_dirty = NULL;
6609 kvm_x86_ops->flush_log_dirty = NULL;
6610 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6611 }
6612
64672c95
YJ
6613 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6614 u64 vmx_msr;
6615
6616 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6617 cpu_preemption_timer_multi =
6618 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6619 } else {
6620 kvm_x86_ops->set_hv_timer = NULL;
6621 kvm_x86_ops->cancel_hv_timer = NULL;
6622 }
6623
bf9f6ac8
FW
6624 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6625
c45dcc71
AR
6626 kvm_mce_cap_supported |= MCG_LMCE_P;
6627
f2c7648d 6628 return alloc_kvm_area();
34a1cd60 6629
34a1cd60 6630out:
23611332
RK
6631 for (i = 0; i < VMX_BITMAP_NR; i++)
6632 free_page((unsigned long)vmx_bitmap[i]);
34a1cd60
TC
6633
6634 return r;
f2c7648d
TC
6635}
6636
6637static __exit void hardware_unsetup(void)
6638{
23611332
RK
6639 int i;
6640
6641 for (i = 0; i < VMX_BITMAP_NR; i++)
6642 free_page((unsigned long)vmx_bitmap[i]);
34a1cd60 6643
f2c7648d
TC
6644 free_kvm_area();
6645}
6646
4b8d54f9
ZE
6647/*
6648 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6649 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6650 */
9fb41ba8 6651static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6652{
b4a2d31d
RK
6653 if (ple_gap)
6654 grow_ple_window(vcpu);
6655
4b8d54f9 6656 kvm_vcpu_on_spin(vcpu);
6affcbed 6657 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE
6658}
6659
87c00572 6660static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6661{
6affcbed 6662 return kvm_skip_emulated_instruction(vcpu);
59708670
SY
6663}
6664
87c00572
GS
6665static int handle_mwait(struct kvm_vcpu *vcpu)
6666{
6667 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6668 return handle_nop(vcpu);
6669}
6670
5f3d45e7
MD
6671static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6672{
6673 return 1;
6674}
6675
87c00572
GS
6676static int handle_monitor(struct kvm_vcpu *vcpu)
6677{
6678 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6679 return handle_nop(vcpu);
6680}
6681
ff2f6fe9
NHE
6682/*
6683 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6684 * We could reuse a single VMCS for all the L2 guests, but we also want the
6685 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6686 * allows keeping them loaded on the processor, and in the future will allow
6687 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6688 * every entry if they never change.
6689 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6690 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6691 *
6692 * The following functions allocate and free a vmcs02 in this pool.
6693 */
6694
6695/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6696static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6697{
6698 struct vmcs02_list *item;
6699 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6700 if (item->vmptr == vmx->nested.current_vmptr) {
6701 list_move(&item->list, &vmx->nested.vmcs02_pool);
6702 return &item->vmcs02;
6703 }
6704
6705 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6706 /* Recycle the least recently used VMCS. */
d74c0e6b
GT
6707 item = list_last_entry(&vmx->nested.vmcs02_pool,
6708 struct vmcs02_list, list);
ff2f6fe9
NHE
6709 item->vmptr = vmx->nested.current_vmptr;
6710 list_move(&item->list, &vmx->nested.vmcs02_pool);
6711 return &item->vmcs02;
6712 }
6713
6714 /* Create a new VMCS */
0fa24ce3 6715 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE
6716 if (!item)
6717 return NULL;
6718 item->vmcs02.vmcs = alloc_vmcs();
355f4fb1 6719 item->vmcs02.shadow_vmcs = NULL;
ff2f6fe9
NHE
6720 if (!item->vmcs02.vmcs) {
6721 kfree(item);
6722 return NULL;
6723 }
6724 loaded_vmcs_init(&item->vmcs02);
6725 item->vmptr = vmx->nested.current_vmptr;
6726 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6727 vmx->nested.vmcs02_num++;
6728 return &item->vmcs02;
6729}
6730
6731/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6732static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6733{
6734 struct vmcs02_list *item;
6735 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6736 if (item->vmptr == vmptr) {
6737 free_loaded_vmcs(&item->vmcs02);
6738 list_del(&item->list);
6739 kfree(item);
6740 vmx->nested.vmcs02_num--;
6741 return;
6742 }
6743}
6744
6745/*
6746 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB
6747 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6748 * must be &vmx->vmcs01.
ff2f6fe9
NHE
6749 */
6750static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6751{
6752 struct vmcs02_list *item, *n;
4fa7734c
PB
6753
6754 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6755 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB
6756 /*
6757 * Something will leak if the above WARN triggers. Better than
6758 * a use-after-free.
6759 */
6760 if (vmx->loaded_vmcs == &item->vmcs02)
6761 continue;
6762
6763 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE
6764 list_del(&item->list);
6765 kfree(item);
4fa7734c 6766 vmx->nested.vmcs02_num--;
ff2f6fe9 6767 }
ff2f6fe9
NHE
6768}
6769
0658fbaa
ACL
6770/*
6771 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6772 * set the success or error code of an emulated VMX instruction, as specified
6773 * by Vol 2B, VMX Instruction Reference, "Conventions".
6774 */
6775static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6776{
6777 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6778 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6779 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6780}
6781
6782static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6783{
6784 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6785 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6786 X86_EFLAGS_SF | X86_EFLAGS_OF))
6787 | X86_EFLAGS_CF);
6788}
6789
145c28dd 6790static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL
6791 u32 vm_instruction_error)
6792{
6793 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6794 /*
6795 * failValid writes the error number to the current VMCS, which
6796 * can't be done there isn't a current VMCS.
6797 */
6798 nested_vmx_failInvalid(vcpu);
6799 return;
6800 }
6801 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6802 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6803 X86_EFLAGS_SF | X86_EFLAGS_OF))
6804 | X86_EFLAGS_ZF);
6805 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6806 /*
6807 * We don't need to force a shadow sync because
6808 * VM_INSTRUCTION_ERROR is not shadowed
6809 */
6810}
145c28dd 6811
ff651cb6
WV
6812static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6813{
6814 /* TODO: not to reset guest simply here. */
6815 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
bbe41b95 6816 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
ff651cb6
WV
6817}
6818
f4124500
JK
6819static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6820{
6821 struct vcpu_vmx *vmx =
6822 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6823
6824 vmx->nested.preemption_timer_expired = true;
6825 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6826 kvm_vcpu_kick(&vmx->vcpu);
6827
6828 return HRTIMER_NORESTART;
6829}
6830
19677e32
BD
6831/*
6832 * Decode the memory-address operand of a vmx instruction, as recorded on an
6833 * exit caused by such an instruction (run by a guest hypervisor).
6834 * On success, returns 0. When the operand is invalid, returns 1 and throws
6835 * #UD or #GP.
6836 */
6837static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6838 unsigned long exit_qualification,
f9eb4af6 6839 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6840{
f9eb4af6
EK
6841 gva_t off;
6842 bool exn;
6843 struct kvm_segment s;
6844
19677e32
BD
6845 /*
6846 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6847 * Execution", on an exit, vmx_instruction_info holds most of the
6848 * addressing components of the operand. Only the displacement part
6849 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6850 * For how an actual address is calculated from all these components,
6851 * refer to Vol. 1, "Operand Addressing".
6852 */
6853 int scaling = vmx_instruction_info & 3;
6854 int addr_size = (vmx_instruction_info >> 7) & 7;
6855 bool is_reg = vmx_instruction_info & (1u << 10);
6856 int seg_reg = (vmx_instruction_info >> 15) & 7;
6857 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6858 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6859 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6860 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6861
6862 if (is_reg) {
6863 kvm_queue_exception(vcpu, UD_VECTOR);
6864 return 1;
6865 }
6866
6867 /* Addr = segment_base + offset */
6868 /* offset = base + [index * scale] + displacement */
f9eb4af6 6869 off = exit_qualification; /* holds the displacement */
19677e32 6870 if (base_is_valid)
f9eb4af6 6871 off += kvm_register_read(vcpu, base_reg);
19677e32 6872 if (index_is_valid)
f9eb4af6
EK
6873 off += kvm_register_read(vcpu, index_reg)<<scaling;
6874 vmx_get_segment(vcpu, &s, seg_reg);
6875 *ret = s.base + off;
19677e32
BD
6876
6877 if (addr_size == 1) /* 32 bit */
6878 *ret &= 0xffffffff;
6879
f9eb4af6
EK
6880 /* Checks for #GP/#SS exceptions. */
6881 exn = false;
ff30ef40
QC
6882 if (is_long_mode(vcpu)) {
6883 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6884 * non-canonical form. This is the only check on the memory
6885 * destination for long mode!
6886 */
6887 exn = is_noncanonical_address(*ret);
6888 } else if (is_protmode(vcpu)) {
f9eb4af6
EK
6889 /* Protected mode: apply checks for segment validity in the
6890 * following order:
6891 * - segment type check (#GP(0) may be thrown)
6892 * - usability check (#GP(0)/#SS(0))
6893 * - limit check (#GP(0)/#SS(0))
6894 */
6895 if (wr)
6896 /* #GP(0) if the destination operand is located in a
6897 * read-only data segment or any code segment.
6898 */
6899 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6900 else
6901 /* #GP(0) if the source operand is located in an
6902 * execute-only code segment
6903 */
6904 exn = ((s.type & 0xa) == 8);
ff30ef40
QC
6905 if (exn) {
6906 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6907 return 1;
6908 }
f9eb4af6
EK
6909 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6910 */
6911 exn = (s.unusable != 0);
6912 /* Protected mode: #GP(0)/#SS(0) if the memory
6913 * operand is outside the segment limit.
6914 */
6915 exn = exn || (off + sizeof(u64) > s.limit);
6916 }
6917 if (exn) {
6918 kvm_queue_exception_e(vcpu,
6919 seg_reg == VCPU_SREG_SS ?
6920 SS_VECTOR : GP_VECTOR,
6921 0);
6922 return 1;
6923 }
6924
19677e32
BD
6925 return 0;
6926}
6927
cbf71279 6928static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
3573e22c
BD
6929{
6930 gva_t gva;
3573e22c 6931 struct x86_exception e;
3573e22c
BD
6932
6933 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 6934 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD
6935 return 1;
6936
cbf71279
RK
6937 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
6938 sizeof(*vmpointer), &e)) {
3573e22c
BD
6939 kvm_inject_page_fault(vcpu, &e);
6940 return 1;
6941 }
6942
3573e22c
BD
6943 return 0;
6944}
6945
e29acc55
JM
6946static int enter_vmx_operation(struct kvm_vcpu *vcpu)
6947{
6948 struct vcpu_vmx *vmx = to_vmx(vcpu);
6949 struct vmcs *shadow_vmcs;
6950
6951 if (cpu_has_vmx_msr_bitmap()) {
6952 vmx->nested.msr_bitmap =
6953 (unsigned long *)__get_free_page(GFP_KERNEL);
6954 if (!vmx->nested.msr_bitmap)
6955 goto out_msr_bitmap;
6956 }
6957
6958 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
6959 if (!vmx->nested.cached_vmcs12)
6960 goto out_cached_vmcs12;
6961
6962 if (enable_shadow_vmcs) {
6963 shadow_vmcs = alloc_vmcs();
6964 if (!shadow_vmcs)
6965 goto out_shadow_vmcs;
6966 /* mark vmcs as shadow */
6967 shadow_vmcs->revision_id |= (1u << 31);
6968 /* init shadow vmcs */
6969 vmcs_clear(shadow_vmcs);
6970 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
6971 }
6972
6973 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6974 vmx->nested.vmcs02_num = 0;
6975
6976 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6977 HRTIMER_MODE_REL_PINNED);
6978 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6979
6980 vmx->nested.vmxon = true;
6981 return 0;
6982
6983out_shadow_vmcs:
6984 kfree(vmx->nested.cached_vmcs12);
6985
6986out_cached_vmcs12:
6987 free_page((unsigned long)vmx->nested.msr_bitmap);
6988
6989out_msr_bitmap:
6990 return -ENOMEM;
6991}
6992
ec378aee
NHE
6993/*
6994 * Emulate the VMXON instruction.
6995 * Currently, we just remember that VMX is active, and do not save or even
6996 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6997 * do not currently need to store anything in that guest-allocated memory
6998 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6999 * argument is different from the VMXON pointer (which the spec says they do).
7000 */
7001static int handle_vmon(struct kvm_vcpu *vcpu)
7002{
e29acc55 7003 int ret;
cbf71279
RK
7004 gpa_t vmptr;
7005 struct page *page;
ec378aee 7006 struct vcpu_vmx *vmx = to_vmx(vcpu);
b3897a49
NHE
7007 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7008 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee 7009
70f3aac9
JM
7010 /*
7011 * The Intel VMX Instruction Reference lists a bunch of bits that are
7012 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7013 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7014 * Otherwise, we should fail with #UD. But most faulting conditions
7015 * have already been checked by hardware, prior to the VM-exit for
7016 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7017 * that bit set to 1 in non-root mode.
ec378aee 7018 */
70f3aac9 7019 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
ec378aee
NHE
7020 kvm_queue_exception(vcpu, UD_VECTOR);
7021 return 1;
7022 }
7023
145c28dd
AG
7024 if (vmx->nested.vmxon) {
7025 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6affcbed 7026 return kvm_skip_emulated_instruction(vcpu);
145c28dd 7027 }
b3897a49 7028
3b84080b 7029 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
b3897a49
NHE
7030 != VMXON_NEEDED_FEATURES) {
7031 kvm_inject_gp(vcpu, 0);
7032 return 1;
7033 }
7034
cbf71279 7035 if (nested_vmx_get_vmptr(vcpu, &vmptr))
21e7fbe7 7036 return 1;
cbf71279
RK
7037
7038 /*
7039 * SDM 3: 24.11.5
7040 * The first 4 bytes of VMXON region contain the supported
7041 * VMCS revision identifier
7042 *
7043 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7044 * which replaces physical address width with 32
7045 */
7046 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7047 nested_vmx_failInvalid(vcpu);
7048 return kvm_skip_emulated_instruction(vcpu);
7049 }
7050
7051 page = nested_get_page(vcpu, vmptr);
7052 if (page == NULL) {
7053 nested_vmx_failInvalid(vcpu);
7054 return kvm_skip_emulated_instruction(vcpu);
7055 }
7056 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7057 kunmap(page);
7058 nested_release_page_clean(page);
7059 nested_vmx_failInvalid(vcpu);
7060 return kvm_skip_emulated_instruction(vcpu);
7061 }
7062 kunmap(page);
7063 nested_release_page_clean(page);
7064
7065 vmx->nested.vmxon_ptr = vmptr;
e29acc55
JM
7066 ret = enter_vmx_operation(vcpu);
7067 if (ret)
7068 return ret;
ec378aee 7069
a25eb114 7070 nested_vmx_succeed(vcpu);
6affcbed 7071 return kvm_skip_emulated_instruction(vcpu);
ec378aee
NHE
7072}
7073
7074/*
7075 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7076 * for running VMX instructions (except VMXON, whose prerequisites are
7077 * slightly different). It also specifies what exception to inject otherwise.
70f3aac9
JM
7078 * Note that many of these exceptions have priority over VM exits, so they
7079 * don't have to be checked again here.
ec378aee
NHE
7080 */
7081static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7082{
70f3aac9 7083 if (!to_vmx(vcpu)->nested.vmxon) {
ec378aee
NHE
7084 kvm_queue_exception(vcpu, UD_VECTOR);
7085 return 0;
7086 }
ec378aee
NHE
7087 return 1;
7088}
7089
e7953d7f
AG
7090static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7091{
9a2a05b9
PB
7092 if (vmx->nested.current_vmptr == -1ull)
7093 return;
7094
7095 /* current_vmptr and current_vmcs12 are always set/reset together */
7096 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7097 return;
7098
012f83cb 7099 if (enable_shadow_vmcs) {
9a2a05b9
PB
7100 /* copy to memory all shadowed fields in case
7101 they were modified */
7102 copy_shadow_to_vmcs12(vmx);
7103 vmx->nested.sync_shadow_vmcs = false;
7ec36296
XG
7104 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7105 SECONDARY_EXEC_SHADOW_VMCS);
9a2a05b9 7106 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 7107 }
705699a1 7108 vmx->nested.posted_intr_nv = -1;
4f2777bc
DM
7109
7110 /* Flush VMCS12 to guest memory */
7111 memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7112 VMCS12_SIZE);
7113
e7953d7f
AG
7114 kunmap(vmx->nested.current_vmcs12_page);
7115 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB
7116 vmx->nested.current_vmptr = -1ull;
7117 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG
7118}
7119
ec378aee
NHE
7120/*
7121 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7122 * just stops using VMX.
7123 */
7124static void free_nested(struct vcpu_vmx *vmx)
7125{
7126 if (!vmx->nested.vmxon)
7127 return;
9a2a05b9 7128
ec378aee 7129 vmx->nested.vmxon = false;
5c614b35 7130 free_vpid(vmx->nested.vpid02);
9a2a05b9 7131 nested_release_vmcs12(vmx);
d048c098
RK
7132 if (vmx->nested.msr_bitmap) {
7133 free_page((unsigned long)vmx->nested.msr_bitmap);
7134 vmx->nested.msr_bitmap = NULL;
7135 }
355f4fb1
JM
7136 if (enable_shadow_vmcs) {
7137 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7138 free_vmcs(vmx->vmcs01.shadow_vmcs);
7139 vmx->vmcs01.shadow_vmcs = NULL;
7140 }
4f2777bc 7141 kfree(vmx->nested.cached_vmcs12);
fe3ef05c
NHE
7142 /* Unpin physical memory we referred to in current vmcs02 */
7143 if (vmx->nested.apic_access_page) {
7144 nested_release_page(vmx->nested.apic_access_page);
48d89b92 7145 vmx->nested.apic_access_page = NULL;
fe3ef05c 7146 }
a7c0b07d
WL
7147 if (vmx->nested.virtual_apic_page) {
7148 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 7149 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 7150 }
705699a1
WV
7151 if (vmx->nested.pi_desc_page) {
7152 kunmap(vmx->nested.pi_desc_page);
7153 nested_release_page(vmx->nested.pi_desc_page);
7154 vmx->nested.pi_desc_page = NULL;
7155 vmx->nested.pi_desc = NULL;
7156 }
ff2f6fe9
NHE
7157
7158 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE
7159}
7160
7161/* Emulate the VMXOFF instruction */
7162static int handle_vmoff(struct kvm_vcpu *vcpu)
7163{
7164 if (!nested_vmx_check_permission(vcpu))
7165 return 1;
7166 free_nested(to_vmx(vcpu));
a25eb114 7167 nested_vmx_succeed(vcpu);
6affcbed 7168 return kvm_skip_emulated_instruction(vcpu);
ec378aee
NHE
7169}
7170
27d6c865
NHE
7171/* Emulate the VMCLEAR instruction */
7172static int handle_vmclear(struct kvm_vcpu *vcpu)
7173{
7174 struct vcpu_vmx *vmx = to_vmx(vcpu);
587d7e72 7175 u32 zero = 0;
27d6c865 7176 gpa_t vmptr;
27d6c865
NHE
7177
7178 if (!nested_vmx_check_permission(vcpu))
7179 return 1;
7180
cbf71279 7181 if (nested_vmx_get_vmptr(vcpu, &vmptr))
27d6c865 7182 return 1;
27d6c865 7183
cbf71279
RK
7184 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7185 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7186 return kvm_skip_emulated_instruction(vcpu);
7187 }
7188
7189 if (vmptr == vmx->nested.vmxon_ptr) {
7190 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7191 return kvm_skip_emulated_instruction(vcpu);
7192 }
7193
9a2a05b9 7194 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 7195 nested_release_vmcs12(vmx);
27d6c865 7196
587d7e72
JM
7197 kvm_vcpu_write_guest(vcpu,
7198 vmptr + offsetof(struct vmcs12, launch_state),
7199 &zero, sizeof(zero));
27d6c865
NHE
7200
7201 nested_free_vmcs02(vmx, vmptr);
7202
27d6c865 7203 nested_vmx_succeed(vcpu);
6affcbed 7204 return kvm_skip_emulated_instruction(vcpu);
27d6c865
NHE
7205}
7206
cd232ad0
NHE
7207static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7208
7209/* Emulate the VMLAUNCH instruction */
7210static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7211{
7212 return nested_vmx_run(vcpu, true);
7213}
7214
7215/* Emulate the VMRESUME instruction */
7216static int handle_vmresume(struct kvm_vcpu *vcpu)
7217{
7218
7219 return nested_vmx_run(vcpu, false);
7220}
7221
49f705c5
NHE
7222enum vmcs_field_type {
7223 VMCS_FIELD_TYPE_U16 = 0,
7224 VMCS_FIELD_TYPE_U64 = 1,
7225 VMCS_FIELD_TYPE_U32 = 2,
7226 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7227};
7228
7229static inline int vmcs_field_type(unsigned long field)
7230{
7231 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
7232 return VMCS_FIELD_TYPE_U32;
7233 return (field >> 13) & 0x3 ;
7234}
7235
7236static inline int vmcs_field_readonly(unsigned long field)
7237{
7238 return (((field >> 10) & 0x3) == 1);
7239}
7240
7241/*
7242 * Read a vmcs12 field. Since these can have varying lengths and we return
7243 * one type, we chose the biggest type (u64) and zero-extend the return value
7244 * to that size. Note that the caller, handle_vmread, might need to use only
7245 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7246 * 64-bit fields are to be returned).
7247 */
a2ae9df7
PB
7248static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7249 unsigned long field, u64 *ret)
49f705c5
NHE
7250{
7251 short offset = vmcs_field_to_offset(field);
7252 char *p;
7253
7254 if (offset < 0)
a2ae9df7 7255 return offset;
49f705c5
NHE
7256
7257 p = ((char *)(get_vmcs12(vcpu))) + offset;
7258
7259 switch (vmcs_field_type(field)) {
7260 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7261 *ret = *((natural_width *)p);
a2ae9df7 7262 return 0;
49f705c5
NHE
7263 case VMCS_FIELD_TYPE_U16:
7264 *ret = *((u16 *)p);
a2ae9df7 7265 return 0;
49f705c5
NHE
7266 case VMCS_FIELD_TYPE_U32:
7267 *ret = *((u32 *)p);
a2ae9df7 7268 return 0;
49f705c5
NHE
7269 case VMCS_FIELD_TYPE_U64:
7270 *ret = *((u64 *)p);
a2ae9df7 7271 return 0;
49f705c5 7272 default:
a2ae9df7
PB
7273 WARN_ON(1);
7274 return -ENOENT;
49f705c5
NHE
7275 }
7276}
7277
20b97fea 7278
a2ae9df7
PB
7279static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7280 unsigned long field, u64 field_value){
20b97fea
AG
7281 short offset = vmcs_field_to_offset(field);
7282 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7283 if (offset < 0)
a2ae9df7 7284 return offset;
20b97fea
AG
7285
7286 switch (vmcs_field_type(field)) {
7287 case VMCS_FIELD_TYPE_U16:
7288 *(u16 *)p = field_value;
a2ae9df7 7289 return 0;
20b97fea
AG
7290 case VMCS_FIELD_TYPE_U32:
7291 *(u32 *)p = field_value;
a2ae9df7 7292 return 0;
20b97fea
AG
7293 case VMCS_FIELD_TYPE_U64:
7294 *(u64 *)p = field_value;
a2ae9df7 7295 return 0;
20b97fea
AG
7296 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7297 *(natural_width *)p = field_value;
a2ae9df7 7298 return 0;
20b97fea 7299 default:
a2ae9df7
PB
7300 WARN_ON(1);
7301 return -ENOENT;
20b97fea
AG
7302 }
7303
7304}
7305
16f5b903
AG
7306static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7307{
7308 int i;
7309 unsigned long field;
7310 u64 field_value;
355f4fb1 7311 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
c2bae893
MK
7312 const unsigned long *fields = shadow_read_write_fields;
7313 const int num_fields = max_shadow_read_write_fields;
16f5b903 7314
282da870
JK
7315 preempt_disable();
7316
16f5b903
AG
7317 vmcs_load(shadow_vmcs);
7318
7319 for (i = 0; i < num_fields; i++) {
7320 field = fields[i];
7321 switch (vmcs_field_type(field)) {
7322 case VMCS_FIELD_TYPE_U16:
7323 field_value = vmcs_read16(field);
7324 break;
7325 case VMCS_FIELD_TYPE_U32:
7326 field_value = vmcs_read32(field);
7327 break;
7328 case VMCS_FIELD_TYPE_U64:
7329 field_value = vmcs_read64(field);
7330 break;
7331 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7332 field_value = vmcs_readl(field);
7333 break;
a2ae9df7
PB
7334 default:
7335 WARN_ON(1);
7336 continue;
16f5b903
AG
7337 }
7338 vmcs12_write_any(&vmx->vcpu, field, field_value);
7339 }
7340
7341 vmcs_clear(shadow_vmcs);
7342 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK
7343
7344 preempt_enable();
16f5b903
AG
7345}
7346
c3114420
AG
7347static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7348{
c2bae893
MK
7349 const unsigned long *fields[] = {
7350 shadow_read_write_fields,
7351 shadow_read_only_fields
c3114420 7352 };
c2bae893 7353 const int max_fields[] = {
c3114420
AG
7354 max_shadow_read_write_fields,
7355 max_shadow_read_only_fields
7356 };
7357 int i, q;
7358 unsigned long field;
7359 u64 field_value = 0;
355f4fb1 7360 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
c3114420
AG
7361
7362 vmcs_load(shadow_vmcs);
7363
c2bae893 7364 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG
7365 for (i = 0; i < max_fields[q]; i++) {
7366 field = fields[q][i];
7367 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7368
7369 switch (vmcs_field_type(field)) {
7370 case VMCS_FIELD_TYPE_U16:
7371 vmcs_write16(field, (u16)field_value);
7372 break;
7373 case VMCS_FIELD_TYPE_U32:
7374 vmcs_write32(field, (u32)field_value);
7375 break;
7376 case VMCS_FIELD_TYPE_U64:
7377 vmcs_write64(field, (u64)field_value);
7378 break;
7379 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7380 vmcs_writel(field, (long)field_value);
7381 break;
a2ae9df7
PB
7382 default:
7383 WARN_ON(1);
7384 break;
c3114420
AG
7385 }
7386 }
7387 }
7388
7389 vmcs_clear(shadow_vmcs);
7390 vmcs_load(vmx->loaded_vmcs->vmcs);
7391}
7392
49f705c5
NHE
7393/*
7394 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7395 * used before) all generate the same failure when it is missing.
7396 */
7397static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7398{
7399 struct vcpu_vmx *vmx = to_vmx(vcpu);
7400 if (vmx->nested.current_vmptr == -1ull) {
7401 nested_vmx_failInvalid(vcpu);
49f705c5
NHE
7402 return 0;
7403 }
7404 return 1;
7405}
7406
7407static int handle_vmread(struct kvm_vcpu *vcpu)
7408{
7409 unsigned long field;
7410 u64 field_value;
7411 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7412 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7413 gva_t gva = 0;
7414
eb277562 7415 if (!nested_vmx_check_permission(vcpu))
49f705c5
NHE
7416 return 1;
7417
6affcbed
KH
7418 if (!nested_vmx_check_vmcs12(vcpu))
7419 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7420
7421 /* Decode instruction info and find the field to read */
27e6fb5d 7422 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 7423 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 7424 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5 7425 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6affcbed 7426 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7427 }
7428 /*
7429 * Now copy part of this value to register or memory, as requested.
7430 * Note that the number of bits actually copied is 32 or 64 depending
7431 * on the guest's mode (32 or 64 bit), not on the given field's length.
7432 */
7433 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 7434 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE
7435 field_value);
7436 } else {
7437 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7438 vmx_instruction_info, true, &gva))
49f705c5 7439 return 1;
70f3aac9 7440 /* _system ok, as hardware has verified cpl=0 */
49f705c5
NHE
7441 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7442 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7443 }
7444
7445 nested_vmx_succeed(vcpu);
6affcbed 7446 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7447}
7448
7449
7450static int handle_vmwrite(struct kvm_vcpu *vcpu)
7451{
7452 unsigned long field;
7453 gva_t gva;
7454 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7455 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE
7456 /* The value to write might be 32 or 64 bits, depending on L1's long
7457 * mode, and eventually we need to write that into a field of several
7458 * possible lengths. The code below first zero-extends the value to 64
6a6256f9 7459 * bit (field_value), and then copies only the appropriate number of
49f705c5
NHE
7460 * bits into the vmcs12 field.
7461 */
7462 u64 field_value = 0;
7463 struct x86_exception e;
7464
eb277562 7465 if (!nested_vmx_check_permission(vcpu))
49f705c5
NHE
7466 return 1;
7467
6affcbed
KH
7468 if (!nested_vmx_check_vmcs12(vcpu))
7469 return kvm_skip_emulated_instruction(vcpu);
eb277562 7470
49f705c5 7471 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7472 field_value = kvm_register_readl(vcpu,
49f705c5
NHE
7473 (((vmx_instruction_info) >> 3) & 0xf));
7474 else {
7475 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7476 vmx_instruction_info, false, &gva))
49f705c5
NHE
7477 return 1;
7478 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7479 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE
7480 kvm_inject_page_fault(vcpu, &e);
7481 return 1;
7482 }
7483 }
7484
7485
27e6fb5d 7486 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE
7487 if (vmcs_field_readonly(field)) {
7488 nested_vmx_failValid(vcpu,
7489 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6affcbed 7490 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7491 }
7492
a2ae9df7 7493 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5 7494 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6affcbed 7495 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7496 }
7497
7498 nested_vmx_succeed(vcpu);
6affcbed 7499 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7500}
7501
a8bc284e
JM
7502static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7503{
7504 vmx->nested.current_vmptr = vmptr;
7505 if (enable_shadow_vmcs) {
7506 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7507 SECONDARY_EXEC_SHADOW_VMCS);
7508 vmcs_write64(VMCS_LINK_POINTER,
7509 __pa(vmx->vmcs01.shadow_vmcs));
7510 vmx->nested.sync_shadow_vmcs = true;
7511 }
7512}
7513
63846663
NHE
7514/* Emulate the VMPTRLD instruction */
7515static int handle_vmptrld(struct kvm_vcpu *vcpu)
7516{
7517 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7518 gpa_t vmptr;
63846663
NHE
7519
7520 if (!nested_vmx_check_permission(vcpu))
7521 return 1;
7522
cbf71279 7523 if (nested_vmx_get_vmptr(vcpu, &vmptr))
63846663 7524 return 1;
63846663 7525
cbf71279
RK
7526 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7527 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7528 return kvm_skip_emulated_instruction(vcpu);
7529 }
7530
7531 if (vmptr == vmx->nested.vmxon_ptr) {
7532 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7533 return kvm_skip_emulated_instruction(vcpu);
7534 }
7535
63846663
NHE
7536 if (vmx->nested.current_vmptr != vmptr) {
7537 struct vmcs12 *new_vmcs12;
7538 struct page *page;
7539 page = nested_get_page(vcpu, vmptr);
7540 if (page == NULL) {
7541 nested_vmx_failInvalid(vcpu);
6affcbed 7542 return kvm_skip_emulated_instruction(vcpu);
63846663
NHE
7543 }
7544 new_vmcs12 = kmap(page);
7545 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7546 kunmap(page);
7547 nested_release_page_clean(page);
7548 nested_vmx_failValid(vcpu,
7549 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6affcbed 7550 return kvm_skip_emulated_instruction(vcpu);
63846663 7551 }
63846663 7552
9a2a05b9 7553 nested_release_vmcs12(vmx);
63846663
NHE
7554 vmx->nested.current_vmcs12 = new_vmcs12;
7555 vmx->nested.current_vmcs12_page = page;
4f2777bc
DM
7556 /*
7557 * Load VMCS12 from guest memory since it is not already
7558 * cached.
7559 */
7560 memcpy(vmx->nested.cached_vmcs12,
7561 vmx->nested.current_vmcs12, VMCS12_SIZE);
a8bc284e 7562 set_current_vmptr(vmx, vmptr);
63846663
NHE
7563 }
7564
7565 nested_vmx_succeed(vcpu);
6affcbed 7566 return kvm_skip_emulated_instruction(vcpu);
63846663
NHE
7567}
7568
6a4d7550
NHE
7569/* Emulate the VMPTRST instruction */
7570static int handle_vmptrst(struct kvm_vcpu *vcpu)
7571{
7572 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7573 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7574 gva_t vmcs_gva;
7575 struct x86_exception e;
7576
7577 if (!nested_vmx_check_permission(vcpu))
7578 return 1;
7579
7580 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7581 vmx_instruction_info, true, &vmcs_gva))
6a4d7550 7582 return 1;
70f3aac9 7583 /* ok to use *_system, as hardware has verified cpl=0 */
6a4d7550
NHE
7584 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7585 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7586 sizeof(u64), &e)) {
7587 kvm_inject_page_fault(vcpu, &e);
7588 return 1;
7589 }
7590 nested_vmx_succeed(vcpu);
6affcbed 7591 return kvm_skip_emulated_instruction(vcpu);
6a4d7550
NHE
7592}
7593
bfd0a56b
NHE
7594/* Emulate the INVEPT instruction */
7595static int handle_invept(struct kvm_vcpu *vcpu)
7596{
b9c237bb 7597 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE
7598 u32 vmx_instruction_info, types;
7599 unsigned long type;
7600 gva_t gva;
7601 struct x86_exception e;
7602 struct {
7603 u64 eptp, gpa;
7604 } operand;
bfd0a56b 7605
b9c237bb
WV
7606 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7607 SECONDARY_EXEC_ENABLE_EPT) ||
7608 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE
7609 kvm_queue_exception(vcpu, UD_VECTOR);
7610 return 1;
7611 }
7612
7613 if (!nested_vmx_check_permission(vcpu))
7614 return 1;
7615
bfd0a56b 7616 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7617 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7618
b9c237bb 7619 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b 7620
85c856b3 7621 if (type >= 32 || !(types & (1 << type))) {
bfd0a56b
NHE
7622 nested_vmx_failValid(vcpu,
7623 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7624 return kvm_skip_emulated_instruction(vcpu);
bfd0a56b
NHE
7625 }
7626
7627 /* According to the Intel VMX instruction reference, the memory
7628 * operand is read even if it isn't needed (e.g., for type==global)
7629 */
7630 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7631 vmx_instruction_info, false, &gva))
bfd0a56b
NHE
7632 return 1;
7633 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7634 sizeof(operand), &e)) {
7635 kvm_inject_page_fault(vcpu, &e);
7636 return 1;
7637 }
7638
7639 switch (type) {
bfd0a56b 7640 case VMX_EPT_EXTENT_GLOBAL:
45e11817
BD
7641 /*
7642 * TODO: track mappings and invalidate
7643 * single context requests appropriately
7644 */
7645 case VMX_EPT_EXTENT_CONTEXT:
bfd0a56b 7646 kvm_mmu_sync_roots(vcpu);
77c3913b 7647 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE
7648 nested_vmx_succeed(vcpu);
7649 break;
7650 default:
7651 BUG_ON(1);
7652 break;
7653 }
7654
6affcbed 7655 return kvm_skip_emulated_instruction(vcpu);
bfd0a56b
NHE
7656}
7657
a642fc30
PM
7658static int handle_invvpid(struct kvm_vcpu *vcpu)
7659{
99b83ac8
WL
7660 struct vcpu_vmx *vmx = to_vmx(vcpu);
7661 u32 vmx_instruction_info;
7662 unsigned long type, types;
7663 gva_t gva;
7664 struct x86_exception e;
40352605
JM
7665 struct {
7666 u64 vpid;
7667 u64 gla;
7668 } operand;
99b83ac8
WL
7669
7670 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7671 SECONDARY_EXEC_ENABLE_VPID) ||
7672 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7673 kvm_queue_exception(vcpu, UD_VECTOR);
7674 return 1;
7675 }
7676
7677 if (!nested_vmx_check_permission(vcpu))
7678 return 1;
7679
7680 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7681 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7682
bcdde302
JD
7683 types = (vmx->nested.nested_vmx_vpid_caps &
7684 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
99b83ac8 7685
85c856b3 7686 if (type >= 32 || !(types & (1 << type))) {
99b83ac8
WL
7687 nested_vmx_failValid(vcpu,
7688 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7689 return kvm_skip_emulated_instruction(vcpu);
99b83ac8
WL
7690 }
7691
7692 /* according to the intel vmx instruction reference, the memory
7693 * operand is read even if it isn't needed (e.g., for type==global)
7694 */
7695 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7696 vmx_instruction_info, false, &gva))
7697 return 1;
40352605
JM
7698 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7699 sizeof(operand), &e)) {
99b83ac8
WL
7700 kvm_inject_page_fault(vcpu, &e);
7701 return 1;
7702 }
40352605
JM
7703 if (operand.vpid >> 16) {
7704 nested_vmx_failValid(vcpu,
7705 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7706 return kvm_skip_emulated_instruction(vcpu);
7707 }
99b83ac8
WL
7708
7709 switch (type) {
bcdde302 7710 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
40352605
JM
7711 if (is_noncanonical_address(operand.gla)) {
7712 nested_vmx_failValid(vcpu,
7713 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7714 return kvm_skip_emulated_instruction(vcpu);
7715 }
7716 /* fall through */
ef697a71 7717 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
bcdde302 7718 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
40352605 7719 if (!operand.vpid) {
bcdde302
JD
7720 nested_vmx_failValid(vcpu,
7721 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7722 return kvm_skip_emulated_instruction(vcpu);
bcdde302
JD
7723 }
7724 break;
99b83ac8 7725 case VMX_VPID_EXTENT_ALL_CONTEXT:
99b83ac8
WL
7726 break;
7727 default:
bcdde302 7728 WARN_ON_ONCE(1);
6affcbed 7729 return kvm_skip_emulated_instruction(vcpu);
99b83ac8
WL
7730 }
7731
bcdde302
JD
7732 __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7733 nested_vmx_succeed(vcpu);
7734
6affcbed 7735 return kvm_skip_emulated_instruction(vcpu);
a642fc30
PM
7736}
7737
843e4330
KH
7738static int handle_pml_full(struct kvm_vcpu *vcpu)
7739{
7740 unsigned long exit_qualification;
7741
7742 trace_kvm_pml_full(vcpu->vcpu_id);
7743
7744 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7745
7746 /*
7747 * PML buffer FULL happened while executing iret from NMI,
7748 * "blocked by NMI" bit has to be set before next VM entry.
7749 */
7750 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
843e4330
KH
7751 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7752 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7753 GUEST_INTR_STATE_NMI);
7754
7755 /*
7756 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7757 * here.., and there's no userspace involvement needed for PML.
7758 */
7759 return 1;
7760}
7761
64672c95
YJ
7762static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7763{
7764 kvm_lapic_expired_hv_timer(vcpu);
7765 return 1;
7766}
7767
6aa8b732
AK
7768/*
7769 * The exit handlers return 1 if the exit was handled fully and guest execution
7770 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7771 * to be done to userspace and return 0.
7772 */
772e0318 7773static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK
7774 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7775 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7776 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7777 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7778 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK
7779 [EXIT_REASON_CR_ACCESS] = handle_cr,
7780 [EXIT_REASON_DR_ACCESS] = handle_dr,
7781 [EXIT_REASON_CPUID] = handle_cpuid,
7782 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7783 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7784 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7785 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7786 [EXIT_REASON_INVD] = handle_invd,
a7052897 7787 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7788 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7789 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7790 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7791 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7792 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7793 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7794 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7795 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7796 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE
7797 [EXIT_REASON_VMOFF] = handle_vmoff,
7798 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY
7799 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7800 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7801 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7802 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7803 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7804 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7805 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7806 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT
7807 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7808 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7809 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7810 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7811 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7812 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7813 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7814 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL
7815 [EXIT_REASON_XSAVES] = handle_xsaves,
7816 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7817 [EXIT_REASON_PML_FULL] = handle_pml_full,
64672c95 7818 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
6aa8b732
AK
7819};
7820
7821static const int kvm_vmx_max_exit_handlers =
50a3485c 7822 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7823
908a7bdd
JK
7824static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7825 struct vmcs12 *vmcs12)
7826{
7827 unsigned long exit_qualification;
7828 gpa_t bitmap, last_bitmap;
7829 unsigned int port;
7830 int size;
7831 u8 b;
7832
908a7bdd 7833 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7834 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK
7835
7836 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7837
7838 port = exit_qualification >> 16;
7839 size = (exit_qualification & 7) + 1;
7840
7841 last_bitmap = (gpa_t)-1;
7842 b = -1;
7843
7844 while (size > 0) {
7845 if (port < 0x8000)
7846 bitmap = vmcs12->io_bitmap_a;
7847 else if (port < 0x10000)
7848 bitmap = vmcs12->io_bitmap_b;
7849 else
1d804d07 7850 return true;
908a7bdd
JK
7851 bitmap += (port & 0x7fff) / 8;
7852
7853 if (last_bitmap != bitmap)
54bf36aa 7854 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7855 return true;
908a7bdd 7856 if (b & (1 << (port & 7)))
1d804d07 7857 return true;
908a7bdd
JK
7858
7859 port++;
7860 size--;
7861 last_bitmap = bitmap;
7862 }
7863
1d804d07 7864 return false;
908a7bdd
JK
7865}
7866
644d711a
NHE
7867/*
7868 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7869 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7870 * disinterest in the current event (read or write a specific MSR) by using an
7871 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7872 */
7873static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7874 struct vmcs12 *vmcs12, u32 exit_reason)
7875{
7876 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7877 gpa_t bitmap;
7878
cbd29cb6 7879 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7880 return true;
644d711a
NHE
7881
7882 /*
7883 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7884 * for the four combinations of read/write and low/high MSR numbers.
7885 * First we need to figure out which of the four to use:
7886 */
7887 bitmap = vmcs12->msr_bitmap;
7888 if (exit_reason == EXIT_REASON_MSR_WRITE)
7889 bitmap += 2048;
7890 if (msr_index >= 0xc0000000) {
7891 msr_index -= 0xc0000000;
7892 bitmap += 1024;
7893 }
7894
7895 /* Then read the msr_index'th bit from this bitmap: */
7896 if (msr_index < 1024*8) {
7897 unsigned char b;
54bf36aa 7898 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7899 return true;
644d711a
NHE
7900 return 1 & (b >> (msr_index & 7));
7901 } else
1d804d07 7902 return true; /* let L1 handle the wrong parameter */
644d711a
NHE
7903}
7904
7905/*
7906 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7907 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7908 * intercept (via guest_host_mask etc.) the current event.
7909 */
7910static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7911 struct vmcs12 *vmcs12)
7912{
7913 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7914 int cr = exit_qualification & 15;
e1d39b17
JS
7915 int reg;
7916 unsigned long val;
644d711a
NHE
7917
7918 switch ((exit_qualification >> 4) & 3) {
7919 case 0: /* mov to cr */
e1d39b17
JS
7920 reg = (exit_qualification >> 8) & 15;
7921 val = kvm_register_readl(vcpu, reg);
644d711a
NHE
7922 switch (cr) {
7923 case 0:
7924 if (vmcs12->cr0_guest_host_mask &
7925 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7926 return true;
644d711a
NHE
7927 break;
7928 case 3:
7929 if ((vmcs12->cr3_target_count >= 1 &&
7930 vmcs12->cr3_target_value0 == val) ||
7931 (vmcs12->cr3_target_count >= 2 &&
7932 vmcs12->cr3_target_value1 == val) ||
7933 (vmcs12->cr3_target_count >= 3 &&
7934 vmcs12->cr3_target_value2 == val) ||
7935 (vmcs12->cr3_target_count >= 4 &&
7936 vmcs12->cr3_target_value3 == val))
1d804d07 7937 return false;
644d711a 7938 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7939 return true;
644d711a
NHE
7940 break;
7941 case 4:
7942 if (vmcs12->cr4_guest_host_mask &
7943 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7944 return true;
644d711a
NHE
7945 break;
7946 case 8:
7947 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7948 return true;
644d711a
NHE
7949 break;
7950 }
7951 break;
7952 case 2: /* clts */
7953 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7954 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7955 return true;
644d711a
NHE
7956 break;
7957 case 1: /* mov from cr */
7958 switch (cr) {
7959 case 3:
7960 if (vmcs12->cpu_based_vm_exec_control &
7961 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7962 return true;
644d711a
NHE
7963 break;
7964 case 8:
7965 if (vmcs12->cpu_based_vm_exec_control &
7966 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7967 return true;
644d711a
NHE
7968 break;
7969 }
7970 break;
7971 case 3: /* lmsw */
7972 /*
7973 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7974 * cr0. Other attempted changes are ignored, with no exit.
7975 */
e1d39b17 7976 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
644d711a
NHE
7977 if (vmcs12->cr0_guest_host_mask & 0xe &
7978 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7979 return true;
644d711a
NHE
7980 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7981 !(vmcs12->cr0_read_shadow & 0x1) &&
7982 (val & 0x1))
1d804d07 7983 return true;
644d711a
NHE
7984 break;
7985 }
1d804d07 7986 return false;
644d711a
NHE
7987}
7988
7989/*
7990 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7991 * should handle it ourselves in L0 (and then continue L2). Only call this
7992 * when in is_guest_mode (L2).
7993 */
7994static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7995{
644d711a
NHE
7996 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7997 struct vcpu_vmx *vmx = to_vmx(vcpu);
7998 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7999 u32 exit_reason = vmx->exit_reason;
644d711a 8000
542060ea
JK
8001 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8002 vmcs_readl(EXIT_QUALIFICATION),
8003 vmx->idt_vectoring_info,
8004 intr_info,
8005 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8006 KVM_ISA_VMX);
8007
644d711a 8008 if (vmx->nested.nested_run_pending)
1d804d07 8009 return false;
644d711a
NHE
8010
8011 if (unlikely(vmx->fail)) {
bd80158a
JK
8012 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8013 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 8014 return true;
644d711a
NHE
8015 }
8016
8017 switch (exit_reason) {
8018 case EXIT_REASON_EXCEPTION_NMI:
ef85b673 8019 if (is_nmi(intr_info))
1d804d07 8020 return false;
644d711a
NHE
8021 else if (is_page_fault(intr_info))
8022 return enable_ept;
e504c909 8023 else if (is_no_device(intr_info) &&
ccf9844e 8024 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 8025 return false;
6f05485d
JK
8026 else if (is_debug(intr_info) &&
8027 vcpu->guest_debug &
8028 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8029 return false;
8030 else if (is_breakpoint(intr_info) &&
8031 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8032 return false;
644d711a
NHE
8033 return vmcs12->exception_bitmap &
8034 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8035 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 8036 return false;
644d711a 8037 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 8038 return true;
644d711a 8039 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 8040 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 8041 case EXIT_REASON_NMI_WINDOW:
3b656cf7 8042 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 8043 case EXIT_REASON_TASK_SWITCH:
1d804d07 8044 return true;
644d711a 8045 case EXIT_REASON_CPUID:
1d804d07 8046 return true;
644d711a
NHE
8047 case EXIT_REASON_HLT:
8048 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8049 case EXIT_REASON_INVD:
1d804d07 8050 return true;
644d711a
NHE
8051 case EXIT_REASON_INVLPG:
8052 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8053 case EXIT_REASON_RDPMC:
8054 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
a5f46457
PB
8055 case EXIT_REASON_RDRAND:
8056 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8057 case EXIT_REASON_RDSEED:
8058 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
b3a2a907 8059 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE
8060 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8061 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8062 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8063 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8064 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8065 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 8066 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE
8067 /*
8068 * VMX instructions trap unconditionally. This allows L1 to
8069 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8070 */
1d804d07 8071 return true;
644d711a
NHE
8072 case EXIT_REASON_CR_ACCESS:
8073 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8074 case EXIT_REASON_DR_ACCESS:
8075 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8076 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 8077 return nested_vmx_exit_handled_io(vcpu, vmcs12);
1b07304c
PB
8078 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8079 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
644d711a
NHE
8080 case EXIT_REASON_MSR_READ:
8081 case EXIT_REASON_MSR_WRITE:
8082 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8083 case EXIT_REASON_INVALID_STATE:
1d804d07 8084 return true;
644d711a
NHE
8085 case EXIT_REASON_MWAIT_INSTRUCTION:
8086 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD
8087 case EXIT_REASON_MONITOR_TRAP_FLAG:
8088 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE
8089 case EXIT_REASON_MONITOR_INSTRUCTION:
8090 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8091 case EXIT_REASON_PAUSE_INSTRUCTION:
8092 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8093 nested_cpu_has2(vmcs12,
8094 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8095 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 8096 return false;
644d711a 8097 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 8098 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE
8099 case EXIT_REASON_APIC_ACCESS:
8100 return nested_cpu_has2(vmcs12,
8101 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 8102 case EXIT_REASON_APIC_WRITE:
608406e2
WV
8103 case EXIT_REASON_EOI_INDUCED:
8104 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 8105 return true;
644d711a 8106 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE
8107 /*
8108 * L0 always deals with the EPT violation. If nested EPT is
8109 * used, and the nested mmu code discovers that the address is
8110 * missing in the guest EPT table (EPT12), the EPT violation
8111 * will be injected with nested_ept_inject_page_fault()
8112 */
1d804d07 8113 return false;
644d711a 8114 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE
8115 /*
8116 * L2 never uses directly L1's EPT, but rather L0's own EPT
8117 * table (shadow on EPT) or a merged EPT table that L0 built
8118 * (EPT on EPT). So any problems with the structure of the
8119 * table is L0's fault.
8120 */
1d804d07 8121 return false;
644d711a
NHE
8122 case EXIT_REASON_WBINVD:
8123 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8124 case EXIT_REASON_XSETBV:
1d804d07 8125 return true;
81dc01f7
WL
8126 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8127 /*
8128 * This should never happen, since it is not possible to
8129 * set XSS to a non-zero value---neither in L1 nor in L2.
8130 * If if it were, XSS would have to be checked against
8131 * the XSS exit bitmap in vmcs12.
8132 */
8133 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
55123e3c
WL
8134 case EXIT_REASON_PREEMPTION_TIMER:
8135 return false;
ab007cc9 8136 case EXIT_REASON_PML_FULL:
03efce6f 8137 /* We emulate PML support to L1. */
ab007cc9 8138 return false;
644d711a 8139 default:
1d804d07 8140 return true;
644d711a
NHE
8141 }
8142}
8143
586f9607
AK
8144static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8145{
8146 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8147 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8148}
8149
a3eaa864 8150static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
843e4330 8151{
a3eaa864
KH
8152 if (vmx->pml_pg) {
8153 __free_page(vmx->pml_pg);
8154 vmx->pml_pg = NULL;
8155 }
843e4330
KH
8156}
8157
54bf36aa 8158static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 8159{
54bf36aa 8160 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH
8161 u64 *pml_buf;
8162 u16 pml_idx;
8163
8164 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8165
8166 /* Do nothing if PML buffer is empty */
8167 if (pml_idx == (PML_ENTITY_NUM - 1))
8168 return;
8169
8170 /* PML index always points to next available PML buffer entity */
8171 if (pml_idx >= PML_ENTITY_NUM)
8172 pml_idx = 0;
8173 else
8174 pml_idx++;
8175
8176 pml_buf = page_address(vmx->pml_pg);
8177 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8178 u64 gpa;
8179
8180 gpa = pml_buf[pml_idx];
8181 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 8182 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH
8183 }
8184
8185 /* reset PML index */
8186 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8187}
8188
8189/*
8190 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8191 * Called before reporting dirty_bitmap to userspace.
8192 */
8193static void kvm_flush_pml_buffers(struct kvm *kvm)
8194{
8195 int i;
8196 struct kvm_vcpu *vcpu;
8197 /*
8198 * We only need to kick vcpu out of guest mode here, as PML buffer
8199 * is flushed at beginning of all VMEXITs, and it's obvious that only
8200 * vcpus running in guest are possible to have unflushed GPAs in PML
8201 * buffer.
8202 */
8203 kvm_for_each_vcpu(i, vcpu, kvm)
8204 kvm_vcpu_kick(vcpu);
8205}
8206
4eb64dce
PB
8207static void vmx_dump_sel(char *name, uint32_t sel)
8208{
8209 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
96794e4e 8210 name, vmcs_read16(sel),
4eb64dce
PB
8211 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8212 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8213 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8214}
8215
8216static void vmx_dump_dtsel(char *name, uint32_t limit)
8217{
8218 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8219 name, vmcs_read32(limit),
8220 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8221}
8222
8223static void dump_vmcs(void)
8224{
8225 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8226 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8227 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8228 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8229 u32 secondary_exec_control = 0;
8230 unsigned long cr4 = vmcs_readl(GUEST_CR4);
f3531054 8231 u64 efer = vmcs_read64(GUEST_IA32_EFER);
4eb64dce
PB
8232 int i, n;
8233
8234 if (cpu_has_secondary_exec_ctrls())
8235 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8236
8237 pr_err("*** Guest State ***\n");
8238 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8239 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8240 vmcs_readl(CR0_GUEST_HOST_MASK));
8241 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8242 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8243 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8244 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8245 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8246 {
845c5b40
PB
8247 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8248 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8249 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8250 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
4eb64dce
PB
8251 }
8252 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8253 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8254 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8255 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8256 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8257 vmcs_readl(GUEST_SYSENTER_ESP),
8258 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8259 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8260 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8261 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8262 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8263 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8264 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8265 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8266 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8267 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8268 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8269 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8270 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
845c5b40
PB
8271 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8272 efer, vmcs_read64(GUEST_IA32_PAT));
8273 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8274 vmcs_read64(GUEST_IA32_DEBUGCTL),
4eb64dce
PB
8275 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8276 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
845c5b40
PB
8277 pr_err("PerfGlobCtl = 0x%016llx\n",
8278 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
4eb64dce 8279 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
845c5b40 8280 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
4eb64dce
PB
8281 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8282 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8283 vmcs_read32(GUEST_ACTIVITY_STATE));
8284 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8285 pr_err("InterruptStatus = %04x\n",
8286 vmcs_read16(GUEST_INTR_STATUS));
8287
8288 pr_err("*** Host State ***\n");
8289 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8290 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8291 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8292 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8293 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8294 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8295 vmcs_read16(HOST_TR_SELECTOR));
8296 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8297 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8298 vmcs_readl(HOST_TR_BASE));
8299 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8300 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8301 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8302 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8303 vmcs_readl(HOST_CR4));
8304 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8305 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8306 vmcs_read32(HOST_IA32_SYSENTER_CS),
8307 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8308 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
845c5b40
PB
8309 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8310 vmcs_read64(HOST_IA32_EFER),
8311 vmcs_read64(HOST_IA32_PAT));
4eb64dce 8312 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
845c5b40
PB
8313 pr_err("PerfGlobCtl = 0x%016llx\n",
8314 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
4eb64dce
PB
8315
8316 pr_err("*** Control State ***\n");
8317 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8318 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8319 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8320 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8321 vmcs_read32(EXCEPTION_BITMAP),
8322 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8323 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8324 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8325 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8326 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8327 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8328 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8329 vmcs_read32(VM_EXIT_INTR_INFO),
8330 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8331 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8332 pr_err(" reason=%08x qualification=%016lx\n",
8333 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8334 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8335 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8336 vmcs_read32(IDT_VECTORING_ERROR_CODE));
845c5b40 8337 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8cfe9866 8338 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
845c5b40
PB
8339 pr_err("TSC Multiplier = 0x%016llx\n",
8340 vmcs_read64(TSC_MULTIPLIER));
4eb64dce
PB
8341 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8342 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8343 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8344 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8345 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
845c5b40 8346 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
4eb64dce
PB
8347 n = vmcs_read32(CR3_TARGET_COUNT);
8348 for (i = 0; i + 1 < n; i += 4)
8349 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8350 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8351 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8352 if (i < n)
8353 pr_err("CR3 target%u=%016lx\n",
8354 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8355 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8356 pr_err("PLE Gap=%08x Window=%08x\n",
8357 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8358 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8359 pr_err("Virtual processor ID = 0x%04x\n",
8360 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8361}
8362
6aa8b732
AK
8363/*
8364 * The guest has exited. See if we can fix it or if we need userspace
8365 * assistance.
8366 */
851ba692 8367static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 8368{
29bd8a78 8369 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 8370 u32 exit_reason = vmx->exit_reason;
1155f76a 8371 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 8372
8b89fe1f 8373 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
db1c056c 8374 vcpu->arch.gpa_available = false;
8b89fe1f 8375
843e4330
KH
8376 /*
8377 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8378 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8379 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8380 * mode as if vcpus is in root mode, the PML buffer must has been
8381 * flushed already.
8382 */
8383 if (enable_pml)
54bf36aa 8384 vmx_flush_pml_buffer(vcpu);
843e4330 8385
80ced186 8386 /* If guest state is invalid, start emulating */
14168786 8387 if (vmx->emulation_required)
80ced186 8388 return handle_invalid_guest_state(vcpu);
1d5a4d9b 8389
644d711a 8390 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK
8391 nested_vmx_vmexit(vcpu, exit_reason,
8392 vmcs_read32(VM_EXIT_INTR_INFO),
8393 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE
8394 return 1;
8395 }
8396
5120702e 8397 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 8398 dump_vmcs();
5120702e
MG
8399 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8400 vcpu->run->fail_entry.hardware_entry_failure_reason
8401 = exit_reason;
8402 return 0;
8403 }
8404
29bd8a78 8405 if (unlikely(vmx->fail)) {
851ba692
AK
8406 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8407 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK
8408 = vmcs_read32(VM_INSTRUCTION_ERROR);
8409 return 0;
8410 }
6aa8b732 8411
b9bf6882
XG
8412 /*
8413 * Note:
8414 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8415 * delivery event since it indicates guest is accessing MMIO.
8416 * The vm-exit can be triggered again after return to guest that
8417 * will cause infinite loop.
8418 */
d77c26fc 8419 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 8420 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 8421 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b244c9fc 8422 exit_reason != EXIT_REASON_PML_FULL &&
b9bf6882
XG
8423 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8424 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8425 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
70bcd708 8426 vcpu->run->internal.ndata = 3;
b9bf6882
XG
8427 vcpu->run->internal.data[0] = vectoring_info;
8428 vcpu->run->internal.data[1] = exit_reason;
70bcd708
PB
8429 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8430 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8431 vcpu->run->internal.ndata++;
8432 vcpu->run->internal.data[3] =
8433 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8434 }
b9bf6882
XG
8435 return 0;
8436 }
3b86cd99 8437
6aa8b732
AK
8438 if (exit_reason < kvm_vmx_max_exit_handlers
8439 && kvm_vmx_exit_handlers[exit_reason])
851ba692 8440 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 8441 else {
6c6c5e03
RK
8442 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8443 exit_reason);
2bc19dc3
MT
8444 kvm_queue_exception(vcpu, UD_VECTOR);
8445 return 1;
6aa8b732 8446 }
6aa8b732
AK
8447}
8448
95ba8273 8449static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 8450{
a7c0b07d
WL
8451 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8452
8453 if (is_guest_mode(vcpu) &&
8454 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8455 return;
8456
95ba8273 8457 if (irr == -1 || tpr < irr) {
6e5d865c
YS
8458 vmcs_write32(TPR_THRESHOLD, 0);
8459 return;
8460 }
8461
95ba8273 8462 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS
8463}
8464
8d14695f
YZ
8465static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8466{
8467 u32 sec_exec_control;
8468
dccbfcf5
RK
8469 /* Postpone execution until vmcs01 is the current VMCS. */
8470 if (is_guest_mode(vcpu)) {
8471 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8472 return;
8473 }
8474
f6e90f9e 8475 if (!cpu_has_vmx_virtualize_x2apic_mode())
8d14695f
YZ
8476 return;
8477
35754c98 8478 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ
8479 return;
8480
8481 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8482
8483 if (set) {
8484 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8485 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8486 } else {
8487 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8488 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
fb6c8198 8489 vmx_flush_tlb_ept_only(vcpu);
8d14695f
YZ
8490 }
8491 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8492
8493 vmx_set_msr_bitmap(vcpu);
8494}
8495
38b99173
TC
8496static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8497{
8498 struct vcpu_vmx *vmx = to_vmx(vcpu);
8499
8500 /*
8501 * Currently we do not handle the nested case where L2 has an
8502 * APIC access page of its own; that page is still pinned.
8503 * Hence, we skip the case where the VCPU is in guest mode _and_
8504 * L1 prepared an APIC access page for L2.
8505 *
8506 * For the case where L1 and L2 share the same APIC access page
8507 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8508 * in the vmcs12), this function will only update either the vmcs01
8509 * or the vmcs02. If the former, the vmcs02 will be updated by
8510 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8511 * the next L2->L1 exit.
8512 */
8513 if (!is_guest_mode(vcpu) ||
4f2777bc 8514 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
fb6c8198 8515 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
38b99173 8516 vmcs_write64(APIC_ACCESS_ADDR, hpa);
fb6c8198
JM
8517 vmx_flush_tlb_ept_only(vcpu);
8518 }
38b99173
TC
8519}
8520
67c9dddc 8521static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
c7c9c56c
YZ
8522{
8523 u16 status;
8524 u8 old;
8525
67c9dddc
PB
8526 if (max_isr == -1)
8527 max_isr = 0;
c7c9c56c
YZ
8528
8529 status = vmcs_read16(GUEST_INTR_STATUS);
8530 old = status >> 8;
67c9dddc 8531 if (max_isr != old) {
c7c9c56c 8532 status &= 0xff;
67c9dddc 8533 status |= max_isr << 8;
c7c9c56c
YZ
8534 vmcs_write16(GUEST_INTR_STATUS, status);
8535 }
8536}
8537
8538static void vmx_set_rvi(int vector)
8539{
8540 u16 status;
8541 u8 old;
8542
4114c27d
WW
8543 if (vector == -1)
8544 vector = 0;
8545
c7c9c56c
YZ
8546 status = vmcs_read16(GUEST_INTR_STATUS);
8547 old = (u8)status & 0xff;
8548 if ((u8)vector != old) {
8549 status &= ~0xff;
8550 status |= (u8)vector;
8551 vmcs_write16(GUEST_INTR_STATUS, status);
8552 }
8553}
8554
8555static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8556{
4114c27d
WW
8557 if (!is_guest_mode(vcpu)) {
8558 vmx_set_rvi(max_irr);
8559 return;
8560 }
8561
c7c9c56c
YZ
8562 if (max_irr == -1)
8563 return;
8564
963fee16 8565 /*
4114c27d
WW
8566 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8567 * handles it.
963fee16 8568 */
4114c27d 8569 if (nested_exit_on_intr(vcpu))
963fee16
WL
8570 return;
8571
963fee16 8572 /*
4114c27d 8573 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL
8574 * is run without virtual interrupt delivery.
8575 */
8576 if (!kvm_event_needs_reinjection(vcpu) &&
8577 vmx_interrupt_allowed(vcpu)) {
8578 kvm_queue_interrupt(vcpu, max_irr, false);
8579 vmx_inject_irq(vcpu);
8580 }
c7c9c56c
YZ
8581}
8582
76dfafd5 8583static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
810e6def
PB
8584{
8585 struct vcpu_vmx *vmx = to_vmx(vcpu);
76dfafd5 8586 int max_irr;
810e6def 8587
76dfafd5
PB
8588 WARN_ON(!vcpu->arch.apicv_active);
8589 if (pi_test_on(&vmx->pi_desc)) {
8590 pi_clear_on(&vmx->pi_desc);
8591 /*
8592 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8593 * But on x86 this is just a compiler barrier anyway.
8594 */
8595 smp_mb__after_atomic();
8596 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8597 } else {
8598 max_irr = kvm_lapic_find_highest_irr(vcpu);
8599 }
8600 vmx_hwapic_irr_update(vcpu, max_irr);
8601 return max_irr;
810e6def
PB
8602}
8603
6308630b 8604static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
c7c9c56c 8605{
d62caabb 8606 if (!kvm_vcpu_apicv_active(vcpu))
3d81bc7e
YZ
8607 return;
8608
c7c9c56c
YZ
8609 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8610 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8611 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8612 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8613}
8614
967235d3
PB
8615static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8616{
8617 struct vcpu_vmx *vmx = to_vmx(vcpu);
8618
8619 pi_clear_on(&vmx->pi_desc);
8620 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8621}
8622
51aa01d1 8623static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8624{
00eba012
AK
8625 u32 exit_intr_info;
8626
8627 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8628 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8629 return;
8630
c5ca8e57 8631 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 8632 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK
8633
8634 /* Handle machine checks before interrupts are enabled */
00eba012 8635 if (is_machine_check(exit_intr_info))
a0861c02
AK
8636 kvm_machine_check();
8637
20f65983 8638 /* We need to handle NMIs before interrupts are enabled */
ef85b673 8639 if (is_nmi(exit_intr_info)) {
ff9d07a0 8640 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8641 asm("int $2");
ff9d07a0
ZY
8642 kvm_after_handle_nmi(&vmx->vcpu);
8643 }
51aa01d1 8644}
20f65983 8645
a547c6db
YZ
8646static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8647{
8648 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3f62de5f 8649 register void *__sp asm(_ASM_SP);
a547c6db 8650
a547c6db
YZ
8651 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8652 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8653 unsigned int vector;
8654 unsigned long entry;
8655 gate_desc *desc;
8656 struct vcpu_vmx *vmx = to_vmx(vcpu);
8657#ifdef CONFIG_X86_64
8658 unsigned long tmp;
8659#endif
8660
8661 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8662 desc = (gate_desc *)vmx->host_idt_base + vector;
8663 entry = gate_offset(*desc);
8664 asm volatile(
8665#ifdef CONFIG_X86_64
8666 "mov %%" _ASM_SP ", %[sp]\n\t"
8667 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8668 "push $%c[ss]\n\t"
8669 "push %[sp]\n\t"
8670#endif
8671 "pushf\n\t"
a547c6db
YZ
8672 __ASM_SIZE(push) " $%c[cs]\n\t"
8673 "call *%[entry]\n\t"
8674 :
8675#ifdef CONFIG_X86_64
3f62de5f 8676 [sp]"=&r"(tmp),
a547c6db 8677#endif
3f62de5f 8678 "+r"(__sp)
a547c6db
YZ
8679 :
8680 [entry]"r"(entry),
8681 [ss]"i"(__KERNEL_DS),
8682 [cs]"i"(__KERNEL_CS)
8683 );
f2485b3e 8684 }
a547c6db 8685}
c207aee4 8686STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
a547c6db 8687
6d396b55
PB
8688static bool vmx_has_high_real_mode_segbase(void)
8689{
8690 return enable_unrestricted_guest || emulate_invalid_guest_state;
8691}
8692
da8999d3
LJ
8693static bool vmx_mpx_supported(void)
8694{
8695 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8696 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8697}
8698
55412b2e
WL
8699static bool vmx_xsaves_supported(void)
8700{
8701 return vmcs_config.cpu_based_2nd_exec_ctrl &
8702 SECONDARY_EXEC_XSAVES;
8703}
8704
51aa01d1
AK
8705static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8706{
c5ca8e57 8707 u32 exit_intr_info;
51aa01d1
AK
8708 bool unblock_nmi;
8709 u8 vector;
8710 bool idtv_info_valid;
8711
8712 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8713
2c82878b
PB
8714 if (vmx->nmi_known_unmasked)
8715 return;
8716 /*
8717 * Can't use vmx->exit_intr_info since we're not sure what
8718 * the exit reason is.
8719 */
8720 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8721 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8722 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8723 /*
8724 * SDM 3: 27.7.1.2 (September 2008)
8725 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8726 * a guest IRET fault.
8727 * SDM 3: 23.2.2 (September 2008)
8728 * Bit 12 is undefined in any of the following cases:
8729 * If the VM exit sets the valid bit in the IDT-vectoring
8730 * information field.
8731 * If the VM exit is due to a double fault.
8732 */
8733 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8734 vector != DF_VECTOR && !idtv_info_valid)
8735 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8736 GUEST_INTR_STATE_NMI);
8737 else
8738 vmx->nmi_known_unmasked =
8739 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8740 & GUEST_INTR_STATE_NMI);
51aa01d1
AK
8741}
8742
3ab66e8a 8743static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK
8744 u32 idt_vectoring_info,
8745 int instr_len_field,
8746 int error_code_field)
51aa01d1 8747{
51aa01d1
AK
8748 u8 vector;
8749 int type;
8750 bool idtv_info_valid;
8751
8752 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8753
3ab66e8a
JK
8754 vcpu->arch.nmi_injected = false;
8755 kvm_clear_exception_queue(vcpu);
8756 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN
8757
8758 if (!idtv_info_valid)
8759 return;
8760
3ab66e8a 8761 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8762
668f612f
AK
8763 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8764 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8765
64a7ec06 8766 switch (type) {
37b96e98 8767 case INTR_TYPE_NMI_INTR:
3ab66e8a 8768 vcpu->arch.nmi_injected = true;
668f612f 8769 /*
7b4a25cb 8770 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN
8771 * Clear bit "block by NMI" before VM entry if a NMI
8772 * delivery faulted.
668f612f 8773 */
3ab66e8a 8774 vmx_set_nmi_mask(vcpu, false);
37b96e98 8775 break;
37b96e98 8776 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8777 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN
8778 /* fall through */
8779 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8780 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8781 u32 err = vmcs_read32(error_code_field);
851eb667 8782 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8783 } else
851eb667 8784 kvm_requeue_exception(vcpu, vector);
37b96e98 8785 break;
66fd3f7f 8786 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8787 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8788 /* fall through */
37b96e98 8789 case INTR_TYPE_EXT_INTR:
3ab66e8a 8790 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN
8791 break;
8792 default:
8793 break;
f7d9238f 8794 }
cf393f75
AK
8795}
8796
83422e17
AK
8797static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8798{
3ab66e8a 8799 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK
8800 VM_EXIT_INSTRUCTION_LEN,
8801 IDT_VECTORING_ERROR_CODE);
8802}
8803
b463a6f7
AK
8804static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8805{
3ab66e8a 8806 __vmx_complete_interrupts(vcpu,
b463a6f7
AK
8807 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8808 VM_ENTRY_INSTRUCTION_LEN,
8809 VM_ENTRY_EXCEPTION_ERROR_CODE);
8810
8811 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8812}
8813
d7cd9796
GN
8814static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8815{
8816 int i, nr_msrs;
8817 struct perf_guest_switch_msr *msrs;
8818
8819 msrs = perf_guest_get_msrs(&nr_msrs);
8820
8821 if (!msrs)
8822 return;
8823
8824 for (i = 0; i < nr_msrs; i++)
8825 if (msrs[i].host == msrs[i].guest)
8826 clear_atomic_switch_msr(vmx, msrs[i].msr);
8827 else
8828 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8829 msrs[i].host);
8830}
8831
33365e7a 8832static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
64672c95
YJ
8833{
8834 struct vcpu_vmx *vmx = to_vmx(vcpu);
8835 u64 tscl;
8836 u32 delta_tsc;
8837
8838 if (vmx->hv_deadline_tsc == -1)
8839 return;
8840
8841 tscl = rdtsc();
8842 if (vmx->hv_deadline_tsc > tscl)
8843 /* sure to be 32 bit only because checked on set_hv_timer */
8844 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8845 cpu_preemption_timer_multi);
8846 else
8847 delta_tsc = 0;
8848
8849 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8850}
8851
a3b5ba49 8852static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8853{
a2fa3e9f 8854 struct vcpu_vmx *vmx = to_vmx(vcpu);
d6e41f11 8855 unsigned long debugctlmsr, cr3, cr4;
104f226b 8856
104f226b
AK
8857 /* Don't enter VMX if guest state is invalid, let the exit handler
8858 start emulation until we arrive back to a valid state */
14168786 8859 if (vmx->emulation_required)
104f226b
AK
8860 return;
8861
a7653ecd
RK
8862 if (vmx->ple_window_dirty) {
8863 vmx->ple_window_dirty = false;
8864 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8865 }
8866
012f83cb
AG
8867 if (vmx->nested.sync_shadow_vmcs) {
8868 copy_vmcs12_to_shadow(vmx);
8869 vmx->nested.sync_shadow_vmcs = false;
8870 }
8871
104f226b
AK
8872 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8873 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8874 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8875 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8876
d6e41f11
AL
8877 cr3 = __get_current_cr3_fast();
8878 if (unlikely(cr3 != vmx->host_state.vmcs_host_cr3)) {
8879 vmcs_writel(HOST_CR3, cr3);
8880 vmx->host_state.vmcs_host_cr3 = cr3;
8881 }
8882
1e02ce4c 8883 cr4 = cr4_read_shadow();
d974baa3
AL
8884 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8885 vmcs_writel(HOST_CR4, cr4);
8886 vmx->host_state.vmcs_host_cr4 = cr4;
8887 }
8888
104f226b
AK
8889 /* When single-stepping over STI and MOV SS, we must clear the
8890 * corresponding interruptibility bits in the guest state. Otherwise
8891 * vmentry fails as it then expects bit 14 (BS) in pending debug
8892 * exceptions being set, but that's not correct for the guest debugging
8893 * case. */
8894 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8895 vmx_set_interrupt_shadow(vcpu, 0);
8896
1be0e61c
XG
8897 if (vmx->guest_pkru_valid)
8898 __write_pkru(vmx->guest_pkru);
8899
d7cd9796 8900 atomic_switch_perf_msrs(vmx);
2a7921b7 8901 debugctlmsr = get_debugctlmsr();
d7cd9796 8902
64672c95
YJ
8903 vmx_arm_hv_timer(vcpu);
8904
d462b819 8905 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8906 asm(
6aa8b732 8907 /* Store host registers */
b188c81f
AK
8908 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8909 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8910 "push %%" _ASM_CX " \n\t"
8911 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8912 "je 1f \n\t"
b188c81f 8913 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8914 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8915 "1: \n\t"
d3edefc0 8916 /* Reload cr2 if changed */
b188c81f
AK
8917 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8918 "mov %%cr2, %%" _ASM_DX " \n\t"
8919 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8920 "je 2f \n\t"
b188c81f 8921 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8922 "2: \n\t"
6aa8b732 8923 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8924 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8925 /* Load guest registers. Don't clobber flags. */
b188c81f
AK
8926 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8927 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8928 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8929 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8930 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8931 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8932#ifdef CONFIG_X86_64
e08aa78a
AK
8933 "mov %c[r8](%0), %%r8 \n\t"
8934 "mov %c[r9](%0), %%r9 \n\t"
8935 "mov %c[r10](%0), %%r10 \n\t"
8936 "mov %c[r11](%0), %%r11 \n\t"
8937 "mov %c[r12](%0), %%r12 \n\t"
8938 "mov %c[r13](%0), %%r13 \n\t"
8939 "mov %c[r14](%0), %%r14 \n\t"
8940 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8941#endif
b188c81f 8942 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8943
6aa8b732 8944 /* Enter guest mode */
83287ea4 8945 "jne 1f \n\t"
4ecac3fd 8946 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK
8947 "jmp 2f \n\t"
8948 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8949 "2: "
6aa8b732 8950 /* Save guest registers, load host registers, keep flags */
b188c81f 8951 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8952 "pop %0 \n\t"
b188c81f
AK
8953 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8954 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8955 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8956 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8957 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8958 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8959 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8960#ifdef CONFIG_X86_64
e08aa78a
AK
8961 "mov %%r8, %c[r8](%0) \n\t"
8962 "mov %%r9, %c[r9](%0) \n\t"
8963 "mov %%r10, %c[r10](%0) \n\t"
8964 "mov %%r11, %c[r11](%0) \n\t"
8965 "mov %%r12, %c[r12](%0) \n\t"
8966 "mov %%r13, %c[r13](%0) \n\t"
8967 "mov %%r14, %c[r14](%0) \n\t"
8968 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8969#endif
b188c81f
AK
8970 "mov %%cr2, %%" _ASM_AX " \n\t"
8971 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8972
b188c81f 8973 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8974 "setbe %c[fail](%0) \n\t"
83287ea4
AK
8975 ".pushsection .rodata \n\t"
8976 ".global vmx_return \n\t"
8977 "vmx_return: " _ASM_PTR " 2b \n\t"
8978 ".popsection"
e08aa78a 8979 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8980 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8981 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8982 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX
8983 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8984 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8985 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8986 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8987 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8988 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8989 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8990#ifdef CONFIG_X86_64
ad312c7c
ZX
8991 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8992 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8993 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8994 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8995 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8996 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8997 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8998 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8999#endif
40712fae
AK
9000 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9001 [wordsize]"i"(sizeof(ulong))
c2036300
LV
9002 : "cc", "memory"
9003#ifdef CONFIG_X86_64
b188c81f 9004 , "rax", "rbx", "rdi", "rsi"
c2036300 9005 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK
9006#else
9007 , "eax", "ebx", "edi", "esi"
c2036300
LV
9008#endif
9009 );
6aa8b732 9010
2a7921b7
GN
9011 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9012 if (debugctlmsr)
9013 update_debugctlmsr(debugctlmsr);
9014
aa67f609
AK
9015#ifndef CONFIG_X86_64
9016 /*
9017 * The sysexit path does not restore ds/es, so we must set them to
9018 * a reasonable value ourselves.
9019 *
9020 * We can't defer this to vmx_load_host_state() since that function
9021 * may be executed in interrupt context, which saves and restore segments
9022 * around it, nullifying its effect.
9023 */
9024 loadsegment(ds, __USER_DS);
9025 loadsegment(es, __USER_DS);
9026#endif
9027
6de4f3ad 9028 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 9029 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 9030 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 9031 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 9032 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT
9033 vcpu->arch.regs_dirty = 0;
9034
1155f76a
AK
9035 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9036
d462b819 9037 vmx->loaded_vmcs->launched = 1;
1b6269db 9038
51aa01d1 9039 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1 9040
1be0e61c
XG
9041 /*
9042 * eager fpu is enabled if PKEY is supported and CR4 is switched
9043 * back on host, so it is safe to read guest PKRU from current
9044 * XSAVE.
9045 */
9046 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9047 vmx->guest_pkru = __read_pkru();
9048 if (vmx->guest_pkru != vmx->host_pkru) {
9049 vmx->guest_pkru_valid = true;
9050 __write_pkru(vmx->host_pkru);
9051 } else
9052 vmx->guest_pkru_valid = false;
9053 }
9054
e0b890d3
GN
9055 /*
9056 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9057 * we did not inject a still-pending event to L1 now because of
9058 * nested_run_pending, we need to re-enable this bit.
9059 */
9060 if (vmx->nested.nested_run_pending)
9061 kvm_make_request(KVM_REQ_EVENT, vcpu);
9062
9063 vmx->nested.nested_run_pending = 0;
9064
51aa01d1
AK
9065 vmx_complete_atomic_exit(vmx);
9066 vmx_recover_nmi_blocking(vmx);
cf393f75 9067 vmx_complete_interrupts(vmx);
6aa8b732 9068}
c207aee4 9069STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
6aa8b732 9070
1279a6b1 9071static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
4fa7734c
PB
9072{
9073 struct vcpu_vmx *vmx = to_vmx(vcpu);
9074 int cpu;
9075
1279a6b1 9076 if (vmx->loaded_vmcs == vmcs)
4fa7734c
PB
9077 return;
9078
9079 cpu = get_cpu();
1279a6b1 9080 vmx->loaded_vmcs = vmcs;
4fa7734c
PB
9081 vmx_vcpu_put(vcpu);
9082 vmx_vcpu_load(vcpu, cpu);
9083 vcpu->cpu = cpu;
9084 put_cpu();
9085}
9086
2f1fe811
JM
9087/*
9088 * Ensure that the current vmcs of the logical processor is the
9089 * vmcs01 of the vcpu before calling free_nested().
9090 */
9091static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9092{
9093 struct vcpu_vmx *vmx = to_vmx(vcpu);
9094 int r;
9095
9096 r = vcpu_load(vcpu);
9097 BUG_ON(r);
1279a6b1 9098 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
2f1fe811
JM
9099 free_nested(vmx);
9100 vcpu_put(vcpu);
9101}
9102
6aa8b732
AK
9103static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9104{
fb3f0f51
RR
9105 struct vcpu_vmx *vmx = to_vmx(vcpu);
9106
843e4330 9107 if (enable_pml)
a3eaa864 9108 vmx_destroy_pml_buffer(vmx);
991e7a0e 9109 free_vpid(vmx->vpid);
4fa7734c 9110 leave_guest_mode(vcpu);
2f1fe811 9111 vmx_free_vcpu_nested(vcpu);
4fa7734c 9112 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR
9113 kfree(vmx->guest_msrs);
9114 kvm_vcpu_uninit(vcpu);
a4770347 9115 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK
9116}
9117
fb3f0f51 9118static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 9119{
fb3f0f51 9120 int err;
c16f862d 9121 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 9122 int cpu;
6aa8b732 9123
a2fa3e9f 9124 if (!vmx)
fb3f0f51
RR
9125 return ERR_PTR(-ENOMEM);
9126
991e7a0e 9127 vmx->vpid = allocate_vpid();
2384d2b3 9128
fb3f0f51
RR
9129 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9130 if (err)
9131 goto free_vcpu;
965b58a5 9132
4e59516a
PF
9133 err = -ENOMEM;
9134
9135 /*
9136 * If PML is turned on, failure on enabling PML just results in failure
9137 * of creating the vcpu, therefore we can simplify PML logic (by
9138 * avoiding dealing with cases, such as enabling PML partially on vcpus
9139 * for the guest, etc.
9140 */
9141 if (enable_pml) {
9142 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9143 if (!vmx->pml_pg)
9144 goto uninit_vcpu;
9145 }
9146
a2fa3e9f 9147 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB
9148 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9149 > PAGE_SIZE);
0123be42 9150
4e59516a
PF
9151 if (!vmx->guest_msrs)
9152 goto free_pml;
965b58a5 9153
d462b819
NHE
9154 vmx->loaded_vmcs = &vmx->vmcs01;
9155 vmx->loaded_vmcs->vmcs = alloc_vmcs();
355f4fb1 9156 vmx->loaded_vmcs->shadow_vmcs = NULL;
d462b819 9157 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 9158 goto free_msrs;
d462b819 9159 loaded_vmcs_init(vmx->loaded_vmcs);
a2fa3e9f 9160
15ad7146
AK
9161 cpu = get_cpu();
9162 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 9163 vmx->vcpu.cpu = cpu;
8b9cf98c 9164 err = vmx_vcpu_setup(vmx);
fb3f0f51 9165 vmx_vcpu_put(&vmx->vcpu);
15ad7146 9166 put_cpu();
fb3f0f51
RR
9167 if (err)
9168 goto free_vmcs;
35754c98 9169 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK
9170 err = alloc_apic_access_page(kvm);
9171 if (err)
5e4a0b3c 9172 goto free_vmcs;
a63cb560 9173 }
fb3f0f51 9174
b927a3ce
SY
9175 if (enable_ept) {
9176 if (!kvm->arch.ept_identity_map_addr)
9177 kvm->arch.ept_identity_map_addr =
9178 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC
9179 err = init_rmode_identity_map(kvm);
9180 if (err)
93ea5388 9181 goto free_vmcs;
b927a3ce 9182 }
b7ebfb05 9183
5c614b35 9184 if (nested) {
b9c237bb 9185 nested_vmx_setup_ctls_msrs(vmx);
5c614b35
WL
9186 vmx->nested.vpid02 = allocate_vpid();
9187 }
b9c237bb 9188
705699a1 9189 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE
9190 vmx->nested.current_vmptr = -1ull;
9191 vmx->nested.current_vmcs12 = NULL;
9192
37e4c997
HZ
9193 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9194
fb3f0f51
RR
9195 return &vmx->vcpu;
9196
9197free_vmcs:
5c614b35 9198 free_vpid(vmx->nested.vpid02);
5f3fbc34 9199 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 9200free_msrs:
fb3f0f51 9201 kfree(vmx->guest_msrs);
4e59516a
PF
9202free_pml:
9203 vmx_destroy_pml_buffer(vmx);
fb3f0f51
RR
9204uninit_vcpu:
9205 kvm_vcpu_uninit(&vmx->vcpu);
9206free_vcpu:
991e7a0e 9207 free_vpid(vmx->vpid);
a4770347 9208 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 9209 return ERR_PTR(err);
6aa8b732
AK
9210}
9211
002c7f7c
YS
9212static void __init vmx_check_processor_compat(void *rtn)
9213{
9214 struct vmcs_config vmcs_conf;
9215
9216 *(int *)rtn = 0;
9217 if (setup_vmcs_config(&vmcs_conf) < 0)
9218 *(int *)rtn = -EIO;
9219 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9220 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9221 smp_processor_id());
9222 *(int *)rtn = -EIO;
9223 }
9224}
9225
67253af5
SY
9226static int get_ept_level(void)
9227{
9228 return VMX_EPT_DEFAULT_GAW + 1;
9229}
9230
4b12f0de 9231static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 9232{
b18d5431
XG
9233 u8 cache;
9234 u64 ipat = 0;
4b12f0de 9235
522c68c4 9236 /* For VT-d and EPT combination
606decd6 9237 * 1. MMIO: always map as UC
522c68c4
SY
9238 * 2. EPT with VT-d:
9239 * a. VT-d without snooping control feature: can't guarantee the
606decd6 9240 * result, try to trust guest.
522c68c4
SY
9241 * b. VT-d with snooping control feature: snooping control feature of
9242 * VT-d engine can guarantee the cache correctness. Just set it
9243 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 9244 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY
9245 * consistent with host MTRR
9246 */
606decd6
PB
9247 if (is_mmio) {
9248 cache = MTRR_TYPE_UNCACHABLE;
9249 goto exit;
9250 }
9251
9252 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG
9253 ipat = VMX_EPT_IPAT_BIT;
9254 cache = MTRR_TYPE_WRBACK;
9255 goto exit;
9256 }
9257
9258 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9259 ipat = VMX_EPT_IPAT_BIT;
0da029ed 9260 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG
9261 cache = MTRR_TYPE_WRBACK;
9262 else
9263 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG
9264 goto exit;
9265 }
9266
ff53604b 9267 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG
9268
9269exit:
9270 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY
9271}
9272
17cc3935 9273static int vmx_get_lpage_level(void)
344f414f 9274{
878403b7
SY
9275 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9276 return PT_DIRECTORY_LEVEL;
9277 else
9278 /* For shadow and EPT supported 1GB page */
9279 return PT_PDPE_LEVEL;
344f414f
JR
9280}
9281
feda805f
XG
9282static void vmcs_set_secondary_exec_control(u32 new_ctl)
9283{
9284 /*
9285 * These bits in the secondary execution controls field
9286 * are dynamic, the others are mostly based on the hypervisor
9287 * architecture and the guest's CPUID. Do not touch the
9288 * dynamic bits.
9289 */
9290 u32 mask =
9291 SECONDARY_EXEC_SHADOW_VMCS |
9292 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9293 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9294
9295 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9296
9297 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9298 (new_ctl & ~mask) | (cur_ctl & mask));
9299}
9300
8322ebbb
DM
9301/*
9302 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9303 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9304 */
9305static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9306{
9307 struct vcpu_vmx *vmx = to_vmx(vcpu);
9308 struct kvm_cpuid_entry2 *entry;
9309
9310 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9311 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9312
9313#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9314 if (entry && (entry->_reg & (_cpuid_mask))) \
9315 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9316} while (0)
9317
9318 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9319 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
9320 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
9321 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
9322 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
9323 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
9324 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
9325 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
9326 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
9327 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
9328 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9329 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
9330 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
9331 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
9332 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
9333
9334 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9335 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
9336 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
9337 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
9338 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
9339 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9340 cr4_fixed1_update(bit(11), ecx, bit(2));
9341
9342#undef cr4_fixed1_update
9343}
9344
0e851880
SY
9345static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9346{
4e47c7a6
SY
9347 struct kvm_cpuid_entry2 *best;
9348 struct vcpu_vmx *vmx = to_vmx(vcpu);
feda805f 9349 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
4e47c7a6 9350
4e47c7a6 9351 if (vmx_rdtscp_supported()) {
1cea0ce6
XG
9352 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9353 if (!rdtscp_enabled)
feda805f 9354 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
f36201e5 9355
8b97265a 9356 if (nested) {
1cea0ce6 9357 if (rdtscp_enabled)
8b97265a
PB
9358 vmx->nested.nested_vmx_secondary_ctls_high |=
9359 SECONDARY_EXEC_RDTSCP;
9360 else
9361 vmx->nested.nested_vmx_secondary_ctls_high &=
9362 ~SECONDARY_EXEC_RDTSCP;
9363 }
4e47c7a6 9364 }
ad756a16 9365
ad756a16
MJ
9366 /* Exposing INVPCID only when PCID is exposed */
9367 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9368 if (vmx_invpcid_supported() &&
29541bb8
XG
9369 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9370 !guest_cpuid_has_pcid(vcpu))) {
feda805f 9371 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
29541bb8 9372
ad756a16 9373 if (best)
4f977045 9374 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 9375 }
8b3e34e4 9376
45bdbcfd
HH
9377 if (cpu_has_secondary_exec_ctrls())
9378 vmcs_set_secondary_exec_control(secondary_exec_ctl);
feda805f 9379
37e4c997
HZ
9380 if (nested_vmx_allowed(vcpu))
9381 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9382 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9383 else
9384 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9385 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
8322ebbb
DM
9386
9387 if (nested_vmx_allowed(vcpu))
9388 nested_vmx_cr_fixed1_bits_update(vcpu);
0e851880
SY
9389}
9390
d4330ef2
JR
9391static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9392{
7b8050f5
NHE
9393 if (func == 1 && nested)
9394 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR
9395}
9396
25d92081
YZ
9397static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9398 struct x86_exception *fault)
9399{
533558bc 9400 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
c5f983f6 9401 struct vcpu_vmx *vmx = to_vmx(vcpu);
533558bc 9402 u32 exit_reason;
c5f983f6 9403 unsigned long exit_qualification = vcpu->arch.exit_qualification;
25d92081 9404
c5f983f6
BD
9405 if (vmx->nested.pml_full) {
9406 exit_reason = EXIT_REASON_PML_FULL;
9407 vmx->nested.pml_full = false;
9408 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9409 } else if (fault->error_code & PFERR_RSVD_MASK)
533558bc 9410 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 9411 else
533558bc 9412 exit_reason = EXIT_REASON_EPT_VIOLATION;
c5f983f6
BD
9413
9414 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
25d92081
YZ
9415 vmcs12->guest_physical_address = fault->address;
9416}
9417
995f00a6
PF
9418static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9419{
9420 return nested_ept_get_cr3(vcpu) & VMX_EPT_AD_ENABLE_BIT;
9421}
9422
155a97a3
NHE
9423/* Callbacks for nested_ept_init_mmu_context: */
9424
9425static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9426{
9427 /* return the page table to be shadowed - in our case, EPT12 */
9428 return get_vmcs12(vcpu)->ept_pointer;
9429}
9430
ae1e2d10 9431static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 9432{
995f00a6 9433 bool wants_ad;
ae1e2d10 9434
ad896af0 9435 WARN_ON(mmu_is_nested(vcpu));
995f00a6
PF
9436 wants_ad = nested_ept_ad_enabled(vcpu);
9437 if (wants_ad && !enable_ept_ad_bits)
ae1e2d10
PB
9438 return 1;
9439
9440 kvm_mmu_unload(vcpu);
ad896af0 9441 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb 9442 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
ae1e2d10 9443 VMX_EPT_EXECUTE_ONLY_BIT,
995f00a6 9444 wants_ad);
155a97a3
NHE
9445 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9446 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9447 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9448
9449 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
ae1e2d10 9450 return 0;
155a97a3
NHE
9451}
9452
9453static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9454{
9455 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9456}
9457
19d5f10b
EK
9458static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9459 u16 error_code)
9460{
9461 bool inequality, bit;
9462
9463 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9464 inequality =
9465 (error_code & vmcs12->page_fault_error_code_mask) !=
9466 vmcs12->page_fault_error_code_match;
9467 return inequality ^ bit;
9468}
9469
feaf0c7d
GN
9470static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9471 struct x86_exception *fault)
9472{
9473 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9474
9475 WARN_ON(!is_guest_mode(vcpu));
9476
19d5f10b 9477 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK
9478 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9479 vmcs_read32(VM_EXIT_INTR_INFO),
9480 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN
9481 else
9482 kvm_inject_page_fault(vcpu, fault);
9483}
9484
6beb7bd5
JM
9485static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9486 struct vmcs12 *vmcs12);
9487
9488static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
a2bcba50
WL
9489 struct vmcs12 *vmcs12)
9490{
9491 struct vcpu_vmx *vmx = to_vmx(vcpu);
6beb7bd5 9492 u64 hpa;
a2bcba50
WL
9493
9494 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a2bcba50
WL
9495 /*
9496 * Translate L1 physical address to host physical
9497 * address for vmcs02. Keep the page pinned, so this
9498 * physical address remains valid. We keep a reference
9499 * to it so we can release it later.
9500 */
9501 if (vmx->nested.apic_access_page) /* shouldn't happen */
9502 nested_release_page(vmx->nested.apic_access_page);
9503 vmx->nested.apic_access_page =
9504 nested_get_page(vcpu, vmcs12->apic_access_addr);
6beb7bd5
JM
9505 /*
9506 * If translation failed, no matter: This feature asks
9507 * to exit when accessing the given address, and if it
9508 * can never be accessed, this feature won't do
9509 * anything anyway.
9510 */
9511 if (vmx->nested.apic_access_page) {
9512 hpa = page_to_phys(vmx->nested.apic_access_page);
9513 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9514 } else {
9515 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9516 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9517 }
9518 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9519 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9520 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9521 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9522 kvm_vcpu_reload_apic_access_page(vcpu);
a2bcba50 9523 }
a7c0b07d
WL
9524
9525 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
a7c0b07d
WL
9526 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9527 nested_release_page(vmx->nested.virtual_apic_page);
9528 vmx->nested.virtual_apic_page =
9529 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9530
9531 /*
6beb7bd5
JM
9532 * If translation failed, VM entry will fail because
9533 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9534 * Failing the vm entry is _not_ what the processor
9535 * does but it's basically the only possibility we
9536 * have. We could still enter the guest if CR8 load
9537 * exits are enabled, CR8 store exits are enabled, and
9538 * virtualize APIC access is disabled; in this case
9539 * the processor would never use the TPR shadow and we
9540 * could simply clear the bit from the execution
9541 * control. But such a configuration is useless, so
9542 * let's keep the code simple.
a7c0b07d 9543 */
6beb7bd5
JM
9544 if (vmx->nested.virtual_apic_page) {
9545 hpa = page_to_phys(vmx->nested.virtual_apic_page);
9546 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9547 }
a7c0b07d
WL
9548 }
9549
705699a1 9550 if (nested_cpu_has_posted_intr(vmcs12)) {
705699a1
WV
9551 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9552 kunmap(vmx->nested.pi_desc_page);
9553 nested_release_page(vmx->nested.pi_desc_page);
9554 }
9555 vmx->nested.pi_desc_page =
9556 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
705699a1
WV
9557 vmx->nested.pi_desc =
9558 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9559 if (!vmx->nested.pi_desc) {
9560 nested_release_page_clean(vmx->nested.pi_desc_page);
6beb7bd5 9561 return;
705699a1
WV
9562 }
9563 vmx->nested.pi_desc =
9564 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9565 (unsigned long)(vmcs12->posted_intr_desc_addr &
9566 (PAGE_SIZE - 1)));
6beb7bd5
JM
9567 vmcs_write64(POSTED_INTR_DESC_ADDR,
9568 page_to_phys(vmx->nested.pi_desc_page) +
9569 (unsigned long)(vmcs12->posted_intr_desc_addr &
9570 (PAGE_SIZE - 1)));
705699a1 9571 }
6beb7bd5
JM
9572 if (cpu_has_vmx_msr_bitmap() &&
9573 nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9574 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9575 ;
9576 else
9577 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9578 CPU_BASED_USE_MSR_BITMAPS);
a2bcba50
WL
9579}
9580
f4124500
JK
9581static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9582{
9583 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9584 struct vcpu_vmx *vmx = to_vmx(vcpu);
9585
9586 if (vcpu->arch.virtual_tsc_khz == 0)
9587 return;
9588
9589 /* Make sure short timeouts reliably trigger an immediate vmexit.
9590 * hrtimer_start does not guarantee this. */
9591 if (preemption_timeout <= 1) {
9592 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9593 return;
9594 }
9595
9596 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9597 preemption_timeout *= 1000000;
9598 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9599 hrtimer_start(&vmx->nested.preemption_timer,
9600 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9601}
9602
56a20510
JM
9603static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
9604 struct vmcs12 *vmcs12)
9605{
9606 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9607 return 0;
9608
9609 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
9610 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
9611 return -EINVAL;
9612
9613 return 0;
9614}
9615
3af18d9c
WV
9616static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9617 struct vmcs12 *vmcs12)
9618{
3af18d9c
WV
9619 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9620 return 0;
9621
5fa99cbe 9622 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
3af18d9c
WV
9623 return -EINVAL;
9624
9625 return 0;
9626}
9627
9628/*
9629 * Merge L0's and L1's MSR bitmap, return false to indicate that
9630 * we do not use the hardware.
9631 */
9632static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9633 struct vmcs12 *vmcs12)
9634{
82f0dd4b 9635 int msr;
f2b93280 9636 struct page *page;
d048c098
RK
9637 unsigned long *msr_bitmap_l1;
9638 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
f2b93280 9639
d048c098 9640 /* This shortcut is ok because we support only x2APIC MSRs so far. */
f2b93280
WV
9641 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9642 return false;
9643
9644 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
05d8d346 9645 if (!page)
f2b93280 9646 return false;
d048c098 9647 msr_bitmap_l1 = (unsigned long *)kmap(page);
f2b93280 9648
d048c098
RK
9649 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9650
f2b93280 9651 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV
9652 if (nested_cpu_has_apic_reg_virt(vmcs12))
9653 for (msr = 0x800; msr <= 0x8ff; msr++)
9654 nested_vmx_disable_intercept_for_msr(
d048c098 9655 msr_bitmap_l1, msr_bitmap_l0,
82f0dd4b 9656 msr, MSR_TYPE_R);
d048c098
RK
9657
9658 nested_vmx_disable_intercept_for_msr(
9659 msr_bitmap_l1, msr_bitmap_l0,
f2b93280
WV
9660 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9661 MSR_TYPE_R | MSR_TYPE_W);
d048c098 9662
608406e2 9663 if (nested_cpu_has_vid(vmcs12)) {
608406e2 9664 nested_vmx_disable_intercept_for_msr(
d048c098 9665 msr_bitmap_l1, msr_bitmap_l0,
608406e2
WV
9666 APIC_BASE_MSR + (APIC_EOI >> 4),
9667 MSR_TYPE_W);
9668 nested_vmx_disable_intercept_for_msr(
d048c098 9669 msr_bitmap_l1, msr_bitmap_l0,
608406e2
WV
9670 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9671 MSR_TYPE_W);
9672 }
82f0dd4b 9673 }
f2b93280
WV
9674 kunmap(page);
9675 nested_release_page_clean(page);
9676
9677 return true;
9678}
9679
9680static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9681 struct vmcs12 *vmcs12)
9682{
82f0dd4b 9683 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 9684 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV
9685 !nested_cpu_has_vid(vmcs12) &&
9686 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV
9687 return 0;
9688
9689 /*
9690 * If virtualize x2apic mode is enabled,
9691 * virtualize apic access must be disabled.
9692 */
82f0dd4b
WV
9693 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9694 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV
9695 return -EINVAL;
9696
608406e2
WV
9697 /*
9698 * If virtual interrupt delivery is enabled,
9699 * we must exit on external interrupts.
9700 */
9701 if (nested_cpu_has_vid(vmcs12) &&
9702 !nested_exit_on_intr(vcpu))
9703 return -EINVAL;
9704
705699a1
WV
9705 /*
9706 * bits 15:8 should be zero in posted_intr_nv,
9707 * the descriptor address has been already checked
9708 * in nested_get_vmcs12_pages.
9709 */
9710 if (nested_cpu_has_posted_intr(vmcs12) &&
9711 (!nested_cpu_has_vid(vmcs12) ||
9712 !nested_exit_intr_ack_set(vcpu) ||
9713 vmcs12->posted_intr_nv & 0xff00))
9714 return -EINVAL;
9715
f2b93280
WV
9716 /* tpr shadow is needed by all apicv features. */
9717 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9718 return -EINVAL;
9719
9720 return 0;
3af18d9c
WV
9721}
9722
e9ac033e
EK
9723static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9724 unsigned long count_field,
92d71bc6 9725 unsigned long addr_field)
ff651cb6 9726{
92d71bc6 9727 int maxphyaddr;
e9ac033e
EK
9728 u64 count, addr;
9729
9730 if (vmcs12_read_any(vcpu, count_field, &count) ||
9731 vmcs12_read_any(vcpu, addr_field, &addr)) {
9732 WARN_ON(1);
9733 return -EINVAL;
9734 }
9735 if (count == 0)
9736 return 0;
92d71bc6 9737 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK
9738 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9739 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
bbe41b95 9740 pr_debug_ratelimited(
e9ac033e
EK
9741 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9742 addr_field, maxphyaddr, count, addr);
9743 return -EINVAL;
9744 }
9745 return 0;
9746}
9747
9748static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9749 struct vmcs12 *vmcs12)
9750{
e9ac033e
EK
9751 if (vmcs12->vm_exit_msr_load_count == 0 &&
9752 vmcs12->vm_exit_msr_store_count == 0 &&
9753 vmcs12->vm_entry_msr_load_count == 0)
9754 return 0; /* Fast path */
e9ac033e 9755 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9756 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9757 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9758 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9759 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9760 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK
9761 return -EINVAL;
9762 return 0;
9763}
9764
c5f983f6
BD
9765static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
9766 struct vmcs12 *vmcs12)
9767{
9768 u64 address = vmcs12->pml_address;
9769 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9770
9771 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
9772 if (!nested_cpu_has_ept(vmcs12) ||
9773 !IS_ALIGNED(address, 4096) ||
9774 address >> maxphyaddr)
9775 return -EINVAL;
9776 }
9777
9778 return 0;
9779}
9780
e9ac033e
EK
9781static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9782 struct vmx_msr_entry *e)
9783{
9784 /* x2APIC MSR accesses are not allowed */
8a9781f7 9785 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK
9786 return -EINVAL;
9787 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9788 e->index == MSR_IA32_UCODE_REV)
9789 return -EINVAL;
9790 if (e->reserved != 0)
ff651cb6
WV
9791 return -EINVAL;
9792 return 0;
9793}
9794
e9ac033e
EK
9795static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9796 struct vmx_msr_entry *e)
ff651cb6
WV
9797{
9798 if (e->index == MSR_FS_BASE ||
9799 e->index == MSR_GS_BASE ||
e9ac033e
EK
9800 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9801 nested_vmx_msr_check_common(vcpu, e))
9802 return -EINVAL;
9803 return 0;
9804}
9805
9806static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9807 struct vmx_msr_entry *e)
9808{
9809 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9810 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV
9811 return -EINVAL;
9812 return 0;
9813}
9814
9815/*
9816 * Load guest's/host's msr at nested entry/exit.
9817 * return 0 for success, entry index for failure.
9818 */
9819static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9820{
9821 u32 i;
9822 struct vmx_msr_entry e;
9823 struct msr_data msr;
9824
9825 msr.host_initiated = false;
9826 for (i = 0; i < count; i++) {
54bf36aa
PB
9827 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9828 &e, sizeof(e))) {
bbe41b95 9829 pr_debug_ratelimited(
e9ac033e
EK
9830 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9831 __func__, i, gpa + i * sizeof(e));
ff651cb6 9832 goto fail;
e9ac033e
EK
9833 }
9834 if (nested_vmx_load_msr_check(vcpu, &e)) {
bbe41b95 9835 pr_debug_ratelimited(
e9ac033e
EK
9836 "%s check failed (%u, 0x%x, 0x%x)\n",
9837 __func__, i, e.index, e.reserved);
9838 goto fail;
9839 }
ff651cb6
WV
9840 msr.index = e.index;
9841 msr.data = e.value;
e9ac033e 9842 if (kvm_set_msr(vcpu, &msr)) {
bbe41b95 9843 pr_debug_ratelimited(
e9ac033e
EK
9844 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9845 __func__, i, e.index, e.value);
ff651cb6 9846 goto fail;
e9ac033e 9847 }
ff651cb6
WV
9848 }
9849 return 0;
9850fail:
9851 return i + 1;
9852}
9853
9854static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9855{
9856 u32 i;
9857 struct vmx_msr_entry e;
9858
9859 for (i = 0; i < count; i++) {
609e36d3 9860 struct msr_data msr_info;
54bf36aa
PB
9861 if (kvm_vcpu_read_guest(vcpu,
9862 gpa + i * sizeof(e),
9863 &e, 2 * sizeof(u32))) {
bbe41b95 9864 pr_debug_ratelimited(
e9ac033e
EK
9865 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9866 __func__, i, gpa + i * sizeof(e));
ff651cb6 9867 return -EINVAL;
e9ac033e
EK
9868 }
9869 if (nested_vmx_store_msr_check(vcpu, &e)) {
bbe41b95 9870 pr_debug_ratelimited(
e9ac033e
EK
9871 "%s check failed (%u, 0x%x, 0x%x)\n",
9872 __func__, i, e.index, e.reserved);
ff651cb6 9873 return -EINVAL;
e9ac033e 9874 }
609e36d3
PB
9875 msr_info.host_initiated = false;
9876 msr_info.index = e.index;
9877 if (kvm_get_msr(vcpu, &msr_info)) {
bbe41b95 9878 pr_debug_ratelimited(
e9ac033e
EK
9879 "%s cannot read MSR (%u, 0x%x)\n",
9880 __func__, i, e.index);
9881 return -EINVAL;
9882 }
54bf36aa
PB
9883 if (kvm_vcpu_write_guest(vcpu,
9884 gpa + i * sizeof(e) +
9885 offsetof(struct vmx_msr_entry, value),
9886 &msr_info.data, sizeof(msr_info.data))) {
bbe41b95 9887 pr_debug_ratelimited(
e9ac033e 9888 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9889 __func__, i, e.index, msr_info.data);
e9ac033e
EK
9890 return -EINVAL;
9891 }
ff651cb6
WV
9892 }
9893 return 0;
9894}
9895
1dc35dac
LP
9896static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9897{
9898 unsigned long invalid_mask;
9899
9900 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9901 return (val & invalid_mask) == 0;
9902}
9903
9ed38ffa
LP
9904/*
9905 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9906 * emulating VM entry into a guest with EPT enabled.
9907 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9908 * is assigned to entry_failure_code on failure.
9909 */
9910static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
ca0bde28 9911 u32 *entry_failure_code)
9ed38ffa 9912{
9ed38ffa 9913 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
1dc35dac 9914 if (!nested_cr3_valid(vcpu, cr3)) {
9ed38ffa
LP
9915 *entry_failure_code = ENTRY_FAIL_DEFAULT;
9916 return 1;
9917 }
9918
9919 /*
9920 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9921 * must not be dereferenced.
9922 */
9923 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9924 !nested_ept) {
9925 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9926 *entry_failure_code = ENTRY_FAIL_PDPTE;
9927 return 1;
9928 }
9929 }
9930
9931 vcpu->arch.cr3 = cr3;
9932 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9933 }
9934
9935 kvm_mmu_reset_context(vcpu);
9936 return 0;
9937}
9938
fe3ef05c
NHE
9939/*
9940 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9941 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9942 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE
9943 * guest in a way that will both be appropriate to L1's requests, and our
9944 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9945 * function also has additional necessary side-effects, like setting various
9946 * vcpu->arch fields.
ee146c1c
LP
9947 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9948 * is assigned to entry_failure_code on failure.
fe3ef05c 9949 */
ee146c1c 9950static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
ca0bde28 9951 bool from_vmentry, u32 *entry_failure_code)
fe3ef05c
NHE
9952{
9953 struct vcpu_vmx *vmx = to_vmx(vcpu);
03efce6f 9954 u32 exec_control, vmcs12_exec_ctrl;
fe3ef05c
NHE
9955
9956 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9957 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9958 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9959 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9960 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9961 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9962 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9963 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9964 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9965 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9966 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9967 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9968 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9969 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9970 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9971 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9972 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9973 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9974 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9975 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9976 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9977 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9978 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9979 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9980 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9981 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9982 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9983 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9984 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9985 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9986 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9987 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9988 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9989 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9990 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9991 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9992
cf8b84f4
JM
9993 if (from_vmentry &&
9994 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
2996fca0
JK
9995 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9996 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9997 } else {
9998 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9999 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10000 }
cf8b84f4
JM
10001 if (from_vmentry) {
10002 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10003 vmcs12->vm_entry_intr_info_field);
10004 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10005 vmcs12->vm_entry_exception_error_code);
10006 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10007 vmcs12->vm_entry_instruction_len);
10008 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10009 vmcs12->guest_interruptibility_info);
10010 } else {
10011 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10012 }
fe3ef05c 10013 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 10014 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE
10015 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10016 vmcs12->guest_pending_dbg_exceptions);
10017 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10018 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10019
81dc01f7
WL
10020 if (nested_cpu_has_xsaves(vmcs12))
10021 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE
10022 vmcs_write64(VMCS_LINK_POINTER, -1ull);
10023
f4124500 10024 exec_control = vmcs12->pin_based_vm_exec_control;
9314006d
PB
10025
10026 /* Preemption timer setting is only taken from vmcs01. */
705699a1 10027 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9314006d
PB
10028 exec_control |= vmcs_config.pin_based_exec_ctrl;
10029 if (vmx->hv_deadline_tsc == -1)
10030 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
705699a1 10031
9314006d 10032 /* Posted interrupts setting is only taken from vmcs12. */
705699a1
WV
10033 if (nested_cpu_has_posted_intr(vmcs12)) {
10034 /*
10035 * Note that we use L0's vector here and in
10036 * vmx_deliver_nested_posted_interrupt.
10037 */
10038 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10039 vmx->nested.pi_pending = false;
0bcf261c 10040 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6beb7bd5 10041 } else {
705699a1 10042 exec_control &= ~PIN_BASED_POSTED_INTR;
6beb7bd5 10043 }
705699a1 10044
f4124500 10045 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 10046
f4124500
JK
10047 vmx->nested.preemption_timer_expired = false;
10048 if (nested_cpu_has_preemption_timer(vmcs12))
10049 vmx_start_preemption_timer(vcpu);
0238ea91 10050
fe3ef05c
NHE
10051 /*
10052 * Whether page-faults are trapped is determined by a combination of
10053 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10054 * If enable_ept, L0 doesn't care about page faults and we should
10055 * set all of these to L1's desires. However, if !enable_ept, L0 does
10056 * care about (at least some) page faults, and because it is not easy
10057 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10058 * to exit on each and every L2 page fault. This is done by setting
10059 * MASK=MATCH=0 and (see below) EB.PF=1.
10060 * Note that below we don't need special code to set EB.PF beyond the
10061 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10062 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10063 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10064 *
10065 * A problem with this approach (when !enable_ept) is that L1 may be
10066 * injected with more page faults than it asked for. This could have
10067 * caused problems, but in practice existing hypervisors don't care.
10068 * To fix this, we will need to emulate the PFEC checking (on the L1
10069 * page tables), using walk_addr(), when injecting PFs to L1.
10070 */
10071 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10072 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10073 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10074 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10075
10076 if (cpu_has_secondary_exec_ctrls()) {
f4124500 10077 exec_control = vmx_secondary_exec_control(vmx);
e2821620 10078
fe3ef05c 10079 /* Take the following fields only from vmcs12 */
696dfd95 10080 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 10081 SECONDARY_EXEC_RDTSCP |
696dfd95 10082 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
dfa169bb 10083 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c 10084 if (nested_cpu_has(vmcs12,
03efce6f
BD
10085 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10086 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10087 ~SECONDARY_EXEC_ENABLE_PML;
10088 exec_control |= vmcs12_exec_ctrl;
10089 }
fe3ef05c 10090
608406e2
WV
10091 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10092 vmcs_write64(EOI_EXIT_BITMAP0,
10093 vmcs12->eoi_exit_bitmap0);
10094 vmcs_write64(EOI_EXIT_BITMAP1,
10095 vmcs12->eoi_exit_bitmap1);
10096 vmcs_write64(EOI_EXIT_BITMAP2,
10097 vmcs12->eoi_exit_bitmap2);
10098 vmcs_write64(EOI_EXIT_BITMAP3,
10099 vmcs12->eoi_exit_bitmap3);
10100 vmcs_write16(GUEST_INTR_STATUS,
10101 vmcs12->guest_intr_status);
10102 }
10103
6beb7bd5
JM
10104 /*
10105 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10106 * nested_get_vmcs12_pages will either fix it up or
10107 * remove the VM execution control.
10108 */
10109 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10110 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10111
fe3ef05c
NHE
10112 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10113 }
10114
10115
10116 /*
10117 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10118 * Some constant fields are set here by vmx_set_constant_host_state().
10119 * Other fields are different per CPU, and will be set later when
10120 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10121 */
a547c6db 10122 vmx_set_constant_host_state(vmx);
fe3ef05c 10123
83bafef1
JM
10124 /*
10125 * Set the MSR load/store lists to match L0's settings.
10126 */
10127 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10128 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10129 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10130 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10131 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10132
fe3ef05c
NHE
10133 /*
10134 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10135 * entry, but only if the current (host) sp changed from the value
10136 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10137 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10138 * here we just force the write to happen on entry.
10139 */
10140 vmx->host_rsp = 0;
10141
10142 exec_control = vmx_exec_control(vmx); /* L0's desires */
10143 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10144 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10145 exec_control &= ~CPU_BASED_TPR_SHADOW;
10146 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d 10147
6beb7bd5
JM
10148 /*
10149 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10150 * nested_get_vmcs12_pages can't fix it up, the illegal value
10151 * will result in a VM entry failure.
10152 */
a7c0b07d 10153 if (exec_control & CPU_BASED_TPR_SHADOW) {
6beb7bd5 10154 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
a7c0b07d
WL
10155 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10156 }
10157
fe3ef05c 10158 /*
3af18d9c 10159 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE
10160 * Rather, exit every time.
10161 */
fe3ef05c
NHE
10162 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10163 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10164
10165 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10166
10167 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10168 * bitwise-or of what L1 wants to trap for L2, and what we want to
10169 * trap. Note that CR0.TS also needs updating - we do this later.
10170 */
10171 update_exception_bitmap(vcpu);
10172 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10173 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10174
8049d651
NHE
10175 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10176 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10177 * bits are further modified by vmx_set_efer() below.
10178 */
f4124500 10179 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE
10180
10181 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10182 * emulated by vmx_set_efer(), below.
10183 */
2961e876 10184 vm_entry_controls_init(vmx,
8049d651
NHE
10185 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10186 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE
10187 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10188
cf8b84f4
JM
10189 if (from_vmentry &&
10190 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
fe3ef05c 10191 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02 10192 vcpu->arch.pat = vmcs12->guest_ia32_pat;
cf8b84f4 10193 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 10194 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
cf8b84f4 10195 }
fe3ef05c
NHE
10196
10197 set_cr4_guest_host_mask(vmx);
10198
cf8b84f4
JM
10199 if (from_vmentry &&
10200 vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
36be0b9d
PB
10201 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10202
27fc51b2
NHE
10203 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10204 vmcs_write64(TSC_OFFSET,
ea26e4ec 10205 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
27fc51b2 10206 else
ea26e4ec 10207 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
c95ba92a
PF
10208 if (kvm_has_tsc_control)
10209 decache_tsc_multiplier(vmx);
fe3ef05c
NHE
10210
10211 if (enable_vpid) {
10212 /*
5c614b35
WL
10213 * There is no direct mapping between vpid02 and vpid12, the
10214 * vpid02 is per-vCPU for L0 and reused while the value of
10215 * vpid12 is changed w/ one invvpid during nested vmentry.
10216 * The vpid12 is allocated by L1 for L2, so it will not
10217 * influence global bitmap(for vpid01 and vpid02 allocation)
10218 * even if spawn a lot of nested vCPUs.
fe3ef05c 10219 */
5c614b35
WL
10220 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10221 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10222 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10223 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10224 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10225 }
10226 } else {
10227 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10228 vmx_flush_tlb(vcpu);
10229 }
10230
fe3ef05c
NHE
10231 }
10232
1fb883bb
LP
10233 if (enable_pml) {
10234 /*
10235 * Conceptually we want to copy the PML address and index from
10236 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10237 * since we always flush the log on each vmexit, this happens
10238 * to be equivalent to simply resetting the fields in vmcs02.
10239 */
10240 ASSERT(vmx->pml_pg);
10241 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10242 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10243 }
10244
155a97a3 10245 if (nested_cpu_has_ept(vmcs12)) {
ae1e2d10
PB
10246 if (nested_ept_init_mmu_context(vcpu)) {
10247 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10248 return 1;
10249 }
fb6c8198
JM
10250 } else if (nested_cpu_has2(vmcs12,
10251 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10252 vmx_flush_tlb_ept_only(vcpu);
155a97a3
NHE
10253 }
10254
fe3ef05c 10255 /*
bd7e5b08
PB
10256 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10257 * bits which we consider mandatory enabled.
fe3ef05c
NHE
10258 * The CR0_READ_SHADOW is what L2 should have expected to read given
10259 * the specifications by L1; It's not enough to take
10260 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10261 * have more bits than L1 expected.
10262 */
10263 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10264 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10265
10266 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10267 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10268
cf8b84f4
JM
10269 if (from_vmentry &&
10270 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
5a6a9748
DM
10271 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10272 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10273 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10274 else
10275 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10276 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10277 vmx_set_efer(vcpu, vcpu->arch.efer);
10278
9ed38ffa 10279 /* Shadow page tables on either EPT or shadow page tables. */
7ad658b6 10280 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
9ed38ffa
LP
10281 entry_failure_code))
10282 return 1;
7ca29de2 10283
feaf0c7d
GN
10284 if (!enable_ept)
10285 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10286
3633cfc3
NHE
10287 /*
10288 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10289 */
10290 if (enable_ept) {
10291 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10292 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10293 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10294 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10295 }
10296
fe3ef05c
NHE
10297 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10298 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
ee146c1c 10299 return 0;
fe3ef05c
NHE
10300}
10301
ca0bde28 10302static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
cd232ad0 10303{
cd232ad0 10304 struct vcpu_vmx *vmx = to_vmx(vcpu);
7c177938 10305
6dfacadd 10306 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
ca0bde28
JM
10307 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10308 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
26539bd0 10309
56a20510
JM
10310 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10311 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10312
ca0bde28
JM
10313 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10314 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
7c177938 10315
ca0bde28
JM
10316 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10317 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
f2b93280 10318
ca0bde28
JM
10319 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10320 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
e9ac033e 10321
c5f983f6
BD
10322 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10323 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10324
7c177938 10325 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
0115f9cb 10326 vmx->nested.nested_vmx_procbased_ctls_low,
b9c237bb 10327 vmx->nested.nested_vmx_procbased_ctls_high) ||
2e5b0bd9
JM
10328 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10329 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10330 vmx->nested.nested_vmx_secondary_ctls_low,
10331 vmx->nested.nested_vmx_secondary_ctls_high)) ||
7c177938 10332 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV
10333 vmx->nested.nested_vmx_pinbased_ctls_low,
10334 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 10335 !vmx_control_verify(vmcs12->vm_exit_controls,
0115f9cb 10336 vmx->nested.nested_vmx_exit_ctls_low,
b9c237bb 10337 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 10338 !vmx_control_verify(vmcs12->vm_entry_controls,
0115f9cb 10339 vmx->nested.nested_vmx_entry_ctls_low,
b9c237bb 10340 vmx->nested.nested_vmx_entry_ctls_high))
ca0bde28 10341 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
7c177938 10342
c7c2c709
JM
10343 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10344 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10345
3899152c 10346 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
1dc35dac 10347 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
ca0bde28
JM
10348 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10349 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10350
10351 return 0;
10352}
10353
10354static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10355 u32 *exit_qual)
10356{
10357 bool ia32e;
10358
10359 *exit_qual = ENTRY_FAIL_DEFAULT;
7c177938 10360
3899152c 10361 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
ca0bde28 10362 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
b428018a 10363 return 1;
ca0bde28
JM
10364
10365 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10366 vmcs12->vmcs_link_pointer != -1ull) {
10367 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
b428018a 10368 return 1;
7c177938
NHE
10369 }
10370
384bb783 10371 /*
cb0c8cda 10372 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK
10373 * are performed on the field for the IA32_EFER MSR:
10374 * - Bits reserved in the IA32_EFER MSR must be 0.
10375 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10376 * the IA-32e mode guest VM-exit control. It must also be identical
10377 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10378 * CR0.PG) is 1.
10379 */
ca0bde28
JM
10380 if (to_vmx(vcpu)->nested.nested_run_pending &&
10381 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
384bb783
JK
10382 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10383 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10384 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10385 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
ca0bde28 10386 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
b428018a 10387 return 1;
384bb783
JK
10388 }
10389
10390 /*
10391 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10392 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10393 * the values of the LMA and LME bits in the field must each be that of
10394 * the host address-space size VM-exit control.
10395 */
10396 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10397 ia32e = (vmcs12->vm_exit_controls &
10398 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10399 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10400 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
ca0bde28 10401 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
b428018a 10402 return 1;
ca0bde28
JM
10403 }
10404
10405 return 0;
10406}
10407
858e25c0
JM
10408static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10409{
10410 struct vcpu_vmx *vmx = to_vmx(vcpu);
10411 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10412 struct loaded_vmcs *vmcs02;
858e25c0
JM
10413 u32 msr_entry_idx;
10414 u32 exit_qual;
10415
10416 vmcs02 = nested_get_current_vmcs02(vmx);
10417 if (!vmcs02)
10418 return -ENOMEM;
10419
10420 enter_guest_mode(vcpu);
10421
10422 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10423 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10424
1279a6b1 10425 vmx_switch_vmcs(vcpu, vmcs02);
858e25c0
JM
10426 vmx_segment_cache_clear(vmx);
10427
10428 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10429 leave_guest_mode(vcpu);
1279a6b1 10430 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
858e25c0
JM
10431 nested_vmx_entry_failure(vcpu, vmcs12,
10432 EXIT_REASON_INVALID_STATE, exit_qual);
10433 return 1;
10434 }
10435
10436 nested_get_vmcs12_pages(vcpu, vmcs12);
10437
10438 msr_entry_idx = nested_vmx_load_msr(vcpu,
10439 vmcs12->vm_entry_msr_load_addr,
10440 vmcs12->vm_entry_msr_load_count);
10441 if (msr_entry_idx) {
10442 leave_guest_mode(vcpu);
1279a6b1 10443 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
858e25c0
JM
10444 nested_vmx_entry_failure(vcpu, vmcs12,
10445 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10446 return 1;
10447 }
10448
858e25c0
JM
10449 /*
10450 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10451 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10452 * returned as far as L1 is concerned. It will only return (and set
10453 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10454 */
10455 return 0;
10456}
10457
ca0bde28
JM
10458/*
10459 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10460 * for running an L2 nested guest.
10461 */
10462static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10463{
10464 struct vmcs12 *vmcs12;
10465 struct vcpu_vmx *vmx = to_vmx(vcpu);
ca0bde28
JM
10466 u32 exit_qual;
10467 int ret;
10468
10469 if (!nested_vmx_check_permission(vcpu))
10470 return 1;
10471
10472 if (!nested_vmx_check_vmcs12(vcpu))
10473 goto out;
10474
10475 vmcs12 = get_vmcs12(vcpu);
10476
10477 if (enable_shadow_vmcs)
10478 copy_shadow_to_vmcs12(vmx);
10479
10480 /*
10481 * The nested entry process starts with enforcing various prerequisites
10482 * on vmcs12 as required by the Intel SDM, and act appropriately when
10483 * they fail: As the SDM explains, some conditions should cause the
10484 * instruction to fail, while others will cause the instruction to seem
10485 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10486 * To speed up the normal (success) code path, we should avoid checking
10487 * for misconfigurations which will anyway be caught by the processor
10488 * when using the merged vmcs02.
10489 */
10490 if (vmcs12->launch_state == launch) {
10491 nested_vmx_failValid(vcpu,
10492 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10493 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10494 goto out;
10495 }
10496
10497 ret = check_vmentry_prereqs(vcpu, vmcs12);
10498 if (ret) {
10499 nested_vmx_failValid(vcpu, ret);
10500 goto out;
10501 }
10502
10503 /*
10504 * After this point, the trap flag no longer triggers a singlestep trap
10505 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10506 * This is not 100% correct; for performance reasons, we delegate most
10507 * of the checks on host state to the processor. If those fail,
10508 * the singlestep trap is missed.
10509 */
10510 skip_emulated_instruction(vcpu);
10511
10512 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10513 if (ret) {
10514 nested_vmx_entry_failure(vcpu, vmcs12,
10515 EXIT_REASON_INVALID_STATE, exit_qual);
10516 return 1;
384bb783
JK
10517 }
10518
7c177938
NHE
10519 /*
10520 * We're finally done with prerequisite checking, and can start with
10521 * the nested entry.
10522 */
10523
858e25c0
JM
10524 ret = enter_vmx_non_root_mode(vcpu, true);
10525 if (ret)
10526 return ret;
ff651cb6 10527
6dfacadd 10528 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 10529 return kvm_vcpu_halt(vcpu);
6dfacadd 10530
7af40ad3
JK
10531 vmx->nested.nested_run_pending = 1;
10532
cd232ad0 10533 return 1;
eb277562
KH
10534
10535out:
6affcbed 10536 return kvm_skip_emulated_instruction(vcpu);
cd232ad0
NHE
10537}
10538
4704d0be
NHE
10539/*
10540 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10541 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10542 * This function returns the new value we should put in vmcs12.guest_cr0.
10543 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10544 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10545 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10546 * didn't trap the bit, because if L1 did, so would L0).
10547 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10548 * been modified by L2, and L1 knows it. So just leave the old value of
10549 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10550 * isn't relevant, because if L0 traps this bit it can set it to anything.
10551 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10552 * changed these bits, and therefore they need to be updated, but L0
10553 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10554 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10555 */
10556static inline unsigned long
10557vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10558{
10559 return
10560 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10561 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10562 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10563 vcpu->arch.cr0_guest_owned_bits));
10564}
10565
10566static inline unsigned long
10567vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10568{
10569 return
10570 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10571 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10572 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10573 vcpu->arch.cr4_guest_owned_bits));
10574}
10575
5f3d5799
JK
10576static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10577 struct vmcs12 *vmcs12)
10578{
10579 u32 idt_vectoring;
10580 unsigned int nr;
10581
851eb667 10582 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK
10583 nr = vcpu->arch.exception.nr;
10584 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10585
10586 if (kvm_exception_is_soft(nr)) {
10587 vmcs12->vm_exit_instruction_len =
10588 vcpu->arch.event_exit_inst_len;
10589 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10590 } else
10591 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10592
10593 if (vcpu->arch.exception.has_error_code) {
10594 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10595 vmcs12->idt_vectoring_error_code =
10596 vcpu->arch.exception.error_code;
10597 }
10598
10599 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 10600 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK
10601 vmcs12->idt_vectoring_info_field =
10602 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10603 } else if (vcpu->arch.interrupt.pending) {
10604 nr = vcpu->arch.interrupt.nr;
10605 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10606
10607 if (vcpu->arch.interrupt.soft) {
10608 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10609 vmcs12->vm_entry_instruction_len =
10610 vcpu->arch.event_exit_inst_len;
10611 } else
10612 idt_vectoring |= INTR_TYPE_EXT_INTR;
10613
10614 vmcs12->idt_vectoring_info_field = idt_vectoring;
10615 }
10616}
10617
b6b8a145
JK
10618static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10619{
10620 struct vcpu_vmx *vmx = to_vmx(vcpu);
10621
acc9ab60
WL
10622 if (vcpu->arch.exception.pending ||
10623 vcpu->arch.nmi_injected ||
10624 vcpu->arch.interrupt.pending)
10625 return -EBUSY;
10626
f4124500
JK
10627 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10628 vmx->nested.preemption_timer_expired) {
10629 if (vmx->nested.nested_run_pending)
10630 return -EBUSY;
10631 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10632 return 0;
10633 }
10634
b6b8a145 10635 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
acc9ab60 10636 if (vmx->nested.nested_run_pending)
b6b8a145
JK
10637 return -EBUSY;
10638 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10639 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10640 INTR_INFO_VALID_MASK, 0);
10641 /*
10642 * The NMI-triggered VM exit counts as injection:
10643 * clear this one and block further NMIs.
10644 */
10645 vcpu->arch.nmi_pending = 0;
10646 vmx_set_nmi_mask(vcpu, true);
10647 return 0;
10648 }
10649
10650 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10651 nested_exit_on_intr(vcpu)) {
10652 if (vmx->nested.nested_run_pending)
10653 return -EBUSY;
10654 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 10655 return 0;
b6b8a145
JK
10656 }
10657
6342c50a
DH
10658 vmx_complete_nested_posted_interrupt(vcpu);
10659 return 0;
b6b8a145
JK
10660}
10661
f4124500
JK
10662static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10663{
10664 ktime_t remaining =
10665 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10666 u64 value;
10667
10668 if (ktime_to_ns(remaining) <= 0)
10669 return 0;
10670
10671 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10672 do_div(value, 1000000);
10673 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10674}
10675
4704d0be 10676/*
cf8b84f4
JM
10677 * Update the guest state fields of vmcs12 to reflect changes that
10678 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10679 * VM-entry controls is also updated, since this is really a guest
10680 * state bit.)
4704d0be 10681 */
cf8b84f4 10682static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be 10683{
4704d0be
NHE
10684 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10685 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10686
4704d0be
NHE
10687 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10688 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10689 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10690
10691 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10692 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10693 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10694 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10695 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10696 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10697 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10698 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10699 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10700 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10701 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10702 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10703 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10704 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10705 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10706 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10707 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10708 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10709 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10710 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10711 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10712 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10713 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10714 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10715 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10716 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10717 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10718 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10719 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10720 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10721 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10722 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10723 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10724 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10725 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10726 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10727
4704d0be
NHE
10728 vmcs12->guest_interruptibility_info =
10729 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10730 vmcs12->guest_pending_dbg_exceptions =
10731 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK
10732 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10733 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10734 else
10735 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 10736
f4124500
JK
10737 if (nested_cpu_has_preemption_timer(vmcs12)) {
10738 if (vmcs12->vm_exit_controls &
10739 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10740 vmcs12->vmx_preemption_timer_value =
10741 vmx_get_preemption_timer_value(vcpu);
10742 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10743 }
7854cbca 10744
3633cfc3
NHE
10745 /*
10746 * In some cases (usually, nested EPT), L2 is allowed to change its
10747 * own CR3 without exiting. If it has changed it, we must keep it.
10748 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10749 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10750 *
10751 * Additionally, restore L2's PDPTR to vmcs12.
10752 */
10753 if (enable_ept) {
f3531054 10754 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
3633cfc3
NHE
10755 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10756 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10757 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10758 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10759 }
10760
d281e13b 10761 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
119a9c01 10762
608406e2
WV
10763 if (nested_cpu_has_vid(vmcs12))
10764 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10765
c18911a2
JK
10766 vmcs12->vm_entry_controls =
10767 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 10768 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 10769
2996fca0
JK
10770 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10771 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10772 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10773 }
10774
4704d0be
NHE
10775 /* TODO: These cannot have changed unless we have MSR bitmaps and
10776 * the relevant bit asks not to trap the change */
b8c07d55 10777 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 10778 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK
10779 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10780 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE
10781 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10782 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10783 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
a87036ad 10784 if (kvm_mpx_supported())
36be0b9d 10785 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
cf8b84f4
JM
10786}
10787
10788/*
10789 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10790 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10791 * and this function updates it to reflect the changes to the guest state while
10792 * L2 was running (and perhaps made some exits which were handled directly by L0
10793 * without going back to L1), and to reflect the exit reason.
10794 * Note that we do not have to copy here all VMCS fields, just those that
10795 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10796 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10797 * which already writes to vmcs12 directly.
10798 */
10799static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10800 u32 exit_reason, u32 exit_intr_info,
10801 unsigned long exit_qualification)
10802{
10803 /* update guest state fields: */
10804 sync_vmcs12(vcpu, vmcs12);
4704d0be
NHE
10805
10806 /* update exit information fields: */
10807
533558bc
JK
10808 vmcs12->vm_exit_reason = exit_reason;
10809 vmcs12->exit_qualification = exit_qualification;
4704d0be 10810
533558bc 10811 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK
10812 if ((vmcs12->vm_exit_intr_info &
10813 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10814 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10815 vmcs12->vm_exit_intr_error_code =
10816 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 10817 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE
10818 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10819 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10820
5f3d5799 10821 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7cdc2d62
JM
10822 vmcs12->launch_state = 1;
10823
5f3d5799
JK
10824 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10825 * instead of reading the real value. */
4704d0be 10826 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK
10827
10828 /*
10829 * Transfer the event that L0 or L1 may wanted to inject into
10830 * L2 to IDT_VECTORING_INFO_FIELD.
10831 */
10832 vmcs12_save_pending_event(vcpu, vmcs12);
10833 }
10834
10835 /*
10836 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10837 * preserved above and would only end up incorrectly in L1.
10838 */
10839 vcpu->arch.nmi_injected = false;
10840 kvm_clear_exception_queue(vcpu);
10841 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE
10842}
10843
10844/*
10845 * A part of what we need to when the nested L2 guest exits and we want to
10846 * run its L1 parent, is to reset L1's guest state to the host state specified
10847 * in vmcs12.
10848 * This function is to be called not only on normal nested exit, but also on
10849 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10850 * Failures During or After Loading Guest State").
10851 * This function should be called when the active VMCS is L1's (vmcs01).
10852 */
733568f9
JK
10853static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10854 struct vmcs12 *vmcs12)
4704d0be 10855{
21feb4eb 10856 struct kvm_segment seg;
ca0bde28 10857 u32 entry_failure_code;
21feb4eb 10858
4704d0be
NHE
10859 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10860 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10861 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE
10862 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10863 else
10864 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10865 vmx_set_efer(vcpu, vcpu->arch.efer);
10866
10867 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10868 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10869 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE
10870 /*
10871 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
bd7e5b08
PB
10872 * actually changed, because vmx_set_cr0 refers to efer set above.
10873 *
10874 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10875 * (KVM doesn't change it);
4704d0be 10876 */
bd7e5b08 10877 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
9e3e4dbf 10878 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be 10879
bd7e5b08 10880 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
4704d0be
NHE
10881 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10882 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10883
29bf08f1 10884 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10885
1dc35dac
LP
10886 /*
10887 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10888 * couldn't have changed.
10889 */
10890 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10891 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
4704d0be 10892
feaf0c7d
GN
10893 if (!enable_ept)
10894 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10895
4704d0be
NHE
10896 if (enable_vpid) {
10897 /*
10898 * Trivially support vpid by letting L2s share their parent
10899 * L1's vpid. TODO: move to a more elaborate solution, giving
10900 * each L2 its own vpid and exposing the vpid feature to L1.
10901 */
10902 vmx_flush_tlb(vcpu);
10903 }
10904
10905
10906 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10907 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10908 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10909 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10910 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10911
36be0b9d
PB
10912 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10913 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10914 vmcs_write64(GUEST_BNDCFGS, 0);
10915
44811c02 10916 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10917 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK
10918 vcpu->arch.pat = vmcs12->host_ia32_pat;
10919 }
4704d0be
NHE
10920 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10921 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10922 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10923
21feb4eb
ACL
10924 /* Set L1 segment info according to Intel SDM
10925 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10926 seg = (struct kvm_segment) {
10927 .base = 0,
10928 .limit = 0xFFFFFFFF,
10929 .selector = vmcs12->host_cs_selector,
10930 .type = 11,
10931 .present = 1,
10932 .s = 1,
10933 .g = 1
10934 };
10935 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10936 seg.l = 1;
10937 else
10938 seg.db = 1;
10939 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10940 seg = (struct kvm_segment) {
10941 .base = 0,
10942 .limit = 0xFFFFFFFF,
10943 .type = 3,
10944 .present = 1,
10945 .s = 1,
10946 .db = 1,
10947 .g = 1
10948 };
10949 seg.selector = vmcs12->host_ds_selector;
10950 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10951 seg.selector = vmcs12->host_es_selector;
10952 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10953 seg.selector = vmcs12->host_ss_selector;
10954 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10955 seg.selector = vmcs12->host_fs_selector;
10956 seg.base = vmcs12->host_fs_base;
10957 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10958 seg.selector = vmcs12->host_gs_selector;
10959 seg.base = vmcs12->host_gs_base;
10960 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10961 seg = (struct kvm_segment) {
205befd9 10962 .base = vmcs12->host_tr_base,
21feb4eb
ACL
10963 .limit = 0x67,
10964 .selector = vmcs12->host_tr_selector,
10965 .type = 11,
10966 .present = 1
10967 };
10968 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10969
503cd0c5
JK
10970 kvm_set_dr(vcpu, 7, 0x400);
10971 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 10972
3af18d9c
WV
10973 if (cpu_has_vmx_msr_bitmap())
10974 vmx_set_msr_bitmap(vcpu);
10975
ff651cb6
WV
10976 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10977 vmcs12->vm_exit_msr_load_count))
10978 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE
10979}
10980
10981/*
10982 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10983 * and modify vmcs12 to make it see what it would expect to see there if
10984 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10985 */
533558bc
JK
10986static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10987 u32 exit_intr_info,
10988 unsigned long exit_qualification)
4704d0be
NHE
10989{
10990 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 10991 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
cf3215d9 10992 u32 vm_inst_error = 0;
4704d0be 10993
5f3d5799
JK
10994 /* trying to cancel vmlaunch/vmresume is a bug */
10995 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10996
4704d0be 10997 leave_guest_mode(vcpu);
533558bc
JK
10998 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10999 exit_qualification);
4704d0be 11000
ff651cb6
WV
11001 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11002 vmcs12->vm_exit_msr_store_count))
11003 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11004
cf3215d9
JM
11005 if (unlikely(vmx->fail))
11006 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11007
1279a6b1 11008 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
f3380ca5 11009
77b0f5d6
BD
11010 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11011 && nested_exit_intr_ack_set(vcpu)) {
11012 int irq = kvm_cpu_get_interrupt(vcpu);
11013 WARN_ON(irq < 0);
11014 vmcs12->vm_exit_intr_info = irq |
11015 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11016 }
11017
542060ea
JK
11018 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11019 vmcs12->exit_qualification,
11020 vmcs12->idt_vectoring_info_field,
11021 vmcs12->vm_exit_intr_info,
11022 vmcs12->vm_exit_intr_error_code,
11023 KVM_ISA_VMX);
4704d0be 11024
8391ce44
PB
11025 vm_entry_controls_reset_shadow(vmx);
11026 vm_exit_controls_reset_shadow(vmx);
36c3cc42
JK
11027 vmx_segment_cache_clear(vmx);
11028
4704d0be
NHE
11029 /* if no vmcs02 cache requested, remove the one we used */
11030 if (VMCS02_POOL_SIZE == 0)
11031 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11032
11033 load_vmcs12_host_state(vcpu, vmcs12);
11034
9314006d 11035 /* Update any VMCS fields that might have changed while L2 ran */
83bafef1
JM
11036 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11037 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
ea26e4ec 11038 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
9314006d
PB
11039 if (vmx->hv_deadline_tsc == -1)
11040 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11041 PIN_BASED_VMX_PREEMPTION_TIMER);
11042 else
11043 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11044 PIN_BASED_VMX_PREEMPTION_TIMER);
c95ba92a
PF
11045 if (kvm_has_tsc_control)
11046 decache_tsc_multiplier(vmx);
4704d0be 11047
dccbfcf5
RK
11048 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11049 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11050 vmx_set_virtual_x2apic_mode(vcpu,
11051 vcpu->arch.apic_base & X2APIC_ENABLE);
fb6c8198
JM
11052 } else if (!nested_cpu_has_ept(vmcs12) &&
11053 nested_cpu_has2(vmcs12,
11054 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11055 vmx_flush_tlb_ept_only(vcpu);
dccbfcf5 11056 }
4704d0be
NHE
11057
11058 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11059 vmx->host_rsp = 0;
11060
11061 /* Unpin physical memory we referred to in vmcs02 */
11062 if (vmx->nested.apic_access_page) {
11063 nested_release_page(vmx->nested.apic_access_page);
48d89b92 11064 vmx->nested.apic_access_page = NULL;
4704d0be 11065 }
a7c0b07d
WL
11066 if (vmx->nested.virtual_apic_page) {
11067 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 11068 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 11069 }
705699a1
WV
11070 if (vmx->nested.pi_desc_page) {
11071 kunmap(vmx->nested.pi_desc_page);
11072 nested_release_page(vmx->nested.pi_desc_page);
11073 vmx->nested.pi_desc_page = NULL;
11074 vmx->nested.pi_desc = NULL;
11075 }
4704d0be 11076
38b99173
TC
11077 /*
11078 * We are now running in L2, mmu_notifier will force to reload the
11079 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11080 */
c83b6d15 11081 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
38b99173 11082
4704d0be
NHE
11083 /*
11084 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11085 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11086 * success or failure flag accordingly.
11087 */
11088 if (unlikely(vmx->fail)) {
11089 vmx->fail = 0;
cf3215d9 11090 nested_vmx_failValid(vcpu, vm_inst_error);
4704d0be
NHE
11091 } else
11092 nested_vmx_succeed(vcpu);
012f83cb
AG
11093 if (enable_shadow_vmcs)
11094 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK
11095
11096 /* in case we halted in L2 */
11097 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE
11098}
11099
42124925
JK
11100/*
11101 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11102 */
11103static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11104{
2f707d97
WL
11105 if (is_guest_mode(vcpu)) {
11106 to_vmx(vcpu)->nested.nested_run_pending = 0;
533558bc 11107 nested_vmx_vmexit(vcpu, -1, 0, 0);
2f707d97 11108 }
42124925
JK
11109 free_nested(to_vmx(vcpu));
11110}
11111
7c177938
NHE
11112/*
11113 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11114 * 23.7 "VM-entry failures during or after loading guest state" (this also
11115 * lists the acceptable exit-reason and exit-qualification parameters).
11116 * It should only be called before L2 actually succeeded to run, and when
11117 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11118 */
11119static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11120 struct vmcs12 *vmcs12,
11121 u32 reason, unsigned long qualification)
11122{
11123 load_vmcs12_host_state(vcpu, vmcs12);
11124 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11125 vmcs12->exit_qualification = qualification;
11126 nested_vmx_succeed(vcpu);
012f83cb
AG
11127 if (enable_shadow_vmcs)
11128 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE
11129}
11130
8a76d7f2
JR
11131static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11132 struct x86_instruction_info *info,
11133 enum x86_intercept_stage stage)
11134{
11135 return X86EMUL_CONTINUE;
11136}
11137
64672c95
YJ
11138#ifdef CONFIG_X86_64
11139/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11140static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11141 u64 divisor, u64 *result)
11142{
11143 u64 low = a << shift, high = a >> (64 - shift);
11144
11145 /* To avoid the overflow on divq */
11146 if (high >= divisor)
11147 return 1;
11148
11149 /* Low hold the result, high hold rem which is discarded */
11150 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11151 "rm" (divisor), "0" (low), "1" (high));
11152 *result = low;
11153
11154 return 0;
11155}
11156
11157static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11158{
11159 struct vcpu_vmx *vmx = to_vmx(vcpu);
9175d2e9
PB
11160 u64 tscl = rdtsc();
11161 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11162 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
64672c95
YJ
11163
11164 /* Convert to host delta tsc if tsc scaling is enabled */
11165 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11166 u64_shl_div_u64(delta_tsc,
11167 kvm_tsc_scaling_ratio_frac_bits,
11168 vcpu->arch.tsc_scaling_ratio,
11169 &delta_tsc))
11170 return -ERANGE;
11171
11172 /*
11173 * If the delta tsc can't fit in the 32 bit after the multi shift,
11174 * we can't use the preemption timer.
11175 * It's possible that it fits on later vmentries, but checking
11176 * on every vmentry is costly so we just use an hrtimer.
11177 */
11178 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11179 return -ERANGE;
11180
11181 vmx->hv_deadline_tsc = tscl + delta_tsc;
11182 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11183 PIN_BASED_VMX_PREEMPTION_TIMER);
c8533544
WL
11184
11185 return delta_tsc == 0;
64672c95
YJ
11186}
11187
11188static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11189{
11190 struct vcpu_vmx *vmx = to_vmx(vcpu);
11191 vmx->hv_deadline_tsc = -1;
11192 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11193 PIN_BASED_VMX_PREEMPTION_TIMER);
11194}
11195#endif
11196
48d89b92 11197static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 11198{
b4a2d31d
RK
11199 if (ple_gap)
11200 shrink_ple_window(vcpu);
ae97a3b8
RK
11201}
11202
843e4330
KH
11203static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11204 struct kvm_memory_slot *slot)
11205{
11206 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11207 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11208}
11209
11210static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11211 struct kvm_memory_slot *slot)
11212{
11213 kvm_mmu_slot_set_dirty(kvm, slot);
11214}
11215
11216static void vmx_flush_log_dirty(struct kvm *kvm)
11217{
11218 kvm_flush_pml_buffers(kvm);
11219}
11220
c5f983f6
BD
11221static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11222{
11223 struct vmcs12 *vmcs12;
11224 struct vcpu_vmx *vmx = to_vmx(vcpu);
11225 gpa_t gpa;
11226 struct page *page = NULL;
11227 u64 *pml_address;
11228
11229 if (is_guest_mode(vcpu)) {
11230 WARN_ON_ONCE(vmx->nested.pml_full);
11231
11232 /*
11233 * Check if PML is enabled for the nested guest.
11234 * Whether eptp bit 6 is set is already checked
11235 * as part of A/D emulation.
11236 */
11237 vmcs12 = get_vmcs12(vcpu);
11238 if (!nested_cpu_has_pml(vmcs12))
11239 return 0;
11240
4769886b 11241 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD
11242 vmx->nested.pml_full = true;
11243 return 1;
11244 }
11245
11246 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11247
11248 page = nested_get_page(vcpu, vmcs12->pml_address);
11249 if (!page)
11250 return 0;
11251
11252 pml_address = kmap(page);
11253 pml_address[vmcs12->guest_pml_index--] = gpa;
11254 kunmap(page);
11255 nested_release_page_clean(page);
11256 }
11257
11258 return 0;
11259}
11260
843e4330
KH
11261static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11262 struct kvm_memory_slot *memslot,
11263 gfn_t offset, unsigned long mask)
11264{
11265 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11266}
11267
bf9f6ac8
FW
11268/*
11269 * This routine does the following things for vCPU which is going
11270 * to be blocked if VT-d PI is enabled.
11271 * - Store the vCPU to the wakeup list, so when interrupts happen
11272 * we can find the right vCPU to wake up.
11273 * - Change the Posted-interrupt descriptor as below:
11274 * 'NDST' <-- vcpu->pre_pcpu
11275 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11276 * - If 'ON' is set during this process, which means at least one
11277 * interrupt is posted for this vCPU, we cannot block it, in
11278 * this case, return 1, otherwise, return 0.
11279 *
11280 */
bc22512b 11281static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8
FW
11282{
11283 unsigned long flags;
11284 unsigned int dest;
11285 struct pi_desc old, new;
11286 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11287
11288 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
11289 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11290 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW
11291 return 0;
11292
11293 vcpu->pre_pcpu = vcpu->cpu;
11294 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11295 vcpu->pre_pcpu), flags);
11296 list_add_tail(&vcpu->blocked_vcpu_list,
11297 &per_cpu(blocked_vcpu_on_cpu,
11298 vcpu->pre_pcpu));
11299 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11300 vcpu->pre_pcpu), flags);
11301
11302 do {
11303 old.control = new.control = pi_desc->control;
11304
11305 /*
11306 * We should not block the vCPU if
11307 * an interrupt is posted for it.
11308 */
11309 if (pi_test_on(pi_desc) == 1) {
11310 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11311 vcpu->pre_pcpu), flags);
11312 list_del(&vcpu->blocked_vcpu_list);
11313 spin_unlock_irqrestore(
11314 &per_cpu(blocked_vcpu_on_cpu_lock,
11315 vcpu->pre_pcpu), flags);
11316 vcpu->pre_pcpu = -1;
11317
11318 return 1;
11319 }
11320
11321 WARN((pi_desc->sn == 1),
11322 "Warning: SN field of posted-interrupts "
11323 "is set before blocking\n");
11324
11325 /*
11326 * Since vCPU can be preempted during this process,
11327 * vcpu->cpu could be different with pre_pcpu, we
11328 * need to set pre_pcpu as the destination of wakeup
11329 * notification event, then we can find the right vCPU
11330 * to wakeup in wakeup handler if interrupts happen
11331 * when the vCPU is in blocked state.
11332 */
11333 dest = cpu_physical_id(vcpu->pre_pcpu);
11334
11335 if (x2apic_enabled())
11336 new.ndst = dest;
11337 else
11338 new.ndst = (dest << 8) & 0xFF00;
11339
11340 /* set 'NV' to 'wakeup vector' */
11341 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11342 } while (cmpxchg(&pi_desc->control, old.control,
11343 new.control) != old.control);
11344
11345 return 0;
11346}
11347
bc22512b
YJ
11348static int vmx_pre_block(struct kvm_vcpu *vcpu)
11349{
11350 if (pi_pre_block(vcpu))
11351 return 1;
11352
64672c95
YJ
11353 if (kvm_lapic_hv_timer_in_use(vcpu))
11354 kvm_lapic_switch_to_sw_timer(vcpu);
11355
bc22512b
YJ
11356 return 0;
11357}
11358
11359static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8
FW
11360{
11361 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11362 struct pi_desc old, new;
11363 unsigned int dest;
11364 unsigned long flags;
11365
11366 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
11367 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11368 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW
11369 return;
11370
11371 do {
11372 old.control = new.control = pi_desc->control;
11373
11374 dest = cpu_physical_id(vcpu->cpu);
11375
11376 if (x2apic_enabled())
11377 new.ndst = dest;
11378 else
11379 new.ndst = (dest << 8) & 0xFF00;
11380
11381 /* Allow posting non-urgent interrupts */
11382 new.sn = 0;
11383
11384 /* set 'NV' to 'notification vector' */
11385 new.nv = POSTED_INTR_VECTOR;
11386 } while (cmpxchg(&pi_desc->control, old.control,
11387 new.control) != old.control);
11388
11389 if(vcpu->pre_pcpu != -1) {
11390 spin_lock_irqsave(
11391 &per_cpu(blocked_vcpu_on_cpu_lock,
11392 vcpu->pre_pcpu), flags);
11393 list_del(&vcpu->blocked_vcpu_list);
11394 spin_unlock_irqrestore(
11395 &per_cpu(blocked_vcpu_on_cpu_lock,
11396 vcpu->pre_pcpu), flags);
11397 vcpu->pre_pcpu = -1;
11398 }
11399}
11400
bc22512b
YJ
11401static void vmx_post_block(struct kvm_vcpu *vcpu)
11402{
64672c95
YJ
11403 if (kvm_x86_ops->set_hv_timer)
11404 kvm_lapic_switch_to_hv_timer(vcpu);
11405
bc22512b
YJ
11406 pi_post_block(vcpu);
11407}
11408
efc64404
FW
11409/*
11410 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11411 *
11412 * @kvm: kvm
11413 * @host_irq: host irq of the interrupt
11414 * @guest_irq: gsi of the interrupt
11415 * @set: set or unset PI
11416 * returns 0 on success, < 0 on failure
11417 */
11418static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11419 uint32_t guest_irq, bool set)
11420{
11421 struct kvm_kernel_irq_routing_entry *e;
11422 struct kvm_irq_routing_table *irq_rt;
11423 struct kvm_lapic_irq irq;
11424 struct kvm_vcpu *vcpu;
11425 struct vcpu_data vcpu_info;
11426 int idx, ret = -EINVAL;
11427
11428 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ
11429 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11430 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW
11431 return 0;
11432
11433 idx = srcu_read_lock(&kvm->irq_srcu);
11434 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11435 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11436
11437 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11438 if (e->type != KVM_IRQ_ROUTING_MSI)
11439 continue;
11440 /*
11441 * VT-d PI cannot support posting multicast/broadcast
11442 * interrupts to a vCPU, we still use interrupt remapping
11443 * for these kind of interrupts.
11444 *
11445 * For lowest-priority interrupts, we only support
11446 * those with single CPU as the destination, e.g. user
11447 * configures the interrupts via /proc/irq or uses
11448 * irqbalance to make the interrupts single-CPU.
11449 *
11450 * We will support full lowest-priority interrupt later.
11451 */
11452
37131313 11453 kvm_set_msi_irq(kvm, e, &irq);
23a1c257
FW
11454 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11455 /*
11456 * Make sure the IRTE is in remapped mode if
11457 * we don't handle it in posted mode.
11458 */
11459 ret = irq_set_vcpu_affinity(host_irq, NULL);
11460 if (ret < 0) {
11461 printk(KERN_INFO
11462 "failed to back to remapped mode, irq: %u\n",
11463 host_irq);
11464 goto out;
11465 }
11466
efc64404 11467 continue;
23a1c257 11468 }
efc64404
FW
11469
11470 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11471 vcpu_info.vector = irq.vector;
11472
b6ce9780 11473 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
efc64404
FW
11474 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11475
11476 if (set)
11477 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11478 else {
11479 /* suppress notification event before unposting */
11480 pi_set_sn(vcpu_to_pi_desc(vcpu));
11481 ret = irq_set_vcpu_affinity(host_irq, NULL);
11482 pi_clear_sn(vcpu_to_pi_desc(vcpu));
11483 }
11484
11485 if (ret < 0) {
11486 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11487 __func__);
11488 goto out;
11489 }
11490 }
11491
11492 ret = 0;
11493out:
11494 srcu_read_unlock(&kvm->irq_srcu, idx);
11495 return ret;
11496}
11497
c45dcc71
AR
11498static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11499{
11500 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11501 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11502 FEATURE_CONTROL_LMCE;
11503 else
11504 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11505 ~FEATURE_CONTROL_LMCE;
11506}
11507
404f6aac 11508static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK
11509 .cpu_has_kvm_support = cpu_has_kvm_support,
11510 .disabled_by_bios = vmx_disabled_by_bios,
11511 .hardware_setup = hardware_setup,
11512 .hardware_unsetup = hardware_unsetup,
002c7f7c 11513 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK
11514 .hardware_enable = hardware_enable,
11515 .hardware_disable = hardware_disable,
04547156 11516 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 11517 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK
11518
11519 .vcpu_create = vmx_create_vcpu,
11520 .vcpu_free = vmx_free_vcpu,
04d2cc77 11521 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 11522
04d2cc77 11523 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK
11524 .vcpu_load = vmx_vcpu_load,
11525 .vcpu_put = vmx_vcpu_put,
11526
a96036b8 11527 .update_bp_intercept = update_exception_bitmap,
6aa8b732
AK
11528 .get_msr = vmx_get_msr,
11529 .set_msr = vmx_set_msr,
11530 .get_segment_base = vmx_get_segment_base,
11531 .get_segment = vmx_get_segment,
11532 .set_segment = vmx_set_segment,
2e4d2653 11533 .get_cpl = vmx_get_cpl,
6aa8b732 11534 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 11535 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 11536 .decache_cr3 = vmx_decache_cr3,
25c4c276 11537 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 11538 .set_cr0 = vmx_set_cr0,
6aa8b732
AK
11539 .set_cr3 = vmx_set_cr3,
11540 .set_cr4 = vmx_set_cr4,
6aa8b732 11541 .set_efer = vmx_set_efer,
6aa8b732
AK
11542 .get_idt = vmx_get_idt,
11543 .set_idt = vmx_set_idt,
11544 .get_gdt = vmx_get_gdt,
11545 .set_gdt = vmx_set_gdt,
73aaf249
JK
11546 .get_dr6 = vmx_get_dr6,
11547 .set_dr6 = vmx_set_dr6,
020df079 11548 .set_dr7 = vmx_set_dr7,
81908bf4 11549 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 11550 .cache_reg = vmx_cache_reg,
6aa8b732
AK
11551 .get_rflags = vmx_get_rflags,
11552 .set_rflags = vmx_set_rflags,
be94f6b7
HH
11553
11554 .get_pkru = vmx_get_pkru,
11555
6aa8b732 11556 .tlb_flush = vmx_flush_tlb,
6aa8b732 11557
6aa8b732 11558 .run = vmx_vcpu_run,
6062d012 11559 .handle_exit = vmx_handle_exit,
6aa8b732 11560 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC
11561 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11562 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 11563 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 11564 .set_irq = vmx_inject_irq,
95ba8273 11565 .set_nmi = vmx_inject_nmi,
298101da 11566 .queue_exception = vmx_queue_exception,
b463a6f7 11567 .cancel_injection = vmx_cancel_injection,
78646121 11568 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 11569 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK
11570 .get_nmi_mask = vmx_get_nmi_mask,
11571 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN
11572 .enable_nmi_window = enable_nmi_window,
11573 .enable_irq_window = enable_irq_window,
11574 .update_cr8_intercept = update_cr8_intercept,
8d14695f 11575 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 11576 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb
AS
11577 .get_enable_apicv = vmx_get_enable_apicv,
11578 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 11579 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 11580 .apicv_post_state_restore = vmx_apicv_post_state_restore,
c7c9c56c
YZ
11581 .hwapic_irr_update = vmx_hwapic_irr_update,
11582 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ
11583 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11584 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 11585
cbc94022 11586 .set_tss_addr = vmx_set_tss_addr,
67253af5 11587 .get_tdp_level = get_ept_level,
4b12f0de 11588 .get_mt_mask = vmx_get_mt_mask,
229456fc 11589
586f9607 11590 .get_exit_info = vmx_get_exit_info,
586f9607 11591
17cc3935 11592 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY
11593
11594 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY
11595
11596 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 11597 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR
11598
11599 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY
11600
11601 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA
11602
11603 .write_tsc_offset = vmx_write_tsc_offset,
1c97f0a0
JR
11604
11605 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR
11606
11607 .check_intercept = vmx_check_intercept,
a547c6db 11608 .handle_external_intr = vmx_handle_external_intr,
da8999d3 11609 .mpx_supported = vmx_mpx_supported,
55412b2e 11610 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK
11611
11612 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK
11613
11614 .sched_in = vmx_sched_in,
843e4330
KH
11615
11616 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11617 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11618 .flush_log_dirty = vmx_flush_log_dirty,
11619 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 11620 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 11621
bf9f6ac8
FW
11622 .pre_block = vmx_pre_block,
11623 .post_block = vmx_post_block,
11624
25462f7f 11625 .pmu_ops = &intel_pmu_ops,
efc64404
FW
11626
11627 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ
11628
11629#ifdef CONFIG_X86_64
11630 .set_hv_timer = vmx_set_hv_timer,
11631 .cancel_hv_timer = vmx_cancel_hv_timer,
11632#endif
c45dcc71
AR
11633
11634 .setup_mce = vmx_setup_mce,
6aa8b732
AK
11635};
11636
11637static int __init vmx_init(void)
11638{
34a1cd60
TC
11639 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11640 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 11641 if (r)
34a1cd60 11642 return r;
25c5f225 11643
2965faa5 11644#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY
11645 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11646 crash_vmclear_local_loaded_vmcss);
11647#endif
11648
fdef3ad1 11649 return 0;
6aa8b732
AK
11650}
11651
11652static void __exit vmx_exit(void)
11653{
2965faa5 11654#ifdef CONFIG_KEXEC_CORE
3b63a43f 11655 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY
11656 synchronize_rcu();
11657#endif
11658
cb498ea2 11659 kvm_exit();
6aa8b732
AK
11660}
11661
11662module_init(vmx_init)
11663module_exit(vmx_exit)