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kvm: x86: hyperv: add KVM_CAP_HYPERV_SYNIC2
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CommitLineData
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
d62caabb 22#include "lapic.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732 25#include <linux/module.h>
9d8f549d 26#include <linux/kernel.h>
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27#include <linux/mm.h>
28#include <linux/highmem.h>
e8edc6e0 29#include <linux/sched.h>
c7addb90 30#include <linux/moduleparam.h>
e9bda3b3 31#include <linux/mod_devicetable.h>
af658dca 32#include <linux/trace_events.h>
5a0e3ad6 33#include <linux/slab.h>
cafd6659 34#include <linux/tboot.h>
f4124500 35#include <linux/hrtimer.h>
c207aee4 36#include <linux/frame.h>
5fdbf976 37#include "kvm_cache_regs.h"
35920a35 38#include "x86.h"
e495606d 39
28b835d6 40#include <asm/cpu.h>
6aa8b732 41#include <asm/io.h>
3b3be0d1 42#include <asm/desc.h>
13673a90 43#include <asm/vmx.h>
6210e37b 44#include <asm/virtext.h>
a0861c02 45#include <asm/mce.h>
952f07ec 46#include <asm/fpu/internal.h>
d7cd9796 47#include <asm/perf_event.h>
81908bf4 48#include <asm/debugreg.h>
8f536b76 49#include <asm/kexec.h>
dab2087d 50#include <asm/apic.h>
efc64404 51#include <asm/irq_remapping.h>
d6e41f11 52#include <asm/mmu_context.h>
6aa8b732 53
229456fc 54#include "trace.h"
25462f7f 55#include "pmu.h"
229456fc 56
4ecac3fd 57#define __ex(x) __kvm_handle_fault_on_reboot(x)
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58#define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 60
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61MODULE_AUTHOR("Qumranet");
62MODULE_LICENSE("GPL");
63
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64static const struct x86_cpu_id vmx_cpu_id[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX),
66 {}
67};
68MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
69
476bc001 70static bool __read_mostly enable_vpid = 1;
736caefe 71module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 72
476bc001 73static bool __read_mostly flexpriority_enabled = 1;
736caefe 74module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 75
476bc001 76static bool __read_mostly enable_ept = 1;
736caefe 77module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 78
476bc001 79static bool __read_mostly enable_unrestricted_guest = 1;
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80module_param_named(unrestricted_guest,
81 enable_unrestricted_guest, bool, S_IRUGO);
82
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83static bool __read_mostly enable_ept_ad_bits = 1;
84module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
85
a27685c3 86static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 87module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 88
476bc001 89static bool __read_mostly fasteoi = 1;
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90module_param(fasteoi, bool, S_IRUGO);
91
5a71785d 92static bool __read_mostly enable_apicv = 1;
01e439be 93module_param(enable_apicv, bool, S_IRUGO);
83d4c286 94
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95static bool __read_mostly enable_shadow_vmcs = 1;
96module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
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97/*
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
101 */
476bc001 102static bool __read_mostly nested = 0;
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103module_param(nested, bool, S_IRUGO);
104
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105static u64 __read_mostly host_xss;
106
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107static bool __read_mostly enable_pml = 1;
108module_param_named(pml, enable_pml, bool, S_IRUGO);
109
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110#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
111
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112/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
113static int __read_mostly cpu_preemption_timer_multi;
114static bool __read_mostly enable_preemption_timer = 1;
115#ifdef CONFIG_X86_64
116module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
117#endif
118
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119#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
120#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
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121#define KVM_VM_CR0_ALWAYS_ON \
122 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
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123#define KVM_CR4_GUEST_OWNED_BITS \
124 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 125 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 126
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127#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
128#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
129
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130#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
131
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132#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
133
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134/*
135 * Hyper-V requires all of these, so mark them as supported even though
136 * they are just treated the same as all-context.
137 */
138#define VMX_VPID_EXTENT_SUPPORTED_MASK \
139 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
140 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
143
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144/*
145 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
146 * ple_gap: upper bound on the amount of time between two successive
147 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 148 * According to test, this time is usually smaller than 128 cycles.
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149 * ple_window: upper bound on the amount of time a guest is allowed to execute
150 * in a PAUSE loop. Tests indicate that most spinlocks are held for
151 * less than 2^12 cycles
152 * Time is measured based on a counter that runs at the same rate as the TSC,
153 * refer SDM volume 3b section 21.6.13 & 22.1.3.
154 */
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155#define KVM_VMX_DEFAULT_PLE_GAP 128
156#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
157#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
158#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
159#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
160 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
161
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162static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
163module_param(ple_gap, int, S_IRUGO);
164
165static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
166module_param(ple_window, int, S_IRUGO);
167
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168/* Default doubles per-vcpu window every exit. */
169static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
170module_param(ple_window_grow, int, S_IRUGO);
171
172/* Default resets per-vcpu window every exit to ple_window. */
173static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
174module_param(ple_window_shrink, int, S_IRUGO);
175
176/* Default is to compute the maximum so we can never overflow. */
177static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
178static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179module_param(ple_window_max, int, S_IRUGO);
180
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181extern const ulong vmx_return;
182
8bf00a52 183#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 184#define VMCS02_POOL_SIZE 1
61d2ef2c 185
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186struct vmcs {
187 u32 revision_id;
188 u32 abort;
189 char data[0];
190};
191
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192/*
193 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
194 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
195 * loaded on this CPU (so we can clear them if the CPU goes down).
196 */
197struct loaded_vmcs {
198 struct vmcs *vmcs;
355f4fb1 199 struct vmcs *shadow_vmcs;
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200 int cpu;
201 int launched;
202 struct list_head loaded_vmcss_on_cpu_link;
203};
204
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205struct shared_msr_entry {
206 unsigned index;
207 u64 data;
d5696725 208 u64 mask;
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209};
210
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211/*
212 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
213 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
214 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
215 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
216 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
217 * More than one of these structures may exist, if L1 runs multiple L2 guests.
218 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
219 * underlying hardware which will be used to run L2.
220 * This structure is packed to ensure that its layout is identical across
221 * machines (necessary for live migration).
222 * If there are changes in this struct, VMCS12_REVISION must be changed.
223 */
22bd0358 224typedef u64 natural_width;
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225struct __packed vmcs12 {
226 /* According to the Intel spec, a VMCS region must start with the
227 * following two fields. Then follow implementation-specific data.
228 */
229 u32 revision_id;
230 u32 abort;
22bd0358 231
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232 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
233 u32 padding[7]; /* room for future expansion */
234
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235 u64 io_bitmap_a;
236 u64 io_bitmap_b;
237 u64 msr_bitmap;
238 u64 vm_exit_msr_store_addr;
239 u64 vm_exit_msr_load_addr;
240 u64 vm_entry_msr_load_addr;
241 u64 tsc_offset;
242 u64 virtual_apic_page_addr;
243 u64 apic_access_addr;
705699a1 244 u64 posted_intr_desc_addr;
22bd0358 245 u64 ept_pointer;
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246 u64 eoi_exit_bitmap0;
247 u64 eoi_exit_bitmap1;
248 u64 eoi_exit_bitmap2;
249 u64 eoi_exit_bitmap3;
81dc01f7 250 u64 xss_exit_bitmap;
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251 u64 guest_physical_address;
252 u64 vmcs_link_pointer;
c5f983f6 253 u64 pml_address;
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254 u64 guest_ia32_debugctl;
255 u64 guest_ia32_pat;
256 u64 guest_ia32_efer;
257 u64 guest_ia32_perf_global_ctrl;
258 u64 guest_pdptr0;
259 u64 guest_pdptr1;
260 u64 guest_pdptr2;
261 u64 guest_pdptr3;
36be0b9d 262 u64 guest_bndcfgs;
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263 u64 host_ia32_pat;
264 u64 host_ia32_efer;
265 u64 host_ia32_perf_global_ctrl;
266 u64 padding64[8]; /* room for future expansion */
267 /*
268 * To allow migration of L1 (complete with its L2 guests) between
269 * machines of different natural widths (32 or 64 bit), we cannot have
270 * unsigned long fields with no explict size. We use u64 (aliased
271 * natural_width) instead. Luckily, x86 is little-endian.
272 */
273 natural_width cr0_guest_host_mask;
274 natural_width cr4_guest_host_mask;
275 natural_width cr0_read_shadow;
276 natural_width cr4_read_shadow;
277 natural_width cr3_target_value0;
278 natural_width cr3_target_value1;
279 natural_width cr3_target_value2;
280 natural_width cr3_target_value3;
281 natural_width exit_qualification;
282 natural_width guest_linear_address;
283 natural_width guest_cr0;
284 natural_width guest_cr3;
285 natural_width guest_cr4;
286 natural_width guest_es_base;
287 natural_width guest_cs_base;
288 natural_width guest_ss_base;
289 natural_width guest_ds_base;
290 natural_width guest_fs_base;
291 natural_width guest_gs_base;
292 natural_width guest_ldtr_base;
293 natural_width guest_tr_base;
294 natural_width guest_gdtr_base;
295 natural_width guest_idtr_base;
296 natural_width guest_dr7;
297 natural_width guest_rsp;
298 natural_width guest_rip;
299 natural_width guest_rflags;
300 natural_width guest_pending_dbg_exceptions;
301 natural_width guest_sysenter_esp;
302 natural_width guest_sysenter_eip;
303 natural_width host_cr0;
304 natural_width host_cr3;
305 natural_width host_cr4;
306 natural_width host_fs_base;
307 natural_width host_gs_base;
308 natural_width host_tr_base;
309 natural_width host_gdtr_base;
310 natural_width host_idtr_base;
311 natural_width host_ia32_sysenter_esp;
312 natural_width host_ia32_sysenter_eip;
313 natural_width host_rsp;
314 natural_width host_rip;
315 natural_width paddingl[8]; /* room for future expansion */
316 u32 pin_based_vm_exec_control;
317 u32 cpu_based_vm_exec_control;
318 u32 exception_bitmap;
319 u32 page_fault_error_code_mask;
320 u32 page_fault_error_code_match;
321 u32 cr3_target_count;
322 u32 vm_exit_controls;
323 u32 vm_exit_msr_store_count;
324 u32 vm_exit_msr_load_count;
325 u32 vm_entry_controls;
326 u32 vm_entry_msr_load_count;
327 u32 vm_entry_intr_info_field;
328 u32 vm_entry_exception_error_code;
329 u32 vm_entry_instruction_len;
330 u32 tpr_threshold;
331 u32 secondary_vm_exec_control;
332 u32 vm_instruction_error;
333 u32 vm_exit_reason;
334 u32 vm_exit_intr_info;
335 u32 vm_exit_intr_error_code;
336 u32 idt_vectoring_info_field;
337 u32 idt_vectoring_error_code;
338 u32 vm_exit_instruction_len;
339 u32 vmx_instruction_info;
340 u32 guest_es_limit;
341 u32 guest_cs_limit;
342 u32 guest_ss_limit;
343 u32 guest_ds_limit;
344 u32 guest_fs_limit;
345 u32 guest_gs_limit;
346 u32 guest_ldtr_limit;
347 u32 guest_tr_limit;
348 u32 guest_gdtr_limit;
349 u32 guest_idtr_limit;
350 u32 guest_es_ar_bytes;
351 u32 guest_cs_ar_bytes;
352 u32 guest_ss_ar_bytes;
353 u32 guest_ds_ar_bytes;
354 u32 guest_fs_ar_bytes;
355 u32 guest_gs_ar_bytes;
356 u32 guest_ldtr_ar_bytes;
357 u32 guest_tr_ar_bytes;
358 u32 guest_interruptibility_info;
359 u32 guest_activity_state;
360 u32 guest_sysenter_cs;
361 u32 host_ia32_sysenter_cs;
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362 u32 vmx_preemption_timer_value;
363 u32 padding32[7]; /* room for future expansion */
22bd0358 364 u16 virtual_processor_id;
705699a1 365 u16 posted_intr_nv;
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366 u16 guest_es_selector;
367 u16 guest_cs_selector;
368 u16 guest_ss_selector;
369 u16 guest_ds_selector;
370 u16 guest_fs_selector;
371 u16 guest_gs_selector;
372 u16 guest_ldtr_selector;
373 u16 guest_tr_selector;
608406e2 374 u16 guest_intr_status;
c5f983f6 375 u16 guest_pml_index;
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376 u16 host_es_selector;
377 u16 host_cs_selector;
378 u16 host_ss_selector;
379 u16 host_ds_selector;
380 u16 host_fs_selector;
381 u16 host_gs_selector;
382 u16 host_tr_selector;
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383};
384
385/*
386 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
387 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
388 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
389 */
390#define VMCS12_REVISION 0x11e57ed0
391
392/*
393 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
394 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
395 * current implementation, 4K are reserved to avoid future complications.
396 */
397#define VMCS12_SIZE 0x1000
398
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399/* Used to remember the last vmcs02 used for some recently used vmcs12s */
400struct vmcs02_list {
401 struct list_head list;
402 gpa_t vmptr;
403 struct loaded_vmcs vmcs02;
404};
405
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406/*
407 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
408 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
409 */
410struct nested_vmx {
411 /* Has the level1 guest done vmxon? */
412 bool vmxon;
3573e22c 413 gpa_t vmxon_ptr;
c5f983f6 414 bool pml_full;
a9d30f33
NHE
415
416 /* The guest-physical address of the current VMCS L1 keeps for L2 */
417 gpa_t current_vmptr;
418 /* The host-usable pointer to the above */
419 struct page *current_vmcs12_page;
420 struct vmcs12 *current_vmcs12;
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DM
421 /*
422 * Cache of the guest's VMCS, existing outside of guest memory.
423 * Loaded from guest memory during VMPTRLD. Flushed to guest
424 * memory during VMXOFF, VMCLEAR, VMPTRLD.
425 */
426 struct vmcs12 *cached_vmcs12;
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AG
427 /*
428 * Indicates if the shadow vmcs must be updated with the
429 * data hold by vmcs12
430 */
431 bool sync_shadow_vmcs;
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432
433 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
434 struct list_head vmcs02_pool;
435 int vmcs02_num;
dccbfcf5 436 bool change_vmcs01_virtual_x2apic_mode;
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437 /* L2 must run next, and mustn't decide to exit to L1. */
438 bool nested_run_pending;
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439 /*
440 * Guest pages referred to in vmcs02 with host-physical pointers, so
441 * we must keep them pinned while L2 runs.
442 */
443 struct page *apic_access_page;
a7c0b07d 444 struct page *virtual_apic_page;
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445 struct page *pi_desc_page;
446 struct pi_desc *pi_desc;
447 bool pi_pending;
448 u16 posted_intr_nv;
f4124500 449
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450 unsigned long *msr_bitmap;
451
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452 struct hrtimer preemption_timer;
453 bool preemption_timer_expired;
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454
455 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
456 u64 vmcs01_debugctl;
b9c237bb 457
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WL
458 u16 vpid02;
459 u16 last_vpid;
460
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461 /*
462 * We only store the "true" versions of the VMX capability MSRs. We
463 * generate the "non-true" versions by setting the must-be-1 bits
464 * according to the SDM.
465 */
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466 u32 nested_vmx_procbased_ctls_low;
467 u32 nested_vmx_procbased_ctls_high;
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468 u32 nested_vmx_secondary_ctls_low;
469 u32 nested_vmx_secondary_ctls_high;
470 u32 nested_vmx_pinbased_ctls_low;
471 u32 nested_vmx_pinbased_ctls_high;
472 u32 nested_vmx_exit_ctls_low;
473 u32 nested_vmx_exit_ctls_high;
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474 u32 nested_vmx_entry_ctls_low;
475 u32 nested_vmx_entry_ctls_high;
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476 u32 nested_vmx_misc_low;
477 u32 nested_vmx_misc_high;
478 u32 nested_vmx_ept_caps;
99b83ac8 479 u32 nested_vmx_vpid_caps;
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DM
480 u64 nested_vmx_basic;
481 u64 nested_vmx_cr0_fixed0;
482 u64 nested_vmx_cr0_fixed1;
483 u64 nested_vmx_cr4_fixed0;
484 u64 nested_vmx_cr4_fixed1;
485 u64 nested_vmx_vmcs_enum;
ec378aee
NHE
486};
487
01e439be 488#define POSTED_INTR_ON 0
ebbfc765
FW
489#define POSTED_INTR_SN 1
490
01e439be
YZ
491/* Posted-Interrupt Descriptor */
492struct pi_desc {
493 u32 pir[8]; /* Posted interrupt requested */
6ef1522f
FW
494 union {
495 struct {
496 /* bit 256 - Outstanding Notification */
497 u16 on : 1,
498 /* bit 257 - Suppress Notification */
499 sn : 1,
500 /* bit 271:258 - Reserved */
501 rsvd_1 : 14;
502 /* bit 279:272 - Notification Vector */
503 u8 nv;
504 /* bit 287:280 - Reserved */
505 u8 rsvd_2;
506 /* bit 319:288 - Notification Destination */
507 u32 ndst;
508 };
509 u64 control;
510 };
511 u32 rsvd[6];
01e439be
YZ
512} __aligned(64);
513
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514static bool pi_test_and_set_on(struct pi_desc *pi_desc)
515{
516 return test_and_set_bit(POSTED_INTR_ON,
517 (unsigned long *)&pi_desc->control);
518}
519
520static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
521{
522 return test_and_clear_bit(POSTED_INTR_ON,
523 (unsigned long *)&pi_desc->control);
524}
525
526static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
527{
528 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
529}
530
ebbfc765
FW
531static inline void pi_clear_sn(struct pi_desc *pi_desc)
532{
533 return clear_bit(POSTED_INTR_SN,
534 (unsigned long *)&pi_desc->control);
535}
536
537static inline void pi_set_sn(struct pi_desc *pi_desc)
538{
539 return set_bit(POSTED_INTR_SN,
540 (unsigned long *)&pi_desc->control);
541}
542
ad361091
PB
543static inline void pi_clear_on(struct pi_desc *pi_desc)
544{
545 clear_bit(POSTED_INTR_ON,
546 (unsigned long *)&pi_desc->control);
547}
548
ebbfc765
FW
549static inline int pi_test_on(struct pi_desc *pi_desc)
550{
551 return test_bit(POSTED_INTR_ON,
552 (unsigned long *)&pi_desc->control);
553}
554
555static inline int pi_test_sn(struct pi_desc *pi_desc)
556{
557 return test_bit(POSTED_INTR_SN,
558 (unsigned long *)&pi_desc->control);
559}
560
a2fa3e9f 561struct vcpu_vmx {
fb3f0f51 562 struct kvm_vcpu vcpu;
313dbd49 563 unsigned long host_rsp;
29bd8a78 564 u8 fail;
9d58b931 565 bool nmi_known_unmasked;
51aa01d1 566 u32 exit_intr_info;
1155f76a 567 u32 idt_vectoring_info;
6de12732 568 ulong rflags;
26bb0981 569 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH
570 int nmsrs;
571 int save_nmsrs;
a547c6db 572 unsigned long host_idt_base;
a2fa3e9f 573#ifdef CONFIG_X86_64
44ea2b17
AK
574 u64 msr_host_kernel_gs_base;
575 u64 msr_guest_kernel_gs_base;
a2fa3e9f 576#endif
2961e876
GN
577 u32 vm_entry_controls_shadow;
578 u32 vm_exit_controls_shadow;
d462b819
NHE
579 /*
580 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
581 * non-nested (L1) guest, it always points to vmcs01. For a nested
582 * guest (L2), it points to a different VMCS.
583 */
584 struct loaded_vmcs vmcs01;
585 struct loaded_vmcs *loaded_vmcs;
586 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK
587 struct msr_autoload {
588 unsigned nr;
589 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
590 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
591 } msr_autoload;
a2fa3e9f
GH
592 struct {
593 int loaded;
594 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK
595#ifdef CONFIG_X86_64
596 u16 ds_sel, es_sel;
597#endif
152d3f2f
LV
598 int gs_ldt_reload_needed;
599 int fs_reload_needed;
da8999d3 600 u64 msr_host_bndcfgs;
d6e41f11 601 unsigned long vmcs_host_cr3; /* May not match real cr3 */
d974baa3 602 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 603 } host_state;
9c8cba37 604 struct {
7ffd92c5 605 int vm86_active;
78ac8b47 606 ulong save_rflags;
f5f7b2fe
AK
607 struct kvm_segment segs[8];
608 } rmode;
609 struct {
610 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK
611 struct kvm_save_segment {
612 u16 selector;
613 unsigned long base;
614 u32 limit;
615 u32 ar;
f5f7b2fe 616 } seg[8];
2fb92db1 617 } segment_cache;
2384d2b3 618 int vpid;
04fa4d32 619 bool emulation_required;
3b86cd99 620
a0861c02 621 u32 exit_reason;
4e47c7a6 622
01e439be
YZ
623 /* Posted interrupt descriptor */
624 struct pi_desc pi_desc;
625
ec378aee
NHE
626 /* Support for a guest hypervisor (nested VMX) */
627 struct nested_vmx nested;
a7653ecd
RK
628
629 /* Dynamic PLE window. */
630 int ple_window;
631 bool ple_window_dirty;
843e4330
KH
632
633 /* Support for PML */
634#define PML_ENTITY_NUM 512
635 struct page *pml_pg;
2680d6da 636
64672c95
YJ
637 /* apic deadline value in host tsc */
638 u64 hv_deadline_tsc;
639
2680d6da 640 u64 current_tsc_ratio;
1be0e61c
XG
641
642 bool guest_pkru_valid;
643 u32 guest_pkru;
644 u32 host_pkru;
3b84080b 645
37e4c997
HZ
646 /*
647 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
648 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
649 * in msr_ia32_feature_control_valid_bits.
650 */
3b84080b 651 u64 msr_ia32_feature_control;
37e4c997 652 u64 msr_ia32_feature_control_valid_bits;
a2fa3e9f
GH
653};
654
2fb92db1
AK
655enum segment_cache_field {
656 SEG_FIELD_SEL = 0,
657 SEG_FIELD_BASE = 1,
658 SEG_FIELD_LIMIT = 2,
659 SEG_FIELD_AR = 3,
660
661 SEG_FIELD_NR = 4
662};
663
a2fa3e9f
GH
664static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
665{
fb3f0f51 666 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH
667}
668
efc64404
FW
669static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
670{
671 return &(to_vmx(vcpu)->pi_desc);
672}
673
22bd0358
NHE
674#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
675#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
676#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
677 [number##_HIGH] = VMCS12_OFFSET(name)+4
678
4607c2d7 679
fe2b201b 680static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG
681 /*
682 * We do NOT shadow fields that are modified when L0
683 * traps and emulates any vmx instruction (e.g. VMPTRLD,
684 * VMXON...) executed by L1.
685 * For example, VM_INSTRUCTION_ERROR is read
686 * by L1 if a vmx instruction fails (part of the error path).
687 * Note the code assumes this logic. If for some reason
688 * we start shadowing these fields then we need to
689 * force a shadow sync when L0 emulates vmx instructions
690 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
691 * by nested_vmx_failValid)
692 */
693 VM_EXIT_REASON,
694 VM_EXIT_INTR_INFO,
695 VM_EXIT_INSTRUCTION_LEN,
696 IDT_VECTORING_INFO_FIELD,
697 IDT_VECTORING_ERROR_CODE,
698 VM_EXIT_INTR_ERROR_CODE,
699 EXIT_QUALIFICATION,
700 GUEST_LINEAR_ADDRESS,
701 GUEST_PHYSICAL_ADDRESS
702};
fe2b201b 703static int max_shadow_read_only_fields =
4607c2d7
AG
704 ARRAY_SIZE(shadow_read_only_fields);
705
fe2b201b 706static unsigned long shadow_read_write_fields[] = {
a7c0b07d 707 TPR_THRESHOLD,
4607c2d7
AG
708 GUEST_RIP,
709 GUEST_RSP,
710 GUEST_CR0,
711 GUEST_CR3,
712 GUEST_CR4,
713 GUEST_INTERRUPTIBILITY_INFO,
714 GUEST_RFLAGS,
715 GUEST_CS_SELECTOR,
716 GUEST_CS_AR_BYTES,
717 GUEST_CS_LIMIT,
718 GUEST_CS_BASE,
719 GUEST_ES_BASE,
36be0b9d 720 GUEST_BNDCFGS,
4607c2d7
AG
721 CR0_GUEST_HOST_MASK,
722 CR0_READ_SHADOW,
723 CR4_READ_SHADOW,
724 TSC_OFFSET,
725 EXCEPTION_BITMAP,
726 CPU_BASED_VM_EXEC_CONTROL,
727 VM_ENTRY_EXCEPTION_ERROR_CODE,
728 VM_ENTRY_INTR_INFO_FIELD,
729 VM_ENTRY_INSTRUCTION_LEN,
730 VM_ENTRY_EXCEPTION_ERROR_CODE,
731 HOST_FS_BASE,
732 HOST_GS_BASE,
733 HOST_FS_SELECTOR,
734 HOST_GS_SELECTOR
735};
fe2b201b 736static int max_shadow_read_write_fields =
4607c2d7
AG
737 ARRAY_SIZE(shadow_read_write_fields);
738
772e0318 739static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 740 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 741 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE
742 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
743 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
744 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
745 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
746 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
747 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
748 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
749 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 750 FIELD(GUEST_INTR_STATUS, guest_intr_status),
c5f983f6 751 FIELD(GUEST_PML_INDEX, guest_pml_index),
22bd0358
NHE
752 FIELD(HOST_ES_SELECTOR, host_es_selector),
753 FIELD(HOST_CS_SELECTOR, host_cs_selector),
754 FIELD(HOST_SS_SELECTOR, host_ss_selector),
755 FIELD(HOST_DS_SELECTOR, host_ds_selector),
756 FIELD(HOST_FS_SELECTOR, host_fs_selector),
757 FIELD(HOST_GS_SELECTOR, host_gs_selector),
758 FIELD(HOST_TR_SELECTOR, host_tr_selector),
759 FIELD64(IO_BITMAP_A, io_bitmap_a),
760 FIELD64(IO_BITMAP_B, io_bitmap_b),
761 FIELD64(MSR_BITMAP, msr_bitmap),
762 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
763 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
764 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
765 FIELD64(TSC_OFFSET, tsc_offset),
766 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
767 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 768 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 769 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV
770 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
771 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
772 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
773 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 774 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE
775 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
776 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
c5f983f6 777 FIELD64(PML_ADDRESS, pml_address),
22bd0358
NHE
778 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
779 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
780 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
781 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
782 FIELD64(GUEST_PDPTR0, guest_pdptr0),
783 FIELD64(GUEST_PDPTR1, guest_pdptr1),
784 FIELD64(GUEST_PDPTR2, guest_pdptr2),
785 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 786 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE
787 FIELD64(HOST_IA32_PAT, host_ia32_pat),
788 FIELD64(HOST_IA32_EFER, host_ia32_efer),
789 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
790 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
791 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
792 FIELD(EXCEPTION_BITMAP, exception_bitmap),
793 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
794 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
795 FIELD(CR3_TARGET_COUNT, cr3_target_count),
796 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
797 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
798 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
799 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
800 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
801 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
802 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
803 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
804 FIELD(TPR_THRESHOLD, tpr_threshold),
805 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
806 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
807 FIELD(VM_EXIT_REASON, vm_exit_reason),
808 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
809 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
810 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
811 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
812 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
813 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
814 FIELD(GUEST_ES_LIMIT, guest_es_limit),
815 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
816 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
817 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
818 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
819 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
820 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
821 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
822 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
823 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
824 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
825 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
826 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
827 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
828 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
829 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
830 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
831 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
832 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
833 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
834 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
835 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 836 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE
837 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
838 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
839 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
840 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
841 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
842 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
843 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
844 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
845 FIELD(EXIT_QUALIFICATION, exit_qualification),
846 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
847 FIELD(GUEST_CR0, guest_cr0),
848 FIELD(GUEST_CR3, guest_cr3),
849 FIELD(GUEST_CR4, guest_cr4),
850 FIELD(GUEST_ES_BASE, guest_es_base),
851 FIELD(GUEST_CS_BASE, guest_cs_base),
852 FIELD(GUEST_SS_BASE, guest_ss_base),
853 FIELD(GUEST_DS_BASE, guest_ds_base),
854 FIELD(GUEST_FS_BASE, guest_fs_base),
855 FIELD(GUEST_GS_BASE, guest_gs_base),
856 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
857 FIELD(GUEST_TR_BASE, guest_tr_base),
858 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
859 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
860 FIELD(GUEST_DR7, guest_dr7),
861 FIELD(GUEST_RSP, guest_rsp),
862 FIELD(GUEST_RIP, guest_rip),
863 FIELD(GUEST_RFLAGS, guest_rflags),
864 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
865 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
866 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
867 FIELD(HOST_CR0, host_cr0),
868 FIELD(HOST_CR3, host_cr3),
869 FIELD(HOST_CR4, host_cr4),
870 FIELD(HOST_FS_BASE, host_fs_base),
871 FIELD(HOST_GS_BASE, host_gs_base),
872 FIELD(HOST_TR_BASE, host_tr_base),
873 FIELD(HOST_GDTR_BASE, host_gdtr_base),
874 FIELD(HOST_IDTR_BASE, host_idtr_base),
875 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
876 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
877 FIELD(HOST_RSP, host_rsp),
878 FIELD(HOST_RIP, host_rip),
879};
22bd0358
NHE
880
881static inline short vmcs_field_to_offset(unsigned long field)
882{
a2ae9df7
PB
883 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
884
885 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
886 vmcs_field_to_offset_table[field] == 0)
887 return -ENOENT;
888
22bd0358
NHE
889 return vmcs_field_to_offset_table[field];
890}
891
a9d30f33
NHE
892static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
893{
4f2777bc 894 return to_vmx(vcpu)->nested.cached_vmcs12;
a9d30f33
NHE
895}
896
897static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
898{
54bf36aa 899 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 900 if (is_error_page(page))
a9d30f33 901 return NULL;
32cad84f 902
a9d30f33
NHE
903 return page;
904}
905
906static void nested_release_page(struct page *page)
907{
908 kvm_release_page_dirty(page);
909}
910
911static void nested_release_page_clean(struct page *page)
912{
913 kvm_release_page_clean(page);
914}
915
995f00a6 916static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
bfd0a56b 917static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
995f00a6 918static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
f53cd63c 919static bool vmx_xsaves_supported(void);
776e58ea 920static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW
921static void vmx_set_segment(struct kvm_vcpu *vcpu,
922 struct kvm_segment *var, int seg);
923static void vmx_get_segment(struct kvm_vcpu *vcpu,
924 struct kvm_segment *var, int seg);
d99e4152
GN
925static bool guest_state_valid(struct kvm_vcpu *vcpu);
926static u32 vmx_segment_access_rights(struct kvm_segment *var);
c3114420 927static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 928static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 929static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 930
6aa8b732
AK
931static DEFINE_PER_CPU(struct vmcs *, vmxarea);
932static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE
933/*
934 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
935 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
936 */
937static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 938
bf9f6ac8
FW
939/*
940 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
941 * can find which vCPU should be waken up.
942 */
943static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
944static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
945
23611332
RK
946enum {
947 VMX_IO_BITMAP_A,
948 VMX_IO_BITMAP_B,
949 VMX_MSR_BITMAP_LEGACY,
950 VMX_MSR_BITMAP_LONGMODE,
951 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
952 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
953 VMX_MSR_BITMAP_LEGACY_X2APIC,
954 VMX_MSR_BITMAP_LONGMODE_X2APIC,
955 VMX_VMREAD_BITMAP,
956 VMX_VMWRITE_BITMAP,
957 VMX_BITMAP_NR
958};
959
960static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
961
962#define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
963#define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
964#define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
965#define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
966#define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
967#define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
968#define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
969#define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
970#define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
971#define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
fdef3ad1 972
110312c8 973static bool cpu_has_load_ia32_efer;
8bf00a52 974static bool cpu_has_load_perf_global_ctrl;
110312c8 975
2384d2b3
SY
976static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
977static DEFINE_SPINLOCK(vmx_vpid_lock);
978
1c3d14fe 979static struct vmcs_config {
6aa8b732
AK
980 int size;
981 int order;
9ac7e3e8 982 u32 basic_cap;
6aa8b732 983 u32 revision_id;
1c3d14fe
YS
984 u32 pin_based_exec_ctrl;
985 u32 cpu_based_exec_ctrl;
f78e0e2e 986 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS
987 u32 vmexit_ctrl;
988 u32 vmentry_ctrl;
989} vmcs_config;
6aa8b732 990
efff9e53 991static struct vmx_capability {
d56f546d
SY
992 u32 ept;
993 u32 vpid;
994} vmx_capability;
995
6aa8b732
AK
996#define VMX_SEGMENT_FIELD(seg) \
997 [VCPU_SREG_##seg] = { \
998 .selector = GUEST_##seg##_SELECTOR, \
999 .base = GUEST_##seg##_BASE, \
1000 .limit = GUEST_##seg##_LIMIT, \
1001 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1002 }
1003
772e0318 1004static const struct kvm_vmx_segment_field {
6aa8b732
AK
1005 unsigned selector;
1006 unsigned base;
1007 unsigned limit;
1008 unsigned ar_bytes;
1009} kvm_vmx_segment_fields[] = {
1010 VMX_SEGMENT_FIELD(CS),
1011 VMX_SEGMENT_FIELD(DS),
1012 VMX_SEGMENT_FIELD(ES),
1013 VMX_SEGMENT_FIELD(FS),
1014 VMX_SEGMENT_FIELD(GS),
1015 VMX_SEGMENT_FIELD(SS),
1016 VMX_SEGMENT_FIELD(TR),
1017 VMX_SEGMENT_FIELD(LDTR),
1018};
1019
26bb0981
AK
1020static u64 host_efer;
1021
6de4f3ad
AK
1022static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1023
4d56c8a7 1024/*
8c06585d 1025 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK
1026 * away by decrementing the array size.
1027 */
6aa8b732 1028static const u32 vmx_msr_index[] = {
05b3e0c2 1029#ifdef CONFIG_X86_64
44ea2b17 1030 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 1031#endif
8c06585d 1032 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 1033};
6aa8b732 1034
5bb16016 1035static inline bool is_exception_n(u32 intr_info, u8 vector)
6aa8b732
AK
1036{
1037 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1038 INTR_INFO_VALID_MASK)) ==
5bb16016
JK
1039 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1040}
1041
6f05485d
JK
1042static inline bool is_debug(u32 intr_info)
1043{
1044 return is_exception_n(intr_info, DB_VECTOR);
1045}
1046
1047static inline bool is_breakpoint(u32 intr_info)
1048{
1049 return is_exception_n(intr_info, BP_VECTOR);
1050}
1051
5bb16016
JK
1052static inline bool is_page_fault(u32 intr_info)
1053{
1054 return is_exception_n(intr_info, PF_VECTOR);
6aa8b732
AK
1055}
1056
31299944 1057static inline bool is_no_device(u32 intr_info)
2ab455cc 1058{
5bb16016 1059 return is_exception_n(intr_info, NM_VECTOR);
2ab455cc
AL
1060}
1061
31299944 1062static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0 1063{
5bb16016 1064 return is_exception_n(intr_info, UD_VECTOR);
7aa81cc0
AL
1065}
1066
31299944 1067static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK
1068{
1069 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1070 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1071}
1072
31299944 1073static inline bool is_machine_check(u32 intr_info)
a0861c02
AK
1074{
1075 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1076 INTR_INFO_VALID_MASK)) ==
1077 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1078}
1079
31299944 1080static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 1081{
04547156 1082 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY
1083}
1084
31299944 1085static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 1086{
04547156 1087 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS
1088}
1089
35754c98 1090static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 1091{
35754c98 1092 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS
1093}
1094
31299944 1095static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 1096{
04547156
SY
1097 return vmcs_config.cpu_based_exec_ctrl &
1098 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY
1099}
1100
774ead3a 1101static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 1102{
04547156
SY
1103 return vmcs_config.cpu_based_2nd_exec_ctrl &
1104 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1105}
1106
8d14695f
YZ
1107static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1108{
1109 return vmcs_config.cpu_based_2nd_exec_ctrl &
1110 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1111}
1112
83d4c286
YZ
1113static inline bool cpu_has_vmx_apic_register_virt(void)
1114{
1115 return vmcs_config.cpu_based_2nd_exec_ctrl &
1116 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1117}
1118
c7c9c56c
YZ
1119static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1120{
1121 return vmcs_config.cpu_based_2nd_exec_ctrl &
1122 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1123}
1124
64672c95
YJ
1125/*
1126 * Comment's format: document - errata name - stepping - processor name.
1127 * Refer from
1128 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1129 */
1130static u32 vmx_preemption_cpu_tfms[] = {
1131/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
11320x000206E6,
1133/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1134/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1135/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
11360x00020652,
1137/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
11380x00020655,
1139/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1140/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1141/*
1142 * 320767.pdf - AAP86 - B1 -
1143 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1144 */
11450x000106E5,
1146/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
11470x000106A0,
1148/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
11490x000106A1,
1150/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
11510x000106A4,
1152 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1153 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1154 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
11550x000106A5,
1156};
1157
1158static inline bool cpu_has_broken_vmx_preemption_timer(void)
1159{
1160 u32 eax = cpuid_eax(0x00000001), i;
1161
1162 /* Clear the reserved bits */
1163 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 1164 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ
1165 if (eax == vmx_preemption_cpu_tfms[i])
1166 return true;
1167
1168 return false;
1169}
1170
1171static inline bool cpu_has_vmx_preemption_timer(void)
1172{
64672c95
YJ
1173 return vmcs_config.pin_based_exec_ctrl &
1174 PIN_BASED_VMX_PREEMPTION_TIMER;
1175}
1176
01e439be
YZ
1177static inline bool cpu_has_vmx_posted_intr(void)
1178{
d6a858d1
PB
1179 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1180 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ
1181}
1182
1183static inline bool cpu_has_vmx_apicv(void)
1184{
1185 return cpu_has_vmx_apic_register_virt() &&
1186 cpu_has_vmx_virtual_intr_delivery() &&
1187 cpu_has_vmx_posted_intr();
1188}
1189
04547156
SY
1190static inline bool cpu_has_vmx_flexpriority(void)
1191{
1192 return cpu_has_vmx_tpr_shadow() &&
1193 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY
1194}
1195
e799794e
MT
1196static inline bool cpu_has_vmx_ept_execute_only(void)
1197{
31299944 1198 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT
1199}
1200
e799794e
MT
1201static inline bool cpu_has_vmx_ept_2m_page(void)
1202{
31299944 1203 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT
1204}
1205
878403b7
SY
1206static inline bool cpu_has_vmx_ept_1g_page(void)
1207{
31299944 1208 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY
1209}
1210
4bc9b982
SY
1211static inline bool cpu_has_vmx_ept_4levels(void)
1212{
1213 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1214}
1215
83c3a331
XH
1216static inline bool cpu_has_vmx_ept_ad_bits(void)
1217{
1218 return vmx_capability.ept & VMX_EPT_AD_BIT;
1219}
1220
31299944 1221static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1222{
31299944 1223 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY
1224}
1225
31299944 1226static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1227{
31299944 1228 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY
1229}
1230
518c8aee
GJ
1231static inline bool cpu_has_vmx_invvpid_single(void)
1232{
1233 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1234}
1235
b9d762fa
GJ
1236static inline bool cpu_has_vmx_invvpid_global(void)
1237{
1238 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1239}
1240
08d839c4
WL
1241static inline bool cpu_has_vmx_invvpid(void)
1242{
1243 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1244}
1245
31299944 1246static inline bool cpu_has_vmx_ept(void)
d56f546d 1247{
04547156
SY
1248 return vmcs_config.cpu_based_2nd_exec_ctrl &
1249 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY
1250}
1251
31299944 1252static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK
1253{
1254 return vmcs_config.cpu_based_2nd_exec_ctrl &
1255 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1256}
1257
31299944 1258static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE
1259{
1260 return vmcs_config.cpu_based_2nd_exec_ctrl &
1261 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1262}
1263
9ac7e3e8
JD
1264static inline bool cpu_has_vmx_basic_inout(void)
1265{
1266 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1267}
1268
35754c98 1269static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1270{
35754c98 1271 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY
1272}
1273
31299944 1274static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1275{
04547156
SY
1276 return vmcs_config.cpu_based_2nd_exec_ctrl &
1277 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY
1278}
1279
31299944 1280static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY
1281{
1282 return vmcs_config.cpu_based_2nd_exec_ctrl &
1283 SECONDARY_EXEC_RDTSCP;
1284}
1285
ad756a16
MJ
1286static inline bool cpu_has_vmx_invpcid(void)
1287{
1288 return vmcs_config.cpu_based_2nd_exec_ctrl &
1289 SECONDARY_EXEC_ENABLE_INVPCID;
1290}
1291
f5f48ee1
SY
1292static inline bool cpu_has_vmx_wbinvd_exit(void)
1293{
1294 return vmcs_config.cpu_based_2nd_exec_ctrl &
1295 SECONDARY_EXEC_WBINVD_EXITING;
1296}
1297
abc4fc58
AG
1298static inline bool cpu_has_vmx_shadow_vmcs(void)
1299{
1300 u64 vmx_msr;
1301 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1302 /* check if the cpu supports writing r/o exit information fields */
1303 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1304 return false;
1305
1306 return vmcs_config.cpu_based_2nd_exec_ctrl &
1307 SECONDARY_EXEC_SHADOW_VMCS;
1308}
1309
843e4330
KH
1310static inline bool cpu_has_vmx_pml(void)
1311{
1312 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1313}
1314
64903d61
HZ
1315static inline bool cpu_has_vmx_tsc_scaling(void)
1316{
1317 return vmcs_config.cpu_based_2nd_exec_ctrl &
1318 SECONDARY_EXEC_TSC_SCALING;
1319}
1320
04547156
SY
1321static inline bool report_flexpriority(void)
1322{
1323 return flexpriority_enabled;
1324}
1325
c7c2c709
JM
1326static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1327{
1328 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1329}
1330
fe3ef05c
NHE
1331static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1332{
1333 return vmcs12->cpu_based_vm_exec_control & bit;
1334}
1335
1336static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1337{
1338 return (vmcs12->cpu_based_vm_exec_control &
1339 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1340 (vmcs12->secondary_vm_exec_control & bit);
1341}
1342
f5c4368f 1343static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE
1344{
1345 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1346}
1347
f4124500
JK
1348static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1349{
1350 return vmcs12->pin_based_vm_exec_control &
1351 PIN_BASED_VMX_PREEMPTION_TIMER;
1352}
1353
155a97a3
NHE
1354static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1355{
1356 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1357}
1358
81dc01f7
WL
1359static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1360{
1361 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1362 vmx_xsaves_supported();
1363}
1364
c5f983f6
BD
1365static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1366{
1367 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1368}
1369
f2b93280
WV
1370static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1371{
1372 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1373}
1374
5c614b35
WL
1375static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1376{
1377 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1378}
1379
82f0dd4b
WV
1380static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1381{
1382 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1383}
1384
608406e2
WV
1385static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1386{
1387 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1388}
1389
705699a1
WV
1390static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1391{
1392 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1393}
1394
ef85b673 1395static inline bool is_nmi(u32 intr_info)
644d711a
NHE
1396{
1397 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
ef85b673 1398 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
644d711a
NHE
1399}
1400
533558bc
JK
1401static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1402 u32 exit_intr_info,
1403 unsigned long exit_qualification);
7c177938
NHE
1404static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1405 struct vmcs12 *vmcs12,
1406 u32 reason, unsigned long qualification);
1407
8b9cf98c 1408static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK
1409{
1410 int i;
1411
a2fa3e9f 1412 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1413 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED
1414 return i;
1415 return -1;
1416}
1417
2384d2b3
SY
1418static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1419{
1420 struct {
1421 u64 vpid : 16;
1422 u64 rsvd : 48;
1423 u64 gva;
1424 } operand = { vpid, 0, gva };
1425
4ecac3fd 1426 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY
1427 /* CF==1 or ZF==1 --> rc = -1 */
1428 "; ja 1f ; ud2 ; 1:"
1429 : : "a"(&operand), "c"(ext) : "cc", "memory");
1430}
1431
1439442c
SY
1432static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1433{
1434 struct {
1435 u64 eptp, gpa;
1436 } operand = {eptp, gpa};
1437
4ecac3fd 1438 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY
1439 /* CF==1 or ZF==1 --> rc = -1 */
1440 "; ja 1f ; ud2 ; 1:\n"
1441 : : "a" (&operand), "c" (ext) : "cc", "memory");
1442}
1443
26bb0981 1444static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED
1445{
1446 int i;
1447
8b9cf98c 1448 i = __find_msr_index(vmx, msr);
a75beee6 1449 if (i >= 0)
a2fa3e9f 1450 return &vmx->guest_msrs[i];
8b6d44c7 1451 return NULL;
7725f0ba
AK
1452}
1453
6aa8b732
AK
1454static void vmcs_clear(struct vmcs *vmcs)
1455{
1456 u64 phys_addr = __pa(vmcs);
1457 u8 error;
1458
4ecac3fd 1459 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1460 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK
1461 : "cc", "memory");
1462 if (error)
1463 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1464 vmcs, phys_addr);
1465}
1466
d462b819
NHE
1467static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1468{
1469 vmcs_clear(loaded_vmcs->vmcs);
355f4fb1
JM
1470 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1471 vmcs_clear(loaded_vmcs->shadow_vmcs);
d462b819
NHE
1472 loaded_vmcs->cpu = -1;
1473 loaded_vmcs->launched = 0;
1474}
1475
7725b894
DX
1476static void vmcs_load(struct vmcs *vmcs)
1477{
1478 u64 phys_addr = __pa(vmcs);
1479 u8 error;
1480
1481 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1482 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX
1483 : "cc", "memory");
1484 if (error)
2844d849 1485 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX
1486 vmcs, phys_addr);
1487}
1488
2965faa5 1489#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY
1490/*
1491 * This bitmap is used to indicate whether the vmclear
1492 * operation is enabled on all cpus. All disabled by
1493 * default.
1494 */
1495static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1496
1497static inline void crash_enable_local_vmclear(int cpu)
1498{
1499 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1500}
1501
1502static inline void crash_disable_local_vmclear(int cpu)
1503{
1504 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1505}
1506
1507static inline int crash_local_vmclear_enabled(int cpu)
1508{
1509 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1510}
1511
1512static void crash_vmclear_local_loaded_vmcss(void)
1513{
1514 int cpu = raw_smp_processor_id();
1515 struct loaded_vmcs *v;
1516
1517 if (!crash_local_vmclear_enabled(cpu))
1518 return;
1519
1520 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1521 loaded_vmcss_on_cpu_link)
1522 vmcs_clear(v->vmcs);
1523}
1524#else
1525static inline void crash_enable_local_vmclear(int cpu) { }
1526static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1527#endif /* CONFIG_KEXEC_CORE */
8f536b76 1528
d462b819 1529static void __loaded_vmcs_clear(void *arg)
6aa8b732 1530{
d462b819 1531 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1532 int cpu = raw_smp_processor_id();
6aa8b732 1533
d462b819
NHE
1534 if (loaded_vmcs->cpu != cpu)
1535 return; /* vcpu migration can race with cpu offline */
1536 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1537 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1538 crash_disable_local_vmclear(cpu);
d462b819 1539 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG
1540
1541 /*
1542 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1543 * is before setting loaded_vmcs->vcpu to -1 which is done in
1544 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1545 * then adds the vmcs into percpu list before it is deleted.
1546 */
1547 smp_wmb();
1548
d462b819 1549 loaded_vmcs_init(loaded_vmcs);
8f536b76 1550 crash_enable_local_vmclear(cpu);
6aa8b732
AK
1551}
1552
d462b819 1553static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1554{
e6c7d321
XG
1555 int cpu = loaded_vmcs->cpu;
1556
1557 if (cpu != -1)
1558 smp_call_function_single(cpu,
1559 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK
1560}
1561
dd5f5341 1562static inline void vpid_sync_vcpu_single(int vpid)
2384d2b3 1563{
dd5f5341 1564 if (vpid == 0)
2384d2b3
SY
1565 return;
1566
518c8aee 1567 if (cpu_has_vmx_invvpid_single())
dd5f5341 1568 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
2384d2b3
SY
1569}
1570
b9d762fa
GJ
1571static inline void vpid_sync_vcpu_global(void)
1572{
1573 if (cpu_has_vmx_invvpid_global())
1574 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1575}
1576
dd5f5341 1577static inline void vpid_sync_context(int vpid)
b9d762fa
GJ
1578{
1579 if (cpu_has_vmx_invvpid_single())
dd5f5341 1580 vpid_sync_vcpu_single(vpid);
b9d762fa
GJ
1581 else
1582 vpid_sync_vcpu_global();
1583}
1584
1439442c
SY
1585static inline void ept_sync_global(void)
1586{
1587 if (cpu_has_vmx_invept_global())
1588 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1589}
1590
1591static inline void ept_sync_context(u64 eptp)
1592{
089d034e 1593 if (enable_ept) {
1439442c
SY
1594 if (cpu_has_vmx_invept_context())
1595 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1596 else
1597 ept_sync_global();
1598 }
1599}
1600
8a86aea9
PB
1601static __always_inline void vmcs_check16(unsigned long field)
1602{
1603 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1604 "16-bit accessor invalid for 64-bit field");
1605 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1606 "16-bit accessor invalid for 64-bit high field");
1607 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1608 "16-bit accessor invalid for 32-bit high field");
1609 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1610 "16-bit accessor invalid for natural width field");
1611}
1612
1613static __always_inline void vmcs_check32(unsigned long field)
1614{
1615 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1616 "32-bit accessor invalid for 16-bit field");
1617 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1618 "32-bit accessor invalid for natural width field");
1619}
1620
1621static __always_inline void vmcs_check64(unsigned long field)
1622{
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1624 "64-bit accessor invalid for 16-bit field");
1625 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1626 "64-bit accessor invalid for 64-bit high field");
1627 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1628 "64-bit accessor invalid for 32-bit field");
1629 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1630 "64-bit accessor invalid for natural width field");
1631}
1632
1633static __always_inline void vmcs_checkl(unsigned long field)
1634{
1635 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1636 "Natural width accessor invalid for 16-bit field");
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1638 "Natural width accessor invalid for 64-bit field");
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1640 "Natural width accessor invalid for 64-bit high field");
1641 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1642 "Natural width accessor invalid for 32-bit field");
1643}
1644
1645static __always_inline unsigned long __vmcs_readl(unsigned long field)
6aa8b732 1646{
5e520e62 1647 unsigned long value;
6aa8b732 1648
5e520e62
AK
1649 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1650 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK
1651 return value;
1652}
1653
96304217 1654static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732 1655{
8a86aea9
PB
1656 vmcs_check16(field);
1657 return __vmcs_readl(field);
6aa8b732
AK
1658}
1659
96304217 1660static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732 1661{
8a86aea9
PB
1662 vmcs_check32(field);
1663 return __vmcs_readl(field);
6aa8b732
AK
1664}
1665
96304217 1666static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1667{
8a86aea9 1668 vmcs_check64(field);
05b3e0c2 1669#ifdef CONFIG_X86_64
8a86aea9 1670 return __vmcs_readl(field);
6aa8b732 1671#else
8a86aea9 1672 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
6aa8b732
AK
1673#endif
1674}
1675
8a86aea9
PB
1676static __always_inline unsigned long vmcs_readl(unsigned long field)
1677{
1678 vmcs_checkl(field);
1679 return __vmcs_readl(field);
1680}
1681
e52de1b8
AK
1682static noinline void vmwrite_error(unsigned long field, unsigned long value)
1683{
1684 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1685 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1686 dump_stack();
1687}
1688
8a86aea9 1689static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
6aa8b732
AK
1690{
1691 u8 error;
1692
4ecac3fd 1693 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1694 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK
1695 if (unlikely(error))
1696 vmwrite_error(field, value);
6aa8b732
AK
1697}
1698
8a86aea9 1699static __always_inline void vmcs_write16(unsigned long field, u16 value)
6aa8b732 1700{
8a86aea9
PB
1701 vmcs_check16(field);
1702 __vmcs_writel(field, value);
6aa8b732
AK
1703}
1704
8a86aea9 1705static __always_inline void vmcs_write32(unsigned long field, u32 value)
6aa8b732 1706{
8a86aea9
PB
1707 vmcs_check32(field);
1708 __vmcs_writel(field, value);
6aa8b732
AK
1709}
1710
8a86aea9 1711static __always_inline void vmcs_write64(unsigned long field, u64 value)
6aa8b732 1712{
8a86aea9
PB
1713 vmcs_check64(field);
1714 __vmcs_writel(field, value);
7682f2d0 1715#ifndef CONFIG_X86_64
6aa8b732 1716 asm volatile ("");
8a86aea9 1717 __vmcs_writel(field+1, value >> 32);
6aa8b732
AK
1718#endif
1719}
1720
8a86aea9 1721static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2ab455cc 1722{
8a86aea9
PB
1723 vmcs_checkl(field);
1724 __vmcs_writel(field, value);
2ab455cc
AL
1725}
1726
8a86aea9 1727static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2ab455cc 1728{
8a86aea9
PB
1729 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1730 "vmcs_clear_bits does not support 64-bit fields");
1731 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2ab455cc
AL
1732}
1733
8a86aea9 1734static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2ab455cc 1735{
8a86aea9
PB
1736 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1737 "vmcs_set_bits does not support 64-bit fields");
1738 __vmcs_writel(field, __vmcs_readl(field) | mask);
2ab455cc
AL
1739}
1740
8391ce44
PB
1741static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1742{
1743 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1744}
1745
2961e876
GN
1746static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1747{
1748 vmcs_write32(VM_ENTRY_CONTROLS, val);
1749 vmx->vm_entry_controls_shadow = val;
1750}
1751
1752static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1753{
1754 if (vmx->vm_entry_controls_shadow != val)
1755 vm_entry_controls_init(vmx, val);
1756}
1757
1758static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1759{
1760 return vmx->vm_entry_controls_shadow;
1761}
1762
1763
1764static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1765{
1766 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1767}
1768
1769static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1770{
1771 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1772}
1773
8391ce44
PB
1774static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1775{
1776 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1777}
1778
2961e876
GN
1779static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1780{
1781 vmcs_write32(VM_EXIT_CONTROLS, val);
1782 vmx->vm_exit_controls_shadow = val;
1783}
1784
1785static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1786{
1787 if (vmx->vm_exit_controls_shadow != val)
1788 vm_exit_controls_init(vmx, val);
1789}
1790
1791static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1792{
1793 return vmx->vm_exit_controls_shadow;
1794}
1795
1796
1797static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1798{
1799 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1800}
1801
1802static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1803{
1804 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1805}
1806
2fb92db1
AK
1807static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1808{
1809 vmx->segment_cache.bitmask = 0;
1810}
1811
1812static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1813 unsigned field)
1814{
1815 bool ret;
1816 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1817
1818 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1819 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1820 vmx->segment_cache.bitmask = 0;
1821 }
1822 ret = vmx->segment_cache.bitmask & mask;
1823 vmx->segment_cache.bitmask |= mask;
1824 return ret;
1825}
1826
1827static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1828{
1829 u16 *p = &vmx->segment_cache.seg[seg].selector;
1830
1831 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1832 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1833 return *p;
1834}
1835
1836static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1837{
1838 ulong *p = &vmx->segment_cache.seg[seg].base;
1839
1840 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1841 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1842 return *p;
1843}
1844
1845static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1846{
1847 u32 *p = &vmx->segment_cache.seg[seg].limit;
1848
1849 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1850 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1851 return *p;
1852}
1853
1854static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1855{
1856 u32 *p = &vmx->segment_cache.seg[seg].ar;
1857
1858 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1859 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1860 return *p;
1861}
1862
abd3f2d6
AK
1863static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1864{
1865 u32 eb;
1866
fd7373cc 1867 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 1868 (1u << DB_VECTOR) | (1u << AC_VECTOR);
fd7373cc
JK
1869 if ((vcpu->guest_debug &
1870 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1871 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1872 eb |= 1u << BP_VECTOR;
7ffd92c5 1873 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1874 eb = ~0;
089d034e 1875 if (enable_ept)
1439442c 1876 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE
1877
1878 /* When we are running a nested L2 guest and L1 specified for it a
1879 * certain exception bitmap, we must trap the same exceptions and pass
1880 * them to L1. When running L2, we will only handle the exceptions
1881 * specified above if L1 did not want them.
1882 */
1883 if (is_guest_mode(vcpu))
1884 eb |= get_vmcs12(vcpu)->exception_bitmap;
1885
abd3f2d6
AK
1886 vmcs_write32(EXCEPTION_BITMAP, eb);
1887}
1888
2961e876
GN
1889static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1890 unsigned long entry, unsigned long exit)
8bf00a52 1891{
2961e876
GN
1892 vm_entry_controls_clearbit(vmx, entry);
1893 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN
1894}
1895
61d2ef2c
AK
1896static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1897{
1898 unsigned i;
1899 struct msr_autoload *m = &vmx->msr_autoload;
1900
8bf00a52
GN
1901 switch (msr) {
1902 case MSR_EFER:
1903 if (cpu_has_load_ia32_efer) {
2961e876
GN
1904 clear_atomic_switch_msr_special(vmx,
1905 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN
1906 VM_EXIT_LOAD_IA32_EFER);
1907 return;
1908 }
1909 break;
1910 case MSR_CORE_PERF_GLOBAL_CTRL:
1911 if (cpu_has_load_perf_global_ctrl) {
2961e876 1912 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN
1913 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1914 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1915 return;
1916 }
1917 break;
110312c8
AK
1918 }
1919
61d2ef2c
AK
1920 for (i = 0; i < m->nr; ++i)
1921 if (m->guest[i].index == msr)
1922 break;
1923
1924 if (i == m->nr)
1925 return;
1926 --m->nr;
1927 m->guest[i] = m->guest[m->nr];
1928 m->host[i] = m->host[m->nr];
1929 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1930 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1931}
1932
2961e876
GN
1933static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1934 unsigned long entry, unsigned long exit,
1935 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1936 u64 guest_val, u64 host_val)
8bf00a52
GN
1937{
1938 vmcs_write64(guest_val_vmcs, guest_val);
1939 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN
1940 vm_entry_controls_setbit(vmx, entry);
1941 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN
1942}
1943
61d2ef2c
AK
1944static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1945 u64 guest_val, u64 host_val)
1946{
1947 unsigned i;
1948 struct msr_autoload *m = &vmx->msr_autoload;
1949
8bf00a52
GN
1950 switch (msr) {
1951 case MSR_EFER:
1952 if (cpu_has_load_ia32_efer) {
2961e876
GN
1953 add_atomic_switch_msr_special(vmx,
1954 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN
1955 VM_EXIT_LOAD_IA32_EFER,
1956 GUEST_IA32_EFER,
1957 HOST_IA32_EFER,
1958 guest_val, host_val);
1959 return;
1960 }
1961 break;
1962 case MSR_CORE_PERF_GLOBAL_CTRL:
1963 if (cpu_has_load_perf_global_ctrl) {
2961e876 1964 add_atomic_switch_msr_special(vmx,
8bf00a52
GN
1965 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1966 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1967 GUEST_IA32_PERF_GLOBAL_CTRL,
1968 HOST_IA32_PERF_GLOBAL_CTRL,
1969 guest_val, host_val);
1970 return;
1971 }
1972 break;
7099e2e1
RK
1973 case MSR_IA32_PEBS_ENABLE:
1974 /* PEBS needs a quiescent period after being disabled (to write
1975 * a record). Disabling PEBS through VMX MSR swapping doesn't
1976 * provide that period, so a CPU could write host's record into
1977 * guest's memory.
1978 */
1979 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK
1980 }
1981
61d2ef2c
AK
1982 for (i = 0; i < m->nr; ++i)
1983 if (m->guest[i].index == msr)
1984 break;
1985
e7fc6f93 1986 if (i == NR_AUTOLOAD_MSRS) {
60266204 1987 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN
1988 "Can't add msr %x\n", msr);
1989 return;
1990 } else if (i == m->nr) {
61d2ef2c
AK
1991 ++m->nr;
1992 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1993 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1994 }
1995
1996 m->guest[i].index = msr;
1997 m->guest[i].value = guest_val;
1998 m->host[i].index = msr;
1999 m->host[i].value = host_val;
2000}
2001
92c0d900 2002static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 2003{
844a5fe2
PB
2004 u64 guest_efer = vmx->vcpu.arch.efer;
2005 u64 ignore_bits = 0;
2006
2007 if (!enable_ept) {
2008 /*
2009 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2010 * host CPUID is more efficient than testing guest CPUID
2011 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2012 */
2013 if (boot_cpu_has(X86_FEATURE_SMEP))
2014 guest_efer |= EFER_NX;
2015 else if (!(guest_efer & EFER_NX))
2016 ignore_bits |= EFER_NX;
2017 }
3a34a881 2018
51c6cf66 2019 /*
844a5fe2 2020 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 2021 */
844a5fe2 2022 ignore_bits |= EFER_SCE;
51c6cf66
AK
2023#ifdef CONFIG_X86_64
2024 ignore_bits |= EFER_LMA | EFER_LME;
2025 /* SCE is meaningful only in long mode on Intel */
2026 if (guest_efer & EFER_LMA)
2027 ignore_bits &= ~(u64)EFER_SCE;
2028#endif
84ad33ef
AK
2029
2030 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL
2031
2032 /*
2033 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2034 * On CPUs that support "load IA32_EFER", always switch EFER
2035 * atomically, since it's faster than switching it manually.
2036 */
2037 if (cpu_has_load_ia32_efer ||
2038 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK
2039 if (!(guest_efer & EFER_LMA))
2040 guest_efer &= ~EFER_LME;
54b98bff
AL
2041 if (guest_efer != host_efer)
2042 add_atomic_switch_msr(vmx, MSR_EFER,
2043 guest_efer, host_efer);
84ad33ef 2044 return false;
844a5fe2
PB
2045 } else {
2046 guest_efer &= ~ignore_bits;
2047 guest_efer |= host_efer & ignore_bits;
2048
2049 vmx->guest_msrs[efer_offset].data = guest_efer;
2050 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 2051
844a5fe2
PB
2052 return true;
2053 }
51c6cf66
AK
2054}
2055
e28baead
AL
2056#ifdef CONFIG_X86_32
2057/*
2058 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2059 * VMCS rather than the segment table. KVM uses this helper to figure
2060 * out the current bases to poke them into the VMCS before entry.
2061 */
2d49ec72
GN
2062static unsigned long segment_base(u16 selector)
2063{
8c2e41f7 2064 struct desc_struct *table;
2d49ec72
GN
2065 unsigned long v;
2066
8c2e41f7 2067 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN
2068 return 0;
2069
45fc8757 2070 table = get_current_gdt_ro();
2d49ec72 2071
8c2e41f7 2072 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN
2073 u16 ldt_selector = kvm_read_ldt();
2074
8c2e41f7 2075 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN
2076 return 0;
2077
8c2e41f7 2078 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 2079 }
8c2e41f7 2080 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN
2081 return v;
2082}
e28baead 2083#endif
2d49ec72 2084
04d2cc77 2085static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 2086{
04d2cc77 2087 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2088 int i;
04d2cc77 2089
a2fa3e9f 2090 if (vmx->host_state.loaded)
33ed6329
AK
2091 return;
2092
a2fa3e9f 2093 vmx->host_state.loaded = 1;
33ed6329
AK
2094 /*
2095 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2096 * allow segment selectors with cpl > 0 or ti == 1.
2097 */
d6e88aec 2098 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 2099 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 2100 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 2101 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 2102 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV
2103 vmx->host_state.fs_reload_needed = 0;
2104 } else {
33ed6329 2105 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 2106 vmx->host_state.fs_reload_needed = 1;
33ed6329 2107 }
9581d442 2108 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH
2109 if (!(vmx->host_state.gs_sel & 7))
2110 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK
2111 else {
2112 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 2113 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK
2114 }
2115
b2da15ac
AK
2116#ifdef CONFIG_X86_64
2117 savesegment(ds, vmx->host_state.ds_sel);
2118 savesegment(es, vmx->host_state.es_sel);
2119#endif
2120
33ed6329
AK
2121#ifdef CONFIG_X86_64
2122 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2123 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2124#else
a2fa3e9f
GH
2125 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2126 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 2127#endif
707c0874
AK
2128
2129#ifdef CONFIG_X86_64
c8770e7b
AK
2130 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2131 if (is_long_mode(&vmx->vcpu))
44ea2b17 2132 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 2133#endif
da8999d3
LJ
2134 if (boot_cpu_has(X86_FEATURE_MPX))
2135 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK
2136 for (i = 0; i < vmx->save_nmsrs; ++i)
2137 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK
2138 vmx->guest_msrs[i].data,
2139 vmx->guest_msrs[i].mask);
33ed6329
AK
2140}
2141
a9b21b62 2142static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 2143{
a2fa3e9f 2144 if (!vmx->host_state.loaded)
33ed6329
AK
2145 return;
2146
e1beb1d3 2147 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 2148 vmx->host_state.loaded = 0;
c8770e7b
AK
2149#ifdef CONFIG_X86_64
2150 if (is_long_mode(&vmx->vcpu))
2151 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2152#endif
152d3f2f 2153 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 2154 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 2155#ifdef CONFIG_X86_64
9581d442 2156 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK
2157#else
2158 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 2159#endif
33ed6329 2160 }
0a77fe4c
AK
2161 if (vmx->host_state.fs_reload_needed)
2162 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK
2163#ifdef CONFIG_X86_64
2164 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2165 loadsegment(ds, vmx->host_state.ds_sel);
2166 loadsegment(es, vmx->host_state.es_sel);
2167 }
b2da15ac 2168#endif
b7ffc44d 2169 invalidate_tss_limit();
44ea2b17 2170#ifdef CONFIG_X86_64
c8770e7b 2171 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 2172#endif
da8999d3
LJ
2173 if (vmx->host_state.msr_host_bndcfgs)
2174 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
45fc8757 2175 load_fixmap_gdt(raw_smp_processor_id());
33ed6329
AK
2176}
2177
a9b21b62
AK
2178static void vmx_load_host_state(struct vcpu_vmx *vmx)
2179{
2180 preempt_disable();
2181 __vmx_load_host_state(vmx);
2182 preempt_enable();
2183}
2184
28b835d6
FW
2185static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2186{
2187 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2188 struct pi_desc old, new;
2189 unsigned int dest;
2190
2191 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
2192 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2193 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW
2194 return;
2195
2196 do {
2197 old.control = new.control = pi_desc->control;
2198
2199 /*
2200 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2201 * are two possible cases:
2202 * 1. After running 'pre_block', context switch
2203 * happened. For this case, 'sn' was set in
2204 * vmx_vcpu_put(), so we need to clear it here.
2205 * 2. After running 'pre_block', we were blocked,
2206 * and woken up by some other guy. For this case,
2207 * we don't need to do anything, 'pi_post_block'
2208 * will do everything for us. However, we cannot
2209 * check whether it is case #1 or case #2 here
2210 * (maybe, not needed), so we also clear sn here,
2211 * I think it is not a big deal.
2212 */
2213 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2214 if (vcpu->cpu != cpu) {
2215 dest = cpu_physical_id(cpu);
2216
2217 if (x2apic_enabled())
2218 new.ndst = dest;
2219 else
2220 new.ndst = (dest << 8) & 0xFF00;
2221 }
2222
2223 /* set 'NV' to 'notification vector' */
2224 new.nv = POSTED_INTR_VECTOR;
2225 }
2226
2227 /* Allow posting non-urgent interrupts */
2228 new.sn = 0;
2229 } while (cmpxchg(&pi_desc->control, old.control,
2230 new.control) != old.control);
2231}
1be0e61c 2232
c95ba92a
PF
2233static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2234{
2235 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2236 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2237}
2238
6aa8b732
AK
2239/*
2240 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2241 * vcpu mutex is already taken.
2242 */
15ad7146 2243static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 2244{
a2fa3e9f 2245 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 2246 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 2247
b80c76ec 2248 if (!already_loaded) {
fe0e80be 2249 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 2250 local_irq_disable();
8f536b76 2251 crash_disable_local_vmclear(cpu);
5a560f8b
XG
2252
2253 /*
2254 * Read loaded_vmcs->cpu should be before fetching
2255 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2256 * See the comments in __loaded_vmcs_clear().
2257 */
2258 smp_rmb();
2259
d462b819
NHE
2260 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2261 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 2262 crash_enable_local_vmclear(cpu);
92fe13be 2263 local_irq_enable();
b80c76ec
JM
2264 }
2265
2266 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2267 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2268 vmcs_load(vmx->loaded_vmcs->vmcs);
2269 }
2270
2271 if (!already_loaded) {
59c58ceb 2272 void *gdt = get_current_gdt_ro();
b80c76ec
JM
2273 unsigned long sysenter_esp;
2274
2275 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 2276
6aa8b732
AK
2277 /*
2278 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 2279 * processors. See 22.2.4.
6aa8b732 2280 */
e0c23063
AL
2281 vmcs_writel(HOST_TR_BASE,
2282 (unsigned long)this_cpu_ptr(&cpu_tss));
59c58ceb 2283 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732 2284
b7ffc44d
AL
2285 /*
2286 * VM exits change the host TR limit to 0x67 after a VM
2287 * exit. This is okay, since 0x67 covers everything except
2288 * the IO bitmap and have have code to handle the IO bitmap
2289 * being lost after a VM exit.
2290 */
2291 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2292
6aa8b732
AK
2293 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2294 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 2295
d462b819 2296 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 2297 }
28b835d6 2298
2680d6da
OH
2299 /* Setup TSC multiplier */
2300 if (kvm_has_tsc_control &&
c95ba92a
PF
2301 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2302 decache_tsc_multiplier(vmx);
2680d6da 2303
28b835d6 2304 vmx_vcpu_pi_load(vcpu, cpu);
1be0e61c 2305 vmx->host_pkru = read_pkru();
28b835d6
FW
2306}
2307
2308static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2309{
2310 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2311
2312 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
2313 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2314 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW
2315 return;
2316
2317 /* Set SN when the vCPU is preempted */
2318 if (vcpu->preempted)
2319 pi_set_sn(pi_desc);
6aa8b732
AK
2320}
2321
2322static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2323{
28b835d6
FW
2324 vmx_vcpu_pi_put(vcpu);
2325
a9b21b62 2326 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK
2327}
2328
edcafe3c
AK
2329static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2330
fe3ef05c
NHE
2331/*
2332 * Return the cr0 value that a nested guest would read. This is a combination
2333 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2334 * its hypervisor (cr0_read_shadow).
2335 */
2336static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2337{
2338 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2339 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2340}
2341static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2342{
2343 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2344 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2345}
2346
6aa8b732
AK
2347static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2348{
78ac8b47 2349 unsigned long rflags, save_rflags;
345dcaa8 2350
6de12732
AK
2351 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2352 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2353 rflags = vmcs_readl(GUEST_RFLAGS);
2354 if (to_vmx(vcpu)->rmode.vm86_active) {
2355 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2356 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2357 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2358 }
2359 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2360 }
6de12732 2361 return to_vmx(vcpu)->rflags;
6aa8b732
AK
2362}
2363
2364static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2365{
6de12732
AK
2366 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2367 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK
2368 if (to_vmx(vcpu)->rmode.vm86_active) {
2369 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2370 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2371 }
6aa8b732
AK
2372 vmcs_writel(GUEST_RFLAGS, rflags);
2373}
2374
be94f6b7
HH
2375static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2376{
2377 return to_vmx(vcpu)->guest_pkru;
2378}
2379
37ccdcbe 2380static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC
2381{
2382 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2383 int ret = 0;
2384
2385 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2386 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2387 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2388 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2389
37ccdcbe 2390 return ret;
2809f5d2
GC
2391}
2392
2393static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2394{
2395 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2396 u32 interruptibility = interruptibility_old;
2397
2398 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2399
48005f64 2400 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2401 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2402 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC
2403 interruptibility |= GUEST_INTR_STATE_STI;
2404
2405 if ((interruptibility != interruptibility_old))
2406 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2407}
2408
6aa8b732
AK
2409static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2410{
2411 unsigned long rip;
6aa8b732 2412
5fdbf976 2413 rip = kvm_rip_read(vcpu);
6aa8b732 2414 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2415 kvm_rip_write(vcpu, rip);
6aa8b732 2416
2809f5d2
GC
2417 /* skipping an emulated instruction also counts */
2418 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK
2419}
2420
0b6ac343
NHE
2421/*
2422 * KVM wants to inject page-faults which it got to the guest. This function
2423 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2424 */
e011c663 2425static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE
2426{
2427 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2428
e011c663 2429 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE
2430 return 0;
2431
d4912215 2432 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
533558bc
JK
2433 vmcs_read32(VM_EXIT_INTR_INFO),
2434 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE
2435 return 1;
2436}
2437
298101da 2438static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR
2439 bool has_error_code, u32 error_code,
2440 bool reinject)
298101da 2441{
77ab6db0 2442 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2443 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2444
e011c663
GN
2445 if (!reinject && is_guest_mode(vcpu) &&
2446 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE
2447 return;
2448
8ab2d2e2 2449 if (has_error_code) {
77ab6db0 2450 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK
2451 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2452 }
77ab6db0 2453
7ffd92c5 2454 if (vmx->rmode.vm86_active) {
71f9833b
SH
2455 int inc_eip = 0;
2456 if (kvm_exception_is_soft(nr))
2457 inc_eip = vcpu->arch.event_exit_inst_len;
2458 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2459 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK
2460 return;
2461 }
2462
66fd3f7f
GN
2463 if (kvm_exception_is_soft(nr)) {
2464 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2465 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK
2466 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2467 } else
2468 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2469
2470 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK
2471}
2472
4e47c7a6
SY
2473static bool vmx_rdtscp_supported(void)
2474{
2475 return cpu_has_vmx_rdtscp();
2476}
2477
ad756a16
MJ
2478static bool vmx_invpcid_supported(void)
2479{
2480 return cpu_has_vmx_invpcid() && enable_ept;
2481}
2482
a75beee6
ED
2483/*
2484 * Swap MSR entry in host/guest MSR entry array.
2485 */
8b9cf98c 2486static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2487{
26bb0981 2488 struct shared_msr_entry tmp;
a2fa3e9f
GH
2489
2490 tmp = vmx->guest_msrs[to];
2491 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2492 vmx->guest_msrs[from] = tmp;
a75beee6
ED
2493}
2494
8d14695f
YZ
2495static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2496{
2497 unsigned long *msr_bitmap;
2498
670125bd 2499 if (is_guest_mode(vcpu))
d048c098 2500 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
3ce424e4
RK
2501 else if (cpu_has_secondary_exec_ctrls() &&
2502 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2503 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
f6e90f9e
WL
2504 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2505 if (is_long_mode(vcpu))
c63e4563 2506 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
f6e90f9e 2507 else
c63e4563 2508 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
f6e90f9e
WL
2509 } else {
2510 if (is_long_mode(vcpu))
c63e4563 2511 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
f6e90f9e 2512 else
c63e4563 2513 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
f6e90f9e 2514 }
8d14695f
YZ
2515 } else {
2516 if (is_long_mode(vcpu))
2517 msr_bitmap = vmx_msr_bitmap_longmode;
2518 else
2519 msr_bitmap = vmx_msr_bitmap_legacy;
2520 }
2521
2522 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2523}
2524
e38aea3e
AK
2525/*
2526 * Set up the vmcs to automatically save and restore system
2527 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2528 * mode, as fiddling with msrs is very expensive.
2529 */
8b9cf98c 2530static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2531{
26bb0981 2532 int save_nmsrs, index;
e38aea3e 2533
a75beee6
ED
2534 save_nmsrs = 0;
2535#ifdef CONFIG_X86_64
8b9cf98c 2536 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2537 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2538 if (index >= 0)
8b9cf98c
RR
2539 move_msr_up(vmx, index, save_nmsrs++);
2540 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2541 if (index >= 0)
8b9cf98c
RR
2542 move_msr_up(vmx, index, save_nmsrs++);
2543 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2544 if (index >= 0)
8b9cf98c 2545 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6 2546 index = __find_msr_index(vmx, MSR_TSC_AUX);
1cea0ce6 2547 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
4e47c7a6 2548 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2549 /*
8c06585d 2550 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED
2551 * if efer.sce is enabled.
2552 */
8c06585d 2553 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2554 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2555 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED
2556 }
2557#endif
92c0d900
AK
2558 index = __find_msr_index(vmx, MSR_EFER);
2559 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2560 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2561
26bb0981 2562 vmx->save_nmsrs = save_nmsrs;
5897297b 2563
8d14695f
YZ
2564 if (cpu_has_vmx_msr_bitmap())
2565 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK
2566}
2567
6aa8b732
AK
2568/*
2569 * reads and returns guest's timestamp counter "register"
be7b263e
HZ
2570 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2571 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
6aa8b732 2572 */
be7b263e 2573static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
6aa8b732
AK
2574{
2575 u64 host_tsc, tsc_offset;
2576
4ea1636b 2577 host_tsc = rdtsc();
6aa8b732 2578 tsc_offset = vmcs_read64(TSC_OFFSET);
be7b263e 2579 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
6aa8b732
AK
2580}
2581
2582/*
99e3e30a 2583 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2584 */
99e3e30a 2585static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2586{
27fc51b2 2587 if (is_guest_mode(vcpu)) {
7991825b 2588 /*
27fc51b2
NHE
2589 * We're here if L1 chose not to trap WRMSR to TSC. According
2590 * to the spec, this should set L1's TSC; The offset that L1
2591 * set for L2 remains unchanged, and still needs to be added
2592 * to the newly set TSC to get L2's TSC.
7991825b 2593 */
27fc51b2 2594 struct vmcs12 *vmcs12;
27fc51b2
NHE
2595 /* recalculate vmcs02.TSC_OFFSET: */
2596 vmcs12 = get_vmcs12(vcpu);
2597 vmcs_write64(TSC_OFFSET, offset +
2598 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2599 vmcs12->tsc_offset : 0));
2600 } else {
489223ed
YY
2601 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2602 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE
2603 vmcs_write64(TSC_OFFSET, offset);
2604 }
6aa8b732
AK
2605}
2606
801d3424
NHE
2607static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2608{
2609 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2610 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2611}
2612
2613/*
2614 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2615 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2616 * all guests if the "nested" module option is off, and can also be disabled
2617 * for a single guest by disabling its VMX cpuid bit.
2618 */
2619static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2620{
2621 return nested && guest_cpuid_has_vmx(vcpu);
2622}
2623
b87a51ae
NHE
2624/*
2625 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2626 * returned for the various VMX controls MSRs when nested VMX is enabled.
2627 * The same values should also be used to verify that vmcs12 control fields are
2628 * valid during nested entry from L1 to L2.
2629 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2630 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2631 * bit in the high half is on if the corresponding bit in the control field
2632 * may be on. See also vmx_control_verify().
b87a51ae 2633 */
b9c237bb 2634static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE
2635{
2636 /*
2637 * Note that as a general rule, the high half of the MSRs (bits in
2638 * the control fields which may be 1) should be initialized by the
2639 * intersection of the underlying hardware's MSR (i.e., features which
2640 * can be supported) and the list of features we want to expose -
2641 * because they are known to be properly supported in our code.
2642 * Also, usually, the low half of the MSRs (bits which must be 1) can
2643 * be set to 0, meaning that L1 may turn off any of these bits. The
2644 * reason is that if one of these bits is necessary, it will appear
2645 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2646 * fields of vmcs01 and vmcs02, will turn these bits off - and
2647 * nested_vmx_exit_handled() will not pass related exits to L1.
2648 * These rules have exceptions below.
2649 */
2650
2651 /* pin-based controls */
eabeaacc 2652 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV
2653 vmx->nested.nested_vmx_pinbased_ctls_low,
2654 vmx->nested.nested_vmx_pinbased_ctls_high);
2655 vmx->nested.nested_vmx_pinbased_ctls_low |=
2656 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2657 vmx->nested.nested_vmx_pinbased_ctls_high &=
2658 PIN_BASED_EXT_INTR_MASK |
2659 PIN_BASED_NMI_EXITING |
2660 PIN_BASED_VIRTUAL_NMIS;
2661 vmx->nested.nested_vmx_pinbased_ctls_high |=
2662 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2663 PIN_BASED_VMX_PREEMPTION_TIMER;
d62caabb 2664 if (kvm_vcpu_apicv_active(&vmx->vcpu))
705699a1
WV
2665 vmx->nested.nested_vmx_pinbased_ctls_high |=
2666 PIN_BASED_POSTED_INTR;
b87a51ae 2667
3dbcd8da 2668 /* exit controls */
c0dfee58 2669 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV
2670 vmx->nested.nested_vmx_exit_ctls_low,
2671 vmx->nested.nested_vmx_exit_ctls_high);
2672 vmx->nested.nested_vmx_exit_ctls_low =
2673 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2674
b9c237bb 2675 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2676#ifdef CONFIG_X86_64
c0dfee58 2677 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2678#endif
f4124500 2679 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV
2680 vmx->nested.nested_vmx_exit_ctls_high |=
2681 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2682 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD
2683 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2684
a87036ad 2685 if (kvm_mpx_supported())
b9c237bb 2686 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2687
2996fca0 2688 /* We support free control of debug control saving. */
0115f9cb 2689 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2996fca0 2690
b87a51ae
NHE
2691 /* entry controls */
2692 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV
2693 vmx->nested.nested_vmx_entry_ctls_low,
2694 vmx->nested.nested_vmx_entry_ctls_high);
2695 vmx->nested.nested_vmx_entry_ctls_low =
2696 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2697 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK
2698#ifdef CONFIG_X86_64
2699 VM_ENTRY_IA32E_MODE |
2700#endif
2701 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV
2702 vmx->nested.nested_vmx_entry_ctls_high |=
2703 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
a87036ad 2704 if (kvm_mpx_supported())
b9c237bb 2705 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2706
2996fca0 2707 /* We support free control of debug control loading. */
0115f9cb 2708 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2996fca0 2709
b87a51ae
NHE
2710 /* cpu-based controls */
2711 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV
2712 vmx->nested.nested_vmx_procbased_ctls_low,
2713 vmx->nested.nested_vmx_procbased_ctls_high);
2714 vmx->nested.nested_vmx_procbased_ctls_low =
2715 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2716 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK
2717 CPU_BASED_VIRTUAL_INTR_PENDING |
2718 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE
2719 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2720 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2721 CPU_BASED_CR3_STORE_EXITING |
2722#ifdef CONFIG_X86_64
2723 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2724#endif
2725 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD
2726 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2727 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2728 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2729 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE
2730 /*
2731 * We can allow some features even when not supported by the
2732 * hardware. For example, L1 can specify an MSR bitmap - and we
2733 * can use it to avoid exits to L1 - even when L0 runs L2
2734 * without MSR bitmaps.
2735 */
b9c237bb
WV
2736 vmx->nested.nested_vmx_procbased_ctls_high |=
2737 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2738 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2739
3dcdf3ec 2740 /* We support free control of CR3 access interception. */
0115f9cb 2741 vmx->nested.nested_vmx_procbased_ctls_low &=
3dcdf3ec
JK
2742 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2743
b87a51ae
NHE
2744 /* secondary cpu-based controls */
2745 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV
2746 vmx->nested.nested_vmx_secondary_ctls_low,
2747 vmx->nested.nested_vmx_secondary_ctls_high);
2748 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2749 vmx->nested.nested_vmx_secondary_ctls_high &=
a5f46457 2750 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
d6851fbe 2751 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2752 SECONDARY_EXEC_RDTSCP |
1b07304c 2753 SECONDARY_EXEC_DESC |
f2b93280 2754 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2755 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2756 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7 2757 SECONDARY_EXEC_WBINVD_EXITING |
dfa169bb 2758 SECONDARY_EXEC_XSAVES;
c18911a2 2759
afa61f75
NHE
2760 if (enable_ept) {
2761 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2762 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2763 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2764 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
7db74265 2765 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
02120c45
BD
2766 if (cpu_has_vmx_ept_execute_only())
2767 vmx->nested.nested_vmx_ept_caps |=
2768 VMX_EPT_EXECUTE_ONLY_BIT;
b9c237bb 2769 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
45e11817 2770 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
7db74265
PB
2771 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2772 VMX_EPT_1GB_PAGE_BIT;
03efce6f
BD
2773 if (enable_ept_ad_bits) {
2774 vmx->nested.nested_vmx_secondary_ctls_high |=
2775 SECONDARY_EXEC_ENABLE_PML;
7461fbc4 2776 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
03efce6f 2777 }
afa61f75 2778 } else
b9c237bb 2779 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2780
ef697a71
PB
2781 /*
2782 * Old versions of KVM use the single-context version without
2783 * checking for support, so declare that it is supported even
2784 * though it is treated as global context. The alternative is
2785 * not failing the single-context invvpid, and it is worse.
2786 */
63cb6d5f
WL
2787 if (enable_vpid) {
2788 vmx->nested.nested_vmx_secondary_ctls_high |=
2789 SECONDARY_EXEC_ENABLE_VPID;
089d7b6e 2790 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
bcdde302 2791 VMX_VPID_EXTENT_SUPPORTED_MASK;
63cb6d5f 2792 } else
089d7b6e 2793 vmx->nested.nested_vmx_vpid_caps = 0;
99b83ac8 2794
0790ec17
RK
2795 if (enable_unrestricted_guest)
2796 vmx->nested.nested_vmx_secondary_ctls_high |=
2797 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2798
c18911a2 2799 /* miscellaneous data */
b9c237bb
WV
2800 rdmsr(MSR_IA32_VMX_MISC,
2801 vmx->nested.nested_vmx_misc_low,
2802 vmx->nested.nested_vmx_misc_high);
2803 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2804 vmx->nested.nested_vmx_misc_low |=
2805 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2806 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2807 vmx->nested.nested_vmx_misc_high = 0;
62cc6b9d
DM
2808
2809 /*
2810 * This MSR reports some information about VMX support. We
2811 * should return information about the VMX we emulate for the
2812 * guest, and the VMCS structure we give it - not about the
2813 * VMX support of the underlying hardware.
2814 */
2815 vmx->nested.nested_vmx_basic =
2816 VMCS12_REVISION |
2817 VMX_BASIC_TRUE_CTLS |
2818 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2819 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2820
2821 if (cpu_has_vmx_basic_inout())
2822 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2823
2824 /*
8322ebbb 2825 * These MSRs specify bits which the guest must keep fixed on
62cc6b9d
DM
2826 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2827 * We picked the standard core2 setting.
2828 */
2829#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2830#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2831 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
62cc6b9d 2832 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
8322ebbb
DM
2833
2834 /* These MSRs specify bits which the guest must keep fixed off. */
2835 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2836 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
62cc6b9d
DM
2837
2838 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2839 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
b87a51ae
NHE
2840}
2841
3899152c
DM
2842/*
2843 * if fixed0[i] == 1: val[i] must be 1
2844 * if fixed1[i] == 0: val[i] must be 0
2845 */
2846static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2847{
2848 return ((val & fixed1) | fixed0) == val;
b87a51ae
NHE
2849}
2850
2851static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2852{
3899152c 2853 return fixed_bits_valid(control, low, high);
b87a51ae
NHE
2854}
2855
2856static inline u64 vmx_control_msr(u32 low, u32 high)
2857{
2858 return low | ((u64)high << 32);
2859}
2860
62cc6b9d
DM
2861static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2862{
2863 superset &= mask;
2864 subset &= mask;
2865
2866 return (superset | subset) == superset;
2867}
2868
2869static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2870{
2871 const u64 feature_and_reserved =
2872 /* feature (except bit 48; see below) */
2873 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2874 /* reserved */
2875 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2876 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2877
2878 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2879 return -EINVAL;
2880
2881 /*
2882 * KVM does not emulate a version of VMX that constrains physical
2883 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2884 */
2885 if (data & BIT_ULL(48))
2886 return -EINVAL;
2887
2888 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2889 vmx_basic_vmcs_revision_id(data))
2890 return -EINVAL;
2891
2892 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2893 return -EINVAL;
2894
2895 vmx->nested.nested_vmx_basic = data;
2896 return 0;
2897}
2898
2899static int
2900vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2901{
2902 u64 supported;
2903 u32 *lowp, *highp;
2904
2905 switch (msr_index) {
2906 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2907 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2908 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2909 break;
2910 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2911 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2912 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2913 break;
2914 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2915 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2916 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2917 break;
2918 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2919 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2920 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2921 break;
2922 case MSR_IA32_VMX_PROCBASED_CTLS2:
2923 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2924 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2925 break;
2926 default:
2927 BUG();
2928 }
2929
2930 supported = vmx_control_msr(*lowp, *highp);
2931
2932 /* Check must-be-1 bits are still 1. */
2933 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2934 return -EINVAL;
2935
2936 /* Check must-be-0 bits are still 0. */
2937 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2938 return -EINVAL;
2939
2940 *lowp = data;
2941 *highp = data >> 32;
2942 return 0;
2943}
2944
2945static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2946{
2947 const u64 feature_and_reserved_bits =
2948 /* feature */
2949 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2950 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2951 /* reserved */
2952 GENMASK_ULL(13, 9) | BIT_ULL(31);
2953 u64 vmx_misc;
2954
2955 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2956 vmx->nested.nested_vmx_misc_high);
2957
2958 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2959 return -EINVAL;
2960
2961 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2962 PIN_BASED_VMX_PREEMPTION_TIMER) &&
2963 vmx_misc_preemption_timer_rate(data) !=
2964 vmx_misc_preemption_timer_rate(vmx_misc))
2965 return -EINVAL;
2966
2967 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2968 return -EINVAL;
2969
2970 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2971 return -EINVAL;
2972
2973 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2974 return -EINVAL;
2975
2976 vmx->nested.nested_vmx_misc_low = data;
2977 vmx->nested.nested_vmx_misc_high = data >> 32;
2978 return 0;
2979}
2980
2981static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2982{
2983 u64 vmx_ept_vpid_cap;
2984
2985 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2986 vmx->nested.nested_vmx_vpid_caps);
2987
2988 /* Every bit is either reserved or a feature bit. */
2989 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2990 return -EINVAL;
2991
2992 vmx->nested.nested_vmx_ept_caps = data;
2993 vmx->nested.nested_vmx_vpid_caps = data >> 32;
2994 return 0;
2995}
2996
2997static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2998{
2999 u64 *msr;
3000
3001 switch (msr_index) {
3002 case MSR_IA32_VMX_CR0_FIXED0:
3003 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3004 break;
3005 case MSR_IA32_VMX_CR4_FIXED0:
3006 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3007 break;
3008 default:
3009 BUG();
3010 }
3011
3012 /*
3013 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3014 * must be 1 in the restored value.
3015 */
3016 if (!is_bitwise_subset(data, *msr, -1ULL))
3017 return -EINVAL;
3018
3019 *msr = data;
3020 return 0;
3021}
3022
3023/*
3024 * Called when userspace is restoring VMX MSRs.
3025 *
3026 * Returns 0 on success, non-0 otherwise.
3027 */
3028static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
b87a51ae 3029{
b9c237bb
WV
3030 struct vcpu_vmx *vmx = to_vmx(vcpu);
3031
b87a51ae 3032 switch (msr_index) {
b87a51ae 3033 case MSR_IA32_VMX_BASIC:
62cc6b9d
DM
3034 return vmx_restore_vmx_basic(vmx, data);
3035 case MSR_IA32_VMX_PINBASED_CTLS:
3036 case MSR_IA32_VMX_PROCBASED_CTLS:
3037 case MSR_IA32_VMX_EXIT_CTLS:
3038 case MSR_IA32_VMX_ENTRY_CTLS:
b87a51ae 3039 /*
62cc6b9d
DM
3040 * The "non-true" VMX capability MSRs are generated from the
3041 * "true" MSRs, so we do not support restoring them directly.
3042 *
3043 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3044 * should restore the "true" MSRs with the must-be-1 bits
3045 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3046 * DEFAULT SETTINGS".
b87a51ae 3047 */
62cc6b9d
DM
3048 return -EINVAL;
3049 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3050 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3051 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3052 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3053 case MSR_IA32_VMX_PROCBASED_CTLS2:
3054 return vmx_restore_control_msr(vmx, msr_index, data);
3055 case MSR_IA32_VMX_MISC:
3056 return vmx_restore_vmx_misc(vmx, data);
3057 case MSR_IA32_VMX_CR0_FIXED0:
3058 case MSR_IA32_VMX_CR4_FIXED0:
3059 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3060 case MSR_IA32_VMX_CR0_FIXED1:
3061 case MSR_IA32_VMX_CR4_FIXED1:
3062 /*
3063 * These MSRs are generated based on the vCPU's CPUID, so we
3064 * do not support restoring them directly.
3065 */
3066 return -EINVAL;
3067 case MSR_IA32_VMX_EPT_VPID_CAP:
3068 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3069 case MSR_IA32_VMX_VMCS_ENUM:
3070 vmx->nested.nested_vmx_vmcs_enum = data;
3071 return 0;
3072 default:
b87a51ae 3073 /*
62cc6b9d 3074 * The rest of the VMX capability MSRs do not support restore.
b87a51ae 3075 */
62cc6b9d
DM
3076 return -EINVAL;
3077 }
3078}
3079
3080/* Returns 0 on success, non-0 otherwise. */
3081static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3082{
3083 struct vcpu_vmx *vmx = to_vmx(vcpu);
3084
3085 switch (msr_index) {
3086 case MSR_IA32_VMX_BASIC:
3087 *pdata = vmx->nested.nested_vmx_basic;
b87a51ae
NHE
3088 break;
3089 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3090 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV
3091 *pdata = vmx_control_msr(
3092 vmx->nested.nested_vmx_pinbased_ctls_low,
3093 vmx->nested.nested_vmx_pinbased_ctls_high);
0115f9cb
DM
3094 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3095 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3096 break;
3097 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3098 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV
3099 *pdata = vmx_control_msr(
3100 vmx->nested.nested_vmx_procbased_ctls_low,
3101 vmx->nested.nested_vmx_procbased_ctls_high);
0115f9cb
DM
3102 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3103 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3104 break;
3105 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3106 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV
3107 *pdata = vmx_control_msr(
3108 vmx->nested.nested_vmx_exit_ctls_low,
3109 vmx->nested.nested_vmx_exit_ctls_high);
0115f9cb
DM
3110 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3111 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3112 break;
3113 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3114 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV
3115 *pdata = vmx_control_msr(
3116 vmx->nested.nested_vmx_entry_ctls_low,
3117 vmx->nested.nested_vmx_entry_ctls_high);
0115f9cb
DM
3118 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3119 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE
3120 break;
3121 case MSR_IA32_VMX_MISC:
b9c237bb
WV
3122 *pdata = vmx_control_msr(
3123 vmx->nested.nested_vmx_misc_low,
3124 vmx->nested.nested_vmx_misc_high);
b87a51ae 3125 break;
b87a51ae 3126 case MSR_IA32_VMX_CR0_FIXED0:
62cc6b9d 3127 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
b87a51ae
NHE
3128 break;
3129 case MSR_IA32_VMX_CR0_FIXED1:
62cc6b9d 3130 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
b87a51ae
NHE
3131 break;
3132 case MSR_IA32_VMX_CR4_FIXED0:
62cc6b9d 3133 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
b87a51ae
NHE
3134 break;
3135 case MSR_IA32_VMX_CR4_FIXED1:
62cc6b9d 3136 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
b87a51ae
NHE
3137 break;
3138 case MSR_IA32_VMX_VMCS_ENUM:
62cc6b9d 3139 *pdata = vmx->nested.nested_vmx_vmcs_enum;
b87a51ae
NHE
3140 break;
3141 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV
3142 *pdata = vmx_control_msr(
3143 vmx->nested.nested_vmx_secondary_ctls_low,
3144 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE
3145 break;
3146 case MSR_IA32_VMX_EPT_VPID_CAP:
089d7b6e
WL
3147 *pdata = vmx->nested.nested_vmx_ept_caps |
3148 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
b87a51ae
NHE
3149 break;
3150 default:
b87a51ae 3151 return 1;
b3897a49
NHE
3152 }
3153
b87a51ae
NHE
3154 return 0;
3155}
3156
37e4c997
HZ
3157static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3158 uint64_t val)
3159{
3160 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3161
3162 return !(val & ~valid_bits);
3163}
3164
6aa8b732
AK
3165/*
3166 * Reads an msr value (of 'msr_index') into 'pdata'.
3167 * Returns 0 on success, non-0 otherwise.
3168 * Assumes vcpu_load() was already called.
3169 */
609e36d3 3170static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 3171{
26bb0981 3172 struct shared_msr_entry *msr;
6aa8b732 3173
609e36d3 3174 switch (msr_info->index) {
05b3e0c2 3175#ifdef CONFIG_X86_64
6aa8b732 3176 case MSR_FS_BASE:
609e36d3 3177 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK
3178 break;
3179 case MSR_GS_BASE:
609e36d3 3180 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 3181 break;
44ea2b17
AK
3182 case MSR_KERNEL_GS_BASE:
3183 vmx_load_host_state(to_vmx(vcpu));
609e36d3 3184 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 3185 break;
26bb0981 3186#endif
6aa8b732 3187 case MSR_EFER:
609e36d3 3188 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 3189 case MSR_IA32_TSC:
be7b263e 3190 msr_info->data = guest_read_tsc(vcpu);
6aa8b732
AK
3191 break;
3192 case MSR_IA32_SYSENTER_CS:
609e36d3 3193 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK
3194 break;
3195 case MSR_IA32_SYSENTER_EIP:
609e36d3 3196 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK
3197 break;
3198 case MSR_IA32_SYSENTER_ESP:
609e36d3 3199 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 3200 break;
0dd376e7 3201 case MSR_IA32_BNDCFGS:
691bd434
HZ
3202 if (!kvm_mpx_supported() ||
3203 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
93c4adc7 3204 return 1;
609e36d3 3205 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 3206 break;
c45dcc71
AR
3207 case MSR_IA32_MCG_EXT_CTL:
3208 if (!msr_info->host_initiated &&
3209 !(to_vmx(vcpu)->msr_ia32_feature_control &
3210 FEATURE_CONTROL_LMCE))
cae50139 3211 return 1;
c45dcc71
AR
3212 msr_info->data = vcpu->arch.mcg_ext_ctl;
3213 break;
cae50139 3214 case MSR_IA32_FEATURE_CONTROL:
3b84080b 3215 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
cae50139
JK
3216 break;
3217 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3218 if (!nested_vmx_allowed(vcpu))
3219 return 1;
609e36d3 3220 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL
3221 case MSR_IA32_XSS:
3222 if (!vmx_xsaves_supported())
3223 return 1;
609e36d3 3224 msr_info->data = vcpu->arch.ia32_xss;
20300099 3225 break;
4e47c7a6 3226 case MSR_TSC_AUX:
81b1b9ca 3227 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
4e47c7a6
SY
3228 return 1;
3229 /* Otherwise falls through */
6aa8b732 3230 default:
609e36d3 3231 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 3232 if (msr) {
609e36d3 3233 msr_info->data = msr->data;
3bab1f5d 3234 break;
6aa8b732 3235 }
609e36d3 3236 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK
3237 }
3238
6aa8b732
AK
3239 return 0;
3240}
3241
cae50139
JK
3242static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3243
6aa8b732
AK
3244/*
3245 * Writes msr value into into the appropriate "register".
3246 * Returns 0 on success, non-0 otherwise.
3247 * Assumes vcpu_load() was already called.
3248 */
8fe8ab46 3249static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 3250{
a2fa3e9f 3251 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 3252 struct shared_msr_entry *msr;
2cc51560 3253 int ret = 0;
8fe8ab46
WA
3254 u32 msr_index = msr_info->index;
3255 u64 data = msr_info->data;
2cc51560 3256
6aa8b732 3257 switch (msr_index) {
3bab1f5d 3258 case MSR_EFER:
8fe8ab46 3259 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 3260 break;
16175a79 3261#ifdef CONFIG_X86_64
6aa8b732 3262 case MSR_FS_BASE:
2fb92db1 3263 vmx_segment_cache_clear(vmx);
6aa8b732
AK
3264 vmcs_writel(GUEST_FS_BASE, data);
3265 break;
3266 case MSR_GS_BASE:
2fb92db1 3267 vmx_segment_cache_clear(vmx);
6aa8b732
AK
3268 vmcs_writel(GUEST_GS_BASE, data);
3269 break;
44ea2b17
AK
3270 case MSR_KERNEL_GS_BASE:
3271 vmx_load_host_state(vmx);
3272 vmx->msr_guest_kernel_gs_base = data;
3273 break;
6aa8b732
AK
3274#endif
3275 case MSR_IA32_SYSENTER_CS:
3276 vmcs_write32(GUEST_SYSENTER_CS, data);
3277 break;
3278 case MSR_IA32_SYSENTER_EIP:
f5b42c33 3279 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK
3280 break;
3281 case MSR_IA32_SYSENTER_ESP:
f5b42c33 3282 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 3283 break;
0dd376e7 3284 case MSR_IA32_BNDCFGS:
691bd434
HZ
3285 if (!kvm_mpx_supported() ||
3286 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
93c4adc7 3287 return 1;
4531662d
JM
3288 if (is_noncanonical_address(data & PAGE_MASK) ||
3289 (data & MSR_IA32_BNDCFGS_RSVD))
93c4adc7 3290 return 1;
0dd376e7
LJ
3291 vmcs_write64(GUEST_BNDCFGS, data);
3292 break;
af24a4e4 3293 case MSR_IA32_TSC:
8fe8ab46 3294 kvm_write_tsc(vcpu, msr_info);
6aa8b732 3295 break;
468d472f
SY
3296 case MSR_IA32_CR_PAT:
3297 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA
3298 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3299 return 1;
468d472f
SY
3300 vmcs_write64(GUEST_IA32_PAT, data);
3301 vcpu->arch.pat = data;
3302 break;
3303 }
8fe8ab46 3304 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 3305 break;
ba904635
WA
3306 case MSR_IA32_TSC_ADJUST:
3307 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 3308 break;
c45dcc71
AR
3309 case MSR_IA32_MCG_EXT_CTL:
3310 if ((!msr_info->host_initiated &&
3311 !(to_vmx(vcpu)->msr_ia32_feature_control &
3312 FEATURE_CONTROL_LMCE)) ||
3313 (data & ~MCG_EXT_CTL_LMCE_EN))
3314 return 1;
3315 vcpu->arch.mcg_ext_ctl = data;
3316 break;
cae50139 3317 case MSR_IA32_FEATURE_CONTROL:
37e4c997 3318 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 3319 (to_vmx(vcpu)->msr_ia32_feature_control &
cae50139
JK
3320 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3321 return 1;
3b84080b 3322 vmx->msr_ia32_feature_control = data;
cae50139
JK
3323 if (msr_info->host_initiated && data == 0)
3324 vmx_leave_nested(vcpu);
3325 break;
3326 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM
3327 if (!msr_info->host_initiated)
3328 return 1; /* they are read-only */
3329 if (!nested_vmx_allowed(vcpu))
3330 return 1;
3331 return vmx_set_vmx_msr(vcpu, msr_index, data);
20300099
WL
3332 case MSR_IA32_XSS:
3333 if (!vmx_xsaves_supported())
3334 return 1;
3335 /*
3336 * The only supported bit as of Skylake is bit 8, but
3337 * it is not supported on KVM.
3338 */
3339 if (data != 0)
3340 return 1;
3341 vcpu->arch.ia32_xss = data;
3342 if (vcpu->arch.ia32_xss != host_xss)
3343 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3344 vcpu->arch.ia32_xss, host_xss);
3345 else
3346 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3347 break;
4e47c7a6 3348 case MSR_TSC_AUX:
81b1b9ca 3349 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
4e47c7a6
SY
3350 return 1;
3351 /* Check reserved bit, higher 32 bits should be zero */
3352 if ((data >> 32) != 0)
3353 return 1;
3354 /* Otherwise falls through */
6aa8b732 3355 default:
8b9cf98c 3356 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 3357 if (msr) {
8b3c3104 3358 u64 old_msr_data = msr->data;
3bab1f5d 3359 msr->data = data;
2225fd56
AK
3360 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3361 preempt_disable();
8b3c3104
AH
3362 ret = kvm_set_shared_msr(msr->index, msr->data,
3363 msr->mask);
2225fd56 3364 preempt_enable();
8b3c3104
AH
3365 if (ret)
3366 msr->data = old_msr_data;
2225fd56 3367 }
3bab1f5d 3368 break;
6aa8b732 3369 }
8fe8ab46 3370 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK
3371 }
3372
2cc51560 3373 return ret;
6aa8b732
AK
3374}
3375
5fdbf976 3376static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 3377{
5fdbf976
MT
3378 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3379 switch (reg) {
3380 case VCPU_REGS_RSP:
3381 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3382 break;
3383 case VCPU_REGS_RIP:
3384 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3385 break;
6de4f3ad
AK
3386 case VCPU_EXREG_PDPTR:
3387 if (enable_ept)
3388 ept_save_pdptrs(vcpu);
3389 break;
5fdbf976
MT
3390 default:
3391 break;
3392 }
6aa8b732
AK
3393}
3394
6aa8b732
AK
3395static __init int cpu_has_kvm_support(void)
3396{
6210e37b 3397 return cpu_has_vmx();
6aa8b732
AK
3398}
3399
3400static __init int vmx_disabled_by_bios(void)
3401{
3402 u64 msr;
3403
3404 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 3405 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 3406 /* launched w/ TXT and VMX disabled */
cafd6659
SW
3407 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3408 && tboot_enabled())
3409 return 1;
23f3e991 3410 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 3411 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 3412 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW
3413 && !tboot_enabled()) {
3414 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 3415 "activate TXT before enabling KVM\n");
cafd6659 3416 return 1;
f9335afe 3417 }
23f3e991
JC
3418 /* launched w/o TXT and VMX disabled */
3419 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3420 && !tboot_enabled())
3421 return 1;
cafd6659
SW
3422 }
3423
3424 return 0;
6aa8b732
AK
3425}
3426
7725b894
DX
3427static void kvm_cpu_vmxon(u64 addr)
3428{
fe0e80be 3429 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS
3430 intel_pt_handle_vmx(1);
3431
7725b894
DX
3432 asm volatile (ASM_VMX_VMXON_RAX
3433 : : "a"(&addr), "m"(addr)
3434 : "memory", "cc");
3435}
3436
13a34e06 3437static int hardware_enable(void)
6aa8b732
AK
3438{
3439 int cpu = raw_smp_processor_id();
3440 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 3441 u64 old, test_bits;
6aa8b732 3442
1e02ce4c 3443 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG
3444 return -EBUSY;
3445
d462b819 3446 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW
3447 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3448 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY
3449
3450 /*
3451 * Now we can enable the vmclear operation in kdump
3452 * since the loaded_vmcss_on_cpu list on this cpu
3453 * has been initialized.
3454 *
3455 * Though the cpu is not in VMX operation now, there
3456 * is no problem to enable the vmclear operation
3457 * for the loaded_vmcss_on_cpu list is empty!
3458 */
3459 crash_enable_local_vmclear(cpu);
3460
6aa8b732 3461 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW
3462
3463 test_bits = FEATURE_CONTROL_LOCKED;
3464 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3465 if (tboot_enabled())
3466 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3467
3468 if ((old & test_bits) != test_bits) {
6aa8b732 3469 /* enable and lock */
cafd6659
SW
3470 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3471 }
fe0e80be
DH
3472 kvm_cpu_vmxon(phys_addr);
3473 ept_sync_global();
10474ae8
AG
3474
3475 return 0;
6aa8b732
AK
3476}
3477
d462b819 3478static void vmclear_local_loaded_vmcss(void)
543e4243
AK
3479{
3480 int cpu = raw_smp_processor_id();
d462b819 3481 struct loaded_vmcs *v, *n;
543e4243 3482
d462b819
NHE
3483 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3484 loaded_vmcss_on_cpu_link)
3485 __loaded_vmcs_clear(v);
543e4243
AK
3486}
3487
710ff4a8
EH
3488
3489/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3490 * tricks.
3491 */
3492static void kvm_cpu_vmxoff(void)
6aa8b732 3493{
4ecac3fd 3494 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1c5ac21a
AS
3495
3496 intel_pt_handle_vmx(0);
fe0e80be 3497 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK
3498}
3499
13a34e06 3500static void hardware_disable(void)
710ff4a8 3501{
fe0e80be
DH
3502 vmclear_local_loaded_vmcss();
3503 kvm_cpu_vmxoff();
710ff4a8
EH
3504}
3505
1c3d14fe 3506static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 3507 u32 msr, u32 *result)
1c3d14fe
YS
3508{
3509 u32 vmx_msr_low, vmx_msr_high;
3510 u32 ctl = ctl_min | ctl_opt;
3511
3512 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3513
3514 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3515 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3516
3517 /* Ensure minimum (required) set of control bits are supported. */
3518 if (ctl_min & ~ctl)
002c7f7c 3519 return -EIO;
1c3d14fe
YS
3520
3521 *result = ctl;
3522 return 0;
3523}
3524
110312c8
AK
3525static __init bool allow_1_setting(u32 msr, u32 ctl)
3526{
3527 u32 vmx_msr_low, vmx_msr_high;
3528
3529 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3530 return vmx_msr_high & ctl;
3531}
3532
002c7f7c 3533static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK
3534{
3535 u32 vmx_msr_low, vmx_msr_high;
d56f546d 3536 u32 min, opt, min2, opt2;
1c3d14fe
YS
3537 u32 _pin_based_exec_control = 0;
3538 u32 _cpu_based_exec_control = 0;
f78e0e2e 3539 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS
3540 u32 _vmexit_control = 0;
3541 u32 _vmentry_control = 0;
3542
10166744 3543 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS
3544#ifdef CONFIG_X86_64
3545 CPU_BASED_CR8_LOAD_EXITING |
3546 CPU_BASED_CR8_STORE_EXITING |
3547#endif
d56f546d
SY
3548 CPU_BASED_CR3_LOAD_EXITING |
3549 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS
3550 CPU_BASED_USE_IO_BITMAPS |
3551 CPU_BASED_MOV_DR_EXITING |
a7052897 3552 CPU_BASED_USE_TSC_OFFSETING |
fee84b07
AK
3553 CPU_BASED_INVLPG_EXITING |
3554 CPU_BASED_RDPMC_EXITING;
443381a8 3555
668fffa3
MT
3556 if (!kvm_mwait_in_guest())
3557 min |= CPU_BASED_MWAIT_EXITING |
3558 CPU_BASED_MONITOR_EXITING;
3559
f78e0e2e 3560 opt = CPU_BASED_TPR_SHADOW |
25c5f225 3561 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 3562 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS
3563 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3564 &_cpu_based_exec_control) < 0)
002c7f7c 3565 return -EIO;
6e5d865c
YS
3566#ifdef CONFIG_X86_64
3567 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3568 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3569 ~CPU_BASED_CR8_STORE_EXITING;
3570#endif
f78e0e2e 3571 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY
3572 min2 = 0;
3573 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3574 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3575 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3576 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3577 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3578 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3579 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3580 SECONDARY_EXEC_RDTSCP |
83d4c286 3581 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3582 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3583 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3584 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 3585 SECONDARY_EXEC_XSAVES |
8b3e34e4 3586 SECONDARY_EXEC_ENABLE_PML |
64903d61 3587 SECONDARY_EXEC_TSC_SCALING;
d56f546d
SY
3588 if (adjust_vmx_controls(min2, opt2,
3589 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY
3590 &_cpu_based_2nd_exec_control) < 0)
3591 return -EIO;
3592 }
3593#ifndef CONFIG_X86_64
3594 if (!(_cpu_based_2nd_exec_control &
3595 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3596 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3597#endif
83d4c286
YZ
3598
3599 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3600 _cpu_based_2nd_exec_control &= ~(
8d14695f 3601 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ
3602 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3603 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3604
d56f546d 3605 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT
3606 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3607 enabled */
5fff7d27
GN
3608 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3609 CPU_BASED_CR3_STORE_EXITING |
3610 CPU_BASED_INVLPG_EXITING);
d56f546d
SY
3611 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3612 vmx_capability.ept, vmx_capability.vpid);
3613 }
1c3d14fe 3614
91fa0f8e 3615 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS
3616#ifdef CONFIG_X86_64
3617 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3618#endif
a547c6db 3619 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
91fa0f8e 3620 VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS
3621 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3622 &_vmexit_control) < 0)
002c7f7c 3623 return -EIO;
1c3d14fe 3624
2c82878b
PB
3625 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3626 PIN_BASED_VIRTUAL_NMIS;
3627 opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ
3628 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3629 &_pin_based_exec_control) < 0)
3630 return -EIO;
3631
1c17c3e6
PB
3632 if (cpu_has_broken_vmx_preemption_timer())
3633 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 3634 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 3635 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ
3636 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3637
c845f9c6 3638 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3639 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS
3640 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3641 &_vmentry_control) < 0)
002c7f7c 3642 return -EIO;
6aa8b732 3643
c68876fd 3644 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS
3645
3646 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3647 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3648 return -EIO;
1c3d14fe
YS
3649
3650#ifdef CONFIG_X86_64
3651 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3652 if (vmx_msr_high & (1u<<16))
002c7f7c 3653 return -EIO;
1c3d14fe
YS
3654#endif
3655
3656 /* Require Write-Back (WB) memory type for VMCS accesses. */
3657 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3658 return -EIO;
1c3d14fe 3659
002c7f7c 3660 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 3661 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 3662 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
002c7f7c 3663 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3664
002c7f7c
YS
3665 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3666 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3667 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS
3668 vmcs_conf->vmexit_ctrl = _vmexit_control;
3669 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3670
110312c8
AK
3671 cpu_has_load_ia32_efer =
3672 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3673 VM_ENTRY_LOAD_IA32_EFER)
3674 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3675 VM_EXIT_LOAD_IA32_EFER);
3676
8bf00a52
GN
3677 cpu_has_load_perf_global_ctrl =
3678 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3679 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3680 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3681 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3682
3683 /*
3684 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
bb3541f1 3685 * but due to errata below it can't be used. Workaround is to use
8bf00a52
GN
3686 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3687 *
3688 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3689 *
3690 * AAK155 (model 26)
3691 * AAP115 (model 30)
3692 * AAT100 (model 37)
3693 * BC86,AAY89,BD102 (model 44)
3694 * BA97 (model 46)
3695 *
3696 */
3697 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3698 switch (boot_cpu_data.x86_model) {
3699 case 26:
3700 case 30:
3701 case 37:
3702 case 44:
3703 case 46:
3704 cpu_has_load_perf_global_ctrl = false;
3705 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3706 "does not work properly. Using workaround\n");
3707 break;
3708 default:
3709 break;
3710 }
3711 }
3712
782511b0 3713 if (boot_cpu_has(X86_FEATURE_XSAVES))
20300099
WL
3714 rdmsrl(MSR_IA32_XSS, host_xss);
3715
1c3d14fe 3716 return 0;
c68876fd 3717}
6aa8b732
AK
3718
3719static struct vmcs *alloc_vmcs_cpu(int cpu)
3720{
3721 int node = cpu_to_node(cpu);
3722 struct page *pages;
3723 struct vmcs *vmcs;
3724
96db800f 3725 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK
3726 if (!pages)
3727 return NULL;
3728 vmcs = page_address(pages);
1c3d14fe
YS
3729 memset(vmcs, 0, vmcs_config.size);
3730 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK
3731 return vmcs;
3732}
3733
3734static struct vmcs *alloc_vmcs(void)
3735{
d3b2c338 3736 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK
3737}
3738
3739static void free_vmcs(struct vmcs *vmcs)
3740{
1c3d14fe 3741 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK
3742}
3743
d462b819
NHE
3744/*
3745 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3746 */
3747static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3748{
3749 if (!loaded_vmcs->vmcs)
3750 return;
3751 loaded_vmcs_clear(loaded_vmcs);
3752 free_vmcs(loaded_vmcs->vmcs);
3753 loaded_vmcs->vmcs = NULL;
355f4fb1 3754 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE
3755}
3756
39959588 3757static void free_kvm_area(void)
6aa8b732
AK
3758{
3759 int cpu;
3760
3230bb47 3761 for_each_possible_cpu(cpu) {
6aa8b732 3762 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA
3763 per_cpu(vmxarea, cpu) = NULL;
3764 }
6aa8b732
AK
3765}
3766
85fd514e
JM
3767enum vmcs_field_type {
3768 VMCS_FIELD_TYPE_U16 = 0,
3769 VMCS_FIELD_TYPE_U64 = 1,
3770 VMCS_FIELD_TYPE_U32 = 2,
3771 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3772};
3773
3774static inline int vmcs_field_type(unsigned long field)
3775{
3776 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
3777 return VMCS_FIELD_TYPE_U32;
3778 return (field >> 13) & 0x3 ;
3779}
3780
3781static inline int vmcs_field_readonly(unsigned long field)
3782{
3783 return (((field >> 10) & 0x3) == 1);
3784}
3785
fe2b201b
BD
3786static void init_vmcs_shadow_fields(void)
3787{
3788 int i, j;
3789
3790 /* No checks for read only fields yet */
3791
3792 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3793 switch (shadow_read_write_fields[i]) {
3794 case GUEST_BNDCFGS:
a87036ad 3795 if (!kvm_mpx_supported())
fe2b201b
BD
3796 continue;
3797 break;
3798 default:
3799 break;
3800 }
3801
3802 if (j < i)
3803 shadow_read_write_fields[j] =
3804 shadow_read_write_fields[i];
3805 j++;
3806 }
3807 max_shadow_read_write_fields = j;
3808
3809 /* shadowed fields guest access without vmexit */
3810 for (i = 0; i < max_shadow_read_write_fields; i++) {
85fd514e
JM
3811 unsigned long field = shadow_read_write_fields[i];
3812
3813 clear_bit(field, vmx_vmwrite_bitmap);
3814 clear_bit(field, vmx_vmread_bitmap);
3815 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
3816 clear_bit(field + 1, vmx_vmwrite_bitmap);
3817 clear_bit(field + 1, vmx_vmread_bitmap);
3818 }
3819 }
3820 for (i = 0; i < max_shadow_read_only_fields; i++) {
3821 unsigned long field = shadow_read_only_fields[i];
3822
3823 clear_bit(field, vmx_vmread_bitmap);
3824 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
3825 clear_bit(field + 1, vmx_vmread_bitmap);
fe2b201b 3826 }
fe2b201b
BD
3827}
3828
6aa8b732
AK
3829static __init int alloc_kvm_area(void)
3830{
3831 int cpu;
3832
3230bb47 3833 for_each_possible_cpu(cpu) {
6aa8b732
AK
3834 struct vmcs *vmcs;
3835
3836 vmcs = alloc_vmcs_cpu(cpu);
3837 if (!vmcs) {
3838 free_kvm_area();
3839 return -ENOMEM;
3840 }
3841
3842 per_cpu(vmxarea, cpu) = vmcs;
3843 }
3844 return 0;
3845}
3846
14168786
GN
3847static bool emulation_required(struct kvm_vcpu *vcpu)
3848{
3849 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3850}
3851
91b0aa2c 3852static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3853 struct kvm_segment *save)
6aa8b732 3854{
d99e4152
GN
3855 if (!emulate_invalid_guest_state) {
3856 /*
3857 * CS and SS RPL should be equal during guest entry according
3858 * to VMX spec, but in reality it is not always so. Since vcpu
3859 * is in the middle of the transition from real mode to
3860 * protected mode it is safe to assume that RPL 0 is a good
3861 * default value.
3862 */
3863 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA
3864 save->selector &= ~SEGMENT_RPL_MASK;
3865 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3866 save->s = 1;
6aa8b732 3867 }
d99e4152 3868 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK
3869}
3870
3871static void enter_pmode(struct kvm_vcpu *vcpu)
3872{
3873 unsigned long flags;
a89a8fb9 3874 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3875
d99e4152
GN
3876 /*
3877 * Update real mode segment cache. It may be not up-to-date if sement
3878 * register was written while vcpu was in a guest mode.
3879 */
3880 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3881 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3882 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3883 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3884 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3885 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3886
7ffd92c5 3887 vmx->rmode.vm86_active = 0;
6aa8b732 3888
2fb92db1
AK
3889 vmx_segment_cache_clear(vmx);
3890
f5f7b2fe 3891 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK
3892
3893 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK
3894 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3895 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK
3896 vmcs_writel(GUEST_RFLAGS, flags);
3897
66aee91a
RR
3898 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3899 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK
3900
3901 update_exception_bitmap(vcpu);
3902
91b0aa2c
GN
3903 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3904 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3905 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3906 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3907 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3908 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK
3909}
3910
f5f7b2fe 3911static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3912{
772e0318 3913 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN
3914 struct kvm_segment var = *save;
3915
3916 var.dpl = 0x3;
3917 if (seg == VCPU_SREG_CS)
3918 var.type = 0x3;
3919
3920 if (!emulate_invalid_guest_state) {
3921 var.selector = var.base >> 4;
3922 var.base = var.base & 0xffff0;
3923 var.limit = 0xffff;
3924 var.g = 0;
3925 var.db = 0;
3926 var.present = 1;
3927 var.s = 1;
3928 var.l = 0;
3929 var.unusable = 0;
3930 var.type = 0x3;
3931 var.avl = 0;
3932 if (save->base & 0xf)
3933 printk_once(KERN_WARNING "kvm: segment base is not "
3934 "paragraph aligned when entering "
3935 "protected mode (seg=%d)", seg);
3936 }
6aa8b732 3937
d99e4152 3938 vmcs_write16(sf->selector, var.selector);
96794e4e 3939 vmcs_writel(sf->base, var.base);
d99e4152
GN
3940 vmcs_write32(sf->limit, var.limit);
3941 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK
3942}
3943
3944static void enter_rmode(struct kvm_vcpu *vcpu)
3945{
3946 unsigned long flags;
a89a8fb9 3947 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3948
f5f7b2fe
AK
3949 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3950 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3951 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3952 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3953 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN
3954 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3955 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3956
7ffd92c5 3957 vmx->rmode.vm86_active = 1;
6aa8b732 3958
776e58ea
GN
3959 /*
3960 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3961 * vcpu. Warn the user that an update is overdue.
776e58ea 3962 */
4918c6ca 3963 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN
3964 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3965 "called before entering vcpu\n");
776e58ea 3966
2fb92db1
AK
3967 vmx_segment_cache_clear(vmx);
3968
4918c6ca 3969 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3970 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK
3971 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3972
3973 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3974 vmx->rmode.save_rflags = flags;
6aa8b732 3975
053de044 3976 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK
3977
3978 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3979 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK
3980 update_exception_bitmap(vcpu);
3981
d99e4152
GN
3982 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3983 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3984 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3985 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3986 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3987 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3988
8668a3c4 3989 kvm_mmu_reset_context(vcpu);
6aa8b732
AK
3990}
3991
401d10de
AS
3992static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3993{
3994 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK
3995 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3996
3997 if (!msr)
3998 return;
401d10de 3999
44ea2b17
AK
4000 /*
4001 * Force kernel_gs_base reloading before EFER changes, as control
4002 * of this msr depends on is_long_mode().
4003 */
4004 vmx_load_host_state(to_vmx(vcpu));
f6801dff 4005 vcpu->arch.efer = efer;
401d10de 4006 if (efer & EFER_LMA) {
2961e876 4007 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS
4008 msr->data = efer;
4009 } else {
2961e876 4010 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS
4011
4012 msr->data = efer & ~EFER_LME;
4013 }
4014 setup_msrs(vmx);
4015}
4016
05b3e0c2 4017#ifdef CONFIG_X86_64
6aa8b732
AK
4018
4019static void enter_lmode(struct kvm_vcpu *vcpu)
4020{
4021 u32 guest_tr_ar;
4022
2fb92db1
AK
4023 vmx_segment_cache_clear(to_vmx(vcpu));
4024
6aa8b732 4025 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 4026 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK
4027 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4028 __func__);
6aa8b732 4029 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL
4030 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4031 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 4032 }
da38f438 4033 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK
4034}
4035
4036static void exit_lmode(struct kvm_vcpu *vcpu)
4037{
2961e876 4038 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 4039 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK
4040}
4041
4042#endif
4043
dd5f5341 4044static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
2384d2b3 4045{
dd180b3e
XG
4046 if (enable_ept) {
4047 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4048 return;
995f00a6 4049 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
f0b98c02
JM
4050 } else {
4051 vpid_sync_context(vpid);
dd180b3e 4052 }
2384d2b3
SY
4053}
4054
dd5f5341
WL
4055static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4056{
4057 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4058}
4059
fb6c8198
JM
4060static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4061{
4062 if (enable_ept)
4063 vmx_flush_tlb(vcpu);
4064}
4065
e8467fda
AK
4066static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4067{
4068 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4069
4070 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4071 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4072}
4073
aff48baa
AK
4074static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4075{
4076 if (enable_ept && is_paging(vcpu))
4077 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4078 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4079}
4080
25c4c276 4081static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 4082{
fc78f519
AK
4083 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4084
4085 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4086 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK
4087}
4088
1439442c
SY
4089static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4090{
d0d538b9
GN
4091 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4092
6de4f3ad
AK
4093 if (!test_bit(VCPU_EXREG_PDPTR,
4094 (unsigned long *)&vcpu->arch.regs_dirty))
4095 return;
4096
1439442c 4097 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN
4098 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4099 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4100 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4101 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY
4102 }
4103}
4104
8f5d549f
AK
4105static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4106{
d0d538b9
GN
4107 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4108
8f5d549f 4109 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN
4110 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4111 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4112 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4113 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 4114 }
6de4f3ad
AK
4115
4116 __set_bit(VCPU_EXREG_PDPTR,
4117 (unsigned long *)&vcpu->arch.regs_avail);
4118 __set_bit(VCPU_EXREG_PDPTR,
4119 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK
4120}
4121
3899152c
DM
4122static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4123{
4124 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4125 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4126 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4127
4128 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4129 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4130 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4131 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4132
4133 return fixed_bits_valid(val, fixed0, fixed1);
4134}
4135
4136static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4137{
4138 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4139 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4140
4141 return fixed_bits_valid(val, fixed0, fixed1);
4142}
4143
4144static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4145{
4146 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4147 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4148
4149 return fixed_bits_valid(val, fixed0, fixed1);
4150}
4151
4152/* No difference in the restrictions on guest and host CR4 in VMX operation. */
4153#define nested_guest_cr4_valid nested_cr4_valid
4154#define nested_host_cr4_valid nested_cr4_valid
4155
5e1746d6 4156static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY
4157
4158static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4159 unsigned long cr0,
4160 struct kvm_vcpu *vcpu)
4161{
5233dd51
MT
4162 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4163 vmx_decache_cr3(vcpu);
1439442c
SY
4164 if (!(cr0 & X86_CR0_PG)) {
4165 /* From paging/starting to nonpaging */
4166 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 4167 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY
4168 (CPU_BASED_CR3_LOAD_EXITING |
4169 CPU_BASED_CR3_STORE_EXITING));
4170 vcpu->arch.cr0 = cr0;
fc78f519 4171 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY
4172 } else if (!is_paging(vcpu)) {
4173 /* From nonpaging to paging */
4174 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 4175 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY
4176 ~(CPU_BASED_CR3_LOAD_EXITING |
4177 CPU_BASED_CR3_STORE_EXITING));
4178 vcpu->arch.cr0 = cr0;
fc78f519 4179 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 4180 }
95eb84a7
SY
4181
4182 if (!(cr0 & X86_CR0_WP))
4183 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY
4184}
4185
6aa8b732
AK
4186static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4187{
7ffd92c5 4188 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK
4189 unsigned long hw_cr0;
4190
5037878e 4191 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 4192 if (enable_unrestricted_guest)
5037878e 4193 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 4194 else {
5037878e 4195 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 4196
218e763f
GN
4197 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4198 enter_pmode(vcpu);
6aa8b732 4199
218e763f
GN
4200 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4201 enter_rmode(vcpu);
4202 }
6aa8b732 4203
05b3e0c2 4204#ifdef CONFIG_X86_64
f6801dff 4205 if (vcpu->arch.efer & EFER_LME) {
707d92fa 4206 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 4207 enter_lmode(vcpu);
707d92fa 4208 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK
4209 exit_lmode(vcpu);
4210 }
4211#endif
4212
089d034e 4213 if (enable_ept)
1439442c
SY
4214 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4215
6aa8b732 4216 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 4217 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 4218 vcpu->arch.cr0 = cr0;
14168786
GN
4219
4220 /* depends on vcpu->arch.cr0 to be set to a new value */
4221 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK
4222}
4223
995f00a6 4224static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
1439442c
SY
4225{
4226 u64 eptp;
4227
4228 /* TODO write the value reading from MSR */
4229 eptp = VMX_EPT_DEFAULT_MT |
4230 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
995f00a6
PF
4231 if (enable_ept_ad_bits &&
4232 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
b38f9934 4233 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY
4234 eptp |= (root_hpa & PAGE_MASK);
4235
4236 return eptp;
4237}
4238
6aa8b732
AK
4239static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4240{
1439442c
SY
4241 unsigned long guest_cr3;
4242 u64 eptp;
4243
4244 guest_cr3 = cr3;
089d034e 4245 if (enable_ept) {
995f00a6 4246 eptp = construct_eptp(vcpu, cr3);
1439442c 4247 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK
4248 if (is_paging(vcpu) || is_guest_mode(vcpu))
4249 guest_cr3 = kvm_read_cr3(vcpu);
4250 else
4251 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 4252 ept_load_pdptrs(vcpu);
1439442c
SY
4253 }
4254
2384d2b3 4255 vmx_flush_tlb(vcpu);
1439442c 4256 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK
4257}
4258
5e1746d6 4259static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 4260{
085e68ee
BS
4261 /*
4262 * Pass through host's Machine Check Enable value to hw_cr4, which
4263 * is in force while we are in guest mode. Do not let guests control
4264 * this bit, even if host CR4.MCE == 0.
4265 */
4266 unsigned long hw_cr4 =
4267 (cr4_read_shadow() & X86_CR4_MCE) |
4268 (cr4 & ~X86_CR4_MCE) |
4269 (to_vmx(vcpu)->rmode.vm86_active ?
4270 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 4271
5e1746d6
NHE
4272 if (cr4 & X86_CR4_VMXE) {
4273 /*
4274 * To use VMXON (and later other VMX instructions), a guest
4275 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4276 * So basically the check on whether to allow nested VMX
4277 * is here.
4278 */
4279 if (!nested_vmx_allowed(vcpu))
4280 return 1;
1a0d74e6 4281 }
3899152c
DM
4282
4283 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE
4284 return 1;
4285
ad312c7c 4286 vcpu->arch.cr4 = cr4;
bc23008b
AK
4287 if (enable_ept) {
4288 if (!is_paging(vcpu)) {
4289 hw_cr4 &= ~X86_CR4_PAE;
4290 hw_cr4 |= X86_CR4_PSE;
4291 } else if (!(cr4 & X86_CR4_PAE)) {
4292 hw_cr4 &= ~X86_CR4_PAE;
4293 }
4294 }
1439442c 4295
656ec4a4
RK
4296 if (!enable_unrestricted_guest && !is_paging(vcpu))
4297 /*
ddba2628
HH
4298 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4299 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4300 * to be manually disabled when guest switches to non-paging
4301 * mode.
4302 *
4303 * If !enable_unrestricted_guest, the CPU is always running
4304 * with CR0.PG=1 and CR4 needs to be modified.
4305 * If enable_unrestricted_guest, the CPU automatically
4306 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 4307 */
ddba2628 4308 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
656ec4a4 4309
1439442c
SY
4310 vmcs_writel(CR4_READ_SHADOW, cr4);
4311 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 4312 return 0;
6aa8b732
AK
4313}
4314
6aa8b732
AK
4315static void vmx_get_segment(struct kvm_vcpu *vcpu,
4316 struct kvm_segment *var, int seg)
4317{
a9179499 4318 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK
4319 u32 ar;
4320
c6ad1153 4321 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 4322 *var = vmx->rmode.segs[seg];
a9179499 4323 if (seg == VCPU_SREG_TR
2fb92db1 4324 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 4325 return;
1390a28b
AK
4326 var->base = vmx_read_guest_seg_base(vmx, seg);
4327 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4328 return;
a9179499 4329 }
2fb92db1
AK
4330 var->base = vmx_read_guest_seg_base(vmx, seg);
4331 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4332 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4333 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 4334 var->unusable = (ar >> 16) & 1;
6aa8b732
AK
4335 var->type = ar & 15;
4336 var->s = (ar >> 4) & 1;
4337 var->dpl = (ar >> 5) & 3;
03617c18
GN
4338 /*
4339 * Some userspaces do not preserve unusable property. Since usable
4340 * segment has to be present according to VMX spec we can use present
4341 * property to amend userspace bug by making unusable segment always
4342 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4343 * segment as unusable.
4344 */
4345 var->present = !var->unusable;
6aa8b732
AK
4346 var->avl = (ar >> 12) & 1;
4347 var->l = (ar >> 13) & 1;
4348 var->db = (ar >> 14) & 1;
4349 var->g = (ar >> 15) & 1;
6aa8b732
AK
4350}
4351
a9179499
AK
4352static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4353{
a9179499
AK
4354 struct kvm_segment s;
4355
4356 if (to_vmx(vcpu)->rmode.vm86_active) {
4357 vmx_get_segment(vcpu, &s, seg);
4358 return s.base;
4359 }
2fb92db1 4360 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK
4361}
4362
b09408d0 4363static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 4364{
b09408d0
MT
4365 struct vcpu_vmx *vmx = to_vmx(vcpu);
4366
ae9fedc7 4367 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 4368 return 0;
ae9fedc7
PB
4369 else {
4370 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 4371 return VMX_AR_DPL(ar);
69c73028 4372 }
69c73028
AK
4373}
4374
653e3108 4375static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 4376{
6aa8b732
AK
4377 u32 ar;
4378
f0495f9b 4379 if (var->unusable || !var->present)
6aa8b732
AK
4380 ar = 1 << 16;
4381 else {
4382 ar = var->type & 15;
4383 ar |= (var->s & 1) << 4;
4384 ar |= (var->dpl & 3) << 5;
4385 ar |= (var->present & 1) << 7;
4386 ar |= (var->avl & 1) << 12;
4387 ar |= (var->l & 1) << 13;
4388 ar |= (var->db & 1) << 14;
4389 ar |= (var->g & 1) << 15;
4390 }
653e3108
AK
4391
4392 return ar;
4393}
4394
4395static void vmx_set_segment(struct kvm_vcpu *vcpu,
4396 struct kvm_segment *var, int seg)
4397{
7ffd92c5 4398 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 4399 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 4400
2fb92db1
AK
4401 vmx_segment_cache_clear(vmx);
4402
1ecd50a9
GN
4403 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4404 vmx->rmode.segs[seg] = *var;
4405 if (seg == VCPU_SREG_TR)
4406 vmcs_write16(sf->selector, var->selector);
4407 else if (var->s)
4408 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 4409 goto out;
653e3108 4410 }
1ecd50a9 4411
653e3108
AK
4412 vmcs_writel(sf->base, var->base);
4413 vmcs_write32(sf->limit, var->limit);
4414 vmcs_write16(sf->selector, var->selector);
3a624e29
NK
4415
4416 /*
4417 * Fix the "Accessed" bit in AR field of segment registers for older
4418 * qemu binaries.
4419 * IA32 arch specifies that at the time of processor reset the
4420 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 4421 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK
4422 * state vmexit when "unrestricted guest" mode is turned on.
4423 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4424 * tree. Newer qemu binaries with that qemu fix would not need this
4425 * kvm hack.
4426 */
4427 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 4428 var->type |= 0x1; /* Accessed */
3a624e29 4429
f924d66d 4430 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN
4431
4432out:
98eb2f8b 4433 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK
4434}
4435
6aa8b732
AK
4436static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4437{
2fb92db1 4438 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK
4439
4440 *db = (ar >> 14) & 1;
4441 *l = (ar >> 13) & 1;
4442}
4443
89a27f4d 4444static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4445{
89a27f4d
GN
4446 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4447 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK
4448}
4449
89a27f4d 4450static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4451{
89a27f4d
GN
4452 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4453 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK
4454}
4455
89a27f4d 4456static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4457{
89a27f4d
GN
4458 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4459 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK
4460}
4461
89a27f4d 4462static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 4463{
89a27f4d
GN
4464 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4465 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK
4466}
4467
648dfaa7
MG
4468static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4469{
4470 struct kvm_segment var;
4471 u32 ar;
4472
4473 vmx_get_segment(vcpu, &var, seg);
07f42f5f 4474 var.dpl = 0x3;
0647f4aa
GN
4475 if (seg == VCPU_SREG_CS)
4476 var.type = 0x3;
648dfaa7
MG
4477 ar = vmx_segment_access_rights(&var);
4478
4479 if (var.base != (var.selector << 4))
4480 return false;
89efbed0 4481 if (var.limit != 0xffff)
648dfaa7 4482 return false;
07f42f5f 4483 if (ar != 0xf3)
648dfaa7
MG
4484 return false;
4485
4486 return true;
4487}
4488
4489static bool code_segment_valid(struct kvm_vcpu *vcpu)
4490{
4491 struct kvm_segment cs;
4492 unsigned int cs_rpl;
4493
4494 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 4495 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 4496
1872a3f4
AK
4497 if (cs.unusable)
4498 return false;
4d283ec9 4499 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG
4500 return false;
4501 if (!cs.s)
4502 return false;
4d283ec9 4503 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG
4504 if (cs.dpl > cs_rpl)
4505 return false;
1872a3f4 4506 } else {
648dfaa7
MG
4507 if (cs.dpl != cs_rpl)
4508 return false;
4509 }
4510 if (!cs.present)
4511 return false;
4512
4513 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4514 return true;
4515}
4516
4517static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4518{
4519 struct kvm_segment ss;
4520 unsigned int ss_rpl;
4521
4522 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 4523 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 4524
1872a3f4
AK
4525 if (ss.unusable)
4526 return true;
4527 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG
4528 return false;
4529 if (!ss.s)
4530 return false;
4531 if (ss.dpl != ss_rpl) /* DPL != RPL */
4532 return false;
4533 if (!ss.present)
4534 return false;
4535
4536 return true;
4537}
4538
4539static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4540{
4541 struct kvm_segment var;
4542 unsigned int rpl;
4543
4544 vmx_get_segment(vcpu, &var, seg);
b32a9918 4545 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 4546
1872a3f4
AK
4547 if (var.unusable)
4548 return true;
648dfaa7
MG
4549 if (!var.s)
4550 return false;
4551 if (!var.present)
4552 return false;
4d283ec9 4553 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG
4554 if (var.dpl < rpl) /* DPL < RPL */
4555 return false;
4556 }
4557
4558 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4559 * rights flags
4560 */
4561 return true;
4562}
4563
4564static bool tr_valid(struct kvm_vcpu *vcpu)
4565{
4566 struct kvm_segment tr;
4567
4568 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4569
1872a3f4
AK
4570 if (tr.unusable)
4571 return false;
b32a9918 4572 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 4573 return false;
1872a3f4 4574 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG
4575 return false;
4576 if (!tr.present)
4577 return false;
4578
4579 return true;
4580}
4581
4582static bool ldtr_valid(struct kvm_vcpu *vcpu)
4583{
4584 struct kvm_segment ldtr;
4585
4586 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4587
1872a3f4
AK
4588 if (ldtr.unusable)
4589 return true;
b32a9918 4590 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG
4591 return false;
4592 if (ldtr.type != 2)
4593 return false;
4594 if (!ldtr.present)
4595 return false;
4596
4597 return true;
4598}
4599
4600static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4601{
4602 struct kvm_segment cs, ss;
4603
4604 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4605 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4606
b32a9918
NA
4607 return ((cs.selector & SEGMENT_RPL_MASK) ==
4608 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG
4609}
4610
4611/*
4612 * Check if guest state is valid. Returns true if valid, false if
4613 * not.
4614 * We assume that registers are always usable
4615 */
4616static bool guest_state_valid(struct kvm_vcpu *vcpu)
4617{
c5e97c80
GN
4618 if (enable_unrestricted_guest)
4619 return true;
4620
648dfaa7 4621 /* real mode guest state checks */
f13882d8 4622 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG
4623 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4624 return false;
4625 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4626 return false;
4627 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4628 return false;
4629 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4630 return false;
4631 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4632 return false;
4633 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4634 return false;
4635 } else {
4636 /* protected mode guest state checks */
4637 if (!cs_ss_rpl_check(vcpu))
4638 return false;
4639 if (!code_segment_valid(vcpu))
4640 return false;
4641 if (!stack_segment_valid(vcpu))
4642 return false;
4643 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4644 return false;
4645 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4646 return false;
4647 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4648 return false;
4649 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4650 return false;
4651 if (!tr_valid(vcpu))
4652 return false;
4653 if (!ldtr_valid(vcpu))
4654 return false;
4655 }
4656 /* TODO:
4657 * - Add checks on RIP
4658 * - Add checks on RFLAGS
4659 */
4660
4661 return true;
4662}
4663
5fa99cbe
JM
4664static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4665{
4666 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4667}
4668
d77c26fc 4669static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4670{
40dcaa9f 4671 gfn_t fn;
195aefde 4672 u16 data = 0;
1f755a82 4673 int idx, r;
6aa8b732 4674
40dcaa9f 4675 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4676 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE
4677 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4678 if (r < 0)
10589a46 4679 goto out;
195aefde 4680 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY
4681 r = kvm_write_guest_page(kvm, fn++, &data,
4682 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4683 if (r < 0)
10589a46 4684 goto out;
195aefde
IE
4685 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4686 if (r < 0)
10589a46 4687 goto out;
195aefde
IE
4688 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4689 if (r < 0)
10589a46 4690 goto out;
195aefde 4691 data = ~0;
10589a46
MT
4692 r = kvm_write_guest_page(kvm, fn, &data,
4693 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4694 sizeof(u8));
10589a46 4695out:
40dcaa9f 4696 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4697 return r;
6aa8b732
AK
4698}
4699
b7ebfb05
SY
4700static int init_rmode_identity_map(struct kvm *kvm)
4701{
f51770ed 4702 int i, idx, r = 0;
ba049e93 4703 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY
4704 u32 tmp;
4705
089d034e 4706 if (!enable_ept)
f51770ed 4707 return 0;
a255d479
TC
4708
4709 /* Protect kvm->arch.ept_identity_pagetable_done. */
4710 mutex_lock(&kvm->slots_lock);
4711
f51770ed 4712 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4713 goto out2;
a255d479 4714
b927a3ce 4715 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC
4716
4717 r = alloc_identity_pagetable(kvm);
f51770ed 4718 if (r < 0)
a255d479
TC
4719 goto out2;
4720
40dcaa9f 4721 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY
4722 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4723 if (r < 0)
4724 goto out;
4725 /* Set up identity-mapping pagetable for EPT in real mode */
4726 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4727 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4728 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4729 r = kvm_write_guest_page(kvm, identity_map_pfn,
4730 &tmp, i * sizeof(tmp), sizeof(tmp));
4731 if (r < 0)
4732 goto out;
4733 }
4734 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4735
b7ebfb05 4736out:
40dcaa9f 4737 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC
4738
4739out2:
4740 mutex_unlock(&kvm->slots_lock);
f51770ed 4741 return r;
b7ebfb05
SY
4742}
4743
6aa8b732
AK
4744static void seg_setup(int seg)
4745{
772e0318 4746 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4747 unsigned int ar;
6aa8b732
AK
4748
4749 vmcs_write16(sf->selector, 0);
4750 vmcs_writel(sf->base, 0);
4751 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN
4752 ar = 0x93;
4753 if (seg == VCPU_SREG_CS)
4754 ar |= 0x08; /* code segment */
3a624e29
NK
4755
4756 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK
4757}
4758
f78e0e2e
SY
4759static int alloc_apic_access_page(struct kvm *kvm)
4760{
4484141a 4761 struct page *page;
f78e0e2e
SY
4762 int r = 0;
4763
79fac95e 4764 mutex_lock(&kvm->slots_lock);
c24ae0dc 4765 if (kvm->arch.apic_access_page_done)
f78e0e2e 4766 goto out;
1d8007bd
PB
4767 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4768 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY
4769 if (r)
4770 goto out;
72dc67a6 4771
73a6d941 4772 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG
4773 if (is_error_page(page)) {
4774 r = -EFAULT;
4775 goto out;
4776 }
4777
c24ae0dc
TC
4778 /*
4779 * Do not pin the page in memory, so that memory hot-unplug
4780 * is able to migrate it.
4781 */
4782 put_page(page);
4783 kvm->arch.apic_access_page_done = true;
f78e0e2e 4784out:
79fac95e 4785 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY
4786 return r;
4787}
4788
b7ebfb05
SY
4789static int alloc_identity_pagetable(struct kvm *kvm)
4790{
a255d479
TC
4791 /* Called with kvm->slots_lock held. */
4792
b7ebfb05
SY
4793 int r = 0;
4794
a255d479
TC
4795 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4796
1d8007bd
PB
4797 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4798 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
b7ebfb05 4799
b7ebfb05
SY
4800 return r;
4801}
4802
991e7a0e 4803static int allocate_vpid(void)
2384d2b3
SY
4804{
4805 int vpid;
4806
919818ab 4807 if (!enable_vpid)
991e7a0e 4808 return 0;
2384d2b3
SY
4809 spin_lock(&vmx_vpid_lock);
4810 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 4811 if (vpid < VMX_NR_VPIDS)
2384d2b3 4812 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL
4813 else
4814 vpid = 0;
2384d2b3 4815 spin_unlock(&vmx_vpid_lock);
991e7a0e 4816 return vpid;
2384d2b3
SY
4817}
4818
991e7a0e 4819static void free_vpid(int vpid)
cdbecfc3 4820{
991e7a0e 4821 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ
4822 return;
4823 spin_lock(&vmx_vpid_lock);
991e7a0e 4824 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ
4825 spin_unlock(&vmx_vpid_lock);
4826}
4827
8d14695f
YZ
4828#define MSR_TYPE_R 1
4829#define MSR_TYPE_W 2
4830static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4831 u32 msr, int type)
25c5f225 4832{
3e7c73e9 4833 int f = sizeof(unsigned long);
25c5f225
SY
4834
4835 if (!cpu_has_vmx_msr_bitmap())
4836 return;
4837
4838 /*
4839 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4840 * have the write-low and read-high bitmap offsets the wrong way round.
4841 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4842 */
25c5f225 4843 if (msr <= 0x1fff) {
8d14695f
YZ
4844 if (type & MSR_TYPE_R)
4845 /* read-low */
4846 __clear_bit(msr, msr_bitmap + 0x000 / f);
4847
4848 if (type & MSR_TYPE_W)
4849 /* write-low */
4850 __clear_bit(msr, msr_bitmap + 0x800 / f);
4851
25c5f225
SY
4852 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4853 msr &= 0x1fff;
8d14695f
YZ
4854 if (type & MSR_TYPE_R)
4855 /* read-high */
4856 __clear_bit(msr, msr_bitmap + 0x400 / f);
4857
4858 if (type & MSR_TYPE_W)
4859 /* write-high */
4860 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4861
4862 }
4863}
4864
f2b93280
WV
4865/*
4866 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4867 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4868 */
4869static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4870 unsigned long *msr_bitmap_nested,
4871 u32 msr, int type)
4872{
4873 int f = sizeof(unsigned long);
4874
4875 if (!cpu_has_vmx_msr_bitmap()) {
4876 WARN_ON(1);
4877 return;
4878 }
4879
4880 /*
4881 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4882 * have the write-low and read-high bitmap offsets the wrong way round.
4883 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4884 */
4885 if (msr <= 0x1fff) {
4886 if (type & MSR_TYPE_R &&
4887 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4888 /* read-low */
4889 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4890
4891 if (type & MSR_TYPE_W &&
4892 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4893 /* write-low */
4894 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4895
4896 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4897 msr &= 0x1fff;
4898 if (type & MSR_TYPE_R &&
4899 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4900 /* read-high */
4901 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4902
4903 if (type & MSR_TYPE_W &&
4904 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4905 /* write-high */
4906 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4907
4908 }
4909}
4910
5897297b
AK
4911static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4912{
4913 if (!longmode_only)
8d14695f
YZ
4914 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4915 msr, MSR_TYPE_R | MSR_TYPE_W);
4916 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4917 msr, MSR_TYPE_R | MSR_TYPE_W);
4918}
4919
2e69f865 4920static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
8d14695f 4921{
f6e90f9e 4922 if (apicv_active) {
c63e4563 4923 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
2e69f865 4924 msr, type);
c63e4563 4925 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
2e69f865 4926 msr, type);
f6e90f9e 4927 } else {
f6e90f9e 4928 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
2e69f865 4929 msr, type);
f6e90f9e 4930 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
2e69f865 4931 msr, type);
f6e90f9e 4932 }
5897297b
AK
4933}
4934
d62caabb 4935static bool vmx_get_enable_apicv(void)
d50ab6c1 4936{
d62caabb 4937 return enable_apicv;
d50ab6c1
PB
4938}
4939
6342c50a 4940static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
705699a1
WV
4941{
4942 struct vcpu_vmx *vmx = to_vmx(vcpu);
4943 int max_irr;
4944 void *vapic_page;
4945 u16 status;
4946
4947 if (vmx->nested.pi_desc &&
4948 vmx->nested.pi_pending) {
4949 vmx->nested.pi_pending = false;
4950 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
6342c50a 4951 return;
705699a1
WV
4952
4953 max_irr = find_last_bit(
4954 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4955
4956 if (max_irr == 256)
6342c50a 4957 return;
705699a1
WV
4958
4959 vapic_page = kmap(vmx->nested.virtual_apic_page);
705699a1
WV
4960 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4961 kunmap(vmx->nested.virtual_apic_page);
4962
4963 status = vmcs_read16(GUEST_INTR_STATUS);
4964 if ((u8)max_irr > ((u8)status & 0xff)) {
4965 status &= ~0xff;
4966 status |= (u8)max_irr;
4967 vmcs_write16(GUEST_INTR_STATUS, status);
4968 }
4969 }
705699a1
WV
4970}
4971
21bc8dc5
RK
4972static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4973{
4974#ifdef CONFIG_SMP
4975 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6
FW
4976 struct vcpu_vmx *vmx = to_vmx(vcpu);
4977
4978 /*
4979 * Currently, we don't support urgent interrupt,
4980 * all interrupts are recognized as non-urgent
4981 * interrupt, so we cannot post interrupts when
4982 * 'SN' is set.
4983 *
4984 * If the vcpu is in guest mode, it means it is
4985 * running instead of being scheduled out and
4986 * waiting in the run queue, and that's the only
4987 * case when 'SN' is set currently, warning if
4988 * 'SN' is set.
4989 */
4990 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4991
21bc8dc5
RK
4992 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4993 POSTED_INTR_VECTOR);
4994 return true;
4995 }
4996#endif
4997 return false;
4998}
4999
705699a1
WV
5000static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5001 int vector)
5002{
5003 struct vcpu_vmx *vmx = to_vmx(vcpu);
5004
5005 if (is_guest_mode(vcpu) &&
5006 vector == vmx->nested.posted_intr_nv) {
5007 /* the PIR and ON have been set by L1. */
21bc8dc5 5008 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV
5009 /*
5010 * If a posted intr is not recognized by hardware,
5011 * we will accomplish it in the next vmentry.
5012 */
5013 vmx->nested.pi_pending = true;
5014 kvm_make_request(KVM_REQ_EVENT, vcpu);
5015 return 0;
5016 }
5017 return -1;
5018}
a20ed54d
YZ
5019/*
5020 * Send interrupt to vcpu via posted interrupt way.
5021 * 1. If target vcpu is running(non-root mode), send posted interrupt
5022 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5023 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5024 * interrupt from PIR in next vmentry.
5025 */
5026static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5027{
5028 struct vcpu_vmx *vmx = to_vmx(vcpu);
5029 int r;
5030
705699a1
WV
5031 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5032 if (!r)
5033 return;
5034
a20ed54d
YZ
5035 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5036 return;
5037
b95234c8
PB
5038 /* If a previous notification has sent the IPI, nothing to do. */
5039 if (pi_test_and_set_on(&vmx->pi_desc))
5040 return;
5041
5042 if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ
5043 kvm_vcpu_kick(vcpu);
5044}
5045
a3a8ff8e
NHE
5046/*
5047 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5048 * will not change in the lifetime of the guest.
5049 * Note that host-state that does change is set elsewhere. E.g., host-state
5050 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5051 */
a547c6db 5052static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE
5053{
5054 u32 low32, high32;
5055 unsigned long tmpl;
5056 struct desc_ptr dt;
d6e41f11 5057 unsigned long cr0, cr3, cr4;
a3a8ff8e 5058
04ac88ab
AL
5059 cr0 = read_cr0();
5060 WARN_ON(cr0 & X86_CR0_TS);
5061 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL
5062
5063 /*
5064 * Save the most likely value for this task's CR3 in the VMCS.
5065 * We can't use __get_current_cr3_fast() because we're not atomic.
5066 */
6c690ee1 5067 cr3 = __read_cr3();
d6e41f11
AL
5068 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5069 vmx->host_state.vmcs_host_cr3 = cr3;
a3a8ff8e 5070
d974baa3 5071 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 5072 cr4 = cr4_read_shadow();
d974baa3
AL
5073 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5074 vmx->host_state.vmcs_host_cr4 = cr4;
5075
a3a8ff8e 5076 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK
5077#ifdef CONFIG_X86_64
5078 /*
5079 * Load null selectors, so we can avoid reloading them in
5080 * __vmx_load_host_state(), in case userspace uses the null selectors
5081 * too (the expected case).
5082 */
5083 vmcs_write16(HOST_DS_SELECTOR, 0);
5084 vmcs_write16(HOST_ES_SELECTOR, 0);
5085#else
a3a8ff8e
NHE
5086 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5087 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 5088#endif
a3a8ff8e
NHE
5089 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5090 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5091
5092 native_store_idt(&dt);
5093 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 5094 vmx->host_idt_base = dt.address;
a3a8ff8e 5095
83287ea4 5096 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE
5097
5098 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5099 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5100 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5101 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5102
5103 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5104 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5105 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5106 }
5107}
5108
bf8179a0
NHE
5109static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5110{
5111 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5112 if (enable_ept)
5113 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE
5114 if (is_guest_mode(&vmx->vcpu))
5115 vmx->vcpu.arch.cr4_guest_owned_bits &=
5116 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE
5117 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5118}
5119
01e439be
YZ
5120static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5121{
5122 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5123
d62caabb 5124 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 5125 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
64672c95
YJ
5126 /* Enable the preemption timer dynamically */
5127 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ
5128 return pin_based_exec_ctrl;
5129}
5130
d62caabb
AS
5131static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5132{
5133 struct vcpu_vmx *vmx = to_vmx(vcpu);
5134
5135 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK
5136 if (cpu_has_secondary_exec_ctrls()) {
5137 if (kvm_vcpu_apicv_active(vcpu))
5138 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5139 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5140 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5141 else
5142 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5143 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5144 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5145 }
5146
5147 if (cpu_has_vmx_msr_bitmap())
5148 vmx_set_msr_bitmap(vcpu);
d62caabb
AS
5149}
5150
bf8179a0
NHE
5151static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5152{
5153 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB
5154
5155 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5156 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5157
35754c98 5158 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE
5159 exec_control &= ~CPU_BASED_TPR_SHADOW;
5160#ifdef CONFIG_X86_64
5161 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5162 CPU_BASED_CR8_LOAD_EXITING;
5163#endif
5164 }
5165 if (!enable_ept)
5166 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5167 CPU_BASED_CR3_LOAD_EXITING |
5168 CPU_BASED_INVLPG_EXITING;
5169 return exec_control;
5170}
5171
5172static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5173{
5174 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 5175 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE
5176 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5177 if (vmx->vpid == 0)
5178 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5179 if (!enable_ept) {
5180 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5181 enable_unrestricted_guest = 0;
ad756a16
MJ
5182 /* Enable INVPCID for non-ept guests may cause performance regression. */
5183 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE
5184 }
5185 if (!enable_unrestricted_guest)
5186 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5187 if (!ple_gap)
5188 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
d62caabb 5189 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
c7c9c56c
YZ
5190 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5191 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 5192 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG
5193 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5194 (handle_vmptrld).
5195 We can NOT enable shadow_vmcs here because we don't have yet
5196 a current VMCS12
5197 */
5198 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH
5199
5200 if (!enable_pml)
5201 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 5202
bf8179a0
NHE
5203 return exec_control;
5204}
5205
ce88decf
XG
5206static void ept_set_mmio_spte_mask(void)
5207{
5208 /*
5209 * EPT Misconfigurations can be generated if the value of bits 2:0
5210 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 5211 */
dcdca5fe
PF
5212 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5213 VMX_EPT_MISCONFIG_WX_VALUE);
ce88decf
XG
5214}
5215
f53cd63c 5216#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK
5217/*
5218 * Sets up the vmcs for emulated real mode.
5219 */
8b9cf98c 5220static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 5221{
2e4ce7f5 5222#ifdef CONFIG_X86_64
6aa8b732 5223 unsigned long a;
2e4ce7f5 5224#endif
6aa8b732 5225 int i;
6aa8b732 5226
6aa8b732 5227 /* I/O */
3e7c73e9
AK
5228 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5229 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 5230
4607c2d7
AG
5231 if (enable_shadow_vmcs) {
5232 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5233 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5234 }
25c5f225 5235 if (cpu_has_vmx_msr_bitmap())
5897297b 5236 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 5237
6aa8b732
AK
5238 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5239
6aa8b732 5240 /* Control */
01e439be 5241 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
64672c95 5242 vmx->hv_deadline_tsc = -1;
6e5d865c 5243
bf8179a0 5244 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 5245
dfa169bb 5246 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE
5247 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5248 vmx_secondary_exec_control(vmx));
dfa169bb 5249 }
f78e0e2e 5250
d62caabb 5251 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ
5252 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5253 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5254 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5255 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5256
5257 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 5258
0bcf261c 5259 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 5260 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ
5261 }
5262
4b8d54f9
ZE
5263 if (ple_gap) {
5264 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK
5265 vmx->ple_window = ple_window;
5266 vmx->ple_window_dirty = true;
4b8d54f9
ZE
5267 }
5268
c3707958
XG
5269 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5270 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK
5271 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5272
9581d442
AK
5273 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5274 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 5275 vmx_set_constant_host_state(vmx);
05b3e0c2 5276#ifdef CONFIG_X86_64
6aa8b732
AK
5277 rdmsrl(MSR_FS_BASE, a);
5278 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5279 rdmsrl(MSR_GS_BASE, a);
5280 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5281#else
5282 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5283 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5284#endif
5285
2cc51560
ED
5286 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5287 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 5288 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 5289 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 5290 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 5291
74545705
RK
5292 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5293 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 5294
03916db9 5295 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK
5296 u32 index = vmx_msr_index[i];
5297 u32 data_low, data_high;
a2fa3e9f 5298 int j = vmx->nmsrs;
6aa8b732
AK
5299
5300 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5301 continue;
432bd6cb
AK
5302 if (wrmsr_safe(index, data_low, data_high) < 0)
5303 continue;
26bb0981
AK
5304 vmx->guest_msrs[j].index = i;
5305 vmx->guest_msrs[j].data = 0;
d5696725 5306 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 5307 ++vmx->nmsrs;
6aa8b732 5308 }
6aa8b732 5309
2961e876
GN
5310
5311 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK
5312
5313 /* 22.2.1, 20.8.1 */
2961e876 5314 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 5315
bd7e5b08
PB
5316 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5317 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5318
bf8179a0 5319 set_cr4_guest_host_mask(vmx);
e00c8cf2 5320
f53cd63c
WL
5321 if (vmx_xsaves_supported())
5322 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5323
4e59516a
PF
5324 if (enable_pml) {
5325 ASSERT(vmx->pml_pg);
5326 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5327 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5328 }
5329
e00c8cf2
AK
5330 return 0;
5331}
5332
d28bc9dd 5333static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK
5334{
5335 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 5336 struct msr_data apic_base_msr;
d28bc9dd 5337 u64 cr0;
e00c8cf2 5338
7ffd92c5 5339 vmx->rmode.vm86_active = 0;
e00c8cf2 5340
ad312c7c 5341 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA
5342 kvm_set_cr8(vcpu, 0);
5343
5344 if (!init_event) {
5345 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5346 MSR_IA32_APICBASE_ENABLE;
5347 if (kvm_vcpu_is_reset_bsp(vcpu))
5348 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5349 apic_base_msr.host_initiated = true;
5350 kvm_set_apic_base(vcpu, &apic_base_msr);
5351 }
e00c8cf2 5352
2fb92db1
AK
5353 vmx_segment_cache_clear(vmx);
5354
5706be0d 5355 seg_setup(VCPU_SREG_CS);
66450a21 5356 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 5357 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK
5358
5359 seg_setup(VCPU_SREG_DS);
5360 seg_setup(VCPU_SREG_ES);
5361 seg_setup(VCPU_SREG_FS);
5362 seg_setup(VCPU_SREG_GS);
5363 seg_setup(VCPU_SREG_SS);
5364
5365 vmcs_write16(GUEST_TR_SELECTOR, 0);
5366 vmcs_writel(GUEST_TR_BASE, 0);
5367 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5368 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5369
5370 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5371 vmcs_writel(GUEST_LDTR_BASE, 0);
5372 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5373 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5374
d28bc9dd
NA
5375 if (!init_event) {
5376 vmcs_write32(GUEST_SYSENTER_CS, 0);
5377 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5378 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5379 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5380 }
e00c8cf2
AK
5381
5382 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 5383 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 5384
e00c8cf2
AK
5385 vmcs_writel(GUEST_GDTR_BASE, 0);
5386 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5387
5388 vmcs_writel(GUEST_IDTR_BASE, 0);
5389 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5390
443381a8 5391 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 5392 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 5393 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
e00c8cf2 5394
e00c8cf2
AK
5395 setup_msrs(vmx);
5396
6aa8b732
AK
5397 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5398
d28bc9dd 5399 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 5400 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 5401 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 5402 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 5403 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY
5404 vmcs_write32(TPR_THRESHOLD, 0);
5405 }
5406
a73896cb 5407 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 5408
d62caabb 5409 if (kvm_vcpu_apicv_active(vcpu))
01e439be
YZ
5410 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5411
2384d2b3
SY
5412 if (vmx->vpid != 0)
5413 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5414
d28bc9dd 5415 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 5416 vmx->vcpu.arch.cr0 = cr0;
f2463247 5417 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 5418 vmx_set_cr4(vcpu, 0);
5690891b 5419 vmx_set_efer(vcpu, 0);
bd7e5b08 5420
d28bc9dd 5421 update_exception_bitmap(vcpu);
6aa8b732 5422
dd5f5341 5423 vpid_sync_context(vmx->vpid);
6aa8b732
AK
5424}
5425
b6f1250e
NHE
5426/*
5427 * In nested virtualization, check if L1 asked to exit on external interrupts.
5428 * For most existing hypervisors, this will always return true.
5429 */
5430static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5431{
5432 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5433 PIN_BASED_EXT_INTR_MASK;
5434}
5435
77b0f5d6
BD
5436/*
5437 * In nested virtualization, check if L1 has set
5438 * VM_EXIT_ACK_INTR_ON_EXIT
5439 */
5440static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5441{
5442 return get_vmcs12(vcpu)->vm_exit_controls &
5443 VM_EXIT_ACK_INTR_ON_EXIT;
5444}
5445
ea8ceb83
JK
5446static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5447{
5448 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5449 PIN_BASED_NMI_EXITING;
5450}
5451
c9a7953f 5452static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 5453{
47c0152e
PB
5454 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5455 CPU_BASED_VIRTUAL_INTR_PENDING);
3b86cd99
JK
5456}
5457
c9a7953f 5458static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 5459{
2c82878b 5460 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK
5461 enable_irq_window(vcpu);
5462 return;
5463 }
3b86cd99 5464
47c0152e
PB
5465 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5466 CPU_BASED_VIRTUAL_NMI_PENDING);
3b86cd99
JK
5467}
5468
66fd3f7f 5469static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 5470{
9c8cba37 5471 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN
5472 uint32_t intr;
5473 int irq = vcpu->arch.interrupt.nr;
9c8cba37 5474
229456fc 5475 trace_kvm_inj_virq(irq);
2714d1d3 5476
fa89a817 5477 ++vcpu->stat.irq_injections;
7ffd92c5 5478 if (vmx->rmode.vm86_active) {
71f9833b
SH
5479 int inc_eip = 0;
5480 if (vcpu->arch.interrupt.soft)
5481 inc_eip = vcpu->arch.event_exit_inst_len;
5482 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 5483 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED
5484 return;
5485 }
66fd3f7f
GN
5486 intr = irq | INTR_INFO_VALID_MASK;
5487 if (vcpu->arch.interrupt.soft) {
5488 intr |= INTR_TYPE_SOFT_INTR;
5489 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5490 vmx->vcpu.arch.event_exit_inst_len);
5491 } else
5492 intr |= INTR_TYPE_EXT_INTR;
5493 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED
5494}
5495
f08864b4
SY
5496static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5497{
66a5a347
JK
5498 struct vcpu_vmx *vmx = to_vmx(vcpu);
5499
c5a6d5f7 5500 if (!is_guest_mode(vcpu)) {
c5a6d5f7
WL
5501 ++vcpu->stat.nmi_injections;
5502 vmx->nmi_known_unmasked = false;
3b86cd99
JK
5503 }
5504
7ffd92c5 5505 if (vmx->rmode.vm86_active) {
71f9833b 5506 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 5507 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK
5508 return;
5509 }
c5a6d5f7 5510
f08864b4
SY
5511 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5512 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY
5513}
5514
3cfc3092
JK
5515static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5516{
9d58b931
AK
5517 if (to_vmx(vcpu)->nmi_known_unmasked)
5518 return false;
c332c83a 5519 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK
5520}
5521
5522static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5523{
5524 struct vcpu_vmx *vmx = to_vmx(vcpu);
5525
2c82878b
PB
5526 vmx->nmi_known_unmasked = !masked;
5527 if (masked)
5528 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5529 GUEST_INTR_STATE_NMI);
5530 else
5531 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5532 GUEST_INTR_STATE_NMI);
3cfc3092
JK
5533}
5534
2505dc9f
JK
5535static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5536{
b6b8a145
JK
5537 if (to_vmx(vcpu)->nested.nested_run_pending)
5538 return 0;
ea8ceb83 5539
2505dc9f
JK
5540 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5541 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5542 | GUEST_INTR_STATE_NMI));
5543}
5544
78646121
GN
5545static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5546{
b6b8a145
JK
5547 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5548 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN
5549 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5550 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN
5551}
5552
cbc94022
IE
5553static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5554{
5555 int ret;
cbc94022 5556
1d8007bd
PB
5557 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5558 PAGE_SIZE * 3);
cbc94022
IE
5559 if (ret)
5560 return ret;
bfc6d222 5561 kvm->arch.tss_addr = addr;
1f755a82 5562 return init_rmode_tss(kvm);
cbc94022
IE
5563}
5564
0ca1b4f4 5565static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 5566{
77ab6db0 5567 switch (vec) {
77ab6db0 5568 case BP_VECTOR:
c573cd22
JK
5569 /*
5570 * Update instruction length as we may reinject the exception
5571 * from user space while in guest debugging mode.
5572 */
5573 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5574 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 5575 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN
5576 return false;
5577 /* fall through */
5578 case DB_VECTOR:
5579 if (vcpu->guest_debug &
5580 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5581 return false;
d0bfb940
JK
5582 /* fall through */
5583 case DE_VECTOR:
77ab6db0
JK
5584 case OF_VECTOR:
5585 case BR_VECTOR:
5586 case UD_VECTOR:
5587 case DF_VECTOR:
5588 case SS_VECTOR:
5589 case GP_VECTOR:
5590 case MF_VECTOR:
0ca1b4f4
GN
5591 return true;
5592 break;
77ab6db0 5593 }
0ca1b4f4
GN
5594 return false;
5595}
5596
5597static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5598 int vec, u32 err_code)
5599{
5600 /*
5601 * Instruction with address size override prefix opcode 0x67
5602 * Cause the #SS fault with 0 error code in VM86 mode.
5603 */
5604 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5605 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5606 if (vcpu->arch.halt_request) {
5607 vcpu->arch.halt_request = 0;
5cb56059 5608 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN
5609 }
5610 return 1;
5611 }
5612 return 0;
5613 }
5614
5615 /*
5616 * Forward all other exceptions that are valid in real mode.
5617 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5618 * the required debugging infrastructure rework.
5619 */
5620 kvm_queue_exception(vcpu, vec);
5621 return 1;
6aa8b732
AK
5622}
5623
a0861c02
AK
5624/*
5625 * Trigger machine check on the host. We assume all the MSRs are already set up
5626 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5627 * We pass a fake environment to the machine check handler because we want
5628 * the guest to be always treated like user space, no matter what context
5629 * it used internally.
5630 */
5631static void kvm_machine_check(void)
5632{
5633#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5634 struct pt_regs regs = {
5635 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5636 .flags = X86_EFLAGS_IF,
5637 };
5638
5639 do_machine_check(&regs, 0);
5640#endif
5641}
5642
851ba692 5643static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK
5644{
5645 /* already handled by vcpu_run */
5646 return 1;
5647}
5648
851ba692 5649static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5650{
1155f76a 5651 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5652 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5653 u32 intr_info, ex_no, error_code;
42dbaa5a 5654 unsigned long cr2, rip, dr6;
6aa8b732
AK
5655 u32 vect_info;
5656 enum emulation_result er;
5657
1155f76a 5658 vect_info = vmx->idt_vectoring_info;
88786475 5659 intr_info = vmx->exit_intr_info;
6aa8b732 5660
a0861c02 5661 if (is_machine_check(intr_info))
851ba692 5662 return handle_machine_check(vcpu);
a0861c02 5663
ef85b673 5664 if (is_nmi(intr_info))
1b6269db 5665 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc 5666
7aa81cc0 5667 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK
5668 if (is_guest_mode(vcpu)) {
5669 kvm_queue_exception(vcpu, UD_VECTOR);
5670 return 1;
5671 }
51d8b661 5672 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5673 if (er != EMULATE_DONE)
7ee5d940 5674 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL
5675 return 1;
5676 }
5677
6aa8b732 5678 error_code = 0;
2e11384c 5679 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5680 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG
5681
5682 /*
5683 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5684 * MMIO, it is better to report an internal error.
5685 * See the comments in vmx_handle_exit.
5686 */
5687 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5688 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5689 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5690 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5691 vcpu->run->internal.ndata = 3;
bf4ca23e
XG
5692 vcpu->run->internal.data[0] = vect_info;
5693 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5694 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG
5695 return 0;
5696 }
5697
6aa8b732 5698 if (is_page_fault(intr_info)) {
1439442c 5699 /* EPT won't cause page fault directly */
cf3ace79 5700 BUG_ON(enable_ept);
6aa8b732 5701 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT
5702 trace_kvm_page_fault(cr2, error_code);
5703
3298b75c 5704 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5705 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5706 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK
5707 }
5708
d0bfb940 5709 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN
5710
5711 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5712 return handle_rmode_exception(vcpu, ex_no, error_code);
5713
42dbaa5a 5714 switch (ex_no) {
54a20552
EN
5715 case AC_VECTOR:
5716 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5717 return 1;
42dbaa5a
JK
5718 case DB_VECTOR:
5719 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5720 if (!(vcpu->guest_debug &
5721 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5722 vcpu->arch.dr6 &= ~15;
6f43ed01 5723 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD
5724 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5725 skip_emulated_instruction(vcpu);
5726
42dbaa5a
JK
5727 kvm_queue_exception(vcpu, DB_VECTOR);
5728 return 1;
5729 }
5730 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5731 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5732 /* fall through */
5733 case BP_VECTOR:
c573cd22
JK
5734 /*
5735 * Update instruction length as we may reinject #BP from
5736 * user space while in guest debugging mode. Reading it for
5737 * #DB as well causes no harm, it is not used in that case.
5738 */
5739 vmx->vcpu.arch.event_exit_inst_len =
5740 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5741 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5742 rip = kvm_rip_read(vcpu);
d0bfb940
JK
5743 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5744 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK
5745 break;
5746 default:
d0bfb940
JK
5747 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5748 kvm_run->ex.exception = ex_no;
5749 kvm_run->ex.error_code = error_code;
42dbaa5a 5750 break;
6aa8b732 5751 }
6aa8b732
AK
5752 return 0;
5753}
5754
851ba692 5755static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5756{
1165f5fe 5757 ++vcpu->stat.irq_exits;
6aa8b732
AK
5758 return 1;
5759}
5760
851ba692 5761static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5762{
851ba692 5763 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK
5764 return 0;
5765}
6aa8b732 5766
851ba692 5767static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5768{
bfdaab09 5769 unsigned long exit_qualification;
6affcbed 5770 int size, in, string, ret;
039576c0 5771 unsigned port;
6aa8b732 5772
bfdaab09 5773 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5774 string = (exit_qualification & 16) != 0;
cf8f70bf 5775 in = (exit_qualification & 8) != 0;
e70669ab 5776
cf8f70bf 5777 ++vcpu->stat.io_exits;
e70669ab 5778
cf8f70bf 5779 if (string || in)
51d8b661 5780 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5781
cf8f70bf
GN
5782 port = exit_qualification >> 16;
5783 size = (exit_qualification & 7) + 1;
cf8f70bf 5784
6affcbed
KH
5785 ret = kvm_skip_emulated_instruction(vcpu);
5786
5787 /*
5788 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5789 * KVM_EXIT_DEBUG here.
5790 */
5791 return kvm_fast_pio_out(vcpu, size, port) && ret;
6aa8b732
AK
5792}
5793
102d8325
IM
5794static void
5795vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5796{
5797 /*
5798 * Patch in the VMCALL instruction:
5799 */
5800 hypercall[0] = 0x0f;
5801 hypercall[1] = 0x01;
5802 hypercall[2] = 0xc1;
102d8325
IM
5803}
5804
0fa06071 5805/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE
5806static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5807{
eeadf9e7 5808 if (is_guest_mode(vcpu)) {
1a0d74e6
JK
5809 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5810 unsigned long orig_val = val;
5811
eeadf9e7
NHE
5812 /*
5813 * We get here when L2 changed cr0 in a way that did not change
5814 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK
5815 * but did change L0 shadowed bits. So we first calculate the
5816 * effective cr0 value that L1 would like to write into the
5817 * hardware. It consists of the L2-owned bits from the new
5818 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5819 */
1a0d74e6
JK
5820 val = (val & ~vmcs12->cr0_guest_host_mask) |
5821 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5822
3899152c 5823 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 5824 return 1;
1a0d74e6
JK
5825
5826 if (kvm_set_cr0(vcpu, val))
5827 return 1;
5828 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5829 return 0;
1a0d74e6
JK
5830 } else {
5831 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 5832 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 5833 return 1;
3899152c 5834
eeadf9e7 5835 return kvm_set_cr0(vcpu, val);
1a0d74e6 5836 }
eeadf9e7
NHE
5837}
5838
5839static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5840{
5841 if (is_guest_mode(vcpu)) {
1a0d74e6
JK
5842 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5843 unsigned long orig_val = val;
5844
5845 /* analogously to handle_set_cr0 */
5846 val = (val & ~vmcs12->cr4_guest_host_mask) |
5847 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5848 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5849 return 1;
1a0d74e6 5850 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE
5851 return 0;
5852 } else
5853 return kvm_set_cr4(vcpu, val);
5854}
5855
851ba692 5856static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5857{
229456fc 5858 unsigned long exit_qualification, val;
6aa8b732
AK
5859 int cr;
5860 int reg;
49a9b07e 5861 int err;
6affcbed 5862 int ret;
6aa8b732 5863
bfdaab09 5864 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK
5865 cr = exit_qualification & 15;
5866 reg = (exit_qualification >> 8) & 15;
5867 switch ((exit_qualification >> 4) & 3) {
5868 case 0: /* mov to cr */
1e32c079 5869 val = kvm_register_readl(vcpu, reg);
229456fc 5870 trace_kvm_cr_write(cr, val);
6aa8b732
AK
5871 switch (cr) {
5872 case 0:
eeadf9e7 5873 err = handle_set_cr0(vcpu, val);
6affcbed 5874 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 5875 case 3:
2390218b 5876 err = kvm_set_cr3(vcpu, val);
6affcbed 5877 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 5878 case 4:
eeadf9e7 5879 err = handle_set_cr4(vcpu, val);
6affcbed 5880 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN
5881 case 8: {
5882 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5883 u8 cr8 = (u8)val;
eea1cff9 5884 err = kvm_set_cr8(vcpu, cr8);
6affcbed 5885 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 5886 if (lapic_in_kernel(vcpu))
6affcbed 5887 return ret;
0a5fff19 5888 if (cr8_prev <= cr8)
6affcbed
KH
5889 return ret;
5890 /*
5891 * TODO: we might be squashing a
5892 * KVM_GUESTDBG_SINGLESTEP-triggered
5893 * KVM_EXIT_DEBUG here.
5894 */
851ba692 5895 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN
5896 return 0;
5897 }
4b8073e4 5898 }
6aa8b732 5899 break;
25c4c276 5900 case 2: /* clts */
bd7e5b08
PB
5901 WARN_ONCE(1, "Guest should always own CR0.TS");
5902 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 5903 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 5904 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5905 case 1: /*mov from cr*/
5906 switch (cr) {
5907 case 3:
9f8fe504
AK
5908 val = kvm_read_cr3(vcpu);
5909 kvm_register_write(vcpu, reg, val);
5910 trace_kvm_cr_read(cr, val);
6affcbed 5911 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 5912 case 8:
229456fc
MT
5913 val = kvm_get_cr8(vcpu);
5914 kvm_register_write(vcpu, reg, val);
5915 trace_kvm_cr_read(cr, val);
6affcbed 5916 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5917 }
5918 break;
5919 case 3: /* lmsw */
a1f83a74 5920 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5921 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5922 kvm_lmsw(vcpu, val);
6aa8b732 5923
6affcbed 5924 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5925 default:
5926 break;
5927 }
851ba692 5928 vcpu->run->exit_reason = 0;
a737f256 5929 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK
5930 (int)(exit_qualification >> 4) & 3, cr);
5931 return 0;
5932}
5933
851ba692 5934static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5935{
bfdaab09 5936 unsigned long exit_qualification;
16f8a6f9
NA
5937 int dr, dr7, reg;
5938
5939 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5940 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5941
5942 /* First, if DR does not exist, trigger UD */
5943 if (!kvm_require_dr(vcpu, dr))
5944 return 1;
6aa8b732 5945
f2483415 5946 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK
5947 if (!kvm_require_cpl(vcpu, 0))
5948 return 1;
16f8a6f9
NA
5949 dr7 = vmcs_readl(GUEST_DR7);
5950 if (dr7 & DR7_GD) {
42dbaa5a
JK
5951 /*
5952 * As the vm-exit takes precedence over the debug trap, we
5953 * need to emulate the latter, either for the host or the
5954 * guest debugging itself.
5955 */
5956 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5957 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5958 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5959 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK
5960 vcpu->run->debug.arch.exception = DB_VECTOR;
5961 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK
5962 return 0;
5963 } else {
7305eb5d 5964 vcpu->arch.dr6 &= ~15;
6f43ed01 5965 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK
5966 kvm_queue_exception(vcpu, DB_VECTOR);
5967 return 1;
5968 }
5969 }
5970
81908bf4 5971 if (vcpu->guest_debug == 0) {
8f22372f
PB
5972 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5973 CPU_BASED_MOV_DR_EXITING);
81908bf4
PB
5974
5975 /*
5976 * No more DR vmexits; force a reload of the debug registers
5977 * and reenter on this instruction. The next vmexit will
5978 * retrieve the full state of the debug registers.
5979 */
5980 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5981 return 1;
5982 }
5983
42dbaa5a
JK
5984 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5985 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5986 unsigned long val;
4c4d563b
JK
5987
5988 if (kvm_get_dr(vcpu, dr, &val))
5989 return 1;
5990 kvm_register_write(vcpu, reg, val);
020df079 5991 } else
5777392e 5992 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK
5993 return 1;
5994
6affcbed 5995 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
5996}
5997
73aaf249
JK
5998static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5999{
6000 return vcpu->arch.dr6;
6001}
6002
6003static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6004{
6005}
6006
81908bf4
PB
6007static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6008{
81908bf4
PB
6009 get_debugreg(vcpu->arch.db[0], 0);
6010 get_debugreg(vcpu->arch.db[1], 1);
6011 get_debugreg(vcpu->arch.db[2], 2);
6012 get_debugreg(vcpu->arch.db[3], 3);
6013 get_debugreg(vcpu->arch.dr6, 6);
6014 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6015
6016 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
8f22372f 6017 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
81908bf4
PB
6018}
6019
020df079
GN
6020static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6021{
6022 vmcs_writel(GUEST_DR7, val);
6023}
6024
851ba692 6025static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 6026{
6a908b62 6027 return kvm_emulate_cpuid(vcpu);
6aa8b732
AK
6028}
6029
851ba692 6030static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 6031{
ad312c7c 6032 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 6033 struct msr_data msr_info;
6aa8b732 6034
609e36d3
PB
6035 msr_info.index = ecx;
6036 msr_info.host_initiated = false;
6037 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 6038 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 6039 kvm_inject_gp(vcpu, 0);
6aa8b732
AK
6040 return 1;
6041 }
6042
609e36d3 6043 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 6044
6aa8b732 6045 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB
6046 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6047 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6affcbed 6048 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
6049}
6050
851ba692 6051static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 6052{
8fe8ab46 6053 struct msr_data msr;
ad312c7c
ZX
6054 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6055 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6056 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 6057
8fe8ab46
WA
6058 msr.data = data;
6059 msr.index = ecx;
6060 msr.host_initiated = false;
854e8bb1 6061 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 6062 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 6063 kvm_inject_gp(vcpu, 0);
6aa8b732
AK
6064 return 1;
6065 }
6066
59200273 6067 trace_kvm_msr_write(ecx, data);
6affcbed 6068 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK
6069}
6070
851ba692 6071static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 6072{
eb90f341 6073 kvm_apic_update_ppr(vcpu);
6e5d865c
YS
6074 return 1;
6075}
6076
851ba692 6077static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 6078{
47c0152e
PB
6079 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6080 CPU_BASED_VIRTUAL_INTR_PENDING);
2714d1d3 6081
3842d135
AK
6082 kvm_make_request(KVM_REQ_EVENT, vcpu);
6083
a26bf12a 6084 ++vcpu->stat.irq_window_exits;
6aa8b732
AK
6085 return 1;
6086}
6087
851ba692 6088static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 6089{
d3bef15f 6090 return kvm_emulate_halt(vcpu);
6aa8b732
AK
6091}
6092
851ba692 6093static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 6094{
0d9c055e 6095 return kvm_emulate_hypercall(vcpu);
c21415e8
IM
6096}
6097
ec25d5e6
GN
6098static int handle_invd(struct kvm_vcpu *vcpu)
6099{
51d8b661 6100 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN
6101}
6102
851ba692 6103static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 6104{
f9c617f6 6105 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT
6106
6107 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 6108 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT
6109}
6110
fee84b07
AK
6111static int handle_rdpmc(struct kvm_vcpu *vcpu)
6112{
6113 int err;
6114
6115 err = kvm_rdpmc(vcpu);
6affcbed 6116 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK
6117}
6118
851ba692 6119static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 6120{
6affcbed 6121 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED
6122}
6123
2acf923e
DC
6124static int handle_xsetbv(struct kvm_vcpu *vcpu)
6125{
6126 u64 new_bv = kvm_read_edx_eax(vcpu);
6127 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6128
6129 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 6130 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC
6131 return 1;
6132}
6133
f53cd63c
WL
6134static int handle_xsaves(struct kvm_vcpu *vcpu)
6135{
6affcbed 6136 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL
6137 WARN(1, "this should never happen\n");
6138 return 1;
6139}
6140
6141static int handle_xrstors(struct kvm_vcpu *vcpu)
6142{
6affcbed 6143 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL
6144 WARN(1, "this should never happen\n");
6145 return 1;
6146}
6147
851ba692 6148static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 6149{
58fbbf26
KT
6150 if (likely(fasteoi)) {
6151 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6152 int access_type, offset;
6153
6154 access_type = exit_qualification & APIC_ACCESS_TYPE;
6155 offset = exit_qualification & APIC_ACCESS_OFFSET;
6156 /*
6157 * Sane guest uses MOV to write EOI, with written value
6158 * not cared. So make a short-circuit here by avoiding
6159 * heavy instruction emulation.
6160 */
6161 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6162 (offset == APIC_EOI)) {
6163 kvm_lapic_set_eoi(vcpu);
6affcbed 6164 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT
6165 }
6166 }
51d8b661 6167 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY
6168}
6169
c7c9c56c
YZ
6170static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6171{
6172 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6173 int vector = exit_qualification & 0xff;
6174
6175 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6176 kvm_apic_set_eoi_accelerated(vcpu, vector);
6177 return 1;
6178}
6179
83d4c286
YZ
6180static int handle_apic_write(struct kvm_vcpu *vcpu)
6181{
6182 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6183 u32 offset = exit_qualification & 0xfff;
6184
6185 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6186 kvm_apic_write_nodecode(vcpu, offset);
6187 return 1;
6188}
6189
851ba692 6190static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 6191{
60637aac 6192 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 6193 unsigned long exit_qualification;
e269fb21
JK
6194 bool has_error_code = false;
6195 u32 error_code = 0;
37817f29 6196 u16 tss_selector;
7f3d35fd 6197 int reason, type, idt_v, idt_index;
64a7ec06
GN
6198
6199 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 6200 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 6201 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE
6202
6203 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6204
6205 reason = (u32)exit_qualification >> 30;
64a7ec06
GN
6206 if (reason == TASK_SWITCH_GATE && idt_v) {
6207 switch (type) {
6208 case INTR_TYPE_NMI_INTR:
6209 vcpu->arch.nmi_injected = false;
654f06fc 6210 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN
6211 break;
6212 case INTR_TYPE_EXT_INTR:
66fd3f7f 6213 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN
6214 kvm_clear_interrupt_queue(vcpu);
6215 break;
6216 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK
6217 if (vmx->idt_vectoring_info &
6218 VECTORING_INFO_DELIVER_CODE_MASK) {
6219 has_error_code = true;
6220 error_code =
6221 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6222 }
6223 /* fall through */
64a7ec06
GN
6224 case INTR_TYPE_SOFT_EXCEPTION:
6225 kvm_clear_exception_queue(vcpu);
6226 break;
6227 default:
6228 break;
6229 }
60637aac 6230 }
37817f29
IE
6231 tss_selector = exit_qualification;
6232
64a7ec06
GN
6233 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6234 type != INTR_TYPE_EXT_INTR &&
6235 type != INTR_TYPE_NMI_INTR))
6236 skip_emulated_instruction(vcpu);
6237
7f3d35fd
KW
6238 if (kvm_task_switch(vcpu, tss_selector,
6239 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6240 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN
6241 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6242 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6243 vcpu->run->internal.ndata = 0;
42dbaa5a 6244 return 0;
acb54517 6245 }
42dbaa5a 6246
42dbaa5a
JK
6247 /*
6248 * TODO: What about debug traps on tss switch?
6249 * Are we supposed to inject them and update dr6?
6250 */
6251
6252 return 1;
37817f29
IE
6253}
6254
851ba692 6255static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 6256{
f9c617f6 6257 unsigned long exit_qualification;
1439442c 6258 gpa_t gpa;
4f5982a5 6259 u32 error_code;
1439442c 6260
f9c617f6 6261 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 6262
0be9c7a8
GN
6263 /*
6264 * EPT violation happened while executing iret from NMI,
6265 * "blocked by NMI" bit has to be set before next VM entry.
6266 * There are errata that may cause this bit to not be set:
6267 * AAK134, BY25.
6268 */
bcd1c294 6269 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
bcd1c294 6270 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN
6271 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6272
1439442c 6273 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 6274 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 6275
27959a44 6276 /* Is it a read fault? */
ab22a473 6277 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS
6278 ? PFERR_USER_MASK : 0;
6279 /* Is it a write fault? */
ab22a473 6280 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS
6281 ? PFERR_WRITE_MASK : 0;
6282 /* Is it a fetch fault? */
ab22a473 6283 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS
6284 ? PFERR_FETCH_MASK : 0;
6285 /* ept page table entry is present? */
6286 error_code |= (exit_qualification &
6287 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6288 EPT_VIOLATION_EXECUTABLE))
6289 ? PFERR_PRESENT_MASK : 0;
4f5982a5 6290
db1c056c 6291 vcpu->arch.gpa_available = true;
25d92081
YZ
6292 vcpu->arch.exit_qualification = exit_qualification;
6293
4f5982a5 6294 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY
6295}
6296
851ba692 6297static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 6298{
f735d4af 6299 int ret;
68f89400
MT
6300 gpa_t gpa;
6301
6302 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 6303 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 6304 trace_kvm_fast_mmio(gpa);
6affcbed 6305 return kvm_skip_emulated_instruction(vcpu);
68c3b4d1 6306 }
68f89400 6307
450869d6 6308 ret = handle_mmio_page_fault(vcpu, gpa, true);
db1c056c 6309 vcpu->arch.gpa_available = true;
b37fbea6 6310 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG
6311 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6312 EMULATE_DONE;
f8f55942
XG
6313
6314 if (unlikely(ret == RET_MMIO_PF_INVALID))
6315 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6316
b37fbea6 6317 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG
6318 return 1;
6319
6320 /* It is the real ept misconfig */
f735d4af 6321 WARN_ON(1);
68f89400 6322
851ba692
AK
6323 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6324 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT
6325
6326 return 0;
6327}
6328
851ba692 6329static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 6330{
47c0152e
PB
6331 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6332 CPU_BASED_VIRTUAL_NMI_PENDING);
f08864b4 6333 ++vcpu->stat.nmi_window_exits;
3842d135 6334 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY
6335
6336 return 1;
6337}
6338
80ced186 6339static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 6340{
8b3079a5
AK
6341 struct vcpu_vmx *vmx = to_vmx(vcpu);
6342 enum emulation_result err = EMULATE_DONE;
80ced186 6343 int ret = 1;
49e9d557
AK
6344 u32 cpu_exec_ctrl;
6345 bool intr_window_requested;
b8405c18 6346 unsigned count = 130;
49e9d557
AK
6347
6348 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6349 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 6350
98eb2f8b 6351 while (vmx->emulation_required && count-- != 0) {
bdea48e3 6352 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK
6353 return handle_interrupt_window(&vmx->vcpu);
6354
72875d8a 6355 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK
6356 return 1;
6357
991eebf9 6358 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 6359
ac0a48c3 6360 if (err == EMULATE_USER_EXIT) {
94452b9e 6361 ++vcpu->stat.mmio_exits;
80ced186
MG
6362 ret = 0;
6363 goto out;
6364 }
1d5a4d9b 6365
de5f70e0
AK
6366 if (err != EMULATE_DONE) {
6367 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6368 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6369 vcpu->run->internal.ndata = 0;
6d77dbfc 6370 return 0;
de5f70e0 6371 }
ea953ef0 6372
8d76c49e
GN
6373 if (vcpu->arch.halt_request) {
6374 vcpu->arch.halt_request = 0;
5cb56059 6375 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN
6376 goto out;
6377 }
6378
ea953ef0 6379 if (signal_pending(current))
80ced186 6380 goto out;
ea953ef0
MG
6381 if (need_resched())
6382 schedule();
6383 }
6384
80ced186
MG
6385out:
6386 return ret;
ea953ef0
MG
6387}
6388
b4a2d31d
RK
6389static int __grow_ple_window(int val)
6390{
6391 if (ple_window_grow < 1)
6392 return ple_window;
6393
6394 val = min(val, ple_window_actual_max);
6395
6396 if (ple_window_grow < ple_window)
6397 val *= ple_window_grow;
6398 else
6399 val += ple_window_grow;
6400
6401 return val;
6402}
6403
6404static int __shrink_ple_window(int val, int modifier, int minimum)
6405{
6406 if (modifier < 1)
6407 return ple_window;
6408
6409 if (modifier < ple_window)
6410 val /= modifier;
6411 else
6412 val -= modifier;
6413
6414 return max(val, minimum);
6415}
6416
6417static void grow_ple_window(struct kvm_vcpu *vcpu)
6418{
6419 struct vcpu_vmx *vmx = to_vmx(vcpu);
6420 int old = vmx->ple_window;
6421
6422 vmx->ple_window = __grow_ple_window(old);
6423
6424 if (vmx->ple_window != old)
6425 vmx->ple_window_dirty = true;
7b46268d
RK
6426
6427 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK
6428}
6429
6430static void shrink_ple_window(struct kvm_vcpu *vcpu)
6431{
6432 struct vcpu_vmx *vmx = to_vmx(vcpu);
6433 int old = vmx->ple_window;
6434
6435 vmx->ple_window = __shrink_ple_window(old,
6436 ple_window_shrink, ple_window);
6437
6438 if (vmx->ple_window != old)
6439 vmx->ple_window_dirty = true;
7b46268d
RK
6440
6441 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK
6442}
6443
6444/*
6445 * ple_window_actual_max is computed to be one grow_ple_window() below
6446 * ple_window_max. (See __grow_ple_window for the reason.)
6447 * This prevents overflows, because ple_window_max is int.
6448 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6449 * this process.
6450 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6451 */
6452static void update_ple_window_actual_max(void)
6453{
6454 ple_window_actual_max =
6455 __shrink_ple_window(max(ple_window_max, ple_window),
6456 ple_window_grow, INT_MIN);
6457}
6458
bf9f6ac8
FW
6459/*
6460 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6461 */
6462static void wakeup_handler(void)
6463{
6464 struct kvm_vcpu *vcpu;
6465 int cpu = smp_processor_id();
6466
6467 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6468 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6469 blocked_vcpu_list) {
6470 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6471
6472 if (pi_test_on(pi_desc) == 1)
6473 kvm_vcpu_kick(vcpu);
6474 }
6475 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6476}
6477
f160c7b7
JS
6478void vmx_enable_tdp(void)
6479{
6480 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6481 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6482 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6483 0ull, VMX_EPT_EXECUTABLE_MASK,
6484 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
995f00a6 6485 VMX_EPT_RWX_MASK);
f160c7b7
JS
6486
6487 ept_set_mmio_spte_mask();
6488 kvm_enable_tdp();
6489}
6490
f2c7648d
TC
6491static __init int hardware_setup(void)
6492{
34a1cd60
TC
6493 int r = -ENOMEM, i, msr;
6494
6495 rdmsrl_safe(MSR_EFER, &host_efer);
6496
6497 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6498 kvm_define_shared_msr(i, vmx_msr_index[i]);
6499
23611332
RK
6500 for (i = 0; i < VMX_BITMAP_NR; i++) {
6501 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6502 if (!vmx_bitmap[i])
6503 goto out;
6504 }
34a1cd60
TC
6505
6506 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
34a1cd60
TC
6507 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6508 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6509
6510 /*
6511 * Allow direct access to the PC debug port (it is often used for I/O
6512 * delays, but the vmexits simply slow things down).
6513 */
6514 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6515 clear_bit(0x80, vmx_io_bitmap_a);
6516
6517 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6518
6519 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6520 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6521
34a1cd60
TC
6522 if (setup_vmcs_config(&vmcs_config) < 0) {
6523 r = -EIO;
23611332 6524 goto out;
baa03522 6525 }
f2c7648d
TC
6526
6527 if (boot_cpu_has(X86_FEATURE_NX))
6528 kvm_enable_efer_bits(EFER_NX);
6529
08d839c4
WL
6530 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6531 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
f2c7648d 6532 enable_vpid = 0;
08d839c4 6533
f2c7648d
TC
6534 if (!cpu_has_vmx_shadow_vmcs())
6535 enable_shadow_vmcs = 0;
6536 if (enable_shadow_vmcs)
6537 init_vmcs_shadow_fields();
6538
6539 if (!cpu_has_vmx_ept() ||
6540 !cpu_has_vmx_ept_4levels()) {
6541 enable_ept = 0;
6542 enable_unrestricted_guest = 0;
6543 enable_ept_ad_bits = 0;
6544 }
6545
fce6ac4c 6546 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
f2c7648d
TC
6547 enable_ept_ad_bits = 0;
6548
6549 if (!cpu_has_vmx_unrestricted_guest())
6550 enable_unrestricted_guest = 0;
6551
ad15a296 6552 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC
6553 flexpriority_enabled = 0;
6554
ad15a296
PB
6555 /*
6556 * set_apic_access_page_addr() is used to reload apic access
6557 * page upon invalidation. No need to do anything if not
6558 * using the APIC_ACCESS_ADDR VMCS field.
6559 */
6560 if (!flexpriority_enabled)
f2c7648d 6561 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC
6562
6563 if (!cpu_has_vmx_tpr_shadow())
6564 kvm_x86_ops->update_cr8_intercept = NULL;
6565
6566 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6567 kvm_disable_largepages();
6568
6569 if (!cpu_has_vmx_ple())
6570 ple_gap = 0;
6571
76dfafd5 6572 if (!cpu_has_vmx_apicv()) {
f2c7648d 6573 enable_apicv = 0;
76dfafd5
PB
6574 kvm_x86_ops->sync_pir_to_irr = NULL;
6575 }
f2c7648d 6576
64903d61
HZ
6577 if (cpu_has_vmx_tsc_scaling()) {
6578 kvm_has_tsc_control = true;
6579 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6580 kvm_tsc_scaling_ratio_frac_bits = 48;
6581 }
6582
baa03522
TC
6583 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6584 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6585 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6586 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6587 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6588 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
baa03522 6589
c63e4563 6590 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
baa03522 6591 vmx_msr_bitmap_legacy, PAGE_SIZE);
c63e4563 6592 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
baa03522 6593 vmx_msr_bitmap_longmode, PAGE_SIZE);
c63e4563 6594 memcpy(vmx_msr_bitmap_legacy_x2apic,
f6e90f9e 6595 vmx_msr_bitmap_legacy, PAGE_SIZE);
c63e4563 6596 memcpy(vmx_msr_bitmap_longmode_x2apic,
f6e90f9e 6597 vmx_msr_bitmap_longmode, PAGE_SIZE);
baa03522 6598
04bb92e4
WL
6599 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6600
40d8338d
RK
6601 for (msr = 0x800; msr <= 0x8ff; msr++) {
6602 if (msr == 0x839 /* TMCCT */)
6603 continue;
2e69f865 6604 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
40d8338d 6605 }
3ce424e4 6606
f6e90f9e 6607 /*
2e69f865
RK
6608 * TPR reads and writes can be virtualized even if virtual interrupt
6609 * delivery is not in use.
f6e90f9e 6610 */
2e69f865
RK
6611 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6612 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
3ce424e4 6613
3ce424e4 6614 /* EOI */
2e69f865 6615 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
3ce424e4 6616 /* SELF-IPI */
2e69f865 6617 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
baa03522 6618
f160c7b7
JS
6619 if (enable_ept)
6620 vmx_enable_tdp();
6621 else
baa03522
TC
6622 kvm_disable_tdp();
6623
6624 update_ple_window_actual_max();
6625
843e4330
KH
6626 /*
6627 * Only enable PML when hardware supports PML feature, and both EPT
6628 * and EPT A/D bit features are enabled -- PML depends on them to work.
6629 */
6630 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6631 enable_pml = 0;
6632
6633 if (!enable_pml) {
6634 kvm_x86_ops->slot_enable_log_dirty = NULL;
6635 kvm_x86_ops->slot_disable_log_dirty = NULL;
6636 kvm_x86_ops->flush_log_dirty = NULL;
6637 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6638 }
6639
64672c95
YJ
6640 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6641 u64 vmx_msr;
6642
6643 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6644 cpu_preemption_timer_multi =
6645 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6646 } else {
6647 kvm_x86_ops->set_hv_timer = NULL;
6648 kvm_x86_ops->cancel_hv_timer = NULL;
6649 }
6650
bf9f6ac8
FW
6651 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6652
c45dcc71
AR
6653 kvm_mce_cap_supported |= MCG_LMCE_P;
6654
f2c7648d 6655 return alloc_kvm_area();
34a1cd60 6656
34a1cd60 6657out:
23611332
RK
6658 for (i = 0; i < VMX_BITMAP_NR; i++)
6659 free_page((unsigned long)vmx_bitmap[i]);
34a1cd60
TC
6660
6661 return r;
f2c7648d
TC
6662}
6663
6664static __exit void hardware_unsetup(void)
6665{
23611332
RK
6666 int i;
6667
6668 for (i = 0; i < VMX_BITMAP_NR; i++)
6669 free_page((unsigned long)vmx_bitmap[i]);
34a1cd60 6670
f2c7648d
TC
6671 free_kvm_area();
6672}
6673
4b8d54f9
ZE
6674/*
6675 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6676 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6677 */
9fb41ba8 6678static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6679{
b4a2d31d
RK
6680 if (ple_gap)
6681 grow_ple_window(vcpu);
6682
4b8d54f9 6683 kvm_vcpu_on_spin(vcpu);
6affcbed 6684 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE
6685}
6686
87c00572 6687static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6688{
6affcbed 6689 return kvm_skip_emulated_instruction(vcpu);
59708670
SY
6690}
6691
87c00572
GS
6692static int handle_mwait(struct kvm_vcpu *vcpu)
6693{
6694 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6695 return handle_nop(vcpu);
6696}
6697
5f3d45e7
MD
6698static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6699{
6700 return 1;
6701}
6702
87c00572
GS
6703static int handle_monitor(struct kvm_vcpu *vcpu)
6704{
6705 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6706 return handle_nop(vcpu);
6707}
6708
ff2f6fe9
NHE
6709/*
6710 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6711 * We could reuse a single VMCS for all the L2 guests, but we also want the
6712 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6713 * allows keeping them loaded on the processor, and in the future will allow
6714 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6715 * every entry if they never change.
6716 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6717 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6718 *
6719 * The following functions allocate and free a vmcs02 in this pool.
6720 */
6721
6722/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6723static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6724{
6725 struct vmcs02_list *item;
6726 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6727 if (item->vmptr == vmx->nested.current_vmptr) {
6728 list_move(&item->list, &vmx->nested.vmcs02_pool);
6729 return &item->vmcs02;
6730 }
6731
6732 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6733 /* Recycle the least recently used VMCS. */
d74c0e6b
GT
6734 item = list_last_entry(&vmx->nested.vmcs02_pool,
6735 struct vmcs02_list, list);
ff2f6fe9
NHE
6736 item->vmptr = vmx->nested.current_vmptr;
6737 list_move(&item->list, &vmx->nested.vmcs02_pool);
6738 return &item->vmcs02;
6739 }
6740
6741 /* Create a new VMCS */
0fa24ce3 6742 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE
6743 if (!item)
6744 return NULL;
6745 item->vmcs02.vmcs = alloc_vmcs();
355f4fb1 6746 item->vmcs02.shadow_vmcs = NULL;
ff2f6fe9
NHE
6747 if (!item->vmcs02.vmcs) {
6748 kfree(item);
6749 return NULL;
6750 }
6751 loaded_vmcs_init(&item->vmcs02);
6752 item->vmptr = vmx->nested.current_vmptr;
6753 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6754 vmx->nested.vmcs02_num++;
6755 return &item->vmcs02;
6756}
6757
6758/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6759static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6760{
6761 struct vmcs02_list *item;
6762 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6763 if (item->vmptr == vmptr) {
6764 free_loaded_vmcs(&item->vmcs02);
6765 list_del(&item->list);
6766 kfree(item);
6767 vmx->nested.vmcs02_num--;
6768 return;
6769 }
6770}
6771
6772/*
6773 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB
6774 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6775 * must be &vmx->vmcs01.
ff2f6fe9
NHE
6776 */
6777static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6778{
6779 struct vmcs02_list *item, *n;
4fa7734c
PB
6780
6781 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6782 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB
6783 /*
6784 * Something will leak if the above WARN triggers. Better than
6785 * a use-after-free.
6786 */
6787 if (vmx->loaded_vmcs == &item->vmcs02)
6788 continue;
6789
6790 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE
6791 list_del(&item->list);
6792 kfree(item);
4fa7734c 6793 vmx->nested.vmcs02_num--;
ff2f6fe9 6794 }
ff2f6fe9
NHE
6795}
6796
0658fbaa
ACL
6797/*
6798 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6799 * set the success or error code of an emulated VMX instruction, as specified
6800 * by Vol 2B, VMX Instruction Reference, "Conventions".
6801 */
6802static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6803{
6804 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6805 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6806 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6807}
6808
6809static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6810{
6811 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6812 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6813 X86_EFLAGS_SF | X86_EFLAGS_OF))
6814 | X86_EFLAGS_CF);
6815}
6816
145c28dd 6817static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL
6818 u32 vm_instruction_error)
6819{
6820 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6821 /*
6822 * failValid writes the error number to the current VMCS, which
6823 * can't be done there isn't a current VMCS.
6824 */
6825 nested_vmx_failInvalid(vcpu);
6826 return;
6827 }
6828 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6829 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6830 X86_EFLAGS_SF | X86_EFLAGS_OF))
6831 | X86_EFLAGS_ZF);
6832 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6833 /*
6834 * We don't need to force a shadow sync because
6835 * VM_INSTRUCTION_ERROR is not shadowed
6836 */
6837}
145c28dd 6838
ff651cb6
WV
6839static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6840{
6841 /* TODO: not to reset guest simply here. */
6842 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
bbe41b95 6843 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
ff651cb6
WV
6844}
6845
f4124500
JK
6846static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6847{
6848 struct vcpu_vmx *vmx =
6849 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6850
6851 vmx->nested.preemption_timer_expired = true;
6852 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6853 kvm_vcpu_kick(&vmx->vcpu);
6854
6855 return HRTIMER_NORESTART;
6856}
6857
19677e32
BD
6858/*
6859 * Decode the memory-address operand of a vmx instruction, as recorded on an
6860 * exit caused by such an instruction (run by a guest hypervisor).
6861 * On success, returns 0. When the operand is invalid, returns 1 and throws
6862 * #UD or #GP.
6863 */
6864static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6865 unsigned long exit_qualification,
f9eb4af6 6866 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6867{
f9eb4af6
EK
6868 gva_t off;
6869 bool exn;
6870 struct kvm_segment s;
6871
19677e32
BD
6872 /*
6873 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6874 * Execution", on an exit, vmx_instruction_info holds most of the
6875 * addressing components of the operand. Only the displacement part
6876 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6877 * For how an actual address is calculated from all these components,
6878 * refer to Vol. 1, "Operand Addressing".
6879 */
6880 int scaling = vmx_instruction_info & 3;
6881 int addr_size = (vmx_instruction_info >> 7) & 7;
6882 bool is_reg = vmx_instruction_info & (1u << 10);
6883 int seg_reg = (vmx_instruction_info >> 15) & 7;
6884 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6885 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6886 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6887 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6888
6889 if (is_reg) {
6890 kvm_queue_exception(vcpu, UD_VECTOR);
6891 return 1;
6892 }
6893
6894 /* Addr = segment_base + offset */
6895 /* offset = base + [index * scale] + displacement */
f9eb4af6 6896 off = exit_qualification; /* holds the displacement */
19677e32 6897 if (base_is_valid)
f9eb4af6 6898 off += kvm_register_read(vcpu, base_reg);
19677e32 6899 if (index_is_valid)
f9eb4af6
EK
6900 off += kvm_register_read(vcpu, index_reg)<<scaling;
6901 vmx_get_segment(vcpu, &s, seg_reg);
6902 *ret = s.base + off;
19677e32
BD
6903
6904 if (addr_size == 1) /* 32 bit */
6905 *ret &= 0xffffffff;
6906
f9eb4af6
EK
6907 /* Checks for #GP/#SS exceptions. */
6908 exn = false;
ff30ef40
QC
6909 if (is_long_mode(vcpu)) {
6910 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6911 * non-canonical form. This is the only check on the memory
6912 * destination for long mode!
6913 */
6914 exn = is_noncanonical_address(*ret);
6915 } else if (is_protmode(vcpu)) {
f9eb4af6
EK
6916 /* Protected mode: apply checks for segment validity in the
6917 * following order:
6918 * - segment type check (#GP(0) may be thrown)
6919 * - usability check (#GP(0)/#SS(0))
6920 * - limit check (#GP(0)/#SS(0))
6921 */
6922 if (wr)
6923 /* #GP(0) if the destination operand is located in a
6924 * read-only data segment or any code segment.
6925 */
6926 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6927 else
6928 /* #GP(0) if the source operand is located in an
6929 * execute-only code segment
6930 */
6931 exn = ((s.type & 0xa) == 8);
ff30ef40
QC
6932 if (exn) {
6933 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6934 return 1;
6935 }
f9eb4af6
EK
6936 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6937 */
6938 exn = (s.unusable != 0);
6939 /* Protected mode: #GP(0)/#SS(0) if the memory
6940 * operand is outside the segment limit.
6941 */
6942 exn = exn || (off + sizeof(u64) > s.limit);
6943 }
6944 if (exn) {
6945 kvm_queue_exception_e(vcpu,
6946 seg_reg == VCPU_SREG_SS ?
6947 SS_VECTOR : GP_VECTOR,
6948 0);
6949 return 1;
6950 }
6951
19677e32
BD
6952 return 0;
6953}
6954
cbf71279 6955static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
3573e22c
BD
6956{
6957 gva_t gva;
3573e22c 6958 struct x86_exception e;
3573e22c
BD
6959
6960 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 6961 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD
6962 return 1;
6963
cbf71279
RK
6964 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
6965 sizeof(*vmpointer), &e)) {
3573e22c
BD
6966 kvm_inject_page_fault(vcpu, &e);
6967 return 1;
6968 }
6969
3573e22c
BD
6970 return 0;
6971}
6972
e29acc55
JM
6973static int enter_vmx_operation(struct kvm_vcpu *vcpu)
6974{
6975 struct vcpu_vmx *vmx = to_vmx(vcpu);
6976 struct vmcs *shadow_vmcs;
6977
6978 if (cpu_has_vmx_msr_bitmap()) {
6979 vmx->nested.msr_bitmap =
6980 (unsigned long *)__get_free_page(GFP_KERNEL);
6981 if (!vmx->nested.msr_bitmap)
6982 goto out_msr_bitmap;
6983 }
6984
6985 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
6986 if (!vmx->nested.cached_vmcs12)
6987 goto out_cached_vmcs12;
6988
6989 if (enable_shadow_vmcs) {
6990 shadow_vmcs = alloc_vmcs();
6991 if (!shadow_vmcs)
6992 goto out_shadow_vmcs;
6993 /* mark vmcs as shadow */
6994 shadow_vmcs->revision_id |= (1u << 31);
6995 /* init shadow vmcs */
6996 vmcs_clear(shadow_vmcs);
6997 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
6998 }
6999
7000 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7001 vmx->nested.vmcs02_num = 0;
7002
7003 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7004 HRTIMER_MODE_REL_PINNED);
7005 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7006
7007 vmx->nested.vmxon = true;
7008 return 0;
7009
7010out_shadow_vmcs:
7011 kfree(vmx->nested.cached_vmcs12);
7012
7013out_cached_vmcs12:
7014 free_page((unsigned long)vmx->nested.msr_bitmap);
7015
7016out_msr_bitmap:
7017 return -ENOMEM;
7018}
7019
ec378aee
NHE
7020/*
7021 * Emulate the VMXON instruction.
7022 * Currently, we just remember that VMX is active, and do not save or even
7023 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7024 * do not currently need to store anything in that guest-allocated memory
7025 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7026 * argument is different from the VMXON pointer (which the spec says they do).
7027 */
7028static int handle_vmon(struct kvm_vcpu *vcpu)
7029{
e29acc55 7030 int ret;
cbf71279
RK
7031 gpa_t vmptr;
7032 struct page *page;
ec378aee 7033 struct vcpu_vmx *vmx = to_vmx(vcpu);
b3897a49
NHE
7034 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7035 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee 7036
70f3aac9
JM
7037 /*
7038 * The Intel VMX Instruction Reference lists a bunch of bits that are
7039 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7040 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7041 * Otherwise, we should fail with #UD. But most faulting conditions
7042 * have already been checked by hardware, prior to the VM-exit for
7043 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7044 * that bit set to 1 in non-root mode.
ec378aee 7045 */
70f3aac9 7046 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
ec378aee
NHE
7047 kvm_queue_exception(vcpu, UD_VECTOR);
7048 return 1;
7049 }
7050
145c28dd
AG
7051 if (vmx->nested.vmxon) {
7052 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6affcbed 7053 return kvm_skip_emulated_instruction(vcpu);
145c28dd 7054 }
b3897a49 7055
3b84080b 7056 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
b3897a49
NHE
7057 != VMXON_NEEDED_FEATURES) {
7058 kvm_inject_gp(vcpu, 0);
7059 return 1;
7060 }
7061
cbf71279 7062 if (nested_vmx_get_vmptr(vcpu, &vmptr))
21e7fbe7 7063 return 1;
cbf71279
RK
7064
7065 /*
7066 * SDM 3: 24.11.5
7067 * The first 4 bytes of VMXON region contain the supported
7068 * VMCS revision identifier
7069 *
7070 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7071 * which replaces physical address width with 32
7072 */
7073 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7074 nested_vmx_failInvalid(vcpu);
7075 return kvm_skip_emulated_instruction(vcpu);
7076 }
7077
7078 page = nested_get_page(vcpu, vmptr);
7079 if (page == NULL) {
7080 nested_vmx_failInvalid(vcpu);
7081 return kvm_skip_emulated_instruction(vcpu);
7082 }
7083 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7084 kunmap(page);
7085 nested_release_page_clean(page);
7086 nested_vmx_failInvalid(vcpu);
7087 return kvm_skip_emulated_instruction(vcpu);
7088 }
7089 kunmap(page);
7090 nested_release_page_clean(page);
7091
7092 vmx->nested.vmxon_ptr = vmptr;
e29acc55
JM
7093 ret = enter_vmx_operation(vcpu);
7094 if (ret)
7095 return ret;
ec378aee 7096
a25eb114 7097 nested_vmx_succeed(vcpu);
6affcbed 7098 return kvm_skip_emulated_instruction(vcpu);
ec378aee
NHE
7099}
7100
7101/*
7102 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7103 * for running VMX instructions (except VMXON, whose prerequisites are
7104 * slightly different). It also specifies what exception to inject otherwise.
70f3aac9
JM
7105 * Note that many of these exceptions have priority over VM exits, so they
7106 * don't have to be checked again here.
ec378aee
NHE
7107 */
7108static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7109{
70f3aac9 7110 if (!to_vmx(vcpu)->nested.vmxon) {
ec378aee
NHE
7111 kvm_queue_exception(vcpu, UD_VECTOR);
7112 return 0;
7113 }
ec378aee
NHE
7114 return 1;
7115}
7116
e7953d7f
AG
7117static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7118{
9a2a05b9
PB
7119 if (vmx->nested.current_vmptr == -1ull)
7120 return;
7121
7122 /* current_vmptr and current_vmcs12 are always set/reset together */
7123 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7124 return;
7125
012f83cb 7126 if (enable_shadow_vmcs) {
9a2a05b9
PB
7127 /* copy to memory all shadowed fields in case
7128 they were modified */
7129 copy_shadow_to_vmcs12(vmx);
7130 vmx->nested.sync_shadow_vmcs = false;
7ec36296
XG
7131 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7132 SECONDARY_EXEC_SHADOW_VMCS);
9a2a05b9 7133 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 7134 }
705699a1 7135 vmx->nested.posted_intr_nv = -1;
4f2777bc
DM
7136
7137 /* Flush VMCS12 to guest memory */
7138 memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7139 VMCS12_SIZE);
7140
e7953d7f
AG
7141 kunmap(vmx->nested.current_vmcs12_page);
7142 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB
7143 vmx->nested.current_vmptr = -1ull;
7144 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG
7145}
7146
ec378aee
NHE
7147/*
7148 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7149 * just stops using VMX.
7150 */
7151static void free_nested(struct vcpu_vmx *vmx)
7152{
7153 if (!vmx->nested.vmxon)
7154 return;
9a2a05b9 7155
ec378aee 7156 vmx->nested.vmxon = false;
5c614b35 7157 free_vpid(vmx->nested.vpid02);
9a2a05b9 7158 nested_release_vmcs12(vmx);
d048c098
RK
7159 if (vmx->nested.msr_bitmap) {
7160 free_page((unsigned long)vmx->nested.msr_bitmap);
7161 vmx->nested.msr_bitmap = NULL;
7162 }
355f4fb1
JM
7163 if (enable_shadow_vmcs) {
7164 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7165 free_vmcs(vmx->vmcs01.shadow_vmcs);
7166 vmx->vmcs01.shadow_vmcs = NULL;
7167 }
4f2777bc 7168 kfree(vmx->nested.cached_vmcs12);
fe3ef05c
NHE
7169 /* Unpin physical memory we referred to in current vmcs02 */
7170 if (vmx->nested.apic_access_page) {
7171 nested_release_page(vmx->nested.apic_access_page);
48d89b92 7172 vmx->nested.apic_access_page = NULL;
fe3ef05c 7173 }
a7c0b07d
WL
7174 if (vmx->nested.virtual_apic_page) {
7175 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 7176 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 7177 }
705699a1
WV
7178 if (vmx->nested.pi_desc_page) {
7179 kunmap(vmx->nested.pi_desc_page);
7180 nested_release_page(vmx->nested.pi_desc_page);
7181 vmx->nested.pi_desc_page = NULL;
7182 vmx->nested.pi_desc = NULL;
7183 }
ff2f6fe9
NHE
7184
7185 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE
7186}
7187
7188/* Emulate the VMXOFF instruction */
7189static int handle_vmoff(struct kvm_vcpu *vcpu)
7190{
7191 if (!nested_vmx_check_permission(vcpu))
7192 return 1;
7193 free_nested(to_vmx(vcpu));
a25eb114 7194 nested_vmx_succeed(vcpu);
6affcbed 7195 return kvm_skip_emulated_instruction(vcpu);
ec378aee
NHE
7196}
7197
27d6c865
NHE
7198/* Emulate the VMCLEAR instruction */
7199static int handle_vmclear(struct kvm_vcpu *vcpu)
7200{
7201 struct vcpu_vmx *vmx = to_vmx(vcpu);
587d7e72 7202 u32 zero = 0;
27d6c865 7203 gpa_t vmptr;
27d6c865
NHE
7204
7205 if (!nested_vmx_check_permission(vcpu))
7206 return 1;
7207
cbf71279 7208 if (nested_vmx_get_vmptr(vcpu, &vmptr))
27d6c865 7209 return 1;
27d6c865 7210
cbf71279
RK
7211 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7212 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7213 return kvm_skip_emulated_instruction(vcpu);
7214 }
7215
7216 if (vmptr == vmx->nested.vmxon_ptr) {
7217 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7218 return kvm_skip_emulated_instruction(vcpu);
7219 }
7220
9a2a05b9 7221 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 7222 nested_release_vmcs12(vmx);
27d6c865 7223
587d7e72
JM
7224 kvm_vcpu_write_guest(vcpu,
7225 vmptr + offsetof(struct vmcs12, launch_state),
7226 &zero, sizeof(zero));
27d6c865
NHE
7227
7228 nested_free_vmcs02(vmx, vmptr);
7229
27d6c865 7230 nested_vmx_succeed(vcpu);
6affcbed 7231 return kvm_skip_emulated_instruction(vcpu);
27d6c865
NHE
7232}
7233
cd232ad0
NHE
7234static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7235
7236/* Emulate the VMLAUNCH instruction */
7237static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7238{
7239 return nested_vmx_run(vcpu, true);
7240}
7241
7242/* Emulate the VMRESUME instruction */
7243static int handle_vmresume(struct kvm_vcpu *vcpu)
7244{
7245
7246 return nested_vmx_run(vcpu, false);
7247}
7248
49f705c5
NHE
7249/*
7250 * Read a vmcs12 field. Since these can have varying lengths and we return
7251 * one type, we chose the biggest type (u64) and zero-extend the return value
7252 * to that size. Note that the caller, handle_vmread, might need to use only
7253 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7254 * 64-bit fields are to be returned).
7255 */
a2ae9df7
PB
7256static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7257 unsigned long field, u64 *ret)
49f705c5
NHE
7258{
7259 short offset = vmcs_field_to_offset(field);
7260 char *p;
7261
7262 if (offset < 0)
a2ae9df7 7263 return offset;
49f705c5
NHE
7264
7265 p = ((char *)(get_vmcs12(vcpu))) + offset;
7266
7267 switch (vmcs_field_type(field)) {
7268 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7269 *ret = *((natural_width *)p);
a2ae9df7 7270 return 0;
49f705c5
NHE
7271 case VMCS_FIELD_TYPE_U16:
7272 *ret = *((u16 *)p);
a2ae9df7 7273 return 0;
49f705c5
NHE
7274 case VMCS_FIELD_TYPE_U32:
7275 *ret = *((u32 *)p);
a2ae9df7 7276 return 0;
49f705c5
NHE
7277 case VMCS_FIELD_TYPE_U64:
7278 *ret = *((u64 *)p);
a2ae9df7 7279 return 0;
49f705c5 7280 default:
a2ae9df7
PB
7281 WARN_ON(1);
7282 return -ENOENT;
49f705c5
NHE
7283 }
7284}
7285
20b97fea 7286
a2ae9df7
PB
7287static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7288 unsigned long field, u64 field_value){
20b97fea
AG
7289 short offset = vmcs_field_to_offset(field);
7290 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7291 if (offset < 0)
a2ae9df7 7292 return offset;
20b97fea
AG
7293
7294 switch (vmcs_field_type(field)) {
7295 case VMCS_FIELD_TYPE_U16:
7296 *(u16 *)p = field_value;
a2ae9df7 7297 return 0;
20b97fea
AG
7298 case VMCS_FIELD_TYPE_U32:
7299 *(u32 *)p = field_value;
a2ae9df7 7300 return 0;
20b97fea
AG
7301 case VMCS_FIELD_TYPE_U64:
7302 *(u64 *)p = field_value;
a2ae9df7 7303 return 0;
20b97fea
AG
7304 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7305 *(natural_width *)p = field_value;
a2ae9df7 7306 return 0;
20b97fea 7307 default:
a2ae9df7
PB
7308 WARN_ON(1);
7309 return -ENOENT;
20b97fea
AG
7310 }
7311
7312}
7313
16f5b903
AG
7314static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7315{
7316 int i;
7317 unsigned long field;
7318 u64 field_value;
355f4fb1 7319 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
c2bae893
MK
7320 const unsigned long *fields = shadow_read_write_fields;
7321 const int num_fields = max_shadow_read_write_fields;
16f5b903 7322
282da870
JK
7323 preempt_disable();
7324
16f5b903
AG
7325 vmcs_load(shadow_vmcs);
7326
7327 for (i = 0; i < num_fields; i++) {
7328 field = fields[i];
7329 switch (vmcs_field_type(field)) {
7330 case VMCS_FIELD_TYPE_U16:
7331 field_value = vmcs_read16(field);
7332 break;
7333 case VMCS_FIELD_TYPE_U32:
7334 field_value = vmcs_read32(field);
7335 break;
7336 case VMCS_FIELD_TYPE_U64:
7337 field_value = vmcs_read64(field);
7338 break;
7339 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7340 field_value = vmcs_readl(field);
7341 break;
a2ae9df7
PB
7342 default:
7343 WARN_ON(1);
7344 continue;
16f5b903
AG
7345 }
7346 vmcs12_write_any(&vmx->vcpu, field, field_value);
7347 }
7348
7349 vmcs_clear(shadow_vmcs);
7350 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK
7351
7352 preempt_enable();
16f5b903
AG
7353}
7354
c3114420
AG
7355static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7356{
c2bae893
MK
7357 const unsigned long *fields[] = {
7358 shadow_read_write_fields,
7359 shadow_read_only_fields
c3114420 7360 };
c2bae893 7361 const int max_fields[] = {
c3114420
AG
7362 max_shadow_read_write_fields,
7363 max_shadow_read_only_fields
7364 };
7365 int i, q;
7366 unsigned long field;
7367 u64 field_value = 0;
355f4fb1 7368 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
c3114420
AG
7369
7370 vmcs_load(shadow_vmcs);
7371
c2bae893 7372 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG
7373 for (i = 0; i < max_fields[q]; i++) {
7374 field = fields[q][i];
7375 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7376
7377 switch (vmcs_field_type(field)) {
7378 case VMCS_FIELD_TYPE_U16:
7379 vmcs_write16(field, (u16)field_value);
7380 break;
7381 case VMCS_FIELD_TYPE_U32:
7382 vmcs_write32(field, (u32)field_value);
7383 break;
7384 case VMCS_FIELD_TYPE_U64:
7385 vmcs_write64(field, (u64)field_value);
7386 break;
7387 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7388 vmcs_writel(field, (long)field_value);
7389 break;
a2ae9df7
PB
7390 default:
7391 WARN_ON(1);
7392 break;
c3114420
AG
7393 }
7394 }
7395 }
7396
7397 vmcs_clear(shadow_vmcs);
7398 vmcs_load(vmx->loaded_vmcs->vmcs);
7399}
7400
49f705c5
NHE
7401/*
7402 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7403 * used before) all generate the same failure when it is missing.
7404 */
7405static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7406{
7407 struct vcpu_vmx *vmx = to_vmx(vcpu);
7408 if (vmx->nested.current_vmptr == -1ull) {
7409 nested_vmx_failInvalid(vcpu);
49f705c5
NHE
7410 return 0;
7411 }
7412 return 1;
7413}
7414
7415static int handle_vmread(struct kvm_vcpu *vcpu)
7416{
7417 unsigned long field;
7418 u64 field_value;
7419 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7420 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7421 gva_t gva = 0;
7422
eb277562 7423 if (!nested_vmx_check_permission(vcpu))
49f705c5
NHE
7424 return 1;
7425
6affcbed
KH
7426 if (!nested_vmx_check_vmcs12(vcpu))
7427 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7428
7429 /* Decode instruction info and find the field to read */
27e6fb5d 7430 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 7431 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 7432 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5 7433 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6affcbed 7434 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7435 }
7436 /*
7437 * Now copy part of this value to register or memory, as requested.
7438 * Note that the number of bits actually copied is 32 or 64 depending
7439 * on the guest's mode (32 or 64 bit), not on the given field's length.
7440 */
7441 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 7442 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE
7443 field_value);
7444 } else {
7445 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7446 vmx_instruction_info, true, &gva))
49f705c5 7447 return 1;
70f3aac9 7448 /* _system ok, as hardware has verified cpl=0 */
49f705c5
NHE
7449 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7450 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7451 }
7452
7453 nested_vmx_succeed(vcpu);
6affcbed 7454 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7455}
7456
7457
7458static int handle_vmwrite(struct kvm_vcpu *vcpu)
7459{
7460 unsigned long field;
7461 gva_t gva;
7462 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7463 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE
7464 /* The value to write might be 32 or 64 bits, depending on L1's long
7465 * mode, and eventually we need to write that into a field of several
7466 * possible lengths. The code below first zero-extends the value to 64
6a6256f9 7467 * bit (field_value), and then copies only the appropriate number of
49f705c5
NHE
7468 * bits into the vmcs12 field.
7469 */
7470 u64 field_value = 0;
7471 struct x86_exception e;
7472
eb277562 7473 if (!nested_vmx_check_permission(vcpu))
49f705c5
NHE
7474 return 1;
7475
6affcbed
KH
7476 if (!nested_vmx_check_vmcs12(vcpu))
7477 return kvm_skip_emulated_instruction(vcpu);
eb277562 7478
49f705c5 7479 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7480 field_value = kvm_register_readl(vcpu,
49f705c5
NHE
7481 (((vmx_instruction_info) >> 3) & 0xf));
7482 else {
7483 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7484 vmx_instruction_info, false, &gva))
49f705c5
NHE
7485 return 1;
7486 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7487 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE
7488 kvm_inject_page_fault(vcpu, &e);
7489 return 1;
7490 }
7491 }
7492
7493
27e6fb5d 7494 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE
7495 if (vmcs_field_readonly(field)) {
7496 nested_vmx_failValid(vcpu,
7497 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6affcbed 7498 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7499 }
7500
a2ae9df7 7501 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5 7502 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6affcbed 7503 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7504 }
7505
7506 nested_vmx_succeed(vcpu);
6affcbed 7507 return kvm_skip_emulated_instruction(vcpu);
49f705c5
NHE
7508}
7509
a8bc284e
JM
7510static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7511{
7512 vmx->nested.current_vmptr = vmptr;
7513 if (enable_shadow_vmcs) {
7514 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7515 SECONDARY_EXEC_SHADOW_VMCS);
7516 vmcs_write64(VMCS_LINK_POINTER,
7517 __pa(vmx->vmcs01.shadow_vmcs));
7518 vmx->nested.sync_shadow_vmcs = true;
7519 }
7520}
7521
63846663
NHE
7522/* Emulate the VMPTRLD instruction */
7523static int handle_vmptrld(struct kvm_vcpu *vcpu)
7524{
7525 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7526 gpa_t vmptr;
63846663
NHE
7527
7528 if (!nested_vmx_check_permission(vcpu))
7529 return 1;
7530
cbf71279 7531 if (nested_vmx_get_vmptr(vcpu, &vmptr))
63846663 7532 return 1;
63846663 7533
cbf71279
RK
7534 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7535 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7536 return kvm_skip_emulated_instruction(vcpu);
7537 }
7538
7539 if (vmptr == vmx->nested.vmxon_ptr) {
7540 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7541 return kvm_skip_emulated_instruction(vcpu);
7542 }
7543
63846663
NHE
7544 if (vmx->nested.current_vmptr != vmptr) {
7545 struct vmcs12 *new_vmcs12;
7546 struct page *page;
7547 page = nested_get_page(vcpu, vmptr);
7548 if (page == NULL) {
7549 nested_vmx_failInvalid(vcpu);
6affcbed 7550 return kvm_skip_emulated_instruction(vcpu);
63846663
NHE
7551 }
7552 new_vmcs12 = kmap(page);
7553 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7554 kunmap(page);
7555 nested_release_page_clean(page);
7556 nested_vmx_failValid(vcpu,
7557 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6affcbed 7558 return kvm_skip_emulated_instruction(vcpu);
63846663 7559 }
63846663 7560
9a2a05b9 7561 nested_release_vmcs12(vmx);
63846663
NHE
7562 vmx->nested.current_vmcs12 = new_vmcs12;
7563 vmx->nested.current_vmcs12_page = page;
4f2777bc
DM
7564 /*
7565 * Load VMCS12 from guest memory since it is not already
7566 * cached.
7567 */
7568 memcpy(vmx->nested.cached_vmcs12,
7569 vmx->nested.current_vmcs12, VMCS12_SIZE);
a8bc284e 7570 set_current_vmptr(vmx, vmptr);
63846663
NHE
7571 }
7572
7573 nested_vmx_succeed(vcpu);
6affcbed 7574 return kvm_skip_emulated_instruction(vcpu);
63846663
NHE
7575}
7576
6a4d7550
NHE
7577/* Emulate the VMPTRST instruction */
7578static int handle_vmptrst(struct kvm_vcpu *vcpu)
7579{
7580 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7581 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7582 gva_t vmcs_gva;
7583 struct x86_exception e;
7584
7585 if (!nested_vmx_check_permission(vcpu))
7586 return 1;
7587
7588 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7589 vmx_instruction_info, true, &vmcs_gva))
6a4d7550 7590 return 1;
70f3aac9 7591 /* ok to use *_system, as hardware has verified cpl=0 */
6a4d7550
NHE
7592 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7593 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7594 sizeof(u64), &e)) {
7595 kvm_inject_page_fault(vcpu, &e);
7596 return 1;
7597 }
7598 nested_vmx_succeed(vcpu);
6affcbed 7599 return kvm_skip_emulated_instruction(vcpu);
6a4d7550
NHE
7600}
7601
bfd0a56b
NHE
7602/* Emulate the INVEPT instruction */
7603static int handle_invept(struct kvm_vcpu *vcpu)
7604{
b9c237bb 7605 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE
7606 u32 vmx_instruction_info, types;
7607 unsigned long type;
7608 gva_t gva;
7609 struct x86_exception e;
7610 struct {
7611 u64 eptp, gpa;
7612 } operand;
bfd0a56b 7613
b9c237bb
WV
7614 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7615 SECONDARY_EXEC_ENABLE_EPT) ||
7616 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE
7617 kvm_queue_exception(vcpu, UD_VECTOR);
7618 return 1;
7619 }
7620
7621 if (!nested_vmx_check_permission(vcpu))
7622 return 1;
7623
bfd0a56b 7624 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7625 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7626
b9c237bb 7627 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b 7628
85c856b3 7629 if (type >= 32 || !(types & (1 << type))) {
bfd0a56b
NHE
7630 nested_vmx_failValid(vcpu,
7631 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7632 return kvm_skip_emulated_instruction(vcpu);
bfd0a56b
NHE
7633 }
7634
7635 /* According to the Intel VMX instruction reference, the memory
7636 * operand is read even if it isn't needed (e.g., for type==global)
7637 */
7638 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7639 vmx_instruction_info, false, &gva))
bfd0a56b
NHE
7640 return 1;
7641 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7642 sizeof(operand), &e)) {
7643 kvm_inject_page_fault(vcpu, &e);
7644 return 1;
7645 }
7646
7647 switch (type) {
bfd0a56b 7648 case VMX_EPT_EXTENT_GLOBAL:
45e11817
BD
7649 /*
7650 * TODO: track mappings and invalidate
7651 * single context requests appropriately
7652 */
7653 case VMX_EPT_EXTENT_CONTEXT:
bfd0a56b 7654 kvm_mmu_sync_roots(vcpu);
77c3913b 7655 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE
7656 nested_vmx_succeed(vcpu);
7657 break;
7658 default:
7659 BUG_ON(1);
7660 break;
7661 }
7662
6affcbed 7663 return kvm_skip_emulated_instruction(vcpu);
bfd0a56b
NHE
7664}
7665
a642fc30
PM
7666static int handle_invvpid(struct kvm_vcpu *vcpu)
7667{
99b83ac8
WL
7668 struct vcpu_vmx *vmx = to_vmx(vcpu);
7669 u32 vmx_instruction_info;
7670 unsigned long type, types;
7671 gva_t gva;
7672 struct x86_exception e;
40352605
JM
7673 struct {
7674 u64 vpid;
7675 u64 gla;
7676 } operand;
99b83ac8
WL
7677
7678 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7679 SECONDARY_EXEC_ENABLE_VPID) ||
7680 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7681 kvm_queue_exception(vcpu, UD_VECTOR);
7682 return 1;
7683 }
7684
7685 if (!nested_vmx_check_permission(vcpu))
7686 return 1;
7687
7688 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7689 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7690
bcdde302
JD
7691 types = (vmx->nested.nested_vmx_vpid_caps &
7692 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
99b83ac8 7693
85c856b3 7694 if (type >= 32 || !(types & (1 << type))) {
99b83ac8
WL
7695 nested_vmx_failValid(vcpu,
7696 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7697 return kvm_skip_emulated_instruction(vcpu);
99b83ac8
WL
7698 }
7699
7700 /* according to the intel vmx instruction reference, the memory
7701 * operand is read even if it isn't needed (e.g., for type==global)
7702 */
7703 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7704 vmx_instruction_info, false, &gva))
7705 return 1;
40352605
JM
7706 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7707 sizeof(operand), &e)) {
99b83ac8
WL
7708 kvm_inject_page_fault(vcpu, &e);
7709 return 1;
7710 }
40352605
JM
7711 if (operand.vpid >> 16) {
7712 nested_vmx_failValid(vcpu,
7713 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7714 return kvm_skip_emulated_instruction(vcpu);
7715 }
99b83ac8
WL
7716
7717 switch (type) {
bcdde302 7718 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
40352605
JM
7719 if (is_noncanonical_address(operand.gla)) {
7720 nested_vmx_failValid(vcpu,
7721 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7722 return kvm_skip_emulated_instruction(vcpu);
7723 }
7724 /* fall through */
ef697a71 7725 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
bcdde302 7726 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
40352605 7727 if (!operand.vpid) {
bcdde302
JD
7728 nested_vmx_failValid(vcpu,
7729 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6affcbed 7730 return kvm_skip_emulated_instruction(vcpu);
bcdde302
JD
7731 }
7732 break;
99b83ac8 7733 case VMX_VPID_EXTENT_ALL_CONTEXT:
99b83ac8
WL
7734 break;
7735 default:
bcdde302 7736 WARN_ON_ONCE(1);
6affcbed 7737 return kvm_skip_emulated_instruction(vcpu);
99b83ac8
WL
7738 }
7739
bcdde302
JD
7740 __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7741 nested_vmx_succeed(vcpu);
7742
6affcbed 7743 return kvm_skip_emulated_instruction(vcpu);
a642fc30
PM
7744}
7745
843e4330
KH
7746static int handle_pml_full(struct kvm_vcpu *vcpu)
7747{
7748 unsigned long exit_qualification;
7749
7750 trace_kvm_pml_full(vcpu->vcpu_id);
7751
7752 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7753
7754 /*
7755 * PML buffer FULL happened while executing iret from NMI,
7756 * "blocked by NMI" bit has to be set before next VM entry.
7757 */
7758 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
843e4330
KH
7759 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7760 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7761 GUEST_INTR_STATE_NMI);
7762
7763 /*
7764 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7765 * here.., and there's no userspace involvement needed for PML.
7766 */
7767 return 1;
7768}
7769
64672c95
YJ
7770static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7771{
7772 kvm_lapic_expired_hv_timer(vcpu);
7773 return 1;
7774}
7775
6aa8b732
AK
7776/*
7777 * The exit handlers return 1 if the exit was handled fully and guest execution
7778 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7779 * to be done to userspace and return 0.
7780 */
772e0318 7781static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK
7782 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7783 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7784 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7785 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7786 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK
7787 [EXIT_REASON_CR_ACCESS] = handle_cr,
7788 [EXIT_REASON_DR_ACCESS] = handle_dr,
7789 [EXIT_REASON_CPUID] = handle_cpuid,
7790 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7791 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7792 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7793 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7794 [EXIT_REASON_INVD] = handle_invd,
a7052897 7795 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7796 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7797 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7798 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7799 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7800 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7801 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7802 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7803 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7804 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE
7805 [EXIT_REASON_VMOFF] = handle_vmoff,
7806 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY
7807 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7808 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7809 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7810 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7811 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7812 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7813 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7814 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT
7815 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7816 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7817 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7818 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7819 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7820 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7821 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7822 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL
7823 [EXIT_REASON_XSAVES] = handle_xsaves,
7824 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7825 [EXIT_REASON_PML_FULL] = handle_pml_full,
64672c95 7826 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
6aa8b732
AK
7827};
7828
7829static const int kvm_vmx_max_exit_handlers =
50a3485c 7830 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7831
908a7bdd
JK
7832static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7833 struct vmcs12 *vmcs12)
7834{
7835 unsigned long exit_qualification;
7836 gpa_t bitmap, last_bitmap;
7837 unsigned int port;
7838 int size;
7839 u8 b;
7840
908a7bdd 7841 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7842 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK
7843
7844 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7845
7846 port = exit_qualification >> 16;
7847 size = (exit_qualification & 7) + 1;
7848
7849 last_bitmap = (gpa_t)-1;
7850 b = -1;
7851
7852 while (size > 0) {
7853 if (port < 0x8000)
7854 bitmap = vmcs12->io_bitmap_a;
7855 else if (port < 0x10000)
7856 bitmap = vmcs12->io_bitmap_b;
7857 else
1d804d07 7858 return true;
908a7bdd
JK
7859 bitmap += (port & 0x7fff) / 8;
7860
7861 if (last_bitmap != bitmap)
54bf36aa 7862 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7863 return true;
908a7bdd 7864 if (b & (1 << (port & 7)))
1d804d07 7865 return true;
908a7bdd
JK
7866
7867 port++;
7868 size--;
7869 last_bitmap = bitmap;
7870 }
7871
1d804d07 7872 return false;
908a7bdd
JK
7873}
7874
644d711a
NHE
7875/*
7876 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7877 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7878 * disinterest in the current event (read or write a specific MSR) by using an
7879 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7880 */
7881static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7882 struct vmcs12 *vmcs12, u32 exit_reason)
7883{
7884 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7885 gpa_t bitmap;
7886
cbd29cb6 7887 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7888 return true;
644d711a
NHE
7889
7890 /*
7891 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7892 * for the four combinations of read/write and low/high MSR numbers.
7893 * First we need to figure out which of the four to use:
7894 */
7895 bitmap = vmcs12->msr_bitmap;
7896 if (exit_reason == EXIT_REASON_MSR_WRITE)
7897 bitmap += 2048;
7898 if (msr_index >= 0xc0000000) {
7899 msr_index -= 0xc0000000;
7900 bitmap += 1024;
7901 }
7902
7903 /* Then read the msr_index'th bit from this bitmap: */
7904 if (msr_index < 1024*8) {
7905 unsigned char b;
54bf36aa 7906 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7907 return true;
644d711a
NHE
7908 return 1 & (b >> (msr_index & 7));
7909 } else
1d804d07 7910 return true; /* let L1 handle the wrong parameter */
644d711a
NHE
7911}
7912
7913/*
7914 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7915 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7916 * intercept (via guest_host_mask etc.) the current event.
7917 */
7918static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7919 struct vmcs12 *vmcs12)
7920{
7921 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7922 int cr = exit_qualification & 15;
e1d39b17
JS
7923 int reg;
7924 unsigned long val;
644d711a
NHE
7925
7926 switch ((exit_qualification >> 4) & 3) {
7927 case 0: /* mov to cr */
e1d39b17
JS
7928 reg = (exit_qualification >> 8) & 15;
7929 val = kvm_register_readl(vcpu, reg);
644d711a
NHE
7930 switch (cr) {
7931 case 0:
7932 if (vmcs12->cr0_guest_host_mask &
7933 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7934 return true;
644d711a
NHE
7935 break;
7936 case 3:
7937 if ((vmcs12->cr3_target_count >= 1 &&
7938 vmcs12->cr3_target_value0 == val) ||
7939 (vmcs12->cr3_target_count >= 2 &&
7940 vmcs12->cr3_target_value1 == val) ||
7941 (vmcs12->cr3_target_count >= 3 &&
7942 vmcs12->cr3_target_value2 == val) ||
7943 (vmcs12->cr3_target_count >= 4 &&
7944 vmcs12->cr3_target_value3 == val))
1d804d07 7945 return false;
644d711a 7946 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7947 return true;
644d711a
NHE
7948 break;
7949 case 4:
7950 if (vmcs12->cr4_guest_host_mask &
7951 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7952 return true;
644d711a
NHE
7953 break;
7954 case 8:
7955 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7956 return true;
644d711a
NHE
7957 break;
7958 }
7959 break;
7960 case 2: /* clts */
7961 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7962 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7963 return true;
644d711a
NHE
7964 break;
7965 case 1: /* mov from cr */
7966 switch (cr) {
7967 case 3:
7968 if (vmcs12->cpu_based_vm_exec_control &
7969 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7970 return true;
644d711a
NHE
7971 break;
7972 case 8:
7973 if (vmcs12->cpu_based_vm_exec_control &
7974 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7975 return true;
644d711a
NHE
7976 break;
7977 }
7978 break;
7979 case 3: /* lmsw */
7980 /*
7981 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7982 * cr0. Other attempted changes are ignored, with no exit.
7983 */
e1d39b17 7984 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
644d711a
NHE
7985 if (vmcs12->cr0_guest_host_mask & 0xe &
7986 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7987 return true;
644d711a
NHE
7988 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7989 !(vmcs12->cr0_read_shadow & 0x1) &&
7990 (val & 0x1))
1d804d07 7991 return true;
644d711a
NHE
7992 break;
7993 }
1d804d07 7994 return false;
644d711a
NHE
7995}
7996
7997/*
7998 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7999 * should handle it ourselves in L0 (and then continue L2). Only call this
8000 * when in is_guest_mode (L2).
8001 */
8002static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8003{
644d711a
NHE
8004 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8005 struct vcpu_vmx *vmx = to_vmx(vcpu);
8006 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 8007 u32 exit_reason = vmx->exit_reason;
644d711a 8008
542060ea
JK
8009 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8010 vmcs_readl(EXIT_QUALIFICATION),
8011 vmx->idt_vectoring_info,
8012 intr_info,
8013 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8014 KVM_ISA_VMX);
8015
644d711a 8016 if (vmx->nested.nested_run_pending)
1d804d07 8017 return false;
644d711a
NHE
8018
8019 if (unlikely(vmx->fail)) {
bd80158a
JK
8020 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8021 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 8022 return true;
644d711a
NHE
8023 }
8024
8025 switch (exit_reason) {
8026 case EXIT_REASON_EXCEPTION_NMI:
ef85b673 8027 if (is_nmi(intr_info))
1d804d07 8028 return false;
644d711a
NHE
8029 else if (is_page_fault(intr_info))
8030 return enable_ept;
e504c909 8031 else if (is_no_device(intr_info) &&
ccf9844e 8032 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 8033 return false;
6f05485d
JK
8034 else if (is_debug(intr_info) &&
8035 vcpu->guest_debug &
8036 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8037 return false;
8038 else if (is_breakpoint(intr_info) &&
8039 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8040 return false;
644d711a
NHE
8041 return vmcs12->exception_bitmap &
8042 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8043 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 8044 return false;
644d711a 8045 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 8046 return true;
644d711a 8047 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 8048 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 8049 case EXIT_REASON_NMI_WINDOW:
3b656cf7 8050 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 8051 case EXIT_REASON_TASK_SWITCH:
1d804d07 8052 return true;
644d711a 8053 case EXIT_REASON_CPUID:
1d804d07 8054 return true;
644d711a
NHE
8055 case EXIT_REASON_HLT:
8056 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8057 case EXIT_REASON_INVD:
1d804d07 8058 return true;
644d711a
NHE
8059 case EXIT_REASON_INVLPG:
8060 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8061 case EXIT_REASON_RDPMC:
8062 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
a5f46457
PB
8063 case EXIT_REASON_RDRAND:
8064 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8065 case EXIT_REASON_RDSEED:
8066 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
b3a2a907 8067 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE
8068 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8069 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8070 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8071 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8072 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8073 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 8074 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE
8075 /*
8076 * VMX instructions trap unconditionally. This allows L1 to
8077 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8078 */
1d804d07 8079 return true;
644d711a
NHE
8080 case EXIT_REASON_CR_ACCESS:
8081 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8082 case EXIT_REASON_DR_ACCESS:
8083 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8084 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 8085 return nested_vmx_exit_handled_io(vcpu, vmcs12);
1b07304c
PB
8086 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8087 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
644d711a
NHE
8088 case EXIT_REASON_MSR_READ:
8089 case EXIT_REASON_MSR_WRITE:
8090 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8091 case EXIT_REASON_INVALID_STATE:
1d804d07 8092 return true;
644d711a
NHE
8093 case EXIT_REASON_MWAIT_INSTRUCTION:
8094 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD
8095 case EXIT_REASON_MONITOR_TRAP_FLAG:
8096 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE
8097 case EXIT_REASON_MONITOR_INSTRUCTION:
8098 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8099 case EXIT_REASON_PAUSE_INSTRUCTION:
8100 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8101 nested_cpu_has2(vmcs12,
8102 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8103 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 8104 return false;
644d711a 8105 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 8106 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE
8107 case EXIT_REASON_APIC_ACCESS:
8108 return nested_cpu_has2(vmcs12,
8109 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 8110 case EXIT_REASON_APIC_WRITE:
608406e2
WV
8111 case EXIT_REASON_EOI_INDUCED:
8112 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 8113 return true;
644d711a 8114 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE
8115 /*
8116 * L0 always deals with the EPT violation. If nested EPT is
8117 * used, and the nested mmu code discovers that the address is
8118 * missing in the guest EPT table (EPT12), the EPT violation
8119 * will be injected with nested_ept_inject_page_fault()
8120 */
1d804d07 8121 return false;
644d711a 8122 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE
8123 /*
8124 * L2 never uses directly L1's EPT, but rather L0's own EPT
8125 * table (shadow on EPT) or a merged EPT table that L0 built
8126 * (EPT on EPT). So any problems with the structure of the
8127 * table is L0's fault.
8128 */
1d804d07 8129 return false;
644d711a
NHE
8130 case EXIT_REASON_WBINVD:
8131 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8132 case EXIT_REASON_XSETBV:
1d804d07 8133 return true;
81dc01f7
WL
8134 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8135 /*
8136 * This should never happen, since it is not possible to
8137 * set XSS to a non-zero value---neither in L1 nor in L2.
8138 * If if it were, XSS would have to be checked against
8139 * the XSS exit bitmap in vmcs12.
8140 */
8141 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
55123e3c
WL
8142 case EXIT_REASON_PREEMPTION_TIMER:
8143 return false;
ab007cc9 8144 case EXIT_REASON_PML_FULL:
03efce6f 8145 /* We emulate PML support to L1. */
ab007cc9 8146 return false;
644d711a 8147 default:
1d804d07 8148 return true;
644d711a
NHE
8149 }
8150}
8151
586f9607
AK
8152static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8153{
8154 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8155 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8156}
8157
a3eaa864 8158static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
843e4330 8159{
a3eaa864
KH
8160 if (vmx->pml_pg) {
8161 __free_page(vmx->pml_pg);
8162 vmx->pml_pg = NULL;
8163 }
843e4330
KH
8164}
8165
54bf36aa 8166static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 8167{
54bf36aa 8168 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH
8169 u64 *pml_buf;
8170 u16 pml_idx;
8171
8172 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8173
8174 /* Do nothing if PML buffer is empty */
8175 if (pml_idx == (PML_ENTITY_NUM - 1))
8176 return;
8177
8178 /* PML index always points to next available PML buffer entity */
8179 if (pml_idx >= PML_ENTITY_NUM)
8180 pml_idx = 0;
8181 else
8182 pml_idx++;
8183
8184 pml_buf = page_address(vmx->pml_pg);
8185 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8186 u64 gpa;
8187
8188 gpa = pml_buf[pml_idx];
8189 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 8190 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH
8191 }
8192
8193 /* reset PML index */
8194 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8195}
8196
8197/*
8198 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8199 * Called before reporting dirty_bitmap to userspace.
8200 */
8201static void kvm_flush_pml_buffers(struct kvm *kvm)
8202{
8203 int i;
8204 struct kvm_vcpu *vcpu;
8205 /*
8206 * We only need to kick vcpu out of guest mode here, as PML buffer
8207 * is flushed at beginning of all VMEXITs, and it's obvious that only
8208 * vcpus running in guest are possible to have unflushed GPAs in PML
8209 * buffer.
8210 */
8211 kvm_for_each_vcpu(i, vcpu, kvm)
8212 kvm_vcpu_kick(vcpu);
8213}
8214
4eb64dce
PB
8215static void vmx_dump_sel(char *name, uint32_t sel)
8216{
8217 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
96794e4e 8218 name, vmcs_read16(sel),
4eb64dce
PB
8219 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8220 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8221 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8222}
8223
8224static void vmx_dump_dtsel(char *name, uint32_t limit)
8225{
8226 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8227 name, vmcs_read32(limit),
8228 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8229}
8230
8231static void dump_vmcs(void)
8232{
8233 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8234 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8235 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8236 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8237 u32 secondary_exec_control = 0;
8238 unsigned long cr4 = vmcs_readl(GUEST_CR4);
f3531054 8239 u64 efer = vmcs_read64(GUEST_IA32_EFER);
4eb64dce
PB
8240 int i, n;
8241
8242 if (cpu_has_secondary_exec_ctrls())
8243 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8244
8245 pr_err("*** Guest State ***\n");
8246 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8247 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8248 vmcs_readl(CR0_GUEST_HOST_MASK));
8249 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8250 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8251 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8252 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8253 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8254 {
845c5b40
PB
8255 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8256 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8257 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8258 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
4eb64dce
PB
8259 }
8260 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8261 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8262 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8263 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8264 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8265 vmcs_readl(GUEST_SYSENTER_ESP),
8266 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8267 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8268 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8269 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8270 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8271 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8272 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8273 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8274 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8275 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8276 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8277 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8278 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
845c5b40
PB
8279 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8280 efer, vmcs_read64(GUEST_IA32_PAT));
8281 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8282 vmcs_read64(GUEST_IA32_DEBUGCTL),
4eb64dce
PB
8283 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8284 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
845c5b40
PB
8285 pr_err("PerfGlobCtl = 0x%016llx\n",
8286 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
4eb64dce 8287 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
845c5b40 8288 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
4eb64dce
PB
8289 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8290 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8291 vmcs_read32(GUEST_ACTIVITY_STATE));
8292 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8293 pr_err("InterruptStatus = %04x\n",
8294 vmcs_read16(GUEST_INTR_STATUS));
8295
8296 pr_err("*** Host State ***\n");
8297 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8298 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8299 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8300 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8301 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8302 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8303 vmcs_read16(HOST_TR_SELECTOR));
8304 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8305 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8306 vmcs_readl(HOST_TR_BASE));
8307 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8308 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8309 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8310 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8311 vmcs_readl(HOST_CR4));
8312 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8313 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8314 vmcs_read32(HOST_IA32_SYSENTER_CS),
8315 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8316 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
845c5b40
PB
8317 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8318 vmcs_read64(HOST_IA32_EFER),
8319 vmcs_read64(HOST_IA32_PAT));
4eb64dce 8320 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
845c5b40
PB
8321 pr_err("PerfGlobCtl = 0x%016llx\n",
8322 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
4eb64dce
PB
8323
8324 pr_err("*** Control State ***\n");
8325 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8326 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8327 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8328 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8329 vmcs_read32(EXCEPTION_BITMAP),
8330 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8331 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8332 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8333 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8334 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8335 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8336 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8337 vmcs_read32(VM_EXIT_INTR_INFO),
8338 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8339 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8340 pr_err(" reason=%08x qualification=%016lx\n",
8341 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8342 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8343 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8344 vmcs_read32(IDT_VECTORING_ERROR_CODE));
845c5b40 8345 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8cfe9866 8346 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
845c5b40
PB
8347 pr_err("TSC Multiplier = 0x%016llx\n",
8348 vmcs_read64(TSC_MULTIPLIER));
4eb64dce
PB
8349 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8350 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8351 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8352 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8353 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
845c5b40 8354 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
4eb64dce
PB
8355 n = vmcs_read32(CR3_TARGET_COUNT);
8356 for (i = 0; i + 1 < n; i += 4)
8357 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8358 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8359 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8360 if (i < n)
8361 pr_err("CR3 target%u=%016lx\n",
8362 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8363 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8364 pr_err("PLE Gap=%08x Window=%08x\n",
8365 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8366 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8367 pr_err("Virtual processor ID = 0x%04x\n",
8368 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8369}
8370
6aa8b732
AK
8371/*
8372 * The guest has exited. See if we can fix it or if we need userspace
8373 * assistance.
8374 */
851ba692 8375static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 8376{
29bd8a78 8377 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 8378 u32 exit_reason = vmx->exit_reason;
1155f76a 8379 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 8380
8b89fe1f 8381 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
db1c056c 8382 vcpu->arch.gpa_available = false;
8b89fe1f 8383
843e4330
KH
8384 /*
8385 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8386 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8387 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8388 * mode as if vcpus is in root mode, the PML buffer must has been
8389 * flushed already.
8390 */
8391 if (enable_pml)
54bf36aa 8392 vmx_flush_pml_buffer(vcpu);
843e4330 8393
80ced186 8394 /* If guest state is invalid, start emulating */
14168786 8395 if (vmx->emulation_required)
80ced186 8396 return handle_invalid_guest_state(vcpu);
1d5a4d9b 8397
644d711a 8398 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK
8399 nested_vmx_vmexit(vcpu, exit_reason,
8400 vmcs_read32(VM_EXIT_INTR_INFO),
8401 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE
8402 return 1;
8403 }
8404
5120702e 8405 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 8406 dump_vmcs();
5120702e
MG
8407 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8408 vcpu->run->fail_entry.hardware_entry_failure_reason
8409 = exit_reason;
8410 return 0;
8411 }
8412
29bd8a78 8413 if (unlikely(vmx->fail)) {
851ba692
AK
8414 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8415 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK
8416 = vmcs_read32(VM_INSTRUCTION_ERROR);
8417 return 0;
8418 }
6aa8b732 8419
b9bf6882
XG
8420 /*
8421 * Note:
8422 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8423 * delivery event since it indicates guest is accessing MMIO.
8424 * The vm-exit can be triggered again after return to guest that
8425 * will cause infinite loop.
8426 */
d77c26fc 8427 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 8428 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 8429 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b244c9fc 8430 exit_reason != EXIT_REASON_PML_FULL &&
b9bf6882
XG
8431 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8432 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8433 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
70bcd708 8434 vcpu->run->internal.ndata = 3;
b9bf6882
XG
8435 vcpu->run->internal.data[0] = vectoring_info;
8436 vcpu->run->internal.data[1] = exit_reason;
70bcd708
PB
8437 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8438 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8439 vcpu->run->internal.ndata++;
8440 vcpu->run->internal.data[3] =
8441 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8442 }
b9bf6882
XG
8443 return 0;
8444 }
3b86cd99 8445
6aa8b732
AK
8446 if (exit_reason < kvm_vmx_max_exit_handlers
8447 && kvm_vmx_exit_handlers[exit_reason])
851ba692 8448 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 8449 else {
6c6c5e03
RK
8450 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8451 exit_reason);
2bc19dc3
MT
8452 kvm_queue_exception(vcpu, UD_VECTOR);
8453 return 1;
6aa8b732 8454 }
6aa8b732
AK
8455}
8456
95ba8273 8457static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 8458{
a7c0b07d
WL
8459 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8460
8461 if (is_guest_mode(vcpu) &&
8462 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8463 return;
8464
95ba8273 8465 if (irr == -1 || tpr < irr) {
6e5d865c
YS
8466 vmcs_write32(TPR_THRESHOLD, 0);
8467 return;
8468 }
8469
95ba8273 8470 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS
8471}
8472
8d14695f
YZ
8473static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8474{
8475 u32 sec_exec_control;
8476
dccbfcf5
RK
8477 /* Postpone execution until vmcs01 is the current VMCS. */
8478 if (is_guest_mode(vcpu)) {
8479 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8480 return;
8481 }
8482
f6e90f9e 8483 if (!cpu_has_vmx_virtualize_x2apic_mode())
8d14695f
YZ
8484 return;
8485
35754c98 8486 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ
8487 return;
8488
8489 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8490
8491 if (set) {
8492 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8493 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8494 } else {
8495 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8496 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
fb6c8198 8497 vmx_flush_tlb_ept_only(vcpu);
8d14695f
YZ
8498 }
8499 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8500
8501 vmx_set_msr_bitmap(vcpu);
8502}
8503
38b99173
TC
8504static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8505{
8506 struct vcpu_vmx *vmx = to_vmx(vcpu);
8507
8508 /*
8509 * Currently we do not handle the nested case where L2 has an
8510 * APIC access page of its own; that page is still pinned.
8511 * Hence, we skip the case where the VCPU is in guest mode _and_
8512 * L1 prepared an APIC access page for L2.
8513 *
8514 * For the case where L1 and L2 share the same APIC access page
8515 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8516 * in the vmcs12), this function will only update either the vmcs01
8517 * or the vmcs02. If the former, the vmcs02 will be updated by
8518 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8519 * the next L2->L1 exit.
8520 */
8521 if (!is_guest_mode(vcpu) ||
4f2777bc 8522 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
fb6c8198 8523 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
38b99173 8524 vmcs_write64(APIC_ACCESS_ADDR, hpa);
fb6c8198
JM
8525 vmx_flush_tlb_ept_only(vcpu);
8526 }
38b99173
TC
8527}
8528
67c9dddc 8529static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
c7c9c56c
YZ
8530{
8531 u16 status;
8532 u8 old;
8533
67c9dddc
PB
8534 if (max_isr == -1)
8535 max_isr = 0;
c7c9c56c
YZ
8536
8537 status = vmcs_read16(GUEST_INTR_STATUS);
8538 old = status >> 8;
67c9dddc 8539 if (max_isr != old) {
c7c9c56c 8540 status &= 0xff;
67c9dddc 8541 status |= max_isr << 8;
c7c9c56c
YZ
8542 vmcs_write16(GUEST_INTR_STATUS, status);
8543 }
8544}
8545
8546static void vmx_set_rvi(int vector)
8547{
8548 u16 status;
8549 u8 old;
8550
4114c27d
WW
8551 if (vector == -1)
8552 vector = 0;
8553
c7c9c56c
YZ
8554 status = vmcs_read16(GUEST_INTR_STATUS);
8555 old = (u8)status & 0xff;
8556 if ((u8)vector != old) {
8557 status &= ~0xff;
8558 status |= (u8)vector;
8559 vmcs_write16(GUEST_INTR_STATUS, status);
8560 }
8561}
8562
8563static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8564{
4114c27d
WW
8565 if (!is_guest_mode(vcpu)) {
8566 vmx_set_rvi(max_irr);
8567 return;
8568 }
8569
c7c9c56c
YZ
8570 if (max_irr == -1)
8571 return;
8572
963fee16 8573 /*
4114c27d
WW
8574 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8575 * handles it.
963fee16 8576 */
4114c27d 8577 if (nested_exit_on_intr(vcpu))
963fee16
WL
8578 return;
8579
963fee16 8580 /*
4114c27d 8581 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL
8582 * is run without virtual interrupt delivery.
8583 */
8584 if (!kvm_event_needs_reinjection(vcpu) &&
8585 vmx_interrupt_allowed(vcpu)) {
8586 kvm_queue_interrupt(vcpu, max_irr, false);
8587 vmx_inject_irq(vcpu);
8588 }
c7c9c56c
YZ
8589}
8590
76dfafd5 8591static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
810e6def
PB
8592{
8593 struct vcpu_vmx *vmx = to_vmx(vcpu);
76dfafd5 8594 int max_irr;
810e6def 8595
76dfafd5
PB
8596 WARN_ON(!vcpu->arch.apicv_active);
8597 if (pi_test_on(&vmx->pi_desc)) {
8598 pi_clear_on(&vmx->pi_desc);
8599 /*
8600 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8601 * But on x86 this is just a compiler barrier anyway.
8602 */
8603 smp_mb__after_atomic();
8604 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8605 } else {
8606 max_irr = kvm_lapic_find_highest_irr(vcpu);
8607 }
8608 vmx_hwapic_irr_update(vcpu, max_irr);
8609 return max_irr;
810e6def
PB
8610}
8611
6308630b 8612static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
c7c9c56c 8613{
d62caabb 8614 if (!kvm_vcpu_apicv_active(vcpu))
3d81bc7e
YZ
8615 return;
8616
c7c9c56c
YZ
8617 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8618 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8619 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8620 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8621}
8622
967235d3
PB
8623static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8624{
8625 struct vcpu_vmx *vmx = to_vmx(vcpu);
8626
8627 pi_clear_on(&vmx->pi_desc);
8628 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8629}
8630
51aa01d1 8631static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8632{
48ae0fb4
JM
8633 u32 exit_intr_info = 0;
8634 u16 basic_exit_reason = (u16)vmx->exit_reason;
00eba012 8635
48ae0fb4
JM
8636 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8637 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
00eba012
AK
8638 return;
8639
48ae0fb4
JM
8640 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
8641 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8642 vmx->exit_intr_info = exit_intr_info;
a0861c02
AK
8643
8644 /* Handle machine checks before interrupts are enabled */
48ae0fb4
JM
8645 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
8646 is_machine_check(exit_intr_info))
a0861c02
AK
8647 kvm_machine_check();
8648
20f65983 8649 /* We need to handle NMIs before interrupts are enabled */
ef85b673 8650 if (is_nmi(exit_intr_info)) {
ff9d07a0 8651 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8652 asm("int $2");
ff9d07a0
ZY
8653 kvm_after_handle_nmi(&vmx->vcpu);
8654 }
51aa01d1 8655}
20f65983 8656
a547c6db
YZ
8657static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8658{
8659 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3f62de5f 8660 register void *__sp asm(_ASM_SP);
a547c6db 8661
a547c6db
YZ
8662 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8663 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8664 unsigned int vector;
8665 unsigned long entry;
8666 gate_desc *desc;
8667 struct vcpu_vmx *vmx = to_vmx(vcpu);
8668#ifdef CONFIG_X86_64
8669 unsigned long tmp;
8670#endif
8671
8672 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8673 desc = (gate_desc *)vmx->host_idt_base + vector;
8674 entry = gate_offset(*desc);
8675 asm volatile(
8676#ifdef CONFIG_X86_64
8677 "mov %%" _ASM_SP ", %[sp]\n\t"
8678 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8679 "push $%c[ss]\n\t"
8680 "push %[sp]\n\t"
8681#endif
8682 "pushf\n\t"
a547c6db
YZ
8683 __ASM_SIZE(push) " $%c[cs]\n\t"
8684 "call *%[entry]\n\t"
8685 :
8686#ifdef CONFIG_X86_64
3f62de5f 8687 [sp]"=&r"(tmp),
a547c6db 8688#endif
3f62de5f 8689 "+r"(__sp)
a547c6db
YZ
8690 :
8691 [entry]"r"(entry),
8692 [ss]"i"(__KERNEL_DS),
8693 [cs]"i"(__KERNEL_CS)
8694 );
f2485b3e 8695 }
a547c6db 8696}
c207aee4 8697STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
a547c6db 8698
6d396b55
PB
8699static bool vmx_has_high_real_mode_segbase(void)
8700{
8701 return enable_unrestricted_guest || emulate_invalid_guest_state;
8702}
8703
da8999d3
LJ
8704static bool vmx_mpx_supported(void)
8705{
8706 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8707 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8708}
8709
55412b2e
WL
8710static bool vmx_xsaves_supported(void)
8711{
8712 return vmcs_config.cpu_based_2nd_exec_ctrl &
8713 SECONDARY_EXEC_XSAVES;
8714}
8715
51aa01d1
AK
8716static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8717{
c5ca8e57 8718 u32 exit_intr_info;
51aa01d1
AK
8719 bool unblock_nmi;
8720 u8 vector;
8721 bool idtv_info_valid;
8722
8723 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8724
2c82878b
PB
8725 if (vmx->nmi_known_unmasked)
8726 return;
8727 /*
8728 * Can't use vmx->exit_intr_info since we're not sure what
8729 * the exit reason is.
8730 */
8731 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8732 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8733 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8734 /*
8735 * SDM 3: 27.7.1.2 (September 2008)
8736 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8737 * a guest IRET fault.
8738 * SDM 3: 23.2.2 (September 2008)
8739 * Bit 12 is undefined in any of the following cases:
8740 * If the VM exit sets the valid bit in the IDT-vectoring
8741 * information field.
8742 * If the VM exit is due to a double fault.
8743 */
8744 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8745 vector != DF_VECTOR && !idtv_info_valid)
8746 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8747 GUEST_INTR_STATE_NMI);
8748 else
8749 vmx->nmi_known_unmasked =
8750 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8751 & GUEST_INTR_STATE_NMI);
51aa01d1
AK
8752}
8753
3ab66e8a 8754static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK
8755 u32 idt_vectoring_info,
8756 int instr_len_field,
8757 int error_code_field)
51aa01d1 8758{
51aa01d1
AK
8759 u8 vector;
8760 int type;
8761 bool idtv_info_valid;
8762
8763 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8764
3ab66e8a
JK
8765 vcpu->arch.nmi_injected = false;
8766 kvm_clear_exception_queue(vcpu);
8767 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN
8768
8769 if (!idtv_info_valid)
8770 return;
8771
3ab66e8a 8772 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8773
668f612f
AK
8774 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8775 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8776
64a7ec06 8777 switch (type) {
37b96e98 8778 case INTR_TYPE_NMI_INTR:
3ab66e8a 8779 vcpu->arch.nmi_injected = true;
668f612f 8780 /*
7b4a25cb 8781 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN
8782 * Clear bit "block by NMI" before VM entry if a NMI
8783 * delivery faulted.
668f612f 8784 */
3ab66e8a 8785 vmx_set_nmi_mask(vcpu, false);
37b96e98 8786 break;
37b96e98 8787 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8788 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN
8789 /* fall through */
8790 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8791 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8792 u32 err = vmcs_read32(error_code_field);
851eb667 8793 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8794 } else
851eb667 8795 kvm_requeue_exception(vcpu, vector);
37b96e98 8796 break;
66fd3f7f 8797 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8798 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8799 /* fall through */
37b96e98 8800 case INTR_TYPE_EXT_INTR:
3ab66e8a 8801 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN
8802 break;
8803 default:
8804 break;
f7d9238f 8805 }
cf393f75
AK
8806}
8807
83422e17
AK
8808static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8809{
3ab66e8a 8810 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK
8811 VM_EXIT_INSTRUCTION_LEN,
8812 IDT_VECTORING_ERROR_CODE);
8813}
8814
b463a6f7
AK
8815static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8816{
3ab66e8a 8817 __vmx_complete_interrupts(vcpu,
b463a6f7
AK
8818 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8819 VM_ENTRY_INSTRUCTION_LEN,
8820 VM_ENTRY_EXCEPTION_ERROR_CODE);
8821
8822 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8823}
8824
d7cd9796
GN
8825static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8826{
8827 int i, nr_msrs;
8828 struct perf_guest_switch_msr *msrs;
8829
8830 msrs = perf_guest_get_msrs(&nr_msrs);
8831
8832 if (!msrs)
8833 return;
8834
8835 for (i = 0; i < nr_msrs; i++)
8836 if (msrs[i].host == msrs[i].guest)
8837 clear_atomic_switch_msr(vmx, msrs[i].msr);
8838 else
8839 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8840 msrs[i].host);
8841}
8842
33365e7a 8843static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
64672c95
YJ
8844{
8845 struct vcpu_vmx *vmx = to_vmx(vcpu);
8846 u64 tscl;
8847 u32 delta_tsc;
8848
8849 if (vmx->hv_deadline_tsc == -1)
8850 return;
8851
8852 tscl = rdtsc();
8853 if (vmx->hv_deadline_tsc > tscl)
8854 /* sure to be 32 bit only because checked on set_hv_timer */
8855 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8856 cpu_preemption_timer_multi);
8857 else
8858 delta_tsc = 0;
8859
8860 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8861}
8862
a3b5ba49 8863static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8864{
a2fa3e9f 8865 struct vcpu_vmx *vmx = to_vmx(vcpu);
d6e41f11 8866 unsigned long debugctlmsr, cr3, cr4;
104f226b 8867
104f226b
AK
8868 /* Don't enter VMX if guest state is invalid, let the exit handler
8869 start emulation until we arrive back to a valid state */
14168786 8870 if (vmx->emulation_required)
104f226b
AK
8871 return;
8872
a7653ecd
RK
8873 if (vmx->ple_window_dirty) {
8874 vmx->ple_window_dirty = false;
8875 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8876 }
8877
012f83cb
AG
8878 if (vmx->nested.sync_shadow_vmcs) {
8879 copy_vmcs12_to_shadow(vmx);
8880 vmx->nested.sync_shadow_vmcs = false;
8881 }
8882
104f226b
AK
8883 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8884 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8885 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8886 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8887
d6e41f11
AL
8888 cr3 = __get_current_cr3_fast();
8889 if (unlikely(cr3 != vmx->host_state.vmcs_host_cr3)) {
8890 vmcs_writel(HOST_CR3, cr3);
8891 vmx->host_state.vmcs_host_cr3 = cr3;
8892 }
8893
1e02ce4c 8894 cr4 = cr4_read_shadow();
d974baa3
AL
8895 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8896 vmcs_writel(HOST_CR4, cr4);
8897 vmx->host_state.vmcs_host_cr4 = cr4;
8898 }
8899
104f226b
AK
8900 /* When single-stepping over STI and MOV SS, we must clear the
8901 * corresponding interruptibility bits in the guest state. Otherwise
8902 * vmentry fails as it then expects bit 14 (BS) in pending debug
8903 * exceptions being set, but that's not correct for the guest debugging
8904 * case. */
8905 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8906 vmx_set_interrupt_shadow(vcpu, 0);
8907
1be0e61c
XG
8908 if (vmx->guest_pkru_valid)
8909 __write_pkru(vmx->guest_pkru);
8910
d7cd9796 8911 atomic_switch_perf_msrs(vmx);
2a7921b7 8912 debugctlmsr = get_debugctlmsr();
d7cd9796 8913
64672c95
YJ
8914 vmx_arm_hv_timer(vcpu);
8915
d462b819 8916 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8917 asm(
6aa8b732 8918 /* Store host registers */
b188c81f
AK
8919 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8920 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8921 "push %%" _ASM_CX " \n\t"
8922 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8923 "je 1f \n\t"
b188c81f 8924 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8925 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8926 "1: \n\t"
d3edefc0 8927 /* Reload cr2 if changed */
b188c81f
AK
8928 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8929 "mov %%cr2, %%" _ASM_DX " \n\t"
8930 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8931 "je 2f \n\t"
b188c81f 8932 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8933 "2: \n\t"
6aa8b732 8934 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8935 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8936 /* Load guest registers. Don't clobber flags. */
b188c81f
AK
8937 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8938 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8939 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8940 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8941 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8942 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8943#ifdef CONFIG_X86_64
e08aa78a
AK
8944 "mov %c[r8](%0), %%r8 \n\t"
8945 "mov %c[r9](%0), %%r9 \n\t"
8946 "mov %c[r10](%0), %%r10 \n\t"
8947 "mov %c[r11](%0), %%r11 \n\t"
8948 "mov %c[r12](%0), %%r12 \n\t"
8949 "mov %c[r13](%0), %%r13 \n\t"
8950 "mov %c[r14](%0), %%r14 \n\t"
8951 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8952#endif
b188c81f 8953 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8954
6aa8b732 8955 /* Enter guest mode */
83287ea4 8956 "jne 1f \n\t"
4ecac3fd 8957 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK
8958 "jmp 2f \n\t"
8959 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8960 "2: "
6aa8b732 8961 /* Save guest registers, load host registers, keep flags */
b188c81f 8962 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8963 "pop %0 \n\t"
b188c81f
AK
8964 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8965 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8966 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8967 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8968 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8969 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8970 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8971#ifdef CONFIG_X86_64
e08aa78a
AK
8972 "mov %%r8, %c[r8](%0) \n\t"
8973 "mov %%r9, %c[r9](%0) \n\t"
8974 "mov %%r10, %c[r10](%0) \n\t"
8975 "mov %%r11, %c[r11](%0) \n\t"
8976 "mov %%r12, %c[r12](%0) \n\t"
8977 "mov %%r13, %c[r13](%0) \n\t"
8978 "mov %%r14, %c[r14](%0) \n\t"
8979 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8980#endif
b188c81f
AK
8981 "mov %%cr2, %%" _ASM_AX " \n\t"
8982 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8983
b188c81f 8984 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8985 "setbe %c[fail](%0) \n\t"
83287ea4
AK
8986 ".pushsection .rodata \n\t"
8987 ".global vmx_return \n\t"
8988 "vmx_return: " _ASM_PTR " 2b \n\t"
8989 ".popsection"
e08aa78a 8990 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8991 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8992 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8993 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX
8994 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8995 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8996 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8997 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8998 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8999 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9000 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 9001#ifdef CONFIG_X86_64
ad312c7c
ZX
9002 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9003 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9004 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9005 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9006 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9007 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9008 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9009 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 9010#endif
40712fae
AK
9011 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9012 [wordsize]"i"(sizeof(ulong))
c2036300
LV
9013 : "cc", "memory"
9014#ifdef CONFIG_X86_64
b188c81f 9015 , "rax", "rbx", "rdi", "rsi"
c2036300 9016 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK
9017#else
9018 , "eax", "ebx", "edi", "esi"
c2036300
LV
9019#endif
9020 );
6aa8b732 9021
2a7921b7
GN
9022 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9023 if (debugctlmsr)
9024 update_debugctlmsr(debugctlmsr);
9025
aa67f609
AK
9026#ifndef CONFIG_X86_64
9027 /*
9028 * The sysexit path does not restore ds/es, so we must set them to
9029 * a reasonable value ourselves.
9030 *
9031 * We can't defer this to vmx_load_host_state() since that function
9032 * may be executed in interrupt context, which saves and restore segments
9033 * around it, nullifying its effect.
9034 */
9035 loadsegment(ds, __USER_DS);
9036 loadsegment(es, __USER_DS);
9037#endif
9038
6de4f3ad 9039 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 9040 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 9041 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 9042 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 9043 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT
9044 vcpu->arch.regs_dirty = 0;
9045
1155f76a
AK
9046 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9047
d462b819 9048 vmx->loaded_vmcs->launched = 1;
1b6269db 9049
51aa01d1 9050 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1 9051
1be0e61c
XG
9052 /*
9053 * eager fpu is enabled if PKEY is supported and CR4 is switched
9054 * back on host, so it is safe to read guest PKRU from current
9055 * XSAVE.
9056 */
9057 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9058 vmx->guest_pkru = __read_pkru();
9059 if (vmx->guest_pkru != vmx->host_pkru) {
9060 vmx->guest_pkru_valid = true;
9061 __write_pkru(vmx->host_pkru);
9062 } else
9063 vmx->guest_pkru_valid = false;
9064 }
9065
e0b890d3
GN
9066 /*
9067 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9068 * we did not inject a still-pending event to L1 now because of
9069 * nested_run_pending, we need to re-enable this bit.
9070 */
9071 if (vmx->nested.nested_run_pending)
9072 kvm_make_request(KVM_REQ_EVENT, vcpu);
9073
9074 vmx->nested.nested_run_pending = 0;
9075
51aa01d1
AK
9076 vmx_complete_atomic_exit(vmx);
9077 vmx_recover_nmi_blocking(vmx);
cf393f75 9078 vmx_complete_interrupts(vmx);
6aa8b732 9079}
c207aee4 9080STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
6aa8b732 9081
1279a6b1 9082static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
4fa7734c
PB
9083{
9084 struct vcpu_vmx *vmx = to_vmx(vcpu);
9085 int cpu;
9086
1279a6b1 9087 if (vmx->loaded_vmcs == vmcs)
4fa7734c
PB
9088 return;
9089
9090 cpu = get_cpu();
1279a6b1 9091 vmx->loaded_vmcs = vmcs;
4fa7734c
PB
9092 vmx_vcpu_put(vcpu);
9093 vmx_vcpu_load(vcpu, cpu);
9094 vcpu->cpu = cpu;
9095 put_cpu();
9096}
9097
2f1fe811
JM
9098/*
9099 * Ensure that the current vmcs of the logical processor is the
9100 * vmcs01 of the vcpu before calling free_nested().
9101 */
9102static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9103{
9104 struct vcpu_vmx *vmx = to_vmx(vcpu);
9105 int r;
9106
9107 r = vcpu_load(vcpu);
9108 BUG_ON(r);
1279a6b1 9109 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
2f1fe811
JM
9110 free_nested(vmx);
9111 vcpu_put(vcpu);
9112}
9113
6aa8b732
AK
9114static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9115{
fb3f0f51
RR
9116 struct vcpu_vmx *vmx = to_vmx(vcpu);
9117
843e4330 9118 if (enable_pml)
a3eaa864 9119 vmx_destroy_pml_buffer(vmx);
991e7a0e 9120 free_vpid(vmx->vpid);
4fa7734c 9121 leave_guest_mode(vcpu);
2f1fe811 9122 vmx_free_vcpu_nested(vcpu);
4fa7734c 9123 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR
9124 kfree(vmx->guest_msrs);
9125 kvm_vcpu_uninit(vcpu);
a4770347 9126 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK
9127}
9128
fb3f0f51 9129static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 9130{
fb3f0f51 9131 int err;
c16f862d 9132 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 9133 int cpu;
6aa8b732 9134
a2fa3e9f 9135 if (!vmx)
fb3f0f51
RR
9136 return ERR_PTR(-ENOMEM);
9137
991e7a0e 9138 vmx->vpid = allocate_vpid();
2384d2b3 9139
fb3f0f51
RR
9140 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9141 if (err)
9142 goto free_vcpu;
965b58a5 9143
4e59516a
PF
9144 err = -ENOMEM;
9145
9146 /*
9147 * If PML is turned on, failure on enabling PML just results in failure
9148 * of creating the vcpu, therefore we can simplify PML logic (by
9149 * avoiding dealing with cases, such as enabling PML partially on vcpus
9150 * for the guest, etc.
9151 */
9152 if (enable_pml) {
9153 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9154 if (!vmx->pml_pg)
9155 goto uninit_vcpu;
9156 }
9157
a2fa3e9f 9158 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB
9159 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9160 > PAGE_SIZE);
0123be42 9161
4e59516a
PF
9162 if (!vmx->guest_msrs)
9163 goto free_pml;
965b58a5 9164
d462b819
NHE
9165 vmx->loaded_vmcs = &vmx->vmcs01;
9166 vmx->loaded_vmcs->vmcs = alloc_vmcs();
355f4fb1 9167 vmx->loaded_vmcs->shadow_vmcs = NULL;
d462b819 9168 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 9169 goto free_msrs;
d462b819 9170 loaded_vmcs_init(vmx->loaded_vmcs);
a2fa3e9f 9171
15ad7146
AK
9172 cpu = get_cpu();
9173 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 9174 vmx->vcpu.cpu = cpu;
8b9cf98c 9175 err = vmx_vcpu_setup(vmx);
fb3f0f51 9176 vmx_vcpu_put(&vmx->vcpu);
15ad7146 9177 put_cpu();
fb3f0f51
RR
9178 if (err)
9179 goto free_vmcs;
35754c98 9180 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK
9181 err = alloc_apic_access_page(kvm);
9182 if (err)
5e4a0b3c 9183 goto free_vmcs;
a63cb560 9184 }
fb3f0f51 9185
b927a3ce
SY
9186 if (enable_ept) {
9187 if (!kvm->arch.ept_identity_map_addr)
9188 kvm->arch.ept_identity_map_addr =
9189 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC
9190 err = init_rmode_identity_map(kvm);
9191 if (err)
93ea5388 9192 goto free_vmcs;
b927a3ce 9193 }
b7ebfb05 9194
5c614b35 9195 if (nested) {
b9c237bb 9196 nested_vmx_setup_ctls_msrs(vmx);
5c614b35
WL
9197 vmx->nested.vpid02 = allocate_vpid();
9198 }
b9c237bb 9199
705699a1 9200 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE
9201 vmx->nested.current_vmptr = -1ull;
9202 vmx->nested.current_vmcs12 = NULL;
9203
37e4c997
HZ
9204 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9205
fb3f0f51
RR
9206 return &vmx->vcpu;
9207
9208free_vmcs:
5c614b35 9209 free_vpid(vmx->nested.vpid02);
5f3fbc34 9210 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 9211free_msrs:
fb3f0f51 9212 kfree(vmx->guest_msrs);
4e59516a
PF
9213free_pml:
9214 vmx_destroy_pml_buffer(vmx);
fb3f0f51
RR
9215uninit_vcpu:
9216 kvm_vcpu_uninit(&vmx->vcpu);
9217free_vcpu:
991e7a0e 9218 free_vpid(vmx->vpid);
a4770347 9219 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 9220 return ERR_PTR(err);
6aa8b732
AK
9221}
9222
002c7f7c
YS
9223static void __init vmx_check_processor_compat(void *rtn)
9224{
9225 struct vmcs_config vmcs_conf;
9226
9227 *(int *)rtn = 0;
9228 if (setup_vmcs_config(&vmcs_conf) < 0)
9229 *(int *)rtn = -EIO;
9230 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9231 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9232 smp_processor_id());
9233 *(int *)rtn = -EIO;
9234 }
9235}
9236
67253af5
SY
9237static int get_ept_level(void)
9238{
9239 return VMX_EPT_DEFAULT_GAW + 1;
9240}
9241
4b12f0de 9242static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 9243{
b18d5431
XG
9244 u8 cache;
9245 u64 ipat = 0;
4b12f0de 9246
522c68c4 9247 /* For VT-d and EPT combination
606decd6 9248 * 1. MMIO: always map as UC
522c68c4
SY
9249 * 2. EPT with VT-d:
9250 * a. VT-d without snooping control feature: can't guarantee the
606decd6 9251 * result, try to trust guest.
522c68c4
SY
9252 * b. VT-d with snooping control feature: snooping control feature of
9253 * VT-d engine can guarantee the cache correctness. Just set it
9254 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 9255 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY
9256 * consistent with host MTRR
9257 */
606decd6
PB
9258 if (is_mmio) {
9259 cache = MTRR_TYPE_UNCACHABLE;
9260 goto exit;
9261 }
9262
9263 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG
9264 ipat = VMX_EPT_IPAT_BIT;
9265 cache = MTRR_TYPE_WRBACK;
9266 goto exit;
9267 }
9268
9269 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9270 ipat = VMX_EPT_IPAT_BIT;
0da029ed 9271 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG
9272 cache = MTRR_TYPE_WRBACK;
9273 else
9274 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG
9275 goto exit;
9276 }
9277
ff53604b 9278 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG
9279
9280exit:
9281 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY
9282}
9283
17cc3935 9284static int vmx_get_lpage_level(void)
344f414f 9285{
878403b7
SY
9286 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9287 return PT_DIRECTORY_LEVEL;
9288 else
9289 /* For shadow and EPT supported 1GB page */
9290 return PT_PDPE_LEVEL;
344f414f
JR
9291}
9292
feda805f
XG
9293static void vmcs_set_secondary_exec_control(u32 new_ctl)
9294{
9295 /*
9296 * These bits in the secondary execution controls field
9297 * are dynamic, the others are mostly based on the hypervisor
9298 * architecture and the guest's CPUID. Do not touch the
9299 * dynamic bits.
9300 */
9301 u32 mask =
9302 SECONDARY_EXEC_SHADOW_VMCS |
9303 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9304 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9305
9306 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9307
9308 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9309 (new_ctl & ~mask) | (cur_ctl & mask));
9310}
9311
8322ebbb
DM
9312/*
9313 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9314 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9315 */
9316static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9317{
9318 struct vcpu_vmx *vmx = to_vmx(vcpu);
9319 struct kvm_cpuid_entry2 *entry;
9320
9321 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9322 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9323
9324#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9325 if (entry && (entry->_reg & (_cpuid_mask))) \
9326 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9327} while (0)
9328
9329 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9330 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
9331 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
9332 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
9333 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
9334 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
9335 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
9336 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
9337 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
9338 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
9339 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9340 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
9341 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
9342 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
9343 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
9344
9345 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9346 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
9347 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
9348 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
9349 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
9350 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9351 cr4_fixed1_update(bit(11), ecx, bit(2));
9352
9353#undef cr4_fixed1_update
9354}
9355
0e851880
SY
9356static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9357{
4e47c7a6
SY
9358 struct kvm_cpuid_entry2 *best;
9359 struct vcpu_vmx *vmx = to_vmx(vcpu);
feda805f 9360 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
4e47c7a6 9361
4e47c7a6 9362 if (vmx_rdtscp_supported()) {
1cea0ce6
XG
9363 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9364 if (!rdtscp_enabled)
feda805f 9365 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
f36201e5 9366
8b97265a 9367 if (nested) {
1cea0ce6 9368 if (rdtscp_enabled)
8b97265a
PB
9369 vmx->nested.nested_vmx_secondary_ctls_high |=
9370 SECONDARY_EXEC_RDTSCP;
9371 else
9372 vmx->nested.nested_vmx_secondary_ctls_high &=
9373 ~SECONDARY_EXEC_RDTSCP;
9374 }
4e47c7a6 9375 }
ad756a16 9376
ad756a16
MJ
9377 /* Exposing INVPCID only when PCID is exposed */
9378 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9379 if (vmx_invpcid_supported() &&
29541bb8
XG
9380 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9381 !guest_cpuid_has_pcid(vcpu))) {
feda805f 9382 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
29541bb8 9383
ad756a16 9384 if (best)
4f977045 9385 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 9386 }
8b3e34e4 9387
45bdbcfd
HH
9388 if (cpu_has_secondary_exec_ctrls())
9389 vmcs_set_secondary_exec_control(secondary_exec_ctl);
feda805f 9390
37e4c997
HZ
9391 if (nested_vmx_allowed(vcpu))
9392 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9393 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9394 else
9395 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9396 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
8322ebbb
DM
9397
9398 if (nested_vmx_allowed(vcpu))
9399 nested_vmx_cr_fixed1_bits_update(vcpu);
0e851880
SY
9400}
9401
d4330ef2
JR
9402static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9403{
7b8050f5
NHE
9404 if (func == 1 && nested)
9405 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR
9406}
9407
25d92081
YZ
9408static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9409 struct x86_exception *fault)
9410{
533558bc 9411 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
c5f983f6 9412 struct vcpu_vmx *vmx = to_vmx(vcpu);
533558bc 9413 u32 exit_reason;
c5f983f6 9414 unsigned long exit_qualification = vcpu->arch.exit_qualification;
25d92081 9415
c5f983f6
BD
9416 if (vmx->nested.pml_full) {
9417 exit_reason = EXIT_REASON_PML_FULL;
9418 vmx->nested.pml_full = false;
9419 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9420 } else if (fault->error_code & PFERR_RSVD_MASK)
533558bc 9421 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 9422 else
533558bc 9423 exit_reason = EXIT_REASON_EPT_VIOLATION;
c5f983f6
BD
9424
9425 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
25d92081
YZ
9426 vmcs12->guest_physical_address = fault->address;
9427}
9428
995f00a6
PF
9429static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9430{
9431 return nested_ept_get_cr3(vcpu) & VMX_EPT_AD_ENABLE_BIT;
9432}
9433
155a97a3
NHE
9434/* Callbacks for nested_ept_init_mmu_context: */
9435
9436static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9437{
9438 /* return the page table to be shadowed - in our case, EPT12 */
9439 return get_vmcs12(vcpu)->ept_pointer;
9440}
9441
ae1e2d10 9442static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 9443{
995f00a6 9444 bool wants_ad;
ae1e2d10 9445
ad896af0 9446 WARN_ON(mmu_is_nested(vcpu));
995f00a6
PF
9447 wants_ad = nested_ept_ad_enabled(vcpu);
9448 if (wants_ad && !enable_ept_ad_bits)
ae1e2d10
PB
9449 return 1;
9450
9451 kvm_mmu_unload(vcpu);
ad896af0 9452 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb 9453 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
ae1e2d10 9454 VMX_EPT_EXECUTE_ONLY_BIT,
995f00a6 9455 wants_ad);
155a97a3
NHE
9456 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9457 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9458 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9459
9460 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
ae1e2d10 9461 return 0;
155a97a3
NHE
9462}
9463
9464static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9465{
9466 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9467}
9468
19d5f10b
EK
9469static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9470 u16 error_code)
9471{
9472 bool inequality, bit;
9473
9474 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9475 inequality =
9476 (error_code & vmcs12->page_fault_error_code_mask) !=
9477 vmcs12->page_fault_error_code_match;
9478 return inequality ^ bit;
9479}
9480
feaf0c7d
GN
9481static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9482 struct x86_exception *fault)
9483{
9484 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9485
9486 WARN_ON(!is_guest_mode(vcpu));
9487
19d5f10b 9488 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK
9489 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9490 vmcs_read32(VM_EXIT_INTR_INFO),
9491 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN
9492 else
9493 kvm_inject_page_fault(vcpu, fault);
9494}
9495
6beb7bd5
JM
9496static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9497 struct vmcs12 *vmcs12);
9498
9499static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
a2bcba50
WL
9500 struct vmcs12 *vmcs12)
9501{
9502 struct vcpu_vmx *vmx = to_vmx(vcpu);
6beb7bd5 9503 u64 hpa;
a2bcba50
WL
9504
9505 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a2bcba50
WL
9506 /*
9507 * Translate L1 physical address to host physical
9508 * address for vmcs02. Keep the page pinned, so this
9509 * physical address remains valid. We keep a reference
9510 * to it so we can release it later.
9511 */
9512 if (vmx->nested.apic_access_page) /* shouldn't happen */
9513 nested_release_page(vmx->nested.apic_access_page);
9514 vmx->nested.apic_access_page =
9515 nested_get_page(vcpu, vmcs12->apic_access_addr);
6beb7bd5
JM
9516 /*
9517 * If translation failed, no matter: This feature asks
9518 * to exit when accessing the given address, and if it
9519 * can never be accessed, this feature won't do
9520 * anything anyway.
9521 */
9522 if (vmx->nested.apic_access_page) {
9523 hpa = page_to_phys(vmx->nested.apic_access_page);
9524 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9525 } else {
9526 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9527 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9528 }
9529 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9530 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9531 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9532 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9533 kvm_vcpu_reload_apic_access_page(vcpu);
a2bcba50 9534 }
a7c0b07d
WL
9535
9536 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
a7c0b07d
WL
9537 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9538 nested_release_page(vmx->nested.virtual_apic_page);
9539 vmx->nested.virtual_apic_page =
9540 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9541
9542 /*
6beb7bd5
JM
9543 * If translation failed, VM entry will fail because
9544 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9545 * Failing the vm entry is _not_ what the processor
9546 * does but it's basically the only possibility we
9547 * have. We could still enter the guest if CR8 load
9548 * exits are enabled, CR8 store exits are enabled, and
9549 * virtualize APIC access is disabled; in this case
9550 * the processor would never use the TPR shadow and we
9551 * could simply clear the bit from the execution
9552 * control. But such a configuration is useless, so
9553 * let's keep the code simple.
a7c0b07d 9554 */
6beb7bd5
JM
9555 if (vmx->nested.virtual_apic_page) {
9556 hpa = page_to_phys(vmx->nested.virtual_apic_page);
9557 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9558 }
a7c0b07d
WL
9559 }
9560
705699a1 9561 if (nested_cpu_has_posted_intr(vmcs12)) {
705699a1
WV
9562 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9563 kunmap(vmx->nested.pi_desc_page);
9564 nested_release_page(vmx->nested.pi_desc_page);
9565 }
9566 vmx->nested.pi_desc_page =
9567 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
705699a1
WV
9568 vmx->nested.pi_desc =
9569 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9570 if (!vmx->nested.pi_desc) {
9571 nested_release_page_clean(vmx->nested.pi_desc_page);
6beb7bd5 9572 return;
705699a1
WV
9573 }
9574 vmx->nested.pi_desc =
9575 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9576 (unsigned long)(vmcs12->posted_intr_desc_addr &
9577 (PAGE_SIZE - 1)));
6beb7bd5
JM
9578 vmcs_write64(POSTED_INTR_DESC_ADDR,
9579 page_to_phys(vmx->nested.pi_desc_page) +
9580 (unsigned long)(vmcs12->posted_intr_desc_addr &
9581 (PAGE_SIZE - 1)));
705699a1 9582 }
6beb7bd5
JM
9583 if (cpu_has_vmx_msr_bitmap() &&
9584 nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9585 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9586 ;
9587 else
9588 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9589 CPU_BASED_USE_MSR_BITMAPS);
a2bcba50
WL
9590}
9591
f4124500
JK
9592static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9593{
9594 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9595 struct vcpu_vmx *vmx = to_vmx(vcpu);
9596
9597 if (vcpu->arch.virtual_tsc_khz == 0)
9598 return;
9599
9600 /* Make sure short timeouts reliably trigger an immediate vmexit.
9601 * hrtimer_start does not guarantee this. */
9602 if (preemption_timeout <= 1) {
9603 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9604 return;
9605 }
9606
9607 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9608 preemption_timeout *= 1000000;
9609 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9610 hrtimer_start(&vmx->nested.preemption_timer,
9611 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9612}
9613
56a20510
JM
9614static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
9615 struct vmcs12 *vmcs12)
9616{
9617 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9618 return 0;
9619
9620 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
9621 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
9622 return -EINVAL;
9623
9624 return 0;
9625}
9626
3af18d9c
WV
9627static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9628 struct vmcs12 *vmcs12)
9629{
3af18d9c
WV
9630 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9631 return 0;
9632
5fa99cbe 9633 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
3af18d9c
WV
9634 return -EINVAL;
9635
9636 return 0;
9637}
9638
9639/*
9640 * Merge L0's and L1's MSR bitmap, return false to indicate that
9641 * we do not use the hardware.
9642 */
9643static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9644 struct vmcs12 *vmcs12)
9645{
82f0dd4b 9646 int msr;
f2b93280 9647 struct page *page;
d048c098
RK
9648 unsigned long *msr_bitmap_l1;
9649 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
f2b93280 9650
d048c098 9651 /* This shortcut is ok because we support only x2APIC MSRs so far. */
f2b93280
WV
9652 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9653 return false;
9654
9655 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
05d8d346 9656 if (!page)
f2b93280 9657 return false;
d048c098 9658 msr_bitmap_l1 = (unsigned long *)kmap(page);
f2b93280 9659
d048c098
RK
9660 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9661
f2b93280 9662 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV
9663 if (nested_cpu_has_apic_reg_virt(vmcs12))
9664 for (msr = 0x800; msr <= 0x8ff; msr++)
9665 nested_vmx_disable_intercept_for_msr(
d048c098 9666 msr_bitmap_l1, msr_bitmap_l0,
82f0dd4b 9667 msr, MSR_TYPE_R);
d048c098
RK
9668
9669 nested_vmx_disable_intercept_for_msr(
9670 msr_bitmap_l1, msr_bitmap_l0,
f2b93280
WV
9671 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9672 MSR_TYPE_R | MSR_TYPE_W);
d048c098 9673
608406e2 9674 if (nested_cpu_has_vid(vmcs12)) {
608406e2 9675 nested_vmx_disable_intercept_for_msr(
d048c098 9676 msr_bitmap_l1, msr_bitmap_l0,
608406e2
WV
9677 APIC_BASE_MSR + (APIC_EOI >> 4),
9678 MSR_TYPE_W);
9679 nested_vmx_disable_intercept_for_msr(
d048c098 9680 msr_bitmap_l1, msr_bitmap_l0,
608406e2
WV
9681 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9682 MSR_TYPE_W);
9683 }
82f0dd4b 9684 }
f2b93280
WV
9685 kunmap(page);
9686 nested_release_page_clean(page);
9687
9688 return true;
9689}
9690
9691static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9692 struct vmcs12 *vmcs12)
9693{
82f0dd4b 9694 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 9695 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV
9696 !nested_cpu_has_vid(vmcs12) &&
9697 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV
9698 return 0;
9699
9700 /*
9701 * If virtualize x2apic mode is enabled,
9702 * virtualize apic access must be disabled.
9703 */
82f0dd4b
WV
9704 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9705 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV
9706 return -EINVAL;
9707
608406e2
WV
9708 /*
9709 * If virtual interrupt delivery is enabled,
9710 * we must exit on external interrupts.
9711 */
9712 if (nested_cpu_has_vid(vmcs12) &&
9713 !nested_exit_on_intr(vcpu))
9714 return -EINVAL;
9715
705699a1
WV
9716 /*
9717 * bits 15:8 should be zero in posted_intr_nv,
9718 * the descriptor address has been already checked
9719 * in nested_get_vmcs12_pages.
9720 */
9721 if (nested_cpu_has_posted_intr(vmcs12) &&
9722 (!nested_cpu_has_vid(vmcs12) ||
9723 !nested_exit_intr_ack_set(vcpu) ||
9724 vmcs12->posted_intr_nv & 0xff00))
9725 return -EINVAL;
9726
f2b93280
WV
9727 /* tpr shadow is needed by all apicv features. */
9728 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9729 return -EINVAL;
9730
9731 return 0;
3af18d9c
WV
9732}
9733
e9ac033e
EK
9734static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9735 unsigned long count_field,
92d71bc6 9736 unsigned long addr_field)
ff651cb6 9737{
92d71bc6 9738 int maxphyaddr;
e9ac033e
EK
9739 u64 count, addr;
9740
9741 if (vmcs12_read_any(vcpu, count_field, &count) ||
9742 vmcs12_read_any(vcpu, addr_field, &addr)) {
9743 WARN_ON(1);
9744 return -EINVAL;
9745 }
9746 if (count == 0)
9747 return 0;
92d71bc6 9748 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK
9749 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9750 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
bbe41b95 9751 pr_debug_ratelimited(
e9ac033e
EK
9752 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9753 addr_field, maxphyaddr, count, addr);
9754 return -EINVAL;
9755 }
9756 return 0;
9757}
9758
9759static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9760 struct vmcs12 *vmcs12)
9761{
e9ac033e
EK
9762 if (vmcs12->vm_exit_msr_load_count == 0 &&
9763 vmcs12->vm_exit_msr_store_count == 0 &&
9764 vmcs12->vm_entry_msr_load_count == 0)
9765 return 0; /* Fast path */
e9ac033e 9766 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9767 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9768 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9769 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9770 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9771 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK
9772 return -EINVAL;
9773 return 0;
9774}
9775
c5f983f6
BD
9776static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
9777 struct vmcs12 *vmcs12)
9778{
9779 u64 address = vmcs12->pml_address;
9780 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9781
9782 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
9783 if (!nested_cpu_has_ept(vmcs12) ||
9784 !IS_ALIGNED(address, 4096) ||
9785 address >> maxphyaddr)
9786 return -EINVAL;
9787 }
9788
9789 return 0;
9790}
9791
e9ac033e
EK
9792static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9793 struct vmx_msr_entry *e)
9794{
9795 /* x2APIC MSR accesses are not allowed */
8a9781f7 9796 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK
9797 return -EINVAL;
9798 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9799 e->index == MSR_IA32_UCODE_REV)
9800 return -EINVAL;
9801 if (e->reserved != 0)
ff651cb6
WV
9802 return -EINVAL;
9803 return 0;
9804}
9805
e9ac033e
EK
9806static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9807 struct vmx_msr_entry *e)
ff651cb6
WV
9808{
9809 if (e->index == MSR_FS_BASE ||
9810 e->index == MSR_GS_BASE ||
e9ac033e
EK
9811 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9812 nested_vmx_msr_check_common(vcpu, e))
9813 return -EINVAL;
9814 return 0;
9815}
9816
9817static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9818 struct vmx_msr_entry *e)
9819{
9820 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9821 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV
9822 return -EINVAL;
9823 return 0;
9824}
9825
9826/*
9827 * Load guest's/host's msr at nested entry/exit.
9828 * return 0 for success, entry index for failure.
9829 */
9830static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9831{
9832 u32 i;
9833 struct vmx_msr_entry e;
9834 struct msr_data msr;
9835
9836 msr.host_initiated = false;
9837 for (i = 0; i < count; i++) {
54bf36aa
PB
9838 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9839 &e, sizeof(e))) {
bbe41b95 9840 pr_debug_ratelimited(
e9ac033e
EK
9841 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9842 __func__, i, gpa + i * sizeof(e));
ff651cb6 9843 goto fail;
e9ac033e
EK
9844 }
9845 if (nested_vmx_load_msr_check(vcpu, &e)) {
bbe41b95 9846 pr_debug_ratelimited(
e9ac033e
EK
9847 "%s check failed (%u, 0x%x, 0x%x)\n",
9848 __func__, i, e.index, e.reserved);
9849 goto fail;
9850 }
ff651cb6
WV
9851 msr.index = e.index;
9852 msr.data = e.value;
e9ac033e 9853 if (kvm_set_msr(vcpu, &msr)) {
bbe41b95 9854 pr_debug_ratelimited(
e9ac033e
EK
9855 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9856 __func__, i, e.index, e.value);
ff651cb6 9857 goto fail;
e9ac033e 9858 }
ff651cb6
WV
9859 }
9860 return 0;
9861fail:
9862 return i + 1;
9863}
9864
9865static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9866{
9867 u32 i;
9868 struct vmx_msr_entry e;
9869
9870 for (i = 0; i < count; i++) {
609e36d3 9871 struct msr_data msr_info;
54bf36aa
PB
9872 if (kvm_vcpu_read_guest(vcpu,
9873 gpa + i * sizeof(e),
9874 &e, 2 * sizeof(u32))) {
bbe41b95 9875 pr_debug_ratelimited(
e9ac033e
EK
9876 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9877 __func__, i, gpa + i * sizeof(e));
ff651cb6 9878 return -EINVAL;
e9ac033e
EK
9879 }
9880 if (nested_vmx_store_msr_check(vcpu, &e)) {
bbe41b95 9881 pr_debug_ratelimited(
e9ac033e
EK
9882 "%s check failed (%u, 0x%x, 0x%x)\n",
9883 __func__, i, e.index, e.reserved);
ff651cb6 9884 return -EINVAL;
e9ac033e 9885 }
609e36d3
PB
9886 msr_info.host_initiated = false;
9887 msr_info.index = e.index;
9888 if (kvm_get_msr(vcpu, &msr_info)) {
bbe41b95 9889 pr_debug_ratelimited(
e9ac033e
EK
9890 "%s cannot read MSR (%u, 0x%x)\n",
9891 __func__, i, e.index);
9892 return -EINVAL;
9893 }
54bf36aa
PB
9894 if (kvm_vcpu_write_guest(vcpu,
9895 gpa + i * sizeof(e) +
9896 offsetof(struct vmx_msr_entry, value),
9897 &msr_info.data, sizeof(msr_info.data))) {
bbe41b95 9898 pr_debug_ratelimited(
e9ac033e 9899 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9900 __func__, i, e.index, msr_info.data);
e9ac033e
EK
9901 return -EINVAL;
9902 }
ff651cb6
WV
9903 }
9904 return 0;
9905}
9906
1dc35dac
LP
9907static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9908{
9909 unsigned long invalid_mask;
9910
9911 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9912 return (val & invalid_mask) == 0;
9913}
9914
9ed38ffa
LP
9915/*
9916 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9917 * emulating VM entry into a guest with EPT enabled.
9918 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9919 * is assigned to entry_failure_code on failure.
9920 */
9921static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
ca0bde28 9922 u32 *entry_failure_code)
9ed38ffa 9923{
9ed38ffa 9924 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
1dc35dac 9925 if (!nested_cr3_valid(vcpu, cr3)) {
9ed38ffa
LP
9926 *entry_failure_code = ENTRY_FAIL_DEFAULT;
9927 return 1;
9928 }
9929
9930 /*
9931 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9932 * must not be dereferenced.
9933 */
9934 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9935 !nested_ept) {
9936 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9937 *entry_failure_code = ENTRY_FAIL_PDPTE;
9938 return 1;
9939 }
9940 }
9941
9942 vcpu->arch.cr3 = cr3;
9943 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9944 }
9945
9946 kvm_mmu_reset_context(vcpu);
9947 return 0;
9948}
9949
fe3ef05c
NHE
9950/*
9951 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9952 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9953 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE
9954 * guest in a way that will both be appropriate to L1's requests, and our
9955 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9956 * function also has additional necessary side-effects, like setting various
9957 * vcpu->arch fields.
ee146c1c
LP
9958 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9959 * is assigned to entry_failure_code on failure.
fe3ef05c 9960 */
ee146c1c 9961static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
ca0bde28 9962 bool from_vmentry, u32 *entry_failure_code)
fe3ef05c
NHE
9963{
9964 struct vcpu_vmx *vmx = to_vmx(vcpu);
03efce6f 9965 u32 exec_control, vmcs12_exec_ctrl;
fe3ef05c
NHE
9966
9967 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9968 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9969 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9970 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9971 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9972 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9973 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9974 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9975 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9976 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9977 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9978 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9979 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9980 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9981 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9982 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9983 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9984 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9985 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9986 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9987 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9988 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9989 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9990 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9991 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9992 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9993 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9994 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9995 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9996 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9997 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9998 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9999 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10000 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10001 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10002 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10003
cf8b84f4
JM
10004 if (from_vmentry &&
10005 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
2996fca0
JK
10006 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10007 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10008 } else {
10009 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10010 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10011 }
cf8b84f4
JM
10012 if (from_vmentry) {
10013 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10014 vmcs12->vm_entry_intr_info_field);
10015 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10016 vmcs12->vm_entry_exception_error_code);
10017 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10018 vmcs12->vm_entry_instruction_len);
10019 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10020 vmcs12->guest_interruptibility_info);
10021 } else {
10022 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10023 }
fe3ef05c 10024 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 10025 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE
10026 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10027 vmcs12->guest_pending_dbg_exceptions);
10028 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10029 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10030
81dc01f7
WL
10031 if (nested_cpu_has_xsaves(vmcs12))
10032 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE
10033 vmcs_write64(VMCS_LINK_POINTER, -1ull);
10034
f4124500 10035 exec_control = vmcs12->pin_based_vm_exec_control;
9314006d
PB
10036
10037 /* Preemption timer setting is only taken from vmcs01. */
705699a1 10038 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9314006d
PB
10039 exec_control |= vmcs_config.pin_based_exec_ctrl;
10040 if (vmx->hv_deadline_tsc == -1)
10041 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
705699a1 10042
9314006d 10043 /* Posted interrupts setting is only taken from vmcs12. */
705699a1
WV
10044 if (nested_cpu_has_posted_intr(vmcs12)) {
10045 /*
10046 * Note that we use L0's vector here and in
10047 * vmx_deliver_nested_posted_interrupt.
10048 */
10049 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10050 vmx->nested.pi_pending = false;
0bcf261c 10051 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6beb7bd5 10052 } else {
705699a1 10053 exec_control &= ~PIN_BASED_POSTED_INTR;
6beb7bd5 10054 }
705699a1 10055
f4124500 10056 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 10057
f4124500
JK
10058 vmx->nested.preemption_timer_expired = false;
10059 if (nested_cpu_has_preemption_timer(vmcs12))
10060 vmx_start_preemption_timer(vcpu);
0238ea91 10061
fe3ef05c
NHE
10062 /*
10063 * Whether page-faults are trapped is determined by a combination of
10064 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10065 * If enable_ept, L0 doesn't care about page faults and we should
10066 * set all of these to L1's desires. However, if !enable_ept, L0 does
10067 * care about (at least some) page faults, and because it is not easy
10068 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10069 * to exit on each and every L2 page fault. This is done by setting
10070 * MASK=MATCH=0 and (see below) EB.PF=1.
10071 * Note that below we don't need special code to set EB.PF beyond the
10072 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10073 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10074 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10075 *
10076 * A problem with this approach (when !enable_ept) is that L1 may be
10077 * injected with more page faults than it asked for. This could have
10078 * caused problems, but in practice existing hypervisors don't care.
10079 * To fix this, we will need to emulate the PFEC checking (on the L1
10080 * page tables), using walk_addr(), when injecting PFs to L1.
10081 */
10082 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10083 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10084 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10085 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10086
10087 if (cpu_has_secondary_exec_ctrls()) {
f4124500 10088 exec_control = vmx_secondary_exec_control(vmx);
e2821620 10089
fe3ef05c 10090 /* Take the following fields only from vmcs12 */
696dfd95 10091 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 10092 SECONDARY_EXEC_RDTSCP |
696dfd95 10093 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
dfa169bb 10094 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c 10095 if (nested_cpu_has(vmcs12,
03efce6f
BD
10096 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10097 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10098 ~SECONDARY_EXEC_ENABLE_PML;
10099 exec_control |= vmcs12_exec_ctrl;
10100 }
fe3ef05c 10101
608406e2
WV
10102 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10103 vmcs_write64(EOI_EXIT_BITMAP0,
10104 vmcs12->eoi_exit_bitmap0);
10105 vmcs_write64(EOI_EXIT_BITMAP1,
10106 vmcs12->eoi_exit_bitmap1);
10107 vmcs_write64(EOI_EXIT_BITMAP2,
10108 vmcs12->eoi_exit_bitmap2);
10109 vmcs_write64(EOI_EXIT_BITMAP3,
10110 vmcs12->eoi_exit_bitmap3);
10111 vmcs_write16(GUEST_INTR_STATUS,
10112 vmcs12->guest_intr_status);
10113 }
10114
6beb7bd5
JM
10115 /*
10116 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10117 * nested_get_vmcs12_pages will either fix it up or
10118 * remove the VM execution control.
10119 */
10120 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10121 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10122
fe3ef05c
NHE
10123 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10124 }
10125
10126
10127 /*
10128 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10129 * Some constant fields are set here by vmx_set_constant_host_state().
10130 * Other fields are different per CPU, and will be set later when
10131 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10132 */
a547c6db 10133 vmx_set_constant_host_state(vmx);
fe3ef05c 10134
83bafef1
JM
10135 /*
10136 * Set the MSR load/store lists to match L0's settings.
10137 */
10138 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10139 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10140 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10141 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10142 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10143
fe3ef05c
NHE
10144 /*
10145 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10146 * entry, but only if the current (host) sp changed from the value
10147 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10148 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10149 * here we just force the write to happen on entry.
10150 */
10151 vmx->host_rsp = 0;
10152
10153 exec_control = vmx_exec_control(vmx); /* L0's desires */
10154 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10155 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10156 exec_control &= ~CPU_BASED_TPR_SHADOW;
10157 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d 10158
6beb7bd5
JM
10159 /*
10160 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10161 * nested_get_vmcs12_pages can't fix it up, the illegal value
10162 * will result in a VM entry failure.
10163 */
a7c0b07d 10164 if (exec_control & CPU_BASED_TPR_SHADOW) {
6beb7bd5 10165 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
a7c0b07d
WL
10166 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10167 }
10168
fe3ef05c 10169 /*
3af18d9c 10170 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE
10171 * Rather, exit every time.
10172 */
fe3ef05c
NHE
10173 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10174 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10175
10176 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10177
10178 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10179 * bitwise-or of what L1 wants to trap for L2, and what we want to
10180 * trap. Note that CR0.TS also needs updating - we do this later.
10181 */
10182 update_exception_bitmap(vcpu);
10183 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10184 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10185
8049d651
NHE
10186 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10187 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10188 * bits are further modified by vmx_set_efer() below.
10189 */
f4124500 10190 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE
10191
10192 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10193 * emulated by vmx_set_efer(), below.
10194 */
2961e876 10195 vm_entry_controls_init(vmx,
8049d651
NHE
10196 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10197 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE
10198 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10199
cf8b84f4
JM
10200 if (from_vmentry &&
10201 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
fe3ef05c 10202 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02 10203 vcpu->arch.pat = vmcs12->guest_ia32_pat;
cf8b84f4 10204 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 10205 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
cf8b84f4 10206 }
fe3ef05c
NHE
10207
10208 set_cr4_guest_host_mask(vmx);
10209
cf8b84f4
JM
10210 if (from_vmentry &&
10211 vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
36be0b9d
PB
10212 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10213
27fc51b2
NHE
10214 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10215 vmcs_write64(TSC_OFFSET,
ea26e4ec 10216 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
27fc51b2 10217 else
ea26e4ec 10218 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
c95ba92a
PF
10219 if (kvm_has_tsc_control)
10220 decache_tsc_multiplier(vmx);
fe3ef05c
NHE
10221
10222 if (enable_vpid) {
10223 /*
5c614b35
WL
10224 * There is no direct mapping between vpid02 and vpid12, the
10225 * vpid02 is per-vCPU for L0 and reused while the value of
10226 * vpid12 is changed w/ one invvpid during nested vmentry.
10227 * The vpid12 is allocated by L1 for L2, so it will not
10228 * influence global bitmap(for vpid01 and vpid02 allocation)
10229 * even if spawn a lot of nested vCPUs.
fe3ef05c 10230 */
5c614b35
WL
10231 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10232 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10233 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10234 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10235 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10236 }
10237 } else {
10238 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10239 vmx_flush_tlb(vcpu);
10240 }
10241
fe3ef05c
NHE
10242 }
10243
1fb883bb
LP
10244 if (enable_pml) {
10245 /*
10246 * Conceptually we want to copy the PML address and index from
10247 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10248 * since we always flush the log on each vmexit, this happens
10249 * to be equivalent to simply resetting the fields in vmcs02.
10250 */
10251 ASSERT(vmx->pml_pg);
10252 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10253 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10254 }
10255
155a97a3 10256 if (nested_cpu_has_ept(vmcs12)) {
ae1e2d10
PB
10257 if (nested_ept_init_mmu_context(vcpu)) {
10258 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10259 return 1;
10260 }
fb6c8198
JM
10261 } else if (nested_cpu_has2(vmcs12,
10262 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10263 vmx_flush_tlb_ept_only(vcpu);
155a97a3
NHE
10264 }
10265
fe3ef05c 10266 /*
bd7e5b08
PB
10267 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10268 * bits which we consider mandatory enabled.
fe3ef05c
NHE
10269 * The CR0_READ_SHADOW is what L2 should have expected to read given
10270 * the specifications by L1; It's not enough to take
10271 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10272 * have more bits than L1 expected.
10273 */
10274 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10275 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10276
10277 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10278 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10279
cf8b84f4
JM
10280 if (from_vmentry &&
10281 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
5a6a9748
DM
10282 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10283 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10284 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10285 else
10286 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10287 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10288 vmx_set_efer(vcpu, vcpu->arch.efer);
10289
9ed38ffa 10290 /* Shadow page tables on either EPT or shadow page tables. */
7ad658b6 10291 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
9ed38ffa
LP
10292 entry_failure_code))
10293 return 1;
7ca29de2 10294
feaf0c7d
GN
10295 if (!enable_ept)
10296 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10297
3633cfc3
NHE
10298 /*
10299 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10300 */
10301 if (enable_ept) {
10302 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10303 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10304 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10305 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10306 }
10307
fe3ef05c
NHE
10308 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10309 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
ee146c1c 10310 return 0;
fe3ef05c
NHE
10311}
10312
ca0bde28 10313static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
cd232ad0 10314{
cd232ad0 10315 struct vcpu_vmx *vmx = to_vmx(vcpu);
7c177938 10316
6dfacadd 10317 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
ca0bde28
JM
10318 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10319 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
26539bd0 10320
56a20510
JM
10321 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10322 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10323
ca0bde28
JM
10324 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10325 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
7c177938 10326
ca0bde28
JM
10327 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10328 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
f2b93280 10329
ca0bde28
JM
10330 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10331 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
e9ac033e 10332
c5f983f6
BD
10333 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10334 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10335
7c177938 10336 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
0115f9cb 10337 vmx->nested.nested_vmx_procbased_ctls_low,
b9c237bb 10338 vmx->nested.nested_vmx_procbased_ctls_high) ||
2e5b0bd9
JM
10339 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10340 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10341 vmx->nested.nested_vmx_secondary_ctls_low,
10342 vmx->nested.nested_vmx_secondary_ctls_high)) ||
7c177938 10343 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV
10344 vmx->nested.nested_vmx_pinbased_ctls_low,
10345 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 10346 !vmx_control_verify(vmcs12->vm_exit_controls,
0115f9cb 10347 vmx->nested.nested_vmx_exit_ctls_low,
b9c237bb 10348 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 10349 !vmx_control_verify(vmcs12->vm_entry_controls,
0115f9cb 10350 vmx->nested.nested_vmx_entry_ctls_low,
b9c237bb 10351 vmx->nested.nested_vmx_entry_ctls_high))
ca0bde28 10352 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
7c177938 10353
c7c2c709
JM
10354 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10355 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10356
3899152c 10357 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
1dc35dac 10358 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
ca0bde28
JM
10359 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10360 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10361
10362 return 0;
10363}
10364
10365static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10366 u32 *exit_qual)
10367{
10368 bool ia32e;
10369
10370 *exit_qual = ENTRY_FAIL_DEFAULT;
7c177938 10371
3899152c 10372 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
ca0bde28 10373 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
b428018a 10374 return 1;
ca0bde28
JM
10375
10376 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10377 vmcs12->vmcs_link_pointer != -1ull) {
10378 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
b428018a 10379 return 1;
7c177938
NHE
10380 }
10381
384bb783 10382 /*
cb0c8cda 10383 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK
10384 * are performed on the field for the IA32_EFER MSR:
10385 * - Bits reserved in the IA32_EFER MSR must be 0.
10386 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10387 * the IA-32e mode guest VM-exit control. It must also be identical
10388 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10389 * CR0.PG) is 1.
10390 */
ca0bde28
JM
10391 if (to_vmx(vcpu)->nested.nested_run_pending &&
10392 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
384bb783
JK
10393 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10394 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10395 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10396 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
ca0bde28 10397 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
b428018a 10398 return 1;
384bb783
JK
10399 }
10400
10401 /*
10402 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10403 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10404 * the values of the LMA and LME bits in the field must each be that of
10405 * the host address-space size VM-exit control.
10406 */
10407 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10408 ia32e = (vmcs12->vm_exit_controls &
10409 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10410 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10411 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
ca0bde28 10412 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
b428018a 10413 return 1;
ca0bde28
JM
10414 }
10415
10416 return 0;
10417}
10418
858e25c0
JM
10419static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10420{
10421 struct vcpu_vmx *vmx = to_vmx(vcpu);
10422 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10423 struct loaded_vmcs *vmcs02;
858e25c0
JM
10424 u32 msr_entry_idx;
10425 u32 exit_qual;
10426
10427 vmcs02 = nested_get_current_vmcs02(vmx);
10428 if (!vmcs02)
10429 return -ENOMEM;
10430
10431 enter_guest_mode(vcpu);
10432
10433 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10434 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10435
1279a6b1 10436 vmx_switch_vmcs(vcpu, vmcs02);
858e25c0
JM
10437 vmx_segment_cache_clear(vmx);
10438
10439 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10440 leave_guest_mode(vcpu);
1279a6b1 10441 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
858e25c0
JM
10442 nested_vmx_entry_failure(vcpu, vmcs12,
10443 EXIT_REASON_INVALID_STATE, exit_qual);
10444 return 1;
10445 }
10446
10447 nested_get_vmcs12_pages(vcpu, vmcs12);
10448
10449 msr_entry_idx = nested_vmx_load_msr(vcpu,
10450 vmcs12->vm_entry_msr_load_addr,
10451 vmcs12->vm_entry_msr_load_count);
10452 if (msr_entry_idx) {
10453 leave_guest_mode(vcpu);
1279a6b1 10454 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
858e25c0
JM
10455 nested_vmx_entry_failure(vcpu, vmcs12,
10456 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10457 return 1;
10458 }
10459
858e25c0
JM
10460 /*
10461 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10462 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10463 * returned as far as L1 is concerned. It will only return (and set
10464 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10465 */
10466 return 0;
10467}
10468
ca0bde28
JM
10469/*
10470 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10471 * for running an L2 nested guest.
10472 */
10473static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10474{
10475 struct vmcs12 *vmcs12;
10476 struct vcpu_vmx *vmx = to_vmx(vcpu);
ca0bde28
JM
10477 u32 exit_qual;
10478 int ret;
10479
10480 if (!nested_vmx_check_permission(vcpu))
10481 return 1;
10482
10483 if (!nested_vmx_check_vmcs12(vcpu))
10484 goto out;
10485
10486 vmcs12 = get_vmcs12(vcpu);
10487
10488 if (enable_shadow_vmcs)
10489 copy_shadow_to_vmcs12(vmx);
10490
10491 /*
10492 * The nested entry process starts with enforcing various prerequisites
10493 * on vmcs12 as required by the Intel SDM, and act appropriately when
10494 * they fail: As the SDM explains, some conditions should cause the
10495 * instruction to fail, while others will cause the instruction to seem
10496 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10497 * To speed up the normal (success) code path, we should avoid checking
10498 * for misconfigurations which will anyway be caught by the processor
10499 * when using the merged vmcs02.
10500 */
10501 if (vmcs12->launch_state == launch) {
10502 nested_vmx_failValid(vcpu,
10503 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10504 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10505 goto out;
10506 }
10507
10508 ret = check_vmentry_prereqs(vcpu, vmcs12);
10509 if (ret) {
10510 nested_vmx_failValid(vcpu, ret);
10511 goto out;
10512 }
10513
10514 /*
10515 * After this point, the trap flag no longer triggers a singlestep trap
10516 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10517 * This is not 100% correct; for performance reasons, we delegate most
10518 * of the checks on host state to the processor. If those fail,
10519 * the singlestep trap is missed.
10520 */
10521 skip_emulated_instruction(vcpu);
10522
10523 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10524 if (ret) {
10525 nested_vmx_entry_failure(vcpu, vmcs12,
10526 EXIT_REASON_INVALID_STATE, exit_qual);
10527 return 1;
384bb783
JK
10528 }
10529
7c177938
NHE
10530 /*
10531 * We're finally done with prerequisite checking, and can start with
10532 * the nested entry.
10533 */
10534
858e25c0
JM
10535 ret = enter_vmx_non_root_mode(vcpu, true);
10536 if (ret)
10537 return ret;
ff651cb6 10538
6dfacadd 10539 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 10540 return kvm_vcpu_halt(vcpu);
6dfacadd 10541
7af40ad3
JK
10542 vmx->nested.nested_run_pending = 1;
10543
cd232ad0 10544 return 1;
eb277562
KH
10545
10546out:
6affcbed 10547 return kvm_skip_emulated_instruction(vcpu);
cd232ad0
NHE
10548}
10549
4704d0be
NHE
10550/*
10551 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10552 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10553 * This function returns the new value we should put in vmcs12.guest_cr0.
10554 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10555 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10556 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10557 * didn't trap the bit, because if L1 did, so would L0).
10558 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10559 * been modified by L2, and L1 knows it. So just leave the old value of
10560 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10561 * isn't relevant, because if L0 traps this bit it can set it to anything.
10562 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10563 * changed these bits, and therefore they need to be updated, but L0
10564 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10565 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10566 */
10567static inline unsigned long
10568vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10569{
10570 return
10571 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10572 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10573 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10574 vcpu->arch.cr0_guest_owned_bits));
10575}
10576
10577static inline unsigned long
10578vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10579{
10580 return
10581 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10582 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10583 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10584 vcpu->arch.cr4_guest_owned_bits));
10585}
10586
5f3d5799
JK
10587static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10588 struct vmcs12 *vmcs12)
10589{
10590 u32 idt_vectoring;
10591 unsigned int nr;
10592
851eb667 10593 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK
10594 nr = vcpu->arch.exception.nr;
10595 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10596
10597 if (kvm_exception_is_soft(nr)) {
10598 vmcs12->vm_exit_instruction_len =
10599 vcpu->arch.event_exit_inst_len;
10600 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10601 } else
10602 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10603
10604 if (vcpu->arch.exception.has_error_code) {
10605 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10606 vmcs12->idt_vectoring_error_code =
10607 vcpu->arch.exception.error_code;
10608 }
10609
10610 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 10611 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK
10612 vmcs12->idt_vectoring_info_field =
10613 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10614 } else if (vcpu->arch.interrupt.pending) {
10615 nr = vcpu->arch.interrupt.nr;
10616 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10617
10618 if (vcpu->arch.interrupt.soft) {
10619 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10620 vmcs12->vm_entry_instruction_len =
10621 vcpu->arch.event_exit_inst_len;
10622 } else
10623 idt_vectoring |= INTR_TYPE_EXT_INTR;
10624
10625 vmcs12->idt_vectoring_info_field = idt_vectoring;
10626 }
10627}
10628
b6b8a145
JK
10629static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10630{
10631 struct vcpu_vmx *vmx = to_vmx(vcpu);
10632
acc9ab60
WL
10633 if (vcpu->arch.exception.pending ||
10634 vcpu->arch.nmi_injected ||
10635 vcpu->arch.interrupt.pending)
10636 return -EBUSY;
10637
f4124500
JK
10638 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10639 vmx->nested.preemption_timer_expired) {
10640 if (vmx->nested.nested_run_pending)
10641 return -EBUSY;
10642 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10643 return 0;
10644 }
10645
b6b8a145 10646 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
acc9ab60 10647 if (vmx->nested.nested_run_pending)
b6b8a145
JK
10648 return -EBUSY;
10649 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10650 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10651 INTR_INFO_VALID_MASK, 0);
10652 /*
10653 * The NMI-triggered VM exit counts as injection:
10654 * clear this one and block further NMIs.
10655 */
10656 vcpu->arch.nmi_pending = 0;
10657 vmx_set_nmi_mask(vcpu, true);
10658 return 0;
10659 }
10660
10661 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10662 nested_exit_on_intr(vcpu)) {
10663 if (vmx->nested.nested_run_pending)
10664 return -EBUSY;
10665 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 10666 return 0;
b6b8a145
JK
10667 }
10668
6342c50a
DH
10669 vmx_complete_nested_posted_interrupt(vcpu);
10670 return 0;
b6b8a145
JK
10671}
10672
f4124500
JK
10673static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10674{
10675 ktime_t remaining =
10676 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10677 u64 value;
10678
10679 if (ktime_to_ns(remaining) <= 0)
10680 return 0;
10681
10682 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10683 do_div(value, 1000000);
10684 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10685}
10686
4704d0be 10687/*
cf8b84f4
JM
10688 * Update the guest state fields of vmcs12 to reflect changes that
10689 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10690 * VM-entry controls is also updated, since this is really a guest
10691 * state bit.)
4704d0be 10692 */
cf8b84f4 10693static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be 10694{
4704d0be
NHE
10695 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10696 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10697
4704d0be
NHE
10698 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10699 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10700 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10701
10702 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10703 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10704 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10705 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10706 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10707 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10708 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10709 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10710 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10711 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10712 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10713 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10714 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10715 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10716 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10717 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10718 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10719 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10720 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10721 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10722 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10723 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10724 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10725 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10726 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10727 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10728 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10729 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10730 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10731 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10732 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10733 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10734 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10735 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10736 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10737 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10738
4704d0be
NHE
10739 vmcs12->guest_interruptibility_info =
10740 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10741 vmcs12->guest_pending_dbg_exceptions =
10742 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK
10743 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10744 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10745 else
10746 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 10747
f4124500
JK
10748 if (nested_cpu_has_preemption_timer(vmcs12)) {
10749 if (vmcs12->vm_exit_controls &
10750 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10751 vmcs12->vmx_preemption_timer_value =
10752 vmx_get_preemption_timer_value(vcpu);
10753 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10754 }
7854cbca 10755
3633cfc3
NHE
10756 /*
10757 * In some cases (usually, nested EPT), L2 is allowed to change its
10758 * own CR3 without exiting. If it has changed it, we must keep it.
10759 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10760 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10761 *
10762 * Additionally, restore L2's PDPTR to vmcs12.
10763 */
10764 if (enable_ept) {
f3531054 10765 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
3633cfc3
NHE
10766 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10767 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10768 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10769 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10770 }
10771
d281e13b 10772 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
119a9c01 10773
608406e2
WV
10774 if (nested_cpu_has_vid(vmcs12))
10775 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10776
c18911a2
JK
10777 vmcs12->vm_entry_controls =
10778 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 10779 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 10780
2996fca0
JK
10781 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10782 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10783 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10784 }
10785
4704d0be
NHE
10786 /* TODO: These cannot have changed unless we have MSR bitmaps and
10787 * the relevant bit asks not to trap the change */
b8c07d55 10788 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 10789 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK
10790 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10791 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE
10792 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10793 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10794 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
a87036ad 10795 if (kvm_mpx_supported())
36be0b9d 10796 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
cf8b84f4
JM
10797}
10798
10799/*
10800 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10801 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10802 * and this function updates it to reflect the changes to the guest state while
10803 * L2 was running (and perhaps made some exits which were handled directly by L0
10804 * without going back to L1), and to reflect the exit reason.
10805 * Note that we do not have to copy here all VMCS fields, just those that
10806 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10807 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10808 * which already writes to vmcs12 directly.
10809 */
10810static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10811 u32 exit_reason, u32 exit_intr_info,
10812 unsigned long exit_qualification)
10813{
10814 /* update guest state fields: */
10815 sync_vmcs12(vcpu, vmcs12);
4704d0be
NHE
10816
10817 /* update exit information fields: */
10818
533558bc
JK
10819 vmcs12->vm_exit_reason = exit_reason;
10820 vmcs12->exit_qualification = exit_qualification;
4704d0be 10821
533558bc 10822 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK
10823 if ((vmcs12->vm_exit_intr_info &
10824 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10825 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10826 vmcs12->vm_exit_intr_error_code =
10827 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 10828 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE
10829 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10830 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10831
5f3d5799 10832 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7cdc2d62
JM
10833 vmcs12->launch_state = 1;
10834
5f3d5799
JK
10835 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10836 * instead of reading the real value. */
4704d0be 10837 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK
10838
10839 /*
10840 * Transfer the event that L0 or L1 may wanted to inject into
10841 * L2 to IDT_VECTORING_INFO_FIELD.
10842 */
10843 vmcs12_save_pending_event(vcpu, vmcs12);
10844 }
10845
10846 /*
10847 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10848 * preserved above and would only end up incorrectly in L1.
10849 */
10850 vcpu->arch.nmi_injected = false;
10851 kvm_clear_exception_queue(vcpu);
10852 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE
10853}
10854
10855/*
10856 * A part of what we need to when the nested L2 guest exits and we want to
10857 * run its L1 parent, is to reset L1's guest state to the host state specified
10858 * in vmcs12.
10859 * This function is to be called not only on normal nested exit, but also on
10860 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10861 * Failures During or After Loading Guest State").
10862 * This function should be called when the active VMCS is L1's (vmcs01).
10863 */
733568f9
JK
10864static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10865 struct vmcs12 *vmcs12)
4704d0be 10866{
21feb4eb 10867 struct kvm_segment seg;
ca0bde28 10868 u32 entry_failure_code;
21feb4eb 10869
4704d0be
NHE
10870 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10871 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10872 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE
10873 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10874 else
10875 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10876 vmx_set_efer(vcpu, vcpu->arch.efer);
10877
10878 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10879 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10880 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE
10881 /*
10882 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
bd7e5b08
PB
10883 * actually changed, because vmx_set_cr0 refers to efer set above.
10884 *
10885 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10886 * (KVM doesn't change it);
4704d0be 10887 */
bd7e5b08 10888 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
9e3e4dbf 10889 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be 10890
bd7e5b08 10891 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
4704d0be
NHE
10892 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10893 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10894
29bf08f1 10895 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10896
1dc35dac
LP
10897 /*
10898 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10899 * couldn't have changed.
10900 */
10901 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10902 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
4704d0be 10903
feaf0c7d
GN
10904 if (!enable_ept)
10905 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10906
4704d0be
NHE
10907 if (enable_vpid) {
10908 /*
10909 * Trivially support vpid by letting L2s share their parent
10910 * L1's vpid. TODO: move to a more elaborate solution, giving
10911 * each L2 its own vpid and exposing the vpid feature to L1.
10912 */
10913 vmx_flush_tlb(vcpu);
10914 }
10915
10916
10917 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10918 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10919 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10920 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10921 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10922
36be0b9d
PB
10923 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10924 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10925 vmcs_write64(GUEST_BNDCFGS, 0);
10926
44811c02 10927 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10928 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK
10929 vcpu->arch.pat = vmcs12->host_ia32_pat;
10930 }
4704d0be
NHE
10931 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10932 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10933 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10934
21feb4eb
ACL
10935 /* Set L1 segment info according to Intel SDM
10936 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10937 seg = (struct kvm_segment) {
10938 .base = 0,
10939 .limit = 0xFFFFFFFF,
10940 .selector = vmcs12->host_cs_selector,
10941 .type = 11,
10942 .present = 1,
10943 .s = 1,
10944 .g = 1
10945 };
10946 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10947 seg.l = 1;
10948 else
10949 seg.db = 1;
10950 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10951 seg = (struct kvm_segment) {
10952 .base = 0,
10953 .limit = 0xFFFFFFFF,
10954 .type = 3,
10955 .present = 1,
10956 .s = 1,
10957 .db = 1,
10958 .g = 1
10959 };
10960 seg.selector = vmcs12->host_ds_selector;
10961 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10962 seg.selector = vmcs12->host_es_selector;
10963 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10964 seg.selector = vmcs12->host_ss_selector;
10965 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10966 seg.selector = vmcs12->host_fs_selector;
10967 seg.base = vmcs12->host_fs_base;
10968 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10969 seg.selector = vmcs12->host_gs_selector;
10970 seg.base = vmcs12->host_gs_base;
10971 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10972 seg = (struct kvm_segment) {
205befd9 10973 .base = vmcs12->host_tr_base,
21feb4eb
ACL
10974 .limit = 0x67,
10975 .selector = vmcs12->host_tr_selector,
10976 .type = 11,
10977 .present = 1
10978 };
10979 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10980
503cd0c5
JK
10981 kvm_set_dr(vcpu, 7, 0x400);
10982 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 10983
3af18d9c
WV
10984 if (cpu_has_vmx_msr_bitmap())
10985 vmx_set_msr_bitmap(vcpu);
10986
ff651cb6
WV
10987 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10988 vmcs12->vm_exit_msr_load_count))
10989 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE
10990}
10991
10992/*
10993 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10994 * and modify vmcs12 to make it see what it would expect to see there if
10995 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10996 */
533558bc
JK
10997static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10998 u32 exit_intr_info,
10999 unsigned long exit_qualification)
4704d0be
NHE
11000{
11001 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 11002 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
cf3215d9 11003 u32 vm_inst_error = 0;
4704d0be 11004
5f3d5799
JK
11005 /* trying to cancel vmlaunch/vmresume is a bug */
11006 WARN_ON_ONCE(vmx->nested.nested_run_pending);
11007
4704d0be 11008 leave_guest_mode(vcpu);
533558bc
JK
11009 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11010 exit_qualification);
4704d0be 11011
ff651cb6
WV
11012 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11013 vmcs12->vm_exit_msr_store_count))
11014 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11015
cf3215d9
JM
11016 if (unlikely(vmx->fail))
11017 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11018
1279a6b1 11019 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
f3380ca5 11020
77b0f5d6
BD
11021 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11022 && nested_exit_intr_ack_set(vcpu)) {
11023 int irq = kvm_cpu_get_interrupt(vcpu);
11024 WARN_ON(irq < 0);
11025 vmcs12->vm_exit_intr_info = irq |
11026 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11027 }
11028
542060ea
JK
11029 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11030 vmcs12->exit_qualification,
11031 vmcs12->idt_vectoring_info_field,
11032 vmcs12->vm_exit_intr_info,
11033 vmcs12->vm_exit_intr_error_code,
11034 KVM_ISA_VMX);
4704d0be 11035
8391ce44
PB
11036 vm_entry_controls_reset_shadow(vmx);
11037 vm_exit_controls_reset_shadow(vmx);
36c3cc42
JK
11038 vmx_segment_cache_clear(vmx);
11039
4704d0be
NHE
11040 /* if no vmcs02 cache requested, remove the one we used */
11041 if (VMCS02_POOL_SIZE == 0)
11042 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11043
11044 load_vmcs12_host_state(vcpu, vmcs12);
11045
9314006d 11046 /* Update any VMCS fields that might have changed while L2 ran */
83bafef1
JM
11047 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11048 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
ea26e4ec 11049 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
9314006d
PB
11050 if (vmx->hv_deadline_tsc == -1)
11051 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11052 PIN_BASED_VMX_PREEMPTION_TIMER);
11053 else
11054 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11055 PIN_BASED_VMX_PREEMPTION_TIMER);
c95ba92a
PF
11056 if (kvm_has_tsc_control)
11057 decache_tsc_multiplier(vmx);
4704d0be 11058
dccbfcf5
RK
11059 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11060 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11061 vmx_set_virtual_x2apic_mode(vcpu,
11062 vcpu->arch.apic_base & X2APIC_ENABLE);
fb6c8198
JM
11063 } else if (!nested_cpu_has_ept(vmcs12) &&
11064 nested_cpu_has2(vmcs12,
11065 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11066 vmx_flush_tlb_ept_only(vcpu);
dccbfcf5 11067 }
4704d0be
NHE
11068
11069 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11070 vmx->host_rsp = 0;
11071
11072 /* Unpin physical memory we referred to in vmcs02 */
11073 if (vmx->nested.apic_access_page) {
11074 nested_release_page(vmx->nested.apic_access_page);
48d89b92 11075 vmx->nested.apic_access_page = NULL;
4704d0be 11076 }
a7c0b07d
WL
11077 if (vmx->nested.virtual_apic_page) {
11078 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 11079 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 11080 }
705699a1
WV
11081 if (vmx->nested.pi_desc_page) {
11082 kunmap(vmx->nested.pi_desc_page);
11083 nested_release_page(vmx->nested.pi_desc_page);
11084 vmx->nested.pi_desc_page = NULL;
11085 vmx->nested.pi_desc = NULL;
11086 }
4704d0be 11087
38b99173
TC
11088 /*
11089 * We are now running in L2, mmu_notifier will force to reload the
11090 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11091 */
c83b6d15 11092 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
38b99173 11093
4704d0be
NHE
11094 /*
11095 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11096 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11097 * success or failure flag accordingly.
11098 */
11099 if (unlikely(vmx->fail)) {
11100 vmx->fail = 0;
cf3215d9 11101 nested_vmx_failValid(vcpu, vm_inst_error);
4704d0be
NHE
11102 } else
11103 nested_vmx_succeed(vcpu);
012f83cb
AG
11104 if (enable_shadow_vmcs)
11105 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK
11106
11107 /* in case we halted in L2 */
11108 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE
11109}
11110
42124925
JK
11111/*
11112 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11113 */
11114static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11115{
2f707d97
WL
11116 if (is_guest_mode(vcpu)) {
11117 to_vmx(vcpu)->nested.nested_run_pending = 0;
533558bc 11118 nested_vmx_vmexit(vcpu, -1, 0, 0);
2f707d97 11119 }
42124925
JK
11120 free_nested(to_vmx(vcpu));
11121}
11122
7c177938
NHE
11123/*
11124 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11125 * 23.7 "VM-entry failures during or after loading guest state" (this also
11126 * lists the acceptable exit-reason and exit-qualification parameters).
11127 * It should only be called before L2 actually succeeded to run, and when
11128 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11129 */
11130static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11131 struct vmcs12 *vmcs12,
11132 u32 reason, unsigned long qualification)
11133{
11134 load_vmcs12_host_state(vcpu, vmcs12);
11135 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11136 vmcs12->exit_qualification = qualification;
11137 nested_vmx_succeed(vcpu);
012f83cb
AG
11138 if (enable_shadow_vmcs)
11139 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE
11140}
11141
8a76d7f2
JR
11142static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11143 struct x86_instruction_info *info,
11144 enum x86_intercept_stage stage)
11145{
11146 return X86EMUL_CONTINUE;
11147}
11148
64672c95
YJ
11149#ifdef CONFIG_X86_64
11150/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11151static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11152 u64 divisor, u64 *result)
11153{
11154 u64 low = a << shift, high = a >> (64 - shift);
11155
11156 /* To avoid the overflow on divq */
11157 if (high >= divisor)
11158 return 1;
11159
11160 /* Low hold the result, high hold rem which is discarded */
11161 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11162 "rm" (divisor), "0" (low), "1" (high));
11163 *result = low;
11164
11165 return 0;
11166}
11167
11168static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11169{
11170 struct vcpu_vmx *vmx = to_vmx(vcpu);
9175d2e9
PB
11171 u64 tscl = rdtsc();
11172 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11173 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
64672c95
YJ
11174
11175 /* Convert to host delta tsc if tsc scaling is enabled */
11176 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11177 u64_shl_div_u64(delta_tsc,
11178 kvm_tsc_scaling_ratio_frac_bits,
11179 vcpu->arch.tsc_scaling_ratio,
11180 &delta_tsc))
11181 return -ERANGE;
11182
11183 /*
11184 * If the delta tsc can't fit in the 32 bit after the multi shift,
11185 * we can't use the preemption timer.
11186 * It's possible that it fits on later vmentries, but checking
11187 * on every vmentry is costly so we just use an hrtimer.
11188 */
11189 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11190 return -ERANGE;
11191
11192 vmx->hv_deadline_tsc = tscl + delta_tsc;
11193 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11194 PIN_BASED_VMX_PREEMPTION_TIMER);
c8533544
WL
11195
11196 return delta_tsc == 0;
64672c95
YJ
11197}
11198
11199static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11200{
11201 struct vcpu_vmx *vmx = to_vmx(vcpu);
11202 vmx->hv_deadline_tsc = -1;
11203 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11204 PIN_BASED_VMX_PREEMPTION_TIMER);
11205}
11206#endif
11207
48d89b92 11208static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 11209{
b4a2d31d
RK
11210 if (ple_gap)
11211 shrink_ple_window(vcpu);
ae97a3b8
RK
11212}
11213
843e4330
KH
11214static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11215 struct kvm_memory_slot *slot)
11216{
11217 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11218 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11219}
11220
11221static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11222 struct kvm_memory_slot *slot)
11223{
11224 kvm_mmu_slot_set_dirty(kvm, slot);
11225}
11226
11227static void vmx_flush_log_dirty(struct kvm *kvm)
11228{
11229 kvm_flush_pml_buffers(kvm);
11230}
11231
c5f983f6
BD
11232static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11233{
11234 struct vmcs12 *vmcs12;
11235 struct vcpu_vmx *vmx = to_vmx(vcpu);
11236 gpa_t gpa;
11237 struct page *page = NULL;
11238 u64 *pml_address;
11239
11240 if (is_guest_mode(vcpu)) {
11241 WARN_ON_ONCE(vmx->nested.pml_full);
11242
11243 /*
11244 * Check if PML is enabled for the nested guest.
11245 * Whether eptp bit 6 is set is already checked
11246 * as part of A/D emulation.
11247 */
11248 vmcs12 = get_vmcs12(vcpu);
11249 if (!nested_cpu_has_pml(vmcs12))
11250 return 0;
11251
4769886b 11252 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD
11253 vmx->nested.pml_full = true;
11254 return 1;
11255 }
11256
11257 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11258
11259 page = nested_get_page(vcpu, vmcs12->pml_address);
11260 if (!page)
11261 return 0;
11262
11263 pml_address = kmap(page);
11264 pml_address[vmcs12->guest_pml_index--] = gpa;
11265 kunmap(page);
11266 nested_release_page_clean(page);
11267 }
11268
11269 return 0;
11270}
11271
843e4330
KH
11272static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11273 struct kvm_memory_slot *memslot,
11274 gfn_t offset, unsigned long mask)
11275{
11276 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11277}
11278
bf9f6ac8
FW
11279/*
11280 * This routine does the following things for vCPU which is going
11281 * to be blocked if VT-d PI is enabled.
11282 * - Store the vCPU to the wakeup list, so when interrupts happen
11283 * we can find the right vCPU to wake up.
11284 * - Change the Posted-interrupt descriptor as below:
11285 * 'NDST' <-- vcpu->pre_pcpu
11286 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11287 * - If 'ON' is set during this process, which means at least one
11288 * interrupt is posted for this vCPU, we cannot block it, in
11289 * this case, return 1, otherwise, return 0.
11290 *
11291 */
bc22512b 11292static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8
FW
11293{
11294 unsigned long flags;
11295 unsigned int dest;
11296 struct pi_desc old, new;
11297 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11298
11299 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
11300 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11301 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW
11302 return 0;
11303
11304 vcpu->pre_pcpu = vcpu->cpu;
11305 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11306 vcpu->pre_pcpu), flags);
11307 list_add_tail(&vcpu->blocked_vcpu_list,
11308 &per_cpu(blocked_vcpu_on_cpu,
11309 vcpu->pre_pcpu));
11310 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11311 vcpu->pre_pcpu), flags);
11312
11313 do {
11314 old.control = new.control = pi_desc->control;
11315
11316 /*
11317 * We should not block the vCPU if
11318 * an interrupt is posted for it.
11319 */
11320 if (pi_test_on(pi_desc) == 1) {
11321 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11322 vcpu->pre_pcpu), flags);
11323 list_del(&vcpu->blocked_vcpu_list);
11324 spin_unlock_irqrestore(
11325 &per_cpu(blocked_vcpu_on_cpu_lock,
11326 vcpu->pre_pcpu), flags);
11327 vcpu->pre_pcpu = -1;
11328
11329 return 1;
11330 }
11331
11332 WARN((pi_desc->sn == 1),
11333 "Warning: SN field of posted-interrupts "
11334 "is set before blocking\n");
11335
11336 /*
11337 * Since vCPU can be preempted during this process,
11338 * vcpu->cpu could be different with pre_pcpu, we
11339 * need to set pre_pcpu as the destination of wakeup
11340 * notification event, then we can find the right vCPU
11341 * to wakeup in wakeup handler if interrupts happen
11342 * when the vCPU is in blocked state.
11343 */
11344 dest = cpu_physical_id(vcpu->pre_pcpu);
11345
11346 if (x2apic_enabled())
11347 new.ndst = dest;
11348 else
11349 new.ndst = (dest << 8) & 0xFF00;
11350
11351 /* set 'NV' to 'wakeup vector' */
11352 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11353 } while (cmpxchg(&pi_desc->control, old.control,
11354 new.control) != old.control);
11355
11356 return 0;
11357}
11358
bc22512b
YJ
11359static int vmx_pre_block(struct kvm_vcpu *vcpu)
11360{
11361 if (pi_pre_block(vcpu))
11362 return 1;
11363
64672c95
YJ
11364 if (kvm_lapic_hv_timer_in_use(vcpu))
11365 kvm_lapic_switch_to_sw_timer(vcpu);
11366
bc22512b
YJ
11367 return 0;
11368}
11369
11370static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8
FW
11371{
11372 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11373 struct pi_desc old, new;
11374 unsigned int dest;
11375 unsigned long flags;
11376
11377 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ
11378 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11379 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW
11380 return;
11381
11382 do {
11383 old.control = new.control = pi_desc->control;
11384
11385 dest = cpu_physical_id(vcpu->cpu);
11386
11387 if (x2apic_enabled())
11388 new.ndst = dest;
11389 else
11390 new.ndst = (dest << 8) & 0xFF00;
11391
11392 /* Allow posting non-urgent interrupts */
11393 new.sn = 0;
11394
11395 /* set 'NV' to 'notification vector' */
11396 new.nv = POSTED_INTR_VECTOR;
11397 } while (cmpxchg(&pi_desc->control, old.control,
11398 new.control) != old.control);
11399
11400 if(vcpu->pre_pcpu != -1) {
11401 spin_lock_irqsave(
11402 &per_cpu(blocked_vcpu_on_cpu_lock,
11403 vcpu->pre_pcpu), flags);
11404 list_del(&vcpu->blocked_vcpu_list);
11405 spin_unlock_irqrestore(
11406 &per_cpu(blocked_vcpu_on_cpu_lock,
11407 vcpu->pre_pcpu), flags);
11408 vcpu->pre_pcpu = -1;
11409 }
11410}
11411
bc22512b
YJ
11412static void vmx_post_block(struct kvm_vcpu *vcpu)
11413{
64672c95
YJ
11414 if (kvm_x86_ops->set_hv_timer)
11415 kvm_lapic_switch_to_hv_timer(vcpu);
11416
bc22512b
YJ
11417 pi_post_block(vcpu);
11418}
11419
efc64404
FW
11420/*
11421 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11422 *
11423 * @kvm: kvm
11424 * @host_irq: host irq of the interrupt
11425 * @guest_irq: gsi of the interrupt
11426 * @set: set or unset PI
11427 * returns 0 on success, < 0 on failure
11428 */
11429static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11430 uint32_t guest_irq, bool set)
11431{
11432 struct kvm_kernel_irq_routing_entry *e;
11433 struct kvm_irq_routing_table *irq_rt;
11434 struct kvm_lapic_irq irq;
11435 struct kvm_vcpu *vcpu;
11436 struct vcpu_data vcpu_info;
11437 int idx, ret = -EINVAL;
11438
11439 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ
11440 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11441 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW
11442 return 0;
11443
11444 idx = srcu_read_lock(&kvm->irq_srcu);
11445 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11446 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11447
11448 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11449 if (e->type != KVM_IRQ_ROUTING_MSI)
11450 continue;
11451 /*
11452 * VT-d PI cannot support posting multicast/broadcast
11453 * interrupts to a vCPU, we still use interrupt remapping
11454 * for these kind of interrupts.
11455 *
11456 * For lowest-priority interrupts, we only support
11457 * those with single CPU as the destination, e.g. user
11458 * configures the interrupts via /proc/irq or uses
11459 * irqbalance to make the interrupts single-CPU.
11460 *
11461 * We will support full lowest-priority interrupt later.
11462 */
11463
37131313 11464 kvm_set_msi_irq(kvm, e, &irq);
23a1c257
FW
11465 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11466 /*
11467 * Make sure the IRTE is in remapped mode if
11468 * we don't handle it in posted mode.
11469 */
11470 ret = irq_set_vcpu_affinity(host_irq, NULL);
11471 if (ret < 0) {
11472 printk(KERN_INFO
11473 "failed to back to remapped mode, irq: %u\n",
11474 host_irq);
11475 goto out;
11476 }
11477
efc64404 11478 continue;
23a1c257 11479 }
efc64404
FW
11480
11481 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11482 vcpu_info.vector = irq.vector;
11483
b6ce9780 11484 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
efc64404
FW
11485 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11486
11487 if (set)
11488 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11489 else {
11490 /* suppress notification event before unposting */
11491 pi_set_sn(vcpu_to_pi_desc(vcpu));
11492 ret = irq_set_vcpu_affinity(host_irq, NULL);
11493 pi_clear_sn(vcpu_to_pi_desc(vcpu));
11494 }
11495
11496 if (ret < 0) {
11497 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11498 __func__);
11499 goto out;
11500 }
11501 }
11502
11503 ret = 0;
11504out:
11505 srcu_read_unlock(&kvm->irq_srcu, idx);
11506 return ret;
11507}
11508
c45dcc71
AR
11509static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11510{
11511 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11512 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11513 FEATURE_CONTROL_LMCE;
11514 else
11515 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11516 ~FEATURE_CONTROL_LMCE;
11517}
11518
404f6aac 11519static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK
11520 .cpu_has_kvm_support = cpu_has_kvm_support,
11521 .disabled_by_bios = vmx_disabled_by_bios,
11522 .hardware_setup = hardware_setup,
11523 .hardware_unsetup = hardware_unsetup,
002c7f7c 11524 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK
11525 .hardware_enable = hardware_enable,
11526 .hardware_disable = hardware_disable,
04547156 11527 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 11528 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK
11529
11530 .vcpu_create = vmx_create_vcpu,
11531 .vcpu_free = vmx_free_vcpu,
04d2cc77 11532 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 11533
04d2cc77 11534 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK
11535 .vcpu_load = vmx_vcpu_load,
11536 .vcpu_put = vmx_vcpu_put,
11537
a96036b8 11538 .update_bp_intercept = update_exception_bitmap,
6aa8b732
AK
11539 .get_msr = vmx_get_msr,
11540 .set_msr = vmx_set_msr,
11541 .get_segment_base = vmx_get_segment_base,
11542 .get_segment = vmx_get_segment,
11543 .set_segment = vmx_set_segment,
2e4d2653 11544 .get_cpl = vmx_get_cpl,
6aa8b732 11545 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 11546 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 11547 .decache_cr3 = vmx_decache_cr3,
25c4c276 11548 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 11549 .set_cr0 = vmx_set_cr0,
6aa8b732
AK
11550 .set_cr3 = vmx_set_cr3,
11551 .set_cr4 = vmx_set_cr4,
6aa8b732 11552 .set_efer = vmx_set_efer,
6aa8b732
AK
11553 .get_idt = vmx_get_idt,
11554 .set_idt = vmx_set_idt,
11555 .get_gdt = vmx_get_gdt,
11556 .set_gdt = vmx_set_gdt,
73aaf249
JK
11557 .get_dr6 = vmx_get_dr6,
11558 .set_dr6 = vmx_set_dr6,
020df079 11559 .set_dr7 = vmx_set_dr7,
81908bf4 11560 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 11561 .cache_reg = vmx_cache_reg,
6aa8b732
AK
11562 .get_rflags = vmx_get_rflags,
11563 .set_rflags = vmx_set_rflags,
be94f6b7
HH
11564
11565 .get_pkru = vmx_get_pkru,
11566
6aa8b732 11567 .tlb_flush = vmx_flush_tlb,
6aa8b732 11568
6aa8b732 11569 .run = vmx_vcpu_run,
6062d012 11570 .handle_exit = vmx_handle_exit,
6aa8b732 11571 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC
11572 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11573 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 11574 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 11575 .set_irq = vmx_inject_irq,
95ba8273 11576 .set_nmi = vmx_inject_nmi,
298101da 11577 .queue_exception = vmx_queue_exception,
b463a6f7 11578 .cancel_injection = vmx_cancel_injection,
78646121 11579 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 11580 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK
11581 .get_nmi_mask = vmx_get_nmi_mask,
11582 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN
11583 .enable_nmi_window = enable_nmi_window,
11584 .enable_irq_window = enable_irq_window,
11585 .update_cr8_intercept = update_cr8_intercept,
8d14695f 11586 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 11587 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb
AS
11588 .get_enable_apicv = vmx_get_enable_apicv,
11589 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 11590 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 11591 .apicv_post_state_restore = vmx_apicv_post_state_restore,
c7c9c56c
YZ
11592 .hwapic_irr_update = vmx_hwapic_irr_update,
11593 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ
11594 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11595 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 11596
cbc94022 11597 .set_tss_addr = vmx_set_tss_addr,
67253af5 11598 .get_tdp_level = get_ept_level,
4b12f0de 11599 .get_mt_mask = vmx_get_mt_mask,
229456fc 11600
586f9607 11601 .get_exit_info = vmx_get_exit_info,
586f9607 11602
17cc3935 11603 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY
11604
11605 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY
11606
11607 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 11608 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR
11609
11610 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY
11611
11612 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA
11613
11614 .write_tsc_offset = vmx_write_tsc_offset,
1c97f0a0
JR
11615
11616 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR
11617
11618 .check_intercept = vmx_check_intercept,
a547c6db 11619 .handle_external_intr = vmx_handle_external_intr,
da8999d3 11620 .mpx_supported = vmx_mpx_supported,
55412b2e 11621 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK
11622
11623 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK
11624
11625 .sched_in = vmx_sched_in,
843e4330
KH
11626
11627 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11628 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11629 .flush_log_dirty = vmx_flush_log_dirty,
11630 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 11631 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 11632
bf9f6ac8
FW
11633 .pre_block = vmx_pre_block,
11634 .post_block = vmx_post_block,
11635
25462f7f 11636 .pmu_ops = &intel_pmu_ops,
efc64404
FW
11637
11638 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ
11639
11640#ifdef CONFIG_X86_64
11641 .set_hv_timer = vmx_set_hv_timer,
11642 .cancel_hv_timer = vmx_cancel_hv_timer,
11643#endif
c45dcc71
AR
11644
11645 .setup_mce = vmx_setup_mce,
6aa8b732
AK
11646};
11647
11648static int __init vmx_init(void)
11649{
34a1cd60
TC
11650 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11651 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 11652 if (r)
34a1cd60 11653 return r;
25c5f225 11654
2965faa5 11655#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY
11656 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11657 crash_vmclear_local_loaded_vmcss);
11658#endif
11659
fdef3ad1 11660 return 0;
6aa8b732
AK
11661}
11662
11663static void __exit vmx_exit(void)
11664{
2965faa5 11665#ifdef CONFIG_KEXEC_CORE
3b63a43f 11666 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY
11667 synchronize_rcu();
11668#endif
11669
cb498ea2 11670 kvm_exit();
6aa8b732
AK
11671}
11672
11673module_init(vmx_init)
11674module_exit(vmx_exit)