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i386/cpu: add crash-information QOM property
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
b834b508 38#if defined(CONFIG_KVM)
ef8621b1 39#include <linux/kvm_para.h>
b834b508 40#endif
65dee380 41
9c17d615 42#include "sysemu/sysemu.h"
53a89e26 43#include "hw/qdev-properties.h"
5232d00a 44#include "hw/i386/topology.h"
bdeec802 45#ifndef CONFIG_USER_ONLY
2001d0cd 46#include "exec/address-spaces.h"
741da0d3 47#include "hw/hw.h"
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
14c985cf 60#define CPUID_2_L3_16MB_16WAY_64B 0x4d
5e891bf8
EH		 61
62
63/* CPUID Leaf 4 constants: */
64
65/* EAX: */
66#define CPUID_4_TYPE_DCACHE 1
67#define CPUID_4_TYPE_ICACHE 2
68#define CPUID_4_TYPE_UNIFIED 3
69
70#define CPUID_4_LEVEL(l) ((l) << 5)
71
72#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73#define CPUID_4_FULLY_ASSOC (1 << 9)
74
75/* EDX: */
76#define CPUID_4_NO_INVD_SHARING (1 << 0)
77#define CPUID_4_INCLUSIVE (1 << 1)
78#define CPUID_4_COMPLEX_IDX (1 << 2)
79
80#define ASSOC_FULL 0xFF
81
82/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
84 a == 2 ? 0x2 : \
85 a == 4 ? 0x4 : \
86 a == 8 ? 0x6 : \
87 a == 16 ? 0x8 : \
88 a == 32 ? 0xA : \
89 a == 48 ? 0xB : \
90 a == 64 ? 0xC : \
91 a == 96 ? 0xD : \
92 a == 128 ? 0xE : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
95
96
97/* Definitions of the hardcoded cache entries we expose: */
98
99/* L1 data cache: */
100#define L1D_LINE_SIZE 64
101#define L1D_ASSOCIATIVITY 8
102#define L1D_SETS 64
103#define L1D_PARTITIONS 1
104/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107#define L1D_LINES_PER_TAG 1
108#define L1D_SIZE_KB_AMD 64
109#define L1D_ASSOCIATIVITY_AMD 2
110
111/* L1 instruction cache: */
112#define L1I_LINE_SIZE 64
113#define L1I_ASSOCIATIVITY 8
114#define L1I_SETS 64
115#define L1I_PARTITIONS 1
116/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119#define L1I_LINES_PER_TAG 1
120#define L1I_SIZE_KB_AMD 64
121#define L1I_ASSOCIATIVITY_AMD 2
122
123/* Level 2 unified cache: */
124#define L2_LINE_SIZE 64
125#define L2_ASSOCIATIVITY 16
126#define L2_SETS 4096
127#define L2_PARTITIONS 1
128/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132#define L2_LINES_PER_TAG 1
133#define L2_SIZE_KB_AMD 512
134
14c985cf 135/* Level 3 unified cache: */
5e891bf8
EH		 136#define L3_SIZE_KB 0 /* disabled */
137#define L3_ASSOCIATIVITY 0 /* disabled */
138#define L3_LINES_PER_TAG 0 /* disabled */
139#define L3_LINE_SIZE 0 /* disabled */
14c985cf
LM		 140#define L3_N_LINE_SIZE 64
141#define L3_N_ASSOCIATIVITY 16
142#define L3_N_SETS 16384
143#define L3_N_PARTITIONS 1
144#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
145#define L3_N_LINES_PER_TAG 1
146#define L3_N_SIZE_KB_AMD 16384
5e891bf8
EH		 147
148/* TLB definitions: */
149
150#define L1_DTLB_2M_ASSOC 1
151#define L1_DTLB_2M_ENTRIES 255
152#define L1_DTLB_4K_ASSOC 1
153#define L1_DTLB_4K_ENTRIES 255
154
155#define L1_ITLB_2M_ASSOC 1
156#define L1_ITLB_2M_ENTRIES 255
157#define L1_ITLB_4K_ASSOC 1
158#define L1_ITLB_4K_ENTRIES 255
159
160#define L2_DTLB_2M_ASSOC 0 /* disabled */
161#define L2_DTLB_2M_ENTRIES 0 /* disabled */
162#define L2_DTLB_4K_ASSOC 4
163#define L2_DTLB_4K_ENTRIES 512
164
165#define L2_ITLB_2M_ASSOC 0 /* disabled */
166#define L2_ITLB_2M_ENTRIES 0 /* disabled */
167#define L2_ITLB_4K_ASSOC 4
168#define L2_ITLB_4K_ENTRIES 512
169
170
171
99b88a17
IM		 172static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
173 uint32_t vendor2, uint32_t vendor3)
174{
175 int i;
176 for (i = 0; i < 4; i++) {
177 dst[i] = vendor1 >> (8 * i);
178 dst[i + 4] = vendor2 >> (8 * i);
179 dst[i + 8] = vendor3 >> (8 * i);
180 }
181 dst[CPUID_VENDOR_SZ] = '\0';
182}
183
621626ce
EH		 184#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
185#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
186 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
187#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
188 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
189 CPUID_PSE36 | CPUID_FXSR)
190#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
191#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
192 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
193 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
194 CPUID_PAE | CPUID_SEP | CPUID_APIC)
195
196#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
197 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
198 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
199 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 200 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 201 /* partly implemented:
202 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
203 /* missing:
204 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
205#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
206 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
207 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 208 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 209 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
210 /* missing:
211 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
212 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
213 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 214 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
215 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 216
217#ifdef TARGET_X86_64
218#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
219#else
220#define TCG_EXT2_X86_64_FEATURES 0
221#endif
222
223#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
224 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
225 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
226 TCG_EXT2_X86_64_FEATURES)
227#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
228 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
229#define TCG_EXT4_FEATURES 0
230#define TCG_SVM_FEATURES 0
231#define TCG_KVM_FEATURES 0
232#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 233 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
234 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 235 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
236 CPUID_7_0_EBX_ERMS)
621626ce 237 /* missing:
07929f2a 238 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 239 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 240 CPUID_7_0_EBX_RDSEED */
6c7c3c21
KS		 241#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
242 CPUID_7_0_ECX_LA57)
95ea69fb 243#define TCG_7_0_EDX_FEATURES 0
303752a9 244#define TCG_APM_FEATURES 0
28b8e4d0 245#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 246#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
247 /* missing:
248 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 249
5ef57876 250typedef struct FeatureWordInfo {
2d5312da
EH		 251 /* feature flags names are taken from "Intel Processor Identification and
252 * the CPUID Instruction" and AMD's "CPUID Specification".
253 * In cases of disagreement between feature naming conventions,
254 * aliases may be added.
255 */
256 const char *feat_names[32];
04d104b6
EH		 257 uint32_t cpuid_eax; /* Input EAX for CPUID */
258 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
259 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
260 int cpuid_reg; /* output register (R_* constant) */
37ce3522 261 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 262 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 263 uint32_t migratable_flags; /* Feature flags known to be migratable */
5ef57876
EH		 264} FeatureWordInfo;
265
266static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 267 [FEAT_1_EDX] = {
2d5312da
EH		 268 .feat_names = {
269 "fpu", "vme", "de", "pse",
270 "tsc", "msr", "pae", "mce",
271 "cx8", "apic", NULL, "sep",
272 "mtrr", "pge", "mca", "cmov",
273 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
274 NULL, "ds" /* Intel dts */, "acpi", "mmx",
275 "fxsr", "sse", "sse2", "ss",
276 "ht" /* Intel htt */, "tm", "ia64", "pbe",
277 },
bffd67b0 278 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 279 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 280 },
281 [FEAT_1_ECX] = {
2d5312da 282 .feat_names = {
16d2fcaa 283 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 284 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 285 "tm2", "ssse3", "cid", NULL,
286 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 287 NULL, "pcid", "dca", "sse4.1",
288 "sse4.2", "x2apic", "movbe", "popcnt",
2d5312da
EH		 289 "tsc-deadline", "aes", "xsave", "osxsave",
290 "avx", "f16c", "rdrand", "hypervisor",
291 },
bffd67b0 292 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 293 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 294 },
2d5312da
EH		 295 /* Feature names that are already defined on feature_name[] but
296 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
297 * names on feat_names below. They are copied automatically
298 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
299 */
bffd67b0 300 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 301 .feat_names = {
302 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
303 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
304 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
305 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
306 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 307 "nx", NULL, "mmxext", NULL /* mmx */,
308 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
309 NULL, "lm", "3dnowext", "3dnow",
2d5312da 310 },
bffd67b0 311 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 312 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 313 },
314 [FEAT_8000_0001_ECX] = {
2d5312da 315 .feat_names = {
fc7dfd20 316 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 317 "cr8legacy", "abm", "sse4a", "misalignsse",
318 "3dnowprefetch", "osvw", "ibs", "xop",
319 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 320 "fma4", "tce", NULL, "nodeid-msr",
321 NULL, "tbm", "topoext", "perfctr-core",
322 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 323 NULL, NULL, NULL, NULL,
324 },
bffd67b0 325 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 326 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 327 },
89e49c8b 328 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 329 .feat_names = {
330 NULL, NULL, "xstore", "xstore-en",
331 NULL, NULL, "xcrypt", "xcrypt-en",
332 "ace2", "ace2-en", "phe", "phe-en",
333 "pmm", "pmm-en", NULL, NULL,
334 NULL, NULL, NULL, NULL,
335 NULL, NULL, NULL, NULL,
336 NULL, NULL, NULL, NULL,
337 NULL, NULL, NULL, NULL,
338 },
89e49c8b 339 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 340 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 341 },
bffd67b0 342 [FEAT_KVM] = {
2d5312da 343 .feat_names = {
fc7dfd20
EH		 344 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
345 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
2d5312da
EH		 346 NULL, NULL, NULL, NULL,
347 NULL, NULL, NULL, NULL,
348 NULL, NULL, NULL, NULL,
349 NULL, NULL, NULL, NULL,
350 "kvmclock-stable-bit", NULL, NULL, NULL,
351 NULL, NULL, NULL, NULL,
352 },
bffd67b0 353 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 354 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 355 },
c35bd19a 356 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 357 .feat_names = {
358 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
359 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
360 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
361 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
362 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
363 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
364 NULL, NULL, NULL, NULL,
365 NULL, NULL, NULL, NULL,
366 NULL, NULL, NULL, NULL,
367 NULL, NULL, NULL, NULL,
368 NULL, NULL, NULL, NULL,
369 },
c35bd19a
EY		 370 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
371 },
372 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 373 .feat_names = {
374 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
375 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
376 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
377 NULL /* hv_create_port */, NULL /* hv_connect_port */,
378 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
379 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
380 NULL, NULL,
381 NULL, NULL, NULL, NULL,
382 NULL, NULL, NULL, NULL,
383 NULL, NULL, NULL, NULL,
384 NULL, NULL, NULL, NULL,
385 },
c35bd19a
EY		 386 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
387 },
388 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 389 .feat_names = {
390 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
391 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
392 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
393 NULL, NULL,
394 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
395 NULL, NULL, NULL, NULL,
396 NULL, NULL, NULL, NULL,
397 NULL, NULL, NULL, NULL,
398 NULL, NULL, NULL, NULL,
399 NULL, NULL, NULL, NULL,
400 },
c35bd19a
EY		 401 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
402 },
bffd67b0 403 [FEAT_SVM] = {
2d5312da 404 .feat_names = {
fc7dfd20
EH		 405 "npt", "lbrv", "svm-lock", "nrip-save",
406 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
407 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 408 "pfthreshold", NULL, NULL, NULL,
409 NULL, NULL, NULL, NULL,
410 NULL, NULL, NULL, NULL,
411 NULL, NULL, NULL, NULL,
412 NULL, NULL, NULL, NULL,
413 },
bffd67b0 414 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 415 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 416 },
417 [FEAT_7_0_EBX] = {
2d5312da 418 .feat_names = {
fc7dfd20 419 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 420 "hle", "avx2", NULL, "smep",
421 "bmi2", "erms", "invpcid", "rtm",
422 NULL, NULL, "mpx", NULL,
423 "avx512f", "avx512dq", "rdseed", "adx",
424 "smap", "avx512ifma", "pcommit", "clflushopt",
425 "clwb", NULL, "avx512pf", "avx512er",
638cbd45 426 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 427 },
04d104b6
EH		 428 .cpuid_eax = 7,
429 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
430 .cpuid_reg = R_EBX,
37ce3522 431 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 432 },
f74eefe0 433 [FEAT_7_0_ECX] = {
2d5312da
EH		 434 .feat_names = {
435 NULL, "avx512vbmi", "umip", "pku",
436 "ospke", NULL, NULL, NULL,
437 NULL, NULL, NULL, NULL,
f7754377 438 NULL, NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 439 "la57", NULL, NULL, NULL,
2d5312da
EH		 440 NULL, NULL, "rdpid", NULL,
441 NULL, NULL, NULL, NULL,
442 NULL, NULL, NULL, NULL,
443 },
f74eefe0
HH		 444 .cpuid_eax = 7,
445 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
446 .cpuid_reg = R_ECX,
447 .tcg_features = TCG_7_0_ECX_FEATURES,
448 },
95ea69fb
LK		 449 [FEAT_7_0_EDX] = {
450 .feat_names = {
451 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
452 NULL, NULL, NULL, NULL,
453 NULL, NULL, NULL, NULL,
454 NULL, NULL, NULL, NULL,
455 NULL, NULL, NULL, NULL,
456 NULL, NULL, NULL, NULL,
457 NULL, NULL, NULL, NULL,
458 NULL, NULL, NULL, NULL,
459 },
460 .cpuid_eax = 7,
461 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
462 .cpuid_reg = R_EDX,
463 .tcg_features = TCG_7_0_EDX_FEATURES,
464 },
303752a9 465 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 466 .feat_names = {
467 NULL, NULL, NULL, NULL,
468 NULL, NULL, NULL, NULL,
469 "invtsc", NULL, NULL, NULL,
470 NULL, NULL, NULL, NULL,
471 NULL, NULL, NULL, NULL,
472 NULL, NULL, NULL, NULL,
473 NULL, NULL, NULL, NULL,
474 NULL, NULL, NULL, NULL,
475 },
303752a9
MT		 476 .cpuid_eax = 0x80000007,
477 .cpuid_reg = R_EDX,
478 .tcg_features = TCG_APM_FEATURES,
479 .unmigratable_flags = CPUID_APM_INVTSC,
480 },
0bb0b2d2 481 [FEAT_XSAVE] = {
2d5312da
EH		 482 .feat_names = {
483 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
484 NULL, NULL, NULL, NULL,
485 NULL, NULL, NULL, NULL,
486 NULL, NULL, NULL, NULL,
487 NULL, NULL, NULL, NULL,
488 NULL, NULL, NULL, NULL,
489 NULL, NULL, NULL, NULL,
490 NULL, NULL, NULL, NULL,
491 },
0bb0b2d2
PB		 492 .cpuid_eax = 0xd,
493 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
494 .cpuid_reg = R_EAX,
c9cfe8f9 495 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 496 },
28b8e4d0 497 [FEAT_6_EAX] = {
2d5312da
EH		 498 .feat_names = {
499 NULL, NULL, "arat", NULL,
500 NULL, NULL, NULL, NULL,
501 NULL, NULL, NULL, NULL,
502 NULL, NULL, NULL, NULL,
503 NULL, NULL, NULL, NULL,
504 NULL, NULL, NULL, NULL,
505 NULL, NULL, NULL, NULL,
506 NULL, NULL, NULL, NULL,
507 },
28b8e4d0
JK		 508 .cpuid_eax = 6, .cpuid_reg = R_EAX,
509 .tcg_features = TCG_6_EAX_FEATURES,
510 },
96193c22
EH		 511 [FEAT_XSAVE_COMP_LO] = {
512 .cpuid_eax = 0xD,
513 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
514 .cpuid_reg = R_EAX,
515 .tcg_features = ~0U,
6fb2fff7
EH		 516 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
517 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
518 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
519 XSTATE_PKRU_MASK,
96193c22
EH		 520 },
521 [FEAT_XSAVE_COMP_HI] = {
522 .cpuid_eax = 0xD,
523 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
524 .cpuid_reg = R_EDX,
525 .tcg_features = ~0U,
526 },
5ef57876
EH		 527};
528
8e8aba50
EH		 529typedef struct X86RegisterInfo32 {
530 /* Name of register */
531 const char *name;
532 /* QAPI enum value register */
533 X86CPURegister32 qapi_enum;
534} X86RegisterInfo32;
535
536#define REGISTER(reg) \
5d371f41 537 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 538static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 539 REGISTER(EAX),
540 REGISTER(ECX),
541 REGISTER(EDX),
542 REGISTER(EBX),
543 REGISTER(ESP),
544 REGISTER(EBP),
545 REGISTER(ESI),
546 REGISTER(EDI),
547};
548#undef REGISTER
549
3f32bd21
RH		 550typedef struct ExtSaveArea {
551 uint32_t feature, bits;
552 uint32_t offset, size;
553} ExtSaveArea;
554
555static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 556 [XSTATE_FP_BIT] = {
557 /* x87 FP state component is always enabled if XSAVE is supported */
558 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
559 /* x87 state is in the legacy region of the XSAVE area */
560 .offset = 0,
561 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
562 },
563 [XSTATE_SSE_BIT] = {
564 /* SSE state component is always enabled if XSAVE is supported */
565 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
566 /* SSE state is in the legacy region of the XSAVE area */
567 .offset = 0,
568 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
569 },
cfc3b074
PB		 570 [XSTATE_YMM_BIT] =
571 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 572 .offset = offsetof(X86XSaveArea, avx_state),
573 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 574 [XSTATE_BNDREGS_BIT] =
575 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 576 .offset = offsetof(X86XSaveArea, bndreg_state),
577 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 578 [XSTATE_BNDCSR_BIT] =
579 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 580 .offset = offsetof(X86XSaveArea, bndcsr_state),
581 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 582 [XSTATE_OPMASK_BIT] =
583 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 584 .offset = offsetof(X86XSaveArea, opmask_state),
585 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 586 [XSTATE_ZMM_Hi256_BIT] =
587 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 588 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
589 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 590 [XSTATE_Hi16_ZMM_BIT] =
591 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 592 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
593 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 594 [XSTATE_PKRU_BIT] =
595 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 596 .offset = offsetof(X86XSaveArea, pkru_state),
597 .size = sizeof(XSavePKRU) },
2560f19f 598};
8e8aba50 599
1fda6198
EH		 600static uint32_t xsave_area_size(uint64_t mask)
601{
602 int i;
e3c9022b 603 uint64_t ret = 0;
1fda6198 604
e3c9022b 605 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 606 const ExtSaveArea *esa = &x86_ext_save_areas[i];
607 if ((mask >> i) & 1) {
608 ret = MAX(ret, esa->offset + esa->size);
609 }
610 }
611 return ret;
612}
613
96193c22
EH		 614static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
615{
616 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
617 cpu->env.features[FEAT_XSAVE_COMP_LO];
618}
619
8b4beddc
EH		 620const char *get_register_name_32(unsigned int reg)
621{
31ccdde2 622 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 623 return NULL;
624 }
8e8aba50 625 return x86_reg_info_32[reg].name;
8b4beddc
EH		 626}
627
84f1b92f
EH		 628/*
629 * Returns the set of feature flags that are supported and migratable by
630 * QEMU, for a given FeatureWord.
631 */
632static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
633{
634 FeatureWordInfo *wi = &feature_word_info[w];
635 uint32_t r = 0;
636 int i;
637
638 for (i = 0; i < 32; i++) {
639 uint32_t f = 1U << i;
6fb2fff7
EH		 640
641 /* If the feature name is known, it is implicitly considered migratable,
642 * unless it is explicitly set in unmigratable_flags */
643 if ((wi->migratable_flags & f) ||
644 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
645 r |= f;
84f1b92f 646 }
84f1b92f
EH		 647 }
648 return r;
649}
650
bb44e0d1
JK		 651void host_cpuid(uint32_t function, uint32_t count,
652 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 653{
a1fd24af
AL		 654 uint32_t vec[4];
655
656#ifdef __x86_64__
657 asm volatile("cpuid"
658 : "=a"(vec[0]), "=b"(vec[1]),
659 "=c"(vec[2]), "=d"(vec[3])
660 : "0"(function), "c"(count) : "cc");
c1f41226 661#elif defined(__i386__)
a1fd24af
AL		 662 asm volatile("pusha \n\t"
663 "cpuid \n\t"
664 "mov %%eax, 0(%2) \n\t"
665 "mov %%ebx, 4(%2) \n\t"
666 "mov %%ecx, 8(%2) \n\t"
667 "mov %%edx, 12(%2) \n\t"
668 "popa"
669 : : "a"(function), "c"(count), "S"(vec)
670 : "memory", "cc");
c1f41226
EH		 671#else
672 abort();
a1fd24af
AL		 673#endif
674
bdde476a 675 if (eax)
a1fd24af 676 *eax = vec[0];
bdde476a 677 if (ebx)
a1fd24af 678 *ebx = vec[1];
bdde476a 679 if (ecx)
a1fd24af 680 *ecx = vec[2];
bdde476a 681 if (edx)
a1fd24af 682 *edx = vec[3];
bdde476a 683}
c6dc6f63 684
d940ee9b
EH		 685/* CPU class name definitions: */
686
687#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
688#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
689
690/* Return type name for a given CPU model name
691 * Caller is responsible for freeing the returned string.
692 */
693static char *x86_cpu_type_name(const char *model_name)
694{
695 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
696}
697
500050d1
AF		 698static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
699{
d940ee9b
EH		 700 ObjectClass *oc;
701 char *typename;
702
500050d1
AF		 703 if (cpu_model == NULL) {
704 return NULL;
705 }
706
d940ee9b
EH		 707 typename = x86_cpu_type_name(cpu_model);
708 oc = object_class_by_name(typename);
709 g_free(typename);
710 return oc;
500050d1
AF		 711}
712
104494ea
IM		 713static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
714{
715 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
716 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
717 return g_strndup(class_name,
718 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
719}
720
d940ee9b 721struct X86CPUDefinition {
c6dc6f63
AP		 722 const char *name;
723 uint32_t level;
90e4b0c3 724 uint32_t xlevel;
99b88a17
IM		 725 /* vendor is zero-terminated, 12 character ASCII string */
726 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 727 int family;
728 int model;
729 int stepping;
0514ef2f 730 FeatureWordArray features;
c6dc6f63 731 char model_id[48];
d940ee9b 732};
c6dc6f63 733
9576de75 734static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 735 {
736 .name = "qemu64",
3046bb5d 737 .level = 0xd,
99b88a17 738 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 739 .family = 6,
f8e6a11a 740 .model = 6,
c6dc6f63 741 .stepping = 3,
0514ef2f 742 .features[FEAT_1_EDX] =
27861ecc 743 PPRO_FEATURES |
c6dc6f63 744 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 745 CPUID_PSE36,
0514ef2f 746 .features[FEAT_1_ECX] =
6aa91e4a 747 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 748 .features[FEAT_8000_0001_EDX] =
c6dc6f63 749 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 750 .features[FEAT_8000_0001_ECX] =
71195672 751 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 752 .xlevel = 0x8000000A,
9cf2cc3d 753 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 754 },
755 {
756 .name = "phenom",
757 .level = 5,
99b88a17 758 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 759 .family = 16,
760 .model = 2,
761 .stepping = 3,
b9fc20bc 762 /* Missing: CPUID_HT */
0514ef2f 763 .features[FEAT_1_EDX] =
27861ecc 764 PPRO_FEATURES |
c6dc6f63 765 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 766 CPUID_PSE36 | CPUID_VME,
0514ef2f 767 .features[FEAT_1_ECX] =
27861ecc 768 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 769 CPUID_EXT_POPCNT,
0514ef2f 770 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 771 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
772 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 773 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 774 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
775 CPUID_EXT3_CR8LEG,
776 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
777 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 778 .features[FEAT_8000_0001_ECX] =
27861ecc 779 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 780 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 781 /* Missing: CPUID_SVM_LBRV */
0514ef2f 782 .features[FEAT_SVM] =
b9fc20bc 783 CPUID_SVM_NPT,
c6dc6f63
AP		 784 .xlevel = 0x8000001A,
785 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
786 },
787 {
788 .name = "core2duo",
789 .level = 10,
99b88a17 790 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 791 .family = 6,
792 .model = 15,
793 .stepping = 11,
b9fc20bc 794 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 795 .features[FEAT_1_EDX] =
27861ecc 796 PPRO_FEATURES |
c6dc6f63 797 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 798 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
799 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 800 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 801 .features[FEAT_1_ECX] =
27861ecc 802 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 803 CPUID_EXT_CX16,
0514ef2f 804 .features[FEAT_8000_0001_EDX] =
27861ecc 805 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 806 .features[FEAT_8000_0001_ECX] =
27861ecc 807 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 808 .xlevel = 0x80000008,
809 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
810 },
811 {
812 .name = "kvm64",
3046bb5d 813 .level = 0xd,
99b88a17 814 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 815 .family = 15,
816 .model = 6,
817 .stepping = 1,
b3a4f0b1 818 /* Missing: CPUID_HT */
0514ef2f 819 .features[FEAT_1_EDX] =
b3a4f0b1 820 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 821 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
822 CPUID_PSE36,
823 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 824 .features[FEAT_1_ECX] =
27861ecc 825 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 826 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 827 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 828 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
829 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
830 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
831 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
832 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 833 .features[FEAT_8000_0001_ECX] =
27861ecc 834 0,
c6dc6f63
AP		 835 .xlevel = 0x80000008,
836 .model_id = "Common KVM processor"
837 },
c6dc6f63
AP		 838 {
839 .name = "qemu32",
840 .level = 4,
99b88a17 841 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 842 .family = 6,
f8e6a11a 843 .model = 6,
c6dc6f63 844 .stepping = 3,
0514ef2f 845 .features[FEAT_1_EDX] =
27861ecc 846 PPRO_FEATURES,
0514ef2f 847 .features[FEAT_1_ECX] =
6aa91e4a 848 CPUID_EXT_SSE3,
58012d66 849 .xlevel = 0x80000004,
9cf2cc3d 850 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 851 },
eafaf1e5
AP		 852 {
853 .name = "kvm32",
854 .level = 5,
99b88a17 855 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 856 .family = 15,
857 .model = 6,
858 .stepping = 1,
0514ef2f 859 .features[FEAT_1_EDX] =
b3a4f0b1 860 PPRO_FEATURES | CPUID_VME |
eafaf1e5 861 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 862 .features[FEAT_1_ECX] =
27861ecc 863 CPUID_EXT_SSE3,
0514ef2f 864 .features[FEAT_8000_0001_ECX] =
27861ecc 865 0,
eafaf1e5
AP		 866 .xlevel = 0x80000008,
867 .model_id = "Common 32-bit KVM processor"
868 },
c6dc6f63
AP		 869 {
870 .name = "coreduo",
871 .level = 10,
99b88a17 872 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 873 .family = 6,
874 .model = 14,
875 .stepping = 8,
b9fc20bc 876 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 877 .features[FEAT_1_EDX] =
27861ecc 878 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 879 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
880 CPUID_SS,
881 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 882 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 883 .features[FEAT_1_ECX] =
e93abc14 884 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 885 .features[FEAT_8000_0001_EDX] =
27861ecc 886 CPUID_EXT2_NX,
c6dc6f63
AP		 887 .xlevel = 0x80000008,
888 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
889 },
890 {
891 .name = "486",
58012d66 892 .level = 1,
99b88a17 893 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 894 .family = 4,
b2a856d9 895 .model = 8,
c6dc6f63 896 .stepping = 0,
0514ef2f 897 .features[FEAT_1_EDX] =
27861ecc 898 I486_FEATURES,
c6dc6f63
AP		 899 .xlevel = 0,
900 },
901 {
902 .name = "pentium",
903 .level = 1,
99b88a17 904 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 905 .family = 5,
906 .model = 4,
907 .stepping = 3,
0514ef2f 908 .features[FEAT_1_EDX] =
27861ecc 909 PENTIUM_FEATURES,
c6dc6f63
AP		 910 .xlevel = 0,
911 },
912 {
913 .name = "pentium2",
914 .level = 2,
99b88a17 915 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 916 .family = 6,
917 .model = 5,
918 .stepping = 2,
0514ef2f 919 .features[FEAT_1_EDX] =
27861ecc 920 PENTIUM2_FEATURES,
c6dc6f63
AP		 921 .xlevel = 0,
922 },
923 {
924 .name = "pentium3",
3046bb5d 925 .level = 3,
99b88a17 926 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 927 .family = 6,
928 .model = 7,
929 .stepping = 3,
0514ef2f 930 .features[FEAT_1_EDX] =
27861ecc 931 PENTIUM3_FEATURES,
c6dc6f63
AP		 932 .xlevel = 0,
933 },
934 {
935 .name = "athlon",
936 .level = 2,
99b88a17 937 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 938 .family = 6,
939 .model = 2,
940 .stepping = 3,
0514ef2f 941 .features[FEAT_1_EDX] =
27861ecc 942 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 943 CPUID_MCA,
0514ef2f 944 .features[FEAT_8000_0001_EDX] =
60032ac0 945 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 946 .xlevel = 0x80000008,
9cf2cc3d 947 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 948 },
949 {
950 .name = "n270",
3046bb5d 951 .level = 10,
99b88a17 952 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 953 .family = 6,
954 .model = 28,
955 .stepping = 2,
b9fc20bc 956 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 957 .features[FEAT_1_EDX] =
27861ecc 958 PPRO_FEATURES |
b9fc20bc
EH		 959 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
960 CPUID_ACPI | CPUID_SS,
c6dc6f63 961 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 962 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
963 * CPUID_EXT_XTPR */
0514ef2f 964 .features[FEAT_1_ECX] =
27861ecc 965 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 966 CPUID_EXT_MOVBE,
0514ef2f 967 .features[FEAT_8000_0001_EDX] =
60032ac0 968 CPUID_EXT2_NX,
0514ef2f 969 .features[FEAT_8000_0001_ECX] =
27861ecc 970 CPUID_EXT3_LAHF_LM,
3046bb5d 971 .xlevel = 0x80000008,
c6dc6f63
AP		 972 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
973 },
3eca4642
EH		 974 {
975 .name = "Conroe",
3046bb5d 976 .level = 10,
99b88a17 977 .vendor = CPUID_VENDOR_INTEL,
3eca4642 978 .family = 6,
ffce9ebb 979 .model = 15,
3eca4642 980 .stepping = 3,
0514ef2f 981 .features[FEAT_1_EDX] =
b3a4f0b1 982 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 983 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
984 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
985 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
986 CPUID_DE | CPUID_FP87,
0514ef2f 987 .features[FEAT_1_ECX] =
27861ecc 988 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 989 .features[FEAT_8000_0001_EDX] =
27861ecc 990 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 991 .features[FEAT_8000_0001_ECX] =
27861ecc 992 CPUID_EXT3_LAHF_LM,
3046bb5d 993 .xlevel = 0x80000008,
3eca4642
EH		 994 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
995 },
996 {
997 .name = "Penryn",
3046bb5d 998 .level = 10,
99b88a17 999 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1000 .family = 6,
ffce9ebb 1001 .model = 23,
3eca4642 1002 .stepping = 3,
0514ef2f 1003 .features[FEAT_1_EDX] =
b3a4f0b1 1004 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1005 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1006 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1007 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1008 CPUID_DE | CPUID_FP87,
0514ef2f 1009 .features[FEAT_1_ECX] =
27861ecc 1010 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1011 CPUID_EXT_SSE3,
0514ef2f 1012 .features[FEAT_8000_0001_EDX] =
27861ecc 1013 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1014 .features[FEAT_8000_0001_ECX] =
27861ecc 1015 CPUID_EXT3_LAHF_LM,
3046bb5d 1016 .xlevel = 0x80000008,
3eca4642
EH		 1017 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1018 },
1019 {
1020 .name = "Nehalem",
3046bb5d 1021 .level = 11,
99b88a17 1022 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1023 .family = 6,
ffce9ebb 1024 .model = 26,
3eca4642 1025 .stepping = 3,
0514ef2f 1026 .features[FEAT_1_EDX] =
b3a4f0b1 1027 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1028 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1029 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1030 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1031 CPUID_DE | CPUID_FP87,
0514ef2f 1032 .features[FEAT_1_ECX] =
27861ecc 1033 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1034 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1035 .features[FEAT_8000_0001_EDX] =
27861ecc 1036 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1037 .features[FEAT_8000_0001_ECX] =
27861ecc 1038 CPUID_EXT3_LAHF_LM,
3046bb5d 1039 .xlevel = 0x80000008,
3eca4642
EH		 1040 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1041 },
1042 {
1043 .name = "Westmere",
1044 .level = 11,
99b88a17 1045 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1046 .family = 6,
1047 .model = 44,
1048 .stepping = 1,
0514ef2f 1049 .features[FEAT_1_EDX] =
b3a4f0b1 1050 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1051 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1052 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1053 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1054 CPUID_DE | CPUID_FP87,
0514ef2f 1055 .features[FEAT_1_ECX] =
27861ecc 1056 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1057 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1058 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1059 .features[FEAT_8000_0001_EDX] =
27861ecc 1060 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1061 .features[FEAT_8000_0001_ECX] =
27861ecc 1062 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1063 .features[FEAT_6_EAX] =
1064 CPUID_6_EAX_ARAT,
3046bb5d 1065 .xlevel = 0x80000008,
3eca4642
EH		 1066 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1067 },
1068 {
1069 .name = "SandyBridge",
1070 .level = 0xd,
99b88a17 1071 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1072 .family = 6,
1073 .model = 42,
1074 .stepping = 1,
0514ef2f 1075 .features[FEAT_1_EDX] =
b3a4f0b1 1076 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1077 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1078 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1079 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1080 CPUID_DE | CPUID_FP87,
0514ef2f 1081 .features[FEAT_1_ECX] =
27861ecc 1082 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1083 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1084 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1085 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1086 CPUID_EXT_SSE3,
0514ef2f 1087 .features[FEAT_8000_0001_EDX] =
27861ecc 1088 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1089 CPUID_EXT2_SYSCALL,
0514ef2f 1090 .features[FEAT_8000_0001_ECX] =
27861ecc 1091 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1092 .features[FEAT_XSAVE] =
1093 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1094 .features[FEAT_6_EAX] =
1095 CPUID_6_EAX_ARAT,
3046bb5d 1096 .xlevel = 0x80000008,
3eca4642
EH		 1097 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1098 },
2f9ac42a
PB		 1099 {
1100 .name = "IvyBridge",
1101 .level = 0xd,
1102 .vendor = CPUID_VENDOR_INTEL,
1103 .family = 6,
1104 .model = 58,
1105 .stepping = 9,
1106 .features[FEAT_1_EDX] =
1107 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1108 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1109 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1110 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1111 CPUID_DE | CPUID_FP87,
1112 .features[FEAT_1_ECX] =
1113 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1114 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1115 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1116 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1117 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1118 .features[FEAT_7_0_EBX] =
1119 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1120 CPUID_7_0_EBX_ERMS,
1121 .features[FEAT_8000_0001_EDX] =
1122 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1123 CPUID_EXT2_SYSCALL,
1124 .features[FEAT_8000_0001_ECX] =
1125 CPUID_EXT3_LAHF_LM,
1126 .features[FEAT_XSAVE] =
1127 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1128 .features[FEAT_6_EAX] =
1129 CPUID_6_EAX_ARAT,
3046bb5d 1130 .xlevel = 0x80000008,
2f9ac42a
PB		 1131 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1132 },
37507094 1133 {
a356850b
EH		 1134 .name = "Haswell-noTSX",
1135 .level = 0xd,
1136 .vendor = CPUID_VENDOR_INTEL,
1137 .family = 6,
1138 .model = 60,
1139 .stepping = 1,
1140 .features[FEAT_1_EDX] =
1141 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1142 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1143 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1144 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1145 CPUID_DE | CPUID_FP87,
1146 .features[FEAT_1_ECX] =
1147 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1148 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1149 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1150 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1151 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1152 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1153 .features[FEAT_8000_0001_EDX] =
1154 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1155 CPUID_EXT2_SYSCALL,
1156 .features[FEAT_8000_0001_ECX] =
becb6667 1157 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1158 .features[FEAT_7_0_EBX] =
1159 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1160 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1161 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1162 .features[FEAT_XSAVE] =
1163 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1164 .features[FEAT_6_EAX] =
1165 CPUID_6_EAX_ARAT,
3046bb5d 1166 .xlevel = 0x80000008,
a356850b
EH		 1167 .model_id = "Intel Core Processor (Haswell, no TSX)",
1168 }, {
37507094
EH		 1169 .name = "Haswell",
1170 .level = 0xd,
99b88a17 1171 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1172 .family = 6,
1173 .model = 60,
1174 .stepping = 1,
0514ef2f 1175 .features[FEAT_1_EDX] =
b3a4f0b1 1176 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1177 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1178 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1179 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1180 CPUID_DE | CPUID_FP87,
0514ef2f 1181 .features[FEAT_1_ECX] =
27861ecc 1182 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1183 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1184 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1185 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1186 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1187 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1188 .features[FEAT_8000_0001_EDX] =
27861ecc 1189 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1190 CPUID_EXT2_SYSCALL,
0514ef2f 1191 .features[FEAT_8000_0001_ECX] =
becb6667 1192 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1193 .features[FEAT_7_0_EBX] =
27861ecc 1194 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1195 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1196 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1197 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1198 .features[FEAT_XSAVE] =
1199 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1200 .features[FEAT_6_EAX] =
1201 CPUID_6_EAX_ARAT,
3046bb5d 1202 .xlevel = 0x80000008,
37507094
EH		 1203 .model_id = "Intel Core Processor (Haswell)",
1204 },
a356850b
EH		 1205 {
1206 .name = "Broadwell-noTSX",
1207 .level = 0xd,
1208 .vendor = CPUID_VENDOR_INTEL,
1209 .family = 6,
1210 .model = 61,
1211 .stepping = 2,
1212 .features[FEAT_1_EDX] =
1213 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1214 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1215 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1216 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1217 CPUID_DE | CPUID_FP87,
1218 .features[FEAT_1_ECX] =
1219 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1220 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1221 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1222 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1223 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1224 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1225 .features[FEAT_8000_0001_EDX] =
1226 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1227 CPUID_EXT2_SYSCALL,
1228 .features[FEAT_8000_0001_ECX] =
becb6667 1229 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1230 .features[FEAT_7_0_EBX] =
1231 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1232 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1233 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1234 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1235 CPUID_7_0_EBX_SMAP,
1236 .features[FEAT_XSAVE] =
1237 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1238 .features[FEAT_6_EAX] =
1239 CPUID_6_EAX_ARAT,
3046bb5d 1240 .xlevel = 0x80000008,
a356850b
EH		 1241 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1242 },
ece01354
EH		 1243 {
1244 .name = "Broadwell",
1245 .level = 0xd,
1246 .vendor = CPUID_VENDOR_INTEL,
1247 .family = 6,
1248 .model = 61,
1249 .stepping = 2,
1250 .features[FEAT_1_EDX] =
b3a4f0b1 1251 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1252 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1253 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1254 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1255 CPUID_DE | CPUID_FP87,
1256 .features[FEAT_1_ECX] =
1257 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1258 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1259 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1260 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1261 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1262 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1263 .features[FEAT_8000_0001_EDX] =
1264 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1265 CPUID_EXT2_SYSCALL,
1266 .features[FEAT_8000_0001_ECX] =
becb6667 1267 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1268 .features[FEAT_7_0_EBX] =
1269 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1270 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1271 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1272 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1273 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1274 .features[FEAT_XSAVE] =
1275 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1276 .features[FEAT_6_EAX] =
1277 CPUID_6_EAX_ARAT,
3046bb5d 1278 .xlevel = 0x80000008,
ece01354
EH		 1279 .model_id = "Intel Core Processor (Broadwell)",
1280 },
f6f949e9
EH		 1281 {
1282 .name = "Skylake-Client",
1283 .level = 0xd,
1284 .vendor = CPUID_VENDOR_INTEL,
1285 .family = 6,
1286 .model = 94,
1287 .stepping = 3,
1288 .features[FEAT_1_EDX] =
1289 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1290 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1291 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1292 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1293 CPUID_DE | CPUID_FP87,
1294 .features[FEAT_1_ECX] =
1295 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1296 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1297 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1298 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1299 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1300 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1301 .features[FEAT_8000_0001_EDX] =
1302 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1303 CPUID_EXT2_SYSCALL,
1304 .features[FEAT_8000_0001_ECX] =
1305 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1306 .features[FEAT_7_0_EBX] =
1307 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1308 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1309 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1310 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1311 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1312 /* Missing: XSAVES (not supported by some Linux versions,
1313 * including v4.1 to v4.6).
1314 * KVM doesn't yet expose any XSAVES state save component,
1315 * and the only one defined in Skylake (processor tracing)
1316 * probably will block migration anyway.
1317 */
1318 .features[FEAT_XSAVE] =
1319 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1320 CPUID_XSAVE_XGETBV1,
1321 .features[FEAT_6_EAX] =
1322 CPUID_6_EAX_ARAT,
1323 .xlevel = 0x80000008,
1324 .model_id = "Intel Core Processor (Skylake)",
1325 },
3eca4642
EH		 1326 {
1327 .name = "Opteron_G1",
1328 .level = 5,
99b88a17 1329 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1330 .family = 15,
1331 .model = 6,
1332 .stepping = 1,
0514ef2f 1333 .features[FEAT_1_EDX] =
b3a4f0b1 1334 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1335 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1336 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1337 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1338 CPUID_DE | CPUID_FP87,
0514ef2f 1339 .features[FEAT_1_ECX] =
27861ecc 1340 CPUID_EXT_SSE3,
0514ef2f 1341 .features[FEAT_8000_0001_EDX] =
2a923a29 1342 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 1343 .xlevel = 0x80000008,
1344 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1345 },
1346 {
1347 .name = "Opteron_G2",
1348 .level = 5,
99b88a17 1349 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1350 .family = 15,
1351 .model = 6,
1352 .stepping = 1,
0514ef2f 1353 .features[FEAT_1_EDX] =
b3a4f0b1 1354 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1355 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1356 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1357 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1358 CPUID_DE | CPUID_FP87,
0514ef2f 1359 .features[FEAT_1_ECX] =
27861ecc 1360 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1361 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1362 .features[FEAT_8000_0001_EDX] =
2a923a29 1363 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1364 .features[FEAT_8000_0001_ECX] =
27861ecc 1365 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1366 .xlevel = 0x80000008,
1367 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1368 },
1369 {
1370 .name = "Opteron_G3",
1371 .level = 5,
99b88a17 1372 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 1373 .family = 16,
1374 .model = 2,
1375 .stepping = 3,
0514ef2f 1376 .features[FEAT_1_EDX] =
b3a4f0b1 1377 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1378 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1379 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1380 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1381 CPUID_DE | CPUID_FP87,
0514ef2f 1382 .features[FEAT_1_ECX] =
27861ecc 1383 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1384 CPUID_EXT_SSE3,
33b5e8c0 1385 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1386 .features[FEAT_8000_0001_EDX] =
2a923a29 1387 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1388 .features[FEAT_8000_0001_ECX] =
27861ecc 1389 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1390 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1391 .xlevel = 0x80000008,
1392 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1393 },
1394 {
1395 .name = "Opteron_G4",
1396 .level = 0xd,
99b88a17 1397 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1398 .family = 21,
1399 .model = 1,
1400 .stepping = 2,
0514ef2f 1401 .features[FEAT_1_EDX] =
b3a4f0b1 1402 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1403 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1404 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1405 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1406 CPUID_DE | CPUID_FP87,
0514ef2f 1407 .features[FEAT_1_ECX] =
27861ecc 1408 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1409 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1410 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1411 CPUID_EXT_SSE3,
33b5e8c0 1412 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1413 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1414 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1415 CPUID_EXT2_SYSCALL,
0514ef2f 1416 .features[FEAT_8000_0001_ECX] =
27861ecc 1417 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1418 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1419 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1420 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1421 /* no xsaveopt! */
3eca4642
EH		 1422 .xlevel = 0x8000001A,
1423 .model_id = "AMD Opteron 62xx class CPU",
1424 },
021941b9
AP		 1425 {
1426 .name = "Opteron_G5",
1427 .level = 0xd,
99b88a17 1428 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1429 .family = 21,
1430 .model = 2,
1431 .stepping = 0,
0514ef2f 1432 .features[FEAT_1_EDX] =
b3a4f0b1 1433 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1434 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1435 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1436 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1437 CPUID_DE | CPUID_FP87,
0514ef2f 1438 .features[FEAT_1_ECX] =
27861ecc 1439 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1440 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1441 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1442 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1443 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1444 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1445 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1446 CPUID_EXT2_SYSCALL,
0514ef2f 1447 .features[FEAT_8000_0001_ECX] =
27861ecc 1448 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1449 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1450 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1451 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1452 /* no xsaveopt! */
021941b9
AP		 1453 .xlevel = 0x8000001A,
1454 .model_id = "AMD Opteron 63xx class CPU",
1455 },
c6dc6f63
AP		 1456};
1457
5114e842
EH		 1458typedef struct PropValue {
1459 const char *prop, *value;
1460} PropValue;
1461
1462/* KVM-specific features that are automatically added/removed
1463 * from all CPU models when KVM is enabled.
1464 */
1465static PropValue kvm_default_props[] = {
1466 { "kvmclock", "on" },
1467 { "kvm-nopiodelay", "on" },
1468 { "kvm-asyncpf", "on" },
1469 { "kvm-steal-time", "on" },
1470 { "kvm-pv-eoi", "on" },
1471 { "kvmclock-stable-bit", "on" },
1472 { "x2apic", "on" },
1473 { "acpi", "off" },
1474 { "monitor", "off" },
1475 { "svm", "off" },
1476 { NULL, NULL },
1477};
1478
04d99c3c
EH		 1479/* TCG-specific defaults that override all CPU models when using TCG
1480 */
1481static PropValue tcg_default_props[] = {
1482 { "vme", "off" },
1483 { NULL, NULL },
1484};
1485
1486
5114e842
EH		 1487void x86_cpu_change_kvm_default(const char *prop, const char *value)
1488{
1489 PropValue *pv;
1490 for (pv = kvm_default_props; pv->prop; pv++) {
1491 if (!strcmp(pv->prop, prop)) {
1492 pv->value = value;
1493 break;
1494 }
1495 }
1496
1497 /* It is valid to call this function only for properties that
1498 * are already present in the kvm_default_props table.
1499 */
1500 assert(pv->prop);
1501}
1502
4d1b279b
EH		 1503static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1504 bool migratable_only);
1505
d940ee9b
EH		 1506#ifdef CONFIG_KVM
1507
40bfe48f
HZ		 1508static bool lmce_supported(void)
1509{
1510 uint64_t mce_cap;
1511
1512 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1513 return false;
1514 }
1515
1516 return !!(mce_cap & MCG_LMCE_P);
1517}
1518
c6dc6f63
AP		 1519static int cpu_x86_fill_model_id(char *str)
1520{
1521 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1522 int i;
1523
1524 for (i = 0; i < 3; i++) {
1525 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1526 memcpy(str + i * 16 + 0, &eax, 4);
1527 memcpy(str + i * 16 + 4, &ebx, 4);
1528 memcpy(str + i * 16 + 8, &ecx, 4);
1529 memcpy(str + i * 16 + 12, &edx, 4);
1530 }
1531 return 0;
1532}
1533
d940ee9b
EH		 1534static X86CPUDefinition host_cpudef;
1535
84f1b92f 1536static Property host_x86_cpu_properties[] = {
120eee7d 1537 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1538 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1539 DEFINE_PROP_END_OF_LIST()
1540};
1541
d940ee9b 1542/* class_init for the "host" CPU model
6e746f30 1543 *
d940ee9b 1544 * This function may be called before KVM is initialized.
6e746f30 1545 */
d940ee9b 1546static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1547{
84f1b92f 1548 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1549 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1550 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1551
d940ee9b 1552 xcc->kvm_required = true;
6e746f30 1553
c6dc6f63 1554 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1555 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1556
1557 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1558 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1559 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1560 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1561
d940ee9b 1562 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1563
d940ee9b 1564 xcc->cpu_def = &host_cpudef;
ee465a3e
EH		 1565 xcc->model_description =
1566 "KVM processor with all supported host features "
1567 "(only available in KVM mode)";
d940ee9b
EH		 1568
1569 /* level, xlevel, xlevel2, and the feature words are initialized on
1570 * instance_init, because they require KVM to be initialized.
1571 */
84f1b92f
EH		 1572
1573 dc->props = host_x86_cpu_properties;
4c315c27
MA		 1574 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1575 dc->cannot_destroy_with_object_finalize_yet = true;
d940ee9b
EH		 1576}
1577
1578static void host_x86_cpu_initfn(Object *obj)
1579{
1580 X86CPU *cpu = X86_CPU(obj);
1581 CPUX86State *env = &cpu->env;
1582 KVMState *s = kvm_state;
d940ee9b 1583
4d1b279b
EH		 1584 /* We can't fill the features array here because we don't know yet if
1585 * "migratable" is true or false.
1586 */
1587 cpu->host_features = true;
1588
104494ea 1589 /* If KVM is disabled, x86_cpu_realizefn() will report an error later */
e4356010 1590 if (kvm_enabled()) {
c39c0edf
EH		 1591 env->cpuid_min_level =
1592 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1593 env->cpuid_min_xlevel =
1594 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1595 env->cpuid_min_xlevel2 =
1596 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
40bfe48f
HZ		 1597
1598 if (lmce_supported()) {
1599 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1600 }
e4356010 1601 }
2a573259 1602
d940ee9b 1603 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1604}
1605
d940ee9b
EH		 1606static const TypeInfo host_x86_cpu_type_info = {
1607 .name = X86_CPU_TYPE_NAME("host"),
1608 .parent = TYPE_X86_CPU,
1609 .instance_init = host_x86_cpu_initfn,
1610 .class_init = host_x86_cpu_class_init,
1611};
1612
1613#endif
1614
8459e396 1615static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1616{
8459e396 1617 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1618 int i;
1619
857aee33 1620 for (i = 0; i < 32; ++i) {
72370dc1 1621 if ((1UL << i) & mask) {
bffd67b0 1622 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1623 assert(reg);
fefb41bf 1624 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1625 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1626 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1627 f->cpuid_eax, reg,
1628 f->feat_names[i] ? "." : "",
1629 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1630 }
857aee33 1631 }
c6dc6f63
AP		 1632}
1633
d7bce999
EB		 1634static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1635 const char *name, void *opaque,
1636 Error **errp)
95b8519d
AF		 1637{
1638 X86CPU *cpu = X86_CPU(obj);
1639 CPUX86State *env = &cpu->env;
1640 int64_t value;
1641
1642 value = (env->cpuid_version >> 8) & 0xf;
1643 if (value == 0xf) {
1644 value += (env->cpuid_version >> 20) & 0xff;
1645 }
51e72bc1 1646 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1647}
1648
d7bce999
EB		 1649static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1650 const char *name, void *opaque,
1651 Error **errp)
ed5e1ec3 1652{
71ad61d3
AF		 1653 X86CPU *cpu = X86_CPU(obj);
1654 CPUX86State *env = &cpu->env;
1655 const int64_t min = 0;
1656 const int64_t max = 0xff + 0xf;
65cd9064 1657 Error *local_err = NULL;
71ad61d3
AF		 1658 int64_t value;
1659
51e72bc1 1660 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1661 if (local_err) {
1662 error_propagate(errp, local_err);
71ad61d3
AF		 1663 return;
1664 }
1665 if (value < min || value > max) {
c6bd8c70
MA		 1666 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1667 name ? name : "null", value, min, max);
71ad61d3
AF		 1668 return;
1669 }
1670
ed5e1ec3 1671 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1672 if (value > 0x0f) {
1673 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1674 } else {
71ad61d3 1675 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1676 }
1677}
1678
d7bce999
EB		 1679static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1680 const char *name, void *opaque,
1681 Error **errp)
67e30c83
AF		 1682{
1683 X86CPU *cpu = X86_CPU(obj);
1684 CPUX86State *env = &cpu->env;
1685 int64_t value;
1686
1687 value = (env->cpuid_version >> 4) & 0xf;
1688 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1689 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1690}
1691
d7bce999
EB		 1692static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1693 const char *name, void *opaque,
1694 Error **errp)
b0704cbd 1695{
c5291a4f
AF		 1696 X86CPU *cpu = X86_CPU(obj);
1697 CPUX86State *env = &cpu->env;
1698 const int64_t min = 0;
1699 const int64_t max = 0xff;
65cd9064 1700 Error *local_err = NULL;
c5291a4f
AF		 1701 int64_t value;
1702
51e72bc1 1703 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1704 if (local_err) {
1705 error_propagate(errp, local_err);
c5291a4f
AF		 1706 return;
1707 }
1708 if (value < min || value > max) {
c6bd8c70
MA		 1709 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1710 name ? name : "null", value, min, max);
c5291a4f
AF		 1711 return;
1712 }
1713
b0704cbd 1714 env->cpuid_version &= ~0xf00f0;
c5291a4f 1715 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1716}
1717
35112e41 1718static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1719 const char *name, void *opaque,
35112e41
AF		 1720 Error **errp)
1721{
1722 X86CPU *cpu = X86_CPU(obj);
1723 CPUX86State *env = &cpu->env;
1724 int64_t value;
1725
1726 value = env->cpuid_version & 0xf;
51e72bc1 1727 visit_type_int(v, name, &value, errp);
35112e41
AF		 1728}
1729
036e2222 1730static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1731 const char *name, void *opaque,
036e2222 1732 Error **errp)
38c3dc46 1733{
036e2222
AF		 1734 X86CPU *cpu = X86_CPU(obj);
1735 CPUX86State *env = &cpu->env;
1736 const int64_t min = 0;
1737 const int64_t max = 0xf;
65cd9064 1738 Error *local_err = NULL;
036e2222
AF		 1739 int64_t value;
1740
51e72bc1 1741 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1742 if (local_err) {
1743 error_propagate(errp, local_err);
036e2222
AF		 1744 return;
1745 }
1746 if (value < min || value > max) {
c6bd8c70
MA		 1747 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1748 name ? name : "null", value, min, max);
036e2222
AF		 1749 return;
1750 }
1751
38c3dc46 1752 env->cpuid_version &= ~0xf;
036e2222 1753 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1754}
1755
d480e1af
AF		 1756static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1757{
1758 X86CPU *cpu = X86_CPU(obj);
1759 CPUX86State *env = &cpu->env;
1760 char *value;
d480e1af 1761
e42a92ae 1762 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1763 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1764 env->cpuid_vendor3);
d480e1af
AF		 1765 return value;
1766}
1767
1768static void x86_cpuid_set_vendor(Object *obj, const char *value,
1769 Error **errp)
1770{
1771 X86CPU *cpu = X86_CPU(obj);
1772 CPUX86State *env = &cpu->env;
1773 int i;
1774
9df694ee 1775 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1776 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1777 return;
1778 }
1779
1780 env->cpuid_vendor1 = 0;
1781 env->cpuid_vendor2 = 0;
1782 env->cpuid_vendor3 = 0;
1783 for (i = 0; i < 4; i++) {
1784 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1785 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1786 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1787 }
d480e1af
AF		 1788}
1789
63e886eb
AF		 1790static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1791{
1792 X86CPU *cpu = X86_CPU(obj);
1793 CPUX86State *env = &cpu->env;
1794 char *value;
1795 int i;
1796
1797 value = g_malloc(48 + 1);
1798 for (i = 0; i < 48; i++) {
1799 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1800 }
1801 value[48] = '\0';
1802 return value;
1803}
1804
938d4c25
AF		 1805static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1806 Error **errp)
dcce6675 1807{
938d4c25
AF		 1808 X86CPU *cpu = X86_CPU(obj);
1809 CPUX86State *env = &cpu->env;
dcce6675
AF		 1810 int c, len, i;
1811
1812 if (model_id == NULL) {
1813 model_id = "";
1814 }
1815 len = strlen(model_id);
d0a6acf4 1816 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1817 for (i = 0; i < 48; i++) {
1818 if (i >= len) {
1819 c = '\0';
1820 } else {
1821 c = (uint8_t)model_id[i];
1822 }
1823 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1824 }
1825}
1826
d7bce999
EB		 1827static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1828 void *opaque, Error **errp)
89e48965
AF		 1829{
1830 X86CPU *cpu = X86_CPU(obj);
1831 int64_t value;
1832
1833 value = cpu->env.tsc_khz * 1000;
51e72bc1 1834 visit_type_int(v, name, &value, errp);
89e48965
AF		 1835}
1836
d7bce999
EB		 1837static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1838 void *opaque, Error **errp)
89e48965
AF		 1839{
1840 X86CPU *cpu = X86_CPU(obj);
1841 const int64_t min = 0;
2e84849a 1842 const int64_t max = INT64_MAX;
65cd9064 1843 Error *local_err = NULL;
89e48965
AF		 1844 int64_t value;
1845
51e72bc1 1846 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1847 if (local_err) {
1848 error_propagate(errp, local_err);
89e48965
AF		 1849 return;
1850 }
1851 if (value < min || value > max) {
c6bd8c70
MA		 1852 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1853 name ? name : "null", value, min, max);
89e48965
AF		 1854 return;
1855 }
1856
36f96c4b 1857 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1858}
1859
7e5292b5 1860/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1861static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1862 const char *name, void *opaque,
1863 Error **errp)
8e8aba50 1864{
7e5292b5 1865 uint32_t *array = (uint32_t *)opaque;
8e8aba50 1866 FeatureWord w;
8e8aba50
EH		 1867 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1868 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1869 X86CPUFeatureWordInfoList *list = NULL;
1870
1871 for (w = 0; w < FEATURE_WORDS; w++) {
1872 FeatureWordInfo *wi = &feature_word_info[w];
1873 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1874 qwi->cpuid_input_eax = wi->cpuid_eax;
1875 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1876 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1877 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1878 qwi->features = array[w];
8e8aba50
EH		 1879
1880 /* List will be in reverse order, but order shouldn't matter */
1881 list_entries[w].next = list;
1882 list_entries[w].value = &word_infos[w];
1883 list = &list_entries[w];
1884 }
1885
6b62d961 1886 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 1887}
1888
d7bce999
EB		 1889static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1890 void *opaque, Error **errp)
c8f0f88e
IM		 1891{
1892 X86CPU *cpu = X86_CPU(obj);
1893 int64_t value = cpu->hyperv_spinlock_attempts;
1894
51e72bc1 1895 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1896}
1897
d7bce999
EB		 1898static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1899 void *opaque, Error **errp)
c8f0f88e
IM		 1900{
1901 const int64_t min = 0xFFF;
1902 const int64_t max = UINT_MAX;
1903 X86CPU *cpu = X86_CPU(obj);
1904 Error *err = NULL;
1905 int64_t value;
1906
51e72bc1 1907 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1908 if (err) {
1909 error_propagate(errp, err);
1910 return;
1911 }
1912
1913 if (value < min || value > max) {
1914 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1915 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1916 object_get_typename(obj), name ? name : "null",
1917 value, min, max);
c8f0f88e
IM		 1918 return;
1919 }
1920 cpu->hyperv_spinlock_attempts = value;
1921}
1922
1923static PropertyInfo qdev_prop_spinlocks = {
1924 .name = "int",
1925 .get = x86_get_hv_spinlocks,
1926 .set = x86_set_hv_spinlocks,
1927};
1928
72ac2e87
IM		 1929/* Convert all '_' in a feature string option name to '-', to make feature
1930 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1931 */
1932static inline void feat2prop(char *s)
1933{
1934 while ((s = strchr(s, '_'))) {
1935 *s = '-';
1936 }
1937}
1938
b54c9377
EH		 1939/* Return the feature property name for a feature flag bit */
1940static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
1941{
1942 /* XSAVE components are automatically enabled by other features,
1943 * so return the original feature name instead
1944 */
1945 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
1946 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
1947
1948 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
1949 x86_ext_save_areas[comp].bits) {
1950 w = x86_ext_save_areas[comp].feature;
1951 bitnr = ctz32(x86_ext_save_areas[comp].bits);
1952 }
1953 }
1954
1955 assert(bitnr < 32);
1956 assert(w < FEATURE_WORDS);
1957 return feature_word_info[w].feat_names[bitnr];
1958}
1959
dc15c051
IM		 1960/* Compatibily hack to maintain legacy +-feat semantic,
1961 * where +-feat overwrites any feature set by
1962 * feat=on|feat even if the later is parsed after +-feat
1963 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
1964 */
2fae0d96 1965static GList *plus_features, *minus_features;
dc15c051 1966
83a00f60
EH		 1967static gint compare_string(gconstpointer a, gconstpointer b)
1968{
1969 return g_strcmp0(a, b);
1970}
1971
8f961357
EH		 1972/* Parse "+feature,-feature,feature=foo" CPU feature string
1973 */
62a48a2a 1974static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 1975 Error **errp)
8f961357 1976{
8f961357 1977 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 1978 static bool cpu_globals_initialized;
83a00f60 1979 bool ambiguous = false;
62a48a2a
IM		 1980
1981 if (cpu_globals_initialized) {
1982 return;
1983 }
1984 cpu_globals_initialized = true;
8f961357 1985
f6750e95
EH		 1986 if (!features) {
1987 return;
1988 }
1989
1990 for (featurestr = strtok(features, ",");
685479bd 1991 featurestr;
f6750e95
EH		 1992 featurestr = strtok(NULL, ",")) {
1993 const char *name;
1994 const char *val = NULL;
1995 char *eq = NULL;
cf2887c9 1996 char num[32];
62a48a2a 1997 GlobalProperty *prop;
c6dc6f63 1998
f6750e95 1999 /* Compatibility syntax: */
c6dc6f63 2000 if (featurestr[0] == '+') {
2fae0d96
EH		 2001 plus_features = g_list_append(plus_features,
2002 g_strdup(featurestr + 1));
f6750e95 2003 continue;
c6dc6f63 2004 } else if (featurestr[0] == '-') {
2fae0d96
EH		 2005 minus_features = g_list_append(minus_features,
2006 g_strdup(featurestr + 1));
f6750e95
EH		 2007 continue;
2008 }
2009
2010 eq = strchr(featurestr, '=');
2011 if (eq) {
2012 *eq++ = 0;
2013 val = eq;
c6dc6f63 2014 } else {
f6750e95 2015 val = "on";
a91987c2 2016 }
f6750e95
EH		 2017
2018 feat2prop(featurestr);
2019 name = featurestr;
2020
83a00f60
EH		 2021 if (g_list_find_custom(plus_features, name, compare_string)) {
2022 error_report("warning: Ambiguous CPU model string. "
2023 "Don't mix both \"+%s\" and \"%s=%s\"",
2024 name, name, val);
2025 ambiguous = true;
2026 }
2027 if (g_list_find_custom(minus_features, name, compare_string)) {
2028 error_report("warning: Ambiguous CPU model string. "
2029 "Don't mix both \"-%s\" and \"%s=%s\"",
2030 name, name, val);
2031 ambiguous = true;
2032 }
2033
f6750e95
EH		 2034 /* Special case: */
2035 if (!strcmp(name, "tsc-freq")) {
2036 int64_t tsc_freq;
2037 char *err;
f6750e95
EH		 2038
2039 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
2040 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
2041 if (tsc_freq < 0 || *err) {
2042 error_setg(errp, "bad numerical value %s", val);
2043 return;
2044 }
2045 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2046 val = num;
2047 name = "tsc-frequency";
c6dc6f63 2048 }
f6750e95 2049
62a48a2a
IM		 2050 prop = g_new0(typeof(*prop), 1);
2051 prop->driver = typename;
2052 prop->property = g_strdup(name);
2053 prop->value = g_strdup(val);
2054 prop->errp = &error_fatal;
2055 qdev_prop_register_global(prop);
f6750e95
EH		 2056 }
2057
83a00f60
EH		 2058 if (ambiguous) {
2059 error_report("warning: Compatibility of ambiguous CPU model "
2060 "strings won't be kept on future QEMU versions");
2061 }
c6dc6f63
AP		 2062}
2063
b54c9377
EH		 2064static void x86_cpu_load_features(X86CPU *cpu, Error **errp);
2065static int x86_cpu_filter_features(X86CPU *cpu);
2066
2067/* Check for missing features that may prevent the CPU class from
2068 * running using the current machine and accelerator.
2069 */
2070static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
2071 strList **missing_feats)
2072{
2073 X86CPU *xc;
2074 FeatureWord w;
2075 Error *err = NULL;
2076 strList **next = missing_feats;
2077
2078 if (xcc->kvm_required && !kvm_enabled()) {
2079 strList *new = g_new0(strList, 1);
2080 new->value = g_strdup("kvm");;
2081 *missing_feats = new;
2082 return;
2083 }
2084
2085 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2086
2087 x86_cpu_load_features(xc, &err);
2088 if (err) {
2089 /* Errors at x86_cpu_load_features should never happen,
2090 * but in case it does, just report the model as not
2091 * runnable at all using the "type" property.
2092 */
2093 strList *new = g_new0(strList, 1);
2094 new->value = g_strdup("type");
2095 *next = new;
2096 next = &new->next;
2097 }
2098
2099 x86_cpu_filter_features(xc);
2100
2101 for (w = 0; w < FEATURE_WORDS; w++) {
2102 uint32_t filtered = xc->filtered_features[w];
2103 int i;
2104 for (i = 0; i < 32; i++) {
2105 if (filtered & (1UL << i)) {
2106 strList *new = g_new0(strList, 1);
2107 new->value = g_strdup(x86_cpu_feature_name(w, i));
2108 *next = new;
2109 next = &new->next;
2110 }
2111 }
2112 }
2113
2114 object_unref(OBJECT(xc));
2115}
2116
8c3329e5 2117/* Print all cpuid feature names in featureset
c6dc6f63 2118 */
8c3329e5 2119static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2120{
8c3329e5
EH		 2121 int bit;
2122 bool first = true;
2123
2124 for (bit = 0; bit < 32; bit++) {
2125 if (featureset[bit]) {
2126 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2127 first = false;
c6dc6f63 2128 }
8c3329e5 2129 }
c6dc6f63
AP		 2130}
2131
ee465a3e
EH		 2132/* Sort alphabetically by type name, listing kvm_required models last. */
2133static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
2134{
2135 ObjectClass *class_a = (ObjectClass *)a;
2136 ObjectClass *class_b = (ObjectClass *)b;
2137 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
2138 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
2139 const char *name_a, *name_b;
2140
2141 if (cc_a->kvm_required != cc_b->kvm_required) {
2142 /* kvm_required items go last */
2143 return cc_a->kvm_required ? 1 : -1;
2144 } else {
2145 name_a = object_class_get_name(class_a);
2146 name_b = object_class_get_name(class_b);
2147 return strcmp(name_a, name_b);
2148 }
2149}
2150
2151static GSList *get_sorted_cpu_model_list(void)
2152{
2153 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
2154 list = g_slist_sort(list, x86_cpu_list_compare);
2155 return list;
2156}
2157
2158static void x86_cpu_list_entry(gpointer data, gpointer user_data)
2159{
2160 ObjectClass *oc = data;
2161 X86CPUClass *cc = X86_CPU_CLASS(oc);
2162 CPUListState *s = user_data;
2163 char *name = x86_cpu_class_get_model_name(cc);
2164 const char *desc = cc->model_description;
2165 if (!desc) {
2166 desc = cc->cpu_def->model_id;
2167 }
2168
2169 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
2170 name, desc);
2171 g_free(name);
2172}
2173
2174/* list available CPU models and flags */
e916cbf8 2175void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2176{
7fc9b714 2177 int i;
ee465a3e
EH		 2178 CPUListState s = {
2179 .file = f,
2180 .cpu_fprintf = cpu_fprintf,
2181 };
2182 GSList *list;
c6dc6f63 2183
ee465a3e
EH		 2184 (*cpu_fprintf)(f, "Available CPUs:\n");
2185 list = get_sorted_cpu_model_list();
2186 g_slist_foreach(list, x86_cpu_list_entry, &s);
2187 g_slist_free(list);
21ad7789 2188
6cdf8854 2189 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2190 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2191 FeatureWordInfo *fw = &feature_word_info[i];
2192
8c3329e5
EH		 2193 (*cpu_fprintf)(f, " ");
2194 listflags(f, cpu_fprintf, fw->feat_names);
2195 (*cpu_fprintf)(f, "\n");
3af60be2 2196 }
c6dc6f63
AP		 2197}
2198
ee465a3e
EH		 2199static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
2200{
2201 ObjectClass *oc = data;
2202 X86CPUClass *cc = X86_CPU_CLASS(oc);
2203 CpuDefinitionInfoList **cpu_list = user_data;
2204 CpuDefinitionInfoList *entry;
2205 CpuDefinitionInfo *info;
2206
2207 info = g_malloc0(sizeof(*info));
2208 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 2209 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
2210 info->has_unavailable_features = true;
8ed877b7 2211 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 2212 info->migration_safe = cc->migration_safe;
2213 info->has_migration_safe = true;
ee465a3e
EH		 2214
2215 entry = g_malloc0(sizeof(*entry));
2216 entry->value = info;
2217 entry->next = *cpu_list;
2218 *cpu_list = entry;
2219}
2220
76b64a7a 2221CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2222{
2223 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 2224 GSList *list = get_sorted_cpu_model_list();
2225 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
2226 g_slist_free(list);
e3966126
AL		 2227 return cpu_list;
2228}
2229
84f1b92f
EH		 2230static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2231 bool migratable_only)
27418adf
EH		 2232{
2233 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2234 uint32_t r;
27418adf 2235
fefb41bf 2236 if (kvm_enabled()) {
84f1b92f
EH		 2237 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2238 wi->cpuid_ecx,
2239 wi->cpuid_reg);
fefb41bf 2240 } else if (tcg_enabled()) {
84f1b92f 2241 r = wi->tcg_features;
fefb41bf
EH		 2242 } else {
2243 return ~0;
2244 }
84f1b92f
EH		 2245 if (migratable_only) {
2246 r &= x86_cpu_get_migratable_flags(w);
2247 }
2248 return r;
27418adf
EH		 2249}
2250
51f63aed
EH		 2251/*
2252 * Filters CPU feature words based on host availability of each feature.
2253 *
51f63aed
EH		 2254 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2255 */
27418adf 2256static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2257{
2258 CPUX86State *env = &cpu->env;
bd87d2a2 2259 FeatureWord w;
51f63aed
EH		 2260 int rv = 0;
2261
bd87d2a2 2262 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f 2263 uint32_t host_feat =
46c032f3 2264 x86_cpu_get_supported_feature_word(w, false);
034acf4a
EH		 2265 uint32_t requested_features = env->features[w];
2266 env->features[w] &= host_feat;
2267 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed 2268 if (cpu->filtered_features[w]) {
51f63aed
EH		 2269 rv = 1;
2270 }
bd87d2a2 2271 }
51f63aed
EH		 2272
2273 return rv;
bc74b7db 2274}
bc74b7db 2275
8ca30e86
EH		 2276static void x86_cpu_report_filtered_features(X86CPU *cpu)
2277{
2278 FeatureWord w;
2279
2280 for (w = 0; w < FEATURE_WORDS; w++) {
2281 report_unavailable_features(w, cpu->filtered_features[w]);
2282 }
2283}
2284
5114e842
EH		 2285static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2286{
2287 PropValue *pv;
2288 for (pv = props; pv->prop; pv++) {
2289 if (!pv->value) {
2290 continue;
2291 }
2292 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2293 &error_abort);
2294 }
2295}
2296
d940ee9b 2297/* Load data from X86CPUDefinition
c080e30e 2298 */
d940ee9b 2299static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2300{
61dcd775 2301 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2302 const char *vendor;
2303 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2304 FeatureWord w;
c6dc6f63 2305
c39c0edf
EH		 2306 /* CPU models only set _minimum_ values for level/xlevel: */
2307 object_property_set_int(OBJECT(cpu), def->level, "min-level", errp);
2308 object_property_set_int(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
2309
2d64255b
AF		 2310 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2311 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2312 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2313 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2314 for (w = 0; w < FEATURE_WORDS; w++) {
2315 env->features[w] = def->features[w];
2316 }
82beb536 2317
9576de75 2318 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2319 if (kvm_enabled()) {
492a4c94
LT		 2320 if (!kvm_irqchip_in_kernel()) {
2321 x86_cpu_change_kvm_default("x2apic", "off");
2322 }
2323
5114e842 2324 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 2325 } else if (tcg_enabled()) {
2326 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 2327 }
5fcca9ff 2328
82beb536 2329 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2330
2331 /* sysenter isn't supported in compatibility mode on AMD,
2332 * syscall isn't supported in compatibility mode on Intel.
2333 * Normally we advertise the actual CPU vendor, but you can
2334 * override this using the 'vendor' property if you want to use
2335 * KVM's sysenter/syscall emulation in compatibility mode and
2336 * when doing cross vendor migration
2337 */
74f54bc4 2338 vendor = def->vendor;
7c08db30
EH		 2339 if (kvm_enabled()) {
2340 uint32_t ebx = 0, ecx = 0, edx = 0;
2341 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2342 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2343 vendor = host_vendor;
2344 }
2345
2346 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2347
c6dc6f63
AP		 2348}
2349
0856579c 2350X86CPU *cpu_x86_init(const char *cpu_model)
7f833247 2351{
a57d0163 2352 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
5c3c6a68
AF		 2353}
2354
d940ee9b
EH		 2355static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2356{
2357 X86CPUDefinition *cpudef = data;
2358 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2359
2360 xcc->cpu_def = cpudef;
bd72159d 2361 xcc->migration_safe = true;
d940ee9b
EH		 2362}
2363
2364static void x86_register_cpudef_type(X86CPUDefinition *def)
2365{
2366 char *typename = x86_cpu_type_name(def->name);
2367 TypeInfo ti = {
2368 .name = typename,
2369 .parent = TYPE_X86_CPU,
2370 .class_init = x86_cpu_cpudef_class_init,
2371 .class_data = def,
2372 };
2373
2a923a29
EH		 2374 /* AMD aliases are handled at runtime based on CPUID vendor, so
2375 * they shouldn't be set on the CPU model table.
2376 */
2377 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
2378
d940ee9b
EH		 2379 type_register(&ti);
2380 g_free(typename);
2381}
2382
c6dc6f63 2383#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2384
0e26b7b8
BS		 2385void cpu_clear_apic_feature(CPUX86State *env)
2386{
0514ef2f 2387 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2388}
2389
c6dc6f63
AP		 2390#endif /* !CONFIG_USER_ONLY */
2391
c6dc6f63
AP		 2392void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2393 uint32_t *eax, uint32_t *ebx,
2394 uint32_t *ecx, uint32_t *edx)
2395{
a60f24b5
AF		 2396 X86CPU *cpu = x86_env_get_cpu(env);
2397 CPUState *cs = CPU(cpu);
14c985cf 2398 uint32_t pkg_offset;
a60f24b5 2399
c6dc6f63
AP		 2400 /* test if maximum index reached */
2401 if (index & 0x80000000) {
b3baa152
BW		 2402 if (index > env->cpuid_xlevel) {
2403 if (env->cpuid_xlevel2 > 0) {
2404 /* Handle the Centaur's CPUID instruction. */
2405 if (index > env->cpuid_xlevel2) {
2406 index = env->cpuid_xlevel2;
2407 } else if (index < 0xC0000000) {
2408 index = env->cpuid_xlevel;
2409 }
2410 } else {
57f26ae7
EH		 2411 /* Intel documentation states that invalid EAX input will
2412 * return the same information as EAX=cpuid_level
2413 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2414 */
2415 index = env->cpuid_level;
b3baa152
BW		 2416 }
2417 }
c6dc6f63
AP		 2418 } else {
2419 if (index > env->cpuid_level)
2420 index = env->cpuid_level;
2421 }
2422
2423 switch(index) {
2424 case 0:
2425 *eax = env->cpuid_level;
5eb2f7a4
EH		 2426 *ebx = env->cpuid_vendor1;
2427 *edx = env->cpuid_vendor2;
2428 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2429 break;
2430 case 1:
2431 *eax = env->cpuid_version;
7e72a45c
EH		 2432 *ebx = (cpu->apic_id << 24) |
2433 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2434 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2435 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2436 *ecx |= CPUID_EXT_OSXSAVE;
2437 }
0514ef2f 2438 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2439 if (cs->nr_cores * cs->nr_threads > 1) {
2440 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2441 *edx |= CPUID_HT;
c6dc6f63
AP		 2442 }
2443 break;
2444 case 2:
2445 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2446 if (cpu->cache_info_passthrough) {
2447 host_cpuid(index, 0, eax, ebx, ecx, edx);
2448 break;
2449 }
5e891bf8 2450 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 2451 *ebx = 0;
14c985cf
LM		 2452 if (!cpu->enable_l3_cache) {
2453 *ecx = 0;
2454 } else {
2455 *ecx = L3_N_DESCRIPTOR;
2456 }
5e891bf8
EH		 2457 *edx = (L1D_DESCRIPTOR << 16) | \
2458 (L1I_DESCRIPTOR << 8) | \
2459 (L2_DESCRIPTOR);
c6dc6f63
AP		 2460 break;
2461 case 4:
2462 /* cache info: needed for Core compatibility */
787aaf57
BC		 2463 if (cpu->cache_info_passthrough) {
2464 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2465 *eax &= ~0xFC000000;
c6dc6f63 2466 } else {
2f7a21c4 2467 *eax = 0;
76c2975a 2468 switch (count) {
c6dc6f63 2469 case 0: /* L1 dcache info */
5e891bf8
EH		 2470 *eax |= CPUID_4_TYPE_DCACHE | \
2471 CPUID_4_LEVEL(1) | \
2472 CPUID_4_SELF_INIT_LEVEL;
2473 *ebx = (L1D_LINE_SIZE - 1) | \
2474 ((L1D_PARTITIONS - 1) << 12) | \
2475 ((L1D_ASSOCIATIVITY - 1) << 22);
2476 *ecx = L1D_SETS - 1;
2477 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2478 break;
2479 case 1: /* L1 icache info */
5e891bf8
EH		 2480 *eax |= CPUID_4_TYPE_ICACHE | \
2481 CPUID_4_LEVEL(1) | \
2482 CPUID_4_SELF_INIT_LEVEL;
2483 *ebx = (L1I_LINE_SIZE - 1) | \
2484 ((L1I_PARTITIONS - 1) << 12) | \
2485 ((L1I_ASSOCIATIVITY - 1) << 22);
2486 *ecx = L1I_SETS - 1;
2487 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2488 break;
2489 case 2: /* L2 cache info */
5e891bf8
EH		 2490 *eax |= CPUID_4_TYPE_UNIFIED | \
2491 CPUID_4_LEVEL(2) | \
2492 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2493 if (cs->nr_threads > 1) {
2494 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2495 }
5e891bf8
EH		 2496 *ebx = (L2_LINE_SIZE - 1) | \
2497 ((L2_PARTITIONS - 1) << 12) | \
2498 ((L2_ASSOCIATIVITY - 1) << 22);
2499 *ecx = L2_SETS - 1;
2500 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63 2501 break;
14c985cf
LM		 2502 case 3: /* L3 cache info */
2503 if (!cpu->enable_l3_cache) {
2504 *eax = 0;
2505 *ebx = 0;
2506 *ecx = 0;
2507 *edx = 0;
2508 break;
2509 }
2510 *eax |= CPUID_4_TYPE_UNIFIED | \
2511 CPUID_4_LEVEL(3) | \
2512 CPUID_4_SELF_INIT_LEVEL;
2513 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2514 *eax |= ((1 << pkg_offset) - 1) << 14;
2515 *ebx = (L3_N_LINE_SIZE - 1) | \
2516 ((L3_N_PARTITIONS - 1) << 12) | \
2517 ((L3_N_ASSOCIATIVITY - 1) << 22);
2518 *ecx = L3_N_SETS - 1;
2519 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2520 break;
c6dc6f63
AP		 2521 default: /* end of info */
2522 *eax = 0;
2523 *ebx = 0;
2524 *ecx = 0;
2525 *edx = 0;
2526 break;
76c2975a
PB		 2527 }
2528 }
2529
2530 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2531 if ((*eax & 31) && cs->nr_cores > 1) {
2532 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2533 }
2534 break;
2535 case 5:
2536 /* mwait info: needed for Core compatibility */
2537 *eax = 0; /* Smallest monitor-line size in bytes */
2538 *ebx = 0; /* Largest monitor-line size in bytes */
2539 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2540 *edx = 0;
2541 break;
2542 case 6:
2543 /* Thermal and Power Leaf */
28b8e4d0 2544 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2545 *ebx = 0;
2546 *ecx = 0;
2547 *edx = 0;
2548 break;
f7911686 2549 case 7:
13526728
EH		 2550 /* Structured Extended Feature Flags Enumeration Leaf */
2551 if (count == 0) {
2552 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2553 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2554 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2555 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2556 *ecx |= CPUID_7_0_ECX_OSPKE;
2557 }
95ea69fb 2558 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 2559 } else {
2560 *eax = 0;
2561 *ebx = 0;
2562 *ecx = 0;
2563 *edx = 0;
2564 }
2565 break;
c6dc6f63
AP		 2566 case 9:
2567 /* Direct Cache Access Information Leaf */
2568 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2569 *ebx = 0;
2570 *ecx = 0;
2571 *edx = 0;
2572 break;
2573 case 0xA:
2574 /* Architectural Performance Monitoring Leaf */
9337e3b6 2575 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2576 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2577
2578 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2579 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2580 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2581 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2582 } else {
2583 *eax = 0;
2584 *ebx = 0;
2585 *ecx = 0;
2586 *edx = 0;
2587 }
c6dc6f63 2588 break;
5232d00a
RK		 2589 case 0xB:
2590 /* Extended Topology Enumeration Leaf */
2591 if (!cpu->enable_cpuid_0xb) {
2592 *eax = *ebx = *ecx = *edx = 0;
2593 break;
2594 }
2595
2596 *ecx = count & 0xff;
2597 *edx = cpu->apic_id;
2598
2599 switch (count) {
2600 case 0:
eab60fb9
MAL		 2601 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
2602 *ebx = cs->nr_threads;
5232d00a
RK		 2603 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2604 break;
2605 case 1:
eab60fb9
MAL		 2606 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2607 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 2608 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2609 break;
2610 default:
2611 *eax = 0;
2612 *ebx = 0;
2613 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2614 }
2615
2616 assert(!(*eax & ~0x1f));
2617 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2618 break;
2560f19f 2619 case 0xD: {
51e49430 2620 /* Processor Extended State */
2560f19f
PB		 2621 *eax = 0;
2622 *ebx = 0;
2623 *ecx = 0;
2624 *edx = 0;
19dc85db 2625 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2626 break;
2627 }
4928cd6d 2628
2560f19f 2629 if (count == 0) {
96193c22
EH		 2630 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
2631 *eax = env->features[FEAT_XSAVE_COMP_LO];
2632 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 2633 *ebx = *ecx;
2634 } else if (count == 1) {
0bb0b2d2 2635 *eax = env->features[FEAT_XSAVE];
f4f1110e 2636 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 2637 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
2638 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 2639 *eax = esa->size;
2640 *ebx = esa->offset;
2560f19f 2641 }
51e49430
SY		 2642 }
2643 break;
2560f19f 2644 }
c6dc6f63
AP		 2645 case 0x80000000:
2646 *eax = env->cpuid_xlevel;
2647 *ebx = env->cpuid_vendor1;
2648 *edx = env->cpuid_vendor2;
2649 *ecx = env->cpuid_vendor3;
2650 break;
2651 case 0x80000001:
2652 *eax = env->cpuid_version;
2653 *ebx = 0;
0514ef2f
EH		 2654 *ecx = env->features[FEAT_8000_0001_ECX];
2655 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2656
2657 /* The Linux kernel checks for the CMPLegacy bit and
2658 * discards multiple thread information if it is set.
cb8d4c8f 2659 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2660 */
ce3960eb 2661 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2662 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2663 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2664 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2665 *ecx |= 1 << 1; /* CmpLegacy bit */
2666 }
2667 }
c6dc6f63
AP		 2668 break;
2669 case 0x80000002:
2670 case 0x80000003:
2671 case 0x80000004:
2672 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2673 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2674 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2675 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2676 break;
2677 case 0x80000005:
2678 /* cache info (L1 cache) */
787aaf57
BC		 2679 if (cpu->cache_info_passthrough) {
2680 host_cpuid(index, 0, eax, ebx, ecx, edx);
2681 break;
2682 }
5e891bf8
EH		 2683 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2684 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2685 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2686 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2687 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2688 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2689 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2690 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2691 break;
2692 case 0x80000006:
2693 /* cache info (L2 cache) */
787aaf57
BC		 2694 if (cpu->cache_info_passthrough) {
2695 host_cpuid(index, 0, eax, ebx, ecx, edx);
2696 break;
2697 }
5e891bf8
EH		 2698 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2699 (L2_DTLB_2M_ENTRIES << 16) | \
2700 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2701 (L2_ITLB_2M_ENTRIES);
2702 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2703 (L2_DTLB_4K_ENTRIES << 16) | \
2704 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2705 (L2_ITLB_4K_ENTRIES);
2706 *ecx = (L2_SIZE_KB_AMD << 16) | \
2707 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2708 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
14c985cf
LM		 2709 if (!cpu->enable_l3_cache) {
2710 *edx = ((L3_SIZE_KB / 512) << 18) | \
2711 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2712 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2713 } else {
2714 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
2715 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
2716 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
2717 }
c6dc6f63 2718 break;
303752a9
MT		 2719 case 0x80000007:
2720 *eax = 0;
2721 *ebx = 0;
2722 *ecx = 0;
2723 *edx = env->features[FEAT_8000_0007_EDX];
2724 break;
c6dc6f63
AP		 2725 case 0x80000008:
2726 /* virtual & phys address size in low 2 bytes. */
0514ef2f 2727 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 2728 /* 64 bit processor */
2729 *eax = cpu->phys_bits; /* configurable physical bits */
2730 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
2731 *eax |= 0x00003900; /* 57 bits virtual */
2732 } else {
2733 *eax |= 0x00003000; /* 48 bits virtual */
2734 }
c6dc6f63 2735 } else {
af45907a 2736 *eax = cpu->phys_bits;
c6dc6f63
AP		 2737 }
2738 *ebx = 0;
2739 *ecx = 0;
2740 *edx = 0;
ce3960eb
AF		 2741 if (cs->nr_cores * cs->nr_threads > 1) {
2742 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2743 }
2744 break;
2745 case 0x8000000A:
0514ef2f 2746 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2747 *eax = 0x00000001; /* SVM Revision */
2748 *ebx = 0x00000010; /* nr of ASIDs */
2749 *ecx = 0;
0514ef2f 2750 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2751 } else {
2752 *eax = 0;
2753 *ebx = 0;
2754 *ecx = 0;
2755 *edx = 0;
2756 }
c6dc6f63 2757 break;
b3baa152
BW		 2758 case 0xC0000000:
2759 *eax = env->cpuid_xlevel2;
2760 *ebx = 0;
2761 *ecx = 0;
2762 *edx = 0;
2763 break;
2764 case 0xC0000001:
2765 /* Support for VIA CPU's CPUID instruction */
2766 *eax = env->cpuid_version;
2767 *ebx = 0;
2768 *ecx = 0;
0514ef2f 2769 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2770 break;
2771 case 0xC0000002:
2772 case 0xC0000003:
2773 case 0xC0000004:
2774 /* Reserved for the future, and now filled with zero */
2775 *eax = 0;
2776 *ebx = 0;
2777 *ecx = 0;
2778 *edx = 0;
2779 break;
c6dc6f63
AP		 2780 default:
2781 /* reserved values: zero */
2782 *eax = 0;
2783 *ebx = 0;
2784 *ecx = 0;
2785 *edx = 0;
2786 break;
2787 }
2788}
5fd2087a
AF		 2789
2790/* CPUClass::reset() */
2791static void x86_cpu_reset(CPUState *s)
2792{
2793 X86CPU *cpu = X86_CPU(s);
2794 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2795 CPUX86State *env = &cpu->env;
a114d25d
RH		 2796 target_ulong cr4;
2797 uint64_t xcr0;
c1958aea
AF		 2798 int i;
2799
5fd2087a
AF		 2800 xcc->parent_reset(s);
2801
5e992a8e 2802 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 2803
c1958aea
AF		 2804 env->old_exception = -1;
2805
2806 /* init to reset state */
2807
c1958aea
AF		 2808 env->hflags2 |= HF2_GIF_MASK;
2809
2810 cpu_x86_update_cr0(env, 0x60000010);
2811 env->a20_mask = ~0x0;
2812 env->smbase = 0x30000;
2813
2814 env->idt.limit = 0xffff;
2815 env->gdt.limit = 0xffff;
2816 env->ldt.limit = 0xffff;
2817 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2818 env->tr.limit = 0xffff;
2819 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2820
2821 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2822 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2823 DESC_R_MASK | DESC_A_MASK);
2824 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2825 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2826 DESC_A_MASK);
2827 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2828 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2829 DESC_A_MASK);
2830 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2831 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2832 DESC_A_MASK);
2833 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2834 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2835 DESC_A_MASK);
2836 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2837 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2838 DESC_A_MASK);
2839
2840 env->eip = 0xfff0;
2841 env->regs[R_EDX] = env->cpuid_version;
2842
2843 env->eflags = 0x2;
2844
2845 /* FPU init */
2846 for (i = 0; i < 8; i++) {
2847 env->fptags[i] = 1;
2848 }
5bde1407 2849 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2850
2851 env->mxcsr = 0x1f80;
a114d25d
RH		 2852 /* All units are in INIT state. */
2853 env->xstate_bv = 0;
c1958aea
AF		 2854
2855 env->pat = 0x0007040600070406ULL;
2856 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2857
2858 memset(env->dr, 0, sizeof(env->dr));
2859 env->dr[6] = DR6_FIXED_1;
2860 env->dr[7] = DR7_FIXED_1;
b3310ab3 2861 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2862 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2863
a114d25d 2864 cr4 = 0;
cfc3b074 2865 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 2866
2867#ifdef CONFIG_USER_ONLY
2868 /* Enable all the features for user-mode. */
2869 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 2870 xcr0 |= XSTATE_SSE_MASK;
a114d25d 2871 }
0f70ed47
PB		 2872 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2873 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 2874 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 2875 xcr0 |= 1ull << i;
2876 }
a114d25d 2877 }
0f70ed47 2878
a114d25d
RH		 2879 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2880 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2881 }
07929f2a
RH		 2882 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2883 cr4 |= CR4_FSGSBASE_MASK;
2884 }
a114d25d
RH		 2885#endif
2886
2887 env->xcr0 = xcr0;
2888 cpu_x86_update_cr4(env, cr4);
0522604b 2889
9db2efd9
AW		 2890 /*
2891 * SDM 11.11.5 requires:
2892 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2893 * - IA32_MTRR_PHYSMASKn.V = 0
2894 * All other bits are undefined. For simplification, zero it all.
2895 */
2896 env->mtrr_deftype = 0;
2897 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2898 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2899
dd673288
IM		 2900#if !defined(CONFIG_USER_ONLY)
2901 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2902 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2903
259186a7 2904 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2905
2906 if (kvm_enabled()) {
2907 kvm_arch_reset_vcpu(cpu);
2908 }
dd673288 2909#endif
5fd2087a
AF		 2910}
2911
dd673288
IM		 2912#ifndef CONFIG_USER_ONLY
2913bool cpu_is_bsp(X86CPU *cpu)
2914{
02e51483 2915 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2916}
65dee380
IM		 2917
2918/* TODO: remove me, when reset over QOM tree is implemented */
2919static void x86_cpu_machine_reset_cb(void *opaque)
2920{
2921 X86CPU *cpu = opaque;
2922 cpu_reset(CPU(cpu));
2923}
dd673288
IM		 2924#endif
2925
de024815
AF		 2926static void mce_init(X86CPU *cpu)
2927{
2928 CPUX86State *cenv = &cpu->env;
2929 unsigned int bank;
2930
2931 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2932 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 2933 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 2934 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
2935 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 2936 cenv->mcg_ctl = ~(uint64_t)0;
2937 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2938 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2939 }
2940 }
2941}
2942
bdeec802 2943#ifndef CONFIG_USER_ONLY
2f114315 2944APICCommonClass *apic_get_class(void)
bdeec802 2945{
bdeec802
IM		 2946 const char *apic_type = "apic";
2947
15eafc2e 2948 if (kvm_apic_in_kernel()) {
bdeec802
IM		 2949 apic_type = "kvm-apic";
2950 } else if (xen_enabled()) {
2951 apic_type = "xen-apic";
2952 }
2953
2f114315
RK		 2954 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
2955}
2956
2957static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2958{
2959 APICCommonState *apic;
2960 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
2961
2962 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 2963
6816b1b3
IM		 2964 object_property_add_child(OBJECT(cpu), "lapic",
2965 OBJECT(cpu->apic_state), &error_abort);
67e55caa 2966 object_unref(OBJECT(cpu->apic_state));
6816b1b3 2967
33d7a288 2968 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2969 /* TODO: convert to link<> */
02e51483 2970 apic = APIC_COMMON(cpu->apic_state);
60671e58 2971 apic->cpu = cpu;
8d42d2d3 2972 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 2973}
2974
2975static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2976{
8d42d2d3
CF		 2977 APICCommonState *apic;
2978 static bool apic_mmio_map_once;
2979
02e51483 2980 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2981 return;
2982 }
6e8e2651
MA		 2983 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2984 errp);
8d42d2d3
CF		 2985
2986 /* Map APIC MMIO area */
2987 apic = APIC_COMMON(cpu->apic_state);
2988 if (!apic_mmio_map_once) {
2989 memory_region_add_subregion_overlap(get_system_memory(),
2990 apic->apicbase &
2991 MSR_IA32_APICBASE_BASE,
2992 &apic->io_memory,
2993 0x1000);
2994 apic_mmio_map_once = true;
2995 }
bdeec802 2996}
f809c605
PB		 2997
2998static void x86_cpu_machine_done(Notifier *n, void *unused)
2999{
3000 X86CPU *cpu = container_of(n, X86CPU, machine_done);
3001 MemoryRegion *smram =
3002 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
3003
3004 if (smram) {
3005 cpu->smram = g_new(MemoryRegion, 1);
3006 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
3007 smram, 0, 1ull << 32);
3008 memory_region_set_enabled(cpu->smram, false);
3009 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
3010 }
3011}
d3c64d6a
IM		 3012#else
3013static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3014{
3015}
bdeec802
IM		 3016#endif
3017
11f6fee5
DDAG		 3018/* Note: Only safe for use on x86(-64) hosts */
3019static uint32_t x86_host_phys_bits(void)
3020{
3021 uint32_t eax;
3022 uint32_t host_phys_bits;
3023
3024 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
3025 if (eax >= 0x80000008) {
3026 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
3027 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3028 * at 23:16 that can specify a maximum physical address bits for
3029 * the guest that can override this value; but I've not seen
3030 * anything with that set.
3031 */
3032 host_phys_bits = eax & 0xff;
3033 } else {
3034 /* It's an odd 64 bit machine that doesn't have the leaf for
3035 * physical address bits; fall back to 36 that's most older
3036 * Intel.
3037 */
3038 host_phys_bits = 36;
3039 }
3040
3041 return host_phys_bits;
3042}
e48638fd 3043
c39c0edf
EH		 3044static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
3045{
3046 if (*min < value) {
3047 *min = value;
3048 }
3049}
3050
3051/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3052static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
3053{
3054 CPUX86State *env = &cpu->env;
3055 FeatureWordInfo *fi = &feature_word_info[w];
3056 uint32_t eax = fi->cpuid_eax;
3057 uint32_t region = eax & 0xF0000000;
3058
3059 if (!env->features[w]) {
3060 return;
3061 }
3062
3063 switch (region) {
3064 case 0x00000000:
3065 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
3066 break;
3067 case 0x80000000:
3068 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
3069 break;
3070 case 0xC0000000:
3071 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
3072 break;
3073 }
3074}
3075
2ca8a8be
EH		 3076/* Calculate XSAVE components based on the configured CPU feature flags */
3077static void x86_cpu_enable_xsave_components(X86CPU *cpu)
3078{
3079 CPUX86State *env = &cpu->env;
3080 int i;
96193c22 3081 uint64_t mask;
2ca8a8be
EH		 3082
3083 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
3084 return;
3085 }
3086
e3c9022b
EH		 3087 mask = 0;
3088 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 3089 const ExtSaveArea *esa = &x86_ext_save_areas[i];
3090 if (env->features[esa->feature] & esa->bits) {
96193c22 3091 mask |= (1ULL << i);
2ca8a8be
EH		 3092 }
3093 }
3094
96193c22
EH		 3095 env->features[FEAT_XSAVE_COMP_LO] = mask;
3096 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 3097}
3098
41f3d4d6
EH		 3099/* Load CPUID data based on configured features */
3100static void x86_cpu_load_features(X86CPU *cpu, Error **errp)
7a059953 3101{
b34d12d1 3102 CPUX86State *env = &cpu->env;
dc15c051 3103 FeatureWord w;
2fae0d96 3104 GList *l;
41f3d4d6 3105 Error *local_err = NULL;
9886e834 3106
dc15c051
IM		 3107 /*TODO: cpu->host_features incorrectly overwrites features
3108 * set using "feat=on|off". Once we fix this, we can convert
3109 * plus_features & minus_features to global properties
3110 * inside x86_cpu_parse_featurestr() too.
3111 */
3112 if (cpu->host_features) {
3113 for (w = 0; w < FEATURE_WORDS; w++) {
3114 env->features[w] =
3115 x86_cpu_get_supported_feature_word(w, cpu->migratable);
3116 }
3117 }
3118
2fae0d96
EH		 3119 for (l = plus_features; l; l = l->next) {
3120 const char *prop = l->data;
3121 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
3122 if (local_err) {
3123 goto out;
3124 }
3125 }
3126
3127 for (l = minus_features; l; l = l->next) {
3128 const char *prop = l->data;
3129 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
3130 if (local_err) {
3131 goto out;
3132 }
dc15c051
IM		 3133 }
3134
aec661de
EH		 3135 if (!kvm_enabled() || !cpu->expose_kvm) {
3136 env->features[FEAT_KVM] = 0;
3137 }
3138
2ca8a8be 3139 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 3140
3141 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3142 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
3143 if (cpu->full_cpuid_auto_level) {
3144 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
3145 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
3146 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
3147 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
3148 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
3149 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
3150 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
3151 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
3152 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
3153 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 3154 /* SVM requires CPUID[0x8000000A] */
3155 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
3156 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
3157 }
c39c0edf
EH		 3158 }
3159
3160 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3161 if (env->cpuid_level == UINT32_MAX) {
3162 env->cpuid_level = env->cpuid_min_level;
3163 }
3164 if (env->cpuid_xlevel == UINT32_MAX) {
3165 env->cpuid_xlevel = env->cpuid_min_xlevel;
3166 }
3167 if (env->cpuid_xlevel2 == UINT32_MAX) {
3168 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 3169 }
7a059953 3170
41f3d4d6
EH		 3171out:
3172 if (local_err != NULL) {
3173 error_propagate(errp, local_err);
3174 }
3175}
3176
3177#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3178 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3179 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3180#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3181 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3182 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
3183static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
3184{
3185 CPUState *cs = CPU(dev);
3186 X86CPU *cpu = X86_CPU(dev);
3187 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3188 CPUX86State *env = &cpu->env;
3189 Error *local_err = NULL;
3190 static bool ht_warned;
3191
3192 if (xcc->kvm_required && !kvm_enabled()) {
3193 char *name = x86_cpu_class_get_model_name(xcc);
3194 error_setg(&local_err, "CPU model '%s' requires KVM", name);
3195 g_free(name);
3196 goto out;
3197 }
3198
3199 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
3200 error_setg(errp, "apic-id property was not initialized properly");
3201 return;
3202 }
3203
3204 x86_cpu_load_features(cpu, &local_err);
3205 if (local_err) {
3206 goto out;
3207 }
3208
8ca30e86
EH		 3209 if (x86_cpu_filter_features(cpu) &&
3210 (cpu->check_cpuid || cpu->enforce_cpuid)) {
3211 x86_cpu_report_filtered_features(cpu);
3212 if (cpu->enforce_cpuid) {
3213 error_setg(&local_err,
3214 kvm_enabled() ?
3215 "Host doesn't support requested features" :
3216 "TCG doesn't support requested features");
3217 goto out;
3218 }
9997cf7b
EH		 3219 }
3220
9b15cd9e
IM		 3221 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3222 * CPUID[1].EDX.
3223 */
e48638fd 3224 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 3225 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3226 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 3227 & CPUID_EXT2_AMD_ALIASES);
3228 }
3229
11f6fee5
DDAG		 3230 /* For 64bit systems think about the number of physical bits to present.
3231 * ideally this should be the same as the host; anything other than matching
3232 * the host can cause incorrect guest behaviour.
3233 * QEMU used to pick the magic value of 40 bits that corresponds to
3234 * consumer AMD devices but nothing else.
3235 */
af45907a 3236 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a 3237 if (kvm_enabled()) {
11f6fee5
DDAG		 3238 uint32_t host_phys_bits = x86_host_phys_bits();
3239 static bool warned;
3240
3241 if (cpu->host_phys_bits) {
3242 /* The user asked for us to use the host physical bits */
3243 cpu->phys_bits = host_phys_bits;
3244 }
3245
3246 /* Print a warning if the user set it to a value that's not the
3247 * host value.
3248 */
3249 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3250 !warned) {
3251 error_report("Warning: Host physical bits (%u)"
3252 " does not match phys-bits property (%u)",
3253 host_phys_bits, cpu->phys_bits);
3254 warned = true;
3255 }
3256
3257 if (cpu->phys_bits &&
3258 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3259 cpu->phys_bits < 32)) {
af45907a
DDAG		 3260 error_setg(errp, "phys-bits should be between 32 and %u "
3261 " (but is %u)",
3262 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3263 return;
3264 }
3265 } else {
11f6fee5 3266 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 3267 error_setg(errp, "TCG only supports phys-bits=%u",
3268 TCG_PHYS_ADDR_BITS);
3269 return;
3270 }
3271 }
11f6fee5
DDAG		 3272 /* 0 means it was not explicitly set by the user (or by machine
3273 * compat_props or by the host code above). In this case, the default
3274 * is the value used by TCG (40).
3275 */
3276 if (cpu->phys_bits == 0) {
3277 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3278 }
af45907a
DDAG		 3279 } else {
3280 /* For 32 bit systems don't use the user set value, but keep
3281 * phys_bits consistent with what we tell the guest.
3282 */
3283 if (cpu->phys_bits != 0) {
3284 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3285 return;
3286 }
fefb41bf 3287
af45907a
DDAG		 3288 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3289 cpu->phys_bits = 36;
3290 } else {
3291 cpu->phys_bits = 32;
3292 }
3293 }
ce5b1bbf
LV		 3294 cpu_exec_realizefn(cs, &local_err);
3295 if (local_err != NULL) {
3296 error_propagate(errp, local_err);
3297 return;
3298 }
42ecabaa 3299
57f2453a
EH		 3300 if (tcg_enabled()) {
3301 tcg_x86_init();
3302 }
3303
65dee380
IM		 3304#ifndef CONFIG_USER_ONLY
3305 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 3306
0514ef2f 3307 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 3308 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 3309 if (local_err != NULL) {
4dc1f449 3310 goto out;
bdeec802
IM		 3311 }
3312 }
65dee380
IM		 3313#endif
3314
7a059953 3315 mce_init(cpu);
2001d0cd
PB		 3316
3317#ifndef CONFIG_USER_ONLY
3318 if (tcg_enabled()) {
56943e8c
PM		 3319 AddressSpace *newas = g_new(AddressSpace, 1);
3320
f809c605 3321 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 3322 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 3323
3324 /* Outer container... */
3325 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 3326 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 3327
3328 /* ... with two regions inside: normal system memory with low
3329 * priority, and...
3330 */
3331 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3332 get_system_memory(), 0, ~0ull);
3333 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3334 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 3335 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 3336 cs->num_ases = 1;
56943e8c 3337 cpu_address_space_init(cs, newas, 0);
f809c605
PB		 3338
3339 /* ... SMRAM with higher priority, linked from /machine/smram. */
3340 cpu->machine_done.notify = x86_cpu_machine_done;
3341 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 3342 }
3343#endif
3344
14a10fc3 3345 qemu_init_vcpu(cs);
d3c64d6a 3346
e48638fd
WH		 3347 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3348 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3349 * based on inputs (sockets,cores,threads), it is still better to gives
3350 * users a warning.
3351 *
3352 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3353 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3354 */
3355 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3356 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3357 " -smp options properly.");
3358 ht_warned = true;
3359 }
3360
d3c64d6a
IM		 3361 x86_cpu_apic_realize(cpu, &local_err);
3362 if (local_err != NULL) {
3363 goto out;
3364 }
14a10fc3 3365 cpu_reset(cs);
2b6f294c 3366
4dc1f449 3367 xcc->parent_realize(dev, &local_err);
2001d0cd 3368
4dc1f449
IM		 3369out:
3370 if (local_err != NULL) {
3371 error_propagate(errp, local_err);
3372 return;
3373 }
7a059953
AF		 3374}
3375
c884776e
IM		 3376static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3377{
3378 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 3379 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3380 Error *local_err = NULL;
c884776e
IM		 3381
3382#ifndef CONFIG_USER_ONLY
3383 cpu_remove_sync(CPU(dev));
3384 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3385#endif
3386
3387 if (cpu->apic_state) {
3388 object_unparent(OBJECT(cpu->apic_state));
3389 cpu->apic_state = NULL;
3390 }
7bbc124e
LV		 3391
3392 xcc->parent_unrealize(dev, &local_err);
3393 if (local_err != NULL) {
3394 error_propagate(errp, local_err);
3395 return;
3396 }
c884776e
IM		 3397}
3398
38e5c119
EH		 3399typedef struct BitProperty {
3400 uint32_t *ptr;
3401 uint32_t mask;
3402} BitProperty;
3403
d7bce999
EB		 3404static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3405 void *opaque, Error **errp)
38e5c119
EH		 3406{
3407 BitProperty *fp = opaque;
3408 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 3409 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3410}
3411
d7bce999
EB		 3412static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3413 void *opaque, Error **errp)
38e5c119
EH		 3414{
3415 DeviceState *dev = DEVICE(obj);
3416 BitProperty *fp = opaque;
3417 Error *local_err = NULL;
3418 bool value;
3419
3420 if (dev->realized) {
3421 qdev_prop_set_after_realize(dev, name, errp);
3422 return;
3423 }
3424
51e72bc1 3425 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3426 if (local_err) {
3427 error_propagate(errp, local_err);
3428 return;
3429 }
3430
3431 if (value) {
3432 *fp->ptr |= fp->mask;
3433 } else {
3434 *fp->ptr &= ~fp->mask;
3435 }
3436}
3437
3438static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3439 void *opaque)
3440{
3441 BitProperty *prop = opaque;
3442 g_free(prop);
3443}
3444
3445/* Register a boolean property to get/set a single bit in a uint32_t field.
3446 *
3447 * The same property name can be registered multiple times to make it affect
3448 * multiple bits in the same FeatureWord. In that case, the getter will return
3449 * true only if all bits are set.
3450 */
3451static void x86_cpu_register_bit_prop(X86CPU *cpu,
3452 const char *prop_name,
3453 uint32_t *field,
3454 int bitnr)
3455{
3456 BitProperty *fp;
3457 ObjectProperty *op;
3458 uint32_t mask = (1UL << bitnr);
3459
3460 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3461 if (op) {
3462 fp = op->opaque;
3463 assert(fp->ptr == field);
3464 fp->mask |= mask;
3465 } else {
3466 fp = g_new0(BitProperty, 1);
3467 fp->ptr = field;
3468 fp->mask = mask;
3469 object_property_add(OBJECT(cpu), prop_name, "bool",
3470 x86_cpu_get_bit_prop,
3471 x86_cpu_set_bit_prop,
3472 x86_cpu_release_bit_prop, fp, &error_abort);
3473 }
3474}
3475
3476static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3477 FeatureWord w,
3478 int bitnr)
3479{
38e5c119 3480 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 3481 const char *name = fi->feat_names[bitnr];
38e5c119 3482
16d2fcaa 3483 if (!name) {
38e5c119
EH		 3484 return;
3485 }
3486
fc7dfd20
EH		 3487 /* Property names should use "-" instead of "_".
3488 * Old names containing underscores are registered as aliases
3489 * using object_property_add_alias()
3490 */
16d2fcaa
EH		 3491 assert(!strchr(name, '_'));
3492 /* aliases don't use "|" delimiters anymore, they are registered
3493 * manually using object_property_add_alias() */
3494 assert(!strchr(name, '|'));
3495 x86_cpu_register_bit_prop(cpu, name, &cpu->env.features[w], bitnr);
38e5c119
EH		 3496}
3497
d187e08d
AN		 3498static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
3499{
3500 X86CPU *cpu = X86_CPU(cs);
3501 CPUX86State *env = &cpu->env;
3502 GuestPanicInformation *panic_info = NULL;
3503
3504 if (env->features[FEAT_HYPERV_EDX] & HV_X64_GUEST_CRASH_MSR_AVAILABLE) {
3505 GuestPanicInformationHyperV *panic_info_hv =
3506 g_malloc0(sizeof(GuestPanicInformationHyperV));
3507 panic_info = g_malloc0(sizeof(GuestPanicInformation));
3508
3509 panic_info->type = GUEST_PANIC_INFORMATION_KIND_HYPER_V;
3510 panic_info->u.hyper_v.data = panic_info_hv;
3511
3512 assert(HV_X64_MSR_CRASH_PARAMS >= 5);
3513 panic_info_hv->arg1 = env->msr_hv_crash_params[0];
3514 panic_info_hv->arg2 = env->msr_hv_crash_params[1];
3515 panic_info_hv->arg3 = env->msr_hv_crash_params[2];
3516 panic_info_hv->arg4 = env->msr_hv_crash_params[3];
3517 panic_info_hv->arg5 = env->msr_hv_crash_params[4];
3518 }
3519
3520 return panic_info;
3521}
3522static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
3523 const char *name, void *opaque,
3524 Error **errp)
3525{
3526 CPUState *cs = CPU(obj);
3527 GuestPanicInformation *panic_info;
3528
3529 if (!cs->crash_occurred) {
3530 error_setg(errp, "No crash occured");
3531 return;
3532 }
3533
3534 panic_info = x86_cpu_get_crash_info(cs);
3535 if (panic_info == NULL) {
3536 error_setg(errp, "No crash information");
3537 return;
3538 }
3539
3540 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
3541 errp);
3542 qapi_free_GuestPanicInformation(panic_info);
3543}
3544
de024815
AF		 3545static void x86_cpu_initfn(Object *obj)
3546{
55e5c285 3547 CPUState *cs = CPU(obj);
de024815 3548 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3549 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3550 CPUX86State *env = &cpu->env;
38e5c119 3551 FeatureWord w;
de024815 3552
c05efcb1 3553 cs->env_ptr = env;
71ad61d3
AF		 3554
3555 object_property_add(obj, "family", "int",
95b8519d 3556 x86_cpuid_version_get_family,
71ad61d3 3557 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3558 object_property_add(obj, "model", "int",
67e30c83 3559 x86_cpuid_version_get_model,
c5291a4f 3560 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3561 object_property_add(obj, "stepping", "int",
35112e41 3562 x86_cpuid_version_get_stepping,
036e2222 3563 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3564 object_property_add_str(obj, "vendor",
3565 x86_cpuid_get_vendor,
3566 x86_cpuid_set_vendor, NULL);
938d4c25 3567 object_property_add_str(obj, "model-id",
63e886eb 3568 x86_cpuid_get_model_id,
938d4c25 3569 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3570 object_property_add(obj, "tsc-frequency", "int",
3571 x86_cpuid_get_tsc_freq,
3572 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 3573 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3574 x86_cpu_get_feature_words,
7e5292b5
EH		 3575 NULL, NULL, (void *)env->features, NULL);
3576 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3577 x86_cpu_get_feature_words,
3578 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3579
d187e08d
AN		 3580 object_property_add(obj, "crash-information", "GuestPanicInformation",
3581 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
3582
92067bf4 3583 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3584
38e5c119
EH		 3585 for (w = 0; w < FEATURE_WORDS; w++) {
3586 int bitnr;
3587
3588 for (bitnr = 0; bitnr < 32; bitnr++) {
3589 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3590 }
3591 }
3592
16d2fcaa
EH		 3593 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
3594 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
3595 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
3596 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
3597 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
3598 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
3599 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
3600
54b8dc7c
EH		 3601 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
3602 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
3603 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
3604 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
3605 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
3606 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
3607 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
3608 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
3609 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
3610 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
3611 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
3612 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
3613 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
3614 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
3615 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
3616 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
3617 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
3618 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
3619 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
3620 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
3621 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
3622
d940ee9b 3623 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
de024815
AF		 3624}
3625
997395d3
IM		 3626static int64_t x86_cpu_get_arch_id(CPUState *cs)
3627{
3628 X86CPU *cpu = X86_CPU(cs);
997395d3 3629
7e72a45c 3630 return cpu->apic_id;
997395d3
IM		 3631}
3632
444d5590
AF		 3633static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3634{
3635 X86CPU *cpu = X86_CPU(cs);
3636
3637 return cpu->env.cr[0] & CR0_PG_MASK;
3638}
3639
f45748f1
AF		 3640static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3641{
3642 X86CPU *cpu = X86_CPU(cs);
3643
3644 cpu->env.eip = value;
3645}
3646
bdf7ae5b
AF		 3647static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3648{
3649 X86CPU *cpu = X86_CPU(cs);
3650
3651 cpu->env.eip = tb->pc - tb->cs_base;
3652}
3653
8c2e1b00
AF		 3654static bool x86_cpu_has_work(CPUState *cs)
3655{
3656 X86CPU *cpu = X86_CPU(cs);
3657 CPUX86State *env = &cpu->env;
3658
6220e900
PD		 3659 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3660 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3661 (env->eflags & IF_MASK)) ||
3662 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3663 CPU_INTERRUPT_INIT |
3664 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3665 CPU_INTERRUPT_MCE)) ||
3666 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3667 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3668}
3669
9337e3b6 3670static Property x86_cpu_properties[] = {
2da00e31
IM		 3671#ifdef CONFIG_USER_ONLY
3672 /* apic_id = 0 by default for *-user, see commit 9886e834 */
3673 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 3674 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
3675 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
3676 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 3677#else
3678 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 3679 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
3680 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
3681 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 3682#endif
9337e3b6 3683 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3684 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3685 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3686 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3687 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3688 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3689 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3690 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3691 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3692 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3693 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3694 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3695 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3696 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 3697 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 3698 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 3699 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 3700 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
3701 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
3702 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
3703 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
3704 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
3705 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
3706 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 3707 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 3708 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 3709 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 3710 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
0b564e6f 3711 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
9337e3b6
EH		 3712 DEFINE_PROP_END_OF_LIST()
3713};
3714
5fd2087a
AF		 3715static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3716{
3717 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3718 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3719 DeviceClass *dc = DEVICE_CLASS(oc);
3720
3721 xcc->parent_realize = dc->realize;
7bbc124e 3722 xcc->parent_unrealize = dc->unrealize;
2b6f294c 3723 dc->realize = x86_cpu_realizefn;
c884776e 3724 dc->unrealize = x86_cpu_unrealizefn;
9337e3b6 3725 dc->props = x86_cpu_properties;
5fd2087a
AF		 3726
3727 xcc->parent_reset = cc->reset;
3728 cc->reset = x86_cpu_reset;
91b1df8c 3729 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3730
500050d1 3731 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3732 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3733 cc->has_work = x86_cpu_has_work;
97a8ea5a 3734 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3735 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3736 cc->dump_state = x86_cpu_dump_state;
f45748f1 3737 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3738 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3739 cc->gdb_read_register = x86_cpu_gdb_read_register;
3740 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3741 cc->get_arch_id = x86_cpu_get_arch_id;
3742 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3743#ifdef CONFIG_USER_ONLY
3744 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3745#else
a23bbfda 3746 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3747 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3748 cc->write_elf64_note = x86_cpu_write_elf64_note;
3749 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3750 cc->write_elf32_note = x86_cpu_write_elf32_note;
3751 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3752 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3753#endif
175cad36
DE		 3754 /* CPU_NB_REGS * 2 = general regs + xmm regs
3755 * 25 = eip, eflags, 6 seg regs, st[0-7], fctrl,...,fop, mxcsr.
3756 */
a0e372f0 3757 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3758#ifndef CONFIG_USER_ONLY
3759 cc->debug_excp_handler = breakpoint_handler;
3760#endif
374e0cd4
RH		 3761 cc->cpu_exec_enter = x86_cpu_exec_enter;
3762 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27 3763
edd12111 3764 dc->cannot_instantiate_with_device_add_yet = false;
5fd2087a
AF		 3765}
3766
3767static const TypeInfo x86_cpu_type_info = {
3768 .name = TYPE_X86_CPU,
3769 .parent = TYPE_CPU,
3770 .instance_size = sizeof(X86CPU),
de024815 3771 .instance_init = x86_cpu_initfn,
d940ee9b 3772 .abstract = true,
5fd2087a
AF		 3773 .class_size = sizeof(X86CPUClass),
3774 .class_init = x86_cpu_common_class_init,
3775};
3776
3777static void x86_cpu_register_types(void)
3778{
d940ee9b
EH		 3779 int i;
3780
5fd2087a 3781 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3782 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3783 x86_register_cpudef_type(&builtin_x86_defs[i]);
3784 }
3785#ifdef CONFIG_KVM
3786 type_register_static(&host_x86_cpu_type_info);
3787#endif
5fd2087a
AF		 3788}
3789
3790type_init(x86_cpu_register_types)
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