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i386: Rename X86CPU::host_features to X86CPU::max_features
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
b834b508 38#if defined(CONFIG_KVM)
ef8621b1 39#include <linux/kvm_para.h>
b834b508 40#endif
65dee380 41
9c17d615 42#include "sysemu/sysemu.h"
53a89e26 43#include "hw/qdev-properties.h"
5232d00a 44#include "hw/i386/topology.h"
bdeec802 45#ifndef CONFIG_USER_ONLY
2001d0cd 46#include "exec/address-spaces.h"
741da0d3 47#include "hw/hw.h"
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
14c985cf 60#define CPUID_2_L3_16MB_16WAY_64B 0x4d
5e891bf8
EH		 61
62
63/* CPUID Leaf 4 constants: */
64
65/* EAX: */
66#define CPUID_4_TYPE_DCACHE 1
67#define CPUID_4_TYPE_ICACHE 2
68#define CPUID_4_TYPE_UNIFIED 3
69
70#define CPUID_4_LEVEL(l) ((l) << 5)
71
72#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73#define CPUID_4_FULLY_ASSOC (1 << 9)
74
75/* EDX: */
76#define CPUID_4_NO_INVD_SHARING (1 << 0)
77#define CPUID_4_INCLUSIVE (1 << 1)
78#define CPUID_4_COMPLEX_IDX (1 << 2)
79
80#define ASSOC_FULL 0xFF
81
82/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
84 a == 2 ? 0x2 : \
85 a == 4 ? 0x4 : \
86 a == 8 ? 0x6 : \
87 a == 16 ? 0x8 : \
88 a == 32 ? 0xA : \
89 a == 48 ? 0xB : \
90 a == 64 ? 0xC : \
91 a == 96 ? 0xD : \
92 a == 128 ? 0xE : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
95
96
97/* Definitions of the hardcoded cache entries we expose: */
98
99/* L1 data cache: */
100#define L1D_LINE_SIZE 64
101#define L1D_ASSOCIATIVITY 8
102#define L1D_SETS 64
103#define L1D_PARTITIONS 1
104/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107#define L1D_LINES_PER_TAG 1
108#define L1D_SIZE_KB_AMD 64
109#define L1D_ASSOCIATIVITY_AMD 2
110
111/* L1 instruction cache: */
112#define L1I_LINE_SIZE 64
113#define L1I_ASSOCIATIVITY 8
114#define L1I_SETS 64
115#define L1I_PARTITIONS 1
116/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119#define L1I_LINES_PER_TAG 1
120#define L1I_SIZE_KB_AMD 64
121#define L1I_ASSOCIATIVITY_AMD 2
122
123/* Level 2 unified cache: */
124#define L2_LINE_SIZE 64
125#define L2_ASSOCIATIVITY 16
126#define L2_SETS 4096
127#define L2_PARTITIONS 1
128/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132#define L2_LINES_PER_TAG 1
133#define L2_SIZE_KB_AMD 512
134
14c985cf 135/* Level 3 unified cache: */
5e891bf8
EH		 136#define L3_SIZE_KB 0 /* disabled */
137#define L3_ASSOCIATIVITY 0 /* disabled */
138#define L3_LINES_PER_TAG 0 /* disabled */
139#define L3_LINE_SIZE 0 /* disabled */
14c985cf
LM		 140#define L3_N_LINE_SIZE 64
141#define L3_N_ASSOCIATIVITY 16
142#define L3_N_SETS 16384
143#define L3_N_PARTITIONS 1
144#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
145#define L3_N_LINES_PER_TAG 1
146#define L3_N_SIZE_KB_AMD 16384
5e891bf8
EH		 147
148/* TLB definitions: */
149
150#define L1_DTLB_2M_ASSOC 1
151#define L1_DTLB_2M_ENTRIES 255
152#define L1_DTLB_4K_ASSOC 1
153#define L1_DTLB_4K_ENTRIES 255
154
155#define L1_ITLB_2M_ASSOC 1
156#define L1_ITLB_2M_ENTRIES 255
157#define L1_ITLB_4K_ASSOC 1
158#define L1_ITLB_4K_ENTRIES 255
159
160#define L2_DTLB_2M_ASSOC 0 /* disabled */
161#define L2_DTLB_2M_ENTRIES 0 /* disabled */
162#define L2_DTLB_4K_ASSOC 4
163#define L2_DTLB_4K_ENTRIES 512
164
165#define L2_ITLB_2M_ASSOC 0 /* disabled */
166#define L2_ITLB_2M_ENTRIES 0 /* disabled */
167#define L2_ITLB_4K_ASSOC 4
168#define L2_ITLB_4K_ENTRIES 512
169
170
171
99b88a17
IM		 172static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
173 uint32_t vendor2, uint32_t vendor3)
174{
175 int i;
176 for (i = 0; i < 4; i++) {
177 dst[i] = vendor1 >> (8 * i);
178 dst[i + 4] = vendor2 >> (8 * i);
179 dst[i + 8] = vendor3 >> (8 * i);
180 }
181 dst[CPUID_VENDOR_SZ] = '\0';
182}
183
621626ce
EH		 184#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
185#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
186 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
187#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
188 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
189 CPUID_PSE36 | CPUID_FXSR)
190#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
191#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
192 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
193 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
194 CPUID_PAE | CPUID_SEP | CPUID_APIC)
195
196#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
197 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
198 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
199 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 200 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 201 /* partly implemented:
202 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
203 /* missing:
204 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
205#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
206 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
207 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 208 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 209 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
210 /* missing:
211 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
212 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
213 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 214 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
215 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 216
217#ifdef TARGET_X86_64
218#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
219#else
220#define TCG_EXT2_X86_64_FEATURES 0
221#endif
222
223#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
224 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
225 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
226 TCG_EXT2_X86_64_FEATURES)
227#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
228 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
229#define TCG_EXT4_FEATURES 0
230#define TCG_SVM_FEATURES 0
231#define TCG_KVM_FEATURES 0
232#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 233 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
234 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 235 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
236 CPUID_7_0_EBX_ERMS)
621626ce 237 /* missing:
07929f2a 238 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 239 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 240 CPUID_7_0_EBX_RDSEED */
6c7c3c21
KS		 241#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
242 CPUID_7_0_ECX_LA57)
95ea69fb 243#define TCG_7_0_EDX_FEATURES 0
303752a9 244#define TCG_APM_FEATURES 0
28b8e4d0 245#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 246#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
247 /* missing:
248 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 249
5ef57876 250typedef struct FeatureWordInfo {
2d5312da
EH		 251 /* feature flags names are taken from "Intel Processor Identification and
252 * the CPUID Instruction" and AMD's "CPUID Specification".
253 * In cases of disagreement between feature naming conventions,
254 * aliases may be added.
255 */
256 const char *feat_names[32];
04d104b6
EH		 257 uint32_t cpuid_eax; /* Input EAX for CPUID */
258 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
259 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
260 int cpuid_reg; /* output register (R_* constant) */
37ce3522 261 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 262 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 263 uint32_t migratable_flags; /* Feature flags known to be migratable */
5ef57876
EH		 264} FeatureWordInfo;
265
266static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 267 [FEAT_1_EDX] = {
2d5312da
EH		 268 .feat_names = {
269 "fpu", "vme", "de", "pse",
270 "tsc", "msr", "pae", "mce",
271 "cx8", "apic", NULL, "sep",
272 "mtrr", "pge", "mca", "cmov",
273 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
274 NULL, "ds" /* Intel dts */, "acpi", "mmx",
275 "fxsr", "sse", "sse2", "ss",
276 "ht" /* Intel htt */, "tm", "ia64", "pbe",
277 },
bffd67b0 278 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 279 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 280 },
281 [FEAT_1_ECX] = {
2d5312da 282 .feat_names = {
16d2fcaa 283 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 284 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 285 "tm2", "ssse3", "cid", NULL,
286 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 287 NULL, "pcid", "dca", "sse4.1",
288 "sse4.2", "x2apic", "movbe", "popcnt",
2d5312da
EH		 289 "tsc-deadline", "aes", "xsave", "osxsave",
290 "avx", "f16c", "rdrand", "hypervisor",
291 },
bffd67b0 292 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 293 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 294 },
2d5312da
EH		 295 /* Feature names that are already defined on feature_name[] but
296 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
297 * names on feat_names below. They are copied automatically
298 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
299 */
bffd67b0 300 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 301 .feat_names = {
302 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
303 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
304 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
305 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
306 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 307 "nx", NULL, "mmxext", NULL /* mmx */,
308 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
309 NULL, "lm", "3dnowext", "3dnow",
2d5312da 310 },
bffd67b0 311 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 312 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 313 },
314 [FEAT_8000_0001_ECX] = {
2d5312da 315 .feat_names = {
fc7dfd20 316 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 317 "cr8legacy", "abm", "sse4a", "misalignsse",
318 "3dnowprefetch", "osvw", "ibs", "xop",
319 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 320 "fma4", "tce", NULL, "nodeid-msr",
321 NULL, "tbm", "topoext", "perfctr-core",
322 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 323 NULL, NULL, NULL, NULL,
324 },
bffd67b0 325 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 326 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 327 },
89e49c8b 328 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 329 .feat_names = {
330 NULL, NULL, "xstore", "xstore-en",
331 NULL, NULL, "xcrypt", "xcrypt-en",
332 "ace2", "ace2-en", "phe", "phe-en",
333 "pmm", "pmm-en", NULL, NULL,
334 NULL, NULL, NULL, NULL,
335 NULL, NULL, NULL, NULL,
336 NULL, NULL, NULL, NULL,
337 NULL, NULL, NULL, NULL,
338 },
89e49c8b 339 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 340 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 341 },
bffd67b0 342 [FEAT_KVM] = {
2d5312da 343 .feat_names = {
fc7dfd20
EH		 344 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
345 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
2d5312da
EH		 346 NULL, NULL, NULL, NULL,
347 NULL, NULL, NULL, NULL,
348 NULL, NULL, NULL, NULL,
349 NULL, NULL, NULL, NULL,
350 "kvmclock-stable-bit", NULL, NULL, NULL,
351 NULL, NULL, NULL, NULL,
352 },
bffd67b0 353 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 354 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 355 },
c35bd19a 356 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 357 .feat_names = {
358 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
359 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
360 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
361 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
362 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
363 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
364 NULL, NULL, NULL, NULL,
365 NULL, NULL, NULL, NULL,
366 NULL, NULL, NULL, NULL,
367 NULL, NULL, NULL, NULL,
368 NULL, NULL, NULL, NULL,
369 },
c35bd19a
EY		 370 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
371 },
372 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 373 .feat_names = {
374 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
375 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
376 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
377 NULL /* hv_create_port */, NULL /* hv_connect_port */,
378 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
379 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
380 NULL, NULL,
381 NULL, NULL, NULL, NULL,
382 NULL, NULL, NULL, NULL,
383 NULL, NULL, NULL, NULL,
384 NULL, NULL, NULL, NULL,
385 },
c35bd19a
EY		 386 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
387 },
388 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 389 .feat_names = {
390 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
391 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
392 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
393 NULL, NULL,
394 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
395 NULL, NULL, NULL, NULL,
396 NULL, NULL, NULL, NULL,
397 NULL, NULL, NULL, NULL,
398 NULL, NULL, NULL, NULL,
399 NULL, NULL, NULL, NULL,
400 },
c35bd19a
EY		 401 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
402 },
bffd67b0 403 [FEAT_SVM] = {
2d5312da 404 .feat_names = {
fc7dfd20
EH		 405 "npt", "lbrv", "svm-lock", "nrip-save",
406 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
407 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 408 "pfthreshold", NULL, NULL, NULL,
409 NULL, NULL, NULL, NULL,
410 NULL, NULL, NULL, NULL,
411 NULL, NULL, NULL, NULL,
412 NULL, NULL, NULL, NULL,
413 },
bffd67b0 414 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 415 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 416 },
417 [FEAT_7_0_EBX] = {
2d5312da 418 .feat_names = {
fc7dfd20 419 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 420 "hle", "avx2", NULL, "smep",
421 "bmi2", "erms", "invpcid", "rtm",
422 NULL, NULL, "mpx", NULL,
423 "avx512f", "avx512dq", "rdseed", "adx",
424 "smap", "avx512ifma", "pcommit", "clflushopt",
425 "clwb", NULL, "avx512pf", "avx512er",
638cbd45 426 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 427 },
04d104b6
EH		 428 .cpuid_eax = 7,
429 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
430 .cpuid_reg = R_EBX,
37ce3522 431 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 432 },
f74eefe0 433 [FEAT_7_0_ECX] = {
2d5312da
EH		 434 .feat_names = {
435 NULL, "avx512vbmi", "umip", "pku",
436 "ospke", NULL, NULL, NULL,
437 NULL, NULL, NULL, NULL,
f7754377 438 NULL, NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 439 "la57", NULL, NULL, NULL,
2d5312da
EH		 440 NULL, NULL, "rdpid", NULL,
441 NULL, NULL, NULL, NULL,
442 NULL, NULL, NULL, NULL,
443 },
f74eefe0
HH		 444 .cpuid_eax = 7,
445 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
446 .cpuid_reg = R_ECX,
447 .tcg_features = TCG_7_0_ECX_FEATURES,
448 },
95ea69fb
LK		 449 [FEAT_7_0_EDX] = {
450 .feat_names = {
451 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
452 NULL, NULL, NULL, NULL,
453 NULL, NULL, NULL, NULL,
454 NULL, NULL, NULL, NULL,
455 NULL, NULL, NULL, NULL,
456 NULL, NULL, NULL, NULL,
457 NULL, NULL, NULL, NULL,
458 NULL, NULL, NULL, NULL,
459 },
460 .cpuid_eax = 7,
461 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
462 .cpuid_reg = R_EDX,
463 .tcg_features = TCG_7_0_EDX_FEATURES,
464 },
303752a9 465 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 466 .feat_names = {
467 NULL, NULL, NULL, NULL,
468 NULL, NULL, NULL, NULL,
469 "invtsc", NULL, NULL, NULL,
470 NULL, NULL, NULL, NULL,
471 NULL, NULL, NULL, NULL,
472 NULL, NULL, NULL, NULL,
473 NULL, NULL, NULL, NULL,
474 NULL, NULL, NULL, NULL,
475 },
303752a9
MT		 476 .cpuid_eax = 0x80000007,
477 .cpuid_reg = R_EDX,
478 .tcg_features = TCG_APM_FEATURES,
479 .unmigratable_flags = CPUID_APM_INVTSC,
480 },
0bb0b2d2 481 [FEAT_XSAVE] = {
2d5312da
EH		 482 .feat_names = {
483 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
484 NULL, NULL, NULL, NULL,
485 NULL, NULL, NULL, NULL,
486 NULL, NULL, NULL, NULL,
487 NULL, NULL, NULL, NULL,
488 NULL, NULL, NULL, NULL,
489 NULL, NULL, NULL, NULL,
490 NULL, NULL, NULL, NULL,
491 },
0bb0b2d2
PB		 492 .cpuid_eax = 0xd,
493 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
494 .cpuid_reg = R_EAX,
c9cfe8f9 495 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 496 },
28b8e4d0 497 [FEAT_6_EAX] = {
2d5312da
EH		 498 .feat_names = {
499 NULL, NULL, "arat", NULL,
500 NULL, NULL, NULL, NULL,
501 NULL, NULL, NULL, NULL,
502 NULL, NULL, NULL, NULL,
503 NULL, NULL, NULL, NULL,
504 NULL, NULL, NULL, NULL,
505 NULL, NULL, NULL, NULL,
506 NULL, NULL, NULL, NULL,
507 },
28b8e4d0
JK		 508 .cpuid_eax = 6, .cpuid_reg = R_EAX,
509 .tcg_features = TCG_6_EAX_FEATURES,
510 },
96193c22
EH		 511 [FEAT_XSAVE_COMP_LO] = {
512 .cpuid_eax = 0xD,
513 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
514 .cpuid_reg = R_EAX,
515 .tcg_features = ~0U,
6fb2fff7
EH		 516 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
517 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
518 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
519 XSTATE_PKRU_MASK,
96193c22
EH		 520 },
521 [FEAT_XSAVE_COMP_HI] = {
522 .cpuid_eax = 0xD,
523 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
524 .cpuid_reg = R_EDX,
525 .tcg_features = ~0U,
526 },
5ef57876
EH		 527};
528
8e8aba50
EH		 529typedef struct X86RegisterInfo32 {
530 /* Name of register */
531 const char *name;
532 /* QAPI enum value register */
533 X86CPURegister32 qapi_enum;
534} X86RegisterInfo32;
535
536#define REGISTER(reg) \
5d371f41 537 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 538static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 539 REGISTER(EAX),
540 REGISTER(ECX),
541 REGISTER(EDX),
542 REGISTER(EBX),
543 REGISTER(ESP),
544 REGISTER(EBP),
545 REGISTER(ESI),
546 REGISTER(EDI),
547};
548#undef REGISTER
549
3f32bd21
RH		 550typedef struct ExtSaveArea {
551 uint32_t feature, bits;
552 uint32_t offset, size;
553} ExtSaveArea;
554
555static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 556 [XSTATE_FP_BIT] = {
557 /* x87 FP state component is always enabled if XSAVE is supported */
558 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
559 /* x87 state is in the legacy region of the XSAVE area */
560 .offset = 0,
561 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
562 },
563 [XSTATE_SSE_BIT] = {
564 /* SSE state component is always enabled if XSAVE is supported */
565 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
566 /* SSE state is in the legacy region of the XSAVE area */
567 .offset = 0,
568 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
569 },
cfc3b074
PB		 570 [XSTATE_YMM_BIT] =
571 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 572 .offset = offsetof(X86XSaveArea, avx_state),
573 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 574 [XSTATE_BNDREGS_BIT] =
575 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 576 .offset = offsetof(X86XSaveArea, bndreg_state),
577 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 578 [XSTATE_BNDCSR_BIT] =
579 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 580 .offset = offsetof(X86XSaveArea, bndcsr_state),
581 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 582 [XSTATE_OPMASK_BIT] =
583 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 584 .offset = offsetof(X86XSaveArea, opmask_state),
585 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 586 [XSTATE_ZMM_Hi256_BIT] =
587 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 588 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
589 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 590 [XSTATE_Hi16_ZMM_BIT] =
591 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 592 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
593 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 594 [XSTATE_PKRU_BIT] =
595 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 596 .offset = offsetof(X86XSaveArea, pkru_state),
597 .size = sizeof(XSavePKRU) },
2560f19f 598};
8e8aba50 599
1fda6198
EH		 600static uint32_t xsave_area_size(uint64_t mask)
601{
602 int i;
e3c9022b 603 uint64_t ret = 0;
1fda6198 604
e3c9022b 605 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 606 const ExtSaveArea *esa = &x86_ext_save_areas[i];
607 if ((mask >> i) & 1) {
608 ret = MAX(ret, esa->offset + esa->size);
609 }
610 }
611 return ret;
612}
613
96193c22
EH		 614static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
615{
616 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
617 cpu->env.features[FEAT_XSAVE_COMP_LO];
618}
619
8b4beddc
EH		 620const char *get_register_name_32(unsigned int reg)
621{
31ccdde2 622 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 623 return NULL;
624 }
8e8aba50 625 return x86_reg_info_32[reg].name;
8b4beddc
EH		 626}
627
84f1b92f
EH		 628/*
629 * Returns the set of feature flags that are supported and migratable by
630 * QEMU, for a given FeatureWord.
631 */
632static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
633{
634 FeatureWordInfo *wi = &feature_word_info[w];
635 uint32_t r = 0;
636 int i;
637
638 for (i = 0; i < 32; i++) {
639 uint32_t f = 1U << i;
6fb2fff7
EH		 640
641 /* If the feature name is known, it is implicitly considered migratable,
642 * unless it is explicitly set in unmigratable_flags */
643 if ((wi->migratable_flags & f) ||
644 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
645 r |= f;
84f1b92f 646 }
84f1b92f
EH		 647 }
648 return r;
649}
650
bb44e0d1
JK		 651void host_cpuid(uint32_t function, uint32_t count,
652 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 653{
a1fd24af
AL		 654 uint32_t vec[4];
655
656#ifdef __x86_64__
657 asm volatile("cpuid"
658 : "=a"(vec[0]), "=b"(vec[1]),
659 "=c"(vec[2]), "=d"(vec[3])
660 : "0"(function), "c"(count) : "cc");
c1f41226 661#elif defined(__i386__)
a1fd24af
AL		 662 asm volatile("pusha \n\t"
663 "cpuid \n\t"
664 "mov %%eax, 0(%2) \n\t"
665 "mov %%ebx, 4(%2) \n\t"
666 "mov %%ecx, 8(%2) \n\t"
667 "mov %%edx, 12(%2) \n\t"
668 "popa"
669 : : "a"(function), "c"(count), "S"(vec)
670 : "memory", "cc");
c1f41226
EH		 671#else
672 abort();
a1fd24af
AL		 673#endif
674
bdde476a 675 if (eax)
a1fd24af 676 *eax = vec[0];
bdde476a 677 if (ebx)
a1fd24af 678 *ebx = vec[1];
bdde476a 679 if (ecx)
a1fd24af 680 *ecx = vec[2];
bdde476a 681 if (edx)
a1fd24af 682 *edx = vec[3];
bdde476a 683}
c6dc6f63 684
d940ee9b
EH		 685/* CPU class name definitions: */
686
687#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
688#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
689
690/* Return type name for a given CPU model name
691 * Caller is responsible for freeing the returned string.
692 */
693static char *x86_cpu_type_name(const char *model_name)
694{
695 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
696}
697
500050d1
AF		 698static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
699{
d940ee9b
EH		 700 ObjectClass *oc;
701 char *typename;
702
500050d1
AF		 703 if (cpu_model == NULL) {
704 return NULL;
705 }
706
d940ee9b
EH		 707 typename = x86_cpu_type_name(cpu_model);
708 oc = object_class_by_name(typename);
709 g_free(typename);
710 return oc;
500050d1
AF		 711}
712
104494ea
IM		 713static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
714{
715 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
716 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
717 return g_strndup(class_name,
718 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
719}
720
d940ee9b 721struct X86CPUDefinition {
c6dc6f63
AP		 722 const char *name;
723 uint32_t level;
90e4b0c3 724 uint32_t xlevel;
99b88a17
IM		 725 /* vendor is zero-terminated, 12 character ASCII string */
726 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 727 int family;
728 int model;
729 int stepping;
0514ef2f 730 FeatureWordArray features;
c6dc6f63 731 char model_id[48];
d940ee9b 732};
c6dc6f63 733
9576de75 734static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 735 {
736 .name = "qemu64",
3046bb5d 737 .level = 0xd,
99b88a17 738 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 739 .family = 6,
f8e6a11a 740 .model = 6,
c6dc6f63 741 .stepping = 3,
0514ef2f 742 .features[FEAT_1_EDX] =
27861ecc 743 PPRO_FEATURES |
c6dc6f63 744 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 745 CPUID_PSE36,
0514ef2f 746 .features[FEAT_1_ECX] =
6aa91e4a 747 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 748 .features[FEAT_8000_0001_EDX] =
c6dc6f63 749 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 750 .features[FEAT_8000_0001_ECX] =
71195672 751 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 752 .xlevel = 0x8000000A,
9cf2cc3d 753 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 754 },
755 {
756 .name = "phenom",
757 .level = 5,
99b88a17 758 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 759 .family = 16,
760 .model = 2,
761 .stepping = 3,
b9fc20bc 762 /* Missing: CPUID_HT */
0514ef2f 763 .features[FEAT_1_EDX] =
27861ecc 764 PPRO_FEATURES |
c6dc6f63 765 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 766 CPUID_PSE36 | CPUID_VME,
0514ef2f 767 .features[FEAT_1_ECX] =
27861ecc 768 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 769 CPUID_EXT_POPCNT,
0514ef2f 770 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 771 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
772 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 773 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 774 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
775 CPUID_EXT3_CR8LEG,
776 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
777 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 778 .features[FEAT_8000_0001_ECX] =
27861ecc 779 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 780 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 781 /* Missing: CPUID_SVM_LBRV */
0514ef2f 782 .features[FEAT_SVM] =
b9fc20bc 783 CPUID_SVM_NPT,
c6dc6f63
AP		 784 .xlevel = 0x8000001A,
785 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
786 },
787 {
788 .name = "core2duo",
789 .level = 10,
99b88a17 790 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 791 .family = 6,
792 .model = 15,
793 .stepping = 11,
b9fc20bc 794 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 795 .features[FEAT_1_EDX] =
27861ecc 796 PPRO_FEATURES |
c6dc6f63 797 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 798 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
799 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 800 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 801 .features[FEAT_1_ECX] =
27861ecc 802 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 803 CPUID_EXT_CX16,
0514ef2f 804 .features[FEAT_8000_0001_EDX] =
27861ecc 805 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 806 .features[FEAT_8000_0001_ECX] =
27861ecc 807 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 808 .xlevel = 0x80000008,
809 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
810 },
811 {
812 .name = "kvm64",
3046bb5d 813 .level = 0xd,
99b88a17 814 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 815 .family = 15,
816 .model = 6,
817 .stepping = 1,
b3a4f0b1 818 /* Missing: CPUID_HT */
0514ef2f 819 .features[FEAT_1_EDX] =
b3a4f0b1 820 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 821 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
822 CPUID_PSE36,
823 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 824 .features[FEAT_1_ECX] =
27861ecc 825 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 826 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 827 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 828 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
829 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
830 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
831 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
832 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 833 .features[FEAT_8000_0001_ECX] =
27861ecc 834 0,
c6dc6f63
AP		 835 .xlevel = 0x80000008,
836 .model_id = "Common KVM processor"
837 },
c6dc6f63
AP		 838 {
839 .name = "qemu32",
840 .level = 4,
99b88a17 841 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 842 .family = 6,
f8e6a11a 843 .model = 6,
c6dc6f63 844 .stepping = 3,
0514ef2f 845 .features[FEAT_1_EDX] =
27861ecc 846 PPRO_FEATURES,
0514ef2f 847 .features[FEAT_1_ECX] =
6aa91e4a 848 CPUID_EXT_SSE3,
58012d66 849 .xlevel = 0x80000004,
9cf2cc3d 850 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 851 },
eafaf1e5
AP		 852 {
853 .name = "kvm32",
854 .level = 5,
99b88a17 855 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 856 .family = 15,
857 .model = 6,
858 .stepping = 1,
0514ef2f 859 .features[FEAT_1_EDX] =
b3a4f0b1 860 PPRO_FEATURES | CPUID_VME |
eafaf1e5 861 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 862 .features[FEAT_1_ECX] =
27861ecc 863 CPUID_EXT_SSE3,
0514ef2f 864 .features[FEAT_8000_0001_ECX] =
27861ecc 865 0,
eafaf1e5
AP		 866 .xlevel = 0x80000008,
867 .model_id = "Common 32-bit KVM processor"
868 },
c6dc6f63
AP		 869 {
870 .name = "coreduo",
871 .level = 10,
99b88a17 872 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 873 .family = 6,
874 .model = 14,
875 .stepping = 8,
b9fc20bc 876 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 877 .features[FEAT_1_EDX] =
27861ecc 878 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 879 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
880 CPUID_SS,
881 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 882 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 883 .features[FEAT_1_ECX] =
e93abc14 884 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 885 .features[FEAT_8000_0001_EDX] =
27861ecc 886 CPUID_EXT2_NX,
c6dc6f63
AP		 887 .xlevel = 0x80000008,
888 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
889 },
890 {
891 .name = "486",
58012d66 892 .level = 1,
99b88a17 893 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 894 .family = 4,
b2a856d9 895 .model = 8,
c6dc6f63 896 .stepping = 0,
0514ef2f 897 .features[FEAT_1_EDX] =
27861ecc 898 I486_FEATURES,
c6dc6f63
AP		 899 .xlevel = 0,
900 },
901 {
902 .name = "pentium",
903 .level = 1,
99b88a17 904 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 905 .family = 5,
906 .model = 4,
907 .stepping = 3,
0514ef2f 908 .features[FEAT_1_EDX] =
27861ecc 909 PENTIUM_FEATURES,
c6dc6f63
AP		 910 .xlevel = 0,
911 },
912 {
913 .name = "pentium2",
914 .level = 2,
99b88a17 915 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 916 .family = 6,
917 .model = 5,
918 .stepping = 2,
0514ef2f 919 .features[FEAT_1_EDX] =
27861ecc 920 PENTIUM2_FEATURES,
c6dc6f63
AP		 921 .xlevel = 0,
922 },
923 {
924 .name = "pentium3",
3046bb5d 925 .level = 3,
99b88a17 926 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 927 .family = 6,
928 .model = 7,
929 .stepping = 3,
0514ef2f 930 .features[FEAT_1_EDX] =
27861ecc 931 PENTIUM3_FEATURES,
c6dc6f63
AP		 932 .xlevel = 0,
933 },
934 {
935 .name = "athlon",
936 .level = 2,
99b88a17 937 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 938 .family = 6,
939 .model = 2,
940 .stepping = 3,
0514ef2f 941 .features[FEAT_1_EDX] =
27861ecc 942 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 943 CPUID_MCA,
0514ef2f 944 .features[FEAT_8000_0001_EDX] =
60032ac0 945 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 946 .xlevel = 0x80000008,
9cf2cc3d 947 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 948 },
949 {
950 .name = "n270",
3046bb5d 951 .level = 10,
99b88a17 952 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 953 .family = 6,
954 .model = 28,
955 .stepping = 2,
b9fc20bc 956 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 957 .features[FEAT_1_EDX] =
27861ecc 958 PPRO_FEATURES |
b9fc20bc
EH		 959 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
960 CPUID_ACPI | CPUID_SS,
c6dc6f63 961 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 962 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
963 * CPUID_EXT_XTPR */
0514ef2f 964 .features[FEAT_1_ECX] =
27861ecc 965 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 966 CPUID_EXT_MOVBE,
0514ef2f 967 .features[FEAT_8000_0001_EDX] =
60032ac0 968 CPUID_EXT2_NX,
0514ef2f 969 .features[FEAT_8000_0001_ECX] =
27861ecc 970 CPUID_EXT3_LAHF_LM,
3046bb5d 971 .xlevel = 0x80000008,
c6dc6f63
AP		 972 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
973 },
3eca4642
EH		 974 {
975 .name = "Conroe",
3046bb5d 976 .level = 10,
99b88a17 977 .vendor = CPUID_VENDOR_INTEL,
3eca4642 978 .family = 6,
ffce9ebb 979 .model = 15,
3eca4642 980 .stepping = 3,
0514ef2f 981 .features[FEAT_1_EDX] =
b3a4f0b1 982 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 983 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
984 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
985 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
986 CPUID_DE | CPUID_FP87,
0514ef2f 987 .features[FEAT_1_ECX] =
27861ecc 988 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 989 .features[FEAT_8000_0001_EDX] =
27861ecc 990 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 991 .features[FEAT_8000_0001_ECX] =
27861ecc 992 CPUID_EXT3_LAHF_LM,
3046bb5d 993 .xlevel = 0x80000008,
3eca4642
EH		 994 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
995 },
996 {
997 .name = "Penryn",
3046bb5d 998 .level = 10,
99b88a17 999 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1000 .family = 6,
ffce9ebb 1001 .model = 23,
3eca4642 1002 .stepping = 3,
0514ef2f 1003 .features[FEAT_1_EDX] =
b3a4f0b1 1004 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1005 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1006 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1007 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1008 CPUID_DE | CPUID_FP87,
0514ef2f 1009 .features[FEAT_1_ECX] =
27861ecc 1010 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1011 CPUID_EXT_SSE3,
0514ef2f 1012 .features[FEAT_8000_0001_EDX] =
27861ecc 1013 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1014 .features[FEAT_8000_0001_ECX] =
27861ecc 1015 CPUID_EXT3_LAHF_LM,
3046bb5d 1016 .xlevel = 0x80000008,
3eca4642
EH		 1017 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1018 },
1019 {
1020 .name = "Nehalem",
3046bb5d 1021 .level = 11,
99b88a17 1022 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1023 .family = 6,
ffce9ebb 1024 .model = 26,
3eca4642 1025 .stepping = 3,
0514ef2f 1026 .features[FEAT_1_EDX] =
b3a4f0b1 1027 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1028 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1029 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1030 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1031 CPUID_DE | CPUID_FP87,
0514ef2f 1032 .features[FEAT_1_ECX] =
27861ecc 1033 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1034 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1035 .features[FEAT_8000_0001_EDX] =
27861ecc 1036 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1037 .features[FEAT_8000_0001_ECX] =
27861ecc 1038 CPUID_EXT3_LAHF_LM,
3046bb5d 1039 .xlevel = 0x80000008,
3eca4642
EH		 1040 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1041 },
1042 {
1043 .name = "Westmere",
1044 .level = 11,
99b88a17 1045 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1046 .family = 6,
1047 .model = 44,
1048 .stepping = 1,
0514ef2f 1049 .features[FEAT_1_EDX] =
b3a4f0b1 1050 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1051 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1052 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1053 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1054 CPUID_DE | CPUID_FP87,
0514ef2f 1055 .features[FEAT_1_ECX] =
27861ecc 1056 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1057 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1058 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1059 .features[FEAT_8000_0001_EDX] =
27861ecc 1060 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1061 .features[FEAT_8000_0001_ECX] =
27861ecc 1062 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1063 .features[FEAT_6_EAX] =
1064 CPUID_6_EAX_ARAT,
3046bb5d 1065 .xlevel = 0x80000008,
3eca4642
EH		 1066 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1067 },
1068 {
1069 .name = "SandyBridge",
1070 .level = 0xd,
99b88a17 1071 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1072 .family = 6,
1073 .model = 42,
1074 .stepping = 1,
0514ef2f 1075 .features[FEAT_1_EDX] =
b3a4f0b1 1076 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1077 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1078 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1079 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1080 CPUID_DE | CPUID_FP87,
0514ef2f 1081 .features[FEAT_1_ECX] =
27861ecc 1082 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1083 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1084 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1085 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1086 CPUID_EXT_SSE3,
0514ef2f 1087 .features[FEAT_8000_0001_EDX] =
27861ecc 1088 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1089 CPUID_EXT2_SYSCALL,
0514ef2f 1090 .features[FEAT_8000_0001_ECX] =
27861ecc 1091 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1092 .features[FEAT_XSAVE] =
1093 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1094 .features[FEAT_6_EAX] =
1095 CPUID_6_EAX_ARAT,
3046bb5d 1096 .xlevel = 0x80000008,
3eca4642
EH		 1097 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1098 },
2f9ac42a
PB		 1099 {
1100 .name = "IvyBridge",
1101 .level = 0xd,
1102 .vendor = CPUID_VENDOR_INTEL,
1103 .family = 6,
1104 .model = 58,
1105 .stepping = 9,
1106 .features[FEAT_1_EDX] =
1107 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1108 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1109 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1110 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1111 CPUID_DE | CPUID_FP87,
1112 .features[FEAT_1_ECX] =
1113 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1114 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1115 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1116 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1117 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1118 .features[FEAT_7_0_EBX] =
1119 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1120 CPUID_7_0_EBX_ERMS,
1121 .features[FEAT_8000_0001_EDX] =
1122 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1123 CPUID_EXT2_SYSCALL,
1124 .features[FEAT_8000_0001_ECX] =
1125 CPUID_EXT3_LAHF_LM,
1126 .features[FEAT_XSAVE] =
1127 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1128 .features[FEAT_6_EAX] =
1129 CPUID_6_EAX_ARAT,
3046bb5d 1130 .xlevel = 0x80000008,
2f9ac42a
PB		 1131 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1132 },
37507094 1133 {
a356850b
EH		 1134 .name = "Haswell-noTSX",
1135 .level = 0xd,
1136 .vendor = CPUID_VENDOR_INTEL,
1137 .family = 6,
1138 .model = 60,
1139 .stepping = 1,
1140 .features[FEAT_1_EDX] =
1141 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1142 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1143 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1144 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1145 CPUID_DE | CPUID_FP87,
1146 .features[FEAT_1_ECX] =
1147 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1148 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1149 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1150 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1151 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1152 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1153 .features[FEAT_8000_0001_EDX] =
1154 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1155 CPUID_EXT2_SYSCALL,
1156 .features[FEAT_8000_0001_ECX] =
becb6667 1157 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1158 .features[FEAT_7_0_EBX] =
1159 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1160 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1161 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1162 .features[FEAT_XSAVE] =
1163 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1164 .features[FEAT_6_EAX] =
1165 CPUID_6_EAX_ARAT,
3046bb5d 1166 .xlevel = 0x80000008,
a356850b
EH		 1167 .model_id = "Intel Core Processor (Haswell, no TSX)",
1168 }, {
37507094
EH		 1169 .name = "Haswell",
1170 .level = 0xd,
99b88a17 1171 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1172 .family = 6,
1173 .model = 60,
1174 .stepping = 1,
0514ef2f 1175 .features[FEAT_1_EDX] =
b3a4f0b1 1176 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1177 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1178 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1179 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1180 CPUID_DE | CPUID_FP87,
0514ef2f 1181 .features[FEAT_1_ECX] =
27861ecc 1182 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1183 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1184 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1185 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1186 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1187 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1188 .features[FEAT_8000_0001_EDX] =
27861ecc 1189 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1190 CPUID_EXT2_SYSCALL,
0514ef2f 1191 .features[FEAT_8000_0001_ECX] =
becb6667 1192 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1193 .features[FEAT_7_0_EBX] =
27861ecc 1194 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1195 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1196 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1197 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1198 .features[FEAT_XSAVE] =
1199 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1200 .features[FEAT_6_EAX] =
1201 CPUID_6_EAX_ARAT,
3046bb5d 1202 .xlevel = 0x80000008,
37507094
EH		 1203 .model_id = "Intel Core Processor (Haswell)",
1204 },
a356850b
EH		 1205 {
1206 .name = "Broadwell-noTSX",
1207 .level = 0xd,
1208 .vendor = CPUID_VENDOR_INTEL,
1209 .family = 6,
1210 .model = 61,
1211 .stepping = 2,
1212 .features[FEAT_1_EDX] =
1213 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1214 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1215 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1216 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1217 CPUID_DE | CPUID_FP87,
1218 .features[FEAT_1_ECX] =
1219 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1220 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1221 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1222 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1223 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1224 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1225 .features[FEAT_8000_0001_EDX] =
1226 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1227 CPUID_EXT2_SYSCALL,
1228 .features[FEAT_8000_0001_ECX] =
becb6667 1229 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1230 .features[FEAT_7_0_EBX] =
1231 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1232 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1233 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1234 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1235 CPUID_7_0_EBX_SMAP,
1236 .features[FEAT_XSAVE] =
1237 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1238 .features[FEAT_6_EAX] =
1239 CPUID_6_EAX_ARAT,
3046bb5d 1240 .xlevel = 0x80000008,
a356850b
EH		 1241 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1242 },
ece01354
EH		 1243 {
1244 .name = "Broadwell",
1245 .level = 0xd,
1246 .vendor = CPUID_VENDOR_INTEL,
1247 .family = 6,
1248 .model = 61,
1249 .stepping = 2,
1250 .features[FEAT_1_EDX] =
b3a4f0b1 1251 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1252 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1253 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1254 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1255 CPUID_DE | CPUID_FP87,
1256 .features[FEAT_1_ECX] =
1257 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1258 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1259 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1260 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1261 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1262 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1263 .features[FEAT_8000_0001_EDX] =
1264 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1265 CPUID_EXT2_SYSCALL,
1266 .features[FEAT_8000_0001_ECX] =
becb6667 1267 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1268 .features[FEAT_7_0_EBX] =
1269 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1270 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1271 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1272 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1273 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1274 .features[FEAT_XSAVE] =
1275 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1276 .features[FEAT_6_EAX] =
1277 CPUID_6_EAX_ARAT,
3046bb5d 1278 .xlevel = 0x80000008,
ece01354
EH		 1279 .model_id = "Intel Core Processor (Broadwell)",
1280 },
f6f949e9
EH		 1281 {
1282 .name = "Skylake-Client",
1283 .level = 0xd,
1284 .vendor = CPUID_VENDOR_INTEL,
1285 .family = 6,
1286 .model = 94,
1287 .stepping = 3,
1288 .features[FEAT_1_EDX] =
1289 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1290 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1291 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1292 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1293 CPUID_DE | CPUID_FP87,
1294 .features[FEAT_1_ECX] =
1295 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1296 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1297 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1298 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1299 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1300 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1301 .features[FEAT_8000_0001_EDX] =
1302 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1303 CPUID_EXT2_SYSCALL,
1304 .features[FEAT_8000_0001_ECX] =
1305 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1306 .features[FEAT_7_0_EBX] =
1307 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1308 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1309 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1310 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1311 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1312 /* Missing: XSAVES (not supported by some Linux versions,
1313 * including v4.1 to v4.6).
1314 * KVM doesn't yet expose any XSAVES state save component,
1315 * and the only one defined in Skylake (processor tracing)
1316 * probably will block migration anyway.
1317 */
1318 .features[FEAT_XSAVE] =
1319 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1320 CPUID_XSAVE_XGETBV1,
1321 .features[FEAT_6_EAX] =
1322 CPUID_6_EAX_ARAT,
1323 .xlevel = 0x80000008,
1324 .model_id = "Intel Core Processor (Skylake)",
1325 },
3eca4642
EH		 1326 {
1327 .name = "Opteron_G1",
1328 .level = 5,
99b88a17 1329 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1330 .family = 15,
1331 .model = 6,
1332 .stepping = 1,
0514ef2f 1333 .features[FEAT_1_EDX] =
b3a4f0b1 1334 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1335 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1336 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1337 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1338 CPUID_DE | CPUID_FP87,
0514ef2f 1339 .features[FEAT_1_ECX] =
27861ecc 1340 CPUID_EXT_SSE3,
0514ef2f 1341 .features[FEAT_8000_0001_EDX] =
2a923a29 1342 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 1343 .xlevel = 0x80000008,
1344 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1345 },
1346 {
1347 .name = "Opteron_G2",
1348 .level = 5,
99b88a17 1349 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1350 .family = 15,
1351 .model = 6,
1352 .stepping = 1,
0514ef2f 1353 .features[FEAT_1_EDX] =
b3a4f0b1 1354 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1355 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1356 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1357 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1358 CPUID_DE | CPUID_FP87,
0514ef2f 1359 .features[FEAT_1_ECX] =
27861ecc 1360 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1361 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1362 .features[FEAT_8000_0001_EDX] =
2a923a29 1363 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1364 .features[FEAT_8000_0001_ECX] =
27861ecc 1365 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1366 .xlevel = 0x80000008,
1367 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1368 },
1369 {
1370 .name = "Opteron_G3",
1371 .level = 5,
99b88a17 1372 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 1373 .family = 16,
1374 .model = 2,
1375 .stepping = 3,
0514ef2f 1376 .features[FEAT_1_EDX] =
b3a4f0b1 1377 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1378 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1379 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1380 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1381 CPUID_DE | CPUID_FP87,
0514ef2f 1382 .features[FEAT_1_ECX] =
27861ecc 1383 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1384 CPUID_EXT_SSE3,
33b5e8c0 1385 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1386 .features[FEAT_8000_0001_EDX] =
2a923a29 1387 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1388 .features[FEAT_8000_0001_ECX] =
27861ecc 1389 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1390 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1391 .xlevel = 0x80000008,
1392 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1393 },
1394 {
1395 .name = "Opteron_G4",
1396 .level = 0xd,
99b88a17 1397 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1398 .family = 21,
1399 .model = 1,
1400 .stepping = 2,
0514ef2f 1401 .features[FEAT_1_EDX] =
b3a4f0b1 1402 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1403 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1404 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1405 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1406 CPUID_DE | CPUID_FP87,
0514ef2f 1407 .features[FEAT_1_ECX] =
27861ecc 1408 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1409 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1410 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1411 CPUID_EXT_SSE3,
33b5e8c0 1412 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1413 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1414 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1415 CPUID_EXT2_SYSCALL,
0514ef2f 1416 .features[FEAT_8000_0001_ECX] =
27861ecc 1417 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1418 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1419 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1420 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1421 /* no xsaveopt! */
3eca4642
EH		 1422 .xlevel = 0x8000001A,
1423 .model_id = "AMD Opteron 62xx class CPU",
1424 },
021941b9
AP		 1425 {
1426 .name = "Opteron_G5",
1427 .level = 0xd,
99b88a17 1428 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1429 .family = 21,
1430 .model = 2,
1431 .stepping = 0,
0514ef2f 1432 .features[FEAT_1_EDX] =
b3a4f0b1 1433 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1434 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1435 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1436 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1437 CPUID_DE | CPUID_FP87,
0514ef2f 1438 .features[FEAT_1_ECX] =
27861ecc 1439 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1440 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1441 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1442 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1443 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1444 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1445 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1446 CPUID_EXT2_SYSCALL,
0514ef2f 1447 .features[FEAT_8000_0001_ECX] =
27861ecc 1448 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1449 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1450 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1451 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1452 /* no xsaveopt! */
021941b9
AP		 1453 .xlevel = 0x8000001A,
1454 .model_id = "AMD Opteron 63xx class CPU",
1455 },
c6dc6f63
AP		 1456};
1457
5114e842
EH		 1458typedef struct PropValue {
1459 const char *prop, *value;
1460} PropValue;
1461
1462/* KVM-specific features that are automatically added/removed
1463 * from all CPU models when KVM is enabled.
1464 */
1465static PropValue kvm_default_props[] = {
1466 { "kvmclock", "on" },
1467 { "kvm-nopiodelay", "on" },
1468 { "kvm-asyncpf", "on" },
1469 { "kvm-steal-time", "on" },
1470 { "kvm-pv-eoi", "on" },
1471 { "kvmclock-stable-bit", "on" },
1472 { "x2apic", "on" },
1473 { "acpi", "off" },
1474 { "monitor", "off" },
1475 { "svm", "off" },
1476 { NULL, NULL },
1477};
1478
04d99c3c
EH		 1479/* TCG-specific defaults that override all CPU models when using TCG
1480 */
1481static PropValue tcg_default_props[] = {
1482 { "vme", "off" },
1483 { NULL, NULL },
1484};
1485
1486
5114e842
EH		 1487void x86_cpu_change_kvm_default(const char *prop, const char *value)
1488{
1489 PropValue *pv;
1490 for (pv = kvm_default_props; pv->prop; pv++) {
1491 if (!strcmp(pv->prop, prop)) {
1492 pv->value = value;
1493 break;
1494 }
1495 }
1496
1497 /* It is valid to call this function only for properties that
1498 * are already present in the kvm_default_props table.
1499 */
1500 assert(pv->prop);
1501}
1502
4d1b279b
EH		 1503static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1504 bool migratable_only);
1505
d940ee9b
EH		 1506#ifdef CONFIG_KVM
1507
40bfe48f
HZ		 1508static bool lmce_supported(void)
1509{
1510 uint64_t mce_cap;
1511
1512 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1513 return false;
1514 }
1515
1516 return !!(mce_cap & MCG_LMCE_P);
1517}
1518
c6dc6f63
AP		 1519static int cpu_x86_fill_model_id(char *str)
1520{
1521 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1522 int i;
1523
1524 for (i = 0; i < 3; i++) {
1525 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1526 memcpy(str + i * 16 + 0, &eax, 4);
1527 memcpy(str + i * 16 + 4, &ebx, 4);
1528 memcpy(str + i * 16 + 8, &ecx, 4);
1529 memcpy(str + i * 16 + 12, &edx, 4);
1530 }
1531 return 0;
1532}
1533
d940ee9b
EH		 1534static X86CPUDefinition host_cpudef;
1535
84f1b92f 1536static Property host_x86_cpu_properties[] = {
120eee7d 1537 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1538 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1539 DEFINE_PROP_END_OF_LIST()
1540};
1541
d940ee9b 1542/* class_init for the "host" CPU model
6e746f30 1543 *
d940ee9b 1544 * This function may be called before KVM is initialized.
6e746f30 1545 */
d940ee9b 1546static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1547{
84f1b92f 1548 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1549 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1550 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1551
d940ee9b 1552 xcc->kvm_required = true;
f48c8837 1553 xcc->ordering = 9;
6e746f30 1554
c6dc6f63 1555 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1556 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1557
1558 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1559 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1560 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1561 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1562
d940ee9b 1563 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1564
d940ee9b 1565 xcc->cpu_def = &host_cpudef;
ee465a3e
EH		 1566 xcc->model_description =
1567 "KVM processor with all supported host features "
1568 "(only available in KVM mode)";
d940ee9b
EH		 1569
1570 /* level, xlevel, xlevel2, and the feature words are initialized on
1571 * instance_init, because they require KVM to be initialized.
1572 */
84f1b92f
EH		 1573
1574 dc->props = host_x86_cpu_properties;
d940ee9b
EH		 1575}
1576
1577static void host_x86_cpu_initfn(Object *obj)
1578{
1579 X86CPU *cpu = X86_CPU(obj);
1580 CPUX86State *env = &cpu->env;
1581 KVMState *s = kvm_state;
d940ee9b 1582
4d1b279b
EH		 1583 /* We can't fill the features array here because we don't know yet if
1584 * "migratable" is true or false.
1585 */
44bd8e53 1586 cpu->max_features = true;
4d1b279b 1587
104494ea 1588 /* If KVM is disabled, x86_cpu_realizefn() will report an error later */
e4356010 1589 if (kvm_enabled()) {
c39c0edf
EH		 1590 env->cpuid_min_level =
1591 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1592 env->cpuid_min_xlevel =
1593 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1594 env->cpuid_min_xlevel2 =
1595 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
40bfe48f
HZ		 1596
1597 if (lmce_supported()) {
1598 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1599 }
e4356010 1600 }
2a573259 1601
d940ee9b 1602 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1603}
1604
d940ee9b
EH		 1605static const TypeInfo host_x86_cpu_type_info = {
1606 .name = X86_CPU_TYPE_NAME("host"),
1607 .parent = TYPE_X86_CPU,
1608 .instance_init = host_x86_cpu_initfn,
1609 .class_init = host_x86_cpu_class_init,
1610};
1611
1612#endif
1613
8459e396 1614static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1615{
8459e396 1616 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1617 int i;
1618
857aee33 1619 for (i = 0; i < 32; ++i) {
72370dc1 1620 if ((1UL << i) & mask) {
bffd67b0 1621 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1622 assert(reg);
fefb41bf 1623 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1624 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1625 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1626 f->cpuid_eax, reg,
1627 f->feat_names[i] ? "." : "",
1628 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1629 }
857aee33 1630 }
c6dc6f63
AP		 1631}
1632
d7bce999
EB		 1633static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1634 const char *name, void *opaque,
1635 Error **errp)
95b8519d
AF		 1636{
1637 X86CPU *cpu = X86_CPU(obj);
1638 CPUX86State *env = &cpu->env;
1639 int64_t value;
1640
1641 value = (env->cpuid_version >> 8) & 0xf;
1642 if (value == 0xf) {
1643 value += (env->cpuid_version >> 20) & 0xff;
1644 }
51e72bc1 1645 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1646}
1647
d7bce999
EB		 1648static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1649 const char *name, void *opaque,
1650 Error **errp)
ed5e1ec3 1651{
71ad61d3
AF		 1652 X86CPU *cpu = X86_CPU(obj);
1653 CPUX86State *env = &cpu->env;
1654 const int64_t min = 0;
1655 const int64_t max = 0xff + 0xf;
65cd9064 1656 Error *local_err = NULL;
71ad61d3
AF		 1657 int64_t value;
1658
51e72bc1 1659 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1660 if (local_err) {
1661 error_propagate(errp, local_err);
71ad61d3
AF		 1662 return;
1663 }
1664 if (value < min || value > max) {
c6bd8c70
MA		 1665 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1666 name ? name : "null", value, min, max);
71ad61d3
AF		 1667 return;
1668 }
1669
ed5e1ec3 1670 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1671 if (value > 0x0f) {
1672 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1673 } else {
71ad61d3 1674 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1675 }
1676}
1677
d7bce999
EB		 1678static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1679 const char *name, void *opaque,
1680 Error **errp)
67e30c83
AF		 1681{
1682 X86CPU *cpu = X86_CPU(obj);
1683 CPUX86State *env = &cpu->env;
1684 int64_t value;
1685
1686 value = (env->cpuid_version >> 4) & 0xf;
1687 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1688 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1689}
1690
d7bce999
EB		 1691static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1692 const char *name, void *opaque,
1693 Error **errp)
b0704cbd 1694{
c5291a4f
AF		 1695 X86CPU *cpu = X86_CPU(obj);
1696 CPUX86State *env = &cpu->env;
1697 const int64_t min = 0;
1698 const int64_t max = 0xff;
65cd9064 1699 Error *local_err = NULL;
c5291a4f
AF		 1700 int64_t value;
1701
51e72bc1 1702 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1703 if (local_err) {
1704 error_propagate(errp, local_err);
c5291a4f
AF		 1705 return;
1706 }
1707 if (value < min || value > max) {
c6bd8c70
MA		 1708 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1709 name ? name : "null", value, min, max);
c5291a4f
AF		 1710 return;
1711 }
1712
b0704cbd 1713 env->cpuid_version &= ~0xf00f0;
c5291a4f 1714 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1715}
1716
35112e41 1717static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1718 const char *name, void *opaque,
35112e41
AF		 1719 Error **errp)
1720{
1721 X86CPU *cpu = X86_CPU(obj);
1722 CPUX86State *env = &cpu->env;
1723 int64_t value;
1724
1725 value = env->cpuid_version & 0xf;
51e72bc1 1726 visit_type_int(v, name, &value, errp);
35112e41
AF		 1727}
1728
036e2222 1729static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1730 const char *name, void *opaque,
036e2222 1731 Error **errp)
38c3dc46 1732{
036e2222
AF		 1733 X86CPU *cpu = X86_CPU(obj);
1734 CPUX86State *env = &cpu->env;
1735 const int64_t min = 0;
1736 const int64_t max = 0xf;
65cd9064 1737 Error *local_err = NULL;
036e2222
AF		 1738 int64_t value;
1739
51e72bc1 1740 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1741 if (local_err) {
1742 error_propagate(errp, local_err);
036e2222
AF		 1743 return;
1744 }
1745 if (value < min || value > max) {
c6bd8c70
MA		 1746 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1747 name ? name : "null", value, min, max);
036e2222
AF		 1748 return;
1749 }
1750
38c3dc46 1751 env->cpuid_version &= ~0xf;
036e2222 1752 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1753}
1754
d480e1af
AF		 1755static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1756{
1757 X86CPU *cpu = X86_CPU(obj);
1758 CPUX86State *env = &cpu->env;
1759 char *value;
d480e1af 1760
e42a92ae 1761 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1762 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1763 env->cpuid_vendor3);
d480e1af
AF		 1764 return value;
1765}
1766
1767static void x86_cpuid_set_vendor(Object *obj, const char *value,
1768 Error **errp)
1769{
1770 X86CPU *cpu = X86_CPU(obj);
1771 CPUX86State *env = &cpu->env;
1772 int i;
1773
9df694ee 1774 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1775 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1776 return;
1777 }
1778
1779 env->cpuid_vendor1 = 0;
1780 env->cpuid_vendor2 = 0;
1781 env->cpuid_vendor3 = 0;
1782 for (i = 0; i < 4; i++) {
1783 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1784 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1785 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1786 }
d480e1af
AF		 1787}
1788
63e886eb
AF		 1789static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1790{
1791 X86CPU *cpu = X86_CPU(obj);
1792 CPUX86State *env = &cpu->env;
1793 char *value;
1794 int i;
1795
1796 value = g_malloc(48 + 1);
1797 for (i = 0; i < 48; i++) {
1798 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1799 }
1800 value[48] = '\0';
1801 return value;
1802}
1803
938d4c25
AF		 1804static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1805 Error **errp)
dcce6675 1806{
938d4c25
AF		 1807 X86CPU *cpu = X86_CPU(obj);
1808 CPUX86State *env = &cpu->env;
dcce6675
AF		 1809 int c, len, i;
1810
1811 if (model_id == NULL) {
1812 model_id = "";
1813 }
1814 len = strlen(model_id);
d0a6acf4 1815 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1816 for (i = 0; i < 48; i++) {
1817 if (i >= len) {
1818 c = '\0';
1819 } else {
1820 c = (uint8_t)model_id[i];
1821 }
1822 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1823 }
1824}
1825
d7bce999
EB		 1826static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1827 void *opaque, Error **errp)
89e48965
AF		 1828{
1829 X86CPU *cpu = X86_CPU(obj);
1830 int64_t value;
1831
1832 value = cpu->env.tsc_khz * 1000;
51e72bc1 1833 visit_type_int(v, name, &value, errp);
89e48965
AF		 1834}
1835
d7bce999
EB		 1836static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1837 void *opaque, Error **errp)
89e48965
AF		 1838{
1839 X86CPU *cpu = X86_CPU(obj);
1840 const int64_t min = 0;
2e84849a 1841 const int64_t max = INT64_MAX;
65cd9064 1842 Error *local_err = NULL;
89e48965
AF		 1843 int64_t value;
1844
51e72bc1 1845 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1846 if (local_err) {
1847 error_propagate(errp, local_err);
89e48965
AF		 1848 return;
1849 }
1850 if (value < min || value > max) {
c6bd8c70
MA		 1851 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1852 name ? name : "null", value, min, max);
89e48965
AF		 1853 return;
1854 }
1855
36f96c4b 1856 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1857}
1858
7e5292b5 1859/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1860static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1861 const char *name, void *opaque,
1862 Error **errp)
8e8aba50 1863{
7e5292b5 1864 uint32_t *array = (uint32_t *)opaque;
8e8aba50 1865 FeatureWord w;
8e8aba50
EH		 1866 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1867 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1868 X86CPUFeatureWordInfoList *list = NULL;
1869
1870 for (w = 0; w < FEATURE_WORDS; w++) {
1871 FeatureWordInfo *wi = &feature_word_info[w];
1872 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1873 qwi->cpuid_input_eax = wi->cpuid_eax;
1874 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1875 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1876 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1877 qwi->features = array[w];
8e8aba50
EH		 1878
1879 /* List will be in reverse order, but order shouldn't matter */
1880 list_entries[w].next = list;
1881 list_entries[w].value = &word_infos[w];
1882 list = &list_entries[w];
1883 }
1884
6b62d961 1885 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 1886}
1887
d7bce999
EB		 1888static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1889 void *opaque, Error **errp)
c8f0f88e
IM		 1890{
1891 X86CPU *cpu = X86_CPU(obj);
1892 int64_t value = cpu->hyperv_spinlock_attempts;
1893
51e72bc1 1894 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1895}
1896
d7bce999
EB		 1897static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1898 void *opaque, Error **errp)
c8f0f88e
IM		 1899{
1900 const int64_t min = 0xFFF;
1901 const int64_t max = UINT_MAX;
1902 X86CPU *cpu = X86_CPU(obj);
1903 Error *err = NULL;
1904 int64_t value;
1905
51e72bc1 1906 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1907 if (err) {
1908 error_propagate(errp, err);
1909 return;
1910 }
1911
1912 if (value < min || value > max) {
1913 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1914 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1915 object_get_typename(obj), name ? name : "null",
1916 value, min, max);
c8f0f88e
IM		 1917 return;
1918 }
1919 cpu->hyperv_spinlock_attempts = value;
1920}
1921
1922static PropertyInfo qdev_prop_spinlocks = {
1923 .name = "int",
1924 .get = x86_get_hv_spinlocks,
1925 .set = x86_set_hv_spinlocks,
1926};
1927
72ac2e87
IM		 1928/* Convert all '_' in a feature string option name to '-', to make feature
1929 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1930 */
1931static inline void feat2prop(char *s)
1932{
1933 while ((s = strchr(s, '_'))) {
1934 *s = '-';
1935 }
1936}
1937
b54c9377
EH		 1938/* Return the feature property name for a feature flag bit */
1939static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
1940{
1941 /* XSAVE components are automatically enabled by other features,
1942 * so return the original feature name instead
1943 */
1944 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
1945 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
1946
1947 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
1948 x86_ext_save_areas[comp].bits) {
1949 w = x86_ext_save_areas[comp].feature;
1950 bitnr = ctz32(x86_ext_save_areas[comp].bits);
1951 }
1952 }
1953
1954 assert(bitnr < 32);
1955 assert(w < FEATURE_WORDS);
1956 return feature_word_info[w].feat_names[bitnr];
1957}
1958
dc15c051
IM		 1959/* Compatibily hack to maintain legacy +-feat semantic,
1960 * where +-feat overwrites any feature set by
1961 * feat=on|feat even if the later is parsed after +-feat
1962 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
1963 */
2fae0d96 1964static GList *plus_features, *minus_features;
dc15c051 1965
83a00f60
EH		 1966static gint compare_string(gconstpointer a, gconstpointer b)
1967{
1968 return g_strcmp0(a, b);
1969}
1970
8f961357
EH		 1971/* Parse "+feature,-feature,feature=foo" CPU feature string
1972 */
62a48a2a 1973static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 1974 Error **errp)
8f961357 1975{
8f961357 1976 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 1977 static bool cpu_globals_initialized;
83a00f60 1978 bool ambiguous = false;
62a48a2a
IM		 1979
1980 if (cpu_globals_initialized) {
1981 return;
1982 }
1983 cpu_globals_initialized = true;
8f961357 1984
f6750e95
EH		 1985 if (!features) {
1986 return;
1987 }
1988
1989 for (featurestr = strtok(features, ",");
685479bd 1990 featurestr;
f6750e95
EH		 1991 featurestr = strtok(NULL, ",")) {
1992 const char *name;
1993 const char *val = NULL;
1994 char *eq = NULL;
cf2887c9 1995 char num[32];
62a48a2a 1996 GlobalProperty *prop;
c6dc6f63 1997
f6750e95 1998 /* Compatibility syntax: */
c6dc6f63 1999 if (featurestr[0] == '+') {
2fae0d96
EH		 2000 plus_features = g_list_append(plus_features,
2001 g_strdup(featurestr + 1));
f6750e95 2002 continue;
c6dc6f63 2003 } else if (featurestr[0] == '-') {
2fae0d96
EH		 2004 minus_features = g_list_append(minus_features,
2005 g_strdup(featurestr + 1));
f6750e95
EH		 2006 continue;
2007 }
2008
2009 eq = strchr(featurestr, '=');
2010 if (eq) {
2011 *eq++ = 0;
2012 val = eq;
c6dc6f63 2013 } else {
f6750e95 2014 val = "on";
a91987c2 2015 }
f6750e95
EH		 2016
2017 feat2prop(featurestr);
2018 name = featurestr;
2019
83a00f60
EH		 2020 if (g_list_find_custom(plus_features, name, compare_string)) {
2021 error_report("warning: Ambiguous CPU model string. "
2022 "Don't mix both \"+%s\" and \"%s=%s\"",
2023 name, name, val);
2024 ambiguous = true;
2025 }
2026 if (g_list_find_custom(minus_features, name, compare_string)) {
2027 error_report("warning: Ambiguous CPU model string. "
2028 "Don't mix both \"-%s\" and \"%s=%s\"",
2029 name, name, val);
2030 ambiguous = true;
2031 }
2032
f6750e95
EH		 2033 /* Special case: */
2034 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 2035 int ret;
f46bfdbf 2036 uint64_t tsc_freq;
f6750e95 2037
f17fd4fd 2038 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 2039 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 2040 error_setg(errp, "bad numerical value %s", val);
2041 return;
2042 }
2043 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2044 val = num;
2045 name = "tsc-frequency";
c6dc6f63 2046 }
f6750e95 2047
62a48a2a
IM		 2048 prop = g_new0(typeof(*prop), 1);
2049 prop->driver = typename;
2050 prop->property = g_strdup(name);
2051 prop->value = g_strdup(val);
2052 prop->errp = &error_fatal;
2053 qdev_prop_register_global(prop);
f6750e95
EH		 2054 }
2055
83a00f60
EH		 2056 if (ambiguous) {
2057 error_report("warning: Compatibility of ambiguous CPU model "
2058 "strings won't be kept on future QEMU versions");
2059 }
c6dc6f63
AP		 2060}
2061
b54c9377
EH		 2062static void x86_cpu_load_features(X86CPU *cpu, Error **errp);
2063static int x86_cpu_filter_features(X86CPU *cpu);
2064
2065/* Check for missing features that may prevent the CPU class from
2066 * running using the current machine and accelerator.
2067 */
2068static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
2069 strList **missing_feats)
2070{
2071 X86CPU *xc;
2072 FeatureWord w;
2073 Error *err = NULL;
2074 strList **next = missing_feats;
2075
2076 if (xcc->kvm_required && !kvm_enabled()) {
2077 strList *new = g_new0(strList, 1);
2078 new->value = g_strdup("kvm");;
2079 *missing_feats = new;
2080 return;
2081 }
2082
2083 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2084
2085 x86_cpu_load_features(xc, &err);
2086 if (err) {
2087 /* Errors at x86_cpu_load_features should never happen,
2088 * but in case it does, just report the model as not
2089 * runnable at all using the "type" property.
2090 */
2091 strList *new = g_new0(strList, 1);
2092 new->value = g_strdup("type");
2093 *next = new;
2094 next = &new->next;
2095 }
2096
2097 x86_cpu_filter_features(xc);
2098
2099 for (w = 0; w < FEATURE_WORDS; w++) {
2100 uint32_t filtered = xc->filtered_features[w];
2101 int i;
2102 for (i = 0; i < 32; i++) {
2103 if (filtered & (1UL << i)) {
2104 strList *new = g_new0(strList, 1);
2105 new->value = g_strdup(x86_cpu_feature_name(w, i));
2106 *next = new;
2107 next = &new->next;
2108 }
2109 }
2110 }
2111
2112 object_unref(OBJECT(xc));
2113}
2114
8c3329e5 2115/* Print all cpuid feature names in featureset
c6dc6f63 2116 */
8c3329e5 2117static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2118{
8c3329e5
EH		 2119 int bit;
2120 bool first = true;
2121
2122 for (bit = 0; bit < 32; bit++) {
2123 if (featureset[bit]) {
2124 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2125 first = false;
c6dc6f63 2126 }
8c3329e5 2127 }
c6dc6f63
AP		 2128}
2129
f48c8837 2130/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 2131static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
2132{
2133 ObjectClass *class_a = (ObjectClass *)a;
2134 ObjectClass *class_b = (ObjectClass *)b;
2135 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
2136 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
2137 const char *name_a, *name_b;
2138
f48c8837
EH		 2139 if (cc_a->ordering != cc_b->ordering) {
2140 return cc_a->ordering - cc_b->ordering;
ee465a3e
EH		 2141 } else {
2142 name_a = object_class_get_name(class_a);
2143 name_b = object_class_get_name(class_b);
2144 return strcmp(name_a, name_b);
2145 }
2146}
2147
2148static GSList *get_sorted_cpu_model_list(void)
2149{
2150 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
2151 list = g_slist_sort(list, x86_cpu_list_compare);
2152 return list;
2153}
2154
2155static void x86_cpu_list_entry(gpointer data, gpointer user_data)
2156{
2157 ObjectClass *oc = data;
2158 X86CPUClass *cc = X86_CPU_CLASS(oc);
2159 CPUListState *s = user_data;
2160 char *name = x86_cpu_class_get_model_name(cc);
2161 const char *desc = cc->model_description;
2162 if (!desc) {
2163 desc = cc->cpu_def->model_id;
2164 }
2165
2166 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
2167 name, desc);
2168 g_free(name);
2169}
2170
2171/* list available CPU models and flags */
e916cbf8 2172void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2173{
7fc9b714 2174 int i;
ee465a3e
EH		 2175 CPUListState s = {
2176 .file = f,
2177 .cpu_fprintf = cpu_fprintf,
2178 };
2179 GSList *list;
c6dc6f63 2180
ee465a3e
EH		 2181 (*cpu_fprintf)(f, "Available CPUs:\n");
2182 list = get_sorted_cpu_model_list();
2183 g_slist_foreach(list, x86_cpu_list_entry, &s);
2184 g_slist_free(list);
21ad7789 2185
6cdf8854 2186 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2187 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2188 FeatureWordInfo *fw = &feature_word_info[i];
2189
8c3329e5
EH		 2190 (*cpu_fprintf)(f, " ");
2191 listflags(f, cpu_fprintf, fw->feat_names);
2192 (*cpu_fprintf)(f, "\n");
3af60be2 2193 }
c6dc6f63
AP		 2194}
2195
ee465a3e
EH		 2196static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
2197{
2198 ObjectClass *oc = data;
2199 X86CPUClass *cc = X86_CPU_CLASS(oc);
2200 CpuDefinitionInfoList **cpu_list = user_data;
2201 CpuDefinitionInfoList *entry;
2202 CpuDefinitionInfo *info;
2203
2204 info = g_malloc0(sizeof(*info));
2205 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 2206 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
2207 info->has_unavailable_features = true;
8ed877b7 2208 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 2209 info->migration_safe = cc->migration_safe;
2210 info->has_migration_safe = true;
ee465a3e
EH		 2211
2212 entry = g_malloc0(sizeof(*entry));
2213 entry->value = info;
2214 entry->next = *cpu_list;
2215 *cpu_list = entry;
2216}
2217
76b64a7a 2218CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2219{
2220 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 2221 GSList *list = get_sorted_cpu_model_list();
2222 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
2223 g_slist_free(list);
e3966126
AL		 2224 return cpu_list;
2225}
2226
84f1b92f
EH		 2227static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2228 bool migratable_only)
27418adf
EH		 2229{
2230 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2231 uint32_t r;
27418adf 2232
fefb41bf 2233 if (kvm_enabled()) {
84f1b92f
EH		 2234 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2235 wi->cpuid_ecx,
2236 wi->cpuid_reg);
fefb41bf 2237 } else if (tcg_enabled()) {
84f1b92f 2238 r = wi->tcg_features;
fefb41bf
EH		 2239 } else {
2240 return ~0;
2241 }
84f1b92f
EH		 2242 if (migratable_only) {
2243 r &= x86_cpu_get_migratable_flags(w);
2244 }
2245 return r;
27418adf
EH		 2246}
2247
51f63aed
EH		 2248/*
2249 * Filters CPU feature words based on host availability of each feature.
2250 *
51f63aed
EH		 2251 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2252 */
27418adf 2253static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2254{
2255 CPUX86State *env = &cpu->env;
bd87d2a2 2256 FeatureWord w;
51f63aed
EH		 2257 int rv = 0;
2258
bd87d2a2 2259 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f 2260 uint32_t host_feat =
46c032f3 2261 x86_cpu_get_supported_feature_word(w, false);
034acf4a
EH		 2262 uint32_t requested_features = env->features[w];
2263 env->features[w] &= host_feat;
2264 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed 2265 if (cpu->filtered_features[w]) {
51f63aed
EH		 2266 rv = 1;
2267 }
bd87d2a2 2268 }
51f63aed
EH		 2269
2270 return rv;
bc74b7db 2271}
bc74b7db 2272
8ca30e86
EH		 2273static void x86_cpu_report_filtered_features(X86CPU *cpu)
2274{
2275 FeatureWord w;
2276
2277 for (w = 0; w < FEATURE_WORDS; w++) {
2278 report_unavailable_features(w, cpu->filtered_features[w]);
2279 }
2280}
2281
5114e842
EH		 2282static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2283{
2284 PropValue *pv;
2285 for (pv = props; pv->prop; pv++) {
2286 if (!pv->value) {
2287 continue;
2288 }
2289 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2290 &error_abort);
2291 }
2292}
2293
d940ee9b 2294/* Load data from X86CPUDefinition
c080e30e 2295 */
d940ee9b 2296static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2297{
61dcd775 2298 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2299 const char *vendor;
2300 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2301 FeatureWord w;
c6dc6f63 2302
c39c0edf
EH		 2303 /* CPU models only set _minimum_ values for level/xlevel: */
2304 object_property_set_int(OBJECT(cpu), def->level, "min-level", errp);
2305 object_property_set_int(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
2306
2d64255b
AF		 2307 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2308 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2309 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2310 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2311 for (w = 0; w < FEATURE_WORDS; w++) {
2312 env->features[w] = def->features[w];
2313 }
82beb536 2314
9576de75 2315 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2316 if (kvm_enabled()) {
492a4c94
LT		 2317 if (!kvm_irqchip_in_kernel()) {
2318 x86_cpu_change_kvm_default("x2apic", "off");
2319 }
2320
5114e842 2321 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 2322 } else if (tcg_enabled()) {
2323 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 2324 }
5fcca9ff 2325
82beb536 2326 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2327
2328 /* sysenter isn't supported in compatibility mode on AMD,
2329 * syscall isn't supported in compatibility mode on Intel.
2330 * Normally we advertise the actual CPU vendor, but you can
2331 * override this using the 'vendor' property if you want to use
2332 * KVM's sysenter/syscall emulation in compatibility mode and
2333 * when doing cross vendor migration
2334 */
74f54bc4 2335 vendor = def->vendor;
7c08db30
EH		 2336 if (kvm_enabled()) {
2337 uint32_t ebx = 0, ecx = 0, edx = 0;
2338 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2339 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2340 vendor = host_vendor;
2341 }
2342
2343 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2344
c6dc6f63
AP		 2345}
2346
0856579c 2347X86CPU *cpu_x86_init(const char *cpu_model)
7f833247 2348{
a57d0163 2349 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
5c3c6a68
AF		 2350}
2351
d940ee9b
EH		 2352static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2353{
2354 X86CPUDefinition *cpudef = data;
2355 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2356
2357 xcc->cpu_def = cpudef;
bd72159d 2358 xcc->migration_safe = true;
d940ee9b
EH		 2359}
2360
2361static void x86_register_cpudef_type(X86CPUDefinition *def)
2362{
2363 char *typename = x86_cpu_type_name(def->name);
2364 TypeInfo ti = {
2365 .name = typename,
2366 .parent = TYPE_X86_CPU,
2367 .class_init = x86_cpu_cpudef_class_init,
2368 .class_data = def,
2369 };
2370
2a923a29
EH		 2371 /* AMD aliases are handled at runtime based on CPUID vendor, so
2372 * they shouldn't be set on the CPU model table.
2373 */
2374 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
2375
d940ee9b
EH		 2376 type_register(&ti);
2377 g_free(typename);
2378}
2379
c6dc6f63 2380#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2381
0e26b7b8
BS		 2382void cpu_clear_apic_feature(CPUX86State *env)
2383{
0514ef2f 2384 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2385}
2386
c6dc6f63
AP		 2387#endif /* !CONFIG_USER_ONLY */
2388
c6dc6f63
AP		 2389void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2390 uint32_t *eax, uint32_t *ebx,
2391 uint32_t *ecx, uint32_t *edx)
2392{
a60f24b5
AF		 2393 X86CPU *cpu = x86_env_get_cpu(env);
2394 CPUState *cs = CPU(cpu);
14c985cf 2395 uint32_t pkg_offset;
a60f24b5 2396
c6dc6f63
AP		 2397 /* test if maximum index reached */
2398 if (index & 0x80000000) {
b3baa152
BW		 2399 if (index > env->cpuid_xlevel) {
2400 if (env->cpuid_xlevel2 > 0) {
2401 /* Handle the Centaur's CPUID instruction. */
2402 if (index > env->cpuid_xlevel2) {
2403 index = env->cpuid_xlevel2;
2404 } else if (index < 0xC0000000) {
2405 index = env->cpuid_xlevel;
2406 }
2407 } else {
57f26ae7
EH		 2408 /* Intel documentation states that invalid EAX input will
2409 * return the same information as EAX=cpuid_level
2410 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2411 */
2412 index = env->cpuid_level;
b3baa152
BW		 2413 }
2414 }
c6dc6f63
AP		 2415 } else {
2416 if (index > env->cpuid_level)
2417 index = env->cpuid_level;
2418 }
2419
2420 switch(index) {
2421 case 0:
2422 *eax = env->cpuid_level;
5eb2f7a4
EH		 2423 *ebx = env->cpuid_vendor1;
2424 *edx = env->cpuid_vendor2;
2425 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2426 break;
2427 case 1:
2428 *eax = env->cpuid_version;
7e72a45c
EH		 2429 *ebx = (cpu->apic_id << 24) |
2430 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2431 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2432 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2433 *ecx |= CPUID_EXT_OSXSAVE;
2434 }
0514ef2f 2435 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2436 if (cs->nr_cores * cs->nr_threads > 1) {
2437 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2438 *edx |= CPUID_HT;
c6dc6f63
AP		 2439 }
2440 break;
2441 case 2:
2442 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2443 if (cpu->cache_info_passthrough) {
2444 host_cpuid(index, 0, eax, ebx, ecx, edx);
2445 break;
2446 }
5e891bf8 2447 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 2448 *ebx = 0;
14c985cf
LM		 2449 if (!cpu->enable_l3_cache) {
2450 *ecx = 0;
2451 } else {
2452 *ecx = L3_N_DESCRIPTOR;
2453 }
5e891bf8
EH		 2454 *edx = (L1D_DESCRIPTOR << 16) | \
2455 (L1I_DESCRIPTOR << 8) | \
2456 (L2_DESCRIPTOR);
c6dc6f63
AP		 2457 break;
2458 case 4:
2459 /* cache info: needed for Core compatibility */
787aaf57
BC		 2460 if (cpu->cache_info_passthrough) {
2461 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2462 *eax &= ~0xFC000000;
c6dc6f63 2463 } else {
2f7a21c4 2464 *eax = 0;
76c2975a 2465 switch (count) {
c6dc6f63 2466 case 0: /* L1 dcache info */
5e891bf8
EH		 2467 *eax |= CPUID_4_TYPE_DCACHE | \
2468 CPUID_4_LEVEL(1) | \
2469 CPUID_4_SELF_INIT_LEVEL;
2470 *ebx = (L1D_LINE_SIZE - 1) | \
2471 ((L1D_PARTITIONS - 1) << 12) | \
2472 ((L1D_ASSOCIATIVITY - 1) << 22);
2473 *ecx = L1D_SETS - 1;
2474 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2475 break;
2476 case 1: /* L1 icache info */
5e891bf8
EH		 2477 *eax |= CPUID_4_TYPE_ICACHE | \
2478 CPUID_4_LEVEL(1) | \
2479 CPUID_4_SELF_INIT_LEVEL;
2480 *ebx = (L1I_LINE_SIZE - 1) | \
2481 ((L1I_PARTITIONS - 1) << 12) | \
2482 ((L1I_ASSOCIATIVITY - 1) << 22);
2483 *ecx = L1I_SETS - 1;
2484 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2485 break;
2486 case 2: /* L2 cache info */
5e891bf8
EH		 2487 *eax |= CPUID_4_TYPE_UNIFIED | \
2488 CPUID_4_LEVEL(2) | \
2489 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2490 if (cs->nr_threads > 1) {
2491 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2492 }
5e891bf8
EH		 2493 *ebx = (L2_LINE_SIZE - 1) | \
2494 ((L2_PARTITIONS - 1) << 12) | \
2495 ((L2_ASSOCIATIVITY - 1) << 22);
2496 *ecx = L2_SETS - 1;
2497 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63 2498 break;
14c985cf
LM		 2499 case 3: /* L3 cache info */
2500 if (!cpu->enable_l3_cache) {
2501 *eax = 0;
2502 *ebx = 0;
2503 *ecx = 0;
2504 *edx = 0;
2505 break;
2506 }
2507 *eax |= CPUID_4_TYPE_UNIFIED | \
2508 CPUID_4_LEVEL(3) | \
2509 CPUID_4_SELF_INIT_LEVEL;
2510 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2511 *eax |= ((1 << pkg_offset) - 1) << 14;
2512 *ebx = (L3_N_LINE_SIZE - 1) | \
2513 ((L3_N_PARTITIONS - 1) << 12) | \
2514 ((L3_N_ASSOCIATIVITY - 1) << 22);
2515 *ecx = L3_N_SETS - 1;
2516 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2517 break;
c6dc6f63
AP		 2518 default: /* end of info */
2519 *eax = 0;
2520 *ebx = 0;
2521 *ecx = 0;
2522 *edx = 0;
2523 break;
76c2975a
PB		 2524 }
2525 }
2526
2527 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2528 if ((*eax & 31) && cs->nr_cores > 1) {
2529 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2530 }
2531 break;
2532 case 5:
2533 /* mwait info: needed for Core compatibility */
2534 *eax = 0; /* Smallest monitor-line size in bytes */
2535 *ebx = 0; /* Largest monitor-line size in bytes */
2536 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2537 *edx = 0;
2538 break;
2539 case 6:
2540 /* Thermal and Power Leaf */
28b8e4d0 2541 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2542 *ebx = 0;
2543 *ecx = 0;
2544 *edx = 0;
2545 break;
f7911686 2546 case 7:
13526728
EH		 2547 /* Structured Extended Feature Flags Enumeration Leaf */
2548 if (count == 0) {
2549 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2550 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2551 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2552 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2553 *ecx |= CPUID_7_0_ECX_OSPKE;
2554 }
95ea69fb 2555 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 2556 } else {
2557 *eax = 0;
2558 *ebx = 0;
2559 *ecx = 0;
2560 *edx = 0;
2561 }
2562 break;
c6dc6f63
AP		 2563 case 9:
2564 /* Direct Cache Access Information Leaf */
2565 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2566 *ebx = 0;
2567 *ecx = 0;
2568 *edx = 0;
2569 break;
2570 case 0xA:
2571 /* Architectural Performance Monitoring Leaf */
9337e3b6 2572 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2573 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2574
2575 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2576 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2577 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2578 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2579 } else {
2580 *eax = 0;
2581 *ebx = 0;
2582 *ecx = 0;
2583 *edx = 0;
2584 }
c6dc6f63 2585 break;
5232d00a
RK		 2586 case 0xB:
2587 /* Extended Topology Enumeration Leaf */
2588 if (!cpu->enable_cpuid_0xb) {
2589 *eax = *ebx = *ecx = *edx = 0;
2590 break;
2591 }
2592
2593 *ecx = count & 0xff;
2594 *edx = cpu->apic_id;
2595
2596 switch (count) {
2597 case 0:
eab60fb9
MAL		 2598 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
2599 *ebx = cs->nr_threads;
5232d00a
RK		 2600 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2601 break;
2602 case 1:
eab60fb9
MAL		 2603 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2604 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 2605 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2606 break;
2607 default:
2608 *eax = 0;
2609 *ebx = 0;
2610 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2611 }
2612
2613 assert(!(*eax & ~0x1f));
2614 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2615 break;
2560f19f 2616 case 0xD: {
51e49430 2617 /* Processor Extended State */
2560f19f
PB		 2618 *eax = 0;
2619 *ebx = 0;
2620 *ecx = 0;
2621 *edx = 0;
19dc85db 2622 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2623 break;
2624 }
4928cd6d 2625
2560f19f 2626 if (count == 0) {
96193c22
EH		 2627 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
2628 *eax = env->features[FEAT_XSAVE_COMP_LO];
2629 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 2630 *ebx = *ecx;
2631 } else if (count == 1) {
0bb0b2d2 2632 *eax = env->features[FEAT_XSAVE];
f4f1110e 2633 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 2634 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
2635 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 2636 *eax = esa->size;
2637 *ebx = esa->offset;
2560f19f 2638 }
51e49430
SY		 2639 }
2640 break;
2560f19f 2641 }
c6dc6f63
AP		 2642 case 0x80000000:
2643 *eax = env->cpuid_xlevel;
2644 *ebx = env->cpuid_vendor1;
2645 *edx = env->cpuid_vendor2;
2646 *ecx = env->cpuid_vendor3;
2647 break;
2648 case 0x80000001:
2649 *eax = env->cpuid_version;
2650 *ebx = 0;
0514ef2f
EH		 2651 *ecx = env->features[FEAT_8000_0001_ECX];
2652 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2653
2654 /* The Linux kernel checks for the CMPLegacy bit and
2655 * discards multiple thread information if it is set.
cb8d4c8f 2656 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2657 */
ce3960eb 2658 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2659 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2660 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2661 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2662 *ecx |= 1 << 1; /* CmpLegacy bit */
2663 }
2664 }
c6dc6f63
AP		 2665 break;
2666 case 0x80000002:
2667 case 0x80000003:
2668 case 0x80000004:
2669 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2670 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2671 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2672 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2673 break;
2674 case 0x80000005:
2675 /* cache info (L1 cache) */
787aaf57
BC		 2676 if (cpu->cache_info_passthrough) {
2677 host_cpuid(index, 0, eax, ebx, ecx, edx);
2678 break;
2679 }
5e891bf8
EH		 2680 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2681 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2682 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2683 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2684 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2685 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2686 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2687 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2688 break;
2689 case 0x80000006:
2690 /* cache info (L2 cache) */
787aaf57
BC		 2691 if (cpu->cache_info_passthrough) {
2692 host_cpuid(index, 0, eax, ebx, ecx, edx);
2693 break;
2694 }
5e891bf8
EH		 2695 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2696 (L2_DTLB_2M_ENTRIES << 16) | \
2697 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2698 (L2_ITLB_2M_ENTRIES);
2699 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2700 (L2_DTLB_4K_ENTRIES << 16) | \
2701 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2702 (L2_ITLB_4K_ENTRIES);
2703 *ecx = (L2_SIZE_KB_AMD << 16) | \
2704 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2705 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
14c985cf
LM		 2706 if (!cpu->enable_l3_cache) {
2707 *edx = ((L3_SIZE_KB / 512) << 18) | \
2708 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2709 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2710 } else {
2711 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
2712 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
2713 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
2714 }
c6dc6f63 2715 break;
303752a9
MT		 2716 case 0x80000007:
2717 *eax = 0;
2718 *ebx = 0;
2719 *ecx = 0;
2720 *edx = env->features[FEAT_8000_0007_EDX];
2721 break;
c6dc6f63
AP		 2722 case 0x80000008:
2723 /* virtual & phys address size in low 2 bytes. */
0514ef2f 2724 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 2725 /* 64 bit processor */
2726 *eax = cpu->phys_bits; /* configurable physical bits */
2727 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
2728 *eax |= 0x00003900; /* 57 bits virtual */
2729 } else {
2730 *eax |= 0x00003000; /* 48 bits virtual */
2731 }
c6dc6f63 2732 } else {
af45907a 2733 *eax = cpu->phys_bits;
c6dc6f63
AP		 2734 }
2735 *ebx = 0;
2736 *ecx = 0;
2737 *edx = 0;
ce3960eb
AF		 2738 if (cs->nr_cores * cs->nr_threads > 1) {
2739 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2740 }
2741 break;
2742 case 0x8000000A:
0514ef2f 2743 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2744 *eax = 0x00000001; /* SVM Revision */
2745 *ebx = 0x00000010; /* nr of ASIDs */
2746 *ecx = 0;
0514ef2f 2747 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2748 } else {
2749 *eax = 0;
2750 *ebx = 0;
2751 *ecx = 0;
2752 *edx = 0;
2753 }
c6dc6f63 2754 break;
b3baa152
BW		 2755 case 0xC0000000:
2756 *eax = env->cpuid_xlevel2;
2757 *ebx = 0;
2758 *ecx = 0;
2759 *edx = 0;
2760 break;
2761 case 0xC0000001:
2762 /* Support for VIA CPU's CPUID instruction */
2763 *eax = env->cpuid_version;
2764 *ebx = 0;
2765 *ecx = 0;
0514ef2f 2766 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2767 break;
2768 case 0xC0000002:
2769 case 0xC0000003:
2770 case 0xC0000004:
2771 /* Reserved for the future, and now filled with zero */
2772 *eax = 0;
2773 *ebx = 0;
2774 *ecx = 0;
2775 *edx = 0;
2776 break;
c6dc6f63
AP		 2777 default:
2778 /* reserved values: zero */
2779 *eax = 0;
2780 *ebx = 0;
2781 *ecx = 0;
2782 *edx = 0;
2783 break;
2784 }
2785}
5fd2087a
AF		 2786
2787/* CPUClass::reset() */
2788static void x86_cpu_reset(CPUState *s)
2789{
2790 X86CPU *cpu = X86_CPU(s);
2791 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2792 CPUX86State *env = &cpu->env;
a114d25d
RH		 2793 target_ulong cr4;
2794 uint64_t xcr0;
c1958aea
AF		 2795 int i;
2796
5fd2087a
AF		 2797 xcc->parent_reset(s);
2798
5e992a8e 2799 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 2800
c1958aea
AF		 2801 env->old_exception = -1;
2802
2803 /* init to reset state */
2804
c1958aea
AF		 2805 env->hflags2 |= HF2_GIF_MASK;
2806
2807 cpu_x86_update_cr0(env, 0x60000010);
2808 env->a20_mask = ~0x0;
2809 env->smbase = 0x30000;
2810
2811 env->idt.limit = 0xffff;
2812 env->gdt.limit = 0xffff;
2813 env->ldt.limit = 0xffff;
2814 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2815 env->tr.limit = 0xffff;
2816 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2817
2818 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2819 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2820 DESC_R_MASK | DESC_A_MASK);
2821 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2822 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2823 DESC_A_MASK);
2824 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2825 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2826 DESC_A_MASK);
2827 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2828 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2829 DESC_A_MASK);
2830 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2831 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2832 DESC_A_MASK);
2833 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2834 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2835 DESC_A_MASK);
2836
2837 env->eip = 0xfff0;
2838 env->regs[R_EDX] = env->cpuid_version;
2839
2840 env->eflags = 0x2;
2841
2842 /* FPU init */
2843 for (i = 0; i < 8; i++) {
2844 env->fptags[i] = 1;
2845 }
5bde1407 2846 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2847
2848 env->mxcsr = 0x1f80;
a114d25d
RH		 2849 /* All units are in INIT state. */
2850 env->xstate_bv = 0;
c1958aea
AF		 2851
2852 env->pat = 0x0007040600070406ULL;
2853 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2854
2855 memset(env->dr, 0, sizeof(env->dr));
2856 env->dr[6] = DR6_FIXED_1;
2857 env->dr[7] = DR7_FIXED_1;
b3310ab3 2858 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2859 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2860
a114d25d 2861 cr4 = 0;
cfc3b074 2862 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 2863
2864#ifdef CONFIG_USER_ONLY
2865 /* Enable all the features for user-mode. */
2866 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 2867 xcr0 |= XSTATE_SSE_MASK;
a114d25d 2868 }
0f70ed47
PB		 2869 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2870 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 2871 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 2872 xcr0 |= 1ull << i;
2873 }
a114d25d 2874 }
0f70ed47 2875
a114d25d
RH		 2876 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2877 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2878 }
07929f2a
RH		 2879 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2880 cr4 |= CR4_FSGSBASE_MASK;
2881 }
a114d25d
RH		 2882#endif
2883
2884 env->xcr0 = xcr0;
2885 cpu_x86_update_cr4(env, cr4);
0522604b 2886
9db2efd9
AW		 2887 /*
2888 * SDM 11.11.5 requires:
2889 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2890 * - IA32_MTRR_PHYSMASKn.V = 0
2891 * All other bits are undefined. For simplification, zero it all.
2892 */
2893 env->mtrr_deftype = 0;
2894 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2895 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2896
dd673288
IM		 2897#if !defined(CONFIG_USER_ONLY)
2898 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2899 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2900
259186a7 2901 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2902
2903 if (kvm_enabled()) {
2904 kvm_arch_reset_vcpu(cpu);
2905 }
dd673288 2906#endif
5fd2087a
AF		 2907}
2908
dd673288
IM		 2909#ifndef CONFIG_USER_ONLY
2910bool cpu_is_bsp(X86CPU *cpu)
2911{
02e51483 2912 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2913}
65dee380
IM		 2914
2915/* TODO: remove me, when reset over QOM tree is implemented */
2916static void x86_cpu_machine_reset_cb(void *opaque)
2917{
2918 X86CPU *cpu = opaque;
2919 cpu_reset(CPU(cpu));
2920}
dd673288
IM		 2921#endif
2922
de024815
AF		 2923static void mce_init(X86CPU *cpu)
2924{
2925 CPUX86State *cenv = &cpu->env;
2926 unsigned int bank;
2927
2928 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2929 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 2930 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 2931 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
2932 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 2933 cenv->mcg_ctl = ~(uint64_t)0;
2934 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2935 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2936 }
2937 }
2938}
2939
bdeec802 2940#ifndef CONFIG_USER_ONLY
2f114315 2941APICCommonClass *apic_get_class(void)
bdeec802 2942{
bdeec802
IM		 2943 const char *apic_type = "apic";
2944
15eafc2e 2945 if (kvm_apic_in_kernel()) {
bdeec802
IM		 2946 apic_type = "kvm-apic";
2947 } else if (xen_enabled()) {
2948 apic_type = "xen-apic";
2949 }
2950
2f114315
RK		 2951 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
2952}
2953
2954static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2955{
2956 APICCommonState *apic;
2957 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
2958
2959 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 2960
6816b1b3
IM		 2961 object_property_add_child(OBJECT(cpu), "lapic",
2962 OBJECT(cpu->apic_state), &error_abort);
67e55caa 2963 object_unref(OBJECT(cpu->apic_state));
6816b1b3 2964
33d7a288 2965 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2966 /* TODO: convert to link<> */
02e51483 2967 apic = APIC_COMMON(cpu->apic_state);
60671e58 2968 apic->cpu = cpu;
8d42d2d3 2969 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 2970}
2971
2972static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2973{
8d42d2d3
CF		 2974 APICCommonState *apic;
2975 static bool apic_mmio_map_once;
2976
02e51483 2977 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2978 return;
2979 }
6e8e2651
MA		 2980 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2981 errp);
8d42d2d3
CF		 2982
2983 /* Map APIC MMIO area */
2984 apic = APIC_COMMON(cpu->apic_state);
2985 if (!apic_mmio_map_once) {
2986 memory_region_add_subregion_overlap(get_system_memory(),
2987 apic->apicbase &
2988 MSR_IA32_APICBASE_BASE,
2989 &apic->io_memory,
2990 0x1000);
2991 apic_mmio_map_once = true;
2992 }
bdeec802 2993}
f809c605
PB		 2994
2995static void x86_cpu_machine_done(Notifier *n, void *unused)
2996{
2997 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2998 MemoryRegion *smram =
2999 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
3000
3001 if (smram) {
3002 cpu->smram = g_new(MemoryRegion, 1);
3003 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
3004 smram, 0, 1ull << 32);
3005 memory_region_set_enabled(cpu->smram, false);
3006 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
3007 }
3008}
d3c64d6a
IM		 3009#else
3010static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3011{
3012}
bdeec802
IM		 3013#endif
3014
11f6fee5
DDAG		 3015/* Note: Only safe for use on x86(-64) hosts */
3016static uint32_t x86_host_phys_bits(void)
3017{
3018 uint32_t eax;
3019 uint32_t host_phys_bits;
3020
3021 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
3022 if (eax >= 0x80000008) {
3023 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
3024 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3025 * at 23:16 that can specify a maximum physical address bits for
3026 * the guest that can override this value; but I've not seen
3027 * anything with that set.
3028 */
3029 host_phys_bits = eax & 0xff;
3030 } else {
3031 /* It's an odd 64 bit machine that doesn't have the leaf for
3032 * physical address bits; fall back to 36 that's most older
3033 * Intel.
3034 */
3035 host_phys_bits = 36;
3036 }
3037
3038 return host_phys_bits;
3039}
e48638fd 3040
c39c0edf
EH		 3041static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
3042{
3043 if (*min < value) {
3044 *min = value;
3045 }
3046}
3047
3048/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3049static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
3050{
3051 CPUX86State *env = &cpu->env;
3052 FeatureWordInfo *fi = &feature_word_info[w];
3053 uint32_t eax = fi->cpuid_eax;
3054 uint32_t region = eax & 0xF0000000;
3055
3056 if (!env->features[w]) {
3057 return;
3058 }
3059
3060 switch (region) {
3061 case 0x00000000:
3062 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
3063 break;
3064 case 0x80000000:
3065 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
3066 break;
3067 case 0xC0000000:
3068 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
3069 break;
3070 }
3071}
3072
2ca8a8be
EH		 3073/* Calculate XSAVE components based on the configured CPU feature flags */
3074static void x86_cpu_enable_xsave_components(X86CPU *cpu)
3075{
3076 CPUX86State *env = &cpu->env;
3077 int i;
96193c22 3078 uint64_t mask;
2ca8a8be
EH		 3079
3080 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
3081 return;
3082 }
3083
e3c9022b
EH		 3084 mask = 0;
3085 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 3086 const ExtSaveArea *esa = &x86_ext_save_areas[i];
3087 if (env->features[esa->feature] & esa->bits) {
96193c22 3088 mask |= (1ULL << i);
2ca8a8be
EH		 3089 }
3090 }
3091
96193c22
EH		 3092 env->features[FEAT_XSAVE_COMP_LO] = mask;
3093 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 3094}
3095
41f3d4d6
EH		 3096/* Load CPUID data based on configured features */
3097static void x86_cpu_load_features(X86CPU *cpu, Error **errp)
7a059953 3098{
b34d12d1 3099 CPUX86State *env = &cpu->env;
dc15c051 3100 FeatureWord w;
2fae0d96 3101 GList *l;
41f3d4d6 3102 Error *local_err = NULL;
9886e834 3103
44bd8e53 3104 /*TODO: cpu->max_features incorrectly overwrites features
dc15c051
IM		 3105 * set using "feat=on|off". Once we fix this, we can convert
3106 * plus_features & minus_features to global properties
3107 * inside x86_cpu_parse_featurestr() too.
3108 */
44bd8e53 3109 if (cpu->max_features) {
dc15c051
IM		 3110 for (w = 0; w < FEATURE_WORDS; w++) {
3111 env->features[w] =
3112 x86_cpu_get_supported_feature_word(w, cpu->migratable);
3113 }
3114 }
3115
2fae0d96
EH		 3116 for (l = plus_features; l; l = l->next) {
3117 const char *prop = l->data;
3118 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
3119 if (local_err) {
3120 goto out;
3121 }
3122 }
3123
3124 for (l = minus_features; l; l = l->next) {
3125 const char *prop = l->data;
3126 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
3127 if (local_err) {
3128 goto out;
3129 }
dc15c051
IM		 3130 }
3131
aec661de
EH		 3132 if (!kvm_enabled() || !cpu->expose_kvm) {
3133 env->features[FEAT_KVM] = 0;
3134 }
3135
2ca8a8be 3136 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 3137
3138 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3139 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
3140 if (cpu->full_cpuid_auto_level) {
3141 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
3142 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
3143 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
3144 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
3145 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
3146 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
3147 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
3148 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
3149 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
3150 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 3151 /* SVM requires CPUID[0x8000000A] */
3152 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
3153 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
3154 }
c39c0edf
EH		 3155 }
3156
3157 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3158 if (env->cpuid_level == UINT32_MAX) {
3159 env->cpuid_level = env->cpuid_min_level;
3160 }
3161 if (env->cpuid_xlevel == UINT32_MAX) {
3162 env->cpuid_xlevel = env->cpuid_min_xlevel;
3163 }
3164 if (env->cpuid_xlevel2 == UINT32_MAX) {
3165 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 3166 }
7a059953 3167
41f3d4d6
EH		 3168out:
3169 if (local_err != NULL) {
3170 error_propagate(errp, local_err);
3171 }
3172}
3173
3174#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3175 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3176 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3177#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3178 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3179 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
3180static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
3181{
3182 CPUState *cs = CPU(dev);
3183 X86CPU *cpu = X86_CPU(dev);
3184 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3185 CPUX86State *env = &cpu->env;
3186 Error *local_err = NULL;
3187 static bool ht_warned;
3188
3189 if (xcc->kvm_required && !kvm_enabled()) {
3190 char *name = x86_cpu_class_get_model_name(xcc);
3191 error_setg(&local_err, "CPU model '%s' requires KVM", name);
3192 g_free(name);
3193 goto out;
3194 }
3195
3196 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
3197 error_setg(errp, "apic-id property was not initialized properly");
3198 return;
3199 }
3200
3201 x86_cpu_load_features(cpu, &local_err);
3202 if (local_err) {
3203 goto out;
3204 }
3205
8ca30e86
EH		 3206 if (x86_cpu_filter_features(cpu) &&
3207 (cpu->check_cpuid || cpu->enforce_cpuid)) {
3208 x86_cpu_report_filtered_features(cpu);
3209 if (cpu->enforce_cpuid) {
3210 error_setg(&local_err,
3211 kvm_enabled() ?
3212 "Host doesn't support requested features" :
3213 "TCG doesn't support requested features");
3214 goto out;
3215 }
9997cf7b
EH		 3216 }
3217
9b15cd9e
IM		 3218 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3219 * CPUID[1].EDX.
3220 */
e48638fd 3221 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 3222 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3223 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 3224 & CPUID_EXT2_AMD_ALIASES);
3225 }
3226
11f6fee5
DDAG		 3227 /* For 64bit systems think about the number of physical bits to present.
3228 * ideally this should be the same as the host; anything other than matching
3229 * the host can cause incorrect guest behaviour.
3230 * QEMU used to pick the magic value of 40 bits that corresponds to
3231 * consumer AMD devices but nothing else.
3232 */
af45907a 3233 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a 3234 if (kvm_enabled()) {
11f6fee5
DDAG		 3235 uint32_t host_phys_bits = x86_host_phys_bits();
3236 static bool warned;
3237
3238 if (cpu->host_phys_bits) {
3239 /* The user asked for us to use the host physical bits */
3240 cpu->phys_bits = host_phys_bits;
3241 }
3242
3243 /* Print a warning if the user set it to a value that's not the
3244 * host value.
3245 */
3246 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3247 !warned) {
3248 error_report("Warning: Host physical bits (%u)"
3249 " does not match phys-bits property (%u)",
3250 host_phys_bits, cpu->phys_bits);
3251 warned = true;
3252 }
3253
3254 if (cpu->phys_bits &&
3255 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3256 cpu->phys_bits < 32)) {
af45907a
DDAG		 3257 error_setg(errp, "phys-bits should be between 32 and %u "
3258 " (but is %u)",
3259 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3260 return;
3261 }
3262 } else {
11f6fee5 3263 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 3264 error_setg(errp, "TCG only supports phys-bits=%u",
3265 TCG_PHYS_ADDR_BITS);
3266 return;
3267 }
3268 }
11f6fee5
DDAG		 3269 /* 0 means it was not explicitly set by the user (or by machine
3270 * compat_props or by the host code above). In this case, the default
3271 * is the value used by TCG (40).
3272 */
3273 if (cpu->phys_bits == 0) {
3274 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3275 }
af45907a
DDAG		 3276 } else {
3277 /* For 32 bit systems don't use the user set value, but keep
3278 * phys_bits consistent with what we tell the guest.
3279 */
3280 if (cpu->phys_bits != 0) {
3281 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3282 return;
3283 }
fefb41bf 3284
af45907a
DDAG		 3285 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3286 cpu->phys_bits = 36;
3287 } else {
3288 cpu->phys_bits = 32;
3289 }
3290 }
ce5b1bbf
LV		 3291 cpu_exec_realizefn(cs, &local_err);
3292 if (local_err != NULL) {
3293 error_propagate(errp, local_err);
3294 return;
3295 }
42ecabaa 3296
57f2453a
EH		 3297 if (tcg_enabled()) {
3298 tcg_x86_init();
3299 }
3300
65dee380
IM		 3301#ifndef CONFIG_USER_ONLY
3302 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 3303
0514ef2f 3304 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 3305 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 3306 if (local_err != NULL) {
4dc1f449 3307 goto out;
bdeec802
IM		 3308 }
3309 }
65dee380
IM		 3310#endif
3311
7a059953 3312 mce_init(cpu);
2001d0cd
PB		 3313
3314#ifndef CONFIG_USER_ONLY
3315 if (tcg_enabled()) {
56943e8c
PM		 3316 AddressSpace *newas = g_new(AddressSpace, 1);
3317
f809c605 3318 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 3319 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 3320
3321 /* Outer container... */
3322 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 3323 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 3324
3325 /* ... with two regions inside: normal system memory with low
3326 * priority, and...
3327 */
3328 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3329 get_system_memory(), 0, ~0ull);
3330 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3331 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 3332 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 3333 cs->num_ases = 1;
56943e8c 3334 cpu_address_space_init(cs, newas, 0);
f809c605
PB		 3335
3336 /* ... SMRAM with higher priority, linked from /machine/smram. */
3337 cpu->machine_done.notify = x86_cpu_machine_done;
3338 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 3339 }
3340#endif
3341
14a10fc3 3342 qemu_init_vcpu(cs);
d3c64d6a 3343
e48638fd
WH		 3344 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3345 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3346 * based on inputs (sockets,cores,threads), it is still better to gives
3347 * users a warning.
3348 *
3349 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3350 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3351 */
3352 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3353 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3354 " -smp options properly.");
3355 ht_warned = true;
3356 }
3357
d3c64d6a
IM		 3358 x86_cpu_apic_realize(cpu, &local_err);
3359 if (local_err != NULL) {
3360 goto out;
3361 }
14a10fc3 3362 cpu_reset(cs);
2b6f294c 3363
4dc1f449 3364 xcc->parent_realize(dev, &local_err);
2001d0cd 3365
4dc1f449
IM		 3366out:
3367 if (local_err != NULL) {
3368 error_propagate(errp, local_err);
3369 return;
3370 }
7a059953
AF		 3371}
3372
c884776e
IM		 3373static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3374{
3375 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 3376 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3377 Error *local_err = NULL;
c884776e
IM		 3378
3379#ifndef CONFIG_USER_ONLY
3380 cpu_remove_sync(CPU(dev));
3381 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3382#endif
3383
3384 if (cpu->apic_state) {
3385 object_unparent(OBJECT(cpu->apic_state));
3386 cpu->apic_state = NULL;
3387 }
7bbc124e
LV		 3388
3389 xcc->parent_unrealize(dev, &local_err);
3390 if (local_err != NULL) {
3391 error_propagate(errp, local_err);
3392 return;
3393 }
c884776e
IM		 3394}
3395
38e5c119
EH		 3396typedef struct BitProperty {
3397 uint32_t *ptr;
3398 uint32_t mask;
3399} BitProperty;
3400
d7bce999
EB		 3401static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3402 void *opaque, Error **errp)
38e5c119
EH		 3403{
3404 BitProperty *fp = opaque;
3405 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 3406 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3407}
3408
d7bce999
EB		 3409static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3410 void *opaque, Error **errp)
38e5c119
EH		 3411{
3412 DeviceState *dev = DEVICE(obj);
3413 BitProperty *fp = opaque;
3414 Error *local_err = NULL;
3415 bool value;
3416
3417 if (dev->realized) {
3418 qdev_prop_set_after_realize(dev, name, errp);
3419 return;
3420 }
3421
51e72bc1 3422 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3423 if (local_err) {
3424 error_propagate(errp, local_err);
3425 return;
3426 }
3427
3428 if (value) {
3429 *fp->ptr |= fp->mask;
3430 } else {
3431 *fp->ptr &= ~fp->mask;
3432 }
3433}
3434
3435static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3436 void *opaque)
3437{
3438 BitProperty *prop = opaque;
3439 g_free(prop);
3440}
3441
3442/* Register a boolean property to get/set a single bit in a uint32_t field.
3443 *
3444 * The same property name can be registered multiple times to make it affect
3445 * multiple bits in the same FeatureWord. In that case, the getter will return
3446 * true only if all bits are set.
3447 */
3448static void x86_cpu_register_bit_prop(X86CPU *cpu,
3449 const char *prop_name,
3450 uint32_t *field,
3451 int bitnr)
3452{
3453 BitProperty *fp;
3454 ObjectProperty *op;
3455 uint32_t mask = (1UL << bitnr);
3456
3457 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3458 if (op) {
3459 fp = op->opaque;
3460 assert(fp->ptr == field);
3461 fp->mask |= mask;
3462 } else {
3463 fp = g_new0(BitProperty, 1);
3464 fp->ptr = field;
3465 fp->mask = mask;
3466 object_property_add(OBJECT(cpu), prop_name, "bool",
3467 x86_cpu_get_bit_prop,
3468 x86_cpu_set_bit_prop,
3469 x86_cpu_release_bit_prop, fp, &error_abort);
3470 }
3471}
3472
3473static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3474 FeatureWord w,
3475 int bitnr)
3476{
38e5c119 3477 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 3478 const char *name = fi->feat_names[bitnr];
38e5c119 3479
16d2fcaa 3480 if (!name) {
38e5c119
EH		 3481 return;
3482 }
3483
fc7dfd20
EH		 3484 /* Property names should use "-" instead of "_".
3485 * Old names containing underscores are registered as aliases
3486 * using object_property_add_alias()
3487 */
16d2fcaa
EH		 3488 assert(!strchr(name, '_'));
3489 /* aliases don't use "|" delimiters anymore, they are registered
3490 * manually using object_property_add_alias() */
3491 assert(!strchr(name, '|'));
3492 x86_cpu_register_bit_prop(cpu, name, &cpu->env.features[w], bitnr);
38e5c119
EH		 3493}
3494
d187e08d
AN		 3495static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
3496{
3497 X86CPU *cpu = X86_CPU(cs);
3498 CPUX86State *env = &cpu->env;
3499 GuestPanicInformation *panic_info = NULL;
3500
3501 if (env->features[FEAT_HYPERV_EDX] & HV_X64_GUEST_CRASH_MSR_AVAILABLE) {
3502 GuestPanicInformationHyperV *panic_info_hv =
3503 g_malloc0(sizeof(GuestPanicInformationHyperV));
3504 panic_info = g_malloc0(sizeof(GuestPanicInformation));
3505
3506 panic_info->type = GUEST_PANIC_INFORMATION_KIND_HYPER_V;
3507 panic_info->u.hyper_v.data = panic_info_hv;
3508
3509 assert(HV_X64_MSR_CRASH_PARAMS >= 5);
3510 panic_info_hv->arg1 = env->msr_hv_crash_params[0];
3511 panic_info_hv->arg2 = env->msr_hv_crash_params[1];
3512 panic_info_hv->arg3 = env->msr_hv_crash_params[2];
3513 panic_info_hv->arg4 = env->msr_hv_crash_params[3];
3514 panic_info_hv->arg5 = env->msr_hv_crash_params[4];
3515 }
3516
3517 return panic_info;
3518}
3519static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
3520 const char *name, void *opaque,
3521 Error **errp)
3522{
3523 CPUState *cs = CPU(obj);
3524 GuestPanicInformation *panic_info;
3525
3526 if (!cs->crash_occurred) {
3527 error_setg(errp, "No crash occured");
3528 return;
3529 }
3530
3531 panic_info = x86_cpu_get_crash_info(cs);
3532 if (panic_info == NULL) {
3533 error_setg(errp, "No crash information");
3534 return;
3535 }
3536
3537 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
3538 errp);
3539 qapi_free_GuestPanicInformation(panic_info);
3540}
3541
de024815
AF		 3542static void x86_cpu_initfn(Object *obj)
3543{
55e5c285 3544 CPUState *cs = CPU(obj);
de024815 3545 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3546 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3547 CPUX86State *env = &cpu->env;
38e5c119 3548 FeatureWord w;
de024815 3549
c05efcb1 3550 cs->env_ptr = env;
71ad61d3
AF		 3551
3552 object_property_add(obj, "family", "int",
95b8519d 3553 x86_cpuid_version_get_family,
71ad61d3 3554 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3555 object_property_add(obj, "model", "int",
67e30c83 3556 x86_cpuid_version_get_model,
c5291a4f 3557 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3558 object_property_add(obj, "stepping", "int",
35112e41 3559 x86_cpuid_version_get_stepping,
036e2222 3560 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3561 object_property_add_str(obj, "vendor",
3562 x86_cpuid_get_vendor,
3563 x86_cpuid_set_vendor, NULL);
938d4c25 3564 object_property_add_str(obj, "model-id",
63e886eb 3565 x86_cpuid_get_model_id,
938d4c25 3566 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3567 object_property_add(obj, "tsc-frequency", "int",
3568 x86_cpuid_get_tsc_freq,
3569 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 3570 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3571 x86_cpu_get_feature_words,
7e5292b5
EH		 3572 NULL, NULL, (void *)env->features, NULL);
3573 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3574 x86_cpu_get_feature_words,
3575 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3576
d187e08d
AN		 3577 object_property_add(obj, "crash-information", "GuestPanicInformation",
3578 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
3579
92067bf4 3580 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3581
38e5c119
EH		 3582 for (w = 0; w < FEATURE_WORDS; w++) {
3583 int bitnr;
3584
3585 for (bitnr = 0; bitnr < 32; bitnr++) {
3586 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3587 }
3588 }
3589
16d2fcaa
EH		 3590 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
3591 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
3592 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
3593 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
3594 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
3595 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
3596 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
3597
54b8dc7c
EH		 3598 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
3599 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
3600 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
3601 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
3602 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
3603 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
3604 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
3605 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
3606 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
3607 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
3608 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
3609 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
3610 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
3611 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
3612 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
3613 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
3614 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
3615 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
3616 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
3617 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
3618 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
3619
d940ee9b 3620 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
de024815
AF		 3621}
3622
997395d3
IM		 3623static int64_t x86_cpu_get_arch_id(CPUState *cs)
3624{
3625 X86CPU *cpu = X86_CPU(cs);
997395d3 3626
7e72a45c 3627 return cpu->apic_id;
997395d3
IM		 3628}
3629
444d5590
AF		 3630static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3631{
3632 X86CPU *cpu = X86_CPU(cs);
3633
3634 return cpu->env.cr[0] & CR0_PG_MASK;
3635}
3636
f45748f1
AF		 3637static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3638{
3639 X86CPU *cpu = X86_CPU(cs);
3640
3641 cpu->env.eip = value;
3642}
3643
bdf7ae5b
AF		 3644static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3645{
3646 X86CPU *cpu = X86_CPU(cs);
3647
3648 cpu->env.eip = tb->pc - tb->cs_base;
3649}
3650
8c2e1b00
AF		 3651static bool x86_cpu_has_work(CPUState *cs)
3652{
3653 X86CPU *cpu = X86_CPU(cs);
3654 CPUX86State *env = &cpu->env;
3655
6220e900
PD		 3656 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3657 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3658 (env->eflags & IF_MASK)) ||
3659 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3660 CPU_INTERRUPT_INIT |
3661 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3662 CPU_INTERRUPT_MCE)) ||
3663 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3664 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3665}
3666
9337e3b6 3667static Property x86_cpu_properties[] = {
2da00e31
IM		 3668#ifdef CONFIG_USER_ONLY
3669 /* apic_id = 0 by default for *-user, see commit 9886e834 */
3670 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 3671 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
3672 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
3673 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 3674#else
3675 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 3676 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
3677 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
3678 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 3679#endif
9337e3b6 3680 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3681 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3682 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3683 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3684 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3685 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3686 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3687 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3688 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3689 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3690 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3691 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3692 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3693 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 3694 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 3695 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 3696 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 3697 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
3698 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
3699 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
3700 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
3701 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
3702 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
3703 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 3704 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 3705 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 3706 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 3707 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
0b564e6f 3708 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
9337e3b6
EH		 3709 DEFINE_PROP_END_OF_LIST()
3710};
3711
5fd2087a
AF		 3712static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3713{
3714 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3715 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3716 DeviceClass *dc = DEVICE_CLASS(oc);
3717
3718 xcc->parent_realize = dc->realize;
7bbc124e 3719 xcc->parent_unrealize = dc->unrealize;
2b6f294c 3720 dc->realize = x86_cpu_realizefn;
c884776e 3721 dc->unrealize = x86_cpu_unrealizefn;
9337e3b6 3722 dc->props = x86_cpu_properties;
5fd2087a
AF		 3723
3724 xcc->parent_reset = cc->reset;
3725 cc->reset = x86_cpu_reset;
91b1df8c 3726 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3727
500050d1 3728 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3729 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3730 cc->has_work = x86_cpu_has_work;
97a8ea5a 3731 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3732 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3733 cc->dump_state = x86_cpu_dump_state;
c86f106b 3734 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 3735 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3736 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3737 cc->gdb_read_register = x86_cpu_gdb_read_register;
3738 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3739 cc->get_arch_id = x86_cpu_get_arch_id;
3740 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3741#ifdef CONFIG_USER_ONLY
3742 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3743#else
a23bbfda 3744 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3745 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3746 cc->write_elf64_note = x86_cpu_write_elf64_note;
3747 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3748 cc->write_elf32_note = x86_cpu_write_elf32_note;
3749 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3750 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3751#endif
175cad36
DE		 3752 /* CPU_NB_REGS * 2 = general regs + xmm regs
3753 * 25 = eip, eflags, 6 seg regs, st[0-7], fctrl,...,fop, mxcsr.
3754 */
a0e372f0 3755 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3756#ifndef CONFIG_USER_ONLY
3757 cc->debug_excp_handler = breakpoint_handler;
3758#endif
374e0cd4
RH		 3759 cc->cpu_exec_enter = x86_cpu_exec_enter;
3760 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27 3761
edd12111 3762 dc->cannot_instantiate_with_device_add_yet = false;
5fd2087a
AF		 3763}
3764
3765static const TypeInfo x86_cpu_type_info = {
3766 .name = TYPE_X86_CPU,
3767 .parent = TYPE_CPU,
3768 .instance_size = sizeof(X86CPU),
de024815 3769 .instance_init = x86_cpu_initfn,
d940ee9b 3770 .abstract = true,
5fd2087a
AF		 3771 .class_size = sizeof(X86CPUClass),
3772 .class_init = x86_cpu_common_class_init,
3773};
3774
3775static void x86_cpu_register_types(void)
3776{
d940ee9b
EH		 3777 int i;
3778
5fd2087a 3779 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3780 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3781 x86_register_cpudef_type(&builtin_x86_defs[i]);
3782 }
3783#ifdef CONFIG_KVM
3784 type_register_static(&host_x86_cpu_type_info);
3785#endif
5fd2087a
AF		 3786}
3787
3788type_init(x86_cpu_register_types)
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