]> git.proxmox.com Git - mirror_qemu.git/blame - target/i386/cpu.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i386: Define static "base" CPU model
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
b834b508 38#if defined(CONFIG_KVM)
ef8621b1 39#include <linux/kvm_para.h>
b834b508 40#endif
65dee380 41
9c17d615 42#include "sysemu/sysemu.h"
53a89e26 43#include "hw/qdev-properties.h"
5232d00a 44#include "hw/i386/topology.h"
bdeec802 45#ifndef CONFIG_USER_ONLY
2001d0cd 46#include "exec/address-spaces.h"
741da0d3 47#include "hw/hw.h"
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
14c985cf 60#define CPUID_2_L3_16MB_16WAY_64B 0x4d
5e891bf8
EH		 61
62
63/* CPUID Leaf 4 constants: */
64
65/* EAX: */
66#define CPUID_4_TYPE_DCACHE 1
67#define CPUID_4_TYPE_ICACHE 2
68#define CPUID_4_TYPE_UNIFIED 3
69
70#define CPUID_4_LEVEL(l) ((l) << 5)
71
72#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73#define CPUID_4_FULLY_ASSOC (1 << 9)
74
75/* EDX: */
76#define CPUID_4_NO_INVD_SHARING (1 << 0)
77#define CPUID_4_INCLUSIVE (1 << 1)
78#define CPUID_4_COMPLEX_IDX (1 << 2)
79
80#define ASSOC_FULL 0xFF
81
82/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
84 a == 2 ? 0x2 : \
85 a == 4 ? 0x4 : \
86 a == 8 ? 0x6 : \
87 a == 16 ? 0x8 : \
88 a == 32 ? 0xA : \
89 a == 48 ? 0xB : \
90 a == 64 ? 0xC : \
91 a == 96 ? 0xD : \
92 a == 128 ? 0xE : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
95
96
97/* Definitions of the hardcoded cache entries we expose: */
98
99/* L1 data cache: */
100#define L1D_LINE_SIZE 64
101#define L1D_ASSOCIATIVITY 8
102#define L1D_SETS 64
103#define L1D_PARTITIONS 1
104/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107#define L1D_LINES_PER_TAG 1
108#define L1D_SIZE_KB_AMD 64
109#define L1D_ASSOCIATIVITY_AMD 2
110
111/* L1 instruction cache: */
112#define L1I_LINE_SIZE 64
113#define L1I_ASSOCIATIVITY 8
114#define L1I_SETS 64
115#define L1I_PARTITIONS 1
116/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119#define L1I_LINES_PER_TAG 1
120#define L1I_SIZE_KB_AMD 64
121#define L1I_ASSOCIATIVITY_AMD 2
122
123/* Level 2 unified cache: */
124#define L2_LINE_SIZE 64
125#define L2_ASSOCIATIVITY 16
126#define L2_SETS 4096
127#define L2_PARTITIONS 1
128/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132#define L2_LINES_PER_TAG 1
133#define L2_SIZE_KB_AMD 512
134
14c985cf 135/* Level 3 unified cache: */
5e891bf8
EH		 136#define L3_SIZE_KB 0 /* disabled */
137#define L3_ASSOCIATIVITY 0 /* disabled */
138#define L3_LINES_PER_TAG 0 /* disabled */
139#define L3_LINE_SIZE 0 /* disabled */
14c985cf
LM		 140#define L3_N_LINE_SIZE 64
141#define L3_N_ASSOCIATIVITY 16
142#define L3_N_SETS 16384
143#define L3_N_PARTITIONS 1
144#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
145#define L3_N_LINES_PER_TAG 1
146#define L3_N_SIZE_KB_AMD 16384
5e891bf8
EH		 147
148/* TLB definitions: */
149
150#define L1_DTLB_2M_ASSOC 1
151#define L1_DTLB_2M_ENTRIES 255
152#define L1_DTLB_4K_ASSOC 1
153#define L1_DTLB_4K_ENTRIES 255
154
155#define L1_ITLB_2M_ASSOC 1
156#define L1_ITLB_2M_ENTRIES 255
157#define L1_ITLB_4K_ASSOC 1
158#define L1_ITLB_4K_ENTRIES 255
159
160#define L2_DTLB_2M_ASSOC 0 /* disabled */
161#define L2_DTLB_2M_ENTRIES 0 /* disabled */
162#define L2_DTLB_4K_ASSOC 4
163#define L2_DTLB_4K_ENTRIES 512
164
165#define L2_ITLB_2M_ASSOC 0 /* disabled */
166#define L2_ITLB_2M_ENTRIES 0 /* disabled */
167#define L2_ITLB_4K_ASSOC 4
168#define L2_ITLB_4K_ENTRIES 512
169
170
171
99b88a17
IM		 172static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
173 uint32_t vendor2, uint32_t vendor3)
174{
175 int i;
176 for (i = 0; i < 4; i++) {
177 dst[i] = vendor1 >> (8 * i);
178 dst[i + 4] = vendor2 >> (8 * i);
179 dst[i + 8] = vendor3 >> (8 * i);
180 }
181 dst[CPUID_VENDOR_SZ] = '\0';
182}
183
621626ce
EH		 184#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
185#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
186 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
187#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
188 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
189 CPUID_PSE36 | CPUID_FXSR)
190#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
191#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
192 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
193 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
194 CPUID_PAE | CPUID_SEP | CPUID_APIC)
195
196#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
197 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
198 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
199 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 200 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 201 /* partly implemented:
202 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
203 /* missing:
204 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
205#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
206 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
207 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 208 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 209 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
210 /* missing:
211 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
212 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
213 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 214 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
215 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 216
217#ifdef TARGET_X86_64
218#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
219#else
220#define TCG_EXT2_X86_64_FEATURES 0
221#endif
222
223#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
224 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
225 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
226 TCG_EXT2_X86_64_FEATURES)
227#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
228 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
229#define TCG_EXT4_FEATURES 0
230#define TCG_SVM_FEATURES 0
231#define TCG_KVM_FEATURES 0
232#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 233 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
234 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 235 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
236 CPUID_7_0_EBX_ERMS)
621626ce 237 /* missing:
07929f2a 238 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 239 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 240 CPUID_7_0_EBX_RDSEED */
6c7c3c21
KS		 241#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
242 CPUID_7_0_ECX_LA57)
95ea69fb 243#define TCG_7_0_EDX_FEATURES 0
303752a9 244#define TCG_APM_FEATURES 0
28b8e4d0 245#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 246#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
247 /* missing:
248 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 249
5ef57876 250typedef struct FeatureWordInfo {
2d5312da
EH		 251 /* feature flags names are taken from "Intel Processor Identification and
252 * the CPUID Instruction" and AMD's "CPUID Specification".
253 * In cases of disagreement between feature naming conventions,
254 * aliases may be added.
255 */
256 const char *feat_names[32];
04d104b6
EH		 257 uint32_t cpuid_eax; /* Input EAX for CPUID */
258 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
259 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
260 int cpuid_reg; /* output register (R_* constant) */
37ce3522 261 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 262 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 263 uint32_t migratable_flags; /* Feature flags known to be migratable */
5ef57876
EH		 264} FeatureWordInfo;
265
266static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 267 [FEAT_1_EDX] = {
2d5312da
EH		 268 .feat_names = {
269 "fpu", "vme", "de", "pse",
270 "tsc", "msr", "pae", "mce",
271 "cx8", "apic", NULL, "sep",
272 "mtrr", "pge", "mca", "cmov",
273 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
274 NULL, "ds" /* Intel dts */, "acpi", "mmx",
275 "fxsr", "sse", "sse2", "ss",
276 "ht" /* Intel htt */, "tm", "ia64", "pbe",
277 },
bffd67b0 278 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 279 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 280 },
281 [FEAT_1_ECX] = {
2d5312da 282 .feat_names = {
16d2fcaa 283 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 284 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 285 "tm2", "ssse3", "cid", NULL,
286 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 287 NULL, "pcid", "dca", "sse4.1",
288 "sse4.2", "x2apic", "movbe", "popcnt",
2d5312da
EH		 289 "tsc-deadline", "aes", "xsave", "osxsave",
290 "avx", "f16c", "rdrand", "hypervisor",
291 },
bffd67b0 292 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 293 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 294 },
2d5312da
EH		 295 /* Feature names that are already defined on feature_name[] but
296 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
297 * names on feat_names below. They are copied automatically
298 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
299 */
bffd67b0 300 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 301 .feat_names = {
302 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
303 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
304 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
305 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
306 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 307 "nx", NULL, "mmxext", NULL /* mmx */,
308 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
309 NULL, "lm", "3dnowext", "3dnow",
2d5312da 310 },
bffd67b0 311 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 312 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 313 },
314 [FEAT_8000_0001_ECX] = {
2d5312da 315 .feat_names = {
fc7dfd20 316 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 317 "cr8legacy", "abm", "sse4a", "misalignsse",
318 "3dnowprefetch", "osvw", "ibs", "xop",
319 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 320 "fma4", "tce", NULL, "nodeid-msr",
321 NULL, "tbm", "topoext", "perfctr-core",
322 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 323 NULL, NULL, NULL, NULL,
324 },
bffd67b0 325 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 326 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 327 },
89e49c8b 328 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 329 .feat_names = {
330 NULL, NULL, "xstore", "xstore-en",
331 NULL, NULL, "xcrypt", "xcrypt-en",
332 "ace2", "ace2-en", "phe", "phe-en",
333 "pmm", "pmm-en", NULL, NULL,
334 NULL, NULL, NULL, NULL,
335 NULL, NULL, NULL, NULL,
336 NULL, NULL, NULL, NULL,
337 NULL, NULL, NULL, NULL,
338 },
89e49c8b 339 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 340 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 341 },
bffd67b0 342 [FEAT_KVM] = {
2d5312da 343 .feat_names = {
fc7dfd20
EH		 344 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
345 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
2d5312da
EH		 346 NULL, NULL, NULL, NULL,
347 NULL, NULL, NULL, NULL,
348 NULL, NULL, NULL, NULL,
349 NULL, NULL, NULL, NULL,
350 "kvmclock-stable-bit", NULL, NULL, NULL,
351 NULL, NULL, NULL, NULL,
352 },
bffd67b0 353 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 354 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 355 },
c35bd19a 356 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 357 .feat_names = {
358 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
359 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
360 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
361 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
362 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
363 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
364 NULL, NULL, NULL, NULL,
365 NULL, NULL, NULL, NULL,
366 NULL, NULL, NULL, NULL,
367 NULL, NULL, NULL, NULL,
368 NULL, NULL, NULL, NULL,
369 },
c35bd19a
EY		 370 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
371 },
372 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 373 .feat_names = {
374 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
375 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
376 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
377 NULL /* hv_create_port */, NULL /* hv_connect_port */,
378 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
379 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
380 NULL, NULL,
381 NULL, NULL, NULL, NULL,
382 NULL, NULL, NULL, NULL,
383 NULL, NULL, NULL, NULL,
384 NULL, NULL, NULL, NULL,
385 },
c35bd19a
EY		 386 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
387 },
388 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 389 .feat_names = {
390 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
391 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
392 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
393 NULL, NULL,
394 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
395 NULL, NULL, NULL, NULL,
396 NULL, NULL, NULL, NULL,
397 NULL, NULL, NULL, NULL,
398 NULL, NULL, NULL, NULL,
399 NULL, NULL, NULL, NULL,
400 },
c35bd19a
EY		 401 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
402 },
bffd67b0 403 [FEAT_SVM] = {
2d5312da 404 .feat_names = {
fc7dfd20
EH		 405 "npt", "lbrv", "svm-lock", "nrip-save",
406 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
407 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 408 "pfthreshold", NULL, NULL, NULL,
409 NULL, NULL, NULL, NULL,
410 NULL, NULL, NULL, NULL,
411 NULL, NULL, NULL, NULL,
412 NULL, NULL, NULL, NULL,
413 },
bffd67b0 414 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 415 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 416 },
417 [FEAT_7_0_EBX] = {
2d5312da 418 .feat_names = {
fc7dfd20 419 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 420 "hle", "avx2", NULL, "smep",
421 "bmi2", "erms", "invpcid", "rtm",
422 NULL, NULL, "mpx", NULL,
423 "avx512f", "avx512dq", "rdseed", "adx",
424 "smap", "avx512ifma", "pcommit", "clflushopt",
425 "clwb", NULL, "avx512pf", "avx512er",
638cbd45 426 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 427 },
04d104b6
EH		 428 .cpuid_eax = 7,
429 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
430 .cpuid_reg = R_EBX,
37ce3522 431 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 432 },
f74eefe0 433 [FEAT_7_0_ECX] = {
2d5312da
EH		 434 .feat_names = {
435 NULL, "avx512vbmi", "umip", "pku",
436 "ospke", NULL, NULL, NULL,
437 NULL, NULL, NULL, NULL,
f7754377 438 NULL, NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 439 "la57", NULL, NULL, NULL,
2d5312da
EH		 440 NULL, NULL, "rdpid", NULL,
441 NULL, NULL, NULL, NULL,
442 NULL, NULL, NULL, NULL,
443 },
f74eefe0
HH		 444 .cpuid_eax = 7,
445 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
446 .cpuid_reg = R_ECX,
447 .tcg_features = TCG_7_0_ECX_FEATURES,
448 },
95ea69fb
LK		 449 [FEAT_7_0_EDX] = {
450 .feat_names = {
451 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
452 NULL, NULL, NULL, NULL,
453 NULL, NULL, NULL, NULL,
454 NULL, NULL, NULL, NULL,
455 NULL, NULL, NULL, NULL,
456 NULL, NULL, NULL, NULL,
457 NULL, NULL, NULL, NULL,
458 NULL, NULL, NULL, NULL,
459 },
460 .cpuid_eax = 7,
461 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
462 .cpuid_reg = R_EDX,
463 .tcg_features = TCG_7_0_EDX_FEATURES,
464 },
303752a9 465 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 466 .feat_names = {
467 NULL, NULL, NULL, NULL,
468 NULL, NULL, NULL, NULL,
469 "invtsc", NULL, NULL, NULL,
470 NULL, NULL, NULL, NULL,
471 NULL, NULL, NULL, NULL,
472 NULL, NULL, NULL, NULL,
473 NULL, NULL, NULL, NULL,
474 NULL, NULL, NULL, NULL,
475 },
303752a9
MT		 476 .cpuid_eax = 0x80000007,
477 .cpuid_reg = R_EDX,
478 .tcg_features = TCG_APM_FEATURES,
479 .unmigratable_flags = CPUID_APM_INVTSC,
480 },
0bb0b2d2 481 [FEAT_XSAVE] = {
2d5312da
EH		 482 .feat_names = {
483 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
484 NULL, NULL, NULL, NULL,
485 NULL, NULL, NULL, NULL,
486 NULL, NULL, NULL, NULL,
487 NULL, NULL, NULL, NULL,
488 NULL, NULL, NULL, NULL,
489 NULL, NULL, NULL, NULL,
490 NULL, NULL, NULL, NULL,
491 },
0bb0b2d2
PB		 492 .cpuid_eax = 0xd,
493 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
494 .cpuid_reg = R_EAX,
c9cfe8f9 495 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 496 },
28b8e4d0 497 [FEAT_6_EAX] = {
2d5312da
EH		 498 .feat_names = {
499 NULL, NULL, "arat", NULL,
500 NULL, NULL, NULL, NULL,
501 NULL, NULL, NULL, NULL,
502 NULL, NULL, NULL, NULL,
503 NULL, NULL, NULL, NULL,
504 NULL, NULL, NULL, NULL,
505 NULL, NULL, NULL, NULL,
506 NULL, NULL, NULL, NULL,
507 },
28b8e4d0
JK		 508 .cpuid_eax = 6, .cpuid_reg = R_EAX,
509 .tcg_features = TCG_6_EAX_FEATURES,
510 },
96193c22
EH		 511 [FEAT_XSAVE_COMP_LO] = {
512 .cpuid_eax = 0xD,
513 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
514 .cpuid_reg = R_EAX,
515 .tcg_features = ~0U,
6fb2fff7
EH		 516 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
517 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
518 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
519 XSTATE_PKRU_MASK,
96193c22
EH		 520 },
521 [FEAT_XSAVE_COMP_HI] = {
522 .cpuid_eax = 0xD,
523 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
524 .cpuid_reg = R_EDX,
525 .tcg_features = ~0U,
526 },
5ef57876
EH		 527};
528
8e8aba50
EH		 529typedef struct X86RegisterInfo32 {
530 /* Name of register */
531 const char *name;
532 /* QAPI enum value register */
533 X86CPURegister32 qapi_enum;
534} X86RegisterInfo32;
535
536#define REGISTER(reg) \
5d371f41 537 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 538static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 539 REGISTER(EAX),
540 REGISTER(ECX),
541 REGISTER(EDX),
542 REGISTER(EBX),
543 REGISTER(ESP),
544 REGISTER(EBP),
545 REGISTER(ESI),
546 REGISTER(EDI),
547};
548#undef REGISTER
549
3f32bd21
RH		 550typedef struct ExtSaveArea {
551 uint32_t feature, bits;
552 uint32_t offset, size;
553} ExtSaveArea;
554
555static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 556 [XSTATE_FP_BIT] = {
557 /* x87 FP state component is always enabled if XSAVE is supported */
558 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
559 /* x87 state is in the legacy region of the XSAVE area */
560 .offset = 0,
561 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
562 },
563 [XSTATE_SSE_BIT] = {
564 /* SSE state component is always enabled if XSAVE is supported */
565 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
566 /* SSE state is in the legacy region of the XSAVE area */
567 .offset = 0,
568 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
569 },
cfc3b074
PB		 570 [XSTATE_YMM_BIT] =
571 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 572 .offset = offsetof(X86XSaveArea, avx_state),
573 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 574 [XSTATE_BNDREGS_BIT] =
575 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 576 .offset = offsetof(X86XSaveArea, bndreg_state),
577 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 578 [XSTATE_BNDCSR_BIT] =
579 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 580 .offset = offsetof(X86XSaveArea, bndcsr_state),
581 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 582 [XSTATE_OPMASK_BIT] =
583 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 584 .offset = offsetof(X86XSaveArea, opmask_state),
585 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 586 [XSTATE_ZMM_Hi256_BIT] =
587 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 588 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
589 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 590 [XSTATE_Hi16_ZMM_BIT] =
591 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 592 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
593 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 594 [XSTATE_PKRU_BIT] =
595 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 596 .offset = offsetof(X86XSaveArea, pkru_state),
597 .size = sizeof(XSavePKRU) },
2560f19f 598};
8e8aba50 599
1fda6198
EH		 600static uint32_t xsave_area_size(uint64_t mask)
601{
602 int i;
e3c9022b 603 uint64_t ret = 0;
1fda6198 604
e3c9022b 605 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 606 const ExtSaveArea *esa = &x86_ext_save_areas[i];
607 if ((mask >> i) & 1) {
608 ret = MAX(ret, esa->offset + esa->size);
609 }
610 }
611 return ret;
612}
613
96193c22
EH		 614static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
615{
616 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
617 cpu->env.features[FEAT_XSAVE_COMP_LO];
618}
619
8b4beddc
EH		 620const char *get_register_name_32(unsigned int reg)
621{
31ccdde2 622 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 623 return NULL;
624 }
8e8aba50 625 return x86_reg_info_32[reg].name;
8b4beddc
EH		 626}
627
84f1b92f
EH		 628/*
629 * Returns the set of feature flags that are supported and migratable by
630 * QEMU, for a given FeatureWord.
631 */
632static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
633{
634 FeatureWordInfo *wi = &feature_word_info[w];
635 uint32_t r = 0;
636 int i;
637
638 for (i = 0; i < 32; i++) {
639 uint32_t f = 1U << i;
6fb2fff7
EH		 640
641 /* If the feature name is known, it is implicitly considered migratable,
642 * unless it is explicitly set in unmigratable_flags */
643 if ((wi->migratable_flags & f) ||
644 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
645 r |= f;
84f1b92f 646 }
84f1b92f
EH		 647 }
648 return r;
649}
650
bb44e0d1
JK		 651void host_cpuid(uint32_t function, uint32_t count,
652 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 653{
a1fd24af
AL		 654 uint32_t vec[4];
655
656#ifdef __x86_64__
657 asm volatile("cpuid"
658 : "=a"(vec[0]), "=b"(vec[1]),
659 "=c"(vec[2]), "=d"(vec[3])
660 : "0"(function), "c"(count) : "cc");
c1f41226 661#elif defined(__i386__)
a1fd24af
AL		 662 asm volatile("pusha \n\t"
663 "cpuid \n\t"
664 "mov %%eax, 0(%2) \n\t"
665 "mov %%ebx, 4(%2) \n\t"
666 "mov %%ecx, 8(%2) \n\t"
667 "mov %%edx, 12(%2) \n\t"
668 "popa"
669 : : "a"(function), "c"(count), "S"(vec)
670 : "memory", "cc");
c1f41226
EH		 671#else
672 abort();
a1fd24af
AL		 673#endif
674
bdde476a 675 if (eax)
a1fd24af 676 *eax = vec[0];
bdde476a 677 if (ebx)
a1fd24af 678 *ebx = vec[1];
bdde476a 679 if (ecx)
a1fd24af 680 *ecx = vec[2];
bdde476a 681 if (edx)
a1fd24af 682 *edx = vec[3];
bdde476a 683}
c6dc6f63 684
d940ee9b
EH		 685/* CPU class name definitions: */
686
687#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
688#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
689
690/* Return type name for a given CPU model name
691 * Caller is responsible for freeing the returned string.
692 */
693static char *x86_cpu_type_name(const char *model_name)
694{
695 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
696}
697
500050d1
AF		 698static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
699{
d940ee9b
EH		 700 ObjectClass *oc;
701 char *typename;
702
500050d1
AF		 703 if (cpu_model == NULL) {
704 return NULL;
705 }
706
d940ee9b
EH		 707 typename = x86_cpu_type_name(cpu_model);
708 oc = object_class_by_name(typename);
709 g_free(typename);
710 return oc;
500050d1
AF		 711}
712
104494ea
IM		 713static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
714{
715 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
716 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
717 return g_strndup(class_name,
718 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
719}
720
d940ee9b 721struct X86CPUDefinition {
c6dc6f63
AP		 722 const char *name;
723 uint32_t level;
90e4b0c3 724 uint32_t xlevel;
99b88a17
IM		 725 /* vendor is zero-terminated, 12 character ASCII string */
726 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 727 int family;
728 int model;
729 int stepping;
0514ef2f 730 FeatureWordArray features;
c6dc6f63 731 char model_id[48];
d940ee9b 732};
c6dc6f63 733
9576de75 734static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 735 {
736 .name = "qemu64",
3046bb5d 737 .level = 0xd,
99b88a17 738 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 739 .family = 6,
f8e6a11a 740 .model = 6,
c6dc6f63 741 .stepping = 3,
0514ef2f 742 .features[FEAT_1_EDX] =
27861ecc 743 PPRO_FEATURES |
c6dc6f63 744 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 745 CPUID_PSE36,
0514ef2f 746 .features[FEAT_1_ECX] =
6aa91e4a 747 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 748 .features[FEAT_8000_0001_EDX] =
c6dc6f63 749 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 750 .features[FEAT_8000_0001_ECX] =
71195672 751 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 752 .xlevel = 0x8000000A,
9cf2cc3d 753 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 754 },
755 {
756 .name = "phenom",
757 .level = 5,
99b88a17 758 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 759 .family = 16,
760 .model = 2,
761 .stepping = 3,
b9fc20bc 762 /* Missing: CPUID_HT */
0514ef2f 763 .features[FEAT_1_EDX] =
27861ecc 764 PPRO_FEATURES |
c6dc6f63 765 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 766 CPUID_PSE36 | CPUID_VME,
0514ef2f 767 .features[FEAT_1_ECX] =
27861ecc 768 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 769 CPUID_EXT_POPCNT,
0514ef2f 770 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 771 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
772 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 773 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 774 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
775 CPUID_EXT3_CR8LEG,
776 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
777 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 778 .features[FEAT_8000_0001_ECX] =
27861ecc 779 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 780 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 781 /* Missing: CPUID_SVM_LBRV */
0514ef2f 782 .features[FEAT_SVM] =
b9fc20bc 783 CPUID_SVM_NPT,
c6dc6f63
AP		 784 .xlevel = 0x8000001A,
785 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
786 },
787 {
788 .name = "core2duo",
789 .level = 10,
99b88a17 790 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 791 .family = 6,
792 .model = 15,
793 .stepping = 11,
b9fc20bc 794 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 795 .features[FEAT_1_EDX] =
27861ecc 796 PPRO_FEATURES |
c6dc6f63 797 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 798 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
799 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 800 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 801 .features[FEAT_1_ECX] =
27861ecc 802 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 803 CPUID_EXT_CX16,
0514ef2f 804 .features[FEAT_8000_0001_EDX] =
27861ecc 805 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 806 .features[FEAT_8000_0001_ECX] =
27861ecc 807 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 808 .xlevel = 0x80000008,
809 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
810 },
811 {
812 .name = "kvm64",
3046bb5d 813 .level = 0xd,
99b88a17 814 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 815 .family = 15,
816 .model = 6,
817 .stepping = 1,
b3a4f0b1 818 /* Missing: CPUID_HT */
0514ef2f 819 .features[FEAT_1_EDX] =
b3a4f0b1 820 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 821 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
822 CPUID_PSE36,
823 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 824 .features[FEAT_1_ECX] =
27861ecc 825 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 826 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 827 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 828 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
829 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
830 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
831 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
832 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 833 .features[FEAT_8000_0001_ECX] =
27861ecc 834 0,
c6dc6f63
AP		 835 .xlevel = 0x80000008,
836 .model_id = "Common KVM processor"
837 },
c6dc6f63
AP		 838 {
839 .name = "qemu32",
840 .level = 4,
99b88a17 841 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 842 .family = 6,
f8e6a11a 843 .model = 6,
c6dc6f63 844 .stepping = 3,
0514ef2f 845 .features[FEAT_1_EDX] =
27861ecc 846 PPRO_FEATURES,
0514ef2f 847 .features[FEAT_1_ECX] =
6aa91e4a 848 CPUID_EXT_SSE3,
58012d66 849 .xlevel = 0x80000004,
9cf2cc3d 850 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 851 },
eafaf1e5
AP		 852 {
853 .name = "kvm32",
854 .level = 5,
99b88a17 855 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 856 .family = 15,
857 .model = 6,
858 .stepping = 1,
0514ef2f 859 .features[FEAT_1_EDX] =
b3a4f0b1 860 PPRO_FEATURES | CPUID_VME |
eafaf1e5 861 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 862 .features[FEAT_1_ECX] =
27861ecc 863 CPUID_EXT_SSE3,
0514ef2f 864 .features[FEAT_8000_0001_ECX] =
27861ecc 865 0,
eafaf1e5
AP		 866 .xlevel = 0x80000008,
867 .model_id = "Common 32-bit KVM processor"
868 },
c6dc6f63
AP		 869 {
870 .name = "coreduo",
871 .level = 10,
99b88a17 872 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 873 .family = 6,
874 .model = 14,
875 .stepping = 8,
b9fc20bc 876 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 877 .features[FEAT_1_EDX] =
27861ecc 878 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 879 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
880 CPUID_SS,
881 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 882 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 883 .features[FEAT_1_ECX] =
e93abc14 884 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 885 .features[FEAT_8000_0001_EDX] =
27861ecc 886 CPUID_EXT2_NX,
c6dc6f63
AP		 887 .xlevel = 0x80000008,
888 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
889 },
890 {
891 .name = "486",
58012d66 892 .level = 1,
99b88a17 893 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 894 .family = 4,
b2a856d9 895 .model = 8,
c6dc6f63 896 .stepping = 0,
0514ef2f 897 .features[FEAT_1_EDX] =
27861ecc 898 I486_FEATURES,
c6dc6f63
AP		 899 .xlevel = 0,
900 },
901 {
902 .name = "pentium",
903 .level = 1,
99b88a17 904 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 905 .family = 5,
906 .model = 4,
907 .stepping = 3,
0514ef2f 908 .features[FEAT_1_EDX] =
27861ecc 909 PENTIUM_FEATURES,
c6dc6f63
AP		 910 .xlevel = 0,
911 },
912 {
913 .name = "pentium2",
914 .level = 2,
99b88a17 915 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 916 .family = 6,
917 .model = 5,
918 .stepping = 2,
0514ef2f 919 .features[FEAT_1_EDX] =
27861ecc 920 PENTIUM2_FEATURES,
c6dc6f63
AP		 921 .xlevel = 0,
922 },
923 {
924 .name = "pentium3",
3046bb5d 925 .level = 3,
99b88a17 926 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 927 .family = 6,
928 .model = 7,
929 .stepping = 3,
0514ef2f 930 .features[FEAT_1_EDX] =
27861ecc 931 PENTIUM3_FEATURES,
c6dc6f63
AP		 932 .xlevel = 0,
933 },
934 {
935 .name = "athlon",
936 .level = 2,
99b88a17 937 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 938 .family = 6,
939 .model = 2,
940 .stepping = 3,
0514ef2f 941 .features[FEAT_1_EDX] =
27861ecc 942 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 943 CPUID_MCA,
0514ef2f 944 .features[FEAT_8000_0001_EDX] =
60032ac0 945 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 946 .xlevel = 0x80000008,
9cf2cc3d 947 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 948 },
949 {
950 .name = "n270",
3046bb5d 951 .level = 10,
99b88a17 952 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 953 .family = 6,
954 .model = 28,
955 .stepping = 2,
b9fc20bc 956 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 957 .features[FEAT_1_EDX] =
27861ecc 958 PPRO_FEATURES |
b9fc20bc
EH		 959 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
960 CPUID_ACPI | CPUID_SS,
c6dc6f63 961 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 962 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
963 * CPUID_EXT_XTPR */
0514ef2f 964 .features[FEAT_1_ECX] =
27861ecc 965 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 966 CPUID_EXT_MOVBE,
0514ef2f 967 .features[FEAT_8000_0001_EDX] =
60032ac0 968 CPUID_EXT2_NX,
0514ef2f 969 .features[FEAT_8000_0001_ECX] =
27861ecc 970 CPUID_EXT3_LAHF_LM,
3046bb5d 971 .xlevel = 0x80000008,
c6dc6f63
AP		 972 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
973 },
3eca4642
EH		 974 {
975 .name = "Conroe",
3046bb5d 976 .level = 10,
99b88a17 977 .vendor = CPUID_VENDOR_INTEL,
3eca4642 978 .family = 6,
ffce9ebb 979 .model = 15,
3eca4642 980 .stepping = 3,
0514ef2f 981 .features[FEAT_1_EDX] =
b3a4f0b1 982 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 983 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
984 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
985 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
986 CPUID_DE | CPUID_FP87,
0514ef2f 987 .features[FEAT_1_ECX] =
27861ecc 988 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 989 .features[FEAT_8000_0001_EDX] =
27861ecc 990 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 991 .features[FEAT_8000_0001_ECX] =
27861ecc 992 CPUID_EXT3_LAHF_LM,
3046bb5d 993 .xlevel = 0x80000008,
3eca4642
EH		 994 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
995 },
996 {
997 .name = "Penryn",
3046bb5d 998 .level = 10,
99b88a17 999 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1000 .family = 6,
ffce9ebb 1001 .model = 23,
3eca4642 1002 .stepping = 3,
0514ef2f 1003 .features[FEAT_1_EDX] =
b3a4f0b1 1004 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1005 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1006 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1007 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1008 CPUID_DE | CPUID_FP87,
0514ef2f 1009 .features[FEAT_1_ECX] =
27861ecc 1010 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1011 CPUID_EXT_SSE3,
0514ef2f 1012 .features[FEAT_8000_0001_EDX] =
27861ecc 1013 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1014 .features[FEAT_8000_0001_ECX] =
27861ecc 1015 CPUID_EXT3_LAHF_LM,
3046bb5d 1016 .xlevel = 0x80000008,
3eca4642
EH		 1017 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1018 },
1019 {
1020 .name = "Nehalem",
3046bb5d 1021 .level = 11,
99b88a17 1022 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1023 .family = 6,
ffce9ebb 1024 .model = 26,
3eca4642 1025 .stepping = 3,
0514ef2f 1026 .features[FEAT_1_EDX] =
b3a4f0b1 1027 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1028 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1029 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1030 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1031 CPUID_DE | CPUID_FP87,
0514ef2f 1032 .features[FEAT_1_ECX] =
27861ecc 1033 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1034 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1035 .features[FEAT_8000_0001_EDX] =
27861ecc 1036 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1037 .features[FEAT_8000_0001_ECX] =
27861ecc 1038 CPUID_EXT3_LAHF_LM,
3046bb5d 1039 .xlevel = 0x80000008,
3eca4642
EH		 1040 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1041 },
1042 {
1043 .name = "Westmere",
1044 .level = 11,
99b88a17 1045 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1046 .family = 6,
1047 .model = 44,
1048 .stepping = 1,
0514ef2f 1049 .features[FEAT_1_EDX] =
b3a4f0b1 1050 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1051 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1052 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1053 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1054 CPUID_DE | CPUID_FP87,
0514ef2f 1055 .features[FEAT_1_ECX] =
27861ecc 1056 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1057 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1058 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1059 .features[FEAT_8000_0001_EDX] =
27861ecc 1060 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1061 .features[FEAT_8000_0001_ECX] =
27861ecc 1062 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1063 .features[FEAT_6_EAX] =
1064 CPUID_6_EAX_ARAT,
3046bb5d 1065 .xlevel = 0x80000008,
3eca4642
EH		 1066 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1067 },
1068 {
1069 .name = "SandyBridge",
1070 .level = 0xd,
99b88a17 1071 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1072 .family = 6,
1073 .model = 42,
1074 .stepping = 1,
0514ef2f 1075 .features[FEAT_1_EDX] =
b3a4f0b1 1076 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1077 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1078 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1079 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1080 CPUID_DE | CPUID_FP87,
0514ef2f 1081 .features[FEAT_1_ECX] =
27861ecc 1082 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1083 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1084 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1085 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1086 CPUID_EXT_SSE3,
0514ef2f 1087 .features[FEAT_8000_0001_EDX] =
27861ecc 1088 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1089 CPUID_EXT2_SYSCALL,
0514ef2f 1090 .features[FEAT_8000_0001_ECX] =
27861ecc 1091 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1092 .features[FEAT_XSAVE] =
1093 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1094 .features[FEAT_6_EAX] =
1095 CPUID_6_EAX_ARAT,
3046bb5d 1096 .xlevel = 0x80000008,
3eca4642
EH		 1097 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1098 },
2f9ac42a
PB		 1099 {
1100 .name = "IvyBridge",
1101 .level = 0xd,
1102 .vendor = CPUID_VENDOR_INTEL,
1103 .family = 6,
1104 .model = 58,
1105 .stepping = 9,
1106 .features[FEAT_1_EDX] =
1107 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1108 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1109 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1110 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1111 CPUID_DE | CPUID_FP87,
1112 .features[FEAT_1_ECX] =
1113 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1114 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1115 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1116 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1117 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1118 .features[FEAT_7_0_EBX] =
1119 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1120 CPUID_7_0_EBX_ERMS,
1121 .features[FEAT_8000_0001_EDX] =
1122 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1123 CPUID_EXT2_SYSCALL,
1124 .features[FEAT_8000_0001_ECX] =
1125 CPUID_EXT3_LAHF_LM,
1126 .features[FEAT_XSAVE] =
1127 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1128 .features[FEAT_6_EAX] =
1129 CPUID_6_EAX_ARAT,
3046bb5d 1130 .xlevel = 0x80000008,
2f9ac42a
PB		 1131 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1132 },
37507094 1133 {
a356850b
EH		 1134 .name = "Haswell-noTSX",
1135 .level = 0xd,
1136 .vendor = CPUID_VENDOR_INTEL,
1137 .family = 6,
1138 .model = 60,
1139 .stepping = 1,
1140 .features[FEAT_1_EDX] =
1141 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1142 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1143 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1144 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1145 CPUID_DE | CPUID_FP87,
1146 .features[FEAT_1_ECX] =
1147 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1148 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1149 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1150 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1151 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1152 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1153 .features[FEAT_8000_0001_EDX] =
1154 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1155 CPUID_EXT2_SYSCALL,
1156 .features[FEAT_8000_0001_ECX] =
becb6667 1157 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1158 .features[FEAT_7_0_EBX] =
1159 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1160 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1161 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1162 .features[FEAT_XSAVE] =
1163 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1164 .features[FEAT_6_EAX] =
1165 CPUID_6_EAX_ARAT,
3046bb5d 1166 .xlevel = 0x80000008,
a356850b
EH		 1167 .model_id = "Intel Core Processor (Haswell, no TSX)",
1168 }, {
37507094
EH		 1169 .name = "Haswell",
1170 .level = 0xd,
99b88a17 1171 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1172 .family = 6,
1173 .model = 60,
1174 .stepping = 1,
0514ef2f 1175 .features[FEAT_1_EDX] =
b3a4f0b1 1176 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1177 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1178 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1179 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1180 CPUID_DE | CPUID_FP87,
0514ef2f 1181 .features[FEAT_1_ECX] =
27861ecc 1182 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1183 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1184 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1185 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1186 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1187 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1188 .features[FEAT_8000_0001_EDX] =
27861ecc 1189 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1190 CPUID_EXT2_SYSCALL,
0514ef2f 1191 .features[FEAT_8000_0001_ECX] =
becb6667 1192 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1193 .features[FEAT_7_0_EBX] =
27861ecc 1194 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1195 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1196 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1197 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1198 .features[FEAT_XSAVE] =
1199 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1200 .features[FEAT_6_EAX] =
1201 CPUID_6_EAX_ARAT,
3046bb5d 1202 .xlevel = 0x80000008,
37507094
EH		 1203 .model_id = "Intel Core Processor (Haswell)",
1204 },
a356850b
EH		 1205 {
1206 .name = "Broadwell-noTSX",
1207 .level = 0xd,
1208 .vendor = CPUID_VENDOR_INTEL,
1209 .family = 6,
1210 .model = 61,
1211 .stepping = 2,
1212 .features[FEAT_1_EDX] =
1213 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1214 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1215 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1216 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1217 CPUID_DE | CPUID_FP87,
1218 .features[FEAT_1_ECX] =
1219 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1220 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1221 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1222 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1223 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1224 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1225 .features[FEAT_8000_0001_EDX] =
1226 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1227 CPUID_EXT2_SYSCALL,
1228 .features[FEAT_8000_0001_ECX] =
becb6667 1229 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1230 .features[FEAT_7_0_EBX] =
1231 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1232 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1233 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1234 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1235 CPUID_7_0_EBX_SMAP,
1236 .features[FEAT_XSAVE] =
1237 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1238 .features[FEAT_6_EAX] =
1239 CPUID_6_EAX_ARAT,
3046bb5d 1240 .xlevel = 0x80000008,
a356850b
EH		 1241 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1242 },
ece01354
EH		 1243 {
1244 .name = "Broadwell",
1245 .level = 0xd,
1246 .vendor = CPUID_VENDOR_INTEL,
1247 .family = 6,
1248 .model = 61,
1249 .stepping = 2,
1250 .features[FEAT_1_EDX] =
b3a4f0b1 1251 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1252 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1253 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1254 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1255 CPUID_DE | CPUID_FP87,
1256 .features[FEAT_1_ECX] =
1257 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1258 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1259 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1260 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1261 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1262 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1263 .features[FEAT_8000_0001_EDX] =
1264 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1265 CPUID_EXT2_SYSCALL,
1266 .features[FEAT_8000_0001_ECX] =
becb6667 1267 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1268 .features[FEAT_7_0_EBX] =
1269 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1270 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1271 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1272 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1273 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1274 .features[FEAT_XSAVE] =
1275 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1276 .features[FEAT_6_EAX] =
1277 CPUID_6_EAX_ARAT,
3046bb5d 1278 .xlevel = 0x80000008,
ece01354
EH		 1279 .model_id = "Intel Core Processor (Broadwell)",
1280 },
f6f949e9
EH		 1281 {
1282 .name = "Skylake-Client",
1283 .level = 0xd,
1284 .vendor = CPUID_VENDOR_INTEL,
1285 .family = 6,
1286 .model = 94,
1287 .stepping = 3,
1288 .features[FEAT_1_EDX] =
1289 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1290 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1291 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1292 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1293 CPUID_DE | CPUID_FP87,
1294 .features[FEAT_1_ECX] =
1295 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1296 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1297 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1298 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1299 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1300 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1301 .features[FEAT_8000_0001_EDX] =
1302 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1303 CPUID_EXT2_SYSCALL,
1304 .features[FEAT_8000_0001_ECX] =
1305 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1306 .features[FEAT_7_0_EBX] =
1307 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1308 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1309 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1310 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1311 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1312 /* Missing: XSAVES (not supported by some Linux versions,
1313 * including v4.1 to v4.6).
1314 * KVM doesn't yet expose any XSAVES state save component,
1315 * and the only one defined in Skylake (processor tracing)
1316 * probably will block migration anyway.
1317 */
1318 .features[FEAT_XSAVE] =
1319 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1320 CPUID_XSAVE_XGETBV1,
1321 .features[FEAT_6_EAX] =
1322 CPUID_6_EAX_ARAT,
1323 .xlevel = 0x80000008,
1324 .model_id = "Intel Core Processor (Skylake)",
1325 },
3eca4642
EH		 1326 {
1327 .name = "Opteron_G1",
1328 .level = 5,
99b88a17 1329 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1330 .family = 15,
1331 .model = 6,
1332 .stepping = 1,
0514ef2f 1333 .features[FEAT_1_EDX] =
b3a4f0b1 1334 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1335 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1336 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1337 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1338 CPUID_DE | CPUID_FP87,
0514ef2f 1339 .features[FEAT_1_ECX] =
27861ecc 1340 CPUID_EXT_SSE3,
0514ef2f 1341 .features[FEAT_8000_0001_EDX] =
2a923a29 1342 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 1343 .xlevel = 0x80000008,
1344 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1345 },
1346 {
1347 .name = "Opteron_G2",
1348 .level = 5,
99b88a17 1349 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1350 .family = 15,
1351 .model = 6,
1352 .stepping = 1,
0514ef2f 1353 .features[FEAT_1_EDX] =
b3a4f0b1 1354 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1355 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1356 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1357 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1358 CPUID_DE | CPUID_FP87,
0514ef2f 1359 .features[FEAT_1_ECX] =
27861ecc 1360 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1361 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1362 .features[FEAT_8000_0001_EDX] =
2a923a29 1363 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1364 .features[FEAT_8000_0001_ECX] =
27861ecc 1365 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1366 .xlevel = 0x80000008,
1367 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1368 },
1369 {
1370 .name = "Opteron_G3",
1371 .level = 5,
99b88a17 1372 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 1373 .family = 16,
1374 .model = 2,
1375 .stepping = 3,
0514ef2f 1376 .features[FEAT_1_EDX] =
b3a4f0b1 1377 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1378 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1379 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1380 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1381 CPUID_DE | CPUID_FP87,
0514ef2f 1382 .features[FEAT_1_ECX] =
27861ecc 1383 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1384 CPUID_EXT_SSE3,
33b5e8c0 1385 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1386 .features[FEAT_8000_0001_EDX] =
2a923a29 1387 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1388 .features[FEAT_8000_0001_ECX] =
27861ecc 1389 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1390 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1391 .xlevel = 0x80000008,
1392 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1393 },
1394 {
1395 .name = "Opteron_G4",
1396 .level = 0xd,
99b88a17 1397 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1398 .family = 21,
1399 .model = 1,
1400 .stepping = 2,
0514ef2f 1401 .features[FEAT_1_EDX] =
b3a4f0b1 1402 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1403 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1404 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1405 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1406 CPUID_DE | CPUID_FP87,
0514ef2f 1407 .features[FEAT_1_ECX] =
27861ecc 1408 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1409 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1410 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1411 CPUID_EXT_SSE3,
33b5e8c0 1412 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1413 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1414 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1415 CPUID_EXT2_SYSCALL,
0514ef2f 1416 .features[FEAT_8000_0001_ECX] =
27861ecc 1417 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1418 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1419 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1420 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1421 /* no xsaveopt! */
3eca4642
EH		 1422 .xlevel = 0x8000001A,
1423 .model_id = "AMD Opteron 62xx class CPU",
1424 },
021941b9
AP		 1425 {
1426 .name = "Opteron_G5",
1427 .level = 0xd,
99b88a17 1428 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1429 .family = 21,
1430 .model = 2,
1431 .stepping = 0,
0514ef2f 1432 .features[FEAT_1_EDX] =
b3a4f0b1 1433 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1434 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1435 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1436 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1437 CPUID_DE | CPUID_FP87,
0514ef2f 1438 .features[FEAT_1_ECX] =
27861ecc 1439 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1440 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1441 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1442 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1443 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1444 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1445 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1446 CPUID_EXT2_SYSCALL,
0514ef2f 1447 .features[FEAT_8000_0001_ECX] =
27861ecc 1448 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1449 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1450 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1451 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1452 /* no xsaveopt! */
021941b9
AP		 1453 .xlevel = 0x8000001A,
1454 .model_id = "AMD Opteron 63xx class CPU",
1455 },
c6dc6f63
AP		 1456};
1457
5114e842
EH		 1458typedef struct PropValue {
1459 const char *prop, *value;
1460} PropValue;
1461
1462/* KVM-specific features that are automatically added/removed
1463 * from all CPU models when KVM is enabled.
1464 */
1465static PropValue kvm_default_props[] = {
1466 { "kvmclock", "on" },
1467 { "kvm-nopiodelay", "on" },
1468 { "kvm-asyncpf", "on" },
1469 { "kvm-steal-time", "on" },
1470 { "kvm-pv-eoi", "on" },
1471 { "kvmclock-stable-bit", "on" },
1472 { "x2apic", "on" },
1473 { "acpi", "off" },
1474 { "monitor", "off" },
1475 { "svm", "off" },
1476 { NULL, NULL },
1477};
1478
04d99c3c
EH		 1479/* TCG-specific defaults that override all CPU models when using TCG
1480 */
1481static PropValue tcg_default_props[] = {
1482 { "vme", "off" },
1483 { NULL, NULL },
1484};
1485
1486
5114e842
EH		 1487void x86_cpu_change_kvm_default(const char *prop, const char *value)
1488{
1489 PropValue *pv;
1490 for (pv = kvm_default_props; pv->prop; pv++) {
1491 if (!strcmp(pv->prop, prop)) {
1492 pv->value = value;
1493 break;
1494 }
1495 }
1496
1497 /* It is valid to call this function only for properties that
1498 * are already present in the kvm_default_props table.
1499 */
1500 assert(pv->prop);
1501}
1502
4d1b279b
EH		 1503static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1504 bool migratable_only);
1505
40bfe48f
HZ		 1506static bool lmce_supported(void)
1507{
c62f2630 1508 uint64_t mce_cap = 0;
40bfe48f 1509
c62f2630 1510#ifdef CONFIG_KVM
40bfe48f
HZ		 1511 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1512 return false;
1513 }
c62f2630 1514#endif
40bfe48f
HZ		 1515
1516 return !!(mce_cap & MCG_LMCE_P);
1517}
1518
c6dc6f63
AP		 1519static int cpu_x86_fill_model_id(char *str)
1520{
1521 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1522 int i;
1523
1524 for (i = 0; i < 3; i++) {
1525 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1526 memcpy(str + i * 16 + 0, &eax, 4);
1527 memcpy(str + i * 16 + 4, &ebx, 4);
1528 memcpy(str + i * 16 + 8, &ecx, 4);
1529 memcpy(str + i * 16 + 12, &edx, 4);
1530 }
1531 return 0;
1532}
1533
c62f2630 1534static Property max_x86_cpu_properties[] = {
120eee7d 1535 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1536 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1537 DEFINE_PROP_END_OF_LIST()
1538};
1539
c62f2630 1540static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1541{
84f1b92f 1542 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1543 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 1544
f48c8837 1545 xcc->ordering = 9;
6e746f30 1546
ee465a3e 1547 xcc->model_description =
c62f2630 1548 "Enables all features supported by the accelerator in the current host";
d940ee9b 1549
c62f2630 1550 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 1551}
1552
0bacd8b3
EH		 1553static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
1554
c62f2630 1555static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 1556{
1557 X86CPU *cpu = X86_CPU(obj);
1558 CPUX86State *env = &cpu->env;
1559 KVMState *s = kvm_state;
d940ee9b 1560
4d1b279b
EH		 1561 /* We can't fill the features array here because we don't know yet if
1562 * "migratable" is true or false.
1563 */
44bd8e53 1564 cpu->max_features = true;
4d1b279b 1565
e4356010 1566 if (kvm_enabled()) {
0bacd8b3
EH		 1567 X86CPUDefinition host_cpudef = { };
1568 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1569
1570 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1571 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1572
1573 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1574 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1575 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1576 host_cpudef.stepping = eax & 0x0F;
1577
1578 cpu_x86_fill_model_id(host_cpudef.model_id);
1579
1580 x86_cpu_load_def(cpu, &host_cpudef, &error_abort);
1581
c39c0edf
EH		 1582 env->cpuid_min_level =
1583 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1584 env->cpuid_min_xlevel =
1585 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1586 env->cpuid_min_xlevel2 =
1587 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
40bfe48f
HZ		 1588
1589 if (lmce_supported()) {
1590 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1591 }
6900d1cc
EH		 1592 } else {
1593 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
1594 "vendor", &error_abort);
1595 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
1596 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
1597 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
1598 object_property_set_str(OBJECT(cpu),
1599 "QEMU TCG CPU version " QEMU_HW_VERSION,
1600 "model-id", &error_abort);
e4356010 1601 }
2a573259 1602
d940ee9b 1603 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1604}
1605
c62f2630
EH		 1606static const TypeInfo max_x86_cpu_type_info = {
1607 .name = X86_CPU_TYPE_NAME("max"),
1608 .parent = TYPE_X86_CPU,
1609 .instance_init = max_x86_cpu_initfn,
1610 .class_init = max_x86_cpu_class_init,
1611};
1612
1613#ifdef CONFIG_KVM
1614
1615static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1616{
1617 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1618
1619 xcc->kvm_required = true;
1620 xcc->ordering = 8;
1621
1622 xcc->model_description =
1623 "KVM processor with all supported host features "
1624 "(only available in KVM mode)";
1625}
1626
d940ee9b
EH		 1627static const TypeInfo host_x86_cpu_type_info = {
1628 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 1629 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 1630 .class_init = host_x86_cpu_class_init,
1631};
1632
1633#endif
1634
8459e396 1635static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1636{
8459e396 1637 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1638 int i;
1639
857aee33 1640 for (i = 0; i < 32; ++i) {
72370dc1 1641 if ((1UL << i) & mask) {
bffd67b0 1642 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1643 assert(reg);
fefb41bf 1644 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1645 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1646 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1647 f->cpuid_eax, reg,
1648 f->feat_names[i] ? "." : "",
1649 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1650 }
857aee33 1651 }
c6dc6f63
AP		 1652}
1653
d7bce999
EB		 1654static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1655 const char *name, void *opaque,
1656 Error **errp)
95b8519d
AF		 1657{
1658 X86CPU *cpu = X86_CPU(obj);
1659 CPUX86State *env = &cpu->env;
1660 int64_t value;
1661
1662 value = (env->cpuid_version >> 8) & 0xf;
1663 if (value == 0xf) {
1664 value += (env->cpuid_version >> 20) & 0xff;
1665 }
51e72bc1 1666 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1667}
1668
d7bce999
EB		 1669static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1670 const char *name, void *opaque,
1671 Error **errp)
ed5e1ec3 1672{
71ad61d3
AF		 1673 X86CPU *cpu = X86_CPU(obj);
1674 CPUX86State *env = &cpu->env;
1675 const int64_t min = 0;
1676 const int64_t max = 0xff + 0xf;
65cd9064 1677 Error *local_err = NULL;
71ad61d3
AF		 1678 int64_t value;
1679
51e72bc1 1680 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1681 if (local_err) {
1682 error_propagate(errp, local_err);
71ad61d3
AF		 1683 return;
1684 }
1685 if (value < min || value > max) {
c6bd8c70
MA		 1686 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1687 name ? name : "null", value, min, max);
71ad61d3
AF		 1688 return;
1689 }
1690
ed5e1ec3 1691 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1692 if (value > 0x0f) {
1693 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1694 } else {
71ad61d3 1695 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1696 }
1697}
1698
d7bce999
EB		 1699static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1700 const char *name, void *opaque,
1701 Error **errp)
67e30c83
AF		 1702{
1703 X86CPU *cpu = X86_CPU(obj);
1704 CPUX86State *env = &cpu->env;
1705 int64_t value;
1706
1707 value = (env->cpuid_version >> 4) & 0xf;
1708 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1709 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1710}
1711
d7bce999
EB		 1712static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1713 const char *name, void *opaque,
1714 Error **errp)
b0704cbd 1715{
c5291a4f
AF		 1716 X86CPU *cpu = X86_CPU(obj);
1717 CPUX86State *env = &cpu->env;
1718 const int64_t min = 0;
1719 const int64_t max = 0xff;
65cd9064 1720 Error *local_err = NULL;
c5291a4f
AF		 1721 int64_t value;
1722
51e72bc1 1723 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1724 if (local_err) {
1725 error_propagate(errp, local_err);
c5291a4f
AF		 1726 return;
1727 }
1728 if (value < min || value > max) {
c6bd8c70
MA		 1729 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1730 name ? name : "null", value, min, max);
c5291a4f
AF		 1731 return;
1732 }
1733
b0704cbd 1734 env->cpuid_version &= ~0xf00f0;
c5291a4f 1735 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1736}
1737
35112e41 1738static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1739 const char *name, void *opaque,
35112e41
AF		 1740 Error **errp)
1741{
1742 X86CPU *cpu = X86_CPU(obj);
1743 CPUX86State *env = &cpu->env;
1744 int64_t value;
1745
1746 value = env->cpuid_version & 0xf;
51e72bc1 1747 visit_type_int(v, name, &value, errp);
35112e41
AF		 1748}
1749
036e2222 1750static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1751 const char *name, void *opaque,
036e2222 1752 Error **errp)
38c3dc46 1753{
036e2222
AF		 1754 X86CPU *cpu = X86_CPU(obj);
1755 CPUX86State *env = &cpu->env;
1756 const int64_t min = 0;
1757 const int64_t max = 0xf;
65cd9064 1758 Error *local_err = NULL;
036e2222
AF		 1759 int64_t value;
1760
51e72bc1 1761 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1762 if (local_err) {
1763 error_propagate(errp, local_err);
036e2222
AF		 1764 return;
1765 }
1766 if (value < min || value > max) {
c6bd8c70
MA		 1767 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1768 name ? name : "null", value, min, max);
036e2222
AF		 1769 return;
1770 }
1771
38c3dc46 1772 env->cpuid_version &= ~0xf;
036e2222 1773 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1774}
1775
d480e1af
AF		 1776static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1777{
1778 X86CPU *cpu = X86_CPU(obj);
1779 CPUX86State *env = &cpu->env;
1780 char *value;
d480e1af 1781
e42a92ae 1782 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1783 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1784 env->cpuid_vendor3);
d480e1af
AF		 1785 return value;
1786}
1787
1788static void x86_cpuid_set_vendor(Object *obj, const char *value,
1789 Error **errp)
1790{
1791 X86CPU *cpu = X86_CPU(obj);
1792 CPUX86State *env = &cpu->env;
1793 int i;
1794
9df694ee 1795 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1796 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1797 return;
1798 }
1799
1800 env->cpuid_vendor1 = 0;
1801 env->cpuid_vendor2 = 0;
1802 env->cpuid_vendor3 = 0;
1803 for (i = 0; i < 4; i++) {
1804 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1805 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1806 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1807 }
d480e1af
AF		 1808}
1809
63e886eb
AF		 1810static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1811{
1812 X86CPU *cpu = X86_CPU(obj);
1813 CPUX86State *env = &cpu->env;
1814 char *value;
1815 int i;
1816
1817 value = g_malloc(48 + 1);
1818 for (i = 0; i < 48; i++) {
1819 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1820 }
1821 value[48] = '\0';
1822 return value;
1823}
1824
938d4c25
AF		 1825static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1826 Error **errp)
dcce6675 1827{
938d4c25
AF		 1828 X86CPU *cpu = X86_CPU(obj);
1829 CPUX86State *env = &cpu->env;
dcce6675
AF		 1830 int c, len, i;
1831
1832 if (model_id == NULL) {
1833 model_id = "";
1834 }
1835 len = strlen(model_id);
d0a6acf4 1836 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1837 for (i = 0; i < 48; i++) {
1838 if (i >= len) {
1839 c = '\0';
1840 } else {
1841 c = (uint8_t)model_id[i];
1842 }
1843 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1844 }
1845}
1846
d7bce999
EB		 1847static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1848 void *opaque, Error **errp)
89e48965
AF		 1849{
1850 X86CPU *cpu = X86_CPU(obj);
1851 int64_t value;
1852
1853 value = cpu->env.tsc_khz * 1000;
51e72bc1 1854 visit_type_int(v, name, &value, errp);
89e48965
AF		 1855}
1856
d7bce999
EB		 1857static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1858 void *opaque, Error **errp)
89e48965
AF		 1859{
1860 X86CPU *cpu = X86_CPU(obj);
1861 const int64_t min = 0;
2e84849a 1862 const int64_t max = INT64_MAX;
65cd9064 1863 Error *local_err = NULL;
89e48965
AF		 1864 int64_t value;
1865
51e72bc1 1866 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1867 if (local_err) {
1868 error_propagate(errp, local_err);
89e48965
AF		 1869 return;
1870 }
1871 if (value < min || value > max) {
c6bd8c70
MA		 1872 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1873 name ? name : "null", value, min, max);
89e48965
AF		 1874 return;
1875 }
1876
36f96c4b 1877 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1878}
1879
7e5292b5 1880/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1881static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1882 const char *name, void *opaque,
1883 Error **errp)
8e8aba50 1884{
7e5292b5 1885 uint32_t *array = (uint32_t *)opaque;
8e8aba50 1886 FeatureWord w;
8e8aba50
EH		 1887 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1888 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1889 X86CPUFeatureWordInfoList *list = NULL;
1890
1891 for (w = 0; w < FEATURE_WORDS; w++) {
1892 FeatureWordInfo *wi = &feature_word_info[w];
1893 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1894 qwi->cpuid_input_eax = wi->cpuid_eax;
1895 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1896 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1897 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1898 qwi->features = array[w];
8e8aba50
EH		 1899
1900 /* List will be in reverse order, but order shouldn't matter */
1901 list_entries[w].next = list;
1902 list_entries[w].value = &word_infos[w];
1903 list = &list_entries[w];
1904 }
1905
6b62d961 1906 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 1907}
1908
d7bce999
EB		 1909static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1910 void *opaque, Error **errp)
c8f0f88e
IM		 1911{
1912 X86CPU *cpu = X86_CPU(obj);
1913 int64_t value = cpu->hyperv_spinlock_attempts;
1914
51e72bc1 1915 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1916}
1917
d7bce999
EB		 1918static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1919 void *opaque, Error **errp)
c8f0f88e
IM		 1920{
1921 const int64_t min = 0xFFF;
1922 const int64_t max = UINT_MAX;
1923 X86CPU *cpu = X86_CPU(obj);
1924 Error *err = NULL;
1925 int64_t value;
1926
51e72bc1 1927 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1928 if (err) {
1929 error_propagate(errp, err);
1930 return;
1931 }
1932
1933 if (value < min || value > max) {
1934 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1935 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1936 object_get_typename(obj), name ? name : "null",
1937 value, min, max);
c8f0f88e
IM		 1938 return;
1939 }
1940 cpu->hyperv_spinlock_attempts = value;
1941}
1942
1943static PropertyInfo qdev_prop_spinlocks = {
1944 .name = "int",
1945 .get = x86_get_hv_spinlocks,
1946 .set = x86_set_hv_spinlocks,
1947};
1948
72ac2e87
IM		 1949/* Convert all '_' in a feature string option name to '-', to make feature
1950 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1951 */
1952static inline void feat2prop(char *s)
1953{
1954 while ((s = strchr(s, '_'))) {
1955 *s = '-';
1956 }
1957}
1958
b54c9377
EH		 1959/* Return the feature property name for a feature flag bit */
1960static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
1961{
1962 /* XSAVE components are automatically enabled by other features,
1963 * so return the original feature name instead
1964 */
1965 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
1966 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
1967
1968 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
1969 x86_ext_save_areas[comp].bits) {
1970 w = x86_ext_save_areas[comp].feature;
1971 bitnr = ctz32(x86_ext_save_areas[comp].bits);
1972 }
1973 }
1974
1975 assert(bitnr < 32);
1976 assert(w < FEATURE_WORDS);
1977 return feature_word_info[w].feat_names[bitnr];
1978}
1979
dc15c051
IM		 1980/* Compatibily hack to maintain legacy +-feat semantic,
1981 * where +-feat overwrites any feature set by
1982 * feat=on|feat even if the later is parsed after +-feat
1983 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
1984 */
2fae0d96 1985static GList *plus_features, *minus_features;
dc15c051 1986
83a00f60
EH		 1987static gint compare_string(gconstpointer a, gconstpointer b)
1988{
1989 return g_strcmp0(a, b);
1990}
1991
8f961357
EH		 1992/* Parse "+feature,-feature,feature=foo" CPU feature string
1993 */
62a48a2a 1994static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 1995 Error **errp)
8f961357 1996{
8f961357 1997 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 1998 static bool cpu_globals_initialized;
83a00f60 1999 bool ambiguous = false;
62a48a2a
IM		 2000
2001 if (cpu_globals_initialized) {
2002 return;
2003 }
2004 cpu_globals_initialized = true;
8f961357 2005
f6750e95
EH		 2006 if (!features) {
2007 return;
2008 }
2009
2010 for (featurestr = strtok(features, ",");
685479bd 2011 featurestr;
f6750e95
EH		 2012 featurestr = strtok(NULL, ",")) {
2013 const char *name;
2014 const char *val = NULL;
2015 char *eq = NULL;
cf2887c9 2016 char num[32];
62a48a2a 2017 GlobalProperty *prop;
c6dc6f63 2018
f6750e95 2019 /* Compatibility syntax: */
c6dc6f63 2020 if (featurestr[0] == '+') {
2fae0d96
EH		 2021 plus_features = g_list_append(plus_features,
2022 g_strdup(featurestr + 1));
f6750e95 2023 continue;
c6dc6f63 2024 } else if (featurestr[0] == '-') {
2fae0d96
EH		 2025 minus_features = g_list_append(minus_features,
2026 g_strdup(featurestr + 1));
f6750e95
EH		 2027 continue;
2028 }
2029
2030 eq = strchr(featurestr, '=');
2031 if (eq) {
2032 *eq++ = 0;
2033 val = eq;
c6dc6f63 2034 } else {
f6750e95 2035 val = "on";
a91987c2 2036 }
f6750e95
EH		 2037
2038 feat2prop(featurestr);
2039 name = featurestr;
2040
83a00f60
EH		 2041 if (g_list_find_custom(plus_features, name, compare_string)) {
2042 error_report("warning: Ambiguous CPU model string. "
2043 "Don't mix both \"+%s\" and \"%s=%s\"",
2044 name, name, val);
2045 ambiguous = true;
2046 }
2047 if (g_list_find_custom(minus_features, name, compare_string)) {
2048 error_report("warning: Ambiguous CPU model string. "
2049 "Don't mix both \"-%s\" and \"%s=%s\"",
2050 name, name, val);
2051 ambiguous = true;
2052 }
2053
f6750e95
EH		 2054 /* Special case: */
2055 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 2056 int ret;
f46bfdbf 2057 uint64_t tsc_freq;
f6750e95 2058
f17fd4fd 2059 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 2060 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 2061 error_setg(errp, "bad numerical value %s", val);
2062 return;
2063 }
2064 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2065 val = num;
2066 name = "tsc-frequency";
c6dc6f63 2067 }
f6750e95 2068
62a48a2a
IM		 2069 prop = g_new0(typeof(*prop), 1);
2070 prop->driver = typename;
2071 prop->property = g_strdup(name);
2072 prop->value = g_strdup(val);
2073 prop->errp = &error_fatal;
2074 qdev_prop_register_global(prop);
f6750e95
EH		 2075 }
2076
83a00f60
EH		 2077 if (ambiguous) {
2078 error_report("warning: Compatibility of ambiguous CPU model "
2079 "strings won't be kept on future QEMU versions");
2080 }
c6dc6f63
AP		 2081}
2082
b8d834a0 2083static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 2084static int x86_cpu_filter_features(X86CPU *cpu);
2085
2086/* Check for missing features that may prevent the CPU class from
2087 * running using the current machine and accelerator.
2088 */
2089static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
2090 strList **missing_feats)
2091{
2092 X86CPU *xc;
2093 FeatureWord w;
2094 Error *err = NULL;
2095 strList **next = missing_feats;
2096
2097 if (xcc->kvm_required && !kvm_enabled()) {
2098 strList *new = g_new0(strList, 1);
2099 new->value = g_strdup("kvm");;
2100 *missing_feats = new;
2101 return;
2102 }
2103
2104 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2105
b8d834a0 2106 x86_cpu_expand_features(xc, &err);
b54c9377 2107 if (err) {
b8d834a0 2108 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 2109 * but in case it does, just report the model as not
2110 * runnable at all using the "type" property.
2111 */
2112 strList *new = g_new0(strList, 1);
2113 new->value = g_strdup("type");
2114 *next = new;
2115 next = &new->next;
2116 }
2117
2118 x86_cpu_filter_features(xc);
2119
2120 for (w = 0; w < FEATURE_WORDS; w++) {
2121 uint32_t filtered = xc->filtered_features[w];
2122 int i;
2123 for (i = 0; i < 32; i++) {
2124 if (filtered & (1UL << i)) {
2125 strList *new = g_new0(strList, 1);
2126 new->value = g_strdup(x86_cpu_feature_name(w, i));
2127 *next = new;
2128 next = &new->next;
2129 }
2130 }
2131 }
2132
2133 object_unref(OBJECT(xc));
2134}
2135
8c3329e5 2136/* Print all cpuid feature names in featureset
c6dc6f63 2137 */
8c3329e5 2138static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2139{
8c3329e5
EH		 2140 int bit;
2141 bool first = true;
2142
2143 for (bit = 0; bit < 32; bit++) {
2144 if (featureset[bit]) {
2145 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2146 first = false;
c6dc6f63 2147 }
8c3329e5 2148 }
c6dc6f63
AP		 2149}
2150
f48c8837 2151/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 2152static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
2153{
2154 ObjectClass *class_a = (ObjectClass *)a;
2155 ObjectClass *class_b = (ObjectClass *)b;
2156 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
2157 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
2158 const char *name_a, *name_b;
2159
f48c8837
EH		 2160 if (cc_a->ordering != cc_b->ordering) {
2161 return cc_a->ordering - cc_b->ordering;
ee465a3e
EH		 2162 } else {
2163 name_a = object_class_get_name(class_a);
2164 name_b = object_class_get_name(class_b);
2165 return strcmp(name_a, name_b);
2166 }
2167}
2168
2169static GSList *get_sorted_cpu_model_list(void)
2170{
2171 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
2172 list = g_slist_sort(list, x86_cpu_list_compare);
2173 return list;
2174}
2175
2176static void x86_cpu_list_entry(gpointer data, gpointer user_data)
2177{
2178 ObjectClass *oc = data;
2179 X86CPUClass *cc = X86_CPU_CLASS(oc);
2180 CPUListState *s = user_data;
2181 char *name = x86_cpu_class_get_model_name(cc);
2182 const char *desc = cc->model_description;
0bacd8b3 2183 if (!desc && cc->cpu_def) {
ee465a3e
EH		 2184 desc = cc->cpu_def->model_id;
2185 }
2186
2187 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
2188 name, desc);
2189 g_free(name);
2190}
2191
2192/* list available CPU models and flags */
e916cbf8 2193void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2194{
7fc9b714 2195 int i;
ee465a3e
EH		 2196 CPUListState s = {
2197 .file = f,
2198 .cpu_fprintf = cpu_fprintf,
2199 };
2200 GSList *list;
c6dc6f63 2201
ee465a3e
EH		 2202 (*cpu_fprintf)(f, "Available CPUs:\n");
2203 list = get_sorted_cpu_model_list();
2204 g_slist_foreach(list, x86_cpu_list_entry, &s);
2205 g_slist_free(list);
21ad7789 2206
6cdf8854 2207 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2208 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2209 FeatureWordInfo *fw = &feature_word_info[i];
2210
8c3329e5
EH		 2211 (*cpu_fprintf)(f, " ");
2212 listflags(f, cpu_fprintf, fw->feat_names);
2213 (*cpu_fprintf)(f, "\n");
3af60be2 2214 }
c6dc6f63
AP		 2215}
2216
ee465a3e
EH		 2217static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
2218{
2219 ObjectClass *oc = data;
2220 X86CPUClass *cc = X86_CPU_CLASS(oc);
2221 CpuDefinitionInfoList **cpu_list = user_data;
2222 CpuDefinitionInfoList *entry;
2223 CpuDefinitionInfo *info;
2224
2225 info = g_malloc0(sizeof(*info));
2226 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 2227 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
2228 info->has_unavailable_features = true;
8ed877b7 2229 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 2230 info->migration_safe = cc->migration_safe;
2231 info->has_migration_safe = true;
5adbed30 2232 info->q_static = cc->static_model;
ee465a3e
EH		 2233
2234 entry = g_malloc0(sizeof(*entry));
2235 entry->value = info;
2236 entry->next = *cpu_list;
2237 *cpu_list = entry;
2238}
2239
76b64a7a 2240CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2241{
2242 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 2243 GSList *list = get_sorted_cpu_model_list();
2244 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
2245 g_slist_free(list);
e3966126
AL		 2246 return cpu_list;
2247}
2248
84f1b92f
EH		 2249static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2250 bool migratable_only)
27418adf
EH		 2251{
2252 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2253 uint32_t r;
27418adf 2254
fefb41bf 2255 if (kvm_enabled()) {
84f1b92f
EH		 2256 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2257 wi->cpuid_ecx,
2258 wi->cpuid_reg);
fefb41bf 2259 } else if (tcg_enabled()) {
84f1b92f 2260 r = wi->tcg_features;
fefb41bf
EH		 2261 } else {
2262 return ~0;
2263 }
84f1b92f
EH		 2264 if (migratable_only) {
2265 r &= x86_cpu_get_migratable_flags(w);
2266 }
2267 return r;
27418adf
EH		 2268}
2269
8ca30e86
EH		 2270static void x86_cpu_report_filtered_features(X86CPU *cpu)
2271{
2272 FeatureWord w;
2273
2274 for (w = 0; w < FEATURE_WORDS; w++) {
2275 report_unavailable_features(w, cpu->filtered_features[w]);
2276 }
2277}
2278
5114e842
EH		 2279static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2280{
2281 PropValue *pv;
2282 for (pv = props; pv->prop; pv++) {
2283 if (!pv->value) {
2284 continue;
2285 }
2286 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2287 &error_abort);
2288 }
2289}
2290
d940ee9b 2291/* Load data from X86CPUDefinition
c080e30e 2292 */
d940ee9b 2293static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2294{
61dcd775 2295 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2296 const char *vendor;
2297 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2298 FeatureWord w;
c6dc6f63 2299
c39c0edf
EH		 2300 /* CPU models only set _minimum_ values for level/xlevel: */
2301 object_property_set_int(OBJECT(cpu), def->level, "min-level", errp);
2302 object_property_set_int(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
2303
2d64255b
AF		 2304 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2305 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2306 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2307 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2308 for (w = 0; w < FEATURE_WORDS; w++) {
2309 env->features[w] = def->features[w];
2310 }
82beb536 2311
9576de75 2312 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2313 if (kvm_enabled()) {
492a4c94
LT		 2314 if (!kvm_irqchip_in_kernel()) {
2315 x86_cpu_change_kvm_default("x2apic", "off");
2316 }
2317
5114e842 2318 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 2319 } else if (tcg_enabled()) {
2320 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 2321 }
5fcca9ff 2322
82beb536 2323 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2324
2325 /* sysenter isn't supported in compatibility mode on AMD,
2326 * syscall isn't supported in compatibility mode on Intel.
2327 * Normally we advertise the actual CPU vendor, but you can
2328 * override this using the 'vendor' property if you want to use
2329 * KVM's sysenter/syscall emulation in compatibility mode and
2330 * when doing cross vendor migration
2331 */
74f54bc4 2332 vendor = def->vendor;
7c08db30
EH		 2333 if (kvm_enabled()) {
2334 uint32_t ebx = 0, ecx = 0, edx = 0;
2335 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2336 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2337 vendor = host_vendor;
2338 }
2339
2340 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2341
c6dc6f63
AP		 2342}
2343
0856579c 2344X86CPU *cpu_x86_init(const char *cpu_model)
7f833247 2345{
a57d0163 2346 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
5c3c6a68
AF		 2347}
2348
d940ee9b
EH		 2349static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2350{
2351 X86CPUDefinition *cpudef = data;
2352 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2353
2354 xcc->cpu_def = cpudef;
bd72159d 2355 xcc->migration_safe = true;
d940ee9b
EH		 2356}
2357
2358static void x86_register_cpudef_type(X86CPUDefinition *def)
2359{
2360 char *typename = x86_cpu_type_name(def->name);
2361 TypeInfo ti = {
2362 .name = typename,
2363 .parent = TYPE_X86_CPU,
2364 .class_init = x86_cpu_cpudef_class_init,
2365 .class_data = def,
2366 };
2367
2a923a29
EH		 2368 /* AMD aliases are handled at runtime based on CPUID vendor, so
2369 * they shouldn't be set on the CPU model table.
2370 */
2371 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
2372
d940ee9b
EH		 2373 type_register(&ti);
2374 g_free(typename);
2375}
2376
c6dc6f63 2377#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2378
0e26b7b8
BS		 2379void cpu_clear_apic_feature(CPUX86State *env)
2380{
0514ef2f 2381 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2382}
2383
c6dc6f63
AP		 2384#endif /* !CONFIG_USER_ONLY */
2385
c6dc6f63
AP		 2386void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2387 uint32_t *eax, uint32_t *ebx,
2388 uint32_t *ecx, uint32_t *edx)
2389{
a60f24b5
AF		 2390 X86CPU *cpu = x86_env_get_cpu(env);
2391 CPUState *cs = CPU(cpu);
14c985cf 2392 uint32_t pkg_offset;
a60f24b5 2393
c6dc6f63
AP		 2394 /* test if maximum index reached */
2395 if (index & 0x80000000) {
b3baa152
BW		 2396 if (index > env->cpuid_xlevel) {
2397 if (env->cpuid_xlevel2 > 0) {
2398 /* Handle the Centaur's CPUID instruction. */
2399 if (index > env->cpuid_xlevel2) {
2400 index = env->cpuid_xlevel2;
2401 } else if (index < 0xC0000000) {
2402 index = env->cpuid_xlevel;
2403 }
2404 } else {
57f26ae7
EH		 2405 /* Intel documentation states that invalid EAX input will
2406 * return the same information as EAX=cpuid_level
2407 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2408 */
2409 index = env->cpuid_level;
b3baa152
BW		 2410 }
2411 }
c6dc6f63
AP		 2412 } else {
2413 if (index > env->cpuid_level)
2414 index = env->cpuid_level;
2415 }
2416
2417 switch(index) {
2418 case 0:
2419 *eax = env->cpuid_level;
5eb2f7a4
EH		 2420 *ebx = env->cpuid_vendor1;
2421 *edx = env->cpuid_vendor2;
2422 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2423 break;
2424 case 1:
2425 *eax = env->cpuid_version;
7e72a45c
EH		 2426 *ebx = (cpu->apic_id << 24) |
2427 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2428 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2429 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2430 *ecx |= CPUID_EXT_OSXSAVE;
2431 }
0514ef2f 2432 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2433 if (cs->nr_cores * cs->nr_threads > 1) {
2434 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2435 *edx |= CPUID_HT;
c6dc6f63
AP		 2436 }
2437 break;
2438 case 2:
2439 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2440 if (cpu->cache_info_passthrough) {
2441 host_cpuid(index, 0, eax, ebx, ecx, edx);
2442 break;
2443 }
5e891bf8 2444 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 2445 *ebx = 0;
14c985cf
LM		 2446 if (!cpu->enable_l3_cache) {
2447 *ecx = 0;
2448 } else {
2449 *ecx = L3_N_DESCRIPTOR;
2450 }
5e891bf8
EH		 2451 *edx = (L1D_DESCRIPTOR << 16) | \
2452 (L1I_DESCRIPTOR << 8) | \
2453 (L2_DESCRIPTOR);
c6dc6f63
AP		 2454 break;
2455 case 4:
2456 /* cache info: needed for Core compatibility */
787aaf57
BC		 2457 if (cpu->cache_info_passthrough) {
2458 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2459 *eax &= ~0xFC000000;
c6dc6f63 2460 } else {
2f7a21c4 2461 *eax = 0;
76c2975a 2462 switch (count) {
c6dc6f63 2463 case 0: /* L1 dcache info */
5e891bf8
EH		 2464 *eax |= CPUID_4_TYPE_DCACHE | \
2465 CPUID_4_LEVEL(1) | \
2466 CPUID_4_SELF_INIT_LEVEL;
2467 *ebx = (L1D_LINE_SIZE - 1) | \
2468 ((L1D_PARTITIONS - 1) << 12) | \
2469 ((L1D_ASSOCIATIVITY - 1) << 22);
2470 *ecx = L1D_SETS - 1;
2471 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2472 break;
2473 case 1: /* L1 icache info */
5e891bf8
EH		 2474 *eax |= CPUID_4_TYPE_ICACHE | \
2475 CPUID_4_LEVEL(1) | \
2476 CPUID_4_SELF_INIT_LEVEL;
2477 *ebx = (L1I_LINE_SIZE - 1) | \
2478 ((L1I_PARTITIONS - 1) << 12) | \
2479 ((L1I_ASSOCIATIVITY - 1) << 22);
2480 *ecx = L1I_SETS - 1;
2481 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2482 break;
2483 case 2: /* L2 cache info */
5e891bf8
EH		 2484 *eax |= CPUID_4_TYPE_UNIFIED | \
2485 CPUID_4_LEVEL(2) | \
2486 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2487 if (cs->nr_threads > 1) {
2488 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2489 }
5e891bf8
EH		 2490 *ebx = (L2_LINE_SIZE - 1) | \
2491 ((L2_PARTITIONS - 1) << 12) | \
2492 ((L2_ASSOCIATIVITY - 1) << 22);
2493 *ecx = L2_SETS - 1;
2494 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63 2495 break;
14c985cf
LM		 2496 case 3: /* L3 cache info */
2497 if (!cpu->enable_l3_cache) {
2498 *eax = 0;
2499 *ebx = 0;
2500 *ecx = 0;
2501 *edx = 0;
2502 break;
2503 }
2504 *eax |= CPUID_4_TYPE_UNIFIED | \
2505 CPUID_4_LEVEL(3) | \
2506 CPUID_4_SELF_INIT_LEVEL;
2507 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2508 *eax |= ((1 << pkg_offset) - 1) << 14;
2509 *ebx = (L3_N_LINE_SIZE - 1) | \
2510 ((L3_N_PARTITIONS - 1) << 12) | \
2511 ((L3_N_ASSOCIATIVITY - 1) << 22);
2512 *ecx = L3_N_SETS - 1;
2513 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2514 break;
c6dc6f63
AP		 2515 default: /* end of info */
2516 *eax = 0;
2517 *ebx = 0;
2518 *ecx = 0;
2519 *edx = 0;
2520 break;
76c2975a
PB		 2521 }
2522 }
2523
2524 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2525 if ((*eax & 31) && cs->nr_cores > 1) {
2526 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2527 }
2528 break;
2529 case 5:
2530 /* mwait info: needed for Core compatibility */
2531 *eax = 0; /* Smallest monitor-line size in bytes */
2532 *ebx = 0; /* Largest monitor-line size in bytes */
2533 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2534 *edx = 0;
2535 break;
2536 case 6:
2537 /* Thermal and Power Leaf */
28b8e4d0 2538 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2539 *ebx = 0;
2540 *ecx = 0;
2541 *edx = 0;
2542 break;
f7911686 2543 case 7:
13526728
EH		 2544 /* Structured Extended Feature Flags Enumeration Leaf */
2545 if (count == 0) {
2546 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2547 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2548 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2549 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2550 *ecx |= CPUID_7_0_ECX_OSPKE;
2551 }
95ea69fb 2552 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 2553 } else {
2554 *eax = 0;
2555 *ebx = 0;
2556 *ecx = 0;
2557 *edx = 0;
2558 }
2559 break;
c6dc6f63
AP		 2560 case 9:
2561 /* Direct Cache Access Information Leaf */
2562 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2563 *ebx = 0;
2564 *ecx = 0;
2565 *edx = 0;
2566 break;
2567 case 0xA:
2568 /* Architectural Performance Monitoring Leaf */
9337e3b6 2569 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2570 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2571
2572 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2573 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2574 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2575 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2576 } else {
2577 *eax = 0;
2578 *ebx = 0;
2579 *ecx = 0;
2580 *edx = 0;
2581 }
c6dc6f63 2582 break;
5232d00a
RK		 2583 case 0xB:
2584 /* Extended Topology Enumeration Leaf */
2585 if (!cpu->enable_cpuid_0xb) {
2586 *eax = *ebx = *ecx = *edx = 0;
2587 break;
2588 }
2589
2590 *ecx = count & 0xff;
2591 *edx = cpu->apic_id;
2592
2593 switch (count) {
2594 case 0:
eab60fb9
MAL		 2595 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
2596 *ebx = cs->nr_threads;
5232d00a
RK		 2597 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2598 break;
2599 case 1:
eab60fb9
MAL		 2600 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2601 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 2602 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2603 break;
2604 default:
2605 *eax = 0;
2606 *ebx = 0;
2607 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2608 }
2609
2610 assert(!(*eax & ~0x1f));
2611 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2612 break;
2560f19f 2613 case 0xD: {
51e49430 2614 /* Processor Extended State */
2560f19f
PB		 2615 *eax = 0;
2616 *ebx = 0;
2617 *ecx = 0;
2618 *edx = 0;
19dc85db 2619 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2620 break;
2621 }
4928cd6d 2622
2560f19f 2623 if (count == 0) {
96193c22
EH		 2624 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
2625 *eax = env->features[FEAT_XSAVE_COMP_LO];
2626 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 2627 *ebx = *ecx;
2628 } else if (count == 1) {
0bb0b2d2 2629 *eax = env->features[FEAT_XSAVE];
f4f1110e 2630 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 2631 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
2632 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 2633 *eax = esa->size;
2634 *ebx = esa->offset;
2560f19f 2635 }
51e49430
SY		 2636 }
2637 break;
2560f19f 2638 }
c6dc6f63
AP		 2639 case 0x80000000:
2640 *eax = env->cpuid_xlevel;
2641 *ebx = env->cpuid_vendor1;
2642 *edx = env->cpuid_vendor2;
2643 *ecx = env->cpuid_vendor3;
2644 break;
2645 case 0x80000001:
2646 *eax = env->cpuid_version;
2647 *ebx = 0;
0514ef2f
EH		 2648 *ecx = env->features[FEAT_8000_0001_ECX];
2649 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2650
2651 /* The Linux kernel checks for the CMPLegacy bit and
2652 * discards multiple thread information if it is set.
cb8d4c8f 2653 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2654 */
ce3960eb 2655 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2656 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2657 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2658 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2659 *ecx |= 1 << 1; /* CmpLegacy bit */
2660 }
2661 }
c6dc6f63
AP		 2662 break;
2663 case 0x80000002:
2664 case 0x80000003:
2665 case 0x80000004:
2666 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2667 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2668 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2669 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2670 break;
2671 case 0x80000005:
2672 /* cache info (L1 cache) */
787aaf57
BC		 2673 if (cpu->cache_info_passthrough) {
2674 host_cpuid(index, 0, eax, ebx, ecx, edx);
2675 break;
2676 }
5e891bf8
EH		 2677 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2678 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2679 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2680 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2681 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2682 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2683 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2684 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2685 break;
2686 case 0x80000006:
2687 /* cache info (L2 cache) */
787aaf57
BC		 2688 if (cpu->cache_info_passthrough) {
2689 host_cpuid(index, 0, eax, ebx, ecx, edx);
2690 break;
2691 }
5e891bf8
EH		 2692 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2693 (L2_DTLB_2M_ENTRIES << 16) | \
2694 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2695 (L2_ITLB_2M_ENTRIES);
2696 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2697 (L2_DTLB_4K_ENTRIES << 16) | \
2698 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2699 (L2_ITLB_4K_ENTRIES);
2700 *ecx = (L2_SIZE_KB_AMD << 16) | \
2701 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2702 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
14c985cf
LM		 2703 if (!cpu->enable_l3_cache) {
2704 *edx = ((L3_SIZE_KB / 512) << 18) | \
2705 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2706 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2707 } else {
2708 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
2709 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
2710 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
2711 }
c6dc6f63 2712 break;
303752a9
MT		 2713 case 0x80000007:
2714 *eax = 0;
2715 *ebx = 0;
2716 *ecx = 0;
2717 *edx = env->features[FEAT_8000_0007_EDX];
2718 break;
c6dc6f63
AP		 2719 case 0x80000008:
2720 /* virtual & phys address size in low 2 bytes. */
0514ef2f 2721 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 2722 /* 64 bit processor */
2723 *eax = cpu->phys_bits; /* configurable physical bits */
2724 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
2725 *eax |= 0x00003900; /* 57 bits virtual */
2726 } else {
2727 *eax |= 0x00003000; /* 48 bits virtual */
2728 }
c6dc6f63 2729 } else {
af45907a 2730 *eax = cpu->phys_bits;
c6dc6f63
AP		 2731 }
2732 *ebx = 0;
2733 *ecx = 0;
2734 *edx = 0;
ce3960eb
AF		 2735 if (cs->nr_cores * cs->nr_threads > 1) {
2736 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2737 }
2738 break;
2739 case 0x8000000A:
0514ef2f 2740 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2741 *eax = 0x00000001; /* SVM Revision */
2742 *ebx = 0x00000010; /* nr of ASIDs */
2743 *ecx = 0;
0514ef2f 2744 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2745 } else {
2746 *eax = 0;
2747 *ebx = 0;
2748 *ecx = 0;
2749 *edx = 0;
2750 }
c6dc6f63 2751 break;
b3baa152
BW		 2752 case 0xC0000000:
2753 *eax = env->cpuid_xlevel2;
2754 *ebx = 0;
2755 *ecx = 0;
2756 *edx = 0;
2757 break;
2758 case 0xC0000001:
2759 /* Support for VIA CPU's CPUID instruction */
2760 *eax = env->cpuid_version;
2761 *ebx = 0;
2762 *ecx = 0;
0514ef2f 2763 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2764 break;
2765 case 0xC0000002:
2766 case 0xC0000003:
2767 case 0xC0000004:
2768 /* Reserved for the future, and now filled with zero */
2769 *eax = 0;
2770 *ebx = 0;
2771 *ecx = 0;
2772 *edx = 0;
2773 break;
c6dc6f63
AP		 2774 default:
2775 /* reserved values: zero */
2776 *eax = 0;
2777 *ebx = 0;
2778 *ecx = 0;
2779 *edx = 0;
2780 break;
2781 }
2782}
5fd2087a
AF		 2783
2784/* CPUClass::reset() */
2785static void x86_cpu_reset(CPUState *s)
2786{
2787 X86CPU *cpu = X86_CPU(s);
2788 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2789 CPUX86State *env = &cpu->env;
a114d25d
RH		 2790 target_ulong cr4;
2791 uint64_t xcr0;
c1958aea
AF		 2792 int i;
2793
5fd2087a
AF		 2794 xcc->parent_reset(s);
2795
5e992a8e 2796 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 2797
c1958aea
AF		 2798 env->old_exception = -1;
2799
2800 /* init to reset state */
2801
c1958aea
AF		 2802 env->hflags2 |= HF2_GIF_MASK;
2803
2804 cpu_x86_update_cr0(env, 0x60000010);
2805 env->a20_mask = ~0x0;
2806 env->smbase = 0x30000;
2807
2808 env->idt.limit = 0xffff;
2809 env->gdt.limit = 0xffff;
2810 env->ldt.limit = 0xffff;
2811 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2812 env->tr.limit = 0xffff;
2813 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2814
2815 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2816 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2817 DESC_R_MASK | DESC_A_MASK);
2818 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2819 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2820 DESC_A_MASK);
2821 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2822 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2823 DESC_A_MASK);
2824 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2825 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2826 DESC_A_MASK);
2827 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2828 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2829 DESC_A_MASK);
2830 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2831 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2832 DESC_A_MASK);
2833
2834 env->eip = 0xfff0;
2835 env->regs[R_EDX] = env->cpuid_version;
2836
2837 env->eflags = 0x2;
2838
2839 /* FPU init */
2840 for (i = 0; i < 8; i++) {
2841 env->fptags[i] = 1;
2842 }
5bde1407 2843 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2844
2845 env->mxcsr = 0x1f80;
a114d25d
RH		 2846 /* All units are in INIT state. */
2847 env->xstate_bv = 0;
c1958aea
AF		 2848
2849 env->pat = 0x0007040600070406ULL;
2850 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2851
2852 memset(env->dr, 0, sizeof(env->dr));
2853 env->dr[6] = DR6_FIXED_1;
2854 env->dr[7] = DR7_FIXED_1;
b3310ab3 2855 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2856 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2857
a114d25d 2858 cr4 = 0;
cfc3b074 2859 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 2860
2861#ifdef CONFIG_USER_ONLY
2862 /* Enable all the features for user-mode. */
2863 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 2864 xcr0 |= XSTATE_SSE_MASK;
a114d25d 2865 }
0f70ed47
PB		 2866 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2867 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 2868 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 2869 xcr0 |= 1ull << i;
2870 }
a114d25d 2871 }
0f70ed47 2872
a114d25d
RH		 2873 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2874 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2875 }
07929f2a
RH		 2876 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2877 cr4 |= CR4_FSGSBASE_MASK;
2878 }
a114d25d
RH		 2879#endif
2880
2881 env->xcr0 = xcr0;
2882 cpu_x86_update_cr4(env, cr4);
0522604b 2883
9db2efd9
AW		 2884 /*
2885 * SDM 11.11.5 requires:
2886 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2887 * - IA32_MTRR_PHYSMASKn.V = 0
2888 * All other bits are undefined. For simplification, zero it all.
2889 */
2890 env->mtrr_deftype = 0;
2891 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2892 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2893
dd673288
IM		 2894#if !defined(CONFIG_USER_ONLY)
2895 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2896 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2897
259186a7 2898 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2899
2900 if (kvm_enabled()) {
2901 kvm_arch_reset_vcpu(cpu);
2902 }
dd673288 2903#endif
5fd2087a
AF		 2904}
2905
dd673288
IM		 2906#ifndef CONFIG_USER_ONLY
2907bool cpu_is_bsp(X86CPU *cpu)
2908{
02e51483 2909 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2910}
65dee380
IM		 2911
2912/* TODO: remove me, when reset over QOM tree is implemented */
2913static void x86_cpu_machine_reset_cb(void *opaque)
2914{
2915 X86CPU *cpu = opaque;
2916 cpu_reset(CPU(cpu));
2917}
dd673288
IM		 2918#endif
2919
de024815
AF		 2920static void mce_init(X86CPU *cpu)
2921{
2922 CPUX86State *cenv = &cpu->env;
2923 unsigned int bank;
2924
2925 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2926 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 2927 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 2928 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
2929 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 2930 cenv->mcg_ctl = ~(uint64_t)0;
2931 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2932 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2933 }
2934 }
2935}
2936
bdeec802 2937#ifndef CONFIG_USER_ONLY
2f114315 2938APICCommonClass *apic_get_class(void)
bdeec802 2939{
bdeec802
IM		 2940 const char *apic_type = "apic";
2941
15eafc2e 2942 if (kvm_apic_in_kernel()) {
bdeec802
IM		 2943 apic_type = "kvm-apic";
2944 } else if (xen_enabled()) {
2945 apic_type = "xen-apic";
2946 }
2947
2f114315
RK		 2948 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
2949}
2950
2951static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2952{
2953 APICCommonState *apic;
2954 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
2955
2956 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 2957
6816b1b3
IM		 2958 object_property_add_child(OBJECT(cpu), "lapic",
2959 OBJECT(cpu->apic_state), &error_abort);
67e55caa 2960 object_unref(OBJECT(cpu->apic_state));
6816b1b3 2961
33d7a288 2962 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2963 /* TODO: convert to link<> */
02e51483 2964 apic = APIC_COMMON(cpu->apic_state);
60671e58 2965 apic->cpu = cpu;
8d42d2d3 2966 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 2967}
2968
2969static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2970{
8d42d2d3
CF		 2971 APICCommonState *apic;
2972 static bool apic_mmio_map_once;
2973
02e51483 2974 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2975 return;
2976 }
6e8e2651
MA		 2977 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2978 errp);
8d42d2d3
CF		 2979
2980 /* Map APIC MMIO area */
2981 apic = APIC_COMMON(cpu->apic_state);
2982 if (!apic_mmio_map_once) {
2983 memory_region_add_subregion_overlap(get_system_memory(),
2984 apic->apicbase &
2985 MSR_IA32_APICBASE_BASE,
2986 &apic->io_memory,
2987 0x1000);
2988 apic_mmio_map_once = true;
2989 }
bdeec802 2990}
f809c605
PB		 2991
2992static void x86_cpu_machine_done(Notifier *n, void *unused)
2993{
2994 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2995 MemoryRegion *smram =
2996 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2997
2998 if (smram) {
2999 cpu->smram = g_new(MemoryRegion, 1);
3000 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
3001 smram, 0, 1ull << 32);
3002 memory_region_set_enabled(cpu->smram, false);
3003 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
3004 }
3005}
d3c64d6a
IM		 3006#else
3007static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3008{
3009}
bdeec802
IM		 3010#endif
3011
11f6fee5
DDAG		 3012/* Note: Only safe for use on x86(-64) hosts */
3013static uint32_t x86_host_phys_bits(void)
3014{
3015 uint32_t eax;
3016 uint32_t host_phys_bits;
3017
3018 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
3019 if (eax >= 0x80000008) {
3020 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
3021 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3022 * at 23:16 that can specify a maximum physical address bits for
3023 * the guest that can override this value; but I've not seen
3024 * anything with that set.
3025 */
3026 host_phys_bits = eax & 0xff;
3027 } else {
3028 /* It's an odd 64 bit machine that doesn't have the leaf for
3029 * physical address bits; fall back to 36 that's most older
3030 * Intel.
3031 */
3032 host_phys_bits = 36;
3033 }
3034
3035 return host_phys_bits;
3036}
e48638fd 3037
c39c0edf
EH		 3038static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
3039{
3040 if (*min < value) {
3041 *min = value;
3042 }
3043}
3044
3045/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3046static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
3047{
3048 CPUX86State *env = &cpu->env;
3049 FeatureWordInfo *fi = &feature_word_info[w];
3050 uint32_t eax = fi->cpuid_eax;
3051 uint32_t region = eax & 0xF0000000;
3052
3053 if (!env->features[w]) {
3054 return;
3055 }
3056
3057 switch (region) {
3058 case 0x00000000:
3059 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
3060 break;
3061 case 0x80000000:
3062 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
3063 break;
3064 case 0xC0000000:
3065 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
3066 break;
3067 }
3068}
3069
2ca8a8be
EH		 3070/* Calculate XSAVE components based on the configured CPU feature flags */
3071static void x86_cpu_enable_xsave_components(X86CPU *cpu)
3072{
3073 CPUX86State *env = &cpu->env;
3074 int i;
96193c22 3075 uint64_t mask;
2ca8a8be
EH		 3076
3077 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
3078 return;
3079 }
3080
e3c9022b
EH		 3081 mask = 0;
3082 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 3083 const ExtSaveArea *esa = &x86_ext_save_areas[i];
3084 if (env->features[esa->feature] & esa->bits) {
96193c22 3085 mask |= (1ULL << i);
2ca8a8be
EH		 3086 }
3087 }
3088
96193c22
EH		 3089 env->features[FEAT_XSAVE_COMP_LO] = mask;
3090 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 3091}
3092
b8d834a0
EH		 3093/***** Steps involved on loading and filtering CPUID data
3094 *
3095 * When initializing and realizing a CPU object, the steps
3096 * involved in setting up CPUID data are:
3097 *
3098 * 1) Loading CPU model definition (X86CPUDefinition). This is
3099 * implemented by x86_cpu_load_def() and should be completely
3100 * transparent, as it is done automatically by instance_init.
3101 * No code should need to look at X86CPUDefinition structs
3102 * outside instance_init.
3103 *
3104 * 2) CPU expansion. This is done by realize before CPUID
3105 * filtering, and will make sure host/accelerator data is
3106 * loaded for CPU models that depend on host capabilities
3107 * (e.g. "host"). Done by x86_cpu_expand_features().
3108 *
3109 * 3) CPUID filtering. This initializes extra data related to
3110 * CPUID, and checks if the host supports all capabilities
3111 * required by the CPU. Runnability of a CPU model is
3112 * determined at this step. Done by x86_cpu_filter_features().
3113 *
3114 * Some operations don't require all steps to be performed.
3115 * More precisely:
3116 *
3117 * - CPU instance creation (instance_init) will run only CPU
3118 * model loading. CPU expansion can't run at instance_init-time
3119 * because host/accelerator data may be not available yet.
3120 * - CPU realization will perform both CPU model expansion and CPUID
3121 * filtering, and return an error in case one of them fails.
3122 * - query-cpu-definitions needs to run all 3 steps. It needs
3123 * to run CPUID filtering, as the 'unavailable-features'
3124 * field is set based on the filtering results.
3125 * - The query-cpu-model-expansion QMP command only needs to run
3126 * CPU model loading and CPU expansion. It should not filter
3127 * any CPUID data based on host capabilities.
3128 */
3129
3130/* Expand CPU configuration data, based on configured features
3131 * and host/accelerator capabilities when appropriate.
3132 */
3133static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 3134{
b34d12d1 3135 CPUX86State *env = &cpu->env;
dc15c051 3136 FeatureWord w;
2fae0d96 3137 GList *l;
41f3d4d6 3138 Error *local_err = NULL;
9886e834 3139
44bd8e53 3140 /*TODO: cpu->max_features incorrectly overwrites features
dc15c051
IM		 3141 * set using "feat=on|off". Once we fix this, we can convert
3142 * plus_features & minus_features to global properties
3143 * inside x86_cpu_parse_featurestr() too.
3144 */
44bd8e53 3145 if (cpu->max_features) {
dc15c051
IM		 3146 for (w = 0; w < FEATURE_WORDS; w++) {
3147 env->features[w] =
3148 x86_cpu_get_supported_feature_word(w, cpu->migratable);
3149 }
3150 }
3151
2fae0d96
EH		 3152 for (l = plus_features; l; l = l->next) {
3153 const char *prop = l->data;
3154 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
3155 if (local_err) {
3156 goto out;
3157 }
3158 }
3159
3160 for (l = minus_features; l; l = l->next) {
3161 const char *prop = l->data;
3162 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
3163 if (local_err) {
3164 goto out;
3165 }
dc15c051
IM		 3166 }
3167
aec661de
EH		 3168 if (!kvm_enabled() || !cpu->expose_kvm) {
3169 env->features[FEAT_KVM] = 0;
3170 }
3171
2ca8a8be 3172 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 3173
3174 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3175 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
3176 if (cpu->full_cpuid_auto_level) {
3177 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
3178 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
3179 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
3180 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
3181 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
3182 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
3183 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
3184 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
3185 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
3186 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 3187 /* SVM requires CPUID[0x8000000A] */
3188 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
3189 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
3190 }
c39c0edf
EH		 3191 }
3192
3193 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3194 if (env->cpuid_level == UINT32_MAX) {
3195 env->cpuid_level = env->cpuid_min_level;
3196 }
3197 if (env->cpuid_xlevel == UINT32_MAX) {
3198 env->cpuid_xlevel = env->cpuid_min_xlevel;
3199 }
3200 if (env->cpuid_xlevel2 == UINT32_MAX) {
3201 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 3202 }
7a059953 3203
41f3d4d6
EH		 3204out:
3205 if (local_err != NULL) {
3206 error_propagate(errp, local_err);
3207 }
3208}
3209
b8d834a0
EH		 3210/*
3211 * Finishes initialization of CPUID data, filters CPU feature
3212 * words based on host availability of each feature.
3213 *
3214 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
3215 */
3216static int x86_cpu_filter_features(X86CPU *cpu)
3217{
3218 CPUX86State *env = &cpu->env;
3219 FeatureWord w;
3220 int rv = 0;
3221
3222 for (w = 0; w < FEATURE_WORDS; w++) {
3223 uint32_t host_feat =
3224 x86_cpu_get_supported_feature_word(w, false);
3225 uint32_t requested_features = env->features[w];
3226 env->features[w] &= host_feat;
3227 cpu->filtered_features[w] = requested_features & ~env->features[w];
3228 if (cpu->filtered_features[w]) {
3229 rv = 1;
3230 }
3231 }
3232
3233 return rv;
3234}
3235
41f3d4d6
EH		 3236#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3237 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3238 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3239#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3240 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3241 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
3242static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
3243{
3244 CPUState *cs = CPU(dev);
3245 X86CPU *cpu = X86_CPU(dev);
3246 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3247 CPUX86State *env = &cpu->env;
3248 Error *local_err = NULL;
3249 static bool ht_warned;
3250
3251 if (xcc->kvm_required && !kvm_enabled()) {
3252 char *name = x86_cpu_class_get_model_name(xcc);
3253 error_setg(&local_err, "CPU model '%s' requires KVM", name);
3254 g_free(name);
3255 goto out;
3256 }
3257
3258 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
3259 error_setg(errp, "apic-id property was not initialized properly");
3260 return;
3261 }
3262
b8d834a0 3263 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 3264 if (local_err) {
3265 goto out;
3266 }
3267
8ca30e86
EH		 3268 if (x86_cpu_filter_features(cpu) &&
3269 (cpu->check_cpuid || cpu->enforce_cpuid)) {
3270 x86_cpu_report_filtered_features(cpu);
3271 if (cpu->enforce_cpuid) {
3272 error_setg(&local_err,
3273 kvm_enabled() ?
3274 "Host doesn't support requested features" :
3275 "TCG doesn't support requested features");
3276 goto out;
3277 }
9997cf7b
EH		 3278 }
3279
9b15cd9e
IM		 3280 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3281 * CPUID[1].EDX.
3282 */
e48638fd 3283 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 3284 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3285 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 3286 & CPUID_EXT2_AMD_ALIASES);
3287 }
3288
11f6fee5
DDAG		 3289 /* For 64bit systems think about the number of physical bits to present.
3290 * ideally this should be the same as the host; anything other than matching
3291 * the host can cause incorrect guest behaviour.
3292 * QEMU used to pick the magic value of 40 bits that corresponds to
3293 * consumer AMD devices but nothing else.
3294 */
af45907a 3295 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a 3296 if (kvm_enabled()) {
11f6fee5
DDAG		 3297 uint32_t host_phys_bits = x86_host_phys_bits();
3298 static bool warned;
3299
3300 if (cpu->host_phys_bits) {
3301 /* The user asked for us to use the host physical bits */
3302 cpu->phys_bits = host_phys_bits;
3303 }
3304
3305 /* Print a warning if the user set it to a value that's not the
3306 * host value.
3307 */
3308 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3309 !warned) {
3310 error_report("Warning: Host physical bits (%u)"
3311 " does not match phys-bits property (%u)",
3312 host_phys_bits, cpu->phys_bits);
3313 warned = true;
3314 }
3315
3316 if (cpu->phys_bits &&
3317 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3318 cpu->phys_bits < 32)) {
af45907a
DDAG		 3319 error_setg(errp, "phys-bits should be between 32 and %u "
3320 " (but is %u)",
3321 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3322 return;
3323 }
3324 } else {
11f6fee5 3325 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 3326 error_setg(errp, "TCG only supports phys-bits=%u",
3327 TCG_PHYS_ADDR_BITS);
3328 return;
3329 }
3330 }
11f6fee5
DDAG		 3331 /* 0 means it was not explicitly set by the user (or by machine
3332 * compat_props or by the host code above). In this case, the default
3333 * is the value used by TCG (40).
3334 */
3335 if (cpu->phys_bits == 0) {
3336 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3337 }
af45907a
DDAG		 3338 } else {
3339 /* For 32 bit systems don't use the user set value, but keep
3340 * phys_bits consistent with what we tell the guest.
3341 */
3342 if (cpu->phys_bits != 0) {
3343 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3344 return;
3345 }
fefb41bf 3346
af45907a
DDAG		 3347 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3348 cpu->phys_bits = 36;
3349 } else {
3350 cpu->phys_bits = 32;
3351 }
3352 }
ce5b1bbf
LV		 3353 cpu_exec_realizefn(cs, &local_err);
3354 if (local_err != NULL) {
3355 error_propagate(errp, local_err);
3356 return;
3357 }
42ecabaa 3358
57f2453a
EH		 3359 if (tcg_enabled()) {
3360 tcg_x86_init();
3361 }
3362
65dee380
IM		 3363#ifndef CONFIG_USER_ONLY
3364 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 3365
0514ef2f 3366 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 3367 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 3368 if (local_err != NULL) {
4dc1f449 3369 goto out;
bdeec802
IM		 3370 }
3371 }
65dee380
IM		 3372#endif
3373
7a059953 3374 mce_init(cpu);
2001d0cd
PB		 3375
3376#ifndef CONFIG_USER_ONLY
3377 if (tcg_enabled()) {
56943e8c
PM		 3378 AddressSpace *newas = g_new(AddressSpace, 1);
3379
f809c605 3380 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 3381 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 3382
3383 /* Outer container... */
3384 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 3385 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 3386
3387 /* ... with two regions inside: normal system memory with low
3388 * priority, and...
3389 */
3390 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3391 get_system_memory(), 0, ~0ull);
3392 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3393 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 3394 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 3395 cs->num_ases = 1;
56943e8c 3396 cpu_address_space_init(cs, newas, 0);
f809c605
PB		 3397
3398 /* ... SMRAM with higher priority, linked from /machine/smram. */
3399 cpu->machine_done.notify = x86_cpu_machine_done;
3400 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 3401 }
3402#endif
3403
14a10fc3 3404 qemu_init_vcpu(cs);
d3c64d6a 3405
e48638fd
WH		 3406 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3407 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3408 * based on inputs (sockets,cores,threads), it is still better to gives
3409 * users a warning.
3410 *
3411 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3412 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3413 */
3414 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3415 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3416 " -smp options properly.");
3417 ht_warned = true;
3418 }
3419
d3c64d6a
IM		 3420 x86_cpu_apic_realize(cpu, &local_err);
3421 if (local_err != NULL) {
3422 goto out;
3423 }
14a10fc3 3424 cpu_reset(cs);
2b6f294c 3425
4dc1f449 3426 xcc->parent_realize(dev, &local_err);
2001d0cd 3427
4dc1f449
IM		 3428out:
3429 if (local_err != NULL) {
3430 error_propagate(errp, local_err);
3431 return;
3432 }
7a059953
AF		 3433}
3434
c884776e
IM		 3435static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3436{
3437 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 3438 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3439 Error *local_err = NULL;
c884776e
IM		 3440
3441#ifndef CONFIG_USER_ONLY
3442 cpu_remove_sync(CPU(dev));
3443 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3444#endif
3445
3446 if (cpu->apic_state) {
3447 object_unparent(OBJECT(cpu->apic_state));
3448 cpu->apic_state = NULL;
3449 }
7bbc124e
LV		 3450
3451 xcc->parent_unrealize(dev, &local_err);
3452 if (local_err != NULL) {
3453 error_propagate(errp, local_err);
3454 return;
3455 }
c884776e
IM		 3456}
3457
38e5c119
EH		 3458typedef struct BitProperty {
3459 uint32_t *ptr;
3460 uint32_t mask;
3461} BitProperty;
3462
d7bce999
EB		 3463static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3464 void *opaque, Error **errp)
38e5c119
EH		 3465{
3466 BitProperty *fp = opaque;
3467 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 3468 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3469}
3470
d7bce999
EB		 3471static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3472 void *opaque, Error **errp)
38e5c119
EH		 3473{
3474 DeviceState *dev = DEVICE(obj);
3475 BitProperty *fp = opaque;
3476 Error *local_err = NULL;
3477 bool value;
3478
3479 if (dev->realized) {
3480 qdev_prop_set_after_realize(dev, name, errp);
3481 return;
3482 }
3483
51e72bc1 3484 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3485 if (local_err) {
3486 error_propagate(errp, local_err);
3487 return;
3488 }
3489
3490 if (value) {
3491 *fp->ptr |= fp->mask;
3492 } else {
3493 *fp->ptr &= ~fp->mask;
3494 }
3495}
3496
3497static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3498 void *opaque)
3499{
3500 BitProperty *prop = opaque;
3501 g_free(prop);
3502}
3503
3504/* Register a boolean property to get/set a single bit in a uint32_t field.
3505 *
3506 * The same property name can be registered multiple times to make it affect
3507 * multiple bits in the same FeatureWord. In that case, the getter will return
3508 * true only if all bits are set.
3509 */
3510static void x86_cpu_register_bit_prop(X86CPU *cpu,
3511 const char *prop_name,
3512 uint32_t *field,
3513 int bitnr)
3514{
3515 BitProperty *fp;
3516 ObjectProperty *op;
3517 uint32_t mask = (1UL << bitnr);
3518
3519 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3520 if (op) {
3521 fp = op->opaque;
3522 assert(fp->ptr == field);
3523 fp->mask |= mask;
3524 } else {
3525 fp = g_new0(BitProperty, 1);
3526 fp->ptr = field;
3527 fp->mask = mask;
3528 object_property_add(OBJECT(cpu), prop_name, "bool",
3529 x86_cpu_get_bit_prop,
3530 x86_cpu_set_bit_prop,
3531 x86_cpu_release_bit_prop, fp, &error_abort);
3532 }
3533}
3534
3535static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3536 FeatureWord w,
3537 int bitnr)
3538{
38e5c119 3539 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 3540 const char *name = fi->feat_names[bitnr];
38e5c119 3541
16d2fcaa 3542 if (!name) {
38e5c119
EH		 3543 return;
3544 }
3545
fc7dfd20
EH		 3546 /* Property names should use "-" instead of "_".
3547 * Old names containing underscores are registered as aliases
3548 * using object_property_add_alias()
3549 */
16d2fcaa
EH		 3550 assert(!strchr(name, '_'));
3551 /* aliases don't use "|" delimiters anymore, they are registered
3552 * manually using object_property_add_alias() */
3553 assert(!strchr(name, '|'));
3554 x86_cpu_register_bit_prop(cpu, name, &cpu->env.features[w], bitnr);
38e5c119
EH		 3555}
3556
d187e08d
AN		 3557static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
3558{
3559 X86CPU *cpu = X86_CPU(cs);
3560 CPUX86State *env = &cpu->env;
3561 GuestPanicInformation *panic_info = NULL;
3562
3563 if (env->features[FEAT_HYPERV_EDX] & HV_X64_GUEST_CRASH_MSR_AVAILABLE) {
3564 GuestPanicInformationHyperV *panic_info_hv =
3565 g_malloc0(sizeof(GuestPanicInformationHyperV));
3566 panic_info = g_malloc0(sizeof(GuestPanicInformation));
3567
3568 panic_info->type = GUEST_PANIC_INFORMATION_KIND_HYPER_V;
3569 panic_info->u.hyper_v.data = panic_info_hv;
3570
3571 assert(HV_X64_MSR_CRASH_PARAMS >= 5);
3572 panic_info_hv->arg1 = env->msr_hv_crash_params[0];
3573 panic_info_hv->arg2 = env->msr_hv_crash_params[1];
3574 panic_info_hv->arg3 = env->msr_hv_crash_params[2];
3575 panic_info_hv->arg4 = env->msr_hv_crash_params[3];
3576 panic_info_hv->arg5 = env->msr_hv_crash_params[4];
3577 }
3578
3579 return panic_info;
3580}
3581static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
3582 const char *name, void *opaque,
3583 Error **errp)
3584{
3585 CPUState *cs = CPU(obj);
3586 GuestPanicInformation *panic_info;
3587
3588 if (!cs->crash_occurred) {
3589 error_setg(errp, "No crash occured");
3590 return;
3591 }
3592
3593 panic_info = x86_cpu_get_crash_info(cs);
3594 if (panic_info == NULL) {
3595 error_setg(errp, "No crash information");
3596 return;
3597 }
3598
3599 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
3600 errp);
3601 qapi_free_GuestPanicInformation(panic_info);
3602}
3603
de024815
AF		 3604static void x86_cpu_initfn(Object *obj)
3605{
55e5c285 3606 CPUState *cs = CPU(obj);
de024815 3607 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3608 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3609 CPUX86State *env = &cpu->env;
38e5c119 3610 FeatureWord w;
de024815 3611
c05efcb1 3612 cs->env_ptr = env;
71ad61d3
AF		 3613
3614 object_property_add(obj, "family", "int",
95b8519d 3615 x86_cpuid_version_get_family,
71ad61d3 3616 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3617 object_property_add(obj, "model", "int",
67e30c83 3618 x86_cpuid_version_get_model,
c5291a4f 3619 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3620 object_property_add(obj, "stepping", "int",
35112e41 3621 x86_cpuid_version_get_stepping,
036e2222 3622 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3623 object_property_add_str(obj, "vendor",
3624 x86_cpuid_get_vendor,
3625 x86_cpuid_set_vendor, NULL);
938d4c25 3626 object_property_add_str(obj, "model-id",
63e886eb 3627 x86_cpuid_get_model_id,
938d4c25 3628 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3629 object_property_add(obj, "tsc-frequency", "int",
3630 x86_cpuid_get_tsc_freq,
3631 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 3632 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3633 x86_cpu_get_feature_words,
7e5292b5
EH		 3634 NULL, NULL, (void *)env->features, NULL);
3635 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3636 x86_cpu_get_feature_words,
3637 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3638
d187e08d
AN		 3639 object_property_add(obj, "crash-information", "GuestPanicInformation",
3640 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
3641
92067bf4 3642 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3643
38e5c119
EH		 3644 for (w = 0; w < FEATURE_WORDS; w++) {
3645 int bitnr;
3646
3647 for (bitnr = 0; bitnr < 32; bitnr++) {
3648 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3649 }
3650 }
3651
16d2fcaa
EH		 3652 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
3653 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
3654 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
3655 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
3656 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
3657 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
3658 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
3659
54b8dc7c
EH		 3660 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
3661 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
3662 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
3663 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
3664 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
3665 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
3666 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
3667 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
3668 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
3669 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
3670 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
3671 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
3672 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
3673 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
3674 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
3675 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
3676 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
3677 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
3678 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
3679 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
3680 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
3681
0bacd8b3
EH		 3682 if (xcc->cpu_def) {
3683 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3684 }
de024815
AF		 3685}
3686
997395d3
IM		 3687static int64_t x86_cpu_get_arch_id(CPUState *cs)
3688{
3689 X86CPU *cpu = X86_CPU(cs);
997395d3 3690
7e72a45c 3691 return cpu->apic_id;
997395d3
IM		 3692}
3693
444d5590
AF		 3694static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3695{
3696 X86CPU *cpu = X86_CPU(cs);
3697
3698 return cpu->env.cr[0] & CR0_PG_MASK;
3699}
3700
f45748f1
AF		 3701static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3702{
3703 X86CPU *cpu = X86_CPU(cs);
3704
3705 cpu->env.eip = value;
3706}
3707
bdf7ae5b
AF		 3708static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3709{
3710 X86CPU *cpu = X86_CPU(cs);
3711
3712 cpu->env.eip = tb->pc - tb->cs_base;
3713}
3714
8c2e1b00
AF		 3715static bool x86_cpu_has_work(CPUState *cs)
3716{
3717 X86CPU *cpu = X86_CPU(cs);
3718 CPUX86State *env = &cpu->env;
3719
6220e900
PD		 3720 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3721 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3722 (env->eflags & IF_MASK)) ||
3723 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3724 CPU_INTERRUPT_INIT |
3725 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3726 CPU_INTERRUPT_MCE)) ||
3727 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3728 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3729}
3730
9337e3b6 3731static Property x86_cpu_properties[] = {
2da00e31
IM		 3732#ifdef CONFIG_USER_ONLY
3733 /* apic_id = 0 by default for *-user, see commit 9886e834 */
3734 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 3735 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
3736 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
3737 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 3738#else
3739 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 3740 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
3741 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
3742 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 3743#endif
9337e3b6 3744 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3745 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3746 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3747 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3748 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3749 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3750 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3751 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3752 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3753 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3754 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3755 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3756 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3757 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 3758 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 3759 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 3760 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 3761 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
3762 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
3763 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
3764 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
3765 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
3766 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
3767 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 3768 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 3769 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 3770 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 3771 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
0b564e6f 3772 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
9337e3b6
EH		 3773 DEFINE_PROP_END_OF_LIST()
3774};
3775
5fd2087a
AF		 3776static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3777{
3778 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3779 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3780 DeviceClass *dc = DEVICE_CLASS(oc);
3781
3782 xcc->parent_realize = dc->realize;
7bbc124e 3783 xcc->parent_unrealize = dc->unrealize;
2b6f294c 3784 dc->realize = x86_cpu_realizefn;
c884776e 3785 dc->unrealize = x86_cpu_unrealizefn;
9337e3b6 3786 dc->props = x86_cpu_properties;
5fd2087a
AF		 3787
3788 xcc->parent_reset = cc->reset;
3789 cc->reset = x86_cpu_reset;
91b1df8c 3790 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3791
500050d1 3792 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3793 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3794 cc->has_work = x86_cpu_has_work;
97a8ea5a 3795 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3796 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3797 cc->dump_state = x86_cpu_dump_state;
c86f106b 3798 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 3799 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3800 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3801 cc->gdb_read_register = x86_cpu_gdb_read_register;
3802 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3803 cc->get_arch_id = x86_cpu_get_arch_id;
3804 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3805#ifdef CONFIG_USER_ONLY
3806 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3807#else
a23bbfda 3808 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3809 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3810 cc->write_elf64_note = x86_cpu_write_elf64_note;
3811 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3812 cc->write_elf32_note = x86_cpu_write_elf32_note;
3813 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3814 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3815#endif
175cad36
DE		 3816 /* CPU_NB_REGS * 2 = general regs + xmm regs
3817 * 25 = eip, eflags, 6 seg regs, st[0-7], fctrl,...,fop, mxcsr.
3818 */
a0e372f0 3819 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3820#ifndef CONFIG_USER_ONLY
3821 cc->debug_excp_handler = breakpoint_handler;
3822#endif
374e0cd4
RH		 3823 cc->cpu_exec_enter = x86_cpu_exec_enter;
3824 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27 3825
edd12111 3826 dc->cannot_instantiate_with_device_add_yet = false;
5fd2087a
AF		 3827}
3828
3829static const TypeInfo x86_cpu_type_info = {
3830 .name = TYPE_X86_CPU,
3831 .parent = TYPE_CPU,
3832 .instance_size = sizeof(X86CPU),
de024815 3833 .instance_init = x86_cpu_initfn,
d940ee9b 3834 .abstract = true,
5fd2087a
AF		 3835 .class_size = sizeof(X86CPUClass),
3836 .class_init = x86_cpu_common_class_init,
3837};
3838
5adbed30
EH		 3839
3840/* "base" CPU model, used by query-cpu-model-expansion */
3841static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
3842{
3843 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3844
3845 xcc->static_model = true;
3846 xcc->migration_safe = true;
3847 xcc->model_description = "base CPU model type with no features enabled";
3848 xcc->ordering = 8;
3849}
3850
3851static const TypeInfo x86_base_cpu_type_info = {
3852 .name = X86_CPU_TYPE_NAME("base"),
3853 .parent = TYPE_X86_CPU,
3854 .class_init = x86_cpu_base_class_init,
3855};
3856
5fd2087a
AF		 3857static void x86_cpu_register_types(void)
3858{
d940ee9b
EH		 3859 int i;
3860
5fd2087a 3861 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3862 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3863 x86_register_cpudef_type(&builtin_x86_defs[i]);
3864 }
c62f2630 3865 type_register_static(&max_x86_cpu_type_info);
5adbed30 3866 type_register_static(&x86_base_cpu_type_info);
d940ee9b
EH		 3867#ifdef CONFIG_KVM
3868 type_register_static(&host_x86_cpu_type_info);
3869#endif
5fd2087a
AF		 3870}
3871
3872type_init(x86_cpu_register_types)
QEMU mirror