]> git.proxmox.com Git - mirror_qemu.git/blame - target/i386/cpu.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i386/kvm: Blacklist TSX on known broken hosts
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
f99fd7ca
EH		 32#include "qapi/qmp/qstring.h"
33#include "qapi/qmp/qdict.h"
34#include "qapi/qmp/qbool.h"
35#include "qapi/qmp/qint.h"
36#include "qapi/qmp/qfloat.h"
c6dc6f63 37
8e8aba50
EH		 38#include "qapi-types.h"
39#include "qapi-visit.h"
7b1b5d19 40#include "qapi/visitor.h"
f99fd7ca 41#include "qom/qom-qobject.h"
9c17d615 42#include "sysemu/arch_init.h"
71ad61d3 43
b834b508 44#if defined(CONFIG_KVM)
ef8621b1 45#include <linux/kvm_para.h>
b834b508 46#endif
65dee380 47
9c17d615 48#include "sysemu/sysemu.h"
53a89e26 49#include "hw/qdev-properties.h"
5232d00a 50#include "hw/i386/topology.h"
bdeec802 51#ifndef CONFIG_USER_ONLY
2001d0cd 52#include "exec/address-spaces.h"
741da0d3 53#include "hw/hw.h"
0d09e41a 54#include "hw/xen/xen.h"
0d09e41a 55#include "hw/i386/apic_internal.h"
bdeec802
IM		 56#endif
57
5e891bf8
EH		 58
59/* Cache topology CPUID constants: */
60
61/* CPUID Leaf 2 Descriptors */
62
63#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
64#define CPUID_2_L1I_32KB_8WAY_64B 0x30
65#define CPUID_2_L2_2MB_8WAY_64B 0x7d
14c985cf 66#define CPUID_2_L3_16MB_16WAY_64B 0x4d
5e891bf8
EH		 67
68
69/* CPUID Leaf 4 constants: */
70
71/* EAX: */
72#define CPUID_4_TYPE_DCACHE 1
73#define CPUID_4_TYPE_ICACHE 2
74#define CPUID_4_TYPE_UNIFIED 3
75
76#define CPUID_4_LEVEL(l) ((l) << 5)
77
78#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
79#define CPUID_4_FULLY_ASSOC (1 << 9)
80
81/* EDX: */
82#define CPUID_4_NO_INVD_SHARING (1 << 0)
83#define CPUID_4_INCLUSIVE (1 << 1)
84#define CPUID_4_COMPLEX_IDX (1 << 2)
85
86#define ASSOC_FULL 0xFF
87
88/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
89#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
90 a == 2 ? 0x2 : \
91 a == 4 ? 0x4 : \
92 a == 8 ? 0x6 : \
93 a == 16 ? 0x8 : \
94 a == 32 ? 0xA : \
95 a == 48 ? 0xB : \
96 a == 64 ? 0xC : \
97 a == 96 ? 0xD : \
98 a == 128 ? 0xE : \
99 a == ASSOC_FULL ? 0xF : \
100 0 /* invalid value */)
101
102
103/* Definitions of the hardcoded cache entries we expose: */
104
105/* L1 data cache: */
106#define L1D_LINE_SIZE 64
107#define L1D_ASSOCIATIVITY 8
108#define L1D_SETS 64
109#define L1D_PARTITIONS 1
110/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
111#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
112/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
113#define L1D_LINES_PER_TAG 1
114#define L1D_SIZE_KB_AMD 64
115#define L1D_ASSOCIATIVITY_AMD 2
116
117/* L1 instruction cache: */
118#define L1I_LINE_SIZE 64
119#define L1I_ASSOCIATIVITY 8
120#define L1I_SETS 64
121#define L1I_PARTITIONS 1
122/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
123#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
124/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
125#define L1I_LINES_PER_TAG 1
126#define L1I_SIZE_KB_AMD 64
127#define L1I_ASSOCIATIVITY_AMD 2
128
129/* Level 2 unified cache: */
130#define L2_LINE_SIZE 64
131#define L2_ASSOCIATIVITY 16
132#define L2_SETS 4096
133#define L2_PARTITIONS 1
134/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
135/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
136#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
137/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
138#define L2_LINES_PER_TAG 1
139#define L2_SIZE_KB_AMD 512
140
14c985cf 141/* Level 3 unified cache: */
5e891bf8
EH		 142#define L3_SIZE_KB 0 /* disabled */
143#define L3_ASSOCIATIVITY 0 /* disabled */
144#define L3_LINES_PER_TAG 0 /* disabled */
145#define L3_LINE_SIZE 0 /* disabled */
14c985cf
LM		 146#define L3_N_LINE_SIZE 64
147#define L3_N_ASSOCIATIVITY 16
148#define L3_N_SETS 16384
149#define L3_N_PARTITIONS 1
150#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
151#define L3_N_LINES_PER_TAG 1
152#define L3_N_SIZE_KB_AMD 16384
5e891bf8
EH		 153
154/* TLB definitions: */
155
156#define L1_DTLB_2M_ASSOC 1
157#define L1_DTLB_2M_ENTRIES 255
158#define L1_DTLB_4K_ASSOC 1
159#define L1_DTLB_4K_ENTRIES 255
160
161#define L1_ITLB_2M_ASSOC 1
162#define L1_ITLB_2M_ENTRIES 255
163#define L1_ITLB_4K_ASSOC 1
164#define L1_ITLB_4K_ENTRIES 255
165
166#define L2_DTLB_2M_ASSOC 0 /* disabled */
167#define L2_DTLB_2M_ENTRIES 0 /* disabled */
168#define L2_DTLB_4K_ASSOC 4
169#define L2_DTLB_4K_ENTRIES 512
170
171#define L2_ITLB_2M_ASSOC 0 /* disabled */
172#define L2_ITLB_2M_ENTRIES 0 /* disabled */
173#define L2_ITLB_4K_ASSOC 4
174#define L2_ITLB_4K_ENTRIES 512
175
176
177
99b88a17
IM		 178static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
179 uint32_t vendor2, uint32_t vendor3)
180{
181 int i;
182 for (i = 0; i < 4; i++) {
183 dst[i] = vendor1 >> (8 * i);
184 dst[i + 4] = vendor2 >> (8 * i);
185 dst[i + 8] = vendor3 >> (8 * i);
186 }
187 dst[CPUID_VENDOR_SZ] = '\0';
188}
189
621626ce
EH		 190#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
191#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
192 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
193#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
194 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
195 CPUID_PSE36 | CPUID_FXSR)
196#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
197#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
198 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
199 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
200 CPUID_PAE | CPUID_SEP | CPUID_APIC)
201
202#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
203 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
204 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
205 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 206 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 207 /* partly implemented:
208 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
209 /* missing:
210 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
211#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
212 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
213 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 214 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 215 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
216 /* missing:
217 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
218 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
219 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 220 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
221 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 222
223#ifdef TARGET_X86_64
224#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
225#else
226#define TCG_EXT2_X86_64_FEATURES 0
227#endif
228
229#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
230 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
231 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
232 TCG_EXT2_X86_64_FEATURES)
233#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
234 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
235#define TCG_EXT4_FEATURES 0
236#define TCG_SVM_FEATURES 0
237#define TCG_KVM_FEATURES 0
238#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 239 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
240 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 241 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
242 CPUID_7_0_EBX_ERMS)
621626ce 243 /* missing:
07929f2a 244 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 245 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 246 CPUID_7_0_EBX_RDSEED */
6c7c3c21
KS		 247#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
248 CPUID_7_0_ECX_LA57)
95ea69fb 249#define TCG_7_0_EDX_FEATURES 0
303752a9 250#define TCG_APM_FEATURES 0
28b8e4d0 251#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 252#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
253 /* missing:
254 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 255
5ef57876 256typedef struct FeatureWordInfo {
2d5312da
EH		 257 /* feature flags names are taken from "Intel Processor Identification and
258 * the CPUID Instruction" and AMD's "CPUID Specification".
259 * In cases of disagreement between feature naming conventions,
260 * aliases may be added.
261 */
262 const char *feat_names[32];
04d104b6
EH		 263 uint32_t cpuid_eax; /* Input EAX for CPUID */
264 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
265 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
266 int cpuid_reg; /* output register (R_* constant) */
37ce3522 267 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 268 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 269 uint32_t migratable_flags; /* Feature flags known to be migratable */
5ef57876
EH		 270} FeatureWordInfo;
271
272static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 273 [FEAT_1_EDX] = {
2d5312da
EH		 274 .feat_names = {
275 "fpu", "vme", "de", "pse",
276 "tsc", "msr", "pae", "mce",
277 "cx8", "apic", NULL, "sep",
278 "mtrr", "pge", "mca", "cmov",
279 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
280 NULL, "ds" /* Intel dts */, "acpi", "mmx",
281 "fxsr", "sse", "sse2", "ss",
282 "ht" /* Intel htt */, "tm", "ia64", "pbe",
283 },
bffd67b0 284 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 285 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 286 },
287 [FEAT_1_ECX] = {
2d5312da 288 .feat_names = {
16d2fcaa 289 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 290 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 291 "tm2", "ssse3", "cid", NULL,
292 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 293 NULL, "pcid", "dca", "sse4.1",
294 "sse4.2", "x2apic", "movbe", "popcnt",
2d5312da
EH		 295 "tsc-deadline", "aes", "xsave", "osxsave",
296 "avx", "f16c", "rdrand", "hypervisor",
297 },
bffd67b0 298 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 299 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 300 },
2d5312da
EH		 301 /* Feature names that are already defined on feature_name[] but
302 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
303 * names on feat_names below. They are copied automatically
304 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
305 */
bffd67b0 306 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 307 .feat_names = {
308 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
309 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
310 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
311 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
312 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 313 "nx", NULL, "mmxext", NULL /* mmx */,
314 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
315 NULL, "lm", "3dnowext", "3dnow",
2d5312da 316 },
bffd67b0 317 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 318 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 319 },
320 [FEAT_8000_0001_ECX] = {
2d5312da 321 .feat_names = {
fc7dfd20 322 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 323 "cr8legacy", "abm", "sse4a", "misalignsse",
324 "3dnowprefetch", "osvw", "ibs", "xop",
325 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 326 "fma4", "tce", NULL, "nodeid-msr",
327 NULL, "tbm", "topoext", "perfctr-core",
328 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 329 NULL, NULL, NULL, NULL,
330 },
bffd67b0 331 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 332 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 333 },
89e49c8b 334 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 335 .feat_names = {
336 NULL, NULL, "xstore", "xstore-en",
337 NULL, NULL, "xcrypt", "xcrypt-en",
338 "ace2", "ace2-en", "phe", "phe-en",
339 "pmm", "pmm-en", NULL, NULL,
340 NULL, NULL, NULL, NULL,
341 NULL, NULL, NULL, NULL,
342 NULL, NULL, NULL, NULL,
343 NULL, NULL, NULL, NULL,
344 },
89e49c8b 345 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 346 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 347 },
bffd67b0 348 [FEAT_KVM] = {
2d5312da 349 .feat_names = {
fc7dfd20
EH		 350 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
351 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
2d5312da
EH		 352 NULL, NULL, NULL, NULL,
353 NULL, NULL, NULL, NULL,
354 NULL, NULL, NULL, NULL,
355 NULL, NULL, NULL, NULL,
356 "kvmclock-stable-bit", NULL, NULL, NULL,
357 NULL, NULL, NULL, NULL,
358 },
bffd67b0 359 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 360 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 361 },
c35bd19a 362 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 363 .feat_names = {
364 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
365 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
366 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
367 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
368 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
369 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
370 NULL, NULL, NULL, NULL,
371 NULL, NULL, NULL, NULL,
372 NULL, NULL, NULL, NULL,
373 NULL, NULL, NULL, NULL,
374 NULL, NULL, NULL, NULL,
375 },
c35bd19a
EY		 376 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
377 },
378 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 379 .feat_names = {
380 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
381 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
382 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
383 NULL /* hv_create_port */, NULL /* hv_connect_port */,
384 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
385 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
386 NULL, NULL,
387 NULL, NULL, NULL, NULL,
388 NULL, NULL, NULL, NULL,
389 NULL, NULL, NULL, NULL,
390 NULL, NULL, NULL, NULL,
391 },
c35bd19a
EY		 392 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
393 },
394 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 395 .feat_names = {
396 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
397 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
398 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
399 NULL, NULL,
400 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
401 NULL, NULL, NULL, NULL,
402 NULL, NULL, NULL, NULL,
403 NULL, NULL, NULL, NULL,
404 NULL, NULL, NULL, NULL,
405 NULL, NULL, NULL, NULL,
406 },
c35bd19a
EY		 407 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
408 },
bffd67b0 409 [FEAT_SVM] = {
2d5312da 410 .feat_names = {
fc7dfd20
EH		 411 "npt", "lbrv", "svm-lock", "nrip-save",
412 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
413 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 414 "pfthreshold", NULL, NULL, NULL,
415 NULL, NULL, NULL, NULL,
416 NULL, NULL, NULL, NULL,
417 NULL, NULL, NULL, NULL,
418 NULL, NULL, NULL, NULL,
419 },
bffd67b0 420 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 421 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 422 },
423 [FEAT_7_0_EBX] = {
2d5312da 424 .feat_names = {
fc7dfd20 425 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 426 "hle", "avx2", NULL, "smep",
427 "bmi2", "erms", "invpcid", "rtm",
428 NULL, NULL, "mpx", NULL,
429 "avx512f", "avx512dq", "rdseed", "adx",
430 "smap", "avx512ifma", "pcommit", "clflushopt",
431 "clwb", NULL, "avx512pf", "avx512er",
638cbd45 432 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 433 },
04d104b6
EH		 434 .cpuid_eax = 7,
435 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
436 .cpuid_reg = R_EBX,
37ce3522 437 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 438 },
f74eefe0 439 [FEAT_7_0_ECX] = {
2d5312da
EH		 440 .feat_names = {
441 NULL, "avx512vbmi", "umip", "pku",
442 "ospke", NULL, NULL, NULL,
443 NULL, NULL, NULL, NULL,
f7754377 444 NULL, NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 445 "la57", NULL, NULL, NULL,
2d5312da
EH		 446 NULL, NULL, "rdpid", NULL,
447 NULL, NULL, NULL, NULL,
448 NULL, NULL, NULL, NULL,
449 },
f74eefe0
HH		 450 .cpuid_eax = 7,
451 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
452 .cpuid_reg = R_ECX,
453 .tcg_features = TCG_7_0_ECX_FEATURES,
454 },
95ea69fb
LK		 455 [FEAT_7_0_EDX] = {
456 .feat_names = {
457 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
458 NULL, NULL, NULL, NULL,
459 NULL, NULL, NULL, NULL,
460 NULL, NULL, NULL, NULL,
461 NULL, NULL, NULL, NULL,
462 NULL, NULL, NULL, NULL,
463 NULL, NULL, NULL, NULL,
464 NULL, NULL, NULL, NULL,
465 },
466 .cpuid_eax = 7,
467 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
468 .cpuid_reg = R_EDX,
469 .tcg_features = TCG_7_0_EDX_FEATURES,
470 },
303752a9 471 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 472 .feat_names = {
473 NULL, NULL, NULL, NULL,
474 NULL, NULL, NULL, NULL,
475 "invtsc", NULL, NULL, NULL,
476 NULL, NULL, NULL, NULL,
477 NULL, NULL, NULL, NULL,
478 NULL, NULL, NULL, NULL,
479 NULL, NULL, NULL, NULL,
480 NULL, NULL, NULL, NULL,
481 },
303752a9
MT		 482 .cpuid_eax = 0x80000007,
483 .cpuid_reg = R_EDX,
484 .tcg_features = TCG_APM_FEATURES,
485 .unmigratable_flags = CPUID_APM_INVTSC,
486 },
0bb0b2d2 487 [FEAT_XSAVE] = {
2d5312da
EH		 488 .feat_names = {
489 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
490 NULL, NULL, NULL, NULL,
491 NULL, NULL, NULL, NULL,
492 NULL, NULL, NULL, NULL,
493 NULL, NULL, NULL, NULL,
494 NULL, NULL, NULL, NULL,
495 NULL, NULL, NULL, NULL,
496 NULL, NULL, NULL, NULL,
497 },
0bb0b2d2
PB		 498 .cpuid_eax = 0xd,
499 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
500 .cpuid_reg = R_EAX,
c9cfe8f9 501 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 502 },
28b8e4d0 503 [FEAT_6_EAX] = {
2d5312da
EH		 504 .feat_names = {
505 NULL, NULL, "arat", NULL,
506 NULL, NULL, NULL, NULL,
507 NULL, NULL, NULL, NULL,
508 NULL, NULL, NULL, NULL,
509 NULL, NULL, NULL, NULL,
510 NULL, NULL, NULL, NULL,
511 NULL, NULL, NULL, NULL,
512 NULL, NULL, NULL, NULL,
513 },
28b8e4d0
JK		 514 .cpuid_eax = 6, .cpuid_reg = R_EAX,
515 .tcg_features = TCG_6_EAX_FEATURES,
516 },
96193c22
EH		 517 [FEAT_XSAVE_COMP_LO] = {
518 .cpuid_eax = 0xD,
519 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
520 .cpuid_reg = R_EAX,
521 .tcg_features = ~0U,
6fb2fff7
EH		 522 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
523 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
524 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
525 XSTATE_PKRU_MASK,
96193c22
EH		 526 },
527 [FEAT_XSAVE_COMP_HI] = {
528 .cpuid_eax = 0xD,
529 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
530 .cpuid_reg = R_EDX,
531 .tcg_features = ~0U,
532 },
5ef57876
EH		 533};
534
8e8aba50
EH		 535typedef struct X86RegisterInfo32 {
536 /* Name of register */
537 const char *name;
538 /* QAPI enum value register */
539 X86CPURegister32 qapi_enum;
540} X86RegisterInfo32;
541
542#define REGISTER(reg) \
5d371f41 543 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 544static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 545 REGISTER(EAX),
546 REGISTER(ECX),
547 REGISTER(EDX),
548 REGISTER(EBX),
549 REGISTER(ESP),
550 REGISTER(EBP),
551 REGISTER(ESI),
552 REGISTER(EDI),
553};
554#undef REGISTER
555
3f32bd21
RH		 556typedef struct ExtSaveArea {
557 uint32_t feature, bits;
558 uint32_t offset, size;
559} ExtSaveArea;
560
561static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 562 [XSTATE_FP_BIT] = {
563 /* x87 FP state component is always enabled if XSAVE is supported */
564 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
565 /* x87 state is in the legacy region of the XSAVE area */
566 .offset = 0,
567 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
568 },
569 [XSTATE_SSE_BIT] = {
570 /* SSE state component is always enabled if XSAVE is supported */
571 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
572 /* SSE state is in the legacy region of the XSAVE area */
573 .offset = 0,
574 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
575 },
cfc3b074
PB		 576 [XSTATE_YMM_BIT] =
577 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 578 .offset = offsetof(X86XSaveArea, avx_state),
579 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 580 [XSTATE_BNDREGS_BIT] =
581 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 582 .offset = offsetof(X86XSaveArea, bndreg_state),
583 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 584 [XSTATE_BNDCSR_BIT] =
585 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 586 .offset = offsetof(X86XSaveArea, bndcsr_state),
587 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 588 [XSTATE_OPMASK_BIT] =
589 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 590 .offset = offsetof(X86XSaveArea, opmask_state),
591 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 592 [XSTATE_ZMM_Hi256_BIT] =
593 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 594 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
595 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 596 [XSTATE_Hi16_ZMM_BIT] =
597 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 598 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
599 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 600 [XSTATE_PKRU_BIT] =
601 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 602 .offset = offsetof(X86XSaveArea, pkru_state),
603 .size = sizeof(XSavePKRU) },
2560f19f 604};
8e8aba50 605
1fda6198
EH		 606static uint32_t xsave_area_size(uint64_t mask)
607{
608 int i;
e3c9022b 609 uint64_t ret = 0;
1fda6198 610
e3c9022b 611 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 612 const ExtSaveArea *esa = &x86_ext_save_areas[i];
613 if ((mask >> i) & 1) {
614 ret = MAX(ret, esa->offset + esa->size);
615 }
616 }
617 return ret;
618}
619
96193c22
EH		 620static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
621{
622 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
623 cpu->env.features[FEAT_XSAVE_COMP_LO];
624}
625
8b4beddc
EH		 626const char *get_register_name_32(unsigned int reg)
627{
31ccdde2 628 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 629 return NULL;
630 }
8e8aba50 631 return x86_reg_info_32[reg].name;
8b4beddc
EH		 632}
633
84f1b92f
EH		 634/*
635 * Returns the set of feature flags that are supported and migratable by
636 * QEMU, for a given FeatureWord.
637 */
638static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
639{
640 FeatureWordInfo *wi = &feature_word_info[w];
641 uint32_t r = 0;
642 int i;
643
644 for (i = 0; i < 32; i++) {
645 uint32_t f = 1U << i;
6fb2fff7
EH		 646
647 /* If the feature name is known, it is implicitly considered migratable,
648 * unless it is explicitly set in unmigratable_flags */
649 if ((wi->migratable_flags & f) ||
650 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
651 r |= f;
84f1b92f 652 }
84f1b92f
EH		 653 }
654 return r;
655}
656
bb44e0d1
JK		 657void host_cpuid(uint32_t function, uint32_t count,
658 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 659{
a1fd24af
AL		 660 uint32_t vec[4];
661
662#ifdef __x86_64__
663 asm volatile("cpuid"
664 : "=a"(vec[0]), "=b"(vec[1]),
665 "=c"(vec[2]), "=d"(vec[3])
666 : "0"(function), "c"(count) : "cc");
c1f41226 667#elif defined(__i386__)
a1fd24af
AL		 668 asm volatile("pusha \n\t"
669 "cpuid \n\t"
670 "mov %%eax, 0(%2) \n\t"
671 "mov %%ebx, 4(%2) \n\t"
672 "mov %%ecx, 8(%2) \n\t"
673 "mov %%edx, 12(%2) \n\t"
674 "popa"
675 : : "a"(function), "c"(count), "S"(vec)
676 : "memory", "cc");
c1f41226
EH		 677#else
678 abort();
a1fd24af
AL		 679#endif
680
bdde476a 681 if (eax)
a1fd24af 682 *eax = vec[0];
bdde476a 683 if (ebx)
a1fd24af 684 *ebx = vec[1];
bdde476a 685 if (ecx)
a1fd24af 686 *ecx = vec[2];
bdde476a 687 if (edx)
a1fd24af 688 *edx = vec[3];
bdde476a 689}
c6dc6f63 690
20271d48
EH		 691void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
692{
693 uint32_t eax, ebx, ecx, edx;
694
695 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
696 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
697
698 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
699 if (family) {
700 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
701 }
702 if (model) {
703 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
704 }
705 if (stepping) {
706 *stepping = eax & 0x0F;
707 }
708}
709
d940ee9b
EH		 710/* CPU class name definitions: */
711
712#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
713#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
714
715/* Return type name for a given CPU model name
716 * Caller is responsible for freeing the returned string.
717 */
718static char *x86_cpu_type_name(const char *model_name)
719{
720 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
721}
722
500050d1
AF		 723static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
724{
d940ee9b
EH		 725 ObjectClass *oc;
726 char *typename;
727
500050d1
AF		 728 if (cpu_model == NULL) {
729 return NULL;
730 }
731
d940ee9b
EH		 732 typename = x86_cpu_type_name(cpu_model);
733 oc = object_class_by_name(typename);
734 g_free(typename);
735 return oc;
500050d1
AF		 736}
737
104494ea
IM		 738static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
739{
740 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
741 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
742 return g_strndup(class_name,
743 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
744}
745
d940ee9b 746struct X86CPUDefinition {
c6dc6f63
AP		 747 const char *name;
748 uint32_t level;
90e4b0c3 749 uint32_t xlevel;
99b88a17
IM		 750 /* vendor is zero-terminated, 12 character ASCII string */
751 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 752 int family;
753 int model;
754 int stepping;
0514ef2f 755 FeatureWordArray features;
c6dc6f63 756 char model_id[48];
d940ee9b 757};
c6dc6f63 758
9576de75 759static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 760 {
761 .name = "qemu64",
3046bb5d 762 .level = 0xd,
99b88a17 763 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 764 .family = 6,
f8e6a11a 765 .model = 6,
c6dc6f63 766 .stepping = 3,
0514ef2f 767 .features[FEAT_1_EDX] =
27861ecc 768 PPRO_FEATURES |
c6dc6f63 769 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 770 CPUID_PSE36,
0514ef2f 771 .features[FEAT_1_ECX] =
6aa91e4a 772 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 773 .features[FEAT_8000_0001_EDX] =
c6dc6f63 774 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 775 .features[FEAT_8000_0001_ECX] =
71195672 776 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 777 .xlevel = 0x8000000A,
9cf2cc3d 778 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 779 },
780 {
781 .name = "phenom",
782 .level = 5,
99b88a17 783 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 784 .family = 16,
785 .model = 2,
786 .stepping = 3,
b9fc20bc 787 /* Missing: CPUID_HT */
0514ef2f 788 .features[FEAT_1_EDX] =
27861ecc 789 PPRO_FEATURES |
c6dc6f63 790 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 791 CPUID_PSE36 | CPUID_VME,
0514ef2f 792 .features[FEAT_1_ECX] =
27861ecc 793 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 794 CPUID_EXT_POPCNT,
0514ef2f 795 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 796 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
797 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 798 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 799 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
800 CPUID_EXT3_CR8LEG,
801 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
802 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 803 .features[FEAT_8000_0001_ECX] =
27861ecc 804 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 805 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 806 /* Missing: CPUID_SVM_LBRV */
0514ef2f 807 .features[FEAT_SVM] =
b9fc20bc 808 CPUID_SVM_NPT,
c6dc6f63
AP		 809 .xlevel = 0x8000001A,
810 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
811 },
812 {
813 .name = "core2duo",
814 .level = 10,
99b88a17 815 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 816 .family = 6,
817 .model = 15,
818 .stepping = 11,
b9fc20bc 819 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 820 .features[FEAT_1_EDX] =
27861ecc 821 PPRO_FEATURES |
c6dc6f63 822 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 823 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
824 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 825 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 826 .features[FEAT_1_ECX] =
27861ecc 827 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 828 CPUID_EXT_CX16,
0514ef2f 829 .features[FEAT_8000_0001_EDX] =
27861ecc 830 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 831 .features[FEAT_8000_0001_ECX] =
27861ecc 832 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 833 .xlevel = 0x80000008,
834 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
835 },
836 {
837 .name = "kvm64",
3046bb5d 838 .level = 0xd,
99b88a17 839 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 840 .family = 15,
841 .model = 6,
842 .stepping = 1,
b3a4f0b1 843 /* Missing: CPUID_HT */
0514ef2f 844 .features[FEAT_1_EDX] =
b3a4f0b1 845 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 846 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
847 CPUID_PSE36,
848 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 849 .features[FEAT_1_ECX] =
27861ecc 850 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 851 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 852 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 853 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
854 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
855 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
856 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
857 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 858 .features[FEAT_8000_0001_ECX] =
27861ecc 859 0,
c6dc6f63
AP		 860 .xlevel = 0x80000008,
861 .model_id = "Common KVM processor"
862 },
c6dc6f63
AP		 863 {
864 .name = "qemu32",
865 .level = 4,
99b88a17 866 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 867 .family = 6,
f8e6a11a 868 .model = 6,
c6dc6f63 869 .stepping = 3,
0514ef2f 870 .features[FEAT_1_EDX] =
27861ecc 871 PPRO_FEATURES,
0514ef2f 872 .features[FEAT_1_ECX] =
6aa91e4a 873 CPUID_EXT_SSE3,
58012d66 874 .xlevel = 0x80000004,
9cf2cc3d 875 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 876 },
eafaf1e5
AP		 877 {
878 .name = "kvm32",
879 .level = 5,
99b88a17 880 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 881 .family = 15,
882 .model = 6,
883 .stepping = 1,
0514ef2f 884 .features[FEAT_1_EDX] =
b3a4f0b1 885 PPRO_FEATURES | CPUID_VME |
eafaf1e5 886 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 887 .features[FEAT_1_ECX] =
27861ecc 888 CPUID_EXT_SSE3,
0514ef2f 889 .features[FEAT_8000_0001_ECX] =
27861ecc 890 0,
eafaf1e5
AP		 891 .xlevel = 0x80000008,
892 .model_id = "Common 32-bit KVM processor"
893 },
c6dc6f63
AP		 894 {
895 .name = "coreduo",
896 .level = 10,
99b88a17 897 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 898 .family = 6,
899 .model = 14,
900 .stepping = 8,
b9fc20bc 901 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 902 .features[FEAT_1_EDX] =
27861ecc 903 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 904 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
905 CPUID_SS,
906 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 907 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 908 .features[FEAT_1_ECX] =
e93abc14 909 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 910 .features[FEAT_8000_0001_EDX] =
27861ecc 911 CPUID_EXT2_NX,
c6dc6f63
AP		 912 .xlevel = 0x80000008,
913 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
914 },
915 {
916 .name = "486",
58012d66 917 .level = 1,
99b88a17 918 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 919 .family = 4,
b2a856d9 920 .model = 8,
c6dc6f63 921 .stepping = 0,
0514ef2f 922 .features[FEAT_1_EDX] =
27861ecc 923 I486_FEATURES,
c6dc6f63
AP		 924 .xlevel = 0,
925 },
926 {
927 .name = "pentium",
928 .level = 1,
99b88a17 929 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 930 .family = 5,
931 .model = 4,
932 .stepping = 3,
0514ef2f 933 .features[FEAT_1_EDX] =
27861ecc 934 PENTIUM_FEATURES,
c6dc6f63
AP		 935 .xlevel = 0,
936 },
937 {
938 .name = "pentium2",
939 .level = 2,
99b88a17 940 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 941 .family = 6,
942 .model = 5,
943 .stepping = 2,
0514ef2f 944 .features[FEAT_1_EDX] =
27861ecc 945 PENTIUM2_FEATURES,
c6dc6f63
AP		 946 .xlevel = 0,
947 },
948 {
949 .name = "pentium3",
3046bb5d 950 .level = 3,
99b88a17 951 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 952 .family = 6,
953 .model = 7,
954 .stepping = 3,
0514ef2f 955 .features[FEAT_1_EDX] =
27861ecc 956 PENTIUM3_FEATURES,
c6dc6f63
AP		 957 .xlevel = 0,
958 },
959 {
960 .name = "athlon",
961 .level = 2,
99b88a17 962 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 963 .family = 6,
964 .model = 2,
965 .stepping = 3,
0514ef2f 966 .features[FEAT_1_EDX] =
27861ecc 967 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 968 CPUID_MCA,
0514ef2f 969 .features[FEAT_8000_0001_EDX] =
60032ac0 970 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 971 .xlevel = 0x80000008,
9cf2cc3d 972 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 973 },
974 {
975 .name = "n270",
3046bb5d 976 .level = 10,
99b88a17 977 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 978 .family = 6,
979 .model = 28,
980 .stepping = 2,
b9fc20bc 981 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 982 .features[FEAT_1_EDX] =
27861ecc 983 PPRO_FEATURES |
b9fc20bc
EH		 984 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
985 CPUID_ACPI | CPUID_SS,
c6dc6f63 986 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 987 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
988 * CPUID_EXT_XTPR */
0514ef2f 989 .features[FEAT_1_ECX] =
27861ecc 990 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 991 CPUID_EXT_MOVBE,
0514ef2f 992 .features[FEAT_8000_0001_EDX] =
60032ac0 993 CPUID_EXT2_NX,
0514ef2f 994 .features[FEAT_8000_0001_ECX] =
27861ecc 995 CPUID_EXT3_LAHF_LM,
3046bb5d 996 .xlevel = 0x80000008,
c6dc6f63
AP		 997 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
998 },
3eca4642
EH		 999 {
1000 .name = "Conroe",
3046bb5d 1001 .level = 10,
99b88a17 1002 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1003 .family = 6,
ffce9ebb 1004 .model = 15,
3eca4642 1005 .stepping = 3,
0514ef2f 1006 .features[FEAT_1_EDX] =
b3a4f0b1 1007 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1008 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1009 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1010 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1011 CPUID_DE | CPUID_FP87,
0514ef2f 1012 .features[FEAT_1_ECX] =
27861ecc 1013 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1014 .features[FEAT_8000_0001_EDX] =
27861ecc 1015 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1016 .features[FEAT_8000_0001_ECX] =
27861ecc 1017 CPUID_EXT3_LAHF_LM,
3046bb5d 1018 .xlevel = 0x80000008,
3eca4642
EH		 1019 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1020 },
1021 {
1022 .name = "Penryn",
3046bb5d 1023 .level = 10,
99b88a17 1024 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1025 .family = 6,
ffce9ebb 1026 .model = 23,
3eca4642 1027 .stepping = 3,
0514ef2f 1028 .features[FEAT_1_EDX] =
b3a4f0b1 1029 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1030 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1031 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1032 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1033 CPUID_DE | CPUID_FP87,
0514ef2f 1034 .features[FEAT_1_ECX] =
27861ecc 1035 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1036 CPUID_EXT_SSE3,
0514ef2f 1037 .features[FEAT_8000_0001_EDX] =
27861ecc 1038 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1039 .features[FEAT_8000_0001_ECX] =
27861ecc 1040 CPUID_EXT3_LAHF_LM,
3046bb5d 1041 .xlevel = 0x80000008,
3eca4642
EH		 1042 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1043 },
1044 {
1045 .name = "Nehalem",
3046bb5d 1046 .level = 11,
99b88a17 1047 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1048 .family = 6,
ffce9ebb 1049 .model = 26,
3eca4642 1050 .stepping = 3,
0514ef2f 1051 .features[FEAT_1_EDX] =
b3a4f0b1 1052 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1053 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1054 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1055 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1056 CPUID_DE | CPUID_FP87,
0514ef2f 1057 .features[FEAT_1_ECX] =
27861ecc 1058 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1059 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1060 .features[FEAT_8000_0001_EDX] =
27861ecc 1061 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1062 .features[FEAT_8000_0001_ECX] =
27861ecc 1063 CPUID_EXT3_LAHF_LM,
3046bb5d 1064 .xlevel = 0x80000008,
3eca4642
EH		 1065 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1066 },
1067 {
1068 .name = "Westmere",
1069 .level = 11,
99b88a17 1070 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1071 .family = 6,
1072 .model = 44,
1073 .stepping = 1,
0514ef2f 1074 .features[FEAT_1_EDX] =
b3a4f0b1 1075 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1076 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1077 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1078 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1079 CPUID_DE | CPUID_FP87,
0514ef2f 1080 .features[FEAT_1_ECX] =
27861ecc 1081 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1082 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1083 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1084 .features[FEAT_8000_0001_EDX] =
27861ecc 1085 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1086 .features[FEAT_8000_0001_ECX] =
27861ecc 1087 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1088 .features[FEAT_6_EAX] =
1089 CPUID_6_EAX_ARAT,
3046bb5d 1090 .xlevel = 0x80000008,
3eca4642
EH		 1091 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1092 },
1093 {
1094 .name = "SandyBridge",
1095 .level = 0xd,
99b88a17 1096 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1097 .family = 6,
1098 .model = 42,
1099 .stepping = 1,
0514ef2f 1100 .features[FEAT_1_EDX] =
b3a4f0b1 1101 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1102 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1103 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1104 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1105 CPUID_DE | CPUID_FP87,
0514ef2f 1106 .features[FEAT_1_ECX] =
27861ecc 1107 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1108 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1109 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1110 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1111 CPUID_EXT_SSE3,
0514ef2f 1112 .features[FEAT_8000_0001_EDX] =
27861ecc 1113 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1114 CPUID_EXT2_SYSCALL,
0514ef2f 1115 .features[FEAT_8000_0001_ECX] =
27861ecc 1116 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1117 .features[FEAT_XSAVE] =
1118 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1119 .features[FEAT_6_EAX] =
1120 CPUID_6_EAX_ARAT,
3046bb5d 1121 .xlevel = 0x80000008,
3eca4642
EH		 1122 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1123 },
2f9ac42a
PB		 1124 {
1125 .name = "IvyBridge",
1126 .level = 0xd,
1127 .vendor = CPUID_VENDOR_INTEL,
1128 .family = 6,
1129 .model = 58,
1130 .stepping = 9,
1131 .features[FEAT_1_EDX] =
1132 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1133 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1134 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1135 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1136 CPUID_DE | CPUID_FP87,
1137 .features[FEAT_1_ECX] =
1138 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1139 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1140 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1141 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1142 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1143 .features[FEAT_7_0_EBX] =
1144 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1145 CPUID_7_0_EBX_ERMS,
1146 .features[FEAT_8000_0001_EDX] =
1147 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1148 CPUID_EXT2_SYSCALL,
1149 .features[FEAT_8000_0001_ECX] =
1150 CPUID_EXT3_LAHF_LM,
1151 .features[FEAT_XSAVE] =
1152 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1153 .features[FEAT_6_EAX] =
1154 CPUID_6_EAX_ARAT,
3046bb5d 1155 .xlevel = 0x80000008,
2f9ac42a
PB		 1156 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1157 },
37507094 1158 {
a356850b
EH		 1159 .name = "Haswell-noTSX",
1160 .level = 0xd,
1161 .vendor = CPUID_VENDOR_INTEL,
1162 .family = 6,
1163 .model = 60,
1164 .stepping = 1,
1165 .features[FEAT_1_EDX] =
1166 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1167 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1168 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1169 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1170 CPUID_DE | CPUID_FP87,
1171 .features[FEAT_1_ECX] =
1172 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1173 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1174 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1175 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1176 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1177 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1178 .features[FEAT_8000_0001_EDX] =
1179 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1180 CPUID_EXT2_SYSCALL,
1181 .features[FEAT_8000_0001_ECX] =
becb6667 1182 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1183 .features[FEAT_7_0_EBX] =
1184 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1185 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1186 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1187 .features[FEAT_XSAVE] =
1188 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1189 .features[FEAT_6_EAX] =
1190 CPUID_6_EAX_ARAT,
3046bb5d 1191 .xlevel = 0x80000008,
a356850b
EH		 1192 .model_id = "Intel Core Processor (Haswell, no TSX)",
1193 }, {
37507094
EH		 1194 .name = "Haswell",
1195 .level = 0xd,
99b88a17 1196 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1197 .family = 6,
1198 .model = 60,
1199 .stepping = 1,
0514ef2f 1200 .features[FEAT_1_EDX] =
b3a4f0b1 1201 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1202 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1203 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1204 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1205 CPUID_DE | CPUID_FP87,
0514ef2f 1206 .features[FEAT_1_ECX] =
27861ecc 1207 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1208 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1209 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1210 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1211 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1212 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1213 .features[FEAT_8000_0001_EDX] =
27861ecc 1214 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1215 CPUID_EXT2_SYSCALL,
0514ef2f 1216 .features[FEAT_8000_0001_ECX] =
becb6667 1217 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1218 .features[FEAT_7_0_EBX] =
27861ecc 1219 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1220 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1221 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1222 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1223 .features[FEAT_XSAVE] =
1224 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1225 .features[FEAT_6_EAX] =
1226 CPUID_6_EAX_ARAT,
3046bb5d 1227 .xlevel = 0x80000008,
37507094
EH		 1228 .model_id = "Intel Core Processor (Haswell)",
1229 },
a356850b
EH		 1230 {
1231 .name = "Broadwell-noTSX",
1232 .level = 0xd,
1233 .vendor = CPUID_VENDOR_INTEL,
1234 .family = 6,
1235 .model = 61,
1236 .stepping = 2,
1237 .features[FEAT_1_EDX] =
1238 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1239 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1240 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1241 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1242 CPUID_DE | CPUID_FP87,
1243 .features[FEAT_1_ECX] =
1244 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1245 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1246 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1247 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1248 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1249 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1250 .features[FEAT_8000_0001_EDX] =
1251 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1252 CPUID_EXT2_SYSCALL,
1253 .features[FEAT_8000_0001_ECX] =
becb6667 1254 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1255 .features[FEAT_7_0_EBX] =
1256 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1257 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1258 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1259 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1260 CPUID_7_0_EBX_SMAP,
1261 .features[FEAT_XSAVE] =
1262 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1263 .features[FEAT_6_EAX] =
1264 CPUID_6_EAX_ARAT,
3046bb5d 1265 .xlevel = 0x80000008,
a356850b
EH		 1266 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1267 },
ece01354
EH		 1268 {
1269 .name = "Broadwell",
1270 .level = 0xd,
1271 .vendor = CPUID_VENDOR_INTEL,
1272 .family = 6,
1273 .model = 61,
1274 .stepping = 2,
1275 .features[FEAT_1_EDX] =
b3a4f0b1 1276 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1277 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1278 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1279 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1280 CPUID_DE | CPUID_FP87,
1281 .features[FEAT_1_ECX] =
1282 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1283 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1284 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1285 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1286 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1287 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1288 .features[FEAT_8000_0001_EDX] =
1289 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1290 CPUID_EXT2_SYSCALL,
1291 .features[FEAT_8000_0001_ECX] =
becb6667 1292 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1293 .features[FEAT_7_0_EBX] =
1294 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1295 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1296 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1297 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1298 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1299 .features[FEAT_XSAVE] =
1300 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1301 .features[FEAT_6_EAX] =
1302 CPUID_6_EAX_ARAT,
3046bb5d 1303 .xlevel = 0x80000008,
ece01354
EH		 1304 .model_id = "Intel Core Processor (Broadwell)",
1305 },
f6f949e9
EH		 1306 {
1307 .name = "Skylake-Client",
1308 .level = 0xd,
1309 .vendor = CPUID_VENDOR_INTEL,
1310 .family = 6,
1311 .model = 94,
1312 .stepping = 3,
1313 .features[FEAT_1_EDX] =
1314 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1315 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1316 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1317 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1318 CPUID_DE | CPUID_FP87,
1319 .features[FEAT_1_ECX] =
1320 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1321 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1322 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1323 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1324 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1325 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1326 .features[FEAT_8000_0001_EDX] =
1327 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1328 CPUID_EXT2_SYSCALL,
1329 .features[FEAT_8000_0001_ECX] =
1330 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1331 .features[FEAT_7_0_EBX] =
1332 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1333 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1334 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1335 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1336 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1337 /* Missing: XSAVES (not supported by some Linux versions,
1338 * including v4.1 to v4.6).
1339 * KVM doesn't yet expose any XSAVES state save component,
1340 * and the only one defined in Skylake (processor tracing)
1341 * probably will block migration anyway.
1342 */
1343 .features[FEAT_XSAVE] =
1344 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1345 CPUID_XSAVE_XGETBV1,
1346 .features[FEAT_6_EAX] =
1347 CPUID_6_EAX_ARAT,
1348 .xlevel = 0x80000008,
1349 .model_id = "Intel Core Processor (Skylake)",
1350 },
3eca4642
EH		 1351 {
1352 .name = "Opteron_G1",
1353 .level = 5,
99b88a17 1354 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1355 .family = 15,
1356 .model = 6,
1357 .stepping = 1,
0514ef2f 1358 .features[FEAT_1_EDX] =
b3a4f0b1 1359 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1360 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1361 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1362 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1363 CPUID_DE | CPUID_FP87,
0514ef2f 1364 .features[FEAT_1_ECX] =
27861ecc 1365 CPUID_EXT_SSE3,
0514ef2f 1366 .features[FEAT_8000_0001_EDX] =
2a923a29 1367 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 1368 .xlevel = 0x80000008,
1369 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1370 },
1371 {
1372 .name = "Opteron_G2",
1373 .level = 5,
99b88a17 1374 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1375 .family = 15,
1376 .model = 6,
1377 .stepping = 1,
0514ef2f 1378 .features[FEAT_1_EDX] =
b3a4f0b1 1379 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1380 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1381 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1382 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1383 CPUID_DE | CPUID_FP87,
0514ef2f 1384 .features[FEAT_1_ECX] =
27861ecc 1385 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1386 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1387 .features[FEAT_8000_0001_EDX] =
2a923a29 1388 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1389 .features[FEAT_8000_0001_ECX] =
27861ecc 1390 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1391 .xlevel = 0x80000008,
1392 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1393 },
1394 {
1395 .name = "Opteron_G3",
1396 .level = 5,
99b88a17 1397 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 1398 .family = 16,
1399 .model = 2,
1400 .stepping = 3,
0514ef2f 1401 .features[FEAT_1_EDX] =
b3a4f0b1 1402 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1403 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1404 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1405 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1406 CPUID_DE | CPUID_FP87,
0514ef2f 1407 .features[FEAT_1_ECX] =
27861ecc 1408 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1409 CPUID_EXT_SSE3,
33b5e8c0 1410 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1411 .features[FEAT_8000_0001_EDX] =
2a923a29 1412 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1413 .features[FEAT_8000_0001_ECX] =
27861ecc 1414 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1415 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1416 .xlevel = 0x80000008,
1417 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1418 },
1419 {
1420 .name = "Opteron_G4",
1421 .level = 0xd,
99b88a17 1422 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1423 .family = 21,
1424 .model = 1,
1425 .stepping = 2,
0514ef2f 1426 .features[FEAT_1_EDX] =
b3a4f0b1 1427 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1428 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1429 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1430 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1431 CPUID_DE | CPUID_FP87,
0514ef2f 1432 .features[FEAT_1_ECX] =
27861ecc 1433 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1434 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1435 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1436 CPUID_EXT_SSE3,
33b5e8c0 1437 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1438 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1439 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1440 CPUID_EXT2_SYSCALL,
0514ef2f 1441 .features[FEAT_8000_0001_ECX] =
27861ecc 1442 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1443 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1444 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1445 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1446 /* no xsaveopt! */
3eca4642
EH		 1447 .xlevel = 0x8000001A,
1448 .model_id = "AMD Opteron 62xx class CPU",
1449 },
021941b9
AP		 1450 {
1451 .name = "Opteron_G5",
1452 .level = 0xd,
99b88a17 1453 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1454 .family = 21,
1455 .model = 2,
1456 .stepping = 0,
0514ef2f 1457 .features[FEAT_1_EDX] =
b3a4f0b1 1458 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1459 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1460 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1461 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1462 CPUID_DE | CPUID_FP87,
0514ef2f 1463 .features[FEAT_1_ECX] =
27861ecc 1464 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1465 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1466 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1467 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1468 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1469 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1470 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1471 CPUID_EXT2_SYSCALL,
0514ef2f 1472 .features[FEAT_8000_0001_ECX] =
27861ecc 1473 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1474 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1475 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1476 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1477 /* no xsaveopt! */
021941b9
AP		 1478 .xlevel = 0x8000001A,
1479 .model_id = "AMD Opteron 63xx class CPU",
1480 },
c6dc6f63
AP		 1481};
1482
5114e842
EH		 1483typedef struct PropValue {
1484 const char *prop, *value;
1485} PropValue;
1486
1487/* KVM-specific features that are automatically added/removed
1488 * from all CPU models when KVM is enabled.
1489 */
1490static PropValue kvm_default_props[] = {
1491 { "kvmclock", "on" },
1492 { "kvm-nopiodelay", "on" },
1493 { "kvm-asyncpf", "on" },
1494 { "kvm-steal-time", "on" },
1495 { "kvm-pv-eoi", "on" },
1496 { "kvmclock-stable-bit", "on" },
1497 { "x2apic", "on" },
1498 { "acpi", "off" },
1499 { "monitor", "off" },
1500 { "svm", "off" },
1501 { NULL, NULL },
1502};
1503
04d99c3c
EH		 1504/* TCG-specific defaults that override all CPU models when using TCG
1505 */
1506static PropValue tcg_default_props[] = {
1507 { "vme", "off" },
1508 { NULL, NULL },
1509};
1510
1511
5114e842
EH		 1512void x86_cpu_change_kvm_default(const char *prop, const char *value)
1513{
1514 PropValue *pv;
1515 for (pv = kvm_default_props; pv->prop; pv++) {
1516 if (!strcmp(pv->prop, prop)) {
1517 pv->value = value;
1518 break;
1519 }
1520 }
1521
1522 /* It is valid to call this function only for properties that
1523 * are already present in the kvm_default_props table.
1524 */
1525 assert(pv->prop);
1526}
1527
4d1b279b
EH		 1528static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1529 bool migratable_only);
1530
40bfe48f
HZ		 1531static bool lmce_supported(void)
1532{
c62f2630 1533 uint64_t mce_cap = 0;
40bfe48f 1534
c62f2630 1535#ifdef CONFIG_KVM
40bfe48f
HZ		 1536 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1537 return false;
1538 }
c62f2630 1539#endif
40bfe48f
HZ		 1540
1541 return !!(mce_cap & MCG_LMCE_P);
1542}
1543
c6dc6f63
AP		 1544static int cpu_x86_fill_model_id(char *str)
1545{
1546 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1547 int i;
1548
1549 for (i = 0; i < 3; i++) {
1550 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1551 memcpy(str + i * 16 + 0, &eax, 4);
1552 memcpy(str + i * 16 + 4, &ebx, 4);
1553 memcpy(str + i * 16 + 8, &ecx, 4);
1554 memcpy(str + i * 16 + 12, &edx, 4);
1555 }
1556 return 0;
1557}
1558
c62f2630 1559static Property max_x86_cpu_properties[] = {
120eee7d 1560 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1561 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1562 DEFINE_PROP_END_OF_LIST()
1563};
1564
c62f2630 1565static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1566{
84f1b92f 1567 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1568 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 1569
f48c8837 1570 xcc->ordering = 9;
6e746f30 1571
ee465a3e 1572 xcc->model_description =
c62f2630 1573 "Enables all features supported by the accelerator in the current host";
d940ee9b 1574
c62f2630 1575 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 1576}
1577
0bacd8b3
EH		 1578static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
1579
c62f2630 1580static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 1581{
1582 X86CPU *cpu = X86_CPU(obj);
1583 CPUX86State *env = &cpu->env;
1584 KVMState *s = kvm_state;
d940ee9b 1585
4d1b279b
EH		 1586 /* We can't fill the features array here because we don't know yet if
1587 * "migratable" is true or false.
1588 */
44bd8e53 1589 cpu->max_features = true;
4d1b279b 1590
e4356010 1591 if (kvm_enabled()) {
0bacd8b3
EH		 1592 X86CPUDefinition host_cpudef = { };
1593 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1594
1595 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1596 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1597
1598 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1599 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1600 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1601 host_cpudef.stepping = eax & 0x0F;
1602
1603 cpu_x86_fill_model_id(host_cpudef.model_id);
1604
1605 x86_cpu_load_def(cpu, &host_cpudef, &error_abort);
1606
c39c0edf
EH		 1607 env->cpuid_min_level =
1608 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1609 env->cpuid_min_xlevel =
1610 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1611 env->cpuid_min_xlevel2 =
1612 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
40bfe48f
HZ		 1613
1614 if (lmce_supported()) {
1615 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1616 }
6900d1cc
EH		 1617 } else {
1618 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
1619 "vendor", &error_abort);
1620 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
1621 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
1622 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
1623 object_property_set_str(OBJECT(cpu),
1624 "QEMU TCG CPU version " QEMU_HW_VERSION,
1625 "model-id", &error_abort);
e4356010 1626 }
2a573259 1627
d940ee9b 1628 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1629}
1630
c62f2630
EH		 1631static const TypeInfo max_x86_cpu_type_info = {
1632 .name = X86_CPU_TYPE_NAME("max"),
1633 .parent = TYPE_X86_CPU,
1634 .instance_init = max_x86_cpu_initfn,
1635 .class_init = max_x86_cpu_class_init,
1636};
1637
1638#ifdef CONFIG_KVM
1639
1640static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1641{
1642 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1643
1644 xcc->kvm_required = true;
1645 xcc->ordering = 8;
1646
1647 xcc->model_description =
1648 "KVM processor with all supported host features "
1649 "(only available in KVM mode)";
1650}
1651
d940ee9b
EH		 1652static const TypeInfo host_x86_cpu_type_info = {
1653 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 1654 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 1655 .class_init = host_x86_cpu_class_init,
1656};
1657
1658#endif
1659
8459e396 1660static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1661{
8459e396 1662 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1663 int i;
1664
857aee33 1665 for (i = 0; i < 32; ++i) {
72370dc1 1666 if ((1UL << i) & mask) {
bffd67b0 1667 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1668 assert(reg);
fefb41bf 1669 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1670 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1671 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1672 f->cpuid_eax, reg,
1673 f->feat_names[i] ? "." : "",
1674 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1675 }
857aee33 1676 }
c6dc6f63
AP		 1677}
1678
d7bce999
EB		 1679static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1680 const char *name, void *opaque,
1681 Error **errp)
95b8519d
AF		 1682{
1683 X86CPU *cpu = X86_CPU(obj);
1684 CPUX86State *env = &cpu->env;
1685 int64_t value;
1686
1687 value = (env->cpuid_version >> 8) & 0xf;
1688 if (value == 0xf) {
1689 value += (env->cpuid_version >> 20) & 0xff;
1690 }
51e72bc1 1691 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1692}
1693
d7bce999
EB		 1694static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1695 const char *name, void *opaque,
1696 Error **errp)
ed5e1ec3 1697{
71ad61d3
AF		 1698 X86CPU *cpu = X86_CPU(obj);
1699 CPUX86State *env = &cpu->env;
1700 const int64_t min = 0;
1701 const int64_t max = 0xff + 0xf;
65cd9064 1702 Error *local_err = NULL;
71ad61d3
AF		 1703 int64_t value;
1704
51e72bc1 1705 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1706 if (local_err) {
1707 error_propagate(errp, local_err);
71ad61d3
AF		 1708 return;
1709 }
1710 if (value < min || value > max) {
c6bd8c70
MA		 1711 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1712 name ? name : "null", value, min, max);
71ad61d3
AF		 1713 return;
1714 }
1715
ed5e1ec3 1716 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1717 if (value > 0x0f) {
1718 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1719 } else {
71ad61d3 1720 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1721 }
1722}
1723
d7bce999
EB		 1724static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1725 const char *name, void *opaque,
1726 Error **errp)
67e30c83
AF		 1727{
1728 X86CPU *cpu = X86_CPU(obj);
1729 CPUX86State *env = &cpu->env;
1730 int64_t value;
1731
1732 value = (env->cpuid_version >> 4) & 0xf;
1733 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1734 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1735}
1736
d7bce999
EB		 1737static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1738 const char *name, void *opaque,
1739 Error **errp)
b0704cbd 1740{
c5291a4f
AF		 1741 X86CPU *cpu = X86_CPU(obj);
1742 CPUX86State *env = &cpu->env;
1743 const int64_t min = 0;
1744 const int64_t max = 0xff;
65cd9064 1745 Error *local_err = NULL;
c5291a4f
AF		 1746 int64_t value;
1747
51e72bc1 1748 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1749 if (local_err) {
1750 error_propagate(errp, local_err);
c5291a4f
AF		 1751 return;
1752 }
1753 if (value < min || value > max) {
c6bd8c70
MA		 1754 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1755 name ? name : "null", value, min, max);
c5291a4f
AF		 1756 return;
1757 }
1758
b0704cbd 1759 env->cpuid_version &= ~0xf00f0;
c5291a4f 1760 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1761}
1762
35112e41 1763static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1764 const char *name, void *opaque,
35112e41
AF		 1765 Error **errp)
1766{
1767 X86CPU *cpu = X86_CPU(obj);
1768 CPUX86State *env = &cpu->env;
1769 int64_t value;
1770
1771 value = env->cpuid_version & 0xf;
51e72bc1 1772 visit_type_int(v, name, &value, errp);
35112e41
AF		 1773}
1774
036e2222 1775static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1776 const char *name, void *opaque,
036e2222 1777 Error **errp)
38c3dc46 1778{
036e2222
AF		 1779 X86CPU *cpu = X86_CPU(obj);
1780 CPUX86State *env = &cpu->env;
1781 const int64_t min = 0;
1782 const int64_t max = 0xf;
65cd9064 1783 Error *local_err = NULL;
036e2222
AF		 1784 int64_t value;
1785
51e72bc1 1786 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1787 if (local_err) {
1788 error_propagate(errp, local_err);
036e2222
AF		 1789 return;
1790 }
1791 if (value < min || value > max) {
c6bd8c70
MA		 1792 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1793 name ? name : "null", value, min, max);
036e2222
AF		 1794 return;
1795 }
1796
38c3dc46 1797 env->cpuid_version &= ~0xf;
036e2222 1798 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1799}
1800
d480e1af
AF		 1801static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1802{
1803 X86CPU *cpu = X86_CPU(obj);
1804 CPUX86State *env = &cpu->env;
1805 char *value;
d480e1af 1806
e42a92ae 1807 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1808 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1809 env->cpuid_vendor3);
d480e1af
AF		 1810 return value;
1811}
1812
1813static void x86_cpuid_set_vendor(Object *obj, const char *value,
1814 Error **errp)
1815{
1816 X86CPU *cpu = X86_CPU(obj);
1817 CPUX86State *env = &cpu->env;
1818 int i;
1819
9df694ee 1820 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1821 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1822 return;
1823 }
1824
1825 env->cpuid_vendor1 = 0;
1826 env->cpuid_vendor2 = 0;
1827 env->cpuid_vendor3 = 0;
1828 for (i = 0; i < 4; i++) {
1829 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1830 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1831 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1832 }
d480e1af
AF		 1833}
1834
63e886eb
AF		 1835static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1836{
1837 X86CPU *cpu = X86_CPU(obj);
1838 CPUX86State *env = &cpu->env;
1839 char *value;
1840 int i;
1841
1842 value = g_malloc(48 + 1);
1843 for (i = 0; i < 48; i++) {
1844 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1845 }
1846 value[48] = '\0';
1847 return value;
1848}
1849
938d4c25
AF		 1850static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1851 Error **errp)
dcce6675 1852{
938d4c25
AF		 1853 X86CPU *cpu = X86_CPU(obj);
1854 CPUX86State *env = &cpu->env;
dcce6675
AF		 1855 int c, len, i;
1856
1857 if (model_id == NULL) {
1858 model_id = "";
1859 }
1860 len = strlen(model_id);
d0a6acf4 1861 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1862 for (i = 0; i < 48; i++) {
1863 if (i >= len) {
1864 c = '\0';
1865 } else {
1866 c = (uint8_t)model_id[i];
1867 }
1868 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1869 }
1870}
1871
d7bce999
EB		 1872static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1873 void *opaque, Error **errp)
89e48965
AF		 1874{
1875 X86CPU *cpu = X86_CPU(obj);
1876 int64_t value;
1877
1878 value = cpu->env.tsc_khz * 1000;
51e72bc1 1879 visit_type_int(v, name, &value, errp);
89e48965
AF		 1880}
1881
d7bce999
EB		 1882static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1883 void *opaque, Error **errp)
89e48965
AF		 1884{
1885 X86CPU *cpu = X86_CPU(obj);
1886 const int64_t min = 0;
2e84849a 1887 const int64_t max = INT64_MAX;
65cd9064 1888 Error *local_err = NULL;
89e48965
AF		 1889 int64_t value;
1890
51e72bc1 1891 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1892 if (local_err) {
1893 error_propagate(errp, local_err);
89e48965
AF		 1894 return;
1895 }
1896 if (value < min || value > max) {
c6bd8c70
MA		 1897 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1898 name ? name : "null", value, min, max);
89e48965
AF		 1899 return;
1900 }
1901
36f96c4b 1902 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1903}
1904
7e5292b5 1905/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1906static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1907 const char *name, void *opaque,
1908 Error **errp)
8e8aba50 1909{
7e5292b5 1910 uint32_t *array = (uint32_t *)opaque;
8e8aba50 1911 FeatureWord w;
8e8aba50
EH		 1912 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1913 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1914 X86CPUFeatureWordInfoList *list = NULL;
1915
1916 for (w = 0; w < FEATURE_WORDS; w++) {
1917 FeatureWordInfo *wi = &feature_word_info[w];
1918 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1919 qwi->cpuid_input_eax = wi->cpuid_eax;
1920 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1921 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1922 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1923 qwi->features = array[w];
8e8aba50
EH		 1924
1925 /* List will be in reverse order, but order shouldn't matter */
1926 list_entries[w].next = list;
1927 list_entries[w].value = &word_infos[w];
1928 list = &list_entries[w];
1929 }
1930
6b62d961 1931 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 1932}
1933
d7bce999
EB		 1934static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1935 void *opaque, Error **errp)
c8f0f88e
IM		 1936{
1937 X86CPU *cpu = X86_CPU(obj);
1938 int64_t value = cpu->hyperv_spinlock_attempts;
1939
51e72bc1 1940 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1941}
1942
d7bce999
EB		 1943static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1944 void *opaque, Error **errp)
c8f0f88e
IM		 1945{
1946 const int64_t min = 0xFFF;
1947 const int64_t max = UINT_MAX;
1948 X86CPU *cpu = X86_CPU(obj);
1949 Error *err = NULL;
1950 int64_t value;
1951
51e72bc1 1952 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1953 if (err) {
1954 error_propagate(errp, err);
1955 return;
1956 }
1957
1958 if (value < min || value > max) {
1959 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1960 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1961 object_get_typename(obj), name ? name : "null",
1962 value, min, max);
c8f0f88e
IM		 1963 return;
1964 }
1965 cpu->hyperv_spinlock_attempts = value;
1966}
1967
1968static PropertyInfo qdev_prop_spinlocks = {
1969 .name = "int",
1970 .get = x86_get_hv_spinlocks,
1971 .set = x86_set_hv_spinlocks,
1972};
1973
72ac2e87
IM		 1974/* Convert all '_' in a feature string option name to '-', to make feature
1975 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1976 */
1977static inline void feat2prop(char *s)
1978{
1979 while ((s = strchr(s, '_'))) {
1980 *s = '-';
1981 }
1982}
1983
b54c9377
EH		 1984/* Return the feature property name for a feature flag bit */
1985static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
1986{
1987 /* XSAVE components are automatically enabled by other features,
1988 * so return the original feature name instead
1989 */
1990 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
1991 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
1992
1993 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
1994 x86_ext_save_areas[comp].bits) {
1995 w = x86_ext_save_areas[comp].feature;
1996 bitnr = ctz32(x86_ext_save_areas[comp].bits);
1997 }
1998 }
1999
2000 assert(bitnr < 32);
2001 assert(w < FEATURE_WORDS);
2002 return feature_word_info[w].feat_names[bitnr];
2003}
2004
dc15c051
IM		 2005/* Compatibily hack to maintain legacy +-feat semantic,
2006 * where +-feat overwrites any feature set by
2007 * feat=on|feat even if the later is parsed after +-feat
2008 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2009 */
2fae0d96 2010static GList *plus_features, *minus_features;
dc15c051 2011
83a00f60
EH		 2012static gint compare_string(gconstpointer a, gconstpointer b)
2013{
2014 return g_strcmp0(a, b);
2015}
2016
8f961357
EH		 2017/* Parse "+feature,-feature,feature=foo" CPU feature string
2018 */
62a48a2a 2019static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 2020 Error **errp)
8f961357 2021{
8f961357 2022 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 2023 static bool cpu_globals_initialized;
83a00f60 2024 bool ambiguous = false;
62a48a2a
IM		 2025
2026 if (cpu_globals_initialized) {
2027 return;
2028 }
2029 cpu_globals_initialized = true;
8f961357 2030
f6750e95
EH		 2031 if (!features) {
2032 return;
2033 }
2034
2035 for (featurestr = strtok(features, ",");
685479bd 2036 featurestr;
f6750e95
EH		 2037 featurestr = strtok(NULL, ",")) {
2038 const char *name;
2039 const char *val = NULL;
2040 char *eq = NULL;
cf2887c9 2041 char num[32];
62a48a2a 2042 GlobalProperty *prop;
c6dc6f63 2043
f6750e95 2044 /* Compatibility syntax: */
c6dc6f63 2045 if (featurestr[0] == '+') {
2fae0d96
EH		 2046 plus_features = g_list_append(plus_features,
2047 g_strdup(featurestr + 1));
f6750e95 2048 continue;
c6dc6f63 2049 } else if (featurestr[0] == '-') {
2fae0d96
EH		 2050 minus_features = g_list_append(minus_features,
2051 g_strdup(featurestr + 1));
f6750e95
EH		 2052 continue;
2053 }
2054
2055 eq = strchr(featurestr, '=');
2056 if (eq) {
2057 *eq++ = 0;
2058 val = eq;
c6dc6f63 2059 } else {
f6750e95 2060 val = "on";
a91987c2 2061 }
f6750e95
EH		 2062
2063 feat2prop(featurestr);
2064 name = featurestr;
2065
83a00f60
EH		 2066 if (g_list_find_custom(plus_features, name, compare_string)) {
2067 error_report("warning: Ambiguous CPU model string. "
2068 "Don't mix both \"+%s\" and \"%s=%s\"",
2069 name, name, val);
2070 ambiguous = true;
2071 }
2072 if (g_list_find_custom(minus_features, name, compare_string)) {
2073 error_report("warning: Ambiguous CPU model string. "
2074 "Don't mix both \"-%s\" and \"%s=%s\"",
2075 name, name, val);
2076 ambiguous = true;
2077 }
2078
f6750e95
EH		 2079 /* Special case: */
2080 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 2081 int ret;
f46bfdbf 2082 uint64_t tsc_freq;
f6750e95 2083
f17fd4fd 2084 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 2085 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 2086 error_setg(errp, "bad numerical value %s", val);
2087 return;
2088 }
2089 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2090 val = num;
2091 name = "tsc-frequency";
c6dc6f63 2092 }
f6750e95 2093
62a48a2a
IM		 2094 prop = g_new0(typeof(*prop), 1);
2095 prop->driver = typename;
2096 prop->property = g_strdup(name);
2097 prop->value = g_strdup(val);
2098 prop->errp = &error_fatal;
2099 qdev_prop_register_global(prop);
f6750e95
EH		 2100 }
2101
83a00f60
EH		 2102 if (ambiguous) {
2103 error_report("warning: Compatibility of ambiguous CPU model "
2104 "strings won't be kept on future QEMU versions");
2105 }
c6dc6f63
AP		 2106}
2107
b8d834a0 2108static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 2109static int x86_cpu_filter_features(X86CPU *cpu);
2110
2111/* Check for missing features that may prevent the CPU class from
2112 * running using the current machine and accelerator.
2113 */
2114static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
2115 strList **missing_feats)
2116{
2117 X86CPU *xc;
2118 FeatureWord w;
2119 Error *err = NULL;
2120 strList **next = missing_feats;
2121
2122 if (xcc->kvm_required && !kvm_enabled()) {
2123 strList *new = g_new0(strList, 1);
2124 new->value = g_strdup("kvm");;
2125 *missing_feats = new;
2126 return;
2127 }
2128
2129 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2130
b8d834a0 2131 x86_cpu_expand_features(xc, &err);
b54c9377 2132 if (err) {
b8d834a0 2133 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 2134 * but in case it does, just report the model as not
2135 * runnable at all using the "type" property.
2136 */
2137 strList *new = g_new0(strList, 1);
2138 new->value = g_strdup("type");
2139 *next = new;
2140 next = &new->next;
2141 }
2142
2143 x86_cpu_filter_features(xc);
2144
2145 for (w = 0; w < FEATURE_WORDS; w++) {
2146 uint32_t filtered = xc->filtered_features[w];
2147 int i;
2148 for (i = 0; i < 32; i++) {
2149 if (filtered & (1UL << i)) {
2150 strList *new = g_new0(strList, 1);
2151 new->value = g_strdup(x86_cpu_feature_name(w, i));
2152 *next = new;
2153 next = &new->next;
2154 }
2155 }
2156 }
2157
2158 object_unref(OBJECT(xc));
2159}
2160
8c3329e5 2161/* Print all cpuid feature names in featureset
c6dc6f63 2162 */
8c3329e5 2163static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2164{
8c3329e5
EH		 2165 int bit;
2166 bool first = true;
2167
2168 for (bit = 0; bit < 32; bit++) {
2169 if (featureset[bit]) {
2170 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2171 first = false;
c6dc6f63 2172 }
8c3329e5 2173 }
c6dc6f63
AP		 2174}
2175
f48c8837 2176/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 2177static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
2178{
2179 ObjectClass *class_a = (ObjectClass *)a;
2180 ObjectClass *class_b = (ObjectClass *)b;
2181 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
2182 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
2183 const char *name_a, *name_b;
2184
f48c8837
EH		 2185 if (cc_a->ordering != cc_b->ordering) {
2186 return cc_a->ordering - cc_b->ordering;
ee465a3e
EH		 2187 } else {
2188 name_a = object_class_get_name(class_a);
2189 name_b = object_class_get_name(class_b);
2190 return strcmp(name_a, name_b);
2191 }
2192}
2193
2194static GSList *get_sorted_cpu_model_list(void)
2195{
2196 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
2197 list = g_slist_sort(list, x86_cpu_list_compare);
2198 return list;
2199}
2200
2201static void x86_cpu_list_entry(gpointer data, gpointer user_data)
2202{
2203 ObjectClass *oc = data;
2204 X86CPUClass *cc = X86_CPU_CLASS(oc);
2205 CPUListState *s = user_data;
2206 char *name = x86_cpu_class_get_model_name(cc);
2207 const char *desc = cc->model_description;
0bacd8b3 2208 if (!desc && cc->cpu_def) {
ee465a3e
EH		 2209 desc = cc->cpu_def->model_id;
2210 }
2211
2212 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
2213 name, desc);
2214 g_free(name);
2215}
2216
2217/* list available CPU models and flags */
e916cbf8 2218void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2219{
7fc9b714 2220 int i;
ee465a3e
EH		 2221 CPUListState s = {
2222 .file = f,
2223 .cpu_fprintf = cpu_fprintf,
2224 };
2225 GSList *list;
c6dc6f63 2226
ee465a3e
EH		 2227 (*cpu_fprintf)(f, "Available CPUs:\n");
2228 list = get_sorted_cpu_model_list();
2229 g_slist_foreach(list, x86_cpu_list_entry, &s);
2230 g_slist_free(list);
21ad7789 2231
6cdf8854 2232 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2233 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2234 FeatureWordInfo *fw = &feature_word_info[i];
2235
8c3329e5
EH		 2236 (*cpu_fprintf)(f, " ");
2237 listflags(f, cpu_fprintf, fw->feat_names);
2238 (*cpu_fprintf)(f, "\n");
3af60be2 2239 }
c6dc6f63
AP		 2240}
2241
ee465a3e
EH		 2242static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
2243{
2244 ObjectClass *oc = data;
2245 X86CPUClass *cc = X86_CPU_CLASS(oc);
2246 CpuDefinitionInfoList **cpu_list = user_data;
2247 CpuDefinitionInfoList *entry;
2248 CpuDefinitionInfo *info;
2249
2250 info = g_malloc0(sizeof(*info));
2251 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 2252 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
2253 info->has_unavailable_features = true;
8ed877b7 2254 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 2255 info->migration_safe = cc->migration_safe;
2256 info->has_migration_safe = true;
5adbed30 2257 info->q_static = cc->static_model;
ee465a3e
EH		 2258
2259 entry = g_malloc0(sizeof(*entry));
2260 entry->value = info;
2261 entry->next = *cpu_list;
2262 *cpu_list = entry;
2263}
2264
76b64a7a 2265CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2266{
2267 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 2268 GSList *list = get_sorted_cpu_model_list();
2269 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
2270 g_slist_free(list);
e3966126
AL		 2271 return cpu_list;
2272}
2273
84f1b92f
EH		 2274static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2275 bool migratable_only)
27418adf
EH		 2276{
2277 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2278 uint32_t r;
27418adf 2279
fefb41bf 2280 if (kvm_enabled()) {
84f1b92f
EH		 2281 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2282 wi->cpuid_ecx,
2283 wi->cpuid_reg);
fefb41bf 2284 } else if (tcg_enabled()) {
84f1b92f 2285 r = wi->tcg_features;
fefb41bf
EH		 2286 } else {
2287 return ~0;
2288 }
84f1b92f
EH		 2289 if (migratable_only) {
2290 r &= x86_cpu_get_migratable_flags(w);
2291 }
2292 return r;
27418adf
EH		 2293}
2294
8ca30e86
EH		 2295static void x86_cpu_report_filtered_features(X86CPU *cpu)
2296{
2297 FeatureWord w;
2298
2299 for (w = 0; w < FEATURE_WORDS; w++) {
2300 report_unavailable_features(w, cpu->filtered_features[w]);
2301 }
2302}
2303
5114e842
EH		 2304static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2305{
2306 PropValue *pv;
2307 for (pv = props; pv->prop; pv++) {
2308 if (!pv->value) {
2309 continue;
2310 }
2311 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2312 &error_abort);
2313 }
2314}
2315
f99fd7ca 2316/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 2317 */
d940ee9b 2318static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2319{
61dcd775 2320 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2321 const char *vendor;
2322 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2323 FeatureWord w;
c6dc6f63 2324
f99fd7ca
EH		 2325 /*NOTE: any property set by this function should be returned by
2326 * x86_cpu_static_props(), so static expansion of
2327 * query-cpu-model-expansion is always complete.
2328 */
2329
c39c0edf
EH		 2330 /* CPU models only set _minimum_ values for level/xlevel: */
2331 object_property_set_int(OBJECT(cpu), def->level, "min-level", errp);
2332 object_property_set_int(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
2333
2d64255b
AF		 2334 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2335 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2336 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2337 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2338 for (w = 0; w < FEATURE_WORDS; w++) {
2339 env->features[w] = def->features[w];
2340 }
82beb536 2341
9576de75 2342 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2343 if (kvm_enabled()) {
492a4c94
LT		 2344 if (!kvm_irqchip_in_kernel()) {
2345 x86_cpu_change_kvm_default("x2apic", "off");
2346 }
2347
5114e842 2348 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 2349 } else if (tcg_enabled()) {
2350 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 2351 }
5fcca9ff 2352
82beb536 2353 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2354
2355 /* sysenter isn't supported in compatibility mode on AMD,
2356 * syscall isn't supported in compatibility mode on Intel.
2357 * Normally we advertise the actual CPU vendor, but you can
2358 * override this using the 'vendor' property if you want to use
2359 * KVM's sysenter/syscall emulation in compatibility mode and
2360 * when doing cross vendor migration
2361 */
74f54bc4 2362 vendor = def->vendor;
7c08db30
EH		 2363 if (kvm_enabled()) {
2364 uint32_t ebx = 0, ecx = 0, edx = 0;
2365 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2366 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2367 vendor = host_vendor;
2368 }
2369
2370 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2371
c6dc6f63
AP		 2372}
2373
f99fd7ca
EH		 2374/* Return a QDict containing keys for all properties that can be included
2375 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
2376 * must be included in the dictionary.
2377 */
2378static QDict *x86_cpu_static_props(void)
2379{
2380 FeatureWord w;
2381 int i;
2382 static const char *props[] = {
2383 "min-level",
2384 "min-xlevel",
2385 "family",
2386 "model",
2387 "stepping",
2388 "model-id",
2389 "vendor",
2390 "lmce",
2391 NULL,
2392 };
2393 static QDict *d;
2394
2395 if (d) {
2396 return d;
2397 }
2398
2399 d = qdict_new();
2400 for (i = 0; props[i]; i++) {
2401 qdict_put_obj(d, props[i], qnull());
2402 }
2403
2404 for (w = 0; w < FEATURE_WORDS; w++) {
2405 FeatureWordInfo *fi = &feature_word_info[w];
2406 int bit;
2407 for (bit = 0; bit < 32; bit++) {
2408 if (!fi->feat_names[bit]) {
2409 continue;
2410 }
2411 qdict_put_obj(d, fi->feat_names[bit], qnull());
2412 }
2413 }
2414
2415 return d;
2416}
2417
2418/* Add an entry to @props dict, with the value for property. */
2419static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
2420{
2421 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
2422 &error_abort);
2423
2424 qdict_put_obj(props, prop, value);
2425}
2426
2427/* Convert CPU model data from X86CPU object to a property dictionary
2428 * that can recreate exactly the same CPU model.
2429 */
2430static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
2431{
2432 QDict *sprops = x86_cpu_static_props();
2433 const QDictEntry *e;
2434
2435 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
2436 const char *prop = qdict_entry_key(e);
2437 x86_cpu_expand_prop(cpu, props, prop);
2438 }
2439}
2440
b8097deb
EH		 2441/* Convert CPU model data from X86CPU object to a property dictionary
2442 * that can recreate exactly the same CPU model, including every
2443 * writeable QOM property.
2444 */
2445static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
2446{
2447 ObjectPropertyIterator iter;
2448 ObjectProperty *prop;
2449
2450 object_property_iter_init(&iter, OBJECT(cpu));
2451 while ((prop = object_property_iter_next(&iter))) {
2452 /* skip read-only or write-only properties */
2453 if (!prop->get || !prop->set) {
2454 continue;
2455 }
2456
2457 /* "hotplugged" is the only property that is configurable
2458 * on the command-line but will be set differently on CPUs
2459 * created using "-cpu ... -smp ..." and by CPUs created
2460 * on the fly by x86_cpu_from_model() for querying. Skip it.
2461 */
2462 if (!strcmp(prop->name, "hotplugged")) {
2463 continue;
2464 }
2465 x86_cpu_expand_prop(cpu, props, prop->name);
2466 }
2467}
2468
f99fd7ca
EH		 2469static void object_apply_props(Object *obj, QDict *props, Error **errp)
2470{
2471 const QDictEntry *prop;
2472 Error *err = NULL;
2473
2474 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
2475 object_property_set_qobject(obj, qdict_entry_value(prop),
2476 qdict_entry_key(prop), &err);
2477 if (err) {
2478 break;
2479 }
2480 }
2481
2482 error_propagate(errp, err);
2483}
2484
2485/* Create X86CPU object according to model+props specification */
2486static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
2487{
2488 X86CPU *xc = NULL;
2489 X86CPUClass *xcc;
2490 Error *err = NULL;
2491
2492 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
2493 if (xcc == NULL) {
2494 error_setg(&err, "CPU model '%s' not found", model);
2495 goto out;
2496 }
2497
2498 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2499 if (props) {
2500 object_apply_props(OBJECT(xc), props, &err);
2501 if (err) {
2502 goto out;
2503 }
2504 }
2505
2506 x86_cpu_expand_features(xc, &err);
2507 if (err) {
2508 goto out;
2509 }
2510
2511out:
2512 if (err) {
2513 error_propagate(errp, err);
2514 object_unref(OBJECT(xc));
2515 xc = NULL;
2516 }
2517 return xc;
2518}
2519
2520CpuModelExpansionInfo *
2521arch_query_cpu_model_expansion(CpuModelExpansionType type,
2522 CpuModelInfo *model,
2523 Error **errp)
2524{
2525 X86CPU *xc = NULL;
2526 Error *err = NULL;
2527 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
2528 QDict *props = NULL;
2529 const char *base_name;
2530
2531 xc = x86_cpu_from_model(model->name,
2532 model->has_props ?
2533 qobject_to_qdict(model->props) :
2534 NULL, &err);
2535 if (err) {
2536 goto out;
2537 }
2538
b8097deb 2539 props = qdict_new();
f99fd7ca
EH		 2540
2541 switch (type) {
2542 case CPU_MODEL_EXPANSION_TYPE_STATIC:
2543 /* Static expansion will be based on "base" only */
2544 base_name = "base";
b8097deb 2545 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 2546 break;
2547 case CPU_MODEL_EXPANSION_TYPE_FULL:
2548 /* As we don't return every single property, full expansion needs
2549 * to keep the original model name+props, and add extra
2550 * properties on top of that.
2551 */
2552 base_name = model->name;
b8097deb 2553 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 2554 break;
2555 default:
2556 error_setg(&err, "Unsupportted expansion type");
2557 goto out;
2558 }
2559
2560 if (!props) {
2561 props = qdict_new();
2562 }
2563 x86_cpu_to_dict(xc, props);
2564
2565 ret->model = g_new0(CpuModelInfo, 1);
2566 ret->model->name = g_strdup(base_name);
2567 ret->model->props = QOBJECT(props);
2568 ret->model->has_props = true;
2569
2570out:
2571 object_unref(OBJECT(xc));
2572 if (err) {
2573 error_propagate(errp, err);
2574 qapi_free_CpuModelExpansionInfo(ret);
2575 ret = NULL;
2576 }
2577 return ret;
2578}
2579
0856579c 2580X86CPU *cpu_x86_init(const char *cpu_model)
7f833247 2581{
a57d0163 2582 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
5c3c6a68
AF		 2583}
2584
d940ee9b
EH		 2585static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2586{
2587 X86CPUDefinition *cpudef = data;
2588 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2589
2590 xcc->cpu_def = cpudef;
bd72159d 2591 xcc->migration_safe = true;
d940ee9b
EH		 2592}
2593
2594static void x86_register_cpudef_type(X86CPUDefinition *def)
2595{
2596 char *typename = x86_cpu_type_name(def->name);
2597 TypeInfo ti = {
2598 .name = typename,
2599 .parent = TYPE_X86_CPU,
2600 .class_init = x86_cpu_cpudef_class_init,
2601 .class_data = def,
2602 };
2603
2a923a29
EH		 2604 /* AMD aliases are handled at runtime based on CPUID vendor, so
2605 * they shouldn't be set on the CPU model table.
2606 */
2607 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
2608
d940ee9b
EH		 2609 type_register(&ti);
2610 g_free(typename);
2611}
2612
c6dc6f63 2613#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2614
0e26b7b8
BS		 2615void cpu_clear_apic_feature(CPUX86State *env)
2616{
0514ef2f 2617 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2618}
2619
c6dc6f63
AP		 2620#endif /* !CONFIG_USER_ONLY */
2621
c6dc6f63
AP		 2622void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2623 uint32_t *eax, uint32_t *ebx,
2624 uint32_t *ecx, uint32_t *edx)
2625{
a60f24b5
AF		 2626 X86CPU *cpu = x86_env_get_cpu(env);
2627 CPUState *cs = CPU(cpu);
14c985cf 2628 uint32_t pkg_offset;
a60f24b5 2629
c6dc6f63
AP		 2630 /* test if maximum index reached */
2631 if (index & 0x80000000) {
b3baa152
BW		 2632 if (index > env->cpuid_xlevel) {
2633 if (env->cpuid_xlevel2 > 0) {
2634 /* Handle the Centaur's CPUID instruction. */
2635 if (index > env->cpuid_xlevel2) {
2636 index = env->cpuid_xlevel2;
2637 } else if (index < 0xC0000000) {
2638 index = env->cpuid_xlevel;
2639 }
2640 } else {
57f26ae7
EH		 2641 /* Intel documentation states that invalid EAX input will
2642 * return the same information as EAX=cpuid_level
2643 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2644 */
2645 index = env->cpuid_level;
b3baa152
BW		 2646 }
2647 }
c6dc6f63
AP		 2648 } else {
2649 if (index > env->cpuid_level)
2650 index = env->cpuid_level;
2651 }
2652
2653 switch(index) {
2654 case 0:
2655 *eax = env->cpuid_level;
5eb2f7a4
EH		 2656 *ebx = env->cpuid_vendor1;
2657 *edx = env->cpuid_vendor2;
2658 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2659 break;
2660 case 1:
2661 *eax = env->cpuid_version;
7e72a45c
EH		 2662 *ebx = (cpu->apic_id << 24) |
2663 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2664 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2665 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2666 *ecx |= CPUID_EXT_OSXSAVE;
2667 }
0514ef2f 2668 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2669 if (cs->nr_cores * cs->nr_threads > 1) {
2670 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2671 *edx |= CPUID_HT;
c6dc6f63
AP		 2672 }
2673 break;
2674 case 2:
2675 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2676 if (cpu->cache_info_passthrough) {
2677 host_cpuid(index, 0, eax, ebx, ecx, edx);
2678 break;
2679 }
5e891bf8 2680 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 2681 *ebx = 0;
14c985cf
LM		 2682 if (!cpu->enable_l3_cache) {
2683 *ecx = 0;
2684 } else {
2685 *ecx = L3_N_DESCRIPTOR;
2686 }
5e891bf8
EH		 2687 *edx = (L1D_DESCRIPTOR << 16) | \
2688 (L1I_DESCRIPTOR << 8) | \
2689 (L2_DESCRIPTOR);
c6dc6f63
AP		 2690 break;
2691 case 4:
2692 /* cache info: needed for Core compatibility */
787aaf57
BC		 2693 if (cpu->cache_info_passthrough) {
2694 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2695 *eax &= ~0xFC000000;
c6dc6f63 2696 } else {
2f7a21c4 2697 *eax = 0;
76c2975a 2698 switch (count) {
c6dc6f63 2699 case 0: /* L1 dcache info */
5e891bf8
EH		 2700 *eax |= CPUID_4_TYPE_DCACHE | \
2701 CPUID_4_LEVEL(1) | \
2702 CPUID_4_SELF_INIT_LEVEL;
2703 *ebx = (L1D_LINE_SIZE - 1) | \
2704 ((L1D_PARTITIONS - 1) << 12) | \
2705 ((L1D_ASSOCIATIVITY - 1) << 22);
2706 *ecx = L1D_SETS - 1;
2707 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2708 break;
2709 case 1: /* L1 icache info */
5e891bf8
EH		 2710 *eax |= CPUID_4_TYPE_ICACHE | \
2711 CPUID_4_LEVEL(1) | \
2712 CPUID_4_SELF_INIT_LEVEL;
2713 *ebx = (L1I_LINE_SIZE - 1) | \
2714 ((L1I_PARTITIONS - 1) << 12) | \
2715 ((L1I_ASSOCIATIVITY - 1) << 22);
2716 *ecx = L1I_SETS - 1;
2717 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2718 break;
2719 case 2: /* L2 cache info */
5e891bf8
EH		 2720 *eax |= CPUID_4_TYPE_UNIFIED | \
2721 CPUID_4_LEVEL(2) | \
2722 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2723 if (cs->nr_threads > 1) {
2724 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2725 }
5e891bf8
EH		 2726 *ebx = (L2_LINE_SIZE - 1) | \
2727 ((L2_PARTITIONS - 1) << 12) | \
2728 ((L2_ASSOCIATIVITY - 1) << 22);
2729 *ecx = L2_SETS - 1;
2730 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63 2731 break;
14c985cf
LM		 2732 case 3: /* L3 cache info */
2733 if (!cpu->enable_l3_cache) {
2734 *eax = 0;
2735 *ebx = 0;
2736 *ecx = 0;
2737 *edx = 0;
2738 break;
2739 }
2740 *eax |= CPUID_4_TYPE_UNIFIED | \
2741 CPUID_4_LEVEL(3) | \
2742 CPUID_4_SELF_INIT_LEVEL;
2743 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2744 *eax |= ((1 << pkg_offset) - 1) << 14;
2745 *ebx = (L3_N_LINE_SIZE - 1) | \
2746 ((L3_N_PARTITIONS - 1) << 12) | \
2747 ((L3_N_ASSOCIATIVITY - 1) << 22);
2748 *ecx = L3_N_SETS - 1;
2749 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2750 break;
c6dc6f63
AP		 2751 default: /* end of info */
2752 *eax = 0;
2753 *ebx = 0;
2754 *ecx = 0;
2755 *edx = 0;
2756 break;
76c2975a
PB		 2757 }
2758 }
2759
2760 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2761 if ((*eax & 31) && cs->nr_cores > 1) {
2762 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2763 }
2764 break;
2765 case 5:
2766 /* mwait info: needed for Core compatibility */
2767 *eax = 0; /* Smallest monitor-line size in bytes */
2768 *ebx = 0; /* Largest monitor-line size in bytes */
2769 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2770 *edx = 0;
2771 break;
2772 case 6:
2773 /* Thermal and Power Leaf */
28b8e4d0 2774 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2775 *ebx = 0;
2776 *ecx = 0;
2777 *edx = 0;
2778 break;
f7911686 2779 case 7:
13526728
EH		 2780 /* Structured Extended Feature Flags Enumeration Leaf */
2781 if (count == 0) {
2782 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2783 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2784 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2785 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2786 *ecx |= CPUID_7_0_ECX_OSPKE;
2787 }
95ea69fb 2788 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 2789 } else {
2790 *eax = 0;
2791 *ebx = 0;
2792 *ecx = 0;
2793 *edx = 0;
2794 }
2795 break;
c6dc6f63
AP		 2796 case 9:
2797 /* Direct Cache Access Information Leaf */
2798 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2799 *ebx = 0;
2800 *ecx = 0;
2801 *edx = 0;
2802 break;
2803 case 0xA:
2804 /* Architectural Performance Monitoring Leaf */
9337e3b6 2805 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2806 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2807
2808 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2809 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2810 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2811 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2812 } else {
2813 *eax = 0;
2814 *ebx = 0;
2815 *ecx = 0;
2816 *edx = 0;
2817 }
c6dc6f63 2818 break;
5232d00a
RK		 2819 case 0xB:
2820 /* Extended Topology Enumeration Leaf */
2821 if (!cpu->enable_cpuid_0xb) {
2822 *eax = *ebx = *ecx = *edx = 0;
2823 break;
2824 }
2825
2826 *ecx = count & 0xff;
2827 *edx = cpu->apic_id;
2828
2829 switch (count) {
2830 case 0:
eab60fb9
MAL		 2831 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
2832 *ebx = cs->nr_threads;
5232d00a
RK		 2833 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2834 break;
2835 case 1:
eab60fb9
MAL		 2836 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2837 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 2838 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2839 break;
2840 default:
2841 *eax = 0;
2842 *ebx = 0;
2843 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2844 }
2845
2846 assert(!(*eax & ~0x1f));
2847 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2848 break;
2560f19f 2849 case 0xD: {
51e49430 2850 /* Processor Extended State */
2560f19f
PB		 2851 *eax = 0;
2852 *ebx = 0;
2853 *ecx = 0;
2854 *edx = 0;
19dc85db 2855 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2856 break;
2857 }
4928cd6d 2858
2560f19f 2859 if (count == 0) {
96193c22
EH		 2860 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
2861 *eax = env->features[FEAT_XSAVE_COMP_LO];
2862 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 2863 *ebx = *ecx;
2864 } else if (count == 1) {
0bb0b2d2 2865 *eax = env->features[FEAT_XSAVE];
f4f1110e 2866 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 2867 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
2868 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 2869 *eax = esa->size;
2870 *ebx = esa->offset;
2560f19f 2871 }
51e49430
SY		 2872 }
2873 break;
2560f19f 2874 }
c6dc6f63
AP		 2875 case 0x80000000:
2876 *eax = env->cpuid_xlevel;
2877 *ebx = env->cpuid_vendor1;
2878 *edx = env->cpuid_vendor2;
2879 *ecx = env->cpuid_vendor3;
2880 break;
2881 case 0x80000001:
2882 *eax = env->cpuid_version;
2883 *ebx = 0;
0514ef2f
EH		 2884 *ecx = env->features[FEAT_8000_0001_ECX];
2885 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2886
2887 /* The Linux kernel checks for the CMPLegacy bit and
2888 * discards multiple thread information if it is set.
cb8d4c8f 2889 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2890 */
ce3960eb 2891 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2892 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2893 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2894 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2895 *ecx |= 1 << 1; /* CmpLegacy bit */
2896 }
2897 }
c6dc6f63
AP		 2898 break;
2899 case 0x80000002:
2900 case 0x80000003:
2901 case 0x80000004:
2902 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2903 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2904 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2905 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2906 break;
2907 case 0x80000005:
2908 /* cache info (L1 cache) */
787aaf57
BC		 2909 if (cpu->cache_info_passthrough) {
2910 host_cpuid(index, 0, eax, ebx, ecx, edx);
2911 break;
2912 }
5e891bf8
EH		 2913 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2914 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2915 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2916 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2917 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2918 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2919 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2920 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2921 break;
2922 case 0x80000006:
2923 /* cache info (L2 cache) */
787aaf57
BC		 2924 if (cpu->cache_info_passthrough) {
2925 host_cpuid(index, 0, eax, ebx, ecx, edx);
2926 break;
2927 }
5e891bf8
EH		 2928 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2929 (L2_DTLB_2M_ENTRIES << 16) | \
2930 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2931 (L2_ITLB_2M_ENTRIES);
2932 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2933 (L2_DTLB_4K_ENTRIES << 16) | \
2934 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2935 (L2_ITLB_4K_ENTRIES);
2936 *ecx = (L2_SIZE_KB_AMD << 16) | \
2937 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2938 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
14c985cf
LM		 2939 if (!cpu->enable_l3_cache) {
2940 *edx = ((L3_SIZE_KB / 512) << 18) | \
2941 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2942 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2943 } else {
2944 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
2945 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
2946 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
2947 }
c6dc6f63 2948 break;
303752a9
MT		 2949 case 0x80000007:
2950 *eax = 0;
2951 *ebx = 0;
2952 *ecx = 0;
2953 *edx = env->features[FEAT_8000_0007_EDX];
2954 break;
c6dc6f63
AP		 2955 case 0x80000008:
2956 /* virtual & phys address size in low 2 bytes. */
0514ef2f 2957 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 2958 /* 64 bit processor */
2959 *eax = cpu->phys_bits; /* configurable physical bits */
2960 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
2961 *eax |= 0x00003900; /* 57 bits virtual */
2962 } else {
2963 *eax |= 0x00003000; /* 48 bits virtual */
2964 }
c6dc6f63 2965 } else {
af45907a 2966 *eax = cpu->phys_bits;
c6dc6f63
AP		 2967 }
2968 *ebx = 0;
2969 *ecx = 0;
2970 *edx = 0;
ce3960eb
AF		 2971 if (cs->nr_cores * cs->nr_threads > 1) {
2972 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2973 }
2974 break;
2975 case 0x8000000A:
0514ef2f 2976 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2977 *eax = 0x00000001; /* SVM Revision */
2978 *ebx = 0x00000010; /* nr of ASIDs */
2979 *ecx = 0;
0514ef2f 2980 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2981 } else {
2982 *eax = 0;
2983 *ebx = 0;
2984 *ecx = 0;
2985 *edx = 0;
2986 }
c6dc6f63 2987 break;
b3baa152
BW		 2988 case 0xC0000000:
2989 *eax = env->cpuid_xlevel2;
2990 *ebx = 0;
2991 *ecx = 0;
2992 *edx = 0;
2993 break;
2994 case 0xC0000001:
2995 /* Support for VIA CPU's CPUID instruction */
2996 *eax = env->cpuid_version;
2997 *ebx = 0;
2998 *ecx = 0;
0514ef2f 2999 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 3000 break;
3001 case 0xC0000002:
3002 case 0xC0000003:
3003 case 0xC0000004:
3004 /* Reserved for the future, and now filled with zero */
3005 *eax = 0;
3006 *ebx = 0;
3007 *ecx = 0;
3008 *edx = 0;
3009 break;
c6dc6f63
AP		 3010 default:
3011 /* reserved values: zero */
3012 *eax = 0;
3013 *ebx = 0;
3014 *ecx = 0;
3015 *edx = 0;
3016 break;
3017 }
3018}
5fd2087a
AF		 3019
3020/* CPUClass::reset() */
3021static void x86_cpu_reset(CPUState *s)
3022{
3023 X86CPU *cpu = X86_CPU(s);
3024 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
3025 CPUX86State *env = &cpu->env;
a114d25d
RH		 3026 target_ulong cr4;
3027 uint64_t xcr0;
c1958aea
AF		 3028 int i;
3029
5fd2087a
AF		 3030 xcc->parent_reset(s);
3031
5e992a8e 3032 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 3033
c1958aea
AF		 3034 env->old_exception = -1;
3035
3036 /* init to reset state */
3037
c1958aea
AF		 3038 env->hflags2 |= HF2_GIF_MASK;
3039
3040 cpu_x86_update_cr0(env, 0x60000010);
3041 env->a20_mask = ~0x0;
3042 env->smbase = 0x30000;
3043
3044 env->idt.limit = 0xffff;
3045 env->gdt.limit = 0xffff;
3046 env->ldt.limit = 0xffff;
3047 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
3048 env->tr.limit = 0xffff;
3049 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
3050
3051 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
3052 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
3053 DESC_R_MASK | DESC_A_MASK);
3054 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
3055 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3056 DESC_A_MASK);
3057 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
3058 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3059 DESC_A_MASK);
3060 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
3061 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3062 DESC_A_MASK);
3063 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
3064 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3065 DESC_A_MASK);
3066 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
3067 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3068 DESC_A_MASK);
3069
3070 env->eip = 0xfff0;
3071 env->regs[R_EDX] = env->cpuid_version;
3072
3073 env->eflags = 0x2;
3074
3075 /* FPU init */
3076 for (i = 0; i < 8; i++) {
3077 env->fptags[i] = 1;
3078 }
5bde1407 3079 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 3080
3081 env->mxcsr = 0x1f80;
a114d25d
RH		 3082 /* All units are in INIT state. */
3083 env->xstate_bv = 0;
c1958aea
AF		 3084
3085 env->pat = 0x0007040600070406ULL;
3086 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
3087
3088 memset(env->dr, 0, sizeof(env->dr));
3089 env->dr[6] = DR6_FIXED_1;
3090 env->dr[7] = DR7_FIXED_1;
b3310ab3 3091 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 3092 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 3093
a114d25d 3094 cr4 = 0;
cfc3b074 3095 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 3096
3097#ifdef CONFIG_USER_ONLY
3098 /* Enable all the features for user-mode. */
3099 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 3100 xcr0 |= XSTATE_SSE_MASK;
a114d25d 3101 }
0f70ed47
PB		 3102 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
3103 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 3104 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 3105 xcr0 |= 1ull << i;
3106 }
a114d25d 3107 }
0f70ed47 3108
a114d25d
RH		 3109 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
3110 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
3111 }
07929f2a
RH		 3112 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
3113 cr4 |= CR4_FSGSBASE_MASK;
3114 }
a114d25d
RH		 3115#endif
3116
3117 env->xcr0 = xcr0;
3118 cpu_x86_update_cr4(env, cr4);
0522604b 3119
9db2efd9
AW		 3120 /*
3121 * SDM 11.11.5 requires:
3122 * - IA32_MTRR_DEF_TYPE MSR.E = 0
3123 * - IA32_MTRR_PHYSMASKn.V = 0
3124 * All other bits are undefined. For simplification, zero it all.
3125 */
3126 env->mtrr_deftype = 0;
3127 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
3128 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
3129
dd673288
IM		 3130#if !defined(CONFIG_USER_ONLY)
3131 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 3132 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 3133
259186a7 3134 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 3135
3136 if (kvm_enabled()) {
3137 kvm_arch_reset_vcpu(cpu);
3138 }
dd673288 3139#endif
5fd2087a
AF		 3140}
3141
dd673288
IM		 3142#ifndef CONFIG_USER_ONLY
3143bool cpu_is_bsp(X86CPU *cpu)
3144{
02e51483 3145 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 3146}
65dee380
IM		 3147
3148/* TODO: remove me, when reset over QOM tree is implemented */
3149static void x86_cpu_machine_reset_cb(void *opaque)
3150{
3151 X86CPU *cpu = opaque;
3152 cpu_reset(CPU(cpu));
3153}
dd673288
IM		 3154#endif
3155
de024815
AF		 3156static void mce_init(X86CPU *cpu)
3157{
3158 CPUX86State *cenv = &cpu->env;
3159 unsigned int bank;
3160
3161 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 3162 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 3163 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 3164 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
3165 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 3166 cenv->mcg_ctl = ~(uint64_t)0;
3167 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
3168 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
3169 }
3170 }
3171}
3172
bdeec802 3173#ifndef CONFIG_USER_ONLY
2f114315 3174APICCommonClass *apic_get_class(void)
bdeec802 3175{
bdeec802
IM		 3176 const char *apic_type = "apic";
3177
15eafc2e 3178 if (kvm_apic_in_kernel()) {
bdeec802
IM		 3179 apic_type = "kvm-apic";
3180 } else if (xen_enabled()) {
3181 apic_type = "xen-apic";
3182 }
3183
2f114315
RK		 3184 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
3185}
3186
3187static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
3188{
3189 APICCommonState *apic;
3190 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
3191
3192 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 3193
6816b1b3
IM		 3194 object_property_add_child(OBJECT(cpu), "lapic",
3195 OBJECT(cpu->apic_state), &error_abort);
67e55caa 3196 object_unref(OBJECT(cpu->apic_state));
6816b1b3 3197
33d7a288 3198 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 3199 /* TODO: convert to link<> */
02e51483 3200 apic = APIC_COMMON(cpu->apic_state);
60671e58 3201 apic->cpu = cpu;
8d42d2d3 3202 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 3203}
3204
3205static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3206{
8d42d2d3
CF		 3207 APICCommonState *apic;
3208 static bool apic_mmio_map_once;
3209
02e51483 3210 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 3211 return;
3212 }
6e8e2651
MA		 3213 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
3214 errp);
8d42d2d3
CF		 3215
3216 /* Map APIC MMIO area */
3217 apic = APIC_COMMON(cpu->apic_state);
3218 if (!apic_mmio_map_once) {
3219 memory_region_add_subregion_overlap(get_system_memory(),
3220 apic->apicbase &
3221 MSR_IA32_APICBASE_BASE,
3222 &apic->io_memory,
3223 0x1000);
3224 apic_mmio_map_once = true;
3225 }
bdeec802 3226}
f809c605
PB		 3227
3228static void x86_cpu_machine_done(Notifier *n, void *unused)
3229{
3230 X86CPU *cpu = container_of(n, X86CPU, machine_done);
3231 MemoryRegion *smram =
3232 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
3233
3234 if (smram) {
3235 cpu->smram = g_new(MemoryRegion, 1);
3236 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
3237 smram, 0, 1ull << 32);
3238 memory_region_set_enabled(cpu->smram, false);
3239 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
3240 }
3241}
d3c64d6a
IM		 3242#else
3243static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3244{
3245}
bdeec802
IM		 3246#endif
3247
11f6fee5
DDAG		 3248/* Note: Only safe for use on x86(-64) hosts */
3249static uint32_t x86_host_phys_bits(void)
3250{
3251 uint32_t eax;
3252 uint32_t host_phys_bits;
3253
3254 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
3255 if (eax >= 0x80000008) {
3256 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
3257 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3258 * at 23:16 that can specify a maximum physical address bits for
3259 * the guest that can override this value; but I've not seen
3260 * anything with that set.
3261 */
3262 host_phys_bits = eax & 0xff;
3263 } else {
3264 /* It's an odd 64 bit machine that doesn't have the leaf for
3265 * physical address bits; fall back to 36 that's most older
3266 * Intel.
3267 */
3268 host_phys_bits = 36;
3269 }
3270
3271 return host_phys_bits;
3272}
e48638fd 3273
c39c0edf
EH		 3274static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
3275{
3276 if (*min < value) {
3277 *min = value;
3278 }
3279}
3280
3281/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3282static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
3283{
3284 CPUX86State *env = &cpu->env;
3285 FeatureWordInfo *fi = &feature_word_info[w];
3286 uint32_t eax = fi->cpuid_eax;
3287 uint32_t region = eax & 0xF0000000;
3288
3289 if (!env->features[w]) {
3290 return;
3291 }
3292
3293 switch (region) {
3294 case 0x00000000:
3295 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
3296 break;
3297 case 0x80000000:
3298 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
3299 break;
3300 case 0xC0000000:
3301 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
3302 break;
3303 }
3304}
3305
2ca8a8be
EH		 3306/* Calculate XSAVE components based on the configured CPU feature flags */
3307static void x86_cpu_enable_xsave_components(X86CPU *cpu)
3308{
3309 CPUX86State *env = &cpu->env;
3310 int i;
96193c22 3311 uint64_t mask;
2ca8a8be
EH		 3312
3313 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
3314 return;
3315 }
3316
e3c9022b
EH		 3317 mask = 0;
3318 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 3319 const ExtSaveArea *esa = &x86_ext_save_areas[i];
3320 if (env->features[esa->feature] & esa->bits) {
96193c22 3321 mask |= (1ULL << i);
2ca8a8be
EH		 3322 }
3323 }
3324
96193c22
EH		 3325 env->features[FEAT_XSAVE_COMP_LO] = mask;
3326 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 3327}
3328
b8d834a0
EH		 3329/***** Steps involved on loading and filtering CPUID data
3330 *
3331 * When initializing and realizing a CPU object, the steps
3332 * involved in setting up CPUID data are:
3333 *
3334 * 1) Loading CPU model definition (X86CPUDefinition). This is
3335 * implemented by x86_cpu_load_def() and should be completely
3336 * transparent, as it is done automatically by instance_init.
3337 * No code should need to look at X86CPUDefinition structs
3338 * outside instance_init.
3339 *
3340 * 2) CPU expansion. This is done by realize before CPUID
3341 * filtering, and will make sure host/accelerator data is
3342 * loaded for CPU models that depend on host capabilities
3343 * (e.g. "host"). Done by x86_cpu_expand_features().
3344 *
3345 * 3) CPUID filtering. This initializes extra data related to
3346 * CPUID, and checks if the host supports all capabilities
3347 * required by the CPU. Runnability of a CPU model is
3348 * determined at this step. Done by x86_cpu_filter_features().
3349 *
3350 * Some operations don't require all steps to be performed.
3351 * More precisely:
3352 *
3353 * - CPU instance creation (instance_init) will run only CPU
3354 * model loading. CPU expansion can't run at instance_init-time
3355 * because host/accelerator data may be not available yet.
3356 * - CPU realization will perform both CPU model expansion and CPUID
3357 * filtering, and return an error in case one of them fails.
3358 * - query-cpu-definitions needs to run all 3 steps. It needs
3359 * to run CPUID filtering, as the 'unavailable-features'
3360 * field is set based on the filtering results.
3361 * - The query-cpu-model-expansion QMP command only needs to run
3362 * CPU model loading and CPU expansion. It should not filter
3363 * any CPUID data based on host capabilities.
3364 */
3365
3366/* Expand CPU configuration data, based on configured features
3367 * and host/accelerator capabilities when appropriate.
3368 */
3369static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 3370{
b34d12d1 3371 CPUX86State *env = &cpu->env;
dc15c051 3372 FeatureWord w;
2fae0d96 3373 GList *l;
41f3d4d6 3374 Error *local_err = NULL;
9886e834 3375
44bd8e53 3376 /*TODO: cpu->max_features incorrectly overwrites features
dc15c051
IM		 3377 * set using "feat=on|off". Once we fix this, we can convert
3378 * plus_features & minus_features to global properties
3379 * inside x86_cpu_parse_featurestr() too.
3380 */
44bd8e53 3381 if (cpu->max_features) {
dc15c051
IM		 3382 for (w = 0; w < FEATURE_WORDS; w++) {
3383 env->features[w] =
3384 x86_cpu_get_supported_feature_word(w, cpu->migratable);
3385 }
3386 }
3387
2fae0d96
EH		 3388 for (l = plus_features; l; l = l->next) {
3389 const char *prop = l->data;
3390 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
3391 if (local_err) {
3392 goto out;
3393 }
3394 }
3395
3396 for (l = minus_features; l; l = l->next) {
3397 const char *prop = l->data;
3398 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
3399 if (local_err) {
3400 goto out;
3401 }
dc15c051
IM		 3402 }
3403
aec661de
EH		 3404 if (!kvm_enabled() || !cpu->expose_kvm) {
3405 env->features[FEAT_KVM] = 0;
3406 }
3407
2ca8a8be 3408 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 3409
3410 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3411 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
3412 if (cpu->full_cpuid_auto_level) {
3413 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
3414 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
3415 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
3416 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
3417 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
3418 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
3419 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
3420 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
3421 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
3422 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 3423 /* SVM requires CPUID[0x8000000A] */
3424 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
3425 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
3426 }
c39c0edf
EH		 3427 }
3428
3429 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3430 if (env->cpuid_level == UINT32_MAX) {
3431 env->cpuid_level = env->cpuid_min_level;
3432 }
3433 if (env->cpuid_xlevel == UINT32_MAX) {
3434 env->cpuid_xlevel = env->cpuid_min_xlevel;
3435 }
3436 if (env->cpuid_xlevel2 == UINT32_MAX) {
3437 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 3438 }
7a059953 3439
41f3d4d6
EH		 3440out:
3441 if (local_err != NULL) {
3442 error_propagate(errp, local_err);
3443 }
3444}
3445
b8d834a0
EH		 3446/*
3447 * Finishes initialization of CPUID data, filters CPU feature
3448 * words based on host availability of each feature.
3449 *
3450 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
3451 */
3452static int x86_cpu_filter_features(X86CPU *cpu)
3453{
3454 CPUX86State *env = &cpu->env;
3455 FeatureWord w;
3456 int rv = 0;
3457
3458 for (w = 0; w < FEATURE_WORDS; w++) {
3459 uint32_t host_feat =
3460 x86_cpu_get_supported_feature_word(w, false);
3461 uint32_t requested_features = env->features[w];
3462 env->features[w] &= host_feat;
3463 cpu->filtered_features[w] = requested_features & ~env->features[w];
3464 if (cpu->filtered_features[w]) {
3465 rv = 1;
3466 }
3467 }
3468
3469 return rv;
3470}
3471
41f3d4d6
EH		 3472#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3473 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3474 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3475#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3476 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3477 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
3478static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
3479{
3480 CPUState *cs = CPU(dev);
3481 X86CPU *cpu = X86_CPU(dev);
3482 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3483 CPUX86State *env = &cpu->env;
3484 Error *local_err = NULL;
3485 static bool ht_warned;
3486
3487 if (xcc->kvm_required && !kvm_enabled()) {
3488 char *name = x86_cpu_class_get_model_name(xcc);
3489 error_setg(&local_err, "CPU model '%s' requires KVM", name);
3490 g_free(name);
3491 goto out;
3492 }
3493
3494 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
3495 error_setg(errp, "apic-id property was not initialized properly");
3496 return;
3497 }
3498
b8d834a0 3499 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 3500 if (local_err) {
3501 goto out;
3502 }
3503
8ca30e86
EH		 3504 if (x86_cpu_filter_features(cpu) &&
3505 (cpu->check_cpuid || cpu->enforce_cpuid)) {
3506 x86_cpu_report_filtered_features(cpu);
3507 if (cpu->enforce_cpuid) {
3508 error_setg(&local_err,
3509 kvm_enabled() ?
3510 "Host doesn't support requested features" :
3511 "TCG doesn't support requested features");
3512 goto out;
3513 }
9997cf7b
EH		 3514 }
3515
9b15cd9e
IM		 3516 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3517 * CPUID[1].EDX.
3518 */
e48638fd 3519 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 3520 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3521 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 3522 & CPUID_EXT2_AMD_ALIASES);
3523 }
3524
11f6fee5
DDAG		 3525 /* For 64bit systems think about the number of physical bits to present.
3526 * ideally this should be the same as the host; anything other than matching
3527 * the host can cause incorrect guest behaviour.
3528 * QEMU used to pick the magic value of 40 bits that corresponds to
3529 * consumer AMD devices but nothing else.
3530 */
af45907a 3531 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a 3532 if (kvm_enabled()) {
11f6fee5
DDAG		 3533 uint32_t host_phys_bits = x86_host_phys_bits();
3534 static bool warned;
3535
3536 if (cpu->host_phys_bits) {
3537 /* The user asked for us to use the host physical bits */
3538 cpu->phys_bits = host_phys_bits;
3539 }
3540
3541 /* Print a warning if the user set it to a value that's not the
3542 * host value.
3543 */
3544 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3545 !warned) {
3546 error_report("Warning: Host physical bits (%u)"
3547 " does not match phys-bits property (%u)",
3548 host_phys_bits, cpu->phys_bits);
3549 warned = true;
3550 }
3551
3552 if (cpu->phys_bits &&
3553 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3554 cpu->phys_bits < 32)) {
af45907a
DDAG		 3555 error_setg(errp, "phys-bits should be between 32 and %u "
3556 " (but is %u)",
3557 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3558 return;
3559 }
3560 } else {
11f6fee5 3561 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 3562 error_setg(errp, "TCG only supports phys-bits=%u",
3563 TCG_PHYS_ADDR_BITS);
3564 return;
3565 }
3566 }
11f6fee5
DDAG		 3567 /* 0 means it was not explicitly set by the user (or by machine
3568 * compat_props or by the host code above). In this case, the default
3569 * is the value used by TCG (40).
3570 */
3571 if (cpu->phys_bits == 0) {
3572 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3573 }
af45907a
DDAG		 3574 } else {
3575 /* For 32 bit systems don't use the user set value, but keep
3576 * phys_bits consistent with what we tell the guest.
3577 */
3578 if (cpu->phys_bits != 0) {
3579 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3580 return;
3581 }
fefb41bf 3582
af45907a
DDAG		 3583 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3584 cpu->phys_bits = 36;
3585 } else {
3586 cpu->phys_bits = 32;
3587 }
3588 }
ce5b1bbf
LV		 3589 cpu_exec_realizefn(cs, &local_err);
3590 if (local_err != NULL) {
3591 error_propagate(errp, local_err);
3592 return;
3593 }
42ecabaa 3594
57f2453a
EH		 3595 if (tcg_enabled()) {
3596 tcg_x86_init();
3597 }
3598
65dee380
IM		 3599#ifndef CONFIG_USER_ONLY
3600 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 3601
0514ef2f 3602 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 3603 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 3604 if (local_err != NULL) {
4dc1f449 3605 goto out;
bdeec802
IM		 3606 }
3607 }
65dee380
IM		 3608#endif
3609
7a059953 3610 mce_init(cpu);
2001d0cd
PB		 3611
3612#ifndef CONFIG_USER_ONLY
3613 if (tcg_enabled()) {
56943e8c
PM		 3614 AddressSpace *newas = g_new(AddressSpace, 1);
3615
f809c605 3616 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 3617 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 3618
3619 /* Outer container... */
3620 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 3621 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 3622
3623 /* ... with two regions inside: normal system memory with low
3624 * priority, and...
3625 */
3626 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3627 get_system_memory(), 0, ~0ull);
3628 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3629 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 3630 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 3631 cs->num_ases = 1;
56943e8c 3632 cpu_address_space_init(cs, newas, 0);
f809c605
PB		 3633
3634 /* ... SMRAM with higher priority, linked from /machine/smram. */
3635 cpu->machine_done.notify = x86_cpu_machine_done;
3636 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 3637 }
3638#endif
3639
14a10fc3 3640 qemu_init_vcpu(cs);
d3c64d6a 3641
e48638fd
WH		 3642 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3643 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3644 * based on inputs (sockets,cores,threads), it is still better to gives
3645 * users a warning.
3646 *
3647 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3648 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3649 */
3650 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3651 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3652 " -smp options properly.");
3653 ht_warned = true;
3654 }
3655
d3c64d6a
IM		 3656 x86_cpu_apic_realize(cpu, &local_err);
3657 if (local_err != NULL) {
3658 goto out;
3659 }
14a10fc3 3660 cpu_reset(cs);
2b6f294c 3661
4dc1f449 3662 xcc->parent_realize(dev, &local_err);
2001d0cd 3663
4dc1f449
IM		 3664out:
3665 if (local_err != NULL) {
3666 error_propagate(errp, local_err);
3667 return;
3668 }
7a059953
AF		 3669}
3670
c884776e
IM		 3671static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3672{
3673 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 3674 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3675 Error *local_err = NULL;
c884776e
IM		 3676
3677#ifndef CONFIG_USER_ONLY
3678 cpu_remove_sync(CPU(dev));
3679 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3680#endif
3681
3682 if (cpu->apic_state) {
3683 object_unparent(OBJECT(cpu->apic_state));
3684 cpu->apic_state = NULL;
3685 }
7bbc124e
LV		 3686
3687 xcc->parent_unrealize(dev, &local_err);
3688 if (local_err != NULL) {
3689 error_propagate(errp, local_err);
3690 return;
3691 }
c884776e
IM		 3692}
3693
38e5c119
EH		 3694typedef struct BitProperty {
3695 uint32_t *ptr;
3696 uint32_t mask;
3697} BitProperty;
3698
d7bce999
EB		 3699static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3700 void *opaque, Error **errp)
38e5c119
EH		 3701{
3702 BitProperty *fp = opaque;
3703 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 3704 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3705}
3706
d7bce999
EB		 3707static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3708 void *opaque, Error **errp)
38e5c119
EH		 3709{
3710 DeviceState *dev = DEVICE(obj);
3711 BitProperty *fp = opaque;
3712 Error *local_err = NULL;
3713 bool value;
3714
3715 if (dev->realized) {
3716 qdev_prop_set_after_realize(dev, name, errp);
3717 return;
3718 }
3719
51e72bc1 3720 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3721 if (local_err) {
3722 error_propagate(errp, local_err);
3723 return;
3724 }
3725
3726 if (value) {
3727 *fp->ptr |= fp->mask;
3728 } else {
3729 *fp->ptr &= ~fp->mask;
3730 }
3731}
3732
3733static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3734 void *opaque)
3735{
3736 BitProperty *prop = opaque;
3737 g_free(prop);
3738}
3739
3740/* Register a boolean property to get/set a single bit in a uint32_t field.
3741 *
3742 * The same property name can be registered multiple times to make it affect
3743 * multiple bits in the same FeatureWord. In that case, the getter will return
3744 * true only if all bits are set.
3745 */
3746static void x86_cpu_register_bit_prop(X86CPU *cpu,
3747 const char *prop_name,
3748 uint32_t *field,
3749 int bitnr)
3750{
3751 BitProperty *fp;
3752 ObjectProperty *op;
3753 uint32_t mask = (1UL << bitnr);
3754
3755 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3756 if (op) {
3757 fp = op->opaque;
3758 assert(fp->ptr == field);
3759 fp->mask |= mask;
3760 } else {
3761 fp = g_new0(BitProperty, 1);
3762 fp->ptr = field;
3763 fp->mask = mask;
3764 object_property_add(OBJECT(cpu), prop_name, "bool",
3765 x86_cpu_get_bit_prop,
3766 x86_cpu_set_bit_prop,
3767 x86_cpu_release_bit_prop, fp, &error_abort);
3768 }
3769}
3770
3771static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3772 FeatureWord w,
3773 int bitnr)
3774{
38e5c119 3775 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 3776 const char *name = fi->feat_names[bitnr];
38e5c119 3777
16d2fcaa 3778 if (!name) {
38e5c119
EH		 3779 return;
3780 }
3781
fc7dfd20
EH		 3782 /* Property names should use "-" instead of "_".
3783 * Old names containing underscores are registered as aliases
3784 * using object_property_add_alias()
3785 */
16d2fcaa
EH		 3786 assert(!strchr(name, '_'));
3787 /* aliases don't use "|" delimiters anymore, they are registered
3788 * manually using object_property_add_alias() */
3789 assert(!strchr(name, '|'));
3790 x86_cpu_register_bit_prop(cpu, name, &cpu->env.features[w], bitnr);
38e5c119
EH		 3791}
3792
d187e08d
AN		 3793static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
3794{
3795 X86CPU *cpu = X86_CPU(cs);
3796 CPUX86State *env = &cpu->env;
3797 GuestPanicInformation *panic_info = NULL;
3798
3799 if (env->features[FEAT_HYPERV_EDX] & HV_X64_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 3800 panic_info = g_malloc0(sizeof(GuestPanicInformation));
3801
e8ed97a6 3802 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d
AN		 3803
3804 assert(HV_X64_MSR_CRASH_PARAMS >= 5);
e8ed97a6
AN		 3805 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
3806 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
3807 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
3808 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
3809 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 3810 }
3811
3812 return panic_info;
3813}
3814static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
3815 const char *name, void *opaque,
3816 Error **errp)
3817{
3818 CPUState *cs = CPU(obj);
3819 GuestPanicInformation *panic_info;
3820
3821 if (!cs->crash_occurred) {
3822 error_setg(errp, "No crash occured");
3823 return;
3824 }
3825
3826 panic_info = x86_cpu_get_crash_info(cs);
3827 if (panic_info == NULL) {
3828 error_setg(errp, "No crash information");
3829 return;
3830 }
3831
3832 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
3833 errp);
3834 qapi_free_GuestPanicInformation(panic_info);
3835}
3836
de024815
AF		 3837static void x86_cpu_initfn(Object *obj)
3838{
55e5c285 3839 CPUState *cs = CPU(obj);
de024815 3840 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3841 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3842 CPUX86State *env = &cpu->env;
38e5c119 3843 FeatureWord w;
de024815 3844
c05efcb1 3845 cs->env_ptr = env;
71ad61d3
AF		 3846
3847 object_property_add(obj, "family", "int",
95b8519d 3848 x86_cpuid_version_get_family,
71ad61d3 3849 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3850 object_property_add(obj, "model", "int",
67e30c83 3851 x86_cpuid_version_get_model,
c5291a4f 3852 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3853 object_property_add(obj, "stepping", "int",
35112e41 3854 x86_cpuid_version_get_stepping,
036e2222 3855 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3856 object_property_add_str(obj, "vendor",
3857 x86_cpuid_get_vendor,
3858 x86_cpuid_set_vendor, NULL);
938d4c25 3859 object_property_add_str(obj, "model-id",
63e886eb 3860 x86_cpuid_get_model_id,
938d4c25 3861 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3862 object_property_add(obj, "tsc-frequency", "int",
3863 x86_cpuid_get_tsc_freq,
3864 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 3865 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3866 x86_cpu_get_feature_words,
7e5292b5
EH		 3867 NULL, NULL, (void *)env->features, NULL);
3868 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3869 x86_cpu_get_feature_words,
3870 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3871
d187e08d
AN		 3872 object_property_add(obj, "crash-information", "GuestPanicInformation",
3873 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
3874
92067bf4 3875 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3876
38e5c119
EH		 3877 for (w = 0; w < FEATURE_WORDS; w++) {
3878 int bitnr;
3879
3880 for (bitnr = 0; bitnr < 32; bitnr++) {
3881 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3882 }
3883 }
3884
16d2fcaa
EH		 3885 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
3886 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
3887 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
3888 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
3889 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
3890 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
3891 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
3892
54b8dc7c
EH		 3893 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
3894 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
3895 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
3896 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
3897 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
3898 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
3899 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
3900 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
3901 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
3902 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
3903 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
3904 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
3905 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
3906 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
3907 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
3908 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
3909 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
3910 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
3911 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
3912 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
3913 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
3914
0bacd8b3
EH		 3915 if (xcc->cpu_def) {
3916 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3917 }
de024815
AF		 3918}
3919
997395d3
IM		 3920static int64_t x86_cpu_get_arch_id(CPUState *cs)
3921{
3922 X86CPU *cpu = X86_CPU(cs);
997395d3 3923
7e72a45c 3924 return cpu->apic_id;
997395d3
IM		 3925}
3926
444d5590
AF		 3927static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3928{
3929 X86CPU *cpu = X86_CPU(cs);
3930
3931 return cpu->env.cr[0] & CR0_PG_MASK;
3932}
3933
f45748f1
AF		 3934static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3935{
3936 X86CPU *cpu = X86_CPU(cs);
3937
3938 cpu->env.eip = value;
3939}
3940
bdf7ae5b
AF		 3941static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3942{
3943 X86CPU *cpu = X86_CPU(cs);
3944
3945 cpu->env.eip = tb->pc - tb->cs_base;
3946}
3947
8c2e1b00
AF		 3948static bool x86_cpu_has_work(CPUState *cs)
3949{
3950 X86CPU *cpu = X86_CPU(cs);
3951 CPUX86State *env = &cpu->env;
3952
6220e900
PD		 3953 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3954 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3955 (env->eflags & IF_MASK)) ||
3956 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3957 CPU_INTERRUPT_INIT |
3958 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3959 CPU_INTERRUPT_MCE)) ||
3960 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3961 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3962}
3963
9337e3b6 3964static Property x86_cpu_properties[] = {
2da00e31
IM		 3965#ifdef CONFIG_USER_ONLY
3966 /* apic_id = 0 by default for *-user, see commit 9886e834 */
3967 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 3968 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
3969 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
3970 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 3971#else
3972 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 3973 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
3974 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
3975 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 3976#endif
9337e3b6 3977 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3978 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3979 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3980 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3981 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3982 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3983 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3984 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3985 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3986 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3987 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3988 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3989 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3990 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 3991 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 3992 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 3993 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 3994 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
3995 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
3996 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
3997 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
3998 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
3999 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4000 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 4001 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 4002 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 4003 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 4004 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 4005 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
4006 false),
0b564e6f 4007 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
9337e3b6
EH		 4008 DEFINE_PROP_END_OF_LIST()
4009};
4010
5fd2087a
AF		 4011static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
4012{
4013 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4014 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 4015 DeviceClass *dc = DEVICE_CLASS(oc);
4016
4017 xcc->parent_realize = dc->realize;
7bbc124e 4018 xcc->parent_unrealize = dc->unrealize;
2b6f294c 4019 dc->realize = x86_cpu_realizefn;
c884776e 4020 dc->unrealize = x86_cpu_unrealizefn;
9337e3b6 4021 dc->props = x86_cpu_properties;
5fd2087a
AF		 4022
4023 xcc->parent_reset = cc->reset;
4024 cc->reset = x86_cpu_reset;
91b1df8c 4025 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 4026
500050d1 4027 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 4028 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 4029 cc->has_work = x86_cpu_has_work;
97a8ea5a 4030 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 4031 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 4032 cc->dump_state = x86_cpu_dump_state;
c86f106b 4033 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 4034 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 4035 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 4036 cc->gdb_read_register = x86_cpu_gdb_read_register;
4037 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 4038 cc->get_arch_id = x86_cpu_get_arch_id;
4039 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 4040#ifdef CONFIG_USER_ONLY
4041 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
4042#else
a23bbfda 4043 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 4044 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 4045 cc->write_elf64_note = x86_cpu_write_elf64_note;
4046 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
4047 cc->write_elf32_note = x86_cpu_write_elf32_note;
4048 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 4049 cc->vmsd = &vmstate_x86_cpu;
c72bf468 4050#endif
175cad36
DE		 4051 /* CPU_NB_REGS * 2 = general regs + xmm regs
4052 * 25 = eip, eflags, 6 seg regs, st[0-7], fctrl,...,fop, mxcsr.
4053 */
a0e372f0 4054 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 4055#ifndef CONFIG_USER_ONLY
4056 cc->debug_excp_handler = breakpoint_handler;
4057#endif
374e0cd4
RH		 4058 cc->cpu_exec_enter = x86_cpu_exec_enter;
4059 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27 4060
edd12111 4061 dc->cannot_instantiate_with_device_add_yet = false;
5fd2087a
AF		 4062}
4063
4064static const TypeInfo x86_cpu_type_info = {
4065 .name = TYPE_X86_CPU,
4066 .parent = TYPE_CPU,
4067 .instance_size = sizeof(X86CPU),
de024815 4068 .instance_init = x86_cpu_initfn,
d940ee9b 4069 .abstract = true,
5fd2087a
AF		 4070 .class_size = sizeof(X86CPUClass),
4071 .class_init = x86_cpu_common_class_init,
4072};
4073
5adbed30
EH		 4074
4075/* "base" CPU model, used by query-cpu-model-expansion */
4076static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
4077{
4078 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4079
4080 xcc->static_model = true;
4081 xcc->migration_safe = true;
4082 xcc->model_description = "base CPU model type with no features enabled";
4083 xcc->ordering = 8;
4084}
4085
4086static const TypeInfo x86_base_cpu_type_info = {
4087 .name = X86_CPU_TYPE_NAME("base"),
4088 .parent = TYPE_X86_CPU,
4089 .class_init = x86_cpu_base_class_init,
4090};
4091
5fd2087a
AF		 4092static void x86_cpu_register_types(void)
4093{
d940ee9b
EH		 4094 int i;
4095
5fd2087a 4096 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 4097 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
4098 x86_register_cpudef_type(&builtin_x86_defs[i]);
4099 }
c62f2630 4100 type_register_static(&max_x86_cpu_type_info);
5adbed30 4101 type_register_static(&x86_base_cpu_type_info);
d940ee9b
EH		 4102#ifdef CONFIG_KVM
4103 type_register_static(&host_x86_cpu_type_info);
4104#endif
5fd2087a
AF		 4105}
4106
4107type_init(x86_cpu_register_types)
QEMU mirror