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target/i386: Use host_vendor_fms() in max_x86_cpu_initfn()
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
01b2ffce 32#include "qapi/qmp/types.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
f99fd7ca 37#include "qom/qom-qobject.h"
9c17d615 38#include "sysemu/arch_init.h"
71ad61d3 39
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
5232d00a 46#include "hw/i386/topology.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
2001d0cd 48#include "exec/address-spaces.h"
741da0d3 49#include "hw/hw.h"
0d09e41a 50#include "hw/xen/xen.h"
0d09e41a 51#include "hw/i386/apic_internal.h"
bdeec802
IM		 52#endif
53
5e891bf8
EH		 54
55/* Cache topology CPUID constants: */
56
57/* CPUID Leaf 2 Descriptors */
58
59#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
60#define CPUID_2_L1I_32KB_8WAY_64B 0x30
61#define CPUID_2_L2_2MB_8WAY_64B 0x7d
14c985cf 62#define CPUID_2_L3_16MB_16WAY_64B 0x4d
5e891bf8
EH		 63
64
65/* CPUID Leaf 4 constants: */
66
67/* EAX: */
68#define CPUID_4_TYPE_DCACHE 1
69#define CPUID_4_TYPE_ICACHE 2
70#define CPUID_4_TYPE_UNIFIED 3
71
72#define CPUID_4_LEVEL(l) ((l) << 5)
73
74#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
75#define CPUID_4_FULLY_ASSOC (1 << 9)
76
77/* EDX: */
78#define CPUID_4_NO_INVD_SHARING (1 << 0)
79#define CPUID_4_INCLUSIVE (1 << 1)
80#define CPUID_4_COMPLEX_IDX (1 << 2)
81
82#define ASSOC_FULL 0xFF
83
84/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
85#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
86 a == 2 ? 0x2 : \
87 a == 4 ? 0x4 : \
88 a == 8 ? 0x6 : \
89 a == 16 ? 0x8 : \
90 a == 32 ? 0xA : \
91 a == 48 ? 0xB : \
92 a == 64 ? 0xC : \
93 a == 96 ? 0xD : \
94 a == 128 ? 0xE : \
95 a == ASSOC_FULL ? 0xF : \
96 0 /* invalid value */)
97
98
99/* Definitions of the hardcoded cache entries we expose: */
100
101/* L1 data cache: */
102#define L1D_LINE_SIZE 64
103#define L1D_ASSOCIATIVITY 8
104#define L1D_SETS 64
105#define L1D_PARTITIONS 1
106/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
107#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
108/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
109#define L1D_LINES_PER_TAG 1
110#define L1D_SIZE_KB_AMD 64
111#define L1D_ASSOCIATIVITY_AMD 2
112
113/* L1 instruction cache: */
114#define L1I_LINE_SIZE 64
115#define L1I_ASSOCIATIVITY 8
116#define L1I_SETS 64
117#define L1I_PARTITIONS 1
118/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
119#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
120/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
121#define L1I_LINES_PER_TAG 1
122#define L1I_SIZE_KB_AMD 64
123#define L1I_ASSOCIATIVITY_AMD 2
124
125/* Level 2 unified cache: */
126#define L2_LINE_SIZE 64
127#define L2_ASSOCIATIVITY 16
128#define L2_SETS 4096
129#define L2_PARTITIONS 1
130/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
131/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
132#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
133/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
134#define L2_LINES_PER_TAG 1
135#define L2_SIZE_KB_AMD 512
136
14c985cf 137/* Level 3 unified cache: */
5e891bf8
EH		 138#define L3_SIZE_KB 0 /* disabled */
139#define L3_ASSOCIATIVITY 0 /* disabled */
140#define L3_LINES_PER_TAG 0 /* disabled */
141#define L3_LINE_SIZE 0 /* disabled */
14c985cf
LM		 142#define L3_N_LINE_SIZE 64
143#define L3_N_ASSOCIATIVITY 16
144#define L3_N_SETS 16384
145#define L3_N_PARTITIONS 1
146#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
147#define L3_N_LINES_PER_TAG 1
148#define L3_N_SIZE_KB_AMD 16384
5e891bf8
EH		 149
150/* TLB definitions: */
151
152#define L1_DTLB_2M_ASSOC 1
153#define L1_DTLB_2M_ENTRIES 255
154#define L1_DTLB_4K_ASSOC 1
155#define L1_DTLB_4K_ENTRIES 255
156
157#define L1_ITLB_2M_ASSOC 1
158#define L1_ITLB_2M_ENTRIES 255
159#define L1_ITLB_4K_ASSOC 1
160#define L1_ITLB_4K_ENTRIES 255
161
162#define L2_DTLB_2M_ASSOC 0 /* disabled */
163#define L2_DTLB_2M_ENTRIES 0 /* disabled */
164#define L2_DTLB_4K_ASSOC 4
165#define L2_DTLB_4K_ENTRIES 512
166
167#define L2_ITLB_2M_ASSOC 0 /* disabled */
168#define L2_ITLB_2M_ENTRIES 0 /* disabled */
169#define L2_ITLB_4K_ASSOC 4
170#define L2_ITLB_4K_ENTRIES 512
171
172
173
99b88a17
IM		 174static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
175 uint32_t vendor2, uint32_t vendor3)
176{
177 int i;
178 for (i = 0; i < 4; i++) {
179 dst[i] = vendor1 >> (8 * i);
180 dst[i + 4] = vendor2 >> (8 * i);
181 dst[i + 8] = vendor3 >> (8 * i);
182 }
183 dst[CPUID_VENDOR_SZ] = '\0';
184}
185
621626ce
EH		 186#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
187#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
188 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
189#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
190 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
191 CPUID_PSE36 | CPUID_FXSR)
192#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
193#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
194 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
195 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
196 CPUID_PAE | CPUID_SEP | CPUID_APIC)
197
198#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
199 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
200 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
201 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 202 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 203 /* partly implemented:
204 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
205 /* missing:
206 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
207#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
208 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
209 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 210 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 211 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
212 /* missing:
213 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
214 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
215 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 216 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
217 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 218
219#ifdef TARGET_X86_64
220#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
221#else
222#define TCG_EXT2_X86_64_FEATURES 0
223#endif
224
225#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
226 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
227 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
228 TCG_EXT2_X86_64_FEATURES)
229#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
230 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
231#define TCG_EXT4_FEATURES 0
232#define TCG_SVM_FEATURES 0
233#define TCG_KVM_FEATURES 0
234#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 235 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
236 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 237 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
238 CPUID_7_0_EBX_ERMS)
621626ce 239 /* missing:
07929f2a 240 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 241 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 242 CPUID_7_0_EBX_RDSEED */
6c7c3c21
KS		 243#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
244 CPUID_7_0_ECX_LA57)
95ea69fb 245#define TCG_7_0_EDX_FEATURES 0
303752a9 246#define TCG_APM_FEATURES 0
28b8e4d0 247#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 248#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
249 /* missing:
250 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 251
5ef57876 252typedef struct FeatureWordInfo {
2d5312da
EH		 253 /* feature flags names are taken from "Intel Processor Identification and
254 * the CPUID Instruction" and AMD's "CPUID Specification".
255 * In cases of disagreement between feature naming conventions,
256 * aliases may be added.
257 */
258 const char *feat_names[32];
04d104b6
EH		 259 uint32_t cpuid_eax; /* Input EAX for CPUID */
260 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
261 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
262 int cpuid_reg; /* output register (R_* constant) */
37ce3522 263 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 264 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 265 uint32_t migratable_flags; /* Feature flags known to be migratable */
5ef57876
EH		 266} FeatureWordInfo;
267
268static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 269 [FEAT_1_EDX] = {
2d5312da
EH		 270 .feat_names = {
271 "fpu", "vme", "de", "pse",
272 "tsc", "msr", "pae", "mce",
273 "cx8", "apic", NULL, "sep",
274 "mtrr", "pge", "mca", "cmov",
275 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
276 NULL, "ds" /* Intel dts */, "acpi", "mmx",
277 "fxsr", "sse", "sse2", "ss",
278 "ht" /* Intel htt */, "tm", "ia64", "pbe",
279 },
bffd67b0 280 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 281 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 282 },
283 [FEAT_1_ECX] = {
2d5312da 284 .feat_names = {
16d2fcaa 285 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 286 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 287 "tm2", "ssse3", "cid", NULL,
288 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 289 NULL, "pcid", "dca", "sse4.1",
290 "sse4.2", "x2apic", "movbe", "popcnt",
2d5312da
EH		 291 "tsc-deadline", "aes", "xsave", "osxsave",
292 "avx", "f16c", "rdrand", "hypervisor",
293 },
bffd67b0 294 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 295 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 296 },
2d5312da
EH		 297 /* Feature names that are already defined on feature_name[] but
298 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
299 * names on feat_names below. They are copied automatically
300 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
301 */
bffd67b0 302 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 303 .feat_names = {
304 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
305 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
306 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
307 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
308 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 309 "nx", NULL, "mmxext", NULL /* mmx */,
310 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
311 NULL, "lm", "3dnowext", "3dnow",
2d5312da 312 },
bffd67b0 313 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 314 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 315 },
316 [FEAT_8000_0001_ECX] = {
2d5312da 317 .feat_names = {
fc7dfd20 318 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 319 "cr8legacy", "abm", "sse4a", "misalignsse",
320 "3dnowprefetch", "osvw", "ibs", "xop",
321 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 322 "fma4", "tce", NULL, "nodeid-msr",
323 NULL, "tbm", "topoext", "perfctr-core",
324 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 325 NULL, NULL, NULL, NULL,
326 },
bffd67b0 327 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 328 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 329 },
89e49c8b 330 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 331 .feat_names = {
332 NULL, NULL, "xstore", "xstore-en",
333 NULL, NULL, "xcrypt", "xcrypt-en",
334 "ace2", "ace2-en", "phe", "phe-en",
335 "pmm", "pmm-en", NULL, NULL,
336 NULL, NULL, NULL, NULL,
337 NULL, NULL, NULL, NULL,
338 NULL, NULL, NULL, NULL,
339 NULL, NULL, NULL, NULL,
340 },
89e49c8b 341 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 342 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 343 },
bffd67b0 344 [FEAT_KVM] = {
2d5312da 345 .feat_names = {
fc7dfd20
EH		 346 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
347 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
2d5312da
EH		 348 NULL, NULL, NULL, NULL,
349 NULL, NULL, NULL, NULL,
350 NULL, NULL, NULL, NULL,
351 NULL, NULL, NULL, NULL,
352 "kvmclock-stable-bit", NULL, NULL, NULL,
353 NULL, NULL, NULL, NULL,
354 },
bffd67b0 355 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 356 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 357 },
c35bd19a 358 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 359 .feat_names = {
360 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
361 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
362 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
363 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
364 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
365 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
366 NULL, NULL, NULL, NULL,
367 NULL, NULL, NULL, NULL,
368 NULL, NULL, NULL, NULL,
369 NULL, NULL, NULL, NULL,
370 NULL, NULL, NULL, NULL,
371 },
c35bd19a
EY		 372 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
373 },
374 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 375 .feat_names = {
376 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
377 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
378 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
379 NULL /* hv_create_port */, NULL /* hv_connect_port */,
380 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
381 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
382 NULL, NULL,
383 NULL, NULL, NULL, NULL,
384 NULL, NULL, NULL, NULL,
385 NULL, NULL, NULL, NULL,
386 NULL, NULL, NULL, NULL,
387 },
c35bd19a
EY		 388 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
389 },
390 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 391 .feat_names = {
392 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
393 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
394 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
395 NULL, NULL,
396 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
397 NULL, NULL, NULL, NULL,
398 NULL, NULL, NULL, NULL,
399 NULL, NULL, NULL, NULL,
400 NULL, NULL, NULL, NULL,
401 NULL, NULL, NULL, NULL,
402 },
c35bd19a
EY		 403 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
404 },
bffd67b0 405 [FEAT_SVM] = {
2d5312da 406 .feat_names = {
fc7dfd20
EH		 407 "npt", "lbrv", "svm-lock", "nrip-save",
408 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
409 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 410 "pfthreshold", NULL, NULL, NULL,
411 NULL, NULL, NULL, NULL,
412 NULL, NULL, NULL, NULL,
413 NULL, NULL, NULL, NULL,
414 NULL, NULL, NULL, NULL,
415 },
bffd67b0 416 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 417 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 418 },
419 [FEAT_7_0_EBX] = {
2d5312da 420 .feat_names = {
fc7dfd20 421 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 422 "hle", "avx2", NULL, "smep",
423 "bmi2", "erms", "invpcid", "rtm",
424 NULL, NULL, "mpx", NULL,
425 "avx512f", "avx512dq", "rdseed", "adx",
426 "smap", "avx512ifma", "pcommit", "clflushopt",
427 "clwb", NULL, "avx512pf", "avx512er",
638cbd45 428 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 429 },
04d104b6
EH		 430 .cpuid_eax = 7,
431 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
432 .cpuid_reg = R_EBX,
37ce3522 433 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 434 },
f74eefe0 435 [FEAT_7_0_ECX] = {
2d5312da
EH		 436 .feat_names = {
437 NULL, "avx512vbmi", "umip", "pku",
438 "ospke", NULL, NULL, NULL,
439 NULL, NULL, NULL, NULL,
f7754377 440 NULL, NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 441 "la57", NULL, NULL, NULL,
2d5312da
EH		 442 NULL, NULL, "rdpid", NULL,
443 NULL, NULL, NULL, NULL,
444 NULL, NULL, NULL, NULL,
445 },
f74eefe0
HH		 446 .cpuid_eax = 7,
447 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
448 .cpuid_reg = R_ECX,
449 .tcg_features = TCG_7_0_ECX_FEATURES,
450 },
95ea69fb
LK		 451 [FEAT_7_0_EDX] = {
452 .feat_names = {
453 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
454 NULL, NULL, NULL, NULL,
455 NULL, NULL, NULL, NULL,
456 NULL, NULL, NULL, NULL,
457 NULL, NULL, NULL, NULL,
458 NULL, NULL, NULL, NULL,
459 NULL, NULL, NULL, NULL,
460 NULL, NULL, NULL, NULL,
461 },
462 .cpuid_eax = 7,
463 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
464 .cpuid_reg = R_EDX,
465 .tcg_features = TCG_7_0_EDX_FEATURES,
466 },
303752a9 467 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 468 .feat_names = {
469 NULL, NULL, NULL, NULL,
470 NULL, NULL, NULL, NULL,
471 "invtsc", NULL, NULL, NULL,
472 NULL, NULL, NULL, NULL,
473 NULL, NULL, NULL, NULL,
474 NULL, NULL, NULL, NULL,
475 NULL, NULL, NULL, NULL,
476 NULL, NULL, NULL, NULL,
477 },
303752a9
MT		 478 .cpuid_eax = 0x80000007,
479 .cpuid_reg = R_EDX,
480 .tcg_features = TCG_APM_FEATURES,
481 .unmigratable_flags = CPUID_APM_INVTSC,
482 },
0bb0b2d2 483 [FEAT_XSAVE] = {
2d5312da
EH		 484 .feat_names = {
485 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
486 NULL, NULL, NULL, NULL,
487 NULL, NULL, NULL, NULL,
488 NULL, NULL, NULL, NULL,
489 NULL, NULL, NULL, NULL,
490 NULL, NULL, NULL, NULL,
491 NULL, NULL, NULL, NULL,
492 NULL, NULL, NULL, NULL,
493 },
0bb0b2d2
PB		 494 .cpuid_eax = 0xd,
495 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
496 .cpuid_reg = R_EAX,
c9cfe8f9 497 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 498 },
28b8e4d0 499 [FEAT_6_EAX] = {
2d5312da
EH		 500 .feat_names = {
501 NULL, NULL, "arat", NULL,
502 NULL, NULL, NULL, NULL,
503 NULL, NULL, NULL, NULL,
504 NULL, NULL, NULL, NULL,
505 NULL, NULL, NULL, NULL,
506 NULL, NULL, NULL, NULL,
507 NULL, NULL, NULL, NULL,
508 NULL, NULL, NULL, NULL,
509 },
28b8e4d0
JK		 510 .cpuid_eax = 6, .cpuid_reg = R_EAX,
511 .tcg_features = TCG_6_EAX_FEATURES,
512 },
96193c22
EH		 513 [FEAT_XSAVE_COMP_LO] = {
514 .cpuid_eax = 0xD,
515 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
516 .cpuid_reg = R_EAX,
517 .tcg_features = ~0U,
6fb2fff7
EH		 518 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
519 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
520 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
521 XSTATE_PKRU_MASK,
96193c22
EH		 522 },
523 [FEAT_XSAVE_COMP_HI] = {
524 .cpuid_eax = 0xD,
525 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
526 .cpuid_reg = R_EDX,
527 .tcg_features = ~0U,
528 },
5ef57876
EH		 529};
530
8e8aba50
EH		 531typedef struct X86RegisterInfo32 {
532 /* Name of register */
533 const char *name;
534 /* QAPI enum value register */
535 X86CPURegister32 qapi_enum;
536} X86RegisterInfo32;
537
538#define REGISTER(reg) \
5d371f41 539 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 540static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 541 REGISTER(EAX),
542 REGISTER(ECX),
543 REGISTER(EDX),
544 REGISTER(EBX),
545 REGISTER(ESP),
546 REGISTER(EBP),
547 REGISTER(ESI),
548 REGISTER(EDI),
549};
550#undef REGISTER
551
3f32bd21
RH		 552typedef struct ExtSaveArea {
553 uint32_t feature, bits;
554 uint32_t offset, size;
555} ExtSaveArea;
556
557static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 558 [XSTATE_FP_BIT] = {
559 /* x87 FP state component is always enabled if XSAVE is supported */
560 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
561 /* x87 state is in the legacy region of the XSAVE area */
562 .offset = 0,
563 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
564 },
565 [XSTATE_SSE_BIT] = {
566 /* SSE state component is always enabled if XSAVE is supported */
567 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
568 /* SSE state is in the legacy region of the XSAVE area */
569 .offset = 0,
570 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
571 },
cfc3b074
PB		 572 [XSTATE_YMM_BIT] =
573 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 574 .offset = offsetof(X86XSaveArea, avx_state),
575 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 576 [XSTATE_BNDREGS_BIT] =
577 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 578 .offset = offsetof(X86XSaveArea, bndreg_state),
579 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 580 [XSTATE_BNDCSR_BIT] =
581 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 582 .offset = offsetof(X86XSaveArea, bndcsr_state),
583 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 584 [XSTATE_OPMASK_BIT] =
585 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 586 .offset = offsetof(X86XSaveArea, opmask_state),
587 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 588 [XSTATE_ZMM_Hi256_BIT] =
589 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 590 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
591 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 592 [XSTATE_Hi16_ZMM_BIT] =
593 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 594 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
595 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 596 [XSTATE_PKRU_BIT] =
597 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 598 .offset = offsetof(X86XSaveArea, pkru_state),
599 .size = sizeof(XSavePKRU) },
2560f19f 600};
8e8aba50 601
1fda6198
EH		 602static uint32_t xsave_area_size(uint64_t mask)
603{
604 int i;
e3c9022b 605 uint64_t ret = 0;
1fda6198 606
e3c9022b 607 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 608 const ExtSaveArea *esa = &x86_ext_save_areas[i];
609 if ((mask >> i) & 1) {
610 ret = MAX(ret, esa->offset + esa->size);
611 }
612 }
613 return ret;
614}
615
96193c22
EH		 616static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
617{
618 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
619 cpu->env.features[FEAT_XSAVE_COMP_LO];
620}
621
8b4beddc
EH		 622const char *get_register_name_32(unsigned int reg)
623{
31ccdde2 624 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 625 return NULL;
626 }
8e8aba50 627 return x86_reg_info_32[reg].name;
8b4beddc
EH		 628}
629
84f1b92f
EH		 630/*
631 * Returns the set of feature flags that are supported and migratable by
632 * QEMU, for a given FeatureWord.
633 */
634static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
635{
636 FeatureWordInfo *wi = &feature_word_info[w];
637 uint32_t r = 0;
638 int i;
639
640 for (i = 0; i < 32; i++) {
641 uint32_t f = 1U << i;
6fb2fff7
EH		 642
643 /* If the feature name is known, it is implicitly considered migratable,
644 * unless it is explicitly set in unmigratable_flags */
645 if ((wi->migratable_flags & f) ||
646 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
647 r |= f;
84f1b92f 648 }
84f1b92f
EH		 649 }
650 return r;
651}
652
bb44e0d1
JK		 653void host_cpuid(uint32_t function, uint32_t count,
654 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 655{
a1fd24af
AL		 656 uint32_t vec[4];
657
658#ifdef __x86_64__
659 asm volatile("cpuid"
660 : "=a"(vec[0]), "=b"(vec[1]),
661 "=c"(vec[2]), "=d"(vec[3])
662 : "0"(function), "c"(count) : "cc");
c1f41226 663#elif defined(__i386__)
a1fd24af
AL		 664 asm volatile("pusha \n\t"
665 "cpuid \n\t"
666 "mov %%eax, 0(%2) \n\t"
667 "mov %%ebx, 4(%2) \n\t"
668 "mov %%ecx, 8(%2) \n\t"
669 "mov %%edx, 12(%2) \n\t"
670 "popa"
671 : : "a"(function), "c"(count), "S"(vec)
672 : "memory", "cc");
c1f41226
EH		 673#else
674 abort();
a1fd24af
AL		 675#endif
676
bdde476a 677 if (eax)
a1fd24af 678 *eax = vec[0];
bdde476a 679 if (ebx)
a1fd24af 680 *ebx = vec[1];
bdde476a 681 if (ecx)
a1fd24af 682 *ecx = vec[2];
bdde476a 683 if (edx)
a1fd24af 684 *edx = vec[3];
bdde476a 685}
c6dc6f63 686
20271d48
EH		 687void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
688{
689 uint32_t eax, ebx, ecx, edx;
690
691 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
692 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
693
694 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
695 if (family) {
696 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
697 }
698 if (model) {
699 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
700 }
701 if (stepping) {
702 *stepping = eax & 0x0F;
703 }
704}
705
d940ee9b
EH		 706/* CPU class name definitions: */
707
708#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
709#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
710
711/* Return type name for a given CPU model name
712 * Caller is responsible for freeing the returned string.
713 */
714static char *x86_cpu_type_name(const char *model_name)
715{
716 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
717}
718
500050d1
AF		 719static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
720{
d940ee9b
EH		 721 ObjectClass *oc;
722 char *typename;
723
500050d1
AF		 724 if (cpu_model == NULL) {
725 return NULL;
726 }
727
d940ee9b
EH		 728 typename = x86_cpu_type_name(cpu_model);
729 oc = object_class_by_name(typename);
730 g_free(typename);
731 return oc;
500050d1
AF		 732}
733
104494ea
IM		 734static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
735{
736 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
737 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
738 return g_strndup(class_name,
739 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
740}
741
d940ee9b 742struct X86CPUDefinition {
c6dc6f63
AP		 743 const char *name;
744 uint32_t level;
90e4b0c3 745 uint32_t xlevel;
99b88a17
IM		 746 /* vendor is zero-terminated, 12 character ASCII string */
747 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 748 int family;
749 int model;
750 int stepping;
0514ef2f 751 FeatureWordArray features;
c6dc6f63 752 char model_id[48];
d940ee9b 753};
c6dc6f63 754
9576de75 755static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 756 {
757 .name = "qemu64",
3046bb5d 758 .level = 0xd,
99b88a17 759 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 760 .family = 6,
f8e6a11a 761 .model = 6,
c6dc6f63 762 .stepping = 3,
0514ef2f 763 .features[FEAT_1_EDX] =
27861ecc 764 PPRO_FEATURES |
c6dc6f63 765 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 766 CPUID_PSE36,
0514ef2f 767 .features[FEAT_1_ECX] =
6aa91e4a 768 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 769 .features[FEAT_8000_0001_EDX] =
c6dc6f63 770 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 771 .features[FEAT_8000_0001_ECX] =
71195672 772 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 773 .xlevel = 0x8000000A,
9cf2cc3d 774 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 775 },
776 {
777 .name = "phenom",
778 .level = 5,
99b88a17 779 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 780 .family = 16,
781 .model = 2,
782 .stepping = 3,
b9fc20bc 783 /* Missing: CPUID_HT */
0514ef2f 784 .features[FEAT_1_EDX] =
27861ecc 785 PPRO_FEATURES |
c6dc6f63 786 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 787 CPUID_PSE36 | CPUID_VME,
0514ef2f 788 .features[FEAT_1_ECX] =
27861ecc 789 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 790 CPUID_EXT_POPCNT,
0514ef2f 791 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 792 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
793 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 794 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 795 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
796 CPUID_EXT3_CR8LEG,
797 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
798 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 799 .features[FEAT_8000_0001_ECX] =
27861ecc 800 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 801 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 802 /* Missing: CPUID_SVM_LBRV */
0514ef2f 803 .features[FEAT_SVM] =
b9fc20bc 804 CPUID_SVM_NPT,
c6dc6f63
AP		 805 .xlevel = 0x8000001A,
806 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
807 },
808 {
809 .name = "core2duo",
810 .level = 10,
99b88a17 811 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 812 .family = 6,
813 .model = 15,
814 .stepping = 11,
b9fc20bc 815 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 816 .features[FEAT_1_EDX] =
27861ecc 817 PPRO_FEATURES |
c6dc6f63 818 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 819 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
820 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 821 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 822 .features[FEAT_1_ECX] =
27861ecc 823 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 824 CPUID_EXT_CX16,
0514ef2f 825 .features[FEAT_8000_0001_EDX] =
27861ecc 826 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 827 .features[FEAT_8000_0001_ECX] =
27861ecc 828 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 829 .xlevel = 0x80000008,
830 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
831 },
832 {
833 .name = "kvm64",
3046bb5d 834 .level = 0xd,
99b88a17 835 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 836 .family = 15,
837 .model = 6,
838 .stepping = 1,
b3a4f0b1 839 /* Missing: CPUID_HT */
0514ef2f 840 .features[FEAT_1_EDX] =
b3a4f0b1 841 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 842 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
843 CPUID_PSE36,
844 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 845 .features[FEAT_1_ECX] =
27861ecc 846 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 847 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 848 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 849 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
850 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
851 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
852 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
853 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 854 .features[FEAT_8000_0001_ECX] =
27861ecc 855 0,
c6dc6f63
AP		 856 .xlevel = 0x80000008,
857 .model_id = "Common KVM processor"
858 },
c6dc6f63
AP		 859 {
860 .name = "qemu32",
861 .level = 4,
99b88a17 862 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 863 .family = 6,
f8e6a11a 864 .model = 6,
c6dc6f63 865 .stepping = 3,
0514ef2f 866 .features[FEAT_1_EDX] =
27861ecc 867 PPRO_FEATURES,
0514ef2f 868 .features[FEAT_1_ECX] =
6aa91e4a 869 CPUID_EXT_SSE3,
58012d66 870 .xlevel = 0x80000004,
9cf2cc3d 871 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 872 },
eafaf1e5
AP		 873 {
874 .name = "kvm32",
875 .level = 5,
99b88a17 876 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 877 .family = 15,
878 .model = 6,
879 .stepping = 1,
0514ef2f 880 .features[FEAT_1_EDX] =
b3a4f0b1 881 PPRO_FEATURES | CPUID_VME |
eafaf1e5 882 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 883 .features[FEAT_1_ECX] =
27861ecc 884 CPUID_EXT_SSE3,
0514ef2f 885 .features[FEAT_8000_0001_ECX] =
27861ecc 886 0,
eafaf1e5
AP		 887 .xlevel = 0x80000008,
888 .model_id = "Common 32-bit KVM processor"
889 },
c6dc6f63
AP		 890 {
891 .name = "coreduo",
892 .level = 10,
99b88a17 893 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 894 .family = 6,
895 .model = 14,
896 .stepping = 8,
b9fc20bc 897 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 898 .features[FEAT_1_EDX] =
27861ecc 899 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 900 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
901 CPUID_SS,
902 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 903 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 904 .features[FEAT_1_ECX] =
e93abc14 905 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 906 .features[FEAT_8000_0001_EDX] =
27861ecc 907 CPUID_EXT2_NX,
c6dc6f63
AP		 908 .xlevel = 0x80000008,
909 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
910 },
911 {
912 .name = "486",
58012d66 913 .level = 1,
99b88a17 914 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 915 .family = 4,
b2a856d9 916 .model = 8,
c6dc6f63 917 .stepping = 0,
0514ef2f 918 .features[FEAT_1_EDX] =
27861ecc 919 I486_FEATURES,
c6dc6f63
AP		 920 .xlevel = 0,
921 },
922 {
923 .name = "pentium",
924 .level = 1,
99b88a17 925 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 926 .family = 5,
927 .model = 4,
928 .stepping = 3,
0514ef2f 929 .features[FEAT_1_EDX] =
27861ecc 930 PENTIUM_FEATURES,
c6dc6f63
AP		 931 .xlevel = 0,
932 },
933 {
934 .name = "pentium2",
935 .level = 2,
99b88a17 936 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 937 .family = 6,
938 .model = 5,
939 .stepping = 2,
0514ef2f 940 .features[FEAT_1_EDX] =
27861ecc 941 PENTIUM2_FEATURES,
c6dc6f63
AP		 942 .xlevel = 0,
943 },
944 {
945 .name = "pentium3",
3046bb5d 946 .level = 3,
99b88a17 947 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 948 .family = 6,
949 .model = 7,
950 .stepping = 3,
0514ef2f 951 .features[FEAT_1_EDX] =
27861ecc 952 PENTIUM3_FEATURES,
c6dc6f63
AP		 953 .xlevel = 0,
954 },
955 {
956 .name = "athlon",
957 .level = 2,
99b88a17 958 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 959 .family = 6,
960 .model = 2,
961 .stepping = 3,
0514ef2f 962 .features[FEAT_1_EDX] =
27861ecc 963 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 964 CPUID_MCA,
0514ef2f 965 .features[FEAT_8000_0001_EDX] =
60032ac0 966 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 967 .xlevel = 0x80000008,
9cf2cc3d 968 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 969 },
970 {
971 .name = "n270",
3046bb5d 972 .level = 10,
99b88a17 973 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 974 .family = 6,
975 .model = 28,
976 .stepping = 2,
b9fc20bc 977 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 978 .features[FEAT_1_EDX] =
27861ecc 979 PPRO_FEATURES |
b9fc20bc
EH		 980 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
981 CPUID_ACPI | CPUID_SS,
c6dc6f63 982 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 983 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
984 * CPUID_EXT_XTPR */
0514ef2f 985 .features[FEAT_1_ECX] =
27861ecc 986 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 987 CPUID_EXT_MOVBE,
0514ef2f 988 .features[FEAT_8000_0001_EDX] =
60032ac0 989 CPUID_EXT2_NX,
0514ef2f 990 .features[FEAT_8000_0001_ECX] =
27861ecc 991 CPUID_EXT3_LAHF_LM,
3046bb5d 992 .xlevel = 0x80000008,
c6dc6f63
AP		 993 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
994 },
3eca4642
EH		 995 {
996 .name = "Conroe",
3046bb5d 997 .level = 10,
99b88a17 998 .vendor = CPUID_VENDOR_INTEL,
3eca4642 999 .family = 6,
ffce9ebb 1000 .model = 15,
3eca4642 1001 .stepping = 3,
0514ef2f 1002 .features[FEAT_1_EDX] =
b3a4f0b1 1003 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1004 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1005 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1006 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1007 CPUID_DE | CPUID_FP87,
0514ef2f 1008 .features[FEAT_1_ECX] =
27861ecc 1009 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1010 .features[FEAT_8000_0001_EDX] =
27861ecc 1011 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1012 .features[FEAT_8000_0001_ECX] =
27861ecc 1013 CPUID_EXT3_LAHF_LM,
3046bb5d 1014 .xlevel = 0x80000008,
3eca4642
EH		 1015 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1016 },
1017 {
1018 .name = "Penryn",
3046bb5d 1019 .level = 10,
99b88a17 1020 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1021 .family = 6,
ffce9ebb 1022 .model = 23,
3eca4642 1023 .stepping = 3,
0514ef2f 1024 .features[FEAT_1_EDX] =
b3a4f0b1 1025 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1026 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1027 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1028 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1029 CPUID_DE | CPUID_FP87,
0514ef2f 1030 .features[FEAT_1_ECX] =
27861ecc 1031 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1032 CPUID_EXT_SSE3,
0514ef2f 1033 .features[FEAT_8000_0001_EDX] =
27861ecc 1034 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1035 .features[FEAT_8000_0001_ECX] =
27861ecc 1036 CPUID_EXT3_LAHF_LM,
3046bb5d 1037 .xlevel = 0x80000008,
3eca4642
EH		 1038 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1039 },
1040 {
1041 .name = "Nehalem",
3046bb5d 1042 .level = 11,
99b88a17 1043 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1044 .family = 6,
ffce9ebb 1045 .model = 26,
3eca4642 1046 .stepping = 3,
0514ef2f 1047 .features[FEAT_1_EDX] =
b3a4f0b1 1048 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1049 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1050 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1051 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1052 CPUID_DE | CPUID_FP87,
0514ef2f 1053 .features[FEAT_1_ECX] =
27861ecc 1054 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1055 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1056 .features[FEAT_8000_0001_EDX] =
27861ecc 1057 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1058 .features[FEAT_8000_0001_ECX] =
27861ecc 1059 CPUID_EXT3_LAHF_LM,
3046bb5d 1060 .xlevel = 0x80000008,
3eca4642
EH		 1061 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1062 },
1063 {
1064 .name = "Westmere",
1065 .level = 11,
99b88a17 1066 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1067 .family = 6,
1068 .model = 44,
1069 .stepping = 1,
0514ef2f 1070 .features[FEAT_1_EDX] =
b3a4f0b1 1071 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1072 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1073 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1074 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1075 CPUID_DE | CPUID_FP87,
0514ef2f 1076 .features[FEAT_1_ECX] =
27861ecc 1077 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1078 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1079 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1080 .features[FEAT_8000_0001_EDX] =
27861ecc 1081 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1082 .features[FEAT_8000_0001_ECX] =
27861ecc 1083 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1084 .features[FEAT_6_EAX] =
1085 CPUID_6_EAX_ARAT,
3046bb5d 1086 .xlevel = 0x80000008,
3eca4642
EH		 1087 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1088 },
1089 {
1090 .name = "SandyBridge",
1091 .level = 0xd,
99b88a17 1092 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1093 .family = 6,
1094 .model = 42,
1095 .stepping = 1,
0514ef2f 1096 .features[FEAT_1_EDX] =
b3a4f0b1 1097 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1098 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1099 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1100 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1101 CPUID_DE | CPUID_FP87,
0514ef2f 1102 .features[FEAT_1_ECX] =
27861ecc 1103 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1104 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1105 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1106 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1107 CPUID_EXT_SSE3,
0514ef2f 1108 .features[FEAT_8000_0001_EDX] =
27861ecc 1109 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1110 CPUID_EXT2_SYSCALL,
0514ef2f 1111 .features[FEAT_8000_0001_ECX] =
27861ecc 1112 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1113 .features[FEAT_XSAVE] =
1114 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1115 .features[FEAT_6_EAX] =
1116 CPUID_6_EAX_ARAT,
3046bb5d 1117 .xlevel = 0x80000008,
3eca4642
EH		 1118 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1119 },
2f9ac42a
PB		 1120 {
1121 .name = "IvyBridge",
1122 .level = 0xd,
1123 .vendor = CPUID_VENDOR_INTEL,
1124 .family = 6,
1125 .model = 58,
1126 .stepping = 9,
1127 .features[FEAT_1_EDX] =
1128 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1129 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1130 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1131 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1132 CPUID_DE | CPUID_FP87,
1133 .features[FEAT_1_ECX] =
1134 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1135 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1136 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1137 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1138 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1139 .features[FEAT_7_0_EBX] =
1140 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1141 CPUID_7_0_EBX_ERMS,
1142 .features[FEAT_8000_0001_EDX] =
1143 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1144 CPUID_EXT2_SYSCALL,
1145 .features[FEAT_8000_0001_ECX] =
1146 CPUID_EXT3_LAHF_LM,
1147 .features[FEAT_XSAVE] =
1148 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1149 .features[FEAT_6_EAX] =
1150 CPUID_6_EAX_ARAT,
3046bb5d 1151 .xlevel = 0x80000008,
2f9ac42a
PB		 1152 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1153 },
37507094 1154 {
a356850b
EH		 1155 .name = "Haswell-noTSX",
1156 .level = 0xd,
1157 .vendor = CPUID_VENDOR_INTEL,
1158 .family = 6,
1159 .model = 60,
1160 .stepping = 1,
1161 .features[FEAT_1_EDX] =
1162 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1163 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1164 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1165 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1166 CPUID_DE | CPUID_FP87,
1167 .features[FEAT_1_ECX] =
1168 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1169 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1170 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1171 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1172 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1173 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1174 .features[FEAT_8000_0001_EDX] =
1175 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1176 CPUID_EXT2_SYSCALL,
1177 .features[FEAT_8000_0001_ECX] =
becb6667 1178 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1179 .features[FEAT_7_0_EBX] =
1180 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1181 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1182 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1183 .features[FEAT_XSAVE] =
1184 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1185 .features[FEAT_6_EAX] =
1186 CPUID_6_EAX_ARAT,
3046bb5d 1187 .xlevel = 0x80000008,
a356850b
EH		 1188 .model_id = "Intel Core Processor (Haswell, no TSX)",
1189 }, {
37507094
EH		 1190 .name = "Haswell",
1191 .level = 0xd,
99b88a17 1192 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1193 .family = 6,
1194 .model = 60,
ec56a4a7 1195 .stepping = 4,
0514ef2f 1196 .features[FEAT_1_EDX] =
b3a4f0b1 1197 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1198 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1199 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1200 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1201 CPUID_DE | CPUID_FP87,
0514ef2f 1202 .features[FEAT_1_ECX] =
27861ecc 1203 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1204 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1205 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1206 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1207 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1208 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1209 .features[FEAT_8000_0001_EDX] =
27861ecc 1210 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1211 CPUID_EXT2_SYSCALL,
0514ef2f 1212 .features[FEAT_8000_0001_ECX] =
becb6667 1213 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1214 .features[FEAT_7_0_EBX] =
27861ecc 1215 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1216 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1217 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1218 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1219 .features[FEAT_XSAVE] =
1220 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1221 .features[FEAT_6_EAX] =
1222 CPUID_6_EAX_ARAT,
3046bb5d 1223 .xlevel = 0x80000008,
37507094
EH		 1224 .model_id = "Intel Core Processor (Haswell)",
1225 },
a356850b
EH		 1226 {
1227 .name = "Broadwell-noTSX",
1228 .level = 0xd,
1229 .vendor = CPUID_VENDOR_INTEL,
1230 .family = 6,
1231 .model = 61,
1232 .stepping = 2,
1233 .features[FEAT_1_EDX] =
1234 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1235 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1236 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1237 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1238 CPUID_DE | CPUID_FP87,
1239 .features[FEAT_1_ECX] =
1240 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1241 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1242 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1243 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1244 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1245 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1246 .features[FEAT_8000_0001_EDX] =
1247 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1248 CPUID_EXT2_SYSCALL,
1249 .features[FEAT_8000_0001_ECX] =
becb6667 1250 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1251 .features[FEAT_7_0_EBX] =
1252 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1253 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1254 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1255 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1256 CPUID_7_0_EBX_SMAP,
1257 .features[FEAT_XSAVE] =
1258 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1259 .features[FEAT_6_EAX] =
1260 CPUID_6_EAX_ARAT,
3046bb5d 1261 .xlevel = 0x80000008,
a356850b
EH		 1262 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1263 },
ece01354
EH		 1264 {
1265 .name = "Broadwell",
1266 .level = 0xd,
1267 .vendor = CPUID_VENDOR_INTEL,
1268 .family = 6,
1269 .model = 61,
1270 .stepping = 2,
1271 .features[FEAT_1_EDX] =
b3a4f0b1 1272 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1273 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1274 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1275 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1276 CPUID_DE | CPUID_FP87,
1277 .features[FEAT_1_ECX] =
1278 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1279 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1280 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1281 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1282 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1283 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1284 .features[FEAT_8000_0001_EDX] =
1285 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1286 CPUID_EXT2_SYSCALL,
1287 .features[FEAT_8000_0001_ECX] =
becb6667 1288 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1289 .features[FEAT_7_0_EBX] =
1290 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1291 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1292 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1293 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1294 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1295 .features[FEAT_XSAVE] =
1296 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1297 .features[FEAT_6_EAX] =
1298 CPUID_6_EAX_ARAT,
3046bb5d 1299 .xlevel = 0x80000008,
ece01354
EH		 1300 .model_id = "Intel Core Processor (Broadwell)",
1301 },
f6f949e9
EH		 1302 {
1303 .name = "Skylake-Client",
1304 .level = 0xd,
1305 .vendor = CPUID_VENDOR_INTEL,
1306 .family = 6,
1307 .model = 94,
1308 .stepping = 3,
1309 .features[FEAT_1_EDX] =
1310 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1311 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1312 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1313 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1314 CPUID_DE | CPUID_FP87,
1315 .features[FEAT_1_ECX] =
1316 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1317 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1318 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1319 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1320 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1321 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1322 .features[FEAT_8000_0001_EDX] =
1323 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1324 CPUID_EXT2_SYSCALL,
1325 .features[FEAT_8000_0001_ECX] =
1326 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1327 .features[FEAT_7_0_EBX] =
1328 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1329 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1330 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1331 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1332 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1333 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 1334 * including v4.1 to v4.12).
f6f949e9
EH		 1335 * KVM doesn't yet expose any XSAVES state save component,
1336 * and the only one defined in Skylake (processor tracing)
1337 * probably will block migration anyway.
1338 */
1339 .features[FEAT_XSAVE] =
1340 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1341 CPUID_XSAVE_XGETBV1,
1342 .features[FEAT_6_EAX] =
1343 CPUID_6_EAX_ARAT,
1344 .xlevel = 0x80000008,
1345 .model_id = "Intel Core Processor (Skylake)",
1346 },
53f9a6f4
BF		 1347 {
1348 .name = "Skylake-Server",
1349 .level = 0xd,
1350 .vendor = CPUID_VENDOR_INTEL,
1351 .family = 6,
1352 .model = 85,
1353 .stepping = 4,
1354 .features[FEAT_1_EDX] =
1355 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1356 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1357 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1358 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1359 CPUID_DE | CPUID_FP87,
1360 .features[FEAT_1_ECX] =
1361 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1362 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1363 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1364 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1365 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1366 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1367 .features[FEAT_8000_0001_EDX] =
1368 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
1369 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1370 .features[FEAT_8000_0001_ECX] =
1371 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1372 .features[FEAT_7_0_EBX] =
1373 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1374 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1375 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1376 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1377 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
1378 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
1379 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
1380 CPUID_7_0_EBX_AVX512VL,
1381 /* Missing: XSAVES (not supported by some Linux versions,
1382 * including v4.1 to v4.12).
1383 * KVM doesn't yet expose any XSAVES state save component,
1384 * and the only one defined in Skylake (processor tracing)
1385 * probably will block migration anyway.
1386 */
1387 .features[FEAT_XSAVE] =
1388 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1389 CPUID_XSAVE_XGETBV1,
1390 .features[FEAT_6_EAX] =
1391 CPUID_6_EAX_ARAT,
1392 .xlevel = 0x80000008,
1393 .model_id = "Intel Xeon Processor (Skylake)",
1394 },
3eca4642
EH		 1395 {
1396 .name = "Opteron_G1",
1397 .level = 5,
99b88a17 1398 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1399 .family = 15,
1400 .model = 6,
1401 .stepping = 1,
0514ef2f 1402 .features[FEAT_1_EDX] =
b3a4f0b1 1403 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1404 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1405 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1406 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1407 CPUID_DE | CPUID_FP87,
0514ef2f 1408 .features[FEAT_1_ECX] =
27861ecc 1409 CPUID_EXT_SSE3,
0514ef2f 1410 .features[FEAT_8000_0001_EDX] =
2a923a29 1411 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 1412 .xlevel = 0x80000008,
1413 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1414 },
1415 {
1416 .name = "Opteron_G2",
1417 .level = 5,
99b88a17 1418 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1419 .family = 15,
1420 .model = 6,
1421 .stepping = 1,
0514ef2f 1422 .features[FEAT_1_EDX] =
b3a4f0b1 1423 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1424 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1425 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1426 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1427 CPUID_DE | CPUID_FP87,
0514ef2f 1428 .features[FEAT_1_ECX] =
27861ecc 1429 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1430 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1431 .features[FEAT_8000_0001_EDX] =
2a923a29 1432 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1433 .features[FEAT_8000_0001_ECX] =
27861ecc 1434 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1435 .xlevel = 0x80000008,
1436 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1437 },
1438 {
1439 .name = "Opteron_G3",
1440 .level = 5,
99b88a17 1441 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 1442 .family = 16,
1443 .model = 2,
1444 .stepping = 3,
0514ef2f 1445 .features[FEAT_1_EDX] =
b3a4f0b1 1446 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1447 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1448 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1449 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1450 CPUID_DE | CPUID_FP87,
0514ef2f 1451 .features[FEAT_1_ECX] =
27861ecc 1452 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1453 CPUID_EXT_SSE3,
33b5e8c0 1454 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1455 .features[FEAT_8000_0001_EDX] =
2a923a29 1456 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1457 .features[FEAT_8000_0001_ECX] =
27861ecc 1458 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1459 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1460 .xlevel = 0x80000008,
1461 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1462 },
1463 {
1464 .name = "Opteron_G4",
1465 .level = 0xd,
99b88a17 1466 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1467 .family = 21,
1468 .model = 1,
1469 .stepping = 2,
0514ef2f 1470 .features[FEAT_1_EDX] =
b3a4f0b1 1471 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1472 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1473 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1474 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1475 CPUID_DE | CPUID_FP87,
0514ef2f 1476 .features[FEAT_1_ECX] =
27861ecc 1477 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1478 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1479 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1480 CPUID_EXT_SSE3,
33b5e8c0 1481 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1482 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1483 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1484 CPUID_EXT2_SYSCALL,
0514ef2f 1485 .features[FEAT_8000_0001_ECX] =
27861ecc 1486 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1487 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1488 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1489 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1490 /* no xsaveopt! */
3eca4642
EH		 1491 .xlevel = 0x8000001A,
1492 .model_id = "AMD Opteron 62xx class CPU",
1493 },
021941b9
AP		 1494 {
1495 .name = "Opteron_G5",
1496 .level = 0xd,
99b88a17 1497 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1498 .family = 21,
1499 .model = 2,
1500 .stepping = 0,
0514ef2f 1501 .features[FEAT_1_EDX] =
b3a4f0b1 1502 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1503 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1504 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1505 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1506 CPUID_DE | CPUID_FP87,
0514ef2f 1507 .features[FEAT_1_ECX] =
27861ecc 1508 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1509 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1510 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1511 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1512 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1513 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1514 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1515 CPUID_EXT2_SYSCALL,
0514ef2f 1516 .features[FEAT_8000_0001_ECX] =
27861ecc 1517 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1518 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1519 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1520 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1521 /* no xsaveopt! */
021941b9
AP		 1522 .xlevel = 0x8000001A,
1523 .model_id = "AMD Opteron 63xx class CPU",
1524 },
c6dc6f63
AP		 1525};
1526
5114e842
EH		 1527typedef struct PropValue {
1528 const char *prop, *value;
1529} PropValue;
1530
1531/* KVM-specific features that are automatically added/removed
1532 * from all CPU models when KVM is enabled.
1533 */
1534static PropValue kvm_default_props[] = {
1535 { "kvmclock", "on" },
1536 { "kvm-nopiodelay", "on" },
1537 { "kvm-asyncpf", "on" },
1538 { "kvm-steal-time", "on" },
1539 { "kvm-pv-eoi", "on" },
1540 { "kvmclock-stable-bit", "on" },
1541 { "x2apic", "on" },
1542 { "acpi", "off" },
1543 { "monitor", "off" },
1544 { "svm", "off" },
1545 { NULL, NULL },
1546};
1547
04d99c3c
EH		 1548/* TCG-specific defaults that override all CPU models when using TCG
1549 */
1550static PropValue tcg_default_props[] = {
1551 { "vme", "off" },
1552 { NULL, NULL },
1553};
1554
1555
5114e842
EH		 1556void x86_cpu_change_kvm_default(const char *prop, const char *value)
1557{
1558 PropValue *pv;
1559 for (pv = kvm_default_props; pv->prop; pv++) {
1560 if (!strcmp(pv->prop, prop)) {
1561 pv->value = value;
1562 break;
1563 }
1564 }
1565
1566 /* It is valid to call this function only for properties that
1567 * are already present in the kvm_default_props table.
1568 */
1569 assert(pv->prop);
1570}
1571
4d1b279b
EH		 1572static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1573 bool migratable_only);
1574
40bfe48f
HZ		 1575static bool lmce_supported(void)
1576{
c62f2630 1577 uint64_t mce_cap = 0;
40bfe48f 1578
c62f2630 1579#ifdef CONFIG_KVM
40bfe48f
HZ		 1580 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1581 return false;
1582 }
c62f2630 1583#endif
40bfe48f
HZ		 1584
1585 return !!(mce_cap & MCG_LMCE_P);
1586}
1587
c6dc6f63
AP		 1588static int cpu_x86_fill_model_id(char *str)
1589{
1590 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1591 int i;
1592
1593 for (i = 0; i < 3; i++) {
1594 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1595 memcpy(str + i * 16 + 0, &eax, 4);
1596 memcpy(str + i * 16 + 4, &ebx, 4);
1597 memcpy(str + i * 16 + 8, &ecx, 4);
1598 memcpy(str + i * 16 + 12, &edx, 4);
1599 }
1600 return 0;
1601}
1602
c62f2630 1603static Property max_x86_cpu_properties[] = {
120eee7d 1604 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1605 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1606 DEFINE_PROP_END_OF_LIST()
1607};
1608
c62f2630 1609static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1610{
84f1b92f 1611 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1612 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 1613
f48c8837 1614 xcc->ordering = 9;
6e746f30 1615
ee465a3e 1616 xcc->model_description =
c62f2630 1617 "Enables all features supported by the accelerator in the current host";
d940ee9b 1618
c62f2630 1619 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 1620}
1621
0bacd8b3
EH		 1622static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
1623
c62f2630 1624static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 1625{
1626 X86CPU *cpu = X86_CPU(obj);
1627 CPUX86State *env = &cpu->env;
1628 KVMState *s = kvm_state;
d940ee9b 1629
4d1b279b
EH		 1630 /* We can't fill the features array here because we don't know yet if
1631 * "migratable" is true or false.
1632 */
44bd8e53 1633 cpu->max_features = true;
4d1b279b 1634
e4356010 1635 if (kvm_enabled()) {
0bacd8b3
EH		 1636 X86CPUDefinition host_cpudef = { };
1637 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1638
bfef6248
EH		 1639 host_vendor_fms(host_cpudef.vendor, &host_cpudef.family,
1640 &host_cpudef.model, &host_cpudef.stepping);
0bacd8b3
EH		 1641
1642 cpu_x86_fill_model_id(host_cpudef.model_id);
1643
1644 x86_cpu_load_def(cpu, &host_cpudef, &error_abort);
1645
c39c0edf
EH		 1646 env->cpuid_min_level =
1647 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1648 env->cpuid_min_xlevel =
1649 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1650 env->cpuid_min_xlevel2 =
1651 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
40bfe48f
HZ		 1652
1653 if (lmce_supported()) {
1654 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1655 }
6900d1cc
EH		 1656 } else {
1657 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
1658 "vendor", &error_abort);
1659 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
1660 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
1661 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
1662 object_property_set_str(OBJECT(cpu),
1663 "QEMU TCG CPU version " QEMU_HW_VERSION,
1664 "model-id", &error_abort);
e4356010 1665 }
2a573259 1666
d940ee9b 1667 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1668}
1669
c62f2630
EH		 1670static const TypeInfo max_x86_cpu_type_info = {
1671 .name = X86_CPU_TYPE_NAME("max"),
1672 .parent = TYPE_X86_CPU,
1673 .instance_init = max_x86_cpu_initfn,
1674 .class_init = max_x86_cpu_class_init,
1675};
1676
1677#ifdef CONFIG_KVM
1678
1679static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1680{
1681 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1682
1683 xcc->kvm_required = true;
1684 xcc->ordering = 8;
1685
1686 xcc->model_description =
1687 "KVM processor with all supported host features "
1688 "(only available in KVM mode)";
1689}
1690
d940ee9b
EH		 1691static const TypeInfo host_x86_cpu_type_info = {
1692 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 1693 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 1694 .class_init = host_x86_cpu_class_init,
1695};
1696
1697#endif
1698
8459e396 1699static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1700{
8459e396 1701 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1702 int i;
1703
857aee33 1704 for (i = 0; i < 32; ++i) {
72370dc1 1705 if ((1UL << i) & mask) {
bffd67b0 1706 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1707 assert(reg);
fefb41bf 1708 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1709 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1710 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1711 f->cpuid_eax, reg,
1712 f->feat_names[i] ? "." : "",
1713 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1714 }
857aee33 1715 }
c6dc6f63
AP		 1716}
1717
d7bce999
EB		 1718static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1719 const char *name, void *opaque,
1720 Error **errp)
95b8519d
AF		 1721{
1722 X86CPU *cpu = X86_CPU(obj);
1723 CPUX86State *env = &cpu->env;
1724 int64_t value;
1725
1726 value = (env->cpuid_version >> 8) & 0xf;
1727 if (value == 0xf) {
1728 value += (env->cpuid_version >> 20) & 0xff;
1729 }
51e72bc1 1730 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1731}
1732
d7bce999
EB		 1733static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1734 const char *name, void *opaque,
1735 Error **errp)
ed5e1ec3 1736{
71ad61d3
AF		 1737 X86CPU *cpu = X86_CPU(obj);
1738 CPUX86State *env = &cpu->env;
1739 const int64_t min = 0;
1740 const int64_t max = 0xff + 0xf;
65cd9064 1741 Error *local_err = NULL;
71ad61d3
AF		 1742 int64_t value;
1743
51e72bc1 1744 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1745 if (local_err) {
1746 error_propagate(errp, local_err);
71ad61d3
AF		 1747 return;
1748 }
1749 if (value < min || value > max) {
c6bd8c70
MA		 1750 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1751 name ? name : "null", value, min, max);
71ad61d3
AF		 1752 return;
1753 }
1754
ed5e1ec3 1755 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1756 if (value > 0x0f) {
1757 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1758 } else {
71ad61d3 1759 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1760 }
1761}
1762
d7bce999
EB		 1763static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1764 const char *name, void *opaque,
1765 Error **errp)
67e30c83
AF		 1766{
1767 X86CPU *cpu = X86_CPU(obj);
1768 CPUX86State *env = &cpu->env;
1769 int64_t value;
1770
1771 value = (env->cpuid_version >> 4) & 0xf;
1772 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1773 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1774}
1775
d7bce999
EB		 1776static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1777 const char *name, void *opaque,
1778 Error **errp)
b0704cbd 1779{
c5291a4f
AF		 1780 X86CPU *cpu = X86_CPU(obj);
1781 CPUX86State *env = &cpu->env;
1782 const int64_t min = 0;
1783 const int64_t max = 0xff;
65cd9064 1784 Error *local_err = NULL;
c5291a4f
AF		 1785 int64_t value;
1786
51e72bc1 1787 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1788 if (local_err) {
1789 error_propagate(errp, local_err);
c5291a4f
AF		 1790 return;
1791 }
1792 if (value < min || value > max) {
c6bd8c70
MA		 1793 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1794 name ? name : "null", value, min, max);
c5291a4f
AF		 1795 return;
1796 }
1797
b0704cbd 1798 env->cpuid_version &= ~0xf00f0;
c5291a4f 1799 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1800}
1801
35112e41 1802static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1803 const char *name, void *opaque,
35112e41
AF		 1804 Error **errp)
1805{
1806 X86CPU *cpu = X86_CPU(obj);
1807 CPUX86State *env = &cpu->env;
1808 int64_t value;
1809
1810 value = env->cpuid_version & 0xf;
51e72bc1 1811 visit_type_int(v, name, &value, errp);
35112e41
AF		 1812}
1813
036e2222 1814static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1815 const char *name, void *opaque,
036e2222 1816 Error **errp)
38c3dc46 1817{
036e2222
AF		 1818 X86CPU *cpu = X86_CPU(obj);
1819 CPUX86State *env = &cpu->env;
1820 const int64_t min = 0;
1821 const int64_t max = 0xf;
65cd9064 1822 Error *local_err = NULL;
036e2222
AF		 1823 int64_t value;
1824
51e72bc1 1825 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1826 if (local_err) {
1827 error_propagate(errp, local_err);
036e2222
AF		 1828 return;
1829 }
1830 if (value < min || value > max) {
c6bd8c70
MA		 1831 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1832 name ? name : "null", value, min, max);
036e2222
AF		 1833 return;
1834 }
1835
38c3dc46 1836 env->cpuid_version &= ~0xf;
036e2222 1837 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1838}
1839
d480e1af
AF		 1840static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1841{
1842 X86CPU *cpu = X86_CPU(obj);
1843 CPUX86State *env = &cpu->env;
1844 char *value;
d480e1af 1845
e42a92ae 1846 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1847 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1848 env->cpuid_vendor3);
d480e1af
AF		 1849 return value;
1850}
1851
1852static void x86_cpuid_set_vendor(Object *obj, const char *value,
1853 Error **errp)
1854{
1855 X86CPU *cpu = X86_CPU(obj);
1856 CPUX86State *env = &cpu->env;
1857 int i;
1858
9df694ee 1859 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1860 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1861 return;
1862 }
1863
1864 env->cpuid_vendor1 = 0;
1865 env->cpuid_vendor2 = 0;
1866 env->cpuid_vendor3 = 0;
1867 for (i = 0; i < 4; i++) {
1868 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1869 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1870 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1871 }
d480e1af
AF		 1872}
1873
63e886eb
AF		 1874static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1875{
1876 X86CPU *cpu = X86_CPU(obj);
1877 CPUX86State *env = &cpu->env;
1878 char *value;
1879 int i;
1880
1881 value = g_malloc(48 + 1);
1882 for (i = 0; i < 48; i++) {
1883 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1884 }
1885 value[48] = '\0';
1886 return value;
1887}
1888
938d4c25
AF		 1889static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1890 Error **errp)
dcce6675 1891{
938d4c25
AF		 1892 X86CPU *cpu = X86_CPU(obj);
1893 CPUX86State *env = &cpu->env;
dcce6675
AF		 1894 int c, len, i;
1895
1896 if (model_id == NULL) {
1897 model_id = "";
1898 }
1899 len = strlen(model_id);
d0a6acf4 1900 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1901 for (i = 0; i < 48; i++) {
1902 if (i >= len) {
1903 c = '\0';
1904 } else {
1905 c = (uint8_t)model_id[i];
1906 }
1907 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1908 }
1909}
1910
d7bce999
EB		 1911static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1912 void *opaque, Error **errp)
89e48965
AF		 1913{
1914 X86CPU *cpu = X86_CPU(obj);
1915 int64_t value;
1916
1917 value = cpu->env.tsc_khz * 1000;
51e72bc1 1918 visit_type_int(v, name, &value, errp);
89e48965
AF		 1919}
1920
d7bce999
EB		 1921static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1922 void *opaque, Error **errp)
89e48965
AF		 1923{
1924 X86CPU *cpu = X86_CPU(obj);
1925 const int64_t min = 0;
2e84849a 1926 const int64_t max = INT64_MAX;
65cd9064 1927 Error *local_err = NULL;
89e48965
AF		 1928 int64_t value;
1929
51e72bc1 1930 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1931 if (local_err) {
1932 error_propagate(errp, local_err);
89e48965
AF		 1933 return;
1934 }
1935 if (value < min || value > max) {
c6bd8c70
MA		 1936 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1937 name ? name : "null", value, min, max);
89e48965
AF		 1938 return;
1939 }
1940
36f96c4b 1941 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1942}
1943
7e5292b5 1944/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1945static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1946 const char *name, void *opaque,
1947 Error **errp)
8e8aba50 1948{
7e5292b5 1949 uint32_t *array = (uint32_t *)opaque;
8e8aba50 1950 FeatureWord w;
8e8aba50
EH		 1951 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1952 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1953 X86CPUFeatureWordInfoList *list = NULL;
1954
1955 for (w = 0; w < FEATURE_WORDS; w++) {
1956 FeatureWordInfo *wi = &feature_word_info[w];
1957 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1958 qwi->cpuid_input_eax = wi->cpuid_eax;
1959 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1960 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1961 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1962 qwi->features = array[w];
8e8aba50
EH		 1963
1964 /* List will be in reverse order, but order shouldn't matter */
1965 list_entries[w].next = list;
1966 list_entries[w].value = &word_infos[w];
1967 list = &list_entries[w];
1968 }
1969
6b62d961 1970 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 1971}
1972
d7bce999
EB		 1973static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1974 void *opaque, Error **errp)
c8f0f88e
IM		 1975{
1976 X86CPU *cpu = X86_CPU(obj);
1977 int64_t value = cpu->hyperv_spinlock_attempts;
1978
51e72bc1 1979 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1980}
1981
d7bce999
EB		 1982static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1983 void *opaque, Error **errp)
c8f0f88e
IM		 1984{
1985 const int64_t min = 0xFFF;
1986 const int64_t max = UINT_MAX;
1987 X86CPU *cpu = X86_CPU(obj);
1988 Error *err = NULL;
1989 int64_t value;
1990
51e72bc1 1991 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1992 if (err) {
1993 error_propagate(errp, err);
1994 return;
1995 }
1996
1997 if (value < min || value > max) {
1998 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1999 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
2000 object_get_typename(obj), name ? name : "null",
2001 value, min, max);
c8f0f88e
IM		 2002 return;
2003 }
2004 cpu->hyperv_spinlock_attempts = value;
2005}
2006
1b6b7d10 2007static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 2008 .name = "int",
2009 .get = x86_get_hv_spinlocks,
2010 .set = x86_set_hv_spinlocks,
2011};
2012
72ac2e87
IM		 2013/* Convert all '_' in a feature string option name to '-', to make feature
2014 * name conform to QOM property naming rule, which uses '-' instead of '_'.
2015 */
2016static inline void feat2prop(char *s)
2017{
2018 while ((s = strchr(s, '_'))) {
2019 *s = '-';
2020 }
2021}
2022
b54c9377
EH		 2023/* Return the feature property name for a feature flag bit */
2024static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
2025{
2026 /* XSAVE components are automatically enabled by other features,
2027 * so return the original feature name instead
2028 */
2029 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
2030 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
2031
2032 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
2033 x86_ext_save_areas[comp].bits) {
2034 w = x86_ext_save_areas[comp].feature;
2035 bitnr = ctz32(x86_ext_save_areas[comp].bits);
2036 }
2037 }
2038
2039 assert(bitnr < 32);
2040 assert(w < FEATURE_WORDS);
2041 return feature_word_info[w].feat_names[bitnr];
2042}
2043
dc15c051
IM		 2044/* Compatibily hack to maintain legacy +-feat semantic,
2045 * where +-feat overwrites any feature set by
2046 * feat=on|feat even if the later is parsed after +-feat
2047 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2048 */
2fae0d96 2049static GList *plus_features, *minus_features;
dc15c051 2050
83a00f60
EH		 2051static gint compare_string(gconstpointer a, gconstpointer b)
2052{
2053 return g_strcmp0(a, b);
2054}
2055
8f961357
EH		 2056/* Parse "+feature,-feature,feature=foo" CPU feature string
2057 */
62a48a2a 2058static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 2059 Error **errp)
8f961357 2060{
8f961357 2061 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 2062 static bool cpu_globals_initialized;
83a00f60 2063 bool ambiguous = false;
62a48a2a
IM		 2064
2065 if (cpu_globals_initialized) {
2066 return;
2067 }
2068 cpu_globals_initialized = true;
8f961357 2069
f6750e95
EH		 2070 if (!features) {
2071 return;
2072 }
2073
2074 for (featurestr = strtok(features, ",");
685479bd 2075 featurestr;
f6750e95
EH		 2076 featurestr = strtok(NULL, ",")) {
2077 const char *name;
2078 const char *val = NULL;
2079 char *eq = NULL;
cf2887c9 2080 char num[32];
62a48a2a 2081 GlobalProperty *prop;
c6dc6f63 2082
f6750e95 2083 /* Compatibility syntax: */
c6dc6f63 2084 if (featurestr[0] == '+') {
2fae0d96
EH		 2085 plus_features = g_list_append(plus_features,
2086 g_strdup(featurestr + 1));
f6750e95 2087 continue;
c6dc6f63 2088 } else if (featurestr[0] == '-') {
2fae0d96
EH		 2089 minus_features = g_list_append(minus_features,
2090 g_strdup(featurestr + 1));
f6750e95
EH		 2091 continue;
2092 }
2093
2094 eq = strchr(featurestr, '=');
2095 if (eq) {
2096 *eq++ = 0;
2097 val = eq;
c6dc6f63 2098 } else {
f6750e95 2099 val = "on";
a91987c2 2100 }
f6750e95
EH		 2101
2102 feat2prop(featurestr);
2103 name = featurestr;
2104
83a00f60 2105 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 2106 warn_report("Ambiguous CPU model string. "
2107 "Don't mix both \"+%s\" and \"%s=%s\"",
2108 name, name, val);
83a00f60
EH		 2109 ambiguous = true;
2110 }
2111 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 2112 warn_report("Ambiguous CPU model string. "
2113 "Don't mix both \"-%s\" and \"%s=%s\"",
2114 name, name, val);
83a00f60
EH		 2115 ambiguous = true;
2116 }
2117
f6750e95
EH		 2118 /* Special case: */
2119 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 2120 int ret;
f46bfdbf 2121 uint64_t tsc_freq;
f6750e95 2122
f17fd4fd 2123 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 2124 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 2125 error_setg(errp, "bad numerical value %s", val);
2126 return;
2127 }
2128 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2129 val = num;
2130 name = "tsc-frequency";
c6dc6f63 2131 }
f6750e95 2132
62a48a2a
IM		 2133 prop = g_new0(typeof(*prop), 1);
2134 prop->driver = typename;
2135 prop->property = g_strdup(name);
2136 prop->value = g_strdup(val);
2137 prop->errp = &error_fatal;
2138 qdev_prop_register_global(prop);
f6750e95
EH		 2139 }
2140
83a00f60 2141 if (ambiguous) {
3dc6f869
AF		 2142 warn_report("Compatibility of ambiguous CPU model "
2143 "strings won't be kept on future QEMU versions");
83a00f60 2144 }
c6dc6f63
AP		 2145}
2146
b8d834a0 2147static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 2148static int x86_cpu_filter_features(X86CPU *cpu);
2149
2150/* Check for missing features that may prevent the CPU class from
2151 * running using the current machine and accelerator.
2152 */
2153static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
2154 strList **missing_feats)
2155{
2156 X86CPU *xc;
2157 FeatureWord w;
2158 Error *err = NULL;
2159 strList **next = missing_feats;
2160
2161 if (xcc->kvm_required && !kvm_enabled()) {
2162 strList *new = g_new0(strList, 1);
2163 new->value = g_strdup("kvm");;
2164 *missing_feats = new;
2165 return;
2166 }
2167
2168 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2169
b8d834a0 2170 x86_cpu_expand_features(xc, &err);
b54c9377 2171 if (err) {
b8d834a0 2172 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 2173 * but in case it does, just report the model as not
2174 * runnable at all using the "type" property.
2175 */
2176 strList *new = g_new0(strList, 1);
2177 new->value = g_strdup("type");
2178 *next = new;
2179 next = &new->next;
2180 }
2181
2182 x86_cpu_filter_features(xc);
2183
2184 for (w = 0; w < FEATURE_WORDS; w++) {
2185 uint32_t filtered = xc->filtered_features[w];
2186 int i;
2187 for (i = 0; i < 32; i++) {
2188 if (filtered & (1UL << i)) {
2189 strList *new = g_new0(strList, 1);
2190 new->value = g_strdup(x86_cpu_feature_name(w, i));
2191 *next = new;
2192 next = &new->next;
2193 }
2194 }
2195 }
2196
2197 object_unref(OBJECT(xc));
2198}
2199
8c3329e5 2200/* Print all cpuid feature names in featureset
c6dc6f63 2201 */
8c3329e5 2202static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2203{
8c3329e5
EH		 2204 int bit;
2205 bool first = true;
2206
2207 for (bit = 0; bit < 32; bit++) {
2208 if (featureset[bit]) {
2209 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2210 first = false;
c6dc6f63 2211 }
8c3329e5 2212 }
c6dc6f63
AP		 2213}
2214
f48c8837 2215/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 2216static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
2217{
2218 ObjectClass *class_a = (ObjectClass *)a;
2219 ObjectClass *class_b = (ObjectClass *)b;
2220 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
2221 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
2222 const char *name_a, *name_b;
2223
f48c8837
EH		 2224 if (cc_a->ordering != cc_b->ordering) {
2225 return cc_a->ordering - cc_b->ordering;
ee465a3e
EH		 2226 } else {
2227 name_a = object_class_get_name(class_a);
2228 name_b = object_class_get_name(class_b);
2229 return strcmp(name_a, name_b);
2230 }
2231}
2232
2233static GSList *get_sorted_cpu_model_list(void)
2234{
2235 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
2236 list = g_slist_sort(list, x86_cpu_list_compare);
2237 return list;
2238}
2239
2240static void x86_cpu_list_entry(gpointer data, gpointer user_data)
2241{
2242 ObjectClass *oc = data;
2243 X86CPUClass *cc = X86_CPU_CLASS(oc);
2244 CPUListState *s = user_data;
2245 char *name = x86_cpu_class_get_model_name(cc);
2246 const char *desc = cc->model_description;
0bacd8b3 2247 if (!desc && cc->cpu_def) {
ee465a3e
EH		 2248 desc = cc->cpu_def->model_id;
2249 }
2250
2251 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
2252 name, desc);
2253 g_free(name);
2254}
2255
2256/* list available CPU models and flags */
e916cbf8 2257void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2258{
7fc9b714 2259 int i;
ee465a3e
EH		 2260 CPUListState s = {
2261 .file = f,
2262 .cpu_fprintf = cpu_fprintf,
2263 };
2264 GSList *list;
c6dc6f63 2265
ee465a3e
EH		 2266 (*cpu_fprintf)(f, "Available CPUs:\n");
2267 list = get_sorted_cpu_model_list();
2268 g_slist_foreach(list, x86_cpu_list_entry, &s);
2269 g_slist_free(list);
21ad7789 2270
6cdf8854 2271 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2272 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2273 FeatureWordInfo *fw = &feature_word_info[i];
2274
8c3329e5
EH		 2275 (*cpu_fprintf)(f, " ");
2276 listflags(f, cpu_fprintf, fw->feat_names);
2277 (*cpu_fprintf)(f, "\n");
3af60be2 2278 }
c6dc6f63
AP		 2279}
2280
ee465a3e
EH		 2281static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
2282{
2283 ObjectClass *oc = data;
2284 X86CPUClass *cc = X86_CPU_CLASS(oc);
2285 CpuDefinitionInfoList **cpu_list = user_data;
2286 CpuDefinitionInfoList *entry;
2287 CpuDefinitionInfo *info;
2288
2289 info = g_malloc0(sizeof(*info));
2290 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 2291 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
2292 info->has_unavailable_features = true;
8ed877b7 2293 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 2294 info->migration_safe = cc->migration_safe;
2295 info->has_migration_safe = true;
5adbed30 2296 info->q_static = cc->static_model;
ee465a3e
EH		 2297
2298 entry = g_malloc0(sizeof(*entry));
2299 entry->value = info;
2300 entry->next = *cpu_list;
2301 *cpu_list = entry;
2302}
2303
76b64a7a 2304CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2305{
2306 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 2307 GSList *list = get_sorted_cpu_model_list();
2308 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
2309 g_slist_free(list);
e3966126
AL		 2310 return cpu_list;
2311}
2312
84f1b92f
EH		 2313static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2314 bool migratable_only)
27418adf
EH		 2315{
2316 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2317 uint32_t r;
27418adf 2318
fefb41bf 2319 if (kvm_enabled()) {
84f1b92f
EH		 2320 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2321 wi->cpuid_ecx,
2322 wi->cpuid_reg);
fefb41bf 2323 } else if (tcg_enabled()) {
84f1b92f 2324 r = wi->tcg_features;
fefb41bf
EH		 2325 } else {
2326 return ~0;
2327 }
84f1b92f
EH		 2328 if (migratable_only) {
2329 r &= x86_cpu_get_migratable_flags(w);
2330 }
2331 return r;
27418adf
EH		 2332}
2333
8ca30e86
EH		 2334static void x86_cpu_report_filtered_features(X86CPU *cpu)
2335{
2336 FeatureWord w;
2337
2338 for (w = 0; w < FEATURE_WORDS; w++) {
2339 report_unavailable_features(w, cpu->filtered_features[w]);
2340 }
2341}
2342
5114e842
EH		 2343static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2344{
2345 PropValue *pv;
2346 for (pv = props; pv->prop; pv++) {
2347 if (!pv->value) {
2348 continue;
2349 }
2350 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2351 &error_abort);
2352 }
2353}
2354
f99fd7ca 2355/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 2356 */
d940ee9b 2357static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2358{
61dcd775 2359 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2360 const char *vendor;
2361 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2362 FeatureWord w;
c6dc6f63 2363
f99fd7ca
EH		 2364 /*NOTE: any property set by this function should be returned by
2365 * x86_cpu_static_props(), so static expansion of
2366 * query-cpu-model-expansion is always complete.
2367 */
2368
c39c0edf 2369 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 2370 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
2371 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 2372
2d64255b
AF		 2373 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2374 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2375 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2376 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2377 for (w = 0; w < FEATURE_WORDS; w++) {
2378 env->features[w] = def->features[w];
2379 }
82beb536 2380
9576de75 2381 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2382 if (kvm_enabled()) {
492a4c94
LT		 2383 if (!kvm_irqchip_in_kernel()) {
2384 x86_cpu_change_kvm_default("x2apic", "off");
2385 }
2386
5114e842 2387 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 2388 } else if (tcg_enabled()) {
2389 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 2390 }
5fcca9ff 2391
82beb536 2392 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2393
2394 /* sysenter isn't supported in compatibility mode on AMD,
2395 * syscall isn't supported in compatibility mode on Intel.
2396 * Normally we advertise the actual CPU vendor, but you can
2397 * override this using the 'vendor' property if you want to use
2398 * KVM's sysenter/syscall emulation in compatibility mode and
2399 * when doing cross vendor migration
2400 */
74f54bc4 2401 vendor = def->vendor;
7c08db30
EH		 2402 if (kvm_enabled()) {
2403 uint32_t ebx = 0, ecx = 0, edx = 0;
2404 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2405 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2406 vendor = host_vendor;
2407 }
2408
2409 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2410
c6dc6f63
AP		 2411}
2412
f99fd7ca
EH		 2413/* Return a QDict containing keys for all properties that can be included
2414 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
2415 * must be included in the dictionary.
2416 */
2417static QDict *x86_cpu_static_props(void)
2418{
2419 FeatureWord w;
2420 int i;
2421 static const char *props[] = {
2422 "min-level",
2423 "min-xlevel",
2424 "family",
2425 "model",
2426 "stepping",
2427 "model-id",
2428 "vendor",
2429 "lmce",
2430 NULL,
2431 };
2432 static QDict *d;
2433
2434 if (d) {
2435 return d;
2436 }
2437
2438 d = qdict_new();
2439 for (i = 0; props[i]; i++) {
006ca09f 2440 qdict_put(d, props[i], qnull());
f99fd7ca
EH		 2441 }
2442
2443 for (w = 0; w < FEATURE_WORDS; w++) {
2444 FeatureWordInfo *fi = &feature_word_info[w];
2445 int bit;
2446 for (bit = 0; bit < 32; bit++) {
2447 if (!fi->feat_names[bit]) {
2448 continue;
2449 }
006ca09f 2450 qdict_put(d, fi->feat_names[bit], qnull());
f99fd7ca
EH		 2451 }
2452 }
2453
2454 return d;
2455}
2456
2457/* Add an entry to @props dict, with the value for property. */
2458static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
2459{
2460 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
2461 &error_abort);
2462
2463 qdict_put_obj(props, prop, value);
2464}
2465
2466/* Convert CPU model data from X86CPU object to a property dictionary
2467 * that can recreate exactly the same CPU model.
2468 */
2469static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
2470{
2471 QDict *sprops = x86_cpu_static_props();
2472 const QDictEntry *e;
2473
2474 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
2475 const char *prop = qdict_entry_key(e);
2476 x86_cpu_expand_prop(cpu, props, prop);
2477 }
2478}
2479
b8097deb
EH		 2480/* Convert CPU model data from X86CPU object to a property dictionary
2481 * that can recreate exactly the same CPU model, including every
2482 * writeable QOM property.
2483 */
2484static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
2485{
2486 ObjectPropertyIterator iter;
2487 ObjectProperty *prop;
2488
2489 object_property_iter_init(&iter, OBJECT(cpu));
2490 while ((prop = object_property_iter_next(&iter))) {
2491 /* skip read-only or write-only properties */
2492 if (!prop->get || !prop->set) {
2493 continue;
2494 }
2495
2496 /* "hotplugged" is the only property that is configurable
2497 * on the command-line but will be set differently on CPUs
2498 * created using "-cpu ... -smp ..." and by CPUs created
2499 * on the fly by x86_cpu_from_model() for querying. Skip it.
2500 */
2501 if (!strcmp(prop->name, "hotplugged")) {
2502 continue;
2503 }
2504 x86_cpu_expand_prop(cpu, props, prop->name);
2505 }
2506}
2507
f99fd7ca
EH		 2508static void object_apply_props(Object *obj, QDict *props, Error **errp)
2509{
2510 const QDictEntry *prop;
2511 Error *err = NULL;
2512
2513 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
2514 object_property_set_qobject(obj, qdict_entry_value(prop),
2515 qdict_entry_key(prop), &err);
2516 if (err) {
2517 break;
2518 }
2519 }
2520
2521 error_propagate(errp, err);
2522}
2523
2524/* Create X86CPU object according to model+props specification */
2525static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
2526{
2527 X86CPU *xc = NULL;
2528 X86CPUClass *xcc;
2529 Error *err = NULL;
2530
2531 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
2532 if (xcc == NULL) {
2533 error_setg(&err, "CPU model '%s' not found", model);
2534 goto out;
2535 }
2536
2537 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2538 if (props) {
2539 object_apply_props(OBJECT(xc), props, &err);
2540 if (err) {
2541 goto out;
2542 }
2543 }
2544
2545 x86_cpu_expand_features(xc, &err);
2546 if (err) {
2547 goto out;
2548 }
2549
2550out:
2551 if (err) {
2552 error_propagate(errp, err);
2553 object_unref(OBJECT(xc));
2554 xc = NULL;
2555 }
2556 return xc;
2557}
2558
2559CpuModelExpansionInfo *
2560arch_query_cpu_model_expansion(CpuModelExpansionType type,
2561 CpuModelInfo *model,
2562 Error **errp)
2563{
2564 X86CPU *xc = NULL;
2565 Error *err = NULL;
2566 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
2567 QDict *props = NULL;
2568 const char *base_name;
2569
2570 xc = x86_cpu_from_model(model->name,
2571 model->has_props ?
2572 qobject_to_qdict(model->props) :
2573 NULL, &err);
2574 if (err) {
2575 goto out;
2576 }
2577
b8097deb 2578 props = qdict_new();
f99fd7ca
EH		 2579
2580 switch (type) {
2581 case CPU_MODEL_EXPANSION_TYPE_STATIC:
2582 /* Static expansion will be based on "base" only */
2583 base_name = "base";
b8097deb 2584 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 2585 break;
2586 case CPU_MODEL_EXPANSION_TYPE_FULL:
2587 /* As we don't return every single property, full expansion needs
2588 * to keep the original model name+props, and add extra
2589 * properties on top of that.
2590 */
2591 base_name = model->name;
b8097deb 2592 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 2593 break;
2594 default:
2595 error_setg(&err, "Unsupportted expansion type");
2596 goto out;
2597 }
2598
2599 if (!props) {
2600 props = qdict_new();
2601 }
2602 x86_cpu_to_dict(xc, props);
2603
2604 ret->model = g_new0(CpuModelInfo, 1);
2605 ret->model->name = g_strdup(base_name);
2606 ret->model->props = QOBJECT(props);
2607 ret->model->has_props = true;
2608
2609out:
2610 object_unref(OBJECT(xc));
2611 if (err) {
2612 error_propagate(errp, err);
2613 qapi_free_CpuModelExpansionInfo(ret);
2614 ret = NULL;
2615 }
2616 return ret;
2617}
2618
00fcd100
AB		 2619static gchar *x86_gdb_arch_name(CPUState *cs)
2620{
2621#ifdef TARGET_X86_64
2622 return g_strdup("i386:x86-64");
2623#else
2624 return g_strdup("i386");
2625#endif
2626}
2627
0856579c 2628X86CPU *cpu_x86_init(const char *cpu_model)
7f833247 2629{
a57d0163 2630 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
5c3c6a68
AF		 2631}
2632
d940ee9b
EH		 2633static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2634{
2635 X86CPUDefinition *cpudef = data;
2636 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2637
2638 xcc->cpu_def = cpudef;
bd72159d 2639 xcc->migration_safe = true;
d940ee9b
EH		 2640}
2641
2642static void x86_register_cpudef_type(X86CPUDefinition *def)
2643{
2644 char *typename = x86_cpu_type_name(def->name);
2645 TypeInfo ti = {
2646 .name = typename,
2647 .parent = TYPE_X86_CPU,
2648 .class_init = x86_cpu_cpudef_class_init,
2649 .class_data = def,
2650 };
2651
2a923a29
EH		 2652 /* AMD aliases are handled at runtime based on CPUID vendor, so
2653 * they shouldn't be set on the CPU model table.
2654 */
2655 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
2656
d940ee9b
EH		 2657 type_register(&ti);
2658 g_free(typename);
2659}
2660
c6dc6f63 2661#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2662
0e26b7b8
BS		 2663void cpu_clear_apic_feature(CPUX86State *env)
2664{
0514ef2f 2665 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2666}
2667
c6dc6f63
AP		 2668#endif /* !CONFIG_USER_ONLY */
2669
c6dc6f63
AP		 2670void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2671 uint32_t *eax, uint32_t *ebx,
2672 uint32_t *ecx, uint32_t *edx)
2673{
a60f24b5
AF		 2674 X86CPU *cpu = x86_env_get_cpu(env);
2675 CPUState *cs = CPU(cpu);
14c985cf 2676 uint32_t pkg_offset;
4ed3d478 2677 uint32_t limit;
1ce36bfe 2678 uint32_t signature[3];
a60f24b5 2679
4ed3d478
DB		 2680 /* Calculate & apply limits for different index ranges */
2681 if (index >= 0xC0000000) {
2682 limit = env->cpuid_xlevel2;
2683 } else if (index >= 0x80000000) {
2684 limit = env->cpuid_xlevel;
1ce36bfe
DB		 2685 } else if (index >= 0x40000000) {
2686 limit = 0x40000001;
c6dc6f63 2687 } else {
4ed3d478
DB		 2688 limit = env->cpuid_level;
2689 }
2690
2691 if (index > limit) {
2692 /* Intel documentation states that invalid EAX input will
2693 * return the same information as EAX=cpuid_level
2694 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2695 */
2696 index = env->cpuid_level;
c6dc6f63
AP		 2697 }
2698
2699 switch(index) {
2700 case 0:
2701 *eax = env->cpuid_level;
5eb2f7a4
EH		 2702 *ebx = env->cpuid_vendor1;
2703 *edx = env->cpuid_vendor2;
2704 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2705 break;
2706 case 1:
2707 *eax = env->cpuid_version;
7e72a45c
EH		 2708 *ebx = (cpu->apic_id << 24) |
2709 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2710 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2711 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2712 *ecx |= CPUID_EXT_OSXSAVE;
2713 }
0514ef2f 2714 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2715 if (cs->nr_cores * cs->nr_threads > 1) {
2716 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2717 *edx |= CPUID_HT;
c6dc6f63
AP		 2718 }
2719 break;
2720 case 2:
2721 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2722 if (cpu->cache_info_passthrough) {
2723 host_cpuid(index, 0, eax, ebx, ecx, edx);
2724 break;
2725 }
5e891bf8 2726 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 2727 *ebx = 0;
14c985cf
LM		 2728 if (!cpu->enable_l3_cache) {
2729 *ecx = 0;
2730 } else {
2731 *ecx = L3_N_DESCRIPTOR;
2732 }
5e891bf8
EH		 2733 *edx = (L1D_DESCRIPTOR << 16) | \
2734 (L1I_DESCRIPTOR << 8) | \
2735 (L2_DESCRIPTOR);
c6dc6f63
AP		 2736 break;
2737 case 4:
2738 /* cache info: needed for Core compatibility */
787aaf57
BC		 2739 if (cpu->cache_info_passthrough) {
2740 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2741 *eax &= ~0xFC000000;
c6dc6f63 2742 } else {
2f7a21c4 2743 *eax = 0;
76c2975a 2744 switch (count) {
c6dc6f63 2745 case 0: /* L1 dcache info */
5e891bf8
EH		 2746 *eax |= CPUID_4_TYPE_DCACHE | \
2747 CPUID_4_LEVEL(1) | \
2748 CPUID_4_SELF_INIT_LEVEL;
2749 *ebx = (L1D_LINE_SIZE - 1) | \
2750 ((L1D_PARTITIONS - 1) << 12) | \
2751 ((L1D_ASSOCIATIVITY - 1) << 22);
2752 *ecx = L1D_SETS - 1;
2753 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2754 break;
2755 case 1: /* L1 icache info */
5e891bf8
EH		 2756 *eax |= CPUID_4_TYPE_ICACHE | \
2757 CPUID_4_LEVEL(1) | \
2758 CPUID_4_SELF_INIT_LEVEL;
2759 *ebx = (L1I_LINE_SIZE - 1) | \
2760 ((L1I_PARTITIONS - 1) << 12) | \
2761 ((L1I_ASSOCIATIVITY - 1) << 22);
2762 *ecx = L1I_SETS - 1;
2763 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2764 break;
2765 case 2: /* L2 cache info */
5e891bf8
EH		 2766 *eax |= CPUID_4_TYPE_UNIFIED | \
2767 CPUID_4_LEVEL(2) | \
2768 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2769 if (cs->nr_threads > 1) {
2770 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2771 }
5e891bf8
EH		 2772 *ebx = (L2_LINE_SIZE - 1) | \
2773 ((L2_PARTITIONS - 1) << 12) | \
2774 ((L2_ASSOCIATIVITY - 1) << 22);
2775 *ecx = L2_SETS - 1;
2776 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63 2777 break;
14c985cf
LM		 2778 case 3: /* L3 cache info */
2779 if (!cpu->enable_l3_cache) {
2780 *eax = 0;
2781 *ebx = 0;
2782 *ecx = 0;
2783 *edx = 0;
2784 break;
2785 }
2786 *eax |= CPUID_4_TYPE_UNIFIED | \
2787 CPUID_4_LEVEL(3) | \
2788 CPUID_4_SELF_INIT_LEVEL;
2789 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2790 *eax |= ((1 << pkg_offset) - 1) << 14;
2791 *ebx = (L3_N_LINE_SIZE - 1) | \
2792 ((L3_N_PARTITIONS - 1) << 12) | \
2793 ((L3_N_ASSOCIATIVITY - 1) << 22);
2794 *ecx = L3_N_SETS - 1;
2795 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2796 break;
c6dc6f63
AP		 2797 default: /* end of info */
2798 *eax = 0;
2799 *ebx = 0;
2800 *ecx = 0;
2801 *edx = 0;
2802 break;
76c2975a
PB		 2803 }
2804 }
2805
2806 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2807 if ((*eax & 31) && cs->nr_cores > 1) {
2808 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2809 }
2810 break;
2811 case 5:
2812 /* mwait info: needed for Core compatibility */
2813 *eax = 0; /* Smallest monitor-line size in bytes */
2814 *ebx = 0; /* Largest monitor-line size in bytes */
2815 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2816 *edx = 0;
2817 break;
2818 case 6:
2819 /* Thermal and Power Leaf */
28b8e4d0 2820 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2821 *ebx = 0;
2822 *ecx = 0;
2823 *edx = 0;
2824 break;
f7911686 2825 case 7:
13526728
EH		 2826 /* Structured Extended Feature Flags Enumeration Leaf */
2827 if (count == 0) {
2828 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2829 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2830 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2831 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2832 *ecx |= CPUID_7_0_ECX_OSPKE;
2833 }
95ea69fb 2834 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 2835 } else {
2836 *eax = 0;
2837 *ebx = 0;
2838 *ecx = 0;
2839 *edx = 0;
2840 }
2841 break;
c6dc6f63
AP		 2842 case 9:
2843 /* Direct Cache Access Information Leaf */
2844 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2845 *ebx = 0;
2846 *ecx = 0;
2847 *edx = 0;
2848 break;
2849 case 0xA:
2850 /* Architectural Performance Monitoring Leaf */
9337e3b6 2851 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2852 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2853
2854 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2855 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2856 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2857 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2858 } else {
2859 *eax = 0;
2860 *ebx = 0;
2861 *ecx = 0;
2862 *edx = 0;
2863 }
c6dc6f63 2864 break;
5232d00a
RK		 2865 case 0xB:
2866 /* Extended Topology Enumeration Leaf */
2867 if (!cpu->enable_cpuid_0xb) {
2868 *eax = *ebx = *ecx = *edx = 0;
2869 break;
2870 }
2871
2872 *ecx = count & 0xff;
2873 *edx = cpu->apic_id;
2874
2875 switch (count) {
2876 case 0:
eab60fb9
MAL		 2877 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
2878 *ebx = cs->nr_threads;
5232d00a
RK		 2879 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2880 break;
2881 case 1:
eab60fb9
MAL		 2882 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2883 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 2884 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2885 break;
2886 default:
2887 *eax = 0;
2888 *ebx = 0;
2889 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2890 }
2891
2892 assert(!(*eax & ~0x1f));
2893 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2894 break;
2560f19f 2895 case 0xD: {
51e49430 2896 /* Processor Extended State */
2560f19f
PB		 2897 *eax = 0;
2898 *ebx = 0;
2899 *ecx = 0;
2900 *edx = 0;
19dc85db 2901 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2902 break;
2903 }
4928cd6d 2904
2560f19f 2905 if (count == 0) {
96193c22
EH		 2906 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
2907 *eax = env->features[FEAT_XSAVE_COMP_LO];
2908 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 2909 *ebx = *ecx;
2910 } else if (count == 1) {
0bb0b2d2 2911 *eax = env->features[FEAT_XSAVE];
f4f1110e 2912 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 2913 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
2914 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 2915 *eax = esa->size;
2916 *ebx = esa->offset;
2560f19f 2917 }
51e49430
SY		 2918 }
2919 break;
2560f19f 2920 }
1ce36bfe
DB		 2921 case 0x40000000:
2922 /*
2923 * CPUID code in kvm_arch_init_vcpu() ignores stuff
2924 * set here, but we restrict to TCG none the less.
2925 */
2926 if (tcg_enabled() && cpu->expose_tcg) {
2927 memcpy(signature, "TCGTCGTCGTCG", 12);
2928 *eax = 0x40000001;
2929 *ebx = signature[0];
2930 *ecx = signature[1];
2931 *edx = signature[2];
2932 } else {
2933 *eax = 0;
2934 *ebx = 0;
2935 *ecx = 0;
2936 *edx = 0;
2937 }
2938 break;
2939 case 0x40000001:
2940 *eax = 0;
2941 *ebx = 0;
2942 *ecx = 0;
2943 *edx = 0;
2944 break;
c6dc6f63
AP		 2945 case 0x80000000:
2946 *eax = env->cpuid_xlevel;
2947 *ebx = env->cpuid_vendor1;
2948 *edx = env->cpuid_vendor2;
2949 *ecx = env->cpuid_vendor3;
2950 break;
2951 case 0x80000001:
2952 *eax = env->cpuid_version;
2953 *ebx = 0;
0514ef2f
EH		 2954 *ecx = env->features[FEAT_8000_0001_ECX];
2955 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2956
2957 /* The Linux kernel checks for the CMPLegacy bit and
2958 * discards multiple thread information if it is set.
cb8d4c8f 2959 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2960 */
ce3960eb 2961 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2962 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2963 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2964 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2965 *ecx |= 1 << 1; /* CmpLegacy bit */
2966 }
2967 }
c6dc6f63
AP		 2968 break;
2969 case 0x80000002:
2970 case 0x80000003:
2971 case 0x80000004:
2972 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2973 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2974 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2975 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2976 break;
2977 case 0x80000005:
2978 /* cache info (L1 cache) */
787aaf57
BC		 2979 if (cpu->cache_info_passthrough) {
2980 host_cpuid(index, 0, eax, ebx, ecx, edx);
2981 break;
2982 }
5e891bf8
EH		 2983 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2984 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2985 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2986 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2987 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2988 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2989 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2990 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2991 break;
2992 case 0x80000006:
2993 /* cache info (L2 cache) */
787aaf57
BC		 2994 if (cpu->cache_info_passthrough) {
2995 host_cpuid(index, 0, eax, ebx, ecx, edx);
2996 break;
2997 }
5e891bf8
EH		 2998 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2999 (L2_DTLB_2M_ENTRIES << 16) | \
3000 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
3001 (L2_ITLB_2M_ENTRIES);
3002 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
3003 (L2_DTLB_4K_ENTRIES << 16) | \
3004 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
3005 (L2_ITLB_4K_ENTRIES);
3006 *ecx = (L2_SIZE_KB_AMD << 16) | \
3007 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
3008 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
14c985cf
LM		 3009 if (!cpu->enable_l3_cache) {
3010 *edx = ((L3_SIZE_KB / 512) << 18) | \
3011 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
3012 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
3013 } else {
3014 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
3015 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
3016 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
3017 }
c6dc6f63 3018 break;
303752a9
MT		 3019 case 0x80000007:
3020 *eax = 0;
3021 *ebx = 0;
3022 *ecx = 0;
3023 *edx = env->features[FEAT_8000_0007_EDX];
3024 break;
c6dc6f63
AP		 3025 case 0x80000008:
3026 /* virtual & phys address size in low 2 bytes. */
0514ef2f 3027 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 3028 /* 64 bit processor */
3029 *eax = cpu->phys_bits; /* configurable physical bits */
3030 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
3031 *eax |= 0x00003900; /* 57 bits virtual */
3032 } else {
3033 *eax |= 0x00003000; /* 48 bits virtual */
3034 }
c6dc6f63 3035 } else {
af45907a 3036 *eax = cpu->phys_bits;
c6dc6f63
AP		 3037 }
3038 *ebx = 0;
3039 *ecx = 0;
3040 *edx = 0;
ce3960eb
AF		 3041 if (cs->nr_cores * cs->nr_threads > 1) {
3042 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 3043 }
3044 break;
3045 case 0x8000000A:
0514ef2f 3046 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 3047 *eax = 0x00000001; /* SVM Revision */
3048 *ebx = 0x00000010; /* nr of ASIDs */
3049 *ecx = 0;
0514ef2f 3050 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 3051 } else {
3052 *eax = 0;
3053 *ebx = 0;
3054 *ecx = 0;
3055 *edx = 0;
3056 }
c6dc6f63 3057 break;
b3baa152
BW		 3058 case 0xC0000000:
3059 *eax = env->cpuid_xlevel2;
3060 *ebx = 0;
3061 *ecx = 0;
3062 *edx = 0;
3063 break;
3064 case 0xC0000001:
3065 /* Support for VIA CPU's CPUID instruction */
3066 *eax = env->cpuid_version;
3067 *ebx = 0;
3068 *ecx = 0;
0514ef2f 3069 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 3070 break;
3071 case 0xC0000002:
3072 case 0xC0000003:
3073 case 0xC0000004:
3074 /* Reserved for the future, and now filled with zero */
3075 *eax = 0;
3076 *ebx = 0;
3077 *ecx = 0;
3078 *edx = 0;
3079 break;
c6dc6f63
AP		 3080 default:
3081 /* reserved values: zero */
3082 *eax = 0;
3083 *ebx = 0;
3084 *ecx = 0;
3085 *edx = 0;
3086 break;
3087 }
3088}
5fd2087a
AF		 3089
3090/* CPUClass::reset() */
3091static void x86_cpu_reset(CPUState *s)
3092{
3093 X86CPU *cpu = X86_CPU(s);
3094 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
3095 CPUX86State *env = &cpu->env;
a114d25d
RH		 3096 target_ulong cr4;
3097 uint64_t xcr0;
c1958aea
AF		 3098 int i;
3099
5fd2087a
AF		 3100 xcc->parent_reset(s);
3101
5e992a8e 3102 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 3103
c1958aea
AF		 3104 env->old_exception = -1;
3105
3106 /* init to reset state */
3107
c1958aea
AF		 3108 env->hflags2 |= HF2_GIF_MASK;
3109
3110 cpu_x86_update_cr0(env, 0x60000010);
3111 env->a20_mask = ~0x0;
3112 env->smbase = 0x30000;
3113
3114 env->idt.limit = 0xffff;
3115 env->gdt.limit = 0xffff;
3116 env->ldt.limit = 0xffff;
3117 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
3118 env->tr.limit = 0xffff;
3119 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
3120
3121 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
3122 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
3123 DESC_R_MASK | DESC_A_MASK);
3124 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
3125 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3126 DESC_A_MASK);
3127 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
3128 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3129 DESC_A_MASK);
3130 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
3131 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3132 DESC_A_MASK);
3133 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
3134 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3135 DESC_A_MASK);
3136 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
3137 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3138 DESC_A_MASK);
3139
3140 env->eip = 0xfff0;
3141 env->regs[R_EDX] = env->cpuid_version;
3142
3143 env->eflags = 0x2;
3144
3145 /* FPU init */
3146 for (i = 0; i < 8; i++) {
3147 env->fptags[i] = 1;
3148 }
5bde1407 3149 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 3150
3151 env->mxcsr = 0x1f80;
a114d25d
RH		 3152 /* All units are in INIT state. */
3153 env->xstate_bv = 0;
c1958aea
AF		 3154
3155 env->pat = 0x0007040600070406ULL;
3156 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
3157
3158 memset(env->dr, 0, sizeof(env->dr));
3159 env->dr[6] = DR6_FIXED_1;
3160 env->dr[7] = DR7_FIXED_1;
b3310ab3 3161 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 3162 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 3163
a114d25d 3164 cr4 = 0;
cfc3b074 3165 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 3166
3167#ifdef CONFIG_USER_ONLY
3168 /* Enable all the features for user-mode. */
3169 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 3170 xcr0 |= XSTATE_SSE_MASK;
a114d25d 3171 }
0f70ed47
PB		 3172 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
3173 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 3174 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 3175 xcr0 |= 1ull << i;
3176 }
a114d25d 3177 }
0f70ed47 3178
a114d25d
RH		 3179 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
3180 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
3181 }
07929f2a
RH		 3182 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
3183 cr4 |= CR4_FSGSBASE_MASK;
3184 }
a114d25d
RH		 3185#endif
3186
3187 env->xcr0 = xcr0;
3188 cpu_x86_update_cr4(env, cr4);
0522604b 3189
9db2efd9
AW		 3190 /*
3191 * SDM 11.11.5 requires:
3192 * - IA32_MTRR_DEF_TYPE MSR.E = 0
3193 * - IA32_MTRR_PHYSMASKn.V = 0
3194 * All other bits are undefined. For simplification, zero it all.
3195 */
3196 env->mtrr_deftype = 0;
3197 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
3198 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
3199
dd673288
IM		 3200#if !defined(CONFIG_USER_ONLY)
3201 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 3202 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 3203
259186a7 3204 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 3205
3206 if (kvm_enabled()) {
3207 kvm_arch_reset_vcpu(cpu);
3208 }
dd673288 3209#endif
5fd2087a
AF		 3210}
3211
dd673288
IM		 3212#ifndef CONFIG_USER_ONLY
3213bool cpu_is_bsp(X86CPU *cpu)
3214{
02e51483 3215 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 3216}
65dee380
IM		 3217
3218/* TODO: remove me, when reset over QOM tree is implemented */
3219static void x86_cpu_machine_reset_cb(void *opaque)
3220{
3221 X86CPU *cpu = opaque;
3222 cpu_reset(CPU(cpu));
3223}
dd673288
IM		 3224#endif
3225
de024815
AF		 3226static void mce_init(X86CPU *cpu)
3227{
3228 CPUX86State *cenv = &cpu->env;
3229 unsigned int bank;
3230
3231 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 3232 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 3233 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 3234 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
3235 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 3236 cenv->mcg_ctl = ~(uint64_t)0;
3237 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
3238 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
3239 }
3240 }
3241}
3242
bdeec802 3243#ifndef CONFIG_USER_ONLY
2f114315 3244APICCommonClass *apic_get_class(void)
bdeec802 3245{
bdeec802
IM		 3246 const char *apic_type = "apic";
3247
15eafc2e 3248 if (kvm_apic_in_kernel()) {
bdeec802
IM		 3249 apic_type = "kvm-apic";
3250 } else if (xen_enabled()) {
3251 apic_type = "xen-apic";
3252 }
3253
2f114315
RK		 3254 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
3255}
3256
3257static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
3258{
3259 APICCommonState *apic;
3260 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
3261
3262 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 3263
6816b1b3
IM		 3264 object_property_add_child(OBJECT(cpu), "lapic",
3265 OBJECT(cpu->apic_state), &error_abort);
67e55caa 3266 object_unref(OBJECT(cpu->apic_state));
6816b1b3 3267
33d7a288 3268 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 3269 /* TODO: convert to link<> */
02e51483 3270 apic = APIC_COMMON(cpu->apic_state);
60671e58 3271 apic->cpu = cpu;
8d42d2d3 3272 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 3273}
3274
3275static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3276{
8d42d2d3
CF		 3277 APICCommonState *apic;
3278 static bool apic_mmio_map_once;
3279
02e51483 3280 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 3281 return;
3282 }
6e8e2651
MA		 3283 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
3284 errp);
8d42d2d3
CF		 3285
3286 /* Map APIC MMIO area */
3287 apic = APIC_COMMON(cpu->apic_state);
3288 if (!apic_mmio_map_once) {
3289 memory_region_add_subregion_overlap(get_system_memory(),
3290 apic->apicbase &
3291 MSR_IA32_APICBASE_BASE,
3292 &apic->io_memory,
3293 0x1000);
3294 apic_mmio_map_once = true;
3295 }
bdeec802 3296}
f809c605
PB		 3297
3298static void x86_cpu_machine_done(Notifier *n, void *unused)
3299{
3300 X86CPU *cpu = container_of(n, X86CPU, machine_done);
3301 MemoryRegion *smram =
3302 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
3303
3304 if (smram) {
3305 cpu->smram = g_new(MemoryRegion, 1);
3306 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
3307 smram, 0, 1ull << 32);
f8c45c65 3308 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 3309 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
3310 }
3311}
d3c64d6a
IM		 3312#else
3313static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3314{
3315}
bdeec802
IM		 3316#endif
3317
11f6fee5
DDAG		 3318/* Note: Only safe for use on x86(-64) hosts */
3319static uint32_t x86_host_phys_bits(void)
3320{
3321 uint32_t eax;
3322 uint32_t host_phys_bits;
3323
3324 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
3325 if (eax >= 0x80000008) {
3326 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
3327 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3328 * at 23:16 that can specify a maximum physical address bits for
3329 * the guest that can override this value; but I've not seen
3330 * anything with that set.
3331 */
3332 host_phys_bits = eax & 0xff;
3333 } else {
3334 /* It's an odd 64 bit machine that doesn't have the leaf for
3335 * physical address bits; fall back to 36 that's most older
3336 * Intel.
3337 */
3338 host_phys_bits = 36;
3339 }
3340
3341 return host_phys_bits;
3342}
e48638fd 3343
c39c0edf
EH		 3344static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
3345{
3346 if (*min < value) {
3347 *min = value;
3348 }
3349}
3350
3351/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3352static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
3353{
3354 CPUX86State *env = &cpu->env;
3355 FeatureWordInfo *fi = &feature_word_info[w];
3356 uint32_t eax = fi->cpuid_eax;
3357 uint32_t region = eax & 0xF0000000;
3358
3359 if (!env->features[w]) {
3360 return;
3361 }
3362
3363 switch (region) {
3364 case 0x00000000:
3365 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
3366 break;
3367 case 0x80000000:
3368 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
3369 break;
3370 case 0xC0000000:
3371 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
3372 break;
3373 }
3374}
3375
2ca8a8be
EH		 3376/* Calculate XSAVE components based on the configured CPU feature flags */
3377static void x86_cpu_enable_xsave_components(X86CPU *cpu)
3378{
3379 CPUX86State *env = &cpu->env;
3380 int i;
96193c22 3381 uint64_t mask;
2ca8a8be
EH		 3382
3383 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
3384 return;
3385 }
3386
e3c9022b
EH		 3387 mask = 0;
3388 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 3389 const ExtSaveArea *esa = &x86_ext_save_areas[i];
3390 if (env->features[esa->feature] & esa->bits) {
96193c22 3391 mask |= (1ULL << i);
2ca8a8be
EH		 3392 }
3393 }
3394
96193c22
EH		 3395 env->features[FEAT_XSAVE_COMP_LO] = mask;
3396 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 3397}
3398
b8d834a0
EH		 3399/***** Steps involved on loading and filtering CPUID data
3400 *
3401 * When initializing and realizing a CPU object, the steps
3402 * involved in setting up CPUID data are:
3403 *
3404 * 1) Loading CPU model definition (X86CPUDefinition). This is
3405 * implemented by x86_cpu_load_def() and should be completely
3406 * transparent, as it is done automatically by instance_init.
3407 * No code should need to look at X86CPUDefinition structs
3408 * outside instance_init.
3409 *
3410 * 2) CPU expansion. This is done by realize before CPUID
3411 * filtering, and will make sure host/accelerator data is
3412 * loaded for CPU models that depend on host capabilities
3413 * (e.g. "host"). Done by x86_cpu_expand_features().
3414 *
3415 * 3) CPUID filtering. This initializes extra data related to
3416 * CPUID, and checks if the host supports all capabilities
3417 * required by the CPU. Runnability of a CPU model is
3418 * determined at this step. Done by x86_cpu_filter_features().
3419 *
3420 * Some operations don't require all steps to be performed.
3421 * More precisely:
3422 *
3423 * - CPU instance creation (instance_init) will run only CPU
3424 * model loading. CPU expansion can't run at instance_init-time
3425 * because host/accelerator data may be not available yet.
3426 * - CPU realization will perform both CPU model expansion and CPUID
3427 * filtering, and return an error in case one of them fails.
3428 * - query-cpu-definitions needs to run all 3 steps. It needs
3429 * to run CPUID filtering, as the 'unavailable-features'
3430 * field is set based on the filtering results.
3431 * - The query-cpu-model-expansion QMP command only needs to run
3432 * CPU model loading and CPU expansion. It should not filter
3433 * any CPUID data based on host capabilities.
3434 */
3435
3436/* Expand CPU configuration data, based on configured features
3437 * and host/accelerator capabilities when appropriate.
3438 */
3439static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 3440{
b34d12d1 3441 CPUX86State *env = &cpu->env;
dc15c051 3442 FeatureWord w;
2fae0d96 3443 GList *l;
41f3d4d6 3444 Error *local_err = NULL;
9886e834 3445
d4a606b3
EH		 3446 /*TODO: Now cpu->max_features doesn't overwrite features
3447 * set using QOM properties, and we can convert
dc15c051
IM		 3448 * plus_features & minus_features to global properties
3449 * inside x86_cpu_parse_featurestr() too.
3450 */
44bd8e53 3451 if (cpu->max_features) {
dc15c051 3452 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 3453 /* Override only features that weren't set explicitly
3454 * by the user.
3455 */
3456 env->features[w] |=
3457 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
3458 ~env->user_features[w];
dc15c051
IM		 3459 }
3460 }
3461
2fae0d96
EH		 3462 for (l = plus_features; l; l = l->next) {
3463 const char *prop = l->data;
3464 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
3465 if (local_err) {
3466 goto out;
3467 }
3468 }
3469
3470 for (l = minus_features; l; l = l->next) {
3471 const char *prop = l->data;
3472 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
3473 if (local_err) {
3474 goto out;
3475 }
dc15c051
IM		 3476 }
3477
aec661de
EH		 3478 if (!kvm_enabled() || !cpu->expose_kvm) {
3479 env->features[FEAT_KVM] = 0;
3480 }
3481
2ca8a8be 3482 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 3483
3484 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3485 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
3486 if (cpu->full_cpuid_auto_level) {
3487 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
3488 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
3489 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
3490 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
3491 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
3492 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
3493 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
3494 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
3495 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
3496 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 3497 /* SVM requires CPUID[0x8000000A] */
3498 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
3499 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
3500 }
c39c0edf
EH		 3501 }
3502
3503 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3504 if (env->cpuid_level == UINT32_MAX) {
3505 env->cpuid_level = env->cpuid_min_level;
3506 }
3507 if (env->cpuid_xlevel == UINT32_MAX) {
3508 env->cpuid_xlevel = env->cpuid_min_xlevel;
3509 }
3510 if (env->cpuid_xlevel2 == UINT32_MAX) {
3511 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 3512 }
7a059953 3513
41f3d4d6
EH		 3514out:
3515 if (local_err != NULL) {
3516 error_propagate(errp, local_err);
3517 }
3518}
3519
b8d834a0
EH		 3520/*
3521 * Finishes initialization of CPUID data, filters CPU feature
3522 * words based on host availability of each feature.
3523 *
3524 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
3525 */
3526static int x86_cpu_filter_features(X86CPU *cpu)
3527{
3528 CPUX86State *env = &cpu->env;
3529 FeatureWord w;
3530 int rv = 0;
3531
3532 for (w = 0; w < FEATURE_WORDS; w++) {
3533 uint32_t host_feat =
3534 x86_cpu_get_supported_feature_word(w, false);
3535 uint32_t requested_features = env->features[w];
3536 env->features[w] &= host_feat;
3537 cpu->filtered_features[w] = requested_features & ~env->features[w];
3538 if (cpu->filtered_features[w]) {
3539 rv = 1;
3540 }
3541 }
3542
3543 return rv;
3544}
3545
41f3d4d6
EH		 3546#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3547 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3548 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3549#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3550 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3551 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
3552static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
3553{
3554 CPUState *cs = CPU(dev);
3555 X86CPU *cpu = X86_CPU(dev);
3556 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3557 CPUX86State *env = &cpu->env;
3558 Error *local_err = NULL;
3559 static bool ht_warned;
3560
3561 if (xcc->kvm_required && !kvm_enabled()) {
3562 char *name = x86_cpu_class_get_model_name(xcc);
3563 error_setg(&local_err, "CPU model '%s' requires KVM", name);
3564 g_free(name);
3565 goto out;
3566 }
3567
3568 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
3569 error_setg(errp, "apic-id property was not initialized properly");
3570 return;
3571 }
3572
b8d834a0 3573 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 3574 if (local_err) {
3575 goto out;
3576 }
3577
8ca30e86
EH		 3578 if (x86_cpu_filter_features(cpu) &&
3579 (cpu->check_cpuid || cpu->enforce_cpuid)) {
3580 x86_cpu_report_filtered_features(cpu);
3581 if (cpu->enforce_cpuid) {
3582 error_setg(&local_err,
3583 kvm_enabled() ?
3584 "Host doesn't support requested features" :
3585 "TCG doesn't support requested features");
3586 goto out;
3587 }
9997cf7b
EH		 3588 }
3589
9b15cd9e
IM		 3590 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3591 * CPUID[1].EDX.
3592 */
e48638fd 3593 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 3594 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3595 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 3596 & CPUID_EXT2_AMD_ALIASES);
3597 }
3598
11f6fee5
DDAG		 3599 /* For 64bit systems think about the number of physical bits to present.
3600 * ideally this should be the same as the host; anything other than matching
3601 * the host can cause incorrect guest behaviour.
3602 * QEMU used to pick the magic value of 40 bits that corresponds to
3603 * consumer AMD devices but nothing else.
3604 */
af45907a 3605 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a 3606 if (kvm_enabled()) {
11f6fee5
DDAG		 3607 uint32_t host_phys_bits = x86_host_phys_bits();
3608 static bool warned;
3609
3610 if (cpu->host_phys_bits) {
3611 /* The user asked for us to use the host physical bits */
3612 cpu->phys_bits = host_phys_bits;
3613 }
3614
3615 /* Print a warning if the user set it to a value that's not the
3616 * host value.
3617 */
3618 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3619 !warned) {
3dc6f869
AF		 3620 warn_report("Host physical bits (%u)"
3621 " does not match phys-bits property (%u)",
3622 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 3623 warned = true;
3624 }
3625
3626 if (cpu->phys_bits &&
3627 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3628 cpu->phys_bits < 32)) {
af45907a
DDAG		 3629 error_setg(errp, "phys-bits should be between 32 and %u "
3630 " (but is %u)",
3631 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3632 return;
3633 }
3634 } else {
11f6fee5 3635 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 3636 error_setg(errp, "TCG only supports phys-bits=%u",
3637 TCG_PHYS_ADDR_BITS);
3638 return;
3639 }
3640 }
11f6fee5
DDAG		 3641 /* 0 means it was not explicitly set by the user (or by machine
3642 * compat_props or by the host code above). In this case, the default
3643 * is the value used by TCG (40).
3644 */
3645 if (cpu->phys_bits == 0) {
3646 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3647 }
af45907a
DDAG		 3648 } else {
3649 /* For 32 bit systems don't use the user set value, but keep
3650 * phys_bits consistent with what we tell the guest.
3651 */
3652 if (cpu->phys_bits != 0) {
3653 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3654 return;
3655 }
fefb41bf 3656
af45907a
DDAG		 3657 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3658 cpu->phys_bits = 36;
3659 } else {
3660 cpu->phys_bits = 32;
3661 }
3662 }
ce5b1bbf
LV		 3663 cpu_exec_realizefn(cs, &local_err);
3664 if (local_err != NULL) {
3665 error_propagate(errp, local_err);
3666 return;
3667 }
42ecabaa 3668
57f2453a
EH		 3669 if (tcg_enabled()) {
3670 tcg_x86_init();
3671 }
3672
65dee380
IM		 3673#ifndef CONFIG_USER_ONLY
3674 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 3675
0514ef2f 3676 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 3677 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 3678 if (local_err != NULL) {
4dc1f449 3679 goto out;
bdeec802
IM		 3680 }
3681 }
65dee380
IM		 3682#endif
3683
7a059953 3684 mce_init(cpu);
2001d0cd
PB		 3685
3686#ifndef CONFIG_USER_ONLY
3687 if (tcg_enabled()) {
f8c45c65
PB		 3688 AddressSpace *as_normal = address_space_init_shareable(cs->memory,
3689 "cpu-memory");
3690 AddressSpace *as_smm = g_new(AddressSpace, 1);
56943e8c 3691
f809c605 3692 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 3693 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 3694
3695 /* Outer container... */
3696 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 3697 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 3698
3699 /* ... with two regions inside: normal system memory with low
3700 * priority, and...
3701 */
3702 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3703 get_system_memory(), 0, ~0ull);
3704 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3705 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 3706 address_space_init(as_smm, cpu->cpu_as_root, "CPU");
3707
3708 cs->num_ases = 2;
3709 cpu_address_space_init(cs, as_normal, 0);
3710 cpu_address_space_init(cs, as_smm, 1);
f809c605
PB		 3711
3712 /* ... SMRAM with higher priority, linked from /machine/smram. */
3713 cpu->machine_done.notify = x86_cpu_machine_done;
3714 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 3715 }
3716#endif
3717
14a10fc3 3718 qemu_init_vcpu(cs);
d3c64d6a 3719
e48638fd
WH		 3720 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3721 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3722 * based on inputs (sockets,cores,threads), it is still better to gives
3723 * users a warning.
3724 *
3725 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3726 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3727 */
3728 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3729 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3730 " -smp options properly.");
3731 ht_warned = true;
3732 }
3733
d3c64d6a
IM		 3734 x86_cpu_apic_realize(cpu, &local_err);
3735 if (local_err != NULL) {
3736 goto out;
3737 }
14a10fc3 3738 cpu_reset(cs);
2b6f294c 3739
4dc1f449 3740 xcc->parent_realize(dev, &local_err);
2001d0cd 3741
4dc1f449
IM		 3742out:
3743 if (local_err != NULL) {
3744 error_propagate(errp, local_err);
3745 return;
3746 }
7a059953
AF		 3747}
3748
c884776e
IM		 3749static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3750{
3751 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 3752 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3753 Error *local_err = NULL;
c884776e
IM		 3754
3755#ifndef CONFIG_USER_ONLY
3756 cpu_remove_sync(CPU(dev));
3757 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3758#endif
3759
3760 if (cpu->apic_state) {
3761 object_unparent(OBJECT(cpu->apic_state));
3762 cpu->apic_state = NULL;
3763 }
7bbc124e
LV		 3764
3765 xcc->parent_unrealize(dev, &local_err);
3766 if (local_err != NULL) {
3767 error_propagate(errp, local_err);
3768 return;
3769 }
c884776e
IM		 3770}
3771
38e5c119 3772typedef struct BitProperty {
a7b0ffac 3773 FeatureWord w;
38e5c119
EH		 3774 uint32_t mask;
3775} BitProperty;
3776
d7bce999
EB		 3777static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3778 void *opaque, Error **errp)
38e5c119 3779{
a7b0ffac 3780 X86CPU *cpu = X86_CPU(obj);
38e5c119 3781 BitProperty *fp = opaque;
a7b0ffac
EH		 3782 uint32_t f = cpu->env.features[fp->w];
3783 bool value = (f & fp->mask) == fp->mask;
51e72bc1 3784 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3785}
3786
d7bce999
EB		 3787static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3788 void *opaque, Error **errp)
38e5c119
EH		 3789{
3790 DeviceState *dev = DEVICE(obj);
a7b0ffac 3791 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 3792 BitProperty *fp = opaque;
3793 Error *local_err = NULL;
3794 bool value;
3795
3796 if (dev->realized) {
3797 qdev_prop_set_after_realize(dev, name, errp);
3798 return;
3799 }
3800
51e72bc1 3801 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3802 if (local_err) {
3803 error_propagate(errp, local_err);
3804 return;
3805 }
3806
3807 if (value) {
a7b0ffac 3808 cpu->env.features[fp->w] |= fp->mask;
38e5c119 3809 } else {
a7b0ffac 3810 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 3811 }
d4a606b3 3812 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 3813}
3814
3815static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3816 void *opaque)
3817{
3818 BitProperty *prop = opaque;
3819 g_free(prop);
3820}
3821
3822/* Register a boolean property to get/set a single bit in a uint32_t field.
3823 *
3824 * The same property name can be registered multiple times to make it affect
3825 * multiple bits in the same FeatureWord. In that case, the getter will return
3826 * true only if all bits are set.
3827 */
3828static void x86_cpu_register_bit_prop(X86CPU *cpu,
3829 const char *prop_name,
a7b0ffac 3830 FeatureWord w,
38e5c119
EH		 3831 int bitnr)
3832{
3833 BitProperty *fp;
3834 ObjectProperty *op;
3835 uint32_t mask = (1UL << bitnr);
3836
3837 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3838 if (op) {
3839 fp = op->opaque;
a7b0ffac 3840 assert(fp->w == w);
38e5c119
EH		 3841 fp->mask |= mask;
3842 } else {
3843 fp = g_new0(BitProperty, 1);
a7b0ffac 3844 fp->w = w;
38e5c119
EH		 3845 fp->mask = mask;
3846 object_property_add(OBJECT(cpu), prop_name, "bool",
3847 x86_cpu_get_bit_prop,
3848 x86_cpu_set_bit_prop,
3849 x86_cpu_release_bit_prop, fp, &error_abort);
3850 }
3851}
3852
3853static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3854 FeatureWord w,
3855 int bitnr)
3856{
38e5c119 3857 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 3858 const char *name = fi->feat_names[bitnr];
38e5c119 3859
16d2fcaa 3860 if (!name) {
38e5c119
EH		 3861 return;
3862 }
3863
fc7dfd20
EH		 3864 /* Property names should use "-" instead of "_".
3865 * Old names containing underscores are registered as aliases
3866 * using object_property_add_alias()
3867 */
16d2fcaa
EH		 3868 assert(!strchr(name, '_'));
3869 /* aliases don't use "|" delimiters anymore, they are registered
3870 * manually using object_property_add_alias() */
3871 assert(!strchr(name, '|'));
a7b0ffac 3872 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 3873}
3874
d187e08d
AN		 3875static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
3876{
3877 X86CPU *cpu = X86_CPU(cs);
3878 CPUX86State *env = &cpu->env;
3879 GuestPanicInformation *panic_info = NULL;
3880
3881 if (env->features[FEAT_HYPERV_EDX] & HV_X64_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 3882 panic_info = g_malloc0(sizeof(GuestPanicInformation));
3883
e8ed97a6 3884 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d
AN		 3885
3886 assert(HV_X64_MSR_CRASH_PARAMS >= 5);
e8ed97a6
AN		 3887 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
3888 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
3889 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
3890 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
3891 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 3892 }
3893
3894 return panic_info;
3895}
3896static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
3897 const char *name, void *opaque,
3898 Error **errp)
3899{
3900 CPUState *cs = CPU(obj);
3901 GuestPanicInformation *panic_info;
3902
3903 if (!cs->crash_occurred) {
3904 error_setg(errp, "No crash occured");
3905 return;
3906 }
3907
3908 panic_info = x86_cpu_get_crash_info(cs);
3909 if (panic_info == NULL) {
3910 error_setg(errp, "No crash information");
3911 return;
3912 }
3913
3914 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
3915 errp);
3916 qapi_free_GuestPanicInformation(panic_info);
3917}
3918
de024815
AF		 3919static void x86_cpu_initfn(Object *obj)
3920{
55e5c285 3921 CPUState *cs = CPU(obj);
de024815 3922 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3923 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3924 CPUX86State *env = &cpu->env;
38e5c119 3925 FeatureWord w;
de024815 3926
c05efcb1 3927 cs->env_ptr = env;
71ad61d3
AF		 3928
3929 object_property_add(obj, "family", "int",
95b8519d 3930 x86_cpuid_version_get_family,
71ad61d3 3931 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3932 object_property_add(obj, "model", "int",
67e30c83 3933 x86_cpuid_version_get_model,
c5291a4f 3934 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3935 object_property_add(obj, "stepping", "int",
35112e41 3936 x86_cpuid_version_get_stepping,
036e2222 3937 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3938 object_property_add_str(obj, "vendor",
3939 x86_cpuid_get_vendor,
3940 x86_cpuid_set_vendor, NULL);
938d4c25 3941 object_property_add_str(obj, "model-id",
63e886eb 3942 x86_cpuid_get_model_id,
938d4c25 3943 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3944 object_property_add(obj, "tsc-frequency", "int",
3945 x86_cpuid_get_tsc_freq,
3946 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 3947 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3948 x86_cpu_get_feature_words,
7e5292b5
EH		 3949 NULL, NULL, (void *)env->features, NULL);
3950 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3951 x86_cpu_get_feature_words,
3952 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3953
d187e08d
AN		 3954 object_property_add(obj, "crash-information", "GuestPanicInformation",
3955 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
3956
92067bf4 3957 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3958
38e5c119
EH		 3959 for (w = 0; w < FEATURE_WORDS; w++) {
3960 int bitnr;
3961
3962 for (bitnr = 0; bitnr < 32; bitnr++) {
3963 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3964 }
3965 }
3966
16d2fcaa
EH		 3967 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
3968 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
3969 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
3970 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
3971 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
3972 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
3973 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
3974
54b8dc7c
EH		 3975 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
3976 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
3977 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
3978 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
3979 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
3980 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
3981 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
3982 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
3983 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
3984 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
3985 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
3986 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
3987 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
3988 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
3989 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
3990 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
3991 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
3992 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
3993 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
3994 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
3995 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
3996
0bacd8b3
EH		 3997 if (xcc->cpu_def) {
3998 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3999 }
de024815
AF		 4000}
4001
997395d3
IM		 4002static int64_t x86_cpu_get_arch_id(CPUState *cs)
4003{
4004 X86CPU *cpu = X86_CPU(cs);
997395d3 4005
7e72a45c 4006 return cpu->apic_id;
997395d3
IM		 4007}
4008
444d5590
AF		 4009static bool x86_cpu_get_paging_enabled(const CPUState *cs)
4010{
4011 X86CPU *cpu = X86_CPU(cs);
4012
4013 return cpu->env.cr[0] & CR0_PG_MASK;
4014}
4015
f45748f1
AF		 4016static void x86_cpu_set_pc(CPUState *cs, vaddr value)
4017{
4018 X86CPU *cpu = X86_CPU(cs);
4019
4020 cpu->env.eip = value;
4021}
4022
bdf7ae5b
AF		 4023static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
4024{
4025 X86CPU *cpu = X86_CPU(cs);
4026
4027 cpu->env.eip = tb->pc - tb->cs_base;
4028}
4029
8c2e1b00
AF		 4030static bool x86_cpu_has_work(CPUState *cs)
4031{
4032 X86CPU *cpu = X86_CPU(cs);
4033 CPUX86State *env = &cpu->env;
4034
6220e900
PD		 4035 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
4036 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 4037 (env->eflags & IF_MASK)) ||
4038 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
4039 CPU_INTERRUPT_INIT |
4040 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 4041 CPU_INTERRUPT_MCE)) ||
4042 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
4043 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 4044}
4045
9337e3b6 4046static Property x86_cpu_properties[] = {
2da00e31
IM		 4047#ifdef CONFIG_USER_ONLY
4048 /* apic_id = 0 by default for *-user, see commit 9886e834 */
4049 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 4050 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
4051 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
4052 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 4053#else
4054 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 4055 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
4056 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
4057 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 4058#endif
15f8b142 4059 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 4060 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 4061 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 4062 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 4063 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 4064 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 4065 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 4066 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 4067 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 4068 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 4069 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 4070 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 4071 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 4072 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 4073 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 4074 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 4075 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 4076 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 4077 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
4078 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
4079 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
4080 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
4081 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
4082 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4083 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 4084 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 4085 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 4086 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 4087 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 4088 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
4089 false),
0b564e6f 4090 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 4091 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
9337e3b6
EH		 4092 DEFINE_PROP_END_OF_LIST()
4093};
4094
5fd2087a
AF		 4095static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
4096{
4097 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4098 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 4099 DeviceClass *dc = DEVICE_CLASS(oc);
4100
4101 xcc->parent_realize = dc->realize;
7bbc124e 4102 xcc->parent_unrealize = dc->unrealize;
2b6f294c 4103 dc->realize = x86_cpu_realizefn;
c884776e 4104 dc->unrealize = x86_cpu_unrealizefn;
9337e3b6 4105 dc->props = x86_cpu_properties;
5fd2087a
AF		 4106
4107 xcc->parent_reset = cc->reset;
4108 cc->reset = x86_cpu_reset;
91b1df8c 4109 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 4110
500050d1 4111 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 4112 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 4113 cc->has_work = x86_cpu_has_work;
79c664f6 4114#ifdef CONFIG_TCG
97a8ea5a 4115 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 4116 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 4117#endif
878096ee 4118 cc->dump_state = x86_cpu_dump_state;
c86f106b 4119 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 4120 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 4121 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 4122 cc->gdb_read_register = x86_cpu_gdb_read_register;
4123 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 4124 cc->get_arch_id = x86_cpu_get_arch_id;
4125 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 4126#ifdef CONFIG_USER_ONLY
4127 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
4128#else
f8c45c65 4129 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 4130 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 4131 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 4132 cc->write_elf64_note = x86_cpu_write_elf64_note;
4133 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
4134 cc->write_elf32_note = x86_cpu_write_elf32_note;
4135 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 4136 cc->vmsd = &vmstate_x86_cpu;
c72bf468 4137#endif
00fcd100
AB		 4138 cc->gdb_arch_name = x86_gdb_arch_name;
4139#ifdef TARGET_X86_64
b8158192
AB		 4140 cc->gdb_core_xml_file = "i386-64bit.xml";
4141 cc->gdb_num_core_regs = 57;
00fcd100 4142#else
b8158192
AB		 4143 cc->gdb_core_xml_file = "i386-32bit.xml";
4144 cc->gdb_num_core_regs = 41;
00fcd100 4145#endif
79c664f6 4146#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 4147 cc->debug_excp_handler = breakpoint_handler;
4148#endif
374e0cd4
RH		 4149 cc->cpu_exec_enter = x86_cpu_exec_enter;
4150 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27 4151
e90f2a8c 4152 dc->user_creatable = true;
5fd2087a
AF		 4153}
4154
4155static const TypeInfo x86_cpu_type_info = {
4156 .name = TYPE_X86_CPU,
4157 .parent = TYPE_CPU,
4158 .instance_size = sizeof(X86CPU),
de024815 4159 .instance_init = x86_cpu_initfn,
d940ee9b 4160 .abstract = true,
5fd2087a
AF		 4161 .class_size = sizeof(X86CPUClass),
4162 .class_init = x86_cpu_common_class_init,
4163};
4164
5adbed30
EH		 4165
4166/* "base" CPU model, used by query-cpu-model-expansion */
4167static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
4168{
4169 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4170
4171 xcc->static_model = true;
4172 xcc->migration_safe = true;
4173 xcc->model_description = "base CPU model type with no features enabled";
4174 xcc->ordering = 8;
4175}
4176
4177static const TypeInfo x86_base_cpu_type_info = {
4178 .name = X86_CPU_TYPE_NAME("base"),
4179 .parent = TYPE_X86_CPU,
4180 .class_init = x86_cpu_base_class_init,
4181};
4182
5fd2087a
AF		 4183static void x86_cpu_register_types(void)
4184{
d940ee9b
EH		 4185 int i;
4186
5fd2087a 4187 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 4188 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
4189 x86_register_cpudef_type(&builtin_x86_defs[i]);
4190 }
c62f2630 4191 type_register_static(&max_x86_cpu_type_info);
5adbed30 4192 type_register_static(&x86_base_cpu_type_info);
d940ee9b
EH		 4193#ifdef CONFIG_KVM
4194 type_register_static(&host_x86_cpu_type_info);
4195#endif
5fd2087a
AF		 4196}
4197
4198type_init(x86_cpu_register_types)
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