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qobject: Explain how QNum works, and why
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
01b2ffce 32#include "qapi/qmp/types.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
f99fd7ca 37#include "qom/qom-qobject.h"
9c17d615 38#include "sysemu/arch_init.h"
71ad61d3 39
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
5232d00a 46#include "hw/i386/topology.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
2001d0cd 48#include "exec/address-spaces.h"
741da0d3 49#include "hw/hw.h"
0d09e41a 50#include "hw/xen/xen.h"
0d09e41a 51#include "hw/i386/apic_internal.h"
bdeec802
IM		 52#endif
53
5e891bf8
EH		 54
55/* Cache topology CPUID constants: */
56
57/* CPUID Leaf 2 Descriptors */
58
59#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
60#define CPUID_2_L1I_32KB_8WAY_64B 0x30
61#define CPUID_2_L2_2MB_8WAY_64B 0x7d
14c985cf 62#define CPUID_2_L3_16MB_16WAY_64B 0x4d
5e891bf8
EH		 63
64
65/* CPUID Leaf 4 constants: */
66
67/* EAX: */
68#define CPUID_4_TYPE_DCACHE 1
69#define CPUID_4_TYPE_ICACHE 2
70#define CPUID_4_TYPE_UNIFIED 3
71
72#define CPUID_4_LEVEL(l) ((l) << 5)
73
74#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
75#define CPUID_4_FULLY_ASSOC (1 << 9)
76
77/* EDX: */
78#define CPUID_4_NO_INVD_SHARING (1 << 0)
79#define CPUID_4_INCLUSIVE (1 << 1)
80#define CPUID_4_COMPLEX_IDX (1 << 2)
81
82#define ASSOC_FULL 0xFF
83
84/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
85#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
86 a == 2 ? 0x2 : \
87 a == 4 ? 0x4 : \
88 a == 8 ? 0x6 : \
89 a == 16 ? 0x8 : \
90 a == 32 ? 0xA : \
91 a == 48 ? 0xB : \
92 a == 64 ? 0xC : \
93 a == 96 ? 0xD : \
94 a == 128 ? 0xE : \
95 a == ASSOC_FULL ? 0xF : \
96 0 /* invalid value */)
97
98
99/* Definitions of the hardcoded cache entries we expose: */
100
101/* L1 data cache: */
102#define L1D_LINE_SIZE 64
103#define L1D_ASSOCIATIVITY 8
104#define L1D_SETS 64
105#define L1D_PARTITIONS 1
106/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
107#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
108/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
109#define L1D_LINES_PER_TAG 1
110#define L1D_SIZE_KB_AMD 64
111#define L1D_ASSOCIATIVITY_AMD 2
112
113/* L1 instruction cache: */
114#define L1I_LINE_SIZE 64
115#define L1I_ASSOCIATIVITY 8
116#define L1I_SETS 64
117#define L1I_PARTITIONS 1
118/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
119#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
120/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
121#define L1I_LINES_PER_TAG 1
122#define L1I_SIZE_KB_AMD 64
123#define L1I_ASSOCIATIVITY_AMD 2
124
125/* Level 2 unified cache: */
126#define L2_LINE_SIZE 64
127#define L2_ASSOCIATIVITY 16
128#define L2_SETS 4096
129#define L2_PARTITIONS 1
130/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
131/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
132#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
133/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
134#define L2_LINES_PER_TAG 1
135#define L2_SIZE_KB_AMD 512
136
14c985cf 137/* Level 3 unified cache: */
5e891bf8
EH		 138#define L3_SIZE_KB 0 /* disabled */
139#define L3_ASSOCIATIVITY 0 /* disabled */
140#define L3_LINES_PER_TAG 0 /* disabled */
141#define L3_LINE_SIZE 0 /* disabled */
14c985cf
LM		 142#define L3_N_LINE_SIZE 64
143#define L3_N_ASSOCIATIVITY 16
144#define L3_N_SETS 16384
145#define L3_N_PARTITIONS 1
146#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
147#define L3_N_LINES_PER_TAG 1
148#define L3_N_SIZE_KB_AMD 16384
5e891bf8
EH		 149
150/* TLB definitions: */
151
152#define L1_DTLB_2M_ASSOC 1
153#define L1_DTLB_2M_ENTRIES 255
154#define L1_DTLB_4K_ASSOC 1
155#define L1_DTLB_4K_ENTRIES 255
156
157#define L1_ITLB_2M_ASSOC 1
158#define L1_ITLB_2M_ENTRIES 255
159#define L1_ITLB_4K_ASSOC 1
160#define L1_ITLB_4K_ENTRIES 255
161
162#define L2_DTLB_2M_ASSOC 0 /* disabled */
163#define L2_DTLB_2M_ENTRIES 0 /* disabled */
164#define L2_DTLB_4K_ASSOC 4
165#define L2_DTLB_4K_ENTRIES 512
166
167#define L2_ITLB_2M_ASSOC 0 /* disabled */
168#define L2_ITLB_2M_ENTRIES 0 /* disabled */
169#define L2_ITLB_4K_ASSOC 4
170#define L2_ITLB_4K_ENTRIES 512
171
172
173
99b88a17
IM		 174static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
175 uint32_t vendor2, uint32_t vendor3)
176{
177 int i;
178 for (i = 0; i < 4; i++) {
179 dst[i] = vendor1 >> (8 * i);
180 dst[i + 4] = vendor2 >> (8 * i);
181 dst[i + 8] = vendor3 >> (8 * i);
182 }
183 dst[CPUID_VENDOR_SZ] = '\0';
184}
185
621626ce
EH		 186#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
187#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
188 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
189#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
190 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
191 CPUID_PSE36 | CPUID_FXSR)
192#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
193#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
194 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
195 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
196 CPUID_PAE | CPUID_SEP | CPUID_APIC)
197
198#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
199 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
200 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
201 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 202 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 203 /* partly implemented:
204 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
205 /* missing:
206 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
207#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
208 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
209 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 210 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 211 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
212 /* missing:
213 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
214 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
215 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 216 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
217 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 218
219#ifdef TARGET_X86_64
220#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
221#else
222#define TCG_EXT2_X86_64_FEATURES 0
223#endif
224
225#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
226 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
227 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
228 TCG_EXT2_X86_64_FEATURES)
229#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
230 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
231#define TCG_EXT4_FEATURES 0
232#define TCG_SVM_FEATURES 0
233#define TCG_KVM_FEATURES 0
234#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 235 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
236 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 237 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
238 CPUID_7_0_EBX_ERMS)
621626ce 239 /* missing:
07929f2a 240 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 241 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 242 CPUID_7_0_EBX_RDSEED */
6c7c3c21
KS		 243#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
244 CPUID_7_0_ECX_LA57)
95ea69fb 245#define TCG_7_0_EDX_FEATURES 0
303752a9 246#define TCG_APM_FEATURES 0
28b8e4d0 247#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 248#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
249 /* missing:
250 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 251
5ef57876 252typedef struct FeatureWordInfo {
2d5312da
EH		 253 /* feature flags names are taken from "Intel Processor Identification and
254 * the CPUID Instruction" and AMD's "CPUID Specification".
255 * In cases of disagreement between feature naming conventions,
256 * aliases may be added.
257 */
258 const char *feat_names[32];
04d104b6
EH		 259 uint32_t cpuid_eax; /* Input EAX for CPUID */
260 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
261 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
262 int cpuid_reg; /* output register (R_* constant) */
37ce3522 263 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 264 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 265 uint32_t migratable_flags; /* Feature flags known to be migratable */
5ef57876
EH		 266} FeatureWordInfo;
267
268static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 269 [FEAT_1_EDX] = {
2d5312da
EH		 270 .feat_names = {
271 "fpu", "vme", "de", "pse",
272 "tsc", "msr", "pae", "mce",
273 "cx8", "apic", NULL, "sep",
274 "mtrr", "pge", "mca", "cmov",
275 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
276 NULL, "ds" /* Intel dts */, "acpi", "mmx",
277 "fxsr", "sse", "sse2", "ss",
278 "ht" /* Intel htt */, "tm", "ia64", "pbe",
279 },
bffd67b0 280 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 281 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 282 },
283 [FEAT_1_ECX] = {
2d5312da 284 .feat_names = {
16d2fcaa 285 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 286 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 287 "tm2", "ssse3", "cid", NULL,
288 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 289 NULL, "pcid", "dca", "sse4.1",
290 "sse4.2", "x2apic", "movbe", "popcnt",
2d5312da
EH		 291 "tsc-deadline", "aes", "xsave", "osxsave",
292 "avx", "f16c", "rdrand", "hypervisor",
293 },
bffd67b0 294 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 295 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 296 },
2d5312da
EH		 297 /* Feature names that are already defined on feature_name[] but
298 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
299 * names on feat_names below. They are copied automatically
300 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
301 */
bffd67b0 302 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 303 .feat_names = {
304 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
305 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
306 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
307 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
308 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 309 "nx", NULL, "mmxext", NULL /* mmx */,
310 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
311 NULL, "lm", "3dnowext", "3dnow",
2d5312da 312 },
bffd67b0 313 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 314 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 315 },
316 [FEAT_8000_0001_ECX] = {
2d5312da 317 .feat_names = {
fc7dfd20 318 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 319 "cr8legacy", "abm", "sse4a", "misalignsse",
320 "3dnowprefetch", "osvw", "ibs", "xop",
321 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 322 "fma4", "tce", NULL, "nodeid-msr",
323 NULL, "tbm", "topoext", "perfctr-core",
324 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 325 NULL, NULL, NULL, NULL,
326 },
bffd67b0 327 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 328 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 329 },
89e49c8b 330 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 331 .feat_names = {
332 NULL, NULL, "xstore", "xstore-en",
333 NULL, NULL, "xcrypt", "xcrypt-en",
334 "ace2", "ace2-en", "phe", "phe-en",
335 "pmm", "pmm-en", NULL, NULL,
336 NULL, NULL, NULL, NULL,
337 NULL, NULL, NULL, NULL,
338 NULL, NULL, NULL, NULL,
339 NULL, NULL, NULL, NULL,
340 },
89e49c8b 341 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 342 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 343 },
bffd67b0 344 [FEAT_KVM] = {
2d5312da 345 .feat_names = {
fc7dfd20
EH		 346 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
347 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
2d5312da
EH		 348 NULL, NULL, NULL, NULL,
349 NULL, NULL, NULL, NULL,
350 NULL, NULL, NULL, NULL,
351 NULL, NULL, NULL, NULL,
352 "kvmclock-stable-bit", NULL, NULL, NULL,
353 NULL, NULL, NULL, NULL,
354 },
bffd67b0 355 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 356 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 357 },
c35bd19a 358 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 359 .feat_names = {
360 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
361 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
362 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
363 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
364 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
365 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
366 NULL, NULL, NULL, NULL,
367 NULL, NULL, NULL, NULL,
368 NULL, NULL, NULL, NULL,
369 NULL, NULL, NULL, NULL,
370 NULL, NULL, NULL, NULL,
371 },
c35bd19a
EY		 372 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
373 },
374 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 375 .feat_names = {
376 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
377 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
378 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
379 NULL /* hv_create_port */, NULL /* hv_connect_port */,
380 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
381 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
382 NULL, NULL,
383 NULL, NULL, NULL, NULL,
384 NULL, NULL, NULL, NULL,
385 NULL, NULL, NULL, NULL,
386 NULL, NULL, NULL, NULL,
387 },
c35bd19a
EY		 388 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
389 },
390 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 391 .feat_names = {
392 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
393 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
394 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
395 NULL, NULL,
396 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
397 NULL, NULL, NULL, NULL,
398 NULL, NULL, NULL, NULL,
399 NULL, NULL, NULL, NULL,
400 NULL, NULL, NULL, NULL,
401 NULL, NULL, NULL, NULL,
402 },
c35bd19a
EY		 403 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
404 },
bffd67b0 405 [FEAT_SVM] = {
2d5312da 406 .feat_names = {
fc7dfd20
EH		 407 "npt", "lbrv", "svm-lock", "nrip-save",
408 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
409 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 410 "pfthreshold", NULL, NULL, NULL,
411 NULL, NULL, NULL, NULL,
412 NULL, NULL, NULL, NULL,
413 NULL, NULL, NULL, NULL,
414 NULL, NULL, NULL, NULL,
415 },
bffd67b0 416 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 417 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 418 },
419 [FEAT_7_0_EBX] = {
2d5312da 420 .feat_names = {
fc7dfd20 421 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 422 "hle", "avx2", NULL, "smep",
423 "bmi2", "erms", "invpcid", "rtm",
424 NULL, NULL, "mpx", NULL,
425 "avx512f", "avx512dq", "rdseed", "adx",
426 "smap", "avx512ifma", "pcommit", "clflushopt",
427 "clwb", NULL, "avx512pf", "avx512er",
638cbd45 428 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 429 },
04d104b6
EH		 430 .cpuid_eax = 7,
431 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
432 .cpuid_reg = R_EBX,
37ce3522 433 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 434 },
f74eefe0 435 [FEAT_7_0_ECX] = {
2d5312da
EH		 436 .feat_names = {
437 NULL, "avx512vbmi", "umip", "pku",
438 "ospke", NULL, NULL, NULL,
439 NULL, NULL, NULL, NULL,
f7754377 440 NULL, NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 441 "la57", NULL, NULL, NULL,
2d5312da
EH		 442 NULL, NULL, "rdpid", NULL,
443 NULL, NULL, NULL, NULL,
444 NULL, NULL, NULL, NULL,
445 },
f74eefe0
HH		 446 .cpuid_eax = 7,
447 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
448 .cpuid_reg = R_ECX,
449 .tcg_features = TCG_7_0_ECX_FEATURES,
450 },
95ea69fb
LK		 451 [FEAT_7_0_EDX] = {
452 .feat_names = {
453 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
454 NULL, NULL, NULL, NULL,
455 NULL, NULL, NULL, NULL,
456 NULL, NULL, NULL, NULL,
457 NULL, NULL, NULL, NULL,
458 NULL, NULL, NULL, NULL,
459 NULL, NULL, NULL, NULL,
460 NULL, NULL, NULL, NULL,
461 },
462 .cpuid_eax = 7,
463 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
464 .cpuid_reg = R_EDX,
465 .tcg_features = TCG_7_0_EDX_FEATURES,
466 },
303752a9 467 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 468 .feat_names = {
469 NULL, NULL, NULL, NULL,
470 NULL, NULL, NULL, NULL,
471 "invtsc", NULL, NULL, NULL,
472 NULL, NULL, NULL, NULL,
473 NULL, NULL, NULL, NULL,
474 NULL, NULL, NULL, NULL,
475 NULL, NULL, NULL, NULL,
476 NULL, NULL, NULL, NULL,
477 },
303752a9
MT		 478 .cpuid_eax = 0x80000007,
479 .cpuid_reg = R_EDX,
480 .tcg_features = TCG_APM_FEATURES,
481 .unmigratable_flags = CPUID_APM_INVTSC,
482 },
0bb0b2d2 483 [FEAT_XSAVE] = {
2d5312da
EH		 484 .feat_names = {
485 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
486 NULL, NULL, NULL, NULL,
487 NULL, NULL, NULL, NULL,
488 NULL, NULL, NULL, NULL,
489 NULL, NULL, NULL, NULL,
490 NULL, NULL, NULL, NULL,
491 NULL, NULL, NULL, NULL,
492 NULL, NULL, NULL, NULL,
493 },
0bb0b2d2
PB		 494 .cpuid_eax = 0xd,
495 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
496 .cpuid_reg = R_EAX,
c9cfe8f9 497 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 498 },
28b8e4d0 499 [FEAT_6_EAX] = {
2d5312da
EH		 500 .feat_names = {
501 NULL, NULL, "arat", NULL,
502 NULL, NULL, NULL, NULL,
503 NULL, NULL, NULL, NULL,
504 NULL, NULL, NULL, NULL,
505 NULL, NULL, NULL, NULL,
506 NULL, NULL, NULL, NULL,
507 NULL, NULL, NULL, NULL,
508 NULL, NULL, NULL, NULL,
509 },
28b8e4d0
JK		 510 .cpuid_eax = 6, .cpuid_reg = R_EAX,
511 .tcg_features = TCG_6_EAX_FEATURES,
512 },
96193c22
EH		 513 [FEAT_XSAVE_COMP_LO] = {
514 .cpuid_eax = 0xD,
515 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
516 .cpuid_reg = R_EAX,
517 .tcg_features = ~0U,
6fb2fff7
EH		 518 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
519 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
520 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
521 XSTATE_PKRU_MASK,
96193c22
EH		 522 },
523 [FEAT_XSAVE_COMP_HI] = {
524 .cpuid_eax = 0xD,
525 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
526 .cpuid_reg = R_EDX,
527 .tcg_features = ~0U,
528 },
5ef57876
EH		 529};
530
8e8aba50
EH		 531typedef struct X86RegisterInfo32 {
532 /* Name of register */
533 const char *name;
534 /* QAPI enum value register */
535 X86CPURegister32 qapi_enum;
536} X86RegisterInfo32;
537
538#define REGISTER(reg) \
5d371f41 539 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 540static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 541 REGISTER(EAX),
542 REGISTER(ECX),
543 REGISTER(EDX),
544 REGISTER(EBX),
545 REGISTER(ESP),
546 REGISTER(EBP),
547 REGISTER(ESI),
548 REGISTER(EDI),
549};
550#undef REGISTER
551
3f32bd21
RH		 552typedef struct ExtSaveArea {
553 uint32_t feature, bits;
554 uint32_t offset, size;
555} ExtSaveArea;
556
557static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 558 [XSTATE_FP_BIT] = {
559 /* x87 FP state component is always enabled if XSAVE is supported */
560 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
561 /* x87 state is in the legacy region of the XSAVE area */
562 .offset = 0,
563 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
564 },
565 [XSTATE_SSE_BIT] = {
566 /* SSE state component is always enabled if XSAVE is supported */
567 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
568 /* SSE state is in the legacy region of the XSAVE area */
569 .offset = 0,
570 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
571 },
cfc3b074
PB		 572 [XSTATE_YMM_BIT] =
573 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 574 .offset = offsetof(X86XSaveArea, avx_state),
575 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 576 [XSTATE_BNDREGS_BIT] =
577 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 578 .offset = offsetof(X86XSaveArea, bndreg_state),
579 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 580 [XSTATE_BNDCSR_BIT] =
581 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 582 .offset = offsetof(X86XSaveArea, bndcsr_state),
583 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 584 [XSTATE_OPMASK_BIT] =
585 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 586 .offset = offsetof(X86XSaveArea, opmask_state),
587 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 588 [XSTATE_ZMM_Hi256_BIT] =
589 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 590 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
591 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 592 [XSTATE_Hi16_ZMM_BIT] =
593 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 594 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
595 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 596 [XSTATE_PKRU_BIT] =
597 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 598 .offset = offsetof(X86XSaveArea, pkru_state),
599 .size = sizeof(XSavePKRU) },
2560f19f 600};
8e8aba50 601
1fda6198
EH		 602static uint32_t xsave_area_size(uint64_t mask)
603{
604 int i;
e3c9022b 605 uint64_t ret = 0;
1fda6198 606
e3c9022b 607 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 608 const ExtSaveArea *esa = &x86_ext_save_areas[i];
609 if ((mask >> i) & 1) {
610 ret = MAX(ret, esa->offset + esa->size);
611 }
612 }
613 return ret;
614}
615
96193c22
EH		 616static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
617{
618 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
619 cpu->env.features[FEAT_XSAVE_COMP_LO];
620}
621
8b4beddc
EH		 622const char *get_register_name_32(unsigned int reg)
623{
31ccdde2 624 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 625 return NULL;
626 }
8e8aba50 627 return x86_reg_info_32[reg].name;
8b4beddc
EH		 628}
629
84f1b92f
EH		 630/*
631 * Returns the set of feature flags that are supported and migratable by
632 * QEMU, for a given FeatureWord.
633 */
634static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
635{
636 FeatureWordInfo *wi = &feature_word_info[w];
637 uint32_t r = 0;
638 int i;
639
640 for (i = 0; i < 32; i++) {
641 uint32_t f = 1U << i;
6fb2fff7
EH		 642
643 /* If the feature name is known, it is implicitly considered migratable,
644 * unless it is explicitly set in unmigratable_flags */
645 if ((wi->migratable_flags & f) ||
646 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
647 r |= f;
84f1b92f 648 }
84f1b92f
EH		 649 }
650 return r;
651}
652
bb44e0d1
JK		 653void host_cpuid(uint32_t function, uint32_t count,
654 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 655{
a1fd24af
AL		 656 uint32_t vec[4];
657
658#ifdef __x86_64__
659 asm volatile("cpuid"
660 : "=a"(vec[0]), "=b"(vec[1]),
661 "=c"(vec[2]), "=d"(vec[3])
662 : "0"(function), "c"(count) : "cc");
c1f41226 663#elif defined(__i386__)
a1fd24af
AL		 664 asm volatile("pusha \n\t"
665 "cpuid \n\t"
666 "mov %%eax, 0(%2) \n\t"
667 "mov %%ebx, 4(%2) \n\t"
668 "mov %%ecx, 8(%2) \n\t"
669 "mov %%edx, 12(%2) \n\t"
670 "popa"
671 : : "a"(function), "c"(count), "S"(vec)
672 : "memory", "cc");
c1f41226
EH		 673#else
674 abort();
a1fd24af
AL		 675#endif
676
bdde476a 677 if (eax)
a1fd24af 678 *eax = vec[0];
bdde476a 679 if (ebx)
a1fd24af 680 *ebx = vec[1];
bdde476a 681 if (ecx)
a1fd24af 682 *ecx = vec[2];
bdde476a 683 if (edx)
a1fd24af 684 *edx = vec[3];
bdde476a 685}
c6dc6f63 686
20271d48
EH		 687void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
688{
689 uint32_t eax, ebx, ecx, edx;
690
691 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
692 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
693
694 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
695 if (family) {
696 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
697 }
698 if (model) {
699 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
700 }
701 if (stepping) {
702 *stepping = eax & 0x0F;
703 }
704}
705
d940ee9b
EH		 706/* CPU class name definitions: */
707
708#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
709#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
710
711/* Return type name for a given CPU model name
712 * Caller is responsible for freeing the returned string.
713 */
714static char *x86_cpu_type_name(const char *model_name)
715{
716 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
717}
718
500050d1
AF		 719static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
720{
d940ee9b
EH		 721 ObjectClass *oc;
722 char *typename;
723
500050d1
AF		 724 if (cpu_model == NULL) {
725 return NULL;
726 }
727
d940ee9b
EH		 728 typename = x86_cpu_type_name(cpu_model);
729 oc = object_class_by_name(typename);
730 g_free(typename);
731 return oc;
500050d1
AF		 732}
733
104494ea
IM		 734static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
735{
736 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
737 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
738 return g_strndup(class_name,
739 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
740}
741
d940ee9b 742struct X86CPUDefinition {
c6dc6f63
AP		 743 const char *name;
744 uint32_t level;
90e4b0c3 745 uint32_t xlevel;
99b88a17
IM		 746 /* vendor is zero-terminated, 12 character ASCII string */
747 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 748 int family;
749 int model;
750 int stepping;
0514ef2f 751 FeatureWordArray features;
c6dc6f63 752 char model_id[48];
d940ee9b 753};
c6dc6f63 754
9576de75 755static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 756 {
757 .name = "qemu64",
3046bb5d 758 .level = 0xd,
99b88a17 759 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 760 .family = 6,
f8e6a11a 761 .model = 6,
c6dc6f63 762 .stepping = 3,
0514ef2f 763 .features[FEAT_1_EDX] =
27861ecc 764 PPRO_FEATURES |
c6dc6f63 765 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 766 CPUID_PSE36,
0514ef2f 767 .features[FEAT_1_ECX] =
6aa91e4a 768 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 769 .features[FEAT_8000_0001_EDX] =
c6dc6f63 770 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 771 .features[FEAT_8000_0001_ECX] =
71195672 772 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 773 .xlevel = 0x8000000A,
9cf2cc3d 774 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 775 },
776 {
777 .name = "phenom",
778 .level = 5,
99b88a17 779 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 780 .family = 16,
781 .model = 2,
782 .stepping = 3,
b9fc20bc 783 /* Missing: CPUID_HT */
0514ef2f 784 .features[FEAT_1_EDX] =
27861ecc 785 PPRO_FEATURES |
c6dc6f63 786 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 787 CPUID_PSE36 | CPUID_VME,
0514ef2f 788 .features[FEAT_1_ECX] =
27861ecc 789 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 790 CPUID_EXT_POPCNT,
0514ef2f 791 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 792 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
793 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 794 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 795 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
796 CPUID_EXT3_CR8LEG,
797 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
798 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 799 .features[FEAT_8000_0001_ECX] =
27861ecc 800 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 801 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 802 /* Missing: CPUID_SVM_LBRV */
0514ef2f 803 .features[FEAT_SVM] =
b9fc20bc 804 CPUID_SVM_NPT,
c6dc6f63
AP		 805 .xlevel = 0x8000001A,
806 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
807 },
808 {
809 .name = "core2duo",
810 .level = 10,
99b88a17 811 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 812 .family = 6,
813 .model = 15,
814 .stepping = 11,
b9fc20bc 815 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 816 .features[FEAT_1_EDX] =
27861ecc 817 PPRO_FEATURES |
c6dc6f63 818 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 819 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
820 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 821 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 822 .features[FEAT_1_ECX] =
27861ecc 823 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 824 CPUID_EXT_CX16,
0514ef2f 825 .features[FEAT_8000_0001_EDX] =
27861ecc 826 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 827 .features[FEAT_8000_0001_ECX] =
27861ecc 828 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 829 .xlevel = 0x80000008,
830 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
831 },
832 {
833 .name = "kvm64",
3046bb5d 834 .level = 0xd,
99b88a17 835 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 836 .family = 15,
837 .model = 6,
838 .stepping = 1,
b3a4f0b1 839 /* Missing: CPUID_HT */
0514ef2f 840 .features[FEAT_1_EDX] =
b3a4f0b1 841 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 842 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
843 CPUID_PSE36,
844 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 845 .features[FEAT_1_ECX] =
27861ecc 846 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 847 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 848 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 849 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
850 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
851 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
852 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
853 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 854 .features[FEAT_8000_0001_ECX] =
27861ecc 855 0,
c6dc6f63
AP		 856 .xlevel = 0x80000008,
857 .model_id = "Common KVM processor"
858 },
c6dc6f63
AP		 859 {
860 .name = "qemu32",
861 .level = 4,
99b88a17 862 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 863 .family = 6,
f8e6a11a 864 .model = 6,
c6dc6f63 865 .stepping = 3,
0514ef2f 866 .features[FEAT_1_EDX] =
27861ecc 867 PPRO_FEATURES,
0514ef2f 868 .features[FEAT_1_ECX] =
6aa91e4a 869 CPUID_EXT_SSE3,
58012d66 870 .xlevel = 0x80000004,
9cf2cc3d 871 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 872 },
eafaf1e5
AP		 873 {
874 .name = "kvm32",
875 .level = 5,
99b88a17 876 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 877 .family = 15,
878 .model = 6,
879 .stepping = 1,
0514ef2f 880 .features[FEAT_1_EDX] =
b3a4f0b1 881 PPRO_FEATURES | CPUID_VME |
eafaf1e5 882 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 883 .features[FEAT_1_ECX] =
27861ecc 884 CPUID_EXT_SSE3,
0514ef2f 885 .features[FEAT_8000_0001_ECX] =
27861ecc 886 0,
eafaf1e5
AP		 887 .xlevel = 0x80000008,
888 .model_id = "Common 32-bit KVM processor"
889 },
c6dc6f63
AP		 890 {
891 .name = "coreduo",
892 .level = 10,
99b88a17 893 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 894 .family = 6,
895 .model = 14,
896 .stepping = 8,
b9fc20bc 897 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 898 .features[FEAT_1_EDX] =
27861ecc 899 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 900 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
901 CPUID_SS,
902 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 903 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 904 .features[FEAT_1_ECX] =
e93abc14 905 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 906 .features[FEAT_8000_0001_EDX] =
27861ecc 907 CPUID_EXT2_NX,
c6dc6f63
AP		 908 .xlevel = 0x80000008,
909 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
910 },
911 {
912 .name = "486",
58012d66 913 .level = 1,
99b88a17 914 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 915 .family = 4,
b2a856d9 916 .model = 8,
c6dc6f63 917 .stepping = 0,
0514ef2f 918 .features[FEAT_1_EDX] =
27861ecc 919 I486_FEATURES,
c6dc6f63
AP		 920 .xlevel = 0,
921 },
922 {
923 .name = "pentium",
924 .level = 1,
99b88a17 925 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 926 .family = 5,
927 .model = 4,
928 .stepping = 3,
0514ef2f 929 .features[FEAT_1_EDX] =
27861ecc 930 PENTIUM_FEATURES,
c6dc6f63
AP		 931 .xlevel = 0,
932 },
933 {
934 .name = "pentium2",
935 .level = 2,
99b88a17 936 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 937 .family = 6,
938 .model = 5,
939 .stepping = 2,
0514ef2f 940 .features[FEAT_1_EDX] =
27861ecc 941 PENTIUM2_FEATURES,
c6dc6f63
AP		 942 .xlevel = 0,
943 },
944 {
945 .name = "pentium3",
3046bb5d 946 .level = 3,
99b88a17 947 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 948 .family = 6,
949 .model = 7,
950 .stepping = 3,
0514ef2f 951 .features[FEAT_1_EDX] =
27861ecc 952 PENTIUM3_FEATURES,
c6dc6f63
AP		 953 .xlevel = 0,
954 },
955 {
956 .name = "athlon",
957 .level = 2,
99b88a17 958 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 959 .family = 6,
960 .model = 2,
961 .stepping = 3,
0514ef2f 962 .features[FEAT_1_EDX] =
27861ecc 963 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 964 CPUID_MCA,
0514ef2f 965 .features[FEAT_8000_0001_EDX] =
60032ac0 966 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 967 .xlevel = 0x80000008,
9cf2cc3d 968 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 969 },
970 {
971 .name = "n270",
3046bb5d 972 .level = 10,
99b88a17 973 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 974 .family = 6,
975 .model = 28,
976 .stepping = 2,
b9fc20bc 977 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 978 .features[FEAT_1_EDX] =
27861ecc 979 PPRO_FEATURES |
b9fc20bc
EH		 980 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
981 CPUID_ACPI | CPUID_SS,
c6dc6f63 982 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 983 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
984 * CPUID_EXT_XTPR */
0514ef2f 985 .features[FEAT_1_ECX] =
27861ecc 986 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 987 CPUID_EXT_MOVBE,
0514ef2f 988 .features[FEAT_8000_0001_EDX] =
60032ac0 989 CPUID_EXT2_NX,
0514ef2f 990 .features[FEAT_8000_0001_ECX] =
27861ecc 991 CPUID_EXT3_LAHF_LM,
3046bb5d 992 .xlevel = 0x80000008,
c6dc6f63
AP		 993 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
994 },
3eca4642
EH		 995 {
996 .name = "Conroe",
3046bb5d 997 .level = 10,
99b88a17 998 .vendor = CPUID_VENDOR_INTEL,
3eca4642 999 .family = 6,
ffce9ebb 1000 .model = 15,
3eca4642 1001 .stepping = 3,
0514ef2f 1002 .features[FEAT_1_EDX] =
b3a4f0b1 1003 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1004 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1005 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1006 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1007 CPUID_DE | CPUID_FP87,
0514ef2f 1008 .features[FEAT_1_ECX] =
27861ecc 1009 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1010 .features[FEAT_8000_0001_EDX] =
27861ecc 1011 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1012 .features[FEAT_8000_0001_ECX] =
27861ecc 1013 CPUID_EXT3_LAHF_LM,
3046bb5d 1014 .xlevel = 0x80000008,
3eca4642
EH		 1015 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1016 },
1017 {
1018 .name = "Penryn",
3046bb5d 1019 .level = 10,
99b88a17 1020 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1021 .family = 6,
ffce9ebb 1022 .model = 23,
3eca4642 1023 .stepping = 3,
0514ef2f 1024 .features[FEAT_1_EDX] =
b3a4f0b1 1025 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1026 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1027 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1028 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1029 CPUID_DE | CPUID_FP87,
0514ef2f 1030 .features[FEAT_1_ECX] =
27861ecc 1031 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1032 CPUID_EXT_SSE3,
0514ef2f 1033 .features[FEAT_8000_0001_EDX] =
27861ecc 1034 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1035 .features[FEAT_8000_0001_ECX] =
27861ecc 1036 CPUID_EXT3_LAHF_LM,
3046bb5d 1037 .xlevel = 0x80000008,
3eca4642
EH		 1038 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1039 },
1040 {
1041 .name = "Nehalem",
3046bb5d 1042 .level = 11,
99b88a17 1043 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1044 .family = 6,
ffce9ebb 1045 .model = 26,
3eca4642 1046 .stepping = 3,
0514ef2f 1047 .features[FEAT_1_EDX] =
b3a4f0b1 1048 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1049 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1050 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1051 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1052 CPUID_DE | CPUID_FP87,
0514ef2f 1053 .features[FEAT_1_ECX] =
27861ecc 1054 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1055 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1056 .features[FEAT_8000_0001_EDX] =
27861ecc 1057 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1058 .features[FEAT_8000_0001_ECX] =
27861ecc 1059 CPUID_EXT3_LAHF_LM,
3046bb5d 1060 .xlevel = 0x80000008,
3eca4642
EH		 1061 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1062 },
1063 {
1064 .name = "Westmere",
1065 .level = 11,
99b88a17 1066 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1067 .family = 6,
1068 .model = 44,
1069 .stepping = 1,
0514ef2f 1070 .features[FEAT_1_EDX] =
b3a4f0b1 1071 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1072 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1073 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1074 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1075 CPUID_DE | CPUID_FP87,
0514ef2f 1076 .features[FEAT_1_ECX] =
27861ecc 1077 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1078 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1079 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1080 .features[FEAT_8000_0001_EDX] =
27861ecc 1081 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1082 .features[FEAT_8000_0001_ECX] =
27861ecc 1083 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1084 .features[FEAT_6_EAX] =
1085 CPUID_6_EAX_ARAT,
3046bb5d 1086 .xlevel = 0x80000008,
3eca4642
EH		 1087 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1088 },
1089 {
1090 .name = "SandyBridge",
1091 .level = 0xd,
99b88a17 1092 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1093 .family = 6,
1094 .model = 42,
1095 .stepping = 1,
0514ef2f 1096 .features[FEAT_1_EDX] =
b3a4f0b1 1097 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1098 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1099 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1100 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1101 CPUID_DE | CPUID_FP87,
0514ef2f 1102 .features[FEAT_1_ECX] =
27861ecc 1103 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1104 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1105 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1106 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1107 CPUID_EXT_SSE3,
0514ef2f 1108 .features[FEAT_8000_0001_EDX] =
27861ecc 1109 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1110 CPUID_EXT2_SYSCALL,
0514ef2f 1111 .features[FEAT_8000_0001_ECX] =
27861ecc 1112 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1113 .features[FEAT_XSAVE] =
1114 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1115 .features[FEAT_6_EAX] =
1116 CPUID_6_EAX_ARAT,
3046bb5d 1117 .xlevel = 0x80000008,
3eca4642
EH		 1118 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1119 },
2f9ac42a
PB		 1120 {
1121 .name = "IvyBridge",
1122 .level = 0xd,
1123 .vendor = CPUID_VENDOR_INTEL,
1124 .family = 6,
1125 .model = 58,
1126 .stepping = 9,
1127 .features[FEAT_1_EDX] =
1128 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1129 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1130 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1131 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1132 CPUID_DE | CPUID_FP87,
1133 .features[FEAT_1_ECX] =
1134 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1135 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1136 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1137 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1138 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1139 .features[FEAT_7_0_EBX] =
1140 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1141 CPUID_7_0_EBX_ERMS,
1142 .features[FEAT_8000_0001_EDX] =
1143 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1144 CPUID_EXT2_SYSCALL,
1145 .features[FEAT_8000_0001_ECX] =
1146 CPUID_EXT3_LAHF_LM,
1147 .features[FEAT_XSAVE] =
1148 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1149 .features[FEAT_6_EAX] =
1150 CPUID_6_EAX_ARAT,
3046bb5d 1151 .xlevel = 0x80000008,
2f9ac42a
PB		 1152 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1153 },
37507094 1154 {
a356850b
EH		 1155 .name = "Haswell-noTSX",
1156 .level = 0xd,
1157 .vendor = CPUID_VENDOR_INTEL,
1158 .family = 6,
1159 .model = 60,
1160 .stepping = 1,
1161 .features[FEAT_1_EDX] =
1162 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1163 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1164 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1165 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1166 CPUID_DE | CPUID_FP87,
1167 .features[FEAT_1_ECX] =
1168 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1169 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1170 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1171 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1172 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1173 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1174 .features[FEAT_8000_0001_EDX] =
1175 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1176 CPUID_EXT2_SYSCALL,
1177 .features[FEAT_8000_0001_ECX] =
becb6667 1178 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1179 .features[FEAT_7_0_EBX] =
1180 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1181 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1182 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1183 .features[FEAT_XSAVE] =
1184 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1185 .features[FEAT_6_EAX] =
1186 CPUID_6_EAX_ARAT,
3046bb5d 1187 .xlevel = 0x80000008,
a356850b
EH		 1188 .model_id = "Intel Core Processor (Haswell, no TSX)",
1189 }, {
37507094
EH		 1190 .name = "Haswell",
1191 .level = 0xd,
99b88a17 1192 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1193 .family = 6,
1194 .model = 60,
ec56a4a7 1195 .stepping = 4,
0514ef2f 1196 .features[FEAT_1_EDX] =
b3a4f0b1 1197 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1198 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1199 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1200 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1201 CPUID_DE | CPUID_FP87,
0514ef2f 1202 .features[FEAT_1_ECX] =
27861ecc 1203 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1204 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1205 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1206 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1207 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1208 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1209 .features[FEAT_8000_0001_EDX] =
27861ecc 1210 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1211 CPUID_EXT2_SYSCALL,
0514ef2f 1212 .features[FEAT_8000_0001_ECX] =
becb6667 1213 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1214 .features[FEAT_7_0_EBX] =
27861ecc 1215 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1216 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1217 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1218 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1219 .features[FEAT_XSAVE] =
1220 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1221 .features[FEAT_6_EAX] =
1222 CPUID_6_EAX_ARAT,
3046bb5d 1223 .xlevel = 0x80000008,
37507094
EH		 1224 .model_id = "Intel Core Processor (Haswell)",
1225 },
a356850b
EH		 1226 {
1227 .name = "Broadwell-noTSX",
1228 .level = 0xd,
1229 .vendor = CPUID_VENDOR_INTEL,
1230 .family = 6,
1231 .model = 61,
1232 .stepping = 2,
1233 .features[FEAT_1_EDX] =
1234 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1235 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1236 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1237 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1238 CPUID_DE | CPUID_FP87,
1239 .features[FEAT_1_ECX] =
1240 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1241 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1242 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1243 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1244 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1245 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1246 .features[FEAT_8000_0001_EDX] =
1247 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1248 CPUID_EXT2_SYSCALL,
1249 .features[FEAT_8000_0001_ECX] =
becb6667 1250 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1251 .features[FEAT_7_0_EBX] =
1252 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1253 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1254 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1255 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1256 CPUID_7_0_EBX_SMAP,
1257 .features[FEAT_XSAVE] =
1258 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1259 .features[FEAT_6_EAX] =
1260 CPUID_6_EAX_ARAT,
3046bb5d 1261 .xlevel = 0x80000008,
a356850b
EH		 1262 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1263 },
ece01354
EH		 1264 {
1265 .name = "Broadwell",
1266 .level = 0xd,
1267 .vendor = CPUID_VENDOR_INTEL,
1268 .family = 6,
1269 .model = 61,
1270 .stepping = 2,
1271 .features[FEAT_1_EDX] =
b3a4f0b1 1272 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1273 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1274 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1275 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1276 CPUID_DE | CPUID_FP87,
1277 .features[FEAT_1_ECX] =
1278 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1279 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1280 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1281 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1282 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1283 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1284 .features[FEAT_8000_0001_EDX] =
1285 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1286 CPUID_EXT2_SYSCALL,
1287 .features[FEAT_8000_0001_ECX] =
becb6667 1288 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1289 .features[FEAT_7_0_EBX] =
1290 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1291 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1292 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1293 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1294 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1295 .features[FEAT_XSAVE] =
1296 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1297 .features[FEAT_6_EAX] =
1298 CPUID_6_EAX_ARAT,
3046bb5d 1299 .xlevel = 0x80000008,
ece01354
EH		 1300 .model_id = "Intel Core Processor (Broadwell)",
1301 },
f6f949e9
EH		 1302 {
1303 .name = "Skylake-Client",
1304 .level = 0xd,
1305 .vendor = CPUID_VENDOR_INTEL,
1306 .family = 6,
1307 .model = 94,
1308 .stepping = 3,
1309 .features[FEAT_1_EDX] =
1310 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1311 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1312 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1313 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1314 CPUID_DE | CPUID_FP87,
1315 .features[FEAT_1_ECX] =
1316 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1317 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1318 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1319 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1320 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1321 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1322 .features[FEAT_8000_0001_EDX] =
1323 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1324 CPUID_EXT2_SYSCALL,
1325 .features[FEAT_8000_0001_ECX] =
1326 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1327 .features[FEAT_7_0_EBX] =
1328 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1329 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1330 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1331 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1332 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1333 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 1334 * including v4.1 to v4.12).
f6f949e9
EH		 1335 * KVM doesn't yet expose any XSAVES state save component,
1336 * and the only one defined in Skylake (processor tracing)
1337 * probably will block migration anyway.
1338 */
1339 .features[FEAT_XSAVE] =
1340 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1341 CPUID_XSAVE_XGETBV1,
1342 .features[FEAT_6_EAX] =
1343 CPUID_6_EAX_ARAT,
1344 .xlevel = 0x80000008,
1345 .model_id = "Intel Core Processor (Skylake)",
1346 },
53f9a6f4
BF		 1347 {
1348 .name = "Skylake-Server",
1349 .level = 0xd,
1350 .vendor = CPUID_VENDOR_INTEL,
1351 .family = 6,
1352 .model = 85,
1353 .stepping = 4,
1354 .features[FEAT_1_EDX] =
1355 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1356 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1357 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1358 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1359 CPUID_DE | CPUID_FP87,
1360 .features[FEAT_1_ECX] =
1361 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1362 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1363 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1364 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1365 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1366 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1367 .features[FEAT_8000_0001_EDX] =
1368 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
1369 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1370 .features[FEAT_8000_0001_ECX] =
1371 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1372 .features[FEAT_7_0_EBX] =
1373 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1374 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1375 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1376 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1377 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
1378 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
1379 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
1380 CPUID_7_0_EBX_AVX512VL,
1381 /* Missing: XSAVES (not supported by some Linux versions,
1382 * including v4.1 to v4.12).
1383 * KVM doesn't yet expose any XSAVES state save component,
1384 * and the only one defined in Skylake (processor tracing)
1385 * probably will block migration anyway.
1386 */
1387 .features[FEAT_XSAVE] =
1388 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1389 CPUID_XSAVE_XGETBV1,
1390 .features[FEAT_6_EAX] =
1391 CPUID_6_EAX_ARAT,
1392 .xlevel = 0x80000008,
1393 .model_id = "Intel Xeon Processor (Skylake)",
1394 },
3eca4642
EH		 1395 {
1396 .name = "Opteron_G1",
1397 .level = 5,
99b88a17 1398 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1399 .family = 15,
1400 .model = 6,
1401 .stepping = 1,
0514ef2f 1402 .features[FEAT_1_EDX] =
b3a4f0b1 1403 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1404 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1405 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1406 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1407 CPUID_DE | CPUID_FP87,
0514ef2f 1408 .features[FEAT_1_ECX] =
27861ecc 1409 CPUID_EXT_SSE3,
0514ef2f 1410 .features[FEAT_8000_0001_EDX] =
2a923a29 1411 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 1412 .xlevel = 0x80000008,
1413 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1414 },
1415 {
1416 .name = "Opteron_G2",
1417 .level = 5,
99b88a17 1418 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1419 .family = 15,
1420 .model = 6,
1421 .stepping = 1,
0514ef2f 1422 .features[FEAT_1_EDX] =
b3a4f0b1 1423 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1424 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1425 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1426 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1427 CPUID_DE | CPUID_FP87,
0514ef2f 1428 .features[FEAT_1_ECX] =
27861ecc 1429 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1430 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1431 .features[FEAT_8000_0001_EDX] =
2a923a29 1432 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1433 .features[FEAT_8000_0001_ECX] =
27861ecc 1434 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1435 .xlevel = 0x80000008,
1436 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1437 },
1438 {
1439 .name = "Opteron_G3",
1440 .level = 5,
99b88a17 1441 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 1442 .family = 16,
1443 .model = 2,
1444 .stepping = 3,
0514ef2f 1445 .features[FEAT_1_EDX] =
b3a4f0b1 1446 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1447 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1448 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1449 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1450 CPUID_DE | CPUID_FP87,
0514ef2f 1451 .features[FEAT_1_ECX] =
27861ecc 1452 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1453 CPUID_EXT_SSE3,
33b5e8c0 1454 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1455 .features[FEAT_8000_0001_EDX] =
2a923a29 1456 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1457 .features[FEAT_8000_0001_ECX] =
27861ecc 1458 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1459 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1460 .xlevel = 0x80000008,
1461 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1462 },
1463 {
1464 .name = "Opteron_G4",
1465 .level = 0xd,
99b88a17 1466 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1467 .family = 21,
1468 .model = 1,
1469 .stepping = 2,
0514ef2f 1470 .features[FEAT_1_EDX] =
b3a4f0b1 1471 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1472 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1473 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1474 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1475 CPUID_DE | CPUID_FP87,
0514ef2f 1476 .features[FEAT_1_ECX] =
27861ecc 1477 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1478 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1479 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1480 CPUID_EXT_SSE3,
33b5e8c0 1481 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1482 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1483 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1484 CPUID_EXT2_SYSCALL,
0514ef2f 1485 .features[FEAT_8000_0001_ECX] =
27861ecc 1486 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1487 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1488 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1489 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1490 /* no xsaveopt! */
3eca4642
EH		 1491 .xlevel = 0x8000001A,
1492 .model_id = "AMD Opteron 62xx class CPU",
1493 },
021941b9
AP		 1494 {
1495 .name = "Opteron_G5",
1496 .level = 0xd,
99b88a17 1497 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1498 .family = 21,
1499 .model = 2,
1500 .stepping = 0,
0514ef2f 1501 .features[FEAT_1_EDX] =
b3a4f0b1 1502 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1503 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1504 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1505 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1506 CPUID_DE | CPUID_FP87,
0514ef2f 1507 .features[FEAT_1_ECX] =
27861ecc 1508 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1509 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1510 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1511 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1512 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1513 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1514 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1515 CPUID_EXT2_SYSCALL,
0514ef2f 1516 .features[FEAT_8000_0001_ECX] =
27861ecc 1517 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1518 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1519 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1520 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1521 /* no xsaveopt! */
021941b9
AP		 1522 .xlevel = 0x8000001A,
1523 .model_id = "AMD Opteron 63xx class CPU",
1524 },
c6dc6f63
AP		 1525};
1526
5114e842
EH		 1527typedef struct PropValue {
1528 const char *prop, *value;
1529} PropValue;
1530
1531/* KVM-specific features that are automatically added/removed
1532 * from all CPU models when KVM is enabled.
1533 */
1534static PropValue kvm_default_props[] = {
1535 { "kvmclock", "on" },
1536 { "kvm-nopiodelay", "on" },
1537 { "kvm-asyncpf", "on" },
1538 { "kvm-steal-time", "on" },
1539 { "kvm-pv-eoi", "on" },
1540 { "kvmclock-stable-bit", "on" },
1541 { "x2apic", "on" },
1542 { "acpi", "off" },
1543 { "monitor", "off" },
1544 { "svm", "off" },
1545 { NULL, NULL },
1546};
1547
04d99c3c
EH		 1548/* TCG-specific defaults that override all CPU models when using TCG
1549 */
1550static PropValue tcg_default_props[] = {
1551 { "vme", "off" },
1552 { NULL, NULL },
1553};
1554
1555
5114e842
EH		 1556void x86_cpu_change_kvm_default(const char *prop, const char *value)
1557{
1558 PropValue *pv;
1559 for (pv = kvm_default_props; pv->prop; pv++) {
1560 if (!strcmp(pv->prop, prop)) {
1561 pv->value = value;
1562 break;
1563 }
1564 }
1565
1566 /* It is valid to call this function only for properties that
1567 * are already present in the kvm_default_props table.
1568 */
1569 assert(pv->prop);
1570}
1571
4d1b279b
EH		 1572static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1573 bool migratable_only);
1574
40bfe48f
HZ		 1575static bool lmce_supported(void)
1576{
c62f2630 1577 uint64_t mce_cap = 0;
40bfe48f 1578
c62f2630 1579#ifdef CONFIG_KVM
40bfe48f
HZ		 1580 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1581 return false;
1582 }
c62f2630 1583#endif
40bfe48f
HZ		 1584
1585 return !!(mce_cap & MCG_LMCE_P);
1586}
1587
7d8050b5
EH		 1588#define CPUID_MODEL_ID_SZ 48
1589
1590/**
1591 * cpu_x86_fill_model_id:
1592 * Get CPUID model ID string from host CPU.
1593 *
1594 * @str should have at least CPUID_MODEL_ID_SZ bytes
1595 *
1596 * The function does NOT add a null terminator to the string
1597 * automatically.
1598 */
c6dc6f63
AP		 1599static int cpu_x86_fill_model_id(char *str)
1600{
1601 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1602 int i;
1603
1604 for (i = 0; i < 3; i++) {
1605 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1606 memcpy(str + i * 16 + 0, &eax, 4);
1607 memcpy(str + i * 16 + 4, &ebx, 4);
1608 memcpy(str + i * 16 + 8, &ecx, 4);
1609 memcpy(str + i * 16 + 12, &edx, 4);
1610 }
1611 return 0;
1612}
1613
c62f2630 1614static Property max_x86_cpu_properties[] = {
120eee7d 1615 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1616 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1617 DEFINE_PROP_END_OF_LIST()
1618};
1619
c62f2630 1620static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1621{
84f1b92f 1622 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1623 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 1624
f48c8837 1625 xcc->ordering = 9;
6e746f30 1626
ee465a3e 1627 xcc->model_description =
c62f2630 1628 "Enables all features supported by the accelerator in the current host";
d940ee9b 1629
c62f2630 1630 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 1631}
1632
0bacd8b3
EH		 1633static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
1634
c62f2630 1635static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 1636{
1637 X86CPU *cpu = X86_CPU(obj);
1638 CPUX86State *env = &cpu->env;
1639 KVMState *s = kvm_state;
d940ee9b 1640
4d1b279b
EH		 1641 /* We can't fill the features array here because we don't know yet if
1642 * "migratable" is true or false.
1643 */
44bd8e53 1644 cpu->max_features = true;
4d1b279b 1645
e4356010 1646 if (kvm_enabled()) {
bd182022
EH		 1647 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
1648 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
1649 int family, model, stepping;
0bacd8b3 1650
bd182022 1651 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 1652
bd182022 1653 cpu_x86_fill_model_id(model_id);
0bacd8b3 1654
bd182022
EH		 1655 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
1656 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
1657 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
1658 object_property_set_int(OBJECT(cpu), stepping, "stepping",
1659 &error_abort);
1660 object_property_set_str(OBJECT(cpu), model_id, "model-id",
1661 &error_abort);
0bacd8b3 1662
c39c0edf
EH		 1663 env->cpuid_min_level =
1664 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1665 env->cpuid_min_xlevel =
1666 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1667 env->cpuid_min_xlevel2 =
1668 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
40bfe48f
HZ		 1669
1670 if (lmce_supported()) {
1671 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1672 }
6900d1cc
EH		 1673 } else {
1674 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
1675 "vendor", &error_abort);
1676 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
1677 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
1678 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
1679 object_property_set_str(OBJECT(cpu),
1680 "QEMU TCG CPU version " QEMU_HW_VERSION,
1681 "model-id", &error_abort);
e4356010 1682 }
2a573259 1683
d940ee9b 1684 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1685}
1686
c62f2630
EH		 1687static const TypeInfo max_x86_cpu_type_info = {
1688 .name = X86_CPU_TYPE_NAME("max"),
1689 .parent = TYPE_X86_CPU,
1690 .instance_init = max_x86_cpu_initfn,
1691 .class_init = max_x86_cpu_class_init,
1692};
1693
1694#ifdef CONFIG_KVM
1695
1696static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1697{
1698 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1699
1700 xcc->kvm_required = true;
1701 xcc->ordering = 8;
1702
1703 xcc->model_description =
1704 "KVM processor with all supported host features "
1705 "(only available in KVM mode)";
1706}
1707
d940ee9b
EH		 1708static const TypeInfo host_x86_cpu_type_info = {
1709 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 1710 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 1711 .class_init = host_x86_cpu_class_init,
1712};
1713
1714#endif
1715
8459e396 1716static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1717{
8459e396 1718 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1719 int i;
1720
857aee33 1721 for (i = 0; i < 32; ++i) {
72370dc1 1722 if ((1UL << i) & mask) {
bffd67b0 1723 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1724 assert(reg);
fefb41bf 1725 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1726 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1727 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1728 f->cpuid_eax, reg,
1729 f->feat_names[i] ? "." : "",
1730 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1731 }
857aee33 1732 }
c6dc6f63
AP		 1733}
1734
d7bce999
EB		 1735static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1736 const char *name, void *opaque,
1737 Error **errp)
95b8519d
AF		 1738{
1739 X86CPU *cpu = X86_CPU(obj);
1740 CPUX86State *env = &cpu->env;
1741 int64_t value;
1742
1743 value = (env->cpuid_version >> 8) & 0xf;
1744 if (value == 0xf) {
1745 value += (env->cpuid_version >> 20) & 0xff;
1746 }
51e72bc1 1747 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1748}
1749
d7bce999
EB		 1750static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1751 const char *name, void *opaque,
1752 Error **errp)
ed5e1ec3 1753{
71ad61d3
AF		 1754 X86CPU *cpu = X86_CPU(obj);
1755 CPUX86State *env = &cpu->env;
1756 const int64_t min = 0;
1757 const int64_t max = 0xff + 0xf;
65cd9064 1758 Error *local_err = NULL;
71ad61d3
AF		 1759 int64_t value;
1760
51e72bc1 1761 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1762 if (local_err) {
1763 error_propagate(errp, local_err);
71ad61d3
AF		 1764 return;
1765 }
1766 if (value < min || value > max) {
c6bd8c70
MA		 1767 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1768 name ? name : "null", value, min, max);
71ad61d3
AF		 1769 return;
1770 }
1771
ed5e1ec3 1772 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1773 if (value > 0x0f) {
1774 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1775 } else {
71ad61d3 1776 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1777 }
1778}
1779
d7bce999
EB		 1780static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1781 const char *name, void *opaque,
1782 Error **errp)
67e30c83
AF		 1783{
1784 X86CPU *cpu = X86_CPU(obj);
1785 CPUX86State *env = &cpu->env;
1786 int64_t value;
1787
1788 value = (env->cpuid_version >> 4) & 0xf;
1789 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1790 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1791}
1792
d7bce999
EB		 1793static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1794 const char *name, void *opaque,
1795 Error **errp)
b0704cbd 1796{
c5291a4f
AF		 1797 X86CPU *cpu = X86_CPU(obj);
1798 CPUX86State *env = &cpu->env;
1799 const int64_t min = 0;
1800 const int64_t max = 0xff;
65cd9064 1801 Error *local_err = NULL;
c5291a4f
AF		 1802 int64_t value;
1803
51e72bc1 1804 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1805 if (local_err) {
1806 error_propagate(errp, local_err);
c5291a4f
AF		 1807 return;
1808 }
1809 if (value < min || value > max) {
c6bd8c70
MA		 1810 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1811 name ? name : "null", value, min, max);
c5291a4f
AF		 1812 return;
1813 }
1814
b0704cbd 1815 env->cpuid_version &= ~0xf00f0;
c5291a4f 1816 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1817}
1818
35112e41 1819static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1820 const char *name, void *opaque,
35112e41
AF		 1821 Error **errp)
1822{
1823 X86CPU *cpu = X86_CPU(obj);
1824 CPUX86State *env = &cpu->env;
1825 int64_t value;
1826
1827 value = env->cpuid_version & 0xf;
51e72bc1 1828 visit_type_int(v, name, &value, errp);
35112e41
AF		 1829}
1830
036e2222 1831static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1832 const char *name, void *opaque,
036e2222 1833 Error **errp)
38c3dc46 1834{
036e2222
AF		 1835 X86CPU *cpu = X86_CPU(obj);
1836 CPUX86State *env = &cpu->env;
1837 const int64_t min = 0;
1838 const int64_t max = 0xf;
65cd9064 1839 Error *local_err = NULL;
036e2222
AF		 1840 int64_t value;
1841
51e72bc1 1842 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1843 if (local_err) {
1844 error_propagate(errp, local_err);
036e2222
AF		 1845 return;
1846 }
1847 if (value < min || value > max) {
c6bd8c70
MA		 1848 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1849 name ? name : "null", value, min, max);
036e2222
AF		 1850 return;
1851 }
1852
38c3dc46 1853 env->cpuid_version &= ~0xf;
036e2222 1854 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1855}
1856
d480e1af
AF		 1857static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1858{
1859 X86CPU *cpu = X86_CPU(obj);
1860 CPUX86State *env = &cpu->env;
1861 char *value;
d480e1af 1862
e42a92ae 1863 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1864 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1865 env->cpuid_vendor3);
d480e1af
AF		 1866 return value;
1867}
1868
1869static void x86_cpuid_set_vendor(Object *obj, const char *value,
1870 Error **errp)
1871{
1872 X86CPU *cpu = X86_CPU(obj);
1873 CPUX86State *env = &cpu->env;
1874 int i;
1875
9df694ee 1876 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1877 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1878 return;
1879 }
1880
1881 env->cpuid_vendor1 = 0;
1882 env->cpuid_vendor2 = 0;
1883 env->cpuid_vendor3 = 0;
1884 for (i = 0; i < 4; i++) {
1885 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1886 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1887 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1888 }
d480e1af
AF		 1889}
1890
63e886eb
AF		 1891static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1892{
1893 X86CPU *cpu = X86_CPU(obj);
1894 CPUX86State *env = &cpu->env;
1895 char *value;
1896 int i;
1897
1898 value = g_malloc(48 + 1);
1899 for (i = 0; i < 48; i++) {
1900 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1901 }
1902 value[48] = '\0';
1903 return value;
1904}
1905
938d4c25
AF		 1906static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1907 Error **errp)
dcce6675 1908{
938d4c25
AF		 1909 X86CPU *cpu = X86_CPU(obj);
1910 CPUX86State *env = &cpu->env;
dcce6675
AF		 1911 int c, len, i;
1912
1913 if (model_id == NULL) {
1914 model_id = "";
1915 }
1916 len = strlen(model_id);
d0a6acf4 1917 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1918 for (i = 0; i < 48; i++) {
1919 if (i >= len) {
1920 c = '\0';
1921 } else {
1922 c = (uint8_t)model_id[i];
1923 }
1924 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1925 }
1926}
1927
d7bce999
EB		 1928static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1929 void *opaque, Error **errp)
89e48965
AF		 1930{
1931 X86CPU *cpu = X86_CPU(obj);
1932 int64_t value;
1933
1934 value = cpu->env.tsc_khz * 1000;
51e72bc1 1935 visit_type_int(v, name, &value, errp);
89e48965
AF		 1936}
1937
d7bce999
EB		 1938static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1939 void *opaque, Error **errp)
89e48965
AF		 1940{
1941 X86CPU *cpu = X86_CPU(obj);
1942 const int64_t min = 0;
2e84849a 1943 const int64_t max = INT64_MAX;
65cd9064 1944 Error *local_err = NULL;
89e48965
AF		 1945 int64_t value;
1946
51e72bc1 1947 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1948 if (local_err) {
1949 error_propagate(errp, local_err);
89e48965
AF		 1950 return;
1951 }
1952 if (value < min || value > max) {
c6bd8c70
MA		 1953 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1954 name ? name : "null", value, min, max);
89e48965
AF		 1955 return;
1956 }
1957
36f96c4b 1958 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1959}
1960
7e5292b5 1961/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1962static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1963 const char *name, void *opaque,
1964 Error **errp)
8e8aba50 1965{
7e5292b5 1966 uint32_t *array = (uint32_t *)opaque;
8e8aba50 1967 FeatureWord w;
8e8aba50
EH		 1968 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1969 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1970 X86CPUFeatureWordInfoList *list = NULL;
1971
1972 for (w = 0; w < FEATURE_WORDS; w++) {
1973 FeatureWordInfo *wi = &feature_word_info[w];
1974 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1975 qwi->cpuid_input_eax = wi->cpuid_eax;
1976 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1977 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1978 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1979 qwi->features = array[w];
8e8aba50
EH		 1980
1981 /* List will be in reverse order, but order shouldn't matter */
1982 list_entries[w].next = list;
1983 list_entries[w].value = &word_infos[w];
1984 list = &list_entries[w];
1985 }
1986
6b62d961 1987 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 1988}
1989
d7bce999
EB		 1990static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1991 void *opaque, Error **errp)
c8f0f88e
IM		 1992{
1993 X86CPU *cpu = X86_CPU(obj);
1994 int64_t value = cpu->hyperv_spinlock_attempts;
1995
51e72bc1 1996 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1997}
1998
d7bce999
EB		 1999static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
2000 void *opaque, Error **errp)
c8f0f88e
IM		 2001{
2002 const int64_t min = 0xFFF;
2003 const int64_t max = UINT_MAX;
2004 X86CPU *cpu = X86_CPU(obj);
2005 Error *err = NULL;
2006 int64_t value;
2007
51e72bc1 2008 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 2009 if (err) {
2010 error_propagate(errp, err);
2011 return;
2012 }
2013
2014 if (value < min || value > max) {
2015 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 2016 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
2017 object_get_typename(obj), name ? name : "null",
2018 value, min, max);
c8f0f88e
IM		 2019 return;
2020 }
2021 cpu->hyperv_spinlock_attempts = value;
2022}
2023
1b6b7d10 2024static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 2025 .name = "int",
2026 .get = x86_get_hv_spinlocks,
2027 .set = x86_set_hv_spinlocks,
2028};
2029
72ac2e87
IM		 2030/* Convert all '_' in a feature string option name to '-', to make feature
2031 * name conform to QOM property naming rule, which uses '-' instead of '_'.
2032 */
2033static inline void feat2prop(char *s)
2034{
2035 while ((s = strchr(s, '_'))) {
2036 *s = '-';
2037 }
2038}
2039
b54c9377
EH		 2040/* Return the feature property name for a feature flag bit */
2041static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
2042{
2043 /* XSAVE components are automatically enabled by other features,
2044 * so return the original feature name instead
2045 */
2046 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
2047 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
2048
2049 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
2050 x86_ext_save_areas[comp].bits) {
2051 w = x86_ext_save_areas[comp].feature;
2052 bitnr = ctz32(x86_ext_save_areas[comp].bits);
2053 }
2054 }
2055
2056 assert(bitnr < 32);
2057 assert(w < FEATURE_WORDS);
2058 return feature_word_info[w].feat_names[bitnr];
2059}
2060
dc15c051
IM		 2061/* Compatibily hack to maintain legacy +-feat semantic,
2062 * where +-feat overwrites any feature set by
2063 * feat=on|feat even if the later is parsed after +-feat
2064 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2065 */
2fae0d96 2066static GList *plus_features, *minus_features;
dc15c051 2067
83a00f60
EH		 2068static gint compare_string(gconstpointer a, gconstpointer b)
2069{
2070 return g_strcmp0(a, b);
2071}
2072
8f961357
EH		 2073/* Parse "+feature,-feature,feature=foo" CPU feature string
2074 */
62a48a2a 2075static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 2076 Error **errp)
8f961357 2077{
8f961357 2078 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 2079 static bool cpu_globals_initialized;
83a00f60 2080 bool ambiguous = false;
62a48a2a
IM		 2081
2082 if (cpu_globals_initialized) {
2083 return;
2084 }
2085 cpu_globals_initialized = true;
8f961357 2086
f6750e95
EH		 2087 if (!features) {
2088 return;
2089 }
2090
2091 for (featurestr = strtok(features, ",");
685479bd 2092 featurestr;
f6750e95
EH		 2093 featurestr = strtok(NULL, ",")) {
2094 const char *name;
2095 const char *val = NULL;
2096 char *eq = NULL;
cf2887c9 2097 char num[32];
62a48a2a 2098 GlobalProperty *prop;
c6dc6f63 2099
f6750e95 2100 /* Compatibility syntax: */
c6dc6f63 2101 if (featurestr[0] == '+') {
2fae0d96
EH		 2102 plus_features = g_list_append(plus_features,
2103 g_strdup(featurestr + 1));
f6750e95 2104 continue;
c6dc6f63 2105 } else if (featurestr[0] == '-') {
2fae0d96
EH		 2106 minus_features = g_list_append(minus_features,
2107 g_strdup(featurestr + 1));
f6750e95
EH		 2108 continue;
2109 }
2110
2111 eq = strchr(featurestr, '=');
2112 if (eq) {
2113 *eq++ = 0;
2114 val = eq;
c6dc6f63 2115 } else {
f6750e95 2116 val = "on";
a91987c2 2117 }
f6750e95
EH		 2118
2119 feat2prop(featurestr);
2120 name = featurestr;
2121
83a00f60 2122 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 2123 warn_report("Ambiguous CPU model string. "
2124 "Don't mix both \"+%s\" and \"%s=%s\"",
2125 name, name, val);
83a00f60
EH		 2126 ambiguous = true;
2127 }
2128 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 2129 warn_report("Ambiguous CPU model string. "
2130 "Don't mix both \"-%s\" and \"%s=%s\"",
2131 name, name, val);
83a00f60
EH		 2132 ambiguous = true;
2133 }
2134
f6750e95
EH		 2135 /* Special case: */
2136 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 2137 int ret;
f46bfdbf 2138 uint64_t tsc_freq;
f6750e95 2139
f17fd4fd 2140 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 2141 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 2142 error_setg(errp, "bad numerical value %s", val);
2143 return;
2144 }
2145 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2146 val = num;
2147 name = "tsc-frequency";
c6dc6f63 2148 }
f6750e95 2149
62a48a2a
IM		 2150 prop = g_new0(typeof(*prop), 1);
2151 prop->driver = typename;
2152 prop->property = g_strdup(name);
2153 prop->value = g_strdup(val);
2154 prop->errp = &error_fatal;
2155 qdev_prop_register_global(prop);
f6750e95
EH		 2156 }
2157
83a00f60 2158 if (ambiguous) {
3dc6f869
AF		 2159 warn_report("Compatibility of ambiguous CPU model "
2160 "strings won't be kept on future QEMU versions");
83a00f60 2161 }
c6dc6f63
AP		 2162}
2163
b8d834a0 2164static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 2165static int x86_cpu_filter_features(X86CPU *cpu);
2166
2167/* Check for missing features that may prevent the CPU class from
2168 * running using the current machine and accelerator.
2169 */
2170static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
2171 strList **missing_feats)
2172{
2173 X86CPU *xc;
2174 FeatureWord w;
2175 Error *err = NULL;
2176 strList **next = missing_feats;
2177
2178 if (xcc->kvm_required && !kvm_enabled()) {
2179 strList *new = g_new0(strList, 1);
2180 new->value = g_strdup("kvm");;
2181 *missing_feats = new;
2182 return;
2183 }
2184
2185 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2186
b8d834a0 2187 x86_cpu_expand_features(xc, &err);
b54c9377 2188 if (err) {
b8d834a0 2189 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 2190 * but in case it does, just report the model as not
2191 * runnable at all using the "type" property.
2192 */
2193 strList *new = g_new0(strList, 1);
2194 new->value = g_strdup("type");
2195 *next = new;
2196 next = &new->next;
2197 }
2198
2199 x86_cpu_filter_features(xc);
2200
2201 for (w = 0; w < FEATURE_WORDS; w++) {
2202 uint32_t filtered = xc->filtered_features[w];
2203 int i;
2204 for (i = 0; i < 32; i++) {
2205 if (filtered & (1UL << i)) {
2206 strList *new = g_new0(strList, 1);
2207 new->value = g_strdup(x86_cpu_feature_name(w, i));
2208 *next = new;
2209 next = &new->next;
2210 }
2211 }
2212 }
2213
2214 object_unref(OBJECT(xc));
2215}
2216
8c3329e5 2217/* Print all cpuid feature names in featureset
c6dc6f63 2218 */
8c3329e5 2219static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2220{
8c3329e5
EH		 2221 int bit;
2222 bool first = true;
2223
2224 for (bit = 0; bit < 32; bit++) {
2225 if (featureset[bit]) {
2226 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2227 first = false;
c6dc6f63 2228 }
8c3329e5 2229 }
c6dc6f63
AP		 2230}
2231
f48c8837 2232/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 2233static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
2234{
2235 ObjectClass *class_a = (ObjectClass *)a;
2236 ObjectClass *class_b = (ObjectClass *)b;
2237 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
2238 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
2239 const char *name_a, *name_b;
2240
f48c8837
EH		 2241 if (cc_a->ordering != cc_b->ordering) {
2242 return cc_a->ordering - cc_b->ordering;
ee465a3e
EH		 2243 } else {
2244 name_a = object_class_get_name(class_a);
2245 name_b = object_class_get_name(class_b);
2246 return strcmp(name_a, name_b);
2247 }
2248}
2249
2250static GSList *get_sorted_cpu_model_list(void)
2251{
2252 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
2253 list = g_slist_sort(list, x86_cpu_list_compare);
2254 return list;
2255}
2256
2257static void x86_cpu_list_entry(gpointer data, gpointer user_data)
2258{
2259 ObjectClass *oc = data;
2260 X86CPUClass *cc = X86_CPU_CLASS(oc);
2261 CPUListState *s = user_data;
2262 char *name = x86_cpu_class_get_model_name(cc);
2263 const char *desc = cc->model_description;
0bacd8b3 2264 if (!desc && cc->cpu_def) {
ee465a3e
EH		 2265 desc = cc->cpu_def->model_id;
2266 }
2267
2268 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
2269 name, desc);
2270 g_free(name);
2271}
2272
2273/* list available CPU models and flags */
e916cbf8 2274void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2275{
7fc9b714 2276 int i;
ee465a3e
EH		 2277 CPUListState s = {
2278 .file = f,
2279 .cpu_fprintf = cpu_fprintf,
2280 };
2281 GSList *list;
c6dc6f63 2282
ee465a3e
EH		 2283 (*cpu_fprintf)(f, "Available CPUs:\n");
2284 list = get_sorted_cpu_model_list();
2285 g_slist_foreach(list, x86_cpu_list_entry, &s);
2286 g_slist_free(list);
21ad7789 2287
6cdf8854 2288 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2289 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2290 FeatureWordInfo *fw = &feature_word_info[i];
2291
8c3329e5
EH		 2292 (*cpu_fprintf)(f, " ");
2293 listflags(f, cpu_fprintf, fw->feat_names);
2294 (*cpu_fprintf)(f, "\n");
3af60be2 2295 }
c6dc6f63
AP		 2296}
2297
ee465a3e
EH		 2298static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
2299{
2300 ObjectClass *oc = data;
2301 X86CPUClass *cc = X86_CPU_CLASS(oc);
2302 CpuDefinitionInfoList **cpu_list = user_data;
2303 CpuDefinitionInfoList *entry;
2304 CpuDefinitionInfo *info;
2305
2306 info = g_malloc0(sizeof(*info));
2307 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 2308 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
2309 info->has_unavailable_features = true;
8ed877b7 2310 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 2311 info->migration_safe = cc->migration_safe;
2312 info->has_migration_safe = true;
5adbed30 2313 info->q_static = cc->static_model;
ee465a3e
EH		 2314
2315 entry = g_malloc0(sizeof(*entry));
2316 entry->value = info;
2317 entry->next = *cpu_list;
2318 *cpu_list = entry;
2319}
2320
76b64a7a 2321CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2322{
2323 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 2324 GSList *list = get_sorted_cpu_model_list();
2325 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
2326 g_slist_free(list);
e3966126
AL		 2327 return cpu_list;
2328}
2329
84f1b92f
EH		 2330static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2331 bool migratable_only)
27418adf
EH		 2332{
2333 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2334 uint32_t r;
27418adf 2335
fefb41bf 2336 if (kvm_enabled()) {
84f1b92f
EH		 2337 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2338 wi->cpuid_ecx,
2339 wi->cpuid_reg);
fefb41bf 2340 } else if (tcg_enabled()) {
84f1b92f 2341 r = wi->tcg_features;
fefb41bf
EH		 2342 } else {
2343 return ~0;
2344 }
84f1b92f
EH		 2345 if (migratable_only) {
2346 r &= x86_cpu_get_migratable_flags(w);
2347 }
2348 return r;
27418adf
EH		 2349}
2350
8ca30e86
EH		 2351static void x86_cpu_report_filtered_features(X86CPU *cpu)
2352{
2353 FeatureWord w;
2354
2355 for (w = 0; w < FEATURE_WORDS; w++) {
2356 report_unavailable_features(w, cpu->filtered_features[w]);
2357 }
2358}
2359
5114e842
EH		 2360static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2361{
2362 PropValue *pv;
2363 for (pv = props; pv->prop; pv++) {
2364 if (!pv->value) {
2365 continue;
2366 }
2367 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2368 &error_abort);
2369 }
2370}
2371
f99fd7ca 2372/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 2373 */
d940ee9b 2374static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2375{
61dcd775 2376 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2377 const char *vendor;
2378 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2379 FeatureWord w;
c6dc6f63 2380
f99fd7ca
EH		 2381 /*NOTE: any property set by this function should be returned by
2382 * x86_cpu_static_props(), so static expansion of
2383 * query-cpu-model-expansion is always complete.
2384 */
2385
c39c0edf 2386 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 2387 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
2388 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 2389
2d64255b
AF		 2390 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2391 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2392 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2393 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2394 for (w = 0; w < FEATURE_WORDS; w++) {
2395 env->features[w] = def->features[w];
2396 }
82beb536 2397
9576de75 2398 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2399 if (kvm_enabled()) {
492a4c94
LT		 2400 if (!kvm_irqchip_in_kernel()) {
2401 x86_cpu_change_kvm_default("x2apic", "off");
2402 }
2403
5114e842 2404 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 2405 } else if (tcg_enabled()) {
2406 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 2407 }
5fcca9ff 2408
82beb536 2409 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2410
2411 /* sysenter isn't supported in compatibility mode on AMD,
2412 * syscall isn't supported in compatibility mode on Intel.
2413 * Normally we advertise the actual CPU vendor, but you can
2414 * override this using the 'vendor' property if you want to use
2415 * KVM's sysenter/syscall emulation in compatibility mode and
2416 * when doing cross vendor migration
2417 */
74f54bc4 2418 vendor = def->vendor;
7c08db30
EH		 2419 if (kvm_enabled()) {
2420 uint32_t ebx = 0, ecx = 0, edx = 0;
2421 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2422 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2423 vendor = host_vendor;
2424 }
2425
2426 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2427
c6dc6f63
AP		 2428}
2429
f99fd7ca
EH		 2430/* Return a QDict containing keys for all properties that can be included
2431 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
2432 * must be included in the dictionary.
2433 */
2434static QDict *x86_cpu_static_props(void)
2435{
2436 FeatureWord w;
2437 int i;
2438 static const char *props[] = {
2439 "min-level",
2440 "min-xlevel",
2441 "family",
2442 "model",
2443 "stepping",
2444 "model-id",
2445 "vendor",
2446 "lmce",
2447 NULL,
2448 };
2449 static QDict *d;
2450
2451 if (d) {
2452 return d;
2453 }
2454
2455 d = qdict_new();
2456 for (i = 0; props[i]; i++) {
006ca09f 2457 qdict_put(d, props[i], qnull());
f99fd7ca
EH		 2458 }
2459
2460 for (w = 0; w < FEATURE_WORDS; w++) {
2461 FeatureWordInfo *fi = &feature_word_info[w];
2462 int bit;
2463 for (bit = 0; bit < 32; bit++) {
2464 if (!fi->feat_names[bit]) {
2465 continue;
2466 }
006ca09f 2467 qdict_put(d, fi->feat_names[bit], qnull());
f99fd7ca
EH		 2468 }
2469 }
2470
2471 return d;
2472}
2473
2474/* Add an entry to @props dict, with the value for property. */
2475static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
2476{
2477 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
2478 &error_abort);
2479
2480 qdict_put_obj(props, prop, value);
2481}
2482
2483/* Convert CPU model data from X86CPU object to a property dictionary
2484 * that can recreate exactly the same CPU model.
2485 */
2486static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
2487{
2488 QDict *sprops = x86_cpu_static_props();
2489 const QDictEntry *e;
2490
2491 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
2492 const char *prop = qdict_entry_key(e);
2493 x86_cpu_expand_prop(cpu, props, prop);
2494 }
2495}
2496
b8097deb
EH		 2497/* Convert CPU model data from X86CPU object to a property dictionary
2498 * that can recreate exactly the same CPU model, including every
2499 * writeable QOM property.
2500 */
2501static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
2502{
2503 ObjectPropertyIterator iter;
2504 ObjectProperty *prop;
2505
2506 object_property_iter_init(&iter, OBJECT(cpu));
2507 while ((prop = object_property_iter_next(&iter))) {
2508 /* skip read-only or write-only properties */
2509 if (!prop->get || !prop->set) {
2510 continue;
2511 }
2512
2513 /* "hotplugged" is the only property that is configurable
2514 * on the command-line but will be set differently on CPUs
2515 * created using "-cpu ... -smp ..." and by CPUs created
2516 * on the fly by x86_cpu_from_model() for querying. Skip it.
2517 */
2518 if (!strcmp(prop->name, "hotplugged")) {
2519 continue;
2520 }
2521 x86_cpu_expand_prop(cpu, props, prop->name);
2522 }
2523}
2524
f99fd7ca
EH		 2525static void object_apply_props(Object *obj, QDict *props, Error **errp)
2526{
2527 const QDictEntry *prop;
2528 Error *err = NULL;
2529
2530 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
2531 object_property_set_qobject(obj, qdict_entry_value(prop),
2532 qdict_entry_key(prop), &err);
2533 if (err) {
2534 break;
2535 }
2536 }
2537
2538 error_propagate(errp, err);
2539}
2540
2541/* Create X86CPU object according to model+props specification */
2542static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
2543{
2544 X86CPU *xc = NULL;
2545 X86CPUClass *xcc;
2546 Error *err = NULL;
2547
2548 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
2549 if (xcc == NULL) {
2550 error_setg(&err, "CPU model '%s' not found", model);
2551 goto out;
2552 }
2553
2554 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2555 if (props) {
2556 object_apply_props(OBJECT(xc), props, &err);
2557 if (err) {
2558 goto out;
2559 }
2560 }
2561
2562 x86_cpu_expand_features(xc, &err);
2563 if (err) {
2564 goto out;
2565 }
2566
2567out:
2568 if (err) {
2569 error_propagate(errp, err);
2570 object_unref(OBJECT(xc));
2571 xc = NULL;
2572 }
2573 return xc;
2574}
2575
2576CpuModelExpansionInfo *
2577arch_query_cpu_model_expansion(CpuModelExpansionType type,
2578 CpuModelInfo *model,
2579 Error **errp)
2580{
2581 X86CPU *xc = NULL;
2582 Error *err = NULL;
2583 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
2584 QDict *props = NULL;
2585 const char *base_name;
2586
2587 xc = x86_cpu_from_model(model->name,
2588 model->has_props ?
2589 qobject_to_qdict(model->props) :
2590 NULL, &err);
2591 if (err) {
2592 goto out;
2593 }
2594
b8097deb 2595 props = qdict_new();
f99fd7ca
EH		 2596
2597 switch (type) {
2598 case CPU_MODEL_EXPANSION_TYPE_STATIC:
2599 /* Static expansion will be based on "base" only */
2600 base_name = "base";
b8097deb 2601 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 2602 break;
2603 case CPU_MODEL_EXPANSION_TYPE_FULL:
2604 /* As we don't return every single property, full expansion needs
2605 * to keep the original model name+props, and add extra
2606 * properties on top of that.
2607 */
2608 base_name = model->name;
b8097deb 2609 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 2610 break;
2611 default:
2612 error_setg(&err, "Unsupportted expansion type");
2613 goto out;
2614 }
2615
2616 if (!props) {
2617 props = qdict_new();
2618 }
2619 x86_cpu_to_dict(xc, props);
2620
2621 ret->model = g_new0(CpuModelInfo, 1);
2622 ret->model->name = g_strdup(base_name);
2623 ret->model->props = QOBJECT(props);
2624 ret->model->has_props = true;
2625
2626out:
2627 object_unref(OBJECT(xc));
2628 if (err) {
2629 error_propagate(errp, err);
2630 qapi_free_CpuModelExpansionInfo(ret);
2631 ret = NULL;
2632 }
2633 return ret;
2634}
2635
00fcd100
AB		 2636static gchar *x86_gdb_arch_name(CPUState *cs)
2637{
2638#ifdef TARGET_X86_64
2639 return g_strdup("i386:x86-64");
2640#else
2641 return g_strdup("i386");
2642#endif
2643}
2644
0856579c 2645X86CPU *cpu_x86_init(const char *cpu_model)
7f833247 2646{
a57d0163 2647 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
5c3c6a68
AF		 2648}
2649
d940ee9b
EH		 2650static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2651{
2652 X86CPUDefinition *cpudef = data;
2653 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2654
2655 xcc->cpu_def = cpudef;
bd72159d 2656 xcc->migration_safe = true;
d940ee9b
EH		 2657}
2658
2659static void x86_register_cpudef_type(X86CPUDefinition *def)
2660{
2661 char *typename = x86_cpu_type_name(def->name);
2662 TypeInfo ti = {
2663 .name = typename,
2664 .parent = TYPE_X86_CPU,
2665 .class_init = x86_cpu_cpudef_class_init,
2666 .class_data = def,
2667 };
2668
2a923a29
EH		 2669 /* AMD aliases are handled at runtime based on CPUID vendor, so
2670 * they shouldn't be set on the CPU model table.
2671 */
2672 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
2673
d940ee9b
EH		 2674 type_register(&ti);
2675 g_free(typename);
2676}
2677
c6dc6f63 2678#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2679
0e26b7b8
BS		 2680void cpu_clear_apic_feature(CPUX86State *env)
2681{
0514ef2f 2682 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2683}
2684
c6dc6f63
AP		 2685#endif /* !CONFIG_USER_ONLY */
2686
c6dc6f63
AP		 2687void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2688 uint32_t *eax, uint32_t *ebx,
2689 uint32_t *ecx, uint32_t *edx)
2690{
a60f24b5
AF		 2691 X86CPU *cpu = x86_env_get_cpu(env);
2692 CPUState *cs = CPU(cpu);
14c985cf 2693 uint32_t pkg_offset;
4ed3d478 2694 uint32_t limit;
1ce36bfe 2695 uint32_t signature[3];
a60f24b5 2696
4ed3d478
DB		 2697 /* Calculate & apply limits for different index ranges */
2698 if (index >= 0xC0000000) {
2699 limit = env->cpuid_xlevel2;
2700 } else if (index >= 0x80000000) {
2701 limit = env->cpuid_xlevel;
1ce36bfe
DB		 2702 } else if (index >= 0x40000000) {
2703 limit = 0x40000001;
c6dc6f63 2704 } else {
4ed3d478
DB		 2705 limit = env->cpuid_level;
2706 }
2707
2708 if (index > limit) {
2709 /* Intel documentation states that invalid EAX input will
2710 * return the same information as EAX=cpuid_level
2711 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2712 */
2713 index = env->cpuid_level;
c6dc6f63
AP		 2714 }
2715
2716 switch(index) {
2717 case 0:
2718 *eax = env->cpuid_level;
5eb2f7a4
EH		 2719 *ebx = env->cpuid_vendor1;
2720 *edx = env->cpuid_vendor2;
2721 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2722 break;
2723 case 1:
2724 *eax = env->cpuid_version;
7e72a45c
EH		 2725 *ebx = (cpu->apic_id << 24) |
2726 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2727 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2728 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2729 *ecx |= CPUID_EXT_OSXSAVE;
2730 }
0514ef2f 2731 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2732 if (cs->nr_cores * cs->nr_threads > 1) {
2733 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2734 *edx |= CPUID_HT;
c6dc6f63
AP		 2735 }
2736 break;
2737 case 2:
2738 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2739 if (cpu->cache_info_passthrough) {
2740 host_cpuid(index, 0, eax, ebx, ecx, edx);
2741 break;
2742 }
5e891bf8 2743 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 2744 *ebx = 0;
14c985cf
LM		 2745 if (!cpu->enable_l3_cache) {
2746 *ecx = 0;
2747 } else {
2748 *ecx = L3_N_DESCRIPTOR;
2749 }
5e891bf8
EH		 2750 *edx = (L1D_DESCRIPTOR << 16) | \
2751 (L1I_DESCRIPTOR << 8) | \
2752 (L2_DESCRIPTOR);
c6dc6f63
AP		 2753 break;
2754 case 4:
2755 /* cache info: needed for Core compatibility */
787aaf57
BC		 2756 if (cpu->cache_info_passthrough) {
2757 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2758 *eax &= ~0xFC000000;
c6dc6f63 2759 } else {
2f7a21c4 2760 *eax = 0;
76c2975a 2761 switch (count) {
c6dc6f63 2762 case 0: /* L1 dcache info */
5e891bf8
EH		 2763 *eax |= CPUID_4_TYPE_DCACHE | \
2764 CPUID_4_LEVEL(1) | \
2765 CPUID_4_SELF_INIT_LEVEL;
2766 *ebx = (L1D_LINE_SIZE - 1) | \
2767 ((L1D_PARTITIONS - 1) << 12) | \
2768 ((L1D_ASSOCIATIVITY - 1) << 22);
2769 *ecx = L1D_SETS - 1;
2770 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2771 break;
2772 case 1: /* L1 icache info */
5e891bf8
EH		 2773 *eax |= CPUID_4_TYPE_ICACHE | \
2774 CPUID_4_LEVEL(1) | \
2775 CPUID_4_SELF_INIT_LEVEL;
2776 *ebx = (L1I_LINE_SIZE - 1) | \
2777 ((L1I_PARTITIONS - 1) << 12) | \
2778 ((L1I_ASSOCIATIVITY - 1) << 22);
2779 *ecx = L1I_SETS - 1;
2780 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2781 break;
2782 case 2: /* L2 cache info */
5e891bf8
EH		 2783 *eax |= CPUID_4_TYPE_UNIFIED | \
2784 CPUID_4_LEVEL(2) | \
2785 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2786 if (cs->nr_threads > 1) {
2787 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2788 }
5e891bf8
EH		 2789 *ebx = (L2_LINE_SIZE - 1) | \
2790 ((L2_PARTITIONS - 1) << 12) | \
2791 ((L2_ASSOCIATIVITY - 1) << 22);
2792 *ecx = L2_SETS - 1;
2793 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63 2794 break;
14c985cf
LM		 2795 case 3: /* L3 cache info */
2796 if (!cpu->enable_l3_cache) {
2797 *eax = 0;
2798 *ebx = 0;
2799 *ecx = 0;
2800 *edx = 0;
2801 break;
2802 }
2803 *eax |= CPUID_4_TYPE_UNIFIED | \
2804 CPUID_4_LEVEL(3) | \
2805 CPUID_4_SELF_INIT_LEVEL;
2806 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2807 *eax |= ((1 << pkg_offset) - 1) << 14;
2808 *ebx = (L3_N_LINE_SIZE - 1) | \
2809 ((L3_N_PARTITIONS - 1) << 12) | \
2810 ((L3_N_ASSOCIATIVITY - 1) << 22);
2811 *ecx = L3_N_SETS - 1;
2812 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2813 break;
c6dc6f63
AP		 2814 default: /* end of info */
2815 *eax = 0;
2816 *ebx = 0;
2817 *ecx = 0;
2818 *edx = 0;
2819 break;
76c2975a
PB		 2820 }
2821 }
2822
2823 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2824 if ((*eax & 31) && cs->nr_cores > 1) {
2825 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2826 }
2827 break;
2828 case 5:
2829 /* mwait info: needed for Core compatibility */
2830 *eax = 0; /* Smallest monitor-line size in bytes */
2831 *ebx = 0; /* Largest monitor-line size in bytes */
2832 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2833 *edx = 0;
2834 break;
2835 case 6:
2836 /* Thermal and Power Leaf */
28b8e4d0 2837 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2838 *ebx = 0;
2839 *ecx = 0;
2840 *edx = 0;
2841 break;
f7911686 2842 case 7:
13526728
EH		 2843 /* Structured Extended Feature Flags Enumeration Leaf */
2844 if (count == 0) {
2845 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2846 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2847 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2848 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2849 *ecx |= CPUID_7_0_ECX_OSPKE;
2850 }
95ea69fb 2851 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 2852 } else {
2853 *eax = 0;
2854 *ebx = 0;
2855 *ecx = 0;
2856 *edx = 0;
2857 }
2858 break;
c6dc6f63
AP		 2859 case 9:
2860 /* Direct Cache Access Information Leaf */
2861 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2862 *ebx = 0;
2863 *ecx = 0;
2864 *edx = 0;
2865 break;
2866 case 0xA:
2867 /* Architectural Performance Monitoring Leaf */
9337e3b6 2868 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2869 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2870
2871 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2872 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2873 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2874 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2875 } else {
2876 *eax = 0;
2877 *ebx = 0;
2878 *ecx = 0;
2879 *edx = 0;
2880 }
c6dc6f63 2881 break;
5232d00a
RK		 2882 case 0xB:
2883 /* Extended Topology Enumeration Leaf */
2884 if (!cpu->enable_cpuid_0xb) {
2885 *eax = *ebx = *ecx = *edx = 0;
2886 break;
2887 }
2888
2889 *ecx = count & 0xff;
2890 *edx = cpu->apic_id;
2891
2892 switch (count) {
2893 case 0:
eab60fb9
MAL		 2894 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
2895 *ebx = cs->nr_threads;
5232d00a
RK		 2896 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2897 break;
2898 case 1:
eab60fb9
MAL		 2899 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2900 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 2901 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2902 break;
2903 default:
2904 *eax = 0;
2905 *ebx = 0;
2906 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2907 }
2908
2909 assert(!(*eax & ~0x1f));
2910 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2911 break;
2560f19f 2912 case 0xD: {
51e49430 2913 /* Processor Extended State */
2560f19f
PB		 2914 *eax = 0;
2915 *ebx = 0;
2916 *ecx = 0;
2917 *edx = 0;
19dc85db 2918 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2919 break;
2920 }
4928cd6d 2921
2560f19f 2922 if (count == 0) {
96193c22
EH		 2923 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
2924 *eax = env->features[FEAT_XSAVE_COMP_LO];
2925 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 2926 *ebx = *ecx;
2927 } else if (count == 1) {
0bb0b2d2 2928 *eax = env->features[FEAT_XSAVE];
f4f1110e 2929 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 2930 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
2931 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 2932 *eax = esa->size;
2933 *ebx = esa->offset;
2560f19f 2934 }
51e49430
SY		 2935 }
2936 break;
2560f19f 2937 }
1ce36bfe
DB		 2938 case 0x40000000:
2939 /*
2940 * CPUID code in kvm_arch_init_vcpu() ignores stuff
2941 * set here, but we restrict to TCG none the less.
2942 */
2943 if (tcg_enabled() && cpu->expose_tcg) {
2944 memcpy(signature, "TCGTCGTCGTCG", 12);
2945 *eax = 0x40000001;
2946 *ebx = signature[0];
2947 *ecx = signature[1];
2948 *edx = signature[2];
2949 } else {
2950 *eax = 0;
2951 *ebx = 0;
2952 *ecx = 0;
2953 *edx = 0;
2954 }
2955 break;
2956 case 0x40000001:
2957 *eax = 0;
2958 *ebx = 0;
2959 *ecx = 0;
2960 *edx = 0;
2961 break;
c6dc6f63
AP		 2962 case 0x80000000:
2963 *eax = env->cpuid_xlevel;
2964 *ebx = env->cpuid_vendor1;
2965 *edx = env->cpuid_vendor2;
2966 *ecx = env->cpuid_vendor3;
2967 break;
2968 case 0x80000001:
2969 *eax = env->cpuid_version;
2970 *ebx = 0;
0514ef2f
EH		 2971 *ecx = env->features[FEAT_8000_0001_ECX];
2972 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2973
2974 /* The Linux kernel checks for the CMPLegacy bit and
2975 * discards multiple thread information if it is set.
cb8d4c8f 2976 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2977 */
ce3960eb 2978 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2979 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2980 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2981 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2982 *ecx |= 1 << 1; /* CmpLegacy bit */
2983 }
2984 }
c6dc6f63
AP		 2985 break;
2986 case 0x80000002:
2987 case 0x80000003:
2988 case 0x80000004:
2989 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2990 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2991 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2992 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2993 break;
2994 case 0x80000005:
2995 /* cache info (L1 cache) */
787aaf57
BC		 2996 if (cpu->cache_info_passthrough) {
2997 host_cpuid(index, 0, eax, ebx, ecx, edx);
2998 break;
2999 }
5e891bf8
EH		 3000 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
3001 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
3002 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
3003 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
3004 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
3005 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
3006 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
3007 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 3008 break;
3009 case 0x80000006:
3010 /* cache info (L2 cache) */
787aaf57
BC		 3011 if (cpu->cache_info_passthrough) {
3012 host_cpuid(index, 0, eax, ebx, ecx, edx);
3013 break;
3014 }
5e891bf8
EH		 3015 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
3016 (L2_DTLB_2M_ENTRIES << 16) | \
3017 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
3018 (L2_ITLB_2M_ENTRIES);
3019 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
3020 (L2_DTLB_4K_ENTRIES << 16) | \
3021 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
3022 (L2_ITLB_4K_ENTRIES);
3023 *ecx = (L2_SIZE_KB_AMD << 16) | \
3024 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
3025 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
14c985cf
LM		 3026 if (!cpu->enable_l3_cache) {
3027 *edx = ((L3_SIZE_KB / 512) << 18) | \
3028 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
3029 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
3030 } else {
3031 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
3032 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
3033 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
3034 }
c6dc6f63 3035 break;
303752a9
MT		 3036 case 0x80000007:
3037 *eax = 0;
3038 *ebx = 0;
3039 *ecx = 0;
3040 *edx = env->features[FEAT_8000_0007_EDX];
3041 break;
c6dc6f63
AP		 3042 case 0x80000008:
3043 /* virtual & phys address size in low 2 bytes. */
0514ef2f 3044 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 3045 /* 64 bit processor */
3046 *eax = cpu->phys_bits; /* configurable physical bits */
3047 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
3048 *eax |= 0x00003900; /* 57 bits virtual */
3049 } else {
3050 *eax |= 0x00003000; /* 48 bits virtual */
3051 }
c6dc6f63 3052 } else {
af45907a 3053 *eax = cpu->phys_bits;
c6dc6f63
AP		 3054 }
3055 *ebx = 0;
3056 *ecx = 0;
3057 *edx = 0;
ce3960eb
AF		 3058 if (cs->nr_cores * cs->nr_threads > 1) {
3059 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 3060 }
3061 break;
3062 case 0x8000000A:
0514ef2f 3063 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 3064 *eax = 0x00000001; /* SVM Revision */
3065 *ebx = 0x00000010; /* nr of ASIDs */
3066 *ecx = 0;
0514ef2f 3067 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 3068 } else {
3069 *eax = 0;
3070 *ebx = 0;
3071 *ecx = 0;
3072 *edx = 0;
3073 }
c6dc6f63 3074 break;
b3baa152
BW		 3075 case 0xC0000000:
3076 *eax = env->cpuid_xlevel2;
3077 *ebx = 0;
3078 *ecx = 0;
3079 *edx = 0;
3080 break;
3081 case 0xC0000001:
3082 /* Support for VIA CPU's CPUID instruction */
3083 *eax = env->cpuid_version;
3084 *ebx = 0;
3085 *ecx = 0;
0514ef2f 3086 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 3087 break;
3088 case 0xC0000002:
3089 case 0xC0000003:
3090 case 0xC0000004:
3091 /* Reserved for the future, and now filled with zero */
3092 *eax = 0;
3093 *ebx = 0;
3094 *ecx = 0;
3095 *edx = 0;
3096 break;
c6dc6f63
AP		 3097 default:
3098 /* reserved values: zero */
3099 *eax = 0;
3100 *ebx = 0;
3101 *ecx = 0;
3102 *edx = 0;
3103 break;
3104 }
3105}
5fd2087a
AF		 3106
3107/* CPUClass::reset() */
3108static void x86_cpu_reset(CPUState *s)
3109{
3110 X86CPU *cpu = X86_CPU(s);
3111 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
3112 CPUX86State *env = &cpu->env;
a114d25d
RH		 3113 target_ulong cr4;
3114 uint64_t xcr0;
c1958aea
AF		 3115 int i;
3116
5fd2087a
AF		 3117 xcc->parent_reset(s);
3118
5e992a8e 3119 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 3120
c1958aea
AF		 3121 env->old_exception = -1;
3122
3123 /* init to reset state */
3124
c1958aea
AF		 3125 env->hflags2 |= HF2_GIF_MASK;
3126
3127 cpu_x86_update_cr0(env, 0x60000010);
3128 env->a20_mask = ~0x0;
3129 env->smbase = 0x30000;
3130
3131 env->idt.limit = 0xffff;
3132 env->gdt.limit = 0xffff;
3133 env->ldt.limit = 0xffff;
3134 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
3135 env->tr.limit = 0xffff;
3136 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
3137
3138 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
3139 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
3140 DESC_R_MASK | DESC_A_MASK);
3141 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
3142 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3143 DESC_A_MASK);
3144 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
3145 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3146 DESC_A_MASK);
3147 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
3148 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3149 DESC_A_MASK);
3150 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
3151 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3152 DESC_A_MASK);
3153 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
3154 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3155 DESC_A_MASK);
3156
3157 env->eip = 0xfff0;
3158 env->regs[R_EDX] = env->cpuid_version;
3159
3160 env->eflags = 0x2;
3161
3162 /* FPU init */
3163 for (i = 0; i < 8; i++) {
3164 env->fptags[i] = 1;
3165 }
5bde1407 3166 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 3167
3168 env->mxcsr = 0x1f80;
a114d25d
RH		 3169 /* All units are in INIT state. */
3170 env->xstate_bv = 0;
c1958aea
AF		 3171
3172 env->pat = 0x0007040600070406ULL;
3173 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
3174
3175 memset(env->dr, 0, sizeof(env->dr));
3176 env->dr[6] = DR6_FIXED_1;
3177 env->dr[7] = DR7_FIXED_1;
b3310ab3 3178 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 3179 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 3180
a114d25d 3181 cr4 = 0;
cfc3b074 3182 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 3183
3184#ifdef CONFIG_USER_ONLY
3185 /* Enable all the features for user-mode. */
3186 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 3187 xcr0 |= XSTATE_SSE_MASK;
a114d25d 3188 }
0f70ed47
PB		 3189 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
3190 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 3191 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 3192 xcr0 |= 1ull << i;
3193 }
a114d25d 3194 }
0f70ed47 3195
a114d25d
RH		 3196 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
3197 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
3198 }
07929f2a
RH		 3199 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
3200 cr4 |= CR4_FSGSBASE_MASK;
3201 }
a114d25d
RH		 3202#endif
3203
3204 env->xcr0 = xcr0;
3205 cpu_x86_update_cr4(env, cr4);
0522604b 3206
9db2efd9
AW		 3207 /*
3208 * SDM 11.11.5 requires:
3209 * - IA32_MTRR_DEF_TYPE MSR.E = 0
3210 * - IA32_MTRR_PHYSMASKn.V = 0
3211 * All other bits are undefined. For simplification, zero it all.
3212 */
3213 env->mtrr_deftype = 0;
3214 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
3215 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
3216
dd673288
IM		 3217#if !defined(CONFIG_USER_ONLY)
3218 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 3219 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 3220
259186a7 3221 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 3222
3223 if (kvm_enabled()) {
3224 kvm_arch_reset_vcpu(cpu);
3225 }
dd673288 3226#endif
5fd2087a
AF		 3227}
3228
dd673288
IM		 3229#ifndef CONFIG_USER_ONLY
3230bool cpu_is_bsp(X86CPU *cpu)
3231{
02e51483 3232 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 3233}
65dee380
IM		 3234
3235/* TODO: remove me, when reset over QOM tree is implemented */
3236static void x86_cpu_machine_reset_cb(void *opaque)
3237{
3238 X86CPU *cpu = opaque;
3239 cpu_reset(CPU(cpu));
3240}
dd673288
IM		 3241#endif
3242
de024815
AF		 3243static void mce_init(X86CPU *cpu)
3244{
3245 CPUX86State *cenv = &cpu->env;
3246 unsigned int bank;
3247
3248 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 3249 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 3250 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 3251 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
3252 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 3253 cenv->mcg_ctl = ~(uint64_t)0;
3254 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
3255 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
3256 }
3257 }
3258}
3259
bdeec802 3260#ifndef CONFIG_USER_ONLY
2f114315 3261APICCommonClass *apic_get_class(void)
bdeec802 3262{
bdeec802
IM		 3263 const char *apic_type = "apic";
3264
15eafc2e 3265 if (kvm_apic_in_kernel()) {
bdeec802
IM		 3266 apic_type = "kvm-apic";
3267 } else if (xen_enabled()) {
3268 apic_type = "xen-apic";
3269 }
3270
2f114315
RK		 3271 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
3272}
3273
3274static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
3275{
3276 APICCommonState *apic;
3277 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
3278
3279 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 3280
6816b1b3
IM		 3281 object_property_add_child(OBJECT(cpu), "lapic",
3282 OBJECT(cpu->apic_state), &error_abort);
67e55caa 3283 object_unref(OBJECT(cpu->apic_state));
6816b1b3 3284
33d7a288 3285 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 3286 /* TODO: convert to link<> */
02e51483 3287 apic = APIC_COMMON(cpu->apic_state);
60671e58 3288 apic->cpu = cpu;
8d42d2d3 3289 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 3290}
3291
3292static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3293{
8d42d2d3
CF		 3294 APICCommonState *apic;
3295 static bool apic_mmio_map_once;
3296
02e51483 3297 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 3298 return;
3299 }
6e8e2651
MA		 3300 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
3301 errp);
8d42d2d3
CF		 3302
3303 /* Map APIC MMIO area */
3304 apic = APIC_COMMON(cpu->apic_state);
3305 if (!apic_mmio_map_once) {
3306 memory_region_add_subregion_overlap(get_system_memory(),
3307 apic->apicbase &
3308 MSR_IA32_APICBASE_BASE,
3309 &apic->io_memory,
3310 0x1000);
3311 apic_mmio_map_once = true;
3312 }
bdeec802 3313}
f809c605
PB		 3314
3315static void x86_cpu_machine_done(Notifier *n, void *unused)
3316{
3317 X86CPU *cpu = container_of(n, X86CPU, machine_done);
3318 MemoryRegion *smram =
3319 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
3320
3321 if (smram) {
3322 cpu->smram = g_new(MemoryRegion, 1);
3323 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
3324 smram, 0, 1ull << 32);
f8c45c65 3325 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 3326 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
3327 }
3328}
d3c64d6a
IM		 3329#else
3330static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3331{
3332}
bdeec802
IM		 3333#endif
3334
11f6fee5
DDAG		 3335/* Note: Only safe for use on x86(-64) hosts */
3336static uint32_t x86_host_phys_bits(void)
3337{
3338 uint32_t eax;
3339 uint32_t host_phys_bits;
3340
3341 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
3342 if (eax >= 0x80000008) {
3343 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
3344 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3345 * at 23:16 that can specify a maximum physical address bits for
3346 * the guest that can override this value; but I've not seen
3347 * anything with that set.
3348 */
3349 host_phys_bits = eax & 0xff;
3350 } else {
3351 /* It's an odd 64 bit machine that doesn't have the leaf for
3352 * physical address bits; fall back to 36 that's most older
3353 * Intel.
3354 */
3355 host_phys_bits = 36;
3356 }
3357
3358 return host_phys_bits;
3359}
e48638fd 3360
c39c0edf
EH		 3361static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
3362{
3363 if (*min < value) {
3364 *min = value;
3365 }
3366}
3367
3368/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3369static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
3370{
3371 CPUX86State *env = &cpu->env;
3372 FeatureWordInfo *fi = &feature_word_info[w];
3373 uint32_t eax = fi->cpuid_eax;
3374 uint32_t region = eax & 0xF0000000;
3375
3376 if (!env->features[w]) {
3377 return;
3378 }
3379
3380 switch (region) {
3381 case 0x00000000:
3382 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
3383 break;
3384 case 0x80000000:
3385 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
3386 break;
3387 case 0xC0000000:
3388 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
3389 break;
3390 }
3391}
3392
2ca8a8be
EH		 3393/* Calculate XSAVE components based on the configured CPU feature flags */
3394static void x86_cpu_enable_xsave_components(X86CPU *cpu)
3395{
3396 CPUX86State *env = &cpu->env;
3397 int i;
96193c22 3398 uint64_t mask;
2ca8a8be
EH		 3399
3400 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
3401 return;
3402 }
3403
e3c9022b
EH		 3404 mask = 0;
3405 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 3406 const ExtSaveArea *esa = &x86_ext_save_areas[i];
3407 if (env->features[esa->feature] & esa->bits) {
96193c22 3408 mask |= (1ULL << i);
2ca8a8be
EH		 3409 }
3410 }
3411
96193c22
EH		 3412 env->features[FEAT_XSAVE_COMP_LO] = mask;
3413 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 3414}
3415
b8d834a0
EH		 3416/***** Steps involved on loading and filtering CPUID data
3417 *
3418 * When initializing and realizing a CPU object, the steps
3419 * involved in setting up CPUID data are:
3420 *
3421 * 1) Loading CPU model definition (X86CPUDefinition). This is
3422 * implemented by x86_cpu_load_def() and should be completely
3423 * transparent, as it is done automatically by instance_init.
3424 * No code should need to look at X86CPUDefinition structs
3425 * outside instance_init.
3426 *
3427 * 2) CPU expansion. This is done by realize before CPUID
3428 * filtering, and will make sure host/accelerator data is
3429 * loaded for CPU models that depend on host capabilities
3430 * (e.g. "host"). Done by x86_cpu_expand_features().
3431 *
3432 * 3) CPUID filtering. This initializes extra data related to
3433 * CPUID, and checks if the host supports all capabilities
3434 * required by the CPU. Runnability of a CPU model is
3435 * determined at this step. Done by x86_cpu_filter_features().
3436 *
3437 * Some operations don't require all steps to be performed.
3438 * More precisely:
3439 *
3440 * - CPU instance creation (instance_init) will run only CPU
3441 * model loading. CPU expansion can't run at instance_init-time
3442 * because host/accelerator data may be not available yet.
3443 * - CPU realization will perform both CPU model expansion and CPUID
3444 * filtering, and return an error in case one of them fails.
3445 * - query-cpu-definitions needs to run all 3 steps. It needs
3446 * to run CPUID filtering, as the 'unavailable-features'
3447 * field is set based on the filtering results.
3448 * - The query-cpu-model-expansion QMP command only needs to run
3449 * CPU model loading and CPU expansion. It should not filter
3450 * any CPUID data based on host capabilities.
3451 */
3452
3453/* Expand CPU configuration data, based on configured features
3454 * and host/accelerator capabilities when appropriate.
3455 */
3456static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 3457{
b34d12d1 3458 CPUX86State *env = &cpu->env;
dc15c051 3459 FeatureWord w;
2fae0d96 3460 GList *l;
41f3d4d6 3461 Error *local_err = NULL;
9886e834 3462
d4a606b3
EH		 3463 /*TODO: Now cpu->max_features doesn't overwrite features
3464 * set using QOM properties, and we can convert
dc15c051
IM		 3465 * plus_features & minus_features to global properties
3466 * inside x86_cpu_parse_featurestr() too.
3467 */
44bd8e53 3468 if (cpu->max_features) {
dc15c051 3469 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 3470 /* Override only features that weren't set explicitly
3471 * by the user.
3472 */
3473 env->features[w] |=
3474 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
3475 ~env->user_features[w];
dc15c051
IM		 3476 }
3477 }
3478
2fae0d96
EH		 3479 for (l = plus_features; l; l = l->next) {
3480 const char *prop = l->data;
3481 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
3482 if (local_err) {
3483 goto out;
3484 }
3485 }
3486
3487 for (l = minus_features; l; l = l->next) {
3488 const char *prop = l->data;
3489 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
3490 if (local_err) {
3491 goto out;
3492 }
dc15c051
IM		 3493 }
3494
aec661de
EH		 3495 if (!kvm_enabled() || !cpu->expose_kvm) {
3496 env->features[FEAT_KVM] = 0;
3497 }
3498
2ca8a8be 3499 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 3500
3501 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3502 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
3503 if (cpu->full_cpuid_auto_level) {
3504 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
3505 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
3506 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
3507 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
3508 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
3509 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
3510 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
3511 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
3512 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
3513 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 3514 /* SVM requires CPUID[0x8000000A] */
3515 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
3516 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
3517 }
c39c0edf
EH		 3518 }
3519
3520 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3521 if (env->cpuid_level == UINT32_MAX) {
3522 env->cpuid_level = env->cpuid_min_level;
3523 }
3524 if (env->cpuid_xlevel == UINT32_MAX) {
3525 env->cpuid_xlevel = env->cpuid_min_xlevel;
3526 }
3527 if (env->cpuid_xlevel2 == UINT32_MAX) {
3528 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 3529 }
7a059953 3530
41f3d4d6
EH		 3531out:
3532 if (local_err != NULL) {
3533 error_propagate(errp, local_err);
3534 }
3535}
3536
b8d834a0
EH		 3537/*
3538 * Finishes initialization of CPUID data, filters CPU feature
3539 * words based on host availability of each feature.
3540 *
3541 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
3542 */
3543static int x86_cpu_filter_features(X86CPU *cpu)
3544{
3545 CPUX86State *env = &cpu->env;
3546 FeatureWord w;
3547 int rv = 0;
3548
3549 for (w = 0; w < FEATURE_WORDS; w++) {
3550 uint32_t host_feat =
3551 x86_cpu_get_supported_feature_word(w, false);
3552 uint32_t requested_features = env->features[w];
3553 env->features[w] &= host_feat;
3554 cpu->filtered_features[w] = requested_features & ~env->features[w];
3555 if (cpu->filtered_features[w]) {
3556 rv = 1;
3557 }
3558 }
3559
3560 return rv;
3561}
3562
41f3d4d6
EH		 3563#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3564 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3565 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3566#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3567 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3568 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
3569static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
3570{
3571 CPUState *cs = CPU(dev);
3572 X86CPU *cpu = X86_CPU(dev);
3573 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3574 CPUX86State *env = &cpu->env;
3575 Error *local_err = NULL;
3576 static bool ht_warned;
3577
3578 if (xcc->kvm_required && !kvm_enabled()) {
3579 char *name = x86_cpu_class_get_model_name(xcc);
3580 error_setg(&local_err, "CPU model '%s' requires KVM", name);
3581 g_free(name);
3582 goto out;
3583 }
3584
3585 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
3586 error_setg(errp, "apic-id property was not initialized properly");
3587 return;
3588 }
3589
b8d834a0 3590 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 3591 if (local_err) {
3592 goto out;
3593 }
3594
8ca30e86
EH		 3595 if (x86_cpu_filter_features(cpu) &&
3596 (cpu->check_cpuid || cpu->enforce_cpuid)) {
3597 x86_cpu_report_filtered_features(cpu);
3598 if (cpu->enforce_cpuid) {
3599 error_setg(&local_err,
3600 kvm_enabled() ?
3601 "Host doesn't support requested features" :
3602 "TCG doesn't support requested features");
3603 goto out;
3604 }
9997cf7b
EH		 3605 }
3606
9b15cd9e
IM		 3607 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3608 * CPUID[1].EDX.
3609 */
e48638fd 3610 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 3611 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3612 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 3613 & CPUID_EXT2_AMD_ALIASES);
3614 }
3615
11f6fee5
DDAG		 3616 /* For 64bit systems think about the number of physical bits to present.
3617 * ideally this should be the same as the host; anything other than matching
3618 * the host can cause incorrect guest behaviour.
3619 * QEMU used to pick the magic value of 40 bits that corresponds to
3620 * consumer AMD devices but nothing else.
3621 */
af45907a 3622 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a 3623 if (kvm_enabled()) {
11f6fee5
DDAG		 3624 uint32_t host_phys_bits = x86_host_phys_bits();
3625 static bool warned;
3626
3627 if (cpu->host_phys_bits) {
3628 /* The user asked for us to use the host physical bits */
3629 cpu->phys_bits = host_phys_bits;
3630 }
3631
3632 /* Print a warning if the user set it to a value that's not the
3633 * host value.
3634 */
3635 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3636 !warned) {
3dc6f869
AF		 3637 warn_report("Host physical bits (%u)"
3638 " does not match phys-bits property (%u)",
3639 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 3640 warned = true;
3641 }
3642
3643 if (cpu->phys_bits &&
3644 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3645 cpu->phys_bits < 32)) {
af45907a
DDAG		 3646 error_setg(errp, "phys-bits should be between 32 and %u "
3647 " (but is %u)",
3648 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3649 return;
3650 }
3651 } else {
11f6fee5 3652 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 3653 error_setg(errp, "TCG only supports phys-bits=%u",
3654 TCG_PHYS_ADDR_BITS);
3655 return;
3656 }
3657 }
11f6fee5
DDAG		 3658 /* 0 means it was not explicitly set by the user (or by machine
3659 * compat_props or by the host code above). In this case, the default
3660 * is the value used by TCG (40).
3661 */
3662 if (cpu->phys_bits == 0) {
3663 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3664 }
af45907a
DDAG		 3665 } else {
3666 /* For 32 bit systems don't use the user set value, but keep
3667 * phys_bits consistent with what we tell the guest.
3668 */
3669 if (cpu->phys_bits != 0) {
3670 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3671 return;
3672 }
fefb41bf 3673
af45907a
DDAG		 3674 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3675 cpu->phys_bits = 36;
3676 } else {
3677 cpu->phys_bits = 32;
3678 }
3679 }
ce5b1bbf
LV		 3680 cpu_exec_realizefn(cs, &local_err);
3681 if (local_err != NULL) {
3682 error_propagate(errp, local_err);
3683 return;
3684 }
42ecabaa 3685
57f2453a
EH		 3686 if (tcg_enabled()) {
3687 tcg_x86_init();
3688 }
3689
65dee380
IM		 3690#ifndef CONFIG_USER_ONLY
3691 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 3692
0514ef2f 3693 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 3694 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 3695 if (local_err != NULL) {
4dc1f449 3696 goto out;
bdeec802
IM		 3697 }
3698 }
65dee380
IM		 3699#endif
3700
7a059953 3701 mce_init(cpu);
2001d0cd
PB		 3702
3703#ifndef CONFIG_USER_ONLY
3704 if (tcg_enabled()) {
f8c45c65
PB		 3705 AddressSpace *as_normal = address_space_init_shareable(cs->memory,
3706 "cpu-memory");
3707 AddressSpace *as_smm = g_new(AddressSpace, 1);
56943e8c 3708
f809c605 3709 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 3710 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 3711
3712 /* Outer container... */
3713 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 3714 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 3715
3716 /* ... with two regions inside: normal system memory with low
3717 * priority, and...
3718 */
3719 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3720 get_system_memory(), 0, ~0ull);
3721 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3722 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 3723 address_space_init(as_smm, cpu->cpu_as_root, "CPU");
3724
3725 cs->num_ases = 2;
3726 cpu_address_space_init(cs, as_normal, 0);
3727 cpu_address_space_init(cs, as_smm, 1);
f809c605
PB		 3728
3729 /* ... SMRAM with higher priority, linked from /machine/smram. */
3730 cpu->machine_done.notify = x86_cpu_machine_done;
3731 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 3732 }
3733#endif
3734
14a10fc3 3735 qemu_init_vcpu(cs);
d3c64d6a 3736
e48638fd
WH		 3737 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3738 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3739 * based on inputs (sockets,cores,threads), it is still better to gives
3740 * users a warning.
3741 *
3742 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3743 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3744 */
3745 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3746 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3747 " -smp options properly.");
3748 ht_warned = true;
3749 }
3750
d3c64d6a
IM		 3751 x86_cpu_apic_realize(cpu, &local_err);
3752 if (local_err != NULL) {
3753 goto out;
3754 }
14a10fc3 3755 cpu_reset(cs);
2b6f294c 3756
4dc1f449 3757 xcc->parent_realize(dev, &local_err);
2001d0cd 3758
4dc1f449
IM		 3759out:
3760 if (local_err != NULL) {
3761 error_propagate(errp, local_err);
3762 return;
3763 }
7a059953
AF		 3764}
3765
c884776e
IM		 3766static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3767{
3768 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 3769 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3770 Error *local_err = NULL;
c884776e
IM		 3771
3772#ifndef CONFIG_USER_ONLY
3773 cpu_remove_sync(CPU(dev));
3774 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3775#endif
3776
3777 if (cpu->apic_state) {
3778 object_unparent(OBJECT(cpu->apic_state));
3779 cpu->apic_state = NULL;
3780 }
7bbc124e
LV		 3781
3782 xcc->parent_unrealize(dev, &local_err);
3783 if (local_err != NULL) {
3784 error_propagate(errp, local_err);
3785 return;
3786 }
c884776e
IM		 3787}
3788
38e5c119 3789typedef struct BitProperty {
a7b0ffac 3790 FeatureWord w;
38e5c119
EH		 3791 uint32_t mask;
3792} BitProperty;
3793
d7bce999
EB		 3794static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3795 void *opaque, Error **errp)
38e5c119 3796{
a7b0ffac 3797 X86CPU *cpu = X86_CPU(obj);
38e5c119 3798 BitProperty *fp = opaque;
a7b0ffac
EH		 3799 uint32_t f = cpu->env.features[fp->w];
3800 bool value = (f & fp->mask) == fp->mask;
51e72bc1 3801 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3802}
3803
d7bce999
EB		 3804static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3805 void *opaque, Error **errp)
38e5c119
EH		 3806{
3807 DeviceState *dev = DEVICE(obj);
a7b0ffac 3808 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 3809 BitProperty *fp = opaque;
3810 Error *local_err = NULL;
3811 bool value;
3812
3813 if (dev->realized) {
3814 qdev_prop_set_after_realize(dev, name, errp);
3815 return;
3816 }
3817
51e72bc1 3818 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3819 if (local_err) {
3820 error_propagate(errp, local_err);
3821 return;
3822 }
3823
3824 if (value) {
a7b0ffac 3825 cpu->env.features[fp->w] |= fp->mask;
38e5c119 3826 } else {
a7b0ffac 3827 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 3828 }
d4a606b3 3829 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 3830}
3831
3832static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3833 void *opaque)
3834{
3835 BitProperty *prop = opaque;
3836 g_free(prop);
3837}
3838
3839/* Register a boolean property to get/set a single bit in a uint32_t field.
3840 *
3841 * The same property name can be registered multiple times to make it affect
3842 * multiple bits in the same FeatureWord. In that case, the getter will return
3843 * true only if all bits are set.
3844 */
3845static void x86_cpu_register_bit_prop(X86CPU *cpu,
3846 const char *prop_name,
a7b0ffac 3847 FeatureWord w,
38e5c119
EH		 3848 int bitnr)
3849{
3850 BitProperty *fp;
3851 ObjectProperty *op;
3852 uint32_t mask = (1UL << bitnr);
3853
3854 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3855 if (op) {
3856 fp = op->opaque;
a7b0ffac 3857 assert(fp->w == w);
38e5c119
EH		 3858 fp->mask |= mask;
3859 } else {
3860 fp = g_new0(BitProperty, 1);
a7b0ffac 3861 fp->w = w;
38e5c119
EH		 3862 fp->mask = mask;
3863 object_property_add(OBJECT(cpu), prop_name, "bool",
3864 x86_cpu_get_bit_prop,
3865 x86_cpu_set_bit_prop,
3866 x86_cpu_release_bit_prop, fp, &error_abort);
3867 }
3868}
3869
3870static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3871 FeatureWord w,
3872 int bitnr)
3873{
38e5c119 3874 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 3875 const char *name = fi->feat_names[bitnr];
38e5c119 3876
16d2fcaa 3877 if (!name) {
38e5c119
EH		 3878 return;
3879 }
3880
fc7dfd20
EH		 3881 /* Property names should use "-" instead of "_".
3882 * Old names containing underscores are registered as aliases
3883 * using object_property_add_alias()
3884 */
16d2fcaa
EH		 3885 assert(!strchr(name, '_'));
3886 /* aliases don't use "|" delimiters anymore, they are registered
3887 * manually using object_property_add_alias() */
3888 assert(!strchr(name, '|'));
a7b0ffac 3889 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 3890}
3891
d187e08d
AN		 3892static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
3893{
3894 X86CPU *cpu = X86_CPU(cs);
3895 CPUX86State *env = &cpu->env;
3896 GuestPanicInformation *panic_info = NULL;
3897
3898 if (env->features[FEAT_HYPERV_EDX] & HV_X64_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 3899 panic_info = g_malloc0(sizeof(GuestPanicInformation));
3900
e8ed97a6 3901 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d
AN		 3902
3903 assert(HV_X64_MSR_CRASH_PARAMS >= 5);
e8ed97a6
AN		 3904 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
3905 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
3906 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
3907 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
3908 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 3909 }
3910
3911 return panic_info;
3912}
3913static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
3914 const char *name, void *opaque,
3915 Error **errp)
3916{
3917 CPUState *cs = CPU(obj);
3918 GuestPanicInformation *panic_info;
3919
3920 if (!cs->crash_occurred) {
3921 error_setg(errp, "No crash occured");
3922 return;
3923 }
3924
3925 panic_info = x86_cpu_get_crash_info(cs);
3926 if (panic_info == NULL) {
3927 error_setg(errp, "No crash information");
3928 return;
3929 }
3930
3931 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
3932 errp);
3933 qapi_free_GuestPanicInformation(panic_info);
3934}
3935
de024815
AF		 3936static void x86_cpu_initfn(Object *obj)
3937{
55e5c285 3938 CPUState *cs = CPU(obj);
de024815 3939 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3940 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3941 CPUX86State *env = &cpu->env;
38e5c119 3942 FeatureWord w;
de024815 3943
c05efcb1 3944 cs->env_ptr = env;
71ad61d3
AF		 3945
3946 object_property_add(obj, "family", "int",
95b8519d 3947 x86_cpuid_version_get_family,
71ad61d3 3948 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3949 object_property_add(obj, "model", "int",
67e30c83 3950 x86_cpuid_version_get_model,
c5291a4f 3951 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3952 object_property_add(obj, "stepping", "int",
35112e41 3953 x86_cpuid_version_get_stepping,
036e2222 3954 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3955 object_property_add_str(obj, "vendor",
3956 x86_cpuid_get_vendor,
3957 x86_cpuid_set_vendor, NULL);
938d4c25 3958 object_property_add_str(obj, "model-id",
63e886eb 3959 x86_cpuid_get_model_id,
938d4c25 3960 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3961 object_property_add(obj, "tsc-frequency", "int",
3962 x86_cpuid_get_tsc_freq,
3963 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 3964 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3965 x86_cpu_get_feature_words,
7e5292b5
EH		 3966 NULL, NULL, (void *)env->features, NULL);
3967 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3968 x86_cpu_get_feature_words,
3969 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3970
d187e08d
AN		 3971 object_property_add(obj, "crash-information", "GuestPanicInformation",
3972 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
3973
92067bf4 3974 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3975
38e5c119
EH		 3976 for (w = 0; w < FEATURE_WORDS; w++) {
3977 int bitnr;
3978
3979 for (bitnr = 0; bitnr < 32; bitnr++) {
3980 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3981 }
3982 }
3983
16d2fcaa
EH		 3984 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
3985 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
3986 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
3987 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
3988 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
3989 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
3990 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
3991
54b8dc7c
EH		 3992 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
3993 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
3994 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
3995 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
3996 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
3997 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
3998 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
3999 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
4000 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
4001 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
4002 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
4003 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
4004 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
4005 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
4006 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
4007 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
4008 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
4009 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
4010 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
4011 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
4012 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
4013
0bacd8b3
EH		 4014 if (xcc->cpu_def) {
4015 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
4016 }
de024815
AF		 4017}
4018
997395d3
IM		 4019static int64_t x86_cpu_get_arch_id(CPUState *cs)
4020{
4021 X86CPU *cpu = X86_CPU(cs);
997395d3 4022
7e72a45c 4023 return cpu->apic_id;
997395d3
IM		 4024}
4025
444d5590
AF		 4026static bool x86_cpu_get_paging_enabled(const CPUState *cs)
4027{
4028 X86CPU *cpu = X86_CPU(cs);
4029
4030 return cpu->env.cr[0] & CR0_PG_MASK;
4031}
4032
f45748f1
AF		 4033static void x86_cpu_set_pc(CPUState *cs, vaddr value)
4034{
4035 X86CPU *cpu = X86_CPU(cs);
4036
4037 cpu->env.eip = value;
4038}
4039
bdf7ae5b
AF		 4040static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
4041{
4042 X86CPU *cpu = X86_CPU(cs);
4043
4044 cpu->env.eip = tb->pc - tb->cs_base;
4045}
4046
8c2e1b00
AF		 4047static bool x86_cpu_has_work(CPUState *cs)
4048{
4049 X86CPU *cpu = X86_CPU(cs);
4050 CPUX86State *env = &cpu->env;
4051
6220e900
PD		 4052 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
4053 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 4054 (env->eflags & IF_MASK)) ||
4055 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
4056 CPU_INTERRUPT_INIT |
4057 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 4058 CPU_INTERRUPT_MCE)) ||
4059 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
4060 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 4061}
4062
9337e3b6 4063static Property x86_cpu_properties[] = {
2da00e31
IM		 4064#ifdef CONFIG_USER_ONLY
4065 /* apic_id = 0 by default for *-user, see commit 9886e834 */
4066 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 4067 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
4068 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
4069 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 4070#else
4071 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 4072 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
4073 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
4074 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 4075#endif
15f8b142 4076 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 4077 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 4078 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 4079 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 4080 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 4081 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 4082 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 4083 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 4084 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 4085 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 4086 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 4087 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 4088 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 4089 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 4090 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 4091 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 4092 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 4093 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 4094 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
4095 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
4096 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
4097 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
4098 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
4099 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4100 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 4101 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 4102 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 4103 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 4104 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 4105 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
4106 false),
0b564e6f 4107 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 4108 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
9337e3b6
EH		 4109 DEFINE_PROP_END_OF_LIST()
4110};
4111
5fd2087a
AF		 4112static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
4113{
4114 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4115 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 4116 DeviceClass *dc = DEVICE_CLASS(oc);
4117
4118 xcc->parent_realize = dc->realize;
7bbc124e 4119 xcc->parent_unrealize = dc->unrealize;
2b6f294c 4120 dc->realize = x86_cpu_realizefn;
c884776e 4121 dc->unrealize = x86_cpu_unrealizefn;
9337e3b6 4122 dc->props = x86_cpu_properties;
5fd2087a
AF		 4123
4124 xcc->parent_reset = cc->reset;
4125 cc->reset = x86_cpu_reset;
91b1df8c 4126 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 4127
500050d1 4128 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 4129 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 4130 cc->has_work = x86_cpu_has_work;
79c664f6 4131#ifdef CONFIG_TCG
97a8ea5a 4132 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 4133 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 4134#endif
878096ee 4135 cc->dump_state = x86_cpu_dump_state;
c86f106b 4136 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 4137 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 4138 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 4139 cc->gdb_read_register = x86_cpu_gdb_read_register;
4140 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 4141 cc->get_arch_id = x86_cpu_get_arch_id;
4142 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 4143#ifdef CONFIG_USER_ONLY
4144 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
4145#else
f8c45c65 4146 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 4147 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 4148 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 4149 cc->write_elf64_note = x86_cpu_write_elf64_note;
4150 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
4151 cc->write_elf32_note = x86_cpu_write_elf32_note;
4152 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 4153 cc->vmsd = &vmstate_x86_cpu;
c72bf468 4154#endif
00fcd100
AB		 4155 cc->gdb_arch_name = x86_gdb_arch_name;
4156#ifdef TARGET_X86_64
b8158192
AB		 4157 cc->gdb_core_xml_file = "i386-64bit.xml";
4158 cc->gdb_num_core_regs = 57;
00fcd100 4159#else
b8158192
AB		 4160 cc->gdb_core_xml_file = "i386-32bit.xml";
4161 cc->gdb_num_core_regs = 41;
00fcd100 4162#endif
79c664f6 4163#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 4164 cc->debug_excp_handler = breakpoint_handler;
4165#endif
374e0cd4
RH		 4166 cc->cpu_exec_enter = x86_cpu_exec_enter;
4167 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27 4168
e90f2a8c 4169 dc->user_creatable = true;
5fd2087a
AF		 4170}
4171
4172static const TypeInfo x86_cpu_type_info = {
4173 .name = TYPE_X86_CPU,
4174 .parent = TYPE_CPU,
4175 .instance_size = sizeof(X86CPU),
de024815 4176 .instance_init = x86_cpu_initfn,
d940ee9b 4177 .abstract = true,
5fd2087a
AF		 4178 .class_size = sizeof(X86CPUClass),
4179 .class_init = x86_cpu_common_class_init,
4180};
4181
5adbed30
EH		 4182
4183/* "base" CPU model, used by query-cpu-model-expansion */
4184static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
4185{
4186 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4187
4188 xcc->static_model = true;
4189 xcc->migration_safe = true;
4190 xcc->model_description = "base CPU model type with no features enabled";
4191 xcc->ordering = 8;
4192}
4193
4194static const TypeInfo x86_base_cpu_type_info = {
4195 .name = X86_CPU_TYPE_NAME("base"),
4196 .parent = TYPE_X86_CPU,
4197 .class_init = x86_cpu_base_class_init,
4198};
4199
5fd2087a
AF		 4200static void x86_cpu_register_types(void)
4201{
d940ee9b
EH		 4202 int i;
4203
5fd2087a 4204 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 4205 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
4206 x86_register_cpudef_type(&builtin_x86_defs[i]);
4207 }
c62f2630 4208 type_register_static(&max_x86_cpu_type_info);
5adbed30 4209 type_register_static(&x86_base_cpu_type_info);
d940ee9b
EH		 4210#ifdef CONFIG_KVM
4211 type_register_static(&host_x86_cpu_type_info);
4212#endif
5fd2087a
AF		 4213}
4214
4215type_init(x86_cpu_register_types)
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