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i386: Add FEAT_8000_0008_EBX CPUID feature word
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
d6dcc558 25#include "sysemu/hvf.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
c6dc6f63 28
d49b6836 29#include "qemu/error-report.h"
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
01b2ffce 33#include "qapi/qmp/types.h"
c6dc6f63 34
8e8aba50
EH		 35#include "qapi-types.h"
36#include "qapi-visit.h"
7b1b5d19 37#include "qapi/visitor.h"
f99fd7ca 38#include "qom/qom-qobject.h"
9c17d615 39#include "sysemu/arch_init.h"
71ad61d3 40
b834b508 41#if defined(CONFIG_KVM)
ef8621b1 42#include <linux/kvm_para.h>
b834b508 43#endif
65dee380 44
9c17d615 45#include "sysemu/sysemu.h"
53a89e26 46#include "hw/qdev-properties.h"
5232d00a 47#include "hw/i386/topology.h"
bdeec802 48#ifndef CONFIG_USER_ONLY
2001d0cd 49#include "exec/address-spaces.h"
741da0d3 50#include "hw/hw.h"
0d09e41a 51#include "hw/xen/xen.h"
0d09e41a 52#include "hw/i386/apic_internal.h"
bdeec802
IM		 53#endif
54
b666d2a4
RH		 55#include "disas/capstone.h"
56
5e891bf8
EH		 57
58/* Cache topology CPUID constants: */
59
60/* CPUID Leaf 2 Descriptors */
61
62#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
63#define CPUID_2_L1I_32KB_8WAY_64B 0x30
64#define CPUID_2_L2_2MB_8WAY_64B 0x7d
14c985cf 65#define CPUID_2_L3_16MB_16WAY_64B 0x4d
5e891bf8
EH		 66
67
68/* CPUID Leaf 4 constants: */
69
70/* EAX: */
71#define CPUID_4_TYPE_DCACHE 1
72#define CPUID_4_TYPE_ICACHE 2
73#define CPUID_4_TYPE_UNIFIED 3
74
75#define CPUID_4_LEVEL(l) ((l) << 5)
76
77#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
78#define CPUID_4_FULLY_ASSOC (1 << 9)
79
80/* EDX: */
81#define CPUID_4_NO_INVD_SHARING (1 << 0)
82#define CPUID_4_INCLUSIVE (1 << 1)
83#define CPUID_4_COMPLEX_IDX (1 << 2)
84
85#define ASSOC_FULL 0xFF
86
87/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
88#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
89 a == 2 ? 0x2 : \
90 a == 4 ? 0x4 : \
91 a == 8 ? 0x6 : \
92 a == 16 ? 0x8 : \
93 a == 32 ? 0xA : \
94 a == 48 ? 0xB : \
95 a == 64 ? 0xC : \
96 a == 96 ? 0xD : \
97 a == 128 ? 0xE : \
98 a == ASSOC_FULL ? 0xF : \
99 0 /* invalid value */)
100
101
102/* Definitions of the hardcoded cache entries we expose: */
103
104/* L1 data cache: */
105#define L1D_LINE_SIZE 64
106#define L1D_ASSOCIATIVITY 8
107#define L1D_SETS 64
108#define L1D_PARTITIONS 1
109/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
110#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
111/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
112#define L1D_LINES_PER_TAG 1
113#define L1D_SIZE_KB_AMD 64
114#define L1D_ASSOCIATIVITY_AMD 2
115
116/* L1 instruction cache: */
117#define L1I_LINE_SIZE 64
118#define L1I_ASSOCIATIVITY 8
119#define L1I_SETS 64
120#define L1I_PARTITIONS 1
121/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
122#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
123/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
124#define L1I_LINES_PER_TAG 1
125#define L1I_SIZE_KB_AMD 64
126#define L1I_ASSOCIATIVITY_AMD 2
127
128/* Level 2 unified cache: */
129#define L2_LINE_SIZE 64
130#define L2_ASSOCIATIVITY 16
131#define L2_SETS 4096
132#define L2_PARTITIONS 1
133/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
134/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
135#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
136/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
137#define L2_LINES_PER_TAG 1
138#define L2_SIZE_KB_AMD 512
139
14c985cf 140/* Level 3 unified cache: */
5e891bf8
EH		 141#define L3_SIZE_KB 0 /* disabled */
142#define L3_ASSOCIATIVITY 0 /* disabled */
143#define L3_LINES_PER_TAG 0 /* disabled */
144#define L3_LINE_SIZE 0 /* disabled */
14c985cf
LM		 145#define L3_N_LINE_SIZE 64
146#define L3_N_ASSOCIATIVITY 16
147#define L3_N_SETS 16384
148#define L3_N_PARTITIONS 1
149#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
150#define L3_N_LINES_PER_TAG 1
151#define L3_N_SIZE_KB_AMD 16384
5e891bf8
EH		 152
153/* TLB definitions: */
154
155#define L1_DTLB_2M_ASSOC 1
156#define L1_DTLB_2M_ENTRIES 255
157#define L1_DTLB_4K_ASSOC 1
158#define L1_DTLB_4K_ENTRIES 255
159
160#define L1_ITLB_2M_ASSOC 1
161#define L1_ITLB_2M_ENTRIES 255
162#define L1_ITLB_4K_ASSOC 1
163#define L1_ITLB_4K_ENTRIES 255
164
165#define L2_DTLB_2M_ASSOC 0 /* disabled */
166#define L2_DTLB_2M_ENTRIES 0 /* disabled */
167#define L2_DTLB_4K_ASSOC 4
168#define L2_DTLB_4K_ENTRIES 512
169
170#define L2_ITLB_2M_ASSOC 0 /* disabled */
171#define L2_ITLB_2M_ENTRIES 0 /* disabled */
172#define L2_ITLB_4K_ASSOC 4
173#define L2_ITLB_4K_ENTRIES 512
174
175
176
99b88a17
IM		 177static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
178 uint32_t vendor2, uint32_t vendor3)
179{
180 int i;
181 for (i = 0; i < 4; i++) {
182 dst[i] = vendor1 >> (8 * i);
183 dst[i + 4] = vendor2 >> (8 * i);
184 dst[i + 8] = vendor3 >> (8 * i);
185 }
186 dst[CPUID_VENDOR_SZ] = '\0';
187}
188
621626ce
EH		 189#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
190#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
191 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
192#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
193 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
194 CPUID_PSE36 | CPUID_FXSR)
195#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
196#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
197 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
198 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
199 CPUID_PAE | CPUID_SEP | CPUID_APIC)
200
201#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
202 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
203 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
204 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 205 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 206 /* partly implemented:
207 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
208 /* missing:
209 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
210#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
211 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
212 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 213 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 214 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
215 /* missing:
216 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
217 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
218 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 219 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
220 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 221
222#ifdef TARGET_X86_64
223#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
224#else
225#define TCG_EXT2_X86_64_FEATURES 0
226#endif
227
228#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
229 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
230 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
231 TCG_EXT2_X86_64_FEATURES)
232#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
233 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
234#define TCG_EXT4_FEATURES 0
235#define TCG_SVM_FEATURES 0
236#define TCG_KVM_FEATURES 0
237#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 238 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
239 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 240 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
241 CPUID_7_0_EBX_ERMS)
621626ce 242 /* missing:
07929f2a 243 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 244 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 245 CPUID_7_0_EBX_RDSEED */
6c7c3c21
KS		 246#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
247 CPUID_7_0_ECX_LA57)
95ea69fb 248#define TCG_7_0_EDX_FEATURES 0
303752a9 249#define TCG_APM_FEATURES 0
28b8e4d0 250#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 251#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
252 /* missing:
253 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 254
5ef57876 255typedef struct FeatureWordInfo {
2d5312da
EH		 256 /* feature flags names are taken from "Intel Processor Identification and
257 * the CPUID Instruction" and AMD's "CPUID Specification".
258 * In cases of disagreement between feature naming conventions,
259 * aliases may be added.
260 */
261 const char *feat_names[32];
04d104b6
EH		 262 uint32_t cpuid_eax; /* Input EAX for CPUID */
263 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
264 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
265 int cpuid_reg; /* output register (R_* constant) */
37ce3522 266 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 267 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 268 uint32_t migratable_flags; /* Feature flags known to be migratable */
5ef57876
EH		 269} FeatureWordInfo;
270
271static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 272 [FEAT_1_EDX] = {
2d5312da
EH		 273 .feat_names = {
274 "fpu", "vme", "de", "pse",
275 "tsc", "msr", "pae", "mce",
276 "cx8", "apic", NULL, "sep",
277 "mtrr", "pge", "mca", "cmov",
278 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
279 NULL, "ds" /* Intel dts */, "acpi", "mmx",
280 "fxsr", "sse", "sse2", "ss",
281 "ht" /* Intel htt */, "tm", "ia64", "pbe",
282 },
bffd67b0 283 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 284 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 285 },
286 [FEAT_1_ECX] = {
2d5312da 287 .feat_names = {
16d2fcaa 288 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 289 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 290 "tm2", "ssse3", "cid", NULL,
291 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 292 NULL, "pcid", "dca", "sse4.1",
293 "sse4.2", "x2apic", "movbe", "popcnt",
2d5312da
EH		 294 "tsc-deadline", "aes", "xsave", "osxsave",
295 "avx", "f16c", "rdrand", "hypervisor",
296 },
bffd67b0 297 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 298 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 299 },
2d5312da
EH		 300 /* Feature names that are already defined on feature_name[] but
301 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
302 * names on feat_names below. They are copied automatically
303 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
304 */
bffd67b0 305 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 306 .feat_names = {
307 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
308 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
309 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
310 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
311 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 312 "nx", NULL, "mmxext", NULL /* mmx */,
313 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
314 NULL, "lm", "3dnowext", "3dnow",
2d5312da 315 },
bffd67b0 316 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 317 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 318 },
319 [FEAT_8000_0001_ECX] = {
2d5312da 320 .feat_names = {
fc7dfd20 321 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 322 "cr8legacy", "abm", "sse4a", "misalignsse",
323 "3dnowprefetch", "osvw", "ibs", "xop",
324 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 325 "fma4", "tce", NULL, "nodeid-msr",
326 NULL, "tbm", "topoext", "perfctr-core",
327 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 328 NULL, NULL, NULL, NULL,
329 },
bffd67b0 330 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 331 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 332 },
89e49c8b 333 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 334 .feat_names = {
335 NULL, NULL, "xstore", "xstore-en",
336 NULL, NULL, "xcrypt", "xcrypt-en",
337 "ace2", "ace2-en", "phe", "phe-en",
338 "pmm", "pmm-en", NULL, NULL,
339 NULL, NULL, NULL, NULL,
340 NULL, NULL, NULL, NULL,
341 NULL, NULL, NULL, NULL,
342 NULL, NULL, NULL, NULL,
343 },
89e49c8b 344 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 345 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 346 },
bffd67b0 347 [FEAT_KVM] = {
2d5312da 348 .feat_names = {
fc7dfd20
EH		 349 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
350 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
6976af66 351 NULL, "kvm-pv-tlb-flush", NULL, NULL,
2d5312da
EH		 352 NULL, NULL, NULL, NULL,
353 NULL, NULL, NULL, NULL,
354 NULL, NULL, NULL, NULL,
355 "kvmclock-stable-bit", NULL, NULL, NULL,
356 NULL, NULL, NULL, NULL,
357 },
bffd67b0 358 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 359 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 360 },
c35bd19a 361 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 362 .feat_names = {
363 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
364 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
365 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
366 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
367 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
368 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
369 NULL, NULL, NULL, NULL,
370 NULL, NULL, NULL, NULL,
371 NULL, NULL, NULL, NULL,
372 NULL, NULL, NULL, NULL,
373 NULL, NULL, NULL, NULL,
374 },
c35bd19a
EY		 375 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
376 },
377 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 378 .feat_names = {
379 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
380 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
381 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
382 NULL /* hv_create_port */, NULL /* hv_connect_port */,
383 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
384 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
385 NULL, NULL,
386 NULL, NULL, NULL, NULL,
387 NULL, NULL, NULL, NULL,
388 NULL, NULL, NULL, NULL,
389 NULL, NULL, NULL, NULL,
390 },
c35bd19a
EY		 391 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
392 },
393 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 394 .feat_names = {
395 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
396 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
397 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
398 NULL, NULL,
399 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
400 NULL, NULL, NULL, NULL,
401 NULL, NULL, NULL, NULL,
402 NULL, NULL, NULL, NULL,
403 NULL, NULL, NULL, NULL,
404 NULL, NULL, NULL, NULL,
405 },
c35bd19a
EY		 406 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
407 },
bffd67b0 408 [FEAT_SVM] = {
2d5312da 409 .feat_names = {
fc7dfd20
EH		 410 "npt", "lbrv", "svm-lock", "nrip-save",
411 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
412 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 413 "pfthreshold", NULL, NULL, NULL,
414 NULL, NULL, NULL, NULL,
415 NULL, NULL, NULL, NULL,
416 NULL, NULL, NULL, NULL,
417 NULL, NULL, NULL, NULL,
418 },
bffd67b0 419 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 420 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 421 },
422 [FEAT_7_0_EBX] = {
2d5312da 423 .feat_names = {
fc7dfd20 424 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 425 "hle", "avx2", NULL, "smep",
426 "bmi2", "erms", "invpcid", "rtm",
427 NULL, NULL, "mpx", NULL,
428 "avx512f", "avx512dq", "rdseed", "adx",
429 "smap", "avx512ifma", "pcommit", "clflushopt",
430 "clwb", NULL, "avx512pf", "avx512er",
638cbd45 431 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 432 },
04d104b6
EH		 433 .cpuid_eax = 7,
434 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
435 .cpuid_reg = R_EBX,
37ce3522 436 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 437 },
f74eefe0 438 [FEAT_7_0_ECX] = {
2d5312da
EH		 439 .feat_names = {
440 NULL, "avx512vbmi", "umip", "pku",
aff9e6e4
YZ		 441 "ospke", NULL, "avx512vbmi2", NULL,
442 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
443 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 444 "la57", NULL, NULL, NULL,
2d5312da
EH		 445 NULL, NULL, "rdpid", NULL,
446 NULL, NULL, NULL, NULL,
447 NULL, NULL, NULL, NULL,
448 },
f74eefe0
HH		 449 .cpuid_eax = 7,
450 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
451 .cpuid_reg = R_ECX,
452 .tcg_features = TCG_7_0_ECX_FEATURES,
453 },
95ea69fb
LK		 454 [FEAT_7_0_EDX] = {
455 .feat_names = {
456 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
457 NULL, NULL, NULL, NULL,
458 NULL, NULL, NULL, NULL,
459 NULL, NULL, NULL, NULL,
460 NULL, NULL, NULL, NULL,
461 NULL, NULL, NULL, NULL,
a2381f09 462 NULL, NULL, "spec-ctrl", NULL,
95ea69fb
LK		 463 NULL, NULL, NULL, NULL,
464 },
465 .cpuid_eax = 7,
466 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
467 .cpuid_reg = R_EDX,
468 .tcg_features = TCG_7_0_EDX_FEATURES,
469 },
303752a9 470 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 471 .feat_names = {
472 NULL, NULL, NULL, NULL,
473 NULL, NULL, NULL, NULL,
474 "invtsc", NULL, NULL, NULL,
475 NULL, NULL, NULL, NULL,
476 NULL, NULL, NULL, NULL,
477 NULL, NULL, NULL, NULL,
478 NULL, NULL, NULL, NULL,
479 NULL, NULL, NULL, NULL,
480 },
303752a9
MT		 481 .cpuid_eax = 0x80000007,
482 .cpuid_reg = R_EDX,
483 .tcg_features = TCG_APM_FEATURES,
484 .unmigratable_flags = CPUID_APM_INVTSC,
485 },
1b3420e1
EH		 486 [FEAT_8000_0008_EBX] = {
487 .feat_names = {
488 NULL, NULL, NULL, NULL,
489 NULL, NULL, NULL, NULL,
490 NULL, NULL, NULL, NULL,
491 "ibpb", NULL, NULL, NULL,
492 NULL, NULL, NULL, NULL,
493 NULL, NULL, NULL, NULL,
494 NULL, NULL, NULL, NULL,
495 NULL, NULL, NULL, NULL,
496 },
497 .cpuid_eax = 0x80000008,
498 .cpuid_reg = R_EBX,
499 .tcg_features = 0,
500 .unmigratable_flags = 0,
501 },
0bb0b2d2 502 [FEAT_XSAVE] = {
2d5312da
EH		 503 .feat_names = {
504 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
505 NULL, NULL, NULL, NULL,
506 NULL, NULL, NULL, NULL,
507 NULL, NULL, NULL, NULL,
508 NULL, NULL, NULL, NULL,
509 NULL, NULL, NULL, NULL,
510 NULL, NULL, NULL, NULL,
511 NULL, NULL, NULL, NULL,
512 },
0bb0b2d2
PB		 513 .cpuid_eax = 0xd,
514 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
515 .cpuid_reg = R_EAX,
c9cfe8f9 516 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 517 },
28b8e4d0 518 [FEAT_6_EAX] = {
2d5312da
EH		 519 .feat_names = {
520 NULL, NULL, "arat", NULL,
521 NULL, NULL, NULL, NULL,
522 NULL, NULL, NULL, NULL,
523 NULL, NULL, NULL, NULL,
524 NULL, NULL, NULL, NULL,
525 NULL, NULL, NULL, NULL,
526 NULL, NULL, NULL, NULL,
527 NULL, NULL, NULL, NULL,
528 },
28b8e4d0
JK		 529 .cpuid_eax = 6, .cpuid_reg = R_EAX,
530 .tcg_features = TCG_6_EAX_FEATURES,
531 },
96193c22
EH		 532 [FEAT_XSAVE_COMP_LO] = {
533 .cpuid_eax = 0xD,
534 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
535 .cpuid_reg = R_EAX,
536 .tcg_features = ~0U,
6fb2fff7
EH		 537 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
538 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
539 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
540 XSTATE_PKRU_MASK,
96193c22
EH		 541 },
542 [FEAT_XSAVE_COMP_HI] = {
543 .cpuid_eax = 0xD,
544 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
545 .cpuid_reg = R_EDX,
546 .tcg_features = ~0U,
547 },
5ef57876
EH		 548};
549
8e8aba50
EH		 550typedef struct X86RegisterInfo32 {
551 /* Name of register */
552 const char *name;
553 /* QAPI enum value register */
554 X86CPURegister32 qapi_enum;
555} X86RegisterInfo32;
556
557#define REGISTER(reg) \
5d371f41 558 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 559static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 560 REGISTER(EAX),
561 REGISTER(ECX),
562 REGISTER(EDX),
563 REGISTER(EBX),
564 REGISTER(ESP),
565 REGISTER(EBP),
566 REGISTER(ESI),
567 REGISTER(EDI),
568};
569#undef REGISTER
570
3f32bd21
RH		 571typedef struct ExtSaveArea {
572 uint32_t feature, bits;
573 uint32_t offset, size;
574} ExtSaveArea;
575
576static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 577 [XSTATE_FP_BIT] = {
578 /* x87 FP state component is always enabled if XSAVE is supported */
579 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
580 /* x87 state is in the legacy region of the XSAVE area */
581 .offset = 0,
582 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
583 },
584 [XSTATE_SSE_BIT] = {
585 /* SSE state component is always enabled if XSAVE is supported */
586 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
587 /* SSE state is in the legacy region of the XSAVE area */
588 .offset = 0,
589 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
590 },
cfc3b074
PB		 591 [XSTATE_YMM_BIT] =
592 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 593 .offset = offsetof(X86XSaveArea, avx_state),
594 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 595 [XSTATE_BNDREGS_BIT] =
596 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 597 .offset = offsetof(X86XSaveArea, bndreg_state),
598 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 599 [XSTATE_BNDCSR_BIT] =
600 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 601 .offset = offsetof(X86XSaveArea, bndcsr_state),
602 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 603 [XSTATE_OPMASK_BIT] =
604 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 605 .offset = offsetof(X86XSaveArea, opmask_state),
606 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 607 [XSTATE_ZMM_Hi256_BIT] =
608 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 609 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
610 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 611 [XSTATE_Hi16_ZMM_BIT] =
612 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 613 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
614 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 615 [XSTATE_PKRU_BIT] =
616 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 617 .offset = offsetof(X86XSaveArea, pkru_state),
618 .size = sizeof(XSavePKRU) },
2560f19f 619};
8e8aba50 620
1fda6198
EH		 621static uint32_t xsave_area_size(uint64_t mask)
622{
623 int i;
e3c9022b 624 uint64_t ret = 0;
1fda6198 625
e3c9022b 626 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 627 const ExtSaveArea *esa = &x86_ext_save_areas[i];
628 if ((mask >> i) & 1) {
629 ret = MAX(ret, esa->offset + esa->size);
630 }
631 }
632 return ret;
633}
634
d6dcc558
SAGDR		 635static inline bool accel_uses_host_cpuid(void)
636{
637 return kvm_enabled() || hvf_enabled();
638}
639
96193c22
EH		 640static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
641{
642 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
643 cpu->env.features[FEAT_XSAVE_COMP_LO];
644}
645
8b4beddc
EH		 646const char *get_register_name_32(unsigned int reg)
647{
31ccdde2 648 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 649 return NULL;
650 }
8e8aba50 651 return x86_reg_info_32[reg].name;
8b4beddc
EH		 652}
653
84f1b92f
EH		 654/*
655 * Returns the set of feature flags that are supported and migratable by
656 * QEMU, for a given FeatureWord.
657 */
658static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
659{
660 FeatureWordInfo *wi = &feature_word_info[w];
661 uint32_t r = 0;
662 int i;
663
664 for (i = 0; i < 32; i++) {
665 uint32_t f = 1U << i;
6fb2fff7
EH		 666
667 /* If the feature name is known, it is implicitly considered migratable,
668 * unless it is explicitly set in unmigratable_flags */
669 if ((wi->migratable_flags & f) ||
670 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
671 r |= f;
84f1b92f 672 }
84f1b92f
EH		 673 }
674 return r;
675}
676
bb44e0d1
JK		 677void host_cpuid(uint32_t function, uint32_t count,
678 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 679{
a1fd24af
AL		 680 uint32_t vec[4];
681
682#ifdef __x86_64__
683 asm volatile("cpuid"
684 : "=a"(vec[0]), "=b"(vec[1]),
685 "=c"(vec[2]), "=d"(vec[3])
686 : "0"(function), "c"(count) : "cc");
c1f41226 687#elif defined(__i386__)
a1fd24af
AL		 688 asm volatile("pusha \n\t"
689 "cpuid \n\t"
690 "mov %%eax, 0(%2) \n\t"
691 "mov %%ebx, 4(%2) \n\t"
692 "mov %%ecx, 8(%2) \n\t"
693 "mov %%edx, 12(%2) \n\t"
694 "popa"
695 : : "a"(function), "c"(count), "S"(vec)
696 : "memory", "cc");
c1f41226
EH		 697#else
698 abort();
a1fd24af
AL		 699#endif
700
bdde476a 701 if (eax)
a1fd24af 702 *eax = vec[0];
bdde476a 703 if (ebx)
a1fd24af 704 *ebx = vec[1];
bdde476a 705 if (ecx)
a1fd24af 706 *ecx = vec[2];
bdde476a 707 if (edx)
a1fd24af 708 *edx = vec[3];
bdde476a 709}
c6dc6f63 710
20271d48
EH		 711void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
712{
713 uint32_t eax, ebx, ecx, edx;
714
715 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
716 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
717
718 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
719 if (family) {
720 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
721 }
722 if (model) {
723 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
724 }
725 if (stepping) {
726 *stepping = eax & 0x0F;
727 }
728}
729
d940ee9b
EH		 730/* CPU class name definitions: */
731
d940ee9b
EH		 732/* Return type name for a given CPU model name
733 * Caller is responsible for freeing the returned string.
734 */
735static char *x86_cpu_type_name(const char *model_name)
736{
737 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
738}
739
500050d1
AF		 740static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
741{
d940ee9b
EH		 742 ObjectClass *oc;
743 char *typename;
744
500050d1
AF		 745 if (cpu_model == NULL) {
746 return NULL;
747 }
748
d940ee9b
EH		 749 typename = x86_cpu_type_name(cpu_model);
750 oc = object_class_by_name(typename);
751 g_free(typename);
752 return oc;
500050d1
AF		 753}
754
104494ea
IM		 755static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
756{
757 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
758 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
759 return g_strndup(class_name,
760 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
761}
762
d940ee9b 763struct X86CPUDefinition {
c6dc6f63
AP		 764 const char *name;
765 uint32_t level;
90e4b0c3 766 uint32_t xlevel;
99b88a17
IM		 767 /* vendor is zero-terminated, 12 character ASCII string */
768 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 769 int family;
770 int model;
771 int stepping;
0514ef2f 772 FeatureWordArray features;
807e9869 773 const char *model_id;
d940ee9b 774};
c6dc6f63 775
9576de75 776static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 777 {
778 .name = "qemu64",
3046bb5d 779 .level = 0xd,
99b88a17 780 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 781 .family = 6,
f8e6a11a 782 .model = 6,
c6dc6f63 783 .stepping = 3,
0514ef2f 784 .features[FEAT_1_EDX] =
27861ecc 785 PPRO_FEATURES |
c6dc6f63 786 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 787 CPUID_PSE36,
0514ef2f 788 .features[FEAT_1_ECX] =
6aa91e4a 789 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 790 .features[FEAT_8000_0001_EDX] =
c6dc6f63 791 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 792 .features[FEAT_8000_0001_ECX] =
71195672 793 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 794 .xlevel = 0x8000000A,
9cf2cc3d 795 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 796 },
797 {
798 .name = "phenom",
799 .level = 5,
99b88a17 800 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 801 .family = 16,
802 .model = 2,
803 .stepping = 3,
b9fc20bc 804 /* Missing: CPUID_HT */
0514ef2f 805 .features[FEAT_1_EDX] =
27861ecc 806 PPRO_FEATURES |
c6dc6f63 807 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 808 CPUID_PSE36 | CPUID_VME,
0514ef2f 809 .features[FEAT_1_ECX] =
27861ecc 810 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 811 CPUID_EXT_POPCNT,
0514ef2f 812 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 813 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
814 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 815 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 816 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
817 CPUID_EXT3_CR8LEG,
818 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
819 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 820 .features[FEAT_8000_0001_ECX] =
27861ecc 821 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 822 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 823 /* Missing: CPUID_SVM_LBRV */
0514ef2f 824 .features[FEAT_SVM] =
b9fc20bc 825 CPUID_SVM_NPT,
c6dc6f63
AP		 826 .xlevel = 0x8000001A,
827 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
828 },
829 {
830 .name = "core2duo",
831 .level = 10,
99b88a17 832 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 833 .family = 6,
834 .model = 15,
835 .stepping = 11,
b9fc20bc 836 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 837 .features[FEAT_1_EDX] =
27861ecc 838 PPRO_FEATURES |
c6dc6f63 839 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 840 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
841 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 842 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 843 .features[FEAT_1_ECX] =
27861ecc 844 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 845 CPUID_EXT_CX16,
0514ef2f 846 .features[FEAT_8000_0001_EDX] =
27861ecc 847 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 848 .features[FEAT_8000_0001_ECX] =
27861ecc 849 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 850 .xlevel = 0x80000008,
851 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
852 },
853 {
854 .name = "kvm64",
3046bb5d 855 .level = 0xd,
99b88a17 856 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 857 .family = 15,
858 .model = 6,
859 .stepping = 1,
b3a4f0b1 860 /* Missing: CPUID_HT */
0514ef2f 861 .features[FEAT_1_EDX] =
b3a4f0b1 862 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 863 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
864 CPUID_PSE36,
865 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 866 .features[FEAT_1_ECX] =
27861ecc 867 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 868 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 869 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 870 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
871 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
872 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
873 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
874 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 875 .features[FEAT_8000_0001_ECX] =
27861ecc 876 0,
c6dc6f63
AP		 877 .xlevel = 0x80000008,
878 .model_id = "Common KVM processor"
879 },
c6dc6f63
AP		 880 {
881 .name = "qemu32",
882 .level = 4,
99b88a17 883 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 884 .family = 6,
f8e6a11a 885 .model = 6,
c6dc6f63 886 .stepping = 3,
0514ef2f 887 .features[FEAT_1_EDX] =
27861ecc 888 PPRO_FEATURES,
0514ef2f 889 .features[FEAT_1_ECX] =
6aa91e4a 890 CPUID_EXT_SSE3,
58012d66 891 .xlevel = 0x80000004,
9cf2cc3d 892 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 893 },
eafaf1e5
AP		 894 {
895 .name = "kvm32",
896 .level = 5,
99b88a17 897 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 898 .family = 15,
899 .model = 6,
900 .stepping = 1,
0514ef2f 901 .features[FEAT_1_EDX] =
b3a4f0b1 902 PPRO_FEATURES | CPUID_VME |
eafaf1e5 903 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 904 .features[FEAT_1_ECX] =
27861ecc 905 CPUID_EXT_SSE3,
0514ef2f 906 .features[FEAT_8000_0001_ECX] =
27861ecc 907 0,
eafaf1e5
AP		 908 .xlevel = 0x80000008,
909 .model_id = "Common 32-bit KVM processor"
910 },
c6dc6f63
AP		 911 {
912 .name = "coreduo",
913 .level = 10,
99b88a17 914 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 915 .family = 6,
916 .model = 14,
917 .stepping = 8,
b9fc20bc 918 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 919 .features[FEAT_1_EDX] =
27861ecc 920 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 921 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
922 CPUID_SS,
923 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 924 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 925 .features[FEAT_1_ECX] =
e93abc14 926 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 927 .features[FEAT_8000_0001_EDX] =
27861ecc 928 CPUID_EXT2_NX,
c6dc6f63
AP		 929 .xlevel = 0x80000008,
930 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
931 },
932 {
933 .name = "486",
58012d66 934 .level = 1,
99b88a17 935 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 936 .family = 4,
b2a856d9 937 .model = 8,
c6dc6f63 938 .stepping = 0,
0514ef2f 939 .features[FEAT_1_EDX] =
27861ecc 940 I486_FEATURES,
c6dc6f63 941 .xlevel = 0,
807e9869 942 .model_id = "",
c6dc6f63
AP		 943 },
944 {
945 .name = "pentium",
946 .level = 1,
99b88a17 947 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 948 .family = 5,
949 .model = 4,
950 .stepping = 3,
0514ef2f 951 .features[FEAT_1_EDX] =
27861ecc 952 PENTIUM_FEATURES,
c6dc6f63 953 .xlevel = 0,
807e9869 954 .model_id = "",
c6dc6f63
AP		 955 },
956 {
957 .name = "pentium2",
958 .level = 2,
99b88a17 959 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 960 .family = 6,
961 .model = 5,
962 .stepping = 2,
0514ef2f 963 .features[FEAT_1_EDX] =
27861ecc 964 PENTIUM2_FEATURES,
c6dc6f63 965 .xlevel = 0,
807e9869 966 .model_id = "",
c6dc6f63
AP		 967 },
968 {
969 .name = "pentium3",
3046bb5d 970 .level = 3,
99b88a17 971 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 972 .family = 6,
973 .model = 7,
974 .stepping = 3,
0514ef2f 975 .features[FEAT_1_EDX] =
27861ecc 976 PENTIUM3_FEATURES,
c6dc6f63 977 .xlevel = 0,
807e9869 978 .model_id = "",
c6dc6f63
AP		 979 },
980 {
981 .name = "athlon",
982 .level = 2,
99b88a17 983 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 984 .family = 6,
985 .model = 2,
986 .stepping = 3,
0514ef2f 987 .features[FEAT_1_EDX] =
27861ecc 988 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 989 CPUID_MCA,
0514ef2f 990 .features[FEAT_8000_0001_EDX] =
60032ac0 991 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 992 .xlevel = 0x80000008,
9cf2cc3d 993 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 994 },
995 {
996 .name = "n270",
3046bb5d 997 .level = 10,
99b88a17 998 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 999 .family = 6,
1000 .model = 28,
1001 .stepping = 2,
b9fc20bc 1002 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1003 .features[FEAT_1_EDX] =
27861ecc 1004 PPRO_FEATURES |
b9fc20bc
EH		 1005 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1006 CPUID_ACPI | CPUID_SS,
c6dc6f63 1007 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1008 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1009 * CPUID_EXT_XTPR */
0514ef2f 1010 .features[FEAT_1_ECX] =
27861ecc 1011 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1012 CPUID_EXT_MOVBE,
0514ef2f 1013 .features[FEAT_8000_0001_EDX] =
60032ac0 1014 CPUID_EXT2_NX,
0514ef2f 1015 .features[FEAT_8000_0001_ECX] =
27861ecc 1016 CPUID_EXT3_LAHF_LM,
3046bb5d 1017 .xlevel = 0x80000008,
c6dc6f63
AP		 1018 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1019 },
3eca4642
EH		 1020 {
1021 .name = "Conroe",
3046bb5d 1022 .level = 10,
99b88a17 1023 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1024 .family = 6,
ffce9ebb 1025 .model = 15,
3eca4642 1026 .stepping = 3,
0514ef2f 1027 .features[FEAT_1_EDX] =
b3a4f0b1 1028 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1029 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1030 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1031 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1032 CPUID_DE | CPUID_FP87,
0514ef2f 1033 .features[FEAT_1_ECX] =
27861ecc 1034 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1035 .features[FEAT_8000_0001_EDX] =
27861ecc 1036 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1037 .features[FEAT_8000_0001_ECX] =
27861ecc 1038 CPUID_EXT3_LAHF_LM,
3046bb5d 1039 .xlevel = 0x80000008,
3eca4642
EH		 1040 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1041 },
1042 {
1043 .name = "Penryn",
3046bb5d 1044 .level = 10,
99b88a17 1045 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1046 .family = 6,
ffce9ebb 1047 .model = 23,
3eca4642 1048 .stepping = 3,
0514ef2f 1049 .features[FEAT_1_EDX] =
b3a4f0b1 1050 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1051 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1052 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1053 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1054 CPUID_DE | CPUID_FP87,
0514ef2f 1055 .features[FEAT_1_ECX] =
27861ecc 1056 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1057 CPUID_EXT_SSE3,
0514ef2f 1058 .features[FEAT_8000_0001_EDX] =
27861ecc 1059 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1060 .features[FEAT_8000_0001_ECX] =
27861ecc 1061 CPUID_EXT3_LAHF_LM,
3046bb5d 1062 .xlevel = 0x80000008,
3eca4642
EH		 1063 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1064 },
1065 {
1066 .name = "Nehalem",
3046bb5d 1067 .level = 11,
99b88a17 1068 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1069 .family = 6,
ffce9ebb 1070 .model = 26,
3eca4642 1071 .stepping = 3,
0514ef2f 1072 .features[FEAT_1_EDX] =
b3a4f0b1 1073 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1074 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1075 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1076 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1077 CPUID_DE | CPUID_FP87,
0514ef2f 1078 .features[FEAT_1_ECX] =
27861ecc 1079 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1080 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1081 .features[FEAT_8000_0001_EDX] =
27861ecc 1082 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1083 .features[FEAT_8000_0001_ECX] =
27861ecc 1084 CPUID_EXT3_LAHF_LM,
3046bb5d 1085 .xlevel = 0x80000008,
3eca4642
EH		 1086 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1087 },
1088 {
1089 .name = "Westmere",
1090 .level = 11,
99b88a17 1091 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1092 .family = 6,
1093 .model = 44,
1094 .stepping = 1,
0514ef2f 1095 .features[FEAT_1_EDX] =
b3a4f0b1 1096 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1097 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1098 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1099 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1100 CPUID_DE | CPUID_FP87,
0514ef2f 1101 .features[FEAT_1_ECX] =
27861ecc 1102 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1103 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1104 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1105 .features[FEAT_8000_0001_EDX] =
27861ecc 1106 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1107 .features[FEAT_8000_0001_ECX] =
27861ecc 1108 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1109 .features[FEAT_6_EAX] =
1110 CPUID_6_EAX_ARAT,
3046bb5d 1111 .xlevel = 0x80000008,
3eca4642
EH		 1112 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1113 },
1114 {
1115 .name = "SandyBridge",
1116 .level = 0xd,
99b88a17 1117 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1118 .family = 6,
1119 .model = 42,
1120 .stepping = 1,
0514ef2f 1121 .features[FEAT_1_EDX] =
b3a4f0b1 1122 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1123 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1124 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1125 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1126 CPUID_DE | CPUID_FP87,
0514ef2f 1127 .features[FEAT_1_ECX] =
27861ecc 1128 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1129 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1130 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1131 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1132 CPUID_EXT_SSE3,
0514ef2f 1133 .features[FEAT_8000_0001_EDX] =
27861ecc 1134 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1135 CPUID_EXT2_SYSCALL,
0514ef2f 1136 .features[FEAT_8000_0001_ECX] =
27861ecc 1137 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1138 .features[FEAT_XSAVE] =
1139 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1140 .features[FEAT_6_EAX] =
1141 CPUID_6_EAX_ARAT,
3046bb5d 1142 .xlevel = 0x80000008,
3eca4642
EH		 1143 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1144 },
2f9ac42a
PB		 1145 {
1146 .name = "IvyBridge",
1147 .level = 0xd,
1148 .vendor = CPUID_VENDOR_INTEL,
1149 .family = 6,
1150 .model = 58,
1151 .stepping = 9,
1152 .features[FEAT_1_EDX] =
1153 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1154 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1155 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1156 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1157 CPUID_DE | CPUID_FP87,
1158 .features[FEAT_1_ECX] =
1159 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1160 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1161 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1162 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1163 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1164 .features[FEAT_7_0_EBX] =
1165 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1166 CPUID_7_0_EBX_ERMS,
1167 .features[FEAT_8000_0001_EDX] =
1168 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1169 CPUID_EXT2_SYSCALL,
1170 .features[FEAT_8000_0001_ECX] =
1171 CPUID_EXT3_LAHF_LM,
1172 .features[FEAT_XSAVE] =
1173 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1174 .features[FEAT_6_EAX] =
1175 CPUID_6_EAX_ARAT,
3046bb5d 1176 .xlevel = 0x80000008,
2f9ac42a
PB		 1177 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1178 },
37507094 1179 {
a356850b
EH		 1180 .name = "Haswell-noTSX",
1181 .level = 0xd,
1182 .vendor = CPUID_VENDOR_INTEL,
1183 .family = 6,
1184 .model = 60,
1185 .stepping = 1,
1186 .features[FEAT_1_EDX] =
1187 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1188 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1189 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1190 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1191 CPUID_DE | CPUID_FP87,
1192 .features[FEAT_1_ECX] =
1193 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1194 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1195 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1196 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1197 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1198 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1199 .features[FEAT_8000_0001_EDX] =
1200 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1201 CPUID_EXT2_SYSCALL,
1202 .features[FEAT_8000_0001_ECX] =
becb6667 1203 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1204 .features[FEAT_7_0_EBX] =
1205 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1206 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1207 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1208 .features[FEAT_XSAVE] =
1209 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1210 .features[FEAT_6_EAX] =
1211 CPUID_6_EAX_ARAT,
3046bb5d 1212 .xlevel = 0x80000008,
a356850b
EH		 1213 .model_id = "Intel Core Processor (Haswell, no TSX)",
1214 }, {
37507094
EH		 1215 .name = "Haswell",
1216 .level = 0xd,
99b88a17 1217 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1218 .family = 6,
1219 .model = 60,
ec56a4a7 1220 .stepping = 4,
0514ef2f 1221 .features[FEAT_1_EDX] =
b3a4f0b1 1222 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1223 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1224 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1225 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1226 CPUID_DE | CPUID_FP87,
0514ef2f 1227 .features[FEAT_1_ECX] =
27861ecc 1228 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1229 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1230 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1231 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1232 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1233 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1234 .features[FEAT_8000_0001_EDX] =
27861ecc 1235 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1236 CPUID_EXT2_SYSCALL,
0514ef2f 1237 .features[FEAT_8000_0001_ECX] =
becb6667 1238 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1239 .features[FEAT_7_0_EBX] =
27861ecc 1240 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1241 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1242 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1243 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1244 .features[FEAT_XSAVE] =
1245 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1246 .features[FEAT_6_EAX] =
1247 CPUID_6_EAX_ARAT,
3046bb5d 1248 .xlevel = 0x80000008,
37507094
EH		 1249 .model_id = "Intel Core Processor (Haswell)",
1250 },
a356850b
EH		 1251 {
1252 .name = "Broadwell-noTSX",
1253 .level = 0xd,
1254 .vendor = CPUID_VENDOR_INTEL,
1255 .family = 6,
1256 .model = 61,
1257 .stepping = 2,
1258 .features[FEAT_1_EDX] =
1259 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1260 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1261 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1262 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1263 CPUID_DE | CPUID_FP87,
1264 .features[FEAT_1_ECX] =
1265 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1266 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1267 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1268 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1269 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1270 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1271 .features[FEAT_8000_0001_EDX] =
1272 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1273 CPUID_EXT2_SYSCALL,
1274 .features[FEAT_8000_0001_ECX] =
becb6667 1275 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1276 .features[FEAT_7_0_EBX] =
1277 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1278 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1279 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1280 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1281 CPUID_7_0_EBX_SMAP,
1282 .features[FEAT_XSAVE] =
1283 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1284 .features[FEAT_6_EAX] =
1285 CPUID_6_EAX_ARAT,
3046bb5d 1286 .xlevel = 0x80000008,
a356850b
EH		 1287 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1288 },
ece01354
EH		 1289 {
1290 .name = "Broadwell",
1291 .level = 0xd,
1292 .vendor = CPUID_VENDOR_INTEL,
1293 .family = 6,
1294 .model = 61,
1295 .stepping = 2,
1296 .features[FEAT_1_EDX] =
b3a4f0b1 1297 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1298 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1299 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1300 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1301 CPUID_DE | CPUID_FP87,
1302 .features[FEAT_1_ECX] =
1303 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1304 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1305 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1306 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1307 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1308 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1309 .features[FEAT_8000_0001_EDX] =
1310 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1311 CPUID_EXT2_SYSCALL,
1312 .features[FEAT_8000_0001_ECX] =
becb6667 1313 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1314 .features[FEAT_7_0_EBX] =
1315 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1316 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1317 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1318 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1319 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1320 .features[FEAT_XSAVE] =
1321 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1322 .features[FEAT_6_EAX] =
1323 CPUID_6_EAX_ARAT,
3046bb5d 1324 .xlevel = 0x80000008,
ece01354
EH		 1325 .model_id = "Intel Core Processor (Broadwell)",
1326 },
f6f949e9
EH		 1327 {
1328 .name = "Skylake-Client",
1329 .level = 0xd,
1330 .vendor = CPUID_VENDOR_INTEL,
1331 .family = 6,
1332 .model = 94,
1333 .stepping = 3,
1334 .features[FEAT_1_EDX] =
1335 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1336 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1337 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1338 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1339 CPUID_DE | CPUID_FP87,
1340 .features[FEAT_1_ECX] =
1341 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1342 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1343 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1344 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1345 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1346 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1347 .features[FEAT_8000_0001_EDX] =
1348 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1349 CPUID_EXT2_SYSCALL,
1350 .features[FEAT_8000_0001_ECX] =
1351 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1352 .features[FEAT_7_0_EBX] =
1353 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1354 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1355 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1356 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1357 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1358 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 1359 * including v4.1 to v4.12).
f6f949e9
EH		 1360 * KVM doesn't yet expose any XSAVES state save component,
1361 * and the only one defined in Skylake (processor tracing)
1362 * probably will block migration anyway.
1363 */
1364 .features[FEAT_XSAVE] =
1365 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1366 CPUID_XSAVE_XGETBV1,
1367 .features[FEAT_6_EAX] =
1368 CPUID_6_EAX_ARAT,
1369 .xlevel = 0x80000008,
1370 .model_id = "Intel Core Processor (Skylake)",
1371 },
53f9a6f4
BF		 1372 {
1373 .name = "Skylake-Server",
1374 .level = 0xd,
1375 .vendor = CPUID_VENDOR_INTEL,
1376 .family = 6,
1377 .model = 85,
1378 .stepping = 4,
1379 .features[FEAT_1_EDX] =
1380 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1381 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1382 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1383 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1384 CPUID_DE | CPUID_FP87,
1385 .features[FEAT_1_ECX] =
1386 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1387 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1388 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1389 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1390 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1391 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1392 .features[FEAT_8000_0001_EDX] =
1393 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
1394 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1395 .features[FEAT_8000_0001_ECX] =
1396 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1397 .features[FEAT_7_0_EBX] =
1398 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1399 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1400 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1401 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1402 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
1403 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
1404 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 1405 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
53f9a6f4
BF		 1406 /* Missing: XSAVES (not supported by some Linux versions,
1407 * including v4.1 to v4.12).
1408 * KVM doesn't yet expose any XSAVES state save component,
1409 * and the only one defined in Skylake (processor tracing)
1410 * probably will block migration anyway.
1411 */
1412 .features[FEAT_XSAVE] =
1413 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1414 CPUID_XSAVE_XGETBV1,
1415 .features[FEAT_6_EAX] =
1416 CPUID_6_EAX_ARAT,
1417 .xlevel = 0x80000008,
1418 .model_id = "Intel Xeon Processor (Skylake)",
1419 },
3eca4642
EH		 1420 {
1421 .name = "Opteron_G1",
1422 .level = 5,
99b88a17 1423 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1424 .family = 15,
1425 .model = 6,
1426 .stepping = 1,
0514ef2f 1427 .features[FEAT_1_EDX] =
b3a4f0b1 1428 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1429 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1430 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1431 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1432 CPUID_DE | CPUID_FP87,
0514ef2f 1433 .features[FEAT_1_ECX] =
27861ecc 1434 CPUID_EXT_SSE3,
0514ef2f 1435 .features[FEAT_8000_0001_EDX] =
2a923a29 1436 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 1437 .xlevel = 0x80000008,
1438 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1439 },
1440 {
1441 .name = "Opteron_G2",
1442 .level = 5,
99b88a17 1443 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1444 .family = 15,
1445 .model = 6,
1446 .stepping = 1,
0514ef2f 1447 .features[FEAT_1_EDX] =
b3a4f0b1 1448 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1449 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1450 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1451 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1452 CPUID_DE | CPUID_FP87,
0514ef2f 1453 .features[FEAT_1_ECX] =
27861ecc 1454 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1455 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1456 .features[FEAT_8000_0001_EDX] =
2a923a29 1457 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1458 .features[FEAT_8000_0001_ECX] =
27861ecc 1459 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1460 .xlevel = 0x80000008,
1461 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1462 },
1463 {
1464 .name = "Opteron_G3",
1465 .level = 5,
99b88a17 1466 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 1467 .family = 16,
1468 .model = 2,
1469 .stepping = 3,
0514ef2f 1470 .features[FEAT_1_EDX] =
b3a4f0b1 1471 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1472 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1473 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1474 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1475 CPUID_DE | CPUID_FP87,
0514ef2f 1476 .features[FEAT_1_ECX] =
27861ecc 1477 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1478 CPUID_EXT_SSE3,
33b5e8c0 1479 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1480 .features[FEAT_8000_0001_EDX] =
2a923a29 1481 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1482 .features[FEAT_8000_0001_ECX] =
27861ecc 1483 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1484 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1485 .xlevel = 0x80000008,
1486 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1487 },
1488 {
1489 .name = "Opteron_G4",
1490 .level = 0xd,
99b88a17 1491 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1492 .family = 21,
1493 .model = 1,
1494 .stepping = 2,
0514ef2f 1495 .features[FEAT_1_EDX] =
b3a4f0b1 1496 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1497 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1498 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1499 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1500 CPUID_DE | CPUID_FP87,
0514ef2f 1501 .features[FEAT_1_ECX] =
27861ecc 1502 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1503 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1504 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1505 CPUID_EXT_SSE3,
33b5e8c0 1506 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1507 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1508 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1509 CPUID_EXT2_SYSCALL,
0514ef2f 1510 .features[FEAT_8000_0001_ECX] =
27861ecc 1511 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1512 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1513 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1514 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1515 /* no xsaveopt! */
3eca4642
EH		 1516 .xlevel = 0x8000001A,
1517 .model_id = "AMD Opteron 62xx class CPU",
1518 },
021941b9
AP		 1519 {
1520 .name = "Opteron_G5",
1521 .level = 0xd,
99b88a17 1522 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1523 .family = 21,
1524 .model = 2,
1525 .stepping = 0,
0514ef2f 1526 .features[FEAT_1_EDX] =
b3a4f0b1 1527 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1528 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1529 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1530 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1531 CPUID_DE | CPUID_FP87,
0514ef2f 1532 .features[FEAT_1_ECX] =
27861ecc 1533 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1534 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1535 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1536 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1537 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1538 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1539 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1540 CPUID_EXT2_SYSCALL,
0514ef2f 1541 .features[FEAT_8000_0001_ECX] =
27861ecc 1542 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1543 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1544 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1545 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1546 /* no xsaveopt! */
021941b9
AP		 1547 .xlevel = 0x8000001A,
1548 .model_id = "AMD Opteron 63xx class CPU",
1549 },
2e2efc7d
BS		 1550 {
1551 .name = "EPYC",
1552 .level = 0xd,
1553 .vendor = CPUID_VENDOR_AMD,
1554 .family = 23,
1555 .model = 1,
1556 .stepping = 2,
1557 .features[FEAT_1_EDX] =
1558 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
1559 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
1560 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
1561 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
1562 CPUID_VME | CPUID_FP87,
1563 .features[FEAT_1_ECX] =
1564 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
1565 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
1566 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1567 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
1568 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1569 .features[FEAT_8000_0001_EDX] =
1570 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
1571 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
1572 CPUID_EXT2_SYSCALL,
1573 .features[FEAT_8000_0001_ECX] =
1574 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
1575 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
1576 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1577 .features[FEAT_7_0_EBX] =
1578 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
1579 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
1580 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
1581 CPUID_7_0_EBX_SHA_NI,
1582 /* Missing: XSAVES (not supported by some Linux versions,
1583 * including v4.1 to v4.12).
1584 * KVM doesn't yet expose any XSAVES state save component.
1585 */
1586 .features[FEAT_XSAVE] =
1587 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1588 CPUID_XSAVE_XGETBV1,
1589 .features[FEAT_6_EAX] =
1590 CPUID_6_EAX_ARAT,
1591 .xlevel = 0x8000000A,
1592 .model_id = "AMD EPYC Processor",
1593 },
c6dc6f63
AP		 1594};
1595
5114e842
EH		 1596typedef struct PropValue {
1597 const char *prop, *value;
1598} PropValue;
1599
1600/* KVM-specific features that are automatically added/removed
1601 * from all CPU models when KVM is enabled.
1602 */
1603static PropValue kvm_default_props[] = {
1604 { "kvmclock", "on" },
1605 { "kvm-nopiodelay", "on" },
1606 { "kvm-asyncpf", "on" },
1607 { "kvm-steal-time", "on" },
1608 { "kvm-pv-eoi", "on" },
1609 { "kvmclock-stable-bit", "on" },
1610 { "x2apic", "on" },
1611 { "acpi", "off" },
1612 { "monitor", "off" },
1613 { "svm", "off" },
1614 { NULL, NULL },
1615};
1616
04d99c3c
EH		 1617/* TCG-specific defaults that override all CPU models when using TCG
1618 */
1619static PropValue tcg_default_props[] = {
1620 { "vme", "off" },
1621 { NULL, NULL },
1622};
1623
1624
5114e842
EH		 1625void x86_cpu_change_kvm_default(const char *prop, const char *value)
1626{
1627 PropValue *pv;
1628 for (pv = kvm_default_props; pv->prop; pv++) {
1629 if (!strcmp(pv->prop, prop)) {
1630 pv->value = value;
1631 break;
1632 }
1633 }
1634
1635 /* It is valid to call this function only for properties that
1636 * are already present in the kvm_default_props table.
1637 */
1638 assert(pv->prop);
1639}
1640
4d1b279b
EH		 1641static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1642 bool migratable_only);
1643
40bfe48f
HZ		 1644static bool lmce_supported(void)
1645{
c62f2630 1646 uint64_t mce_cap = 0;
40bfe48f 1647
c62f2630 1648#ifdef CONFIG_KVM
40bfe48f
HZ		 1649 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1650 return false;
1651 }
c62f2630 1652#endif
40bfe48f
HZ		 1653
1654 return !!(mce_cap & MCG_LMCE_P);
1655}
1656
7d8050b5
EH		 1657#define CPUID_MODEL_ID_SZ 48
1658
1659/**
1660 * cpu_x86_fill_model_id:
1661 * Get CPUID model ID string from host CPU.
1662 *
1663 * @str should have at least CPUID_MODEL_ID_SZ bytes
1664 *
1665 * The function does NOT add a null terminator to the string
1666 * automatically.
1667 */
c6dc6f63
AP		 1668static int cpu_x86_fill_model_id(char *str)
1669{
1670 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1671 int i;
1672
1673 for (i = 0; i < 3; i++) {
1674 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1675 memcpy(str + i * 16 + 0, &eax, 4);
1676 memcpy(str + i * 16 + 4, &ebx, 4);
1677 memcpy(str + i * 16 + 8, &ecx, 4);
1678 memcpy(str + i * 16 + 12, &edx, 4);
1679 }
1680 return 0;
1681}
1682
c62f2630 1683static Property max_x86_cpu_properties[] = {
120eee7d 1684 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1685 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1686 DEFINE_PROP_END_OF_LIST()
1687};
1688
c62f2630 1689static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1690{
84f1b92f 1691 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1692 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 1693
f48c8837 1694 xcc->ordering = 9;
6e746f30 1695
ee465a3e 1696 xcc->model_description =
c62f2630 1697 "Enables all features supported by the accelerator in the current host";
d940ee9b 1698
c62f2630 1699 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 1700}
1701
0bacd8b3
EH		 1702static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
1703
c62f2630 1704static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 1705{
1706 X86CPU *cpu = X86_CPU(obj);
1707 CPUX86State *env = &cpu->env;
1708 KVMState *s = kvm_state;
d940ee9b 1709
4d1b279b
EH		 1710 /* We can't fill the features array here because we don't know yet if
1711 * "migratable" is true or false.
1712 */
44bd8e53 1713 cpu->max_features = true;
4d1b279b 1714
d6dcc558 1715 if (accel_uses_host_cpuid()) {
bd182022
EH		 1716 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
1717 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
1718 int family, model, stepping;
d6dcc558
SAGDR		 1719 X86CPUDefinition host_cpudef = { };
1720 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1721
1722 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1723 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
0bacd8b3 1724
bd182022 1725 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 1726
bd182022 1727 cpu_x86_fill_model_id(model_id);
0bacd8b3 1728
bd182022
EH		 1729 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
1730 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
1731 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
1732 object_property_set_int(OBJECT(cpu), stepping, "stepping",
1733 &error_abort);
1734 object_property_set_str(OBJECT(cpu), model_id, "model-id",
1735 &error_abort);
0bacd8b3 1736
d6dcc558
SAGDR		 1737 if (kvm_enabled()) {
1738 env->cpuid_min_level =
1739 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1740 env->cpuid_min_xlevel =
1741 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1742 env->cpuid_min_xlevel2 =
1743 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1744 } else {
1745 env->cpuid_min_level =
1746 hvf_get_supported_cpuid(0x0, 0, R_EAX);
1747 env->cpuid_min_xlevel =
1748 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
1749 env->cpuid_min_xlevel2 =
1750 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
1751 }
40bfe48f
HZ		 1752
1753 if (lmce_supported()) {
1754 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1755 }
6900d1cc
EH		 1756 } else {
1757 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
1758 "vendor", &error_abort);
1759 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
1760 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
1761 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
1762 object_property_set_str(OBJECT(cpu),
1763 "QEMU TCG CPU version " QEMU_HW_VERSION,
1764 "model-id", &error_abort);
e4356010 1765 }
2a573259 1766
d940ee9b 1767 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1768}
1769
c62f2630
EH		 1770static const TypeInfo max_x86_cpu_type_info = {
1771 .name = X86_CPU_TYPE_NAME("max"),
1772 .parent = TYPE_X86_CPU,
1773 .instance_init = max_x86_cpu_initfn,
1774 .class_init = max_x86_cpu_class_init,
1775};
1776
d6dcc558 1777#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 1778static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1779{
1780 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1781
d6dcc558 1782 xcc->host_cpuid_required = true;
c62f2630
EH		 1783 xcc->ordering = 8;
1784
d6dcc558
SAGDR		 1785 if (kvm_enabled()) {
1786 xcc->model_description =
1787 "KVM processor with all supported host features ";
1788 } else if (hvf_enabled()) {
1789 xcc->model_description =
1790 "HVF processor with all supported host features ";
1791 }
c62f2630
EH		 1792}
1793
d940ee9b
EH		 1794static const TypeInfo host_x86_cpu_type_info = {
1795 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 1796 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 1797 .class_init = host_x86_cpu_class_init,
1798};
1799
1800#endif
1801
8459e396 1802static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1803{
8459e396 1804 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1805 int i;
1806
857aee33 1807 for (i = 0; i < 32; ++i) {
72370dc1 1808 if ((1UL << i) & mask) {
bffd67b0 1809 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1810 assert(reg);
8297be80
AF		 1811 warn_report("%s doesn't support requested feature: "
1812 "CPUID.%02XH:%s%s%s [bit %d]",
d6dcc558 1813 accel_uses_host_cpuid() ? "host" : "TCG",
8297be80
AF		 1814 f->cpuid_eax, reg,
1815 f->feat_names[i] ? "." : "",
1816 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1817 }
857aee33 1818 }
c6dc6f63
AP		 1819}
1820
d7bce999
EB		 1821static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1822 const char *name, void *opaque,
1823 Error **errp)
95b8519d
AF		 1824{
1825 X86CPU *cpu = X86_CPU(obj);
1826 CPUX86State *env = &cpu->env;
1827 int64_t value;
1828
1829 value = (env->cpuid_version >> 8) & 0xf;
1830 if (value == 0xf) {
1831 value += (env->cpuid_version >> 20) & 0xff;
1832 }
51e72bc1 1833 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1834}
1835
d7bce999
EB		 1836static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1837 const char *name, void *opaque,
1838 Error **errp)
ed5e1ec3 1839{
71ad61d3
AF		 1840 X86CPU *cpu = X86_CPU(obj);
1841 CPUX86State *env = &cpu->env;
1842 const int64_t min = 0;
1843 const int64_t max = 0xff + 0xf;
65cd9064 1844 Error *local_err = NULL;
71ad61d3
AF		 1845 int64_t value;
1846
51e72bc1 1847 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1848 if (local_err) {
1849 error_propagate(errp, local_err);
71ad61d3
AF		 1850 return;
1851 }
1852 if (value < min || value > max) {
c6bd8c70
MA		 1853 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1854 name ? name : "null", value, min, max);
71ad61d3
AF		 1855 return;
1856 }
1857
ed5e1ec3 1858 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1859 if (value > 0x0f) {
1860 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1861 } else {
71ad61d3 1862 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1863 }
1864}
1865
d7bce999
EB		 1866static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1867 const char *name, void *opaque,
1868 Error **errp)
67e30c83
AF		 1869{
1870 X86CPU *cpu = X86_CPU(obj);
1871 CPUX86State *env = &cpu->env;
1872 int64_t value;
1873
1874 value = (env->cpuid_version >> 4) & 0xf;
1875 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1876 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1877}
1878
d7bce999
EB		 1879static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1880 const char *name, void *opaque,
1881 Error **errp)
b0704cbd 1882{
c5291a4f
AF		 1883 X86CPU *cpu = X86_CPU(obj);
1884 CPUX86State *env = &cpu->env;
1885 const int64_t min = 0;
1886 const int64_t max = 0xff;
65cd9064 1887 Error *local_err = NULL;
c5291a4f
AF		 1888 int64_t value;
1889
51e72bc1 1890 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1891 if (local_err) {
1892 error_propagate(errp, local_err);
c5291a4f
AF		 1893 return;
1894 }
1895 if (value < min || value > max) {
c6bd8c70
MA		 1896 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1897 name ? name : "null", value, min, max);
c5291a4f
AF		 1898 return;
1899 }
1900
b0704cbd 1901 env->cpuid_version &= ~0xf00f0;
c5291a4f 1902 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1903}
1904
35112e41 1905static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1906 const char *name, void *opaque,
35112e41
AF		 1907 Error **errp)
1908{
1909 X86CPU *cpu = X86_CPU(obj);
1910 CPUX86State *env = &cpu->env;
1911 int64_t value;
1912
1913 value = env->cpuid_version & 0xf;
51e72bc1 1914 visit_type_int(v, name, &value, errp);
35112e41
AF		 1915}
1916
036e2222 1917static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1918 const char *name, void *opaque,
036e2222 1919 Error **errp)
38c3dc46 1920{
036e2222
AF		 1921 X86CPU *cpu = X86_CPU(obj);
1922 CPUX86State *env = &cpu->env;
1923 const int64_t min = 0;
1924 const int64_t max = 0xf;
65cd9064 1925 Error *local_err = NULL;
036e2222
AF		 1926 int64_t value;
1927
51e72bc1 1928 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1929 if (local_err) {
1930 error_propagate(errp, local_err);
036e2222
AF		 1931 return;
1932 }
1933 if (value < min || value > max) {
c6bd8c70
MA		 1934 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1935 name ? name : "null", value, min, max);
036e2222
AF		 1936 return;
1937 }
1938
38c3dc46 1939 env->cpuid_version &= ~0xf;
036e2222 1940 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1941}
1942
d480e1af
AF		 1943static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1944{
1945 X86CPU *cpu = X86_CPU(obj);
1946 CPUX86State *env = &cpu->env;
1947 char *value;
d480e1af 1948
e42a92ae 1949 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1950 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1951 env->cpuid_vendor3);
d480e1af
AF		 1952 return value;
1953}
1954
1955static void x86_cpuid_set_vendor(Object *obj, const char *value,
1956 Error **errp)
1957{
1958 X86CPU *cpu = X86_CPU(obj);
1959 CPUX86State *env = &cpu->env;
1960 int i;
1961
9df694ee 1962 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1963 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1964 return;
1965 }
1966
1967 env->cpuid_vendor1 = 0;
1968 env->cpuid_vendor2 = 0;
1969 env->cpuid_vendor3 = 0;
1970 for (i = 0; i < 4; i++) {
1971 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1972 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1973 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1974 }
d480e1af
AF		 1975}
1976
63e886eb
AF		 1977static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1978{
1979 X86CPU *cpu = X86_CPU(obj);
1980 CPUX86State *env = &cpu->env;
1981 char *value;
1982 int i;
1983
1984 value = g_malloc(48 + 1);
1985 for (i = 0; i < 48; i++) {
1986 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1987 }
1988 value[48] = '\0';
1989 return value;
1990}
1991
938d4c25
AF		 1992static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1993 Error **errp)
dcce6675 1994{
938d4c25
AF		 1995 X86CPU *cpu = X86_CPU(obj);
1996 CPUX86State *env = &cpu->env;
dcce6675
AF		 1997 int c, len, i;
1998
1999 if (model_id == NULL) {
2000 model_id = "";
2001 }
2002 len = strlen(model_id);
d0a6acf4 2003 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 2004 for (i = 0; i < 48; i++) {
2005 if (i >= len) {
2006 c = '\0';
2007 } else {
2008 c = (uint8_t)model_id[i];
2009 }
2010 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
2011 }
2012}
2013
d7bce999
EB		 2014static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
2015 void *opaque, Error **errp)
89e48965
AF		 2016{
2017 X86CPU *cpu = X86_CPU(obj);
2018 int64_t value;
2019
2020 value = cpu->env.tsc_khz * 1000;
51e72bc1 2021 visit_type_int(v, name, &value, errp);
89e48965
AF		 2022}
2023
d7bce999
EB		 2024static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
2025 void *opaque, Error **errp)
89e48965
AF		 2026{
2027 X86CPU *cpu = X86_CPU(obj);
2028 const int64_t min = 0;
2e84849a 2029 const int64_t max = INT64_MAX;
65cd9064 2030 Error *local_err = NULL;
89e48965
AF		 2031 int64_t value;
2032
51e72bc1 2033 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2034 if (local_err) {
2035 error_propagate(errp, local_err);
89e48965
AF		 2036 return;
2037 }
2038 if (value < min || value > max) {
c6bd8c70
MA		 2039 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2040 name ? name : "null", value, min, max);
89e48965
AF		 2041 return;
2042 }
2043
36f96c4b 2044 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 2045}
2046
7e5292b5 2047/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 2048static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
2049 const char *name, void *opaque,
2050 Error **errp)
8e8aba50 2051{
7e5292b5 2052 uint32_t *array = (uint32_t *)opaque;
8e8aba50 2053 FeatureWord w;
8e8aba50
EH		 2054 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
2055 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
2056 X86CPUFeatureWordInfoList *list = NULL;
2057
2058 for (w = 0; w < FEATURE_WORDS; w++) {
2059 FeatureWordInfo *wi = &feature_word_info[w];
2060 X86CPUFeatureWordInfo *qwi = &word_infos[w];
2061 qwi->cpuid_input_eax = wi->cpuid_eax;
2062 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
2063 qwi->cpuid_input_ecx = wi->cpuid_ecx;
2064 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 2065 qwi->features = array[w];
8e8aba50
EH		 2066
2067 /* List will be in reverse order, but order shouldn't matter */
2068 list_entries[w].next = list;
2069 list_entries[w].value = &word_infos[w];
2070 list = &list_entries[w];
2071 }
2072
6b62d961 2073 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 2074}
2075
d7bce999
EB		 2076static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
2077 void *opaque, Error **errp)
c8f0f88e
IM		 2078{
2079 X86CPU *cpu = X86_CPU(obj);
2080 int64_t value = cpu->hyperv_spinlock_attempts;
2081
51e72bc1 2082 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 2083}
2084
d7bce999
EB		 2085static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
2086 void *opaque, Error **errp)
c8f0f88e
IM		 2087{
2088 const int64_t min = 0xFFF;
2089 const int64_t max = UINT_MAX;
2090 X86CPU *cpu = X86_CPU(obj);
2091 Error *err = NULL;
2092 int64_t value;
2093
51e72bc1 2094 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 2095 if (err) {
2096 error_propagate(errp, err);
2097 return;
2098 }
2099
2100 if (value < min || value > max) {
2101 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 2102 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
2103 object_get_typename(obj), name ? name : "null",
2104 value, min, max);
c8f0f88e
IM		 2105 return;
2106 }
2107 cpu->hyperv_spinlock_attempts = value;
2108}
2109
1b6b7d10 2110static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 2111 .name = "int",
2112 .get = x86_get_hv_spinlocks,
2113 .set = x86_set_hv_spinlocks,
2114};
2115
72ac2e87
IM		 2116/* Convert all '_' in a feature string option name to '-', to make feature
2117 * name conform to QOM property naming rule, which uses '-' instead of '_'.
2118 */
2119static inline void feat2prop(char *s)
2120{
2121 while ((s = strchr(s, '_'))) {
2122 *s = '-';
2123 }
2124}
2125
b54c9377
EH		 2126/* Return the feature property name for a feature flag bit */
2127static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
2128{
2129 /* XSAVE components are automatically enabled by other features,
2130 * so return the original feature name instead
2131 */
2132 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
2133 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
2134
2135 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
2136 x86_ext_save_areas[comp].bits) {
2137 w = x86_ext_save_areas[comp].feature;
2138 bitnr = ctz32(x86_ext_save_areas[comp].bits);
2139 }
2140 }
2141
2142 assert(bitnr < 32);
2143 assert(w < FEATURE_WORDS);
2144 return feature_word_info[w].feat_names[bitnr];
2145}
2146
dc15c051
IM		 2147/* Compatibily hack to maintain legacy +-feat semantic,
2148 * where +-feat overwrites any feature set by
2149 * feat=on|feat even if the later is parsed after +-feat
2150 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2151 */
2fae0d96 2152static GList *plus_features, *minus_features;
dc15c051 2153
83a00f60
EH		 2154static gint compare_string(gconstpointer a, gconstpointer b)
2155{
2156 return g_strcmp0(a, b);
2157}
2158
8f961357
EH		 2159/* Parse "+feature,-feature,feature=foo" CPU feature string
2160 */
62a48a2a 2161static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 2162 Error **errp)
8f961357 2163{
8f961357 2164 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 2165 static bool cpu_globals_initialized;
83a00f60 2166 bool ambiguous = false;
62a48a2a
IM		 2167
2168 if (cpu_globals_initialized) {
2169 return;
2170 }
2171 cpu_globals_initialized = true;
8f961357 2172
f6750e95
EH		 2173 if (!features) {
2174 return;
2175 }
2176
2177 for (featurestr = strtok(features, ",");
685479bd 2178 featurestr;
f6750e95
EH		 2179 featurestr = strtok(NULL, ",")) {
2180 const char *name;
2181 const char *val = NULL;
2182 char *eq = NULL;
cf2887c9 2183 char num[32];
62a48a2a 2184 GlobalProperty *prop;
c6dc6f63 2185
f6750e95 2186 /* Compatibility syntax: */
c6dc6f63 2187 if (featurestr[0] == '+') {
2fae0d96
EH		 2188 plus_features = g_list_append(plus_features,
2189 g_strdup(featurestr + 1));
f6750e95 2190 continue;
c6dc6f63 2191 } else if (featurestr[0] == '-') {
2fae0d96
EH		 2192 minus_features = g_list_append(minus_features,
2193 g_strdup(featurestr + 1));
f6750e95
EH		 2194 continue;
2195 }
2196
2197 eq = strchr(featurestr, '=');
2198 if (eq) {
2199 *eq++ = 0;
2200 val = eq;
c6dc6f63 2201 } else {
f6750e95 2202 val = "on";
a91987c2 2203 }
f6750e95
EH		 2204
2205 feat2prop(featurestr);
2206 name = featurestr;
2207
83a00f60 2208 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 2209 warn_report("Ambiguous CPU model string. "
2210 "Don't mix both \"+%s\" and \"%s=%s\"",
2211 name, name, val);
83a00f60
EH		 2212 ambiguous = true;
2213 }
2214 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 2215 warn_report("Ambiguous CPU model string. "
2216 "Don't mix both \"-%s\" and \"%s=%s\"",
2217 name, name, val);
83a00f60
EH		 2218 ambiguous = true;
2219 }
2220
f6750e95
EH		 2221 /* Special case: */
2222 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 2223 int ret;
f46bfdbf 2224 uint64_t tsc_freq;
f6750e95 2225
f17fd4fd 2226 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 2227 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 2228 error_setg(errp, "bad numerical value %s", val);
2229 return;
2230 }
2231 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2232 val = num;
2233 name = "tsc-frequency";
c6dc6f63 2234 }
f6750e95 2235
62a48a2a
IM		 2236 prop = g_new0(typeof(*prop), 1);
2237 prop->driver = typename;
2238 prop->property = g_strdup(name);
2239 prop->value = g_strdup(val);
2240 prop->errp = &error_fatal;
2241 qdev_prop_register_global(prop);
f6750e95
EH		 2242 }
2243
83a00f60 2244 if (ambiguous) {
3dc6f869
AF		 2245 warn_report("Compatibility of ambiguous CPU model "
2246 "strings won't be kept on future QEMU versions");
83a00f60 2247 }
c6dc6f63
AP		 2248}
2249
b8d834a0 2250static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 2251static int x86_cpu_filter_features(X86CPU *cpu);
2252
2253/* Check for missing features that may prevent the CPU class from
2254 * running using the current machine and accelerator.
2255 */
2256static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
2257 strList **missing_feats)
2258{
2259 X86CPU *xc;
2260 FeatureWord w;
2261 Error *err = NULL;
2262 strList **next = missing_feats;
2263
d6dcc558 2264 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 2265 strList *new = g_new0(strList, 1);
3c254ab8 2266 new->value = g_strdup("kvm");
b54c9377
EH		 2267 *missing_feats = new;
2268 return;
2269 }
2270
2271 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2272
b8d834a0 2273 x86_cpu_expand_features(xc, &err);
b54c9377 2274 if (err) {
b8d834a0 2275 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 2276 * but in case it does, just report the model as not
2277 * runnable at all using the "type" property.
2278 */
2279 strList *new = g_new0(strList, 1);
2280 new->value = g_strdup("type");
2281 *next = new;
2282 next = &new->next;
2283 }
2284
2285 x86_cpu_filter_features(xc);
2286
2287 for (w = 0; w < FEATURE_WORDS; w++) {
2288 uint32_t filtered = xc->filtered_features[w];
2289 int i;
2290 for (i = 0; i < 32; i++) {
2291 if (filtered & (1UL << i)) {
2292 strList *new = g_new0(strList, 1);
2293 new->value = g_strdup(x86_cpu_feature_name(w, i));
2294 *next = new;
2295 next = &new->next;
2296 }
2297 }
2298 }
2299
2300 object_unref(OBJECT(xc));
2301}
2302
8c3329e5 2303/* Print all cpuid feature names in featureset
c6dc6f63 2304 */
8c3329e5 2305static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2306{
8c3329e5
EH		 2307 int bit;
2308 bool first = true;
2309
2310 for (bit = 0; bit < 32; bit++) {
2311 if (featureset[bit]) {
2312 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2313 first = false;
c6dc6f63 2314 }
8c3329e5 2315 }
c6dc6f63
AP		 2316}
2317
f48c8837 2318/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 2319static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
2320{
2321 ObjectClass *class_a = (ObjectClass *)a;
2322 ObjectClass *class_b = (ObjectClass *)b;
2323 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
2324 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
2325 const char *name_a, *name_b;
2326
f48c8837
EH		 2327 if (cc_a->ordering != cc_b->ordering) {
2328 return cc_a->ordering - cc_b->ordering;
ee465a3e
EH		 2329 } else {
2330 name_a = object_class_get_name(class_a);
2331 name_b = object_class_get_name(class_b);
2332 return strcmp(name_a, name_b);
2333 }
2334}
2335
2336static GSList *get_sorted_cpu_model_list(void)
2337{
2338 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
2339 list = g_slist_sort(list, x86_cpu_list_compare);
2340 return list;
2341}
2342
2343static void x86_cpu_list_entry(gpointer data, gpointer user_data)
2344{
2345 ObjectClass *oc = data;
2346 X86CPUClass *cc = X86_CPU_CLASS(oc);
2347 CPUListState *s = user_data;
2348 char *name = x86_cpu_class_get_model_name(cc);
2349 const char *desc = cc->model_description;
0bacd8b3 2350 if (!desc && cc->cpu_def) {
ee465a3e
EH		 2351 desc = cc->cpu_def->model_id;
2352 }
2353
2354 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
2355 name, desc);
2356 g_free(name);
2357}
2358
2359/* list available CPU models and flags */
e916cbf8 2360void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2361{
7fc9b714 2362 int i;
ee465a3e
EH		 2363 CPUListState s = {
2364 .file = f,
2365 .cpu_fprintf = cpu_fprintf,
2366 };
2367 GSList *list;
c6dc6f63 2368
ee465a3e
EH		 2369 (*cpu_fprintf)(f, "Available CPUs:\n");
2370 list = get_sorted_cpu_model_list();
2371 g_slist_foreach(list, x86_cpu_list_entry, &s);
2372 g_slist_free(list);
21ad7789 2373
6cdf8854 2374 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2375 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2376 FeatureWordInfo *fw = &feature_word_info[i];
2377
8c3329e5
EH		 2378 (*cpu_fprintf)(f, " ");
2379 listflags(f, cpu_fprintf, fw->feat_names);
2380 (*cpu_fprintf)(f, "\n");
3af60be2 2381 }
c6dc6f63
AP		 2382}
2383
ee465a3e
EH		 2384static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
2385{
2386 ObjectClass *oc = data;
2387 X86CPUClass *cc = X86_CPU_CLASS(oc);
2388 CpuDefinitionInfoList **cpu_list = user_data;
2389 CpuDefinitionInfoList *entry;
2390 CpuDefinitionInfo *info;
2391
2392 info = g_malloc0(sizeof(*info));
2393 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 2394 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
2395 info->has_unavailable_features = true;
8ed877b7 2396 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 2397 info->migration_safe = cc->migration_safe;
2398 info->has_migration_safe = true;
5adbed30 2399 info->q_static = cc->static_model;
ee465a3e
EH		 2400
2401 entry = g_malloc0(sizeof(*entry));
2402 entry->value = info;
2403 entry->next = *cpu_list;
2404 *cpu_list = entry;
2405}
2406
76b64a7a 2407CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2408{
2409 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 2410 GSList *list = get_sorted_cpu_model_list();
2411 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
2412 g_slist_free(list);
e3966126
AL		 2413 return cpu_list;
2414}
2415
84f1b92f
EH		 2416static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2417 bool migratable_only)
27418adf
EH		 2418{
2419 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2420 uint32_t r;
27418adf 2421
fefb41bf 2422 if (kvm_enabled()) {
84f1b92f
EH		 2423 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2424 wi->cpuid_ecx,
2425 wi->cpuid_reg);
d6dcc558
SAGDR		 2426 } else if (hvf_enabled()) {
2427 r = hvf_get_supported_cpuid(wi->cpuid_eax,
2428 wi->cpuid_ecx,
2429 wi->cpuid_reg);
fefb41bf 2430 } else if (tcg_enabled()) {
84f1b92f 2431 r = wi->tcg_features;
fefb41bf
EH		 2432 } else {
2433 return ~0;
2434 }
84f1b92f
EH		 2435 if (migratable_only) {
2436 r &= x86_cpu_get_migratable_flags(w);
2437 }
2438 return r;
27418adf
EH		 2439}
2440
8ca30e86
EH		 2441static void x86_cpu_report_filtered_features(X86CPU *cpu)
2442{
2443 FeatureWord w;
2444
2445 for (w = 0; w < FEATURE_WORDS; w++) {
2446 report_unavailable_features(w, cpu->filtered_features[w]);
2447 }
2448}
2449
5114e842
EH		 2450static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2451{
2452 PropValue *pv;
2453 for (pv = props; pv->prop; pv++) {
2454 if (!pv->value) {
2455 continue;
2456 }
2457 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2458 &error_abort);
2459 }
2460}
2461
f99fd7ca 2462/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 2463 */
d940ee9b 2464static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2465{
61dcd775 2466 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2467 const char *vendor;
2468 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2469 FeatureWord w;
c6dc6f63 2470
f99fd7ca
EH		 2471 /*NOTE: any property set by this function should be returned by
2472 * x86_cpu_static_props(), so static expansion of
2473 * query-cpu-model-expansion is always complete.
2474 */
2475
c39c0edf 2476 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 2477 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
2478 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 2479
2d64255b
AF		 2480 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2481 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2482 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2483 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2484 for (w = 0; w < FEATURE_WORDS; w++) {
2485 env->features[w] = def->features[w];
2486 }
82beb536 2487
9576de75 2488 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 2489 /* TODO: in-kernel irqchip for hvf */
82beb536 2490 if (kvm_enabled()) {
492a4c94
LT		 2491 if (!kvm_irqchip_in_kernel()) {
2492 x86_cpu_change_kvm_default("x2apic", "off");
2493 }
2494
5114e842 2495 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 2496 } else if (tcg_enabled()) {
2497 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 2498 }
5fcca9ff 2499
82beb536 2500 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2501
2502 /* sysenter isn't supported in compatibility mode on AMD,
2503 * syscall isn't supported in compatibility mode on Intel.
2504 * Normally we advertise the actual CPU vendor, but you can
2505 * override this using the 'vendor' property if you want to use
2506 * KVM's sysenter/syscall emulation in compatibility mode and
2507 * when doing cross vendor migration
2508 */
74f54bc4 2509 vendor = def->vendor;
d6dcc558 2510 if (accel_uses_host_cpuid()) {
7c08db30
EH		 2511 uint32_t ebx = 0, ecx = 0, edx = 0;
2512 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2513 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2514 vendor = host_vendor;
2515 }
2516
2517 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2518
c6dc6f63
AP		 2519}
2520
f99fd7ca
EH		 2521/* Return a QDict containing keys for all properties that can be included
2522 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
2523 * must be included in the dictionary.
2524 */
2525static QDict *x86_cpu_static_props(void)
2526{
2527 FeatureWord w;
2528 int i;
2529 static const char *props[] = {
2530 "min-level",
2531 "min-xlevel",
2532 "family",
2533 "model",
2534 "stepping",
2535 "model-id",
2536 "vendor",
2537 "lmce",
2538 NULL,
2539 };
2540 static QDict *d;
2541
2542 if (d) {
2543 return d;
2544 }
2545
2546 d = qdict_new();
2547 for (i = 0; props[i]; i++) {
0f9afc2a 2548 qdict_put_null(d, props[i]);
f99fd7ca
EH		 2549 }
2550
2551 for (w = 0; w < FEATURE_WORDS; w++) {
2552 FeatureWordInfo *fi = &feature_word_info[w];
2553 int bit;
2554 for (bit = 0; bit < 32; bit++) {
2555 if (!fi->feat_names[bit]) {
2556 continue;
2557 }
0f9afc2a 2558 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 2559 }
2560 }
2561
2562 return d;
2563}
2564
2565/* Add an entry to @props dict, with the value for property. */
2566static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
2567{
2568 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
2569 &error_abort);
2570
2571 qdict_put_obj(props, prop, value);
2572}
2573
2574/* Convert CPU model data from X86CPU object to a property dictionary
2575 * that can recreate exactly the same CPU model.
2576 */
2577static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
2578{
2579 QDict *sprops = x86_cpu_static_props();
2580 const QDictEntry *e;
2581
2582 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
2583 const char *prop = qdict_entry_key(e);
2584 x86_cpu_expand_prop(cpu, props, prop);
2585 }
2586}
2587
b8097deb
EH		 2588/* Convert CPU model data from X86CPU object to a property dictionary
2589 * that can recreate exactly the same CPU model, including every
2590 * writeable QOM property.
2591 */
2592static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
2593{
2594 ObjectPropertyIterator iter;
2595 ObjectProperty *prop;
2596
2597 object_property_iter_init(&iter, OBJECT(cpu));
2598 while ((prop = object_property_iter_next(&iter))) {
2599 /* skip read-only or write-only properties */
2600 if (!prop->get || !prop->set) {
2601 continue;
2602 }
2603
2604 /* "hotplugged" is the only property that is configurable
2605 * on the command-line but will be set differently on CPUs
2606 * created using "-cpu ... -smp ..." and by CPUs created
2607 * on the fly by x86_cpu_from_model() for querying. Skip it.
2608 */
2609 if (!strcmp(prop->name, "hotplugged")) {
2610 continue;
2611 }
2612 x86_cpu_expand_prop(cpu, props, prop->name);
2613 }
2614}
2615
f99fd7ca
EH		 2616static void object_apply_props(Object *obj, QDict *props, Error **errp)
2617{
2618 const QDictEntry *prop;
2619 Error *err = NULL;
2620
2621 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
2622 object_property_set_qobject(obj, qdict_entry_value(prop),
2623 qdict_entry_key(prop), &err);
2624 if (err) {
2625 break;
2626 }
2627 }
2628
2629 error_propagate(errp, err);
2630}
2631
2632/* Create X86CPU object according to model+props specification */
2633static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
2634{
2635 X86CPU *xc = NULL;
2636 X86CPUClass *xcc;
2637 Error *err = NULL;
2638
2639 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
2640 if (xcc == NULL) {
2641 error_setg(&err, "CPU model '%s' not found", model);
2642 goto out;
2643 }
2644
2645 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2646 if (props) {
2647 object_apply_props(OBJECT(xc), props, &err);
2648 if (err) {
2649 goto out;
2650 }
2651 }
2652
2653 x86_cpu_expand_features(xc, &err);
2654 if (err) {
2655 goto out;
2656 }
2657
2658out:
2659 if (err) {
2660 error_propagate(errp, err);
2661 object_unref(OBJECT(xc));
2662 xc = NULL;
2663 }
2664 return xc;
2665}
2666
2667CpuModelExpansionInfo *
2668arch_query_cpu_model_expansion(CpuModelExpansionType type,
2669 CpuModelInfo *model,
2670 Error **errp)
2671{
2672 X86CPU *xc = NULL;
2673 Error *err = NULL;
2674 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
2675 QDict *props = NULL;
2676 const char *base_name;
2677
2678 xc = x86_cpu_from_model(model->name,
2679 model->has_props ?
2680 qobject_to_qdict(model->props) :
2681 NULL, &err);
2682 if (err) {
2683 goto out;
2684 }
2685
b8097deb 2686 props = qdict_new();
f99fd7ca
EH		 2687
2688 switch (type) {
2689 case CPU_MODEL_EXPANSION_TYPE_STATIC:
2690 /* Static expansion will be based on "base" only */
2691 base_name = "base";
b8097deb 2692 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 2693 break;
2694 case CPU_MODEL_EXPANSION_TYPE_FULL:
2695 /* As we don't return every single property, full expansion needs
2696 * to keep the original model name+props, and add extra
2697 * properties on top of that.
2698 */
2699 base_name = model->name;
b8097deb 2700 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 2701 break;
2702 default:
2703 error_setg(&err, "Unsupportted expansion type");
2704 goto out;
2705 }
2706
2707 if (!props) {
2708 props = qdict_new();
2709 }
2710 x86_cpu_to_dict(xc, props);
2711
2712 ret->model = g_new0(CpuModelInfo, 1);
2713 ret->model->name = g_strdup(base_name);
2714 ret->model->props = QOBJECT(props);
2715 ret->model->has_props = true;
2716
2717out:
2718 object_unref(OBJECT(xc));
2719 if (err) {
2720 error_propagate(errp, err);
2721 qapi_free_CpuModelExpansionInfo(ret);
2722 ret = NULL;
2723 }
2724 return ret;
2725}
2726
00fcd100
AB		 2727static gchar *x86_gdb_arch_name(CPUState *cs)
2728{
2729#ifdef TARGET_X86_64
2730 return g_strdup("i386:x86-64");
2731#else
2732 return g_strdup("i386");
2733#endif
2734}
2735
d940ee9b
EH		 2736static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2737{
2738 X86CPUDefinition *cpudef = data;
2739 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2740
2741 xcc->cpu_def = cpudef;
bd72159d 2742 xcc->migration_safe = true;
d940ee9b
EH		 2743}
2744
2745static void x86_register_cpudef_type(X86CPUDefinition *def)
2746{
2747 char *typename = x86_cpu_type_name(def->name);
2748 TypeInfo ti = {
2749 .name = typename,
2750 .parent = TYPE_X86_CPU,
2751 .class_init = x86_cpu_cpudef_class_init,
2752 .class_data = def,
2753 };
2754
2a923a29
EH		 2755 /* AMD aliases are handled at runtime based on CPUID vendor, so
2756 * they shouldn't be set on the CPU model table.
2757 */
2758 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 2759 /* catch mistakes instead of silently truncating model_id when too long */
2760 assert(def->model_id && strlen(def->model_id) <= 48);
2761
2a923a29 2762
d940ee9b
EH		 2763 type_register(&ti);
2764 g_free(typename);
2765}
2766
c6dc6f63 2767#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2768
0e26b7b8
BS		 2769void cpu_clear_apic_feature(CPUX86State *env)
2770{
0514ef2f 2771 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2772}
2773
c6dc6f63
AP		 2774#endif /* !CONFIG_USER_ONLY */
2775
c6dc6f63
AP		 2776void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2777 uint32_t *eax, uint32_t *ebx,
2778 uint32_t *ecx, uint32_t *edx)
2779{
a60f24b5
AF		 2780 X86CPU *cpu = x86_env_get_cpu(env);
2781 CPUState *cs = CPU(cpu);
14c985cf 2782 uint32_t pkg_offset;
4ed3d478 2783 uint32_t limit;
1ce36bfe 2784 uint32_t signature[3];
a60f24b5 2785
4ed3d478
DB		 2786 /* Calculate & apply limits for different index ranges */
2787 if (index >= 0xC0000000) {
2788 limit = env->cpuid_xlevel2;
2789 } else if (index >= 0x80000000) {
2790 limit = env->cpuid_xlevel;
1ce36bfe
DB		 2791 } else if (index >= 0x40000000) {
2792 limit = 0x40000001;
c6dc6f63 2793 } else {
4ed3d478
DB		 2794 limit = env->cpuid_level;
2795 }
2796
2797 if (index > limit) {
2798 /* Intel documentation states that invalid EAX input will
2799 * return the same information as EAX=cpuid_level
2800 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2801 */
2802 index = env->cpuid_level;
c6dc6f63
AP		 2803 }
2804
2805 switch(index) {
2806 case 0:
2807 *eax = env->cpuid_level;
5eb2f7a4
EH		 2808 *ebx = env->cpuid_vendor1;
2809 *edx = env->cpuid_vendor2;
2810 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2811 break;
2812 case 1:
2813 *eax = env->cpuid_version;
7e72a45c
EH		 2814 *ebx = (cpu->apic_id << 24) |
2815 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2816 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2817 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2818 *ecx |= CPUID_EXT_OSXSAVE;
2819 }
0514ef2f 2820 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2821 if (cs->nr_cores * cs->nr_threads > 1) {
2822 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2823 *edx |= CPUID_HT;
c6dc6f63
AP		 2824 }
2825 break;
2826 case 2:
2827 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2828 if (cpu->cache_info_passthrough) {
2829 host_cpuid(index, 0, eax, ebx, ecx, edx);
2830 break;
2831 }
5e891bf8 2832 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 2833 *ebx = 0;
14c985cf
LM		 2834 if (!cpu->enable_l3_cache) {
2835 *ecx = 0;
2836 } else {
2837 *ecx = L3_N_DESCRIPTOR;
2838 }
5e891bf8
EH		 2839 *edx = (L1D_DESCRIPTOR << 16) | \
2840 (L1I_DESCRIPTOR << 8) | \
2841 (L2_DESCRIPTOR);
c6dc6f63
AP		 2842 break;
2843 case 4:
2844 /* cache info: needed for Core compatibility */
787aaf57
BC		 2845 if (cpu->cache_info_passthrough) {
2846 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2847 *eax &= ~0xFC000000;
c6dc6f63 2848 } else {
2f7a21c4 2849 *eax = 0;
76c2975a 2850 switch (count) {
c6dc6f63 2851 case 0: /* L1 dcache info */
5e891bf8
EH		 2852 *eax |= CPUID_4_TYPE_DCACHE | \
2853 CPUID_4_LEVEL(1) | \
2854 CPUID_4_SELF_INIT_LEVEL;
2855 *ebx = (L1D_LINE_SIZE - 1) | \
2856 ((L1D_PARTITIONS - 1) << 12) | \
2857 ((L1D_ASSOCIATIVITY - 1) << 22);
2858 *ecx = L1D_SETS - 1;
2859 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2860 break;
2861 case 1: /* L1 icache info */
5e891bf8
EH		 2862 *eax |= CPUID_4_TYPE_ICACHE | \
2863 CPUID_4_LEVEL(1) | \
2864 CPUID_4_SELF_INIT_LEVEL;
2865 *ebx = (L1I_LINE_SIZE - 1) | \
2866 ((L1I_PARTITIONS - 1) << 12) | \
2867 ((L1I_ASSOCIATIVITY - 1) << 22);
2868 *ecx = L1I_SETS - 1;
2869 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2870 break;
2871 case 2: /* L2 cache info */
5e891bf8
EH		 2872 *eax |= CPUID_4_TYPE_UNIFIED | \
2873 CPUID_4_LEVEL(2) | \
2874 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2875 if (cs->nr_threads > 1) {
2876 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2877 }
5e891bf8
EH		 2878 *ebx = (L2_LINE_SIZE - 1) | \
2879 ((L2_PARTITIONS - 1) << 12) | \
2880 ((L2_ASSOCIATIVITY - 1) << 22);
2881 *ecx = L2_SETS - 1;
2882 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63 2883 break;
14c985cf
LM		 2884 case 3: /* L3 cache info */
2885 if (!cpu->enable_l3_cache) {
2886 *eax = 0;
2887 *ebx = 0;
2888 *ecx = 0;
2889 *edx = 0;
2890 break;
2891 }
2892 *eax |= CPUID_4_TYPE_UNIFIED | \
2893 CPUID_4_LEVEL(3) | \
2894 CPUID_4_SELF_INIT_LEVEL;
2895 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2896 *eax |= ((1 << pkg_offset) - 1) << 14;
2897 *ebx = (L3_N_LINE_SIZE - 1) | \
2898 ((L3_N_PARTITIONS - 1) << 12) | \
2899 ((L3_N_ASSOCIATIVITY - 1) << 22);
2900 *ecx = L3_N_SETS - 1;
2901 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2902 break;
c6dc6f63
AP		 2903 default: /* end of info */
2904 *eax = 0;
2905 *ebx = 0;
2906 *ecx = 0;
2907 *edx = 0;
2908 break;
76c2975a
PB		 2909 }
2910 }
2911
2912 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2913 if ((*eax & 31) && cs->nr_cores > 1) {
2914 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2915 }
2916 break;
2917 case 5:
2918 /* mwait info: needed for Core compatibility */
2919 *eax = 0; /* Smallest monitor-line size in bytes */
2920 *ebx = 0; /* Largest monitor-line size in bytes */
2921 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2922 *edx = 0;
2923 break;
2924 case 6:
2925 /* Thermal and Power Leaf */
28b8e4d0 2926 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2927 *ebx = 0;
2928 *ecx = 0;
2929 *edx = 0;
2930 break;
f7911686 2931 case 7:
13526728
EH		 2932 /* Structured Extended Feature Flags Enumeration Leaf */
2933 if (count == 0) {
2934 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2935 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2936 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2937 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2938 *ecx |= CPUID_7_0_ECX_OSPKE;
2939 }
95ea69fb 2940 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 2941 } else {
2942 *eax = 0;
2943 *ebx = 0;
2944 *ecx = 0;
2945 *edx = 0;
2946 }
2947 break;
c6dc6f63
AP		 2948 case 9:
2949 /* Direct Cache Access Information Leaf */
2950 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2951 *ebx = 0;
2952 *ecx = 0;
2953 *edx = 0;
2954 break;
2955 case 0xA:
2956 /* Architectural Performance Monitoring Leaf */
9337e3b6 2957 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2958 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2959
2960 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2961 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2962 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2963 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 2964 } else if (hvf_enabled() && cpu->enable_pmu) {
2965 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
2966 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
2967 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
2968 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 2969 } else {
2970 *eax = 0;
2971 *ebx = 0;
2972 *ecx = 0;
2973 *edx = 0;
2974 }
c6dc6f63 2975 break;
5232d00a
RK		 2976 case 0xB:
2977 /* Extended Topology Enumeration Leaf */
2978 if (!cpu->enable_cpuid_0xb) {
2979 *eax = *ebx = *ecx = *edx = 0;
2980 break;
2981 }
2982
2983 *ecx = count & 0xff;
2984 *edx = cpu->apic_id;
2985
2986 switch (count) {
2987 case 0:
eab60fb9
MAL		 2988 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
2989 *ebx = cs->nr_threads;
5232d00a
RK		 2990 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2991 break;
2992 case 1:
eab60fb9
MAL		 2993 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2994 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 2995 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2996 break;
2997 default:
2998 *eax = 0;
2999 *ebx = 0;
3000 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
3001 }
3002
3003 assert(!(*eax & ~0x1f));
3004 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
3005 break;
2560f19f 3006 case 0xD: {
51e49430 3007 /* Processor Extended State */
2560f19f
PB		 3008 *eax = 0;
3009 *ebx = 0;
3010 *ecx = 0;
3011 *edx = 0;
19dc85db 3012 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 3013 break;
3014 }
4928cd6d 3015
2560f19f 3016 if (count == 0) {
96193c22
EH		 3017 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
3018 *eax = env->features[FEAT_XSAVE_COMP_LO];
3019 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 3020 *ebx = *ecx;
3021 } else if (count == 1) {
0bb0b2d2 3022 *eax = env->features[FEAT_XSAVE];
f4f1110e 3023 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 3024 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
3025 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 3026 *eax = esa->size;
3027 *ebx = esa->offset;
2560f19f 3028 }
51e49430
SY		 3029 }
3030 break;
2560f19f 3031 }
1ce36bfe
DB		 3032 case 0x40000000:
3033 /*
3034 * CPUID code in kvm_arch_init_vcpu() ignores stuff
3035 * set here, but we restrict to TCG none the less.
3036 */
3037 if (tcg_enabled() && cpu->expose_tcg) {
3038 memcpy(signature, "TCGTCGTCGTCG", 12);
3039 *eax = 0x40000001;
3040 *ebx = signature[0];
3041 *ecx = signature[1];
3042 *edx = signature[2];
3043 } else {
3044 *eax = 0;
3045 *ebx = 0;
3046 *ecx = 0;
3047 *edx = 0;
3048 }
3049 break;
3050 case 0x40000001:
3051 *eax = 0;
3052 *ebx = 0;
3053 *ecx = 0;
3054 *edx = 0;
3055 break;
c6dc6f63
AP		 3056 case 0x80000000:
3057 *eax = env->cpuid_xlevel;
3058 *ebx = env->cpuid_vendor1;
3059 *edx = env->cpuid_vendor2;
3060 *ecx = env->cpuid_vendor3;
3061 break;
3062 case 0x80000001:
3063 *eax = env->cpuid_version;
3064 *ebx = 0;
0514ef2f
EH		 3065 *ecx = env->features[FEAT_8000_0001_ECX];
3066 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 3067
3068 /* The Linux kernel checks for the CMPLegacy bit and
3069 * discards multiple thread information if it is set.
cb8d4c8f 3070 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 3071 */
ce3960eb 3072 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 3073 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
3074 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
3075 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 3076 *ecx |= 1 << 1; /* CmpLegacy bit */
3077 }
3078 }
c6dc6f63
AP		 3079 break;
3080 case 0x80000002:
3081 case 0x80000003:
3082 case 0x80000004:
3083 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
3084 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
3085 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
3086 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
3087 break;
3088 case 0x80000005:
3089 /* cache info (L1 cache) */
787aaf57
BC		 3090 if (cpu->cache_info_passthrough) {
3091 host_cpuid(index, 0, eax, ebx, ecx, edx);
3092 break;
3093 }
5e891bf8
EH		 3094 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
3095 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
3096 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
3097 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
3098 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
3099 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
3100 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
3101 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 3102 break;
3103 case 0x80000006:
3104 /* cache info (L2 cache) */
787aaf57
BC		 3105 if (cpu->cache_info_passthrough) {
3106 host_cpuid(index, 0, eax, ebx, ecx, edx);
3107 break;
3108 }
5e891bf8
EH		 3109 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
3110 (L2_DTLB_2M_ENTRIES << 16) | \
3111 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
3112 (L2_ITLB_2M_ENTRIES);
3113 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
3114 (L2_DTLB_4K_ENTRIES << 16) | \
3115 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
3116 (L2_ITLB_4K_ENTRIES);
3117 *ecx = (L2_SIZE_KB_AMD << 16) | \
3118 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
3119 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
14c985cf
LM		 3120 if (!cpu->enable_l3_cache) {
3121 *edx = ((L3_SIZE_KB / 512) << 18) | \
3122 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
3123 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
3124 } else {
3125 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
3126 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
3127 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
3128 }
c6dc6f63 3129 break;
303752a9
MT		 3130 case 0x80000007:
3131 *eax = 0;
3132 *ebx = 0;
3133 *ecx = 0;
3134 *edx = env->features[FEAT_8000_0007_EDX];
3135 break;
c6dc6f63
AP		 3136 case 0x80000008:
3137 /* virtual & phys address size in low 2 bytes. */
0514ef2f 3138 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 3139 /* 64 bit processor */
3140 *eax = cpu->phys_bits; /* configurable physical bits */
3141 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
3142 *eax |= 0x00003900; /* 57 bits virtual */
3143 } else {
3144 *eax |= 0x00003000; /* 48 bits virtual */
3145 }
c6dc6f63 3146 } else {
af45907a 3147 *eax = cpu->phys_bits;
c6dc6f63 3148 }
1b3420e1 3149 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 3150 *ecx = 0;
3151 *edx = 0;
ce3960eb
AF		 3152 if (cs->nr_cores * cs->nr_threads > 1) {
3153 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 3154 }
3155 break;
3156 case 0x8000000A:
0514ef2f 3157 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 3158 *eax = 0x00000001; /* SVM Revision */
3159 *ebx = 0x00000010; /* nr of ASIDs */
3160 *ecx = 0;
0514ef2f 3161 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 3162 } else {
3163 *eax = 0;
3164 *ebx = 0;
3165 *ecx = 0;
3166 *edx = 0;
3167 }
c6dc6f63 3168 break;
b3baa152
BW		 3169 case 0xC0000000:
3170 *eax = env->cpuid_xlevel2;
3171 *ebx = 0;
3172 *ecx = 0;
3173 *edx = 0;
3174 break;
3175 case 0xC0000001:
3176 /* Support for VIA CPU's CPUID instruction */
3177 *eax = env->cpuid_version;
3178 *ebx = 0;
3179 *ecx = 0;
0514ef2f 3180 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 3181 break;
3182 case 0xC0000002:
3183 case 0xC0000003:
3184 case 0xC0000004:
3185 /* Reserved for the future, and now filled with zero */
3186 *eax = 0;
3187 *ebx = 0;
3188 *ecx = 0;
3189 *edx = 0;
3190 break;
c6dc6f63
AP		 3191 default:
3192 /* reserved values: zero */
3193 *eax = 0;
3194 *ebx = 0;
3195 *ecx = 0;
3196 *edx = 0;
3197 break;
3198 }
3199}
5fd2087a
AF		 3200
3201/* CPUClass::reset() */
3202static void x86_cpu_reset(CPUState *s)
3203{
3204 X86CPU *cpu = X86_CPU(s);
3205 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
3206 CPUX86State *env = &cpu->env;
a114d25d
RH		 3207 target_ulong cr4;
3208 uint64_t xcr0;
c1958aea
AF		 3209 int i;
3210
5fd2087a
AF		 3211 xcc->parent_reset(s);
3212
5e992a8e 3213 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 3214
c1958aea
AF		 3215 env->old_exception = -1;
3216
3217 /* init to reset state */
3218
c1958aea
AF		 3219 env->hflags2 |= HF2_GIF_MASK;
3220
3221 cpu_x86_update_cr0(env, 0x60000010);
3222 env->a20_mask = ~0x0;
3223 env->smbase = 0x30000;
3224
3225 env->idt.limit = 0xffff;
3226 env->gdt.limit = 0xffff;
3227 env->ldt.limit = 0xffff;
3228 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
3229 env->tr.limit = 0xffff;
3230 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
3231
3232 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
3233 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
3234 DESC_R_MASK | DESC_A_MASK);
3235 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
3236 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3237 DESC_A_MASK);
3238 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
3239 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3240 DESC_A_MASK);
3241 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
3242 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3243 DESC_A_MASK);
3244 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
3245 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3246 DESC_A_MASK);
3247 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
3248 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3249 DESC_A_MASK);
3250
3251 env->eip = 0xfff0;
3252 env->regs[R_EDX] = env->cpuid_version;
3253
3254 env->eflags = 0x2;
3255
3256 /* FPU init */
3257 for (i = 0; i < 8; i++) {
3258 env->fptags[i] = 1;
3259 }
5bde1407 3260 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 3261
3262 env->mxcsr = 0x1f80;
a114d25d
RH		 3263 /* All units are in INIT state. */
3264 env->xstate_bv = 0;
c1958aea
AF		 3265
3266 env->pat = 0x0007040600070406ULL;
3267 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
3268
3269 memset(env->dr, 0, sizeof(env->dr));
3270 env->dr[6] = DR6_FIXED_1;
3271 env->dr[7] = DR7_FIXED_1;
b3310ab3 3272 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 3273 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 3274
a114d25d 3275 cr4 = 0;
cfc3b074 3276 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 3277
3278#ifdef CONFIG_USER_ONLY
3279 /* Enable all the features for user-mode. */
3280 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 3281 xcr0 |= XSTATE_SSE_MASK;
a114d25d 3282 }
0f70ed47
PB		 3283 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
3284 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 3285 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 3286 xcr0 |= 1ull << i;
3287 }
a114d25d 3288 }
0f70ed47 3289
a114d25d
RH		 3290 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
3291 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
3292 }
07929f2a
RH		 3293 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
3294 cr4 |= CR4_FSGSBASE_MASK;
3295 }
a114d25d
RH		 3296#endif
3297
3298 env->xcr0 = xcr0;
3299 cpu_x86_update_cr4(env, cr4);
0522604b 3300
9db2efd9
AW		 3301 /*
3302 * SDM 11.11.5 requires:
3303 * - IA32_MTRR_DEF_TYPE MSR.E = 0
3304 * - IA32_MTRR_PHYSMASKn.V = 0
3305 * All other bits are undefined. For simplification, zero it all.
3306 */
3307 env->mtrr_deftype = 0;
3308 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
3309 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
3310
b7394c83
SAGDR		 3311 env->interrupt_injected = -1;
3312 env->exception_injected = -1;
3313 env->nmi_injected = false;
dd673288
IM		 3314#if !defined(CONFIG_USER_ONLY)
3315 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 3316 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 3317
259186a7 3318 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 3319
3320 if (kvm_enabled()) {
3321 kvm_arch_reset_vcpu(cpu);
3322 }
d6dcc558
SAGDR		 3323 else if (hvf_enabled()) {
3324 hvf_reset_vcpu(s);
3325 }
dd673288 3326#endif
5fd2087a
AF		 3327}
3328
dd673288
IM		 3329#ifndef CONFIG_USER_ONLY
3330bool cpu_is_bsp(X86CPU *cpu)
3331{
02e51483 3332 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 3333}
65dee380
IM		 3334
3335/* TODO: remove me, when reset over QOM tree is implemented */
3336static void x86_cpu_machine_reset_cb(void *opaque)
3337{
3338 X86CPU *cpu = opaque;
3339 cpu_reset(CPU(cpu));
3340}
dd673288
IM		 3341#endif
3342
de024815
AF		 3343static void mce_init(X86CPU *cpu)
3344{
3345 CPUX86State *cenv = &cpu->env;
3346 unsigned int bank;
3347
3348 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 3349 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 3350 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 3351 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
3352 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 3353 cenv->mcg_ctl = ~(uint64_t)0;
3354 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
3355 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
3356 }
3357 }
3358}
3359
bdeec802 3360#ifndef CONFIG_USER_ONLY
2f114315 3361APICCommonClass *apic_get_class(void)
bdeec802 3362{
bdeec802
IM		 3363 const char *apic_type = "apic";
3364
d6dcc558 3365 /* TODO: in-kernel irqchip for hvf */
15eafc2e 3366 if (kvm_apic_in_kernel()) {
bdeec802
IM		 3367 apic_type = "kvm-apic";
3368 } else if (xen_enabled()) {
3369 apic_type = "xen-apic";
3370 }
3371
2f114315
RK		 3372 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
3373}
3374
3375static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
3376{
3377 APICCommonState *apic;
3378 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
3379
3380 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 3381
6816b1b3
IM		 3382 object_property_add_child(OBJECT(cpu), "lapic",
3383 OBJECT(cpu->apic_state), &error_abort);
67e55caa 3384 object_unref(OBJECT(cpu->apic_state));
6816b1b3 3385
33d7a288 3386 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 3387 /* TODO: convert to link<> */
02e51483 3388 apic = APIC_COMMON(cpu->apic_state);
60671e58 3389 apic->cpu = cpu;
8d42d2d3 3390 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 3391}
3392
3393static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3394{
8d42d2d3
CF		 3395 APICCommonState *apic;
3396 static bool apic_mmio_map_once;
3397
02e51483 3398 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 3399 return;
3400 }
6e8e2651
MA		 3401 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
3402 errp);
8d42d2d3
CF		 3403
3404 /* Map APIC MMIO area */
3405 apic = APIC_COMMON(cpu->apic_state);
3406 if (!apic_mmio_map_once) {
3407 memory_region_add_subregion_overlap(get_system_memory(),
3408 apic->apicbase &
3409 MSR_IA32_APICBASE_BASE,
3410 &apic->io_memory,
3411 0x1000);
3412 apic_mmio_map_once = true;
3413 }
bdeec802 3414}
f809c605
PB		 3415
3416static void x86_cpu_machine_done(Notifier *n, void *unused)
3417{
3418 X86CPU *cpu = container_of(n, X86CPU, machine_done);
3419 MemoryRegion *smram =
3420 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
3421
3422 if (smram) {
3423 cpu->smram = g_new(MemoryRegion, 1);
3424 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
3425 smram, 0, 1ull << 32);
f8c45c65 3426 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 3427 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
3428 }
3429}
d3c64d6a
IM		 3430#else
3431static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3432{
3433}
bdeec802
IM		 3434#endif
3435
11f6fee5
DDAG		 3436/* Note: Only safe for use on x86(-64) hosts */
3437static uint32_t x86_host_phys_bits(void)
3438{
3439 uint32_t eax;
3440 uint32_t host_phys_bits;
3441
3442 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
3443 if (eax >= 0x80000008) {
3444 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
3445 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3446 * at 23:16 that can specify a maximum physical address bits for
3447 * the guest that can override this value; but I've not seen
3448 * anything with that set.
3449 */
3450 host_phys_bits = eax & 0xff;
3451 } else {
3452 /* It's an odd 64 bit machine that doesn't have the leaf for
3453 * physical address bits; fall back to 36 that's most older
3454 * Intel.
3455 */
3456 host_phys_bits = 36;
3457 }
3458
3459 return host_phys_bits;
3460}
e48638fd 3461
c39c0edf
EH		 3462static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
3463{
3464 if (*min < value) {
3465 *min = value;
3466 }
3467}
3468
3469/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3470static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
3471{
3472 CPUX86State *env = &cpu->env;
3473 FeatureWordInfo *fi = &feature_word_info[w];
3474 uint32_t eax = fi->cpuid_eax;
3475 uint32_t region = eax & 0xF0000000;
3476
3477 if (!env->features[w]) {
3478 return;
3479 }
3480
3481 switch (region) {
3482 case 0x00000000:
3483 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
3484 break;
3485 case 0x80000000:
3486 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
3487 break;
3488 case 0xC0000000:
3489 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
3490 break;
3491 }
3492}
3493
2ca8a8be
EH		 3494/* Calculate XSAVE components based on the configured CPU feature flags */
3495static void x86_cpu_enable_xsave_components(X86CPU *cpu)
3496{
3497 CPUX86State *env = &cpu->env;
3498 int i;
96193c22 3499 uint64_t mask;
2ca8a8be
EH		 3500
3501 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
3502 return;
3503 }
3504
e3c9022b
EH		 3505 mask = 0;
3506 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 3507 const ExtSaveArea *esa = &x86_ext_save_areas[i];
3508 if (env->features[esa->feature] & esa->bits) {
96193c22 3509 mask |= (1ULL << i);
2ca8a8be
EH		 3510 }
3511 }
3512
96193c22
EH		 3513 env->features[FEAT_XSAVE_COMP_LO] = mask;
3514 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 3515}
3516
b8d834a0
EH		 3517/***** Steps involved on loading and filtering CPUID data
3518 *
3519 * When initializing and realizing a CPU object, the steps
3520 * involved in setting up CPUID data are:
3521 *
3522 * 1) Loading CPU model definition (X86CPUDefinition). This is
3523 * implemented by x86_cpu_load_def() and should be completely
3524 * transparent, as it is done automatically by instance_init.
3525 * No code should need to look at X86CPUDefinition structs
3526 * outside instance_init.
3527 *
3528 * 2) CPU expansion. This is done by realize before CPUID
3529 * filtering, and will make sure host/accelerator data is
3530 * loaded for CPU models that depend on host capabilities
3531 * (e.g. "host"). Done by x86_cpu_expand_features().
3532 *
3533 * 3) CPUID filtering. This initializes extra data related to
3534 * CPUID, and checks if the host supports all capabilities
3535 * required by the CPU. Runnability of a CPU model is
3536 * determined at this step. Done by x86_cpu_filter_features().
3537 *
3538 * Some operations don't require all steps to be performed.
3539 * More precisely:
3540 *
3541 * - CPU instance creation (instance_init) will run only CPU
3542 * model loading. CPU expansion can't run at instance_init-time
3543 * because host/accelerator data may be not available yet.
3544 * - CPU realization will perform both CPU model expansion and CPUID
3545 * filtering, and return an error in case one of them fails.
3546 * - query-cpu-definitions needs to run all 3 steps. It needs
3547 * to run CPUID filtering, as the 'unavailable-features'
3548 * field is set based on the filtering results.
3549 * - The query-cpu-model-expansion QMP command only needs to run
3550 * CPU model loading and CPU expansion. It should not filter
3551 * any CPUID data based on host capabilities.
3552 */
3553
3554/* Expand CPU configuration data, based on configured features
3555 * and host/accelerator capabilities when appropriate.
3556 */
3557static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 3558{
b34d12d1 3559 CPUX86State *env = &cpu->env;
dc15c051 3560 FeatureWord w;
2fae0d96 3561 GList *l;
41f3d4d6 3562 Error *local_err = NULL;
9886e834 3563
d4a606b3
EH		 3564 /*TODO: Now cpu->max_features doesn't overwrite features
3565 * set using QOM properties, and we can convert
dc15c051
IM		 3566 * plus_features & minus_features to global properties
3567 * inside x86_cpu_parse_featurestr() too.
3568 */
44bd8e53 3569 if (cpu->max_features) {
dc15c051 3570 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 3571 /* Override only features that weren't set explicitly
3572 * by the user.
3573 */
3574 env->features[w] |=
3575 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
3576 ~env->user_features[w];
dc15c051
IM		 3577 }
3578 }
3579
2fae0d96
EH		 3580 for (l = plus_features; l; l = l->next) {
3581 const char *prop = l->data;
3582 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
3583 if (local_err) {
3584 goto out;
3585 }
3586 }
3587
3588 for (l = minus_features; l; l = l->next) {
3589 const char *prop = l->data;
3590 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
3591 if (local_err) {
3592 goto out;
3593 }
dc15c051
IM		 3594 }
3595
aec661de
EH		 3596 if (!kvm_enabled() || !cpu->expose_kvm) {
3597 env->features[FEAT_KVM] = 0;
3598 }
3599
2ca8a8be 3600 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 3601
3602 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3603 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
3604 if (cpu->full_cpuid_auto_level) {
3605 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
3606 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
3607 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
3608 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
3609 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
3610 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
3611 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 3612 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 3613 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
3614 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
3615 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 3616 /* SVM requires CPUID[0x8000000A] */
3617 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
3618 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
3619 }
c39c0edf
EH		 3620 }
3621
3622 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3623 if (env->cpuid_level == UINT32_MAX) {
3624 env->cpuid_level = env->cpuid_min_level;
3625 }
3626 if (env->cpuid_xlevel == UINT32_MAX) {
3627 env->cpuid_xlevel = env->cpuid_min_xlevel;
3628 }
3629 if (env->cpuid_xlevel2 == UINT32_MAX) {
3630 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 3631 }
7a059953 3632
41f3d4d6
EH		 3633out:
3634 if (local_err != NULL) {
3635 error_propagate(errp, local_err);
3636 }
3637}
3638
b8d834a0
EH		 3639/*
3640 * Finishes initialization of CPUID data, filters CPU feature
3641 * words based on host availability of each feature.
3642 *
3643 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
3644 */
3645static int x86_cpu_filter_features(X86CPU *cpu)
3646{
3647 CPUX86State *env = &cpu->env;
3648 FeatureWord w;
3649 int rv = 0;
3650
3651 for (w = 0; w < FEATURE_WORDS; w++) {
3652 uint32_t host_feat =
3653 x86_cpu_get_supported_feature_word(w, false);
3654 uint32_t requested_features = env->features[w];
3655 env->features[w] &= host_feat;
3656 cpu->filtered_features[w] = requested_features & ~env->features[w];
3657 if (cpu->filtered_features[w]) {
3658 rv = 1;
3659 }
3660 }
3661
3662 return rv;
3663}
3664
41f3d4d6
EH		 3665#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3666 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3667 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3668#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3669 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3670 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
3671static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
3672{
3673 CPUState *cs = CPU(dev);
3674 X86CPU *cpu = X86_CPU(dev);
3675 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3676 CPUX86State *env = &cpu->env;
3677 Error *local_err = NULL;
3678 static bool ht_warned;
3679
d6dcc558 3680 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
41f3d4d6
EH		 3681 char *name = x86_cpu_class_get_model_name(xcc);
3682 error_setg(&local_err, "CPU model '%s' requires KVM", name);
3683 g_free(name);
3684 goto out;
3685 }
3686
3687 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
3688 error_setg(errp, "apic-id property was not initialized properly");
3689 return;
3690 }
3691
b8d834a0 3692 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 3693 if (local_err) {
3694 goto out;
3695 }
3696
8ca30e86
EH		 3697 if (x86_cpu_filter_features(cpu) &&
3698 (cpu->check_cpuid || cpu->enforce_cpuid)) {
3699 x86_cpu_report_filtered_features(cpu);
3700 if (cpu->enforce_cpuid) {
3701 error_setg(&local_err,
d6dcc558 3702 accel_uses_host_cpuid() ?
8ca30e86
EH		 3703 "Host doesn't support requested features" :
3704 "TCG doesn't support requested features");
3705 goto out;
3706 }
9997cf7b
EH		 3707 }
3708
9b15cd9e
IM		 3709 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3710 * CPUID[1].EDX.
3711 */
e48638fd 3712 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 3713 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3714 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 3715 & CPUID_EXT2_AMD_ALIASES);
3716 }
3717
11f6fee5
DDAG		 3718 /* For 64bit systems think about the number of physical bits to present.
3719 * ideally this should be the same as the host; anything other than matching
3720 * the host can cause incorrect guest behaviour.
3721 * QEMU used to pick the magic value of 40 bits that corresponds to
3722 * consumer AMD devices but nothing else.
3723 */
af45907a 3724 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 3725 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 3726 uint32_t host_phys_bits = x86_host_phys_bits();
3727 static bool warned;
3728
3729 if (cpu->host_phys_bits) {
3730 /* The user asked for us to use the host physical bits */
3731 cpu->phys_bits = host_phys_bits;
3732 }
3733
3734 /* Print a warning if the user set it to a value that's not the
3735 * host value.
3736 */
3737 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3738 !warned) {
3dc6f869
AF		 3739 warn_report("Host physical bits (%u)"
3740 " does not match phys-bits property (%u)",
3741 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 3742 warned = true;
3743 }
3744
3745 if (cpu->phys_bits &&
3746 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3747 cpu->phys_bits < 32)) {
af45907a
DDAG		 3748 error_setg(errp, "phys-bits should be between 32 and %u "
3749 " (but is %u)",
3750 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3751 return;
3752 }
3753 } else {
11f6fee5 3754 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 3755 error_setg(errp, "TCG only supports phys-bits=%u",
3756 TCG_PHYS_ADDR_BITS);
3757 return;
3758 }
3759 }
11f6fee5
DDAG		 3760 /* 0 means it was not explicitly set by the user (or by machine
3761 * compat_props or by the host code above). In this case, the default
3762 * is the value used by TCG (40).
3763 */
3764 if (cpu->phys_bits == 0) {
3765 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3766 }
af45907a
DDAG		 3767 } else {
3768 /* For 32 bit systems don't use the user set value, but keep
3769 * phys_bits consistent with what we tell the guest.
3770 */
3771 if (cpu->phys_bits != 0) {
3772 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3773 return;
3774 }
fefb41bf 3775
af45907a
DDAG		 3776 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3777 cpu->phys_bits = 36;
3778 } else {
3779 cpu->phys_bits = 32;
3780 }
3781 }
ce5b1bbf
LV		 3782 cpu_exec_realizefn(cs, &local_err);
3783 if (local_err != NULL) {
3784 error_propagate(errp, local_err);
3785 return;
3786 }
42ecabaa 3787
65dee380
IM		 3788#ifndef CONFIG_USER_ONLY
3789 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 3790
0514ef2f 3791 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 3792 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 3793 if (local_err != NULL) {
4dc1f449 3794 goto out;
bdeec802
IM		 3795 }
3796 }
65dee380
IM		 3797#endif
3798
7a059953 3799 mce_init(cpu);
2001d0cd
PB		 3800
3801#ifndef CONFIG_USER_ONLY
3802 if (tcg_enabled()) {
f809c605 3803 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 3804 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 3805
3806 /* Outer container... */
3807 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 3808 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 3809
3810 /* ... with two regions inside: normal system memory with low
3811 * priority, and...
3812 */
3813 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3814 get_system_memory(), 0, ~0ull);
3815 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3816 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 3817
3818 cs->num_ases = 2;
80ceb07a
PX		 3819 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
3820 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 3821
3822 /* ... SMRAM with higher priority, linked from /machine/smram. */
3823 cpu->machine_done.notify = x86_cpu_machine_done;
3824 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 3825 }
3826#endif
3827
14a10fc3 3828 qemu_init_vcpu(cs);
d3c64d6a 3829
e48638fd
WH		 3830 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3831 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3832 * based on inputs (sockets,cores,threads), it is still better to gives
3833 * users a warning.
3834 *
3835 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3836 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3837 */
3838 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3839 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3840 " -smp options properly.");
3841 ht_warned = true;
3842 }
3843
d3c64d6a
IM		 3844 x86_cpu_apic_realize(cpu, &local_err);
3845 if (local_err != NULL) {
3846 goto out;
3847 }
14a10fc3 3848 cpu_reset(cs);
2b6f294c 3849
4dc1f449 3850 xcc->parent_realize(dev, &local_err);
2001d0cd 3851
4dc1f449
IM		 3852out:
3853 if (local_err != NULL) {
3854 error_propagate(errp, local_err);
3855 return;
3856 }
7a059953
AF		 3857}
3858
c884776e
IM		 3859static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3860{
3861 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 3862 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3863 Error *local_err = NULL;
c884776e
IM		 3864
3865#ifndef CONFIG_USER_ONLY
3866 cpu_remove_sync(CPU(dev));
3867 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3868#endif
3869
3870 if (cpu->apic_state) {
3871 object_unparent(OBJECT(cpu->apic_state));
3872 cpu->apic_state = NULL;
3873 }
7bbc124e
LV		 3874
3875 xcc->parent_unrealize(dev, &local_err);
3876 if (local_err != NULL) {
3877 error_propagate(errp, local_err);
3878 return;
3879 }
c884776e
IM		 3880}
3881
38e5c119 3882typedef struct BitProperty {
a7b0ffac 3883 FeatureWord w;
38e5c119
EH		 3884 uint32_t mask;
3885} BitProperty;
3886
d7bce999
EB		 3887static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3888 void *opaque, Error **errp)
38e5c119 3889{
a7b0ffac 3890 X86CPU *cpu = X86_CPU(obj);
38e5c119 3891 BitProperty *fp = opaque;
a7b0ffac
EH		 3892 uint32_t f = cpu->env.features[fp->w];
3893 bool value = (f & fp->mask) == fp->mask;
51e72bc1 3894 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3895}
3896
d7bce999
EB		 3897static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3898 void *opaque, Error **errp)
38e5c119
EH		 3899{
3900 DeviceState *dev = DEVICE(obj);
a7b0ffac 3901 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 3902 BitProperty *fp = opaque;
3903 Error *local_err = NULL;
3904 bool value;
3905
3906 if (dev->realized) {
3907 qdev_prop_set_after_realize(dev, name, errp);
3908 return;
3909 }
3910
51e72bc1 3911 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3912 if (local_err) {
3913 error_propagate(errp, local_err);
3914 return;
3915 }
3916
3917 if (value) {
a7b0ffac 3918 cpu->env.features[fp->w] |= fp->mask;
38e5c119 3919 } else {
a7b0ffac 3920 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 3921 }
d4a606b3 3922 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 3923}
3924
3925static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3926 void *opaque)
3927{
3928 BitProperty *prop = opaque;
3929 g_free(prop);
3930}
3931
3932/* Register a boolean property to get/set a single bit in a uint32_t field.
3933 *
3934 * The same property name can be registered multiple times to make it affect
3935 * multiple bits in the same FeatureWord. In that case, the getter will return
3936 * true only if all bits are set.
3937 */
3938static void x86_cpu_register_bit_prop(X86CPU *cpu,
3939 const char *prop_name,
a7b0ffac 3940 FeatureWord w,
38e5c119
EH		 3941 int bitnr)
3942{
3943 BitProperty *fp;
3944 ObjectProperty *op;
3945 uint32_t mask = (1UL << bitnr);
3946
3947 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3948 if (op) {
3949 fp = op->opaque;
a7b0ffac 3950 assert(fp->w == w);
38e5c119
EH		 3951 fp->mask |= mask;
3952 } else {
3953 fp = g_new0(BitProperty, 1);
a7b0ffac 3954 fp->w = w;
38e5c119
EH		 3955 fp->mask = mask;
3956 object_property_add(OBJECT(cpu), prop_name, "bool",
3957 x86_cpu_get_bit_prop,
3958 x86_cpu_set_bit_prop,
3959 x86_cpu_release_bit_prop, fp, &error_abort);
3960 }
3961}
3962
3963static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3964 FeatureWord w,
3965 int bitnr)
3966{
38e5c119 3967 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 3968 const char *name = fi->feat_names[bitnr];
38e5c119 3969
16d2fcaa 3970 if (!name) {
38e5c119
EH		 3971 return;
3972 }
3973
fc7dfd20
EH		 3974 /* Property names should use "-" instead of "_".
3975 * Old names containing underscores are registered as aliases
3976 * using object_property_add_alias()
3977 */
16d2fcaa
EH		 3978 assert(!strchr(name, '_'));
3979 /* aliases don't use "|" delimiters anymore, they are registered
3980 * manually using object_property_add_alias() */
3981 assert(!strchr(name, '|'));
a7b0ffac 3982 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 3983}
3984
d187e08d
AN		 3985static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
3986{
3987 X86CPU *cpu = X86_CPU(cs);
3988 CPUX86State *env = &cpu->env;
3989 GuestPanicInformation *panic_info = NULL;
3990
5e953812 3991 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 3992 panic_info = g_malloc0(sizeof(GuestPanicInformation));
3993
e8ed97a6 3994 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 3995
5e953812 3996 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 3997 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
3998 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
3999 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
4000 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
4001 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 4002 }
4003
4004 return panic_info;
4005}
4006static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
4007 const char *name, void *opaque,
4008 Error **errp)
4009{
4010 CPUState *cs = CPU(obj);
4011 GuestPanicInformation *panic_info;
4012
4013 if (!cs->crash_occurred) {
4014 error_setg(errp, "No crash occured");
4015 return;
4016 }
4017
4018 panic_info = x86_cpu_get_crash_info(cs);
4019 if (panic_info == NULL) {
4020 error_setg(errp, "No crash information");
4021 return;
4022 }
4023
4024 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
4025 errp);
4026 qapi_free_GuestPanicInformation(panic_info);
4027}
4028
de024815
AF		 4029static void x86_cpu_initfn(Object *obj)
4030{
55e5c285 4031 CPUState *cs = CPU(obj);
de024815 4032 X86CPU *cpu = X86_CPU(obj);
d940ee9b 4033 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 4034 CPUX86State *env = &cpu->env;
38e5c119 4035 FeatureWord w;
de024815 4036
c05efcb1 4037 cs->env_ptr = env;
71ad61d3
AF		 4038
4039 object_property_add(obj, "family", "int",
95b8519d 4040 x86_cpuid_version_get_family,
71ad61d3 4041 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 4042 object_property_add(obj, "model", "int",
67e30c83 4043 x86_cpuid_version_get_model,
c5291a4f 4044 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 4045 object_property_add(obj, "stepping", "int",
35112e41 4046 x86_cpuid_version_get_stepping,
036e2222 4047 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 4048 object_property_add_str(obj, "vendor",
4049 x86_cpuid_get_vendor,
4050 x86_cpuid_set_vendor, NULL);
938d4c25 4051 object_property_add_str(obj, "model-id",
63e886eb 4052 x86_cpuid_get_model_id,
938d4c25 4053 x86_cpuid_set_model_id, NULL);
89e48965
AF		 4054 object_property_add(obj, "tsc-frequency", "int",
4055 x86_cpuid_get_tsc_freq,
4056 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 4057 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
4058 x86_cpu_get_feature_words,
7e5292b5
EH		 4059 NULL, NULL, (void *)env->features, NULL);
4060 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
4061 x86_cpu_get_feature_words,
4062 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 4063
d187e08d
AN		 4064 object_property_add(obj, "crash-information", "GuestPanicInformation",
4065 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
4066
92067bf4 4067 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 4068
38e5c119
EH		 4069 for (w = 0; w < FEATURE_WORDS; w++) {
4070 int bitnr;
4071
4072 for (bitnr = 0; bitnr < 32; bitnr++) {
4073 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
4074 }
4075 }
4076
16d2fcaa
EH		 4077 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
4078 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
4079 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
4080 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
4081 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
4082 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
4083 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
4084
54b8dc7c
EH		 4085 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
4086 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
4087 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
4088 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
4089 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
4090 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
4091 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
4092 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
4093 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
4094 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
4095 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
4096 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
4097 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
4098 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
4099 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
4100 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
4101 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
4102 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
4103 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
4104 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
4105 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
4106
0bacd8b3
EH		 4107 if (xcc->cpu_def) {
4108 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
4109 }
de024815
AF		 4110}
4111
997395d3
IM		 4112static int64_t x86_cpu_get_arch_id(CPUState *cs)
4113{
4114 X86CPU *cpu = X86_CPU(cs);
997395d3 4115
7e72a45c 4116 return cpu->apic_id;
997395d3
IM		 4117}
4118
444d5590
AF		 4119static bool x86_cpu_get_paging_enabled(const CPUState *cs)
4120{
4121 X86CPU *cpu = X86_CPU(cs);
4122
4123 return cpu->env.cr[0] & CR0_PG_MASK;
4124}
4125
f45748f1
AF		 4126static void x86_cpu_set_pc(CPUState *cs, vaddr value)
4127{
4128 X86CPU *cpu = X86_CPU(cs);
4129
4130 cpu->env.eip = value;
4131}
4132
bdf7ae5b
AF		 4133static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
4134{
4135 X86CPU *cpu = X86_CPU(cs);
4136
4137 cpu->env.eip = tb->pc - tb->cs_base;
4138}
4139
8c2e1b00
AF		 4140static bool x86_cpu_has_work(CPUState *cs)
4141{
4142 X86CPU *cpu = X86_CPU(cs);
4143 CPUX86State *env = &cpu->env;
4144
6220e900
PD		 4145 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
4146 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 4147 (env->eflags & IF_MASK)) ||
4148 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
4149 CPU_INTERRUPT_INIT |
4150 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 4151 CPU_INTERRUPT_MCE)) ||
4152 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
4153 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 4154}
4155
f50f3dd5
RH		 4156static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
4157{
4158 X86CPU *cpu = X86_CPU(cs);
4159 CPUX86State *env = &cpu->env;
4160
4161 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
4162 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
4163 : bfd_mach_i386_i8086);
4164 info->print_insn = print_insn_i386;
b666d2a4
RH		 4165
4166 info->cap_arch = CS_ARCH_X86;
4167 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
4168 : env->hflags & HF_CS32_MASK ? CS_MODE_32
4169 : CS_MODE_16);
15fa1a0a
RH		 4170 info->cap_insn_unit = 1;
4171 info->cap_insn_split = 8;
f50f3dd5
RH		 4172}
4173
35b1b927
TW		 4174void x86_update_hflags(CPUX86State *env)
4175{
4176 uint32_t hflags;
4177#define HFLAG_COPY_MASK \
4178 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
4179 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
4180 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
4181 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
4182
4183 hflags = env->hflags & HFLAG_COPY_MASK;
4184 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
4185 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
4186 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
4187 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
4188 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
4189
4190 if (env->cr[4] & CR4_OSFXSR_MASK) {
4191 hflags |= HF_OSFXSR_MASK;
4192 }
4193
4194 if (env->efer & MSR_EFER_LMA) {
4195 hflags |= HF_LMA_MASK;
4196 }
4197
4198 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
4199 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
4200 } else {
4201 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
4202 (DESC_B_SHIFT - HF_CS32_SHIFT);
4203 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
4204 (DESC_B_SHIFT - HF_SS32_SHIFT);
4205 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
4206 !(hflags & HF_CS32_MASK)) {
4207 hflags |= HF_ADDSEG_MASK;
4208 } else {
4209 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
4210 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
4211 }
4212 }
4213 env->hflags = hflags;
4214}
4215
9337e3b6 4216static Property x86_cpu_properties[] = {
2da00e31
IM		 4217#ifdef CONFIG_USER_ONLY
4218 /* apic_id = 0 by default for *-user, see commit 9886e834 */
4219 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 4220 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
4221 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
4222 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 4223#else
4224 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 4225 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
4226 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
4227 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 4228#endif
15f8b142 4229 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 4230 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 4231 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 4232 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 4233 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 4234 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 4235 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 4236 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 4237 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 4238 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 4239 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 4240 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 4241 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 4242 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 4243 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 4244 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 4245 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 4246 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 4247 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
4248 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
4249 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
4250 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
4251 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
4252 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4253 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 4254 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 4255 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 4256 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 4257 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 4258 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
4259 false),
0b564e6f 4260 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 4261 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
6c69dfb6
GA		 4262
4263 /*
4264 * From "Requirements for Implementing the Microsoft
4265 * Hypervisor Interface":
4266 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
4267 *
4268 * "Starting with Windows Server 2012 and Windows 8, if
4269 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
4270 * the hypervisor imposes no specific limit to the number of VPs.
4271 * In this case, Windows Server 2012 guest VMs may use more than
4272 * 64 VPs, up to the maximum supported number of processors applicable
4273 * to the specific Windows version being used."
4274 */
4275 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9337e3b6
EH		 4276 DEFINE_PROP_END_OF_LIST()
4277};
4278
5fd2087a
AF		 4279static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
4280{
4281 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4282 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 4283 DeviceClass *dc = DEVICE_CLASS(oc);
4284
4285 xcc->parent_realize = dc->realize;
7bbc124e 4286 xcc->parent_unrealize = dc->unrealize;
2b6f294c 4287 dc->realize = x86_cpu_realizefn;
c884776e 4288 dc->unrealize = x86_cpu_unrealizefn;
9337e3b6 4289 dc->props = x86_cpu_properties;
5fd2087a
AF		 4290
4291 xcc->parent_reset = cc->reset;
4292 cc->reset = x86_cpu_reset;
91b1df8c 4293 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 4294
500050d1 4295 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 4296 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 4297 cc->has_work = x86_cpu_has_work;
79c664f6 4298#ifdef CONFIG_TCG
97a8ea5a 4299 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 4300 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 4301#endif
878096ee 4302 cc->dump_state = x86_cpu_dump_state;
c86f106b 4303 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 4304 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 4305 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 4306 cc->gdb_read_register = x86_cpu_gdb_read_register;
4307 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 4308 cc->get_arch_id = x86_cpu_get_arch_id;
4309 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 4310#ifdef CONFIG_USER_ONLY
4311 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
4312#else
f8c45c65 4313 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 4314 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 4315 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 4316 cc->write_elf64_note = x86_cpu_write_elf64_note;
4317 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
4318 cc->write_elf32_note = x86_cpu_write_elf32_note;
4319 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 4320 cc->vmsd = &vmstate_x86_cpu;
c72bf468 4321#endif
00fcd100
AB		 4322 cc->gdb_arch_name = x86_gdb_arch_name;
4323#ifdef TARGET_X86_64
b8158192
AB		 4324 cc->gdb_core_xml_file = "i386-64bit.xml";
4325 cc->gdb_num_core_regs = 57;
00fcd100 4326#else
b8158192
AB		 4327 cc->gdb_core_xml_file = "i386-32bit.xml";
4328 cc->gdb_num_core_regs = 41;
00fcd100 4329#endif
79c664f6 4330#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 4331 cc->debug_excp_handler = breakpoint_handler;
4332#endif
374e0cd4
RH		 4333 cc->cpu_exec_enter = x86_cpu_exec_enter;
4334 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 4335#ifdef CONFIG_TCG
55c3ceef 4336 cc->tcg_initialize = tcg_x86_init;
74d7fc7f 4337#endif
f50f3dd5 4338 cc->disas_set_info = x86_disas_set_info;
4c315c27 4339
e90f2a8c 4340 dc->user_creatable = true;
5fd2087a
AF		 4341}
4342
4343static const TypeInfo x86_cpu_type_info = {
4344 .name = TYPE_X86_CPU,
4345 .parent = TYPE_CPU,
4346 .instance_size = sizeof(X86CPU),
de024815 4347 .instance_init = x86_cpu_initfn,
d940ee9b 4348 .abstract = true,
5fd2087a
AF		 4349 .class_size = sizeof(X86CPUClass),
4350 .class_init = x86_cpu_common_class_init,
4351};
4352
5adbed30
EH		 4353
4354/* "base" CPU model, used by query-cpu-model-expansion */
4355static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
4356{
4357 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4358
4359 xcc->static_model = true;
4360 xcc->migration_safe = true;
4361 xcc->model_description = "base CPU model type with no features enabled";
4362 xcc->ordering = 8;
4363}
4364
4365static const TypeInfo x86_base_cpu_type_info = {
4366 .name = X86_CPU_TYPE_NAME("base"),
4367 .parent = TYPE_X86_CPU,
4368 .class_init = x86_cpu_base_class_init,
4369};
4370
5fd2087a
AF		 4371static void x86_cpu_register_types(void)
4372{
d940ee9b
EH		 4373 int i;
4374
5fd2087a 4375 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 4376 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
4377 x86_register_cpudef_type(&builtin_x86_defs[i]);
4378 }
c62f2630 4379 type_register_static(&max_x86_cpu_type_info);
5adbed30 4380 type_register_static(&x86_base_cpu_type_info);
d6dcc558 4381#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 4382 type_register_static(&host_x86_cpu_type_info);
4383#endif
5fd2087a
AF		 4384}
4385
4386type_init(x86_cpu_register_types)
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