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target-i386: add KVM_HINTS_DEDICATED performance hint
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
f348b6d1 21#include "qemu/cutils.h"
c6dc6f63
AP		 22
23#include "cpu.h"
63c91552 24#include "exec/exec-all.h"
9c17d615 25#include "sysemu/kvm.h"
d6dcc558 26#include "sysemu/hvf.h"
8932cfdf 27#include "sysemu/cpus.h"
50a2c6e5 28#include "kvm_i386.h"
c6dc6f63 29
d49b6836 30#include "qemu/error-report.h"
1de7afc9
PB		 31#include "qemu/option.h"
32#include "qemu/config-file.h"
e688df6b 33#include "qapi/error.h"
112ed241
MA		 34#include "qapi/qapi-visit-misc.h"
35#include "qapi/qapi-visit-run-state.h"
452fcdbc 36#include "qapi/qmp/qdict.h"
7b1b5d19 37#include "qapi/qmp/qerror.h"
7b1b5d19 38#include "qapi/visitor.h"
f99fd7ca 39#include "qom/qom-qobject.h"
9c17d615 40#include "sysemu/arch_init.h"
71ad61d3 41
b834b508 42#if defined(CONFIG_KVM)
ef8621b1 43#include <linux/kvm_para.h>
b834b508 44#endif
65dee380 45
9c17d615 46#include "sysemu/sysemu.h"
53a89e26 47#include "hw/qdev-properties.h"
5232d00a 48#include "hw/i386/topology.h"
bdeec802 49#ifndef CONFIG_USER_ONLY
2001d0cd 50#include "exec/address-spaces.h"
741da0d3 51#include "hw/hw.h"
0d09e41a 52#include "hw/xen/xen.h"
0d09e41a 53#include "hw/i386/apic_internal.h"
bdeec802
IM		 54#endif
55
b666d2a4
RH		 56#include "disas/capstone.h"
57
5e891bf8
EH		 58
59/* Cache topology CPUID constants: */
60
61/* CPUID Leaf 2 Descriptors */
62
63#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
64#define CPUID_2_L1I_32KB_8WAY_64B 0x30
65#define CPUID_2_L2_2MB_8WAY_64B 0x7d
14c985cf 66#define CPUID_2_L3_16MB_16WAY_64B 0x4d
5e891bf8
EH		 67
68
69/* CPUID Leaf 4 constants: */
70
71/* EAX: */
72#define CPUID_4_TYPE_DCACHE 1
73#define CPUID_4_TYPE_ICACHE 2
74#define CPUID_4_TYPE_UNIFIED 3
75
76#define CPUID_4_LEVEL(l) ((l) << 5)
77
78#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
79#define CPUID_4_FULLY_ASSOC (1 << 9)
80
81/* EDX: */
82#define CPUID_4_NO_INVD_SHARING (1 << 0)
83#define CPUID_4_INCLUSIVE (1 << 1)
84#define CPUID_4_COMPLEX_IDX (1 << 2)
85
86#define ASSOC_FULL 0xFF
87
88/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
89#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
90 a == 2 ? 0x2 : \
91 a == 4 ? 0x4 : \
92 a == 8 ? 0x6 : \
93 a == 16 ? 0x8 : \
94 a == 32 ? 0xA : \
95 a == 48 ? 0xB : \
96 a == 64 ? 0xC : \
97 a == 96 ? 0xD : \
98 a == 128 ? 0xE : \
99 a == ASSOC_FULL ? 0xF : \
100 0 /* invalid value */)
101
102
103/* Definitions of the hardcoded cache entries we expose: */
104
105/* L1 data cache: */
106#define L1D_LINE_SIZE 64
107#define L1D_ASSOCIATIVITY 8
108#define L1D_SETS 64
109#define L1D_PARTITIONS 1
110/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
111#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
112/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
113#define L1D_LINES_PER_TAG 1
114#define L1D_SIZE_KB_AMD 64
115#define L1D_ASSOCIATIVITY_AMD 2
116
117/* L1 instruction cache: */
118#define L1I_LINE_SIZE 64
119#define L1I_ASSOCIATIVITY 8
120#define L1I_SETS 64
121#define L1I_PARTITIONS 1
122/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
123#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
124/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
125#define L1I_LINES_PER_TAG 1
126#define L1I_SIZE_KB_AMD 64
127#define L1I_ASSOCIATIVITY_AMD 2
128
129/* Level 2 unified cache: */
130#define L2_LINE_SIZE 64
131#define L2_ASSOCIATIVITY 16
132#define L2_SETS 4096
133#define L2_PARTITIONS 1
134/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
135/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
136#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
137/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
138#define L2_LINES_PER_TAG 1
139#define L2_SIZE_KB_AMD 512
140
14c985cf 141/* Level 3 unified cache: */
5e891bf8
EH		 142#define L3_SIZE_KB 0 /* disabled */
143#define L3_ASSOCIATIVITY 0 /* disabled */
144#define L3_LINES_PER_TAG 0 /* disabled */
145#define L3_LINE_SIZE 0 /* disabled */
14c985cf
LM		 146#define L3_N_LINE_SIZE 64
147#define L3_N_ASSOCIATIVITY 16
148#define L3_N_SETS 16384
149#define L3_N_PARTITIONS 1
150#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
151#define L3_N_LINES_PER_TAG 1
152#define L3_N_SIZE_KB_AMD 16384
5e891bf8
EH		 153
154/* TLB definitions: */
155
156#define L1_DTLB_2M_ASSOC 1
157#define L1_DTLB_2M_ENTRIES 255
158#define L1_DTLB_4K_ASSOC 1
159#define L1_DTLB_4K_ENTRIES 255
160
161#define L1_ITLB_2M_ASSOC 1
162#define L1_ITLB_2M_ENTRIES 255
163#define L1_ITLB_4K_ASSOC 1
164#define L1_ITLB_4K_ENTRIES 255
165
166#define L2_DTLB_2M_ASSOC 0 /* disabled */
167#define L2_DTLB_2M_ENTRIES 0 /* disabled */
168#define L2_DTLB_4K_ASSOC 4
169#define L2_DTLB_4K_ENTRIES 512
170
171#define L2_ITLB_2M_ASSOC 0 /* disabled */
172#define L2_ITLB_2M_ENTRIES 0 /* disabled */
173#define L2_ITLB_4K_ASSOC 4
174#define L2_ITLB_4K_ENTRIES 512
175
176
177
99b88a17
IM		 178static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
179 uint32_t vendor2, uint32_t vendor3)
180{
181 int i;
182 for (i = 0; i < 4; i++) {
183 dst[i] = vendor1 >> (8 * i);
184 dst[i + 4] = vendor2 >> (8 * i);
185 dst[i + 8] = vendor3 >> (8 * i);
186 }
187 dst[CPUID_VENDOR_SZ] = '\0';
188}
189
621626ce
EH		 190#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
191#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
192 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
193#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
194 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
195 CPUID_PSE36 | CPUID_FXSR)
196#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
197#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
198 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
199 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
200 CPUID_PAE | CPUID_SEP | CPUID_APIC)
201
202#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
203 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
204 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
205 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 206 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 207 /* partly implemented:
208 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
209 /* missing:
210 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
211#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
212 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
213 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 214 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 215 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
216 /* missing:
217 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
218 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
219 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 220 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
221 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 222
223#ifdef TARGET_X86_64
224#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
225#else
226#define TCG_EXT2_X86_64_FEATURES 0
227#endif
228
229#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
230 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
231 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
232 TCG_EXT2_X86_64_FEATURES)
233#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
234 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
235#define TCG_EXT4_FEATURES 0
236#define TCG_SVM_FEATURES 0
237#define TCG_KVM_FEATURES 0
238#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 239 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
240 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 241 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
242 CPUID_7_0_EBX_ERMS)
621626ce 243 /* missing:
07929f2a 244 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 245 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 246 CPUID_7_0_EBX_RDSEED */
6c7c3c21
KS		 247#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
248 CPUID_7_0_ECX_LA57)
95ea69fb 249#define TCG_7_0_EDX_FEATURES 0
303752a9 250#define TCG_APM_FEATURES 0
28b8e4d0 251#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 252#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
253 /* missing:
254 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 255
5ef57876 256typedef struct FeatureWordInfo {
2d5312da
EH		 257 /* feature flags names are taken from "Intel Processor Identification and
258 * the CPUID Instruction" and AMD's "CPUID Specification".
259 * In cases of disagreement between feature naming conventions,
260 * aliases may be added.
261 */
262 const char *feat_names[32];
04d104b6
EH		 263 uint32_t cpuid_eax; /* Input EAX for CPUID */
264 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
265 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
266 int cpuid_reg; /* output register (R_* constant) */
37ce3522 267 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 268 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 269 uint32_t migratable_flags; /* Feature flags known to be migratable */
5ef57876
EH		 270} FeatureWordInfo;
271
272static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 273 [FEAT_1_EDX] = {
2d5312da
EH		 274 .feat_names = {
275 "fpu", "vme", "de", "pse",
276 "tsc", "msr", "pae", "mce",
277 "cx8", "apic", NULL, "sep",
278 "mtrr", "pge", "mca", "cmov",
279 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
280 NULL, "ds" /* Intel dts */, "acpi", "mmx",
281 "fxsr", "sse", "sse2", "ss",
282 "ht" /* Intel htt */, "tm", "ia64", "pbe",
283 },
bffd67b0 284 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 285 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 286 },
287 [FEAT_1_ECX] = {
2d5312da 288 .feat_names = {
16d2fcaa 289 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 290 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 291 "tm2", "ssse3", "cid", NULL,
292 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 293 NULL, "pcid", "dca", "sse4.1",
294 "sse4.2", "x2apic", "movbe", "popcnt",
2d5312da
EH		 295 "tsc-deadline", "aes", "xsave", "osxsave",
296 "avx", "f16c", "rdrand", "hypervisor",
297 },
bffd67b0 298 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 299 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 300 },
2d5312da
EH		 301 /* Feature names that are already defined on feature_name[] but
302 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
303 * names on feat_names below. They are copied automatically
304 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
305 */
bffd67b0 306 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 307 .feat_names = {
308 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
309 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
310 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
311 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
312 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 313 "nx", NULL, "mmxext", NULL /* mmx */,
314 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
315 NULL, "lm", "3dnowext", "3dnow",
2d5312da 316 },
bffd67b0 317 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 318 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 319 },
320 [FEAT_8000_0001_ECX] = {
2d5312da 321 .feat_names = {
fc7dfd20 322 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 323 "cr8legacy", "abm", "sse4a", "misalignsse",
324 "3dnowprefetch", "osvw", "ibs", "xop",
325 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 326 "fma4", "tce", NULL, "nodeid-msr",
327 NULL, "tbm", "topoext", "perfctr-core",
328 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 329 NULL, NULL, NULL, NULL,
330 },
bffd67b0 331 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 332 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 333 },
89e49c8b 334 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 335 .feat_names = {
336 NULL, NULL, "xstore", "xstore-en",
337 NULL, NULL, "xcrypt", "xcrypt-en",
338 "ace2", "ace2-en", "phe", "phe-en",
339 "pmm", "pmm-en", NULL, NULL,
340 NULL, NULL, NULL, NULL,
341 NULL, NULL, NULL, NULL,
342 NULL, NULL, NULL, NULL,
343 NULL, NULL, NULL, NULL,
344 },
89e49c8b 345 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 346 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 347 },
bffd67b0 348 [FEAT_KVM] = {
2d5312da 349 .feat_names = {
fc7dfd20
EH		 350 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
351 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
6976af66 352 NULL, "kvm-pv-tlb-flush", NULL, NULL,
2d5312da
EH		 353 NULL, NULL, NULL, NULL,
354 NULL, NULL, NULL, NULL,
355 NULL, NULL, NULL, NULL,
356 "kvmclock-stable-bit", NULL, NULL, NULL,
357 NULL, NULL, NULL, NULL,
358 },
bffd67b0 359 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 360 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 361 },
be777326
WL		 362 [FEAT_KVM_HINTS] = {
363 .feat_names = {
364 "kvm-hint-dedicated", NULL, NULL, NULL,
365 NULL, NULL, NULL, NULL,
366 NULL, NULL, NULL, NULL,
367 NULL, NULL, NULL, NULL,
368 NULL, NULL, NULL, NULL,
369 NULL, NULL, NULL, NULL,
370 NULL, NULL, NULL, NULL,
371 NULL, NULL, NULL, NULL,
372 },
373 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EDX,
374 .tcg_features = TCG_KVM_FEATURES,
375 },
c35bd19a 376 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 377 .feat_names = {
378 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
379 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
380 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
381 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
382 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
383 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
384 NULL, NULL, NULL, NULL,
385 NULL, NULL, NULL, NULL,
386 NULL, NULL, NULL, NULL,
387 NULL, NULL, NULL, NULL,
388 NULL, NULL, NULL, NULL,
389 },
c35bd19a
EY		 390 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
391 },
392 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 393 .feat_names = {
394 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
395 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
396 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
397 NULL /* hv_create_port */, NULL /* hv_connect_port */,
398 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
399 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
400 NULL, NULL,
401 NULL, NULL, NULL, NULL,
402 NULL, NULL, NULL, NULL,
403 NULL, NULL, NULL, NULL,
404 NULL, NULL, NULL, NULL,
405 },
c35bd19a
EY		 406 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
407 },
408 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 409 .feat_names = {
410 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
411 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
412 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
413 NULL, NULL,
414 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
415 NULL, NULL, NULL, NULL,
416 NULL, NULL, NULL, NULL,
417 NULL, NULL, NULL, NULL,
418 NULL, NULL, NULL, NULL,
419 NULL, NULL, NULL, NULL,
420 },
c35bd19a
EY		 421 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
422 },
bffd67b0 423 [FEAT_SVM] = {
2d5312da 424 .feat_names = {
fc7dfd20
EH		 425 "npt", "lbrv", "svm-lock", "nrip-save",
426 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
427 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 428 "pfthreshold", NULL, NULL, NULL,
429 NULL, NULL, NULL, NULL,
430 NULL, NULL, NULL, NULL,
431 NULL, NULL, NULL, NULL,
432 NULL, NULL, NULL, NULL,
433 },
bffd67b0 434 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 435 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 436 },
437 [FEAT_7_0_EBX] = {
2d5312da 438 .feat_names = {
fc7dfd20 439 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 440 "hle", "avx2", NULL, "smep",
441 "bmi2", "erms", "invpcid", "rtm",
442 NULL, NULL, "mpx", NULL,
443 "avx512f", "avx512dq", "rdseed", "adx",
444 "smap", "avx512ifma", "pcommit", "clflushopt",
445 "clwb", NULL, "avx512pf", "avx512er",
638cbd45 446 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 447 },
04d104b6
EH		 448 .cpuid_eax = 7,
449 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
450 .cpuid_reg = R_EBX,
37ce3522 451 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 452 },
f74eefe0 453 [FEAT_7_0_ECX] = {
2d5312da
EH		 454 .feat_names = {
455 NULL, "avx512vbmi", "umip", "pku",
aff9e6e4
YZ		 456 "ospke", NULL, "avx512vbmi2", NULL,
457 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
458 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 459 "la57", NULL, NULL, NULL,
2d5312da
EH		 460 NULL, NULL, "rdpid", NULL,
461 NULL, NULL, NULL, NULL,
462 NULL, NULL, NULL, NULL,
463 },
f74eefe0
HH		 464 .cpuid_eax = 7,
465 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
466 .cpuid_reg = R_ECX,
467 .tcg_features = TCG_7_0_ECX_FEATURES,
468 },
95ea69fb
LK		 469 [FEAT_7_0_EDX] = {
470 .feat_names = {
471 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
472 NULL, NULL, NULL, NULL,
473 NULL, NULL, NULL, NULL,
474 NULL, NULL, NULL, NULL,
475 NULL, NULL, NULL, NULL,
476 NULL, NULL, NULL, NULL,
a2381f09 477 NULL, NULL, "spec-ctrl", NULL,
95ea69fb
LK		 478 NULL, NULL, NULL, NULL,
479 },
480 .cpuid_eax = 7,
481 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
482 .cpuid_reg = R_EDX,
483 .tcg_features = TCG_7_0_EDX_FEATURES,
484 },
303752a9 485 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 486 .feat_names = {
487 NULL, NULL, NULL, NULL,
488 NULL, NULL, NULL, NULL,
489 "invtsc", NULL, NULL, NULL,
490 NULL, NULL, NULL, NULL,
491 NULL, NULL, NULL, NULL,
492 NULL, NULL, NULL, NULL,
493 NULL, NULL, NULL, NULL,
494 NULL, NULL, NULL, NULL,
495 },
303752a9
MT		 496 .cpuid_eax = 0x80000007,
497 .cpuid_reg = R_EDX,
498 .tcg_features = TCG_APM_FEATURES,
499 .unmigratable_flags = CPUID_APM_INVTSC,
500 },
1b3420e1
EH		 501 [FEAT_8000_0008_EBX] = {
502 .feat_names = {
503 NULL, NULL, NULL, NULL,
504 NULL, NULL, NULL, NULL,
505 NULL, NULL, NULL, NULL,
506 "ibpb", NULL, NULL, NULL,
507 NULL, NULL, NULL, NULL,
508 NULL, NULL, NULL, NULL,
509 NULL, NULL, NULL, NULL,
510 NULL, NULL, NULL, NULL,
511 },
512 .cpuid_eax = 0x80000008,
513 .cpuid_reg = R_EBX,
514 .tcg_features = 0,
515 .unmigratable_flags = 0,
516 },
0bb0b2d2 517 [FEAT_XSAVE] = {
2d5312da
EH		 518 .feat_names = {
519 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
520 NULL, NULL, NULL, NULL,
521 NULL, NULL, NULL, NULL,
522 NULL, NULL, NULL, NULL,
523 NULL, NULL, NULL, NULL,
524 NULL, NULL, NULL, NULL,
525 NULL, NULL, NULL, NULL,
526 NULL, NULL, NULL, NULL,
527 },
0bb0b2d2
PB		 528 .cpuid_eax = 0xd,
529 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
530 .cpuid_reg = R_EAX,
c9cfe8f9 531 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 532 },
28b8e4d0 533 [FEAT_6_EAX] = {
2d5312da
EH		 534 .feat_names = {
535 NULL, NULL, "arat", NULL,
536 NULL, NULL, NULL, NULL,
537 NULL, NULL, NULL, NULL,
538 NULL, NULL, NULL, NULL,
539 NULL, NULL, NULL, NULL,
540 NULL, NULL, NULL, NULL,
541 NULL, NULL, NULL, NULL,
542 NULL, NULL, NULL, NULL,
543 },
28b8e4d0
JK		 544 .cpuid_eax = 6, .cpuid_reg = R_EAX,
545 .tcg_features = TCG_6_EAX_FEATURES,
546 },
96193c22
EH		 547 [FEAT_XSAVE_COMP_LO] = {
548 .cpuid_eax = 0xD,
549 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
550 .cpuid_reg = R_EAX,
551 .tcg_features = ~0U,
6fb2fff7
EH		 552 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
553 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
554 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
555 XSTATE_PKRU_MASK,
96193c22
EH		 556 },
557 [FEAT_XSAVE_COMP_HI] = {
558 .cpuid_eax = 0xD,
559 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
560 .cpuid_reg = R_EDX,
561 .tcg_features = ~0U,
562 },
5ef57876
EH		 563};
564
8e8aba50
EH		 565typedef struct X86RegisterInfo32 {
566 /* Name of register */
567 const char *name;
568 /* QAPI enum value register */
569 X86CPURegister32 qapi_enum;
570} X86RegisterInfo32;
571
572#define REGISTER(reg) \
5d371f41 573 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 574static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 575 REGISTER(EAX),
576 REGISTER(ECX),
577 REGISTER(EDX),
578 REGISTER(EBX),
579 REGISTER(ESP),
580 REGISTER(EBP),
581 REGISTER(ESI),
582 REGISTER(EDI),
583};
584#undef REGISTER
585
3f32bd21
RH		 586typedef struct ExtSaveArea {
587 uint32_t feature, bits;
588 uint32_t offset, size;
589} ExtSaveArea;
590
591static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 592 [XSTATE_FP_BIT] = {
593 /* x87 FP state component is always enabled if XSAVE is supported */
594 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
595 /* x87 state is in the legacy region of the XSAVE area */
596 .offset = 0,
597 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
598 },
599 [XSTATE_SSE_BIT] = {
600 /* SSE state component is always enabled if XSAVE is supported */
601 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
602 /* SSE state is in the legacy region of the XSAVE area */
603 .offset = 0,
604 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
605 },
cfc3b074
PB		 606 [XSTATE_YMM_BIT] =
607 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 608 .offset = offsetof(X86XSaveArea, avx_state),
609 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 610 [XSTATE_BNDREGS_BIT] =
611 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 612 .offset = offsetof(X86XSaveArea, bndreg_state),
613 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 614 [XSTATE_BNDCSR_BIT] =
615 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 616 .offset = offsetof(X86XSaveArea, bndcsr_state),
617 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 618 [XSTATE_OPMASK_BIT] =
619 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 620 .offset = offsetof(X86XSaveArea, opmask_state),
621 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 622 [XSTATE_ZMM_Hi256_BIT] =
623 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 624 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
625 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 626 [XSTATE_Hi16_ZMM_BIT] =
627 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 628 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
629 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 630 [XSTATE_PKRU_BIT] =
631 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 632 .offset = offsetof(X86XSaveArea, pkru_state),
633 .size = sizeof(XSavePKRU) },
2560f19f 634};
8e8aba50 635
1fda6198
EH		 636static uint32_t xsave_area_size(uint64_t mask)
637{
638 int i;
e3c9022b 639 uint64_t ret = 0;
1fda6198 640
e3c9022b 641 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 642 const ExtSaveArea *esa = &x86_ext_save_areas[i];
643 if ((mask >> i) & 1) {
644 ret = MAX(ret, esa->offset + esa->size);
645 }
646 }
647 return ret;
648}
649
d6dcc558
SAGDR		 650static inline bool accel_uses_host_cpuid(void)
651{
652 return kvm_enabled() || hvf_enabled();
653}
654
96193c22
EH		 655static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
656{
657 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
658 cpu->env.features[FEAT_XSAVE_COMP_LO];
659}
660
8b4beddc
EH		 661const char *get_register_name_32(unsigned int reg)
662{
31ccdde2 663 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 664 return NULL;
665 }
8e8aba50 666 return x86_reg_info_32[reg].name;
8b4beddc
EH		 667}
668
84f1b92f
EH		 669/*
670 * Returns the set of feature flags that are supported and migratable by
671 * QEMU, for a given FeatureWord.
672 */
673static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
674{
675 FeatureWordInfo *wi = &feature_word_info[w];
676 uint32_t r = 0;
677 int i;
678
679 for (i = 0; i < 32; i++) {
680 uint32_t f = 1U << i;
6fb2fff7
EH		 681
682 /* If the feature name is known, it is implicitly considered migratable,
683 * unless it is explicitly set in unmigratable_flags */
684 if ((wi->migratable_flags & f) ||
685 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
686 r |= f;
84f1b92f 687 }
84f1b92f
EH		 688 }
689 return r;
690}
691
bb44e0d1
JK		 692void host_cpuid(uint32_t function, uint32_t count,
693 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 694{
a1fd24af
AL		 695 uint32_t vec[4];
696
697#ifdef __x86_64__
698 asm volatile("cpuid"
699 : "=a"(vec[0]), "=b"(vec[1]),
700 "=c"(vec[2]), "=d"(vec[3])
701 : "0"(function), "c"(count) : "cc");
c1f41226 702#elif defined(__i386__)
a1fd24af
AL		 703 asm volatile("pusha \n\t"
704 "cpuid \n\t"
705 "mov %%eax, 0(%2) \n\t"
706 "mov %%ebx, 4(%2) \n\t"
707 "mov %%ecx, 8(%2) \n\t"
708 "mov %%edx, 12(%2) \n\t"
709 "popa"
710 : : "a"(function), "c"(count), "S"(vec)
711 : "memory", "cc");
c1f41226
EH		 712#else
713 abort();
a1fd24af
AL		 714#endif
715
bdde476a 716 if (eax)
a1fd24af 717 *eax = vec[0];
bdde476a 718 if (ebx)
a1fd24af 719 *ebx = vec[1];
bdde476a 720 if (ecx)
a1fd24af 721 *ecx = vec[2];
bdde476a 722 if (edx)
a1fd24af 723 *edx = vec[3];
bdde476a 724}
c6dc6f63 725
20271d48
EH		 726void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
727{
728 uint32_t eax, ebx, ecx, edx;
729
730 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
731 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
732
733 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
734 if (family) {
735 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
736 }
737 if (model) {
738 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
739 }
740 if (stepping) {
741 *stepping = eax & 0x0F;
742 }
743}
744
d940ee9b
EH		 745/* CPU class name definitions: */
746
d940ee9b
EH		 747/* Return type name for a given CPU model name
748 * Caller is responsible for freeing the returned string.
749 */
750static char *x86_cpu_type_name(const char *model_name)
751{
752 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
753}
754
500050d1
AF		 755static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
756{
d940ee9b
EH		 757 ObjectClass *oc;
758 char *typename;
759
500050d1
AF		 760 if (cpu_model == NULL) {
761 return NULL;
762 }
763
d940ee9b
EH		 764 typename = x86_cpu_type_name(cpu_model);
765 oc = object_class_by_name(typename);
766 g_free(typename);
767 return oc;
500050d1
AF		 768}
769
104494ea
IM		 770static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
771{
772 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
773 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
774 return g_strndup(class_name,
775 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
776}
777
d940ee9b 778struct X86CPUDefinition {
c6dc6f63
AP		 779 const char *name;
780 uint32_t level;
90e4b0c3 781 uint32_t xlevel;
99b88a17
IM		 782 /* vendor is zero-terminated, 12 character ASCII string */
783 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 784 int family;
785 int model;
786 int stepping;
0514ef2f 787 FeatureWordArray features;
807e9869 788 const char *model_id;
d940ee9b 789};
c6dc6f63 790
9576de75 791static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 792 {
793 .name = "qemu64",
3046bb5d 794 .level = 0xd,
99b88a17 795 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 796 .family = 6,
f8e6a11a 797 .model = 6,
c6dc6f63 798 .stepping = 3,
0514ef2f 799 .features[FEAT_1_EDX] =
27861ecc 800 PPRO_FEATURES |
c6dc6f63 801 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 802 CPUID_PSE36,
0514ef2f 803 .features[FEAT_1_ECX] =
6aa91e4a 804 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 805 .features[FEAT_8000_0001_EDX] =
c6dc6f63 806 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 807 .features[FEAT_8000_0001_ECX] =
71195672 808 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 809 .xlevel = 0x8000000A,
9cf2cc3d 810 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 811 },
812 {
813 .name = "phenom",
814 .level = 5,
99b88a17 815 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 816 .family = 16,
817 .model = 2,
818 .stepping = 3,
b9fc20bc 819 /* Missing: CPUID_HT */
0514ef2f 820 .features[FEAT_1_EDX] =
27861ecc 821 PPRO_FEATURES |
c6dc6f63 822 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 823 CPUID_PSE36 | CPUID_VME,
0514ef2f 824 .features[FEAT_1_ECX] =
27861ecc 825 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 826 CPUID_EXT_POPCNT,
0514ef2f 827 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 828 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
829 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 830 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 831 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
832 CPUID_EXT3_CR8LEG,
833 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
834 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 835 .features[FEAT_8000_0001_ECX] =
27861ecc 836 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 837 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 838 /* Missing: CPUID_SVM_LBRV */
0514ef2f 839 .features[FEAT_SVM] =
b9fc20bc 840 CPUID_SVM_NPT,
c6dc6f63
AP		 841 .xlevel = 0x8000001A,
842 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
843 },
844 {
845 .name = "core2duo",
846 .level = 10,
99b88a17 847 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 848 .family = 6,
849 .model = 15,
850 .stepping = 11,
b9fc20bc 851 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 852 .features[FEAT_1_EDX] =
27861ecc 853 PPRO_FEATURES |
c6dc6f63 854 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 855 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
856 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 857 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 858 .features[FEAT_1_ECX] =
27861ecc 859 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 860 CPUID_EXT_CX16,
0514ef2f 861 .features[FEAT_8000_0001_EDX] =
27861ecc 862 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 863 .features[FEAT_8000_0001_ECX] =
27861ecc 864 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 865 .xlevel = 0x80000008,
866 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
867 },
868 {
869 .name = "kvm64",
3046bb5d 870 .level = 0xd,
99b88a17 871 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 872 .family = 15,
873 .model = 6,
874 .stepping = 1,
b3a4f0b1 875 /* Missing: CPUID_HT */
0514ef2f 876 .features[FEAT_1_EDX] =
b3a4f0b1 877 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 878 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
879 CPUID_PSE36,
880 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 881 .features[FEAT_1_ECX] =
27861ecc 882 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 883 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 884 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 885 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
886 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
887 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
888 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
889 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 890 .features[FEAT_8000_0001_ECX] =
27861ecc 891 0,
c6dc6f63
AP		 892 .xlevel = 0x80000008,
893 .model_id = "Common KVM processor"
894 },
c6dc6f63
AP		 895 {
896 .name = "qemu32",
897 .level = 4,
99b88a17 898 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 899 .family = 6,
f8e6a11a 900 .model = 6,
c6dc6f63 901 .stepping = 3,
0514ef2f 902 .features[FEAT_1_EDX] =
27861ecc 903 PPRO_FEATURES,
0514ef2f 904 .features[FEAT_1_ECX] =
6aa91e4a 905 CPUID_EXT_SSE3,
58012d66 906 .xlevel = 0x80000004,
9cf2cc3d 907 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 908 },
eafaf1e5
AP		 909 {
910 .name = "kvm32",
911 .level = 5,
99b88a17 912 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 913 .family = 15,
914 .model = 6,
915 .stepping = 1,
0514ef2f 916 .features[FEAT_1_EDX] =
b3a4f0b1 917 PPRO_FEATURES | CPUID_VME |
eafaf1e5 918 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 919 .features[FEAT_1_ECX] =
27861ecc 920 CPUID_EXT_SSE3,
0514ef2f 921 .features[FEAT_8000_0001_ECX] =
27861ecc 922 0,
eafaf1e5
AP		 923 .xlevel = 0x80000008,
924 .model_id = "Common 32-bit KVM processor"
925 },
c6dc6f63
AP		 926 {
927 .name = "coreduo",
928 .level = 10,
99b88a17 929 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 930 .family = 6,
931 .model = 14,
932 .stepping = 8,
b9fc20bc 933 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 934 .features[FEAT_1_EDX] =
27861ecc 935 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 936 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
937 CPUID_SS,
938 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 939 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 940 .features[FEAT_1_ECX] =
e93abc14 941 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 942 .features[FEAT_8000_0001_EDX] =
27861ecc 943 CPUID_EXT2_NX,
c6dc6f63
AP		 944 .xlevel = 0x80000008,
945 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
946 },
947 {
948 .name = "486",
58012d66 949 .level = 1,
99b88a17 950 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 951 .family = 4,
b2a856d9 952 .model = 8,
c6dc6f63 953 .stepping = 0,
0514ef2f 954 .features[FEAT_1_EDX] =
27861ecc 955 I486_FEATURES,
c6dc6f63 956 .xlevel = 0,
807e9869 957 .model_id = "",
c6dc6f63
AP		 958 },
959 {
960 .name = "pentium",
961 .level = 1,
99b88a17 962 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 963 .family = 5,
964 .model = 4,
965 .stepping = 3,
0514ef2f 966 .features[FEAT_1_EDX] =
27861ecc 967 PENTIUM_FEATURES,
c6dc6f63 968 .xlevel = 0,
807e9869 969 .model_id = "",
c6dc6f63
AP		 970 },
971 {
972 .name = "pentium2",
973 .level = 2,
99b88a17 974 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 975 .family = 6,
976 .model = 5,
977 .stepping = 2,
0514ef2f 978 .features[FEAT_1_EDX] =
27861ecc 979 PENTIUM2_FEATURES,
c6dc6f63 980 .xlevel = 0,
807e9869 981 .model_id = "",
c6dc6f63
AP		 982 },
983 {
984 .name = "pentium3",
3046bb5d 985 .level = 3,
99b88a17 986 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 987 .family = 6,
988 .model = 7,
989 .stepping = 3,
0514ef2f 990 .features[FEAT_1_EDX] =
27861ecc 991 PENTIUM3_FEATURES,
c6dc6f63 992 .xlevel = 0,
807e9869 993 .model_id = "",
c6dc6f63
AP		 994 },
995 {
996 .name = "athlon",
997 .level = 2,
99b88a17 998 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 999 .family = 6,
1000 .model = 2,
1001 .stepping = 3,
0514ef2f 1002 .features[FEAT_1_EDX] =
27861ecc 1003 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 1004 CPUID_MCA,
0514ef2f 1005 .features[FEAT_8000_0001_EDX] =
60032ac0 1006 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 1007 .xlevel = 0x80000008,
9cf2cc3d 1008 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1009 },
1010 {
1011 .name = "n270",
3046bb5d 1012 .level = 10,
99b88a17 1013 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1014 .family = 6,
1015 .model = 28,
1016 .stepping = 2,
b9fc20bc 1017 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1018 .features[FEAT_1_EDX] =
27861ecc 1019 PPRO_FEATURES |
b9fc20bc
EH		 1020 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1021 CPUID_ACPI | CPUID_SS,
c6dc6f63 1022 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1023 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1024 * CPUID_EXT_XTPR */
0514ef2f 1025 .features[FEAT_1_ECX] =
27861ecc 1026 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1027 CPUID_EXT_MOVBE,
0514ef2f 1028 .features[FEAT_8000_0001_EDX] =
60032ac0 1029 CPUID_EXT2_NX,
0514ef2f 1030 .features[FEAT_8000_0001_ECX] =
27861ecc 1031 CPUID_EXT3_LAHF_LM,
3046bb5d 1032 .xlevel = 0x80000008,
c6dc6f63
AP		 1033 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1034 },
3eca4642
EH		 1035 {
1036 .name = "Conroe",
3046bb5d 1037 .level = 10,
99b88a17 1038 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1039 .family = 6,
ffce9ebb 1040 .model = 15,
3eca4642 1041 .stepping = 3,
0514ef2f 1042 .features[FEAT_1_EDX] =
b3a4f0b1 1043 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1044 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1045 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1046 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1047 CPUID_DE | CPUID_FP87,
0514ef2f 1048 .features[FEAT_1_ECX] =
27861ecc 1049 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1050 .features[FEAT_8000_0001_EDX] =
27861ecc 1051 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1052 .features[FEAT_8000_0001_ECX] =
27861ecc 1053 CPUID_EXT3_LAHF_LM,
3046bb5d 1054 .xlevel = 0x80000008,
3eca4642
EH		 1055 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1056 },
1057 {
1058 .name = "Penryn",
3046bb5d 1059 .level = 10,
99b88a17 1060 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1061 .family = 6,
ffce9ebb 1062 .model = 23,
3eca4642 1063 .stepping = 3,
0514ef2f 1064 .features[FEAT_1_EDX] =
b3a4f0b1 1065 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1066 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1067 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1068 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1069 CPUID_DE | CPUID_FP87,
0514ef2f 1070 .features[FEAT_1_ECX] =
27861ecc 1071 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1072 CPUID_EXT_SSE3,
0514ef2f 1073 .features[FEAT_8000_0001_EDX] =
27861ecc 1074 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1075 .features[FEAT_8000_0001_ECX] =
27861ecc 1076 CPUID_EXT3_LAHF_LM,
3046bb5d 1077 .xlevel = 0x80000008,
3eca4642
EH		 1078 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1079 },
1080 {
1081 .name = "Nehalem",
3046bb5d 1082 .level = 11,
99b88a17 1083 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1084 .family = 6,
ffce9ebb 1085 .model = 26,
3eca4642 1086 .stepping = 3,
0514ef2f 1087 .features[FEAT_1_EDX] =
b3a4f0b1 1088 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1089 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1090 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1091 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1092 CPUID_DE | CPUID_FP87,
0514ef2f 1093 .features[FEAT_1_ECX] =
27861ecc 1094 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1095 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1096 .features[FEAT_8000_0001_EDX] =
27861ecc 1097 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1098 .features[FEAT_8000_0001_ECX] =
27861ecc 1099 CPUID_EXT3_LAHF_LM,
3046bb5d 1100 .xlevel = 0x80000008,
3eca4642
EH		 1101 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1102 },
ac96c413
EH		 1103 {
1104 .name = "Nehalem-IBRS",
1105 .level = 11,
1106 .vendor = CPUID_VENDOR_INTEL,
1107 .family = 6,
1108 .model = 26,
1109 .stepping = 3,
1110 .features[FEAT_1_EDX] =
1111 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1112 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1113 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1114 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1115 CPUID_DE | CPUID_FP87,
1116 .features[FEAT_1_ECX] =
1117 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1118 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1119 .features[FEAT_7_0_EDX] =
1120 CPUID_7_0_EDX_SPEC_CTRL,
1121 .features[FEAT_8000_0001_EDX] =
1122 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1123 .features[FEAT_8000_0001_ECX] =
1124 CPUID_EXT3_LAHF_LM,
1125 .xlevel = 0x80000008,
1126 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1127 },
3eca4642
EH		 1128 {
1129 .name = "Westmere",
1130 .level = 11,
99b88a17 1131 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1132 .family = 6,
1133 .model = 44,
1134 .stepping = 1,
0514ef2f 1135 .features[FEAT_1_EDX] =
b3a4f0b1 1136 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1137 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1138 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1139 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1140 CPUID_DE | CPUID_FP87,
0514ef2f 1141 .features[FEAT_1_ECX] =
27861ecc 1142 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1143 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1144 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1145 .features[FEAT_8000_0001_EDX] =
27861ecc 1146 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1147 .features[FEAT_8000_0001_ECX] =
27861ecc 1148 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1149 .features[FEAT_6_EAX] =
1150 CPUID_6_EAX_ARAT,
3046bb5d 1151 .xlevel = 0x80000008,
3eca4642
EH		 1152 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1153 },
ac96c413
EH		 1154 {
1155 .name = "Westmere-IBRS",
1156 .level = 11,
1157 .vendor = CPUID_VENDOR_INTEL,
1158 .family = 6,
1159 .model = 44,
1160 .stepping = 1,
1161 .features[FEAT_1_EDX] =
1162 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1163 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1164 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1165 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1166 CPUID_DE | CPUID_FP87,
1167 .features[FEAT_1_ECX] =
1168 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1169 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1170 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1171 .features[FEAT_8000_0001_EDX] =
1172 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1173 .features[FEAT_8000_0001_ECX] =
1174 CPUID_EXT3_LAHF_LM,
1175 .features[FEAT_7_0_EDX] =
1176 CPUID_7_0_EDX_SPEC_CTRL,
1177 .features[FEAT_6_EAX] =
1178 CPUID_6_EAX_ARAT,
1179 .xlevel = 0x80000008,
1180 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1181 },
3eca4642
EH		 1182 {
1183 .name = "SandyBridge",
1184 .level = 0xd,
99b88a17 1185 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1186 .family = 6,
1187 .model = 42,
1188 .stepping = 1,
0514ef2f 1189 .features[FEAT_1_EDX] =
b3a4f0b1 1190 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1191 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1192 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1193 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1194 CPUID_DE | CPUID_FP87,
0514ef2f 1195 .features[FEAT_1_ECX] =
27861ecc 1196 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1197 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1198 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1199 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1200 CPUID_EXT_SSE3,
0514ef2f 1201 .features[FEAT_8000_0001_EDX] =
27861ecc 1202 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1203 CPUID_EXT2_SYSCALL,
0514ef2f 1204 .features[FEAT_8000_0001_ECX] =
27861ecc 1205 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1206 .features[FEAT_XSAVE] =
1207 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1208 .features[FEAT_6_EAX] =
1209 CPUID_6_EAX_ARAT,
3046bb5d 1210 .xlevel = 0x80000008,
3eca4642
EH		 1211 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1212 },
ac96c413
EH		 1213 {
1214 .name = "SandyBridge-IBRS",
1215 .level = 0xd,
1216 .vendor = CPUID_VENDOR_INTEL,
1217 .family = 6,
1218 .model = 42,
1219 .stepping = 1,
1220 .features[FEAT_1_EDX] =
1221 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1222 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1223 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1224 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1225 CPUID_DE | CPUID_FP87,
1226 .features[FEAT_1_ECX] =
1227 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1228 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1229 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1230 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1231 CPUID_EXT_SSE3,
1232 .features[FEAT_8000_0001_EDX] =
1233 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1234 CPUID_EXT2_SYSCALL,
1235 .features[FEAT_8000_0001_ECX] =
1236 CPUID_EXT3_LAHF_LM,
1237 .features[FEAT_7_0_EDX] =
1238 CPUID_7_0_EDX_SPEC_CTRL,
1239 .features[FEAT_XSAVE] =
1240 CPUID_XSAVE_XSAVEOPT,
1241 .features[FEAT_6_EAX] =
1242 CPUID_6_EAX_ARAT,
1243 .xlevel = 0x80000008,
1244 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1245 },
2f9ac42a
PB		 1246 {
1247 .name = "IvyBridge",
1248 .level = 0xd,
1249 .vendor = CPUID_VENDOR_INTEL,
1250 .family = 6,
1251 .model = 58,
1252 .stepping = 9,
1253 .features[FEAT_1_EDX] =
1254 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1255 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1256 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1257 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1258 CPUID_DE | CPUID_FP87,
1259 .features[FEAT_1_ECX] =
1260 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1261 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1262 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1263 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1264 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1265 .features[FEAT_7_0_EBX] =
1266 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1267 CPUID_7_0_EBX_ERMS,
1268 .features[FEAT_8000_0001_EDX] =
1269 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1270 CPUID_EXT2_SYSCALL,
1271 .features[FEAT_8000_0001_ECX] =
1272 CPUID_EXT3_LAHF_LM,
1273 .features[FEAT_XSAVE] =
1274 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1275 .features[FEAT_6_EAX] =
1276 CPUID_6_EAX_ARAT,
3046bb5d 1277 .xlevel = 0x80000008,
2f9ac42a
PB		 1278 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1279 },
ac96c413
EH		 1280 {
1281 .name = "IvyBridge-IBRS",
1282 .level = 0xd,
1283 .vendor = CPUID_VENDOR_INTEL,
1284 .family = 6,
1285 .model = 58,
1286 .stepping = 9,
1287 .features[FEAT_1_EDX] =
1288 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1289 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1290 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1291 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1292 CPUID_DE | CPUID_FP87,
1293 .features[FEAT_1_ECX] =
1294 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1295 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1296 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1297 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1298 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1299 .features[FEAT_7_0_EBX] =
1300 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1301 CPUID_7_0_EBX_ERMS,
1302 .features[FEAT_8000_0001_EDX] =
1303 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1304 CPUID_EXT2_SYSCALL,
1305 .features[FEAT_8000_0001_ECX] =
1306 CPUID_EXT3_LAHF_LM,
1307 .features[FEAT_7_0_EDX] =
1308 CPUID_7_0_EDX_SPEC_CTRL,
1309 .features[FEAT_XSAVE] =
1310 CPUID_XSAVE_XSAVEOPT,
1311 .features[FEAT_6_EAX] =
1312 CPUID_6_EAX_ARAT,
1313 .xlevel = 0x80000008,
1314 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
1315 },
37507094 1316 {
a356850b
EH		 1317 .name = "Haswell-noTSX",
1318 .level = 0xd,
1319 .vendor = CPUID_VENDOR_INTEL,
1320 .family = 6,
1321 .model = 60,
1322 .stepping = 1,
1323 .features[FEAT_1_EDX] =
1324 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1325 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1326 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1327 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1328 CPUID_DE | CPUID_FP87,
1329 .features[FEAT_1_ECX] =
1330 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1331 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1332 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1333 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1334 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1335 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1336 .features[FEAT_8000_0001_EDX] =
1337 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1338 CPUID_EXT2_SYSCALL,
1339 .features[FEAT_8000_0001_ECX] =
becb6667 1340 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1341 .features[FEAT_7_0_EBX] =
1342 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1343 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1344 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1345 .features[FEAT_XSAVE] =
1346 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1347 .features[FEAT_6_EAX] =
1348 CPUID_6_EAX_ARAT,
3046bb5d 1349 .xlevel = 0x80000008,
a356850b 1350 .model_id = "Intel Core Processor (Haswell, no TSX)",
ac96c413
EH		 1351 },
1352 {
1353 .name = "Haswell-noTSX-IBRS",
1354 .level = 0xd,
1355 .vendor = CPUID_VENDOR_INTEL,
1356 .family = 6,
1357 .model = 60,
1358 .stepping = 1,
1359 .features[FEAT_1_EDX] =
1360 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1361 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1362 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1363 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1364 CPUID_DE | CPUID_FP87,
1365 .features[FEAT_1_ECX] =
1366 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1367 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1368 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1369 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1370 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1371 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1372 .features[FEAT_8000_0001_EDX] =
1373 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1374 CPUID_EXT2_SYSCALL,
1375 .features[FEAT_8000_0001_ECX] =
1376 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1377 .features[FEAT_7_0_EDX] =
1378 CPUID_7_0_EDX_SPEC_CTRL,
1379 .features[FEAT_7_0_EBX] =
1380 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1381 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1382 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1383 .features[FEAT_XSAVE] =
1384 CPUID_XSAVE_XSAVEOPT,
1385 .features[FEAT_6_EAX] =
1386 CPUID_6_EAX_ARAT,
1387 .xlevel = 0x80000008,
1388 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
1389 },
1390 {
37507094
EH		 1391 .name = "Haswell",
1392 .level = 0xd,
99b88a17 1393 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1394 .family = 6,
1395 .model = 60,
ec56a4a7 1396 .stepping = 4,
0514ef2f 1397 .features[FEAT_1_EDX] =
b3a4f0b1 1398 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1399 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1400 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1401 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1402 CPUID_DE | CPUID_FP87,
0514ef2f 1403 .features[FEAT_1_ECX] =
27861ecc 1404 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1405 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1406 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1407 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1408 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1409 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1410 .features[FEAT_8000_0001_EDX] =
27861ecc 1411 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1412 CPUID_EXT2_SYSCALL,
0514ef2f 1413 .features[FEAT_8000_0001_ECX] =
becb6667 1414 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1415 .features[FEAT_7_0_EBX] =
27861ecc 1416 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1417 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1418 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1419 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1420 .features[FEAT_XSAVE] =
1421 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1422 .features[FEAT_6_EAX] =
1423 CPUID_6_EAX_ARAT,
3046bb5d 1424 .xlevel = 0x80000008,
37507094
EH		 1425 .model_id = "Intel Core Processor (Haswell)",
1426 },
ac96c413
EH		 1427 {
1428 .name = "Haswell-IBRS",
1429 .level = 0xd,
1430 .vendor = CPUID_VENDOR_INTEL,
1431 .family = 6,
1432 .model = 60,
1433 .stepping = 4,
1434 .features[FEAT_1_EDX] =
1435 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1436 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1437 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1438 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1439 CPUID_DE | CPUID_FP87,
1440 .features[FEAT_1_ECX] =
1441 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1442 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1443 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1444 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1445 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1446 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1447 .features[FEAT_8000_0001_EDX] =
1448 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1449 CPUID_EXT2_SYSCALL,
1450 .features[FEAT_8000_0001_ECX] =
1451 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1452 .features[FEAT_7_0_EDX] =
1453 CPUID_7_0_EDX_SPEC_CTRL,
1454 .features[FEAT_7_0_EBX] =
1455 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1456 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1457 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1458 CPUID_7_0_EBX_RTM,
1459 .features[FEAT_XSAVE] =
1460 CPUID_XSAVE_XSAVEOPT,
1461 .features[FEAT_6_EAX] =
1462 CPUID_6_EAX_ARAT,
1463 .xlevel = 0x80000008,
1464 .model_id = "Intel Core Processor (Haswell, IBRS)",
1465 },
a356850b
EH		 1466 {
1467 .name = "Broadwell-noTSX",
1468 .level = 0xd,
1469 .vendor = CPUID_VENDOR_INTEL,
1470 .family = 6,
1471 .model = 61,
1472 .stepping = 2,
1473 .features[FEAT_1_EDX] =
1474 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1475 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1476 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1477 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1478 CPUID_DE | CPUID_FP87,
1479 .features[FEAT_1_ECX] =
1480 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1481 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1482 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1483 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1484 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1485 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1486 .features[FEAT_8000_0001_EDX] =
1487 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1488 CPUID_EXT2_SYSCALL,
1489 .features[FEAT_8000_0001_ECX] =
becb6667 1490 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1491 .features[FEAT_7_0_EBX] =
1492 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1493 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1494 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1495 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1496 CPUID_7_0_EBX_SMAP,
1497 .features[FEAT_XSAVE] =
1498 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1499 .features[FEAT_6_EAX] =
1500 CPUID_6_EAX_ARAT,
3046bb5d 1501 .xlevel = 0x80000008,
a356850b
EH		 1502 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1503 },
ac96c413
EH		 1504 {
1505 .name = "Broadwell-noTSX-IBRS",
1506 .level = 0xd,
1507 .vendor = CPUID_VENDOR_INTEL,
1508 .family = 6,
1509 .model = 61,
1510 .stepping = 2,
1511 .features[FEAT_1_EDX] =
1512 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1513 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1514 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1515 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1516 CPUID_DE | CPUID_FP87,
1517 .features[FEAT_1_ECX] =
1518 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1519 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1520 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1521 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1522 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1523 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1524 .features[FEAT_8000_0001_EDX] =
1525 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1526 CPUID_EXT2_SYSCALL,
1527 .features[FEAT_8000_0001_ECX] =
1528 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1529 .features[FEAT_7_0_EDX] =
1530 CPUID_7_0_EDX_SPEC_CTRL,
1531 .features[FEAT_7_0_EBX] =
1532 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1533 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1534 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1535 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1536 CPUID_7_0_EBX_SMAP,
1537 .features[FEAT_XSAVE] =
1538 CPUID_XSAVE_XSAVEOPT,
1539 .features[FEAT_6_EAX] =
1540 CPUID_6_EAX_ARAT,
1541 .xlevel = 0x80000008,
1542 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
1543 },
ece01354
EH		 1544 {
1545 .name = "Broadwell",
1546 .level = 0xd,
1547 .vendor = CPUID_VENDOR_INTEL,
1548 .family = 6,
1549 .model = 61,
1550 .stepping = 2,
1551 .features[FEAT_1_EDX] =
b3a4f0b1 1552 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1553 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1554 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1555 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1556 CPUID_DE | CPUID_FP87,
1557 .features[FEAT_1_ECX] =
1558 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1559 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1560 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1561 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1562 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1563 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1564 .features[FEAT_8000_0001_EDX] =
1565 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1566 CPUID_EXT2_SYSCALL,
1567 .features[FEAT_8000_0001_ECX] =
becb6667 1568 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1569 .features[FEAT_7_0_EBX] =
1570 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1571 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1572 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1573 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1574 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1575 .features[FEAT_XSAVE] =
1576 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1577 .features[FEAT_6_EAX] =
1578 CPUID_6_EAX_ARAT,
3046bb5d 1579 .xlevel = 0x80000008,
ece01354
EH		 1580 .model_id = "Intel Core Processor (Broadwell)",
1581 },
ac96c413
EH		 1582 {
1583 .name = "Broadwell-IBRS",
1584 .level = 0xd,
1585 .vendor = CPUID_VENDOR_INTEL,
1586 .family = 6,
1587 .model = 61,
1588 .stepping = 2,
1589 .features[FEAT_1_EDX] =
1590 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1591 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1592 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1593 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1594 CPUID_DE | CPUID_FP87,
1595 .features[FEAT_1_ECX] =
1596 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1597 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1598 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1599 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1600 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1601 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1602 .features[FEAT_8000_0001_EDX] =
1603 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1604 CPUID_EXT2_SYSCALL,
1605 .features[FEAT_8000_0001_ECX] =
1606 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1607 .features[FEAT_7_0_EDX] =
1608 CPUID_7_0_EDX_SPEC_CTRL,
1609 .features[FEAT_7_0_EBX] =
1610 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1611 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1612 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1613 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1614 CPUID_7_0_EBX_SMAP,
1615 .features[FEAT_XSAVE] =
1616 CPUID_XSAVE_XSAVEOPT,
1617 .features[FEAT_6_EAX] =
1618 CPUID_6_EAX_ARAT,
1619 .xlevel = 0x80000008,
1620 .model_id = "Intel Core Processor (Broadwell, IBRS)",
1621 },
f6f949e9
EH		 1622 {
1623 .name = "Skylake-Client",
1624 .level = 0xd,
1625 .vendor = CPUID_VENDOR_INTEL,
1626 .family = 6,
1627 .model = 94,
1628 .stepping = 3,
1629 .features[FEAT_1_EDX] =
1630 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1631 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1632 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1633 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1634 CPUID_DE | CPUID_FP87,
1635 .features[FEAT_1_ECX] =
1636 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1637 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1638 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1639 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1640 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1641 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1642 .features[FEAT_8000_0001_EDX] =
1643 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1644 CPUID_EXT2_SYSCALL,
1645 .features[FEAT_8000_0001_ECX] =
1646 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1647 .features[FEAT_7_0_EBX] =
1648 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1649 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1650 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1651 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1652 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1653 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 1654 * including v4.1 to v4.12).
f6f949e9
EH		 1655 * KVM doesn't yet expose any XSAVES state save component,
1656 * and the only one defined in Skylake (processor tracing)
1657 * probably will block migration anyway.
1658 */
1659 .features[FEAT_XSAVE] =
1660 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1661 CPUID_XSAVE_XGETBV1,
1662 .features[FEAT_6_EAX] =
1663 CPUID_6_EAX_ARAT,
1664 .xlevel = 0x80000008,
1665 .model_id = "Intel Core Processor (Skylake)",
1666 },
ac96c413
EH		 1667 {
1668 .name = "Skylake-Client-IBRS",
1669 .level = 0xd,
1670 .vendor = CPUID_VENDOR_INTEL,
1671 .family = 6,
1672 .model = 94,
1673 .stepping = 3,
1674 .features[FEAT_1_EDX] =
1675 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1676 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1677 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1678 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1679 CPUID_DE | CPUID_FP87,
1680 .features[FEAT_1_ECX] =
1681 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1682 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1683 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1684 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1685 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1686 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1687 .features[FEAT_8000_0001_EDX] =
1688 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1689 CPUID_EXT2_SYSCALL,
1690 .features[FEAT_8000_0001_ECX] =
1691 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1692 .features[FEAT_7_0_EDX] =
1693 CPUID_7_0_EDX_SPEC_CTRL,
1694 .features[FEAT_7_0_EBX] =
1695 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1696 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1697 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1698 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1699 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1700 /* Missing: XSAVES (not supported by some Linux versions,
1701 * including v4.1 to v4.12).
1702 * KVM doesn't yet expose any XSAVES state save component,
1703 * and the only one defined in Skylake (processor tracing)
1704 * probably will block migration anyway.
1705 */
1706 .features[FEAT_XSAVE] =
1707 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1708 CPUID_XSAVE_XGETBV1,
1709 .features[FEAT_6_EAX] =
1710 CPUID_6_EAX_ARAT,
1711 .xlevel = 0x80000008,
1712 .model_id = "Intel Core Processor (Skylake, IBRS)",
1713 },
53f9a6f4
BF		 1714 {
1715 .name = "Skylake-Server",
1716 .level = 0xd,
1717 .vendor = CPUID_VENDOR_INTEL,
1718 .family = 6,
1719 .model = 85,
1720 .stepping = 4,
1721 .features[FEAT_1_EDX] =
1722 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1723 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1724 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1725 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1726 CPUID_DE | CPUID_FP87,
1727 .features[FEAT_1_ECX] =
1728 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1729 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1730 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1731 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1732 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1733 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1734 .features[FEAT_8000_0001_EDX] =
1735 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
1736 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1737 .features[FEAT_8000_0001_ECX] =
1738 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1739 .features[FEAT_7_0_EBX] =
1740 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1741 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1742 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1743 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1744 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
1745 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
1746 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 1747 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
53f9a6f4
BF		 1748 /* Missing: XSAVES (not supported by some Linux versions,
1749 * including v4.1 to v4.12).
1750 * KVM doesn't yet expose any XSAVES state save component,
1751 * and the only one defined in Skylake (processor tracing)
1752 * probably will block migration anyway.
1753 */
1754 .features[FEAT_XSAVE] =
1755 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1756 CPUID_XSAVE_XGETBV1,
1757 .features[FEAT_6_EAX] =
1758 CPUID_6_EAX_ARAT,
1759 .xlevel = 0x80000008,
1760 .model_id = "Intel Xeon Processor (Skylake)",
1761 },
ac96c413
EH		 1762 {
1763 .name = "Skylake-Server-IBRS",
1764 .level = 0xd,
1765 .vendor = CPUID_VENDOR_INTEL,
1766 .family = 6,
1767 .model = 85,
1768 .stepping = 4,
1769 .features[FEAT_1_EDX] =
1770 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1771 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1772 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1773 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1774 CPUID_DE | CPUID_FP87,
1775 .features[FEAT_1_ECX] =
1776 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1777 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1778 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1779 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1780 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1781 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1782 .features[FEAT_8000_0001_EDX] =
1783 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
1784 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1785 .features[FEAT_8000_0001_ECX] =
1786 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1787 .features[FEAT_7_0_EDX] =
1788 CPUID_7_0_EDX_SPEC_CTRL,
1789 .features[FEAT_7_0_EBX] =
1790 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1791 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1792 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1793 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1794 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
1795 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
1796 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
1797 CPUID_7_0_EBX_AVX512VL,
1798 /* Missing: XSAVES (not supported by some Linux versions,
1799 * including v4.1 to v4.12).
1800 * KVM doesn't yet expose any XSAVES state save component,
1801 * and the only one defined in Skylake (processor tracing)
1802 * probably will block migration anyway.
1803 */
1804 .features[FEAT_XSAVE] =
1805 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1806 CPUID_XSAVE_XGETBV1,
1807 .features[FEAT_6_EAX] =
1808 CPUID_6_EAX_ARAT,
1809 .xlevel = 0x80000008,
1810 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
1811 },
3eca4642
EH		 1812 {
1813 .name = "Opteron_G1",
1814 .level = 5,
99b88a17 1815 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1816 .family = 15,
1817 .model = 6,
1818 .stepping = 1,
0514ef2f 1819 .features[FEAT_1_EDX] =
b3a4f0b1 1820 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1821 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1822 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1823 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1824 CPUID_DE | CPUID_FP87,
0514ef2f 1825 .features[FEAT_1_ECX] =
27861ecc 1826 CPUID_EXT_SSE3,
0514ef2f 1827 .features[FEAT_8000_0001_EDX] =
2a923a29 1828 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 1829 .xlevel = 0x80000008,
1830 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1831 },
1832 {
1833 .name = "Opteron_G2",
1834 .level = 5,
99b88a17 1835 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1836 .family = 15,
1837 .model = 6,
1838 .stepping = 1,
0514ef2f 1839 .features[FEAT_1_EDX] =
b3a4f0b1 1840 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1841 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1842 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1843 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1844 CPUID_DE | CPUID_FP87,
0514ef2f 1845 .features[FEAT_1_ECX] =
27861ecc 1846 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1847 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1848 .features[FEAT_8000_0001_EDX] =
2a923a29 1849 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1850 .features[FEAT_8000_0001_ECX] =
27861ecc 1851 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1852 .xlevel = 0x80000008,
1853 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1854 },
1855 {
1856 .name = "Opteron_G3",
1857 .level = 5,
99b88a17 1858 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 1859 .family = 16,
1860 .model = 2,
1861 .stepping = 3,
0514ef2f 1862 .features[FEAT_1_EDX] =
b3a4f0b1 1863 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1864 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1865 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1866 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1867 CPUID_DE | CPUID_FP87,
0514ef2f 1868 .features[FEAT_1_ECX] =
27861ecc 1869 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1870 CPUID_EXT_SSE3,
33b5e8c0 1871 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1872 .features[FEAT_8000_0001_EDX] =
2a923a29 1873 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1874 .features[FEAT_8000_0001_ECX] =
27861ecc 1875 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1876 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1877 .xlevel = 0x80000008,
1878 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1879 },
1880 {
1881 .name = "Opteron_G4",
1882 .level = 0xd,
99b88a17 1883 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1884 .family = 21,
1885 .model = 1,
1886 .stepping = 2,
0514ef2f 1887 .features[FEAT_1_EDX] =
b3a4f0b1 1888 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1889 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1890 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1891 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1892 CPUID_DE | CPUID_FP87,
0514ef2f 1893 .features[FEAT_1_ECX] =
27861ecc 1894 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1895 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1896 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1897 CPUID_EXT_SSE3,
33b5e8c0 1898 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1899 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1900 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1901 CPUID_EXT2_SYSCALL,
0514ef2f 1902 .features[FEAT_8000_0001_ECX] =
27861ecc 1903 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1904 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1905 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1906 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1907 /* no xsaveopt! */
3eca4642
EH		 1908 .xlevel = 0x8000001A,
1909 .model_id = "AMD Opteron 62xx class CPU",
1910 },
021941b9
AP		 1911 {
1912 .name = "Opteron_G5",
1913 .level = 0xd,
99b88a17 1914 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1915 .family = 21,
1916 .model = 2,
1917 .stepping = 0,
0514ef2f 1918 .features[FEAT_1_EDX] =
b3a4f0b1 1919 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1920 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1921 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1922 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1923 CPUID_DE | CPUID_FP87,
0514ef2f 1924 .features[FEAT_1_ECX] =
27861ecc 1925 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1926 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1927 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1928 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1929 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1930 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1931 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1932 CPUID_EXT2_SYSCALL,
0514ef2f 1933 .features[FEAT_8000_0001_ECX] =
27861ecc 1934 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1935 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1936 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1937 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1938 /* no xsaveopt! */
021941b9
AP		 1939 .xlevel = 0x8000001A,
1940 .model_id = "AMD Opteron 63xx class CPU",
1941 },
2e2efc7d
BS		 1942 {
1943 .name = "EPYC",
1944 .level = 0xd,
1945 .vendor = CPUID_VENDOR_AMD,
1946 .family = 23,
1947 .model = 1,
1948 .stepping = 2,
1949 .features[FEAT_1_EDX] =
1950 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
1951 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
1952 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
1953 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
1954 CPUID_VME | CPUID_FP87,
1955 .features[FEAT_1_ECX] =
1956 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
1957 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
1958 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1959 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
1960 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1961 .features[FEAT_8000_0001_EDX] =
1962 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
1963 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
1964 CPUID_EXT2_SYSCALL,
1965 .features[FEAT_8000_0001_ECX] =
1966 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
1967 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
1968 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1969 .features[FEAT_7_0_EBX] =
1970 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
1971 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
1972 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
1973 CPUID_7_0_EBX_SHA_NI,
1974 /* Missing: XSAVES (not supported by some Linux versions,
1975 * including v4.1 to v4.12).
1976 * KVM doesn't yet expose any XSAVES state save component.
1977 */
1978 .features[FEAT_XSAVE] =
1979 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1980 CPUID_XSAVE_XGETBV1,
1981 .features[FEAT_6_EAX] =
1982 CPUID_6_EAX_ARAT,
1983 .xlevel = 0x8000000A,
1984 .model_id = "AMD EPYC Processor",
1985 },
6cfbc54e
EH		 1986 {
1987 .name = "EPYC-IBPB",
1988 .level = 0xd,
1989 .vendor = CPUID_VENDOR_AMD,
1990 .family = 23,
1991 .model = 1,
1992 .stepping = 2,
1993 .features[FEAT_1_EDX] =
1994 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
1995 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
1996 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
1997 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
1998 CPUID_VME | CPUID_FP87,
1999 .features[FEAT_1_ECX] =
2000 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2001 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2002 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2003 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2004 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2005 .features[FEAT_8000_0001_EDX] =
2006 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2007 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2008 CPUID_EXT2_SYSCALL,
2009 .features[FEAT_8000_0001_ECX] =
2010 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2011 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2012 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2013 .features[FEAT_8000_0008_EBX] =
2014 CPUID_8000_0008_EBX_IBPB,
2015 .features[FEAT_7_0_EBX] =
2016 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2017 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2018 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2019 CPUID_7_0_EBX_SHA_NI,
2020 /* Missing: XSAVES (not supported by some Linux versions,
2021 * including v4.1 to v4.12).
2022 * KVM doesn't yet expose any XSAVES state save component.
2023 */
2024 .features[FEAT_XSAVE] =
2025 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2026 CPUID_XSAVE_XGETBV1,
2027 .features[FEAT_6_EAX] =
2028 CPUID_6_EAX_ARAT,
2029 .xlevel = 0x8000000A,
2030 .model_id = "AMD EPYC Processor (with IBPB)",
2031 },
c6dc6f63
AP		 2032};
2033
5114e842
EH		 2034typedef struct PropValue {
2035 const char *prop, *value;
2036} PropValue;
2037
2038/* KVM-specific features that are automatically added/removed
2039 * from all CPU models when KVM is enabled.
2040 */
2041static PropValue kvm_default_props[] = {
2042 { "kvmclock", "on" },
2043 { "kvm-nopiodelay", "on" },
2044 { "kvm-asyncpf", "on" },
2045 { "kvm-steal-time", "on" },
2046 { "kvm-pv-eoi", "on" },
2047 { "kvmclock-stable-bit", "on" },
2048 { "x2apic", "on" },
2049 { "acpi", "off" },
2050 { "monitor", "off" },
2051 { "svm", "off" },
2052 { NULL, NULL },
2053};
2054
04d99c3c
EH		 2055/* TCG-specific defaults that override all CPU models when using TCG
2056 */
2057static PropValue tcg_default_props[] = {
2058 { "vme", "off" },
2059 { NULL, NULL },
2060};
2061
2062
5114e842
EH		 2063void x86_cpu_change_kvm_default(const char *prop, const char *value)
2064{
2065 PropValue *pv;
2066 for (pv = kvm_default_props; pv->prop; pv++) {
2067 if (!strcmp(pv->prop, prop)) {
2068 pv->value = value;
2069 break;
2070 }
2071 }
2072
2073 /* It is valid to call this function only for properties that
2074 * are already present in the kvm_default_props table.
2075 */
2076 assert(pv->prop);
2077}
2078
4d1b279b
EH		 2079static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2080 bool migratable_only);
2081
40bfe48f
HZ		 2082static bool lmce_supported(void)
2083{
c62f2630 2084 uint64_t mce_cap = 0;
40bfe48f 2085
c62f2630 2086#ifdef CONFIG_KVM
40bfe48f
HZ		 2087 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
2088 return false;
2089 }
c62f2630 2090#endif
40bfe48f
HZ		 2091
2092 return !!(mce_cap & MCG_LMCE_P);
2093}
2094
7d8050b5
EH		 2095#define CPUID_MODEL_ID_SZ 48
2096
2097/**
2098 * cpu_x86_fill_model_id:
2099 * Get CPUID model ID string from host CPU.
2100 *
2101 * @str should have at least CPUID_MODEL_ID_SZ bytes
2102 *
2103 * The function does NOT add a null terminator to the string
2104 * automatically.
2105 */
c6dc6f63
AP		 2106static int cpu_x86_fill_model_id(char *str)
2107{
2108 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2109 int i;
2110
2111 for (i = 0; i < 3; i++) {
2112 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
2113 memcpy(str + i * 16 + 0, &eax, 4);
2114 memcpy(str + i * 16 + 4, &ebx, 4);
2115 memcpy(str + i * 16 + 8, &ecx, 4);
2116 memcpy(str + i * 16 + 12, &edx, 4);
2117 }
2118 return 0;
2119}
2120
c62f2630 2121static Property max_x86_cpu_properties[] = {
120eee7d 2122 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 2123 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 2124 DEFINE_PROP_END_OF_LIST()
2125};
2126
c62f2630 2127static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 2128{
84f1b92f 2129 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 2130 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 2131
f48c8837 2132 xcc->ordering = 9;
6e746f30 2133
ee465a3e 2134 xcc->model_description =
c62f2630 2135 "Enables all features supported by the accelerator in the current host";
d940ee9b 2136
c62f2630 2137 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 2138}
2139
0bacd8b3
EH		 2140static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
2141
c62f2630 2142static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 2143{
2144 X86CPU *cpu = X86_CPU(obj);
2145 CPUX86State *env = &cpu->env;
2146 KVMState *s = kvm_state;
d940ee9b 2147
4d1b279b
EH		 2148 /* We can't fill the features array here because we don't know yet if
2149 * "migratable" is true or false.
2150 */
44bd8e53 2151 cpu->max_features = true;
4d1b279b 2152
d6dcc558 2153 if (accel_uses_host_cpuid()) {
bd182022
EH		 2154 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
2155 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
2156 int family, model, stepping;
d6dcc558
SAGDR		 2157 X86CPUDefinition host_cpudef = { };
2158 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2159
2160 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
2161 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
0bacd8b3 2162
bd182022 2163 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 2164
bd182022 2165 cpu_x86_fill_model_id(model_id);
0bacd8b3 2166
bd182022
EH		 2167 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
2168 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
2169 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
2170 object_property_set_int(OBJECT(cpu), stepping, "stepping",
2171 &error_abort);
2172 object_property_set_str(OBJECT(cpu), model_id, "model-id",
2173 &error_abort);
0bacd8b3 2174
d6dcc558
SAGDR		 2175 if (kvm_enabled()) {
2176 env->cpuid_min_level =
2177 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
2178 env->cpuid_min_xlevel =
2179 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
2180 env->cpuid_min_xlevel2 =
2181 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2182 } else {
2183 env->cpuid_min_level =
2184 hvf_get_supported_cpuid(0x0, 0, R_EAX);
2185 env->cpuid_min_xlevel =
2186 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
2187 env->cpuid_min_xlevel2 =
2188 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
2189 }
40bfe48f
HZ		 2190
2191 if (lmce_supported()) {
2192 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
2193 }
6900d1cc
EH		 2194 } else {
2195 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
2196 "vendor", &error_abort);
2197 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
2198 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
2199 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
2200 object_property_set_str(OBJECT(cpu),
2201 "QEMU TCG CPU version " QEMU_HW_VERSION,
2202 "model-id", &error_abort);
e4356010 2203 }
2a573259 2204
d940ee9b 2205 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 2206}
2207
c62f2630
EH		 2208static const TypeInfo max_x86_cpu_type_info = {
2209 .name = X86_CPU_TYPE_NAME("max"),
2210 .parent = TYPE_X86_CPU,
2211 .instance_init = max_x86_cpu_initfn,
2212 .class_init = max_x86_cpu_class_init,
2213};
2214
d6dcc558 2215#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 2216static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
2217{
2218 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2219
d6dcc558 2220 xcc->host_cpuid_required = true;
c62f2630
EH		 2221 xcc->ordering = 8;
2222
d6dcc558
SAGDR		 2223 if (kvm_enabled()) {
2224 xcc->model_description =
2225 "KVM processor with all supported host features ";
2226 } else if (hvf_enabled()) {
2227 xcc->model_description =
2228 "HVF processor with all supported host features ";
2229 }
c62f2630
EH		 2230}
2231
d940ee9b
EH		 2232static const TypeInfo host_x86_cpu_type_info = {
2233 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 2234 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 2235 .class_init = host_x86_cpu_class_init,
2236};
2237
2238#endif
2239
8459e396 2240static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 2241{
8459e396 2242 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 2243 int i;
2244
857aee33 2245 for (i = 0; i < 32; ++i) {
72370dc1 2246 if ((1UL << i) & mask) {
bffd67b0 2247 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 2248 assert(reg);
8297be80
AF		 2249 warn_report("%s doesn't support requested feature: "
2250 "CPUID.%02XH:%s%s%s [bit %d]",
d6dcc558 2251 accel_uses_host_cpuid() ? "host" : "TCG",
8297be80
AF		 2252 f->cpuid_eax, reg,
2253 f->feat_names[i] ? "." : "",
2254 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 2255 }
857aee33 2256 }
c6dc6f63
AP		 2257}
2258
d7bce999
EB		 2259static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
2260 const char *name, void *opaque,
2261 Error **errp)
95b8519d
AF		 2262{
2263 X86CPU *cpu = X86_CPU(obj);
2264 CPUX86State *env = &cpu->env;
2265 int64_t value;
2266
2267 value = (env->cpuid_version >> 8) & 0xf;
2268 if (value == 0xf) {
2269 value += (env->cpuid_version >> 20) & 0xff;
2270 }
51e72bc1 2271 visit_type_int(v, name, &value, errp);
95b8519d
AF		 2272}
2273
d7bce999
EB		 2274static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
2275 const char *name, void *opaque,
2276 Error **errp)
ed5e1ec3 2277{
71ad61d3
AF		 2278 X86CPU *cpu = X86_CPU(obj);
2279 CPUX86State *env = &cpu->env;
2280 const int64_t min = 0;
2281 const int64_t max = 0xff + 0xf;
65cd9064 2282 Error *local_err = NULL;
71ad61d3
AF		 2283 int64_t value;
2284
51e72bc1 2285 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2286 if (local_err) {
2287 error_propagate(errp, local_err);
71ad61d3
AF		 2288 return;
2289 }
2290 if (value < min || value > max) {
c6bd8c70
MA		 2291 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2292 name ? name : "null", value, min, max);
71ad61d3
AF		 2293 return;
2294 }
2295
ed5e1ec3 2296 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 2297 if (value > 0x0f) {
2298 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 2299 } else {
71ad61d3 2300 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 2301 }
2302}
2303
d7bce999
EB		 2304static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
2305 const char *name, void *opaque,
2306 Error **errp)
67e30c83
AF		 2307{
2308 X86CPU *cpu = X86_CPU(obj);
2309 CPUX86State *env = &cpu->env;
2310 int64_t value;
2311
2312 value = (env->cpuid_version >> 4) & 0xf;
2313 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 2314 visit_type_int(v, name, &value, errp);
67e30c83
AF		 2315}
2316
d7bce999
EB		 2317static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
2318 const char *name, void *opaque,
2319 Error **errp)
b0704cbd 2320{
c5291a4f
AF		 2321 X86CPU *cpu = X86_CPU(obj);
2322 CPUX86State *env = &cpu->env;
2323 const int64_t min = 0;
2324 const int64_t max = 0xff;
65cd9064 2325 Error *local_err = NULL;
c5291a4f
AF		 2326 int64_t value;
2327
51e72bc1 2328 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2329 if (local_err) {
2330 error_propagate(errp, local_err);
c5291a4f
AF		 2331 return;
2332 }
2333 if (value < min || value > max) {
c6bd8c70
MA		 2334 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2335 name ? name : "null", value, min, max);
c5291a4f
AF		 2336 return;
2337 }
2338
b0704cbd 2339 env->cpuid_version &= ~0xf00f0;
c5291a4f 2340 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 2341}
2342
35112e41 2343static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 2344 const char *name, void *opaque,
35112e41
AF		 2345 Error **errp)
2346{
2347 X86CPU *cpu = X86_CPU(obj);
2348 CPUX86State *env = &cpu->env;
2349 int64_t value;
2350
2351 value = env->cpuid_version & 0xf;
51e72bc1 2352 visit_type_int(v, name, &value, errp);
35112e41
AF		 2353}
2354
036e2222 2355static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 2356 const char *name, void *opaque,
036e2222 2357 Error **errp)
38c3dc46 2358{
036e2222
AF		 2359 X86CPU *cpu = X86_CPU(obj);
2360 CPUX86State *env = &cpu->env;
2361 const int64_t min = 0;
2362 const int64_t max = 0xf;
65cd9064 2363 Error *local_err = NULL;
036e2222
AF		 2364 int64_t value;
2365
51e72bc1 2366 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2367 if (local_err) {
2368 error_propagate(errp, local_err);
036e2222
AF		 2369 return;
2370 }
2371 if (value < min || value > max) {
c6bd8c70
MA		 2372 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2373 name ? name : "null", value, min, max);
036e2222
AF		 2374 return;
2375 }
2376
38c3dc46 2377 env->cpuid_version &= ~0xf;
036e2222 2378 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 2379}
2380
d480e1af
AF		 2381static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
2382{
2383 X86CPU *cpu = X86_CPU(obj);
2384 CPUX86State *env = &cpu->env;
2385 char *value;
d480e1af 2386
e42a92ae 2387 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 2388 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
2389 env->cpuid_vendor3);
d480e1af
AF		 2390 return value;
2391}
2392
2393static void x86_cpuid_set_vendor(Object *obj, const char *value,
2394 Error **errp)
2395{
2396 X86CPU *cpu = X86_CPU(obj);
2397 CPUX86State *env = &cpu->env;
2398 int i;
2399
9df694ee 2400 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 2401 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 2402 return;
2403 }
2404
2405 env->cpuid_vendor1 = 0;
2406 env->cpuid_vendor2 = 0;
2407 env->cpuid_vendor3 = 0;
2408 for (i = 0; i < 4; i++) {
2409 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
2410 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
2411 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
2412 }
d480e1af
AF		 2413}
2414
63e886eb
AF		 2415static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
2416{
2417 X86CPU *cpu = X86_CPU(obj);
2418 CPUX86State *env = &cpu->env;
2419 char *value;
2420 int i;
2421
2422 value = g_malloc(48 + 1);
2423 for (i = 0; i < 48; i++) {
2424 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
2425 }
2426 value[48] = '\0';
2427 return value;
2428}
2429
938d4c25
AF		 2430static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
2431 Error **errp)
dcce6675 2432{
938d4c25
AF		 2433 X86CPU *cpu = X86_CPU(obj);
2434 CPUX86State *env = &cpu->env;
dcce6675
AF		 2435 int c, len, i;
2436
2437 if (model_id == NULL) {
2438 model_id = "";
2439 }
2440 len = strlen(model_id);
d0a6acf4 2441 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 2442 for (i = 0; i < 48; i++) {
2443 if (i >= len) {
2444 c = '\0';
2445 } else {
2446 c = (uint8_t)model_id[i];
2447 }
2448 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
2449 }
2450}
2451
d7bce999
EB		 2452static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
2453 void *opaque, Error **errp)
89e48965
AF		 2454{
2455 X86CPU *cpu = X86_CPU(obj);
2456 int64_t value;
2457
2458 value = cpu->env.tsc_khz * 1000;
51e72bc1 2459 visit_type_int(v, name, &value, errp);
89e48965
AF		 2460}
2461
d7bce999
EB		 2462static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
2463 void *opaque, Error **errp)
89e48965
AF		 2464{
2465 X86CPU *cpu = X86_CPU(obj);
2466 const int64_t min = 0;
2e84849a 2467 const int64_t max = INT64_MAX;
65cd9064 2468 Error *local_err = NULL;
89e48965
AF		 2469 int64_t value;
2470
51e72bc1 2471 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2472 if (local_err) {
2473 error_propagate(errp, local_err);
89e48965
AF		 2474 return;
2475 }
2476 if (value < min || value > max) {
c6bd8c70
MA		 2477 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2478 name ? name : "null", value, min, max);
89e48965
AF		 2479 return;
2480 }
2481
36f96c4b 2482 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 2483}
2484
7e5292b5 2485/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 2486static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
2487 const char *name, void *opaque,
2488 Error **errp)
8e8aba50 2489{
7e5292b5 2490 uint32_t *array = (uint32_t *)opaque;
8e8aba50 2491 FeatureWord w;
8e8aba50
EH		 2492 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
2493 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
2494 X86CPUFeatureWordInfoList *list = NULL;
2495
2496 for (w = 0; w < FEATURE_WORDS; w++) {
2497 FeatureWordInfo *wi = &feature_word_info[w];
2498 X86CPUFeatureWordInfo *qwi = &word_infos[w];
2499 qwi->cpuid_input_eax = wi->cpuid_eax;
2500 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
2501 qwi->cpuid_input_ecx = wi->cpuid_ecx;
2502 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 2503 qwi->features = array[w];
8e8aba50
EH		 2504
2505 /* List will be in reverse order, but order shouldn't matter */
2506 list_entries[w].next = list;
2507 list_entries[w].value = &word_infos[w];
2508 list = &list_entries[w];
2509 }
2510
6b62d961 2511 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 2512}
2513
d7bce999
EB		 2514static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
2515 void *opaque, Error **errp)
c8f0f88e
IM		 2516{
2517 X86CPU *cpu = X86_CPU(obj);
2518 int64_t value = cpu->hyperv_spinlock_attempts;
2519
51e72bc1 2520 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 2521}
2522
d7bce999
EB		 2523static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
2524 void *opaque, Error **errp)
c8f0f88e
IM		 2525{
2526 const int64_t min = 0xFFF;
2527 const int64_t max = UINT_MAX;
2528 X86CPU *cpu = X86_CPU(obj);
2529 Error *err = NULL;
2530 int64_t value;
2531
51e72bc1 2532 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 2533 if (err) {
2534 error_propagate(errp, err);
2535 return;
2536 }
2537
2538 if (value < min || value > max) {
2539 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 2540 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
2541 object_get_typename(obj), name ? name : "null",
2542 value, min, max);
c8f0f88e
IM		 2543 return;
2544 }
2545 cpu->hyperv_spinlock_attempts = value;
2546}
2547
1b6b7d10 2548static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 2549 .name = "int",
2550 .get = x86_get_hv_spinlocks,
2551 .set = x86_set_hv_spinlocks,
2552};
2553
72ac2e87
IM		 2554/* Convert all '_' in a feature string option name to '-', to make feature
2555 * name conform to QOM property naming rule, which uses '-' instead of '_'.
2556 */
2557static inline void feat2prop(char *s)
2558{
2559 while ((s = strchr(s, '_'))) {
2560 *s = '-';
2561 }
2562}
2563
b54c9377
EH		 2564/* Return the feature property name for a feature flag bit */
2565static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
2566{
2567 /* XSAVE components are automatically enabled by other features,
2568 * so return the original feature name instead
2569 */
2570 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
2571 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
2572
2573 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
2574 x86_ext_save_areas[comp].bits) {
2575 w = x86_ext_save_areas[comp].feature;
2576 bitnr = ctz32(x86_ext_save_areas[comp].bits);
2577 }
2578 }
2579
2580 assert(bitnr < 32);
2581 assert(w < FEATURE_WORDS);
2582 return feature_word_info[w].feat_names[bitnr];
2583}
2584
dc15c051
IM		 2585/* Compatibily hack to maintain legacy +-feat semantic,
2586 * where +-feat overwrites any feature set by
2587 * feat=on|feat even if the later is parsed after +-feat
2588 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2589 */
2fae0d96 2590static GList *plus_features, *minus_features;
dc15c051 2591
83a00f60
EH		 2592static gint compare_string(gconstpointer a, gconstpointer b)
2593{
2594 return g_strcmp0(a, b);
2595}
2596
8f961357
EH		 2597/* Parse "+feature,-feature,feature=foo" CPU feature string
2598 */
62a48a2a 2599static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 2600 Error **errp)
8f961357 2601{
8f961357 2602 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 2603 static bool cpu_globals_initialized;
83a00f60 2604 bool ambiguous = false;
62a48a2a
IM		 2605
2606 if (cpu_globals_initialized) {
2607 return;
2608 }
2609 cpu_globals_initialized = true;
8f961357 2610
f6750e95
EH		 2611 if (!features) {
2612 return;
2613 }
2614
2615 for (featurestr = strtok(features, ",");
685479bd 2616 featurestr;
f6750e95
EH		 2617 featurestr = strtok(NULL, ",")) {
2618 const char *name;
2619 const char *val = NULL;
2620 char *eq = NULL;
cf2887c9 2621 char num[32];
62a48a2a 2622 GlobalProperty *prop;
c6dc6f63 2623
f6750e95 2624 /* Compatibility syntax: */
c6dc6f63 2625 if (featurestr[0] == '+') {
2fae0d96
EH		 2626 plus_features = g_list_append(plus_features,
2627 g_strdup(featurestr + 1));
f6750e95 2628 continue;
c6dc6f63 2629 } else if (featurestr[0] == '-') {
2fae0d96
EH		 2630 minus_features = g_list_append(minus_features,
2631 g_strdup(featurestr + 1));
f6750e95
EH		 2632 continue;
2633 }
2634
2635 eq = strchr(featurestr, '=');
2636 if (eq) {
2637 *eq++ = 0;
2638 val = eq;
c6dc6f63 2639 } else {
f6750e95 2640 val = "on";
a91987c2 2641 }
f6750e95
EH		 2642
2643 feat2prop(featurestr);
2644 name = featurestr;
2645
83a00f60 2646 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 2647 warn_report("Ambiguous CPU model string. "
2648 "Don't mix both \"+%s\" and \"%s=%s\"",
2649 name, name, val);
83a00f60
EH		 2650 ambiguous = true;
2651 }
2652 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 2653 warn_report("Ambiguous CPU model string. "
2654 "Don't mix both \"-%s\" and \"%s=%s\"",
2655 name, name, val);
83a00f60
EH		 2656 ambiguous = true;
2657 }
2658
f6750e95
EH		 2659 /* Special case: */
2660 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 2661 int ret;
f46bfdbf 2662 uint64_t tsc_freq;
f6750e95 2663
f17fd4fd 2664 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 2665 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 2666 error_setg(errp, "bad numerical value %s", val);
2667 return;
2668 }
2669 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2670 val = num;
2671 name = "tsc-frequency";
c6dc6f63 2672 }
f6750e95 2673
62a48a2a
IM		 2674 prop = g_new0(typeof(*prop), 1);
2675 prop->driver = typename;
2676 prop->property = g_strdup(name);
2677 prop->value = g_strdup(val);
2678 prop->errp = &error_fatal;
2679 qdev_prop_register_global(prop);
f6750e95
EH		 2680 }
2681
83a00f60 2682 if (ambiguous) {
3dc6f869
AF		 2683 warn_report("Compatibility of ambiguous CPU model "
2684 "strings won't be kept on future QEMU versions");
83a00f60 2685 }
c6dc6f63
AP		 2686}
2687
b8d834a0 2688static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 2689static int x86_cpu_filter_features(X86CPU *cpu);
2690
2691/* Check for missing features that may prevent the CPU class from
2692 * running using the current machine and accelerator.
2693 */
2694static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
2695 strList **missing_feats)
2696{
2697 X86CPU *xc;
2698 FeatureWord w;
2699 Error *err = NULL;
2700 strList **next = missing_feats;
2701
d6dcc558 2702 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 2703 strList *new = g_new0(strList, 1);
3c254ab8 2704 new->value = g_strdup("kvm");
b54c9377
EH		 2705 *missing_feats = new;
2706 return;
2707 }
2708
2709 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2710
b8d834a0 2711 x86_cpu_expand_features(xc, &err);
b54c9377 2712 if (err) {
b8d834a0 2713 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 2714 * but in case it does, just report the model as not
2715 * runnable at all using the "type" property.
2716 */
2717 strList *new = g_new0(strList, 1);
2718 new->value = g_strdup("type");
2719 *next = new;
2720 next = &new->next;
2721 }
2722
2723 x86_cpu_filter_features(xc);
2724
2725 for (w = 0; w < FEATURE_WORDS; w++) {
2726 uint32_t filtered = xc->filtered_features[w];
2727 int i;
2728 for (i = 0; i < 32; i++) {
2729 if (filtered & (1UL << i)) {
2730 strList *new = g_new0(strList, 1);
2731 new->value = g_strdup(x86_cpu_feature_name(w, i));
2732 *next = new;
2733 next = &new->next;
2734 }
2735 }
2736 }
2737
2738 object_unref(OBJECT(xc));
2739}
2740
8c3329e5 2741/* Print all cpuid feature names in featureset
c6dc6f63 2742 */
8c3329e5 2743static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2744{
8c3329e5
EH		 2745 int bit;
2746 bool first = true;
2747
2748 for (bit = 0; bit < 32; bit++) {
2749 if (featureset[bit]) {
2750 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2751 first = false;
c6dc6f63 2752 }
8c3329e5 2753 }
c6dc6f63
AP		 2754}
2755
f48c8837 2756/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 2757static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
2758{
2759 ObjectClass *class_a = (ObjectClass *)a;
2760 ObjectClass *class_b = (ObjectClass *)b;
2761 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
2762 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
2763 const char *name_a, *name_b;
2764
f48c8837
EH		 2765 if (cc_a->ordering != cc_b->ordering) {
2766 return cc_a->ordering - cc_b->ordering;
ee465a3e
EH		 2767 } else {
2768 name_a = object_class_get_name(class_a);
2769 name_b = object_class_get_name(class_b);
2770 return strcmp(name_a, name_b);
2771 }
2772}
2773
2774static GSList *get_sorted_cpu_model_list(void)
2775{
2776 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
2777 list = g_slist_sort(list, x86_cpu_list_compare);
2778 return list;
2779}
2780
2781static void x86_cpu_list_entry(gpointer data, gpointer user_data)
2782{
2783 ObjectClass *oc = data;
2784 X86CPUClass *cc = X86_CPU_CLASS(oc);
2785 CPUListState *s = user_data;
2786 char *name = x86_cpu_class_get_model_name(cc);
2787 const char *desc = cc->model_description;
0bacd8b3 2788 if (!desc && cc->cpu_def) {
ee465a3e
EH		 2789 desc = cc->cpu_def->model_id;
2790 }
2791
2792 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
2793 name, desc);
2794 g_free(name);
2795}
2796
2797/* list available CPU models and flags */
e916cbf8 2798void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2799{
7fc9b714 2800 int i;
ee465a3e
EH		 2801 CPUListState s = {
2802 .file = f,
2803 .cpu_fprintf = cpu_fprintf,
2804 };
2805 GSList *list;
c6dc6f63 2806
ee465a3e
EH		 2807 (*cpu_fprintf)(f, "Available CPUs:\n");
2808 list = get_sorted_cpu_model_list();
2809 g_slist_foreach(list, x86_cpu_list_entry, &s);
2810 g_slist_free(list);
21ad7789 2811
6cdf8854 2812 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2813 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2814 FeatureWordInfo *fw = &feature_word_info[i];
2815
8c3329e5
EH		 2816 (*cpu_fprintf)(f, " ");
2817 listflags(f, cpu_fprintf, fw->feat_names);
2818 (*cpu_fprintf)(f, "\n");
3af60be2 2819 }
c6dc6f63
AP		 2820}
2821
ee465a3e
EH		 2822static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
2823{
2824 ObjectClass *oc = data;
2825 X86CPUClass *cc = X86_CPU_CLASS(oc);
2826 CpuDefinitionInfoList **cpu_list = user_data;
2827 CpuDefinitionInfoList *entry;
2828 CpuDefinitionInfo *info;
2829
2830 info = g_malloc0(sizeof(*info));
2831 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 2832 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
2833 info->has_unavailable_features = true;
8ed877b7 2834 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 2835 info->migration_safe = cc->migration_safe;
2836 info->has_migration_safe = true;
5adbed30 2837 info->q_static = cc->static_model;
ee465a3e
EH		 2838
2839 entry = g_malloc0(sizeof(*entry));
2840 entry->value = info;
2841 entry->next = *cpu_list;
2842 *cpu_list = entry;
2843}
2844
76b64a7a 2845CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2846{
2847 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 2848 GSList *list = get_sorted_cpu_model_list();
2849 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
2850 g_slist_free(list);
e3966126
AL		 2851 return cpu_list;
2852}
2853
84f1b92f
EH		 2854static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2855 bool migratable_only)
27418adf
EH		 2856{
2857 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2858 uint32_t r;
27418adf 2859
fefb41bf 2860 if (kvm_enabled()) {
84f1b92f
EH		 2861 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2862 wi->cpuid_ecx,
2863 wi->cpuid_reg);
d6dcc558
SAGDR		 2864 } else if (hvf_enabled()) {
2865 r = hvf_get_supported_cpuid(wi->cpuid_eax,
2866 wi->cpuid_ecx,
2867 wi->cpuid_reg);
fefb41bf 2868 } else if (tcg_enabled()) {
84f1b92f 2869 r = wi->tcg_features;
fefb41bf
EH		 2870 } else {
2871 return ~0;
2872 }
84f1b92f
EH		 2873 if (migratable_only) {
2874 r &= x86_cpu_get_migratable_flags(w);
2875 }
2876 return r;
27418adf
EH		 2877}
2878
8ca30e86
EH		 2879static void x86_cpu_report_filtered_features(X86CPU *cpu)
2880{
2881 FeatureWord w;
2882
2883 for (w = 0; w < FEATURE_WORDS; w++) {
2884 report_unavailable_features(w, cpu->filtered_features[w]);
2885 }
2886}
2887
5114e842
EH		 2888static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2889{
2890 PropValue *pv;
2891 for (pv = props; pv->prop; pv++) {
2892 if (!pv->value) {
2893 continue;
2894 }
2895 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2896 &error_abort);
2897 }
2898}
2899
f99fd7ca 2900/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 2901 */
d940ee9b 2902static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2903{
61dcd775 2904 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2905 const char *vendor;
2906 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2907 FeatureWord w;
c6dc6f63 2908
f99fd7ca
EH		 2909 /*NOTE: any property set by this function should be returned by
2910 * x86_cpu_static_props(), so static expansion of
2911 * query-cpu-model-expansion is always complete.
2912 */
2913
c39c0edf 2914 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 2915 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
2916 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 2917
2d64255b
AF		 2918 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2919 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2920 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2921 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2922 for (w = 0; w < FEATURE_WORDS; w++) {
2923 env->features[w] = def->features[w];
2924 }
82beb536 2925
9576de75 2926 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 2927 /* TODO: in-kernel irqchip for hvf */
82beb536 2928 if (kvm_enabled()) {
492a4c94
LT		 2929 if (!kvm_irqchip_in_kernel()) {
2930 x86_cpu_change_kvm_default("x2apic", "off");
2931 }
2932
5114e842 2933 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 2934 } else if (tcg_enabled()) {
2935 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 2936 }
5fcca9ff 2937
82beb536 2938 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2939
2940 /* sysenter isn't supported in compatibility mode on AMD,
2941 * syscall isn't supported in compatibility mode on Intel.
2942 * Normally we advertise the actual CPU vendor, but you can
2943 * override this using the 'vendor' property if you want to use
2944 * KVM's sysenter/syscall emulation in compatibility mode and
2945 * when doing cross vendor migration
2946 */
74f54bc4 2947 vendor = def->vendor;
d6dcc558 2948 if (accel_uses_host_cpuid()) {
7c08db30
EH		 2949 uint32_t ebx = 0, ecx = 0, edx = 0;
2950 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2951 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2952 vendor = host_vendor;
2953 }
2954
2955 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2956
c6dc6f63
AP		 2957}
2958
f99fd7ca
EH		 2959/* Return a QDict containing keys for all properties that can be included
2960 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
2961 * must be included in the dictionary.
2962 */
2963static QDict *x86_cpu_static_props(void)
2964{
2965 FeatureWord w;
2966 int i;
2967 static const char *props[] = {
2968 "min-level",
2969 "min-xlevel",
2970 "family",
2971 "model",
2972 "stepping",
2973 "model-id",
2974 "vendor",
2975 "lmce",
2976 NULL,
2977 };
2978 static QDict *d;
2979
2980 if (d) {
2981 return d;
2982 }
2983
2984 d = qdict_new();
2985 for (i = 0; props[i]; i++) {
0f9afc2a 2986 qdict_put_null(d, props[i]);
f99fd7ca
EH		 2987 }
2988
2989 for (w = 0; w < FEATURE_WORDS; w++) {
2990 FeatureWordInfo *fi = &feature_word_info[w];
2991 int bit;
2992 for (bit = 0; bit < 32; bit++) {
2993 if (!fi->feat_names[bit]) {
2994 continue;
2995 }
0f9afc2a 2996 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 2997 }
2998 }
2999
3000 return d;
3001}
3002
3003/* Add an entry to @props dict, with the value for property. */
3004static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
3005{
3006 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
3007 &error_abort);
3008
3009 qdict_put_obj(props, prop, value);
3010}
3011
3012/* Convert CPU model data from X86CPU object to a property dictionary
3013 * that can recreate exactly the same CPU model.
3014 */
3015static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
3016{
3017 QDict *sprops = x86_cpu_static_props();
3018 const QDictEntry *e;
3019
3020 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
3021 const char *prop = qdict_entry_key(e);
3022 x86_cpu_expand_prop(cpu, props, prop);
3023 }
3024}
3025
b8097deb
EH		 3026/* Convert CPU model data from X86CPU object to a property dictionary
3027 * that can recreate exactly the same CPU model, including every
3028 * writeable QOM property.
3029 */
3030static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
3031{
3032 ObjectPropertyIterator iter;
3033 ObjectProperty *prop;
3034
3035 object_property_iter_init(&iter, OBJECT(cpu));
3036 while ((prop = object_property_iter_next(&iter))) {
3037 /* skip read-only or write-only properties */
3038 if (!prop->get || !prop->set) {
3039 continue;
3040 }
3041
3042 /* "hotplugged" is the only property that is configurable
3043 * on the command-line but will be set differently on CPUs
3044 * created using "-cpu ... -smp ..." and by CPUs created
3045 * on the fly by x86_cpu_from_model() for querying. Skip it.
3046 */
3047 if (!strcmp(prop->name, "hotplugged")) {
3048 continue;
3049 }
3050 x86_cpu_expand_prop(cpu, props, prop->name);
3051 }
3052}
3053
f99fd7ca
EH		 3054static void object_apply_props(Object *obj, QDict *props, Error **errp)
3055{
3056 const QDictEntry *prop;
3057 Error *err = NULL;
3058
3059 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
3060 object_property_set_qobject(obj, qdict_entry_value(prop),
3061 qdict_entry_key(prop), &err);
3062 if (err) {
3063 break;
3064 }
3065 }
3066
3067 error_propagate(errp, err);
3068}
3069
3070/* Create X86CPU object according to model+props specification */
3071static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
3072{
3073 X86CPU *xc = NULL;
3074 X86CPUClass *xcc;
3075 Error *err = NULL;
3076
3077 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
3078 if (xcc == NULL) {
3079 error_setg(&err, "CPU model '%s' not found", model);
3080 goto out;
3081 }
3082
3083 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3084 if (props) {
3085 object_apply_props(OBJECT(xc), props, &err);
3086 if (err) {
3087 goto out;
3088 }
3089 }
3090
3091 x86_cpu_expand_features(xc, &err);
3092 if (err) {
3093 goto out;
3094 }
3095
3096out:
3097 if (err) {
3098 error_propagate(errp, err);
3099 object_unref(OBJECT(xc));
3100 xc = NULL;
3101 }
3102 return xc;
3103}
3104
3105CpuModelExpansionInfo *
3106arch_query_cpu_model_expansion(CpuModelExpansionType type,
3107 CpuModelInfo *model,
3108 Error **errp)
3109{
3110 X86CPU *xc = NULL;
3111 Error *err = NULL;
3112 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
3113 QDict *props = NULL;
3114 const char *base_name;
3115
3116 xc = x86_cpu_from_model(model->name,
3117 model->has_props ?
3118 qobject_to_qdict(model->props) :
3119 NULL, &err);
3120 if (err) {
3121 goto out;
3122 }
3123
b8097deb 3124 props = qdict_new();
f99fd7ca
EH		 3125
3126 switch (type) {
3127 case CPU_MODEL_EXPANSION_TYPE_STATIC:
3128 /* Static expansion will be based on "base" only */
3129 base_name = "base";
b8097deb 3130 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 3131 break;
3132 case CPU_MODEL_EXPANSION_TYPE_FULL:
3133 /* As we don't return every single property, full expansion needs
3134 * to keep the original model name+props, and add extra
3135 * properties on top of that.
3136 */
3137 base_name = model->name;
b8097deb 3138 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 3139 break;
3140 default:
3141 error_setg(&err, "Unsupportted expansion type");
3142 goto out;
3143 }
3144
3145 if (!props) {
3146 props = qdict_new();
3147 }
3148 x86_cpu_to_dict(xc, props);
3149
3150 ret->model = g_new0(CpuModelInfo, 1);
3151 ret->model->name = g_strdup(base_name);
3152 ret->model->props = QOBJECT(props);
3153 ret->model->has_props = true;
3154
3155out:
3156 object_unref(OBJECT(xc));
3157 if (err) {
3158 error_propagate(errp, err);
3159 qapi_free_CpuModelExpansionInfo(ret);
3160 ret = NULL;
3161 }
3162 return ret;
3163}
3164
00fcd100
AB		 3165static gchar *x86_gdb_arch_name(CPUState *cs)
3166{
3167#ifdef TARGET_X86_64
3168 return g_strdup("i386:x86-64");
3169#else
3170 return g_strdup("i386");
3171#endif
3172}
3173
d940ee9b
EH		 3174static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
3175{
3176 X86CPUDefinition *cpudef = data;
3177 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3178
3179 xcc->cpu_def = cpudef;
bd72159d 3180 xcc->migration_safe = true;
d940ee9b
EH		 3181}
3182
3183static void x86_register_cpudef_type(X86CPUDefinition *def)
3184{
3185 char *typename = x86_cpu_type_name(def->name);
3186 TypeInfo ti = {
3187 .name = typename,
3188 .parent = TYPE_X86_CPU,
3189 .class_init = x86_cpu_cpudef_class_init,
3190 .class_data = def,
3191 };
3192
2a923a29
EH		 3193 /* AMD aliases are handled at runtime based on CPUID vendor, so
3194 * they shouldn't be set on the CPU model table.
3195 */
3196 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 3197 /* catch mistakes instead of silently truncating model_id when too long */
3198 assert(def->model_id && strlen(def->model_id) <= 48);
3199
2a923a29 3200
d940ee9b
EH		 3201 type_register(&ti);
3202 g_free(typename);
3203}
3204
c6dc6f63 3205#if !defined(CONFIG_USER_ONLY)
c6dc6f63 3206
0e26b7b8
BS		 3207void cpu_clear_apic_feature(CPUX86State *env)
3208{
0514ef2f 3209 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 3210}
3211
c6dc6f63
AP		 3212#endif /* !CONFIG_USER_ONLY */
3213
c6dc6f63
AP		 3214void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
3215 uint32_t *eax, uint32_t *ebx,
3216 uint32_t *ecx, uint32_t *edx)
3217{
a60f24b5
AF		 3218 X86CPU *cpu = x86_env_get_cpu(env);
3219 CPUState *cs = CPU(cpu);
14c985cf 3220 uint32_t pkg_offset;
4ed3d478 3221 uint32_t limit;
1ce36bfe 3222 uint32_t signature[3];
a60f24b5 3223
4ed3d478
DB		 3224 /* Calculate & apply limits for different index ranges */
3225 if (index >= 0xC0000000) {
3226 limit = env->cpuid_xlevel2;
3227 } else if (index >= 0x80000000) {
3228 limit = env->cpuid_xlevel;
1ce36bfe
DB		 3229 } else if (index >= 0x40000000) {
3230 limit = 0x40000001;
c6dc6f63 3231 } else {
4ed3d478
DB		 3232 limit = env->cpuid_level;
3233 }
3234
3235 if (index > limit) {
3236 /* Intel documentation states that invalid EAX input will
3237 * return the same information as EAX=cpuid_level
3238 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
3239 */
3240 index = env->cpuid_level;
c6dc6f63
AP		 3241 }
3242
3243 switch(index) {
3244 case 0:
3245 *eax = env->cpuid_level;
5eb2f7a4
EH		 3246 *ebx = env->cpuid_vendor1;
3247 *edx = env->cpuid_vendor2;
3248 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 3249 break;
3250 case 1:
3251 *eax = env->cpuid_version;
7e72a45c
EH		 3252 *ebx = (cpu->apic_id << 24) |
3253 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 3254 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 3255 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
3256 *ecx |= CPUID_EXT_OSXSAVE;
3257 }
0514ef2f 3258 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 3259 if (cs->nr_cores * cs->nr_threads > 1) {
3260 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 3261 *edx |= CPUID_HT;
c6dc6f63
AP		 3262 }
3263 break;
3264 case 2:
3265 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 3266 if (cpu->cache_info_passthrough) {
3267 host_cpuid(index, 0, eax, ebx, ecx, edx);
3268 break;
3269 }
5e891bf8 3270 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 3271 *ebx = 0;
14c985cf
LM		 3272 if (!cpu->enable_l3_cache) {
3273 *ecx = 0;
3274 } else {
3275 *ecx = L3_N_DESCRIPTOR;
3276 }
5e891bf8
EH		 3277 *edx = (L1D_DESCRIPTOR << 16) | \
3278 (L1I_DESCRIPTOR << 8) | \
3279 (L2_DESCRIPTOR);
c6dc6f63
AP		 3280 break;
3281 case 4:
3282 /* cache info: needed for Core compatibility */
787aaf57
BC		 3283 if (cpu->cache_info_passthrough) {
3284 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 3285 *eax &= ~0xFC000000;
c6dc6f63 3286 } else {
2f7a21c4 3287 *eax = 0;
76c2975a 3288 switch (count) {
c6dc6f63 3289 case 0: /* L1 dcache info */
5e891bf8
EH		 3290 *eax |= CPUID_4_TYPE_DCACHE | \
3291 CPUID_4_LEVEL(1) | \
3292 CPUID_4_SELF_INIT_LEVEL;
3293 *ebx = (L1D_LINE_SIZE - 1) | \
3294 ((L1D_PARTITIONS - 1) << 12) | \
3295 ((L1D_ASSOCIATIVITY - 1) << 22);
3296 *ecx = L1D_SETS - 1;
3297 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 3298 break;
3299 case 1: /* L1 icache info */
5e891bf8
EH		 3300 *eax |= CPUID_4_TYPE_ICACHE | \
3301 CPUID_4_LEVEL(1) | \
3302 CPUID_4_SELF_INIT_LEVEL;
3303 *ebx = (L1I_LINE_SIZE - 1) | \
3304 ((L1I_PARTITIONS - 1) << 12) | \
3305 ((L1I_ASSOCIATIVITY - 1) << 22);
3306 *ecx = L1I_SETS - 1;
3307 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 3308 break;
3309 case 2: /* L2 cache info */
5e891bf8
EH		 3310 *eax |= CPUID_4_TYPE_UNIFIED | \
3311 CPUID_4_LEVEL(2) | \
3312 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 3313 if (cs->nr_threads > 1) {
3314 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 3315 }
5e891bf8
EH		 3316 *ebx = (L2_LINE_SIZE - 1) | \
3317 ((L2_PARTITIONS - 1) << 12) | \
3318 ((L2_ASSOCIATIVITY - 1) << 22);
3319 *ecx = L2_SETS - 1;
3320 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63 3321 break;
14c985cf
LM		 3322 case 3: /* L3 cache info */
3323 if (!cpu->enable_l3_cache) {
3324 *eax = 0;
3325 *ebx = 0;
3326 *ecx = 0;
3327 *edx = 0;
3328 break;
3329 }
3330 *eax |= CPUID_4_TYPE_UNIFIED | \
3331 CPUID_4_LEVEL(3) | \
3332 CPUID_4_SELF_INIT_LEVEL;
3333 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
3334 *eax |= ((1 << pkg_offset) - 1) << 14;
3335 *ebx = (L3_N_LINE_SIZE - 1) | \
3336 ((L3_N_PARTITIONS - 1) << 12) | \
3337 ((L3_N_ASSOCIATIVITY - 1) << 22);
3338 *ecx = L3_N_SETS - 1;
3339 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
3340 break;
c6dc6f63
AP		 3341 default: /* end of info */
3342 *eax = 0;
3343 *ebx = 0;
3344 *ecx = 0;
3345 *edx = 0;
3346 break;
76c2975a
PB		 3347 }
3348 }
3349
3350 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
3351 if ((*eax & 31) && cs->nr_cores > 1) {
3352 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 3353 }
3354 break;
3355 case 5:
3356 /* mwait info: needed for Core compatibility */
3357 *eax = 0; /* Smallest monitor-line size in bytes */
3358 *ebx = 0; /* Largest monitor-line size in bytes */
3359 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
3360 *edx = 0;
3361 break;
3362 case 6:
3363 /* Thermal and Power Leaf */
28b8e4d0 3364 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 3365 *ebx = 0;
3366 *ecx = 0;
3367 *edx = 0;
3368 break;
f7911686 3369 case 7:
13526728
EH		 3370 /* Structured Extended Feature Flags Enumeration Leaf */
3371 if (count == 0) {
3372 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 3373 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 3374 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 3375 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
3376 *ecx |= CPUID_7_0_ECX_OSPKE;
3377 }
95ea69fb 3378 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 3379 } else {
3380 *eax = 0;
3381 *ebx = 0;
3382 *ecx = 0;
3383 *edx = 0;
3384 }
3385 break;
c6dc6f63
AP		 3386 case 9:
3387 /* Direct Cache Access Information Leaf */
3388 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
3389 *ebx = 0;
3390 *ecx = 0;
3391 *edx = 0;
3392 break;
3393 case 0xA:
3394 /* Architectural Performance Monitoring Leaf */
9337e3b6 3395 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 3396 KVMState *s = cs->kvm_state;
a0fa8208
GN		 3397
3398 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
3399 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
3400 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
3401 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 3402 } else if (hvf_enabled() && cpu->enable_pmu) {
3403 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
3404 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
3405 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
3406 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 3407 } else {
3408 *eax = 0;
3409 *ebx = 0;
3410 *ecx = 0;
3411 *edx = 0;
3412 }
c6dc6f63 3413 break;
5232d00a
RK		 3414 case 0xB:
3415 /* Extended Topology Enumeration Leaf */
3416 if (!cpu->enable_cpuid_0xb) {
3417 *eax = *ebx = *ecx = *edx = 0;
3418 break;
3419 }
3420
3421 *ecx = count & 0xff;
3422 *edx = cpu->apic_id;
3423
3424 switch (count) {
3425 case 0:
eab60fb9
MAL		 3426 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
3427 *ebx = cs->nr_threads;
5232d00a
RK		 3428 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
3429 break;
3430 case 1:
eab60fb9
MAL		 3431 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
3432 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 3433 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
3434 break;
3435 default:
3436 *eax = 0;
3437 *ebx = 0;
3438 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
3439 }
3440
3441 assert(!(*eax & ~0x1f));
3442 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
3443 break;
2560f19f 3444 case 0xD: {
51e49430 3445 /* Processor Extended State */
2560f19f
PB		 3446 *eax = 0;
3447 *ebx = 0;
3448 *ecx = 0;
3449 *edx = 0;
19dc85db 3450 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 3451 break;
3452 }
4928cd6d 3453
2560f19f 3454 if (count == 0) {
96193c22
EH		 3455 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
3456 *eax = env->features[FEAT_XSAVE_COMP_LO];
3457 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 3458 *ebx = *ecx;
3459 } else if (count == 1) {
0bb0b2d2 3460 *eax = env->features[FEAT_XSAVE];
f4f1110e 3461 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 3462 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
3463 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 3464 *eax = esa->size;
3465 *ebx = esa->offset;
2560f19f 3466 }
51e49430
SY		 3467 }
3468 break;
2560f19f 3469 }
1ce36bfe
DB		 3470 case 0x40000000:
3471 /*
3472 * CPUID code in kvm_arch_init_vcpu() ignores stuff
3473 * set here, but we restrict to TCG none the less.
3474 */
3475 if (tcg_enabled() && cpu->expose_tcg) {
3476 memcpy(signature, "TCGTCGTCGTCG", 12);
3477 *eax = 0x40000001;
3478 *ebx = signature[0];
3479 *ecx = signature[1];
3480 *edx = signature[2];
3481 } else {
3482 *eax = 0;
3483 *ebx = 0;
3484 *ecx = 0;
3485 *edx = 0;
3486 }
3487 break;
3488 case 0x40000001:
3489 *eax = 0;
3490 *ebx = 0;
3491 *ecx = 0;
3492 *edx = 0;
3493 break;
c6dc6f63
AP		 3494 case 0x80000000:
3495 *eax = env->cpuid_xlevel;
3496 *ebx = env->cpuid_vendor1;
3497 *edx = env->cpuid_vendor2;
3498 *ecx = env->cpuid_vendor3;
3499 break;
3500 case 0x80000001:
3501 *eax = env->cpuid_version;
3502 *ebx = 0;
0514ef2f
EH		 3503 *ecx = env->features[FEAT_8000_0001_ECX];
3504 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 3505
3506 /* The Linux kernel checks for the CMPLegacy bit and
3507 * discards multiple thread information if it is set.
cb8d4c8f 3508 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 3509 */
ce3960eb 3510 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 3511 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
3512 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
3513 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 3514 *ecx |= 1 << 1; /* CmpLegacy bit */
3515 }
3516 }
c6dc6f63
AP		 3517 break;
3518 case 0x80000002:
3519 case 0x80000003:
3520 case 0x80000004:
3521 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
3522 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
3523 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
3524 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
3525 break;
3526 case 0x80000005:
3527 /* cache info (L1 cache) */
787aaf57
BC		 3528 if (cpu->cache_info_passthrough) {
3529 host_cpuid(index, 0, eax, ebx, ecx, edx);
3530 break;
3531 }
5e891bf8
EH		 3532 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
3533 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
3534 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
3535 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
3536 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
3537 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
3538 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
3539 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 3540 break;
3541 case 0x80000006:
3542 /* cache info (L2 cache) */
787aaf57
BC		 3543 if (cpu->cache_info_passthrough) {
3544 host_cpuid(index, 0, eax, ebx, ecx, edx);
3545 break;
3546 }
5e891bf8
EH		 3547 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
3548 (L2_DTLB_2M_ENTRIES << 16) | \
3549 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
3550 (L2_ITLB_2M_ENTRIES);
3551 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
3552 (L2_DTLB_4K_ENTRIES << 16) | \
3553 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
3554 (L2_ITLB_4K_ENTRIES);
3555 *ecx = (L2_SIZE_KB_AMD << 16) | \
3556 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
3557 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
14c985cf
LM		 3558 if (!cpu->enable_l3_cache) {
3559 *edx = ((L3_SIZE_KB / 512) << 18) | \
3560 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
3561 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
3562 } else {
3563 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
3564 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
3565 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
3566 }
c6dc6f63 3567 break;
303752a9
MT		 3568 case 0x80000007:
3569 *eax = 0;
3570 *ebx = 0;
3571 *ecx = 0;
3572 *edx = env->features[FEAT_8000_0007_EDX];
3573 break;
c6dc6f63
AP		 3574 case 0x80000008:
3575 /* virtual & phys address size in low 2 bytes. */
0514ef2f 3576 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 3577 /* 64 bit processor */
3578 *eax = cpu->phys_bits; /* configurable physical bits */
3579 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
3580 *eax |= 0x00003900; /* 57 bits virtual */
3581 } else {
3582 *eax |= 0x00003000; /* 48 bits virtual */
3583 }
c6dc6f63 3584 } else {
af45907a 3585 *eax = cpu->phys_bits;
c6dc6f63 3586 }
1b3420e1 3587 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 3588 *ecx = 0;
3589 *edx = 0;
ce3960eb
AF		 3590 if (cs->nr_cores * cs->nr_threads > 1) {
3591 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 3592 }
3593 break;
3594 case 0x8000000A:
0514ef2f 3595 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 3596 *eax = 0x00000001; /* SVM Revision */
3597 *ebx = 0x00000010; /* nr of ASIDs */
3598 *ecx = 0;
0514ef2f 3599 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 3600 } else {
3601 *eax = 0;
3602 *ebx = 0;
3603 *ecx = 0;
3604 *edx = 0;
3605 }
c6dc6f63 3606 break;
b3baa152
BW		 3607 case 0xC0000000:
3608 *eax = env->cpuid_xlevel2;
3609 *ebx = 0;
3610 *ecx = 0;
3611 *edx = 0;
3612 break;
3613 case 0xC0000001:
3614 /* Support for VIA CPU's CPUID instruction */
3615 *eax = env->cpuid_version;
3616 *ebx = 0;
3617 *ecx = 0;
0514ef2f 3618 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 3619 break;
3620 case 0xC0000002:
3621 case 0xC0000003:
3622 case 0xC0000004:
3623 /* Reserved for the future, and now filled with zero */
3624 *eax = 0;
3625 *ebx = 0;
3626 *ecx = 0;
3627 *edx = 0;
3628 break;
c6dc6f63
AP		 3629 default:
3630 /* reserved values: zero */
3631 *eax = 0;
3632 *ebx = 0;
3633 *ecx = 0;
3634 *edx = 0;
3635 break;
3636 }
3637}
5fd2087a
AF		 3638
3639/* CPUClass::reset() */
3640static void x86_cpu_reset(CPUState *s)
3641{
3642 X86CPU *cpu = X86_CPU(s);
3643 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
3644 CPUX86State *env = &cpu->env;
a114d25d
RH		 3645 target_ulong cr4;
3646 uint64_t xcr0;
c1958aea
AF		 3647 int i;
3648
5fd2087a
AF		 3649 xcc->parent_reset(s);
3650
5e992a8e 3651 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 3652
c1958aea
AF		 3653 env->old_exception = -1;
3654
3655 /* init to reset state */
3656
c1958aea
AF		 3657 env->hflags2 |= HF2_GIF_MASK;
3658
3659 cpu_x86_update_cr0(env, 0x60000010);
3660 env->a20_mask = ~0x0;
3661 env->smbase = 0x30000;
3662
3663 env->idt.limit = 0xffff;
3664 env->gdt.limit = 0xffff;
3665 env->ldt.limit = 0xffff;
3666 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
3667 env->tr.limit = 0xffff;
3668 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
3669
3670 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
3671 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
3672 DESC_R_MASK | DESC_A_MASK);
3673 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
3674 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3675 DESC_A_MASK);
3676 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
3677 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3678 DESC_A_MASK);
3679 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
3680 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3681 DESC_A_MASK);
3682 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
3683 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3684 DESC_A_MASK);
3685 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
3686 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3687 DESC_A_MASK);
3688
3689 env->eip = 0xfff0;
3690 env->regs[R_EDX] = env->cpuid_version;
3691
3692 env->eflags = 0x2;
3693
3694 /* FPU init */
3695 for (i = 0; i < 8; i++) {
3696 env->fptags[i] = 1;
3697 }
5bde1407 3698 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 3699
3700 env->mxcsr = 0x1f80;
a114d25d
RH		 3701 /* All units are in INIT state. */
3702 env->xstate_bv = 0;
c1958aea
AF		 3703
3704 env->pat = 0x0007040600070406ULL;
3705 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
3706
3707 memset(env->dr, 0, sizeof(env->dr));
3708 env->dr[6] = DR6_FIXED_1;
3709 env->dr[7] = DR7_FIXED_1;
b3310ab3 3710 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 3711 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 3712
a114d25d 3713 cr4 = 0;
cfc3b074 3714 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 3715
3716#ifdef CONFIG_USER_ONLY
3717 /* Enable all the features for user-mode. */
3718 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 3719 xcr0 |= XSTATE_SSE_MASK;
a114d25d 3720 }
0f70ed47
PB		 3721 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
3722 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 3723 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 3724 xcr0 |= 1ull << i;
3725 }
a114d25d 3726 }
0f70ed47 3727
a114d25d
RH		 3728 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
3729 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
3730 }
07929f2a
RH		 3731 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
3732 cr4 |= CR4_FSGSBASE_MASK;
3733 }
a114d25d
RH		 3734#endif
3735
3736 env->xcr0 = xcr0;
3737 cpu_x86_update_cr4(env, cr4);
0522604b 3738
9db2efd9
AW		 3739 /*
3740 * SDM 11.11.5 requires:
3741 * - IA32_MTRR_DEF_TYPE MSR.E = 0
3742 * - IA32_MTRR_PHYSMASKn.V = 0
3743 * All other bits are undefined. For simplification, zero it all.
3744 */
3745 env->mtrr_deftype = 0;
3746 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
3747 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
3748
b7394c83
SAGDR		 3749 env->interrupt_injected = -1;
3750 env->exception_injected = -1;
3751 env->nmi_injected = false;
dd673288
IM		 3752#if !defined(CONFIG_USER_ONLY)
3753 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 3754 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 3755
259186a7 3756 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 3757
3758 if (kvm_enabled()) {
3759 kvm_arch_reset_vcpu(cpu);
3760 }
d6dcc558
SAGDR		 3761 else if (hvf_enabled()) {
3762 hvf_reset_vcpu(s);
3763 }
dd673288 3764#endif
5fd2087a
AF		 3765}
3766
dd673288
IM		 3767#ifndef CONFIG_USER_ONLY
3768bool cpu_is_bsp(X86CPU *cpu)
3769{
02e51483 3770 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 3771}
65dee380
IM		 3772
3773/* TODO: remove me, when reset over QOM tree is implemented */
3774static void x86_cpu_machine_reset_cb(void *opaque)
3775{
3776 X86CPU *cpu = opaque;
3777 cpu_reset(CPU(cpu));
3778}
dd673288
IM		 3779#endif
3780
de024815
AF		 3781static void mce_init(X86CPU *cpu)
3782{
3783 CPUX86State *cenv = &cpu->env;
3784 unsigned int bank;
3785
3786 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 3787 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 3788 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 3789 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
3790 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 3791 cenv->mcg_ctl = ~(uint64_t)0;
3792 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
3793 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
3794 }
3795 }
3796}
3797
bdeec802 3798#ifndef CONFIG_USER_ONLY
2f114315 3799APICCommonClass *apic_get_class(void)
bdeec802 3800{
bdeec802
IM		 3801 const char *apic_type = "apic";
3802
d6dcc558 3803 /* TODO: in-kernel irqchip for hvf */
15eafc2e 3804 if (kvm_apic_in_kernel()) {
bdeec802
IM		 3805 apic_type = "kvm-apic";
3806 } else if (xen_enabled()) {
3807 apic_type = "xen-apic";
3808 }
3809
2f114315
RK		 3810 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
3811}
3812
3813static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
3814{
3815 APICCommonState *apic;
3816 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
3817
3818 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 3819
6816b1b3
IM		 3820 object_property_add_child(OBJECT(cpu), "lapic",
3821 OBJECT(cpu->apic_state), &error_abort);
67e55caa 3822 object_unref(OBJECT(cpu->apic_state));
6816b1b3 3823
33d7a288 3824 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 3825 /* TODO: convert to link<> */
02e51483 3826 apic = APIC_COMMON(cpu->apic_state);
60671e58 3827 apic->cpu = cpu;
8d42d2d3 3828 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 3829}
3830
3831static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3832{
8d42d2d3
CF		 3833 APICCommonState *apic;
3834 static bool apic_mmio_map_once;
3835
02e51483 3836 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 3837 return;
3838 }
6e8e2651
MA		 3839 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
3840 errp);
8d42d2d3
CF		 3841
3842 /* Map APIC MMIO area */
3843 apic = APIC_COMMON(cpu->apic_state);
3844 if (!apic_mmio_map_once) {
3845 memory_region_add_subregion_overlap(get_system_memory(),
3846 apic->apicbase &
3847 MSR_IA32_APICBASE_BASE,
3848 &apic->io_memory,
3849 0x1000);
3850 apic_mmio_map_once = true;
3851 }
bdeec802 3852}
f809c605
PB		 3853
3854static void x86_cpu_machine_done(Notifier *n, void *unused)
3855{
3856 X86CPU *cpu = container_of(n, X86CPU, machine_done);
3857 MemoryRegion *smram =
3858 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
3859
3860 if (smram) {
3861 cpu->smram = g_new(MemoryRegion, 1);
3862 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
3863 smram, 0, 1ull << 32);
f8c45c65 3864 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 3865 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
3866 }
3867}
d3c64d6a
IM		 3868#else
3869static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3870{
3871}
bdeec802
IM		 3872#endif
3873
11f6fee5
DDAG		 3874/* Note: Only safe for use on x86(-64) hosts */
3875static uint32_t x86_host_phys_bits(void)
3876{
3877 uint32_t eax;
3878 uint32_t host_phys_bits;
3879
3880 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
3881 if (eax >= 0x80000008) {
3882 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
3883 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3884 * at 23:16 that can specify a maximum physical address bits for
3885 * the guest that can override this value; but I've not seen
3886 * anything with that set.
3887 */
3888 host_phys_bits = eax & 0xff;
3889 } else {
3890 /* It's an odd 64 bit machine that doesn't have the leaf for
3891 * physical address bits; fall back to 36 that's most older
3892 * Intel.
3893 */
3894 host_phys_bits = 36;
3895 }
3896
3897 return host_phys_bits;
3898}
e48638fd 3899
c39c0edf
EH		 3900static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
3901{
3902 if (*min < value) {
3903 *min = value;
3904 }
3905}
3906
3907/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3908static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
3909{
3910 CPUX86State *env = &cpu->env;
3911 FeatureWordInfo *fi = &feature_word_info[w];
3912 uint32_t eax = fi->cpuid_eax;
3913 uint32_t region = eax & 0xF0000000;
3914
3915 if (!env->features[w]) {
3916 return;
3917 }
3918
3919 switch (region) {
3920 case 0x00000000:
3921 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
3922 break;
3923 case 0x80000000:
3924 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
3925 break;
3926 case 0xC0000000:
3927 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
3928 break;
3929 }
3930}
3931
2ca8a8be
EH		 3932/* Calculate XSAVE components based on the configured CPU feature flags */
3933static void x86_cpu_enable_xsave_components(X86CPU *cpu)
3934{
3935 CPUX86State *env = &cpu->env;
3936 int i;
96193c22 3937 uint64_t mask;
2ca8a8be
EH		 3938
3939 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
3940 return;
3941 }
3942
e3c9022b
EH		 3943 mask = 0;
3944 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 3945 const ExtSaveArea *esa = &x86_ext_save_areas[i];
3946 if (env->features[esa->feature] & esa->bits) {
96193c22 3947 mask |= (1ULL << i);
2ca8a8be
EH		 3948 }
3949 }
3950
96193c22
EH		 3951 env->features[FEAT_XSAVE_COMP_LO] = mask;
3952 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 3953}
3954
b8d834a0
EH		 3955/***** Steps involved on loading and filtering CPUID data
3956 *
3957 * When initializing and realizing a CPU object, the steps
3958 * involved in setting up CPUID data are:
3959 *
3960 * 1) Loading CPU model definition (X86CPUDefinition). This is
3961 * implemented by x86_cpu_load_def() and should be completely
3962 * transparent, as it is done automatically by instance_init.
3963 * No code should need to look at X86CPUDefinition structs
3964 * outside instance_init.
3965 *
3966 * 2) CPU expansion. This is done by realize before CPUID
3967 * filtering, and will make sure host/accelerator data is
3968 * loaded for CPU models that depend on host capabilities
3969 * (e.g. "host"). Done by x86_cpu_expand_features().
3970 *
3971 * 3) CPUID filtering. This initializes extra data related to
3972 * CPUID, and checks if the host supports all capabilities
3973 * required by the CPU. Runnability of a CPU model is
3974 * determined at this step. Done by x86_cpu_filter_features().
3975 *
3976 * Some operations don't require all steps to be performed.
3977 * More precisely:
3978 *
3979 * - CPU instance creation (instance_init) will run only CPU
3980 * model loading. CPU expansion can't run at instance_init-time
3981 * because host/accelerator data may be not available yet.
3982 * - CPU realization will perform both CPU model expansion and CPUID
3983 * filtering, and return an error in case one of them fails.
3984 * - query-cpu-definitions needs to run all 3 steps. It needs
3985 * to run CPUID filtering, as the 'unavailable-features'
3986 * field is set based on the filtering results.
3987 * - The query-cpu-model-expansion QMP command only needs to run
3988 * CPU model loading and CPU expansion. It should not filter
3989 * any CPUID data based on host capabilities.
3990 */
3991
3992/* Expand CPU configuration data, based on configured features
3993 * and host/accelerator capabilities when appropriate.
3994 */
3995static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 3996{
b34d12d1 3997 CPUX86State *env = &cpu->env;
dc15c051 3998 FeatureWord w;
2fae0d96 3999 GList *l;
41f3d4d6 4000 Error *local_err = NULL;
9886e834 4001
d4a606b3
EH		 4002 /*TODO: Now cpu->max_features doesn't overwrite features
4003 * set using QOM properties, and we can convert
dc15c051
IM		 4004 * plus_features & minus_features to global properties
4005 * inside x86_cpu_parse_featurestr() too.
4006 */
44bd8e53 4007 if (cpu->max_features) {
dc15c051 4008 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 4009 /* Override only features that weren't set explicitly
4010 * by the user.
4011 */
4012 env->features[w] |=
4013 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
4014 ~env->user_features[w];
dc15c051
IM		 4015 }
4016 }
4017
2fae0d96
EH		 4018 for (l = plus_features; l; l = l->next) {
4019 const char *prop = l->data;
4020 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
4021 if (local_err) {
4022 goto out;
4023 }
4024 }
4025
4026 for (l = minus_features; l; l = l->next) {
4027 const char *prop = l->data;
4028 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
4029 if (local_err) {
4030 goto out;
4031 }
dc15c051
IM		 4032 }
4033
aec661de
EH		 4034 if (!kvm_enabled() || !cpu->expose_kvm) {
4035 env->features[FEAT_KVM] = 0;
4036 }
4037
2ca8a8be 4038 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 4039
4040 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
4041 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
4042 if (cpu->full_cpuid_auto_level) {
4043 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
4044 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
4045 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
4046 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
4047 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
4048 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
4049 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 4050 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 4051 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
4052 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
4053 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 4054 /* SVM requires CPUID[0x8000000A] */
4055 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
4056 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
4057 }
c39c0edf
EH		 4058 }
4059
4060 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
4061 if (env->cpuid_level == UINT32_MAX) {
4062 env->cpuid_level = env->cpuid_min_level;
4063 }
4064 if (env->cpuid_xlevel == UINT32_MAX) {
4065 env->cpuid_xlevel = env->cpuid_min_xlevel;
4066 }
4067 if (env->cpuid_xlevel2 == UINT32_MAX) {
4068 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 4069 }
7a059953 4070
41f3d4d6
EH		 4071out:
4072 if (local_err != NULL) {
4073 error_propagate(errp, local_err);
4074 }
4075}
4076
b8d834a0
EH		 4077/*
4078 * Finishes initialization of CPUID data, filters CPU feature
4079 * words based on host availability of each feature.
4080 *
4081 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
4082 */
4083static int x86_cpu_filter_features(X86CPU *cpu)
4084{
4085 CPUX86State *env = &cpu->env;
4086 FeatureWord w;
4087 int rv = 0;
4088
4089 for (w = 0; w < FEATURE_WORDS; w++) {
4090 uint32_t host_feat =
4091 x86_cpu_get_supported_feature_word(w, false);
4092 uint32_t requested_features = env->features[w];
4093 env->features[w] &= host_feat;
4094 cpu->filtered_features[w] = requested_features & ~env->features[w];
4095 if (cpu->filtered_features[w]) {
4096 rv = 1;
4097 }
4098 }
4099
4100 return rv;
4101}
4102
41f3d4d6
EH		 4103#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
4104 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
4105 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
4106#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
4107 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
4108 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
4109static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
4110{
4111 CPUState *cs = CPU(dev);
4112 X86CPU *cpu = X86_CPU(dev);
4113 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
4114 CPUX86State *env = &cpu->env;
4115 Error *local_err = NULL;
4116 static bool ht_warned;
4117
d6dcc558 4118 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
41f3d4d6
EH		 4119 char *name = x86_cpu_class_get_model_name(xcc);
4120 error_setg(&local_err, "CPU model '%s' requires KVM", name);
4121 g_free(name);
4122 goto out;
4123 }
4124
4125 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
4126 error_setg(errp, "apic-id property was not initialized properly");
4127 return;
4128 }
4129
b8d834a0 4130 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 4131 if (local_err) {
4132 goto out;
4133 }
4134
8ca30e86
EH		 4135 if (x86_cpu_filter_features(cpu) &&
4136 (cpu->check_cpuid || cpu->enforce_cpuid)) {
4137 x86_cpu_report_filtered_features(cpu);
4138 if (cpu->enforce_cpuid) {
4139 error_setg(&local_err,
d6dcc558 4140 accel_uses_host_cpuid() ?
8ca30e86
EH		 4141 "Host doesn't support requested features" :
4142 "TCG doesn't support requested features");
4143 goto out;
4144 }
9997cf7b
EH		 4145 }
4146
9b15cd9e
IM		 4147 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
4148 * CPUID[1].EDX.
4149 */
e48638fd 4150 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 4151 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
4152 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 4153 & CPUID_EXT2_AMD_ALIASES);
4154 }
4155
11f6fee5
DDAG		 4156 /* For 64bit systems think about the number of physical bits to present.
4157 * ideally this should be the same as the host; anything other than matching
4158 * the host can cause incorrect guest behaviour.
4159 * QEMU used to pick the magic value of 40 bits that corresponds to
4160 * consumer AMD devices but nothing else.
4161 */
af45907a 4162 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 4163 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 4164 uint32_t host_phys_bits = x86_host_phys_bits();
4165 static bool warned;
4166
4167 if (cpu->host_phys_bits) {
4168 /* The user asked for us to use the host physical bits */
4169 cpu->phys_bits = host_phys_bits;
4170 }
4171
4172 /* Print a warning if the user set it to a value that's not the
4173 * host value.
4174 */
4175 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
4176 !warned) {
3dc6f869
AF		 4177 warn_report("Host physical bits (%u)"
4178 " does not match phys-bits property (%u)",
4179 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 4180 warned = true;
4181 }
4182
4183 if (cpu->phys_bits &&
4184 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
4185 cpu->phys_bits < 32)) {
af45907a
DDAG		 4186 error_setg(errp, "phys-bits should be between 32 and %u "
4187 " (but is %u)",
4188 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
4189 return;
4190 }
4191 } else {
11f6fee5 4192 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 4193 error_setg(errp, "TCG only supports phys-bits=%u",
4194 TCG_PHYS_ADDR_BITS);
4195 return;
4196 }
4197 }
11f6fee5
DDAG		 4198 /* 0 means it was not explicitly set by the user (or by machine
4199 * compat_props or by the host code above). In this case, the default
4200 * is the value used by TCG (40).
4201 */
4202 if (cpu->phys_bits == 0) {
4203 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
4204 }
af45907a
DDAG		 4205 } else {
4206 /* For 32 bit systems don't use the user set value, but keep
4207 * phys_bits consistent with what we tell the guest.
4208 */
4209 if (cpu->phys_bits != 0) {
4210 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
4211 return;
4212 }
fefb41bf 4213
af45907a
DDAG		 4214 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
4215 cpu->phys_bits = 36;
4216 } else {
4217 cpu->phys_bits = 32;
4218 }
4219 }
ce5b1bbf
LV		 4220 cpu_exec_realizefn(cs, &local_err);
4221 if (local_err != NULL) {
4222 error_propagate(errp, local_err);
4223 return;
4224 }
42ecabaa 4225
65dee380
IM		 4226#ifndef CONFIG_USER_ONLY
4227 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 4228
0514ef2f 4229 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 4230 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 4231 if (local_err != NULL) {
4dc1f449 4232 goto out;
bdeec802
IM		 4233 }
4234 }
65dee380
IM		 4235#endif
4236
7a059953 4237 mce_init(cpu);
2001d0cd
PB		 4238
4239#ifndef CONFIG_USER_ONLY
4240 if (tcg_enabled()) {
f809c605 4241 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 4242 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 4243
4244 /* Outer container... */
4245 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 4246 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 4247
4248 /* ... with two regions inside: normal system memory with low
4249 * priority, and...
4250 */
4251 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
4252 get_system_memory(), 0, ~0ull);
4253 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
4254 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 4255
4256 cs->num_ases = 2;
80ceb07a
PX		 4257 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
4258 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 4259
4260 /* ... SMRAM with higher priority, linked from /machine/smram. */
4261 cpu->machine_done.notify = x86_cpu_machine_done;
4262 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 4263 }
4264#endif
4265
14a10fc3 4266 qemu_init_vcpu(cs);
d3c64d6a 4267
e48638fd
WH		 4268 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
4269 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
4270 * based on inputs (sockets,cores,threads), it is still better to gives
4271 * users a warning.
4272 *
4273 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
4274 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
4275 */
4276 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
4277 error_report("AMD CPU doesn't support hyperthreading. Please configure"
4278 " -smp options properly.");
4279 ht_warned = true;
4280 }
4281
d3c64d6a
IM		 4282 x86_cpu_apic_realize(cpu, &local_err);
4283 if (local_err != NULL) {
4284 goto out;
4285 }
14a10fc3 4286 cpu_reset(cs);
2b6f294c 4287
4dc1f449 4288 xcc->parent_realize(dev, &local_err);
2001d0cd 4289
4dc1f449
IM		 4290out:
4291 if (local_err != NULL) {
4292 error_propagate(errp, local_err);
4293 return;
4294 }
7a059953
AF		 4295}
4296
c884776e
IM		 4297static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
4298{
4299 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 4300 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
4301 Error *local_err = NULL;
c884776e
IM		 4302
4303#ifndef CONFIG_USER_ONLY
4304 cpu_remove_sync(CPU(dev));
4305 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
4306#endif
4307
4308 if (cpu->apic_state) {
4309 object_unparent(OBJECT(cpu->apic_state));
4310 cpu->apic_state = NULL;
4311 }
7bbc124e
LV		 4312
4313 xcc->parent_unrealize(dev, &local_err);
4314 if (local_err != NULL) {
4315 error_propagate(errp, local_err);
4316 return;
4317 }
c884776e
IM		 4318}
4319
38e5c119 4320typedef struct BitProperty {
a7b0ffac 4321 FeatureWord w;
38e5c119
EH		 4322 uint32_t mask;
4323} BitProperty;
4324
d7bce999
EB		 4325static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
4326 void *opaque, Error **errp)
38e5c119 4327{
a7b0ffac 4328 X86CPU *cpu = X86_CPU(obj);
38e5c119 4329 BitProperty *fp = opaque;
a7b0ffac
EH		 4330 uint32_t f = cpu->env.features[fp->w];
4331 bool value = (f & fp->mask) == fp->mask;
51e72bc1 4332 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 4333}
4334
d7bce999
EB		 4335static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
4336 void *opaque, Error **errp)
38e5c119
EH		 4337{
4338 DeviceState *dev = DEVICE(obj);
a7b0ffac 4339 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 4340 BitProperty *fp = opaque;
4341 Error *local_err = NULL;
4342 bool value;
4343
4344 if (dev->realized) {
4345 qdev_prop_set_after_realize(dev, name, errp);
4346 return;
4347 }
4348
51e72bc1 4349 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 4350 if (local_err) {
4351 error_propagate(errp, local_err);
4352 return;
4353 }
4354
4355 if (value) {
a7b0ffac 4356 cpu->env.features[fp->w] |= fp->mask;
38e5c119 4357 } else {
a7b0ffac 4358 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 4359 }
d4a606b3 4360 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 4361}
4362
4363static void x86_cpu_release_bit_prop(Object *obj, const char *name,
4364 void *opaque)
4365{
4366 BitProperty *prop = opaque;
4367 g_free(prop);
4368}
4369
4370/* Register a boolean property to get/set a single bit in a uint32_t field.
4371 *
4372 * The same property name can be registered multiple times to make it affect
4373 * multiple bits in the same FeatureWord. In that case, the getter will return
4374 * true only if all bits are set.
4375 */
4376static void x86_cpu_register_bit_prop(X86CPU *cpu,
4377 const char *prop_name,
a7b0ffac 4378 FeatureWord w,
38e5c119
EH		 4379 int bitnr)
4380{
4381 BitProperty *fp;
4382 ObjectProperty *op;
4383 uint32_t mask = (1UL << bitnr);
4384
4385 op = object_property_find(OBJECT(cpu), prop_name, NULL);
4386 if (op) {
4387 fp = op->opaque;
a7b0ffac 4388 assert(fp->w == w);
38e5c119
EH		 4389 fp->mask |= mask;
4390 } else {
4391 fp = g_new0(BitProperty, 1);
a7b0ffac 4392 fp->w = w;
38e5c119
EH		 4393 fp->mask = mask;
4394 object_property_add(OBJECT(cpu), prop_name, "bool",
4395 x86_cpu_get_bit_prop,
4396 x86_cpu_set_bit_prop,
4397 x86_cpu_release_bit_prop, fp, &error_abort);
4398 }
4399}
4400
4401static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
4402 FeatureWord w,
4403 int bitnr)
4404{
38e5c119 4405 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 4406 const char *name = fi->feat_names[bitnr];
38e5c119 4407
16d2fcaa 4408 if (!name) {
38e5c119
EH		 4409 return;
4410 }
4411
fc7dfd20
EH		 4412 /* Property names should use "-" instead of "_".
4413 * Old names containing underscores are registered as aliases
4414 * using object_property_add_alias()
4415 */
16d2fcaa
EH		 4416 assert(!strchr(name, '_'));
4417 /* aliases don't use "|" delimiters anymore, they are registered
4418 * manually using object_property_add_alias() */
4419 assert(!strchr(name, '|'));
a7b0ffac 4420 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 4421}
4422
d187e08d
AN		 4423static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
4424{
4425 X86CPU *cpu = X86_CPU(cs);
4426 CPUX86State *env = &cpu->env;
4427 GuestPanicInformation *panic_info = NULL;
4428
5e953812 4429 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 4430 panic_info = g_malloc0(sizeof(GuestPanicInformation));
4431
e8ed97a6 4432 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 4433
5e953812 4434 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 4435 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
4436 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
4437 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
4438 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
4439 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 4440 }
4441
4442 return panic_info;
4443}
4444static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
4445 const char *name, void *opaque,
4446 Error **errp)
4447{
4448 CPUState *cs = CPU(obj);
4449 GuestPanicInformation *panic_info;
4450
4451 if (!cs->crash_occurred) {
4452 error_setg(errp, "No crash occured");
4453 return;
4454 }
4455
4456 panic_info = x86_cpu_get_crash_info(cs);
4457 if (panic_info == NULL) {
4458 error_setg(errp, "No crash information");
4459 return;
4460 }
4461
4462 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
4463 errp);
4464 qapi_free_GuestPanicInformation(panic_info);
4465}
4466
de024815
AF		 4467static void x86_cpu_initfn(Object *obj)
4468{
55e5c285 4469 CPUState *cs = CPU(obj);
de024815 4470 X86CPU *cpu = X86_CPU(obj);
d940ee9b 4471 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 4472 CPUX86State *env = &cpu->env;
38e5c119 4473 FeatureWord w;
de024815 4474
c05efcb1 4475 cs->env_ptr = env;
71ad61d3
AF		 4476
4477 object_property_add(obj, "family", "int",
95b8519d 4478 x86_cpuid_version_get_family,
71ad61d3 4479 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 4480 object_property_add(obj, "model", "int",
67e30c83 4481 x86_cpuid_version_get_model,
c5291a4f 4482 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 4483 object_property_add(obj, "stepping", "int",
35112e41 4484 x86_cpuid_version_get_stepping,
036e2222 4485 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 4486 object_property_add_str(obj, "vendor",
4487 x86_cpuid_get_vendor,
4488 x86_cpuid_set_vendor, NULL);
938d4c25 4489 object_property_add_str(obj, "model-id",
63e886eb 4490 x86_cpuid_get_model_id,
938d4c25 4491 x86_cpuid_set_model_id, NULL);
89e48965
AF		 4492 object_property_add(obj, "tsc-frequency", "int",
4493 x86_cpuid_get_tsc_freq,
4494 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 4495 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
4496 x86_cpu_get_feature_words,
7e5292b5
EH		 4497 NULL, NULL, (void *)env->features, NULL);
4498 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
4499 x86_cpu_get_feature_words,
4500 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 4501
d187e08d
AN		 4502 object_property_add(obj, "crash-information", "GuestPanicInformation",
4503 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
4504
92067bf4 4505 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 4506
38e5c119
EH		 4507 for (w = 0; w < FEATURE_WORDS; w++) {
4508 int bitnr;
4509
4510 for (bitnr = 0; bitnr < 32; bitnr++) {
4511 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
4512 }
4513 }
4514
16d2fcaa
EH		 4515 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
4516 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
4517 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
4518 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
4519 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
4520 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
4521 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
4522
54b8dc7c
EH		 4523 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
4524 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
4525 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
4526 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
4527 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
4528 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
4529 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
4530 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
4531 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
4532 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
4533 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
4534 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
4535 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
4536 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
4537 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
4538 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
4539 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
4540 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
4541 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
4542 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
4543 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
4544
0bacd8b3
EH		 4545 if (xcc->cpu_def) {
4546 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
4547 }
de024815
AF		 4548}
4549
997395d3
IM		 4550static int64_t x86_cpu_get_arch_id(CPUState *cs)
4551{
4552 X86CPU *cpu = X86_CPU(cs);
997395d3 4553
7e72a45c 4554 return cpu->apic_id;
997395d3
IM		 4555}
4556
444d5590
AF		 4557static bool x86_cpu_get_paging_enabled(const CPUState *cs)
4558{
4559 X86CPU *cpu = X86_CPU(cs);
4560
4561 return cpu->env.cr[0] & CR0_PG_MASK;
4562}
4563
f45748f1
AF		 4564static void x86_cpu_set_pc(CPUState *cs, vaddr value)
4565{
4566 X86CPU *cpu = X86_CPU(cs);
4567
4568 cpu->env.eip = value;
4569}
4570
bdf7ae5b
AF		 4571static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
4572{
4573 X86CPU *cpu = X86_CPU(cs);
4574
4575 cpu->env.eip = tb->pc - tb->cs_base;
4576}
4577
8c2e1b00
AF		 4578static bool x86_cpu_has_work(CPUState *cs)
4579{
4580 X86CPU *cpu = X86_CPU(cs);
4581 CPUX86State *env = &cpu->env;
4582
6220e900
PD		 4583 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
4584 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 4585 (env->eflags & IF_MASK)) ||
4586 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
4587 CPU_INTERRUPT_INIT |
4588 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 4589 CPU_INTERRUPT_MCE)) ||
4590 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
4591 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 4592}
4593
f50f3dd5
RH		 4594static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
4595{
4596 X86CPU *cpu = X86_CPU(cs);
4597 CPUX86State *env = &cpu->env;
4598
4599 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
4600 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
4601 : bfd_mach_i386_i8086);
4602 info->print_insn = print_insn_i386;
b666d2a4
RH		 4603
4604 info->cap_arch = CS_ARCH_X86;
4605 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
4606 : env->hflags & HF_CS32_MASK ? CS_MODE_32
4607 : CS_MODE_16);
15fa1a0a
RH		 4608 info->cap_insn_unit = 1;
4609 info->cap_insn_split = 8;
f50f3dd5
RH		 4610}
4611
35b1b927
TW		 4612void x86_update_hflags(CPUX86State *env)
4613{
4614 uint32_t hflags;
4615#define HFLAG_COPY_MASK \
4616 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
4617 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
4618 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
4619 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
4620
4621 hflags = env->hflags & HFLAG_COPY_MASK;
4622 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
4623 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
4624 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
4625 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
4626 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
4627
4628 if (env->cr[4] & CR4_OSFXSR_MASK) {
4629 hflags |= HF_OSFXSR_MASK;
4630 }
4631
4632 if (env->efer & MSR_EFER_LMA) {
4633 hflags |= HF_LMA_MASK;
4634 }
4635
4636 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
4637 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
4638 } else {
4639 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
4640 (DESC_B_SHIFT - HF_CS32_SHIFT);
4641 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
4642 (DESC_B_SHIFT - HF_SS32_SHIFT);
4643 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
4644 !(hflags & HF_CS32_MASK)) {
4645 hflags |= HF_ADDSEG_MASK;
4646 } else {
4647 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
4648 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
4649 }
4650 }
4651 env->hflags = hflags;
4652}
4653
9337e3b6 4654static Property x86_cpu_properties[] = {
2da00e31
IM		 4655#ifdef CONFIG_USER_ONLY
4656 /* apic_id = 0 by default for *-user, see commit 9886e834 */
4657 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 4658 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
4659 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
4660 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 4661#else
4662 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 4663 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
4664 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
4665 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 4666#endif
15f8b142 4667 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 4668 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 4669 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 4670 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 4671 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 4672 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 4673 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 4674 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 4675 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 4676 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 4677 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 4678 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 4679 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 4680 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 4681 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 4682 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 4683 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 4684 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 4685 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
4686 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
4687 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
4688 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
4689 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
4690 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4691 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 4692 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 4693 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 4694 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 4695 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 4696 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
4697 false),
0b564e6f 4698 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 4699 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
6c69dfb6
GA		 4700
4701 /*
4702 * From "Requirements for Implementing the Microsoft
4703 * Hypervisor Interface":
4704 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
4705 *
4706 * "Starting with Windows Server 2012 and Windows 8, if
4707 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
4708 * the hypervisor imposes no specific limit to the number of VPs.
4709 * In this case, Windows Server 2012 guest VMs may use more than
4710 * 64 VPs, up to the maximum supported number of processors applicable
4711 * to the specific Windows version being used."
4712 */
4713 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9337e3b6
EH		 4714 DEFINE_PROP_END_OF_LIST()
4715};
4716
5fd2087a
AF		 4717static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
4718{
4719 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4720 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 4721 DeviceClass *dc = DEVICE_CLASS(oc);
4722
bf853881
PMD		 4723 device_class_set_parent_realize(dc, x86_cpu_realizefn,
4724 &xcc->parent_realize);
4725 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
4726 &xcc->parent_unrealize);
9337e3b6 4727 dc->props = x86_cpu_properties;
5fd2087a
AF		 4728
4729 xcc->parent_reset = cc->reset;
4730 cc->reset = x86_cpu_reset;
91b1df8c 4731 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 4732
500050d1 4733 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 4734 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 4735 cc->has_work = x86_cpu_has_work;
79c664f6 4736#ifdef CONFIG_TCG
97a8ea5a 4737 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 4738 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 4739#endif
878096ee 4740 cc->dump_state = x86_cpu_dump_state;
c86f106b 4741 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 4742 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 4743 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 4744 cc->gdb_read_register = x86_cpu_gdb_read_register;
4745 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 4746 cc->get_arch_id = x86_cpu_get_arch_id;
4747 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 4748#ifdef CONFIG_USER_ONLY
4749 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
4750#else
f8c45c65 4751 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 4752 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 4753 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 4754 cc->write_elf64_note = x86_cpu_write_elf64_note;
4755 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
4756 cc->write_elf32_note = x86_cpu_write_elf32_note;
4757 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 4758 cc->vmsd = &vmstate_x86_cpu;
c72bf468 4759#endif
00fcd100
AB		 4760 cc->gdb_arch_name = x86_gdb_arch_name;
4761#ifdef TARGET_X86_64
b8158192
AB		 4762 cc->gdb_core_xml_file = "i386-64bit.xml";
4763 cc->gdb_num_core_regs = 57;
00fcd100 4764#else
b8158192
AB		 4765 cc->gdb_core_xml_file = "i386-32bit.xml";
4766 cc->gdb_num_core_regs = 41;
00fcd100 4767#endif
79c664f6 4768#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 4769 cc->debug_excp_handler = breakpoint_handler;
4770#endif
374e0cd4
RH		 4771 cc->cpu_exec_enter = x86_cpu_exec_enter;
4772 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 4773#ifdef CONFIG_TCG
55c3ceef 4774 cc->tcg_initialize = tcg_x86_init;
74d7fc7f 4775#endif
f50f3dd5 4776 cc->disas_set_info = x86_disas_set_info;
4c315c27 4777
e90f2a8c 4778 dc->user_creatable = true;
5fd2087a
AF		 4779}
4780
4781static const TypeInfo x86_cpu_type_info = {
4782 .name = TYPE_X86_CPU,
4783 .parent = TYPE_CPU,
4784 .instance_size = sizeof(X86CPU),
de024815 4785 .instance_init = x86_cpu_initfn,
d940ee9b 4786 .abstract = true,
5fd2087a
AF		 4787 .class_size = sizeof(X86CPUClass),
4788 .class_init = x86_cpu_common_class_init,
4789};
4790
5adbed30
EH		 4791
4792/* "base" CPU model, used by query-cpu-model-expansion */
4793static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
4794{
4795 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4796
4797 xcc->static_model = true;
4798 xcc->migration_safe = true;
4799 xcc->model_description = "base CPU model type with no features enabled";
4800 xcc->ordering = 8;
4801}
4802
4803static const TypeInfo x86_base_cpu_type_info = {
4804 .name = X86_CPU_TYPE_NAME("base"),
4805 .parent = TYPE_X86_CPU,
4806 .class_init = x86_cpu_base_class_init,
4807};
4808
5fd2087a
AF		 4809static void x86_cpu_register_types(void)
4810{
d940ee9b
EH		 4811 int i;
4812
5fd2087a 4813 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 4814 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
4815 x86_register_cpudef_type(&builtin_x86_defs[i]);
4816 }
c62f2630 4817 type_register_static(&max_x86_cpu_type_info);
5adbed30 4818 type_register_static(&x86_base_cpu_type_info);
d6dcc558 4819#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 4820 type_register_static(&host_x86_cpu_type_info);
4821#endif
5fd2087a
AF		 4822}
4823
4824type_init(x86_cpu_register_types)
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