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cpu: drop unnecessary NULL check and cpu_common_class_by_name()
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
f348b6d1 21#include "qemu/cutils.h"
c6dc6f63
AP		 22
23#include "cpu.h"
63c91552 24#include "exec/exec-all.h"
9c17d615 25#include "sysemu/kvm.h"
d6dcc558 26#include "sysemu/hvf.h"
8932cfdf 27#include "sysemu/cpus.h"
50a2c6e5 28#include "kvm_i386.h"
6cb8f2a6 29#include "sev_i386.h"
c6dc6f63 30
d49b6836 31#include "qemu/error-report.h"
1de7afc9
PB		 32#include "qemu/option.h"
33#include "qemu/config-file.h"
e688df6b 34#include "qapi/error.h"
112ed241
MA		 35#include "qapi/qapi-visit-misc.h"
36#include "qapi/qapi-visit-run-state.h"
452fcdbc 37#include "qapi/qmp/qdict.h"
7b1b5d19 38#include "qapi/qmp/qerror.h"
7b1b5d19 39#include "qapi/visitor.h"
f99fd7ca 40#include "qom/qom-qobject.h"
9c17d615 41#include "sysemu/arch_init.h"
71ad61d3 42
b834b508 43#if defined(CONFIG_KVM)
ef8621b1 44#include <linux/kvm_para.h>
b834b508 45#endif
65dee380 46
9c17d615 47#include "sysemu/sysemu.h"
53a89e26 48#include "hw/qdev-properties.h"
5232d00a 49#include "hw/i386/topology.h"
bdeec802 50#ifndef CONFIG_USER_ONLY
2001d0cd 51#include "exec/address-spaces.h"
741da0d3 52#include "hw/hw.h"
0d09e41a 53#include "hw/xen/xen.h"
0d09e41a 54#include "hw/i386/apic_internal.h"
bdeec802
IM		 55#endif
56
b666d2a4
RH		 57#include "disas/capstone.h"
58
5e891bf8
EH		 59
60/* Cache topology CPUID constants: */
61
62/* CPUID Leaf 2 Descriptors */
63
64#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
65#define CPUID_2_L1I_32KB_8WAY_64B 0x30
66#define CPUID_2_L2_2MB_8WAY_64B 0x7d
14c985cf 67#define CPUID_2_L3_16MB_16WAY_64B 0x4d
5e891bf8
EH		 68
69
70/* CPUID Leaf 4 constants: */
71
72/* EAX: */
73#define CPUID_4_TYPE_DCACHE 1
74#define CPUID_4_TYPE_ICACHE 2
75#define CPUID_4_TYPE_UNIFIED 3
76
77#define CPUID_4_LEVEL(l) ((l) << 5)
78
79#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
80#define CPUID_4_FULLY_ASSOC (1 << 9)
81
82/* EDX: */
83#define CPUID_4_NO_INVD_SHARING (1 << 0)
84#define CPUID_4_INCLUSIVE (1 << 1)
85#define CPUID_4_COMPLEX_IDX (1 << 2)
86
87#define ASSOC_FULL 0xFF
88
89/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
90#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
91 a == 2 ? 0x2 : \
92 a == 4 ? 0x4 : \
93 a == 8 ? 0x6 : \
94 a == 16 ? 0x8 : \
95 a == 32 ? 0xA : \
96 a == 48 ? 0xB : \
97 a == 64 ? 0xC : \
98 a == 96 ? 0xD : \
99 a == 128 ? 0xE : \
100 a == ASSOC_FULL ? 0xF : \
101 0 /* invalid value */)
102
103
104/* Definitions of the hardcoded cache entries we expose: */
105
106/* L1 data cache: */
107#define L1D_LINE_SIZE 64
108#define L1D_ASSOCIATIVITY 8
109#define L1D_SETS 64
110#define L1D_PARTITIONS 1
111/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
112#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
113/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
114#define L1D_LINES_PER_TAG 1
115#define L1D_SIZE_KB_AMD 64
116#define L1D_ASSOCIATIVITY_AMD 2
117
118/* L1 instruction cache: */
119#define L1I_LINE_SIZE 64
120#define L1I_ASSOCIATIVITY 8
121#define L1I_SETS 64
122#define L1I_PARTITIONS 1
123/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
124#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
125/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
126#define L1I_LINES_PER_TAG 1
127#define L1I_SIZE_KB_AMD 64
128#define L1I_ASSOCIATIVITY_AMD 2
129
130/* Level 2 unified cache: */
131#define L2_LINE_SIZE 64
132#define L2_ASSOCIATIVITY 16
133#define L2_SETS 4096
134#define L2_PARTITIONS 1
135/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
136/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
137#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
138/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
139#define L2_LINES_PER_TAG 1
140#define L2_SIZE_KB_AMD 512
141
14c985cf 142/* Level 3 unified cache: */
5e891bf8
EH		 143#define L3_SIZE_KB 0 /* disabled */
144#define L3_ASSOCIATIVITY 0 /* disabled */
145#define L3_LINES_PER_TAG 0 /* disabled */
146#define L3_LINE_SIZE 0 /* disabled */
14c985cf
LM		 147#define L3_N_LINE_SIZE 64
148#define L3_N_ASSOCIATIVITY 16
149#define L3_N_SETS 16384
150#define L3_N_PARTITIONS 1
151#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
152#define L3_N_LINES_PER_TAG 1
153#define L3_N_SIZE_KB_AMD 16384
5e891bf8
EH		 154
155/* TLB definitions: */
156
157#define L1_DTLB_2M_ASSOC 1
158#define L1_DTLB_2M_ENTRIES 255
159#define L1_DTLB_4K_ASSOC 1
160#define L1_DTLB_4K_ENTRIES 255
161
162#define L1_ITLB_2M_ASSOC 1
163#define L1_ITLB_2M_ENTRIES 255
164#define L1_ITLB_4K_ASSOC 1
165#define L1_ITLB_4K_ENTRIES 255
166
167#define L2_DTLB_2M_ASSOC 0 /* disabled */
168#define L2_DTLB_2M_ENTRIES 0 /* disabled */
169#define L2_DTLB_4K_ASSOC 4
170#define L2_DTLB_4K_ENTRIES 512
171
172#define L2_ITLB_2M_ASSOC 0 /* disabled */
173#define L2_ITLB_2M_ENTRIES 0 /* disabled */
174#define L2_ITLB_4K_ASSOC 4
175#define L2_ITLB_4K_ENTRIES 512
176
e37a5c7f
CP		 177/* CPUID Leaf 0x14 constants: */
178#define INTEL_PT_MAX_SUBLEAF 0x1
179/*
180 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
181 * MSR can be accessed;
182 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
183 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
184 * of Intel PT MSRs across warm reset;
185 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
186 */
187#define INTEL_PT_MINIMAL_EBX 0xf
188/*
189 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
190 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
191 * accessed;
192 * bit[01]: ToPA tables can hold any number of output entries, up to the
193 * maximum allowed by the MaskOrTableOffset field of
194 * IA32_RTIT_OUTPUT_MASK_PTRS;
195 * bit[02]: Support Single-Range Output scheme;
196 */
197#define INTEL_PT_MINIMAL_ECX 0x7
198#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
199#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
200#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
201#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
202#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 203
99b88a17
IM		 204static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
205 uint32_t vendor2, uint32_t vendor3)
206{
207 int i;
208 for (i = 0; i < 4; i++) {
209 dst[i] = vendor1 >> (8 * i);
210 dst[i + 4] = vendor2 >> (8 * i);
211 dst[i + 8] = vendor3 >> (8 * i);
212 }
213 dst[CPUID_VENDOR_SZ] = '\0';
214}
215
621626ce
EH		 216#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
217#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
218 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
219#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
220 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
221 CPUID_PSE36 | CPUID_FXSR)
222#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
223#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
224 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
225 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
226 CPUID_PAE | CPUID_SEP | CPUID_APIC)
227
228#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
229 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
230 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
231 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 232 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 233 /* partly implemented:
234 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
235 /* missing:
236 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
237#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
238 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
239 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 240 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 241 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
242 /* missing:
243 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
244 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
245 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 246 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
247 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 248
249#ifdef TARGET_X86_64
250#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
251#else
252#define TCG_EXT2_X86_64_FEATURES 0
253#endif
254
255#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
256 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
257 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
258 TCG_EXT2_X86_64_FEATURES)
259#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
260 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
261#define TCG_EXT4_FEATURES 0
262#define TCG_SVM_FEATURES 0
263#define TCG_KVM_FEATURES 0
264#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 265 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
266 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 267 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
268 CPUID_7_0_EBX_ERMS)
621626ce 269 /* missing:
07929f2a 270 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 271 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 272 CPUID_7_0_EBX_RDSEED */
6c7c3c21
KS		 273#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
274 CPUID_7_0_ECX_LA57)
95ea69fb 275#define TCG_7_0_EDX_FEATURES 0
303752a9 276#define TCG_APM_FEATURES 0
28b8e4d0 277#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 278#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
279 /* missing:
280 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 281
5ef57876 282typedef struct FeatureWordInfo {
2d5312da
EH		 283 /* feature flags names are taken from "Intel Processor Identification and
284 * the CPUID Instruction" and AMD's "CPUID Specification".
285 * In cases of disagreement between feature naming conventions,
286 * aliases may be added.
287 */
288 const char *feat_names[32];
04d104b6
EH		 289 uint32_t cpuid_eax; /* Input EAX for CPUID */
290 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
291 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
292 int cpuid_reg; /* output register (R_* constant) */
37ce3522 293 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 294 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 295 uint32_t migratable_flags; /* Feature flags known to be migratable */
5ef57876
EH		 296} FeatureWordInfo;
297
298static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 299 [FEAT_1_EDX] = {
2d5312da
EH		 300 .feat_names = {
301 "fpu", "vme", "de", "pse",
302 "tsc", "msr", "pae", "mce",
303 "cx8", "apic", NULL, "sep",
304 "mtrr", "pge", "mca", "cmov",
305 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
306 NULL, "ds" /* Intel dts */, "acpi", "mmx",
307 "fxsr", "sse", "sse2", "ss",
308 "ht" /* Intel htt */, "tm", "ia64", "pbe",
309 },
bffd67b0 310 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 311 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 312 },
313 [FEAT_1_ECX] = {
2d5312da 314 .feat_names = {
16d2fcaa 315 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 316 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 317 "tm2", "ssse3", "cid", NULL,
318 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 319 NULL, "pcid", "dca", "sse4.1",
320 "sse4.2", "x2apic", "movbe", "popcnt",
2d5312da
EH		 321 "tsc-deadline", "aes", "xsave", "osxsave",
322 "avx", "f16c", "rdrand", "hypervisor",
323 },
bffd67b0 324 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 325 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 326 },
2d5312da
EH		 327 /* Feature names that are already defined on feature_name[] but
328 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
329 * names on feat_names below. They are copied automatically
330 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
331 */
bffd67b0 332 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 333 .feat_names = {
334 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
335 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
336 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
337 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
338 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 339 "nx", NULL, "mmxext", NULL /* mmx */,
340 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
341 NULL, "lm", "3dnowext", "3dnow",
2d5312da 342 },
bffd67b0 343 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 344 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 345 },
346 [FEAT_8000_0001_ECX] = {
2d5312da 347 .feat_names = {
fc7dfd20 348 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 349 "cr8legacy", "abm", "sse4a", "misalignsse",
350 "3dnowprefetch", "osvw", "ibs", "xop",
351 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 352 "fma4", "tce", NULL, "nodeid-msr",
353 NULL, "tbm", "topoext", "perfctr-core",
354 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 355 NULL, NULL, NULL, NULL,
356 },
bffd67b0 357 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 358 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 359 },
89e49c8b 360 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 361 .feat_names = {
362 NULL, NULL, "xstore", "xstore-en",
363 NULL, NULL, "xcrypt", "xcrypt-en",
364 "ace2", "ace2-en", "phe", "phe-en",
365 "pmm", "pmm-en", NULL, NULL,
366 NULL, NULL, NULL, NULL,
367 NULL, NULL, NULL, NULL,
368 NULL, NULL, NULL, NULL,
369 NULL, NULL, NULL, NULL,
370 },
89e49c8b 371 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 372 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 373 },
bffd67b0 374 [FEAT_KVM] = {
2d5312da 375 .feat_names = {
fc7dfd20
EH		 376 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
377 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
6976af66 378 NULL, "kvm-pv-tlb-flush", NULL, NULL,
2d5312da
EH		 379 NULL, NULL, NULL, NULL,
380 NULL, NULL, NULL, NULL,
381 NULL, NULL, NULL, NULL,
382 "kvmclock-stable-bit", NULL, NULL, NULL,
383 NULL, NULL, NULL, NULL,
384 },
bffd67b0 385 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 386 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 387 },
be777326
WL		 388 [FEAT_KVM_HINTS] = {
389 .feat_names = {
390 "kvm-hint-dedicated", NULL, NULL, NULL,
391 NULL, NULL, NULL, NULL,
392 NULL, NULL, NULL, NULL,
393 NULL, NULL, NULL, NULL,
394 NULL, NULL, NULL, NULL,
395 NULL, NULL, NULL, NULL,
396 NULL, NULL, NULL, NULL,
397 NULL, NULL, NULL, NULL,
398 },
399 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EDX,
400 .tcg_features = TCG_KVM_FEATURES,
401 },
c35bd19a 402 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 403 .feat_names = {
404 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
405 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
406 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
407 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
408 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
409 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
410 NULL, NULL, NULL, NULL,
411 NULL, NULL, NULL, NULL,
412 NULL, NULL, NULL, NULL,
413 NULL, NULL, NULL, NULL,
414 NULL, NULL, NULL, NULL,
415 },
c35bd19a
EY		 416 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
417 },
418 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 419 .feat_names = {
420 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
421 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
422 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
423 NULL /* hv_create_port */, NULL /* hv_connect_port */,
424 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
425 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
426 NULL, NULL,
427 NULL, NULL, NULL, NULL,
428 NULL, NULL, NULL, NULL,
429 NULL, NULL, NULL, NULL,
430 NULL, NULL, NULL, NULL,
431 },
c35bd19a
EY		 432 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
433 },
434 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 435 .feat_names = {
436 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
437 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
438 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
439 NULL, NULL,
440 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
441 NULL, NULL, NULL, NULL,
442 NULL, NULL, NULL, NULL,
443 NULL, NULL, NULL, NULL,
444 NULL, NULL, NULL, NULL,
445 NULL, NULL, NULL, NULL,
446 },
c35bd19a
EY		 447 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
448 },
bffd67b0 449 [FEAT_SVM] = {
2d5312da 450 .feat_names = {
fc7dfd20
EH		 451 "npt", "lbrv", "svm-lock", "nrip-save",
452 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
453 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 454 "pfthreshold", NULL, NULL, NULL,
455 NULL, NULL, NULL, NULL,
456 NULL, NULL, NULL, NULL,
457 NULL, NULL, NULL, NULL,
458 NULL, NULL, NULL, NULL,
459 },
bffd67b0 460 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 461 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 462 },
463 [FEAT_7_0_EBX] = {
2d5312da 464 .feat_names = {
fc7dfd20 465 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 466 "hle", "avx2", NULL, "smep",
467 "bmi2", "erms", "invpcid", "rtm",
468 NULL, NULL, "mpx", NULL,
469 "avx512f", "avx512dq", "rdseed", "adx",
470 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 471 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 472 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 473 },
04d104b6
EH		 474 .cpuid_eax = 7,
475 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
476 .cpuid_reg = R_EBX,
37ce3522 477 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 478 },
f74eefe0 479 [FEAT_7_0_ECX] = {
2d5312da
EH		 480 .feat_names = {
481 NULL, "avx512vbmi", "umip", "pku",
aff9e6e4
YZ		 482 "ospke", NULL, "avx512vbmi2", NULL,
483 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
484 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 485 "la57", NULL, NULL, NULL,
2d5312da
EH		 486 NULL, NULL, "rdpid", NULL,
487 NULL, NULL, NULL, NULL,
488 NULL, NULL, NULL, NULL,
489 },
f74eefe0
HH		 490 .cpuid_eax = 7,
491 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
492 .cpuid_reg = R_ECX,
493 .tcg_features = TCG_7_0_ECX_FEATURES,
494 },
95ea69fb
LK		 495 [FEAT_7_0_EDX] = {
496 .feat_names = {
497 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
498 NULL, NULL, NULL, NULL,
499 NULL, NULL, NULL, NULL,
500 NULL, NULL, NULL, NULL,
501 NULL, NULL, NULL, NULL,
502 NULL, NULL, NULL, NULL,
a2381f09 503 NULL, NULL, "spec-ctrl", NULL,
95ea69fb
LK		 504 NULL, NULL, NULL, NULL,
505 },
506 .cpuid_eax = 7,
507 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
508 .cpuid_reg = R_EDX,
509 .tcg_features = TCG_7_0_EDX_FEATURES,
510 },
303752a9 511 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 512 .feat_names = {
513 NULL, NULL, NULL, NULL,
514 NULL, NULL, NULL, NULL,
515 "invtsc", NULL, NULL, NULL,
516 NULL, NULL, NULL, NULL,
517 NULL, NULL, NULL, NULL,
518 NULL, NULL, NULL, NULL,
519 NULL, NULL, NULL, NULL,
520 NULL, NULL, NULL, NULL,
521 },
303752a9
MT		 522 .cpuid_eax = 0x80000007,
523 .cpuid_reg = R_EDX,
524 .tcg_features = TCG_APM_FEATURES,
525 .unmigratable_flags = CPUID_APM_INVTSC,
526 },
1b3420e1
EH		 527 [FEAT_8000_0008_EBX] = {
528 .feat_names = {
529 NULL, NULL, NULL, NULL,
530 NULL, NULL, NULL, NULL,
531 NULL, NULL, NULL, NULL,
532 "ibpb", NULL, NULL, NULL,
533 NULL, NULL, NULL, NULL,
534 NULL, NULL, NULL, NULL,
535 NULL, NULL, NULL, NULL,
536 NULL, NULL, NULL, NULL,
537 },
538 .cpuid_eax = 0x80000008,
539 .cpuid_reg = R_EBX,
540 .tcg_features = 0,
541 .unmigratable_flags = 0,
542 },
0bb0b2d2 543 [FEAT_XSAVE] = {
2d5312da
EH		 544 .feat_names = {
545 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
546 NULL, NULL, NULL, NULL,
547 NULL, NULL, NULL, NULL,
548 NULL, NULL, NULL, NULL,
549 NULL, NULL, NULL, NULL,
550 NULL, NULL, NULL, NULL,
551 NULL, NULL, NULL, NULL,
552 NULL, NULL, NULL, NULL,
553 },
0bb0b2d2
PB		 554 .cpuid_eax = 0xd,
555 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
556 .cpuid_reg = R_EAX,
c9cfe8f9 557 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 558 },
28b8e4d0 559 [FEAT_6_EAX] = {
2d5312da
EH		 560 .feat_names = {
561 NULL, NULL, "arat", NULL,
562 NULL, NULL, NULL, NULL,
563 NULL, NULL, NULL, NULL,
564 NULL, NULL, NULL, NULL,
565 NULL, NULL, NULL, NULL,
566 NULL, NULL, NULL, NULL,
567 NULL, NULL, NULL, NULL,
568 NULL, NULL, NULL, NULL,
569 },
28b8e4d0
JK		 570 .cpuid_eax = 6, .cpuid_reg = R_EAX,
571 .tcg_features = TCG_6_EAX_FEATURES,
572 },
96193c22
EH		 573 [FEAT_XSAVE_COMP_LO] = {
574 .cpuid_eax = 0xD,
575 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
576 .cpuid_reg = R_EAX,
577 .tcg_features = ~0U,
6fb2fff7
EH		 578 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
579 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
580 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
581 XSTATE_PKRU_MASK,
96193c22
EH		 582 },
583 [FEAT_XSAVE_COMP_HI] = {
584 .cpuid_eax = 0xD,
585 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
586 .cpuid_reg = R_EDX,
587 .tcg_features = ~0U,
588 },
5ef57876
EH		 589};
590
8e8aba50
EH		 591typedef struct X86RegisterInfo32 {
592 /* Name of register */
593 const char *name;
594 /* QAPI enum value register */
595 X86CPURegister32 qapi_enum;
596} X86RegisterInfo32;
597
598#define REGISTER(reg) \
5d371f41 599 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 600static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 601 REGISTER(EAX),
602 REGISTER(ECX),
603 REGISTER(EDX),
604 REGISTER(EBX),
605 REGISTER(ESP),
606 REGISTER(EBP),
607 REGISTER(ESI),
608 REGISTER(EDI),
609};
610#undef REGISTER
611
3f32bd21
RH		 612typedef struct ExtSaveArea {
613 uint32_t feature, bits;
614 uint32_t offset, size;
615} ExtSaveArea;
616
617static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 618 [XSTATE_FP_BIT] = {
619 /* x87 FP state component is always enabled if XSAVE is supported */
620 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
621 /* x87 state is in the legacy region of the XSAVE area */
622 .offset = 0,
623 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
624 },
625 [XSTATE_SSE_BIT] = {
626 /* SSE state component is always enabled if XSAVE is supported */
627 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
628 /* SSE state is in the legacy region of the XSAVE area */
629 .offset = 0,
630 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
631 },
cfc3b074
PB		 632 [XSTATE_YMM_BIT] =
633 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 634 .offset = offsetof(X86XSaveArea, avx_state),
635 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 636 [XSTATE_BNDREGS_BIT] =
637 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 638 .offset = offsetof(X86XSaveArea, bndreg_state),
639 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 640 [XSTATE_BNDCSR_BIT] =
641 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 642 .offset = offsetof(X86XSaveArea, bndcsr_state),
643 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 644 [XSTATE_OPMASK_BIT] =
645 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 646 .offset = offsetof(X86XSaveArea, opmask_state),
647 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 648 [XSTATE_ZMM_Hi256_BIT] =
649 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 650 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
651 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 652 [XSTATE_Hi16_ZMM_BIT] =
653 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 654 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
655 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 656 [XSTATE_PKRU_BIT] =
657 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 658 .offset = offsetof(X86XSaveArea, pkru_state),
659 .size = sizeof(XSavePKRU) },
2560f19f 660};
8e8aba50 661
1fda6198
EH		 662static uint32_t xsave_area_size(uint64_t mask)
663{
664 int i;
e3c9022b 665 uint64_t ret = 0;
1fda6198 666
e3c9022b 667 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 668 const ExtSaveArea *esa = &x86_ext_save_areas[i];
669 if ((mask >> i) & 1) {
670 ret = MAX(ret, esa->offset + esa->size);
671 }
672 }
673 return ret;
674}
675
d6dcc558
SAGDR		 676static inline bool accel_uses_host_cpuid(void)
677{
678 return kvm_enabled() || hvf_enabled();
679}
680
96193c22
EH		 681static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
682{
683 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
684 cpu->env.features[FEAT_XSAVE_COMP_LO];
685}
686
8b4beddc
EH		 687const char *get_register_name_32(unsigned int reg)
688{
31ccdde2 689 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 690 return NULL;
691 }
8e8aba50 692 return x86_reg_info_32[reg].name;
8b4beddc
EH		 693}
694
84f1b92f
EH		 695/*
696 * Returns the set of feature flags that are supported and migratable by
697 * QEMU, for a given FeatureWord.
698 */
699static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
700{
701 FeatureWordInfo *wi = &feature_word_info[w];
702 uint32_t r = 0;
703 int i;
704
705 for (i = 0; i < 32; i++) {
706 uint32_t f = 1U << i;
6fb2fff7
EH		 707
708 /* If the feature name is known, it is implicitly considered migratable,
709 * unless it is explicitly set in unmigratable_flags */
710 if ((wi->migratable_flags & f) ||
711 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
712 r |= f;
84f1b92f 713 }
84f1b92f
EH		 714 }
715 return r;
716}
717
bb44e0d1
JK		 718void host_cpuid(uint32_t function, uint32_t count,
719 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 720{
a1fd24af
AL		 721 uint32_t vec[4];
722
723#ifdef __x86_64__
724 asm volatile("cpuid"
725 : "=a"(vec[0]), "=b"(vec[1]),
726 "=c"(vec[2]), "=d"(vec[3])
727 : "0"(function), "c"(count) : "cc");
c1f41226 728#elif defined(__i386__)
a1fd24af
AL		 729 asm volatile("pusha \n\t"
730 "cpuid \n\t"
731 "mov %%eax, 0(%2) \n\t"
732 "mov %%ebx, 4(%2) \n\t"
733 "mov %%ecx, 8(%2) \n\t"
734 "mov %%edx, 12(%2) \n\t"
735 "popa"
736 : : "a"(function), "c"(count), "S"(vec)
737 : "memory", "cc");
c1f41226
EH		 738#else
739 abort();
a1fd24af
AL		 740#endif
741
bdde476a 742 if (eax)
a1fd24af 743 *eax = vec[0];
bdde476a 744 if (ebx)
a1fd24af 745 *ebx = vec[1];
bdde476a 746 if (ecx)
a1fd24af 747 *ecx = vec[2];
bdde476a 748 if (edx)
a1fd24af 749 *edx = vec[3];
bdde476a 750}
c6dc6f63 751
20271d48
EH		 752void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
753{
754 uint32_t eax, ebx, ecx, edx;
755
756 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
757 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
758
759 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
760 if (family) {
761 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
762 }
763 if (model) {
764 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
765 }
766 if (stepping) {
767 *stepping = eax & 0x0F;
768 }
769}
770
d940ee9b
EH		 771/* CPU class name definitions: */
772
d940ee9b
EH		 773/* Return type name for a given CPU model name
774 * Caller is responsible for freeing the returned string.
775 */
776static char *x86_cpu_type_name(const char *model_name)
777{
778 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
779}
780
500050d1
AF		 781static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
782{
d940ee9b 783 ObjectClass *oc;
99193d8f 784 char *typename = x86_cpu_type_name(cpu_model);
d940ee9b
EH		 785 oc = object_class_by_name(typename);
786 g_free(typename);
787 return oc;
500050d1
AF		 788}
789
104494ea
IM		 790static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
791{
792 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
793 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
794 return g_strndup(class_name,
795 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
796}
797
d940ee9b 798struct X86CPUDefinition {
c6dc6f63
AP		 799 const char *name;
800 uint32_t level;
90e4b0c3 801 uint32_t xlevel;
99b88a17
IM		 802 /* vendor is zero-terminated, 12 character ASCII string */
803 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 804 int family;
805 int model;
806 int stepping;
0514ef2f 807 FeatureWordArray features;
807e9869 808 const char *model_id;
d940ee9b 809};
c6dc6f63 810
9576de75 811static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 812 {
813 .name = "qemu64",
3046bb5d 814 .level = 0xd,
99b88a17 815 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 816 .family = 6,
f8e6a11a 817 .model = 6,
c6dc6f63 818 .stepping = 3,
0514ef2f 819 .features[FEAT_1_EDX] =
27861ecc 820 PPRO_FEATURES |
c6dc6f63 821 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 822 CPUID_PSE36,
0514ef2f 823 .features[FEAT_1_ECX] =
6aa91e4a 824 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 825 .features[FEAT_8000_0001_EDX] =
c6dc6f63 826 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 827 .features[FEAT_8000_0001_ECX] =
71195672 828 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 829 .xlevel = 0x8000000A,
9cf2cc3d 830 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 831 },
832 {
833 .name = "phenom",
834 .level = 5,
99b88a17 835 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 836 .family = 16,
837 .model = 2,
838 .stepping = 3,
b9fc20bc 839 /* Missing: CPUID_HT */
0514ef2f 840 .features[FEAT_1_EDX] =
27861ecc 841 PPRO_FEATURES |
c6dc6f63 842 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 843 CPUID_PSE36 | CPUID_VME,
0514ef2f 844 .features[FEAT_1_ECX] =
27861ecc 845 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 846 CPUID_EXT_POPCNT,
0514ef2f 847 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 848 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
849 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 850 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 851 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
852 CPUID_EXT3_CR8LEG,
853 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
854 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 855 .features[FEAT_8000_0001_ECX] =
27861ecc 856 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 857 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 858 /* Missing: CPUID_SVM_LBRV */
0514ef2f 859 .features[FEAT_SVM] =
b9fc20bc 860 CPUID_SVM_NPT,
c6dc6f63
AP		 861 .xlevel = 0x8000001A,
862 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
863 },
864 {
865 .name = "core2duo",
866 .level = 10,
99b88a17 867 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 868 .family = 6,
869 .model = 15,
870 .stepping = 11,
b9fc20bc 871 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 872 .features[FEAT_1_EDX] =
27861ecc 873 PPRO_FEATURES |
c6dc6f63 874 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 875 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
876 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 877 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 878 .features[FEAT_1_ECX] =
27861ecc 879 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 880 CPUID_EXT_CX16,
0514ef2f 881 .features[FEAT_8000_0001_EDX] =
27861ecc 882 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 883 .features[FEAT_8000_0001_ECX] =
27861ecc 884 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 885 .xlevel = 0x80000008,
886 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
887 },
888 {
889 .name = "kvm64",
3046bb5d 890 .level = 0xd,
99b88a17 891 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 892 .family = 15,
893 .model = 6,
894 .stepping = 1,
b3a4f0b1 895 /* Missing: CPUID_HT */
0514ef2f 896 .features[FEAT_1_EDX] =
b3a4f0b1 897 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 898 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
899 CPUID_PSE36,
900 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 901 .features[FEAT_1_ECX] =
27861ecc 902 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 903 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 904 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 905 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
906 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
907 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
908 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
909 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 910 .features[FEAT_8000_0001_ECX] =
27861ecc 911 0,
c6dc6f63
AP		 912 .xlevel = 0x80000008,
913 .model_id = "Common KVM processor"
914 },
c6dc6f63
AP		 915 {
916 .name = "qemu32",
917 .level = 4,
99b88a17 918 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 919 .family = 6,
f8e6a11a 920 .model = 6,
c6dc6f63 921 .stepping = 3,
0514ef2f 922 .features[FEAT_1_EDX] =
27861ecc 923 PPRO_FEATURES,
0514ef2f 924 .features[FEAT_1_ECX] =
6aa91e4a 925 CPUID_EXT_SSE3,
58012d66 926 .xlevel = 0x80000004,
9cf2cc3d 927 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 928 },
eafaf1e5
AP		 929 {
930 .name = "kvm32",
931 .level = 5,
99b88a17 932 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 933 .family = 15,
934 .model = 6,
935 .stepping = 1,
0514ef2f 936 .features[FEAT_1_EDX] =
b3a4f0b1 937 PPRO_FEATURES | CPUID_VME |
eafaf1e5 938 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 939 .features[FEAT_1_ECX] =
27861ecc 940 CPUID_EXT_SSE3,
0514ef2f 941 .features[FEAT_8000_0001_ECX] =
27861ecc 942 0,
eafaf1e5
AP		 943 .xlevel = 0x80000008,
944 .model_id = "Common 32-bit KVM processor"
945 },
c6dc6f63
AP		 946 {
947 .name = "coreduo",
948 .level = 10,
99b88a17 949 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 950 .family = 6,
951 .model = 14,
952 .stepping = 8,
b9fc20bc 953 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 954 .features[FEAT_1_EDX] =
27861ecc 955 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 956 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
957 CPUID_SS,
958 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 959 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 960 .features[FEAT_1_ECX] =
e93abc14 961 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 962 .features[FEAT_8000_0001_EDX] =
27861ecc 963 CPUID_EXT2_NX,
c6dc6f63
AP		 964 .xlevel = 0x80000008,
965 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
966 },
967 {
968 .name = "486",
58012d66 969 .level = 1,
99b88a17 970 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 971 .family = 4,
b2a856d9 972 .model = 8,
c6dc6f63 973 .stepping = 0,
0514ef2f 974 .features[FEAT_1_EDX] =
27861ecc 975 I486_FEATURES,
c6dc6f63 976 .xlevel = 0,
807e9869 977 .model_id = "",
c6dc6f63
AP		 978 },
979 {
980 .name = "pentium",
981 .level = 1,
99b88a17 982 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 983 .family = 5,
984 .model = 4,
985 .stepping = 3,
0514ef2f 986 .features[FEAT_1_EDX] =
27861ecc 987 PENTIUM_FEATURES,
c6dc6f63 988 .xlevel = 0,
807e9869 989 .model_id = "",
c6dc6f63
AP		 990 },
991 {
992 .name = "pentium2",
993 .level = 2,
99b88a17 994 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 995 .family = 6,
996 .model = 5,
997 .stepping = 2,
0514ef2f 998 .features[FEAT_1_EDX] =
27861ecc 999 PENTIUM2_FEATURES,
c6dc6f63 1000 .xlevel = 0,
807e9869 1001 .model_id = "",
c6dc6f63
AP		 1002 },
1003 {
1004 .name = "pentium3",
3046bb5d 1005 .level = 3,
99b88a17 1006 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1007 .family = 6,
1008 .model = 7,
1009 .stepping = 3,
0514ef2f 1010 .features[FEAT_1_EDX] =
27861ecc 1011 PENTIUM3_FEATURES,
c6dc6f63 1012 .xlevel = 0,
807e9869 1013 .model_id = "",
c6dc6f63
AP		 1014 },
1015 {
1016 .name = "athlon",
1017 .level = 2,
99b88a17 1018 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1019 .family = 6,
1020 .model = 2,
1021 .stepping = 3,
0514ef2f 1022 .features[FEAT_1_EDX] =
27861ecc 1023 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 1024 CPUID_MCA,
0514ef2f 1025 .features[FEAT_8000_0001_EDX] =
60032ac0 1026 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 1027 .xlevel = 0x80000008,
9cf2cc3d 1028 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1029 },
1030 {
1031 .name = "n270",
3046bb5d 1032 .level = 10,
99b88a17 1033 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1034 .family = 6,
1035 .model = 28,
1036 .stepping = 2,
b9fc20bc 1037 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1038 .features[FEAT_1_EDX] =
27861ecc 1039 PPRO_FEATURES |
b9fc20bc
EH		 1040 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1041 CPUID_ACPI | CPUID_SS,
c6dc6f63 1042 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1043 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1044 * CPUID_EXT_XTPR */
0514ef2f 1045 .features[FEAT_1_ECX] =
27861ecc 1046 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1047 CPUID_EXT_MOVBE,
0514ef2f 1048 .features[FEAT_8000_0001_EDX] =
60032ac0 1049 CPUID_EXT2_NX,
0514ef2f 1050 .features[FEAT_8000_0001_ECX] =
27861ecc 1051 CPUID_EXT3_LAHF_LM,
3046bb5d 1052 .xlevel = 0x80000008,
c6dc6f63
AP		 1053 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1054 },
3eca4642
EH		 1055 {
1056 .name = "Conroe",
3046bb5d 1057 .level = 10,
99b88a17 1058 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1059 .family = 6,
ffce9ebb 1060 .model = 15,
3eca4642 1061 .stepping = 3,
0514ef2f 1062 .features[FEAT_1_EDX] =
b3a4f0b1 1063 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1064 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1065 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1066 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1067 CPUID_DE | CPUID_FP87,
0514ef2f 1068 .features[FEAT_1_ECX] =
27861ecc 1069 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1070 .features[FEAT_8000_0001_EDX] =
27861ecc 1071 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1072 .features[FEAT_8000_0001_ECX] =
27861ecc 1073 CPUID_EXT3_LAHF_LM,
3046bb5d 1074 .xlevel = 0x80000008,
3eca4642
EH		 1075 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1076 },
1077 {
1078 .name = "Penryn",
3046bb5d 1079 .level = 10,
99b88a17 1080 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1081 .family = 6,
ffce9ebb 1082 .model = 23,
3eca4642 1083 .stepping = 3,
0514ef2f 1084 .features[FEAT_1_EDX] =
b3a4f0b1 1085 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1086 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1087 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1088 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1089 CPUID_DE | CPUID_FP87,
0514ef2f 1090 .features[FEAT_1_ECX] =
27861ecc 1091 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1092 CPUID_EXT_SSE3,
0514ef2f 1093 .features[FEAT_8000_0001_EDX] =
27861ecc 1094 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1095 .features[FEAT_8000_0001_ECX] =
27861ecc 1096 CPUID_EXT3_LAHF_LM,
3046bb5d 1097 .xlevel = 0x80000008,
3eca4642
EH		 1098 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1099 },
1100 {
1101 .name = "Nehalem",
3046bb5d 1102 .level = 11,
99b88a17 1103 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1104 .family = 6,
ffce9ebb 1105 .model = 26,
3eca4642 1106 .stepping = 3,
0514ef2f 1107 .features[FEAT_1_EDX] =
b3a4f0b1 1108 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1109 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1110 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1111 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1112 CPUID_DE | CPUID_FP87,
0514ef2f 1113 .features[FEAT_1_ECX] =
27861ecc 1114 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1115 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1116 .features[FEAT_8000_0001_EDX] =
27861ecc 1117 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1118 .features[FEAT_8000_0001_ECX] =
27861ecc 1119 CPUID_EXT3_LAHF_LM,
3046bb5d 1120 .xlevel = 0x80000008,
3eca4642
EH		 1121 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1122 },
ac96c413
EH		 1123 {
1124 .name = "Nehalem-IBRS",
1125 .level = 11,
1126 .vendor = CPUID_VENDOR_INTEL,
1127 .family = 6,
1128 .model = 26,
1129 .stepping = 3,
1130 .features[FEAT_1_EDX] =
1131 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1132 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1133 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1134 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1135 CPUID_DE | CPUID_FP87,
1136 .features[FEAT_1_ECX] =
1137 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1138 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1139 .features[FEAT_7_0_EDX] =
1140 CPUID_7_0_EDX_SPEC_CTRL,
1141 .features[FEAT_8000_0001_EDX] =
1142 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1143 .features[FEAT_8000_0001_ECX] =
1144 CPUID_EXT3_LAHF_LM,
1145 .xlevel = 0x80000008,
1146 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1147 },
3eca4642
EH		 1148 {
1149 .name = "Westmere",
1150 .level = 11,
99b88a17 1151 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1152 .family = 6,
1153 .model = 44,
1154 .stepping = 1,
0514ef2f 1155 .features[FEAT_1_EDX] =
b3a4f0b1 1156 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1157 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1158 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1159 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1160 CPUID_DE | CPUID_FP87,
0514ef2f 1161 .features[FEAT_1_ECX] =
27861ecc 1162 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1163 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1164 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1165 .features[FEAT_8000_0001_EDX] =
27861ecc 1166 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1167 .features[FEAT_8000_0001_ECX] =
27861ecc 1168 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1169 .features[FEAT_6_EAX] =
1170 CPUID_6_EAX_ARAT,
3046bb5d 1171 .xlevel = 0x80000008,
3eca4642
EH		 1172 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1173 },
ac96c413
EH		 1174 {
1175 .name = "Westmere-IBRS",
1176 .level = 11,
1177 .vendor = CPUID_VENDOR_INTEL,
1178 .family = 6,
1179 .model = 44,
1180 .stepping = 1,
1181 .features[FEAT_1_EDX] =
1182 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1183 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1184 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1185 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1186 CPUID_DE | CPUID_FP87,
1187 .features[FEAT_1_ECX] =
1188 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1189 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1190 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1191 .features[FEAT_8000_0001_EDX] =
1192 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1193 .features[FEAT_8000_0001_ECX] =
1194 CPUID_EXT3_LAHF_LM,
1195 .features[FEAT_7_0_EDX] =
1196 CPUID_7_0_EDX_SPEC_CTRL,
1197 .features[FEAT_6_EAX] =
1198 CPUID_6_EAX_ARAT,
1199 .xlevel = 0x80000008,
1200 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1201 },
3eca4642
EH		 1202 {
1203 .name = "SandyBridge",
1204 .level = 0xd,
99b88a17 1205 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1206 .family = 6,
1207 .model = 42,
1208 .stepping = 1,
0514ef2f 1209 .features[FEAT_1_EDX] =
b3a4f0b1 1210 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1211 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1212 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1213 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1214 CPUID_DE | CPUID_FP87,
0514ef2f 1215 .features[FEAT_1_ECX] =
27861ecc 1216 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1217 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1218 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1219 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1220 CPUID_EXT_SSE3,
0514ef2f 1221 .features[FEAT_8000_0001_EDX] =
27861ecc 1222 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1223 CPUID_EXT2_SYSCALL,
0514ef2f 1224 .features[FEAT_8000_0001_ECX] =
27861ecc 1225 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1226 .features[FEAT_XSAVE] =
1227 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1228 .features[FEAT_6_EAX] =
1229 CPUID_6_EAX_ARAT,
3046bb5d 1230 .xlevel = 0x80000008,
3eca4642
EH		 1231 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1232 },
ac96c413
EH		 1233 {
1234 .name = "SandyBridge-IBRS",
1235 .level = 0xd,
1236 .vendor = CPUID_VENDOR_INTEL,
1237 .family = 6,
1238 .model = 42,
1239 .stepping = 1,
1240 .features[FEAT_1_EDX] =
1241 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1242 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1243 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1244 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1245 CPUID_DE | CPUID_FP87,
1246 .features[FEAT_1_ECX] =
1247 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1248 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1249 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1250 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1251 CPUID_EXT_SSE3,
1252 .features[FEAT_8000_0001_EDX] =
1253 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1254 CPUID_EXT2_SYSCALL,
1255 .features[FEAT_8000_0001_ECX] =
1256 CPUID_EXT3_LAHF_LM,
1257 .features[FEAT_7_0_EDX] =
1258 CPUID_7_0_EDX_SPEC_CTRL,
1259 .features[FEAT_XSAVE] =
1260 CPUID_XSAVE_XSAVEOPT,
1261 .features[FEAT_6_EAX] =
1262 CPUID_6_EAX_ARAT,
1263 .xlevel = 0x80000008,
1264 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1265 },
2f9ac42a
PB		 1266 {
1267 .name = "IvyBridge",
1268 .level = 0xd,
1269 .vendor = CPUID_VENDOR_INTEL,
1270 .family = 6,
1271 .model = 58,
1272 .stepping = 9,
1273 .features[FEAT_1_EDX] =
1274 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1275 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1276 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1277 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1278 CPUID_DE | CPUID_FP87,
1279 .features[FEAT_1_ECX] =
1280 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1281 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1282 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1283 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1284 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1285 .features[FEAT_7_0_EBX] =
1286 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1287 CPUID_7_0_EBX_ERMS,
1288 .features[FEAT_8000_0001_EDX] =
1289 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1290 CPUID_EXT2_SYSCALL,
1291 .features[FEAT_8000_0001_ECX] =
1292 CPUID_EXT3_LAHF_LM,
1293 .features[FEAT_XSAVE] =
1294 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1295 .features[FEAT_6_EAX] =
1296 CPUID_6_EAX_ARAT,
3046bb5d 1297 .xlevel = 0x80000008,
2f9ac42a
PB		 1298 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1299 },
ac96c413
EH		 1300 {
1301 .name = "IvyBridge-IBRS",
1302 .level = 0xd,
1303 .vendor = CPUID_VENDOR_INTEL,
1304 .family = 6,
1305 .model = 58,
1306 .stepping = 9,
1307 .features[FEAT_1_EDX] =
1308 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1309 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1310 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1311 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1312 CPUID_DE | CPUID_FP87,
1313 .features[FEAT_1_ECX] =
1314 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1315 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1316 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1317 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1318 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1319 .features[FEAT_7_0_EBX] =
1320 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1321 CPUID_7_0_EBX_ERMS,
1322 .features[FEAT_8000_0001_EDX] =
1323 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1324 CPUID_EXT2_SYSCALL,
1325 .features[FEAT_8000_0001_ECX] =
1326 CPUID_EXT3_LAHF_LM,
1327 .features[FEAT_7_0_EDX] =
1328 CPUID_7_0_EDX_SPEC_CTRL,
1329 .features[FEAT_XSAVE] =
1330 CPUID_XSAVE_XSAVEOPT,
1331 .features[FEAT_6_EAX] =
1332 CPUID_6_EAX_ARAT,
1333 .xlevel = 0x80000008,
1334 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
1335 },
37507094 1336 {
a356850b
EH		 1337 .name = "Haswell-noTSX",
1338 .level = 0xd,
1339 .vendor = CPUID_VENDOR_INTEL,
1340 .family = 6,
1341 .model = 60,
1342 .stepping = 1,
1343 .features[FEAT_1_EDX] =
1344 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1345 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1346 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1347 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1348 CPUID_DE | CPUID_FP87,
1349 .features[FEAT_1_ECX] =
1350 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1351 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1352 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1353 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1354 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1355 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1356 .features[FEAT_8000_0001_EDX] =
1357 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1358 CPUID_EXT2_SYSCALL,
1359 .features[FEAT_8000_0001_ECX] =
becb6667 1360 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1361 .features[FEAT_7_0_EBX] =
1362 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1363 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1364 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1365 .features[FEAT_XSAVE] =
1366 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1367 .features[FEAT_6_EAX] =
1368 CPUID_6_EAX_ARAT,
3046bb5d 1369 .xlevel = 0x80000008,
a356850b 1370 .model_id = "Intel Core Processor (Haswell, no TSX)",
ac96c413
EH		 1371 },
1372 {
1373 .name = "Haswell-noTSX-IBRS",
1374 .level = 0xd,
1375 .vendor = CPUID_VENDOR_INTEL,
1376 .family = 6,
1377 .model = 60,
1378 .stepping = 1,
1379 .features[FEAT_1_EDX] =
1380 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1381 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1382 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1383 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1384 CPUID_DE | CPUID_FP87,
1385 .features[FEAT_1_ECX] =
1386 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1387 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1388 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1389 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1390 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1391 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1392 .features[FEAT_8000_0001_EDX] =
1393 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1394 CPUID_EXT2_SYSCALL,
1395 .features[FEAT_8000_0001_ECX] =
1396 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1397 .features[FEAT_7_0_EDX] =
1398 CPUID_7_0_EDX_SPEC_CTRL,
1399 .features[FEAT_7_0_EBX] =
1400 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1401 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1402 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1403 .features[FEAT_XSAVE] =
1404 CPUID_XSAVE_XSAVEOPT,
1405 .features[FEAT_6_EAX] =
1406 CPUID_6_EAX_ARAT,
1407 .xlevel = 0x80000008,
1408 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
1409 },
1410 {
37507094
EH		 1411 .name = "Haswell",
1412 .level = 0xd,
99b88a17 1413 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1414 .family = 6,
1415 .model = 60,
ec56a4a7 1416 .stepping = 4,
0514ef2f 1417 .features[FEAT_1_EDX] =
b3a4f0b1 1418 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1419 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1420 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1421 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1422 CPUID_DE | CPUID_FP87,
0514ef2f 1423 .features[FEAT_1_ECX] =
27861ecc 1424 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1425 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1426 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1427 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1428 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1429 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1430 .features[FEAT_8000_0001_EDX] =
27861ecc 1431 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1432 CPUID_EXT2_SYSCALL,
0514ef2f 1433 .features[FEAT_8000_0001_ECX] =
becb6667 1434 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1435 .features[FEAT_7_0_EBX] =
27861ecc 1436 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1437 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1438 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1439 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1440 .features[FEAT_XSAVE] =
1441 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1442 .features[FEAT_6_EAX] =
1443 CPUID_6_EAX_ARAT,
3046bb5d 1444 .xlevel = 0x80000008,
37507094
EH		 1445 .model_id = "Intel Core Processor (Haswell)",
1446 },
ac96c413
EH		 1447 {
1448 .name = "Haswell-IBRS",
1449 .level = 0xd,
1450 .vendor = CPUID_VENDOR_INTEL,
1451 .family = 6,
1452 .model = 60,
1453 .stepping = 4,
1454 .features[FEAT_1_EDX] =
1455 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1456 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1457 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1458 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1459 CPUID_DE | CPUID_FP87,
1460 .features[FEAT_1_ECX] =
1461 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1462 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1463 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1464 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1465 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1466 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1467 .features[FEAT_8000_0001_EDX] =
1468 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1469 CPUID_EXT2_SYSCALL,
1470 .features[FEAT_8000_0001_ECX] =
1471 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1472 .features[FEAT_7_0_EDX] =
1473 CPUID_7_0_EDX_SPEC_CTRL,
1474 .features[FEAT_7_0_EBX] =
1475 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1476 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1477 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1478 CPUID_7_0_EBX_RTM,
1479 .features[FEAT_XSAVE] =
1480 CPUID_XSAVE_XSAVEOPT,
1481 .features[FEAT_6_EAX] =
1482 CPUID_6_EAX_ARAT,
1483 .xlevel = 0x80000008,
1484 .model_id = "Intel Core Processor (Haswell, IBRS)",
1485 },
a356850b
EH		 1486 {
1487 .name = "Broadwell-noTSX",
1488 .level = 0xd,
1489 .vendor = CPUID_VENDOR_INTEL,
1490 .family = 6,
1491 .model = 61,
1492 .stepping = 2,
1493 .features[FEAT_1_EDX] =
1494 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1495 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1496 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1497 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1498 CPUID_DE | CPUID_FP87,
1499 .features[FEAT_1_ECX] =
1500 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1501 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1502 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1503 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1504 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1505 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1506 .features[FEAT_8000_0001_EDX] =
1507 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1508 CPUID_EXT2_SYSCALL,
1509 .features[FEAT_8000_0001_ECX] =
becb6667 1510 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1511 .features[FEAT_7_0_EBX] =
1512 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1513 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1514 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1515 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1516 CPUID_7_0_EBX_SMAP,
1517 .features[FEAT_XSAVE] =
1518 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1519 .features[FEAT_6_EAX] =
1520 CPUID_6_EAX_ARAT,
3046bb5d 1521 .xlevel = 0x80000008,
a356850b
EH		 1522 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1523 },
ac96c413
EH		 1524 {
1525 .name = "Broadwell-noTSX-IBRS",
1526 .level = 0xd,
1527 .vendor = CPUID_VENDOR_INTEL,
1528 .family = 6,
1529 .model = 61,
1530 .stepping = 2,
1531 .features[FEAT_1_EDX] =
1532 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1533 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1534 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1535 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1536 CPUID_DE | CPUID_FP87,
1537 .features[FEAT_1_ECX] =
1538 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1539 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1540 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1541 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1542 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1543 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1544 .features[FEAT_8000_0001_EDX] =
1545 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1546 CPUID_EXT2_SYSCALL,
1547 .features[FEAT_8000_0001_ECX] =
1548 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1549 .features[FEAT_7_0_EDX] =
1550 CPUID_7_0_EDX_SPEC_CTRL,
1551 .features[FEAT_7_0_EBX] =
1552 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1553 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1554 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1555 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1556 CPUID_7_0_EBX_SMAP,
1557 .features[FEAT_XSAVE] =
1558 CPUID_XSAVE_XSAVEOPT,
1559 .features[FEAT_6_EAX] =
1560 CPUID_6_EAX_ARAT,
1561 .xlevel = 0x80000008,
1562 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
1563 },
ece01354
EH		 1564 {
1565 .name = "Broadwell",
1566 .level = 0xd,
1567 .vendor = CPUID_VENDOR_INTEL,
1568 .family = 6,
1569 .model = 61,
1570 .stepping = 2,
1571 .features[FEAT_1_EDX] =
b3a4f0b1 1572 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1573 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1574 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1575 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1576 CPUID_DE | CPUID_FP87,
1577 .features[FEAT_1_ECX] =
1578 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1579 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1580 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1581 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1582 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1583 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1584 .features[FEAT_8000_0001_EDX] =
1585 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1586 CPUID_EXT2_SYSCALL,
1587 .features[FEAT_8000_0001_ECX] =
becb6667 1588 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1589 .features[FEAT_7_0_EBX] =
1590 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1591 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1592 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1593 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1594 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1595 .features[FEAT_XSAVE] =
1596 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1597 .features[FEAT_6_EAX] =
1598 CPUID_6_EAX_ARAT,
3046bb5d 1599 .xlevel = 0x80000008,
ece01354
EH		 1600 .model_id = "Intel Core Processor (Broadwell)",
1601 },
ac96c413
EH		 1602 {
1603 .name = "Broadwell-IBRS",
1604 .level = 0xd,
1605 .vendor = CPUID_VENDOR_INTEL,
1606 .family = 6,
1607 .model = 61,
1608 .stepping = 2,
1609 .features[FEAT_1_EDX] =
1610 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1611 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1612 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1613 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1614 CPUID_DE | CPUID_FP87,
1615 .features[FEAT_1_ECX] =
1616 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1617 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1618 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1619 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1620 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1621 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1622 .features[FEAT_8000_0001_EDX] =
1623 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1624 CPUID_EXT2_SYSCALL,
1625 .features[FEAT_8000_0001_ECX] =
1626 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1627 .features[FEAT_7_0_EDX] =
1628 CPUID_7_0_EDX_SPEC_CTRL,
1629 .features[FEAT_7_0_EBX] =
1630 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1631 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1632 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1633 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1634 CPUID_7_0_EBX_SMAP,
1635 .features[FEAT_XSAVE] =
1636 CPUID_XSAVE_XSAVEOPT,
1637 .features[FEAT_6_EAX] =
1638 CPUID_6_EAX_ARAT,
1639 .xlevel = 0x80000008,
1640 .model_id = "Intel Core Processor (Broadwell, IBRS)",
1641 },
f6f949e9
EH		 1642 {
1643 .name = "Skylake-Client",
1644 .level = 0xd,
1645 .vendor = CPUID_VENDOR_INTEL,
1646 .family = 6,
1647 .model = 94,
1648 .stepping = 3,
1649 .features[FEAT_1_EDX] =
1650 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1651 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1652 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1653 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1654 CPUID_DE | CPUID_FP87,
1655 .features[FEAT_1_ECX] =
1656 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1657 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1658 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1659 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1660 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1661 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1662 .features[FEAT_8000_0001_EDX] =
1663 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1664 CPUID_EXT2_SYSCALL,
1665 .features[FEAT_8000_0001_ECX] =
1666 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1667 .features[FEAT_7_0_EBX] =
1668 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1669 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1670 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1671 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1672 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1673 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 1674 * including v4.1 to v4.12).
f6f949e9
EH		 1675 * KVM doesn't yet expose any XSAVES state save component,
1676 * and the only one defined in Skylake (processor tracing)
1677 * probably will block migration anyway.
1678 */
1679 .features[FEAT_XSAVE] =
1680 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1681 CPUID_XSAVE_XGETBV1,
1682 .features[FEAT_6_EAX] =
1683 CPUID_6_EAX_ARAT,
1684 .xlevel = 0x80000008,
1685 .model_id = "Intel Core Processor (Skylake)",
1686 },
ac96c413
EH		 1687 {
1688 .name = "Skylake-Client-IBRS",
1689 .level = 0xd,
1690 .vendor = CPUID_VENDOR_INTEL,
1691 .family = 6,
1692 .model = 94,
1693 .stepping = 3,
1694 .features[FEAT_1_EDX] =
1695 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1696 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1697 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1698 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1699 CPUID_DE | CPUID_FP87,
1700 .features[FEAT_1_ECX] =
1701 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1702 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1703 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1704 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1705 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1706 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1707 .features[FEAT_8000_0001_EDX] =
1708 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1709 CPUID_EXT2_SYSCALL,
1710 .features[FEAT_8000_0001_ECX] =
1711 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1712 .features[FEAT_7_0_EDX] =
1713 CPUID_7_0_EDX_SPEC_CTRL,
1714 .features[FEAT_7_0_EBX] =
1715 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1716 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1717 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1718 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1719 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1720 /* Missing: XSAVES (not supported by some Linux versions,
1721 * including v4.1 to v4.12).
1722 * KVM doesn't yet expose any XSAVES state save component,
1723 * and the only one defined in Skylake (processor tracing)
1724 * probably will block migration anyway.
1725 */
1726 .features[FEAT_XSAVE] =
1727 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1728 CPUID_XSAVE_XGETBV1,
1729 .features[FEAT_6_EAX] =
1730 CPUID_6_EAX_ARAT,
1731 .xlevel = 0x80000008,
1732 .model_id = "Intel Core Processor (Skylake, IBRS)",
1733 },
53f9a6f4
BF		 1734 {
1735 .name = "Skylake-Server",
1736 .level = 0xd,
1737 .vendor = CPUID_VENDOR_INTEL,
1738 .family = 6,
1739 .model = 85,
1740 .stepping = 4,
1741 .features[FEAT_1_EDX] =
1742 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1743 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1744 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1745 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1746 CPUID_DE | CPUID_FP87,
1747 .features[FEAT_1_ECX] =
1748 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1749 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1750 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1751 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1752 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1753 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1754 .features[FEAT_8000_0001_EDX] =
1755 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
1756 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1757 .features[FEAT_8000_0001_ECX] =
1758 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1759 .features[FEAT_7_0_EBX] =
1760 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1761 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1762 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1763 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1764 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
1765 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
1766 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 1767 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
53f9a6f4
BF		 1768 /* Missing: XSAVES (not supported by some Linux versions,
1769 * including v4.1 to v4.12).
1770 * KVM doesn't yet expose any XSAVES state save component,
1771 * and the only one defined in Skylake (processor tracing)
1772 * probably will block migration anyway.
1773 */
1774 .features[FEAT_XSAVE] =
1775 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1776 CPUID_XSAVE_XGETBV1,
1777 .features[FEAT_6_EAX] =
1778 CPUID_6_EAX_ARAT,
1779 .xlevel = 0x80000008,
1780 .model_id = "Intel Xeon Processor (Skylake)",
1781 },
ac96c413
EH		 1782 {
1783 .name = "Skylake-Server-IBRS",
1784 .level = 0xd,
1785 .vendor = CPUID_VENDOR_INTEL,
1786 .family = 6,
1787 .model = 85,
1788 .stepping = 4,
1789 .features[FEAT_1_EDX] =
1790 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1791 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1792 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1793 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1794 CPUID_DE | CPUID_FP87,
1795 .features[FEAT_1_ECX] =
1796 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1797 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1798 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1799 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1800 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1801 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1802 .features[FEAT_8000_0001_EDX] =
1803 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
1804 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1805 .features[FEAT_8000_0001_ECX] =
1806 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1807 .features[FEAT_7_0_EDX] =
1808 CPUID_7_0_EDX_SPEC_CTRL,
1809 .features[FEAT_7_0_EBX] =
1810 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1811 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1812 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1813 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1814 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
1815 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
1816 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
1817 CPUID_7_0_EBX_AVX512VL,
1818 /* Missing: XSAVES (not supported by some Linux versions,
1819 * including v4.1 to v4.12).
1820 * KVM doesn't yet expose any XSAVES state save component,
1821 * and the only one defined in Skylake (processor tracing)
1822 * probably will block migration anyway.
1823 */
1824 .features[FEAT_XSAVE] =
1825 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1826 CPUID_XSAVE_XGETBV1,
1827 .features[FEAT_6_EAX] =
1828 CPUID_6_EAX_ARAT,
1829 .xlevel = 0x80000008,
1830 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
1831 },
3eca4642
EH		 1832 {
1833 .name = "Opteron_G1",
1834 .level = 5,
99b88a17 1835 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1836 .family = 15,
1837 .model = 6,
1838 .stepping = 1,
0514ef2f 1839 .features[FEAT_1_EDX] =
b3a4f0b1 1840 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1841 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1842 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1843 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1844 CPUID_DE | CPUID_FP87,
0514ef2f 1845 .features[FEAT_1_ECX] =
27861ecc 1846 CPUID_EXT_SSE3,
0514ef2f 1847 .features[FEAT_8000_0001_EDX] =
2a923a29 1848 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 1849 .xlevel = 0x80000008,
1850 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1851 },
1852 {
1853 .name = "Opteron_G2",
1854 .level = 5,
99b88a17 1855 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1856 .family = 15,
1857 .model = 6,
1858 .stepping = 1,
0514ef2f 1859 .features[FEAT_1_EDX] =
b3a4f0b1 1860 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1861 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1862 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1863 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1864 CPUID_DE | CPUID_FP87,
0514ef2f 1865 .features[FEAT_1_ECX] =
27861ecc 1866 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1867 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1868 .features[FEAT_8000_0001_EDX] =
2a923a29 1869 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1870 .features[FEAT_8000_0001_ECX] =
27861ecc 1871 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1872 .xlevel = 0x80000008,
1873 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1874 },
1875 {
1876 .name = "Opteron_G3",
1877 .level = 5,
99b88a17 1878 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 1879 .family = 16,
1880 .model = 2,
1881 .stepping = 3,
0514ef2f 1882 .features[FEAT_1_EDX] =
b3a4f0b1 1883 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1884 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1885 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1886 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1887 CPUID_DE | CPUID_FP87,
0514ef2f 1888 .features[FEAT_1_ECX] =
27861ecc 1889 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1890 CPUID_EXT_SSE3,
33b5e8c0 1891 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1892 .features[FEAT_8000_0001_EDX] =
2a923a29 1893 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1894 .features[FEAT_8000_0001_ECX] =
27861ecc 1895 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1896 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1897 .xlevel = 0x80000008,
1898 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1899 },
1900 {
1901 .name = "Opteron_G4",
1902 .level = 0xd,
99b88a17 1903 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1904 .family = 21,
1905 .model = 1,
1906 .stepping = 2,
0514ef2f 1907 .features[FEAT_1_EDX] =
b3a4f0b1 1908 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1909 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1910 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1911 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1912 CPUID_DE | CPUID_FP87,
0514ef2f 1913 .features[FEAT_1_ECX] =
27861ecc 1914 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1915 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1916 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1917 CPUID_EXT_SSE3,
33b5e8c0 1918 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1919 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1920 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1921 CPUID_EXT2_SYSCALL,
0514ef2f 1922 .features[FEAT_8000_0001_ECX] =
27861ecc 1923 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1924 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1925 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1926 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1927 /* no xsaveopt! */
3eca4642
EH		 1928 .xlevel = 0x8000001A,
1929 .model_id = "AMD Opteron 62xx class CPU",
1930 },
021941b9
AP		 1931 {
1932 .name = "Opteron_G5",
1933 .level = 0xd,
99b88a17 1934 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1935 .family = 21,
1936 .model = 2,
1937 .stepping = 0,
0514ef2f 1938 .features[FEAT_1_EDX] =
b3a4f0b1 1939 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1940 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1941 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1942 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1943 CPUID_DE | CPUID_FP87,
0514ef2f 1944 .features[FEAT_1_ECX] =
27861ecc 1945 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1946 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1947 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1948 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1949 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1950 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 1951 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1952 CPUID_EXT2_SYSCALL,
0514ef2f 1953 .features[FEAT_8000_0001_ECX] =
27861ecc 1954 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1955 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1956 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1957 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1958 /* no xsaveopt! */
021941b9
AP		 1959 .xlevel = 0x8000001A,
1960 .model_id = "AMD Opteron 63xx class CPU",
1961 },
2e2efc7d
BS		 1962 {
1963 .name = "EPYC",
1964 .level = 0xd,
1965 .vendor = CPUID_VENDOR_AMD,
1966 .family = 23,
1967 .model = 1,
1968 .stepping = 2,
1969 .features[FEAT_1_EDX] =
1970 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
1971 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
1972 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
1973 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
1974 CPUID_VME | CPUID_FP87,
1975 .features[FEAT_1_ECX] =
1976 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
1977 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
1978 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1979 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
1980 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1981 .features[FEAT_8000_0001_EDX] =
1982 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
1983 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
1984 CPUID_EXT2_SYSCALL,
1985 .features[FEAT_8000_0001_ECX] =
1986 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
1987 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
1988 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1989 .features[FEAT_7_0_EBX] =
1990 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
1991 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
1992 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
1993 CPUID_7_0_EBX_SHA_NI,
1994 /* Missing: XSAVES (not supported by some Linux versions,
1995 * including v4.1 to v4.12).
1996 * KVM doesn't yet expose any XSAVES state save component.
1997 */
1998 .features[FEAT_XSAVE] =
1999 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2000 CPUID_XSAVE_XGETBV1,
2001 .features[FEAT_6_EAX] =
2002 CPUID_6_EAX_ARAT,
2003 .xlevel = 0x8000000A,
2004 .model_id = "AMD EPYC Processor",
2005 },
6cfbc54e
EH		 2006 {
2007 .name = "EPYC-IBPB",
2008 .level = 0xd,
2009 .vendor = CPUID_VENDOR_AMD,
2010 .family = 23,
2011 .model = 1,
2012 .stepping = 2,
2013 .features[FEAT_1_EDX] =
2014 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2015 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2016 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2017 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2018 CPUID_VME | CPUID_FP87,
2019 .features[FEAT_1_ECX] =
2020 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2021 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2022 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2023 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2024 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2025 .features[FEAT_8000_0001_EDX] =
2026 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2027 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2028 CPUID_EXT2_SYSCALL,
2029 .features[FEAT_8000_0001_ECX] =
2030 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2031 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2032 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2033 .features[FEAT_8000_0008_EBX] =
2034 CPUID_8000_0008_EBX_IBPB,
2035 .features[FEAT_7_0_EBX] =
2036 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2037 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2038 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2039 CPUID_7_0_EBX_SHA_NI,
2040 /* Missing: XSAVES (not supported by some Linux versions,
2041 * including v4.1 to v4.12).
2042 * KVM doesn't yet expose any XSAVES state save component.
2043 */
2044 .features[FEAT_XSAVE] =
2045 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2046 CPUID_XSAVE_XGETBV1,
2047 .features[FEAT_6_EAX] =
2048 CPUID_6_EAX_ARAT,
2049 .xlevel = 0x8000000A,
2050 .model_id = "AMD EPYC Processor (with IBPB)",
2051 },
c6dc6f63
AP		 2052};
2053
5114e842
EH		 2054typedef struct PropValue {
2055 const char *prop, *value;
2056} PropValue;
2057
2058/* KVM-specific features that are automatically added/removed
2059 * from all CPU models when KVM is enabled.
2060 */
2061static PropValue kvm_default_props[] = {
2062 { "kvmclock", "on" },
2063 { "kvm-nopiodelay", "on" },
2064 { "kvm-asyncpf", "on" },
2065 { "kvm-steal-time", "on" },
2066 { "kvm-pv-eoi", "on" },
2067 { "kvmclock-stable-bit", "on" },
2068 { "x2apic", "on" },
2069 { "acpi", "off" },
2070 { "monitor", "off" },
2071 { "svm", "off" },
2072 { NULL, NULL },
2073};
2074
04d99c3c
EH		 2075/* TCG-specific defaults that override all CPU models when using TCG
2076 */
2077static PropValue tcg_default_props[] = {
2078 { "vme", "off" },
2079 { NULL, NULL },
2080};
2081
2082
5114e842
EH		 2083void x86_cpu_change_kvm_default(const char *prop, const char *value)
2084{
2085 PropValue *pv;
2086 for (pv = kvm_default_props; pv->prop; pv++) {
2087 if (!strcmp(pv->prop, prop)) {
2088 pv->value = value;
2089 break;
2090 }
2091 }
2092
2093 /* It is valid to call this function only for properties that
2094 * are already present in the kvm_default_props table.
2095 */
2096 assert(pv->prop);
2097}
2098
4d1b279b
EH		 2099static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2100 bool migratable_only);
2101
40bfe48f
HZ		 2102static bool lmce_supported(void)
2103{
c62f2630 2104 uint64_t mce_cap = 0;
40bfe48f 2105
c62f2630 2106#ifdef CONFIG_KVM
40bfe48f
HZ		 2107 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
2108 return false;
2109 }
c62f2630 2110#endif
40bfe48f
HZ		 2111
2112 return !!(mce_cap & MCG_LMCE_P);
2113}
2114
7d8050b5
EH		 2115#define CPUID_MODEL_ID_SZ 48
2116
2117/**
2118 * cpu_x86_fill_model_id:
2119 * Get CPUID model ID string from host CPU.
2120 *
2121 * @str should have at least CPUID_MODEL_ID_SZ bytes
2122 *
2123 * The function does NOT add a null terminator to the string
2124 * automatically.
2125 */
c6dc6f63
AP		 2126static int cpu_x86_fill_model_id(char *str)
2127{
2128 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2129 int i;
2130
2131 for (i = 0; i < 3; i++) {
2132 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
2133 memcpy(str + i * 16 + 0, &eax, 4);
2134 memcpy(str + i * 16 + 4, &ebx, 4);
2135 memcpy(str + i * 16 + 8, &ecx, 4);
2136 memcpy(str + i * 16 + 12, &edx, 4);
2137 }
2138 return 0;
2139}
2140
c62f2630 2141static Property max_x86_cpu_properties[] = {
120eee7d 2142 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 2143 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 2144 DEFINE_PROP_END_OF_LIST()
2145};
2146
c62f2630 2147static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 2148{
84f1b92f 2149 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 2150 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 2151
f48c8837 2152 xcc->ordering = 9;
6e746f30 2153
ee465a3e 2154 xcc->model_description =
c62f2630 2155 "Enables all features supported by the accelerator in the current host";
d940ee9b 2156
c62f2630 2157 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 2158}
2159
0bacd8b3
EH		 2160static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
2161
c62f2630 2162static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 2163{
2164 X86CPU *cpu = X86_CPU(obj);
2165 CPUX86State *env = &cpu->env;
2166 KVMState *s = kvm_state;
d940ee9b 2167
4d1b279b
EH		 2168 /* We can't fill the features array here because we don't know yet if
2169 * "migratable" is true or false.
2170 */
44bd8e53 2171 cpu->max_features = true;
4d1b279b 2172
d6dcc558 2173 if (accel_uses_host_cpuid()) {
bd182022
EH		 2174 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
2175 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
2176 int family, model, stepping;
d6dcc558
SAGDR		 2177 X86CPUDefinition host_cpudef = { };
2178 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2179
2180 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
2181 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
0bacd8b3 2182
bd182022 2183 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 2184
bd182022 2185 cpu_x86_fill_model_id(model_id);
0bacd8b3 2186
bd182022
EH		 2187 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
2188 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
2189 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
2190 object_property_set_int(OBJECT(cpu), stepping, "stepping",
2191 &error_abort);
2192 object_property_set_str(OBJECT(cpu), model_id, "model-id",
2193 &error_abort);
0bacd8b3 2194
d6dcc558
SAGDR		 2195 if (kvm_enabled()) {
2196 env->cpuid_min_level =
2197 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
2198 env->cpuid_min_xlevel =
2199 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
2200 env->cpuid_min_xlevel2 =
2201 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2202 } else {
2203 env->cpuid_min_level =
2204 hvf_get_supported_cpuid(0x0, 0, R_EAX);
2205 env->cpuid_min_xlevel =
2206 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
2207 env->cpuid_min_xlevel2 =
2208 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
2209 }
40bfe48f
HZ		 2210
2211 if (lmce_supported()) {
2212 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
2213 }
6900d1cc
EH		 2214 } else {
2215 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
2216 "vendor", &error_abort);
2217 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
2218 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
2219 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
2220 object_property_set_str(OBJECT(cpu),
2221 "QEMU TCG CPU version " QEMU_HW_VERSION,
2222 "model-id", &error_abort);
e4356010 2223 }
2a573259 2224
d940ee9b 2225 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 2226}
2227
c62f2630
EH		 2228static const TypeInfo max_x86_cpu_type_info = {
2229 .name = X86_CPU_TYPE_NAME("max"),
2230 .parent = TYPE_X86_CPU,
2231 .instance_init = max_x86_cpu_initfn,
2232 .class_init = max_x86_cpu_class_init,
2233};
2234
d6dcc558 2235#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 2236static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
2237{
2238 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2239
d6dcc558 2240 xcc->host_cpuid_required = true;
c62f2630
EH		 2241 xcc->ordering = 8;
2242
d6dcc558
SAGDR		 2243 if (kvm_enabled()) {
2244 xcc->model_description =
2245 "KVM processor with all supported host features ";
2246 } else if (hvf_enabled()) {
2247 xcc->model_description =
2248 "HVF processor with all supported host features ";
2249 }
c62f2630
EH		 2250}
2251
d940ee9b
EH		 2252static const TypeInfo host_x86_cpu_type_info = {
2253 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 2254 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 2255 .class_init = host_x86_cpu_class_init,
2256};
2257
2258#endif
2259
8459e396 2260static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 2261{
8459e396 2262 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 2263 int i;
2264
857aee33 2265 for (i = 0; i < 32; ++i) {
72370dc1 2266 if ((1UL << i) & mask) {
bffd67b0 2267 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 2268 assert(reg);
8297be80
AF		 2269 warn_report("%s doesn't support requested feature: "
2270 "CPUID.%02XH:%s%s%s [bit %d]",
d6dcc558 2271 accel_uses_host_cpuid() ? "host" : "TCG",
8297be80
AF		 2272 f->cpuid_eax, reg,
2273 f->feat_names[i] ? "." : "",
2274 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 2275 }
857aee33 2276 }
c6dc6f63
AP		 2277}
2278
d7bce999
EB		 2279static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
2280 const char *name, void *opaque,
2281 Error **errp)
95b8519d
AF		 2282{
2283 X86CPU *cpu = X86_CPU(obj);
2284 CPUX86State *env = &cpu->env;
2285 int64_t value;
2286
2287 value = (env->cpuid_version >> 8) & 0xf;
2288 if (value == 0xf) {
2289 value += (env->cpuid_version >> 20) & 0xff;
2290 }
51e72bc1 2291 visit_type_int(v, name, &value, errp);
95b8519d
AF		 2292}
2293
d7bce999
EB		 2294static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
2295 const char *name, void *opaque,
2296 Error **errp)
ed5e1ec3 2297{
71ad61d3
AF		 2298 X86CPU *cpu = X86_CPU(obj);
2299 CPUX86State *env = &cpu->env;
2300 const int64_t min = 0;
2301 const int64_t max = 0xff + 0xf;
65cd9064 2302 Error *local_err = NULL;
71ad61d3
AF		 2303 int64_t value;
2304
51e72bc1 2305 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2306 if (local_err) {
2307 error_propagate(errp, local_err);
71ad61d3
AF		 2308 return;
2309 }
2310 if (value < min || value > max) {
c6bd8c70
MA		 2311 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2312 name ? name : "null", value, min, max);
71ad61d3
AF		 2313 return;
2314 }
2315
ed5e1ec3 2316 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 2317 if (value > 0x0f) {
2318 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 2319 } else {
71ad61d3 2320 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 2321 }
2322}
2323
d7bce999
EB		 2324static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
2325 const char *name, void *opaque,
2326 Error **errp)
67e30c83
AF		 2327{
2328 X86CPU *cpu = X86_CPU(obj);
2329 CPUX86State *env = &cpu->env;
2330 int64_t value;
2331
2332 value = (env->cpuid_version >> 4) & 0xf;
2333 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 2334 visit_type_int(v, name, &value, errp);
67e30c83
AF		 2335}
2336
d7bce999
EB		 2337static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
2338 const char *name, void *opaque,
2339 Error **errp)
b0704cbd 2340{
c5291a4f
AF		 2341 X86CPU *cpu = X86_CPU(obj);
2342 CPUX86State *env = &cpu->env;
2343 const int64_t min = 0;
2344 const int64_t max = 0xff;
65cd9064 2345 Error *local_err = NULL;
c5291a4f
AF		 2346 int64_t value;
2347
51e72bc1 2348 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2349 if (local_err) {
2350 error_propagate(errp, local_err);
c5291a4f
AF		 2351 return;
2352 }
2353 if (value < min || value > max) {
c6bd8c70
MA		 2354 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2355 name ? name : "null", value, min, max);
c5291a4f
AF		 2356 return;
2357 }
2358
b0704cbd 2359 env->cpuid_version &= ~0xf00f0;
c5291a4f 2360 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 2361}
2362
35112e41 2363static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 2364 const char *name, void *opaque,
35112e41
AF		 2365 Error **errp)
2366{
2367 X86CPU *cpu = X86_CPU(obj);
2368 CPUX86State *env = &cpu->env;
2369 int64_t value;
2370
2371 value = env->cpuid_version & 0xf;
51e72bc1 2372 visit_type_int(v, name, &value, errp);
35112e41
AF		 2373}
2374
036e2222 2375static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 2376 const char *name, void *opaque,
036e2222 2377 Error **errp)
38c3dc46 2378{
036e2222
AF		 2379 X86CPU *cpu = X86_CPU(obj);
2380 CPUX86State *env = &cpu->env;
2381 const int64_t min = 0;
2382 const int64_t max = 0xf;
65cd9064 2383 Error *local_err = NULL;
036e2222
AF		 2384 int64_t value;
2385
51e72bc1 2386 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2387 if (local_err) {
2388 error_propagate(errp, local_err);
036e2222
AF		 2389 return;
2390 }
2391 if (value < min || value > max) {
c6bd8c70
MA		 2392 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2393 name ? name : "null", value, min, max);
036e2222
AF		 2394 return;
2395 }
2396
38c3dc46 2397 env->cpuid_version &= ~0xf;
036e2222 2398 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 2399}
2400
d480e1af
AF		 2401static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
2402{
2403 X86CPU *cpu = X86_CPU(obj);
2404 CPUX86State *env = &cpu->env;
2405 char *value;
d480e1af 2406
e42a92ae 2407 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 2408 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
2409 env->cpuid_vendor3);
d480e1af
AF		 2410 return value;
2411}
2412
2413static void x86_cpuid_set_vendor(Object *obj, const char *value,
2414 Error **errp)
2415{
2416 X86CPU *cpu = X86_CPU(obj);
2417 CPUX86State *env = &cpu->env;
2418 int i;
2419
9df694ee 2420 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 2421 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 2422 return;
2423 }
2424
2425 env->cpuid_vendor1 = 0;
2426 env->cpuid_vendor2 = 0;
2427 env->cpuid_vendor3 = 0;
2428 for (i = 0; i < 4; i++) {
2429 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
2430 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
2431 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
2432 }
d480e1af
AF		 2433}
2434
63e886eb
AF		 2435static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
2436{
2437 X86CPU *cpu = X86_CPU(obj);
2438 CPUX86State *env = &cpu->env;
2439 char *value;
2440 int i;
2441
2442 value = g_malloc(48 + 1);
2443 for (i = 0; i < 48; i++) {
2444 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
2445 }
2446 value[48] = '\0';
2447 return value;
2448}
2449
938d4c25
AF		 2450static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
2451 Error **errp)
dcce6675 2452{
938d4c25
AF		 2453 X86CPU *cpu = X86_CPU(obj);
2454 CPUX86State *env = &cpu->env;
dcce6675
AF		 2455 int c, len, i;
2456
2457 if (model_id == NULL) {
2458 model_id = "";
2459 }
2460 len = strlen(model_id);
d0a6acf4 2461 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 2462 for (i = 0; i < 48; i++) {
2463 if (i >= len) {
2464 c = '\0';
2465 } else {
2466 c = (uint8_t)model_id[i];
2467 }
2468 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
2469 }
2470}
2471
d7bce999
EB		 2472static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
2473 void *opaque, Error **errp)
89e48965
AF		 2474{
2475 X86CPU *cpu = X86_CPU(obj);
2476 int64_t value;
2477
2478 value = cpu->env.tsc_khz * 1000;
51e72bc1 2479 visit_type_int(v, name, &value, errp);
89e48965
AF		 2480}
2481
d7bce999
EB		 2482static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
2483 void *opaque, Error **errp)
89e48965
AF		 2484{
2485 X86CPU *cpu = X86_CPU(obj);
2486 const int64_t min = 0;
2e84849a 2487 const int64_t max = INT64_MAX;
65cd9064 2488 Error *local_err = NULL;
89e48965
AF		 2489 int64_t value;
2490
51e72bc1 2491 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2492 if (local_err) {
2493 error_propagate(errp, local_err);
89e48965
AF		 2494 return;
2495 }
2496 if (value < min || value > max) {
c6bd8c70
MA		 2497 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2498 name ? name : "null", value, min, max);
89e48965
AF		 2499 return;
2500 }
2501
36f96c4b 2502 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 2503}
2504
7e5292b5 2505/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 2506static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
2507 const char *name, void *opaque,
2508 Error **errp)
8e8aba50 2509{
7e5292b5 2510 uint32_t *array = (uint32_t *)opaque;
8e8aba50 2511 FeatureWord w;
8e8aba50
EH		 2512 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
2513 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
2514 X86CPUFeatureWordInfoList *list = NULL;
2515
2516 for (w = 0; w < FEATURE_WORDS; w++) {
2517 FeatureWordInfo *wi = &feature_word_info[w];
2518 X86CPUFeatureWordInfo *qwi = &word_infos[w];
2519 qwi->cpuid_input_eax = wi->cpuid_eax;
2520 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
2521 qwi->cpuid_input_ecx = wi->cpuid_ecx;
2522 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 2523 qwi->features = array[w];
8e8aba50
EH		 2524
2525 /* List will be in reverse order, but order shouldn't matter */
2526 list_entries[w].next = list;
2527 list_entries[w].value = &word_infos[w];
2528 list = &list_entries[w];
2529 }
2530
6b62d961 2531 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 2532}
2533
d7bce999
EB		 2534static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
2535 void *opaque, Error **errp)
c8f0f88e
IM		 2536{
2537 X86CPU *cpu = X86_CPU(obj);
2538 int64_t value = cpu->hyperv_spinlock_attempts;
2539
51e72bc1 2540 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 2541}
2542
d7bce999
EB		 2543static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
2544 void *opaque, Error **errp)
c8f0f88e
IM		 2545{
2546 const int64_t min = 0xFFF;
2547 const int64_t max = UINT_MAX;
2548 X86CPU *cpu = X86_CPU(obj);
2549 Error *err = NULL;
2550 int64_t value;
2551
51e72bc1 2552 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 2553 if (err) {
2554 error_propagate(errp, err);
2555 return;
2556 }
2557
2558 if (value < min || value > max) {
2559 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 2560 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
2561 object_get_typename(obj), name ? name : "null",
2562 value, min, max);
c8f0f88e
IM		 2563 return;
2564 }
2565 cpu->hyperv_spinlock_attempts = value;
2566}
2567
1b6b7d10 2568static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 2569 .name = "int",
2570 .get = x86_get_hv_spinlocks,
2571 .set = x86_set_hv_spinlocks,
2572};
2573
72ac2e87
IM		 2574/* Convert all '_' in a feature string option name to '-', to make feature
2575 * name conform to QOM property naming rule, which uses '-' instead of '_'.
2576 */
2577static inline void feat2prop(char *s)
2578{
2579 while ((s = strchr(s, '_'))) {
2580 *s = '-';
2581 }
2582}
2583
b54c9377
EH		 2584/* Return the feature property name for a feature flag bit */
2585static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
2586{
2587 /* XSAVE components are automatically enabled by other features,
2588 * so return the original feature name instead
2589 */
2590 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
2591 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
2592
2593 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
2594 x86_ext_save_areas[comp].bits) {
2595 w = x86_ext_save_areas[comp].feature;
2596 bitnr = ctz32(x86_ext_save_areas[comp].bits);
2597 }
2598 }
2599
2600 assert(bitnr < 32);
2601 assert(w < FEATURE_WORDS);
2602 return feature_word_info[w].feat_names[bitnr];
2603}
2604
dc15c051
IM		 2605/* Compatibily hack to maintain legacy +-feat semantic,
2606 * where +-feat overwrites any feature set by
2607 * feat=on|feat even if the later is parsed after +-feat
2608 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2609 */
2fae0d96 2610static GList *plus_features, *minus_features;
dc15c051 2611
83a00f60
EH		 2612static gint compare_string(gconstpointer a, gconstpointer b)
2613{
2614 return g_strcmp0(a, b);
2615}
2616
8f961357
EH		 2617/* Parse "+feature,-feature,feature=foo" CPU feature string
2618 */
62a48a2a 2619static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 2620 Error **errp)
8f961357 2621{
8f961357 2622 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 2623 static bool cpu_globals_initialized;
83a00f60 2624 bool ambiguous = false;
62a48a2a
IM		 2625
2626 if (cpu_globals_initialized) {
2627 return;
2628 }
2629 cpu_globals_initialized = true;
8f961357 2630
f6750e95
EH		 2631 if (!features) {
2632 return;
2633 }
2634
2635 for (featurestr = strtok(features, ",");
685479bd 2636 featurestr;
f6750e95
EH		 2637 featurestr = strtok(NULL, ",")) {
2638 const char *name;
2639 const char *val = NULL;
2640 char *eq = NULL;
cf2887c9 2641 char num[32];
62a48a2a 2642 GlobalProperty *prop;
c6dc6f63 2643
f6750e95 2644 /* Compatibility syntax: */
c6dc6f63 2645 if (featurestr[0] == '+') {
2fae0d96
EH		 2646 plus_features = g_list_append(plus_features,
2647 g_strdup(featurestr + 1));
f6750e95 2648 continue;
c6dc6f63 2649 } else if (featurestr[0] == '-') {
2fae0d96
EH		 2650 minus_features = g_list_append(minus_features,
2651 g_strdup(featurestr + 1));
f6750e95
EH		 2652 continue;
2653 }
2654
2655 eq = strchr(featurestr, '=');
2656 if (eq) {
2657 *eq++ = 0;
2658 val = eq;
c6dc6f63 2659 } else {
f6750e95 2660 val = "on";
a91987c2 2661 }
f6750e95
EH		 2662
2663 feat2prop(featurestr);
2664 name = featurestr;
2665
83a00f60 2666 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 2667 warn_report("Ambiguous CPU model string. "
2668 "Don't mix both \"+%s\" and \"%s=%s\"",
2669 name, name, val);
83a00f60
EH		 2670 ambiguous = true;
2671 }
2672 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 2673 warn_report("Ambiguous CPU model string. "
2674 "Don't mix both \"-%s\" and \"%s=%s\"",
2675 name, name, val);
83a00f60
EH		 2676 ambiguous = true;
2677 }
2678
f6750e95
EH		 2679 /* Special case: */
2680 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 2681 int ret;
f46bfdbf 2682 uint64_t tsc_freq;
f6750e95 2683
f17fd4fd 2684 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 2685 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 2686 error_setg(errp, "bad numerical value %s", val);
2687 return;
2688 }
2689 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2690 val = num;
2691 name = "tsc-frequency";
c6dc6f63 2692 }
f6750e95 2693
62a48a2a
IM		 2694 prop = g_new0(typeof(*prop), 1);
2695 prop->driver = typename;
2696 prop->property = g_strdup(name);
2697 prop->value = g_strdup(val);
2698 prop->errp = &error_fatal;
2699 qdev_prop_register_global(prop);
f6750e95
EH		 2700 }
2701
83a00f60 2702 if (ambiguous) {
3dc6f869
AF		 2703 warn_report("Compatibility of ambiguous CPU model "
2704 "strings won't be kept on future QEMU versions");
83a00f60 2705 }
c6dc6f63
AP		 2706}
2707
b8d834a0 2708static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 2709static int x86_cpu_filter_features(X86CPU *cpu);
2710
2711/* Check for missing features that may prevent the CPU class from
2712 * running using the current machine and accelerator.
2713 */
2714static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
2715 strList **missing_feats)
2716{
2717 X86CPU *xc;
2718 FeatureWord w;
2719 Error *err = NULL;
2720 strList **next = missing_feats;
2721
d6dcc558 2722 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 2723 strList *new = g_new0(strList, 1);
3c254ab8 2724 new->value = g_strdup("kvm");
b54c9377
EH		 2725 *missing_feats = new;
2726 return;
2727 }
2728
2729 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2730
b8d834a0 2731 x86_cpu_expand_features(xc, &err);
b54c9377 2732 if (err) {
b8d834a0 2733 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 2734 * but in case it does, just report the model as not
2735 * runnable at all using the "type" property.
2736 */
2737 strList *new = g_new0(strList, 1);
2738 new->value = g_strdup("type");
2739 *next = new;
2740 next = &new->next;
2741 }
2742
2743 x86_cpu_filter_features(xc);
2744
2745 for (w = 0; w < FEATURE_WORDS; w++) {
2746 uint32_t filtered = xc->filtered_features[w];
2747 int i;
2748 for (i = 0; i < 32; i++) {
2749 if (filtered & (1UL << i)) {
2750 strList *new = g_new0(strList, 1);
2751 new->value = g_strdup(x86_cpu_feature_name(w, i));
2752 *next = new;
2753 next = &new->next;
2754 }
2755 }
2756 }
2757
2758 object_unref(OBJECT(xc));
2759}
2760
8c3329e5 2761/* Print all cpuid feature names in featureset
c6dc6f63 2762 */
8c3329e5 2763static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2764{
8c3329e5
EH		 2765 int bit;
2766 bool first = true;
2767
2768 for (bit = 0; bit < 32; bit++) {
2769 if (featureset[bit]) {
2770 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2771 first = false;
c6dc6f63 2772 }
8c3329e5 2773 }
c6dc6f63
AP		 2774}
2775
f48c8837 2776/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 2777static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
2778{
2779 ObjectClass *class_a = (ObjectClass *)a;
2780 ObjectClass *class_b = (ObjectClass *)b;
2781 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
2782 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
2783 const char *name_a, *name_b;
2784
f48c8837
EH		 2785 if (cc_a->ordering != cc_b->ordering) {
2786 return cc_a->ordering - cc_b->ordering;
ee465a3e
EH		 2787 } else {
2788 name_a = object_class_get_name(class_a);
2789 name_b = object_class_get_name(class_b);
2790 return strcmp(name_a, name_b);
2791 }
2792}
2793
2794static GSList *get_sorted_cpu_model_list(void)
2795{
2796 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
2797 list = g_slist_sort(list, x86_cpu_list_compare);
2798 return list;
2799}
2800
2801static void x86_cpu_list_entry(gpointer data, gpointer user_data)
2802{
2803 ObjectClass *oc = data;
2804 X86CPUClass *cc = X86_CPU_CLASS(oc);
2805 CPUListState *s = user_data;
2806 char *name = x86_cpu_class_get_model_name(cc);
2807 const char *desc = cc->model_description;
0bacd8b3 2808 if (!desc && cc->cpu_def) {
ee465a3e
EH		 2809 desc = cc->cpu_def->model_id;
2810 }
2811
2812 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
2813 name, desc);
2814 g_free(name);
2815}
2816
2817/* list available CPU models and flags */
e916cbf8 2818void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2819{
7fc9b714 2820 int i;
ee465a3e
EH		 2821 CPUListState s = {
2822 .file = f,
2823 .cpu_fprintf = cpu_fprintf,
2824 };
2825 GSList *list;
c6dc6f63 2826
ee465a3e
EH		 2827 (*cpu_fprintf)(f, "Available CPUs:\n");
2828 list = get_sorted_cpu_model_list();
2829 g_slist_foreach(list, x86_cpu_list_entry, &s);
2830 g_slist_free(list);
21ad7789 2831
6cdf8854 2832 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2833 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2834 FeatureWordInfo *fw = &feature_word_info[i];
2835
8c3329e5
EH		 2836 (*cpu_fprintf)(f, " ");
2837 listflags(f, cpu_fprintf, fw->feat_names);
2838 (*cpu_fprintf)(f, "\n");
3af60be2 2839 }
c6dc6f63
AP		 2840}
2841
ee465a3e
EH		 2842static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
2843{
2844 ObjectClass *oc = data;
2845 X86CPUClass *cc = X86_CPU_CLASS(oc);
2846 CpuDefinitionInfoList **cpu_list = user_data;
2847 CpuDefinitionInfoList *entry;
2848 CpuDefinitionInfo *info;
2849
2850 info = g_malloc0(sizeof(*info));
2851 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 2852 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
2853 info->has_unavailable_features = true;
8ed877b7 2854 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 2855 info->migration_safe = cc->migration_safe;
2856 info->has_migration_safe = true;
5adbed30 2857 info->q_static = cc->static_model;
ee465a3e
EH		 2858
2859 entry = g_malloc0(sizeof(*entry));
2860 entry->value = info;
2861 entry->next = *cpu_list;
2862 *cpu_list = entry;
2863}
2864
76b64a7a 2865CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2866{
2867 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 2868 GSList *list = get_sorted_cpu_model_list();
2869 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
2870 g_slist_free(list);
e3966126
AL		 2871 return cpu_list;
2872}
2873
84f1b92f
EH		 2874static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2875 bool migratable_only)
27418adf
EH		 2876{
2877 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2878 uint32_t r;
27418adf 2879
fefb41bf 2880 if (kvm_enabled()) {
84f1b92f
EH		 2881 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2882 wi->cpuid_ecx,
2883 wi->cpuid_reg);
d6dcc558
SAGDR		 2884 } else if (hvf_enabled()) {
2885 r = hvf_get_supported_cpuid(wi->cpuid_eax,
2886 wi->cpuid_ecx,
2887 wi->cpuid_reg);
fefb41bf 2888 } else if (tcg_enabled()) {
84f1b92f 2889 r = wi->tcg_features;
fefb41bf
EH		 2890 } else {
2891 return ~0;
2892 }
84f1b92f
EH		 2893 if (migratable_only) {
2894 r &= x86_cpu_get_migratable_flags(w);
2895 }
2896 return r;
27418adf
EH		 2897}
2898
8ca30e86
EH		 2899static void x86_cpu_report_filtered_features(X86CPU *cpu)
2900{
2901 FeatureWord w;
2902
2903 for (w = 0; w < FEATURE_WORDS; w++) {
2904 report_unavailable_features(w, cpu->filtered_features[w]);
2905 }
2906}
2907
5114e842
EH		 2908static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2909{
2910 PropValue *pv;
2911 for (pv = props; pv->prop; pv++) {
2912 if (!pv->value) {
2913 continue;
2914 }
2915 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2916 &error_abort);
2917 }
2918}
2919
f99fd7ca 2920/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 2921 */
d940ee9b 2922static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2923{
61dcd775 2924 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2925 const char *vendor;
2926 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2927 FeatureWord w;
c6dc6f63 2928
f99fd7ca
EH		 2929 /*NOTE: any property set by this function should be returned by
2930 * x86_cpu_static_props(), so static expansion of
2931 * query-cpu-model-expansion is always complete.
2932 */
2933
c39c0edf 2934 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 2935 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
2936 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 2937
2d64255b
AF		 2938 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2939 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2940 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2941 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2942 for (w = 0; w < FEATURE_WORDS; w++) {
2943 env->features[w] = def->features[w];
2944 }
82beb536 2945
9576de75 2946 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 2947 /* TODO: in-kernel irqchip for hvf */
82beb536 2948 if (kvm_enabled()) {
492a4c94
LT		 2949 if (!kvm_irqchip_in_kernel()) {
2950 x86_cpu_change_kvm_default("x2apic", "off");
2951 }
2952
5114e842 2953 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 2954 } else if (tcg_enabled()) {
2955 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 2956 }
5fcca9ff 2957
82beb536 2958 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2959
2960 /* sysenter isn't supported in compatibility mode on AMD,
2961 * syscall isn't supported in compatibility mode on Intel.
2962 * Normally we advertise the actual CPU vendor, but you can
2963 * override this using the 'vendor' property if you want to use
2964 * KVM's sysenter/syscall emulation in compatibility mode and
2965 * when doing cross vendor migration
2966 */
74f54bc4 2967 vendor = def->vendor;
d6dcc558 2968 if (accel_uses_host_cpuid()) {
7c08db30
EH		 2969 uint32_t ebx = 0, ecx = 0, edx = 0;
2970 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2971 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2972 vendor = host_vendor;
2973 }
2974
2975 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2976
c6dc6f63
AP		 2977}
2978
f99fd7ca
EH		 2979/* Return a QDict containing keys for all properties that can be included
2980 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
2981 * must be included in the dictionary.
2982 */
2983static QDict *x86_cpu_static_props(void)
2984{
2985 FeatureWord w;
2986 int i;
2987 static const char *props[] = {
2988 "min-level",
2989 "min-xlevel",
2990 "family",
2991 "model",
2992 "stepping",
2993 "model-id",
2994 "vendor",
2995 "lmce",
2996 NULL,
2997 };
2998 static QDict *d;
2999
3000 if (d) {
3001 return d;
3002 }
3003
3004 d = qdict_new();
3005 for (i = 0; props[i]; i++) {
0f9afc2a 3006 qdict_put_null(d, props[i]);
f99fd7ca
EH		 3007 }
3008
3009 for (w = 0; w < FEATURE_WORDS; w++) {
3010 FeatureWordInfo *fi = &feature_word_info[w];
3011 int bit;
3012 for (bit = 0; bit < 32; bit++) {
3013 if (!fi->feat_names[bit]) {
3014 continue;
3015 }
0f9afc2a 3016 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 3017 }
3018 }
3019
3020 return d;
3021}
3022
3023/* Add an entry to @props dict, with the value for property. */
3024static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
3025{
3026 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
3027 &error_abort);
3028
3029 qdict_put_obj(props, prop, value);
3030}
3031
3032/* Convert CPU model data from X86CPU object to a property dictionary
3033 * that can recreate exactly the same CPU model.
3034 */
3035static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
3036{
3037 QDict *sprops = x86_cpu_static_props();
3038 const QDictEntry *e;
3039
3040 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
3041 const char *prop = qdict_entry_key(e);
3042 x86_cpu_expand_prop(cpu, props, prop);
3043 }
3044}
3045
b8097deb
EH		 3046/* Convert CPU model data from X86CPU object to a property dictionary
3047 * that can recreate exactly the same CPU model, including every
3048 * writeable QOM property.
3049 */
3050static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
3051{
3052 ObjectPropertyIterator iter;
3053 ObjectProperty *prop;
3054
3055 object_property_iter_init(&iter, OBJECT(cpu));
3056 while ((prop = object_property_iter_next(&iter))) {
3057 /* skip read-only or write-only properties */
3058 if (!prop->get || !prop->set) {
3059 continue;
3060 }
3061
3062 /* "hotplugged" is the only property that is configurable
3063 * on the command-line but will be set differently on CPUs
3064 * created using "-cpu ... -smp ..." and by CPUs created
3065 * on the fly by x86_cpu_from_model() for querying. Skip it.
3066 */
3067 if (!strcmp(prop->name, "hotplugged")) {
3068 continue;
3069 }
3070 x86_cpu_expand_prop(cpu, props, prop->name);
3071 }
3072}
3073
f99fd7ca
EH		 3074static void object_apply_props(Object *obj, QDict *props, Error **errp)
3075{
3076 const QDictEntry *prop;
3077 Error *err = NULL;
3078
3079 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
3080 object_property_set_qobject(obj, qdict_entry_value(prop),
3081 qdict_entry_key(prop), &err);
3082 if (err) {
3083 break;
3084 }
3085 }
3086
3087 error_propagate(errp, err);
3088}
3089
3090/* Create X86CPU object according to model+props specification */
3091static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
3092{
3093 X86CPU *xc = NULL;
3094 X86CPUClass *xcc;
3095 Error *err = NULL;
3096
3097 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
3098 if (xcc == NULL) {
3099 error_setg(&err, "CPU model '%s' not found", model);
3100 goto out;
3101 }
3102
3103 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3104 if (props) {
3105 object_apply_props(OBJECT(xc), props, &err);
3106 if (err) {
3107 goto out;
3108 }
3109 }
3110
3111 x86_cpu_expand_features(xc, &err);
3112 if (err) {
3113 goto out;
3114 }
3115
3116out:
3117 if (err) {
3118 error_propagate(errp, err);
3119 object_unref(OBJECT(xc));
3120 xc = NULL;
3121 }
3122 return xc;
3123}
3124
3125CpuModelExpansionInfo *
3126arch_query_cpu_model_expansion(CpuModelExpansionType type,
3127 CpuModelInfo *model,
3128 Error **errp)
3129{
3130 X86CPU *xc = NULL;
3131 Error *err = NULL;
3132 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
3133 QDict *props = NULL;
3134 const char *base_name;
3135
3136 xc = x86_cpu_from_model(model->name,
3137 model->has_props ?
3138 qobject_to_qdict(model->props) :
3139 NULL, &err);
3140 if (err) {
3141 goto out;
3142 }
3143
b8097deb 3144 props = qdict_new();
f99fd7ca
EH		 3145
3146 switch (type) {
3147 case CPU_MODEL_EXPANSION_TYPE_STATIC:
3148 /* Static expansion will be based on "base" only */
3149 base_name = "base";
b8097deb 3150 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 3151 break;
3152 case CPU_MODEL_EXPANSION_TYPE_FULL:
3153 /* As we don't return every single property, full expansion needs
3154 * to keep the original model name+props, and add extra
3155 * properties on top of that.
3156 */
3157 base_name = model->name;
b8097deb 3158 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 3159 break;
3160 default:
3161 error_setg(&err, "Unsupportted expansion type");
3162 goto out;
3163 }
3164
3165 if (!props) {
3166 props = qdict_new();
3167 }
3168 x86_cpu_to_dict(xc, props);
3169
3170 ret->model = g_new0(CpuModelInfo, 1);
3171 ret->model->name = g_strdup(base_name);
3172 ret->model->props = QOBJECT(props);
3173 ret->model->has_props = true;
3174
3175out:
3176 object_unref(OBJECT(xc));
3177 if (err) {
3178 error_propagate(errp, err);
3179 qapi_free_CpuModelExpansionInfo(ret);
3180 ret = NULL;
3181 }
3182 return ret;
3183}
3184
00fcd100
AB		 3185static gchar *x86_gdb_arch_name(CPUState *cs)
3186{
3187#ifdef TARGET_X86_64
3188 return g_strdup("i386:x86-64");
3189#else
3190 return g_strdup("i386");
3191#endif
3192}
3193
d940ee9b
EH		 3194static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
3195{
3196 X86CPUDefinition *cpudef = data;
3197 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3198
3199 xcc->cpu_def = cpudef;
bd72159d 3200 xcc->migration_safe = true;
d940ee9b
EH		 3201}
3202
3203static void x86_register_cpudef_type(X86CPUDefinition *def)
3204{
3205 char *typename = x86_cpu_type_name(def->name);
3206 TypeInfo ti = {
3207 .name = typename,
3208 .parent = TYPE_X86_CPU,
3209 .class_init = x86_cpu_cpudef_class_init,
3210 .class_data = def,
3211 };
3212
2a923a29
EH		 3213 /* AMD aliases are handled at runtime based on CPUID vendor, so
3214 * they shouldn't be set on the CPU model table.
3215 */
3216 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 3217 /* catch mistakes instead of silently truncating model_id when too long */
3218 assert(def->model_id && strlen(def->model_id) <= 48);
3219
2a923a29 3220
d940ee9b
EH		 3221 type_register(&ti);
3222 g_free(typename);
3223}
3224
c6dc6f63 3225#if !defined(CONFIG_USER_ONLY)
c6dc6f63 3226
0e26b7b8
BS		 3227void cpu_clear_apic_feature(CPUX86State *env)
3228{
0514ef2f 3229 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 3230}
3231
c6dc6f63
AP		 3232#endif /* !CONFIG_USER_ONLY */
3233
c6dc6f63
AP		 3234void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
3235 uint32_t *eax, uint32_t *ebx,
3236 uint32_t *ecx, uint32_t *edx)
3237{
a60f24b5
AF		 3238 X86CPU *cpu = x86_env_get_cpu(env);
3239 CPUState *cs = CPU(cpu);
14c985cf 3240 uint32_t pkg_offset;
4ed3d478 3241 uint32_t limit;
1ce36bfe 3242 uint32_t signature[3];
a60f24b5 3243
4ed3d478
DB		 3244 /* Calculate & apply limits for different index ranges */
3245 if (index >= 0xC0000000) {
3246 limit = env->cpuid_xlevel2;
3247 } else if (index >= 0x80000000) {
3248 limit = env->cpuid_xlevel;
1ce36bfe
DB		 3249 } else if (index >= 0x40000000) {
3250 limit = 0x40000001;
c6dc6f63 3251 } else {
4ed3d478
DB		 3252 limit = env->cpuid_level;
3253 }
3254
3255 if (index > limit) {
3256 /* Intel documentation states that invalid EAX input will
3257 * return the same information as EAX=cpuid_level
3258 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
3259 */
3260 index = env->cpuid_level;
c6dc6f63
AP		 3261 }
3262
3263 switch(index) {
3264 case 0:
3265 *eax = env->cpuid_level;
5eb2f7a4
EH		 3266 *ebx = env->cpuid_vendor1;
3267 *edx = env->cpuid_vendor2;
3268 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 3269 break;
3270 case 1:
3271 *eax = env->cpuid_version;
7e72a45c
EH		 3272 *ebx = (cpu->apic_id << 24) |
3273 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 3274 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 3275 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
3276 *ecx |= CPUID_EXT_OSXSAVE;
3277 }
0514ef2f 3278 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 3279 if (cs->nr_cores * cs->nr_threads > 1) {
3280 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 3281 *edx |= CPUID_HT;
c6dc6f63
AP		 3282 }
3283 break;
3284 case 2:
3285 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 3286 if (cpu->cache_info_passthrough) {
3287 host_cpuid(index, 0, eax, ebx, ecx, edx);
3288 break;
3289 }
5e891bf8 3290 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 3291 *ebx = 0;
14c985cf
LM		 3292 if (!cpu->enable_l3_cache) {
3293 *ecx = 0;
3294 } else {
3295 *ecx = L3_N_DESCRIPTOR;
3296 }
5e891bf8
EH		 3297 *edx = (L1D_DESCRIPTOR << 16) | \
3298 (L1I_DESCRIPTOR << 8) | \
3299 (L2_DESCRIPTOR);
c6dc6f63
AP		 3300 break;
3301 case 4:
3302 /* cache info: needed for Core compatibility */
787aaf57
BC		 3303 if (cpu->cache_info_passthrough) {
3304 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 3305 *eax &= ~0xFC000000;
c6dc6f63 3306 } else {
2f7a21c4 3307 *eax = 0;
76c2975a 3308 switch (count) {
c6dc6f63 3309 case 0: /* L1 dcache info */
5e891bf8
EH		 3310 *eax |= CPUID_4_TYPE_DCACHE | \
3311 CPUID_4_LEVEL(1) | \
3312 CPUID_4_SELF_INIT_LEVEL;
3313 *ebx = (L1D_LINE_SIZE - 1) | \
3314 ((L1D_PARTITIONS - 1) << 12) | \
3315 ((L1D_ASSOCIATIVITY - 1) << 22);
3316 *ecx = L1D_SETS - 1;
3317 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 3318 break;
3319 case 1: /* L1 icache info */
5e891bf8
EH		 3320 *eax |= CPUID_4_TYPE_ICACHE | \
3321 CPUID_4_LEVEL(1) | \
3322 CPUID_4_SELF_INIT_LEVEL;
3323 *ebx = (L1I_LINE_SIZE - 1) | \
3324 ((L1I_PARTITIONS - 1) << 12) | \
3325 ((L1I_ASSOCIATIVITY - 1) << 22);
3326 *ecx = L1I_SETS - 1;
3327 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 3328 break;
3329 case 2: /* L2 cache info */
5e891bf8
EH		 3330 *eax |= CPUID_4_TYPE_UNIFIED | \
3331 CPUID_4_LEVEL(2) | \
3332 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 3333 if (cs->nr_threads > 1) {
3334 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 3335 }
5e891bf8
EH		 3336 *ebx = (L2_LINE_SIZE - 1) | \
3337 ((L2_PARTITIONS - 1) << 12) | \
3338 ((L2_ASSOCIATIVITY - 1) << 22);
3339 *ecx = L2_SETS - 1;
3340 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63 3341 break;
14c985cf
LM		 3342 case 3: /* L3 cache info */
3343 if (!cpu->enable_l3_cache) {
3344 *eax = 0;
3345 *ebx = 0;
3346 *ecx = 0;
3347 *edx = 0;
3348 break;
3349 }
3350 *eax |= CPUID_4_TYPE_UNIFIED | \
3351 CPUID_4_LEVEL(3) | \
3352 CPUID_4_SELF_INIT_LEVEL;
3353 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
3354 *eax |= ((1 << pkg_offset) - 1) << 14;
3355 *ebx = (L3_N_LINE_SIZE - 1) | \
3356 ((L3_N_PARTITIONS - 1) << 12) | \
3357 ((L3_N_ASSOCIATIVITY - 1) << 22);
3358 *ecx = L3_N_SETS - 1;
3359 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
3360 break;
c6dc6f63
AP		 3361 default: /* end of info */
3362 *eax = 0;
3363 *ebx = 0;
3364 *ecx = 0;
3365 *edx = 0;
3366 break;
76c2975a
PB		 3367 }
3368 }
3369
3370 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
3371 if ((*eax & 31) && cs->nr_cores > 1) {
3372 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 3373 }
3374 break;
3375 case 5:
3376 /* mwait info: needed for Core compatibility */
3377 *eax = 0; /* Smallest monitor-line size in bytes */
3378 *ebx = 0; /* Largest monitor-line size in bytes */
3379 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
3380 *edx = 0;
3381 break;
3382 case 6:
3383 /* Thermal and Power Leaf */
28b8e4d0 3384 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 3385 *ebx = 0;
3386 *ecx = 0;
3387 *edx = 0;
3388 break;
f7911686 3389 case 7:
13526728
EH		 3390 /* Structured Extended Feature Flags Enumeration Leaf */
3391 if (count == 0) {
3392 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 3393 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 3394 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 3395 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
3396 *ecx |= CPUID_7_0_ECX_OSPKE;
3397 }
95ea69fb 3398 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 3399 } else {
3400 *eax = 0;
3401 *ebx = 0;
3402 *ecx = 0;
3403 *edx = 0;
3404 }
3405 break;
c6dc6f63
AP		 3406 case 9:
3407 /* Direct Cache Access Information Leaf */
3408 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
3409 *ebx = 0;
3410 *ecx = 0;
3411 *edx = 0;
3412 break;
3413 case 0xA:
3414 /* Architectural Performance Monitoring Leaf */
9337e3b6 3415 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 3416 KVMState *s = cs->kvm_state;
a0fa8208
GN		 3417
3418 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
3419 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
3420 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
3421 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 3422 } else if (hvf_enabled() && cpu->enable_pmu) {
3423 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
3424 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
3425 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
3426 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 3427 } else {
3428 *eax = 0;
3429 *ebx = 0;
3430 *ecx = 0;
3431 *edx = 0;
3432 }
c6dc6f63 3433 break;
5232d00a
RK		 3434 case 0xB:
3435 /* Extended Topology Enumeration Leaf */
3436 if (!cpu->enable_cpuid_0xb) {
3437 *eax = *ebx = *ecx = *edx = 0;
3438 break;
3439 }
3440
3441 *ecx = count & 0xff;
3442 *edx = cpu->apic_id;
3443
3444 switch (count) {
3445 case 0:
eab60fb9
MAL		 3446 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
3447 *ebx = cs->nr_threads;
5232d00a
RK		 3448 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
3449 break;
3450 case 1:
eab60fb9
MAL		 3451 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
3452 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 3453 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
3454 break;
3455 default:
3456 *eax = 0;
3457 *ebx = 0;
3458 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
3459 }
3460
3461 assert(!(*eax & ~0x1f));
3462 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
3463 break;
2560f19f 3464 case 0xD: {
51e49430 3465 /* Processor Extended State */
2560f19f
PB		 3466 *eax = 0;
3467 *ebx = 0;
3468 *ecx = 0;
3469 *edx = 0;
19dc85db 3470 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 3471 break;
3472 }
4928cd6d 3473
2560f19f 3474 if (count == 0) {
96193c22
EH		 3475 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
3476 *eax = env->features[FEAT_XSAVE_COMP_LO];
3477 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 3478 *ebx = *ecx;
3479 } else if (count == 1) {
0bb0b2d2 3480 *eax = env->features[FEAT_XSAVE];
f4f1110e 3481 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 3482 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
3483 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 3484 *eax = esa->size;
3485 *ebx = esa->offset;
2560f19f 3486 }
51e49430
SY		 3487 }
3488 break;
2560f19f 3489 }
e37a5c7f
CP		 3490 case 0x14: {
3491 /* Intel Processor Trace Enumeration */
3492 *eax = 0;
3493 *ebx = 0;
3494 *ecx = 0;
3495 *edx = 0;
3496 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
3497 !kvm_enabled()) {
3498 break;
3499 }
3500
3501 if (count == 0) {
3502 *eax = INTEL_PT_MAX_SUBLEAF;
3503 *ebx = INTEL_PT_MINIMAL_EBX;
3504 *ecx = INTEL_PT_MINIMAL_ECX;
3505 } else if (count == 1) {
3506 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
3507 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
3508 }
3509 break;
3510 }
1ce36bfe
DB		 3511 case 0x40000000:
3512 /*
3513 * CPUID code in kvm_arch_init_vcpu() ignores stuff
3514 * set here, but we restrict to TCG none the less.
3515 */
3516 if (tcg_enabled() && cpu->expose_tcg) {
3517 memcpy(signature, "TCGTCGTCGTCG", 12);
3518 *eax = 0x40000001;
3519 *ebx = signature[0];
3520 *ecx = signature[1];
3521 *edx = signature[2];
3522 } else {
3523 *eax = 0;
3524 *ebx = 0;
3525 *ecx = 0;
3526 *edx = 0;
3527 }
3528 break;
3529 case 0x40000001:
3530 *eax = 0;
3531 *ebx = 0;
3532 *ecx = 0;
3533 *edx = 0;
3534 break;
c6dc6f63
AP		 3535 case 0x80000000:
3536 *eax = env->cpuid_xlevel;
3537 *ebx = env->cpuid_vendor1;
3538 *edx = env->cpuid_vendor2;
3539 *ecx = env->cpuid_vendor3;
3540 break;
3541 case 0x80000001:
3542 *eax = env->cpuid_version;
3543 *ebx = 0;
0514ef2f
EH		 3544 *ecx = env->features[FEAT_8000_0001_ECX];
3545 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 3546
3547 /* The Linux kernel checks for the CMPLegacy bit and
3548 * discards multiple thread information if it is set.
cb8d4c8f 3549 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 3550 */
ce3960eb 3551 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 3552 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
3553 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
3554 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 3555 *ecx |= 1 << 1; /* CmpLegacy bit */
3556 }
3557 }
c6dc6f63
AP		 3558 break;
3559 case 0x80000002:
3560 case 0x80000003:
3561 case 0x80000004:
3562 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
3563 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
3564 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
3565 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
3566 break;
3567 case 0x80000005:
3568 /* cache info (L1 cache) */
787aaf57
BC		 3569 if (cpu->cache_info_passthrough) {
3570 host_cpuid(index, 0, eax, ebx, ecx, edx);
3571 break;
3572 }
5e891bf8
EH		 3573 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
3574 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
3575 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
3576 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
3577 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
3578 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
3579 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
3580 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 3581 break;
3582 case 0x80000006:
3583 /* cache info (L2 cache) */
787aaf57
BC		 3584 if (cpu->cache_info_passthrough) {
3585 host_cpuid(index, 0, eax, ebx, ecx, edx);
3586 break;
3587 }
5e891bf8
EH		 3588 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
3589 (L2_DTLB_2M_ENTRIES << 16) | \
3590 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
3591 (L2_ITLB_2M_ENTRIES);
3592 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
3593 (L2_DTLB_4K_ENTRIES << 16) | \
3594 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
3595 (L2_ITLB_4K_ENTRIES);
3596 *ecx = (L2_SIZE_KB_AMD << 16) | \
3597 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
3598 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
14c985cf
LM		 3599 if (!cpu->enable_l3_cache) {
3600 *edx = ((L3_SIZE_KB / 512) << 18) | \
3601 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
3602 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
3603 } else {
3604 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
3605 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
3606 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
3607 }
c6dc6f63 3608 break;
303752a9
MT		 3609 case 0x80000007:
3610 *eax = 0;
3611 *ebx = 0;
3612 *ecx = 0;
3613 *edx = env->features[FEAT_8000_0007_EDX];
3614 break;
c6dc6f63
AP		 3615 case 0x80000008:
3616 /* virtual & phys address size in low 2 bytes. */
0514ef2f 3617 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 3618 /* 64 bit processor */
3619 *eax = cpu->phys_bits; /* configurable physical bits */
3620 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
3621 *eax |= 0x00003900; /* 57 bits virtual */
3622 } else {
3623 *eax |= 0x00003000; /* 48 bits virtual */
3624 }
c6dc6f63 3625 } else {
af45907a 3626 *eax = cpu->phys_bits;
c6dc6f63 3627 }
1b3420e1 3628 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 3629 *ecx = 0;
3630 *edx = 0;
ce3960eb
AF		 3631 if (cs->nr_cores * cs->nr_threads > 1) {
3632 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 3633 }
3634 break;
3635 case 0x8000000A:
0514ef2f 3636 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 3637 *eax = 0x00000001; /* SVM Revision */
3638 *ebx = 0x00000010; /* nr of ASIDs */
3639 *ecx = 0;
0514ef2f 3640 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 3641 } else {
3642 *eax = 0;
3643 *ebx = 0;
3644 *ecx = 0;
3645 *edx = 0;
3646 }
c6dc6f63 3647 break;
b3baa152
BW		 3648 case 0xC0000000:
3649 *eax = env->cpuid_xlevel2;
3650 *ebx = 0;
3651 *ecx = 0;
3652 *edx = 0;
3653 break;
3654 case 0xC0000001:
3655 /* Support for VIA CPU's CPUID instruction */
3656 *eax = env->cpuid_version;
3657 *ebx = 0;
3658 *ecx = 0;
0514ef2f 3659 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 3660 break;
3661 case 0xC0000002:
3662 case 0xC0000003:
3663 case 0xC0000004:
3664 /* Reserved for the future, and now filled with zero */
3665 *eax = 0;
3666 *ebx = 0;
3667 *ecx = 0;
3668 *edx = 0;
3669 break;
6cb8f2a6
BS		 3670 case 0x8000001F:
3671 *eax = sev_enabled() ? 0x2 : 0;
3672 *ebx = sev_get_cbit_position();
3673 *ebx |= sev_get_reduced_phys_bits() << 6;
3674 *ecx = 0;
3675 *edx = 0;
3676 break;
c6dc6f63
AP		 3677 default:
3678 /* reserved values: zero */
3679 *eax = 0;
3680 *ebx = 0;
3681 *ecx = 0;
3682 *edx = 0;
3683 break;
3684 }
3685}
5fd2087a
AF		 3686
3687/* CPUClass::reset() */
3688static void x86_cpu_reset(CPUState *s)
3689{
3690 X86CPU *cpu = X86_CPU(s);
3691 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
3692 CPUX86State *env = &cpu->env;
a114d25d
RH		 3693 target_ulong cr4;
3694 uint64_t xcr0;
c1958aea
AF		 3695 int i;
3696
5fd2087a
AF		 3697 xcc->parent_reset(s);
3698
5e992a8e 3699 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 3700
c1958aea
AF		 3701 env->old_exception = -1;
3702
3703 /* init to reset state */
3704
c1958aea
AF		 3705 env->hflags2 |= HF2_GIF_MASK;
3706
3707 cpu_x86_update_cr0(env, 0x60000010);
3708 env->a20_mask = ~0x0;
3709 env->smbase = 0x30000;
e13713db 3710 env->msr_smi_count = 0;
c1958aea
AF		 3711
3712 env->idt.limit = 0xffff;
3713 env->gdt.limit = 0xffff;
3714 env->ldt.limit = 0xffff;
3715 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
3716 env->tr.limit = 0xffff;
3717 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
3718
3719 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
3720 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
3721 DESC_R_MASK | DESC_A_MASK);
3722 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
3723 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3724 DESC_A_MASK);
3725 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
3726 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3727 DESC_A_MASK);
3728 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
3729 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3730 DESC_A_MASK);
3731 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
3732 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3733 DESC_A_MASK);
3734 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
3735 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
3736 DESC_A_MASK);
3737
3738 env->eip = 0xfff0;
3739 env->regs[R_EDX] = env->cpuid_version;
3740
3741 env->eflags = 0x2;
3742
3743 /* FPU init */
3744 for (i = 0; i < 8; i++) {
3745 env->fptags[i] = 1;
3746 }
5bde1407 3747 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 3748
3749 env->mxcsr = 0x1f80;
a114d25d
RH		 3750 /* All units are in INIT state. */
3751 env->xstate_bv = 0;
c1958aea
AF		 3752
3753 env->pat = 0x0007040600070406ULL;
3754 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
3755
3756 memset(env->dr, 0, sizeof(env->dr));
3757 env->dr[6] = DR6_FIXED_1;
3758 env->dr[7] = DR7_FIXED_1;
b3310ab3 3759 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 3760 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 3761
a114d25d 3762 cr4 = 0;
cfc3b074 3763 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 3764
3765#ifdef CONFIG_USER_ONLY
3766 /* Enable all the features for user-mode. */
3767 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 3768 xcr0 |= XSTATE_SSE_MASK;
a114d25d 3769 }
0f70ed47
PB		 3770 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
3771 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 3772 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 3773 xcr0 |= 1ull << i;
3774 }
a114d25d 3775 }
0f70ed47 3776
a114d25d
RH		 3777 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
3778 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
3779 }
07929f2a
RH		 3780 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
3781 cr4 |= CR4_FSGSBASE_MASK;
3782 }
a114d25d
RH		 3783#endif
3784
3785 env->xcr0 = xcr0;
3786 cpu_x86_update_cr4(env, cr4);
0522604b 3787
9db2efd9
AW		 3788 /*
3789 * SDM 11.11.5 requires:
3790 * - IA32_MTRR_DEF_TYPE MSR.E = 0
3791 * - IA32_MTRR_PHYSMASKn.V = 0
3792 * All other bits are undefined. For simplification, zero it all.
3793 */
3794 env->mtrr_deftype = 0;
3795 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
3796 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
3797
b7394c83
SAGDR		 3798 env->interrupt_injected = -1;
3799 env->exception_injected = -1;
3800 env->nmi_injected = false;
dd673288
IM		 3801#if !defined(CONFIG_USER_ONLY)
3802 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 3803 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 3804
259186a7 3805 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 3806
3807 if (kvm_enabled()) {
3808 kvm_arch_reset_vcpu(cpu);
3809 }
d6dcc558
SAGDR		 3810 else if (hvf_enabled()) {
3811 hvf_reset_vcpu(s);
3812 }
dd673288 3813#endif
5fd2087a
AF		 3814}
3815
dd673288
IM		 3816#ifndef CONFIG_USER_ONLY
3817bool cpu_is_bsp(X86CPU *cpu)
3818{
02e51483 3819 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 3820}
65dee380
IM		 3821
3822/* TODO: remove me, when reset over QOM tree is implemented */
3823static void x86_cpu_machine_reset_cb(void *opaque)
3824{
3825 X86CPU *cpu = opaque;
3826 cpu_reset(CPU(cpu));
3827}
dd673288
IM		 3828#endif
3829
de024815
AF		 3830static void mce_init(X86CPU *cpu)
3831{
3832 CPUX86State *cenv = &cpu->env;
3833 unsigned int bank;
3834
3835 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 3836 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 3837 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 3838 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
3839 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 3840 cenv->mcg_ctl = ~(uint64_t)0;
3841 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
3842 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
3843 }
3844 }
3845}
3846
bdeec802 3847#ifndef CONFIG_USER_ONLY
2f114315 3848APICCommonClass *apic_get_class(void)
bdeec802 3849{
bdeec802
IM		 3850 const char *apic_type = "apic";
3851
d6dcc558 3852 /* TODO: in-kernel irqchip for hvf */
15eafc2e 3853 if (kvm_apic_in_kernel()) {
bdeec802
IM		 3854 apic_type = "kvm-apic";
3855 } else if (xen_enabled()) {
3856 apic_type = "xen-apic";
3857 }
3858
2f114315
RK		 3859 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
3860}
3861
3862static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
3863{
3864 APICCommonState *apic;
3865 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
3866
3867 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 3868
6816b1b3
IM		 3869 object_property_add_child(OBJECT(cpu), "lapic",
3870 OBJECT(cpu->apic_state), &error_abort);
67e55caa 3871 object_unref(OBJECT(cpu->apic_state));
6816b1b3 3872
33d7a288 3873 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 3874 /* TODO: convert to link<> */
02e51483 3875 apic = APIC_COMMON(cpu->apic_state);
60671e58 3876 apic->cpu = cpu;
8d42d2d3 3877 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 3878}
3879
3880static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3881{
8d42d2d3
CF		 3882 APICCommonState *apic;
3883 static bool apic_mmio_map_once;
3884
02e51483 3885 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 3886 return;
3887 }
6e8e2651
MA		 3888 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
3889 errp);
8d42d2d3
CF		 3890
3891 /* Map APIC MMIO area */
3892 apic = APIC_COMMON(cpu->apic_state);
3893 if (!apic_mmio_map_once) {
3894 memory_region_add_subregion_overlap(get_system_memory(),
3895 apic->apicbase &
3896 MSR_IA32_APICBASE_BASE,
3897 &apic->io_memory,
3898 0x1000);
3899 apic_mmio_map_once = true;
3900 }
bdeec802 3901}
f809c605
PB		 3902
3903static void x86_cpu_machine_done(Notifier *n, void *unused)
3904{
3905 X86CPU *cpu = container_of(n, X86CPU, machine_done);
3906 MemoryRegion *smram =
3907 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
3908
3909 if (smram) {
3910 cpu->smram = g_new(MemoryRegion, 1);
3911 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
3912 smram, 0, 1ull << 32);
f8c45c65 3913 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 3914 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
3915 }
3916}
d3c64d6a
IM		 3917#else
3918static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3919{
3920}
bdeec802
IM		 3921#endif
3922
11f6fee5
DDAG		 3923/* Note: Only safe for use on x86(-64) hosts */
3924static uint32_t x86_host_phys_bits(void)
3925{
3926 uint32_t eax;
3927 uint32_t host_phys_bits;
3928
3929 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
3930 if (eax >= 0x80000008) {
3931 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
3932 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3933 * at 23:16 that can specify a maximum physical address bits for
3934 * the guest that can override this value; but I've not seen
3935 * anything with that set.
3936 */
3937 host_phys_bits = eax & 0xff;
3938 } else {
3939 /* It's an odd 64 bit machine that doesn't have the leaf for
3940 * physical address bits; fall back to 36 that's most older
3941 * Intel.
3942 */
3943 host_phys_bits = 36;
3944 }
3945
3946 return host_phys_bits;
3947}
e48638fd 3948
c39c0edf
EH		 3949static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
3950{
3951 if (*min < value) {
3952 *min = value;
3953 }
3954}
3955
3956/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3957static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
3958{
3959 CPUX86State *env = &cpu->env;
3960 FeatureWordInfo *fi = &feature_word_info[w];
3961 uint32_t eax = fi->cpuid_eax;
3962 uint32_t region = eax & 0xF0000000;
3963
3964 if (!env->features[w]) {
3965 return;
3966 }
3967
3968 switch (region) {
3969 case 0x00000000:
3970 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
3971 break;
3972 case 0x80000000:
3973 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
3974 break;
3975 case 0xC0000000:
3976 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
3977 break;
3978 }
3979}
3980
2ca8a8be
EH		 3981/* Calculate XSAVE components based on the configured CPU feature flags */
3982static void x86_cpu_enable_xsave_components(X86CPU *cpu)
3983{
3984 CPUX86State *env = &cpu->env;
3985 int i;
96193c22 3986 uint64_t mask;
2ca8a8be
EH		 3987
3988 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
3989 return;
3990 }
3991
e3c9022b
EH		 3992 mask = 0;
3993 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 3994 const ExtSaveArea *esa = &x86_ext_save_areas[i];
3995 if (env->features[esa->feature] & esa->bits) {
96193c22 3996 mask |= (1ULL << i);
2ca8a8be
EH		 3997 }
3998 }
3999
96193c22
EH		 4000 env->features[FEAT_XSAVE_COMP_LO] = mask;
4001 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 4002}
4003
b8d834a0
EH		 4004/***** Steps involved on loading and filtering CPUID data
4005 *
4006 * When initializing and realizing a CPU object, the steps
4007 * involved in setting up CPUID data are:
4008 *
4009 * 1) Loading CPU model definition (X86CPUDefinition). This is
4010 * implemented by x86_cpu_load_def() and should be completely
4011 * transparent, as it is done automatically by instance_init.
4012 * No code should need to look at X86CPUDefinition structs
4013 * outside instance_init.
4014 *
4015 * 2) CPU expansion. This is done by realize before CPUID
4016 * filtering, and will make sure host/accelerator data is
4017 * loaded for CPU models that depend on host capabilities
4018 * (e.g. "host"). Done by x86_cpu_expand_features().
4019 *
4020 * 3) CPUID filtering. This initializes extra data related to
4021 * CPUID, and checks if the host supports all capabilities
4022 * required by the CPU. Runnability of a CPU model is
4023 * determined at this step. Done by x86_cpu_filter_features().
4024 *
4025 * Some operations don't require all steps to be performed.
4026 * More precisely:
4027 *
4028 * - CPU instance creation (instance_init) will run only CPU
4029 * model loading. CPU expansion can't run at instance_init-time
4030 * because host/accelerator data may be not available yet.
4031 * - CPU realization will perform both CPU model expansion and CPUID
4032 * filtering, and return an error in case one of them fails.
4033 * - query-cpu-definitions needs to run all 3 steps. It needs
4034 * to run CPUID filtering, as the 'unavailable-features'
4035 * field is set based on the filtering results.
4036 * - The query-cpu-model-expansion QMP command only needs to run
4037 * CPU model loading and CPU expansion. It should not filter
4038 * any CPUID data based on host capabilities.
4039 */
4040
4041/* Expand CPU configuration data, based on configured features
4042 * and host/accelerator capabilities when appropriate.
4043 */
4044static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 4045{
b34d12d1 4046 CPUX86State *env = &cpu->env;
dc15c051 4047 FeatureWord w;
2fae0d96 4048 GList *l;
41f3d4d6 4049 Error *local_err = NULL;
9886e834 4050
d4a606b3
EH		 4051 /*TODO: Now cpu->max_features doesn't overwrite features
4052 * set using QOM properties, and we can convert
dc15c051
IM		 4053 * plus_features & minus_features to global properties
4054 * inside x86_cpu_parse_featurestr() too.
4055 */
44bd8e53 4056 if (cpu->max_features) {
dc15c051 4057 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 4058 /* Override only features that weren't set explicitly
4059 * by the user.
4060 */
4061 env->features[w] |=
4062 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
4063 ~env->user_features[w];
dc15c051
IM		 4064 }
4065 }
4066
2fae0d96
EH		 4067 for (l = plus_features; l; l = l->next) {
4068 const char *prop = l->data;
4069 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
4070 if (local_err) {
4071 goto out;
4072 }
4073 }
4074
4075 for (l = minus_features; l; l = l->next) {
4076 const char *prop = l->data;
4077 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
4078 if (local_err) {
4079 goto out;
4080 }
dc15c051
IM		 4081 }
4082
aec661de
EH		 4083 if (!kvm_enabled() || !cpu->expose_kvm) {
4084 env->features[FEAT_KVM] = 0;
4085 }
4086
2ca8a8be 4087 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 4088
4089 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
4090 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
4091 if (cpu->full_cpuid_auto_level) {
4092 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
4093 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
4094 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
4095 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
4096 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
4097 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
4098 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 4099 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 4100 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
4101 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
4102 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 4103 /* SVM requires CPUID[0x8000000A] */
4104 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
4105 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
4106 }
6cb8f2a6
BS		 4107
4108 /* SEV requires CPUID[0x8000001F] */
4109 if (sev_enabled()) {
4110 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
4111 }
c39c0edf
EH		 4112 }
4113
4114 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
4115 if (env->cpuid_level == UINT32_MAX) {
4116 env->cpuid_level = env->cpuid_min_level;
4117 }
4118 if (env->cpuid_xlevel == UINT32_MAX) {
4119 env->cpuid_xlevel = env->cpuid_min_xlevel;
4120 }
4121 if (env->cpuid_xlevel2 == UINT32_MAX) {
4122 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 4123 }
7a059953 4124
41f3d4d6
EH		 4125out:
4126 if (local_err != NULL) {
4127 error_propagate(errp, local_err);
4128 }
4129}
4130
b8d834a0
EH		 4131/*
4132 * Finishes initialization of CPUID data, filters CPU feature
4133 * words based on host availability of each feature.
4134 *
4135 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
4136 */
4137static int x86_cpu_filter_features(X86CPU *cpu)
4138{
4139 CPUX86State *env = &cpu->env;
4140 FeatureWord w;
4141 int rv = 0;
4142
4143 for (w = 0; w < FEATURE_WORDS; w++) {
4144 uint32_t host_feat =
4145 x86_cpu_get_supported_feature_word(w, false);
4146 uint32_t requested_features = env->features[w];
4147 env->features[w] &= host_feat;
4148 cpu->filtered_features[w] = requested_features & ~env->features[w];
4149 if (cpu->filtered_features[w]) {
4150 rv = 1;
4151 }
4152 }
4153
e37a5c7f
CP		 4154 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
4155 kvm_enabled()) {
4156 KVMState *s = CPU(cpu)->kvm_state;
4157 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
4158 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
4159 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
4160 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
4161 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
4162
4163 if (!eax_0 ||
4164 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
4165 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
4166 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
4167 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
4168 INTEL_PT_ADDR_RANGES_NUM) ||
4169 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
4170 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP))) {
4171 /*
4172 * Processor Trace capabilities aren't configurable, so if the
4173 * host can't emulate the capabilities we report on
4174 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
4175 */
4176 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
4177 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
4178 rv = 1;
4179 }
4180 }
4181
b8d834a0
EH		 4182 return rv;
4183}
4184
41f3d4d6
EH		 4185#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
4186 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
4187 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
4188#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
4189 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
4190 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
4191static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
4192{
4193 CPUState *cs = CPU(dev);
4194 X86CPU *cpu = X86_CPU(dev);
4195 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
4196 CPUX86State *env = &cpu->env;
4197 Error *local_err = NULL;
4198 static bool ht_warned;
4199
d6dcc558 4200 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
41f3d4d6
EH		 4201 char *name = x86_cpu_class_get_model_name(xcc);
4202 error_setg(&local_err, "CPU model '%s' requires KVM", name);
4203 g_free(name);
4204 goto out;
4205 }
4206
4207 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
4208 error_setg(errp, "apic-id property was not initialized properly");
4209 return;
4210 }
4211
b8d834a0 4212 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 4213 if (local_err) {
4214 goto out;
4215 }
4216
8ca30e86
EH		 4217 if (x86_cpu_filter_features(cpu) &&
4218 (cpu->check_cpuid || cpu->enforce_cpuid)) {
4219 x86_cpu_report_filtered_features(cpu);
4220 if (cpu->enforce_cpuid) {
4221 error_setg(&local_err,
d6dcc558 4222 accel_uses_host_cpuid() ?
8ca30e86
EH		 4223 "Host doesn't support requested features" :
4224 "TCG doesn't support requested features");
4225 goto out;
4226 }
9997cf7b
EH		 4227 }
4228
9b15cd9e
IM		 4229 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
4230 * CPUID[1].EDX.
4231 */
e48638fd 4232 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 4233 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
4234 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 4235 & CPUID_EXT2_AMD_ALIASES);
4236 }
4237
11f6fee5
DDAG		 4238 /* For 64bit systems think about the number of physical bits to present.
4239 * ideally this should be the same as the host; anything other than matching
4240 * the host can cause incorrect guest behaviour.
4241 * QEMU used to pick the magic value of 40 bits that corresponds to
4242 * consumer AMD devices but nothing else.
4243 */
af45907a 4244 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 4245 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 4246 uint32_t host_phys_bits = x86_host_phys_bits();
4247 static bool warned;
4248
4249 if (cpu->host_phys_bits) {
4250 /* The user asked for us to use the host physical bits */
4251 cpu->phys_bits = host_phys_bits;
4252 }
4253
4254 /* Print a warning if the user set it to a value that's not the
4255 * host value.
4256 */
4257 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
4258 !warned) {
3dc6f869
AF		 4259 warn_report("Host physical bits (%u)"
4260 " does not match phys-bits property (%u)",
4261 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 4262 warned = true;
4263 }
4264
4265 if (cpu->phys_bits &&
4266 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
4267 cpu->phys_bits < 32)) {
af45907a
DDAG		 4268 error_setg(errp, "phys-bits should be between 32 and %u "
4269 " (but is %u)",
4270 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
4271 return;
4272 }
4273 } else {
11f6fee5 4274 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 4275 error_setg(errp, "TCG only supports phys-bits=%u",
4276 TCG_PHYS_ADDR_BITS);
4277 return;
4278 }
4279 }
11f6fee5
DDAG		 4280 /* 0 means it was not explicitly set by the user (or by machine
4281 * compat_props or by the host code above). In this case, the default
4282 * is the value used by TCG (40).
4283 */
4284 if (cpu->phys_bits == 0) {
4285 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
4286 }
af45907a
DDAG		 4287 } else {
4288 /* For 32 bit systems don't use the user set value, but keep
4289 * phys_bits consistent with what we tell the guest.
4290 */
4291 if (cpu->phys_bits != 0) {
4292 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
4293 return;
4294 }
fefb41bf 4295
af45907a
DDAG		 4296 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
4297 cpu->phys_bits = 36;
4298 } else {
4299 cpu->phys_bits = 32;
4300 }
4301 }
ce5b1bbf
LV		 4302 cpu_exec_realizefn(cs, &local_err);
4303 if (local_err != NULL) {
4304 error_propagate(errp, local_err);
4305 return;
4306 }
42ecabaa 4307
65dee380
IM		 4308#ifndef CONFIG_USER_ONLY
4309 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 4310
0514ef2f 4311 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 4312 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 4313 if (local_err != NULL) {
4dc1f449 4314 goto out;
bdeec802
IM		 4315 }
4316 }
65dee380
IM		 4317#endif
4318
7a059953 4319 mce_init(cpu);
2001d0cd
PB		 4320
4321#ifndef CONFIG_USER_ONLY
4322 if (tcg_enabled()) {
f809c605 4323 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 4324 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 4325
4326 /* Outer container... */
4327 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 4328 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 4329
4330 /* ... with two regions inside: normal system memory with low
4331 * priority, and...
4332 */
4333 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
4334 get_system_memory(), 0, ~0ull);
4335 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
4336 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 4337
4338 cs->num_ases = 2;
80ceb07a
PX		 4339 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
4340 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 4341
4342 /* ... SMRAM with higher priority, linked from /machine/smram. */
4343 cpu->machine_done.notify = x86_cpu_machine_done;
4344 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 4345 }
4346#endif
4347
14a10fc3 4348 qemu_init_vcpu(cs);
d3c64d6a 4349
e48638fd
WH		 4350 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
4351 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
4352 * based on inputs (sockets,cores,threads), it is still better to gives
4353 * users a warning.
4354 *
4355 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
4356 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
4357 */
4358 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
4359 error_report("AMD CPU doesn't support hyperthreading. Please configure"
4360 " -smp options properly.");
4361 ht_warned = true;
4362 }
4363
d3c64d6a
IM		 4364 x86_cpu_apic_realize(cpu, &local_err);
4365 if (local_err != NULL) {
4366 goto out;
4367 }
14a10fc3 4368 cpu_reset(cs);
2b6f294c 4369
4dc1f449 4370 xcc->parent_realize(dev, &local_err);
2001d0cd 4371
4dc1f449
IM		 4372out:
4373 if (local_err != NULL) {
4374 error_propagate(errp, local_err);
4375 return;
4376 }
7a059953
AF		 4377}
4378
c884776e
IM		 4379static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
4380{
4381 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 4382 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
4383 Error *local_err = NULL;
c884776e
IM		 4384
4385#ifndef CONFIG_USER_ONLY
4386 cpu_remove_sync(CPU(dev));
4387 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
4388#endif
4389
4390 if (cpu->apic_state) {
4391 object_unparent(OBJECT(cpu->apic_state));
4392 cpu->apic_state = NULL;
4393 }
7bbc124e
LV		 4394
4395 xcc->parent_unrealize(dev, &local_err);
4396 if (local_err != NULL) {
4397 error_propagate(errp, local_err);
4398 return;
4399 }
c884776e
IM		 4400}
4401
38e5c119 4402typedef struct BitProperty {
a7b0ffac 4403 FeatureWord w;
38e5c119
EH		 4404 uint32_t mask;
4405} BitProperty;
4406
d7bce999
EB		 4407static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
4408 void *opaque, Error **errp)
38e5c119 4409{
a7b0ffac 4410 X86CPU *cpu = X86_CPU(obj);
38e5c119 4411 BitProperty *fp = opaque;
a7b0ffac
EH		 4412 uint32_t f = cpu->env.features[fp->w];
4413 bool value = (f & fp->mask) == fp->mask;
51e72bc1 4414 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 4415}
4416
d7bce999
EB		 4417static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
4418 void *opaque, Error **errp)
38e5c119
EH		 4419{
4420 DeviceState *dev = DEVICE(obj);
a7b0ffac 4421 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 4422 BitProperty *fp = opaque;
4423 Error *local_err = NULL;
4424 bool value;
4425
4426 if (dev->realized) {
4427 qdev_prop_set_after_realize(dev, name, errp);
4428 return;
4429 }
4430
51e72bc1 4431 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 4432 if (local_err) {
4433 error_propagate(errp, local_err);
4434 return;
4435 }
4436
4437 if (value) {
a7b0ffac 4438 cpu->env.features[fp->w] |= fp->mask;
38e5c119 4439 } else {
a7b0ffac 4440 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 4441 }
d4a606b3 4442 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 4443}
4444
4445static void x86_cpu_release_bit_prop(Object *obj, const char *name,
4446 void *opaque)
4447{
4448 BitProperty *prop = opaque;
4449 g_free(prop);
4450}
4451
4452/* Register a boolean property to get/set a single bit in a uint32_t field.
4453 *
4454 * The same property name can be registered multiple times to make it affect
4455 * multiple bits in the same FeatureWord. In that case, the getter will return
4456 * true only if all bits are set.
4457 */
4458static void x86_cpu_register_bit_prop(X86CPU *cpu,
4459 const char *prop_name,
a7b0ffac 4460 FeatureWord w,
38e5c119
EH		 4461 int bitnr)
4462{
4463 BitProperty *fp;
4464 ObjectProperty *op;
4465 uint32_t mask = (1UL << bitnr);
4466
4467 op = object_property_find(OBJECT(cpu), prop_name, NULL);
4468 if (op) {
4469 fp = op->opaque;
a7b0ffac 4470 assert(fp->w == w);
38e5c119
EH		 4471 fp->mask |= mask;
4472 } else {
4473 fp = g_new0(BitProperty, 1);
a7b0ffac 4474 fp->w = w;
38e5c119
EH		 4475 fp->mask = mask;
4476 object_property_add(OBJECT(cpu), prop_name, "bool",
4477 x86_cpu_get_bit_prop,
4478 x86_cpu_set_bit_prop,
4479 x86_cpu_release_bit_prop, fp, &error_abort);
4480 }
4481}
4482
4483static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
4484 FeatureWord w,
4485 int bitnr)
4486{
38e5c119 4487 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 4488 const char *name = fi->feat_names[bitnr];
38e5c119 4489
16d2fcaa 4490 if (!name) {
38e5c119
EH		 4491 return;
4492 }
4493
fc7dfd20
EH		 4494 /* Property names should use "-" instead of "_".
4495 * Old names containing underscores are registered as aliases
4496 * using object_property_add_alias()
4497 */
16d2fcaa
EH		 4498 assert(!strchr(name, '_'));
4499 /* aliases don't use "|" delimiters anymore, they are registered
4500 * manually using object_property_add_alias() */
4501 assert(!strchr(name, '|'));
a7b0ffac 4502 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 4503}
4504
d187e08d
AN		 4505static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
4506{
4507 X86CPU *cpu = X86_CPU(cs);
4508 CPUX86State *env = &cpu->env;
4509 GuestPanicInformation *panic_info = NULL;
4510
5e953812 4511 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 4512 panic_info = g_malloc0(sizeof(GuestPanicInformation));
4513
e8ed97a6 4514 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 4515
5e953812 4516 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 4517 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
4518 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
4519 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
4520 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
4521 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 4522 }
4523
4524 return panic_info;
4525}
4526static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
4527 const char *name, void *opaque,
4528 Error **errp)
4529{
4530 CPUState *cs = CPU(obj);
4531 GuestPanicInformation *panic_info;
4532
4533 if (!cs->crash_occurred) {
4534 error_setg(errp, "No crash occured");
4535 return;
4536 }
4537
4538 panic_info = x86_cpu_get_crash_info(cs);
4539 if (panic_info == NULL) {
4540 error_setg(errp, "No crash information");
4541 return;
4542 }
4543
4544 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
4545 errp);
4546 qapi_free_GuestPanicInformation(panic_info);
4547}
4548
de024815
AF		 4549static void x86_cpu_initfn(Object *obj)
4550{
55e5c285 4551 CPUState *cs = CPU(obj);
de024815 4552 X86CPU *cpu = X86_CPU(obj);
d940ee9b 4553 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 4554 CPUX86State *env = &cpu->env;
38e5c119 4555 FeatureWord w;
de024815 4556
c05efcb1 4557 cs->env_ptr = env;
71ad61d3
AF		 4558
4559 object_property_add(obj, "family", "int",
95b8519d 4560 x86_cpuid_version_get_family,
71ad61d3 4561 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 4562 object_property_add(obj, "model", "int",
67e30c83 4563 x86_cpuid_version_get_model,
c5291a4f 4564 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 4565 object_property_add(obj, "stepping", "int",
35112e41 4566 x86_cpuid_version_get_stepping,
036e2222 4567 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 4568 object_property_add_str(obj, "vendor",
4569 x86_cpuid_get_vendor,
4570 x86_cpuid_set_vendor, NULL);
938d4c25 4571 object_property_add_str(obj, "model-id",
63e886eb 4572 x86_cpuid_get_model_id,
938d4c25 4573 x86_cpuid_set_model_id, NULL);
89e48965
AF		 4574 object_property_add(obj, "tsc-frequency", "int",
4575 x86_cpuid_get_tsc_freq,
4576 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 4577 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
4578 x86_cpu_get_feature_words,
7e5292b5
EH		 4579 NULL, NULL, (void *)env->features, NULL);
4580 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
4581 x86_cpu_get_feature_words,
4582 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 4583
d187e08d
AN		 4584 object_property_add(obj, "crash-information", "GuestPanicInformation",
4585 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
4586
92067bf4 4587 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 4588
38e5c119
EH		 4589 for (w = 0; w < FEATURE_WORDS; w++) {
4590 int bitnr;
4591
4592 for (bitnr = 0; bitnr < 32; bitnr++) {
4593 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
4594 }
4595 }
4596
16d2fcaa
EH		 4597 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
4598 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
4599 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
4600 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
4601 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
4602 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
4603 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
4604
54b8dc7c
EH		 4605 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
4606 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
4607 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
4608 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
4609 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
4610 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
4611 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
4612 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
4613 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
4614 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
4615 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
4616 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
4617 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
4618 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
4619 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
4620 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
4621 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
4622 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
4623 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
4624 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
4625 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
4626
0bacd8b3
EH		 4627 if (xcc->cpu_def) {
4628 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
4629 }
de024815
AF		 4630}
4631
997395d3
IM		 4632static int64_t x86_cpu_get_arch_id(CPUState *cs)
4633{
4634 X86CPU *cpu = X86_CPU(cs);
997395d3 4635
7e72a45c 4636 return cpu->apic_id;
997395d3
IM		 4637}
4638
444d5590
AF		 4639static bool x86_cpu_get_paging_enabled(const CPUState *cs)
4640{
4641 X86CPU *cpu = X86_CPU(cs);
4642
4643 return cpu->env.cr[0] & CR0_PG_MASK;
4644}
4645
f45748f1
AF		 4646static void x86_cpu_set_pc(CPUState *cs, vaddr value)
4647{
4648 X86CPU *cpu = X86_CPU(cs);
4649
4650 cpu->env.eip = value;
4651}
4652
bdf7ae5b
AF		 4653static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
4654{
4655 X86CPU *cpu = X86_CPU(cs);
4656
4657 cpu->env.eip = tb->pc - tb->cs_base;
4658}
4659
8c2e1b00
AF		 4660static bool x86_cpu_has_work(CPUState *cs)
4661{
4662 X86CPU *cpu = X86_CPU(cs);
4663 CPUX86State *env = &cpu->env;
4664
6220e900
PD		 4665 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
4666 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 4667 (env->eflags & IF_MASK)) ||
4668 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
4669 CPU_INTERRUPT_INIT |
4670 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 4671 CPU_INTERRUPT_MCE)) ||
4672 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
4673 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 4674}
4675
f50f3dd5
RH		 4676static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
4677{
4678 X86CPU *cpu = X86_CPU(cs);
4679 CPUX86State *env = &cpu->env;
4680
4681 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
4682 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
4683 : bfd_mach_i386_i8086);
4684 info->print_insn = print_insn_i386;
b666d2a4
RH		 4685
4686 info->cap_arch = CS_ARCH_X86;
4687 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
4688 : env->hflags & HF_CS32_MASK ? CS_MODE_32
4689 : CS_MODE_16);
15fa1a0a
RH		 4690 info->cap_insn_unit = 1;
4691 info->cap_insn_split = 8;
f50f3dd5
RH		 4692}
4693
35b1b927
TW		 4694void x86_update_hflags(CPUX86State *env)
4695{
4696 uint32_t hflags;
4697#define HFLAG_COPY_MASK \
4698 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
4699 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
4700 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
4701 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
4702
4703 hflags = env->hflags & HFLAG_COPY_MASK;
4704 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
4705 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
4706 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
4707 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
4708 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
4709
4710 if (env->cr[4] & CR4_OSFXSR_MASK) {
4711 hflags |= HF_OSFXSR_MASK;
4712 }
4713
4714 if (env->efer & MSR_EFER_LMA) {
4715 hflags |= HF_LMA_MASK;
4716 }
4717
4718 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
4719 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
4720 } else {
4721 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
4722 (DESC_B_SHIFT - HF_CS32_SHIFT);
4723 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
4724 (DESC_B_SHIFT - HF_SS32_SHIFT);
4725 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
4726 !(hflags & HF_CS32_MASK)) {
4727 hflags |= HF_ADDSEG_MASK;
4728 } else {
4729 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
4730 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
4731 }
4732 }
4733 env->hflags = hflags;
4734}
4735
9337e3b6 4736static Property x86_cpu_properties[] = {
2da00e31
IM		 4737#ifdef CONFIG_USER_ONLY
4738 /* apic_id = 0 by default for *-user, see commit 9886e834 */
4739 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 4740 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
4741 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
4742 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 4743#else
4744 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 4745 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
4746 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
4747 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 4748#endif
15f8b142 4749 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 4750 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 4751 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 4752 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 4753 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 4754 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 4755 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 4756 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 4757 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 4758 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 4759 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 4760 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 4761 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 4762 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 4763 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 4764 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 4765 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 4766 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 4767 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
4768 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
4769 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
4770 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
4771 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
4772 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4773 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 4774 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 4775 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 4776 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 4777 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 4778 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
4779 false),
0b564e6f 4780 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 4781 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
6c69dfb6
GA		 4782
4783 /*
4784 * From "Requirements for Implementing the Microsoft
4785 * Hypervisor Interface":
4786 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
4787 *
4788 * "Starting with Windows Server 2012 and Windows 8, if
4789 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
4790 * the hypervisor imposes no specific limit to the number of VPs.
4791 * In this case, Windows Server 2012 guest VMs may use more than
4792 * 64 VPs, up to the maximum supported number of processors applicable
4793 * to the specific Windows version being used."
4794 */
4795 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9337e3b6
EH		 4796 DEFINE_PROP_END_OF_LIST()
4797};
4798
5fd2087a
AF		 4799static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
4800{
4801 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4802 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 4803 DeviceClass *dc = DEVICE_CLASS(oc);
4804
bf853881
PMD		 4805 device_class_set_parent_realize(dc, x86_cpu_realizefn,
4806 &xcc->parent_realize);
4807 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
4808 &xcc->parent_unrealize);
9337e3b6 4809 dc->props = x86_cpu_properties;
5fd2087a
AF		 4810
4811 xcc->parent_reset = cc->reset;
4812 cc->reset = x86_cpu_reset;
91b1df8c 4813 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 4814
500050d1 4815 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 4816 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 4817 cc->has_work = x86_cpu_has_work;
79c664f6 4818#ifdef CONFIG_TCG
97a8ea5a 4819 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 4820 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 4821#endif
878096ee 4822 cc->dump_state = x86_cpu_dump_state;
c86f106b 4823 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 4824 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 4825 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 4826 cc->gdb_read_register = x86_cpu_gdb_read_register;
4827 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 4828 cc->get_arch_id = x86_cpu_get_arch_id;
4829 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 4830#ifdef CONFIG_USER_ONLY
4831 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
4832#else
f8c45c65 4833 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 4834 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 4835 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 4836 cc->write_elf64_note = x86_cpu_write_elf64_note;
4837 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
4838 cc->write_elf32_note = x86_cpu_write_elf32_note;
4839 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 4840 cc->vmsd = &vmstate_x86_cpu;
c72bf468 4841#endif
00fcd100
AB		 4842 cc->gdb_arch_name = x86_gdb_arch_name;
4843#ifdef TARGET_X86_64
b8158192
AB		 4844 cc->gdb_core_xml_file = "i386-64bit.xml";
4845 cc->gdb_num_core_regs = 57;
00fcd100 4846#else
b8158192
AB		 4847 cc->gdb_core_xml_file = "i386-32bit.xml";
4848 cc->gdb_num_core_regs = 41;
00fcd100 4849#endif
79c664f6 4850#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 4851 cc->debug_excp_handler = breakpoint_handler;
4852#endif
374e0cd4
RH		 4853 cc->cpu_exec_enter = x86_cpu_exec_enter;
4854 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 4855#ifdef CONFIG_TCG
55c3ceef 4856 cc->tcg_initialize = tcg_x86_init;
74d7fc7f 4857#endif
f50f3dd5 4858 cc->disas_set_info = x86_disas_set_info;
4c315c27 4859
e90f2a8c 4860 dc->user_creatable = true;
5fd2087a
AF		 4861}
4862
4863static const TypeInfo x86_cpu_type_info = {
4864 .name = TYPE_X86_CPU,
4865 .parent = TYPE_CPU,
4866 .instance_size = sizeof(X86CPU),
de024815 4867 .instance_init = x86_cpu_initfn,
d940ee9b 4868 .abstract = true,
5fd2087a
AF		 4869 .class_size = sizeof(X86CPUClass),
4870 .class_init = x86_cpu_common_class_init,
4871};
4872
5adbed30
EH		 4873
4874/* "base" CPU model, used by query-cpu-model-expansion */
4875static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
4876{
4877 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4878
4879 xcc->static_model = true;
4880 xcc->migration_safe = true;
4881 xcc->model_description = "base CPU model type with no features enabled";
4882 xcc->ordering = 8;
4883}
4884
4885static const TypeInfo x86_base_cpu_type_info = {
4886 .name = X86_CPU_TYPE_NAME("base"),
4887 .parent = TYPE_X86_CPU,
4888 .class_init = x86_cpu_base_class_init,
4889};
4890
5fd2087a
AF		 4891static void x86_cpu_register_types(void)
4892{
d940ee9b
EH		 4893 int i;
4894
5fd2087a 4895 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 4896 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
4897 x86_register_cpudef_type(&builtin_x86_defs[i]);
4898 }
c62f2630 4899 type_register_static(&max_x86_cpu_type_info);
5adbed30 4900 type_register_static(&x86_base_cpu_type_info);
d6dcc558 4901#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 4902 type_register_static(&host_x86_cpu_type_info);
4903#endif
5fd2087a
AF		 4904}
4905
4906type_init(x86_cpu_register_types)
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