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qdev-properties: Add a new macro with bitmask check for uint64_t property
[mirror_qemu.git] / target / i386 / cpu.c
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c6dc6f63 1/*
79f1a68a 2 * i386 CPUID, CPU class, definitions, models
c6dc6f63
AP		 3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
d9ff33ad 9 * version 2.1 of the License, or (at your option) any later version.
c6dc6f63
AP		 10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
0442428a 23#include "qemu/qemu-print.h"
15e09912 24#include "qemu/hw-version.h"
c6dc6f63 25#include "cpu.h"
ed69e831 26#include "tcg/helper-tcg.h"
71e8a915 27#include "sysemu/reset.h"
d6dcc558 28#include "sysemu/hvf.h"
a9dc68d9 29#include "kvm/kvm_i386.h"
93777de3 30#include "sev.h"
f83aeeae 31#include "qapi/error.h"
8ac25c84 32#include "qapi/qapi-visit-machine.h"
7b1b5d19 33#include "qapi/qmp/qerror.h"
7f7b4e7a 34#include "qapi/qapi-commands-machine-target.h"
1814eab6 35#include "standard-headers/asm-x86/kvm_para.h"
53a89e26 36#include "hw/qdev-properties.h"
5232d00a 37#include "hw/i386/topology.h"
bdeec802 38#ifndef CONFIG_USER_ONLY
2001d0cd 39#include "exec/address-spaces.h"
0e11fc69 40#include "hw/boards.h"
1dec2e1f 41#include "hw/i386/sgx-epc.h"
bdeec802
IM		 42#endif
43
b666d2a4 44#include "disas/capstone.h"
79f1a68a 45#include "cpu-internal.h"
b666d2a4 46
7e3482f8
EH		 47/* Helpers for building CPUID[2] descriptors: */
48
49struct CPUID2CacheDescriptorInfo {
50 enum CacheType type;
51 int level;
52 int size;
53 int line_size;
54 int associativity;
55};
5e891bf8 56
7e3482f8
EH		 57/*
58 * Known CPUID 2 cache descriptors.
59 * From Intel SDM Volume 2A, CPUID instruction
60 */
61struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 62 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 63 .associativity = 4, .line_size = 32, },
5f00335a 64 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 65 .associativity = 4, .line_size = 32, },
5f00335a 66 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 67 .associativity = 4, .line_size = 64, },
5f00335a 68 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 69 .associativity = 2, .line_size = 32, },
5f00335a 70 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 71 .associativity = 4, .line_size = 32, },
5f00335a 72 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 73 .associativity = 4, .line_size = 64, },
5f00335a 74 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 75 .associativity = 6, .line_size = 64, },
5f00335a 76 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 77 .associativity = 2, .line_size = 64, },
5f00335a 78 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 79 .associativity = 8, .line_size = 64, },
80 /* lines per sector is not supported cpuid2_cache_descriptor(),
81 * so descriptors 0x22, 0x23 are not included
82 */
5f00335a 83 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 84 .associativity = 16, .line_size = 64, },
85 /* lines per sector is not supported cpuid2_cache_descriptor(),
86 * so descriptors 0x25, 0x20 are not included
87 */
5f00335a 88 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 89 .associativity = 8, .line_size = 64, },
5f00335a 90 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 91 .associativity = 8, .line_size = 64, },
5f00335a 92 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 93 .associativity = 4, .line_size = 32, },
5f00335a 94 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 95 .associativity = 4, .line_size = 32, },
5f00335a 96 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 97 .associativity = 4, .line_size = 32, },
5f00335a 98 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 99 .associativity = 4, .line_size = 32, },
5f00335a 100 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 101 .associativity = 4, .line_size = 32, },
5f00335a 102 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 103 .associativity = 4, .line_size = 64, },
5f00335a 104 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 105 .associativity = 8, .line_size = 64, },
5f00335a 106 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 107 .associativity = 12, .line_size = 64, },
108 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 109 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 110 .associativity = 12, .line_size = 64, },
5f00335a 111 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 112 .associativity = 16, .line_size = 64, },
5f00335a 113 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 114 .associativity = 12, .line_size = 64, },
5f00335a 115 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 116 .associativity = 16, .line_size = 64, },
5f00335a 117 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 118 .associativity = 24, .line_size = 64, },
5f00335a 119 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 120 .associativity = 8, .line_size = 64, },
5f00335a 121 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 122 .associativity = 4, .line_size = 64, },
5f00335a 123 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 124 .associativity = 4, .line_size = 64, },
5f00335a 125 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 126 .associativity = 4, .line_size = 64, },
5f00335a 127 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 128 .associativity = 4, .line_size = 64, },
129 /* lines per sector is not supported cpuid2_cache_descriptor(),
130 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
131 */
5f00335a 132 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 133 .associativity = 8, .line_size = 64, },
5f00335a 134 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 135 .associativity = 2, .line_size = 64, },
5f00335a 136 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 137 .associativity = 8, .line_size = 64, },
5f00335a 138 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 139 .associativity = 8, .line_size = 32, },
5f00335a 140 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 141 .associativity = 8, .line_size = 32, },
5f00335a 142 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 143 .associativity = 8, .line_size = 32, },
5f00335a 144 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 145 .associativity = 8, .line_size = 32, },
5f00335a 146 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 147 .associativity = 4, .line_size = 64, },
5f00335a 148 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 149 .associativity = 8, .line_size = 64, },
5f00335a 150 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 151 .associativity = 4, .line_size = 64, },
5f00335a 152 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 153 .associativity = 4, .line_size = 64, },
5f00335a 154 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 155 .associativity = 4, .line_size = 64, },
5f00335a 156 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 157 .associativity = 8, .line_size = 64, },
5f00335a 158 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 159 .associativity = 8, .line_size = 64, },
5f00335a 160 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 161 .associativity = 8, .line_size = 64, },
5f00335a 162 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 163 .associativity = 12, .line_size = 64, },
5f00335a 164 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 165 .associativity = 12, .line_size = 64, },
5f00335a 166 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 167 .associativity = 12, .line_size = 64, },
5f00335a 168 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 169 .associativity = 16, .line_size = 64, },
5f00335a 170 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 171 .associativity = 16, .line_size = 64, },
5f00335a 172 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 173 .associativity = 16, .line_size = 64, },
5f00335a 174 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 175 .associativity = 24, .line_size = 64, },
5f00335a 176 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 177 .associativity = 24, .line_size = 64, },
5f00335a 178 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 179 .associativity = 24, .line_size = 64, },
180};
181
182/*
183 * "CPUID leaf 2 does not report cache descriptor information,
184 * use CPUID leaf 4 to query cache parameters"
185 */
186#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 187
7e3482f8
EH		 188/*
189 * Return a CPUID 2 cache descriptor for a given cache.
190 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
191 */
192static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
193{
194 int i;
195
196 assert(cache->size > 0);
197 assert(cache->level > 0);
198 assert(cache->line_size > 0);
199 assert(cache->associativity > 0);
200 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
201 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
202 if (d->level == cache->level && d->type == cache->type &&
203 d->size == cache->size && d->line_size == cache->line_size &&
204 d->associativity == cache->associativity) {
205 return i;
206 }
207 }
5e891bf8 208
7e3482f8
EH		 209 return CACHE_DESCRIPTOR_UNAVAILABLE;
210}
5e891bf8
EH		 211
212/* CPUID Leaf 4 constants: */
213
214/* EAX: */
7e3482f8
EH		 215#define CACHE_TYPE_D 1
216#define CACHE_TYPE_I 2
217#define CACHE_TYPE_UNIFIED 3
5e891bf8 218
7e3482f8 219#define CACHE_LEVEL(l) (l << 5)
5e891bf8 220
7e3482f8 221#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 222
223/* EDX: */
7e3482f8
EH		 224#define CACHE_NO_INVD_SHARING (1 << 0)
225#define CACHE_INCLUSIVE (1 << 1)
226#define CACHE_COMPLEX_IDX (1 << 2)
227
228/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 229#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
230 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
231 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
232 0 /* Invalid value */)
7e3482f8
EH		 233
234
235/* Encode cache info for CPUID[4] */
236static void encode_cache_cpuid4(CPUCacheInfo *cache,
237 int num_apic_ids, int num_cores,
238 uint32_t *eax, uint32_t *ebx,
239 uint32_t *ecx, uint32_t *edx)
240{
241 assert(cache->size == cache->line_size * cache->associativity *
242 cache->partitions * cache->sets);
243
244 assert(num_apic_ids > 0);
245 *eax = CACHE_TYPE(cache->type) |
246 CACHE_LEVEL(cache->level) |
247 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
248 ((num_cores - 1) << 26) |
249 ((num_apic_ids - 1) << 14);
250
251 assert(cache->line_size > 0);
252 assert(cache->partitions > 0);
253 assert(cache->associativity > 0);
254 /* We don't implement fully-associative caches */
255 assert(cache->associativity < cache->sets);
256 *ebx = (cache->line_size - 1) |
257 ((cache->partitions - 1) << 12) |
258 ((cache->associativity - 1) << 22);
259
260 assert(cache->sets > 0);
261 *ecx = cache->sets - 1;
262
263 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
264 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
265 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
266}
267
268/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
269static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
270{
271 assert(cache->size % 1024 == 0);
272 assert(cache->lines_per_tag > 0);
273 assert(cache->associativity > 0);
274 assert(cache->line_size > 0);
275 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
276 (cache->lines_per_tag << 8) | (cache->line_size);
277}
5e891bf8
EH		 278
279#define ASSOC_FULL 0xFF
280
281/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
282#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
283 a == 2 ? 0x2 : \
284 a == 4 ? 0x4 : \
285 a == 8 ? 0x6 : \
286 a == 16 ? 0x8 : \
287 a == 32 ? 0xA : \
288 a == 48 ? 0xB : \
289 a == 64 ? 0xC : \
290 a == 96 ? 0xD : \
291 a == 128 ? 0xE : \
292 a == ASSOC_FULL ? 0xF : \
293 0 /* invalid value */)
294
7e3482f8
EH		 295/*
296 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
297 * @l3 can be NULL.
298 */
299static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
300 CPUCacheInfo *l3,
301 uint32_t *ecx, uint32_t *edx)
302{
303 assert(l2->size % 1024 == 0);
304 assert(l2->associativity > 0);
305 assert(l2->lines_per_tag > 0);
306 assert(l2->line_size > 0);
307 *ecx = ((l2->size / 1024) << 16) |
308 (AMD_ENC_ASSOC(l2->associativity) << 12) |
309 (l2->lines_per_tag << 8) | (l2->line_size);
310
311 if (l3) {
312 assert(l3->size % (512 * 1024) == 0);
313 assert(l3->associativity > 0);
314 assert(l3->lines_per_tag > 0);
315 assert(l3->line_size > 0);
316 *edx = ((l3->size / (512 * 1024)) << 18) |
317 (AMD_ENC_ASSOC(l3->associativity) << 12) |
318 (l3->lines_per_tag << 8) | (l3->line_size);
319 } else {
320 *edx = 0;
321 }
322}
5e891bf8 323
8f4202fb 324/* Encode cache info for CPUID[8000001D] */
2f084d1e
BM		 325static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
326 X86CPUTopoInfo *topo_info,
327 uint32_t *eax, uint32_t *ebx,
328 uint32_t *ecx, uint32_t *edx)
8f4202fb 329{
2f084d1e 330 uint32_t l3_threads;
8f4202fb
BM		 331 assert(cache->size == cache->line_size * cache->associativity *
332 cache->partitions * cache->sets);
333
334 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
335 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
336
337 /* L3 is shared among multiple cores */
338 if (cache->level == 3) {
2f084d1e
BM		 339 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
340 *eax |= (l3_threads - 1) << 14;
8f4202fb 341 } else {
2f084d1e 342 *eax |= ((topo_info->threads_per_core - 1) << 14);
8f4202fb
BM		 343 }
344
345 assert(cache->line_size > 0);
346 assert(cache->partitions > 0);
347 assert(cache->associativity > 0);
348 /* We don't implement fully-associative caches */
349 assert(cache->associativity < cache->sets);
350 *ebx = (cache->line_size - 1) |
351 ((cache->partitions - 1) << 12) |
352 ((cache->associativity - 1) << 22);
353
354 assert(cache->sets > 0);
355 *ecx = cache->sets - 1;
356
357 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
358 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
359 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
360}
361
ed78467a 362/* Encode cache info for CPUID[8000001E] */
31ada106
BM		 363static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
364 uint32_t *eax, uint32_t *ebx,
365 uint32_t *ecx, uint32_t *edx)
ed78467a 366{
31ada106
BM		 367 X86CPUTopoIDs topo_ids;
368
369 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
ed78467a 370
ed78467a 371 *eax = cpu->apic_id;
31ada106 372
ed78467a 373 /*
31ada106
BM		 374 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
375 * Read-only. Reset: 0000_XXXXh.
376 * See Core::X86::Cpuid::ExtApicId.
377 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
378 * Bits Description
379 * 31:16 Reserved.
380 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
381 * The number of threads per core is ThreadsPerCore+1.
382 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
383 *
384 * NOTE: CoreId is already part of apic_id. Just use it. We can
385 * use all the 8 bits to represent the core_id here.
ed78467a 386 */
31ada106
BM		 387 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
388
ed78467a 389 /*
31ada106
BM		 390 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
391 * Read-only. Reset: 0000_0XXXh.
392 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
393 * Bits Description
394 * 31:11 Reserved.
395 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
396 * ValidValues:
397 * Value Description
398 * 000b 1 node per processor.
399 * 001b 2 nodes per processor.
400 * 010b Reserved.
401 * 011b 4 nodes per processor.
402 * 111b-100b Reserved.
403 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
404 *
405 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
406 * But users can create more nodes than the actual hardware can
407 * support. To genaralize we can use all the upper 8 bits for nodes.
408 * NodeId is combination of node and socket_id which is already decoded
409 * in apic_id. Just use it by shifting.
ed78467a 410 */
31ada106
BM		 411 *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
412 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
413
ed78467a
BM		 414 *edx = 0;
415}
416
ab8f992e
BM		 417/*
418 * Definitions of the hardcoded cache entries we expose:
419 * These are legacy cache values. If there is a need to change any
420 * of these values please use builtin_x86_defs
421 */
5e891bf8
EH		 422
423/* L1 data cache: */
ab8f992e 424static CPUCacheInfo legacy_l1d_cache = {
5f00335a 425 .type = DATA_CACHE,
7e3482f8
EH		 426 .level = 1,
427 .size = 32 * KiB,
428 .self_init = 1,
429 .line_size = 64,
430 .associativity = 8,
431 .sets = 64,
432 .partitions = 1,
433 .no_invd_sharing = true,
434};
435
5e891bf8 436/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 437static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 438 .type = DATA_CACHE,
7e3482f8
EH		 439 .level = 1,
440 .size = 64 * KiB,
441 .self_init = 1,
442 .line_size = 64,
443 .associativity = 2,
444 .sets = 512,
445 .partitions = 1,
446 .lines_per_tag = 1,
447 .no_invd_sharing = true,
448};
5e891bf8
EH		 449
450/* L1 instruction cache: */
ab8f992e 451static CPUCacheInfo legacy_l1i_cache = {
5f00335a 452 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 453 .level = 1,
454 .size = 32 * KiB,
455 .self_init = 1,
456 .line_size = 64,
457 .associativity = 8,
458 .sets = 64,
459 .partitions = 1,
460 .no_invd_sharing = true,
461};
462
5e891bf8 463/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 464static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 465 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 466 .level = 1,
467 .size = 64 * KiB,
468 .self_init = 1,
469 .line_size = 64,
470 .associativity = 2,
471 .sets = 512,
472 .partitions = 1,
473 .lines_per_tag = 1,
474 .no_invd_sharing = true,
475};
5e891bf8
EH		 476
477/* Level 2 unified cache: */
ab8f992e 478static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 479 .type = UNIFIED_CACHE,
480 .level = 2,
481 .size = 4 * MiB,
482 .self_init = 1,
483 .line_size = 64,
484 .associativity = 16,
485 .sets = 4096,
486 .partitions = 1,
487 .no_invd_sharing = true,
488};
489
5e891bf8 490/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 491static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 492 .type = UNIFIED_CACHE,
493 .level = 2,
494 .size = 2 * MiB,
495 .line_size = 64,
496 .associativity = 8,
497};
498
499
5e891bf8 500/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 501static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 502 .type = UNIFIED_CACHE,
503 .level = 2,
504 .size = 512 * KiB,
505 .line_size = 64,
506 .lines_per_tag = 1,
507 .associativity = 16,
508 .sets = 512,
509 .partitions = 1,
510};
5e891bf8 511
14c985cf 512/* Level 3 unified cache: */
ab8f992e 513static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 514 .type = UNIFIED_CACHE,
515 .level = 3,
516 .size = 16 * MiB,
517 .line_size = 64,
518 .associativity = 16,
519 .sets = 16384,
520 .partitions = 1,
521 .lines_per_tag = 1,
522 .self_init = true,
523 .inclusive = true,
524 .complex_indexing = true,
525};
5e891bf8
EH		 526
527/* TLB definitions: */
528
529#define L1_DTLB_2M_ASSOC 1
530#define L1_DTLB_2M_ENTRIES 255
531#define L1_DTLB_4K_ASSOC 1
532#define L1_DTLB_4K_ENTRIES 255
533
534#define L1_ITLB_2M_ASSOC 1
535#define L1_ITLB_2M_ENTRIES 255
536#define L1_ITLB_4K_ASSOC 1
537#define L1_ITLB_4K_ENTRIES 255
538
539#define L2_DTLB_2M_ASSOC 0 /* disabled */
540#define L2_DTLB_2M_ENTRIES 0 /* disabled */
541#define L2_DTLB_4K_ASSOC 4
542#define L2_DTLB_4K_ENTRIES 512
543
544#define L2_ITLB_2M_ASSOC 0 /* disabled */
545#define L2_ITLB_2M_ENTRIES 0 /* disabled */
546#define L2_ITLB_4K_ASSOC 4
547#define L2_ITLB_4K_ENTRIES 512
548
e37a5c7f
CP		 549/* CPUID Leaf 0x14 constants: */
550#define INTEL_PT_MAX_SUBLEAF 0x1
551/*
552 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
553 * MSR can be accessed;
554 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
555 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
556 * of Intel PT MSRs across warm reset;
557 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
558 */
559#define INTEL_PT_MINIMAL_EBX 0xf
560/*
561 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
562 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
563 * accessed;
564 * bit[01]: ToPA tables can hold any number of output entries, up to the
565 * maximum allowed by the MaskOrTableOffset field of
566 * IA32_RTIT_OUTPUT_MASK_PTRS;
567 * bit[02]: Support Single-Range Output scheme;
568 */
569#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 570/* generated packets which contain IP payloads have LIP values */
571#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 572#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
573#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
574#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
575#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
576#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 577
f21a4817
JL		 578/* CPUID Leaf 0x1D constants: */
579#define INTEL_AMX_TILE_MAX_SUBLEAF 0x1
580#define INTEL_AMX_TOTAL_TILE_BYTES 0x2000
581#define INTEL_AMX_BYTES_PER_TILE 0x400
582#define INTEL_AMX_BYTES_PER_ROW 0x40
583#define INTEL_AMX_TILE_MAX_NAMES 0x8
584#define INTEL_AMX_TILE_MAX_ROWS 0x10
585
586/* CPUID Leaf 0x1E constants: */
587#define INTEL_AMX_TMUL_MAX_K 0x10
588#define INTEL_AMX_TMUL_MAX_N 0x40
589
f5cc5a5c
CF		 590void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
591 uint32_t vendor2, uint32_t vendor3)
99b88a17
IM		 592{
593 int i;
594 for (i = 0; i < 4; i++) {
595 dst[i] = vendor1 >> (8 * i);
596 dst[i + 4] = vendor2 >> (8 * i);
597 dst[i + 8] = vendor3 >> (8 * i);
598 }
599 dst[CPUID_VENDOR_SZ] = '\0';
600}
601
621626ce
EH		 602#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
603#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
604 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
605#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
606 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
607 CPUID_PSE36 | CPUID_FXSR)
608#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
609#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
610 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
611 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
612 CPUID_PAE | CPUID_SEP | CPUID_APIC)
613
614#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
615 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
616 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
617 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 618 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 619 /* partly implemented:
620 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
621 /* missing:
622 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
623#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
624 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
625 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 626 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
369fd5ca
RH		 627 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
628 CPUID_EXT_RDRAND)
621626ce
EH		 629 /* missing:
630 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
631 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
632 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db 633 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
369fd5ca 634 CPUID_EXT_F16C */
621626ce
EH		 635
636#ifdef TARGET_X86_64
637#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
638#else
639#define TCG_EXT2_X86_64_FEATURES 0
640#endif
641
642#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
643 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
644 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
645 TCG_EXT2_X86_64_FEATURES)
646#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
647 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
648#define TCG_EXT4_FEATURES 0
900eeca5
LL		 649#define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \
650 CPUID_SVM_SVME_ADDR_CHK)
621626ce
EH		 651#define TCG_KVM_FEATURES 0
652#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 653 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
654 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 655 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
656 CPUID_7_0_EBX_ERMS)
621626ce 657 /* missing:
07929f2a 658 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 659 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 660 CPUID_7_0_EBX_RDSEED */
637f1ee3 661#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \
9ccb9784 662 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
e7e7bdab 663 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS)
95ea69fb 664#define TCG_7_0_EDX_FEATURES 0
80db491d 665#define TCG_7_1_EAX_FEATURES 0
303752a9 666#define TCG_APM_FEATURES 0
28b8e4d0 667#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 668#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
669 /* missing:
670 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
d1615ea5 671#define TCG_14_0_ECX_FEATURES 0
4b841a79 672#define TCG_SGX_12_0_EAX_FEATURES 0
120ca112 673#define TCG_SGX_12_0_EBX_FEATURES 0
165981a5 674#define TCG_SGX_12_1_EAX_FEATURES 0
621626ce 675
79f1a68a 676FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 677 [FEAT_1_EDX] = {
07585923 678 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 679 .feat_names = {
680 "fpu", "vme", "de", "pse",
681 "tsc", "msr", "pae", "mce",
682 "cx8", "apic", NULL, "sep",
683 "mtrr", "pge", "mca", "cmov",
684 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
685 NULL, "ds" /* Intel dts */, "acpi", "mmx",
686 "fxsr", "sse", "sse2", "ss",
687 "ht" /* Intel htt */, "tm", "ia64", "pbe",
688 },
07585923 689 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 690 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 691 },
692 [FEAT_1_ECX] = {
07585923 693 .type = CPUID_FEATURE_WORD,
2d5312da 694 .feat_names = {
16d2fcaa 695 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 696 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 697 "tm2", "ssse3", "cid", NULL,
698 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 699 NULL, "pcid", "dca", "sse4.1",
700 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 701 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 702 "avx", "f16c", "rdrand", "hypervisor",
703 },
07585923 704 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 705 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 706 },
2d5312da
EH		 707 /* Feature names that are already defined on feature_name[] but
708 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
709 * names on feat_names below. They are copied automatically
710 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
711 */
bffd67b0 712 [FEAT_8000_0001_EDX] = {
07585923 713 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 714 .feat_names = {
715 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
716 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
717 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
718 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
719 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 720 "nx", NULL, "mmxext", NULL /* mmx */,
721 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
722 NULL, "lm", "3dnowext", "3dnow",
2d5312da 723 },
07585923 724 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 725 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 726 },
727 [FEAT_8000_0001_ECX] = {
07585923 728 .type = CPUID_FEATURE_WORD,
2d5312da 729 .feat_names = {
fc7dfd20 730 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 731 "cr8legacy", "abm", "sse4a", "misalignsse",
732 "3dnowprefetch", "osvw", "ibs", "xop",
733 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 734 "fma4", "tce", NULL, "nodeid-msr",
735 NULL, "tbm", "topoext", "perfctr-core",
736 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 737 NULL, NULL, NULL, NULL,
738 },
07585923 739 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 740 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 741 /*
742 * TOPOEXT is always allowed but can't be enabled blindly by
743 * "-cpu host", as it requires consistent cache topology info
744 * to be provided so it doesn't confuse guests.
745 */
746 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 747 },
89e49c8b 748 [FEAT_C000_0001_EDX] = {
07585923 749 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 750 .feat_names = {
751 NULL, NULL, "xstore", "xstore-en",
752 NULL, NULL, "xcrypt", "xcrypt-en",
753 "ace2", "ace2-en", "phe", "phe-en",
754 "pmm", "pmm-en", NULL, NULL,
755 NULL, NULL, NULL, NULL,
756 NULL, NULL, NULL, NULL,
757 NULL, NULL, NULL, NULL,
758 NULL, NULL, NULL, NULL,
759 },
07585923 760 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 761 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 762 },
bffd67b0 763 [FEAT_KVM] = {
07585923 764 .type = CPUID_FEATURE_WORD,
2d5312da 765 .feat_names = {
fc7dfd20
EH		 766 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
767 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 768 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
c1bb5418 769 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
2d5312da
EH		 770 NULL, NULL, NULL, NULL,
771 NULL, NULL, NULL, NULL,
772 "kvmclock-stable-bit", NULL, NULL, NULL,
773 NULL, NULL, NULL, NULL,
774 },
07585923 775 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 776 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 777 },
be777326 778 [FEAT_KVM_HINTS] = {
07585923 779 .type = CPUID_FEATURE_WORD,
be777326
WL		 780 .feat_names = {
781 "kvm-hint-dedicated", NULL, NULL, NULL,
782 NULL, NULL, NULL, NULL,
783 NULL, NULL, NULL, NULL,
784 NULL, NULL, NULL, NULL,
785 NULL, NULL, NULL, NULL,
786 NULL, NULL, NULL, NULL,
787 NULL, NULL, NULL, NULL,
788 NULL, NULL, NULL, NULL,
789 },
07585923 790 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 791 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 792 /*
793 * KVM hints aren't auto-enabled by -cpu host, they need to be
794 * explicitly enabled in the command-line.
795 */
796 .no_autoenable_flags = ~0U,
be777326 797 },
bffd67b0 798 [FEAT_SVM] = {
07585923 799 .type = CPUID_FEATURE_WORD,
2d5312da 800 .feat_names = {
fc7dfd20
EH		 801 "npt", "lbrv", "svm-lock", "nrip-save",
802 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
803 NULL, NULL, "pause-filter", NULL,
5447089c
WH		 804 "pfthreshold", "avic", NULL, "v-vmsave-vmload",
805 "vgif", NULL, NULL, NULL,
2d5312da
EH		 806 NULL, NULL, NULL, NULL,
807 NULL, NULL, NULL, NULL,
5447089c 808 "svme-addr-chk", NULL, NULL, NULL,
2d5312da 809 },
07585923 810 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 811 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 812 },
813 [FEAT_7_0_EBX] = {
07585923 814 .type = CPUID_FEATURE_WORD,
2d5312da 815 .feat_names = {
5c76b651 816 "fsgsbase", "tsc-adjust", "sgx", "bmi1",
2d5312da
EH		 817 "hle", "avx2", NULL, "smep",
818 "bmi2", "erms", "invpcid", "rtm",
819 NULL, NULL, "mpx", NULL,
820 "avx512f", "avx512dq", "rdseed", "adx",
821 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 822 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 823 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 824 },
07585923
RH		 825 .cpuid = {
826 .eax = 7,
827 .needs_ecx = true, .ecx = 0,
828 .reg = R_EBX,
829 },
37ce3522 830 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 831 },
f74eefe0 832 [FEAT_7_0_ECX] = {
07585923 833 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 834 .feat_names = {
835 NULL, "avx512vbmi", "umip", "pku",
67192a29 836 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
aff9e6e4
YZ		 837 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
838 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 839 "la57", NULL, NULL, NULL,
2d5312da 840 NULL, NULL, "rdpid", NULL,
06e878b4 841 "bus-lock-detect", "cldemote", NULL, "movdiri",
5c76b651 842 "movdir64b", NULL, "sgxlc", "pks",
2d5312da 843 },
07585923
RH		 844 .cpuid = {
845 .eax = 7,
846 .needs_ecx = true, .ecx = 0,
847 .reg = R_ECX,
848 },
f74eefe0
HH		 849 .tcg_features = TCG_7_0_ECX_FEATURES,
850 },
95ea69fb 851 [FEAT_7_0_EDX] = {
07585923 852 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 853 .feat_names = {
854 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
5cb287d2 855 "fsrm", NULL, NULL, NULL,
353f98c9 856 "avx512-vp2intersect", NULL, "md-clear", NULL,
5dd13f2a 857 NULL, NULL, "serialize", NULL,
b3c7344e 858 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
f21a4817
JL		 859 NULL, NULL, "amx-bf16", "avx512-fp16",
860 "amx-tile", "amx-int8", "spec-ctrl", "stibp",
597360c0 861 NULL, "arch-capabilities", "core-capability", "ssbd",
95ea69fb 862 },
07585923
RH		 863 .cpuid = {
864 .eax = 7,
865 .needs_ecx = true, .ecx = 0,
866 .reg = R_EDX,
867 },
95ea69fb
LK		 868 .tcg_features = TCG_7_0_EDX_FEATURES,
869 },
80db491d
JL		 870 [FEAT_7_1_EAX] = {
871 .type = CPUID_FEATURE_WORD,
872 .feat_names = {
873 NULL, NULL, NULL, NULL,
c1826ea6 874 "avx-vnni", "avx512-bf16", NULL, NULL,
80db491d
JL		 875 NULL, NULL, NULL, NULL,
876 NULL, NULL, NULL, NULL,
877 NULL, NULL, NULL, NULL,
878 NULL, NULL, NULL, NULL,
879 NULL, NULL, NULL, NULL,
880 NULL, NULL, NULL, NULL,
881 },
882 .cpuid = {
883 .eax = 7,
884 .needs_ecx = true, .ecx = 1,
885 .reg = R_EAX,
886 },
887 .tcg_features = TCG_7_1_EAX_FEATURES,
888 },
303752a9 889 [FEAT_8000_0007_EDX] = {
07585923 890 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 891 .feat_names = {
892 NULL, NULL, NULL, NULL,
893 NULL, NULL, NULL, NULL,
894 "invtsc", NULL, NULL, NULL,
895 NULL, NULL, NULL, NULL,
896 NULL, NULL, NULL, NULL,
897 NULL, NULL, NULL, NULL,
898 NULL, NULL, NULL, NULL,
899 NULL, NULL, NULL, NULL,
900 },
07585923 901 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 902 .tcg_features = TCG_APM_FEATURES,
903 .unmigratable_flags = CPUID_APM_INVTSC,
904 },
1b3420e1 905 [FEAT_8000_0008_EBX] = {
07585923 906 .type = CPUID_FEATURE_WORD,
1b3420e1 907 .feat_names = {
e900135d 908 "clzero", NULL, "xsaveerptr", NULL,
1b3420e1 909 NULL, NULL, NULL, NULL,
59a80a19 910 NULL, "wbnoinvd", NULL, NULL,
623972ce 911 "ibpb", NULL, "ibrs", "amd-stibp",
1b3420e1
EH		 912 NULL, NULL, NULL, NULL,
913 NULL, NULL, NULL, NULL,
254790a9 914 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 915 NULL, NULL, NULL, NULL,
916 },
07585923 917 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 918 .tcg_features = 0,
919 .unmigratable_flags = 0,
920 },
0bb0b2d2 921 [FEAT_XSAVE] = {
07585923 922 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 923 .feat_names = {
924 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
f21a4817 925 "xfd", NULL, NULL, NULL,
2d5312da
EH		 926 NULL, NULL, NULL, NULL,
927 NULL, NULL, NULL, NULL,
928 NULL, NULL, NULL, NULL,
929 NULL, NULL, NULL, NULL,
930 NULL, NULL, NULL, NULL,
931 NULL, NULL, NULL, NULL,
932 },
07585923
RH		 933 .cpuid = {
934 .eax = 0xd,
935 .needs_ecx = true, .ecx = 1,
936 .reg = R_EAX,
937 },
c9cfe8f9 938 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 939 },
28b8e4d0 940 [FEAT_6_EAX] = {
07585923 941 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 942 .feat_names = {
943 NULL, NULL, "arat", NULL,
944 NULL, NULL, NULL, NULL,
945 NULL, NULL, NULL, NULL,
946 NULL, NULL, NULL, NULL,
947 NULL, NULL, NULL, NULL,
948 NULL, NULL, NULL, NULL,
949 NULL, NULL, NULL, NULL,
950 NULL, NULL, NULL, NULL,
951 },
07585923 952 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 953 .tcg_features = TCG_6_EAX_FEATURES,
954 },
96193c22 955 [FEAT_XSAVE_COMP_LO] = {
07585923
RH		 956 .type = CPUID_FEATURE_WORD,
957 .cpuid = {
958 .eax = 0xD,
959 .needs_ecx = true, .ecx = 0,
960 .reg = R_EAX,
961 },
96193c22 962 .tcg_features = ~0U,
6fb2fff7
EH		 963 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
964 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
965 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
966 XSTATE_PKRU_MASK,
96193c22
EH		 967 },
968 [FEAT_XSAVE_COMP_HI] = {
07585923
RH		 969 .type = CPUID_FEATURE_WORD,
970 .cpuid = {
971 .eax = 0xD,
972 .needs_ecx = true, .ecx = 0,
973 .reg = R_EDX,
974 },
96193c22
EH		 975 .tcg_features = ~0U,
976 },
d86f9636
RH		 977 /*Below are MSR exposed features*/
978 [FEAT_ARCH_CAPABILITIES] = {
979 .type = MSR_FEATURE_WORD,
980 .feat_names = {
981 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
2a9758c5 982 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
7fac3863 983 "taa-no", NULL, NULL, NULL,
d86f9636
RH		 984 NULL, NULL, NULL, NULL,
985 NULL, NULL, NULL, NULL,
986 NULL, NULL, NULL, NULL,
987 NULL, NULL, NULL, NULL,
988 NULL, NULL, NULL, NULL,
989 },
990 .msr = {
991 .index = MSR_IA32_ARCH_CAPABILITIES,
d86f9636
RH		 992 },
993 },
597360c0
XL		 994 [FEAT_CORE_CAPABILITY] = {
995 .type = MSR_FEATURE_WORD,
996 .feat_names = {
997 NULL, NULL, NULL, NULL,
998 NULL, "split-lock-detect", NULL, NULL,
999 NULL, NULL, NULL, NULL,
1000 NULL, NULL, NULL, NULL,
1001 NULL, NULL, NULL, NULL,
1002 NULL, NULL, NULL, NULL,
1003 NULL, NULL, NULL, NULL,
1004 NULL, NULL, NULL, NULL,
1005 },
1006 .msr = {
1007 .index = MSR_IA32_CORE_CAPABILITY,
597360c0
XL		 1008 },
1009 },
ea39f9b6
LX		 1010 [FEAT_PERF_CAPABILITIES] = {
1011 .type = MSR_FEATURE_WORD,
1012 .feat_names = {
1013 NULL, NULL, NULL, NULL,
1014 NULL, NULL, NULL, NULL,
1015 NULL, NULL, NULL, NULL,
1016 NULL, "full-width-write", NULL, NULL,
1017 NULL, NULL, NULL, NULL,
1018 NULL, NULL, NULL, NULL,
1019 NULL, NULL, NULL, NULL,
1020 NULL, NULL, NULL, NULL,
1021 },
1022 .msr = {
1023 .index = MSR_IA32_PERF_CAPABILITIES,
1024 },
1025 },
20a78b02
PB		 1026
1027 [FEAT_VMX_PROCBASED_CTLS] = {
1028 .type = MSR_FEATURE_WORD,
1029 .feat_names = {
1030 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1031 NULL, NULL, NULL, "vmx-hlt-exit",
1032 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1033 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1034 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1035 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1036 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1037 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1038 },
1039 .msr = {
1040 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1041 }
1042 },
1043
1044 [FEAT_VMX_SECONDARY_CTLS] = {
1045 .type = MSR_FEATURE_WORD,
1046 .feat_names = {
1047 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1048 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1049 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1050 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1051 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1052 "vmx-xsaves", NULL, NULL, NULL,
9ce8af4d 1053 NULL, "vmx-tsc-scaling", NULL, NULL,
20a78b02
PB		 1054 NULL, NULL, NULL, NULL,
1055 },
1056 .msr = {
1057 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1058 }
1059 },
1060
1061 [FEAT_VMX_PINBASED_CTLS] = {
1062 .type = MSR_FEATURE_WORD,
1063 .feat_names = {
1064 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1065 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1066 NULL, NULL, NULL, NULL,
1067 NULL, NULL, NULL, NULL,
1068 NULL, NULL, NULL, NULL,
1069 NULL, NULL, NULL, NULL,
1070 NULL, NULL, NULL, NULL,
1071 NULL, NULL, NULL, NULL,
1072 },
1073 .msr = {
1074 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1075 }
1076 },
1077
1078 [FEAT_VMX_EXIT_CTLS] = {
1079 .type = MSR_FEATURE_WORD,
1080 /*
1081 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1082 * the LM CPUID bit.
1083 */
1084 .feat_names = {
1085 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1086 NULL, NULL, NULL, NULL,
1087 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1088 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1089 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1090 "vmx-exit-save-efer", "vmx-exit-load-efer",
1091 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1092 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
52a44ad2 1093 NULL, "vmx-exit-load-pkrs", NULL, NULL,
20a78b02
PB		 1094 },
1095 .msr = {
1096 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1097 }
1098 },
1099
1100 [FEAT_VMX_ENTRY_CTLS] = {
1101 .type = MSR_FEATURE_WORD,
1102 .feat_names = {
1103 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1104 NULL, NULL, NULL, NULL,
1105 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1106 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1107 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
52a44ad2 1108 NULL, NULL, "vmx-entry-load-pkrs", NULL,
20a78b02
PB		 1109 NULL, NULL, NULL, NULL,
1110 NULL, NULL, NULL, NULL,
1111 },
1112 .msr = {
1113 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1114 }
1115 },
1116
1117 [FEAT_VMX_MISC] = {
1118 .type = MSR_FEATURE_WORD,
1119 .feat_names = {
1120 NULL, NULL, NULL, NULL,
1121 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1122 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1123 NULL, NULL, NULL, NULL,
1124 NULL, NULL, NULL, NULL,
1125 NULL, NULL, NULL, NULL,
1126 NULL, NULL, NULL, NULL,
1127 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1128 },
1129 .msr = {
1130 .index = MSR_IA32_VMX_MISC,
1131 }
1132 },
1133
1134 [FEAT_VMX_EPT_VPID_CAPS] = {
1135 .type = MSR_FEATURE_WORD,
1136 .feat_names = {
1137 "vmx-ept-execonly", NULL, NULL, NULL,
1138 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1139 NULL, NULL, NULL, NULL,
1140 NULL, NULL, NULL, NULL,
1141 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1142 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1143 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1144 NULL, NULL, NULL, NULL,
1145 "vmx-invvpid", NULL, NULL, NULL,
1146 NULL, NULL, NULL, NULL,
1147 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1148 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1149 NULL, NULL, NULL, NULL,
1150 NULL, NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 },
1155 .msr = {
1156 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1157 }
1158 },
1159
1160 [FEAT_VMX_BASIC] = {
1161 .type = MSR_FEATURE_WORD,
1162 .feat_names = {
1163 [54] = "vmx-ins-outs",
1164 [55] = "vmx-true-ctls",
1165 },
1166 .msr = {
1167 .index = MSR_IA32_VMX_BASIC,
1168 },
1169 /* Just to be safe - we don't support setting the MSEG version field. */
1170 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1171 },
1172
1173 [FEAT_VMX_VMFUNC] = {
1174 .type = MSR_FEATURE_WORD,
1175 .feat_names = {
1176 [0] = "vmx-eptp-switching",
1177 },
1178 .msr = {
1179 .index = MSR_IA32_VMX_VMFUNC,
1180 }
1181 },
1182
d1615ea5
LK		 1183 [FEAT_14_0_ECX] = {
1184 .type = CPUID_FEATURE_WORD,
1185 .feat_names = {
1186 NULL, NULL, NULL, NULL,
1187 NULL, NULL, NULL, NULL,
1188 NULL, NULL, NULL, NULL,
1189 NULL, NULL, NULL, NULL,
1190 NULL, NULL, NULL, NULL,
1191 NULL, NULL, NULL, NULL,
1192 NULL, NULL, NULL, NULL,
1193 NULL, NULL, NULL, "intel-pt-lip",
1194 },
1195 .cpuid = {
1196 .eax = 0x14,
1197 .needs_ecx = true, .ecx = 0,
1198 .reg = R_ECX,
1199 },
1200 .tcg_features = TCG_14_0_ECX_FEATURES,
1201 },
1202
4b841a79
SC		 1203 [FEAT_SGX_12_0_EAX] = {
1204 .type = CPUID_FEATURE_WORD,
1205 .feat_names = {
1206 "sgx1", "sgx2", NULL, NULL,
1207 NULL, NULL, NULL, NULL,
1208 NULL, NULL, NULL, NULL,
1209 NULL, NULL, NULL, NULL,
1210 NULL, NULL, NULL, NULL,
1211 NULL, NULL, NULL, NULL,
1212 NULL, NULL, NULL, NULL,
1213 NULL, NULL, NULL, NULL,
1214 },
1215 .cpuid = {
1216 .eax = 0x12,
1217 .needs_ecx = true, .ecx = 0,
1218 .reg = R_EAX,
1219 },
1220 .tcg_features = TCG_SGX_12_0_EAX_FEATURES,
1221 },
120ca112
SC		 1222
1223 [FEAT_SGX_12_0_EBX] = {
1224 .type = CPUID_FEATURE_WORD,
1225 .feat_names = {
1226 "sgx-exinfo" , NULL, NULL, NULL,
1227 NULL, NULL, NULL, NULL,
1228 NULL, NULL, NULL, NULL,
1229 NULL, NULL, NULL, NULL,
1230 NULL, NULL, NULL, NULL,
1231 NULL, NULL, NULL, NULL,
1232 NULL, NULL, NULL, NULL,
1233 NULL, NULL, NULL, NULL,
1234 },
1235 .cpuid = {
1236 .eax = 0x12,
1237 .needs_ecx = true, .ecx = 0,
1238 .reg = R_EBX,
1239 },
1240 .tcg_features = TCG_SGX_12_0_EBX_FEATURES,
1241 },
165981a5
SC		 1242
1243 [FEAT_SGX_12_1_EAX] = {
1244 .type = CPUID_FEATURE_WORD,
1245 .feat_names = {
1246 NULL, "sgx-debug", "sgx-mode64", NULL,
1247 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
1248 NULL, NULL, NULL, NULL,
1249 NULL, NULL, NULL, NULL,
1250 NULL, NULL, NULL, NULL,
1251 NULL, NULL, NULL, NULL,
1252 NULL, NULL, NULL, NULL,
1253 NULL, NULL, NULL, NULL,
1254 },
1255 .cpuid = {
1256 .eax = 0x12,
1257 .needs_ecx = true, .ecx = 1,
1258 .reg = R_EAX,
1259 },
1260 .tcg_features = TCG_SGX_12_1_EAX_FEATURES,
1261 },
5ef57876
EH		 1262};
1263
99e24dbd
PB		 1264typedef struct FeatureMask {
1265 FeatureWord index;
ede146c2 1266 uint64_t mask;
99e24dbd
PB		 1267} FeatureMask;
1268
1269typedef struct FeatureDep {
1270 FeatureMask from, to;
1271} FeatureDep;
1272
1273static FeatureDep feature_dependencies[] = {
1274 {
1275 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
ede146c2 1276 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
99e24dbd
PB		 1277 },
1278 {
1279 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
ede146c2 1280 .to = { FEAT_CORE_CAPABILITY, ~0ull },
99e24dbd 1281 },
ea39f9b6
LX		 1282 {
1283 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1284 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1285 },
20a78b02
PB		 1286 {
1287 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1288 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1289 },
1290 {
1291 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1292 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1293 },
1294 {
1295 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1296 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1297 },
1298 {
1299 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1300 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1301 },
1302 {
1303 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1304 .to = { FEAT_VMX_MISC, ~0ull },
1305 },
1306 {
1307 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1308 .to = { FEAT_VMX_BASIC, ~0ull },
1309 },
1310 {
1311 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1312 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1313 },
1314 {
1315 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1316 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1317 },
1318 {
1319 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1320 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1321 },
1322 {
1323 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1324 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1325 },
1326 {
1327 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1328 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1329 },
1330 {
1331 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1332 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1333 },
d1615ea5
LK		 1334 {
1335 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT },
1336 .to = { FEAT_14_0_ECX, ~0ull },
1337 },
20a78b02
PB		 1338 {
1339 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1340 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1341 },
1342 {
1343 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1344 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1345 },
1346 {
1347 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1348 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1349 },
1350 {
1351 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1352 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1353 },
1354 {
1355 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1356 .to = { FEAT_VMX_VMFUNC, ~0ull },
1357 },
730319ae
EH		 1358 {
1359 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1360 .to = { FEAT_SVM, ~0ull },
1361 },
99e24dbd
PB		 1362};
1363
8e8aba50
EH		 1364typedef struct X86RegisterInfo32 {
1365 /* Name of register */
1366 const char *name;
1367 /* QAPI enum value register */
1368 X86CPURegister32 qapi_enum;
1369} X86RegisterInfo32;
1370
1371#define REGISTER(reg) \
5d371f41 1372 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1373static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1374 REGISTER(EAX),
1375 REGISTER(ECX),
1376 REGISTER(EDX),
1377 REGISTER(EBX),
1378 REGISTER(ESP),
1379 REGISTER(EBP),
1380 REGISTER(ESI),
1381 REGISTER(EDI),
1382};
1383#undef REGISTER
1384
fea45008 1385ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
e3c9022b
EH		 1386 [XSTATE_FP_BIT] = {
1387 /* x87 FP state component is always enabled if XSAVE is supported */
1388 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
e3c9022b
EH		 1389 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1390 },
1391 [XSTATE_SSE_BIT] = {
1392 /* SSE state component is always enabled if XSAVE is supported */
1393 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
e3c9022b
EH		 1394 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1395 },
cfc3b074
PB		 1396 [XSTATE_YMM_BIT] =
1397 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6 1398 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1399 [XSTATE_BNDREGS_BIT] =
1400 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6 1401 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1402 [XSTATE_BNDCSR_BIT] =
1403 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6 1404 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1405 [XSTATE_OPMASK_BIT] =
1406 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1407 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1408 [XSTATE_ZMM_Hi256_BIT] =
1409 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1410 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1411 [XSTATE_Hi16_ZMM_BIT] =
1412 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1413 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1414 [XSTATE_PKRU_BIT] =
1415 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6 1416 .size = sizeof(XSavePKRU) },
1f16764f
JL		 1417 [XSTATE_XTILE_CFG_BIT] = {
1418 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
1419 .size = sizeof(XSaveXTILECFG),
1420 },
1421 [XSTATE_XTILE_DATA_BIT] = {
1422 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
1423 .size = sizeof(XSaveXTILEDATA)
1424 },
2560f19f 1425};
8e8aba50 1426
1fda6198
EH		 1427static uint32_t xsave_area_size(uint64_t mask)
1428{
1429 int i;
e3c9022b 1430 uint64_t ret = 0;
1fda6198 1431
e3c9022b 1432 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1433 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1434 if ((mask >> i) & 1) {
1435 ret = MAX(ret, esa->offset + esa->size);
1436 }
1437 }
1438 return ret;
1439}
1440
d6dcc558
SAGDR		 1441static inline bool accel_uses_host_cpuid(void)
1442{
1443 return kvm_enabled() || hvf_enabled();
1444}
1445
96193c22
EH		 1446static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1447{
1448 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1449 cpu->env.features[FEAT_XSAVE_COMP_LO];
1450}
1451
ed69e831
CF		 1452/* Return name of 32-bit register, from a R_* constant */
1453static const char *get_register_name_32(unsigned int reg)
8b4beddc 1454{
31ccdde2 1455 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1456 return NULL;
1457 }
8e8aba50 1458 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1459}
1460
84f1b92f
EH		 1461/*
1462 * Returns the set of feature flags that are supported and migratable by
1463 * QEMU, for a given FeatureWord.
1464 */
ede146c2 1465static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
84f1b92f
EH		 1466{
1467 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 1468 uint64_t r = 0;
84f1b92f
EH		 1469 int i;
1470
ede146c2
PB		 1471 for (i = 0; i < 64; i++) {
1472 uint64_t f = 1ULL << i;
6fb2fff7
EH		 1473
1474 /* If the feature name is known, it is implicitly considered migratable,
1475 * unless it is explicitly set in unmigratable_flags */
1476 if ((wi->migratable_flags & f) ||
1477 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1478 r |= f;
84f1b92f 1479 }
84f1b92f
EH		 1480 }
1481 return r;
1482}
1483
bb44e0d1
JK		 1484void host_cpuid(uint32_t function, uint32_t count,
1485 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1486{
a1fd24af
AL		 1487 uint32_t vec[4];
1488
1489#ifdef __x86_64__
1490 asm volatile("cpuid"
1491 : "=a"(vec[0]), "=b"(vec[1]),
1492 "=c"(vec[2]), "=d"(vec[3])
1493 : "0"(function), "c"(count) : "cc");
c1f41226 1494#elif defined(__i386__)
a1fd24af
AL		 1495 asm volatile("pusha \n\t"
1496 "cpuid \n\t"
1497 "mov %%eax, 0(%2) \n\t"
1498 "mov %%ebx, 4(%2) \n\t"
1499 "mov %%ecx, 8(%2) \n\t"
1500 "mov %%edx, 12(%2) \n\t"
1501 "popa"
1502 : : "a"(function), "c"(count), "S"(vec)
1503 : "memory", "cc");
c1f41226
EH		 1504#else
1505 abort();
a1fd24af
AL		 1506#endif
1507
bdde476a 1508 if (eax)
a1fd24af 1509 *eax = vec[0];
bdde476a 1510 if (ebx)
a1fd24af 1511 *ebx = vec[1];
bdde476a 1512 if (ecx)
a1fd24af 1513 *ecx = vec[2];
bdde476a 1514 if (edx)
a1fd24af 1515 *edx = vec[3];
bdde476a 1516}
c6dc6f63 1517
d940ee9b
EH		 1518/* CPU class name definitions: */
1519
d940ee9b
EH		 1520/* Return type name for a given CPU model name
1521 * Caller is responsible for freeing the returned string.
1522 */
1523static char *x86_cpu_type_name(const char *model_name)
1524{
1525 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1526}
1527
500050d1
AF		 1528static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1529{
88703ce2
EH		 1530 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1531 return object_class_by_name(typename);
500050d1
AF		 1532}
1533
104494ea
IM		 1534static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1535{
1536 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1537 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1538 return g_strndup(class_name,
1539 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1540}
1541
dcafd1ef
EH		 1542typedef struct X86CPUVersionDefinition {
1543 X86CPUVersion version;
53db89d9 1544 const char *alias;
c63938df 1545 const char *note;
dcafd1ef
EH		 1546 PropValue *props;
1547} X86CPUVersionDefinition;
1548
1549/* Base definition for a CPU model */
1550typedef struct X86CPUDefinition {
c6dc6f63
AP		 1551 const char *name;
1552 uint32_t level;
90e4b0c3 1553 uint32_t xlevel;
99b88a17
IM		 1554 /* vendor is zero-terminated, 12 character ASCII string */
1555 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1556 int family;
1557 int model;
1558 int stepping;
0514ef2f 1559 FeatureWordArray features;
807e9869 1560 const char *model_id;
e845de38 1561 const CPUCaches *const cache_info;
dcafd1ef
EH		 1562 /*
1563 * Definitions for alternative versions of CPU model.
1564 * List is terminated by item with version == 0.
1565 * If NULL, version 1 will be registered automatically.
1566 */
1567 const X86CPUVersionDefinition *versions;
61ad65d0 1568 const char *deprecation_note;
dcafd1ef
EH		 1569} X86CPUDefinition;
1570
1571/* Reference to a specific CPU model version */
1572struct X86CPUModel {
1573 /* Base CPU definition */
e11fd689 1574 const X86CPUDefinition *cpudef;
dcafd1ef
EH		 1575 /* CPU model version */
1576 X86CPUVersion version;
c63938df 1577 const char *note;
0788a56b
EH		 1578 /*
1579 * If true, this is an alias CPU model.
1580 * This matters only for "-cpu help" and query-cpu-definitions
1581 */
1582 bool is_alias;
d940ee9b 1583};
c6dc6f63 1584
dcafd1ef 1585/* Get full model name for CPU version */
e11fd689 1586static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef,
dcafd1ef
EH		 1587 X86CPUVersion version)
1588{
1589 assert(version > 0);
1590 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1591}
1592
e11fd689
PMD		 1593static const X86CPUVersionDefinition *
1594x86_cpu_def_get_versions(const X86CPUDefinition *def)
dcafd1ef
EH		 1595{
1596 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1597 static const X86CPUVersionDefinition default_version_list[] = {
1598 { 1 },
1599 { /* end of list */ }
1600 };
1601
1602 return def->versions ?: default_version_list;
1603}
1604
e845de38 1605static const CPUCaches epyc_cache_info = {
a9f27ea9 1606 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1607 .type = DATA_CACHE,
fe52acd2
BM		 1608 .level = 1,
1609 .size = 32 * KiB,
1610 .line_size = 64,
1611 .associativity = 8,
1612 .partitions = 1,
1613 .sets = 64,
1614 .lines_per_tag = 1,
1615 .self_init = 1,
1616 .no_invd_sharing = true,
1617 },
a9f27ea9 1618 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1619 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1620 .level = 1,
1621 .size = 64 * KiB,
1622 .line_size = 64,
1623 .associativity = 4,
1624 .partitions = 1,
1625 .sets = 256,
1626 .lines_per_tag = 1,
1627 .self_init = 1,
1628 .no_invd_sharing = true,
1629 },
a9f27ea9 1630 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1631 .type = UNIFIED_CACHE,
1632 .level = 2,
1633 .size = 512 * KiB,
1634 .line_size = 64,
1635 .associativity = 8,
1636 .partitions = 1,
1637 .sets = 1024,
1638 .lines_per_tag = 1,
1639 },
a9f27ea9 1640 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1641 .type = UNIFIED_CACHE,
1642 .level = 3,
1643 .size = 8 * MiB,
1644 .line_size = 64,
1645 .associativity = 16,
1646 .partitions = 1,
1647 .sets = 8192,
1648 .lines_per_tag = 1,
1649 .self_init = true,
1650 .inclusive = true,
1651 .complex_indexing = true,
1652 },
1653};
1654
e845de38 1655static const CPUCaches epyc_rome_cache_info = {
143c30d4
MB		 1656 .l1d_cache = &(CPUCacheInfo) {
1657 .type = DATA_CACHE,
1658 .level = 1,
1659 .size = 32 * KiB,
1660 .line_size = 64,
1661 .associativity = 8,
1662 .partitions = 1,
1663 .sets = 64,
1664 .lines_per_tag = 1,
1665 .self_init = 1,
1666 .no_invd_sharing = true,
1667 },
1668 .l1i_cache = &(CPUCacheInfo) {
1669 .type = INSTRUCTION_CACHE,
1670 .level = 1,
1671 .size = 32 * KiB,
1672 .line_size = 64,
1673 .associativity = 8,
1674 .partitions = 1,
1675 .sets = 64,
1676 .lines_per_tag = 1,
1677 .self_init = 1,
1678 .no_invd_sharing = true,
1679 },
1680 .l2_cache = &(CPUCacheInfo) {
1681 .type = UNIFIED_CACHE,
1682 .level = 2,
1683 .size = 512 * KiB,
1684 .line_size = 64,
1685 .associativity = 8,
1686 .partitions = 1,
1687 .sets = 1024,
1688 .lines_per_tag = 1,
1689 },
1690 .l3_cache = &(CPUCacheInfo) {
1691 .type = UNIFIED_CACHE,
1692 .level = 3,
1693 .size = 16 * MiB,
1694 .line_size = 64,
1695 .associativity = 16,
1696 .partitions = 1,
1697 .sets = 16384,
1698 .lines_per_tag = 1,
1699 .self_init = true,
1700 .inclusive = true,
1701 .complex_indexing = true,
1702 },
1703};
1704
e845de38 1705static const CPUCaches epyc_milan_cache_info = {
623972ce
BM		 1706 .l1d_cache = &(CPUCacheInfo) {
1707 .type = DATA_CACHE,
1708 .level = 1,
1709 .size = 32 * KiB,
1710 .line_size = 64,
1711 .associativity = 8,
1712 .partitions = 1,
1713 .sets = 64,
1714 .lines_per_tag = 1,
1715 .self_init = 1,
1716 .no_invd_sharing = true,
1717 },
1718 .l1i_cache = &(CPUCacheInfo) {
1719 .type = INSTRUCTION_CACHE,
1720 .level = 1,
1721 .size = 32 * KiB,
1722 .line_size = 64,
1723 .associativity = 8,
1724 .partitions = 1,
1725 .sets = 64,
1726 .lines_per_tag = 1,
1727 .self_init = 1,
1728 .no_invd_sharing = true,
1729 },
1730 .l2_cache = &(CPUCacheInfo) {
1731 .type = UNIFIED_CACHE,
1732 .level = 2,
1733 .size = 512 * KiB,
1734 .line_size = 64,
1735 .associativity = 8,
1736 .partitions = 1,
1737 .sets = 1024,
1738 .lines_per_tag = 1,
1739 },
1740 .l3_cache = &(CPUCacheInfo) {
1741 .type = UNIFIED_CACHE,
1742 .level = 3,
1743 .size = 32 * MiB,
1744 .line_size = 64,
1745 .associativity = 16,
1746 .partitions = 1,
1747 .sets = 32768,
1748 .lines_per_tag = 1,
1749 .self_init = true,
1750 .inclusive = true,
1751 .complex_indexing = true,
1752 },
1753};
1754
0723cc8a
PB		 1755/* The following VMX features are not supported by KVM and are left out in the
1756 * CPU definitions:
1757 *
1758 * Dual-monitor support (all processors)
1759 * Entry to SMM
1760 * Deactivate dual-monitor treatment
1761 * Number of CR3-target values
1762 * Shutdown activity state
1763 * Wait-for-SIPI activity state
1764 * PAUSE-loop exiting (Westmere and newer)
1765 * EPT-violation #VE (Broadwell and newer)
1766 * Inject event with insn length=0 (Skylake and newer)
1767 * Conceal non-root operation from PT
1768 * Conceal VM exits from PT
1769 * Conceal VM entries from PT
1770 * Enable ENCLS exiting
1771 * Mode-based execute control (XS/XU)
1772 s TSC scaling (Skylake Server and newer)
1773 * GPA translation for PT (IceLake and newer)
1774 * User wait and pause
1775 * ENCLV exiting
1776 * Load IA32_RTIT_CTL
1777 * Clear IA32_RTIT_CTL
1778 * Advanced VM-exit information for EPT violations
1779 * Sub-page write permissions
1780 * PT in VMX operation
1781 */
1782
e11fd689 1783static const X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1784 {
1785 .name = "qemu64",
3046bb5d 1786 .level = 0xd,
99b88a17 1787 .vendor = CPUID_VENDOR_AMD,
b7c29017
DB		 1788 .family = 15,
1789 .model = 107,
1790 .stepping = 1,
0514ef2f 1791 .features[FEAT_1_EDX] =
27861ecc 1792 PPRO_FEATURES |
c6dc6f63 1793 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1794 CPUID_PSE36,
0514ef2f 1795 .features[FEAT_1_ECX] =
6aa91e4a 1796 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1797 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1798 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1799 .features[FEAT_8000_0001_ECX] =
71195672 1800 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1801 .xlevel = 0x8000000A,
9cf2cc3d 1802 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1803 },
1804 {
1805 .name = "phenom",
1806 .level = 5,
99b88a17 1807 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1808 .family = 16,
1809 .model = 2,
1810 .stepping = 3,
b9fc20bc 1811 /* Missing: CPUID_HT */
0514ef2f 1812 .features[FEAT_1_EDX] =
27861ecc 1813 PPRO_FEATURES |
c6dc6f63 1814 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1815 CPUID_PSE36 | CPUID_VME,
0514ef2f 1816 .features[FEAT_1_ECX] =
27861ecc 1817 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1818 CPUID_EXT_POPCNT,
0514ef2f 1819 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1820 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1821 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1822 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1823 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1824 CPUID_EXT3_CR8LEG,
1825 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1826 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1827 .features[FEAT_8000_0001_ECX] =
27861ecc 1828 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1829 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1830 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1831 .features[FEAT_SVM] =
b9fc20bc 1832 CPUID_SVM_NPT,
c6dc6f63
AP		 1833 .xlevel = 0x8000001A,
1834 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1835 },
1836 {
1837 .name = "core2duo",
1838 .level = 10,
99b88a17 1839 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1840 .family = 6,
1841 .model = 15,
1842 .stepping = 11,
b9fc20bc 1843 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1844 .features[FEAT_1_EDX] =
27861ecc 1845 PPRO_FEATURES |
c6dc6f63 1846 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1847 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1848 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1849 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1850 .features[FEAT_1_ECX] =
27861ecc 1851 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1852 CPUID_EXT_CX16,
0514ef2f 1853 .features[FEAT_8000_0001_EDX] =
27861ecc 1854 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1855 .features[FEAT_8000_0001_ECX] =
27861ecc 1856 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 1857 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1858 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1859 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1860 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1861 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1862 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1863 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1864 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1865 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1866 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1867 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1868 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1869 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1870 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1871 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1872 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1873 .features[FEAT_VMX_SECONDARY_CTLS] =
1874 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
c6dc6f63
AP		 1875 .xlevel = 0x80000008,
1876 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1877 },
1878 {
1879 .name = "kvm64",
3046bb5d 1880 .level = 0xd,
99b88a17 1881 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1882 .family = 15,
1883 .model = 6,
1884 .stepping = 1,
b3a4f0b1 1885 /* Missing: CPUID_HT */
0514ef2f 1886 .features[FEAT_1_EDX] =
b3a4f0b1 1887 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1888 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1889 CPUID_PSE36,
1890 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1891 .features[FEAT_1_ECX] =
27861ecc 1892 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1893 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1894 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1895 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1896 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1897 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1898 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1899 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1900 .features[FEAT_8000_0001_ECX] =
27861ecc 1901 0,
0723cc8a
PB		 1902 /* VMX features from Cedar Mill/Prescott */
1903 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1904 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1905 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1906 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1907 VMX_PIN_BASED_NMI_EXITING,
1908 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1909 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1910 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1911 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1912 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1913 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1914 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1915 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
c6dc6f63
AP		 1916 .xlevel = 0x80000008,
1917 .model_id = "Common KVM processor"
1918 },
c6dc6f63
AP		 1919 {
1920 .name = "qemu32",
1921 .level = 4,
99b88a17 1922 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1923 .family = 6,
f8e6a11a 1924 .model = 6,
c6dc6f63 1925 .stepping = 3,
0514ef2f 1926 .features[FEAT_1_EDX] =
27861ecc 1927 PPRO_FEATURES,
0514ef2f 1928 .features[FEAT_1_ECX] =
6aa91e4a 1929 CPUID_EXT_SSE3,
58012d66 1930 .xlevel = 0x80000004,
9cf2cc3d 1931 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1932 },
eafaf1e5
AP		 1933 {
1934 .name = "kvm32",
1935 .level = 5,
99b88a17 1936 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1937 .family = 15,
1938 .model = 6,
1939 .stepping = 1,
0514ef2f 1940 .features[FEAT_1_EDX] =
b3a4f0b1 1941 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1942 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1943 .features[FEAT_1_ECX] =
27861ecc 1944 CPUID_EXT_SSE3,
0514ef2f 1945 .features[FEAT_8000_0001_ECX] =
27861ecc 1946 0,
0723cc8a
PB		 1947 /* VMX features from Yonah */
1948 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1949 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1950 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1951 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1952 VMX_PIN_BASED_NMI_EXITING,
1953 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1954 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1955 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1956 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1957 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1958 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1959 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
eafaf1e5
AP		 1960 .xlevel = 0x80000008,
1961 .model_id = "Common 32-bit KVM processor"
1962 },
c6dc6f63
AP		 1963 {
1964 .name = "coreduo",
1965 .level = 10,
99b88a17 1966 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1967 .family = 6,
1968 .model = 14,
1969 .stepping = 8,
b9fc20bc 1970 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1971 .features[FEAT_1_EDX] =
27861ecc 1972 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1973 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1974 CPUID_SS,
1975 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1976 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1977 .features[FEAT_1_ECX] =
e93abc14 1978 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1979 .features[FEAT_8000_0001_EDX] =
27861ecc 1980 CPUID_EXT2_NX,
0723cc8a
PB		 1981 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1982 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1983 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1984 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1985 VMX_PIN_BASED_NMI_EXITING,
1986 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1987 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1988 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1989 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1990 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1991 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1992 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
c6dc6f63
AP		 1993 .xlevel = 0x80000008,
1994 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1995 },
1996 {
1997 .name = "486",
58012d66 1998 .level = 1,
99b88a17 1999 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 2000 .family = 4,
b2a856d9 2001 .model = 8,
c6dc6f63 2002 .stepping = 0,
0514ef2f 2003 .features[FEAT_1_EDX] =
27861ecc 2004 I486_FEATURES,
c6dc6f63 2005 .xlevel = 0,
807e9869 2006 .model_id = "",
c6dc6f63
AP		 2007 },
2008 {
2009 .name = "pentium",
2010 .level = 1,
99b88a17 2011 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2012 .family = 5,
2013 .model = 4,
2014 .stepping = 3,
0514ef2f 2015 .features[FEAT_1_EDX] =
27861ecc 2016 PENTIUM_FEATURES,
c6dc6f63 2017 .xlevel = 0,
807e9869 2018 .model_id = "",
c6dc6f63
AP		 2019 },
2020 {
2021 .name = "pentium2",
2022 .level = 2,
99b88a17 2023 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2024 .family = 6,
2025 .model = 5,
2026 .stepping = 2,
0514ef2f 2027 .features[FEAT_1_EDX] =
27861ecc 2028 PENTIUM2_FEATURES,
c6dc6f63 2029 .xlevel = 0,
807e9869 2030 .model_id = "",
c6dc6f63
AP		 2031 },
2032 {
2033 .name = "pentium3",
3046bb5d 2034 .level = 3,
99b88a17 2035 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2036 .family = 6,
2037 .model = 7,
2038 .stepping = 3,
0514ef2f 2039 .features[FEAT_1_EDX] =
27861ecc 2040 PENTIUM3_FEATURES,
c6dc6f63 2041 .xlevel = 0,
807e9869 2042 .model_id = "",
c6dc6f63
AP		 2043 },
2044 {
2045 .name = "athlon",
2046 .level = 2,
99b88a17 2047 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 2048 .family = 6,
2049 .model = 2,
2050 .stepping = 3,
0514ef2f 2051 .features[FEAT_1_EDX] =
27861ecc 2052 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 2053 CPUID_MCA,
0514ef2f 2054 .features[FEAT_8000_0001_EDX] =
60032ac0 2055 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 2056 .xlevel = 0x80000008,
9cf2cc3d 2057 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 2058 },
2059 {
2060 .name = "n270",
3046bb5d 2061 .level = 10,
99b88a17 2062 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2063 .family = 6,
2064 .model = 28,
2065 .stepping = 2,
b9fc20bc 2066 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2067 .features[FEAT_1_EDX] =
27861ecc 2068 PPRO_FEATURES |
b9fc20bc
EH		 2069 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2070 CPUID_ACPI | CPUID_SS,
c6dc6f63 2071 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 2072 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2073 * CPUID_EXT_XTPR */
0514ef2f 2074 .features[FEAT_1_ECX] =
27861ecc 2075 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 2076 CPUID_EXT_MOVBE,
0514ef2f 2077 .features[FEAT_8000_0001_EDX] =
60032ac0 2078 CPUID_EXT2_NX,
0514ef2f 2079 .features[FEAT_8000_0001_ECX] =
27861ecc 2080 CPUID_EXT3_LAHF_LM,
3046bb5d 2081 .xlevel = 0x80000008,
c6dc6f63
AP		 2082 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2083 },
3eca4642
EH		 2084 {
2085 .name = "Conroe",
3046bb5d 2086 .level = 10,
99b88a17 2087 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2088 .family = 6,
ffce9ebb 2089 .model = 15,
3eca4642 2090 .stepping = 3,
0514ef2f 2091 .features[FEAT_1_EDX] =
b3a4f0b1 2092 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2093 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2094 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2095 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2096 CPUID_DE | CPUID_FP87,
0514ef2f 2097 .features[FEAT_1_ECX] =
27861ecc 2098 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2099 .features[FEAT_8000_0001_EDX] =
27861ecc 2100 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2101 .features[FEAT_8000_0001_ECX] =
27861ecc 2102 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2103 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2104 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2105 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2106 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2107 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2108 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2109 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2110 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2111 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2112 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2113 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2114 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2115 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2116 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2117 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2118 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2119 .features[FEAT_VMX_SECONDARY_CTLS] =
2120 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
3046bb5d 2121 .xlevel = 0x80000008,
3eca4642
EH		 2122 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2123 },
2124 {
2125 .name = "Penryn",
3046bb5d 2126 .level = 10,
99b88a17 2127 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2128 .family = 6,
ffce9ebb 2129 .model = 23,
3eca4642 2130 .stepping = 3,
0514ef2f 2131 .features[FEAT_1_EDX] =
b3a4f0b1 2132 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2133 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2134 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2135 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2136 CPUID_DE | CPUID_FP87,
0514ef2f 2137 .features[FEAT_1_ECX] =
27861ecc 2138 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 2139 CPUID_EXT_SSE3,
0514ef2f 2140 .features[FEAT_8000_0001_EDX] =
27861ecc 2141 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2142 .features[FEAT_8000_0001_ECX] =
27861ecc 2143 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2144 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2145 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2146 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2147 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2148 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2149 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2150 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2151 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2152 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2153 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2154 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2155 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2156 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2157 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2158 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2159 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2160 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2161 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2162 .features[FEAT_VMX_SECONDARY_CTLS] =
2163 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2164 VMX_SECONDARY_EXEC_WBINVD_EXITING,
3046bb5d 2165 .xlevel = 0x80000008,
3eca4642
EH		 2166 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2167 },
2168 {
2169 .name = "Nehalem",
3046bb5d 2170 .level = 11,
99b88a17 2171 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2172 .family = 6,
ffce9ebb 2173 .model = 26,
3eca4642 2174 .stepping = 3,
0514ef2f 2175 .features[FEAT_1_EDX] =
b3a4f0b1 2176 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2177 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2178 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2179 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2180 CPUID_DE | CPUID_FP87,
0514ef2f 2181 .features[FEAT_1_ECX] =
27861ecc 2182 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 2183 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2184 .features[FEAT_8000_0001_EDX] =
27861ecc 2185 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2186 .features[FEAT_8000_0001_ECX] =
27861ecc 2187 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2188 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2189 MSR_VMX_BASIC_TRUE_CTLS,
2190 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2191 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2192 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2193 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2194 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2195 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2196 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2197 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2198 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2199 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2200 .features[FEAT_VMX_EXIT_CTLS] =
2201 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2202 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2203 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2204 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2205 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2206 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2207 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2208 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2209 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2210 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2211 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2212 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2213 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2214 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2215 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2216 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2217 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2218 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2219 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2220 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2221 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2222 .features[FEAT_VMX_SECONDARY_CTLS] =
2223 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2224 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2225 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2226 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2227 VMX_SECONDARY_EXEC_ENABLE_VPID,
3046bb5d 2228 .xlevel = 0x80000008,
3eca4642 2229 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
d86a7088
EH		 2230 .versions = (X86CPUVersionDefinition[]) {
2231 { .version = 1 },
2232 {
2233 .version = 2,
53db89d9 2234 .alias = "Nehalem-IBRS",
d86a7088
EH		 2235 .props = (PropValue[]) {
2236 { "spec-ctrl", "on" },
2237 { "model-id",
2238 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2239 { /* end of list */ }
2240 }
2241 },
2242 { /* end of list */ }
2243 }
3eca4642
EH		 2244 },
2245 {
2246 .name = "Westmere",
2247 .level = 11,
99b88a17 2248 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2249 .family = 6,
2250 .model = 44,
2251 .stepping = 1,
0514ef2f 2252 .features[FEAT_1_EDX] =
b3a4f0b1 2253 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2254 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2255 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2256 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2257 CPUID_DE | CPUID_FP87,
0514ef2f 2258 .features[FEAT_1_ECX] =
27861ecc 2259 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 2260 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2261 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 2262 .features[FEAT_8000_0001_EDX] =
27861ecc 2263 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2264 .features[FEAT_8000_0001_ECX] =
27861ecc 2265 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 2266 .features[FEAT_6_EAX] =
2267 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2268 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2269 MSR_VMX_BASIC_TRUE_CTLS,
2270 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2271 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2272 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2273 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2274 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2275 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2276 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2277 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2278 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2279 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2280 .features[FEAT_VMX_EXIT_CTLS] =
2281 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2282 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2283 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2284 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2285 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2286 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2287 MSR_VMX_MISC_STORE_LMA,
2288 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2289 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2290 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2291 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2292 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2293 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2294 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2295 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2296 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2297 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2298 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2299 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2300 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2301 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2302 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2303 .features[FEAT_VMX_SECONDARY_CTLS] =
2304 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2305 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2306 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2307 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2308 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2309 .xlevel = 0x80000008,
3eca4642 2310 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
d86a7088
EH		 2311 .versions = (X86CPUVersionDefinition[]) {
2312 { .version = 1 },
2313 {
2314 .version = 2,
53db89d9 2315 .alias = "Westmere-IBRS",
d86a7088
EH		 2316 .props = (PropValue[]) {
2317 { "spec-ctrl", "on" },
2318 { "model-id",
2319 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2320 { /* end of list */ }
2321 }
2322 },
2323 { /* end of list */ }
2324 }
3eca4642
EH		 2325 },
2326 {
2327 .name = "SandyBridge",
2328 .level = 0xd,
99b88a17 2329 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2330 .family = 6,
2331 .model = 42,
2332 .stepping = 1,
0514ef2f 2333 .features[FEAT_1_EDX] =
b3a4f0b1 2334 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2335 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2336 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2337 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2338 CPUID_DE | CPUID_FP87,
0514ef2f 2339 .features[FEAT_1_ECX] =
27861ecc 2340 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2341 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2342 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2343 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2344 CPUID_EXT_SSE3,
0514ef2f 2345 .features[FEAT_8000_0001_EDX] =
27861ecc 2346 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2347 CPUID_EXT2_SYSCALL,
0514ef2f 2348 .features[FEAT_8000_0001_ECX] =
27861ecc 2349 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 2350 .features[FEAT_XSAVE] =
2351 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2352 .features[FEAT_6_EAX] =
2353 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2354 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2355 MSR_VMX_BASIC_TRUE_CTLS,
2356 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2357 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2358 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2359 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2360 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2361 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2362 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2363 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2364 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2365 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2366 .features[FEAT_VMX_EXIT_CTLS] =
2367 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2368 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2369 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2370 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2371 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2372 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2373 MSR_VMX_MISC_STORE_LMA,
2374 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2375 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2376 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2377 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2378 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2379 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2380 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2381 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2382 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2383 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2384 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2385 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2386 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2387 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2388 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2389 .features[FEAT_VMX_SECONDARY_CTLS] =
2390 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2391 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2392 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2393 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2394 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2395 .xlevel = 0x80000008,
3eca4642 2396 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
d86a7088
EH		 2397 .versions = (X86CPUVersionDefinition[]) {
2398 { .version = 1 },
2399 {
2400 .version = 2,
53db89d9 2401 .alias = "SandyBridge-IBRS",
d86a7088
EH		 2402 .props = (PropValue[]) {
2403 { "spec-ctrl", "on" },
2404 { "model-id",
2405 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2406 { /* end of list */ }
2407 }
2408 },
2409 { /* end of list */ }
2410 }
3eca4642 2411 },
2f9ac42a
PB		 2412 {
2413 .name = "IvyBridge",
2414 .level = 0xd,
2415 .vendor = CPUID_VENDOR_INTEL,
2416 .family = 6,
2417 .model = 58,
2418 .stepping = 9,
2419 .features[FEAT_1_EDX] =
2420 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2421 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2422 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2423 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2424 CPUID_DE | CPUID_FP87,
2425 .features[FEAT_1_ECX] =
2426 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2427 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2428 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2429 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2430 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2431 .features[FEAT_7_0_EBX] =
2432 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2433 CPUID_7_0_EBX_ERMS,
2434 .features[FEAT_8000_0001_EDX] =
2435 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2436 CPUID_EXT2_SYSCALL,
2437 .features[FEAT_8000_0001_ECX] =
2438 CPUID_EXT3_LAHF_LM,
2439 .features[FEAT_XSAVE] =
2440 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2441 .features[FEAT_6_EAX] =
2442 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2443 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2444 MSR_VMX_BASIC_TRUE_CTLS,
2445 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2446 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2447 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2448 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2449 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2450 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2451 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2452 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2453 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2454 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2455 .features[FEAT_VMX_EXIT_CTLS] =
2456 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2457 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2458 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2459 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2460 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2461 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2462 MSR_VMX_MISC_STORE_LMA,
2463 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2464 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2465 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2466 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2467 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2468 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2469 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2470 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2471 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2472 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2473 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2474 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2475 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2476 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2477 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2478 .features[FEAT_VMX_SECONDARY_CTLS] =
2479 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2480 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2481 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2482 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2483 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2484 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2485 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2486 VMX_SECONDARY_EXEC_RDRAND_EXITING,
3046bb5d 2487 .xlevel = 0x80000008,
2f9ac42a 2488 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
d86a7088
EH		 2489 .versions = (X86CPUVersionDefinition[]) {
2490 { .version = 1 },
2491 {
2492 .version = 2,
53db89d9 2493 .alias = "IvyBridge-IBRS",
d86a7088
EH		 2494 .props = (PropValue[]) {
2495 { "spec-ctrl", "on" },
2496 { "model-id",
2497 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2498 { /* end of list */ }
2499 }
2500 },
2501 { /* end of list */ }
2502 }
2f9ac42a 2503 },
ac96c413 2504 {
37507094
EH		 2505 .name = "Haswell",
2506 .level = 0xd,
99b88a17 2507 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2508 .family = 6,
2509 .model = 60,
ec56a4a7 2510 .stepping = 4,
0514ef2f 2511 .features[FEAT_1_EDX] =
b3a4f0b1 2512 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2513 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2514 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2515 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2516 CPUID_DE | CPUID_FP87,
0514ef2f 2517 .features[FEAT_1_ECX] =
27861ecc 2518 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2519 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2520 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2521 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2522 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2523 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2524 .features[FEAT_8000_0001_EDX] =
27861ecc 2525 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2526 CPUID_EXT2_SYSCALL,
0514ef2f 2527 .features[FEAT_8000_0001_ECX] =
becb6667 2528 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2529 .features[FEAT_7_0_EBX] =
27861ecc 2530 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2531 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2532 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2533 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2534 .features[FEAT_XSAVE] =
2535 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2536 .features[FEAT_6_EAX] =
2537 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2538 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2539 MSR_VMX_BASIC_TRUE_CTLS,
2540 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2541 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2542 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2543 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2544 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2545 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2546 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2547 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2548 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2549 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2550 .features[FEAT_VMX_EXIT_CTLS] =
2551 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2552 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2553 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2554 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2555 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2556 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2557 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2558 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2559 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2560 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2561 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2562 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2563 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2564 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2565 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2566 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2567 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2568 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2569 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2570 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2571 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2572 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2573 .features[FEAT_VMX_SECONDARY_CTLS] =
2574 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2575 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2576 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2577 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2578 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2579 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2580 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2581 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2582 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2583 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2584 .xlevel = 0x80000008,
37507094 2585 .model_id = "Intel Core Processor (Haswell)",
d86a7088
EH		 2586 .versions = (X86CPUVersionDefinition[]) {
2587 { .version = 1 },
2588 {
2589 .version = 2,
53db89d9 2590 .alias = "Haswell-noTSX",
d86a7088
EH		 2591 .props = (PropValue[]) {
2592 { "hle", "off" },
2593 { "rtm", "off" },
2594 { "stepping", "1" },
2595 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2596 { /* end of list */ }
2597 },
2598 },
2599 {
2600 .version = 3,
53db89d9 2601 .alias = "Haswell-IBRS",
d86a7088
EH		 2602 .props = (PropValue[]) {
2603 /* Restore TSX features removed by -v2 above */
2604 { "hle", "on" },
2605 { "rtm", "on" },
2606 /*
2607 * Haswell and Haswell-IBRS had stepping=4 in
2608 * QEMU 4.0 and older
2609 */
2610 { "stepping", "4" },
2611 { "spec-ctrl", "on" },
2612 { "model-id",
2613 "Intel Core Processor (Haswell, IBRS)" },
2614 { /* end of list */ }
2615 }
2616 },
2617 {
2618 .version = 4,
53db89d9 2619 .alias = "Haswell-noTSX-IBRS",
d86a7088
EH		 2620 .props = (PropValue[]) {
2621 { "hle", "off" },
2622 { "rtm", "off" },
2623 /* spec-ctrl was already enabled by -v3 above */
2624 { "stepping", "1" },
2625 { "model-id",
2626 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2627 { /* end of list */ }
2628 }
2629 },
2630 { /* end of list */ }
2631 }
37507094 2632 },
ece01354
EH		 2633 {
2634 .name = "Broadwell",
2635 .level = 0xd,
2636 .vendor = CPUID_VENDOR_INTEL,
2637 .family = 6,
2638 .model = 61,
2639 .stepping = 2,
2640 .features[FEAT_1_EDX] =
b3a4f0b1 2641 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2642 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2643 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2644 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2645 CPUID_DE | CPUID_FP87,
2646 .features[FEAT_1_ECX] =
2647 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2648 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2649 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2650 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2651 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2652 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2653 .features[FEAT_8000_0001_EDX] =
2654 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2655 CPUID_EXT2_SYSCALL,
2656 .features[FEAT_8000_0001_ECX] =
becb6667 2657 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2658 .features[FEAT_7_0_EBX] =
2659 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2660 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2661 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2662 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2663 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2664 .features[FEAT_XSAVE] =
2665 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2666 .features[FEAT_6_EAX] =
2667 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2668 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2669 MSR_VMX_BASIC_TRUE_CTLS,
2670 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2671 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2672 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2673 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2674 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2675 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2676 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2677 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2678 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2679 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2680 .features[FEAT_VMX_EXIT_CTLS] =
2681 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2682 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2683 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2684 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2685 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2686 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2687 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2688 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2689 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2690 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2691 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2692 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2693 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2694 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2695 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2696 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2697 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2698 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2699 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2700 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2701 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2702 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2703 .features[FEAT_VMX_SECONDARY_CTLS] =
2704 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2705 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2706 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2707 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2708 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2709 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2710 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2711 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2712 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2713 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2714 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2715 .xlevel = 0x80000008,
ece01354 2716 .model_id = "Intel Core Processor (Broadwell)",
d86a7088
EH		 2717 .versions = (X86CPUVersionDefinition[]) {
2718 { .version = 1 },
2719 {
2720 .version = 2,
53db89d9 2721 .alias = "Broadwell-noTSX",
d86a7088
EH		 2722 .props = (PropValue[]) {
2723 { "hle", "off" },
2724 { "rtm", "off" },
2725 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2726 { /* end of list */ }
2727 },
2728 },
2729 {
2730 .version = 3,
53db89d9 2731 .alias = "Broadwell-IBRS",
d86a7088
EH		 2732 .props = (PropValue[]) {
2733 /* Restore TSX features removed by -v2 above */
2734 { "hle", "on" },
2735 { "rtm", "on" },
2736 { "spec-ctrl", "on" },
2737 { "model-id",
2738 "Intel Core Processor (Broadwell, IBRS)" },
2739 { /* end of list */ }
2740 }
2741 },
2742 {
2743 .version = 4,
53db89d9 2744 .alias = "Broadwell-noTSX-IBRS",
d86a7088
EH		 2745 .props = (PropValue[]) {
2746 { "hle", "off" },
2747 { "rtm", "off" },
2748 /* spec-ctrl was already enabled by -v3 above */
2749 { "model-id",
2750 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2751 { /* end of list */ }
2752 }
2753 },
2754 { /* end of list */ }
2755 }
ece01354 2756 },
f6f949e9
EH		 2757 {
2758 .name = "Skylake-Client",
2759 .level = 0xd,
2760 .vendor = CPUID_VENDOR_INTEL,
2761 .family = 6,
2762 .model = 94,
2763 .stepping = 3,
2764 .features[FEAT_1_EDX] =
2765 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2766 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2767 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2768 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2769 CPUID_DE | CPUID_FP87,
2770 .features[FEAT_1_ECX] =
2771 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2772 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2773 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2774 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2775 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2776 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2777 .features[FEAT_8000_0001_EDX] =
2778 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2779 CPUID_EXT2_SYSCALL,
2780 .features[FEAT_8000_0001_ECX] =
2781 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2782 .features[FEAT_7_0_EBX] =
2783 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2784 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2785 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2786 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2787 CPUID_7_0_EBX_SMAP,
7bde6b18 2788 /* XSAVES is added in version 4 */
f6f949e9
EH		 2789 .features[FEAT_XSAVE] =
2790 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2791 CPUID_XSAVE_XGETBV1,
2792 .features[FEAT_6_EAX] =
2793 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2794 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2795 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2796 MSR_VMX_BASIC_TRUE_CTLS,
2797 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2798 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2799 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2800 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2801 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2802 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2803 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2804 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2805 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2806 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2807 .features[FEAT_VMX_EXIT_CTLS] =
2808 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2809 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2810 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2811 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2812 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2813 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2814 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2815 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2816 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2817 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2818 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2819 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2820 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2821 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2822 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2823 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2824 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2825 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2826 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2827 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2828 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2829 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2830 .features[FEAT_VMX_SECONDARY_CTLS] =
2831 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2832 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2833 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2834 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2835 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2836 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2837 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2838 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
f6f949e9
EH		 2839 .xlevel = 0x80000008,
2840 .model_id = "Intel Core Processor (Skylake)",
d86a7088
EH		 2841 .versions = (X86CPUVersionDefinition[]) {
2842 { .version = 1 },
2843 {
2844 .version = 2,
53db89d9 2845 .alias = "Skylake-Client-IBRS",
d86a7088
EH		 2846 .props = (PropValue[]) {
2847 { "spec-ctrl", "on" },
2848 { "model-id",
2849 "Intel Core Processor (Skylake, IBRS)" },
2850 { /* end of list */ }
2851 }
2852 },
9ab2237f
EH		 2853 {
2854 .version = 3,
02fa60d1 2855 .alias = "Skylake-Client-noTSX-IBRS",
9ab2237f
EH		 2856 .props = (PropValue[]) {
2857 { "hle", "off" },
2858 { "rtm", "off" },
673b0add
KC		 2859 { "model-id",
2860 "Intel Core Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 2861 { /* end of list */ }
2862 }
2863 },
7bde6b18
VK		 2864 {
2865 .version = 4,
2866 .note = "IBRS, XSAVES, no TSX",
2867 .props = (PropValue[]) {
2868 { "xsaves", "on" },
2869 { "vmx-xsaves", "on" },
2870 { /* end of list */ }
2871 }
2872 },
d86a7088
EH		 2873 { /* end of list */ }
2874 }
f6f949e9 2875 },
53f9a6f4
BF		 2876 {
2877 .name = "Skylake-Server",
2878 .level = 0xd,
2879 .vendor = CPUID_VENDOR_INTEL,
2880 .family = 6,
2881 .model = 85,
2882 .stepping = 4,
2883 .features[FEAT_1_EDX] =
2884 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2885 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2886 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2887 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2888 CPUID_DE | CPUID_FP87,
2889 .features[FEAT_1_ECX] =
2890 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2891 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2892 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2893 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2894 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2895 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2896 .features[FEAT_8000_0001_EDX] =
2897 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2898 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2899 .features[FEAT_8000_0001_ECX] =
2900 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2901 .features[FEAT_7_0_EBX] =
2902 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2903 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2904 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2905 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2906 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
53f9a6f4
BF		 2907 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2908 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2909 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 2910 .features[FEAT_7_0_ECX] =
2911 CPUID_7_0_ECX_PKU,
7bde6b18 2912 /* XSAVES is added in version 5 */
53f9a6f4
BF		 2913 .features[FEAT_XSAVE] =
2914 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2915 CPUID_XSAVE_XGETBV1,
2916 .features[FEAT_6_EAX] =
2917 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2918 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2919 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2920 MSR_VMX_BASIC_TRUE_CTLS,
2921 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2922 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2923 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2924 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2925 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2926 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2927 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2928 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2929 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2930 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2931 .features[FEAT_VMX_EXIT_CTLS] =
2932 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2933 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2934 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2935 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2936 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2937 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2938 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2939 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2940 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2941 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2942 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2943 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2944 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2945 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2946 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2947 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2948 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2949 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2950 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2951 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2952 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2953 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2954 .features[FEAT_VMX_SECONDARY_CTLS] =
2955 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2956 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2957 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2958 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2959 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2960 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2961 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2962 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 2963 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2964 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
53f9a6f4
BF		 2965 .xlevel = 0x80000008,
2966 .model_id = "Intel Xeon Processor (Skylake)",
d86a7088
EH		 2967 .versions = (X86CPUVersionDefinition[]) {
2968 { .version = 1 },
2969 {
2970 .version = 2,
53db89d9 2971 .alias = "Skylake-Server-IBRS",
d86a7088
EH		 2972 .props = (PropValue[]) {
2973 /* clflushopt was not added to Skylake-Server-IBRS */
2974 /* TODO: add -v3 including clflushopt */
2975 { "clflushopt", "off" },
2976 { "spec-ctrl", "on" },
2977 { "model-id",
2978 "Intel Xeon Processor (Skylake, IBRS)" },
2979 { /* end of list */ }
2980 }
2981 },
9ab2237f
EH		 2982 {
2983 .version = 3,
02fa60d1 2984 .alias = "Skylake-Server-noTSX-IBRS",
9ab2237f
EH		 2985 .props = (PropValue[]) {
2986 { "hle", "off" },
2987 { "rtm", "off" },
673b0add
KC		 2988 { "model-id",
2989 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 2990 { /* end of list */ }
2991 }
2992 },
644e3c5d
CQ		 2993 {
2994 .version = 4,
2995 .props = (PropValue[]) {
2996 { "vmx-eptp-switching", "on" },
2997 { /* end of list */ }
2998 }
2999 },
7bde6b18
VK		 3000 {
3001 .version = 5,
3002 .note = "IBRS, XSAVES, EPT switching, no TSX",
3003 .props = (PropValue[]) {
3004 { "xsaves", "on" },
3005 { "vmx-xsaves", "on" },
3006 { /* end of list */ }
3007 }
3008 },
d86a7088
EH		 3009 { /* end of list */ }
3010 }
53f9a6f4 3011 },
c7a88b52
TX		 3012 {
3013 .name = "Cascadelake-Server",
3014 .level = 0xd,
3015 .vendor = CPUID_VENDOR_INTEL,
3016 .family = 6,
3017 .model = 85,
b0a19803 3018 .stepping = 6,
c7a88b52
TX		 3019 .features[FEAT_1_EDX] =
3020 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3021 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3022 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3023 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3024 CPUID_DE | CPUID_FP87,
3025 .features[FEAT_1_ECX] =
3026 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3027 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3028 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3029 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3030 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3031 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3032 .features[FEAT_8000_0001_EDX] =
3033 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3034 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3035 .features[FEAT_8000_0001_ECX] =
3036 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3037 .features[FEAT_7_0_EBX] =
3038 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3039 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3040 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3041 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3042 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
c7a88b52
TX		 3043 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3044 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3045 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
c7a88b52 3046 .features[FEAT_7_0_ECX] =
bb4928c7 3047 CPUID_7_0_ECX_PKU |
c7a88b52
TX		 3048 CPUID_7_0_ECX_AVX512VNNI,
3049 .features[FEAT_7_0_EDX] =
3050 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3051 /* XSAVES is added in version 5 */
c7a88b52
TX		 3052 .features[FEAT_XSAVE] =
3053 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3054 CPUID_XSAVE_XGETBV1,
3055 .features[FEAT_6_EAX] =
3056 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3057 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3058 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3059 MSR_VMX_BASIC_TRUE_CTLS,
3060 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3061 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3062 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3063 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3064 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3065 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3066 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3067 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3068 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3069 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3070 .features[FEAT_VMX_EXIT_CTLS] =
3071 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3072 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3073 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3074 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3075 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3076 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3077 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3078 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3079 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3080 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3081 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3082 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3083 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3084 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3085 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3086 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3087 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3088 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3089 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3090 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3091 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3092 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3093 .features[FEAT_VMX_SECONDARY_CTLS] =
3094 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3095 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3096 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3097 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3098 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3099 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3100 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3101 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3102 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3103 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
c7a88b52
TX		 3104 .xlevel = 0x80000008,
3105 .model_id = "Intel Xeon Processor (Cascadelake)",
fd63c6d1
EH		 3106 .versions = (X86CPUVersionDefinition[]) {
3107 { .version = 1 },
3108 { .version = 2,
47f0d11d 3109 .note = "ARCH_CAPABILITIES",
fd63c6d1
EH		 3110 .props = (PropValue[]) {
3111 { "arch-capabilities", "on" },
3112 { "rdctl-no", "on" },
3113 { "ibrs-all", "on" },
3114 { "skip-l1dfl-vmentry", "on" },
3115 { "mds-no", "on" },
3116 { /* end of list */ }
3117 },
3118 },
9ab2237f 3119 { .version = 3,
02fa60d1 3120 .alias = "Cascadelake-Server-noTSX",
47f0d11d 3121 .note = "ARCH_CAPABILITIES, no TSX",
9ab2237f
EH		 3122 .props = (PropValue[]) {
3123 { "hle", "off" },
3124 { "rtm", "off" },
3125 { /* end of list */ }
3126 },
3127 },
644e3c5d
CQ		 3128 { .version = 4,
3129 .note = "ARCH_CAPABILITIES, no TSX",
3130 .props = (PropValue[]) {
3131 { "vmx-eptp-switching", "on" },
3132 { /* end of list */ }
3133 },
3134 },
7bde6b18
VK		 3135 { .version = 5,
3136 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX",
3137 .props = (PropValue[]) {
3138 { "xsaves", "on" },
3139 { "vmx-xsaves", "on" },
3140 { /* end of list */ }
3141 },
3142 },
fd63c6d1
EH		 3143 { /* end of list */ }
3144 }
c7a88b52 3145 },
22a866b6
CZ		 3146 {
3147 .name = "Cooperlake",
3148 .level = 0xd,
3149 .vendor = CPUID_VENDOR_INTEL,
3150 .family = 6,
3151 .model = 85,
3152 .stepping = 10,
3153 .features[FEAT_1_EDX] =
3154 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3155 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3156 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3157 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3158 CPUID_DE | CPUID_FP87,
3159 .features[FEAT_1_ECX] =
3160 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3161 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3162 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3163 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3164 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3165 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3166 .features[FEAT_8000_0001_EDX] =
3167 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3168 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3169 .features[FEAT_8000_0001_ECX] =
3170 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3171 .features[FEAT_7_0_EBX] =
3172 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3173 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3174 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3175 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3176 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3177 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3178 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3179 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3180 .features[FEAT_7_0_ECX] =
3181 CPUID_7_0_ECX_PKU |
3182 CPUID_7_0_ECX_AVX512VNNI,
3183 .features[FEAT_7_0_EDX] =
3184 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3185 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3186 .features[FEAT_ARCH_CAPABILITIES] =
3187 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
2dea9d9c
XL		 3188 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3189 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
22a866b6 3190 .features[FEAT_7_1_EAX] =
f429dbf8 3191 CPUID_7_1_EAX_AVX512_BF16,
7bde6b18 3192 /* XSAVES is added in version 2 */
22a866b6
CZ		 3193 .features[FEAT_XSAVE] =
3194 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3195 CPUID_XSAVE_XGETBV1,
3196 .features[FEAT_6_EAX] =
3197 CPUID_6_EAX_ARAT,
2dea9d9c
XL		 3198 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3199 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3200 MSR_VMX_BASIC_TRUE_CTLS,
3201 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3202 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3203 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3204 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3205 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3206 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3207 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3208 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3209 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3210 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3211 .features[FEAT_VMX_EXIT_CTLS] =
3212 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3213 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3214 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3215 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3216 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3217 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3218 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3219 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3220 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3221 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3222 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3223 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3224 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3225 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3226 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3227 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3228 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3229 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3230 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3231 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3232 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3233 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3234 .features[FEAT_VMX_SECONDARY_CTLS] =
3235 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3236 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3237 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3238 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3239 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3240 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3241 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3242 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3243 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3244 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3245 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
22a866b6
CZ		 3246 .xlevel = 0x80000008,
3247 .model_id = "Intel Xeon Processor (Cooperlake)",
7bde6b18
VK		 3248 .versions = (X86CPUVersionDefinition[]) {
3249 { .version = 1 },
3250 { .version = 2,
3251 .note = "XSAVES",
3252 .props = (PropValue[]) {
3253 { "xsaves", "on" },
3254 { "vmx-xsaves", "on" },
3255 { /* end of list */ }
3256 },
3257 },
3258 { /* end of list */ }
3259 }
22a866b6 3260 },
8a11c62d
RH		 3261 {
3262 .name = "Icelake-Server",
3263 .level = 0xd,
3264 .vendor = CPUID_VENDOR_INTEL,
3265 .family = 6,
3266 .model = 134,
3267 .stepping = 0,
3268 .features[FEAT_1_EDX] =
3269 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3270 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3271 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3272 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3273 CPUID_DE | CPUID_FP87,
3274 .features[FEAT_1_ECX] =
3275 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3276 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3277 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3278 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3279 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3280 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3281 .features[FEAT_8000_0001_EDX] =
3282 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3283 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3284 .features[FEAT_8000_0001_ECX] =
3285 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3286 .features[FEAT_8000_0008_EBX] =
3287 CPUID_8000_0008_EBX_WBNOINVD,
3288 .features[FEAT_7_0_EBX] =
3289 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3290 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3291 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3292 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3293 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
8a11c62d
RH		 3294 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3295 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3296 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
8a11c62d 3297 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3298 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3299 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3300 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3301 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3302 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3303 .features[FEAT_7_0_EDX] =
76e5a4d5 3304 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3305 /* XSAVES is added in version 5 */
8a11c62d
RH		 3306 .features[FEAT_XSAVE] =
3307 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3308 CPUID_XSAVE_XGETBV1,
3309 .features[FEAT_6_EAX] =
3310 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3311 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3312 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3313 MSR_VMX_BASIC_TRUE_CTLS,
3314 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3315 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3316 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3317 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3318 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3319 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3320 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3321 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3322 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3323 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3324 .features[FEAT_VMX_EXIT_CTLS] =
3325 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3326 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3327 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3328 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3329 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3330 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3331 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3332 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3333 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3334 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3335 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3336 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3337 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3338 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3339 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3340 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3341 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3342 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3343 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3344 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3345 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3346 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3347 .features[FEAT_VMX_SECONDARY_CTLS] =
3348 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3349 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3350 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3351 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3352 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3353 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3354 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3355 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3356 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
8a11c62d
RH		 3357 .xlevel = 0x80000008,
3358 .model_id = "Intel Xeon Processor (Icelake)",
9ab2237f
EH		 3359 .versions = (X86CPUVersionDefinition[]) {
3360 { .version = 1 },
3361 {
3362 .version = 2,
47f0d11d 3363 .note = "no TSX",
02fa60d1 3364 .alias = "Icelake-Server-noTSX",
9ab2237f
EH		 3365 .props = (PropValue[]) {
3366 { "hle", "off" },
3367 { "rtm", "off" },
3368 { /* end of list */ }
3369 },
3370 },
d965dc35
XL		 3371 {
3372 .version = 3,
3373 .props = (PropValue[]) {
3374 { "arch-capabilities", "on" },
3375 { "rdctl-no", "on" },
3376 { "ibrs-all", "on" },
3377 { "skip-l1dfl-vmentry", "on" },
3378 { "mds-no", "on" },
3379 { "pschange-mc-no", "on" },
3380 { "taa-no", "on" },
3381 { /* end of list */ }
3382 },
3383 },
e0013791
CQ		 3384 {
3385 .version = 4,
3386 .props = (PropValue[]) {
3387 { "sha-ni", "on" },
3388 { "avx512ifma", "on" },
3389 { "rdpid", "on" },
3390 { "fsrm", "on" },
3391 { "vmx-rdseed-exit", "on" },
3392 { "vmx-pml", "on" },
3393 { "vmx-eptp-switching", "on" },
3394 { "model", "106" },
3395 { /* end of list */ }
3396 },
3397 },
7bde6b18
VK		 3398 {
3399 .version = 5,
3400 .note = "XSAVES",
3401 .props = (PropValue[]) {
3402 { "xsaves", "on" },
3403 { "vmx-xsaves", "on" },
3404 { /* end of list */ }
3405 },
3406 },
12cab535
VK		 3407 {
3408 .version = 6,
3409 .note = "5-level EPT",
3410 .props = (PropValue[]) {
3411 { "vmx-page-walk-5", "on" },
3412 { /* end of list */ }
3413 },
3414 },
9ab2237f
EH		 3415 { /* end of list */ }
3416 }
8a11c62d 3417 },
8b44d860
TX		 3418 {
3419 .name = "Denverton",
3420 .level = 21,
3421 .vendor = CPUID_VENDOR_INTEL,
3422 .family = 6,
3423 .model = 95,
3424 .stepping = 1,
3425 .features[FEAT_1_EDX] =
3426 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3427 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3428 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3429 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3430 CPUID_SSE | CPUID_SSE2,
3431 .features[FEAT_1_ECX] =
3432 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3433 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3434 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3435 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3436 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3437 .features[FEAT_8000_0001_EDX] =
3438 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3439 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3440 .features[FEAT_8000_0001_ECX] =
3441 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3442 .features[FEAT_7_0_EBX] =
3443 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3444 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3445 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3446 .features[FEAT_7_0_EDX] =
3447 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3448 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3449 /* XSAVES is added in version 3 */
8b44d860
TX		 3450 .features[FEAT_XSAVE] =
3451 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3452 .features[FEAT_6_EAX] =
3453 CPUID_6_EAX_ARAT,
3454 .features[FEAT_ARCH_CAPABILITIES] =
3455 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
0723cc8a
PB		 3456 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3457 MSR_VMX_BASIC_TRUE_CTLS,
3458 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3459 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3460 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3461 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3462 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3463 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3464 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3465 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3466 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3467 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3468 .features[FEAT_VMX_EXIT_CTLS] =
3469 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3470 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3471 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3472 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3473 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3474 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3475 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3476 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3477 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3478 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3479 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3480 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3481 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3482 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3483 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3484 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3485 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3486 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3487 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3488 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3489 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3490 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3491 .features[FEAT_VMX_SECONDARY_CTLS] =
3492 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3493 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3494 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3495 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3496 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3497 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3498 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3499 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3500 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3501 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3502 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8b44d860
TX		 3503 .xlevel = 0x80000008,
3504 .model_id = "Intel Atom Processor (Denverton)",
ab0c942c
TX		 3505 .versions = (X86CPUVersionDefinition[]) {
3506 { .version = 1 },
3507 {
3508 .version = 2,
47f0d11d 3509 .note = "no MPX, no MONITOR",
ab0c942c
TX		 3510 .props = (PropValue[]) {
3511 { "monitor", "off" },
3512 { "mpx", "off" },
3513 { /* end of list */ },
3514 },
3515 },
7bde6b18
VK		 3516 {
3517 .version = 3,
3518 .note = "XSAVES, no MPX, no MONITOR",
3519 .props = (PropValue[]) {
3520 { "xsaves", "on" },
3521 { "vmx-xsaves", "on" },
3522 { /* end of list */ },
3523 },
3524 },
ab0c942c
TX		 3525 { /* end of list */ },
3526 },
8b44d860 3527 },
0b18874b 3528 {
ff656fcd 3529 .name = "Snowridge",
0b18874b
PL		 3530 .level = 27,
3531 .vendor = CPUID_VENDOR_INTEL,
3532 .family = 6,
3533 .model = 134,
3534 .stepping = 1,
3535 .features[FEAT_1_EDX] =
3536 /* missing: CPUID_PN CPUID_IA64 */
3537 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3538 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3539 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3540 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3541 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3542 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3543 CPUID_MMX |
3544 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3545 .features[FEAT_1_ECX] =
3546 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
0b18874b
PL		 3547 CPUID_EXT_SSSE3 |
3548 CPUID_EXT_CX16 |
3549 CPUID_EXT_SSE41 |
3550 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3551 CPUID_EXT_POPCNT |
3552 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3553 CPUID_EXT_RDRAND,
3554 .features[FEAT_8000_0001_EDX] =
3555 CPUID_EXT2_SYSCALL |
3556 CPUID_EXT2_NX |
3557 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3558 CPUID_EXT2_LM,
3559 .features[FEAT_8000_0001_ECX] =
3560 CPUID_EXT3_LAHF_LM |
3561 CPUID_EXT3_3DNOWPREFETCH,
3562 .features[FEAT_7_0_EBX] =
3563 CPUID_7_0_EBX_FSGSBASE |
3564 CPUID_7_0_EBX_SMEP |
3565 CPUID_7_0_EBX_ERMS |
3566 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
3567 CPUID_7_0_EBX_RDSEED |
3568 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3569 CPUID_7_0_EBX_CLWB |
3570 CPUID_7_0_EBX_SHA_NI,
3571 .features[FEAT_7_0_ECX] =
3572 CPUID_7_0_ECX_UMIP |
3573 /* missing bit 5 */
3574 CPUID_7_0_ECX_GFNI |
3575 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
3576 CPUID_7_0_ECX_MOVDIR64B,
3577 .features[FEAT_7_0_EDX] =
3578 CPUID_7_0_EDX_SPEC_CTRL |
3579 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
3580 CPUID_7_0_EDX_CORE_CAPABILITY,
3581 .features[FEAT_CORE_CAPABILITY] =
3582 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
7bde6b18 3583 /* XSAVES is is added in version 3 */
0b18874b
PL		 3584 .features[FEAT_XSAVE] =
3585 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3586 CPUID_XSAVE_XGETBV1,
3587 .features[FEAT_6_EAX] =
3588 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3589 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3590 MSR_VMX_BASIC_TRUE_CTLS,
3591 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3592 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3593 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3594 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3595 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3596 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3597 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3598 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3599 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3600 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3601 .features[FEAT_VMX_EXIT_CTLS] =
3602 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3603 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3604 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3605 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3606 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3607 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3608 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3609 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3610 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3611 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3612 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3613 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3614 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3615 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3616 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3617 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3618 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3619 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3620 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3621 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3622 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3623 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3624 .features[FEAT_VMX_SECONDARY_CTLS] =
3625 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3626 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3627 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3628 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3629 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3630 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3631 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3632 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3633 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3634 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3635 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
0b18874b
PL		 3636 .xlevel = 0x80000008,
3637 .model_id = "Intel Atom Processor (SnowRidge)",
69edb0f3
XL		 3638 .versions = (X86CPUVersionDefinition[]) {
3639 { .version = 1 },
3640 {
3641 .version = 2,
3642 .props = (PropValue[]) {
3643 { "mpx", "off" },
3644 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3645 { /* end of list */ },
3646 },
3647 },
7bde6b18
VK		 3648 {
3649 .version = 3,
3650 .note = "XSAVES, no MPX",
3651 .props = (PropValue[]) {
3652 { "xsaves", "on" },
3653 { "vmx-xsaves", "on" },
3654 { /* end of list */ },
3655 },
3656 },
56bb24e5
CQ		 3657 {
3658 .version = 4,
07db29f2 3659 .note = "no split lock detect, no core-capability",
56bb24e5
CQ		 3660 .props = (PropValue[]) {
3661 { "split-lock-detect", "off" },
07db29f2 3662 { "core-capability", "off" },
56bb24e5
CQ		 3663 { /* end of list */ },
3664 },
3665 },
69edb0f3
XL		 3666 { /* end of list */ },
3667 },
0b18874b 3668 },
a1849515
BF		 3669 {
3670 .name = "KnightsMill",
3671 .level = 0xd,
3672 .vendor = CPUID_VENDOR_INTEL,
3673 .family = 6,
3674 .model = 133,
3675 .stepping = 0,
3676 .features[FEAT_1_EDX] =
3677 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
3678 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
3679 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
3680 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
3681 CPUID_PSE | CPUID_DE | CPUID_FP87,
3682 .features[FEAT_1_ECX] =
3683 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3684 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3685 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3686 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3687 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3688 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3689 .features[FEAT_8000_0001_EDX] =
3690 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3691 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3692 .features[FEAT_8000_0001_ECX] =
3693 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3694 .features[FEAT_7_0_EBX] =
3695 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3696 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
3697 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
3698 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
3699 CPUID_7_0_EBX_AVX512ER,
3700 .features[FEAT_7_0_ECX] =
3701 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3702 .features[FEAT_7_0_EDX] =
3703 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
3704 .features[FEAT_XSAVE] =
3705 CPUID_XSAVE_XSAVEOPT,
3706 .features[FEAT_6_EAX] =
3707 CPUID_6_EAX_ARAT,
3708 .xlevel = 0x80000008,
3709 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
3710 },
3eca4642
EH		 3711 {
3712 .name = "Opteron_G1",
3713 .level = 5,
99b88a17 3714 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3715 .family = 15,
3716 .model = 6,
3717 .stepping = 1,
0514ef2f 3718 .features[FEAT_1_EDX] =
b3a4f0b1 3719 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3720 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3721 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3722 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3723 CPUID_DE | CPUID_FP87,
0514ef2f 3724 .features[FEAT_1_ECX] =
27861ecc 3725 CPUID_EXT_SSE3,
0514ef2f 3726 .features[FEAT_8000_0001_EDX] =
2a923a29 3727 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 3728 .xlevel = 0x80000008,
3729 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
3730 },
3731 {
3732 .name = "Opteron_G2",
3733 .level = 5,
99b88a17 3734 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3735 .family = 15,
3736 .model = 6,
3737 .stepping = 1,
0514ef2f 3738 .features[FEAT_1_EDX] =
b3a4f0b1 3739 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3740 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3741 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3742 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3743 CPUID_DE | CPUID_FP87,
0514ef2f 3744 .features[FEAT_1_ECX] =
27861ecc 3745 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 3746 .features[FEAT_8000_0001_EDX] =
2a923a29 3747 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 3748 .features[FEAT_8000_0001_ECX] =
27861ecc 3749 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 3750 .xlevel = 0x80000008,
3751 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
3752 },
3753 {
3754 .name = "Opteron_G3",
3755 .level = 5,
99b88a17 3756 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 3757 .family = 16,
3758 .model = 2,
3759 .stepping = 3,
0514ef2f 3760 .features[FEAT_1_EDX] =
b3a4f0b1 3761 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3762 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3763 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3764 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3765 CPUID_DE | CPUID_FP87,
0514ef2f 3766 .features[FEAT_1_ECX] =
27861ecc 3767 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 3768 CPUID_EXT_SSE3,
0514ef2f 3769 .features[FEAT_8000_0001_EDX] =
483c6ad4
BP		 3770 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
3771 CPUID_EXT2_RDTSCP,
0514ef2f 3772 .features[FEAT_8000_0001_ECX] =
27861ecc 3773 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 3774 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 3775 .xlevel = 0x80000008,
3776 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
3777 },
3778 {
3779 .name = "Opteron_G4",
3780 .level = 0xd,
99b88a17 3781 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3782 .family = 21,
3783 .model = 1,
3784 .stepping = 2,
0514ef2f 3785 .features[FEAT_1_EDX] =
b3a4f0b1 3786 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3787 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3788 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3789 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3790 CPUID_DE | CPUID_FP87,
0514ef2f 3791 .features[FEAT_1_ECX] =
27861ecc 3792 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 3793 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3794 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
3795 CPUID_EXT_SSE3,
0514ef2f 3796 .features[FEAT_8000_0001_EDX] =
2a923a29 3797 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 3798 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 3799 .features[FEAT_8000_0001_ECX] =
27861ecc 3800 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 3801 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3802 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3803 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 3804 .features[FEAT_SVM] =
3805 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 3806 /* no xsaveopt! */
3eca4642
EH		 3807 .xlevel = 0x8000001A,
3808 .model_id = "AMD Opteron 62xx class CPU",
3809 },
021941b9
AP		 3810 {
3811 .name = "Opteron_G5",
3812 .level = 0xd,
99b88a17 3813 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 3814 .family = 21,
3815 .model = 2,
3816 .stepping = 0,
0514ef2f 3817 .features[FEAT_1_EDX] =
b3a4f0b1 3818 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3819 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3820 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3821 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3822 CPUID_DE | CPUID_FP87,
0514ef2f 3823 .features[FEAT_1_ECX] =
27861ecc 3824 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 3825 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3826 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
3827 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 3828 .features[FEAT_8000_0001_EDX] =
2a923a29 3829 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 3830 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 3831 .features[FEAT_8000_0001_ECX] =
27861ecc 3832 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 3833 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3834 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3835 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 3836 .features[FEAT_SVM] =
3837 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 3838 /* no xsaveopt! */
021941b9
AP		 3839 .xlevel = 0x8000001A,
3840 .model_id = "AMD Opteron 63xx class CPU",
3841 },
2e2efc7d
BS		 3842 {
3843 .name = "EPYC",
3844 .level = 0xd,
3845 .vendor = CPUID_VENDOR_AMD,
3846 .family = 23,
3847 .model = 1,
3848 .stepping = 2,
3849 .features[FEAT_1_EDX] =
3850 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3851 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3852 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3853 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3854 CPUID_VME | CPUID_FP87,
3855 .features[FEAT_1_ECX] =
3856 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3857 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
3858 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3859 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3860 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3861 .features[FEAT_8000_0001_EDX] =
3862 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3863 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3864 CPUID_EXT2_SYSCALL,
3865 .features[FEAT_8000_0001_ECX] =
3866 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3867 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 3868 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3869 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 3870 .features[FEAT_7_0_EBX] =
3871 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3872 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3873 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3874 CPUID_7_0_EBX_SHA_NI,
2e2efc7d
BS		 3875 .features[FEAT_XSAVE] =
3876 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3877 CPUID_XSAVE_XGETBV1,
3878 .features[FEAT_6_EAX] =
3879 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 3880 .features[FEAT_SVM] =
3881 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 3882 .xlevel = 0x8000001E,
2e2efc7d 3883 .model_id = "AMD EPYC Processor",
fe52acd2 3884 .cache_info = &epyc_cache_info,
d86a7088
EH		 3885 .versions = (X86CPUVersionDefinition[]) {
3886 { .version = 1 },
3887 {
3888 .version = 2,
53db89d9 3889 .alias = "EPYC-IBPB",
d86a7088
EH		 3890 .props = (PropValue[]) {
3891 { "ibpb", "on" },
3892 { "model-id",
3893 "AMD EPYC Processor (with IBPB)" },
3894 { /* end of list */ }
3895 }
3896 },
a16e8dbc
MB		 3897 {
3898 .version = 3,
3899 .props = (PropValue[]) {
3900 { "ibpb", "on" },
3901 { "perfctr-core", "on" },
3902 { "clzero", "on" },
3903 { "xsaveerptr", "on" },
3904 { "xsaves", "on" },
3905 { "model-id",
3906 "AMD EPYC Processor" },
3907 { /* end of list */ }
3908 }
3909 },
d86a7088
EH		 3910 { /* end of list */ }
3911 }
2e2efc7d 3912 },
8d031cec
PW		 3913 {
3914 .name = "Dhyana",
3915 .level = 0xd,
3916 .vendor = CPUID_VENDOR_HYGON,
3917 .family = 24,
3918 .model = 0,
3919 .stepping = 1,
3920 .features[FEAT_1_EDX] =
3921 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3922 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3923 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3924 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3925 CPUID_VME | CPUID_FP87,
3926 .features[FEAT_1_ECX] =
3927 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3928 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
3929 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3930 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3931 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
3932 .features[FEAT_8000_0001_EDX] =
3933 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3934 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3935 CPUID_EXT2_SYSCALL,
3936 .features[FEAT_8000_0001_ECX] =
3937 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3938 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
3939 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3940 CPUID_EXT3_TOPOEXT,
3941 .features[FEAT_8000_0008_EBX] =
3942 CPUID_8000_0008_EBX_IBPB,
3943 .features[FEAT_7_0_EBX] =
3944 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3945 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3946 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
7bde6b18 3947 /* XSAVES is added in version 2 */
8d031cec
PW		 3948 .features[FEAT_XSAVE] =
3949 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3950 CPUID_XSAVE_XGETBV1,
3951 .features[FEAT_6_EAX] =
3952 CPUID_6_EAX_ARAT,
3953 .features[FEAT_SVM] =
3954 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3955 .xlevel = 0x8000001E,
3956 .model_id = "Hygon Dhyana Processor",
3957 .cache_info = &epyc_cache_info,
7bde6b18
VK		 3958 .versions = (X86CPUVersionDefinition[]) {
3959 { .version = 1 },
3960 { .version = 2,
3961 .note = "XSAVES",
3962 .props = (PropValue[]) {
3963 { "xsaves", "on" },
3964 { /* end of list */ }
3965 },
3966 },
3967 { /* end of list */ }
3968 }
8d031cec 3969 },
143c30d4
MB		 3970 {
3971 .name = "EPYC-Rome",
3972 .level = 0xd,
3973 .vendor = CPUID_VENDOR_AMD,
3974 .family = 23,
3975 .model = 49,
3976 .stepping = 0,
3977 .features[FEAT_1_EDX] =
3978 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3979 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3980 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3981 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3982 CPUID_VME | CPUID_FP87,
3983 .features[FEAT_1_ECX] =
3984 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3985 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
3986 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3987 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3988 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3989 .features[FEAT_8000_0001_EDX] =
3990 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3991 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3992 CPUID_EXT2_SYSCALL,
3993 .features[FEAT_8000_0001_ECX] =
3994 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3995 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
3996 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3997 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
3998 .features[FEAT_8000_0008_EBX] =
3999 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4000 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4001 CPUID_8000_0008_EBX_STIBP,
4002 .features[FEAT_7_0_EBX] =
4003 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4004 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4005 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4006 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4007 .features[FEAT_7_0_ECX] =
4008 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4009 .features[FEAT_XSAVE] =
4010 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4011 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4012 .features[FEAT_6_EAX] =
4013 CPUID_6_EAX_ARAT,
4014 .features[FEAT_SVM] =
4015 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4016 .xlevel = 0x8000001E,
4017 .model_id = "AMD EPYC-Rome Processor",
4018 .cache_info = &epyc_rome_cache_info,
cdeaed27
BM		 4019 .versions = (X86CPUVersionDefinition[]) {
4020 { .version = 1 },
4021 {
4022 .version = 2,
4023 .props = (PropValue[]) {
4024 { "ibrs", "on" },
4025 { "amd-ssbd", "on" },
4026 { /* end of list */ }
4027 }
4028 },
4029 { /* end of list */ }
4030 }
143c30d4 4031 },
623972ce
BM		 4032 {
4033 .name = "EPYC-Milan",
4034 .level = 0xd,
4035 .vendor = CPUID_VENDOR_AMD,
4036 .family = 25,
4037 .model = 1,
4038 .stepping = 1,
4039 .features[FEAT_1_EDX] =
4040 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4041 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4042 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4043 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4044 CPUID_VME | CPUID_FP87,
4045 .features[FEAT_1_ECX] =
4046 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4047 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4048 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4049 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4050 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
4051 CPUID_EXT_PCID,
4052 .features[FEAT_8000_0001_EDX] =
4053 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4054 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4055 CPUID_EXT2_SYSCALL,
4056 .features[FEAT_8000_0001_ECX] =
4057 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4058 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4059 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4060 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4061 .features[FEAT_8000_0008_EBX] =
4062 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4063 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4064 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
4065 CPUID_8000_0008_EBX_AMD_SSBD,
4066 .features[FEAT_7_0_EBX] =
4067 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4068 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4069 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4070 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS |
4071 CPUID_7_0_EBX_INVPCID,
4072 .features[FEAT_7_0_ECX] =
4073 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU,
4074 .features[FEAT_7_0_EDX] =
4075 CPUID_7_0_EDX_FSRM,
4076 .features[FEAT_XSAVE] =
4077 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4078 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4079 .features[FEAT_6_EAX] =
4080 CPUID_6_EAX_ARAT,
4081 .features[FEAT_SVM] =
4082 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK,
4083 .xlevel = 0x8000001E,
4084 .model_id = "AMD EPYC-Milan Processor",
4085 .cache_info = &epyc_milan_cache_info,
4086 },
c6dc6f63
AP		 4087};
4088
ad183928
EH		 4089/*
4090 * We resolve CPU model aliases using -v1 when using "-machine
4091 * none", but this is just for compatibility while libvirt isn't
4092 * adapted to resolve CPU model versions before creating VMs.
32048d72 4093 * See "Runnability guarantee of CPU models" at
a476b216 4094 * docs/about/deprecated.rst.
ad183928
EH		 4095 */
4096X86CPUVersion default_cpu_version = 1;
0788a56b
EH		 4097
4098void x86_cpu_set_default_version(X86CPUVersion version)
4099{
4100 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4101 assert(version != CPU_VERSION_AUTO);
4102 default_cpu_version = version;
4103}
4104
dcafd1ef
EH		 4105static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4106{
4107 int v = 0;
4108 const X86CPUVersionDefinition *vdef =
4109 x86_cpu_def_get_versions(model->cpudef);
4110 while (vdef->version) {
4111 v = vdef->version;
4112 vdef++;
4113 }
4114 return v;
4115}
4116
4117/* Return the actual version being used for a specific CPU model */
4118static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4119{
4120 X86CPUVersion v = model->version;
0788a56b
EH		 4121 if (v == CPU_VERSION_AUTO) {
4122 v = default_cpu_version;
4123 }
dcafd1ef
EH		 4124 if (v == CPU_VERSION_LATEST) {
4125 return x86_cpu_model_last_version(model);
4126 }
4127 return v;
4128}
4129
c62f2630 4130static Property max_x86_cpu_properties[] = {
120eee7d 4131 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 4132 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 4133 DEFINE_PROP_END_OF_LIST()
4134};
4135
c62f2630 4136static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 4137{
84f1b92f 4138 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 4139 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 4140
f48c8837 4141 xcc->ordering = 9;
6e746f30 4142
ee465a3e 4143 xcc->model_description =
c62f2630 4144 "Enables all features supported by the accelerator in the current host";
d940ee9b 4145
4f67d30b 4146 device_class_set_props(dc, max_x86_cpu_properties);
d940ee9b
EH		 4147}
4148
c62f2630 4149static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 4150{
4151 X86CPU *cpu = X86_CPU(obj);
d940ee9b 4152
4d1b279b
EH		 4153 /* We can't fill the features array here because we don't know yet if
4154 * "migratable" is true or false.
4155 */
44bd8e53 4156 cpu->max_features = true;
5325cc34 4157 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
f5cc5a5c
CF		 4158
4159 /*
4160 * these defaults are used for TCG and all other accelerators
4161 * besides KVM and HVF, which overwrite these values
4162 */
4163 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
4164 &error_abort);
40b3cc35
DB		 4165#ifdef TARGET_X86_64
4166 object_property_set_int(OBJECT(cpu), "family", 15, &error_abort);
4167 object_property_set_int(OBJECT(cpu), "model", 107, &error_abort);
4168 object_property_set_int(OBJECT(cpu), "stepping", 1, &error_abort);
4169#else
f5cc5a5c
CF		 4170 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
4171 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
4172 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
40b3cc35 4173#endif
f5cc5a5c
CF		 4174 object_property_set_str(OBJECT(cpu), "model-id",
4175 "QEMU TCG CPU version " QEMU_HW_VERSION,
4176 &error_abort);
c6dc6f63
AP		 4177}
4178
c62f2630
EH		 4179static const TypeInfo max_x86_cpu_type_info = {
4180 .name = X86_CPU_TYPE_NAME("max"),
4181 .parent = TYPE_X86_CPU,
4182 .instance_init = max_x86_cpu_initfn,
4183 .class_init = max_x86_cpu_class_init,
4184};
4185
07585923
RH		 4186static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4187{
4188 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4189
4190 switch (f->type) {
4191 case CPUID_FEATURE_WORD:
4192 {
4193 const char *reg = get_register_name_32(f->cpuid.reg);
4194 assert(reg);
4195 return g_strdup_printf("CPUID.%02XH:%s",
4196 f->cpuid.eax, reg);
4197 }
4198 case MSR_FEATURE_WORD:
4199 return g_strdup_printf("MSR(%02XH)",
4200 f->msr.index);
4201 }
4202
4203 return NULL;
4204}
4205
245edd0c 4206static bool x86_cpu_have_filtered_features(X86CPU *cpu)
c6dc6f63 4207{
245edd0c
PB		 4208 FeatureWord w;
4209
4210 for (w = 0; w < FEATURE_WORDS; w++) {
4211 if (cpu->filtered_features[w]) {
4212 return true;
4213 }
4214 }
4215
4216 return false;
4217}
4218
ede146c2 4219static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
245edd0c
PB		 4220 const char *verbose_prefix)
4221{
4222 CPUX86State *env = &cpu->env;
8459e396 4223 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 4224 int i;
4225
245edd0c
PB		 4226 if (!cpu->force_features) {
4227 env->features[w] &= ~mask;
4228 }
4229 cpu->filtered_features[w] |= mask;
4230
4231 if (!verbose_prefix) {
4232 return;
4233 }
4234
ede146c2
PB		 4235 for (i = 0; i < 64; ++i) {
4236 if ((1ULL << i) & mask) {
88703ce2 4237 g_autofree char *feat_word_str = feature_word_description(f, i);
245edd0c
PB		 4238 warn_report("%s: %s%s%s [bit %d]",
4239 verbose_prefix,
07585923 4240 feat_word_str,
8297be80
AF		 4241 f->feat_names[i] ? "." : "",
4242 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 4243 }
857aee33 4244 }
c6dc6f63
AP		 4245}
4246
d7bce999
EB		 4247static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4248 const char *name, void *opaque,
4249 Error **errp)
95b8519d
AF		 4250{
4251 X86CPU *cpu = X86_CPU(obj);
4252 CPUX86State *env = &cpu->env;
4253 int64_t value;
4254
4255 value = (env->cpuid_version >> 8) & 0xf;
4256 if (value == 0xf) {
4257 value += (env->cpuid_version >> 20) & 0xff;
4258 }
51e72bc1 4259 visit_type_int(v, name, &value, errp);
95b8519d
AF		 4260}
4261
d7bce999
EB		 4262static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4263 const char *name, void *opaque,
4264 Error **errp)
ed5e1ec3 4265{
71ad61d3
AF		 4266 X86CPU *cpu = X86_CPU(obj);
4267 CPUX86State *env = &cpu->env;
4268 const int64_t min = 0;
4269 const int64_t max = 0xff + 0xf;
4270 int64_t value;
4271
668f62ec 4272 if (!visit_type_int(v, name, &value, errp)) {
71ad61d3
AF		 4273 return;
4274 }
4275 if (value < min || value > max) {
c6bd8c70
MA		 4276 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4277 name ? name : "null", value, min, max);
71ad61d3
AF		 4278 return;
4279 }
4280
ed5e1ec3 4281 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 4282 if (value > 0x0f) {
4283 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 4284 } else {
71ad61d3 4285 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 4286 }
4287}
4288
d7bce999
EB		 4289static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4290 const char *name, void *opaque,
4291 Error **errp)
67e30c83
AF		 4292{
4293 X86CPU *cpu = X86_CPU(obj);
4294 CPUX86State *env = &cpu->env;
4295 int64_t value;
4296
4297 value = (env->cpuid_version >> 4) & 0xf;
4298 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 4299 visit_type_int(v, name, &value, errp);
67e30c83
AF		 4300}
4301
d7bce999
EB		 4302static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4303 const char *name, void *opaque,
4304 Error **errp)
b0704cbd 4305{
c5291a4f
AF		 4306 X86CPU *cpu = X86_CPU(obj);
4307 CPUX86State *env = &cpu->env;
4308 const int64_t min = 0;
4309 const int64_t max = 0xff;
4310 int64_t value;
4311
668f62ec 4312 if (!visit_type_int(v, name, &value, errp)) {
c5291a4f
AF		 4313 return;
4314 }
4315 if (value < min || value > max) {
c6bd8c70
MA		 4316 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4317 name ? name : "null", value, min, max);
c5291a4f
AF		 4318 return;
4319 }
4320
b0704cbd 4321 env->cpuid_version &= ~0xf00f0;
c5291a4f 4322 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 4323}
4324
35112e41 4325static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 4326 const char *name, void *opaque,
35112e41
AF		 4327 Error **errp)
4328{
4329 X86CPU *cpu = X86_CPU(obj);
4330 CPUX86State *env = &cpu->env;
4331 int64_t value;
4332
4333 value = env->cpuid_version & 0xf;
51e72bc1 4334 visit_type_int(v, name, &value, errp);
35112e41
AF		 4335}
4336
036e2222 4337static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 4338 const char *name, void *opaque,
036e2222 4339 Error **errp)
38c3dc46 4340{
036e2222
AF		 4341 X86CPU *cpu = X86_CPU(obj);
4342 CPUX86State *env = &cpu->env;
4343 const int64_t min = 0;
4344 const int64_t max = 0xf;
4345 int64_t value;
4346
668f62ec 4347 if (!visit_type_int(v, name, &value, errp)) {
036e2222
AF		 4348 return;
4349 }
4350 if (value < min || value > max) {
c6bd8c70
MA		 4351 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4352 name ? name : "null", value, min, max);
036e2222
AF		 4353 return;
4354 }
4355
38c3dc46 4356 env->cpuid_version &= ~0xf;
036e2222 4357 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 4358}
4359
d480e1af
AF		 4360static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4361{
4362 X86CPU *cpu = X86_CPU(obj);
4363 CPUX86State *env = &cpu->env;
4364 char *value;
d480e1af 4365
e42a92ae 4366 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 4367 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4368 env->cpuid_vendor3);
d480e1af
AF		 4369 return value;
4370}
4371
4372static void x86_cpuid_set_vendor(Object *obj, const char *value,
4373 Error **errp)
4374{
4375 X86CPU *cpu = X86_CPU(obj);
4376 CPUX86State *env = &cpu->env;
4377 int i;
4378
9df694ee 4379 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 4380 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 4381 return;
4382 }
4383
4384 env->cpuid_vendor1 = 0;
4385 env->cpuid_vendor2 = 0;
4386 env->cpuid_vendor3 = 0;
4387 for (i = 0; i < 4; i++) {
4388 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
4389 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4390 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4391 }
d480e1af
AF		 4392}
4393
63e886eb
AF		 4394static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4395{
4396 X86CPU *cpu = X86_CPU(obj);
4397 CPUX86State *env = &cpu->env;
4398 char *value;
4399 int i;
4400
4401 value = g_malloc(48 + 1);
4402 for (i = 0; i < 48; i++) {
4403 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4404 }
4405 value[48] = '\0';
4406 return value;
4407}
4408
938d4c25
AF		 4409static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4410 Error **errp)
dcce6675 4411{
938d4c25
AF		 4412 X86CPU *cpu = X86_CPU(obj);
4413 CPUX86State *env = &cpu->env;
dcce6675
AF		 4414 int c, len, i;
4415
4416 if (model_id == NULL) {
4417 model_id = "";
4418 }
4419 len = strlen(model_id);
d0a6acf4 4420 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 4421 for (i = 0; i < 48; i++) {
4422 if (i >= len) {
4423 c = '\0';
4424 } else {
4425 c = (uint8_t)model_id[i];
4426 }
4427 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4428 }
4429}
4430
d7bce999
EB		 4431static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4432 void *opaque, Error **errp)
89e48965
AF		 4433{
4434 X86CPU *cpu = X86_CPU(obj);
4435 int64_t value;
4436
4437 value = cpu->env.tsc_khz * 1000;
51e72bc1 4438 visit_type_int(v, name, &value, errp);
89e48965
AF		 4439}
4440
d7bce999
EB		 4441static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
4442 void *opaque, Error **errp)
89e48965
AF		 4443{
4444 X86CPU *cpu = X86_CPU(obj);
4445 const int64_t min = 0;
2e84849a 4446 const int64_t max = INT64_MAX;
89e48965
AF		 4447 int64_t value;
4448
668f62ec 4449 if (!visit_type_int(v, name, &value, errp)) {
89e48965
AF		 4450 return;
4451 }
4452 if (value < min || value > max) {
c6bd8c70
MA		 4453 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4454 name ? name : "null", value, min, max);
89e48965
AF		 4455 return;
4456 }
4457
36f96c4b 4458 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 4459}
4460
7e5292b5 4461/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 4462static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
4463 const char *name, void *opaque,
4464 Error **errp)
8e8aba50 4465{
ede146c2 4466 uint64_t *array = (uint64_t *)opaque;
8e8aba50 4467 FeatureWord w;
8e8aba50
EH		 4468 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
4469 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
4470 X86CPUFeatureWordInfoList *list = NULL;
4471
4472 for (w = 0; w < FEATURE_WORDS; w++) {
4473 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 4474 /*
4475 * We didn't have MSR features when "feature-words" was
4476 * introduced. Therefore skipped other type entries.
4477 */
4478 if (wi->type != CPUID_FEATURE_WORD) {
4479 continue;
4480 }
8e8aba50 4481 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 4482 qwi->cpuid_input_eax = wi->cpuid.eax;
4483 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
4484 qwi->cpuid_input_ecx = wi->cpuid.ecx;
4485 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 4486 qwi->features = array[w];
8e8aba50
EH		 4487
4488 /* List will be in reverse order, but order shouldn't matter */
4489 list_entries[w].next = list;
4490 list_entries[w].value = &word_infos[w];
4491 list = &list_entries[w];
4492 }
4493
6b62d961 4494 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 4495}
4496
72ac2e87
IM		 4497/* Convert all '_' in a feature string option name to '-', to make feature
4498 * name conform to QOM property naming rule, which uses '-' instead of '_'.
4499 */
4500static inline void feat2prop(char *s)
4501{
4502 while ((s = strchr(s, '_'))) {
4503 *s = '-';
4504 }
4505}
4506
b54c9377
EH		 4507/* Return the feature property name for a feature flag bit */
4508static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
4509{
ede146c2 4510 const char *name;
b54c9377
EH		 4511 /* XSAVE components are automatically enabled by other features,
4512 * so return the original feature name instead
4513 */
4514 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
4515 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
4516
4517 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
4518 x86_ext_save_areas[comp].bits) {
4519 w = x86_ext_save_areas[comp].feature;
4520 bitnr = ctz32(x86_ext_save_areas[comp].bits);
4521 }
4522 }
4523
ede146c2 4524 assert(bitnr < 64);
b54c9377 4525 assert(w < FEATURE_WORDS);
ede146c2
PB		 4526 name = feature_word_info[w].feat_names[bitnr];
4527 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
4528 return name;
b54c9377
EH		 4529}
4530
dc15c051
IM		 4531/* Compatibily hack to maintain legacy +-feat semantic,
4532 * where +-feat overwrites any feature set by
4533 * feat=on|feat even if the later is parsed after +-feat
4534 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4535 */
2fae0d96 4536static GList *plus_features, *minus_features;
dc15c051 4537
83a00f60
EH		 4538static gint compare_string(gconstpointer a, gconstpointer b)
4539{
4540 return g_strcmp0(a, b);
4541}
4542
8f961357
EH		 4543/* Parse "+feature,-feature,feature=foo" CPU feature string
4544 */
62a48a2a 4545static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 4546 Error **errp)
8f961357 4547{
8f961357 4548 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 4549 static bool cpu_globals_initialized;
83a00f60 4550 bool ambiguous = false;
62a48a2a
IM		 4551
4552 if (cpu_globals_initialized) {
4553 return;
4554 }
4555 cpu_globals_initialized = true;
8f961357 4556
f6750e95
EH		 4557 if (!features) {
4558 return;
4559 }
4560
4561 for (featurestr = strtok(features, ",");
685479bd 4562 featurestr;
f6750e95
EH		 4563 featurestr = strtok(NULL, ",")) {
4564 const char *name;
4565 const char *val = NULL;
4566 char *eq = NULL;
cf2887c9 4567 char num[32];
62a48a2a 4568 GlobalProperty *prop;
c6dc6f63 4569
f6750e95 4570 /* Compatibility syntax: */
c6dc6f63 4571 if (featurestr[0] == '+') {
2fae0d96
EH		 4572 plus_features = g_list_append(plus_features,
4573 g_strdup(featurestr + 1));
f6750e95 4574 continue;
c6dc6f63 4575 } else if (featurestr[0] == '-') {
2fae0d96
EH		 4576 minus_features = g_list_append(minus_features,
4577 g_strdup(featurestr + 1));
f6750e95
EH		 4578 continue;
4579 }
4580
4581 eq = strchr(featurestr, '=');
4582 if (eq) {
4583 *eq++ = 0;
4584 val = eq;
c6dc6f63 4585 } else {
f6750e95 4586 val = "on";
a91987c2 4587 }
f6750e95
EH		 4588
4589 feat2prop(featurestr);
4590 name = featurestr;
4591
83a00f60 4592 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 4593 warn_report("Ambiguous CPU model string. "
4594 "Don't mix both \"+%s\" and \"%s=%s\"",
4595 name, name, val);
83a00f60
EH		 4596 ambiguous = true;
4597 }
4598 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 4599 warn_report("Ambiguous CPU model string. "
4600 "Don't mix both \"-%s\" and \"%s=%s\"",
4601 name, name, val);
83a00f60
EH		 4602 ambiguous = true;
4603 }
4604
f6750e95
EH		 4605 /* Special case: */
4606 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 4607 int ret;
f46bfdbf 4608 uint64_t tsc_freq;
f6750e95 4609
f17fd4fd 4610 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 4611 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 4612 error_setg(errp, "bad numerical value %s", val);
4613 return;
4614 }
4615 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
4616 val = num;
4617 name = "tsc-frequency";
c6dc6f63 4618 }
f6750e95 4619
62a48a2a
IM		 4620 prop = g_new0(typeof(*prop), 1);
4621 prop->driver = typename;
4622 prop->property = g_strdup(name);
4623 prop->value = g_strdup(val);
62a48a2a 4624 qdev_prop_register_global(prop);
f6750e95
EH		 4625 }
4626
83a00f60 4627 if (ambiguous) {
3dc6f869
AF		 4628 warn_report("Compatibility of ambiguous CPU model "
4629 "strings won't be kept on future QEMU versions");
83a00f60 4630 }
c6dc6f63
AP		 4631}
4632
245edd0c 4633static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
b54c9377 4634
5a853fc5
EH		 4635/* Build a list with the name of all features on a feature word array */
4636static void x86_cpu_list_feature_names(FeatureWordArray features,
c3033fd3 4637 strList **list)
5a853fc5 4638{
c3033fd3 4639 strList **tail = list;
5a853fc5 4640 FeatureWord w;
5a853fc5
EH		 4641
4642 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 4643 uint64_t filtered = features[w];
5a853fc5 4644 int i;
ede146c2
PB		 4645 for (i = 0; i < 64; i++) {
4646 if (filtered & (1ULL << i)) {
c3033fd3 4647 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i)));
5a853fc5
EH		 4648 }
4649 }
4650 }
4651}
4652
506174bf
EH		 4653static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
4654 const char *name, void *opaque,
4655 Error **errp)
4656{
4657 X86CPU *xc = X86_CPU(obj);
4658 strList *result = NULL;
4659
4660 x86_cpu_list_feature_names(xc->filtered_features, &result);
4661 visit_type_strList(v, "unavailable-features", &result, errp);
4662}
4663
b54c9377
EH		 4664/* Check for missing features that may prevent the CPU class from
4665 * running using the current machine and accelerator.
4666 */
4667static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
c3033fd3 4668 strList **list)
b54c9377 4669{
c3033fd3 4670 strList **tail = list;
b54c9377 4671 X86CPU *xc;
b54c9377 4672 Error *err = NULL;
b54c9377 4673
d6dcc558 4674 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
c3033fd3 4675 QAPI_LIST_APPEND(tail, g_strdup("kvm"));
b54c9377
EH		 4676 return;
4677 }
4678
3c75e12e 4679 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
b54c9377 4680
b8d834a0 4681 x86_cpu_expand_features(xc, &err);
b54c9377 4682 if (err) {
b8d834a0 4683 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 4684 * but in case it does, just report the model as not
4685 * runnable at all using the "type" property.
4686 */
c3033fd3 4687 QAPI_LIST_APPEND(tail, g_strdup("type"));
3aa8203e 4688 error_free(err);
b54c9377
EH		 4689 }
4690
245edd0c 4691 x86_cpu_filter_features(xc, false);
b54c9377 4692
c3033fd3 4693 x86_cpu_list_feature_names(xc->filtered_features, tail);
b54c9377
EH		 4694
4695 object_unref(OBJECT(xc));
4696}
4697
8c3329e5 4698/* Print all cpuid feature names in featureset
c6dc6f63 4699 */
0442428a 4700static void listflags(GList *features)
0856579c 4701{
cc643b1e
DB		 4702 size_t len = 0;
4703 GList *tmp;
4704
4705 for (tmp = features; tmp; tmp = tmp->next) {
4706 const char *name = tmp->data;
4707 if ((len + strlen(name) + 1) >= 75) {
0442428a 4708 qemu_printf("\n");
cc643b1e 4709 len = 0;
c6dc6f63 4710 }
0442428a 4711 qemu_printf("%s%s", len == 0 ? " " : " ", name);
cc643b1e 4712 len += strlen(name) + 1;
8c3329e5 4713 }
0442428a 4714 qemu_printf("\n");
c6dc6f63
AP		 4715}
4716
f48c8837 4717/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 4718static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
4719{
4720 ObjectClass *class_a = (ObjectClass *)a;
4721 ObjectClass *class_b = (ObjectClass *)b;
4722 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
4723 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b 4724 int ret;
ee465a3e 4725
f48c8837 4726 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 4727 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 4728 } else {
88703ce2
EH		 4729 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
4730 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
c7dbff4b 4731 ret = strcmp(name_a, name_b);
ee465a3e 4732 }
c7dbff4b 4733 return ret;
ee465a3e
EH		 4734}
4735
4736static GSList *get_sorted_cpu_model_list(void)
4737{
4738 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
4739 list = g_slist_sort(list, x86_cpu_list_compare);
4740 return list;
4741}
4742
164e779c
EH		 4743static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
4744{
3c75e12e 4745 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
164e779c
EH		 4746 char *r = object_property_get_str(obj, "model-id", &error_abort);
4747 object_unref(obj);
4748 return r;
4749}
4750
0788a56b
EH		 4751static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
4752{
4753 X86CPUVersion version;
4754
4755 if (!cc->model || !cc->model->is_alias) {
4756 return NULL;
4757 }
4758 version = x86_cpu_model_resolve_version(cc->model);
4759 if (version <= 0) {
4760 return NULL;
4761 }
4762 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
4763}
4764
ee465a3e
EH		 4765static void x86_cpu_list_entry(gpointer data, gpointer user_data)
4766{
4767 ObjectClass *oc = data;
4768 X86CPUClass *cc = X86_CPU_CLASS(oc);
88703ce2
EH		 4769 g_autofree char *name = x86_cpu_class_get_model_name(cc);
4770 g_autofree char *desc = g_strdup(cc->model_description);
4771 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
c63938df 4772 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
164e779c 4773
0788a56b
EH		 4774 if (!desc && alias_of) {
4775 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
4776 desc = g_strdup("(alias configured by machine type)");
4777 } else {
4778 desc = g_strdup_printf("(alias of %s)", alias_of);
4779 }
4780 }
c63938df
TX		 4781 if (!desc && cc->model && cc->model->note) {
4782 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
4783 }
164e779c 4784 if (!desc) {
c63938df 4785 desc = g_strdup_printf("%s", model_id);
ee465a3e
EH		 4786 }
4787
61848717 4788 qemu_printf("x86 %-20s %s\n", name, desc);
ee465a3e
EH		 4789}
4790
4791/* list available CPU models and flags */
0442428a 4792void x86_cpu_list(void)
c6dc6f63 4793{
cc643b1e 4794 int i, j;
ee465a3e 4795 GSList *list;
cc643b1e 4796 GList *names = NULL;
c6dc6f63 4797
0442428a 4798 qemu_printf("Available CPUs:\n");
ee465a3e 4799 list = get_sorted_cpu_model_list();
0442428a 4800 g_slist_foreach(list, x86_cpu_list_entry, NULL);
ee465a3e 4801 g_slist_free(list);
21ad7789 4802
cc643b1e 4803 names = NULL;
3af60be2
JK		 4804 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
4805 FeatureWordInfo *fw = &feature_word_info[i];
ede146c2 4806 for (j = 0; j < 64; j++) {
cc643b1e
DB		 4807 if (fw->feat_names[j]) {
4808 names = g_list_append(names, (gpointer)fw->feat_names[j]);
4809 }
4810 }
3af60be2 4811 }
cc643b1e
DB		 4812
4813 names = g_list_sort(names, (GCompareFunc)strcmp);
4814
0442428a
MA		 4815 qemu_printf("\nRecognized CPUID flags:\n");
4816 listflags(names);
4817 qemu_printf("\n");
cc643b1e 4818 g_list_free(names);
c6dc6f63
AP		 4819}
4820
ee465a3e
EH		 4821static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
4822{
4823 ObjectClass *oc = data;
4824 X86CPUClass *cc = X86_CPU_CLASS(oc);
4825 CpuDefinitionInfoList **cpu_list = user_data;
ee465a3e
EH		 4826 CpuDefinitionInfo *info;
4827
4828 info = g_malloc0(sizeof(*info));
4829 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 4830 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
4831 info->has_unavailable_features = true;
8ed877b7 4832 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 4833 info->migration_safe = cc->migration_safe;
4834 info->has_migration_safe = true;
5adbed30 4835 info->q_static = cc->static_model;
61ad65d0
RH		 4836 if (cc->model && cc->model->cpudef->deprecation_note) {
4837 info->deprecated = true;
4838 } else {
4839 info->deprecated = false;
4840 }
0788a56b
EH		 4841 /*
4842 * Old machine types won't report aliases, so that alias translation
4843 * doesn't break compatibility with previous QEMU versions.
4844 */
4845 if (default_cpu_version != CPU_VERSION_LEGACY) {
4846 info->alias_of = x86_cpu_class_get_alias_of(cc);
4847 info->has_alias_of = !!info->alias_of;
4848 }
ee465a3e 4849
54aa3de7 4850 QAPI_LIST_PREPEND(*cpu_list, info);
ee465a3e
EH		 4851}
4852
25a9d6ca 4853CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
e3966126
AL		 4854{
4855 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 4856 GSList *list = get_sorted_cpu_model_list();
4857 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
4858 g_slist_free(list);
e3966126
AL		 4859 return cpu_list;
4860}
4861
58f7db26
PB		 4862uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
4863 bool migratable_only)
27418adf
EH		 4864{
4865 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 4866 uint64_t r = 0;
27418adf 4867
fefb41bf 4868 if (kvm_enabled()) {
07585923
RH		 4869 switch (wi->type) {
4870 case CPUID_FEATURE_WORD:
4871 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
4872 wi->cpuid.ecx,
4873 wi->cpuid.reg);
4874 break;
4875 case MSR_FEATURE_WORD:
d86f9636
RH		 4876 r = kvm_arch_get_supported_msr_feature(kvm_state,
4877 wi->msr.index);
07585923
RH		 4878 break;
4879 }
d6dcc558 4880 } else if (hvf_enabled()) {
07585923
RH		 4881 if (wi->type != CPUID_FEATURE_WORD) {
4882 return 0;
4883 }
4884 r = hvf_get_supported_cpuid(wi->cpuid.eax,
4885 wi->cpuid.ecx,
4886 wi->cpuid.reg);
fefb41bf 4887 } else if (tcg_enabled()) {
84f1b92f 4888 r = wi->tcg_features;
fefb41bf
EH		 4889 } else {
4890 return ~0;
4891 }
5ea9e9e2
PB		 4892#ifndef TARGET_X86_64
4893 if (w == FEAT_8000_0001_EDX) {
4894 r &= ~CPUID_EXT2_LM;
4895 }
4896#endif
84f1b92f
EH		 4897 if (migratable_only) {
4898 r &= x86_cpu_get_migratable_flags(w);
4899 }
4900 return r;
27418adf
EH		 4901}
4902
798d8ec0
PB		 4903static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index,
4904 uint32_t *eax, uint32_t *ebx,
4905 uint32_t *ecx, uint32_t *edx)
4906{
4907 uint32_t level, unused;
4908
4909 /* Only return valid host leaves. */
4910 switch (func) {
4911 case 2:
4912 case 4:
4913 host_cpuid(0, 0, &level, &unused, &unused, &unused);
4914 break;
4915 case 0x80000005:
4916 case 0x80000006:
4917 case 0x8000001d:
4918 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused);
4919 break;
4920 default:
4921 return;
4922 }
4923
4924 if (func > level) {
4925 *eax = 0;
4926 *ebx = 0;
4927 *ecx = 0;
4928 *edx = 0;
4929 } else {
4930 host_cpuid(func, index, eax, ebx, ecx, edx);
4931 }
4932}
4933
5b8978d8
CF		 4934/*
4935 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
4936 */
f5cc5a5c 4937void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5114e842
EH		 4938{
4939 PropValue *pv;
4940 for (pv = props; pv->prop; pv++) {
4941 if (!pv->value) {
4942 continue;
4943 }
5325cc34 4944 object_property_parse(OBJECT(cpu), pv->prop, pv->value,
5114e842
EH		 4945 &error_abort);
4946 }
4947}
4948
5b8978d8
CF		 4949/*
4950 * Apply properties for the CPU model version specified in model.
4951 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
4952 */
4953
dcafd1ef
EH		 4954static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
4955{
4956 const X86CPUVersionDefinition *vdef;
4957 X86CPUVersion version = x86_cpu_model_resolve_version(model);
4958
4959 if (version == CPU_VERSION_LEGACY) {
4960 return;
4961 }
4962
4963 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
4964 PropValue *p;
4965
4966 for (p = vdef->props; p && p->prop; p++) {
5325cc34 4967 object_property_parse(OBJECT(cpu), p->prop, p->value,
dcafd1ef
EH		 4968 &error_abort);
4969 }
4970
4971 if (vdef->version == version) {
4972 break;
4973 }
4974 }
4975
4976 /*
4977 * If we reached the end of the list, version number was invalid
4978 */
4979 assert(vdef->version == version);
4980}
4981
5b8978d8
CF		 4982/*
4983 * Load data from X86CPUDefinition into a X86CPU object.
4984 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
c080e30e 4985 */
49e2fa85 4986static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
c6dc6f63 4987{
e11fd689 4988 const X86CPUDefinition *def = model->cpudef;
61dcd775 4989 CPUX86State *env = &cpu->env;
e1c224b4 4990 FeatureWord w;
c6dc6f63 4991
f99fd7ca
EH		 4992 /*NOTE: any property set by this function should be returned by
4993 * x86_cpu_static_props(), so static expansion of
4994 * query-cpu-model-expansion is always complete.
4995 */
4996
c39c0edf 4997 /* CPU models only set _minimum_ values for level/xlevel: */
5325cc34 4998 object_property_set_uint(OBJECT(cpu), "min-level", def->level,
49e2fa85 4999 &error_abort);
5325cc34 5000 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
49e2fa85
MA		 5001 &error_abort);
5002
5325cc34
MA		 5003 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
5004 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
5005 object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
49e2fa85 5006 &error_abort);
5325cc34 5007 object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
49e2fa85 5008 &error_abort);
e1c224b4
EH		 5009 for (w = 0; w < FEATURE_WORDS; w++) {
5010 env->features[w] = def->features[w];
5011 }
82beb536 5012
a9f27ea9
EH		 5013 /* legacy-cache defaults to 'off' if CPU model provides cache info */
5014 cpu->legacy_cache = !def->cache_info;
ab8f992e 5015
82beb536 5016 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 5017
5018 /* sysenter isn't supported in compatibility mode on AMD,
5019 * syscall isn't supported in compatibility mode on Intel.
5020 * Normally we advertise the actual CPU vendor, but you can
5021 * override this using the 'vendor' property if you want to use
5022 * KVM's sysenter/syscall emulation in compatibility mode and
5023 * when doing cross vendor migration
5024 */
7c08db30 5025
f5cc5a5c
CF		 5026 /*
5027 * vendor property is set here but then overloaded with the
5028 * host cpu vendor for KVM and HVF.
5029 */
5030 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort);
7c08db30 5031
dcafd1ef 5032 x86_cpu_apply_version_props(cpu, model);
1f43671a
XL		 5033
5034 /*
5035 * Properties in versioned CPU model are not user specified features.
5036 * We can simply clear env->user_features here since it will be filled later
5037 * in x86_cpu_expand_features() based on plus_features and minus_features.
5038 */
5039 memset(&env->user_features, 0, sizeof(env->user_features));
c6dc6f63
AP		 5040}
5041
00fcd100
AB		 5042static gchar *x86_gdb_arch_name(CPUState *cs)
5043{
5044#ifdef TARGET_X86_64
5045 return g_strdup("i386:x86-64");
5046#else
5047 return g_strdup("i386");
5048#endif
5049}
5050
d940ee9b
EH		 5051static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5052{
dcafd1ef 5053 X86CPUModel *model = data;
d940ee9b 5054 X86CPUClass *xcc = X86_CPU_CLASS(oc);
61ad65d0 5055 CPUClass *cc = CPU_CLASS(oc);
d940ee9b 5056
dcafd1ef 5057 xcc->model = model;
bd72159d 5058 xcc->migration_safe = true;
61ad65d0 5059 cc->deprecation_note = model->cpudef->deprecation_note;
d940ee9b
EH		 5060}
5061
dcafd1ef 5062static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
d940ee9b 5063{
88703ce2 5064 g_autofree char *typename = x86_cpu_type_name(name);
d940ee9b
EH		 5065 TypeInfo ti = {
5066 .name = typename,
5067 .parent = TYPE_X86_CPU,
5068 .class_init = x86_cpu_cpudef_class_init,
dcafd1ef 5069 .class_data = model,
d940ee9b
EH		 5070 };
5071
dcafd1ef 5072 type_register(&ti);
dcafd1ef
EH		 5073}
5074
5b8978d8
CF		 5075
5076/*
5077 * register builtin_x86_defs;
5078 * "max", "base" and subclasses ("host") are not registered here.
5079 * See x86_cpu_register_types for all model registrations.
5080 */
e11fd689 5081static void x86_register_cpudef_types(const X86CPUDefinition *def)
dcafd1ef
EH		 5082{
5083 X86CPUModel *m;
5084 const X86CPUVersionDefinition *vdef;
dcafd1ef 5085
2a923a29
EH		 5086 /* AMD aliases are handled at runtime based on CPUID vendor, so
5087 * they shouldn't be set on the CPU model table.
5088 */
5089 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 5090 /* catch mistakes instead of silently truncating model_id when too long */
5091 assert(def->model_id && strlen(def->model_id) <= 48);
5092
dcafd1ef
EH		 5093 /* Unversioned model: */
5094 m = g_new0(X86CPUModel, 1);
5095 m->cpudef = def;
0788a56b
EH		 5096 m->version = CPU_VERSION_AUTO;
5097 m->is_alias = true;
dcafd1ef
EH		 5098 x86_register_cpu_model_type(def->name, m);
5099
5100 /* Versioned models: */
5101
5102 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5103 X86CPUModel *m = g_new0(X86CPUModel, 1);
88703ce2
EH		 5104 g_autofree char *name =
5105 x86_cpu_versioned_model_name(def, vdef->version);
dcafd1ef
EH		 5106 m->cpudef = def;
5107 m->version = vdef->version;
c63938df 5108 m->note = vdef->note;
dcafd1ef 5109 x86_register_cpu_model_type(name, m);
53db89d9
EH		 5110
5111 if (vdef->alias) {
5112 X86CPUModel *am = g_new0(X86CPUModel, 1);
5113 am->cpudef = def;
5114 am->version = vdef->version;
0788a56b 5115 am->is_alias = true;
53db89d9
EH		 5116 x86_register_cpu_model_type(vdef->alias, am);
5117 }
dcafd1ef 5118 }
2a923a29 5119
d940ee9b
EH		 5120}
5121
97afb47e
LL		 5122uint32_t cpu_x86_virtual_addr_width(CPUX86State *env)
5123{
5124 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5125 return 57; /* 57 bits virtual */
5126 } else {
5127 return 48; /* 48 bits virtual */
5128 }
5129}
5130
c6dc6f63
AP		 5131void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5132 uint32_t *eax, uint32_t *ebx,
5133 uint32_t *ecx, uint32_t *edx)
5134{
6aa9e42f
RH		 5135 X86CPU *cpu = env_archcpu(env);
5136 CPUState *cs = env_cpu(env);
d65af288 5137 uint32_t die_offset;
4ed3d478 5138 uint32_t limit;
1ce36bfe 5139 uint32_t signature[3];
f20dec0b
BM		 5140 X86CPUTopoInfo topo_info;
5141
5142 topo_info.dies_per_pkg = env->nr_dies;
5143 topo_info.cores_per_die = cs->nr_cores;
5144 topo_info.threads_per_core = cs->nr_threads;
a60f24b5 5145
4ed3d478
DB		 5146 /* Calculate & apply limits for different index ranges */
5147 if (index >= 0xC0000000) {
5148 limit = env->cpuid_xlevel2;
5149 } else if (index >= 0x80000000) {
5150 limit = env->cpuid_xlevel;
1ce36bfe
DB		 5151 } else if (index >= 0x40000000) {
5152 limit = 0x40000001;
c6dc6f63 5153 } else {
4ed3d478
DB		 5154 limit = env->cpuid_level;
5155 }
5156
5157 if (index > limit) {
5158 /* Intel documentation states that invalid EAX input will
5159 * return the same information as EAX=cpuid_level
5160 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5161 */
5162 index = env->cpuid_level;
c6dc6f63
AP		 5163 }
5164
5165 switch(index) {
5166 case 0:
5167 *eax = env->cpuid_level;
5eb2f7a4
EH		 5168 *ebx = env->cpuid_vendor1;
5169 *edx = env->cpuid_vendor2;
5170 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 5171 break;
5172 case 1:
5173 *eax = env->cpuid_version;
7e72a45c
EH		 5174 *ebx = (cpu->apic_id << 24) |
5175 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 5176 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 5177 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5178 *ecx |= CPUID_EXT_OSXSAVE;
5179 }
0514ef2f 5180 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 5181 if (cs->nr_cores * cs->nr_threads > 1) {
5182 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 5183 *edx |= CPUID_HT;
c6dc6f63 5184 }
ea39f9b6
LX		 5185 if (!cpu->enable_pmu) {
5186 *ecx &= ~CPUID_EXT_PDCM;
5187 }
c6dc6f63
AP		 5188 break;
5189 case 2:
5190 /* cache info: needed for Pentium Pro compatibility */
787aaf57 5191 if (cpu->cache_info_passthrough) {
798d8ec0 5192 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57 5193 break;
a7a0da84
MR		 5194 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
5195 *eax = *ebx = *ecx = *edx = 0;
5196 break;
787aaf57 5197 }
5e891bf8 5198 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 5199 *ebx = 0;
14c985cf
LM		 5200 if (!cpu->enable_l3_cache) {
5201 *ecx = 0;
5202 } else {
a9f27ea9 5203 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 5204 }
a9f27ea9
EH		 5205 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5206 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
5207 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 5208 break;
5209 case 4:
5210 /* cache info: needed for Core compatibility */
787aaf57 5211 if (cpu->cache_info_passthrough) {
798d8ec0 5212 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 5213 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 5214 *eax &= ~0xFC000000;
7e3482f8
EH		 5215 if ((*eax & 31) && cs->nr_cores > 1) {
5216 *eax |= (cs->nr_cores - 1) << 26;
5217 }
a7a0da84
MR		 5218 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
5219 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 5220 } else {
2f7a21c4 5221 *eax = 0;
76c2975a 5222 switch (count) {
c6dc6f63 5223 case 0: /* L1 dcache info */
a9f27ea9
EH		 5224 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5225 1, cs->nr_cores,
7e3482f8 5226 eax, ebx, ecx, edx);
c6dc6f63
AP		 5227 break;
5228 case 1: /* L1 icache info */
a9f27ea9
EH		 5229 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5230 1, cs->nr_cores,
7e3482f8 5231 eax, ebx, ecx, edx);
c6dc6f63
AP		 5232 break;
5233 case 2: /* L2 cache info */
a9f27ea9
EH		 5234 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5235 cs->nr_threads, cs->nr_cores,
7e3482f8 5236 eax, ebx, ecx, edx);
c6dc6f63 5237 break;
14c985cf 5238 case 3: /* L3 cache info */
f20dec0b 5239 die_offset = apicid_die_offset(&topo_info);
7e3482f8 5240 if (cpu->enable_l3_cache) {
a9f27ea9 5241 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
d65af288 5242 (1 << die_offset), cs->nr_cores,
7e3482f8 5243 eax, ebx, ecx, edx);
14c985cf
LM		 5244 break;
5245 }
7e3482f8 5246 /* fall through */
c6dc6f63 5247 default: /* end of info */
7e3482f8 5248 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 5249 break;
76c2975a
PB		 5250 }
5251 }
c6dc6f63
AP		 5252 break;
5253 case 5:
2266d443
MT		 5254 /* MONITOR/MWAIT Leaf */
5255 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5256 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5257 *ecx = cpu->mwait.ecx; /* flags */
5258 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 5259 break;
5260 case 6:
5261 /* Thermal and Power Leaf */
28b8e4d0 5262 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 5263 *ebx = 0;
5264 *ecx = 0;
5265 *edx = 0;
5266 break;
f7911686 5267 case 7:
13526728
EH		 5268 /* Structured Extended Feature Flags Enumeration Leaf */
5269 if (count == 0) {
80db491d
JL		 5270 /* Maximum ECX value for sub-leaves */
5271 *eax = env->cpuid_level_func7;
0514ef2f 5272 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 5273 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 5274 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5275 *ecx |= CPUID_7_0_ECX_OSPKE;
5276 }
95ea69fb 5277 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
1dec2e1f
SC		 5278
5279 /*
5280 * SGX cannot be emulated in software. If hardware does not
5281 * support enabling SGX and/or SGX flexible launch control,
5282 * then we need to update the VM's CPUID values accordingly.
5283 */
5284 if ((*ebx & CPUID_7_0_EBX_SGX) &&
5285 (!kvm_enabled() ||
5286 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_EBX) &
5287 CPUID_7_0_EBX_SGX))) {
5288 *ebx &= ~CPUID_7_0_EBX_SGX;
5289 }
5290
5291 if ((*ecx & CPUID_7_0_ECX_SGX_LC) &&
5292 (!(*ebx & CPUID_7_0_EBX_SGX) || !kvm_enabled() ||
5293 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_ECX) &
5294 CPUID_7_0_ECX_SGX_LC))) {
5295 *ecx &= ~CPUID_7_0_ECX_SGX_LC;
5296 }
80db491d
JL		 5297 } else if (count == 1) {
5298 *eax = env->features[FEAT_7_1_EAX];
5299 *ebx = 0;
5300 *ecx = 0;
5301 *edx = 0;
f7911686
YW		 5302 } else {
5303 *eax = 0;
5304 *ebx = 0;
5305 *ecx = 0;
5306 *edx = 0;
5307 }
5308 break;
c6dc6f63
AP		 5309 case 9:
5310 /* Direct Cache Access Information Leaf */
5311 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5312 *ebx = 0;
5313 *ecx = 0;
5314 *edx = 0;
5315 break;
5316 case 0xA:
5317 /* Architectural Performance Monitoring Leaf */
9337e3b6 5318 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 5319 KVMState *s = cs->kvm_state;
a0fa8208
GN		 5320
5321 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
5322 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
5323 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
5324 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 5325 } else if (hvf_enabled() && cpu->enable_pmu) {
5326 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
5327 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
5328 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
5329 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 5330 } else {
5331 *eax = 0;
5332 *ebx = 0;
5333 *ecx = 0;
5334 *edx = 0;
5335 }
c6dc6f63 5336 break;
5232d00a
RK		 5337 case 0xB:
5338 /* Extended Topology Enumeration Leaf */
5339 if (!cpu->enable_cpuid_0xb) {
5340 *eax = *ebx = *ecx = *edx = 0;
5341 break;
5342 }
5343
5344 *ecx = count & 0xff;
5345 *edx = cpu->apic_id;
5346
5347 switch (count) {
5348 case 0:
f20dec0b 5349 *eax = apicid_core_offset(&topo_info);
eab60fb9 5350 *ebx = cs->nr_threads;
5232d00a
RK		 5351 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5352 break;
5353 case 1:
fb49865d 5354 *eax = apicid_pkg_offset(&topo_info);
eab60fb9 5355 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 5356 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5357 break;
5358 default:
5359 *eax = 0;
5360 *ebx = 0;
5361 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5362 }
5363
a94e1428
LX		 5364 assert(!(*eax & ~0x1f));
5365 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5366 break;
5367 case 0x1F:
5368 /* V2 Extended Topology Enumeration Leaf */
5369 if (env->nr_dies < 2) {
5370 *eax = *ebx = *ecx = *edx = 0;
5371 break;
5372 }
5373
5374 *ecx = count & 0xff;
5375 *edx = cpu->apic_id;
5376 switch (count) {
5377 case 0:
f20dec0b 5378 *eax = apicid_core_offset(&topo_info);
a94e1428
LX		 5379 *ebx = cs->nr_threads;
5380 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5381 break;
5382 case 1:
f20dec0b 5383 *eax = apicid_die_offset(&topo_info);
a94e1428
LX		 5384 *ebx = cs->nr_cores * cs->nr_threads;
5385 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5386 break;
5387 case 2:
fb49865d 5388 *eax = apicid_pkg_offset(&topo_info);
a94e1428
LX		 5389 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
5390 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
5391 break;
5392 default:
5393 *eax = 0;
5394 *ebx = 0;
5395 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5396 }
5232d00a
RK		 5397 assert(!(*eax & ~0x1f));
5398 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5399 break;
2560f19f 5400 case 0xD: {
51e49430 5401 /* Processor Extended State */
2560f19f
PB		 5402 *eax = 0;
5403 *ebx = 0;
5404 *ecx = 0;
5405 *edx = 0;
19dc85db 5406 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 5407 break;
5408 }
4928cd6d 5409
2560f19f 5410 if (count == 0) {
96193c22
EH		 5411 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
5412 *eax = env->features[FEAT_XSAVE_COMP_LO];
5413 *edx = env->features[FEAT_XSAVE_COMP_HI];
76ecd7a5
BS		 5414 /*
5415 * The initial value of xcr0 and ebx == 0, On host without kvm
5416 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5417 * even through guest update xcr0, this will crash some legacy guest
5418 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5419 */
5420 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0);
2560f19f 5421 } else if (count == 1) {
0bb0b2d2 5422 *eax = env->features[FEAT_XSAVE];
f4f1110e 5423 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 5424 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
5425 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 5426 *eax = esa->size;
5427 *ebx = esa->offset;
0f17f6b3
JL		 5428 *ecx = esa->ecx &
5429 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK);
2560f19f 5430 }
51e49430
SY		 5431 }
5432 break;
2560f19f 5433 }
1dec2e1f
SC		 5434 case 0x12:
5435#ifndef CONFIG_USER_ONLY
5436 if (!kvm_enabled() ||
5437 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) {
5438 *eax = *ebx = *ecx = *edx = 0;
5439 break;
5440 }
5441
5442 /*
5443 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve
5444 * the EPC properties, e.g. confidentiality and integrity, from the
5445 * host's first EPC section, i.e. assume there is one EPC section or
5446 * that all EPC sections have the same security properties.
5447 */
5448 if (count > 1) {
5449 uint64_t epc_addr, epc_size;
5450
5451 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) {
5452 *eax = *ebx = *ecx = *edx = 0;
5453 break;
5454 }
5455 host_cpuid(index, 2, eax, ebx, ecx, edx);
5456 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1;
5457 *ebx = (uint32_t)(epc_addr >> 32);
5458 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf);
5459 *edx = (uint32_t)(epc_size >> 32);
5460 break;
5461 }
5462
5463 /*
5464 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware
5465 * and KVM, i.e. QEMU cannot emulate features to override what KVM
5466 * supports. Features can be further restricted by userspace, but not
5467 * made more permissive.
5468 */
5469 *eax = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_EAX);
5470 *ebx = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_EBX);
5471 *ecx = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_ECX);
5472 *edx = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_EDX);
5473
5474 if (count == 0) {
5475 *eax &= env->features[FEAT_SGX_12_0_EAX];
5476 *ebx &= env->features[FEAT_SGX_12_0_EBX];
5477 } else {
5478 *eax &= env->features[FEAT_SGX_12_1_EAX];
5479 *ebx &= 0; /* ebx reserve */
5480 *ecx &= env->features[FEAT_XSAVE_COMP_LO];
5481 *edx &= env->features[FEAT_XSAVE_COMP_HI];
5482
5483 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */
5484 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
5485
5486 /* Access to PROVISIONKEY requires additional credentials. */
c22f5467
SC		 5487 if ((*eax & (1U << 4)) &&
5488 !kvm_enable_sgx_provisioning(cs->kvm_state)) {
5489 *eax &= ~(1U << 4);
5490 }
1dec2e1f
SC		 5491 }
5492#endif
5493 break;
e37a5c7f
CP		 5494 case 0x14: {
5495 /* Intel Processor Trace Enumeration */
5496 *eax = 0;
5497 *ebx = 0;
5498 *ecx = 0;
5499 *edx = 0;
5500 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
5501 !kvm_enabled()) {
5502 break;
5503 }
5504
5505 if (count == 0) {
5506 *eax = INTEL_PT_MAX_SUBLEAF;
5507 *ebx = INTEL_PT_MINIMAL_EBX;
5508 *ecx = INTEL_PT_MINIMAL_ECX;
d1615ea5
LK		 5509 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) {
5510 *ecx |= CPUID_14_0_ECX_LIP;
5511 }
e37a5c7f
CP		 5512 } else if (count == 1) {
5513 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
5514 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
5515 }
5516 break;
5517 }
f21a4817
JL		 5518 case 0x1D: {
5519 /* AMX TILE */
5520 *eax = 0;
5521 *ebx = 0;
5522 *ecx = 0;
5523 *edx = 0;
5524 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
5525 break;
5526 }
5527
5528 if (count == 0) {
5529 /* Highest numbered palette subleaf */
5530 *eax = INTEL_AMX_TILE_MAX_SUBLEAF;
5531 } else if (count == 1) {
5532 *eax = INTEL_AMX_TOTAL_TILE_BYTES |
5533 (INTEL_AMX_BYTES_PER_TILE << 16);
5534 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16);
5535 *ecx = INTEL_AMX_TILE_MAX_ROWS;
5536 }
5537 break;
5538 }
5539 case 0x1E: {
5540 /* AMX TMUL */
5541 *eax = 0;
5542 *ebx = 0;
5543 *ecx = 0;
5544 *edx = 0;
5545 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
5546 break;
5547 }
5548
5549 if (count == 0) {
5550 /* Highest numbered palette subleaf */
5551 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8);
5552 }
5553 break;
5554 }
1ce36bfe
DB		 5555 case 0x40000000:
5556 /*
5557 * CPUID code in kvm_arch_init_vcpu() ignores stuff
5558 * set here, but we restrict to TCG none the less.
5559 */
5560 if (tcg_enabled() && cpu->expose_tcg) {
5561 memcpy(signature, "TCGTCGTCGTCG", 12);
5562 *eax = 0x40000001;
5563 *ebx = signature[0];
5564 *ecx = signature[1];
5565 *edx = signature[2];
5566 } else {
5567 *eax = 0;
5568 *ebx = 0;
5569 *ecx = 0;
5570 *edx = 0;
5571 }
5572 break;
5573 case 0x40000001:
5574 *eax = 0;
5575 *ebx = 0;
5576 *ecx = 0;
5577 *edx = 0;
5578 break;
c6dc6f63
AP		 5579 case 0x80000000:
5580 *eax = env->cpuid_xlevel;
5581 *ebx = env->cpuid_vendor1;
5582 *edx = env->cpuid_vendor2;
5583 *ecx = env->cpuid_vendor3;
5584 break;
5585 case 0x80000001:
5586 *eax = env->cpuid_version;
5587 *ebx = 0;
0514ef2f
EH		 5588 *ecx = env->features[FEAT_8000_0001_ECX];
5589 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 5590
5591 /* The Linux kernel checks for the CMPLegacy bit and
5592 * discards multiple thread information if it is set.
cb8d4c8f 5593 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 5594 */
ce3960eb 5595 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 5596 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
5597 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
5598 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 5599 *ecx |= 1 << 1; /* CmpLegacy bit */
5600 }
5601 }
c6dc6f63
AP		 5602 break;
5603 case 0x80000002:
5604 case 0x80000003:
5605 case 0x80000004:
5606 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
5607 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
5608 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
5609 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
5610 break;
5611 case 0x80000005:
5612 /* cache info (L1 cache) */
787aaf57 5613 if (cpu->cache_info_passthrough) {
798d8ec0 5614 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57
BC		 5615 break;
5616 }
78ee6bd0 5617 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
5e891bf8 5618 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
78ee6bd0 5619 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
5e891bf8 5620 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 5621 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
5622 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 5623 break;
5624 case 0x80000006:
5625 /* cache info (L2 cache) */
787aaf57 5626 if (cpu->cache_info_passthrough) {
798d8ec0 5627 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57
BC		 5628 break;
5629 }
78ee6bd0
PMD		 5630 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
5631 (L2_DTLB_2M_ENTRIES << 16) |
5632 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
5e891bf8 5633 (L2_ITLB_2M_ENTRIES);
78ee6bd0
PMD		 5634 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
5635 (L2_DTLB_4K_ENTRIES << 16) |
5636 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
5e891bf8 5637 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 5638 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
5639 cpu->enable_l3_cache ?
5640 env->cache_info_amd.l3_cache : NULL,
5641 ecx, edx);
c6dc6f63 5642 break;
303752a9
MT		 5643 case 0x80000007:
5644 *eax = 0;
5645 *ebx = 0;
5646 *ecx = 0;
5647 *edx = env->features[FEAT_8000_0007_EDX];
5648 break;
c6dc6f63
AP		 5649 case 0x80000008:
5650 /* virtual & phys address size in low 2 bytes. */
97afb47e 5651 *eax = cpu->phys_bits;
0514ef2f 5652 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21 5653 /* 64 bit processor */
97afb47e 5654 *eax |= (cpu_x86_virtual_addr_width(env) << 8);
c6dc6f63 5655 }
1b3420e1 5656 *ebx = env->features[FEAT_8000_0008_EBX];
ce3960eb 5657 if (cs->nr_cores * cs->nr_threads > 1) {
cac9edfc
BM		 5658 /*
5659 * Bits 15:12 is "The number of bits in the initial
5660 * Core::X86::Apic::ApicId[ApicId] value that indicate
fb49865d 5661 * thread ID within a package".
cac9edfc
BM		 5662 * Bits 7:0 is "The number of threads in the package is NC+1"
5663 */
fb49865d 5664 *ecx = (apicid_pkg_offset(&topo_info) << 12) |
cac9edfc
BM		 5665 ((cs->nr_cores * cs->nr_threads) - 1);
5666 } else {
5667 *ecx = 0;
c6dc6f63 5668 }
cac9edfc 5669 *edx = 0;
c6dc6f63
AP		 5670 break;
5671 case 0x8000000A:
0514ef2f 5672 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 5673 *eax = 0x00000001; /* SVM Revision */
5674 *ebx = 0x00000010; /* nr of ASIDs */
5675 *ecx = 0;
0514ef2f 5676 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 5677 } else {
5678 *eax = 0;
5679 *ebx = 0;
5680 *ecx = 0;
5681 *edx = 0;
5682 }
c6dc6f63 5683 break;
8f4202fb
BM		 5684 case 0x8000001D:
5685 *eax = 0;
a4e0b436 5686 if (cpu->cache_info_passthrough) {
798d8ec0 5687 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
a4e0b436
SL		 5688 break;
5689 }
8f4202fb
BM		 5690 switch (count) {
5691 case 0: /* L1 dcache info */
2f084d1e
BM		 5692 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
5693 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5694 break;
5695 case 1: /* L1 icache info */
2f084d1e
BM		 5696 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
5697 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5698 break;
5699 case 2: /* L2 cache info */
2f084d1e
BM		 5700 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
5701 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5702 break;
5703 case 3: /* L3 cache info */
2f084d1e
BM		 5704 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
5705 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5706 break;
5707 default: /* end of info */
5708 *eax = *ebx = *ecx = *edx = 0;
5709 break;
5710 }
5711 break;
ed78467a 5712 case 0x8000001E:
35ac5dfb
BM		 5713 if (cpu->core_id <= 255) {
5714 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx);
5715 } else {
5716 *eax = 0;
5717 *ebx = 0;
5718 *ecx = 0;
5719 *edx = 0;
5720 }
ed78467a 5721 break;
b3baa152
BW		 5722 case 0xC0000000:
5723 *eax = env->cpuid_xlevel2;
5724 *ebx = 0;
5725 *ecx = 0;
5726 *edx = 0;
5727 break;
5728 case 0xC0000001:
5729 /* Support for VIA CPU's CPUID instruction */
5730 *eax = env->cpuid_version;
5731 *ebx = 0;
5732 *ecx = 0;
0514ef2f 5733 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 5734 break;
5735 case 0xC0000002:
5736 case 0xC0000003:
5737 case 0xC0000004:
5738 /* Reserved for the future, and now filled with zero */
5739 *eax = 0;
5740 *ebx = 0;
5741 *ecx = 0;
5742 *edx = 0;
5743 break;
6cb8f2a6 5744 case 0x8000001F:
02eacf31
PMD		 5745 *eax = *ebx = *ecx = *edx = 0;
5746 if (sev_enabled()) {
5747 *eax = 0x2;
5748 *eax |= sev_es_enabled() ? 0x8 : 0;
5749 *ebx = sev_get_cbit_position();
5750 *ebx |= sev_get_reduced_phys_bits() << 6;
5751 }
6cb8f2a6 5752 break;
c6dc6f63
AP		 5753 default:
5754 /* reserved values: zero */
5755 *eax = 0;
5756 *ebx = 0;
5757 *ecx = 0;
5758 *edx = 0;
5759 break;
5760 }
5761}
5fd2087a 5762
db888065
SC		 5763static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env)
5764{
5765#ifndef CONFIG_USER_ONLY
5766 /* Those default values are defined in Skylake HW */
5767 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL;
5768 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL;
5769 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL;
5770 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL;
5771#endif
5772}
5773
781c67ca 5774static void x86_cpu_reset(DeviceState *dev)
5fd2087a 5775{
781c67ca 5776 CPUState *s = CPU(dev);
5fd2087a
AF		 5777 X86CPU *cpu = X86_CPU(s);
5778 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
5779 CPUX86State *env = &cpu->env;
a114d25d
RH		 5780 target_ulong cr4;
5781 uint64_t xcr0;
c1958aea
AF		 5782 int i;
5783
781c67ca 5784 xcc->parent_reset(dev);
5fd2087a 5785
5e992a8e 5786 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 5787
c1958aea
AF		 5788 env->old_exception = -1;
5789
5790 /* init to reset state */
e3126a5c 5791 env->int_ctl = 0;
c1958aea 5792 env->hflags2 |= HF2_GIF_MASK;
b67e2796 5793 env->hflags2 |= HF2_VGIF_MASK;
b16c0e20 5794 env->hflags &= ~HF_GUEST_MASK;
c1958aea
AF		 5795
5796 cpu_x86_update_cr0(env, 0x60000010);
5797 env->a20_mask = ~0x0;
5798 env->smbase = 0x30000;
e13713db 5799 env->msr_smi_count = 0;
c1958aea
AF		 5800
5801 env->idt.limit = 0xffff;
5802 env->gdt.limit = 0xffff;
5803 env->ldt.limit = 0xffff;
5804 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
5805 env->tr.limit = 0xffff;
5806 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
5807
5808 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
5809 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
5810 DESC_R_MASK | DESC_A_MASK);
5811 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
5812 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5813 DESC_A_MASK);
5814 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
5815 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5816 DESC_A_MASK);
5817 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
5818 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5819 DESC_A_MASK);
5820 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
5821 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5822 DESC_A_MASK);
5823 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
5824 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5825 DESC_A_MASK);
5826
5827 env->eip = 0xfff0;
5828 env->regs[R_EDX] = env->cpuid_version;
5829
5830 env->eflags = 0x2;
5831
5832 /* FPU init */
5833 for (i = 0; i < 8; i++) {
5834 env->fptags[i] = 1;
5835 }
5bde1407 5836 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 5837
5838 env->mxcsr = 0x1f80;
a114d25d
RH		 5839 /* All units are in INIT state. */
5840 env->xstate_bv = 0;
c1958aea
AF		 5841
5842 env->pat = 0x0007040600070406ULL;
5286c366
PB		 5843
5844 if (kvm_enabled()) {
5845 /*
5846 * KVM handles TSC = 0 specially and thinks we are hot-plugging
5847 * a new CPU, use 1 instead to force a reset.
5848 */
5849 if (env->tsc != 0) {
5850 env->tsc = 1;
5851 }
5852 } else {
5853 env->tsc = 0;
5854 }
5855
c1958aea 5856 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4cfd7bab
WL		 5857 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
5858 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
5859 }
c1958aea
AF		 5860
5861 memset(env->dr, 0, sizeof(env->dr));
5862 env->dr[6] = DR6_FIXED_1;
5863 env->dr[7] = DR7_FIXED_1;
b3310ab3 5864 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 5865 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 5866
a114d25d 5867 cr4 = 0;
cfc3b074 5868 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 5869
5870#ifdef CONFIG_USER_ONLY
5871 /* Enable all the features for user-mode. */
5872 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 5873 xcr0 |= XSTATE_SSE_MASK;
a114d25d 5874 }
0f70ed47
PB		 5875 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
5876 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 5877 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 5878 xcr0 |= 1ull << i;
5879 }
a114d25d 5880 }
0f70ed47 5881
a114d25d
RH		 5882 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
5883 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
5884 }
07929f2a
RH		 5885 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
5886 cr4 |= CR4_FSGSBASE_MASK;
5887 }
a114d25d
RH		 5888#endif
5889
5890 env->xcr0 = xcr0;
5891 cpu_x86_update_cr4(env, cr4);
0522604b 5892
9db2efd9
AW		 5893 /*
5894 * SDM 11.11.5 requires:
5895 * - IA32_MTRR_DEF_TYPE MSR.E = 0
5896 * - IA32_MTRR_PHYSMASKn.V = 0
5897 * All other bits are undefined. For simplification, zero it all.
5898 */
5899 env->mtrr_deftype = 0;
5900 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
5901 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
5902
b7394c83 5903 env->interrupt_injected = -1;
fd13f23b
LA		 5904 env->exception_nr = -1;
5905 env->exception_pending = 0;
5906 env->exception_injected = 0;
5907 env->exception_has_payload = false;
5908 env->exception_payload = 0;
b7394c83 5909 env->nmi_injected = false;
dd673288
IM		 5910#if !defined(CONFIG_USER_ONLY)
5911 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 5912 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 5913
259186a7 5914 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 5915
5916 if (kvm_enabled()) {
5917 kvm_arch_reset_vcpu(cpu);
5918 }
db888065
SC		 5919
5920 x86_cpu_set_sgxlepubkeyhash(env);
cabf9862 5921
3e4546d5 5922 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT;
cabf9862 5923
dd673288 5924#endif
5fd2087a
AF		 5925}
5926
de024815
AF		 5927static void mce_init(X86CPU *cpu)
5928{
5929 CPUX86State *cenv = &cpu->env;
5930 unsigned int bank;
5931
5932 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 5933 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 5934 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 5935 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
5936 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 5937 cenv->mcg_ctl = ~(uint64_t)0;
5938 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
5939 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
5940 }
5941 }
5942}
5943
c39c0edf
EH		 5944static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
5945{
5946 if (*min < value) {
5947 *min = value;
5948 }
5949}
5950
5951/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
5952static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
5953{
5954 CPUX86State *env = &cpu->env;
5955 FeatureWordInfo *fi = &feature_word_info[w];
07585923 5956 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 5957 uint32_t region = eax & 0xF0000000;
5958
07585923 5959 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 5960 if (!env->features[w]) {
5961 return;
5962 }
5963
5964 switch (region) {
5965 case 0x00000000:
5966 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
5967 break;
5968 case 0x80000000:
5969 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
5970 break;
5971 case 0xC0000000:
5972 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
5973 break;
5974 }
80db491d
JL		 5975
5976 if (eax == 7) {
5977 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
5978 fi->cpuid.ecx);
5979 }
c39c0edf
EH		 5980}
5981
2ca8a8be
EH		 5982/* Calculate XSAVE components based on the configured CPU feature flags */
5983static void x86_cpu_enable_xsave_components(X86CPU *cpu)
5984{
5985 CPUX86State *env = &cpu->env;
5986 int i;
96193c22 5987 uint64_t mask;
19db68ca 5988 static bool request_perm;
2ca8a8be
EH		 5989
5990 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
19ca8285
XL		 5991 env->features[FEAT_XSAVE_COMP_LO] = 0;
5992 env->features[FEAT_XSAVE_COMP_HI] = 0;
2ca8a8be
EH		 5993 return;
5994 }
5995
e3c9022b
EH		 5996 mask = 0;
5997 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 5998 const ExtSaveArea *esa = &x86_ext_save_areas[i];
5999 if (env->features[esa->feature] & esa->bits) {
96193c22 6000 mask |= (1ULL << i);
2ca8a8be
EH		 6001 }
6002 }
6003
19db68ca
YZ		 6004 /* Only request permission for first vcpu */
6005 if (kvm_enabled() && !request_perm) {
6006 kvm_request_xsave_components(cpu, mask);
6007 request_perm = true;
6008 }
6009
96193c22
EH		 6010 env->features[FEAT_XSAVE_COMP_LO] = mask;
6011 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 6012}
6013
b8d834a0
EH		 6014/***** Steps involved on loading and filtering CPUID data
6015 *
6016 * When initializing and realizing a CPU object, the steps
6017 * involved in setting up CPUID data are:
6018 *
6019 * 1) Loading CPU model definition (X86CPUDefinition). This is
dcafd1ef 6020 * implemented by x86_cpu_load_model() and should be completely
b8d834a0
EH		 6021 * transparent, as it is done automatically by instance_init.
6022 * No code should need to look at X86CPUDefinition structs
6023 * outside instance_init.
6024 *
6025 * 2) CPU expansion. This is done by realize before CPUID
6026 * filtering, and will make sure host/accelerator data is
6027 * loaded for CPU models that depend on host capabilities
6028 * (e.g. "host"). Done by x86_cpu_expand_features().
6029 *
6030 * 3) CPUID filtering. This initializes extra data related to
6031 * CPUID, and checks if the host supports all capabilities
6032 * required by the CPU. Runnability of a CPU model is
6033 * determined at this step. Done by x86_cpu_filter_features().
6034 *
6035 * Some operations don't require all steps to be performed.
6036 * More precisely:
6037 *
6038 * - CPU instance creation (instance_init) will run only CPU
6039 * model loading. CPU expansion can't run at instance_init-time
6040 * because host/accelerator data may be not available yet.
6041 * - CPU realization will perform both CPU model expansion and CPUID
6042 * filtering, and return an error in case one of them fails.
6043 * - query-cpu-definitions needs to run all 3 steps. It needs
6044 * to run CPUID filtering, as the 'unavailable-features'
6045 * field is set based on the filtering results.
6046 * - The query-cpu-model-expansion QMP command only needs to run
6047 * CPU model loading and CPU expansion. It should not filter
6048 * any CPUID data based on host capabilities.
6049 */
6050
6051/* Expand CPU configuration data, based on configured features
6052 * and host/accelerator capabilities when appropriate.
6053 */
79f1a68a 6054void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 6055{
b34d12d1 6056 CPUX86State *env = &cpu->env;
dc15c051 6057 FeatureWord w;
99e24dbd 6058 int i;
2fae0d96 6059 GList *l;
9886e834 6060
99e24dbd
PB		 6061 for (l = plus_features; l; l = l->next) {
6062 const char *prop = l->data;
992861fb
MA		 6063 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
6064 return;
99e24dbd
PB		 6065 }
6066 }
6067
6068 for (l = minus_features; l; l = l->next) {
6069 const char *prop = l->data;
992861fb
MA		 6070 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
6071 return;
99e24dbd
PB		 6072 }
6073 }
6074
d4a606b3
EH		 6075 /*TODO: Now cpu->max_features doesn't overwrite features
6076 * set using QOM properties, and we can convert
dc15c051
IM		 6077 * plus_features & minus_features to global properties
6078 * inside x86_cpu_parse_featurestr() too.
6079 */
44bd8e53 6080 if (cpu->max_features) {
dc15c051 6081 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 6082 /* Override only features that weren't set explicitly
6083 * by the user.
6084 */
6085 env->features[w] |=
6086 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
78ee6bd0 6087 ~env->user_features[w] &
0d914f39 6088 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 6089 }
6090 }
6091
99e24dbd
PB		 6092 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
6093 FeatureDep *d = &feature_dependencies[i];
6094 if (!(env->features[d->from.index] & d->from.mask)) {
ede146c2 6095 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
2fae0d96 6096
99e24dbd
PB		 6097 /* Not an error unless the dependent feature was added explicitly. */
6098 mark_unavailable_features(cpu, d->to.index,
6099 unavailable_features & env->user_features[d->to.index],
6100 "This feature depends on other features that were not requested");
6101
99e24dbd 6102 env->features[d->to.index] &= ~unavailable_features;
2fae0d96 6103 }
dc15c051
IM		 6104 }
6105
aec661de
EH		 6106 if (!kvm_enabled() || !cpu->expose_kvm) {
6107 env->features[FEAT_KVM] = 0;
6108 }
6109
2ca8a8be 6110 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 6111
6112 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6113 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
6114 if (cpu->full_cpuid_auto_level) {
6115 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
6116 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
6117 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
6118 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
80db491d 6119 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
c39c0edf
EH		 6120 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
6121 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
6122 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 6123 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 6124 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
6125 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
6126 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
f24c3a79
LK		 6127
6128 /* Intel Processor Trace requires CPUID[0x14] */
ddc2fc9e
LK		 6129 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
6130 if (cpu->intel_pt_auto_level) {
6131 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
6132 } else if (cpu->env.cpuid_min_level < 0x14) {
6133 mark_unavailable_features(cpu, FEAT_7_0_EBX,
6134 CPUID_7_0_EBX_INTEL_PT,
b7d77f5a 6135 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\"");
ddc2fc9e 6136 }
f24c3a79
LK		 6137 }
6138
760746ac
ZP		 6139 /*
6140 * Intel CPU topology with multi-dies support requires CPUID[0x1F].
6141 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect
6142 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless
6143 * cpu->vendor_cpuid_only has been unset for compatibility with older
6144 * machine types.
6145 */
6146 if ((env->nr_dies > 1) &&
6147 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) {
a94e1428
LX		 6148 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
6149 }
6150
0c3d7c00
EH		 6151 /* SVM requires CPUID[0x8000000A] */
6152 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
6153 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
6154 }
6cb8f2a6
BS		 6155
6156 /* SEV requires CPUID[0x8000001F] */
6157 if (sev_enabled()) {
6158 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
6159 }
dca6cffc
SC		 6160
6161 /* SGX requires CPUID[0x12] for EPC enumeration */
6162 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) {
6163 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12);
6164 }
c39c0edf
EH		 6165 }
6166
6167 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
80db491d
JL		 6168 if (env->cpuid_level_func7 == UINT32_MAX) {
6169 env->cpuid_level_func7 = env->cpuid_min_level_func7;
6170 }
c39c0edf
EH		 6171 if (env->cpuid_level == UINT32_MAX) {
6172 env->cpuid_level = env->cpuid_min_level;
6173 }
6174 if (env->cpuid_xlevel == UINT32_MAX) {
6175 env->cpuid_xlevel = env->cpuid_min_xlevel;
6176 }
6177 if (env->cpuid_xlevel2 == UINT32_MAX) {
6178 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 6179 }
071ce4b0
VK		 6180
6181 if (kvm_enabled()) {
6182 kvm_hyperv_expand_features(cpu, errp);
6183 }
41f3d4d6
EH		 6184}
6185
b8d834a0
EH		 6186/*
6187 * Finishes initialization of CPUID data, filters CPU feature
6188 * words based on host availability of each feature.
6189 *
6190 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6191 */
245edd0c 6192static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
b8d834a0
EH		 6193{
6194 CPUX86State *env = &cpu->env;
6195 FeatureWord w;
245edd0c
PB		 6196 const char *prefix = NULL;
6197
6198 if (verbose) {
6199 prefix = accel_uses_host_cpuid()
6200 ? "host doesn't support requested feature"
6201 : "TCG doesn't support requested feature";
6202 }
b8d834a0
EH		 6203
6204 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 6205 uint64_t host_feat =
b8d834a0 6206 x86_cpu_get_supported_feature_word(w, false);
ede146c2
PB		 6207 uint64_t requested_features = env->features[w];
6208 uint64_t unavailable_features = requested_features & ~host_feat;
245edd0c 6209 mark_unavailable_features(cpu, w, unavailable_features, prefix);
b8d834a0
EH		 6210 }
6211
e37a5c7f
CP		 6212 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6213 kvm_enabled()) {
6214 KVMState *s = CPU(cpu)->kvm_state;
6215 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6216 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6217 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6218 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6219 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6220
6221 if (!eax_0 ||
6222 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6223 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6224 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6225 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6226 INTEL_PT_ADDR_RANGES_NUM) ||
6227 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96 6228 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
d1615ea5
LK		 6229 ((ecx_0 & CPUID_14_0_ECX_LIP) !=
6230 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) {
e37a5c7f
CP		 6231 /*
6232 * Processor Trace capabilities aren't configurable, so if the
6233 * host can't emulate the capabilities we report on
6234 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6235 */
245edd0c 6236 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
e37a5c7f
CP		 6237 }
6238 }
b8d834a0
EH		 6239}
6240
08856771
VK		 6241static void x86_cpu_hyperv_realize(X86CPU *cpu)
6242{
6243 size_t len;
6244
6245 /* Hyper-V vendor id */
6246 if (!cpu->hyperv_vendor) {
4519259a
VK		 6247 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv",
6248 &error_abort);
6249 }
6250 len = strlen(cpu->hyperv_vendor);
6251 if (len > 12) {
6252 warn_report("hv-vendor-id truncated to 12 characters");
6253 len = 12;
08856771 6254 }
4519259a
VK		 6255 memset(cpu->hyperv_vendor_id, 0, 12);
6256 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len);
735db465
VK		 6257
6258 /* 'Hv#1' interface identification*/
6259 cpu->hyperv_interface_id[0] = 0x31237648;
6260 cpu->hyperv_interface_id[1] = 0;
6261 cpu->hyperv_interface_id[2] = 0;
6262 cpu->hyperv_interface_id[3] = 0;
fb7e31aa 6263
23eb5d03
VK		 6264 /* Hypervisor implementation limits */
6265 cpu->hyperv_limits[0] = 64;
6266 cpu->hyperv_limits[1] = 0;
6267 cpu->hyperv_limits[2] = 0;
08856771
VK		 6268}
6269
41f3d4d6
EH		 6270static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6271{
6272 CPUState *cs = CPU(dev);
6273 X86CPU *cpu = X86_CPU(dev);
6274 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6275 CPUX86State *env = &cpu->env;
6276 Error *local_err = NULL;
6277 static bool ht_warned;
6278
41f3d4d6
EH		 6279 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6280 error_setg(errp, "apic-id property was not initialized properly");
6281 return;
6282 }
6283
662175b9
CF		 6284 /*
6285 * Process Hyper-V enlightenments.
6286 * Note: this currently has to happen before the expansion of CPU features.
6287 */
6288 x86_cpu_hyperv_realize(cpu);
6289
b8d834a0 6290 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 6291 if (local_err) {
6292 goto out;
6293 }
6294
245edd0c
PB		 6295 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
6296
6297 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
6298 error_setg(&local_err,
6299 accel_uses_host_cpuid() ?
6300 "Host doesn't support requested features" :
6301 "TCG doesn't support requested features");
6302 goto out;
9997cf7b
EH		 6303 }
6304
9b15cd9e
IM		 6305 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6306 * CPUID[1].EDX.
6307 */
e48638fd 6308 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 6309 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
6310 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 6311 & CPUID_EXT2_AMD_ALIASES);
6312 }
6313
db888065
SC		 6314 x86_cpu_set_sgxlepubkeyhash(env);
6315
662175b9
CF		 6316 /*
6317 * note: the call to the framework needs to happen after feature expansion,
6318 * but before the checks/modifications to ucode_rev, mwait, phys_bits.
6319 * These may be set by the accel-specific code,
6320 * and the results are subsequently checked / assumed in this function.
6321 */
6322 cpu_exec_realizefn(cs, &local_err);
6323 if (local_err != NULL) {
6324 error_propagate(errp, local_err);
6325 return;
6326 }
6327
6328 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
6329 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6330 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name);
6331 goto out;
6332 }
6333
6334 if (cpu->ucode_rev == 0) {
6335 /*
6336 * The default is the same as KVM's. Note that this check
6337 * needs to happen after the evenual setting of ucode_rev in
6338 * accel-specific code in cpu_exec_realizefn.
6339 */
6340 if (IS_AMD_CPU(env)) {
6341 cpu->ucode_rev = 0x01000065;
6342 } else {
6343 cpu->ucode_rev = 0x100000000ULL;
6344 }
6345 }
6346
6347 /*
6348 * mwait extended info: needed for Core compatibility
6349 * We always wake on interrupt even if host does not have the capability.
6350 *
6351 * requires the accel-specific code in cpu_exec_realizefn to
6352 * have already acquired the CPUID data into cpu->mwait.
6353 */
6354 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
6355
11f6fee5
DDAG		 6356 /* For 64bit systems think about the number of physical bits to present.
6357 * ideally this should be the same as the host; anything other than matching
6358 * the host can cause incorrect guest behaviour.
6359 * QEMU used to pick the magic value of 40 bits that corresponds to
6360 * consumer AMD devices but nothing else.
662175b9
CF		 6361 *
6362 * Note that this code assumes features expansion has already been done
6363 * (as it checks for CPUID_EXT2_LM), and also assumes that potential
6364 * phys_bits adjustments to match the host have been already done in
6365 * accel-specific code in cpu_exec_realizefn.
11f6fee5 6366 */
af45907a 6367 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
b8184135
PB		 6368 if (cpu->phys_bits &&
6369 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
6370 cpu->phys_bits < 32)) {
6371 error_setg(errp, "phys-bits should be between 32 and %u "
6372 " (but is %u)",
6373 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
6374 return;
af45907a 6375 }
f5cc5a5c
CF		 6376 /*
6377 * 0 means it was not explicitly set by the user (or by machine
6378 * compat_props or by the host code in host-cpu.c).
6379 * In this case, the default is the value used by TCG (40).
11f6fee5
DDAG		 6380 */
6381 if (cpu->phys_bits == 0) {
6382 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
6383 }
af45907a
DDAG		 6384 } else {
6385 /* For 32 bit systems don't use the user set value, but keep
6386 * phys_bits consistent with what we tell the guest.
6387 */
6388 if (cpu->phys_bits != 0) {
6389 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
6390 return;
6391 }
fefb41bf 6392
af45907a
DDAG		 6393 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
6394 cpu->phys_bits = 36;
6395 } else {
6396 cpu->phys_bits = 32;
6397 }
6398 }
a9f27ea9
EH		 6399
6400 /* Cache information initialization */
6401 if (!cpu->legacy_cache) {
dcafd1ef 6402 if (!xcc->model || !xcc->model->cpudef->cache_info) {
88703ce2 6403 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
a9f27ea9
EH		 6404 error_setg(errp,
6405 "CPU model '%s' doesn't support legacy-cache=off", name);
a9f27ea9
EH		 6406 return;
6407 }
6408 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
dcafd1ef 6409 *xcc->model->cpudef->cache_info;
a9f27ea9
EH		 6410 } else {
6411 /* Build legacy cache information */
6412 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
6413 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
6414 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
6415 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
6416
6417 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
6418 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
6419 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
6420 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
6421
6422 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
6423 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
6424 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
6425 env->cache_info_amd.l3_cache = &legacy_l3_cache;
6426 }
6427
65dee380 6428#ifndef CONFIG_USER_ONLY
0e11fc69 6429 MachineState *ms = MACHINE(qdev_get_machine());
65dee380 6430 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 6431
0e11fc69 6432 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
d3c64d6a 6433 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 6434 if (local_err != NULL) {
4dc1f449 6435 goto out;
bdeec802
IM		 6436 }
6437 }
65dee380
IM		 6438#endif
6439
7a059953 6440 mce_init(cpu);
2001d0cd 6441
14a10fc3 6442 qemu_init_vcpu(cs);
d3c64d6a 6443
6b2942f9
BM		 6444 /*
6445 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6446 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6447 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 6448 * users a warning.
6449 *
6450 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6451 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6452 */
0765691e
MA		 6453 if (IS_AMD_CPU(env) &&
6454 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
6455 cs->nr_threads > 1 && !ht_warned) {
6456 warn_report("This family of AMD CPU doesn't support "
6457 "hyperthreading(%d)",
6458 cs->nr_threads);
6459 error_printf("Please configure -smp options properly"
6460 " or try enabling topoext feature.\n");
6461 ht_warned = true;
e48638fd
WH		 6462 }
6463
79f1a68a 6464#ifndef CONFIG_USER_ONLY
d3c64d6a
IM		 6465 x86_cpu_apic_realize(cpu, &local_err);
6466 if (local_err != NULL) {
6467 goto out;
6468 }
79f1a68a 6469#endif /* !CONFIG_USER_ONLY */
14a10fc3 6470 cpu_reset(cs);
2b6f294c 6471
4dc1f449 6472 xcc->parent_realize(dev, &local_err);
2001d0cd 6473
4dc1f449
IM		 6474out:
6475 if (local_err != NULL) {
6476 error_propagate(errp, local_err);
6477 return;
6478 }
7a059953
AF		 6479}
6480
b69c3c21 6481static void x86_cpu_unrealizefn(DeviceState *dev)
c884776e
IM		 6482{
6483 X86CPU *cpu = X86_CPU(dev);
7bbc124e 6484 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
c884776e
IM		 6485
6486#ifndef CONFIG_USER_ONLY
6487 cpu_remove_sync(CPU(dev));
6488 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
6489#endif
6490
6491 if (cpu->apic_state) {
6492 object_unparent(OBJECT(cpu->apic_state));
6493 cpu->apic_state = NULL;
6494 }
7bbc124e 6495
b69c3c21 6496 xcc->parent_unrealize(dev);
c884776e
IM		 6497}
6498
38e5c119 6499typedef struct BitProperty {
a7b0ffac 6500 FeatureWord w;
ede146c2 6501 uint64_t mask;
38e5c119
EH		 6502} BitProperty;
6503
d7bce999
EB		 6504static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
6505 void *opaque, Error **errp)
38e5c119 6506{
a7b0ffac 6507 X86CPU *cpu = X86_CPU(obj);
38e5c119 6508 BitProperty *fp = opaque;
ede146c2 6509 uint64_t f = cpu->env.features[fp->w];
a7b0ffac 6510 bool value = (f & fp->mask) == fp->mask;
51e72bc1 6511 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 6512}
6513
d7bce999
EB		 6514static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
6515 void *opaque, Error **errp)
38e5c119
EH		 6516{
6517 DeviceState *dev = DEVICE(obj);
a7b0ffac 6518 X86CPU *cpu = X86_CPU(obj);
38e5c119 6519 BitProperty *fp = opaque;
38e5c119
EH		 6520 bool value;
6521
6522 if (dev->realized) {
6523 qdev_prop_set_after_realize(dev, name, errp);
6524 return;
6525 }
6526
668f62ec 6527 if (!visit_type_bool(v, name, &value, errp)) {
38e5c119
EH		 6528 return;
6529 }
6530
6531 if (value) {
a7b0ffac 6532 cpu->env.features[fp->w] |= fp->mask;
38e5c119 6533 } else {
a7b0ffac 6534 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 6535 }
d4a606b3 6536 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 6537}
6538
38e5c119
EH		 6539/* Register a boolean property to get/set a single bit in a uint32_t field.
6540 *
6541 * The same property name can be registered multiple times to make it affect
6542 * multiple bits in the same FeatureWord. In that case, the getter will return
6543 * true only if all bits are set.
6544 */
f5730c69 6545static void x86_cpu_register_bit_prop(X86CPUClass *xcc,
38e5c119 6546 const char *prop_name,
a7b0ffac 6547 FeatureWord w,
38e5c119
EH		 6548 int bitnr)
6549{
f5730c69 6550 ObjectClass *oc = OBJECT_CLASS(xcc);
38e5c119
EH		 6551 BitProperty *fp;
6552 ObjectProperty *op;
ede146c2 6553 uint64_t mask = (1ULL << bitnr);
38e5c119 6554
f5730c69 6555 op = object_class_property_find(oc, prop_name);
38e5c119
EH		 6556 if (op) {
6557 fp = op->opaque;
a7b0ffac 6558 assert(fp->w == w);
38e5c119
EH		 6559 fp->mask |= mask;
6560 } else {
6561 fp = g_new0(BitProperty, 1);
a7b0ffac 6562 fp->w = w;
38e5c119 6563 fp->mask = mask;
f5730c69
EH		 6564 object_class_property_add(oc, prop_name, "bool",
6565 x86_cpu_get_bit_prop,
6566 x86_cpu_set_bit_prop,
6567 NULL, fp);
38e5c119
EH		 6568 }
6569}
6570
f5730c69 6571static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc,
38e5c119
EH		 6572 FeatureWord w,
6573 int bitnr)
6574{
38e5c119 6575 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 6576 const char *name = fi->feat_names[bitnr];
38e5c119 6577
16d2fcaa 6578 if (!name) {
38e5c119
EH		 6579 return;
6580 }
6581
fc7dfd20
EH		 6582 /* Property names should use "-" instead of "_".
6583 * Old names containing underscores are registered as aliases
6584 * using object_property_add_alias()
6585 */
16d2fcaa
EH		 6586 assert(!strchr(name, '_'));
6587 /* aliases don't use "|" delimiters anymore, they are registered
6588 * manually using object_property_add_alias() */
6589 assert(!strchr(name, '|'));
f5730c69 6590 x86_cpu_register_bit_prop(xcc, name, w, bitnr);
38e5c119
EH		 6591}
6592
4db4385a
CF		 6593static void x86_cpu_post_initfn(Object *obj)
6594{
6595 accel_cpu_instance_init(CPU(obj));
6596}
6597
de024815
AF		 6598static void x86_cpu_initfn(Object *obj)
6599{
6600 X86CPU *cpu = X86_CPU(obj);
d940ee9b 6601 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815
AF		 6602 CPUX86State *env = &cpu->env;
6603
c26ae610 6604 env->nr_dies = 1;
7506ed90 6605 cpu_set_cpustate_pointers(cpu);
71ad61d3 6606
8e8aba50
EH		 6607 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
6608 x86_cpu_get_feature_words,
d2623129 6609 NULL, NULL, (void *)env->features);
7e5292b5
EH		 6610 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
6611 x86_cpu_get_feature_words,
d2623129 6612 NULL, NULL, (void *)cpu->filtered_features);
d187e08d 6613
d2623129
MA		 6614 object_property_add_alias(obj, "sse3", obj, "pni");
6615 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq");
6616 object_property_add_alias(obj, "sse4-1", obj, "sse4.1");
6617 object_property_add_alias(obj, "sse4-2", obj, "sse4.2");
6618 object_property_add_alias(obj, "xd", obj, "nx");
6619 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt");
6620 object_property_add_alias(obj, "i64", obj, "lm");
6621
6622 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl");
6623 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust");
6624 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt");
6625 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm");
6626 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy");
6627 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr");
6628 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core");
6629 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb");
6630 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
6631 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
6632 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
db5daafa 6633 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int");
d2623129
MA		 6634 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
6635 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
6636 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
6637 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control");
6638 object_property_add_alias(obj, "svm_lock", obj, "svm-lock");
6639 object_property_add_alias(obj, "nrip_save", obj, "nrip-save");
6640 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale");
6641 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean");
6642 object_property_add_alias(obj, "pause_filter", obj, "pause-filter");
6643 object_property_add_alias(obj, "sse4_1", obj, "sse4.1");
6644 object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
54b8dc7c 6645
e1f9a8e8
VK		 6646 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic");
6647
dcafd1ef 6648 if (xcc->model) {
49e2fa85 6649 x86_cpu_load_model(cpu, xcc->model);
0bacd8b3 6650 }
de024815
AF		 6651}
6652
997395d3
IM		 6653static int64_t x86_cpu_get_arch_id(CPUState *cs)
6654{
6655 X86CPU *cpu = X86_CPU(cs);
997395d3 6656
7e72a45c 6657 return cpu->apic_id;
997395d3
IM		 6658}
6659
6bc0d6a0 6660#if !defined(CONFIG_USER_ONLY)
444d5590
AF		 6661static bool x86_cpu_get_paging_enabled(const CPUState *cs)
6662{
6663 X86CPU *cpu = X86_CPU(cs);
6664
6665 return cpu->env.cr[0] & CR0_PG_MASK;
6666}
6bc0d6a0 6667#endif /* !CONFIG_USER_ONLY */
444d5590 6668
f45748f1
AF		 6669static void x86_cpu_set_pc(CPUState *cs, vaddr value)
6670{
6671 X86CPU *cpu = X86_CPU(cs);
6672
6673 cpu->env.eip = value;
6674}
6675
92d5f1a4 6676int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 6677{
6678 X86CPU *cpu = X86_CPU(cs);
6679 CPUX86State *env = &cpu->env;
6680
92d5f1a4
PB		 6681#if !defined(CONFIG_USER_ONLY)
6682 if (interrupt_request & CPU_INTERRUPT_POLL) {
6683 return CPU_INTERRUPT_POLL;
6684 }
6685#endif
6686 if (interrupt_request & CPU_INTERRUPT_SIPI) {
6687 return CPU_INTERRUPT_SIPI;
6688 }
6689
6690 if (env->hflags2 & HF2_GIF_MASK) {
6691 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
6692 !(env->hflags & HF_SMM_MASK)) {
6693 return CPU_INTERRUPT_SMI;
6694 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
6695 !(env->hflags2 & HF2_NMI_MASK)) {
6696 return CPU_INTERRUPT_NMI;
6697 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
6698 return CPU_INTERRUPT_MCE;
6699 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
6700 (((env->hflags2 & HF2_VINTR_MASK) &&
6701 (env->hflags2 & HF2_HIF_MASK)) ||
6702 (!(env->hflags2 & HF2_VINTR_MASK) &&
6703 (env->eflags & IF_MASK &&
6704 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
6705 return CPU_INTERRUPT_HARD;
6706#if !defined(CONFIG_USER_ONLY)
b67e2796
LL		 6707 } else if (env->hflags2 & HF2_VGIF_MASK) {
6708 if((interrupt_request & CPU_INTERRUPT_VIRQ) &&
92d5f1a4
PB		 6709 (env->eflags & IF_MASK) &&
6710 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
b67e2796
LL		 6711 return CPU_INTERRUPT_VIRQ;
6712 }
92d5f1a4
PB		 6713#endif
6714 }
6715 }
6716
6717 return 0;
6718}
6719
6720static bool x86_cpu_has_work(CPUState *cs)
6721{
6722 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 6723}
6724
f50f3dd5
RH		 6725static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
6726{
6727 X86CPU *cpu = X86_CPU(cs);
6728 CPUX86State *env = &cpu->env;
6729
6730 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
6731 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
6732 : bfd_mach_i386_i8086);
b666d2a4
RH		 6733
6734 info->cap_arch = CS_ARCH_X86;
6735 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
6736 : env->hflags & HF_CS32_MASK ? CS_MODE_32
6737 : CS_MODE_16);
15fa1a0a
RH		 6738 info->cap_insn_unit = 1;
6739 info->cap_insn_split = 8;
f50f3dd5
RH		 6740}
6741
35b1b927
TW		 6742void x86_update_hflags(CPUX86State *env)
6743{
6744 uint32_t hflags;
6745#define HFLAG_COPY_MASK \
6746 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
6747 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
6748 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
6749 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
6750
6751 hflags = env->hflags & HFLAG_COPY_MASK;
6752 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
6753 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
6754 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
6755 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
6756 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
6757
6758 if (env->cr[4] & CR4_OSFXSR_MASK) {
6759 hflags |= HF_OSFXSR_MASK;
6760 }
6761
6762 if (env->efer & MSR_EFER_LMA) {
6763 hflags |= HF_LMA_MASK;
6764 }
6765
6766 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
6767 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
6768 } else {
6769 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
6770 (DESC_B_SHIFT - HF_CS32_SHIFT);
6771 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
6772 (DESC_B_SHIFT - HF_SS32_SHIFT);
6773 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
6774 !(hflags & HF_CS32_MASK)) {
6775 hflags |= HF_ADDSEG_MASK;
6776 } else {
6777 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
6778 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
6779 }
6780 }
6781 env->hflags = hflags;
6782}
6783
9337e3b6 6784static Property x86_cpu_properties[] = {
2da00e31
IM		 6785#ifdef CONFIG_USER_ONLY
6786 /* apic_id = 0 by default for *-user, see commit 9886e834 */
6787 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 6788 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
6789 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
176d2cda 6790 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
d89c2b8b 6791 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 6792#else
6793 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 6794 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
6795 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
176d2cda 6796 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
d89c2b8b 6797 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 6798#endif
15f8b142 6799 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 6800 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2d384d7c 6801
915aee93 6802 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
f701c082 6803 HYPERV_SPINLOCK_NEVER_NOTIFY),
2d384d7c
VK		 6804 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
6805 HYPERV_FEAT_RELAXED, 0),
6806 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
6807 HYPERV_FEAT_VAPIC, 0),
6808 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
6809 HYPERV_FEAT_TIME, 0),
6810 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
6811 HYPERV_FEAT_CRASH, 0),
6812 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
6813 HYPERV_FEAT_RESET, 0),
6814 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
6815 HYPERV_FEAT_VPINDEX, 0),
6816 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
6817 HYPERV_FEAT_RUNTIME, 0),
6818 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
6819 HYPERV_FEAT_SYNIC, 0),
6820 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
6821 HYPERV_FEAT_STIMER, 0),
6822 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
6823 HYPERV_FEAT_FREQUENCIES, 0),
6824 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
6825 HYPERV_FEAT_REENLIGHTENMENT, 0),
6826 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
6827 HYPERV_FEAT_TLBFLUSH, 0),
6828 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
6829 HYPERV_FEAT_EVMCS, 0),
6830 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
6831 HYPERV_FEAT_IPI, 0),
128531d9
VK		 6832 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
6833 HYPERV_FEAT_STIMER_DIRECT, 0),
e1f9a8e8
VK		 6834 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features,
6835 HYPERV_FEAT_AVIC, 0),
30d6ff66
VK		 6836 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
6837 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
73d24074
JD		 6838 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features,
6839 HYPERV_FEAT_SYNDBG, 0),
e48ddcc6 6840 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
70367f09 6841 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false),
2d384d7c 6842
af7228b8
VK		 6843 /* WS2008R2 identify by default */
6844 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build,
f701ecec 6845 0x3839),
af7228b8 6846 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major,
f701ecec 6847 0x000A),
af7228b8 6848 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor,
f701ecec 6849 0x0000),
af7228b8
VK		 6850 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0),
6851 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0),
6852 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0),
6853
15e41345 6854 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 6855 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
dac1deae 6856 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
f522d2ac 6857 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 6858 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 6859 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
258fe08b 6860 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
fcc35e7c 6861 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
80db491d
JL		 6862 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
6863 UINT32_MAX),
c39c0edf
EH		 6864 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
6865 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
6866 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
6867 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
6868 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
6869 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4e45aff3 6870 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
c39c0edf 6871 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
08856771 6872 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
5232d00a 6873 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
a7a0da84 6874 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true),
87f8b626 6875 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 6876 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 6877 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
6878 false),
988f7b8b
VK		 6879 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid,
6880 false),
0b564e6f 6881 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 6882 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 6883 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
6884 true),
ab8f992e 6885 /*
a9f27ea9
EH		 6886 * lecacy_cache defaults to true unless the CPU model provides its
6887 * own cache information (see x86_cpu_load_def()).
ab8f992e 6888 */
a9f27ea9 6889 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 6890
6891 /*
6892 * From "Requirements for Implementing the Microsoft
6893 * Hypervisor Interface":
6894 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
6895 *
6896 * "Starting with Windows Server 2012 and Windows 8, if
6897 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
6898 * the hypervisor imposes no specific limit to the number of VPs.
6899 * In this case, Windows Server 2012 guest VMs may use more than
6900 * 64 VPs, up to the maximum supported number of processors applicable
6901 * to the specific Windows version being used."
6902 */
6903 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 6904 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
6905 false),
f24c3a79
LK		 6906 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
6907 true),
9337e3b6
EH		 6908 DEFINE_PROP_END_OF_LIST()
6909};
6910
8b80bd28
PMD		 6911#ifndef CONFIG_USER_ONLY
6912#include "hw/core/sysemu-cpu-ops.h"
6913
6914static const struct SysemuCPUOps i386_sysemu_ops = {
2b60b62e 6915 .get_memory_mapping = x86_cpu_get_memory_mapping,
6bc0d6a0 6916 .get_paging_enabled = x86_cpu_get_paging_enabled,
08928c6d 6917 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
faf39e82 6918 .asidx_from_attrs = x86_asidx_from_attrs,
83ec01b6 6919 .get_crash_info = x86_cpu_get_crash_info,
715e3c1a
PMD		 6920 .write_elf32_note = x86_cpu_write_elf32_note,
6921 .write_elf64_note = x86_cpu_write_elf64_note,
6922 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
6923 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
feece4d0 6924 .legacy_vmsd = &vmstate_x86_cpu,
8b80bd28
PMD		 6925};
6926#endif
6927
5fd2087a
AF		 6928static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
6929{
6930 X86CPUClass *xcc = X86_CPU_CLASS(oc);
6931 CPUClass *cc = CPU_CLASS(oc);
2b6f294c 6932 DeviceClass *dc = DEVICE_CLASS(oc);
f5730c69 6933 FeatureWord w;
2b6f294c 6934
bf853881
PMD		 6935 device_class_set_parent_realize(dc, x86_cpu_realizefn,
6936 &xcc->parent_realize);
6937 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
6938 &xcc->parent_unrealize);
4f67d30b 6939 device_class_set_props(dc, x86_cpu_properties);
5fd2087a 6940
781c67ca 6941 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset);
91b1df8c 6942 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 6943
500050d1 6944 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 6945 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 6946 cc->has_work = x86_cpu_has_work;
878096ee 6947 cc->dump_state = x86_cpu_dump_state;
f45748f1 6948 cc->set_pc = x86_cpu_set_pc;
5b50e790
AF		 6949 cc->gdb_read_register = x86_cpu_gdb_read_register;
6950 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590 6951 cc->get_arch_id = x86_cpu_get_arch_id;
ed69e831 6952
5d004421 6953#ifndef CONFIG_USER_ONLY
8b80bd28 6954 cc->sysemu_ops = &i386_sysemu_ops;
ed69e831
CF		 6955#endif /* !CONFIG_USER_ONLY */
6956
00fcd100
AB		 6957 cc->gdb_arch_name = x86_gdb_arch_name;
6958#ifdef TARGET_X86_64
b8158192 6959 cc->gdb_core_xml_file = "i386-64bit.xml";
7b0f97ba 6960 cc->gdb_num_core_regs = 66;
00fcd100 6961#else
b8158192 6962 cc->gdb_core_xml_file = "i386-32bit.xml";
7b0f97ba 6963 cc->gdb_num_core_regs = 50;
74d7fc7f 6964#endif
f50f3dd5 6965 cc->disas_set_info = x86_disas_set_info;
4c315c27 6966
e90f2a8c 6967 dc->user_creatable = true;
3e0dceaf
EH		 6968
6969 object_class_property_add(oc, "family", "int",
6970 x86_cpuid_version_get_family,
6971 x86_cpuid_version_set_family, NULL, NULL);
6972 object_class_property_add(oc, "model", "int",
6973 x86_cpuid_version_get_model,
6974 x86_cpuid_version_set_model, NULL, NULL);
6975 object_class_property_add(oc, "stepping", "int",
6976 x86_cpuid_version_get_stepping,
6977 x86_cpuid_version_set_stepping, NULL, NULL);
6978 object_class_property_add_str(oc, "vendor",
6979 x86_cpuid_get_vendor,
6980 x86_cpuid_set_vendor);
6981 object_class_property_add_str(oc, "model-id",
6982 x86_cpuid_get_model_id,
6983 x86_cpuid_set_model_id);
6984 object_class_property_add(oc, "tsc-frequency", "int",
6985 x86_cpuid_get_tsc_freq,
6986 x86_cpuid_set_tsc_freq, NULL, NULL);
6987 /*
6988 * The "unavailable-features" property has the same semantics as
6989 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
6990 * QMP command: they list the features that would have prevented the
6991 * CPU from running if the "enforce" flag was set.
6992 */
6993 object_class_property_add(oc, "unavailable-features", "strList",
6994 x86_cpu_get_unavailable_features,
6995 NULL, NULL, NULL);
6996
6997#if !defined(CONFIG_USER_ONLY)
6998 object_class_property_add(oc, "crash-information", "GuestPanicInformation",
6999 x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
7000#endif
7001
f5730c69
EH		 7002 for (w = 0; w < FEATURE_WORDS; w++) {
7003 int bitnr;
7004 for (bitnr = 0; bitnr < 64; bitnr++) {
7005 x86_cpu_register_feature_bit_props(xcc, w, bitnr);
7006 }
7007 }
5fd2087a
AF		 7008}
7009
7010static const TypeInfo x86_cpu_type_info = {
7011 .name = TYPE_X86_CPU,
7012 .parent = TYPE_CPU,
7013 .instance_size = sizeof(X86CPU),
de024815 7014 .instance_init = x86_cpu_initfn,
4db4385a
CF		 7015 .instance_post_init = x86_cpu_post_initfn,
7016
d940ee9b 7017 .abstract = true,
5fd2087a
AF		 7018 .class_size = sizeof(X86CPUClass),
7019 .class_init = x86_cpu_common_class_init,
7020};
7021
5adbed30
EH		 7022/* "base" CPU model, used by query-cpu-model-expansion */
7023static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
7024{
7025 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7026
7027 xcc->static_model = true;
7028 xcc->migration_safe = true;
7029 xcc->model_description = "base CPU model type with no features enabled";
7030 xcc->ordering = 8;
7031}
7032
7033static const TypeInfo x86_base_cpu_type_info = {
7034 .name = X86_CPU_TYPE_NAME("base"),
7035 .parent = TYPE_X86_CPU,
7036 .class_init = x86_cpu_base_class_init,
7037};
7038
5fd2087a
AF		 7039static void x86_cpu_register_types(void)
7040{
d940ee9b
EH		 7041 int i;
7042
5fd2087a 7043 type_register_static(&x86_cpu_type_info);
d940ee9b 7044 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
dcafd1ef 7045 x86_register_cpudef_types(&builtin_x86_defs[i]);
d940ee9b 7046 }
c62f2630 7047 type_register_static(&max_x86_cpu_type_info);
5adbed30 7048 type_register_static(&x86_base_cpu_type_info);
5fd2087a
AF		 7049}
7050
7051type_init(x86_cpu_register_types)
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