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i386: remove the new CPUID 'PCONFIG' from Icelake-Server CPU model
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
631be321 23#include "qemu/bitops.h"
c6dc6f63
AP		 24
25#include "cpu.h"
63c91552 26#include "exec/exec-all.h"
9c17d615 27#include "sysemu/kvm.h"
d6dcc558 28#include "sysemu/hvf.h"
8932cfdf 29#include "sysemu/cpus.h"
50a2c6e5 30#include "kvm_i386.h"
6cb8f2a6 31#include "sev_i386.h"
c6dc6f63 32
d49b6836 33#include "qemu/error-report.h"
1de7afc9
PB		 34#include "qemu/option.h"
35#include "qemu/config-file.h"
e688df6b 36#include "qapi/error.h"
112ed241
MA		 37#include "qapi/qapi-visit-misc.h"
38#include "qapi/qapi-visit-run-state.h"
452fcdbc 39#include "qapi/qmp/qdict.h"
7b1b5d19 40#include "qapi/qmp/qerror.h"
7b1b5d19 41#include "qapi/visitor.h"
f99fd7ca 42#include "qom/qom-qobject.h"
9c17d615 43#include "sysemu/arch_init.h"
71ad61d3 44
1814eab6 45#include "standard-headers/asm-x86/kvm_para.h"
65dee380 46
9c17d615 47#include "sysemu/sysemu.h"
53a89e26 48#include "hw/qdev-properties.h"
5232d00a 49#include "hw/i386/topology.h"
bdeec802 50#ifndef CONFIG_USER_ONLY
2001d0cd 51#include "exec/address-spaces.h"
741da0d3 52#include "hw/hw.h"
0d09e41a 53#include "hw/xen/xen.h"
0d09e41a 54#include "hw/i386/apic_internal.h"
bdeec802
IM		 55#endif
56
b666d2a4
RH		 57#include "disas/capstone.h"
58
7e3482f8
EH		 59/* Helpers for building CPUID[2] descriptors: */
60
61struct CPUID2CacheDescriptorInfo {
62 enum CacheType type;
63 int level;
64 int size;
65 int line_size;
66 int associativity;
67};
5e891bf8 68
7e3482f8
EH		 69/*
70 * Known CPUID 2 cache descriptors.
71 * From Intel SDM Volume 2A, CPUID instruction
72 */
73struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 74 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 75 .associativity = 4, .line_size = 32, },
5f00335a 76 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 77 .associativity = 4, .line_size = 32, },
5f00335a 78 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 79 .associativity = 4, .line_size = 64, },
5f00335a 80 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 81 .associativity = 2, .line_size = 32, },
5f00335a 82 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 83 .associativity = 4, .line_size = 32, },
5f00335a 84 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 85 .associativity = 4, .line_size = 64, },
5f00335a 86 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 87 .associativity = 6, .line_size = 64, },
5f00335a 88 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 89 .associativity = 2, .line_size = 64, },
5f00335a 90 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 91 .associativity = 8, .line_size = 64, },
92 /* lines per sector is not supported cpuid2_cache_descriptor(),
93 * so descriptors 0x22, 0x23 are not included
94 */
5f00335a 95 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 96 .associativity = 16, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x25, 0x20 are not included
99 */
5f00335a 100 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 101 .associativity = 8, .line_size = 64, },
5f00335a 102 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 103 .associativity = 8, .line_size = 64, },
5f00335a 104 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 105 .associativity = 4, .line_size = 32, },
5f00335a 106 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 107 .associativity = 4, .line_size = 32, },
5f00335a 108 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 109 .associativity = 4, .line_size = 32, },
5f00335a 110 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 111 .associativity = 4, .line_size = 32, },
5f00335a 112 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 113 .associativity = 4, .line_size = 32, },
5f00335a 114 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 115 .associativity = 4, .line_size = 64, },
5f00335a 116 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 117 .associativity = 8, .line_size = 64, },
5f00335a 118 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 119 .associativity = 12, .line_size = 64, },
120 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 121 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 122 .associativity = 12, .line_size = 64, },
5f00335a 123 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 124 .associativity = 16, .line_size = 64, },
5f00335a 125 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 126 .associativity = 12, .line_size = 64, },
5f00335a 127 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 128 .associativity = 16, .line_size = 64, },
5f00335a 129 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 130 .associativity = 24, .line_size = 64, },
5f00335a 131 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 132 .associativity = 8, .line_size = 64, },
5f00335a 133 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 134 .associativity = 4, .line_size = 64, },
5f00335a 135 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 136 .associativity = 4, .line_size = 64, },
5f00335a 137 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 138 .associativity = 4, .line_size = 64, },
5f00335a 139 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 140 .associativity = 4, .line_size = 64, },
141 /* lines per sector is not supported cpuid2_cache_descriptor(),
142 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
143 */
5f00335a 144 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 145 .associativity = 8, .line_size = 64, },
5f00335a 146 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 147 .associativity = 2, .line_size = 64, },
5f00335a 148 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 149 .associativity = 8, .line_size = 64, },
5f00335a 150 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 151 .associativity = 8, .line_size = 32, },
5f00335a 152 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 153 .associativity = 8, .line_size = 32, },
5f00335a 154 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 155 .associativity = 8, .line_size = 32, },
5f00335a 156 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 157 .associativity = 8, .line_size = 32, },
5f00335a 158 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 159 .associativity = 4, .line_size = 64, },
5f00335a 160 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 161 .associativity = 8, .line_size = 64, },
5f00335a 162 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 163 .associativity = 4, .line_size = 64, },
5f00335a 164 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 165 .associativity = 4, .line_size = 64, },
5f00335a 166 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 167 .associativity = 4, .line_size = 64, },
5f00335a 168 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 169 .associativity = 8, .line_size = 64, },
5f00335a 170 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 171 .associativity = 8, .line_size = 64, },
5f00335a 172 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 173 .associativity = 8, .line_size = 64, },
5f00335a 174 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 175 .associativity = 12, .line_size = 64, },
5f00335a 176 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 177 .associativity = 12, .line_size = 64, },
5f00335a 178 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 179 .associativity = 12, .line_size = 64, },
5f00335a 180 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 181 .associativity = 16, .line_size = 64, },
5f00335a 182 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 183 .associativity = 16, .line_size = 64, },
5f00335a 184 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 185 .associativity = 16, .line_size = 64, },
5f00335a 186 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 187 .associativity = 24, .line_size = 64, },
5f00335a 188 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 189 .associativity = 24, .line_size = 64, },
5f00335a 190 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 191 .associativity = 24, .line_size = 64, },
192};
193
194/*
195 * "CPUID leaf 2 does not report cache descriptor information,
196 * use CPUID leaf 4 to query cache parameters"
197 */
198#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 199
7e3482f8
EH		 200/*
201 * Return a CPUID 2 cache descriptor for a given cache.
202 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
203 */
204static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
205{
206 int i;
207
208 assert(cache->size > 0);
209 assert(cache->level > 0);
210 assert(cache->line_size > 0);
211 assert(cache->associativity > 0);
212 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
213 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
214 if (d->level == cache->level && d->type == cache->type &&
215 d->size == cache->size && d->line_size == cache->line_size &&
216 d->associativity == cache->associativity) {
217 return i;
218 }
219 }
5e891bf8 220
7e3482f8
EH		 221 return CACHE_DESCRIPTOR_UNAVAILABLE;
222}
5e891bf8
EH		 223
224/* CPUID Leaf 4 constants: */
225
226/* EAX: */
7e3482f8
EH		 227#define CACHE_TYPE_D 1
228#define CACHE_TYPE_I 2
229#define CACHE_TYPE_UNIFIED 3
5e891bf8 230
7e3482f8 231#define CACHE_LEVEL(l) (l << 5)
5e891bf8 232
7e3482f8 233#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 234
235/* EDX: */
7e3482f8
EH		 236#define CACHE_NO_INVD_SHARING (1 << 0)
237#define CACHE_INCLUSIVE (1 << 1)
238#define CACHE_COMPLEX_IDX (1 << 2)
239
240/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 241#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
242 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
243 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
244 0 /* Invalid value */)
7e3482f8
EH		 245
246
247/* Encode cache info for CPUID[4] */
248static void encode_cache_cpuid4(CPUCacheInfo *cache,
249 int num_apic_ids, int num_cores,
250 uint32_t *eax, uint32_t *ebx,
251 uint32_t *ecx, uint32_t *edx)
252{
253 assert(cache->size == cache->line_size * cache->associativity *
254 cache->partitions * cache->sets);
255
256 assert(num_apic_ids > 0);
257 *eax = CACHE_TYPE(cache->type) |
258 CACHE_LEVEL(cache->level) |
259 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
260 ((num_cores - 1) << 26) |
261 ((num_apic_ids - 1) << 14);
262
263 assert(cache->line_size > 0);
264 assert(cache->partitions > 0);
265 assert(cache->associativity > 0);
266 /* We don't implement fully-associative caches */
267 assert(cache->associativity < cache->sets);
268 *ebx = (cache->line_size - 1) |
269 ((cache->partitions - 1) << 12) |
270 ((cache->associativity - 1) << 22);
271
272 assert(cache->sets > 0);
273 *ecx = cache->sets - 1;
274
275 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
276 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
277 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
278}
279
280/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
281static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
282{
283 assert(cache->size % 1024 == 0);
284 assert(cache->lines_per_tag > 0);
285 assert(cache->associativity > 0);
286 assert(cache->line_size > 0);
287 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
288 (cache->lines_per_tag << 8) | (cache->line_size);
289}
5e891bf8
EH		 290
291#define ASSOC_FULL 0xFF
292
293/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
294#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
295 a == 2 ? 0x2 : \
296 a == 4 ? 0x4 : \
297 a == 8 ? 0x6 : \
298 a == 16 ? 0x8 : \
299 a == 32 ? 0xA : \
300 a == 48 ? 0xB : \
301 a == 64 ? 0xC : \
302 a == 96 ? 0xD : \
303 a == 128 ? 0xE : \
304 a == ASSOC_FULL ? 0xF : \
305 0 /* invalid value */)
306
7e3482f8
EH		 307/*
308 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
309 * @l3 can be NULL.
310 */
311static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
312 CPUCacheInfo *l3,
313 uint32_t *ecx, uint32_t *edx)
314{
315 assert(l2->size % 1024 == 0);
316 assert(l2->associativity > 0);
317 assert(l2->lines_per_tag > 0);
318 assert(l2->line_size > 0);
319 *ecx = ((l2->size / 1024) << 16) |
320 (AMD_ENC_ASSOC(l2->associativity) << 12) |
321 (l2->lines_per_tag << 8) | (l2->line_size);
322
323 if (l3) {
324 assert(l3->size % (512 * 1024) == 0);
325 assert(l3->associativity > 0);
326 assert(l3->lines_per_tag > 0);
327 assert(l3->line_size > 0);
328 *edx = ((l3->size / (512 * 1024)) << 18) |
329 (AMD_ENC_ASSOC(l3->associativity) << 12) |
330 (l3->lines_per_tag << 8) | (l3->line_size);
331 } else {
332 *edx = 0;
333 }
334}
5e891bf8 335
8f4202fb
BM		 336/*
337 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
338 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
339 * Define the constants to build the cpu topology. Right now, TOPOEXT
340 * feature is enabled only on EPYC. So, these constants are based on
341 * EPYC supported configurations. We may need to handle the cases if
342 * these values change in future.
343 */
344/* Maximum core complexes in a node */
345#define MAX_CCX 2
346/* Maximum cores in a core complex */
347#define MAX_CORES_IN_CCX 4
348/* Maximum cores in a node */
349#define MAX_CORES_IN_NODE 8
350/* Maximum nodes in a socket */
351#define MAX_NODES_PER_SOCKET 4
352
353/*
354 * Figure out the number of nodes required to build this config.
355 * Max cores in a node is 8
356 */
357static int nodes_in_socket(int nr_cores)
358{
359 int nodes;
360
361 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
362
363 /* Hardware does not support config with 3 nodes, return 4 in that case */
364 return (nodes == 3) ? 4 : nodes;
365}
366
367/*
368 * Decide the number of cores in a core complex with the given nr_cores using
369 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
370 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
371 * L3 cache is shared across all cores in a core complex. So, this will also
372 * tell us how many cores are sharing the L3 cache.
373 */
374static int cores_in_core_complex(int nr_cores)
375{
376 int nodes;
377
378 /* Check if we can fit all the cores in one core complex */
379 if (nr_cores <= MAX_CORES_IN_CCX) {
380 return nr_cores;
381 }
382 /* Get the number of nodes required to build this config */
383 nodes = nodes_in_socket(nr_cores);
384
385 /*
386 * Divide the cores accros all the core complexes
387 * Return rounded up value
388 */
389 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
390}
391
392/* Encode cache info for CPUID[8000001D] */
393static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
394 uint32_t *eax, uint32_t *ebx,
395 uint32_t *ecx, uint32_t *edx)
396{
397 uint32_t l3_cores;
398 assert(cache->size == cache->line_size * cache->associativity *
399 cache->partitions * cache->sets);
400
401 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
402 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
403
404 /* L3 is shared among multiple cores */
405 if (cache->level == 3) {
406 l3_cores = cores_in_core_complex(cs->nr_cores);
407 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
408 } else {
409 *eax |= ((cs->nr_threads - 1) << 14);
410 }
411
412 assert(cache->line_size > 0);
413 assert(cache->partitions > 0);
414 assert(cache->associativity > 0);
415 /* We don't implement fully-associative caches */
416 assert(cache->associativity < cache->sets);
417 *ebx = (cache->line_size - 1) |
418 ((cache->partitions - 1) << 12) |
419 ((cache->associativity - 1) << 22);
420
421 assert(cache->sets > 0);
422 *ecx = cache->sets - 1;
423
424 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
425 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
426 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
427}
428
ed78467a
BM		 429/* Data structure to hold the configuration info for a given core index */
430struct core_topology {
431 /* core complex id of the current core index */
432 int ccx_id;
433 /*
434 * Adjusted core index for this core in the topology
435 * This can be 0,1,2,3 with max 4 cores in a core complex
436 */
437 int core_id;
438 /* Node id for this core index */
439 int node_id;
440 /* Number of nodes in this config */
441 int num_nodes;
442};
443
444/*
445 * Build the configuration closely match the EPYC hardware. Using the EPYC
446 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
447 * right now. This could change in future.
448 * nr_cores : Total number of cores in the config
449 * core_id : Core index of the current CPU
450 * topo : Data structure to hold all the config info for this core index
451 */
452static void build_core_topology(int nr_cores, int core_id,
453 struct core_topology *topo)
454{
455 int nodes, cores_in_ccx;
456
457 /* First get the number of nodes required */
458 nodes = nodes_in_socket(nr_cores);
459
460 cores_in_ccx = cores_in_core_complex(nr_cores);
461
462 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
463 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
464 topo->core_id = core_id % cores_in_ccx;
465 topo->num_nodes = nodes;
466}
467
468/* Encode cache info for CPUID[8000001E] */
469static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
470 uint32_t *eax, uint32_t *ebx,
471 uint32_t *ecx, uint32_t *edx)
472{
473 struct core_topology topo = {0};
631be321
BM		 474 unsigned long nodes;
475 int shift;
ed78467a
BM		 476
477 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
478 *eax = cpu->apic_id;
479 /*
480 * CPUID_Fn8000001E_EBX
481 * 31:16 Reserved
482 * 15:8 Threads per core (The number of threads per core is
483 * Threads per core + 1)
484 * 7:0 Core id (see bit decoding below)
485 * SMT:
486 * 4:3 node id
487 * 2 Core complex id
488 * 1:0 Core id
489 * Non SMT:
490 * 5:4 node id
491 * 3 Core complex id
492 * 1:0 Core id
493 */
494 if (cs->nr_threads - 1) {
495 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
496 (topo.ccx_id << 2) | topo.core_id;
497 } else {
498 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
499 }
500 /*
501 * CPUID_Fn8000001E_ECX
502 * 31:11 Reserved
503 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
504 * 7:0 Node id (see bit decoding below)
505 * 2 Socket id
506 * 1:0 Node id
507 */
631be321
BM		 508 if (topo.num_nodes <= 4) {
509 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
510 topo.node_id;
511 } else {
512 /*
513 * Node id fix up. Actual hardware supports up to 4 nodes. But with
514 * more than 32 cores, we may end up with more than 4 nodes.
515 * Node id is a combination of socket id and node id. Only requirement
516 * here is that this number should be unique accross the system.
517 * Shift the socket id to accommodate more nodes. We dont expect both
518 * socket id and node id to be big number at the same time. This is not
519 * an ideal config but we need to to support it. Max nodes we can have
520 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
521 * 5 bits for nodes. Find the left most set bit to represent the total
522 * number of nodes. find_last_bit returns last set bit(0 based). Left
523 * shift(+1) the socket id to represent all the nodes.
524 */
525 nodes = topo.num_nodes - 1;
526 shift = find_last_bit(&nodes, 8);
527 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
528 topo.node_id;
529 }
ed78467a
BM		 530 *edx = 0;
531}
532
ab8f992e
BM		 533/*
534 * Definitions of the hardcoded cache entries we expose:
535 * These are legacy cache values. If there is a need to change any
536 * of these values please use builtin_x86_defs
537 */
5e891bf8
EH		 538
539/* L1 data cache: */
ab8f992e 540static CPUCacheInfo legacy_l1d_cache = {
5f00335a 541 .type = DATA_CACHE,
7e3482f8
EH		 542 .level = 1,
543 .size = 32 * KiB,
544 .self_init = 1,
545 .line_size = 64,
546 .associativity = 8,
547 .sets = 64,
548 .partitions = 1,
549 .no_invd_sharing = true,
550};
551
5e891bf8 552/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 553static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 554 .type = DATA_CACHE,
7e3482f8
EH		 555 .level = 1,
556 .size = 64 * KiB,
557 .self_init = 1,
558 .line_size = 64,
559 .associativity = 2,
560 .sets = 512,
561 .partitions = 1,
562 .lines_per_tag = 1,
563 .no_invd_sharing = true,
564};
5e891bf8
EH		 565
566/* L1 instruction cache: */
ab8f992e 567static CPUCacheInfo legacy_l1i_cache = {
5f00335a 568 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 569 .level = 1,
570 .size = 32 * KiB,
571 .self_init = 1,
572 .line_size = 64,
573 .associativity = 8,
574 .sets = 64,
575 .partitions = 1,
576 .no_invd_sharing = true,
577};
578
5e891bf8 579/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 580static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 581 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 582 .level = 1,
583 .size = 64 * KiB,
584 .self_init = 1,
585 .line_size = 64,
586 .associativity = 2,
587 .sets = 512,
588 .partitions = 1,
589 .lines_per_tag = 1,
590 .no_invd_sharing = true,
591};
5e891bf8
EH		 592
593/* Level 2 unified cache: */
ab8f992e 594static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 595 .type = UNIFIED_CACHE,
596 .level = 2,
597 .size = 4 * MiB,
598 .self_init = 1,
599 .line_size = 64,
600 .associativity = 16,
601 .sets = 4096,
602 .partitions = 1,
603 .no_invd_sharing = true,
604};
605
5e891bf8 606/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 607static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 608 .type = UNIFIED_CACHE,
609 .level = 2,
610 .size = 2 * MiB,
611 .line_size = 64,
612 .associativity = 8,
613};
614
615
5e891bf8 616/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 617static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 618 .type = UNIFIED_CACHE,
619 .level = 2,
620 .size = 512 * KiB,
621 .line_size = 64,
622 .lines_per_tag = 1,
623 .associativity = 16,
624 .sets = 512,
625 .partitions = 1,
626};
5e891bf8 627
14c985cf 628/* Level 3 unified cache: */
ab8f992e 629static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 630 .type = UNIFIED_CACHE,
631 .level = 3,
632 .size = 16 * MiB,
633 .line_size = 64,
634 .associativity = 16,
635 .sets = 16384,
636 .partitions = 1,
637 .lines_per_tag = 1,
638 .self_init = true,
639 .inclusive = true,
640 .complex_indexing = true,
641};
5e891bf8
EH		 642
643/* TLB definitions: */
644
645#define L1_DTLB_2M_ASSOC 1
646#define L1_DTLB_2M_ENTRIES 255
647#define L1_DTLB_4K_ASSOC 1
648#define L1_DTLB_4K_ENTRIES 255
649
650#define L1_ITLB_2M_ASSOC 1
651#define L1_ITLB_2M_ENTRIES 255
652#define L1_ITLB_4K_ASSOC 1
653#define L1_ITLB_4K_ENTRIES 255
654
655#define L2_DTLB_2M_ASSOC 0 /* disabled */
656#define L2_DTLB_2M_ENTRIES 0 /* disabled */
657#define L2_DTLB_4K_ASSOC 4
658#define L2_DTLB_4K_ENTRIES 512
659
660#define L2_ITLB_2M_ASSOC 0 /* disabled */
661#define L2_ITLB_2M_ENTRIES 0 /* disabled */
662#define L2_ITLB_4K_ASSOC 4
663#define L2_ITLB_4K_ENTRIES 512
664
e37a5c7f
CP		 665/* CPUID Leaf 0x14 constants: */
666#define INTEL_PT_MAX_SUBLEAF 0x1
667/*
668 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
669 * MSR can be accessed;
670 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
671 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
672 * of Intel PT MSRs across warm reset;
673 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
674 */
675#define INTEL_PT_MINIMAL_EBX 0xf
676/*
677 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
678 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
679 * accessed;
680 * bit[01]: ToPA tables can hold any number of output entries, up to the
681 * maximum allowed by the MaskOrTableOffset field of
682 * IA32_RTIT_OUTPUT_MASK_PTRS;
683 * bit[02]: Support Single-Range Output scheme;
684 */
685#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 686/* generated packets which contain IP payloads have LIP values */
687#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 688#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
689#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
690#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
691#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
692#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 693
99b88a17
IM		 694static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
695 uint32_t vendor2, uint32_t vendor3)
696{
697 int i;
698 for (i = 0; i < 4; i++) {
699 dst[i] = vendor1 >> (8 * i);
700 dst[i + 4] = vendor2 >> (8 * i);
701 dst[i + 8] = vendor3 >> (8 * i);
702 }
703 dst[CPUID_VENDOR_SZ] = '\0';
704}
705
621626ce
EH		 706#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
707#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
708 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
709#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
710 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
711 CPUID_PSE36 | CPUID_FXSR)
712#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
713#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
714 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
715 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
716 CPUID_PAE | CPUID_SEP | CPUID_APIC)
717
718#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
719 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
720 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
721 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 722 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 723 /* partly implemented:
724 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
725 /* missing:
726 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
727#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
728 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
729 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 730 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 731 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
732 /* missing:
733 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
734 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
735 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 736 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
737 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 738
739#ifdef TARGET_X86_64
740#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
741#else
742#define TCG_EXT2_X86_64_FEATURES 0
743#endif
744
745#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
746 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
747 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
748 TCG_EXT2_X86_64_FEATURES)
749#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
750 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
751#define TCG_EXT4_FEATURES 0
fe441054 752#define TCG_SVM_FEATURES CPUID_SVM_NPT
621626ce
EH		 753#define TCG_KVM_FEATURES 0
754#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 755 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
756 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 757 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
758 CPUID_7_0_EBX_ERMS)
621626ce 759 /* missing:
07929f2a 760 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 761 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 762 CPUID_7_0_EBX_RDSEED */
9ccb9784
EH		 763#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
764 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
6c7c3c21 765 CPUID_7_0_ECX_LA57)
95ea69fb 766#define TCG_7_0_EDX_FEATURES 0
303752a9 767#define TCG_APM_FEATURES 0
28b8e4d0 768#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 769#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
770 /* missing:
771 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 772
07585923
RH		 773typedef enum FeatureWordType {
774 CPUID_FEATURE_WORD,
775 MSR_FEATURE_WORD,
776} FeatureWordType;
777
5ef57876 778typedef struct FeatureWordInfo {
07585923 779 FeatureWordType type;
2d5312da
EH		 780 /* feature flags names are taken from "Intel Processor Identification and
781 * the CPUID Instruction" and AMD's "CPUID Specification".
782 * In cases of disagreement between feature naming conventions,
783 * aliases may be added.
784 */
785 const char *feat_names[32];
07585923
RH		 786 union {
787 /* If type==CPUID_FEATURE_WORD */
788 struct {
789 uint32_t eax; /* Input EAX for CPUID */
790 bool needs_ecx; /* CPUID instruction uses ECX as input */
791 uint32_t ecx; /* Input ECX value for CPUID */
792 int reg; /* output register (R_* constant) */
793 } cpuid;
794 /* If type==MSR_FEATURE_WORD */
795 struct {
796 uint32_t index;
797 struct { /*CPUID that enumerate this MSR*/
798 FeatureWord cpuid_class;
799 uint32_t cpuid_flag;
800 } cpuid_dep;
801 } msr;
802 };
37ce3522 803 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 804 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 805 uint32_t migratable_flags; /* Feature flags known to be migratable */
0d914f39
EH		 806 /* Features that shouldn't be auto-enabled by "-cpu host" */
807 uint32_t no_autoenable_flags;
5ef57876
EH		 808} FeatureWordInfo;
809
810static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 811 [FEAT_1_EDX] = {
07585923 812 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 813 .feat_names = {
814 "fpu", "vme", "de", "pse",
815 "tsc", "msr", "pae", "mce",
816 "cx8", "apic", NULL, "sep",
817 "mtrr", "pge", "mca", "cmov",
818 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
819 NULL, "ds" /* Intel dts */, "acpi", "mmx",
820 "fxsr", "sse", "sse2", "ss",
821 "ht" /* Intel htt */, "tm", "ia64", "pbe",
822 },
07585923 823 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 824 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 825 },
826 [FEAT_1_ECX] = {
07585923 827 .type = CPUID_FEATURE_WORD,
2d5312da 828 .feat_names = {
16d2fcaa 829 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 830 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 831 "tm2", "ssse3", "cid", NULL,
832 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 833 NULL, "pcid", "dca", "sse4.1",
834 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 835 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 836 "avx", "f16c", "rdrand", "hypervisor",
837 },
07585923 838 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 839 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 840 },
2d5312da
EH		 841 /* Feature names that are already defined on feature_name[] but
842 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
843 * names on feat_names below. They are copied automatically
844 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
845 */
bffd67b0 846 [FEAT_8000_0001_EDX] = {
07585923 847 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 848 .feat_names = {
849 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
850 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
851 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
852 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
853 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 854 "nx", NULL, "mmxext", NULL /* mmx */,
855 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
856 NULL, "lm", "3dnowext", "3dnow",
2d5312da 857 },
07585923 858 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 859 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 860 },
861 [FEAT_8000_0001_ECX] = {
07585923 862 .type = CPUID_FEATURE_WORD,
2d5312da 863 .feat_names = {
fc7dfd20 864 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 865 "cr8legacy", "abm", "sse4a", "misalignsse",
866 "3dnowprefetch", "osvw", "ibs", "xop",
867 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 868 "fma4", "tce", NULL, "nodeid-msr",
869 NULL, "tbm", "topoext", "perfctr-core",
870 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 871 NULL, NULL, NULL, NULL,
872 },
07585923 873 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 874 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 875 /*
876 * TOPOEXT is always allowed but can't be enabled blindly by
877 * "-cpu host", as it requires consistent cache topology info
878 * to be provided so it doesn't confuse guests.
879 */
880 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 881 },
89e49c8b 882 [FEAT_C000_0001_EDX] = {
07585923 883 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 884 .feat_names = {
885 NULL, NULL, "xstore", "xstore-en",
886 NULL, NULL, "xcrypt", "xcrypt-en",
887 "ace2", "ace2-en", "phe", "phe-en",
888 "pmm", "pmm-en", NULL, NULL,
889 NULL, NULL, NULL, NULL,
890 NULL, NULL, NULL, NULL,
891 NULL, NULL, NULL, NULL,
892 NULL, NULL, NULL, NULL,
893 },
07585923 894 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 895 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 896 },
bffd67b0 897 [FEAT_KVM] = {
07585923 898 .type = CPUID_FEATURE_WORD,
2d5312da 899 .feat_names = {
fc7dfd20
EH		 900 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
901 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 902 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
2d5312da
EH		 903 NULL, NULL, NULL, NULL,
904 NULL, NULL, NULL, NULL,
905 NULL, NULL, NULL, NULL,
906 "kvmclock-stable-bit", NULL, NULL, NULL,
907 NULL, NULL, NULL, NULL,
908 },
07585923 909 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 910 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 911 },
be777326 912 [FEAT_KVM_HINTS] = {
07585923 913 .type = CPUID_FEATURE_WORD,
be777326
WL		 914 .feat_names = {
915 "kvm-hint-dedicated", NULL, NULL, NULL,
916 NULL, NULL, NULL, NULL,
917 NULL, NULL, NULL, NULL,
918 NULL, NULL, NULL, NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 },
07585923 924 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 925 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 926 /*
927 * KVM hints aren't auto-enabled by -cpu host, they need to be
928 * explicitly enabled in the command-line.
929 */
930 .no_autoenable_flags = ~0U,
be777326 931 },
abd5fc4c
VK		 932 /*
933 * .feat_names are commented out for Hyper-V enlightenments because we
934 * don't want to have two different ways for enabling them on QEMU command
935 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
936 * enabling several feature bits simultaneously, exposing these bits
937 * individually may just confuse guests.
938 */
c35bd19a 939 [FEAT_HYPERV_EAX] = {
07585923 940 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 941 .feat_names = {
942 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
943 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
944 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
945 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
946 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
947 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
ba6a4fd9
VK		 948 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
949 NULL, NULL,
2d5312da
EH		 950 NULL, NULL, NULL, NULL,
951 NULL, NULL, NULL, NULL,
952 NULL, NULL, NULL, NULL,
953 NULL, NULL, NULL, NULL,
954 },
07585923 955 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
c35bd19a
EY		 956 },
957 [FEAT_HYPERV_EBX] = {
07585923 958 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 959 .feat_names = {
960 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
961 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
962 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
963 NULL /* hv_create_port */, NULL /* hv_connect_port */,
964 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
965 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
966 NULL, NULL,
967 NULL, NULL, NULL, NULL,
968 NULL, NULL, NULL, NULL,
969 NULL, NULL, NULL, NULL,
970 NULL, NULL, NULL, NULL,
971 },
07585923 972 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
c35bd19a
EY		 973 },
974 [FEAT_HYPERV_EDX] = {
07585923 975 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 976 .feat_names = {
977 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
978 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
979 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
980 NULL, NULL,
981 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
982 NULL, NULL, NULL, NULL,
983 NULL, NULL, NULL, NULL,
984 NULL, NULL, NULL, NULL,
985 NULL, NULL, NULL, NULL,
986 NULL, NULL, NULL, NULL,
987 },
07585923 988 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
c35bd19a 989 },
a2b107db
VK		 990 [FEAT_HV_RECOMM_EAX] = {
991 .type = CPUID_FEATURE_WORD,
992 .feat_names = {
993 NULL /* hv_recommend_pv_as_switch */,
994 NULL /* hv_recommend_pv_tlbflush_local */,
995 NULL /* hv_recommend_pv_tlbflush_remote */,
996 NULL /* hv_recommend_msr_apic_access */,
997 NULL /* hv_recommend_msr_reset */,
998 NULL /* hv_recommend_relaxed_timing */,
999 NULL /* hv_recommend_dma_remapping */,
1000 NULL /* hv_recommend_int_remapping */,
1001 NULL /* hv_recommend_x2apic_msrs */,
1002 NULL /* hv_recommend_autoeoi_deprecation */,
1003 NULL /* hv_recommend_pv_ipi */,
1004 NULL /* hv_recommend_ex_hypercalls */,
1005 NULL /* hv_hypervisor_is_nested */,
1006 NULL /* hv_recommend_int_mbec */,
1007 NULL /* hv_recommend_evmcs */,
1008 NULL,
1009 NULL, NULL, NULL, NULL,
1010 NULL, NULL, NULL, NULL,
1011 NULL, NULL, NULL, NULL,
1012 NULL, NULL, NULL, NULL,
1013 },
1014 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
1015 },
1016 [FEAT_HV_NESTED_EAX] = {
1017 .type = CPUID_FEATURE_WORD,
1018 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
1019 },
bffd67b0 1020 [FEAT_SVM] = {
07585923 1021 .type = CPUID_FEATURE_WORD,
2d5312da 1022 .feat_names = {
fc7dfd20
EH		 1023 "npt", "lbrv", "svm-lock", "nrip-save",
1024 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1025 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 1026 "pfthreshold", NULL, NULL, NULL,
1027 NULL, NULL, NULL, NULL,
1028 NULL, NULL, NULL, NULL,
1029 NULL, NULL, NULL, NULL,
1030 NULL, NULL, NULL, NULL,
1031 },
07585923 1032 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 1033 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 1034 },
1035 [FEAT_7_0_EBX] = {
07585923 1036 .type = CPUID_FEATURE_WORD,
2d5312da 1037 .feat_names = {
fc7dfd20 1038 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 1039 "hle", "avx2", NULL, "smep",
1040 "bmi2", "erms", "invpcid", "rtm",
1041 NULL, NULL, "mpx", NULL,
1042 "avx512f", "avx512dq", "rdseed", "adx",
1043 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 1044 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 1045 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 1046 },
07585923
RH		 1047 .cpuid = {
1048 .eax = 7,
1049 .needs_ecx = true, .ecx = 0,
1050 .reg = R_EBX,
1051 },
37ce3522 1052 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 1053 },
f74eefe0 1054 [FEAT_7_0_ECX] = {
07585923 1055 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1056 .feat_names = {
1057 NULL, "avx512vbmi", "umip", "pku",
9ccb9784 1058 NULL /* ospke */, NULL, "avx512vbmi2", NULL,
aff9e6e4
YZ		 1059 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1060 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 1061 "la57", NULL, NULL, NULL,
2d5312da 1062 NULL, NULL, "rdpid", NULL,
24261de4 1063 NULL, "cldemote", NULL, "movdiri",
1c65775f 1064 "movdir64b", NULL, NULL, NULL,
2d5312da 1065 },
07585923
RH		 1066 .cpuid = {
1067 .eax = 7,
1068 .needs_ecx = true, .ecx = 0,
1069 .reg = R_ECX,
1070 },
f74eefe0
HH		 1071 .tcg_features = TCG_7_0_ECX_FEATURES,
1072 },
95ea69fb 1073 [FEAT_7_0_EDX] = {
07585923 1074 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 1075 .feat_names = {
1076 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1077 NULL, NULL, NULL, NULL,
1078 NULL, NULL, NULL, NULL,
1079 NULL, NULL, NULL, NULL,
5131dc43 1080 NULL, NULL, "pconfig", NULL,
95ea69fb 1081 NULL, NULL, NULL, NULL,
0e891658 1082 NULL, NULL, "spec-ctrl", "stibp",
3fc7c731 1083 NULL, "arch-capabilities", NULL, "ssbd",
95ea69fb 1084 },
07585923
RH		 1085 .cpuid = {
1086 .eax = 7,
1087 .needs_ecx = true, .ecx = 0,
1088 .reg = R_EDX,
1089 },
95ea69fb 1090 .tcg_features = TCG_7_0_EDX_FEATURES,
3fc7c731 1091 .unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES,
95ea69fb 1092 },
303752a9 1093 [FEAT_8000_0007_EDX] = {
07585923 1094 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1095 .feat_names = {
1096 NULL, NULL, NULL, NULL,
1097 NULL, NULL, NULL, NULL,
1098 "invtsc", NULL, NULL, NULL,
1099 NULL, NULL, NULL, NULL,
1100 NULL, NULL, NULL, NULL,
1101 NULL, NULL, NULL, NULL,
1102 NULL, NULL, NULL, NULL,
1103 NULL, NULL, NULL, NULL,
1104 },
07585923 1105 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 1106 .tcg_features = TCG_APM_FEATURES,
1107 .unmigratable_flags = CPUID_APM_INVTSC,
1108 },
1b3420e1 1109 [FEAT_8000_0008_EBX] = {
07585923 1110 .type = CPUID_FEATURE_WORD,
1b3420e1
EH		 1111 .feat_names = {
1112 NULL, NULL, NULL, NULL,
1113 NULL, NULL, NULL, NULL,
59a80a19 1114 NULL, "wbnoinvd", NULL, NULL,
1b3420e1
EH		 1115 "ibpb", NULL, NULL, NULL,
1116 NULL, NULL, NULL, NULL,
1117 NULL, NULL, NULL, NULL,
254790a9 1118 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 1119 NULL, NULL, NULL, NULL,
1120 },
07585923 1121 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 1122 .tcg_features = 0,
1123 .unmigratable_flags = 0,
1124 },
0bb0b2d2 1125 [FEAT_XSAVE] = {
07585923 1126 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1127 .feat_names = {
1128 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1129 NULL, NULL, NULL, NULL,
1130 NULL, NULL, NULL, NULL,
1131 NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 },
07585923
RH		 1137 .cpuid = {
1138 .eax = 0xd,
1139 .needs_ecx = true, .ecx = 1,
1140 .reg = R_EAX,
1141 },
c9cfe8f9 1142 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 1143 },
28b8e4d0 1144 [FEAT_6_EAX] = {
07585923 1145 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1146 .feat_names = {
1147 NULL, NULL, "arat", NULL,
1148 NULL, NULL, NULL, NULL,
1149 NULL, NULL, NULL, NULL,
1150 NULL, NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 },
07585923 1156 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 1157 .tcg_features = TCG_6_EAX_FEATURES,
1158 },
96193c22 1159 [FEAT_XSAVE_COMP_LO] = {
07585923
RH		 1160 .type = CPUID_FEATURE_WORD,
1161 .cpuid = {
1162 .eax = 0xD,
1163 .needs_ecx = true, .ecx = 0,
1164 .reg = R_EAX,
1165 },
96193c22 1166 .tcg_features = ~0U,
6fb2fff7
EH		 1167 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1168 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1169 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1170 XSTATE_PKRU_MASK,
96193c22
EH		 1171 },
1172 [FEAT_XSAVE_COMP_HI] = {
07585923
RH		 1173 .type = CPUID_FEATURE_WORD,
1174 .cpuid = {
1175 .eax = 0xD,
1176 .needs_ecx = true, .ecx = 0,
1177 .reg = R_EDX,
1178 },
96193c22
EH		 1179 .tcg_features = ~0U,
1180 },
d86f9636
RH		 1181 /*Below are MSR exposed features*/
1182 [FEAT_ARCH_CAPABILITIES] = {
1183 .type = MSR_FEATURE_WORD,
1184 .feat_names = {
1185 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1186 "ssb-no", NULL, NULL, NULL,
1187 NULL, NULL, NULL, NULL,
1188 NULL, NULL, NULL, NULL,
1189 NULL, NULL, NULL, NULL,
1190 NULL, NULL, NULL, NULL,
1191 NULL, NULL, NULL, NULL,
1192 NULL, NULL, NULL, NULL,
1193 },
1194 .msr = {
1195 .index = MSR_IA32_ARCH_CAPABILITIES,
1196 .cpuid_dep = {
1197 FEAT_7_0_EDX,
1198 CPUID_7_0_EDX_ARCH_CAPABILITIES
1199 }
1200 },
1201 },
5ef57876
EH		 1202};
1203
8e8aba50
EH		 1204typedef struct X86RegisterInfo32 {
1205 /* Name of register */
1206 const char *name;
1207 /* QAPI enum value register */
1208 X86CPURegister32 qapi_enum;
1209} X86RegisterInfo32;
1210
1211#define REGISTER(reg) \
5d371f41 1212 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1213static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1214 REGISTER(EAX),
1215 REGISTER(ECX),
1216 REGISTER(EDX),
1217 REGISTER(EBX),
1218 REGISTER(ESP),
1219 REGISTER(EBP),
1220 REGISTER(ESI),
1221 REGISTER(EDI),
1222};
1223#undef REGISTER
1224
3f32bd21
RH		 1225typedef struct ExtSaveArea {
1226 uint32_t feature, bits;
1227 uint32_t offset, size;
1228} ExtSaveArea;
1229
1230static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 1231 [XSTATE_FP_BIT] = {
1232 /* x87 FP state component is always enabled if XSAVE is supported */
1233 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1234 /* x87 state is in the legacy region of the XSAVE area */
1235 .offset = 0,
1236 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1237 },
1238 [XSTATE_SSE_BIT] = {
1239 /* SSE state component is always enabled if XSAVE is supported */
1240 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1241 /* SSE state is in the legacy region of the XSAVE area */
1242 .offset = 0,
1243 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1244 },
cfc3b074
PB		 1245 [XSTATE_YMM_BIT] =
1246 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 1247 .offset = offsetof(X86XSaveArea, avx_state),
1248 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1249 [XSTATE_BNDREGS_BIT] =
1250 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1251 .offset = offsetof(X86XSaveArea, bndreg_state),
1252 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1253 [XSTATE_BNDCSR_BIT] =
1254 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1255 .offset = offsetof(X86XSaveArea, bndcsr_state),
1256 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1257 [XSTATE_OPMASK_BIT] =
1258 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1259 .offset = offsetof(X86XSaveArea, opmask_state),
1260 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1261 [XSTATE_ZMM_Hi256_BIT] =
1262 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1263 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1264 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1265 [XSTATE_Hi16_ZMM_BIT] =
1266 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1267 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1268 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1269 [XSTATE_PKRU_BIT] =
1270 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 1271 .offset = offsetof(X86XSaveArea, pkru_state),
1272 .size = sizeof(XSavePKRU) },
2560f19f 1273};
8e8aba50 1274
1fda6198
EH		 1275static uint32_t xsave_area_size(uint64_t mask)
1276{
1277 int i;
e3c9022b 1278 uint64_t ret = 0;
1fda6198 1279
e3c9022b 1280 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1281 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1282 if ((mask >> i) & 1) {
1283 ret = MAX(ret, esa->offset + esa->size);
1284 }
1285 }
1286 return ret;
1287}
1288
d6dcc558
SAGDR		 1289static inline bool accel_uses_host_cpuid(void)
1290{
1291 return kvm_enabled() || hvf_enabled();
1292}
1293
96193c22
EH		 1294static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1295{
1296 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1297 cpu->env.features[FEAT_XSAVE_COMP_LO];
1298}
1299
8b4beddc
EH		 1300const char *get_register_name_32(unsigned int reg)
1301{
31ccdde2 1302 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1303 return NULL;
1304 }
8e8aba50 1305 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1306}
1307
84f1b92f
EH		 1308/*
1309 * Returns the set of feature flags that are supported and migratable by
1310 * QEMU, for a given FeatureWord.
1311 */
1312static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1313{
1314 FeatureWordInfo *wi = &feature_word_info[w];
1315 uint32_t r = 0;
1316 int i;
1317
1318 for (i = 0; i < 32; i++) {
1319 uint32_t f = 1U << i;
6fb2fff7
EH		 1320
1321 /* If the feature name is known, it is implicitly considered migratable,
1322 * unless it is explicitly set in unmigratable_flags */
1323 if ((wi->migratable_flags & f) ||
1324 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1325 r |= f;
84f1b92f 1326 }
84f1b92f
EH		 1327 }
1328 return r;
1329}
1330
bb44e0d1
JK		 1331void host_cpuid(uint32_t function, uint32_t count,
1332 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1333{
a1fd24af
AL		 1334 uint32_t vec[4];
1335
1336#ifdef __x86_64__
1337 asm volatile("cpuid"
1338 : "=a"(vec[0]), "=b"(vec[1]),
1339 "=c"(vec[2]), "=d"(vec[3])
1340 : "0"(function), "c"(count) : "cc");
c1f41226 1341#elif defined(__i386__)
a1fd24af
AL		 1342 asm volatile("pusha \n\t"
1343 "cpuid \n\t"
1344 "mov %%eax, 0(%2) \n\t"
1345 "mov %%ebx, 4(%2) \n\t"
1346 "mov %%ecx, 8(%2) \n\t"
1347 "mov %%edx, 12(%2) \n\t"
1348 "popa"
1349 : : "a"(function), "c"(count), "S"(vec)
1350 : "memory", "cc");
c1f41226
EH		 1351#else
1352 abort();
a1fd24af
AL		 1353#endif
1354
bdde476a 1355 if (eax)
a1fd24af 1356 *eax = vec[0];
bdde476a 1357 if (ebx)
a1fd24af 1358 *ebx = vec[1];
bdde476a 1359 if (ecx)
a1fd24af 1360 *ecx = vec[2];
bdde476a 1361 if (edx)
a1fd24af 1362 *edx = vec[3];
bdde476a 1363}
c6dc6f63 1364
20271d48
EH		 1365void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1366{
1367 uint32_t eax, ebx, ecx, edx;
1368
1369 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1370 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1371
1372 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1373 if (family) {
1374 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1375 }
1376 if (model) {
1377 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1378 }
1379 if (stepping) {
1380 *stepping = eax & 0x0F;
1381 }
1382}
1383
d940ee9b
EH		 1384/* CPU class name definitions: */
1385
d940ee9b
EH		 1386/* Return type name for a given CPU model name
1387 * Caller is responsible for freeing the returned string.
1388 */
1389static char *x86_cpu_type_name(const char *model_name)
1390{
1391 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1392}
1393
500050d1
AF		 1394static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1395{
d940ee9b 1396 ObjectClass *oc;
99193d8f 1397 char *typename = x86_cpu_type_name(cpu_model);
d940ee9b
EH		 1398 oc = object_class_by_name(typename);
1399 g_free(typename);
1400 return oc;
500050d1
AF		 1401}
1402
104494ea
IM		 1403static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1404{
1405 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1406 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1407 return g_strndup(class_name,
1408 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1409}
1410
d940ee9b 1411struct X86CPUDefinition {
c6dc6f63
AP		 1412 const char *name;
1413 uint32_t level;
90e4b0c3 1414 uint32_t xlevel;
99b88a17
IM		 1415 /* vendor is zero-terminated, 12 character ASCII string */
1416 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1417 int family;
1418 int model;
1419 int stepping;
0514ef2f 1420 FeatureWordArray features;
807e9869 1421 const char *model_id;
6aaeb054 1422 CPUCaches *cache_info;
d940ee9b 1423};
c6dc6f63 1424
fe52acd2 1425static CPUCaches epyc_cache_info = {
a9f27ea9 1426 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1427 .type = DATA_CACHE,
fe52acd2
BM		 1428 .level = 1,
1429 .size = 32 * KiB,
1430 .line_size = 64,
1431 .associativity = 8,
1432 .partitions = 1,
1433 .sets = 64,
1434 .lines_per_tag = 1,
1435 .self_init = 1,
1436 .no_invd_sharing = true,
1437 },
a9f27ea9 1438 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1439 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1440 .level = 1,
1441 .size = 64 * KiB,
1442 .line_size = 64,
1443 .associativity = 4,
1444 .partitions = 1,
1445 .sets = 256,
1446 .lines_per_tag = 1,
1447 .self_init = 1,
1448 .no_invd_sharing = true,
1449 },
a9f27ea9 1450 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1451 .type = UNIFIED_CACHE,
1452 .level = 2,
1453 .size = 512 * KiB,
1454 .line_size = 64,
1455 .associativity = 8,
1456 .partitions = 1,
1457 .sets = 1024,
1458 .lines_per_tag = 1,
1459 },
a9f27ea9 1460 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1461 .type = UNIFIED_CACHE,
1462 .level = 3,
1463 .size = 8 * MiB,
1464 .line_size = 64,
1465 .associativity = 16,
1466 .partitions = 1,
1467 .sets = 8192,
1468 .lines_per_tag = 1,
1469 .self_init = true,
1470 .inclusive = true,
1471 .complex_indexing = true,
1472 },
1473};
1474
9576de75 1475static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1476 {
1477 .name = "qemu64",
3046bb5d 1478 .level = 0xd,
99b88a17 1479 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 1480 .family = 6,
f8e6a11a 1481 .model = 6,
c6dc6f63 1482 .stepping = 3,
0514ef2f 1483 .features[FEAT_1_EDX] =
27861ecc 1484 PPRO_FEATURES |
c6dc6f63 1485 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1486 CPUID_PSE36,
0514ef2f 1487 .features[FEAT_1_ECX] =
6aa91e4a 1488 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1489 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1490 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1491 .features[FEAT_8000_0001_ECX] =
71195672 1492 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1493 .xlevel = 0x8000000A,
9cf2cc3d 1494 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1495 },
1496 {
1497 .name = "phenom",
1498 .level = 5,
99b88a17 1499 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1500 .family = 16,
1501 .model = 2,
1502 .stepping = 3,
b9fc20bc 1503 /* Missing: CPUID_HT */
0514ef2f 1504 .features[FEAT_1_EDX] =
27861ecc 1505 PPRO_FEATURES |
c6dc6f63 1506 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1507 CPUID_PSE36 | CPUID_VME,
0514ef2f 1508 .features[FEAT_1_ECX] =
27861ecc 1509 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1510 CPUID_EXT_POPCNT,
0514ef2f 1511 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1512 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1513 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1514 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1515 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1516 CPUID_EXT3_CR8LEG,
1517 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1518 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1519 .features[FEAT_8000_0001_ECX] =
27861ecc 1520 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1521 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1522 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1523 .features[FEAT_SVM] =
b9fc20bc 1524 CPUID_SVM_NPT,
c6dc6f63
AP		 1525 .xlevel = 0x8000001A,
1526 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1527 },
1528 {
1529 .name = "core2duo",
1530 .level = 10,
99b88a17 1531 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1532 .family = 6,
1533 .model = 15,
1534 .stepping = 11,
b9fc20bc 1535 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1536 .features[FEAT_1_EDX] =
27861ecc 1537 PPRO_FEATURES |
c6dc6f63 1538 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1539 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1540 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1541 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1542 .features[FEAT_1_ECX] =
27861ecc 1543 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1544 CPUID_EXT_CX16,
0514ef2f 1545 .features[FEAT_8000_0001_EDX] =
27861ecc 1546 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1547 .features[FEAT_8000_0001_ECX] =
27861ecc 1548 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 1549 .xlevel = 0x80000008,
1550 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1551 },
1552 {
1553 .name = "kvm64",
3046bb5d 1554 .level = 0xd,
99b88a17 1555 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1556 .family = 15,
1557 .model = 6,
1558 .stepping = 1,
b3a4f0b1 1559 /* Missing: CPUID_HT */
0514ef2f 1560 .features[FEAT_1_EDX] =
b3a4f0b1 1561 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1562 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1563 CPUID_PSE36,
1564 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1565 .features[FEAT_1_ECX] =
27861ecc 1566 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1567 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1568 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1569 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1570 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1571 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1572 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1573 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1574 .features[FEAT_8000_0001_ECX] =
27861ecc 1575 0,
c6dc6f63
AP		 1576 .xlevel = 0x80000008,
1577 .model_id = "Common KVM processor"
1578 },
c6dc6f63
AP		 1579 {
1580 .name = "qemu32",
1581 .level = 4,
99b88a17 1582 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1583 .family = 6,
f8e6a11a 1584 .model = 6,
c6dc6f63 1585 .stepping = 3,
0514ef2f 1586 .features[FEAT_1_EDX] =
27861ecc 1587 PPRO_FEATURES,
0514ef2f 1588 .features[FEAT_1_ECX] =
6aa91e4a 1589 CPUID_EXT_SSE3,
58012d66 1590 .xlevel = 0x80000004,
9cf2cc3d 1591 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1592 },
eafaf1e5
AP		 1593 {
1594 .name = "kvm32",
1595 .level = 5,
99b88a17 1596 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1597 .family = 15,
1598 .model = 6,
1599 .stepping = 1,
0514ef2f 1600 .features[FEAT_1_EDX] =
b3a4f0b1 1601 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1602 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1603 .features[FEAT_1_ECX] =
27861ecc 1604 CPUID_EXT_SSE3,
0514ef2f 1605 .features[FEAT_8000_0001_ECX] =
27861ecc 1606 0,
eafaf1e5
AP		 1607 .xlevel = 0x80000008,
1608 .model_id = "Common 32-bit KVM processor"
1609 },
c6dc6f63
AP		 1610 {
1611 .name = "coreduo",
1612 .level = 10,
99b88a17 1613 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1614 .family = 6,
1615 .model = 14,
1616 .stepping = 8,
b9fc20bc 1617 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1618 .features[FEAT_1_EDX] =
27861ecc 1619 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1620 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1621 CPUID_SS,
1622 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1623 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1624 .features[FEAT_1_ECX] =
e93abc14 1625 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1626 .features[FEAT_8000_0001_EDX] =
27861ecc 1627 CPUID_EXT2_NX,
c6dc6f63
AP		 1628 .xlevel = 0x80000008,
1629 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1630 },
1631 {
1632 .name = "486",
58012d66 1633 .level = 1,
99b88a17 1634 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1635 .family = 4,
b2a856d9 1636 .model = 8,
c6dc6f63 1637 .stepping = 0,
0514ef2f 1638 .features[FEAT_1_EDX] =
27861ecc 1639 I486_FEATURES,
c6dc6f63 1640 .xlevel = 0,
807e9869 1641 .model_id = "",
c6dc6f63
AP		 1642 },
1643 {
1644 .name = "pentium",
1645 .level = 1,
99b88a17 1646 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1647 .family = 5,
1648 .model = 4,
1649 .stepping = 3,
0514ef2f 1650 .features[FEAT_1_EDX] =
27861ecc 1651 PENTIUM_FEATURES,
c6dc6f63 1652 .xlevel = 0,
807e9869 1653 .model_id = "",
c6dc6f63
AP		 1654 },
1655 {
1656 .name = "pentium2",
1657 .level = 2,
99b88a17 1658 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1659 .family = 6,
1660 .model = 5,
1661 .stepping = 2,
0514ef2f 1662 .features[FEAT_1_EDX] =
27861ecc 1663 PENTIUM2_FEATURES,
c6dc6f63 1664 .xlevel = 0,
807e9869 1665 .model_id = "",
c6dc6f63
AP		 1666 },
1667 {
1668 .name = "pentium3",
3046bb5d 1669 .level = 3,
99b88a17 1670 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1671 .family = 6,
1672 .model = 7,
1673 .stepping = 3,
0514ef2f 1674 .features[FEAT_1_EDX] =
27861ecc 1675 PENTIUM3_FEATURES,
c6dc6f63 1676 .xlevel = 0,
807e9869 1677 .model_id = "",
c6dc6f63
AP		 1678 },
1679 {
1680 .name = "athlon",
1681 .level = 2,
99b88a17 1682 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1683 .family = 6,
1684 .model = 2,
1685 .stepping = 3,
0514ef2f 1686 .features[FEAT_1_EDX] =
27861ecc 1687 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 1688 CPUID_MCA,
0514ef2f 1689 .features[FEAT_8000_0001_EDX] =
60032ac0 1690 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 1691 .xlevel = 0x80000008,
9cf2cc3d 1692 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1693 },
1694 {
1695 .name = "n270",
3046bb5d 1696 .level = 10,
99b88a17 1697 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1698 .family = 6,
1699 .model = 28,
1700 .stepping = 2,
b9fc20bc 1701 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1702 .features[FEAT_1_EDX] =
27861ecc 1703 PPRO_FEATURES |
b9fc20bc
EH		 1704 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1705 CPUID_ACPI | CPUID_SS,
c6dc6f63 1706 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1707 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1708 * CPUID_EXT_XTPR */
0514ef2f 1709 .features[FEAT_1_ECX] =
27861ecc 1710 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1711 CPUID_EXT_MOVBE,
0514ef2f 1712 .features[FEAT_8000_0001_EDX] =
60032ac0 1713 CPUID_EXT2_NX,
0514ef2f 1714 .features[FEAT_8000_0001_ECX] =
27861ecc 1715 CPUID_EXT3_LAHF_LM,
3046bb5d 1716 .xlevel = 0x80000008,
c6dc6f63
AP		 1717 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1718 },
3eca4642
EH		 1719 {
1720 .name = "Conroe",
3046bb5d 1721 .level = 10,
99b88a17 1722 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1723 .family = 6,
ffce9ebb 1724 .model = 15,
3eca4642 1725 .stepping = 3,
0514ef2f 1726 .features[FEAT_1_EDX] =
b3a4f0b1 1727 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1728 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1729 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1730 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1731 CPUID_DE | CPUID_FP87,
0514ef2f 1732 .features[FEAT_1_ECX] =
27861ecc 1733 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1734 .features[FEAT_8000_0001_EDX] =
27861ecc 1735 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1736 .features[FEAT_8000_0001_ECX] =
27861ecc 1737 CPUID_EXT3_LAHF_LM,
3046bb5d 1738 .xlevel = 0x80000008,
3eca4642
EH		 1739 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1740 },
1741 {
1742 .name = "Penryn",
3046bb5d 1743 .level = 10,
99b88a17 1744 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1745 .family = 6,
ffce9ebb 1746 .model = 23,
3eca4642 1747 .stepping = 3,
0514ef2f 1748 .features[FEAT_1_EDX] =
b3a4f0b1 1749 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1750 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1751 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1752 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1753 CPUID_DE | CPUID_FP87,
0514ef2f 1754 .features[FEAT_1_ECX] =
27861ecc 1755 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1756 CPUID_EXT_SSE3,
0514ef2f 1757 .features[FEAT_8000_0001_EDX] =
27861ecc 1758 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1759 .features[FEAT_8000_0001_ECX] =
27861ecc 1760 CPUID_EXT3_LAHF_LM,
3046bb5d 1761 .xlevel = 0x80000008,
3eca4642
EH		 1762 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1763 },
1764 {
1765 .name = "Nehalem",
3046bb5d 1766 .level = 11,
99b88a17 1767 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1768 .family = 6,
ffce9ebb 1769 .model = 26,
3eca4642 1770 .stepping = 3,
0514ef2f 1771 .features[FEAT_1_EDX] =
b3a4f0b1 1772 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1773 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1774 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1775 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1776 CPUID_DE | CPUID_FP87,
0514ef2f 1777 .features[FEAT_1_ECX] =
27861ecc 1778 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1779 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1780 .features[FEAT_8000_0001_EDX] =
27861ecc 1781 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1782 .features[FEAT_8000_0001_ECX] =
27861ecc 1783 CPUID_EXT3_LAHF_LM,
3046bb5d 1784 .xlevel = 0x80000008,
3eca4642
EH		 1785 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1786 },
ac96c413
EH		 1787 {
1788 .name = "Nehalem-IBRS",
1789 .level = 11,
1790 .vendor = CPUID_VENDOR_INTEL,
1791 .family = 6,
1792 .model = 26,
1793 .stepping = 3,
1794 .features[FEAT_1_EDX] =
1795 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1796 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1797 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1798 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1799 CPUID_DE | CPUID_FP87,
1800 .features[FEAT_1_ECX] =
1801 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1802 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1803 .features[FEAT_7_0_EDX] =
1804 CPUID_7_0_EDX_SPEC_CTRL,
1805 .features[FEAT_8000_0001_EDX] =
1806 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1807 .features[FEAT_8000_0001_ECX] =
1808 CPUID_EXT3_LAHF_LM,
1809 .xlevel = 0x80000008,
1810 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1811 },
3eca4642
EH		 1812 {
1813 .name = "Westmere",
1814 .level = 11,
99b88a17 1815 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1816 .family = 6,
1817 .model = 44,
1818 .stepping = 1,
0514ef2f 1819 .features[FEAT_1_EDX] =
b3a4f0b1 1820 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1821 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1822 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1823 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1824 CPUID_DE | CPUID_FP87,
0514ef2f 1825 .features[FEAT_1_ECX] =
27861ecc 1826 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1827 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1828 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1829 .features[FEAT_8000_0001_EDX] =
27861ecc 1830 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1831 .features[FEAT_8000_0001_ECX] =
27861ecc 1832 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1833 .features[FEAT_6_EAX] =
1834 CPUID_6_EAX_ARAT,
3046bb5d 1835 .xlevel = 0x80000008,
3eca4642
EH		 1836 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1837 },
ac96c413
EH		 1838 {
1839 .name = "Westmere-IBRS",
1840 .level = 11,
1841 .vendor = CPUID_VENDOR_INTEL,
1842 .family = 6,
1843 .model = 44,
1844 .stepping = 1,
1845 .features[FEAT_1_EDX] =
1846 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1847 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1848 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1849 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1850 CPUID_DE | CPUID_FP87,
1851 .features[FEAT_1_ECX] =
1852 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1853 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1854 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1855 .features[FEAT_8000_0001_EDX] =
1856 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1857 .features[FEAT_8000_0001_ECX] =
1858 CPUID_EXT3_LAHF_LM,
1859 .features[FEAT_7_0_EDX] =
1860 CPUID_7_0_EDX_SPEC_CTRL,
1861 .features[FEAT_6_EAX] =
1862 CPUID_6_EAX_ARAT,
1863 .xlevel = 0x80000008,
1864 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1865 },
3eca4642
EH		 1866 {
1867 .name = "SandyBridge",
1868 .level = 0xd,
99b88a17 1869 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1870 .family = 6,
1871 .model = 42,
1872 .stepping = 1,
0514ef2f 1873 .features[FEAT_1_EDX] =
b3a4f0b1 1874 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1875 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1876 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1877 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1878 CPUID_DE | CPUID_FP87,
0514ef2f 1879 .features[FEAT_1_ECX] =
27861ecc 1880 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1881 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1882 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1883 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1884 CPUID_EXT_SSE3,
0514ef2f 1885 .features[FEAT_8000_0001_EDX] =
27861ecc 1886 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1887 CPUID_EXT2_SYSCALL,
0514ef2f 1888 .features[FEAT_8000_0001_ECX] =
27861ecc 1889 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1890 .features[FEAT_XSAVE] =
1891 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1892 .features[FEAT_6_EAX] =
1893 CPUID_6_EAX_ARAT,
3046bb5d 1894 .xlevel = 0x80000008,
3eca4642
EH		 1895 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1896 },
ac96c413
EH		 1897 {
1898 .name = "SandyBridge-IBRS",
1899 .level = 0xd,
1900 .vendor = CPUID_VENDOR_INTEL,
1901 .family = 6,
1902 .model = 42,
1903 .stepping = 1,
1904 .features[FEAT_1_EDX] =
1905 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1906 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1907 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1908 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1909 CPUID_DE | CPUID_FP87,
1910 .features[FEAT_1_ECX] =
1911 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1912 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1913 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1914 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1915 CPUID_EXT_SSE3,
1916 .features[FEAT_8000_0001_EDX] =
1917 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1918 CPUID_EXT2_SYSCALL,
1919 .features[FEAT_8000_0001_ECX] =
1920 CPUID_EXT3_LAHF_LM,
1921 .features[FEAT_7_0_EDX] =
1922 CPUID_7_0_EDX_SPEC_CTRL,
1923 .features[FEAT_XSAVE] =
1924 CPUID_XSAVE_XSAVEOPT,
1925 .features[FEAT_6_EAX] =
1926 CPUID_6_EAX_ARAT,
1927 .xlevel = 0x80000008,
1928 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1929 },
2f9ac42a
PB		 1930 {
1931 .name = "IvyBridge",
1932 .level = 0xd,
1933 .vendor = CPUID_VENDOR_INTEL,
1934 .family = 6,
1935 .model = 58,
1936 .stepping = 9,
1937 .features[FEAT_1_EDX] =
1938 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1939 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1940 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1941 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1942 CPUID_DE | CPUID_FP87,
1943 .features[FEAT_1_ECX] =
1944 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1945 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1946 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1947 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1948 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1949 .features[FEAT_7_0_EBX] =
1950 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1951 CPUID_7_0_EBX_ERMS,
1952 .features[FEAT_8000_0001_EDX] =
1953 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1954 CPUID_EXT2_SYSCALL,
1955 .features[FEAT_8000_0001_ECX] =
1956 CPUID_EXT3_LAHF_LM,
1957 .features[FEAT_XSAVE] =
1958 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1959 .features[FEAT_6_EAX] =
1960 CPUID_6_EAX_ARAT,
3046bb5d 1961 .xlevel = 0x80000008,
2f9ac42a
PB		 1962 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1963 },
ac96c413
EH		 1964 {
1965 .name = "IvyBridge-IBRS",
1966 .level = 0xd,
1967 .vendor = CPUID_VENDOR_INTEL,
1968 .family = 6,
1969 .model = 58,
1970 .stepping = 9,
1971 .features[FEAT_1_EDX] =
1972 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1973 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1974 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1975 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1976 CPUID_DE | CPUID_FP87,
1977 .features[FEAT_1_ECX] =
1978 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1979 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1980 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1981 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1982 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1983 .features[FEAT_7_0_EBX] =
1984 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1985 CPUID_7_0_EBX_ERMS,
1986 .features[FEAT_8000_0001_EDX] =
1987 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1988 CPUID_EXT2_SYSCALL,
1989 .features[FEAT_8000_0001_ECX] =
1990 CPUID_EXT3_LAHF_LM,
1991 .features[FEAT_7_0_EDX] =
1992 CPUID_7_0_EDX_SPEC_CTRL,
1993 .features[FEAT_XSAVE] =
1994 CPUID_XSAVE_XSAVEOPT,
1995 .features[FEAT_6_EAX] =
1996 CPUID_6_EAX_ARAT,
1997 .xlevel = 0x80000008,
1998 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
1999 },
37507094 2000 {
a356850b
EH		 2001 .name = "Haswell-noTSX",
2002 .level = 0xd,
2003 .vendor = CPUID_VENDOR_INTEL,
2004 .family = 6,
2005 .model = 60,
2006 .stepping = 1,
2007 .features[FEAT_1_EDX] =
2008 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2009 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2010 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2011 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2012 CPUID_DE | CPUID_FP87,
2013 .features[FEAT_1_ECX] =
2014 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2015 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2016 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2017 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2018 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2019 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2020 .features[FEAT_8000_0001_EDX] =
2021 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2022 CPUID_EXT2_SYSCALL,
2023 .features[FEAT_8000_0001_ECX] =
becb6667 2024 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 2025 .features[FEAT_7_0_EBX] =
2026 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2027 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2028 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2029 .features[FEAT_XSAVE] =
2030 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2031 .features[FEAT_6_EAX] =
2032 CPUID_6_EAX_ARAT,
3046bb5d 2033 .xlevel = 0x80000008,
a356850b 2034 .model_id = "Intel Core Processor (Haswell, no TSX)",
ac96c413
EH		 2035 },
2036 {
2037 .name = "Haswell-noTSX-IBRS",
2038 .level = 0xd,
2039 .vendor = CPUID_VENDOR_INTEL,
2040 .family = 6,
2041 .model = 60,
2042 .stepping = 1,
2043 .features[FEAT_1_EDX] =
2044 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2045 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2046 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2047 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2048 CPUID_DE | CPUID_FP87,
2049 .features[FEAT_1_ECX] =
2050 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2051 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2052 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2053 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2054 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2055 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2056 .features[FEAT_8000_0001_EDX] =
2057 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2058 CPUID_EXT2_SYSCALL,
2059 .features[FEAT_8000_0001_ECX] =
2060 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2061 .features[FEAT_7_0_EDX] =
2062 CPUID_7_0_EDX_SPEC_CTRL,
2063 .features[FEAT_7_0_EBX] =
2064 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2065 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2066 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2067 .features[FEAT_XSAVE] =
2068 CPUID_XSAVE_XSAVEOPT,
2069 .features[FEAT_6_EAX] =
2070 CPUID_6_EAX_ARAT,
2071 .xlevel = 0x80000008,
2072 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
2073 },
2074 {
37507094
EH		 2075 .name = "Haswell",
2076 .level = 0xd,
99b88a17 2077 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2078 .family = 6,
2079 .model = 60,
ec56a4a7 2080 .stepping = 4,
0514ef2f 2081 .features[FEAT_1_EDX] =
b3a4f0b1 2082 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2083 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2084 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2085 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2086 CPUID_DE | CPUID_FP87,
0514ef2f 2087 .features[FEAT_1_ECX] =
27861ecc 2088 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2089 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2090 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2091 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2092 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2093 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2094 .features[FEAT_8000_0001_EDX] =
27861ecc 2095 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2096 CPUID_EXT2_SYSCALL,
0514ef2f 2097 .features[FEAT_8000_0001_ECX] =
becb6667 2098 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2099 .features[FEAT_7_0_EBX] =
27861ecc 2100 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2101 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2102 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2103 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2104 .features[FEAT_XSAVE] =
2105 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2106 .features[FEAT_6_EAX] =
2107 CPUID_6_EAX_ARAT,
3046bb5d 2108 .xlevel = 0x80000008,
37507094
EH		 2109 .model_id = "Intel Core Processor (Haswell)",
2110 },
ac96c413
EH		 2111 {
2112 .name = "Haswell-IBRS",
2113 .level = 0xd,
2114 .vendor = CPUID_VENDOR_INTEL,
2115 .family = 6,
2116 .model = 60,
2117 .stepping = 4,
2118 .features[FEAT_1_EDX] =
2119 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2120 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2121 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2122 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2123 CPUID_DE | CPUID_FP87,
2124 .features[FEAT_1_ECX] =
2125 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2126 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2127 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2128 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2129 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2130 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2131 .features[FEAT_8000_0001_EDX] =
2132 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2133 CPUID_EXT2_SYSCALL,
2134 .features[FEAT_8000_0001_ECX] =
2135 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2136 .features[FEAT_7_0_EDX] =
2137 CPUID_7_0_EDX_SPEC_CTRL,
2138 .features[FEAT_7_0_EBX] =
2139 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2140 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2141 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2142 CPUID_7_0_EBX_RTM,
2143 .features[FEAT_XSAVE] =
2144 CPUID_XSAVE_XSAVEOPT,
2145 .features[FEAT_6_EAX] =
2146 CPUID_6_EAX_ARAT,
2147 .xlevel = 0x80000008,
2148 .model_id = "Intel Core Processor (Haswell, IBRS)",
2149 },
a356850b
EH		 2150 {
2151 .name = "Broadwell-noTSX",
2152 .level = 0xd,
2153 .vendor = CPUID_VENDOR_INTEL,
2154 .family = 6,
2155 .model = 61,
2156 .stepping = 2,
2157 .features[FEAT_1_EDX] =
2158 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2159 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2160 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2161 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2162 CPUID_DE | CPUID_FP87,
2163 .features[FEAT_1_ECX] =
2164 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2165 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2166 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2167 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2168 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2169 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2170 .features[FEAT_8000_0001_EDX] =
2171 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2172 CPUID_EXT2_SYSCALL,
2173 .features[FEAT_8000_0001_ECX] =
becb6667 2174 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 2175 .features[FEAT_7_0_EBX] =
2176 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2177 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2178 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2179 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2180 CPUID_7_0_EBX_SMAP,
2181 .features[FEAT_XSAVE] =
2182 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2183 .features[FEAT_6_EAX] =
2184 CPUID_6_EAX_ARAT,
3046bb5d 2185 .xlevel = 0x80000008,
a356850b
EH		 2186 .model_id = "Intel Core Processor (Broadwell, no TSX)",
2187 },
ac96c413
EH		 2188 {
2189 .name = "Broadwell-noTSX-IBRS",
2190 .level = 0xd,
2191 .vendor = CPUID_VENDOR_INTEL,
2192 .family = 6,
2193 .model = 61,
2194 .stepping = 2,
2195 .features[FEAT_1_EDX] =
2196 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2197 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2198 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2199 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2200 CPUID_DE | CPUID_FP87,
2201 .features[FEAT_1_ECX] =
2202 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2203 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2204 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2205 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2206 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2207 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2208 .features[FEAT_8000_0001_EDX] =
2209 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2210 CPUID_EXT2_SYSCALL,
2211 .features[FEAT_8000_0001_ECX] =
2212 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2213 .features[FEAT_7_0_EDX] =
2214 CPUID_7_0_EDX_SPEC_CTRL,
2215 .features[FEAT_7_0_EBX] =
2216 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2217 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2218 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2219 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2220 CPUID_7_0_EBX_SMAP,
2221 .features[FEAT_XSAVE] =
2222 CPUID_XSAVE_XSAVEOPT,
2223 .features[FEAT_6_EAX] =
2224 CPUID_6_EAX_ARAT,
2225 .xlevel = 0x80000008,
2226 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
2227 },
ece01354
EH		 2228 {
2229 .name = "Broadwell",
2230 .level = 0xd,
2231 .vendor = CPUID_VENDOR_INTEL,
2232 .family = 6,
2233 .model = 61,
2234 .stepping = 2,
2235 .features[FEAT_1_EDX] =
b3a4f0b1 2236 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2237 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2238 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2239 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2240 CPUID_DE | CPUID_FP87,
2241 .features[FEAT_1_ECX] =
2242 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2243 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2244 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2245 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2246 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2247 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2248 .features[FEAT_8000_0001_EDX] =
2249 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2250 CPUID_EXT2_SYSCALL,
2251 .features[FEAT_8000_0001_ECX] =
becb6667 2252 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2253 .features[FEAT_7_0_EBX] =
2254 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2255 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2256 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2257 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2258 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2259 .features[FEAT_XSAVE] =
2260 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2261 .features[FEAT_6_EAX] =
2262 CPUID_6_EAX_ARAT,
3046bb5d 2263 .xlevel = 0x80000008,
ece01354
EH		 2264 .model_id = "Intel Core Processor (Broadwell)",
2265 },
ac96c413
EH		 2266 {
2267 .name = "Broadwell-IBRS",
2268 .level = 0xd,
2269 .vendor = CPUID_VENDOR_INTEL,
2270 .family = 6,
2271 .model = 61,
2272 .stepping = 2,
2273 .features[FEAT_1_EDX] =
2274 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2275 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2276 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2277 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2278 CPUID_DE | CPUID_FP87,
2279 .features[FEAT_1_ECX] =
2280 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2281 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2282 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2283 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2284 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2285 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2286 .features[FEAT_8000_0001_EDX] =
2287 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2288 CPUID_EXT2_SYSCALL,
2289 .features[FEAT_8000_0001_ECX] =
2290 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2291 .features[FEAT_7_0_EDX] =
2292 CPUID_7_0_EDX_SPEC_CTRL,
2293 .features[FEAT_7_0_EBX] =
2294 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2295 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2296 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2297 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2298 CPUID_7_0_EBX_SMAP,
2299 .features[FEAT_XSAVE] =
2300 CPUID_XSAVE_XSAVEOPT,
2301 .features[FEAT_6_EAX] =
2302 CPUID_6_EAX_ARAT,
2303 .xlevel = 0x80000008,
2304 .model_id = "Intel Core Processor (Broadwell, IBRS)",
2305 },
f6f949e9
EH		 2306 {
2307 .name = "Skylake-Client",
2308 .level = 0xd,
2309 .vendor = CPUID_VENDOR_INTEL,
2310 .family = 6,
2311 .model = 94,
2312 .stepping = 3,
2313 .features[FEAT_1_EDX] =
2314 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2315 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2316 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2317 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2318 CPUID_DE | CPUID_FP87,
2319 .features[FEAT_1_ECX] =
2320 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2321 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2322 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2323 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2324 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2325 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2326 .features[FEAT_8000_0001_EDX] =
2327 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2328 CPUID_EXT2_SYSCALL,
2329 .features[FEAT_8000_0001_ECX] =
2330 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2331 .features[FEAT_7_0_EBX] =
2332 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2333 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2334 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2335 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2336 CPUID_7_0_EBX_SMAP,
f6f949e9 2337 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 2338 * including v4.1 to v4.12).
f6f949e9
EH		 2339 * KVM doesn't yet expose any XSAVES state save component,
2340 * and the only one defined in Skylake (processor tracing)
2341 * probably will block migration anyway.
2342 */
2343 .features[FEAT_XSAVE] =
2344 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2345 CPUID_XSAVE_XGETBV1,
2346 .features[FEAT_6_EAX] =
2347 CPUID_6_EAX_ARAT,
2348 .xlevel = 0x80000008,
2349 .model_id = "Intel Core Processor (Skylake)",
2350 },
ac96c413
EH		 2351 {
2352 .name = "Skylake-Client-IBRS",
2353 .level = 0xd,
2354 .vendor = CPUID_VENDOR_INTEL,
2355 .family = 6,
2356 .model = 94,
2357 .stepping = 3,
2358 .features[FEAT_1_EDX] =
2359 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2360 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2361 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2362 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2363 CPUID_DE | CPUID_FP87,
2364 .features[FEAT_1_ECX] =
2365 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2366 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2367 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2368 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2369 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2370 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2371 .features[FEAT_8000_0001_EDX] =
2372 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2373 CPUID_EXT2_SYSCALL,
2374 .features[FEAT_8000_0001_ECX] =
2375 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2376 .features[FEAT_7_0_EDX] =
2377 CPUID_7_0_EDX_SPEC_CTRL,
2378 .features[FEAT_7_0_EBX] =
2379 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2380 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2381 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2382 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2383 CPUID_7_0_EBX_SMAP,
ac96c413
EH		 2384 /* Missing: XSAVES (not supported by some Linux versions,
2385 * including v4.1 to v4.12).
2386 * KVM doesn't yet expose any XSAVES state save component,
2387 * and the only one defined in Skylake (processor tracing)
2388 * probably will block migration anyway.
2389 */
2390 .features[FEAT_XSAVE] =
2391 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2392 CPUID_XSAVE_XGETBV1,
2393 .features[FEAT_6_EAX] =
2394 CPUID_6_EAX_ARAT,
2395 .xlevel = 0x80000008,
2396 .model_id = "Intel Core Processor (Skylake, IBRS)",
2397 },
53f9a6f4
BF		 2398 {
2399 .name = "Skylake-Server",
2400 .level = 0xd,
2401 .vendor = CPUID_VENDOR_INTEL,
2402 .family = 6,
2403 .model = 85,
2404 .stepping = 4,
2405 .features[FEAT_1_EDX] =
2406 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2407 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2408 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2409 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2410 CPUID_DE | CPUID_FP87,
2411 .features[FEAT_1_ECX] =
2412 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2413 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2414 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2415 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2416 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2417 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2418 .features[FEAT_8000_0001_EDX] =
2419 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2420 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2421 .features[FEAT_8000_0001_ECX] =
2422 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2423 .features[FEAT_7_0_EBX] =
2424 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2425 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2426 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2427 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2428 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
53f9a6f4
BF		 2429 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2430 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2431 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 2432 .features[FEAT_7_0_ECX] =
2433 CPUID_7_0_ECX_PKU,
53f9a6f4
BF		 2434 /* Missing: XSAVES (not supported by some Linux versions,
2435 * including v4.1 to v4.12).
2436 * KVM doesn't yet expose any XSAVES state save component,
2437 * and the only one defined in Skylake (processor tracing)
2438 * probably will block migration anyway.
2439 */
2440 .features[FEAT_XSAVE] =
2441 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2442 CPUID_XSAVE_XGETBV1,
2443 .features[FEAT_6_EAX] =
2444 CPUID_6_EAX_ARAT,
2445 .xlevel = 0x80000008,
2446 .model_id = "Intel Xeon Processor (Skylake)",
2447 },
ac96c413
EH		 2448 {
2449 .name = "Skylake-Server-IBRS",
2450 .level = 0xd,
2451 .vendor = CPUID_VENDOR_INTEL,
2452 .family = 6,
2453 .model = 85,
2454 .stepping = 4,
2455 .features[FEAT_1_EDX] =
2456 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2457 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2458 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2459 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2460 CPUID_DE | CPUID_FP87,
2461 .features[FEAT_1_ECX] =
2462 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2463 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2464 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2465 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2466 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2467 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2468 .features[FEAT_8000_0001_EDX] =
2469 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2470 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2471 .features[FEAT_8000_0001_ECX] =
2472 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2473 .features[FEAT_7_0_EDX] =
2474 CPUID_7_0_EDX_SPEC_CTRL,
2475 .features[FEAT_7_0_EBX] =
2476 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2477 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2478 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2479 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2480 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
ac96c413
EH		 2481 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2482 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2483 CPUID_7_0_EBX_AVX512VL,
09b9ee64
TX		 2484 .features[FEAT_7_0_ECX] =
2485 CPUID_7_0_ECX_PKU,
ac96c413
EH		 2486 /* Missing: XSAVES (not supported by some Linux versions,
2487 * including v4.1 to v4.12).
2488 * KVM doesn't yet expose any XSAVES state save component,
2489 * and the only one defined in Skylake (processor tracing)
2490 * probably will block migration anyway.
2491 */
2492 .features[FEAT_XSAVE] =
2493 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2494 CPUID_XSAVE_XGETBV1,
2495 .features[FEAT_6_EAX] =
2496 CPUID_6_EAX_ARAT,
2497 .xlevel = 0x80000008,
2498 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2499 },
c7a88b52
TX		 2500 {
2501 .name = "Cascadelake-Server",
2502 .level = 0xd,
2503 .vendor = CPUID_VENDOR_INTEL,
2504 .family = 6,
2505 .model = 85,
b0a19803 2506 .stepping = 6,
c7a88b52
TX		 2507 .features[FEAT_1_EDX] =
2508 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2509 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2510 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2511 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2512 CPUID_DE | CPUID_FP87,
2513 .features[FEAT_1_ECX] =
2514 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2515 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2516 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2517 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2518 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2519 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2520 .features[FEAT_8000_0001_EDX] =
2521 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2522 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2523 .features[FEAT_8000_0001_ECX] =
2524 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2525 .features[FEAT_7_0_EBX] =
2526 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2527 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2528 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2529 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2530 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
c7a88b52
TX		 2531 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2532 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2533 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
2534 CPUID_7_0_EBX_INTEL_PT,
2535 .features[FEAT_7_0_ECX] =
2536 CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE |
2537 CPUID_7_0_ECX_AVX512VNNI,
2538 .features[FEAT_7_0_EDX] =
2539 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2540 /* Missing: XSAVES (not supported by some Linux versions,
2541 * including v4.1 to v4.12).
2542 * KVM doesn't yet expose any XSAVES state save component,
2543 * and the only one defined in Skylake (processor tracing)
2544 * probably will block migration anyway.
2545 */
2546 .features[FEAT_XSAVE] =
2547 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2548 CPUID_XSAVE_XGETBV1,
2549 .features[FEAT_6_EAX] =
2550 CPUID_6_EAX_ARAT,
2551 .xlevel = 0x80000008,
2552 .model_id = "Intel Xeon Processor (Cascadelake)",
2553 },
8a11c62d
RH		 2554 {
2555 .name = "Icelake-Client",
2556 .level = 0xd,
2557 .vendor = CPUID_VENDOR_INTEL,
2558 .family = 6,
2559 .model = 126,
2560 .stepping = 0,
2561 .features[FEAT_1_EDX] =
2562 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2563 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2564 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2565 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2566 CPUID_DE | CPUID_FP87,
2567 .features[FEAT_1_ECX] =
2568 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2569 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2570 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2571 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2572 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2573 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2574 .features[FEAT_8000_0001_EDX] =
2575 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2576 CPUID_EXT2_SYSCALL,
2577 .features[FEAT_8000_0001_ECX] =
2578 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2579 .features[FEAT_8000_0008_EBX] =
2580 CPUID_8000_0008_EBX_WBNOINVD,
2581 .features[FEAT_7_0_EBX] =
2582 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2583 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2584 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2585 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2586 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_INTEL_PT,
8a11c62d
RH		 2587 .features[FEAT_7_0_ECX] =
2588 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2589 CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2590 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2591 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2592 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2593 .features[FEAT_7_0_EDX] =
2594 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2595 /* Missing: XSAVES (not supported by some Linux versions,
2596 * including v4.1 to v4.12).
2597 * KVM doesn't yet expose any XSAVES state save component,
2598 * and the only one defined in Skylake (processor tracing)
2599 * probably will block migration anyway.
2600 */
2601 .features[FEAT_XSAVE] =
2602 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2603 CPUID_XSAVE_XGETBV1,
2604 .features[FEAT_6_EAX] =
2605 CPUID_6_EAX_ARAT,
2606 .xlevel = 0x80000008,
2607 .model_id = "Intel Core Processor (Icelake)",
2608 },
2609 {
2610 .name = "Icelake-Server",
2611 .level = 0xd,
2612 .vendor = CPUID_VENDOR_INTEL,
2613 .family = 6,
2614 .model = 134,
2615 .stepping = 0,
2616 .features[FEAT_1_EDX] =
2617 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2618 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2619 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2620 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2621 CPUID_DE | CPUID_FP87,
2622 .features[FEAT_1_ECX] =
2623 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2624 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2625 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2626 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2627 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2628 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2629 .features[FEAT_8000_0001_EDX] =
2630 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2631 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2632 .features[FEAT_8000_0001_ECX] =
2633 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2634 .features[FEAT_8000_0008_EBX] =
2635 CPUID_8000_0008_EBX_WBNOINVD,
2636 .features[FEAT_7_0_EBX] =
2637 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2638 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2639 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2640 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2641 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
8a11c62d
RH		 2642 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2643 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2644 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
2645 CPUID_7_0_EBX_INTEL_PT,
2646 .features[FEAT_7_0_ECX] =
2647 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2648 CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2649 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2650 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2651 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
2652 .features[FEAT_7_0_EDX] =
76e5a4d5 2653 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
8a11c62d
RH		 2654 /* Missing: XSAVES (not supported by some Linux versions,
2655 * including v4.1 to v4.12).
2656 * KVM doesn't yet expose any XSAVES state save component,
2657 * and the only one defined in Skylake (processor tracing)
2658 * probably will block migration anyway.
2659 */
2660 .features[FEAT_XSAVE] =
2661 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2662 CPUID_XSAVE_XGETBV1,
2663 .features[FEAT_6_EAX] =
2664 CPUID_6_EAX_ARAT,
2665 .xlevel = 0x80000008,
2666 .model_id = "Intel Xeon Processor (Icelake)",
2667 },
a1849515
BF		 2668 {
2669 .name = "KnightsMill",
2670 .level = 0xd,
2671 .vendor = CPUID_VENDOR_INTEL,
2672 .family = 6,
2673 .model = 133,
2674 .stepping = 0,
2675 .features[FEAT_1_EDX] =
2676 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2677 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2678 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2679 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2680 CPUID_PSE | CPUID_DE | CPUID_FP87,
2681 .features[FEAT_1_ECX] =
2682 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2683 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2684 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2685 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2686 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2687 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2688 .features[FEAT_8000_0001_EDX] =
2689 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2690 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2691 .features[FEAT_8000_0001_ECX] =
2692 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2693 .features[FEAT_7_0_EBX] =
2694 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2695 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2696 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2697 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2698 CPUID_7_0_EBX_AVX512ER,
2699 .features[FEAT_7_0_ECX] =
2700 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2701 .features[FEAT_7_0_EDX] =
2702 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2703 .features[FEAT_XSAVE] =
2704 CPUID_XSAVE_XSAVEOPT,
2705 .features[FEAT_6_EAX] =
2706 CPUID_6_EAX_ARAT,
2707 .xlevel = 0x80000008,
2708 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2709 },
3eca4642
EH		 2710 {
2711 .name = "Opteron_G1",
2712 .level = 5,
99b88a17 2713 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2714 .family = 15,
2715 .model = 6,
2716 .stepping = 1,
0514ef2f 2717 .features[FEAT_1_EDX] =
b3a4f0b1 2718 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2719 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2720 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2721 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2722 CPUID_DE | CPUID_FP87,
0514ef2f 2723 .features[FEAT_1_ECX] =
27861ecc 2724 CPUID_EXT_SSE3,
0514ef2f 2725 .features[FEAT_8000_0001_EDX] =
2a923a29 2726 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 2727 .xlevel = 0x80000008,
2728 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2729 },
2730 {
2731 .name = "Opteron_G2",
2732 .level = 5,
99b88a17 2733 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2734 .family = 15,
2735 .model = 6,
2736 .stepping = 1,
0514ef2f 2737 .features[FEAT_1_EDX] =
b3a4f0b1 2738 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2739 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2740 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2741 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2742 CPUID_DE | CPUID_FP87,
0514ef2f 2743 .features[FEAT_1_ECX] =
27861ecc 2744 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 2745 .features[FEAT_8000_0001_EDX] =
2a923a29 2746 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2747 .features[FEAT_8000_0001_ECX] =
27861ecc 2748 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2749 .xlevel = 0x80000008,
2750 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2751 },
2752 {
2753 .name = "Opteron_G3",
2754 .level = 5,
99b88a17 2755 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 2756 .family = 16,
2757 .model = 2,
2758 .stepping = 3,
0514ef2f 2759 .features[FEAT_1_EDX] =
b3a4f0b1 2760 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2761 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2762 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2763 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2764 CPUID_DE | CPUID_FP87,
0514ef2f 2765 .features[FEAT_1_ECX] =
27861ecc 2766 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 2767 CPUID_EXT_SSE3,
0514ef2f 2768 .features[FEAT_8000_0001_EDX] =
483c6ad4
BP		 2769 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
2770 CPUID_EXT2_RDTSCP,
0514ef2f 2771 .features[FEAT_8000_0001_ECX] =
27861ecc 2772 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 2773 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2774 .xlevel = 0x80000008,
2775 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2776 },
2777 {
2778 .name = "Opteron_G4",
2779 .level = 0xd,
99b88a17 2780 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2781 .family = 21,
2782 .model = 1,
2783 .stepping = 2,
0514ef2f 2784 .features[FEAT_1_EDX] =
b3a4f0b1 2785 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2786 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2787 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2788 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2789 CPUID_DE | CPUID_FP87,
0514ef2f 2790 .features[FEAT_1_ECX] =
27861ecc 2791 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2792 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2793 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2794 CPUID_EXT_SSE3,
0514ef2f 2795 .features[FEAT_8000_0001_EDX] =
2a923a29 2796 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 2797 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 2798 .features[FEAT_8000_0001_ECX] =
27861ecc 2799 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2800 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2801 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2802 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 2803 .features[FEAT_SVM] =
2804 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 2805 /* no xsaveopt! */
3eca4642
EH		 2806 .xlevel = 0x8000001A,
2807 .model_id = "AMD Opteron 62xx class CPU",
2808 },
021941b9
AP		 2809 {
2810 .name = "Opteron_G5",
2811 .level = 0xd,
99b88a17 2812 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 2813 .family = 21,
2814 .model = 2,
2815 .stepping = 0,
0514ef2f 2816 .features[FEAT_1_EDX] =
b3a4f0b1 2817 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2818 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2819 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2820 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2821 CPUID_DE | CPUID_FP87,
0514ef2f 2822 .features[FEAT_1_ECX] =
27861ecc 2823 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 2824 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2825 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2826 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 2827 .features[FEAT_8000_0001_EDX] =
2a923a29 2828 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 2829 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 2830 .features[FEAT_8000_0001_ECX] =
27861ecc 2831 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2832 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2833 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2834 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 2835 .features[FEAT_SVM] =
2836 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 2837 /* no xsaveopt! */
021941b9
AP		 2838 .xlevel = 0x8000001A,
2839 .model_id = "AMD Opteron 63xx class CPU",
2840 },
2e2efc7d
BS		 2841 {
2842 .name = "EPYC",
2843 .level = 0xd,
2844 .vendor = CPUID_VENDOR_AMD,
2845 .family = 23,
2846 .model = 1,
2847 .stepping = 2,
2848 .features[FEAT_1_EDX] =
2849 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2850 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2851 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2852 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2853 CPUID_VME | CPUID_FP87,
2854 .features[FEAT_1_ECX] =
2855 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2856 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2857 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2858 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2859 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2860 .features[FEAT_8000_0001_EDX] =
2861 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2862 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2863 CPUID_EXT2_SYSCALL,
2864 .features[FEAT_8000_0001_ECX] =
2865 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2866 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2867 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2868 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 2869 .features[FEAT_7_0_EBX] =
2870 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2871 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2872 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2873 CPUID_7_0_EBX_SHA_NI,
2874 /* Missing: XSAVES (not supported by some Linux versions,
2875 * including v4.1 to v4.12).
2876 * KVM doesn't yet expose any XSAVES state save component.
2877 */
2878 .features[FEAT_XSAVE] =
2879 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2880 CPUID_XSAVE_XGETBV1,
2881 .features[FEAT_6_EAX] =
2882 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 2883 .features[FEAT_SVM] =
2884 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 2885 .xlevel = 0x8000001E,
2e2efc7d 2886 .model_id = "AMD EPYC Processor",
fe52acd2 2887 .cache_info = &epyc_cache_info,
2e2efc7d 2888 },
6cfbc54e
EH		 2889 {
2890 .name = "EPYC-IBPB",
2891 .level = 0xd,
2892 .vendor = CPUID_VENDOR_AMD,
2893 .family = 23,
2894 .model = 1,
2895 .stepping = 2,
2896 .features[FEAT_1_EDX] =
2897 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2898 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2899 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2900 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2901 CPUID_VME | CPUID_FP87,
2902 .features[FEAT_1_ECX] =
2903 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2904 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2905 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2906 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2907 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2908 .features[FEAT_8000_0001_EDX] =
2909 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2910 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2911 CPUID_EXT2_SYSCALL,
2912 .features[FEAT_8000_0001_ECX] =
2913 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2914 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2915 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2916 CPUID_EXT3_TOPOEXT,
6cfbc54e
EH		 2917 .features[FEAT_8000_0008_EBX] =
2918 CPUID_8000_0008_EBX_IBPB,
2919 .features[FEAT_7_0_EBX] =
2920 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2921 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2922 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2923 CPUID_7_0_EBX_SHA_NI,
2924 /* Missing: XSAVES (not supported by some Linux versions,
2925 * including v4.1 to v4.12).
2926 * KVM doesn't yet expose any XSAVES state save component.
2927 */
2928 .features[FEAT_XSAVE] =
2929 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2930 CPUID_XSAVE_XGETBV1,
2931 .features[FEAT_6_EAX] =
2932 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 2933 .features[FEAT_SVM] =
2934 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 2935 .xlevel = 0x8000001E,
6cfbc54e 2936 .model_id = "AMD EPYC Processor (with IBPB)",
fe52acd2 2937 .cache_info = &epyc_cache_info,
6cfbc54e 2938 },
c6dc6f63
AP		 2939};
2940
5114e842
EH		 2941typedef struct PropValue {
2942 const char *prop, *value;
2943} PropValue;
2944
2945/* KVM-specific features that are automatically added/removed
2946 * from all CPU models when KVM is enabled.
2947 */
2948static PropValue kvm_default_props[] = {
2949 { "kvmclock", "on" },
2950 { "kvm-nopiodelay", "on" },
2951 { "kvm-asyncpf", "on" },
2952 { "kvm-steal-time", "on" },
2953 { "kvm-pv-eoi", "on" },
2954 { "kvmclock-stable-bit", "on" },
2955 { "x2apic", "on" },
2956 { "acpi", "off" },
2957 { "monitor", "off" },
2958 { "svm", "off" },
2959 { NULL, NULL },
2960};
2961
04d99c3c
EH		 2962/* TCG-specific defaults that override all CPU models when using TCG
2963 */
2964static PropValue tcg_default_props[] = {
2965 { "vme", "off" },
2966 { NULL, NULL },
2967};
2968
2969
5114e842
EH		 2970void x86_cpu_change_kvm_default(const char *prop, const char *value)
2971{
2972 PropValue *pv;
2973 for (pv = kvm_default_props; pv->prop; pv++) {
2974 if (!strcmp(pv->prop, prop)) {
2975 pv->value = value;
2976 break;
2977 }
2978 }
2979
2980 /* It is valid to call this function only for properties that
2981 * are already present in the kvm_default_props table.
2982 */
2983 assert(pv->prop);
2984}
2985
4d1b279b
EH		 2986static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2987 bool migratable_only);
2988
40bfe48f
HZ		 2989static bool lmce_supported(void)
2990{
c62f2630 2991 uint64_t mce_cap = 0;
40bfe48f 2992
c62f2630 2993#ifdef CONFIG_KVM
40bfe48f
HZ		 2994 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
2995 return false;
2996 }
c62f2630 2997#endif
40bfe48f
HZ		 2998
2999 return !!(mce_cap & MCG_LMCE_P);
3000}
3001
7d8050b5
EH		 3002#define CPUID_MODEL_ID_SZ 48
3003
3004/**
3005 * cpu_x86_fill_model_id:
3006 * Get CPUID model ID string from host CPU.
3007 *
3008 * @str should have at least CPUID_MODEL_ID_SZ bytes
3009 *
3010 * The function does NOT add a null terminator to the string
3011 * automatically.
3012 */
c6dc6f63
AP		 3013static int cpu_x86_fill_model_id(char *str)
3014{
3015 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3016 int i;
3017
3018 for (i = 0; i < 3; i++) {
3019 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
3020 memcpy(str + i * 16 + 0, &eax, 4);
3021 memcpy(str + i * 16 + 4, &ebx, 4);
3022 memcpy(str + i * 16 + 8, &ecx, 4);
3023 memcpy(str + i * 16 + 12, &edx, 4);
3024 }
3025 return 0;
3026}
3027
c62f2630 3028static Property max_x86_cpu_properties[] = {
120eee7d 3029 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 3030 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 3031 DEFINE_PROP_END_OF_LIST()
3032};
3033
c62f2630 3034static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 3035{
84f1b92f 3036 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 3037 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 3038
f48c8837 3039 xcc->ordering = 9;
6e746f30 3040
ee465a3e 3041 xcc->model_description =
c62f2630 3042 "Enables all features supported by the accelerator in the current host";
d940ee9b 3043
c62f2630 3044 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 3045}
3046
0bacd8b3
EH		 3047static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
3048
c62f2630 3049static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 3050{
3051 X86CPU *cpu = X86_CPU(obj);
3052 CPUX86State *env = &cpu->env;
3053 KVMState *s = kvm_state;
d940ee9b 3054
4d1b279b
EH		 3055 /* We can't fill the features array here because we don't know yet if
3056 * "migratable" is true or false.
3057 */
44bd8e53 3058 cpu->max_features = true;
4d1b279b 3059
d6dcc558 3060 if (accel_uses_host_cpuid()) {
bd182022
EH		 3061 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
3062 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
3063 int family, model, stepping;
d6dcc558
SAGDR		 3064 X86CPUDefinition host_cpudef = { };
3065 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3066
3067 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
3068 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
0bacd8b3 3069
bd182022 3070 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 3071
bd182022 3072 cpu_x86_fill_model_id(model_id);
0bacd8b3 3073
bd182022
EH		 3074 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
3075 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
3076 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
3077 object_property_set_int(OBJECT(cpu), stepping, "stepping",
3078 &error_abort);
3079 object_property_set_str(OBJECT(cpu), model_id, "model-id",
3080 &error_abort);
0bacd8b3 3081
d6dcc558
SAGDR		 3082 if (kvm_enabled()) {
3083 env->cpuid_min_level =
3084 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
3085 env->cpuid_min_xlevel =
3086 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
3087 env->cpuid_min_xlevel2 =
3088 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
3089 } else {
3090 env->cpuid_min_level =
3091 hvf_get_supported_cpuid(0x0, 0, R_EAX);
3092 env->cpuid_min_xlevel =
3093 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
3094 env->cpuid_min_xlevel2 =
3095 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
3096 }
40bfe48f
HZ		 3097
3098 if (lmce_supported()) {
3099 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
3100 }
6900d1cc
EH		 3101 } else {
3102 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
3103 "vendor", &error_abort);
3104 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
3105 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
3106 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
3107 object_property_set_str(OBJECT(cpu),
3108 "QEMU TCG CPU version " QEMU_HW_VERSION,
3109 "model-id", &error_abort);
e4356010 3110 }
2a573259 3111
d940ee9b 3112 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 3113}
3114
c62f2630
EH		 3115static const TypeInfo max_x86_cpu_type_info = {
3116 .name = X86_CPU_TYPE_NAME("max"),
3117 .parent = TYPE_X86_CPU,
3118 .instance_init = max_x86_cpu_initfn,
3119 .class_init = max_x86_cpu_class_init,
3120};
3121
d6dcc558 3122#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 3123static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
3124{
3125 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3126
d6dcc558 3127 xcc->host_cpuid_required = true;
c62f2630
EH		 3128 xcc->ordering = 8;
3129
02693cc4
GK		 3130#if defined(CONFIG_KVM)
3131 xcc->model_description =
3132 "KVM processor with all supported host features ";
3133#elif defined(CONFIG_HVF)
3134 xcc->model_description =
3135 "HVF processor with all supported host features ";
3136#endif
c62f2630
EH		 3137}
3138
d940ee9b
EH		 3139static const TypeInfo host_x86_cpu_type_info = {
3140 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 3141 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 3142 .class_init = host_x86_cpu_class_init,
3143};
3144
3145#endif
3146
07585923
RH		 3147static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
3148{
3149 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
3150
3151 switch (f->type) {
3152 case CPUID_FEATURE_WORD:
3153 {
3154 const char *reg = get_register_name_32(f->cpuid.reg);
3155 assert(reg);
3156 return g_strdup_printf("CPUID.%02XH:%s",
3157 f->cpuid.eax, reg);
3158 }
3159 case MSR_FEATURE_WORD:
3160 return g_strdup_printf("MSR(%02XH)",
3161 f->msr.index);
3162 }
3163
3164 return NULL;
3165}
3166
8459e396 3167static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 3168{
8459e396 3169 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63 3170 int i;
07585923 3171 char *feat_word_str;
c6dc6f63 3172
857aee33 3173 for (i = 0; i < 32; ++i) {
72370dc1 3174 if ((1UL << i) & mask) {
07585923
RH		 3175 feat_word_str = feature_word_description(f, i);
3176 warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
d6dcc558 3177 accel_uses_host_cpuid() ? "host" : "TCG",
07585923 3178 feat_word_str,
8297be80
AF		 3179 f->feat_names[i] ? "." : "",
3180 f->feat_names[i] ? f->feat_names[i] : "", i);
07585923 3181 g_free(feat_word_str);
c6dc6f63 3182 }
857aee33 3183 }
c6dc6f63
AP		 3184}
3185
d7bce999
EB		 3186static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
3187 const char *name, void *opaque,
3188 Error **errp)
95b8519d
AF		 3189{
3190 X86CPU *cpu = X86_CPU(obj);
3191 CPUX86State *env = &cpu->env;
3192 int64_t value;
3193
3194 value = (env->cpuid_version >> 8) & 0xf;
3195 if (value == 0xf) {
3196 value += (env->cpuid_version >> 20) & 0xff;
3197 }
51e72bc1 3198 visit_type_int(v, name, &value, errp);
95b8519d
AF		 3199}
3200
d7bce999
EB		 3201static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
3202 const char *name, void *opaque,
3203 Error **errp)
ed5e1ec3 3204{
71ad61d3
AF		 3205 X86CPU *cpu = X86_CPU(obj);
3206 CPUX86State *env = &cpu->env;
3207 const int64_t min = 0;
3208 const int64_t max = 0xff + 0xf;
65cd9064 3209 Error *local_err = NULL;
71ad61d3
AF		 3210 int64_t value;
3211
51e72bc1 3212 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3213 if (local_err) {
3214 error_propagate(errp, local_err);
71ad61d3
AF		 3215 return;
3216 }
3217 if (value < min || value > max) {
c6bd8c70
MA		 3218 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3219 name ? name : "null", value, min, max);
71ad61d3
AF		 3220 return;
3221 }
3222
ed5e1ec3 3223 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 3224 if (value > 0x0f) {
3225 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 3226 } else {
71ad61d3 3227 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 3228 }
3229}
3230
d7bce999
EB		 3231static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
3232 const char *name, void *opaque,
3233 Error **errp)
67e30c83
AF		 3234{
3235 X86CPU *cpu = X86_CPU(obj);
3236 CPUX86State *env = &cpu->env;
3237 int64_t value;
3238
3239 value = (env->cpuid_version >> 4) & 0xf;
3240 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 3241 visit_type_int(v, name, &value, errp);
67e30c83
AF		 3242}
3243
d7bce999
EB		 3244static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
3245 const char *name, void *opaque,
3246 Error **errp)
b0704cbd 3247{
c5291a4f
AF		 3248 X86CPU *cpu = X86_CPU(obj);
3249 CPUX86State *env = &cpu->env;
3250 const int64_t min = 0;
3251 const int64_t max = 0xff;
65cd9064 3252 Error *local_err = NULL;
c5291a4f
AF		 3253 int64_t value;
3254
51e72bc1 3255 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3256 if (local_err) {
3257 error_propagate(errp, local_err);
c5291a4f
AF		 3258 return;
3259 }
3260 if (value < min || value > max) {
c6bd8c70
MA		 3261 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3262 name ? name : "null", value, min, max);
c5291a4f
AF		 3263 return;
3264 }
3265
b0704cbd 3266 env->cpuid_version &= ~0xf00f0;
c5291a4f 3267 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 3268}
3269
35112e41 3270static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 3271 const char *name, void *opaque,
35112e41
AF		 3272 Error **errp)
3273{
3274 X86CPU *cpu = X86_CPU(obj);
3275 CPUX86State *env = &cpu->env;
3276 int64_t value;
3277
3278 value = env->cpuid_version & 0xf;
51e72bc1 3279 visit_type_int(v, name, &value, errp);
35112e41
AF		 3280}
3281
036e2222 3282static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 3283 const char *name, void *opaque,
036e2222 3284 Error **errp)
38c3dc46 3285{
036e2222
AF		 3286 X86CPU *cpu = X86_CPU(obj);
3287 CPUX86State *env = &cpu->env;
3288 const int64_t min = 0;
3289 const int64_t max = 0xf;
65cd9064 3290 Error *local_err = NULL;
036e2222
AF		 3291 int64_t value;
3292
51e72bc1 3293 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3294 if (local_err) {
3295 error_propagate(errp, local_err);
036e2222
AF		 3296 return;
3297 }
3298 if (value < min || value > max) {
c6bd8c70
MA		 3299 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3300 name ? name : "null", value, min, max);
036e2222
AF		 3301 return;
3302 }
3303
38c3dc46 3304 env->cpuid_version &= ~0xf;
036e2222 3305 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 3306}
3307
d480e1af
AF		 3308static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
3309{
3310 X86CPU *cpu = X86_CPU(obj);
3311 CPUX86State *env = &cpu->env;
3312 char *value;
d480e1af 3313
e42a92ae 3314 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 3315 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
3316 env->cpuid_vendor3);
d480e1af
AF		 3317 return value;
3318}
3319
3320static void x86_cpuid_set_vendor(Object *obj, const char *value,
3321 Error **errp)
3322{
3323 X86CPU *cpu = X86_CPU(obj);
3324 CPUX86State *env = &cpu->env;
3325 int i;
3326
9df694ee 3327 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 3328 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 3329 return;
3330 }
3331
3332 env->cpuid_vendor1 = 0;
3333 env->cpuid_vendor2 = 0;
3334 env->cpuid_vendor3 = 0;
3335 for (i = 0; i < 4; i++) {
3336 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
3337 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
3338 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
3339 }
d480e1af
AF		 3340}
3341
63e886eb
AF		 3342static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
3343{
3344 X86CPU *cpu = X86_CPU(obj);
3345 CPUX86State *env = &cpu->env;
3346 char *value;
3347 int i;
3348
3349 value = g_malloc(48 + 1);
3350 for (i = 0; i < 48; i++) {
3351 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
3352 }
3353 value[48] = '\0';
3354 return value;
3355}
3356
938d4c25
AF		 3357static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
3358 Error **errp)
dcce6675 3359{
938d4c25
AF		 3360 X86CPU *cpu = X86_CPU(obj);
3361 CPUX86State *env = &cpu->env;
dcce6675
AF		 3362 int c, len, i;
3363
3364 if (model_id == NULL) {
3365 model_id = "";
3366 }
3367 len = strlen(model_id);
d0a6acf4 3368 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 3369 for (i = 0; i < 48; i++) {
3370 if (i >= len) {
3371 c = '\0';
3372 } else {
3373 c = (uint8_t)model_id[i];
3374 }
3375 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
3376 }
3377}
3378
d7bce999
EB		 3379static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
3380 void *opaque, Error **errp)
89e48965
AF		 3381{
3382 X86CPU *cpu = X86_CPU(obj);
3383 int64_t value;
3384
3385 value = cpu->env.tsc_khz * 1000;
51e72bc1 3386 visit_type_int(v, name, &value, errp);
89e48965
AF		 3387}
3388
d7bce999
EB		 3389static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
3390 void *opaque, Error **errp)
89e48965
AF		 3391{
3392 X86CPU *cpu = X86_CPU(obj);
3393 const int64_t min = 0;
2e84849a 3394 const int64_t max = INT64_MAX;
65cd9064 3395 Error *local_err = NULL;
89e48965
AF		 3396 int64_t value;
3397
51e72bc1 3398 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3399 if (local_err) {
3400 error_propagate(errp, local_err);
89e48965
AF		 3401 return;
3402 }
3403 if (value < min || value > max) {
c6bd8c70
MA		 3404 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3405 name ? name : "null", value, min, max);
89e48965
AF		 3406 return;
3407 }
3408
36f96c4b 3409 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 3410}
3411
7e5292b5 3412/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 3413static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
3414 const char *name, void *opaque,
3415 Error **errp)
8e8aba50 3416{
7e5292b5 3417 uint32_t *array = (uint32_t *)opaque;
8e8aba50 3418 FeatureWord w;
8e8aba50
EH		 3419 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
3420 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
3421 X86CPUFeatureWordInfoList *list = NULL;
3422
3423 for (w = 0; w < FEATURE_WORDS; w++) {
3424 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 3425 /*
3426 * We didn't have MSR features when "feature-words" was
3427 * introduced. Therefore skipped other type entries.
3428 */
3429 if (wi->type != CPUID_FEATURE_WORD) {
3430 continue;
3431 }
8e8aba50 3432 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 3433 qwi->cpuid_input_eax = wi->cpuid.eax;
3434 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
3435 qwi->cpuid_input_ecx = wi->cpuid.ecx;
3436 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 3437 qwi->features = array[w];
8e8aba50
EH		 3438
3439 /* List will be in reverse order, but order shouldn't matter */
3440 list_entries[w].next = list;
3441 list_entries[w].value = &word_infos[w];
3442 list = &list_entries[w];
3443 }
3444
6b62d961 3445 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 3446}
3447
d7bce999
EB		 3448static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3449 void *opaque, Error **errp)
c8f0f88e
IM		 3450{
3451 X86CPU *cpu = X86_CPU(obj);
3452 int64_t value = cpu->hyperv_spinlock_attempts;
3453
51e72bc1 3454 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 3455}
3456
d7bce999
EB		 3457static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3458 void *opaque, Error **errp)
c8f0f88e
IM		 3459{
3460 const int64_t min = 0xFFF;
3461 const int64_t max = UINT_MAX;
3462 X86CPU *cpu = X86_CPU(obj);
3463 Error *err = NULL;
3464 int64_t value;
3465
51e72bc1 3466 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 3467 if (err) {
3468 error_propagate(errp, err);
3469 return;
3470 }
3471
3472 if (value < min || value > max) {
3473 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 3474 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
3475 object_get_typename(obj), name ? name : "null",
3476 value, min, max);
c8f0f88e
IM		 3477 return;
3478 }
3479 cpu->hyperv_spinlock_attempts = value;
3480}
3481
1b6b7d10 3482static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 3483 .name = "int",
3484 .get = x86_get_hv_spinlocks,
3485 .set = x86_set_hv_spinlocks,
3486};
3487
72ac2e87
IM		 3488/* Convert all '_' in a feature string option name to '-', to make feature
3489 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3490 */
3491static inline void feat2prop(char *s)
3492{
3493 while ((s = strchr(s, '_'))) {
3494 *s = '-';
3495 }
3496}
3497
b54c9377
EH		 3498/* Return the feature property name for a feature flag bit */
3499static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
3500{
3501 /* XSAVE components are automatically enabled by other features,
3502 * so return the original feature name instead
3503 */
3504 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
3505 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
3506
3507 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
3508 x86_ext_save_areas[comp].bits) {
3509 w = x86_ext_save_areas[comp].feature;
3510 bitnr = ctz32(x86_ext_save_areas[comp].bits);
3511 }
3512 }
3513
3514 assert(bitnr < 32);
3515 assert(w < FEATURE_WORDS);
3516 return feature_word_info[w].feat_names[bitnr];
3517}
3518
dc15c051
IM		 3519/* Compatibily hack to maintain legacy +-feat semantic,
3520 * where +-feat overwrites any feature set by
3521 * feat=on|feat even if the later is parsed after +-feat
3522 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3523 */
2fae0d96 3524static GList *plus_features, *minus_features;
dc15c051 3525
83a00f60
EH		 3526static gint compare_string(gconstpointer a, gconstpointer b)
3527{
3528 return g_strcmp0(a, b);
3529}
3530
8f961357
EH		 3531/* Parse "+feature,-feature,feature=foo" CPU feature string
3532 */
62a48a2a 3533static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 3534 Error **errp)
8f961357 3535{
8f961357 3536 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 3537 static bool cpu_globals_initialized;
83a00f60 3538 bool ambiguous = false;
62a48a2a
IM		 3539
3540 if (cpu_globals_initialized) {
3541 return;
3542 }
3543 cpu_globals_initialized = true;
8f961357 3544
f6750e95
EH		 3545 if (!features) {
3546 return;
3547 }
3548
3549 for (featurestr = strtok(features, ",");
685479bd 3550 featurestr;
f6750e95
EH		 3551 featurestr = strtok(NULL, ",")) {
3552 const char *name;
3553 const char *val = NULL;
3554 char *eq = NULL;
cf2887c9 3555 char num[32];
62a48a2a 3556 GlobalProperty *prop;
c6dc6f63 3557
f6750e95 3558 /* Compatibility syntax: */
c6dc6f63 3559 if (featurestr[0] == '+') {
2fae0d96
EH		 3560 plus_features = g_list_append(plus_features,
3561 g_strdup(featurestr + 1));
f6750e95 3562 continue;
c6dc6f63 3563 } else if (featurestr[0] == '-') {
2fae0d96
EH		 3564 minus_features = g_list_append(minus_features,
3565 g_strdup(featurestr + 1));
f6750e95
EH		 3566 continue;
3567 }
3568
3569 eq = strchr(featurestr, '=');
3570 if (eq) {
3571 *eq++ = 0;
3572 val = eq;
c6dc6f63 3573 } else {
f6750e95 3574 val = "on";
a91987c2 3575 }
f6750e95
EH		 3576
3577 feat2prop(featurestr);
3578 name = featurestr;
3579
83a00f60 3580 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 3581 warn_report("Ambiguous CPU model string. "
3582 "Don't mix both \"+%s\" and \"%s=%s\"",
3583 name, name, val);
83a00f60
EH		 3584 ambiguous = true;
3585 }
3586 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 3587 warn_report("Ambiguous CPU model string. "
3588 "Don't mix both \"-%s\" and \"%s=%s\"",
3589 name, name, val);
83a00f60
EH		 3590 ambiguous = true;
3591 }
3592
f6750e95
EH		 3593 /* Special case: */
3594 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 3595 int ret;
f46bfdbf 3596 uint64_t tsc_freq;
f6750e95 3597
f17fd4fd 3598 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 3599 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 3600 error_setg(errp, "bad numerical value %s", val);
3601 return;
3602 }
3603 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3604 val = num;
3605 name = "tsc-frequency";
c6dc6f63 3606 }
f6750e95 3607
62a48a2a
IM		 3608 prop = g_new0(typeof(*prop), 1);
3609 prop->driver = typename;
3610 prop->property = g_strdup(name);
3611 prop->value = g_strdup(val);
62a48a2a 3612 qdev_prop_register_global(prop);
f6750e95
EH		 3613 }
3614
83a00f60 3615 if (ambiguous) {
3dc6f869
AF		 3616 warn_report("Compatibility of ambiguous CPU model "
3617 "strings won't be kept on future QEMU versions");
83a00f60 3618 }
c6dc6f63
AP		 3619}
3620
b8d834a0 3621static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 3622static int x86_cpu_filter_features(X86CPU *cpu);
3623
3624/* Check for missing features that may prevent the CPU class from
3625 * running using the current machine and accelerator.
3626 */
3627static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3628 strList **missing_feats)
3629{
3630 X86CPU *xc;
3631 FeatureWord w;
3632 Error *err = NULL;
3633 strList **next = missing_feats;
3634
d6dcc558 3635 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 3636 strList *new = g_new0(strList, 1);
3c254ab8 3637 new->value = g_strdup("kvm");
b54c9377
EH		 3638 *missing_feats = new;
3639 return;
3640 }
3641
3642 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3643
b8d834a0 3644 x86_cpu_expand_features(xc, &err);
b54c9377 3645 if (err) {
b8d834a0 3646 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 3647 * but in case it does, just report the model as not
3648 * runnable at all using the "type" property.
3649 */
3650 strList *new = g_new0(strList, 1);
3651 new->value = g_strdup("type");
3652 *next = new;
3653 next = &new->next;
3654 }
3655
3656 x86_cpu_filter_features(xc);
3657
3658 for (w = 0; w < FEATURE_WORDS; w++) {
3659 uint32_t filtered = xc->filtered_features[w];
3660 int i;
3661 for (i = 0; i < 32; i++) {
3662 if (filtered & (1UL << i)) {
3663 strList *new = g_new0(strList, 1);
3664 new->value = g_strdup(x86_cpu_feature_name(w, i));
3665 *next = new;
3666 next = &new->next;
3667 }
3668 }
3669 }
3670
3671 object_unref(OBJECT(xc));
3672}
3673
8c3329e5 3674/* Print all cpuid feature names in featureset
c6dc6f63 3675 */
cc643b1e 3676static void listflags(FILE *f, fprintf_function print, GList *features)
0856579c 3677{
cc643b1e
DB		 3678 size_t len = 0;
3679 GList *tmp;
3680
3681 for (tmp = features; tmp; tmp = tmp->next) {
3682 const char *name = tmp->data;
3683 if ((len + strlen(name) + 1) >= 75) {
3684 print(f, "\n");
3685 len = 0;
c6dc6f63 3686 }
cc643b1e
DB		 3687 print(f, "%s%s", len == 0 ? " " : " ", name);
3688 len += strlen(name) + 1;
8c3329e5 3689 }
cc643b1e 3690 print(f, "\n");
c6dc6f63
AP		 3691}
3692
f48c8837 3693/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 3694static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3695{
3696 ObjectClass *class_a = (ObjectClass *)a;
3697 ObjectClass *class_b = (ObjectClass *)b;
3698 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3699 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b
DB		 3700 char *name_a, *name_b;
3701 int ret;
ee465a3e 3702
f48c8837 3703 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 3704 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 3705 } else {
c7dbff4b
DB		 3706 name_a = x86_cpu_class_get_model_name(cc_a);
3707 name_b = x86_cpu_class_get_model_name(cc_b);
3708 ret = strcmp(name_a, name_b);
3709 g_free(name_a);
3710 g_free(name_b);
ee465a3e 3711 }
c7dbff4b 3712 return ret;
ee465a3e
EH		 3713}
3714
3715static GSList *get_sorted_cpu_model_list(void)
3716{
3717 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3718 list = g_slist_sort(list, x86_cpu_list_compare);
3719 return list;
3720}
3721
3722static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3723{
3724 ObjectClass *oc = data;
3725 X86CPUClass *cc = X86_CPU_CLASS(oc);
3726 CPUListState *s = user_data;
3727 char *name = x86_cpu_class_get_model_name(cc);
3728 const char *desc = cc->model_description;
0bacd8b3 3729 if (!desc && cc->cpu_def) {
ee465a3e
EH		 3730 desc = cc->cpu_def->model_id;
3731 }
3732
081492ca 3733 (*s->cpu_fprintf)(s->file, "x86 %-20s %-48s\n",
ee465a3e
EH		 3734 name, desc);
3735 g_free(name);
3736}
3737
3738/* list available CPU models and flags */
e916cbf8 3739void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 3740{
cc643b1e 3741 int i, j;
ee465a3e
EH		 3742 CPUListState s = {
3743 .file = f,
3744 .cpu_fprintf = cpu_fprintf,
3745 };
3746 GSList *list;
cc643b1e 3747 GList *names = NULL;
c6dc6f63 3748
ee465a3e
EH		 3749 (*cpu_fprintf)(f, "Available CPUs:\n");
3750 list = get_sorted_cpu_model_list();
3751 g_slist_foreach(list, x86_cpu_list_entry, &s);
3752 g_slist_free(list);
21ad7789 3753
cc643b1e 3754 names = NULL;
3af60be2
JK		 3755 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3756 FeatureWordInfo *fw = &feature_word_info[i];
cc643b1e
DB		 3757 for (j = 0; j < 32; j++) {
3758 if (fw->feat_names[j]) {
3759 names = g_list_append(names, (gpointer)fw->feat_names[j]);
3760 }
3761 }
3af60be2 3762 }
cc643b1e
DB		 3763
3764 names = g_list_sort(names, (GCompareFunc)strcmp);
3765
3766 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3767 listflags(f, cpu_fprintf, names);
3768 (*cpu_fprintf)(f, "\n");
3769 g_list_free(names);
c6dc6f63
AP		 3770}
3771
ee465a3e
EH		 3772static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3773{
3774 ObjectClass *oc = data;
3775 X86CPUClass *cc = X86_CPU_CLASS(oc);
3776 CpuDefinitionInfoList **cpu_list = user_data;
3777 CpuDefinitionInfoList *entry;
3778 CpuDefinitionInfo *info;
3779
3780 info = g_malloc0(sizeof(*info));
3781 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 3782 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3783 info->has_unavailable_features = true;
8ed877b7 3784 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 3785 info->migration_safe = cc->migration_safe;
3786 info->has_migration_safe = true;
5adbed30 3787 info->q_static = cc->static_model;
ee465a3e
EH		 3788
3789 entry = g_malloc0(sizeof(*entry));
3790 entry->value = info;
3791 entry->next = *cpu_list;
3792 *cpu_list = entry;
3793}
3794
76b64a7a 3795CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 3796{
3797 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 3798 GSList *list = get_sorted_cpu_model_list();
3799 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3800 g_slist_free(list);
e3966126
AL		 3801 return cpu_list;
3802}
3803
84f1b92f
EH		 3804static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3805 bool migratable_only)
27418adf
EH		 3806{
3807 FeatureWordInfo *wi = &feature_word_info[w];
07585923 3808 uint32_t r = 0;
27418adf 3809
fefb41bf 3810 if (kvm_enabled()) {
07585923
RH		 3811 switch (wi->type) {
3812 case CPUID_FEATURE_WORD:
3813 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
3814 wi->cpuid.ecx,
3815 wi->cpuid.reg);
3816 break;
3817 case MSR_FEATURE_WORD:
d86f9636
RH		 3818 r = kvm_arch_get_supported_msr_feature(kvm_state,
3819 wi->msr.index);
07585923
RH		 3820 break;
3821 }
d6dcc558 3822 } else if (hvf_enabled()) {
07585923
RH		 3823 if (wi->type != CPUID_FEATURE_WORD) {
3824 return 0;
3825 }
3826 r = hvf_get_supported_cpuid(wi->cpuid.eax,
3827 wi->cpuid.ecx,
3828 wi->cpuid.reg);
fefb41bf 3829 } else if (tcg_enabled()) {
84f1b92f 3830 r = wi->tcg_features;
fefb41bf
EH		 3831 } else {
3832 return ~0;
3833 }
84f1b92f
EH		 3834 if (migratable_only) {
3835 r &= x86_cpu_get_migratable_flags(w);
3836 }
3837 return r;
27418adf
EH		 3838}
3839
8ca30e86
EH		 3840static void x86_cpu_report_filtered_features(X86CPU *cpu)
3841{
3842 FeatureWord w;
3843
3844 for (w = 0; w < FEATURE_WORDS; w++) {
3845 report_unavailable_features(w, cpu->filtered_features[w]);
3846 }
3847}
3848
5114e842
EH		 3849static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3850{
3851 PropValue *pv;
3852 for (pv = props; pv->prop; pv++) {
3853 if (!pv->value) {
3854 continue;
3855 }
3856 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3857 &error_abort);
3858 }
3859}
3860
f99fd7ca 3861/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 3862 */
d940ee9b 3863static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 3864{
61dcd775 3865 CPUX86State *env = &cpu->env;
74f54bc4
EH		 3866 const char *vendor;
3867 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 3868 FeatureWord w;
c6dc6f63 3869
f99fd7ca
EH		 3870 /*NOTE: any property set by this function should be returned by
3871 * x86_cpu_static_props(), so static expansion of
3872 * query-cpu-model-expansion is always complete.
3873 */
3874
c39c0edf 3875 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 3876 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3877 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 3878
2d64255b
AF		 3879 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3880 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3881 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 3882 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 3883 for (w = 0; w < FEATURE_WORDS; w++) {
3884 env->features[w] = def->features[w];
3885 }
82beb536 3886
a9f27ea9
EH		 3887 /* legacy-cache defaults to 'off' if CPU model provides cache info */
3888 cpu->legacy_cache = !def->cache_info;
ab8f992e 3889
9576de75 3890 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 3891 /* TODO: in-kernel irqchip for hvf */
82beb536 3892 if (kvm_enabled()) {
492a4c94
LT		 3893 if (!kvm_irqchip_in_kernel()) {
3894 x86_cpu_change_kvm_default("x2apic", "off");
3895 }
3896
5114e842 3897 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 3898 } else if (tcg_enabled()) {
3899 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 3900 }
5fcca9ff 3901
82beb536 3902 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 3903
3904 /* sysenter isn't supported in compatibility mode on AMD,
3905 * syscall isn't supported in compatibility mode on Intel.
3906 * Normally we advertise the actual CPU vendor, but you can
3907 * override this using the 'vendor' property if you want to use
3908 * KVM's sysenter/syscall emulation in compatibility mode and
3909 * when doing cross vendor migration
3910 */
74f54bc4 3911 vendor = def->vendor;
d6dcc558 3912 if (accel_uses_host_cpuid()) {
7c08db30
EH		 3913 uint32_t ebx = 0, ecx = 0, edx = 0;
3914 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3915 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3916 vendor = host_vendor;
3917 }
3918
3919 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3920
c6dc6f63
AP		 3921}
3922
f99fd7ca
EH		 3923/* Return a QDict containing keys for all properties that can be included
3924 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3925 * must be included in the dictionary.
3926 */
3927static QDict *x86_cpu_static_props(void)
3928{
3929 FeatureWord w;
3930 int i;
3931 static const char *props[] = {
3932 "min-level",
3933 "min-xlevel",
3934 "family",
3935 "model",
3936 "stepping",
3937 "model-id",
3938 "vendor",
3939 "lmce",
3940 NULL,
3941 };
3942 static QDict *d;
3943
3944 if (d) {
3945 return d;
3946 }
3947
3948 d = qdict_new();
3949 for (i = 0; props[i]; i++) {
0f9afc2a 3950 qdict_put_null(d, props[i]);
f99fd7ca
EH		 3951 }
3952
3953 for (w = 0; w < FEATURE_WORDS; w++) {
3954 FeatureWordInfo *fi = &feature_word_info[w];
3955 int bit;
3956 for (bit = 0; bit < 32; bit++) {
3957 if (!fi->feat_names[bit]) {
3958 continue;
3959 }
0f9afc2a 3960 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 3961 }
3962 }
3963
3964 return d;
3965}
3966
3967/* Add an entry to @props dict, with the value for property. */
3968static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
3969{
3970 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
3971 &error_abort);
3972
3973 qdict_put_obj(props, prop, value);
3974}
3975
3976/* Convert CPU model data from X86CPU object to a property dictionary
3977 * that can recreate exactly the same CPU model.
3978 */
3979static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
3980{
3981 QDict *sprops = x86_cpu_static_props();
3982 const QDictEntry *e;
3983
3984 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
3985 const char *prop = qdict_entry_key(e);
3986 x86_cpu_expand_prop(cpu, props, prop);
3987 }
3988}
3989
b8097deb
EH		 3990/* Convert CPU model data from X86CPU object to a property dictionary
3991 * that can recreate exactly the same CPU model, including every
3992 * writeable QOM property.
3993 */
3994static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
3995{
3996 ObjectPropertyIterator iter;
3997 ObjectProperty *prop;
3998
3999 object_property_iter_init(&iter, OBJECT(cpu));
4000 while ((prop = object_property_iter_next(&iter))) {
4001 /* skip read-only or write-only properties */
4002 if (!prop->get || !prop->set) {
4003 continue;
4004 }
4005
4006 /* "hotplugged" is the only property that is configurable
4007 * on the command-line but will be set differently on CPUs
4008 * created using "-cpu ... -smp ..." and by CPUs created
4009 * on the fly by x86_cpu_from_model() for querying. Skip it.
4010 */
4011 if (!strcmp(prop->name, "hotplugged")) {
4012 continue;
4013 }
4014 x86_cpu_expand_prop(cpu, props, prop->name);
4015 }
4016}
4017
f99fd7ca
EH		 4018static void object_apply_props(Object *obj, QDict *props, Error **errp)
4019{
4020 const QDictEntry *prop;
4021 Error *err = NULL;
4022
4023 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
4024 object_property_set_qobject(obj, qdict_entry_value(prop),
4025 qdict_entry_key(prop), &err);
4026 if (err) {
4027 break;
4028 }
4029 }
4030
4031 error_propagate(errp, err);
4032}
4033
4034/* Create X86CPU object according to model+props specification */
4035static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
4036{
4037 X86CPU *xc = NULL;
4038 X86CPUClass *xcc;
4039 Error *err = NULL;
4040
4041 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
4042 if (xcc == NULL) {
4043 error_setg(&err, "CPU model '%s' not found", model);
4044 goto out;
4045 }
4046
4047 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
4048 if (props) {
4049 object_apply_props(OBJECT(xc), props, &err);
4050 if (err) {
4051 goto out;
4052 }
4053 }
4054
4055 x86_cpu_expand_features(xc, &err);
4056 if (err) {
4057 goto out;
4058 }
4059
4060out:
4061 if (err) {
4062 error_propagate(errp, err);
4063 object_unref(OBJECT(xc));
4064 xc = NULL;
4065 }
4066 return xc;
4067}
4068
4069CpuModelExpansionInfo *
4070arch_query_cpu_model_expansion(CpuModelExpansionType type,
4071 CpuModelInfo *model,
4072 Error **errp)
4073{
4074 X86CPU *xc = NULL;
4075 Error *err = NULL;
4076 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
4077 QDict *props = NULL;
4078 const char *base_name;
4079
4080 xc = x86_cpu_from_model(model->name,
4081 model->has_props ?
7dc847eb 4082 qobject_to(QDict, model->props) :
f99fd7ca
EH		 4083 NULL, &err);
4084 if (err) {
4085 goto out;
4086 }
4087
b8097deb 4088 props = qdict_new();
e38bf612
EH		 4089 ret->model = g_new0(CpuModelInfo, 1);
4090 ret->model->props = QOBJECT(props);
4091 ret->model->has_props = true;
f99fd7ca
EH		 4092
4093 switch (type) {
4094 case CPU_MODEL_EXPANSION_TYPE_STATIC:
4095 /* Static expansion will be based on "base" only */
4096 base_name = "base";
b8097deb 4097 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 4098 break;
4099 case CPU_MODEL_EXPANSION_TYPE_FULL:
4100 /* As we don't return every single property, full expansion needs
4101 * to keep the original model name+props, and add extra
4102 * properties on top of that.
4103 */
4104 base_name = model->name;
b8097deb 4105 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 4106 break;
4107 default:
df68a7f3 4108 error_setg(&err, "Unsupported expansion type");
f99fd7ca
EH		 4109 goto out;
4110 }
4111
f99fd7ca
EH		 4112 x86_cpu_to_dict(xc, props);
4113
f99fd7ca 4114 ret->model->name = g_strdup(base_name);
f99fd7ca
EH		 4115
4116out:
4117 object_unref(OBJECT(xc));
4118 if (err) {
4119 error_propagate(errp, err);
4120 qapi_free_CpuModelExpansionInfo(ret);
4121 ret = NULL;
4122 }
4123 return ret;
4124}
4125
00fcd100
AB		 4126static gchar *x86_gdb_arch_name(CPUState *cs)
4127{
4128#ifdef TARGET_X86_64
4129 return g_strdup("i386:x86-64");
4130#else
4131 return g_strdup("i386");
4132#endif
4133}
4134
d940ee9b
EH		 4135static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
4136{
4137 X86CPUDefinition *cpudef = data;
4138 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4139
4140 xcc->cpu_def = cpudef;
bd72159d 4141 xcc->migration_safe = true;
d940ee9b
EH		 4142}
4143
4144static void x86_register_cpudef_type(X86CPUDefinition *def)
4145{
4146 char *typename = x86_cpu_type_name(def->name);
4147 TypeInfo ti = {
4148 .name = typename,
4149 .parent = TYPE_X86_CPU,
4150 .class_init = x86_cpu_cpudef_class_init,
4151 .class_data = def,
4152 };
4153
2a923a29
EH		 4154 /* AMD aliases are handled at runtime based on CPUID vendor, so
4155 * they shouldn't be set on the CPU model table.
4156 */
4157 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 4158 /* catch mistakes instead of silently truncating model_id when too long */
4159 assert(def->model_id && strlen(def->model_id) <= 48);
4160
2a923a29 4161
d940ee9b
EH		 4162 type_register(&ti);
4163 g_free(typename);
4164}
4165
c6dc6f63 4166#if !defined(CONFIG_USER_ONLY)
c6dc6f63 4167
0e26b7b8
BS		 4168void cpu_clear_apic_feature(CPUX86State *env)
4169{
0514ef2f 4170 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 4171}
4172
c6dc6f63
AP		 4173#endif /* !CONFIG_USER_ONLY */
4174
c6dc6f63
AP		 4175void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
4176 uint32_t *eax, uint32_t *ebx,
4177 uint32_t *ecx, uint32_t *edx)
4178{
a60f24b5
AF		 4179 X86CPU *cpu = x86_env_get_cpu(env);
4180 CPUState *cs = CPU(cpu);
14c985cf 4181 uint32_t pkg_offset;
4ed3d478 4182 uint32_t limit;
1ce36bfe 4183 uint32_t signature[3];
a60f24b5 4184
4ed3d478
DB		 4185 /* Calculate & apply limits for different index ranges */
4186 if (index >= 0xC0000000) {
4187 limit = env->cpuid_xlevel2;
4188 } else if (index >= 0x80000000) {
4189 limit = env->cpuid_xlevel;
1ce36bfe
DB		 4190 } else if (index >= 0x40000000) {
4191 limit = 0x40000001;
c6dc6f63 4192 } else {
4ed3d478
DB		 4193 limit = env->cpuid_level;
4194 }
4195
4196 if (index > limit) {
4197 /* Intel documentation states that invalid EAX input will
4198 * return the same information as EAX=cpuid_level
4199 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
4200 */
4201 index = env->cpuid_level;
c6dc6f63
AP		 4202 }
4203
4204 switch(index) {
4205 case 0:
4206 *eax = env->cpuid_level;
5eb2f7a4
EH		 4207 *ebx = env->cpuid_vendor1;
4208 *edx = env->cpuid_vendor2;
4209 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 4210 break;
4211 case 1:
4212 *eax = env->cpuid_version;
7e72a45c
EH		 4213 *ebx = (cpu->apic_id << 24) |
4214 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 4215 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 4216 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
4217 *ecx |= CPUID_EXT_OSXSAVE;
4218 }
0514ef2f 4219 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 4220 if (cs->nr_cores * cs->nr_threads > 1) {
4221 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 4222 *edx |= CPUID_HT;
c6dc6f63
AP		 4223 }
4224 break;
4225 case 2:
4226 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 4227 if (cpu->cache_info_passthrough) {
4228 host_cpuid(index, 0, eax, ebx, ecx, edx);
4229 break;
4230 }
5e891bf8 4231 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 4232 *ebx = 0;
14c985cf
LM		 4233 if (!cpu->enable_l3_cache) {
4234 *ecx = 0;
4235 } else {
a9f27ea9 4236 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 4237 }
a9f27ea9
EH		 4238 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
4239 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
4240 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 4241 break;
4242 case 4:
4243 /* cache info: needed for Core compatibility */
787aaf57
BC		 4244 if (cpu->cache_info_passthrough) {
4245 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 4246 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 4247 *eax &= ~0xFC000000;
7e3482f8
EH		 4248 if ((*eax & 31) && cs->nr_cores > 1) {
4249 *eax |= (cs->nr_cores - 1) << 26;
4250 }
c6dc6f63 4251 } else {
2f7a21c4 4252 *eax = 0;
76c2975a 4253 switch (count) {
c6dc6f63 4254 case 0: /* L1 dcache info */
a9f27ea9
EH		 4255 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
4256 1, cs->nr_cores,
7e3482f8 4257 eax, ebx, ecx, edx);
c6dc6f63
AP		 4258 break;
4259 case 1: /* L1 icache info */
a9f27ea9
EH		 4260 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
4261 1, cs->nr_cores,
7e3482f8 4262 eax, ebx, ecx, edx);
c6dc6f63
AP		 4263 break;
4264 case 2: /* L2 cache info */
a9f27ea9
EH		 4265 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
4266 cs->nr_threads, cs->nr_cores,
7e3482f8 4267 eax, ebx, ecx, edx);
c6dc6f63 4268 break;
14c985cf 4269 case 3: /* L3 cache info */
7e3482f8
EH		 4270 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4271 if (cpu->enable_l3_cache) {
a9f27ea9
EH		 4272 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
4273 (1 << pkg_offset), cs->nr_cores,
7e3482f8 4274 eax, ebx, ecx, edx);
14c985cf
LM		 4275 break;
4276 }
7e3482f8 4277 /* fall through */
c6dc6f63 4278 default: /* end of info */
7e3482f8 4279 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 4280 break;
76c2975a
PB		 4281 }
4282 }
c6dc6f63
AP		 4283 break;
4284 case 5:
2266d443
MT		 4285 /* MONITOR/MWAIT Leaf */
4286 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
4287 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
4288 *ecx = cpu->mwait.ecx; /* flags */
4289 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 4290 break;
4291 case 6:
4292 /* Thermal and Power Leaf */
28b8e4d0 4293 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 4294 *ebx = 0;
4295 *ecx = 0;
4296 *edx = 0;
4297 break;
f7911686 4298 case 7:
13526728
EH		 4299 /* Structured Extended Feature Flags Enumeration Leaf */
4300 if (count == 0) {
4301 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 4302 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 4303 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 4304 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
4305 *ecx |= CPUID_7_0_ECX_OSPKE;
4306 }
95ea69fb 4307 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 4308 } else {
4309 *eax = 0;
4310 *ebx = 0;
4311 *ecx = 0;
4312 *edx = 0;
4313 }
4314 break;
c6dc6f63
AP		 4315 case 9:
4316 /* Direct Cache Access Information Leaf */
4317 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
4318 *ebx = 0;
4319 *ecx = 0;
4320 *edx = 0;
4321 break;
4322 case 0xA:
4323 /* Architectural Performance Monitoring Leaf */
9337e3b6 4324 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 4325 KVMState *s = cs->kvm_state;
a0fa8208
GN		 4326
4327 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
4328 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
4329 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
4330 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 4331 } else if (hvf_enabled() && cpu->enable_pmu) {
4332 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
4333 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
4334 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
4335 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 4336 } else {
4337 *eax = 0;
4338 *ebx = 0;
4339 *ecx = 0;
4340 *edx = 0;
4341 }
c6dc6f63 4342 break;
5232d00a
RK		 4343 case 0xB:
4344 /* Extended Topology Enumeration Leaf */
4345 if (!cpu->enable_cpuid_0xb) {
4346 *eax = *ebx = *ecx = *edx = 0;
4347 break;
4348 }
4349
4350 *ecx = count & 0xff;
4351 *edx = cpu->apic_id;
4352
4353 switch (count) {
4354 case 0:
eab60fb9
MAL		 4355 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
4356 *ebx = cs->nr_threads;
5232d00a
RK		 4357 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
4358 break;
4359 case 1:
eab60fb9
MAL		 4360 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4361 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 4362 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
4363 break;
4364 default:
4365 *eax = 0;
4366 *ebx = 0;
4367 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
4368 }
4369
4370 assert(!(*eax & ~0x1f));
4371 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
4372 break;
2560f19f 4373 case 0xD: {
51e49430 4374 /* Processor Extended State */
2560f19f
PB		 4375 *eax = 0;
4376 *ebx = 0;
4377 *ecx = 0;
4378 *edx = 0;
19dc85db 4379 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 4380 break;
4381 }
4928cd6d 4382
2560f19f 4383 if (count == 0) {
96193c22
EH		 4384 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
4385 *eax = env->features[FEAT_XSAVE_COMP_LO];
4386 *edx = env->features[FEAT_XSAVE_COMP_HI];
de2e68c9 4387 *ebx = xsave_area_size(env->xcr0);
2560f19f 4388 } else if (count == 1) {
0bb0b2d2 4389 *eax = env->features[FEAT_XSAVE];
f4f1110e 4390 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 4391 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
4392 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 4393 *eax = esa->size;
4394 *ebx = esa->offset;
2560f19f 4395 }
51e49430
SY		 4396 }
4397 break;
2560f19f 4398 }
e37a5c7f
CP		 4399 case 0x14: {
4400 /* Intel Processor Trace Enumeration */
4401 *eax = 0;
4402 *ebx = 0;
4403 *ecx = 0;
4404 *edx = 0;
4405 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
4406 !kvm_enabled()) {
4407 break;
4408 }
4409
4410 if (count == 0) {
4411 *eax = INTEL_PT_MAX_SUBLEAF;
4412 *ebx = INTEL_PT_MINIMAL_EBX;
4413 *ecx = INTEL_PT_MINIMAL_ECX;
4414 } else if (count == 1) {
4415 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
4416 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
4417 }
4418 break;
4419 }
1ce36bfe
DB		 4420 case 0x40000000:
4421 /*
4422 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4423 * set here, but we restrict to TCG none the less.
4424 */
4425 if (tcg_enabled() && cpu->expose_tcg) {
4426 memcpy(signature, "TCGTCGTCGTCG", 12);
4427 *eax = 0x40000001;
4428 *ebx = signature[0];
4429 *ecx = signature[1];
4430 *edx = signature[2];
4431 } else {
4432 *eax = 0;
4433 *ebx = 0;
4434 *ecx = 0;
4435 *edx = 0;
4436 }
4437 break;
4438 case 0x40000001:
4439 *eax = 0;
4440 *ebx = 0;
4441 *ecx = 0;
4442 *edx = 0;
4443 break;
c6dc6f63
AP		 4444 case 0x80000000:
4445 *eax = env->cpuid_xlevel;
4446 *ebx = env->cpuid_vendor1;
4447 *edx = env->cpuid_vendor2;
4448 *ecx = env->cpuid_vendor3;
4449 break;
4450 case 0x80000001:
4451 *eax = env->cpuid_version;
4452 *ebx = 0;
0514ef2f
EH		 4453 *ecx = env->features[FEAT_8000_0001_ECX];
4454 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 4455
4456 /* The Linux kernel checks for the CMPLegacy bit and
4457 * discards multiple thread information if it is set.
cb8d4c8f 4458 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 4459 */
ce3960eb 4460 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 4461 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
4462 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
4463 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 4464 *ecx |= 1 << 1; /* CmpLegacy bit */
4465 }
4466 }
c6dc6f63
AP		 4467 break;
4468 case 0x80000002:
4469 case 0x80000003:
4470 case 0x80000004:
4471 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
4472 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
4473 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
4474 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
4475 break;
4476 case 0x80000005:
4477 /* cache info (L1 cache) */
787aaf57
BC		 4478 if (cpu->cache_info_passthrough) {
4479 host_cpuid(index, 0, eax, ebx, ecx, edx);
4480 break;
4481 }
5e891bf8
EH		 4482 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
4483 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
4484 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
4485 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4486 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
4487 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 4488 break;
4489 case 0x80000006:
4490 /* cache info (L2 cache) */
787aaf57
BC		 4491 if (cpu->cache_info_passthrough) {
4492 host_cpuid(index, 0, eax, ebx, ecx, edx);
4493 break;
4494 }
5e891bf8
EH		 4495 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
4496 (L2_DTLB_2M_ENTRIES << 16) | \
4497 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
4498 (L2_ITLB_2M_ENTRIES);
4499 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
4500 (L2_DTLB_4K_ENTRIES << 16) | \
4501 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
4502 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4503 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
4504 cpu->enable_l3_cache ?
4505 env->cache_info_amd.l3_cache : NULL,
4506 ecx, edx);
c6dc6f63 4507 break;
303752a9
MT		 4508 case 0x80000007:
4509 *eax = 0;
4510 *ebx = 0;
4511 *ecx = 0;
4512 *edx = env->features[FEAT_8000_0007_EDX];
4513 break;
c6dc6f63
AP		 4514 case 0x80000008:
4515 /* virtual & phys address size in low 2 bytes. */
0514ef2f 4516 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 4517 /* 64 bit processor */
4518 *eax = cpu->phys_bits; /* configurable physical bits */
4519 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
4520 *eax |= 0x00003900; /* 57 bits virtual */
4521 } else {
4522 *eax |= 0x00003000; /* 48 bits virtual */
4523 }
c6dc6f63 4524 } else {
af45907a 4525 *eax = cpu->phys_bits;
c6dc6f63 4526 }
1b3420e1 4527 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 4528 *ecx = 0;
4529 *edx = 0;
ce3960eb
AF		 4530 if (cs->nr_cores * cs->nr_threads > 1) {
4531 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 4532 }
4533 break;
4534 case 0x8000000A:
0514ef2f 4535 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 4536 *eax = 0x00000001; /* SVM Revision */
4537 *ebx = 0x00000010; /* nr of ASIDs */
4538 *ecx = 0;
0514ef2f 4539 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 4540 } else {
4541 *eax = 0;
4542 *ebx = 0;
4543 *ecx = 0;
4544 *edx = 0;
4545 }
c6dc6f63 4546 break;
8f4202fb
BM		 4547 case 0x8000001D:
4548 *eax = 0;
4549 switch (count) {
4550 case 0: /* L1 dcache info */
4551 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
4552 eax, ebx, ecx, edx);
4553 break;
4554 case 1: /* L1 icache info */
4555 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
4556 eax, ebx, ecx, edx);
4557 break;
4558 case 2: /* L2 cache info */
4559 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
4560 eax, ebx, ecx, edx);
4561 break;
4562 case 3: /* L3 cache info */
4563 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
4564 eax, ebx, ecx, edx);
4565 break;
4566 default: /* end of info */
4567 *eax = *ebx = *ecx = *edx = 0;
4568 break;
4569 }
4570 break;
ed78467a
BM		 4571 case 0x8000001E:
4572 assert(cpu->core_id <= 255);
4573 encode_topo_cpuid8000001e(cs, cpu,
4574 eax, ebx, ecx, edx);
4575 break;
b3baa152
BW		 4576 case 0xC0000000:
4577 *eax = env->cpuid_xlevel2;
4578 *ebx = 0;
4579 *ecx = 0;
4580 *edx = 0;
4581 break;
4582 case 0xC0000001:
4583 /* Support for VIA CPU's CPUID instruction */
4584 *eax = env->cpuid_version;
4585 *ebx = 0;
4586 *ecx = 0;
0514ef2f 4587 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 4588 break;
4589 case 0xC0000002:
4590 case 0xC0000003:
4591 case 0xC0000004:
4592 /* Reserved for the future, and now filled with zero */
4593 *eax = 0;
4594 *ebx = 0;
4595 *ecx = 0;
4596 *edx = 0;
4597 break;
6cb8f2a6
BS		 4598 case 0x8000001F:
4599 *eax = sev_enabled() ? 0x2 : 0;
4600 *ebx = sev_get_cbit_position();
4601 *ebx |= sev_get_reduced_phys_bits() << 6;
4602 *ecx = 0;
4603 *edx = 0;
4604 break;
c6dc6f63
AP		 4605 default:
4606 /* reserved values: zero */
4607 *eax = 0;
4608 *ebx = 0;
4609 *ecx = 0;
4610 *edx = 0;
4611 break;
4612 }
4613}
5fd2087a
AF		 4614
4615/* CPUClass::reset() */
4616static void x86_cpu_reset(CPUState *s)
4617{
4618 X86CPU *cpu = X86_CPU(s);
4619 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
4620 CPUX86State *env = &cpu->env;
a114d25d
RH		 4621 target_ulong cr4;
4622 uint64_t xcr0;
c1958aea
AF		 4623 int i;
4624
5fd2087a
AF		 4625 xcc->parent_reset(s);
4626
5e992a8e 4627 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 4628
c1958aea
AF		 4629 env->old_exception = -1;
4630
4631 /* init to reset state */
4632
c1958aea
AF		 4633 env->hflags2 |= HF2_GIF_MASK;
4634
4635 cpu_x86_update_cr0(env, 0x60000010);
4636 env->a20_mask = ~0x0;
4637 env->smbase = 0x30000;
e13713db 4638 env->msr_smi_count = 0;
c1958aea
AF		 4639
4640 env->idt.limit = 0xffff;
4641 env->gdt.limit = 0xffff;
4642 env->ldt.limit = 0xffff;
4643 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4644 env->tr.limit = 0xffff;
4645 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4646
4647 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4648 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4649 DESC_R_MASK | DESC_A_MASK);
4650 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4651 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4652 DESC_A_MASK);
4653 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4654 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4655 DESC_A_MASK);
4656 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4657 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4658 DESC_A_MASK);
4659 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4660 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4661 DESC_A_MASK);
4662 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4663 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4664 DESC_A_MASK);
4665
4666 env->eip = 0xfff0;
4667 env->regs[R_EDX] = env->cpuid_version;
4668
4669 env->eflags = 0x2;
4670
4671 /* FPU init */
4672 for (i = 0; i < 8; i++) {
4673 env->fptags[i] = 1;
4674 }
5bde1407 4675 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 4676
4677 env->mxcsr = 0x1f80;
a114d25d
RH		 4678 /* All units are in INIT state. */
4679 env->xstate_bv = 0;
c1958aea
AF		 4680
4681 env->pat = 0x0007040600070406ULL;
4682 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4683
4684 memset(env->dr, 0, sizeof(env->dr));
4685 env->dr[6] = DR6_FIXED_1;
4686 env->dr[7] = DR7_FIXED_1;
b3310ab3 4687 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 4688 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 4689
a114d25d 4690 cr4 = 0;
cfc3b074 4691 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 4692
4693#ifdef CONFIG_USER_ONLY
4694 /* Enable all the features for user-mode. */
4695 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 4696 xcr0 |= XSTATE_SSE_MASK;
a114d25d 4697 }
0f70ed47
PB		 4698 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4699 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 4700 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 4701 xcr0 |= 1ull << i;
4702 }
a114d25d 4703 }
0f70ed47 4704
a114d25d
RH		 4705 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4706 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4707 }
07929f2a
RH		 4708 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4709 cr4 |= CR4_FSGSBASE_MASK;
4710 }
a114d25d
RH		 4711#endif
4712
4713 env->xcr0 = xcr0;
4714 cpu_x86_update_cr4(env, cr4);
0522604b 4715
9db2efd9
AW		 4716 /*
4717 * SDM 11.11.5 requires:
4718 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4719 * - IA32_MTRR_PHYSMASKn.V = 0
4720 * All other bits are undefined. For simplification, zero it all.
4721 */
4722 env->mtrr_deftype = 0;
4723 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4724 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4725
b7394c83
SAGDR		 4726 env->interrupt_injected = -1;
4727 env->exception_injected = -1;
4728 env->nmi_injected = false;
dd673288
IM		 4729#if !defined(CONFIG_USER_ONLY)
4730 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 4731 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 4732
259186a7 4733 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 4734
4735 if (kvm_enabled()) {
4736 kvm_arch_reset_vcpu(cpu);
4737 }
d6dcc558
SAGDR		 4738 else if (hvf_enabled()) {
4739 hvf_reset_vcpu(s);
4740 }
dd673288 4741#endif
5fd2087a
AF		 4742}
4743
dd673288
IM		 4744#ifndef CONFIG_USER_ONLY
4745bool cpu_is_bsp(X86CPU *cpu)
4746{
02e51483 4747 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 4748}
65dee380
IM		 4749
4750/* TODO: remove me, when reset over QOM tree is implemented */
4751static void x86_cpu_machine_reset_cb(void *opaque)
4752{
4753 X86CPU *cpu = opaque;
4754 cpu_reset(CPU(cpu));
4755}
dd673288
IM		 4756#endif
4757
de024815
AF		 4758static void mce_init(X86CPU *cpu)
4759{
4760 CPUX86State *cenv = &cpu->env;
4761 unsigned int bank;
4762
4763 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 4764 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 4765 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 4766 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4767 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 4768 cenv->mcg_ctl = ~(uint64_t)0;
4769 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4770 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4771 }
4772 }
4773}
4774
bdeec802 4775#ifndef CONFIG_USER_ONLY
2f114315 4776APICCommonClass *apic_get_class(void)
bdeec802 4777{
bdeec802
IM		 4778 const char *apic_type = "apic";
4779
d6dcc558 4780 /* TODO: in-kernel irqchip for hvf */
15eafc2e 4781 if (kvm_apic_in_kernel()) {
bdeec802
IM		 4782 apic_type = "kvm-apic";
4783 } else if (xen_enabled()) {
4784 apic_type = "xen-apic";
4785 }
4786
2f114315
RK		 4787 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4788}
4789
4790static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4791{
4792 APICCommonState *apic;
4793 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4794
4795 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 4796
6816b1b3
IM		 4797 object_property_add_child(OBJECT(cpu), "lapic",
4798 OBJECT(cpu->apic_state), &error_abort);
67e55caa 4799 object_unref(OBJECT(cpu->apic_state));
6816b1b3 4800
33d7a288 4801 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 4802 /* TODO: convert to link<> */
02e51483 4803 apic = APIC_COMMON(cpu->apic_state);
60671e58 4804 apic->cpu = cpu;
8d42d2d3 4805 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 4806}
4807
4808static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4809{
8d42d2d3
CF		 4810 APICCommonState *apic;
4811 static bool apic_mmio_map_once;
4812
02e51483 4813 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 4814 return;
4815 }
6e8e2651
MA		 4816 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4817 errp);
8d42d2d3
CF		 4818
4819 /* Map APIC MMIO area */
4820 apic = APIC_COMMON(cpu->apic_state);
4821 if (!apic_mmio_map_once) {
4822 memory_region_add_subregion_overlap(get_system_memory(),
4823 apic->apicbase &
4824 MSR_IA32_APICBASE_BASE,
4825 &apic->io_memory,
4826 0x1000);
4827 apic_mmio_map_once = true;
4828 }
bdeec802 4829}
f809c605
PB		 4830
4831static void x86_cpu_machine_done(Notifier *n, void *unused)
4832{
4833 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4834 MemoryRegion *smram =
4835 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4836
4837 if (smram) {
4838 cpu->smram = g_new(MemoryRegion, 1);
4839 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4840 smram, 0, 1ull << 32);
f8c45c65 4841 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 4842 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4843 }
4844}
d3c64d6a
IM		 4845#else
4846static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4847{
4848}
bdeec802
IM		 4849#endif
4850
11f6fee5
DDAG		 4851/* Note: Only safe for use on x86(-64) hosts */
4852static uint32_t x86_host_phys_bits(void)
4853{
4854 uint32_t eax;
4855 uint32_t host_phys_bits;
4856
4857 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4858 if (eax >= 0x80000008) {
4859 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4860 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4861 * at 23:16 that can specify a maximum physical address bits for
4862 * the guest that can override this value; but I've not seen
4863 * anything with that set.
4864 */
4865 host_phys_bits = eax & 0xff;
4866 } else {
4867 /* It's an odd 64 bit machine that doesn't have the leaf for
4868 * physical address bits; fall back to 36 that's most older
4869 * Intel.
4870 */
4871 host_phys_bits = 36;
4872 }
4873
4874 return host_phys_bits;
4875}
e48638fd 4876
c39c0edf
EH		 4877static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4878{
4879 if (*min < value) {
4880 *min = value;
4881 }
4882}
4883
4884/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4885static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4886{
4887 CPUX86State *env = &cpu->env;
4888 FeatureWordInfo *fi = &feature_word_info[w];
07585923 4889 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 4890 uint32_t region = eax & 0xF0000000;
4891
07585923 4892 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 4893 if (!env->features[w]) {
4894 return;
4895 }
4896
4897 switch (region) {
4898 case 0x00000000:
4899 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4900 break;
4901 case 0x80000000:
4902 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4903 break;
4904 case 0xC0000000:
4905 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4906 break;
4907 }
4908}
4909
2ca8a8be
EH		 4910/* Calculate XSAVE components based on the configured CPU feature flags */
4911static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4912{
4913 CPUX86State *env = &cpu->env;
4914 int i;
96193c22 4915 uint64_t mask;
2ca8a8be
EH		 4916
4917 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4918 return;
4919 }
4920
e3c9022b
EH		 4921 mask = 0;
4922 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 4923 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4924 if (env->features[esa->feature] & esa->bits) {
96193c22 4925 mask |= (1ULL << i);
2ca8a8be
EH		 4926 }
4927 }
4928
96193c22
EH		 4929 env->features[FEAT_XSAVE_COMP_LO] = mask;
4930 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 4931}
4932
b8d834a0
EH		 4933/***** Steps involved on loading and filtering CPUID data
4934 *
4935 * When initializing and realizing a CPU object, the steps
4936 * involved in setting up CPUID data are:
4937 *
4938 * 1) Loading CPU model definition (X86CPUDefinition). This is
4939 * implemented by x86_cpu_load_def() and should be completely
4940 * transparent, as it is done automatically by instance_init.
4941 * No code should need to look at X86CPUDefinition structs
4942 * outside instance_init.
4943 *
4944 * 2) CPU expansion. This is done by realize before CPUID
4945 * filtering, and will make sure host/accelerator data is
4946 * loaded for CPU models that depend on host capabilities
4947 * (e.g. "host"). Done by x86_cpu_expand_features().
4948 *
4949 * 3) CPUID filtering. This initializes extra data related to
4950 * CPUID, and checks if the host supports all capabilities
4951 * required by the CPU. Runnability of a CPU model is
4952 * determined at this step. Done by x86_cpu_filter_features().
4953 *
4954 * Some operations don't require all steps to be performed.
4955 * More precisely:
4956 *
4957 * - CPU instance creation (instance_init) will run only CPU
4958 * model loading. CPU expansion can't run at instance_init-time
4959 * because host/accelerator data may be not available yet.
4960 * - CPU realization will perform both CPU model expansion and CPUID
4961 * filtering, and return an error in case one of them fails.
4962 * - query-cpu-definitions needs to run all 3 steps. It needs
4963 * to run CPUID filtering, as the 'unavailable-features'
4964 * field is set based on the filtering results.
4965 * - The query-cpu-model-expansion QMP command only needs to run
4966 * CPU model loading and CPU expansion. It should not filter
4967 * any CPUID data based on host capabilities.
4968 */
4969
4970/* Expand CPU configuration data, based on configured features
4971 * and host/accelerator capabilities when appropriate.
4972 */
4973static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 4974{
b34d12d1 4975 CPUX86State *env = &cpu->env;
dc15c051 4976 FeatureWord w;
2fae0d96 4977 GList *l;
41f3d4d6 4978 Error *local_err = NULL;
9886e834 4979
d4a606b3
EH		 4980 /*TODO: Now cpu->max_features doesn't overwrite features
4981 * set using QOM properties, and we can convert
dc15c051
IM		 4982 * plus_features & minus_features to global properties
4983 * inside x86_cpu_parse_featurestr() too.
4984 */
44bd8e53 4985 if (cpu->max_features) {
dc15c051 4986 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 4987 /* Override only features that weren't set explicitly
4988 * by the user.
4989 */
4990 env->features[w] |=
4991 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
0d914f39
EH		 4992 ~env->user_features[w] & \
4993 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 4994 }
4995 }
4996
2fae0d96
EH		 4997 for (l = plus_features; l; l = l->next) {
4998 const char *prop = l->data;
4999 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
5000 if (local_err) {
5001 goto out;
5002 }
5003 }
5004
5005 for (l = minus_features; l; l = l->next) {
5006 const char *prop = l->data;
5007 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
5008 if (local_err) {
5009 goto out;
5010 }
dc15c051
IM		 5011 }
5012
aec661de
EH		 5013 if (!kvm_enabled() || !cpu->expose_kvm) {
5014 env->features[FEAT_KVM] = 0;
5015 }
5016
2ca8a8be 5017 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 5018
5019 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
5020 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
5021 if (cpu->full_cpuid_auto_level) {
5022 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
5023 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
5024 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
5025 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
5026 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
5027 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
5028 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 5029 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 5030 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
5031 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
5032 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 5033 /* SVM requires CPUID[0x8000000A] */
5034 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5035 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
5036 }
6cb8f2a6
BS		 5037
5038 /* SEV requires CPUID[0x8000001F] */
5039 if (sev_enabled()) {
5040 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
5041 }
c39c0edf
EH		 5042 }
5043
5044 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
5045 if (env->cpuid_level == UINT32_MAX) {
5046 env->cpuid_level = env->cpuid_min_level;
5047 }
5048 if (env->cpuid_xlevel == UINT32_MAX) {
5049 env->cpuid_xlevel = env->cpuid_min_xlevel;
5050 }
5051 if (env->cpuid_xlevel2 == UINT32_MAX) {
5052 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 5053 }
7a059953 5054
41f3d4d6
EH		 5055out:
5056 if (local_err != NULL) {
5057 error_propagate(errp, local_err);
5058 }
5059}
5060
b8d834a0
EH		 5061/*
5062 * Finishes initialization of CPUID data, filters CPU feature
5063 * words based on host availability of each feature.
5064 *
5065 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
5066 */
5067static int x86_cpu_filter_features(X86CPU *cpu)
5068{
5069 CPUX86State *env = &cpu->env;
5070 FeatureWord w;
5071 int rv = 0;
5072
5073 for (w = 0; w < FEATURE_WORDS; w++) {
5074 uint32_t host_feat =
5075 x86_cpu_get_supported_feature_word(w, false);
5076 uint32_t requested_features = env->features[w];
5077 env->features[w] &= host_feat;
5078 cpu->filtered_features[w] = requested_features & ~env->features[w];
5079 if (cpu->filtered_features[w]) {
5080 rv = 1;
5081 }
5082 }
5083
e37a5c7f
CP		 5084 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5085 kvm_enabled()) {
5086 KVMState *s = CPU(cpu)->kvm_state;
5087 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
5088 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
5089 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
5090 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
5091 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
5092
5093 if (!eax_0 ||
5094 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
5095 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
5096 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
5097 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
5098 INTEL_PT_ADDR_RANGES_NUM) ||
5099 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96
LK		 5100 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
5101 (ecx_0 & INTEL_PT_IP_LIP)) {
e37a5c7f
CP		 5102 /*
5103 * Processor Trace capabilities aren't configurable, so if the
5104 * host can't emulate the capabilities we report on
5105 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
5106 */
5107 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
5108 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
5109 rv = 1;
5110 }
5111 }
5112
b8d834a0
EH		 5113 return rv;
5114}
5115
41f3d4d6
EH		 5116#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
5117 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
5118 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
5119#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
5120 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
5121 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
5122static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
5123{
5124 CPUState *cs = CPU(dev);
5125 X86CPU *cpu = X86_CPU(dev);
5126 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5127 CPUX86State *env = &cpu->env;
5128 Error *local_err = NULL;
5129 static bool ht_warned;
5130
2266d443
MT		 5131 if (xcc->host_cpuid_required) {
5132 if (!accel_uses_host_cpuid()) {
5133 char *name = x86_cpu_class_get_model_name(xcc);
5134 error_setg(&local_err, "CPU model '%s' requires KVM", name);
5135 g_free(name);
5136 goto out;
5137 }
5138
5139 if (enable_cpu_pm) {
5140 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
5141 &cpu->mwait.ecx, &cpu->mwait.edx);
5142 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
5143 }
41f3d4d6
EH		 5144 }
5145
2266d443
MT		 5146 /* mwait extended info: needed for Core compatibility */
5147 /* We always wake on interrupt even if host does not have the capability */
5148 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
5149
41f3d4d6
EH		 5150 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
5151 error_setg(errp, "apic-id property was not initialized properly");
5152 return;
5153 }
5154
b8d834a0 5155 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 5156 if (local_err) {
5157 goto out;
5158 }
5159
8ca30e86
EH		 5160 if (x86_cpu_filter_features(cpu) &&
5161 (cpu->check_cpuid || cpu->enforce_cpuid)) {
5162 x86_cpu_report_filtered_features(cpu);
5163 if (cpu->enforce_cpuid) {
5164 error_setg(&local_err,
d6dcc558 5165 accel_uses_host_cpuid() ?
8ca30e86
EH		 5166 "Host doesn't support requested features" :
5167 "TCG doesn't support requested features");
5168 goto out;
5169 }
9997cf7b
EH		 5170 }
5171
9b15cd9e
IM		 5172 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
5173 * CPUID[1].EDX.
5174 */
e48638fd 5175 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 5176 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
5177 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 5178 & CPUID_EXT2_AMD_ALIASES);
5179 }
5180
11f6fee5
DDAG		 5181 /* For 64bit systems think about the number of physical bits to present.
5182 * ideally this should be the same as the host; anything other than matching
5183 * the host can cause incorrect guest behaviour.
5184 * QEMU used to pick the magic value of 40 bits that corresponds to
5185 * consumer AMD devices but nothing else.
5186 */
af45907a 5187 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 5188 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 5189 uint32_t host_phys_bits = x86_host_phys_bits();
5190 static bool warned;
5191
5192 if (cpu->host_phys_bits) {
5193 /* The user asked for us to use the host physical bits */
5194 cpu->phys_bits = host_phys_bits;
258fe08b
EH		 5195 if (cpu->host_phys_bits_limit &&
5196 cpu->phys_bits > cpu->host_phys_bits_limit) {
5197 cpu->phys_bits = cpu->host_phys_bits_limit;
5198 }
11f6fee5
DDAG		 5199 }
5200
5201 /* Print a warning if the user set it to a value that's not the
5202 * host value.
5203 */
5204 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
5205 !warned) {
3dc6f869
AF		 5206 warn_report("Host physical bits (%u)"
5207 " does not match phys-bits property (%u)",
5208 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 5209 warned = true;
5210 }
5211
5212 if (cpu->phys_bits &&
5213 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
5214 cpu->phys_bits < 32)) {
af45907a
DDAG		 5215 error_setg(errp, "phys-bits should be between 32 and %u "
5216 " (but is %u)",
5217 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
5218 return;
5219 }
5220 } else {
11f6fee5 5221 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 5222 error_setg(errp, "TCG only supports phys-bits=%u",
5223 TCG_PHYS_ADDR_BITS);
5224 return;
5225 }
5226 }
11f6fee5
DDAG		 5227 /* 0 means it was not explicitly set by the user (or by machine
5228 * compat_props or by the host code above). In this case, the default
5229 * is the value used by TCG (40).
5230 */
5231 if (cpu->phys_bits == 0) {
5232 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
5233 }
af45907a
DDAG		 5234 } else {
5235 /* For 32 bit systems don't use the user set value, but keep
5236 * phys_bits consistent with what we tell the guest.
5237 */
5238 if (cpu->phys_bits != 0) {
5239 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
5240 return;
5241 }
fefb41bf 5242
af45907a
DDAG		 5243 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
5244 cpu->phys_bits = 36;
5245 } else {
5246 cpu->phys_bits = 32;
5247 }
5248 }
a9f27ea9
EH		 5249
5250 /* Cache information initialization */
5251 if (!cpu->legacy_cache) {
5252 if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
5253 char *name = x86_cpu_class_get_model_name(xcc);
5254 error_setg(errp,
5255 "CPU model '%s' doesn't support legacy-cache=off", name);
5256 g_free(name);
5257 return;
5258 }
5259 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
5260 *xcc->cpu_def->cache_info;
5261 } else {
5262 /* Build legacy cache information */
5263 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
5264 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
5265 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
5266 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
5267
5268 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
5269 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
5270 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
5271 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
5272
5273 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
5274 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
5275 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
5276 env->cache_info_amd.l3_cache = &legacy_l3_cache;
5277 }
5278
5279
ce5b1bbf
LV		 5280 cpu_exec_realizefn(cs, &local_err);
5281 if (local_err != NULL) {
5282 error_propagate(errp, local_err);
5283 return;
5284 }
42ecabaa 5285
65dee380
IM		 5286#ifndef CONFIG_USER_ONLY
5287 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 5288
0514ef2f 5289 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 5290 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 5291 if (local_err != NULL) {
4dc1f449 5292 goto out;
bdeec802
IM		 5293 }
5294 }
65dee380
IM		 5295#endif
5296
7a059953 5297 mce_init(cpu);
2001d0cd
PB		 5298
5299#ifndef CONFIG_USER_ONLY
5300 if (tcg_enabled()) {
f809c605 5301 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 5302 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 5303
5304 /* Outer container... */
5305 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 5306 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 5307
5308 /* ... with two regions inside: normal system memory with low
5309 * priority, and...
5310 */
5311 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
5312 get_system_memory(), 0, ~0ull);
5313 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
5314 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 5315
5316 cs->num_ases = 2;
80ceb07a
PX		 5317 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
5318 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 5319
5320 /* ... SMRAM with higher priority, linked from /machine/smram. */
5321 cpu->machine_done.notify = x86_cpu_machine_done;
5322 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 5323 }
5324#endif
5325
14a10fc3 5326 qemu_init_vcpu(cs);
d3c64d6a 5327
6b2942f9
BM		 5328 /*
5329 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
5330 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
5331 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 5332 * users a warning.
5333 *
5334 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
5335 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
5336 */
0765691e
MA		 5337 if (IS_AMD_CPU(env) &&
5338 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
5339 cs->nr_threads > 1 && !ht_warned) {
5340 warn_report("This family of AMD CPU doesn't support "
5341 "hyperthreading(%d)",
5342 cs->nr_threads);
5343 error_printf("Please configure -smp options properly"
5344 " or try enabling topoext feature.\n");
5345 ht_warned = true;
e48638fd
WH		 5346 }
5347
d3c64d6a
IM		 5348 x86_cpu_apic_realize(cpu, &local_err);
5349 if (local_err != NULL) {
5350 goto out;
5351 }
14a10fc3 5352 cpu_reset(cs);
2b6f294c 5353
4dc1f449 5354 xcc->parent_realize(dev, &local_err);
2001d0cd 5355
4dc1f449
IM		 5356out:
5357 if (local_err != NULL) {
5358 error_propagate(errp, local_err);
5359 return;
5360 }
7a059953
AF		 5361}
5362
c884776e
IM		 5363static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
5364{
5365 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 5366 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5367 Error *local_err = NULL;
c884776e
IM		 5368
5369#ifndef CONFIG_USER_ONLY
5370 cpu_remove_sync(CPU(dev));
5371 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
5372#endif
5373
5374 if (cpu->apic_state) {
5375 object_unparent(OBJECT(cpu->apic_state));
5376 cpu->apic_state = NULL;
5377 }
7bbc124e
LV		 5378
5379 xcc->parent_unrealize(dev, &local_err);
5380 if (local_err != NULL) {
5381 error_propagate(errp, local_err);
5382 return;
5383 }
c884776e
IM		 5384}
5385
38e5c119 5386typedef struct BitProperty {
a7b0ffac 5387 FeatureWord w;
38e5c119
EH		 5388 uint32_t mask;
5389} BitProperty;
5390
d7bce999
EB		 5391static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
5392 void *opaque, Error **errp)
38e5c119 5393{
a7b0ffac 5394 X86CPU *cpu = X86_CPU(obj);
38e5c119 5395 BitProperty *fp = opaque;
a7b0ffac
EH		 5396 uint32_t f = cpu->env.features[fp->w];
5397 bool value = (f & fp->mask) == fp->mask;
51e72bc1 5398 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 5399}
5400
d7bce999
EB		 5401static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
5402 void *opaque, Error **errp)
38e5c119
EH		 5403{
5404 DeviceState *dev = DEVICE(obj);
a7b0ffac 5405 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 5406 BitProperty *fp = opaque;
5407 Error *local_err = NULL;
5408 bool value;
5409
5410 if (dev->realized) {
5411 qdev_prop_set_after_realize(dev, name, errp);
5412 return;
5413 }
5414
51e72bc1 5415 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 5416 if (local_err) {
5417 error_propagate(errp, local_err);
5418 return;
5419 }
5420
5421 if (value) {
a7b0ffac 5422 cpu->env.features[fp->w] |= fp->mask;
38e5c119 5423 } else {
a7b0ffac 5424 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 5425 }
d4a606b3 5426 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 5427}
5428
5429static void x86_cpu_release_bit_prop(Object *obj, const char *name,
5430 void *opaque)
5431{
5432 BitProperty *prop = opaque;
5433 g_free(prop);
5434}
5435
5436/* Register a boolean property to get/set a single bit in a uint32_t field.
5437 *
5438 * The same property name can be registered multiple times to make it affect
5439 * multiple bits in the same FeatureWord. In that case, the getter will return
5440 * true only if all bits are set.
5441 */
5442static void x86_cpu_register_bit_prop(X86CPU *cpu,
5443 const char *prop_name,
a7b0ffac 5444 FeatureWord w,
38e5c119
EH		 5445 int bitnr)
5446{
5447 BitProperty *fp;
5448 ObjectProperty *op;
5449 uint32_t mask = (1UL << bitnr);
5450
5451 op = object_property_find(OBJECT(cpu), prop_name, NULL);
5452 if (op) {
5453 fp = op->opaque;
a7b0ffac 5454 assert(fp->w == w);
38e5c119
EH		 5455 fp->mask |= mask;
5456 } else {
5457 fp = g_new0(BitProperty, 1);
a7b0ffac 5458 fp->w = w;
38e5c119
EH		 5459 fp->mask = mask;
5460 object_property_add(OBJECT(cpu), prop_name, "bool",
5461 x86_cpu_get_bit_prop,
5462 x86_cpu_set_bit_prop,
5463 x86_cpu_release_bit_prop, fp, &error_abort);
5464 }
5465}
5466
5467static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
5468 FeatureWord w,
5469 int bitnr)
5470{
38e5c119 5471 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 5472 const char *name = fi->feat_names[bitnr];
38e5c119 5473
16d2fcaa 5474 if (!name) {
38e5c119
EH		 5475 return;
5476 }
5477
fc7dfd20
EH		 5478 /* Property names should use "-" instead of "_".
5479 * Old names containing underscores are registered as aliases
5480 * using object_property_add_alias()
5481 */
16d2fcaa
EH		 5482 assert(!strchr(name, '_'));
5483 /* aliases don't use "|" delimiters anymore, they are registered
5484 * manually using object_property_add_alias() */
5485 assert(!strchr(name, '|'));
a7b0ffac 5486 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 5487}
5488
d187e08d
AN		 5489static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
5490{
5491 X86CPU *cpu = X86_CPU(cs);
5492 CPUX86State *env = &cpu->env;
5493 GuestPanicInformation *panic_info = NULL;
5494
5e953812 5495 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 5496 panic_info = g_malloc0(sizeof(GuestPanicInformation));
5497
e8ed97a6 5498 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 5499
5e953812 5500 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 5501 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
5502 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
5503 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
5504 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
5505 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 5506 }
5507
5508 return panic_info;
5509}
5510static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
5511 const char *name, void *opaque,
5512 Error **errp)
5513{
5514 CPUState *cs = CPU(obj);
5515 GuestPanicInformation *panic_info;
5516
5517 if (!cs->crash_occurred) {
5518 error_setg(errp, "No crash occured");
5519 return;
5520 }
5521
5522 panic_info = x86_cpu_get_crash_info(cs);
5523 if (panic_info == NULL) {
5524 error_setg(errp, "No crash information");
5525 return;
5526 }
5527
5528 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
5529 errp);
5530 qapi_free_GuestPanicInformation(panic_info);
5531}
5532
de024815
AF		 5533static void x86_cpu_initfn(Object *obj)
5534{
55e5c285 5535 CPUState *cs = CPU(obj);
de024815 5536 X86CPU *cpu = X86_CPU(obj);
d940ee9b 5537 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 5538 CPUX86State *env = &cpu->env;
38e5c119 5539 FeatureWord w;
de024815 5540
c05efcb1 5541 cs->env_ptr = env;
71ad61d3
AF		 5542
5543 object_property_add(obj, "family", "int",
95b8519d 5544 x86_cpuid_version_get_family,
71ad61d3 5545 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 5546 object_property_add(obj, "model", "int",
67e30c83 5547 x86_cpuid_version_get_model,
c5291a4f 5548 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 5549 object_property_add(obj, "stepping", "int",
35112e41 5550 x86_cpuid_version_get_stepping,
036e2222 5551 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 5552 object_property_add_str(obj, "vendor",
5553 x86_cpuid_get_vendor,
5554 x86_cpuid_set_vendor, NULL);
938d4c25 5555 object_property_add_str(obj, "model-id",
63e886eb 5556 x86_cpuid_get_model_id,
938d4c25 5557 x86_cpuid_set_model_id, NULL);
89e48965
AF		 5558 object_property_add(obj, "tsc-frequency", "int",
5559 x86_cpuid_get_tsc_freq,
5560 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 5561 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
5562 x86_cpu_get_feature_words,
7e5292b5
EH		 5563 NULL, NULL, (void *)env->features, NULL);
5564 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
5565 x86_cpu_get_feature_words,
5566 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 5567
d187e08d
AN		 5568 object_property_add(obj, "crash-information", "GuestPanicInformation",
5569 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
5570
92067bf4 5571 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 5572
38e5c119
EH		 5573 for (w = 0; w < FEATURE_WORDS; w++) {
5574 int bitnr;
5575
5576 for (bitnr = 0; bitnr < 32; bitnr++) {
5577 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
5578 }
5579 }
5580
16d2fcaa
EH		 5581 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
5582 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
5583 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
5584 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
5585 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
5586 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
5587 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
5588
54b8dc7c
EH		 5589 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
5590 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
5591 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
5592 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
5593 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
5594 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
5595 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
5596 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
5597 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
5598 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
5599 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
5600 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
5601 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
5602 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
5603 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
5604 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
5605 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
5606 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
5607 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
5608 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
5609 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
5610
0bacd8b3
EH		 5611 if (xcc->cpu_def) {
5612 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
5613 }
de024815
AF		 5614}
5615
997395d3
IM		 5616static int64_t x86_cpu_get_arch_id(CPUState *cs)
5617{
5618 X86CPU *cpu = X86_CPU(cs);
997395d3 5619
7e72a45c 5620 return cpu->apic_id;
997395d3
IM		 5621}
5622
444d5590
AF		 5623static bool x86_cpu_get_paging_enabled(const CPUState *cs)
5624{
5625 X86CPU *cpu = X86_CPU(cs);
5626
5627 return cpu->env.cr[0] & CR0_PG_MASK;
5628}
5629
f45748f1
AF		 5630static void x86_cpu_set_pc(CPUState *cs, vaddr value)
5631{
5632 X86CPU *cpu = X86_CPU(cs);
5633
5634 cpu->env.eip = value;
5635}
5636
bdf7ae5b
AF		 5637static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
5638{
5639 X86CPU *cpu = X86_CPU(cs);
5640
5641 cpu->env.eip = tb->pc - tb->cs_base;
5642}
5643
92d5f1a4 5644int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 5645{
5646 X86CPU *cpu = X86_CPU(cs);
5647 CPUX86State *env = &cpu->env;
5648
92d5f1a4
PB		 5649#if !defined(CONFIG_USER_ONLY)
5650 if (interrupt_request & CPU_INTERRUPT_POLL) {
5651 return CPU_INTERRUPT_POLL;
5652 }
5653#endif
5654 if (interrupt_request & CPU_INTERRUPT_SIPI) {
5655 return CPU_INTERRUPT_SIPI;
5656 }
5657
5658 if (env->hflags2 & HF2_GIF_MASK) {
5659 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
5660 !(env->hflags & HF_SMM_MASK)) {
5661 return CPU_INTERRUPT_SMI;
5662 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
5663 !(env->hflags2 & HF2_NMI_MASK)) {
5664 return CPU_INTERRUPT_NMI;
5665 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
5666 return CPU_INTERRUPT_MCE;
5667 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
5668 (((env->hflags2 & HF2_VINTR_MASK) &&
5669 (env->hflags2 & HF2_HIF_MASK)) ||
5670 (!(env->hflags2 & HF2_VINTR_MASK) &&
5671 (env->eflags & IF_MASK &&
5672 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
5673 return CPU_INTERRUPT_HARD;
5674#if !defined(CONFIG_USER_ONLY)
5675 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
5676 (env->eflags & IF_MASK) &&
5677 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
5678 return CPU_INTERRUPT_VIRQ;
5679#endif
5680 }
5681 }
5682
5683 return 0;
5684}
5685
5686static bool x86_cpu_has_work(CPUState *cs)
5687{
5688 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 5689}
5690
f50f3dd5
RH		 5691static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
5692{
5693 X86CPU *cpu = X86_CPU(cs);
5694 CPUX86State *env = &cpu->env;
5695
5696 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
5697 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
5698 : bfd_mach_i386_i8086);
5699 info->print_insn = print_insn_i386;
b666d2a4
RH		 5700
5701 info->cap_arch = CS_ARCH_X86;
5702 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
5703 : env->hflags & HF_CS32_MASK ? CS_MODE_32
5704 : CS_MODE_16);
15fa1a0a
RH		 5705 info->cap_insn_unit = 1;
5706 info->cap_insn_split = 8;
f50f3dd5
RH		 5707}
5708
35b1b927
TW		 5709void x86_update_hflags(CPUX86State *env)
5710{
5711 uint32_t hflags;
5712#define HFLAG_COPY_MASK \
5713 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5714 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5715 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5716 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5717
5718 hflags = env->hflags & HFLAG_COPY_MASK;
5719 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5720 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5721 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5722 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5723 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5724
5725 if (env->cr[4] & CR4_OSFXSR_MASK) {
5726 hflags |= HF_OSFXSR_MASK;
5727 }
5728
5729 if (env->efer & MSR_EFER_LMA) {
5730 hflags |= HF_LMA_MASK;
5731 }
5732
5733 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5734 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5735 } else {
5736 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5737 (DESC_B_SHIFT - HF_CS32_SHIFT);
5738 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5739 (DESC_B_SHIFT - HF_SS32_SHIFT);
5740 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5741 !(hflags & HF_CS32_MASK)) {
5742 hflags |= HF_ADDSEG_MASK;
5743 } else {
5744 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5745 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5746 }
5747 }
5748 env->hflags = hflags;
5749}
5750
9337e3b6 5751static Property x86_cpu_properties[] = {
2da00e31
IM		 5752#ifdef CONFIG_USER_ONLY
5753 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5754 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 5755 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5756 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5757 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 5758#else
5759 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 5760 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5761 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5762 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 5763#endif
15f8b142 5764 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 5765 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 5766 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 5767 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 5768 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 5769 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 5770 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 5771 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 5772 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 5773 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 5774 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 5775 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
9445597b 5776 DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
ba6a4fd9 5777 DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment, false),
47512009 5778 DEFINE_PROP_BOOL("hv-tlbflush", X86CPU, hyperv_tlbflush, false),
e204ac61 5779 DEFINE_PROP_BOOL("hv-evmcs", X86CPU, hyperv_evmcs, false),
6b7a9830 5780 DEFINE_PROP_BOOL("hv-ipi", X86CPU, hyperv_ipi, false),
15e41345 5781 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 5782 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 5783 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 5784 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 5785 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
258fe08b 5786 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
fcc35e7c 5787 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 5788 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5789 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5790 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5791 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5792 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5793 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5794 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 5795 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 5796 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 5797 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 5798 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 5799 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5800 false),
0b564e6f 5801 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 5802 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 5803 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
5804 true),
ab8f992e 5805 /*
a9f27ea9
EH		 5806 * lecacy_cache defaults to true unless the CPU model provides its
5807 * own cache information (see x86_cpu_load_def()).
ab8f992e 5808 */
a9f27ea9 5809 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 5810
5811 /*
5812 * From "Requirements for Implementing the Microsoft
5813 * Hypervisor Interface":
5814 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5815 *
5816 * "Starting with Windows Server 2012 and Windows 8, if
5817 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5818 * the hypervisor imposes no specific limit to the number of VPs.
5819 * In this case, Windows Server 2012 guest VMs may use more than
5820 * 64 VPs, up to the maximum supported number of processors applicable
5821 * to the specific Windows version being used."
5822 */
5823 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 5824 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
5825 false),
9337e3b6
EH		 5826 DEFINE_PROP_END_OF_LIST()
5827};
5828
5fd2087a
AF		 5829static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5830{
5831 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5832 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 5833 DeviceClass *dc = DEVICE_CLASS(oc);
5834
bf853881
PMD		 5835 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5836 &xcc->parent_realize);
5837 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5838 &xcc->parent_unrealize);
9337e3b6 5839 dc->props = x86_cpu_properties;
5fd2087a
AF		 5840
5841 xcc->parent_reset = cc->reset;
5842 cc->reset = x86_cpu_reset;
91b1df8c 5843 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 5844
500050d1 5845 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 5846 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 5847 cc->has_work = x86_cpu_has_work;
79c664f6 5848#ifdef CONFIG_TCG
97a8ea5a 5849 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 5850 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 5851#endif
878096ee 5852 cc->dump_state = x86_cpu_dump_state;
c86f106b 5853 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 5854 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 5855 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 5856 cc->gdb_read_register = x86_cpu_gdb_read_register;
5857 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 5858 cc->get_arch_id = x86_cpu_get_arch_id;
5859 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 5860#ifdef CONFIG_USER_ONLY
5861 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
5862#else
f8c45c65 5863 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 5864 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 5865 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 5866 cc->write_elf64_note = x86_cpu_write_elf64_note;
5867 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5868 cc->write_elf32_note = x86_cpu_write_elf32_note;
5869 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 5870 cc->vmsd = &vmstate_x86_cpu;
c72bf468 5871#endif
00fcd100
AB		 5872 cc->gdb_arch_name = x86_gdb_arch_name;
5873#ifdef TARGET_X86_64
b8158192
AB		 5874 cc->gdb_core_xml_file = "i386-64bit.xml";
5875 cc->gdb_num_core_regs = 57;
00fcd100 5876#else
b8158192
AB		 5877 cc->gdb_core_xml_file = "i386-32bit.xml";
5878 cc->gdb_num_core_regs = 41;
00fcd100 5879#endif
79c664f6 5880#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 5881 cc->debug_excp_handler = breakpoint_handler;
5882#endif
374e0cd4
RH		 5883 cc->cpu_exec_enter = x86_cpu_exec_enter;
5884 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 5885#ifdef CONFIG_TCG
55c3ceef 5886 cc->tcg_initialize = tcg_x86_init;
74d7fc7f 5887#endif
f50f3dd5 5888 cc->disas_set_info = x86_disas_set_info;
4c315c27 5889
e90f2a8c 5890 dc->user_creatable = true;
5fd2087a
AF		 5891}
5892
5893static const TypeInfo x86_cpu_type_info = {
5894 .name = TYPE_X86_CPU,
5895 .parent = TYPE_CPU,
5896 .instance_size = sizeof(X86CPU),
de024815 5897 .instance_init = x86_cpu_initfn,
d940ee9b 5898 .abstract = true,
5fd2087a
AF		 5899 .class_size = sizeof(X86CPUClass),
5900 .class_init = x86_cpu_common_class_init,
5901};
5902
5adbed30
EH		 5903
5904/* "base" CPU model, used by query-cpu-model-expansion */
5905static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
5906{
5907 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5908
5909 xcc->static_model = true;
5910 xcc->migration_safe = true;
5911 xcc->model_description = "base CPU model type with no features enabled";
5912 xcc->ordering = 8;
5913}
5914
5915static const TypeInfo x86_base_cpu_type_info = {
5916 .name = X86_CPU_TYPE_NAME("base"),
5917 .parent = TYPE_X86_CPU,
5918 .class_init = x86_cpu_base_class_init,
5919};
5920
5fd2087a
AF		 5921static void x86_cpu_register_types(void)
5922{
d940ee9b
EH		 5923 int i;
5924
5fd2087a 5925 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 5926 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
5927 x86_register_cpudef_type(&builtin_x86_defs[i]);
5928 }
c62f2630 5929 type_register_static(&max_x86_cpu_type_info);
5adbed30 5930 type_register_static(&x86_base_cpu_type_info);
d6dcc558 5931#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 5932 type_register_static(&host_x86_cpu_type_info);
5933#endif
5fd2087a
AF		 5934}
5935
5936type_init(x86_cpu_register_types)
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