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x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIES
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
631be321 23#include "qemu/bitops.h"
c6dc6f63
AP		 24
25#include "cpu.h"
63c91552 26#include "exec/exec-all.h"
9c17d615 27#include "sysemu/kvm.h"
d6dcc558 28#include "sysemu/hvf.h"
8932cfdf 29#include "sysemu/cpus.h"
50a2c6e5 30#include "kvm_i386.h"
6cb8f2a6 31#include "sev_i386.h"
c6dc6f63 32
d49b6836 33#include "qemu/error-report.h"
1de7afc9
PB		 34#include "qemu/option.h"
35#include "qemu/config-file.h"
e688df6b 36#include "qapi/error.h"
112ed241
MA		 37#include "qapi/qapi-visit-misc.h"
38#include "qapi/qapi-visit-run-state.h"
452fcdbc 39#include "qapi/qmp/qdict.h"
7b1b5d19 40#include "qapi/qmp/qerror.h"
7b1b5d19 41#include "qapi/visitor.h"
f99fd7ca 42#include "qom/qom-qobject.h"
9c17d615 43#include "sysemu/arch_init.h"
71ad61d3 44
1814eab6 45#include "standard-headers/asm-x86/kvm_para.h"
65dee380 46
9c17d615 47#include "sysemu/sysemu.h"
53a89e26 48#include "hw/qdev-properties.h"
5232d00a 49#include "hw/i386/topology.h"
bdeec802 50#ifndef CONFIG_USER_ONLY
2001d0cd 51#include "exec/address-spaces.h"
741da0d3 52#include "hw/hw.h"
0d09e41a 53#include "hw/xen/xen.h"
0d09e41a 54#include "hw/i386/apic_internal.h"
bdeec802
IM		 55#endif
56
b666d2a4
RH		 57#include "disas/capstone.h"
58
7e3482f8
EH		 59/* Helpers for building CPUID[2] descriptors: */
60
61struct CPUID2CacheDescriptorInfo {
62 enum CacheType type;
63 int level;
64 int size;
65 int line_size;
66 int associativity;
67};
5e891bf8 68
7e3482f8
EH		 69/*
70 * Known CPUID 2 cache descriptors.
71 * From Intel SDM Volume 2A, CPUID instruction
72 */
73struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 74 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 75 .associativity = 4, .line_size = 32, },
5f00335a 76 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 77 .associativity = 4, .line_size = 32, },
5f00335a 78 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 79 .associativity = 4, .line_size = 64, },
5f00335a 80 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 81 .associativity = 2, .line_size = 32, },
5f00335a 82 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 83 .associativity = 4, .line_size = 32, },
5f00335a 84 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 85 .associativity = 4, .line_size = 64, },
5f00335a 86 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 87 .associativity = 6, .line_size = 64, },
5f00335a 88 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 89 .associativity = 2, .line_size = 64, },
5f00335a 90 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 91 .associativity = 8, .line_size = 64, },
92 /* lines per sector is not supported cpuid2_cache_descriptor(),
93 * so descriptors 0x22, 0x23 are not included
94 */
5f00335a 95 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 96 .associativity = 16, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x25, 0x20 are not included
99 */
5f00335a 100 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 101 .associativity = 8, .line_size = 64, },
5f00335a 102 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 103 .associativity = 8, .line_size = 64, },
5f00335a 104 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 105 .associativity = 4, .line_size = 32, },
5f00335a 106 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 107 .associativity = 4, .line_size = 32, },
5f00335a 108 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 109 .associativity = 4, .line_size = 32, },
5f00335a 110 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 111 .associativity = 4, .line_size = 32, },
5f00335a 112 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 113 .associativity = 4, .line_size = 32, },
5f00335a 114 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 115 .associativity = 4, .line_size = 64, },
5f00335a 116 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 117 .associativity = 8, .line_size = 64, },
5f00335a 118 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 119 .associativity = 12, .line_size = 64, },
120 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 121 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 122 .associativity = 12, .line_size = 64, },
5f00335a 123 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 124 .associativity = 16, .line_size = 64, },
5f00335a 125 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 126 .associativity = 12, .line_size = 64, },
5f00335a 127 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 128 .associativity = 16, .line_size = 64, },
5f00335a 129 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 130 .associativity = 24, .line_size = 64, },
5f00335a 131 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 132 .associativity = 8, .line_size = 64, },
5f00335a 133 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 134 .associativity = 4, .line_size = 64, },
5f00335a 135 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 136 .associativity = 4, .line_size = 64, },
5f00335a 137 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 138 .associativity = 4, .line_size = 64, },
5f00335a 139 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 140 .associativity = 4, .line_size = 64, },
141 /* lines per sector is not supported cpuid2_cache_descriptor(),
142 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
143 */
5f00335a 144 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 145 .associativity = 8, .line_size = 64, },
5f00335a 146 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 147 .associativity = 2, .line_size = 64, },
5f00335a 148 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 149 .associativity = 8, .line_size = 64, },
5f00335a 150 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 151 .associativity = 8, .line_size = 32, },
5f00335a 152 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 153 .associativity = 8, .line_size = 32, },
5f00335a 154 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 155 .associativity = 8, .line_size = 32, },
5f00335a 156 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 157 .associativity = 8, .line_size = 32, },
5f00335a 158 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 159 .associativity = 4, .line_size = 64, },
5f00335a 160 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 161 .associativity = 8, .line_size = 64, },
5f00335a 162 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 163 .associativity = 4, .line_size = 64, },
5f00335a 164 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 165 .associativity = 4, .line_size = 64, },
5f00335a 166 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 167 .associativity = 4, .line_size = 64, },
5f00335a 168 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 169 .associativity = 8, .line_size = 64, },
5f00335a 170 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 171 .associativity = 8, .line_size = 64, },
5f00335a 172 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 173 .associativity = 8, .line_size = 64, },
5f00335a 174 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 175 .associativity = 12, .line_size = 64, },
5f00335a 176 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 177 .associativity = 12, .line_size = 64, },
5f00335a 178 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 179 .associativity = 12, .line_size = 64, },
5f00335a 180 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 181 .associativity = 16, .line_size = 64, },
5f00335a 182 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 183 .associativity = 16, .line_size = 64, },
5f00335a 184 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 185 .associativity = 16, .line_size = 64, },
5f00335a 186 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 187 .associativity = 24, .line_size = 64, },
5f00335a 188 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 189 .associativity = 24, .line_size = 64, },
5f00335a 190 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 191 .associativity = 24, .line_size = 64, },
192};
193
194/*
195 * "CPUID leaf 2 does not report cache descriptor information,
196 * use CPUID leaf 4 to query cache parameters"
197 */
198#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 199
7e3482f8
EH		 200/*
201 * Return a CPUID 2 cache descriptor for a given cache.
202 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
203 */
204static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
205{
206 int i;
207
208 assert(cache->size > 0);
209 assert(cache->level > 0);
210 assert(cache->line_size > 0);
211 assert(cache->associativity > 0);
212 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
213 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
214 if (d->level == cache->level && d->type == cache->type &&
215 d->size == cache->size && d->line_size == cache->line_size &&
216 d->associativity == cache->associativity) {
217 return i;
218 }
219 }
5e891bf8 220
7e3482f8
EH		 221 return CACHE_DESCRIPTOR_UNAVAILABLE;
222}
5e891bf8
EH		 223
224/* CPUID Leaf 4 constants: */
225
226/* EAX: */
7e3482f8
EH		 227#define CACHE_TYPE_D 1
228#define CACHE_TYPE_I 2
229#define CACHE_TYPE_UNIFIED 3
5e891bf8 230
7e3482f8 231#define CACHE_LEVEL(l) (l << 5)
5e891bf8 232
7e3482f8 233#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 234
235/* EDX: */
7e3482f8
EH		 236#define CACHE_NO_INVD_SHARING (1 << 0)
237#define CACHE_INCLUSIVE (1 << 1)
238#define CACHE_COMPLEX_IDX (1 << 2)
239
240/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 241#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
242 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
243 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
244 0 /* Invalid value */)
7e3482f8
EH		 245
246
247/* Encode cache info for CPUID[4] */
248static void encode_cache_cpuid4(CPUCacheInfo *cache,
249 int num_apic_ids, int num_cores,
250 uint32_t *eax, uint32_t *ebx,
251 uint32_t *ecx, uint32_t *edx)
252{
253 assert(cache->size == cache->line_size * cache->associativity *
254 cache->partitions * cache->sets);
255
256 assert(num_apic_ids > 0);
257 *eax = CACHE_TYPE(cache->type) |
258 CACHE_LEVEL(cache->level) |
259 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
260 ((num_cores - 1) << 26) |
261 ((num_apic_ids - 1) << 14);
262
263 assert(cache->line_size > 0);
264 assert(cache->partitions > 0);
265 assert(cache->associativity > 0);
266 /* We don't implement fully-associative caches */
267 assert(cache->associativity < cache->sets);
268 *ebx = (cache->line_size - 1) |
269 ((cache->partitions - 1) << 12) |
270 ((cache->associativity - 1) << 22);
271
272 assert(cache->sets > 0);
273 *ecx = cache->sets - 1;
274
275 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
276 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
277 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
278}
279
280/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
281static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
282{
283 assert(cache->size % 1024 == 0);
284 assert(cache->lines_per_tag > 0);
285 assert(cache->associativity > 0);
286 assert(cache->line_size > 0);
287 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
288 (cache->lines_per_tag << 8) | (cache->line_size);
289}
5e891bf8
EH		 290
291#define ASSOC_FULL 0xFF
292
293/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
294#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
295 a == 2 ? 0x2 : \
296 a == 4 ? 0x4 : \
297 a == 8 ? 0x6 : \
298 a == 16 ? 0x8 : \
299 a == 32 ? 0xA : \
300 a == 48 ? 0xB : \
301 a == 64 ? 0xC : \
302 a == 96 ? 0xD : \
303 a == 128 ? 0xE : \
304 a == ASSOC_FULL ? 0xF : \
305 0 /* invalid value */)
306
7e3482f8
EH		 307/*
308 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
309 * @l3 can be NULL.
310 */
311static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
312 CPUCacheInfo *l3,
313 uint32_t *ecx, uint32_t *edx)
314{
315 assert(l2->size % 1024 == 0);
316 assert(l2->associativity > 0);
317 assert(l2->lines_per_tag > 0);
318 assert(l2->line_size > 0);
319 *ecx = ((l2->size / 1024) << 16) |
320 (AMD_ENC_ASSOC(l2->associativity) << 12) |
321 (l2->lines_per_tag << 8) | (l2->line_size);
322
323 if (l3) {
324 assert(l3->size % (512 * 1024) == 0);
325 assert(l3->associativity > 0);
326 assert(l3->lines_per_tag > 0);
327 assert(l3->line_size > 0);
328 *edx = ((l3->size / (512 * 1024)) << 18) |
329 (AMD_ENC_ASSOC(l3->associativity) << 12) |
330 (l3->lines_per_tag << 8) | (l3->line_size);
331 } else {
332 *edx = 0;
333 }
334}
5e891bf8 335
8f4202fb
BM		 336/*
337 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
338 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
339 * Define the constants to build the cpu topology. Right now, TOPOEXT
340 * feature is enabled only on EPYC. So, these constants are based on
341 * EPYC supported configurations. We may need to handle the cases if
342 * these values change in future.
343 */
344/* Maximum core complexes in a node */
345#define MAX_CCX 2
346/* Maximum cores in a core complex */
347#define MAX_CORES_IN_CCX 4
348/* Maximum cores in a node */
349#define MAX_CORES_IN_NODE 8
350/* Maximum nodes in a socket */
351#define MAX_NODES_PER_SOCKET 4
352
353/*
354 * Figure out the number of nodes required to build this config.
355 * Max cores in a node is 8
356 */
357static int nodes_in_socket(int nr_cores)
358{
359 int nodes;
360
361 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
362
363 /* Hardware does not support config with 3 nodes, return 4 in that case */
364 return (nodes == 3) ? 4 : nodes;
365}
366
367/*
368 * Decide the number of cores in a core complex with the given nr_cores using
369 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
370 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
371 * L3 cache is shared across all cores in a core complex. So, this will also
372 * tell us how many cores are sharing the L3 cache.
373 */
374static int cores_in_core_complex(int nr_cores)
375{
376 int nodes;
377
378 /* Check if we can fit all the cores in one core complex */
379 if (nr_cores <= MAX_CORES_IN_CCX) {
380 return nr_cores;
381 }
382 /* Get the number of nodes required to build this config */
383 nodes = nodes_in_socket(nr_cores);
384
385 /*
386 * Divide the cores accros all the core complexes
387 * Return rounded up value
388 */
389 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
390}
391
392/* Encode cache info for CPUID[8000001D] */
393static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
394 uint32_t *eax, uint32_t *ebx,
395 uint32_t *ecx, uint32_t *edx)
396{
397 uint32_t l3_cores;
398 assert(cache->size == cache->line_size * cache->associativity *
399 cache->partitions * cache->sets);
400
401 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
402 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
403
404 /* L3 is shared among multiple cores */
405 if (cache->level == 3) {
406 l3_cores = cores_in_core_complex(cs->nr_cores);
407 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
408 } else {
409 *eax |= ((cs->nr_threads - 1) << 14);
410 }
411
412 assert(cache->line_size > 0);
413 assert(cache->partitions > 0);
414 assert(cache->associativity > 0);
415 /* We don't implement fully-associative caches */
416 assert(cache->associativity < cache->sets);
417 *ebx = (cache->line_size - 1) |
418 ((cache->partitions - 1) << 12) |
419 ((cache->associativity - 1) << 22);
420
421 assert(cache->sets > 0);
422 *ecx = cache->sets - 1;
423
424 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
425 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
426 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
427}
428
ed78467a
BM		 429/* Data structure to hold the configuration info for a given core index */
430struct core_topology {
431 /* core complex id of the current core index */
432 int ccx_id;
433 /*
434 * Adjusted core index for this core in the topology
435 * This can be 0,1,2,3 with max 4 cores in a core complex
436 */
437 int core_id;
438 /* Node id for this core index */
439 int node_id;
440 /* Number of nodes in this config */
441 int num_nodes;
442};
443
444/*
445 * Build the configuration closely match the EPYC hardware. Using the EPYC
446 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
447 * right now. This could change in future.
448 * nr_cores : Total number of cores in the config
449 * core_id : Core index of the current CPU
450 * topo : Data structure to hold all the config info for this core index
451 */
452static void build_core_topology(int nr_cores, int core_id,
453 struct core_topology *topo)
454{
455 int nodes, cores_in_ccx;
456
457 /* First get the number of nodes required */
458 nodes = nodes_in_socket(nr_cores);
459
460 cores_in_ccx = cores_in_core_complex(nr_cores);
461
462 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
463 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
464 topo->core_id = core_id % cores_in_ccx;
465 topo->num_nodes = nodes;
466}
467
468/* Encode cache info for CPUID[8000001E] */
469static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
470 uint32_t *eax, uint32_t *ebx,
471 uint32_t *ecx, uint32_t *edx)
472{
473 struct core_topology topo = {0};
631be321
BM		 474 unsigned long nodes;
475 int shift;
ed78467a
BM		 476
477 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
478 *eax = cpu->apic_id;
479 /*
480 * CPUID_Fn8000001E_EBX
481 * 31:16 Reserved
482 * 15:8 Threads per core (The number of threads per core is
483 * Threads per core + 1)
484 * 7:0 Core id (see bit decoding below)
485 * SMT:
486 * 4:3 node id
487 * 2 Core complex id
488 * 1:0 Core id
489 * Non SMT:
490 * 5:4 node id
491 * 3 Core complex id
492 * 1:0 Core id
493 */
494 if (cs->nr_threads - 1) {
495 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
496 (topo.ccx_id << 2) | topo.core_id;
497 } else {
498 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
499 }
500 /*
501 * CPUID_Fn8000001E_ECX
502 * 31:11 Reserved
503 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
504 * 7:0 Node id (see bit decoding below)
505 * 2 Socket id
506 * 1:0 Node id
507 */
631be321
BM		 508 if (topo.num_nodes <= 4) {
509 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
510 topo.node_id;
511 } else {
512 /*
513 * Node id fix up. Actual hardware supports up to 4 nodes. But with
514 * more than 32 cores, we may end up with more than 4 nodes.
515 * Node id is a combination of socket id and node id. Only requirement
516 * here is that this number should be unique accross the system.
517 * Shift the socket id to accommodate more nodes. We dont expect both
518 * socket id and node id to be big number at the same time. This is not
519 * an ideal config but we need to to support it. Max nodes we can have
520 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
521 * 5 bits for nodes. Find the left most set bit to represent the total
522 * number of nodes. find_last_bit returns last set bit(0 based). Left
523 * shift(+1) the socket id to represent all the nodes.
524 */
525 nodes = topo.num_nodes - 1;
526 shift = find_last_bit(&nodes, 8);
527 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
528 topo.node_id;
529 }
ed78467a
BM		 530 *edx = 0;
531}
532
ab8f992e
BM		 533/*
534 * Definitions of the hardcoded cache entries we expose:
535 * These are legacy cache values. If there is a need to change any
536 * of these values please use builtin_x86_defs
537 */
5e891bf8
EH		 538
539/* L1 data cache: */
ab8f992e 540static CPUCacheInfo legacy_l1d_cache = {
5f00335a 541 .type = DATA_CACHE,
7e3482f8
EH		 542 .level = 1,
543 .size = 32 * KiB,
544 .self_init = 1,
545 .line_size = 64,
546 .associativity = 8,
547 .sets = 64,
548 .partitions = 1,
549 .no_invd_sharing = true,
550};
551
5e891bf8 552/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 553static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 554 .type = DATA_CACHE,
7e3482f8
EH		 555 .level = 1,
556 .size = 64 * KiB,
557 .self_init = 1,
558 .line_size = 64,
559 .associativity = 2,
560 .sets = 512,
561 .partitions = 1,
562 .lines_per_tag = 1,
563 .no_invd_sharing = true,
564};
5e891bf8
EH		 565
566/* L1 instruction cache: */
ab8f992e 567static CPUCacheInfo legacy_l1i_cache = {
5f00335a 568 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 569 .level = 1,
570 .size = 32 * KiB,
571 .self_init = 1,
572 .line_size = 64,
573 .associativity = 8,
574 .sets = 64,
575 .partitions = 1,
576 .no_invd_sharing = true,
577};
578
5e891bf8 579/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 580static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 581 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 582 .level = 1,
583 .size = 64 * KiB,
584 .self_init = 1,
585 .line_size = 64,
586 .associativity = 2,
587 .sets = 512,
588 .partitions = 1,
589 .lines_per_tag = 1,
590 .no_invd_sharing = true,
591};
5e891bf8
EH		 592
593/* Level 2 unified cache: */
ab8f992e 594static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 595 .type = UNIFIED_CACHE,
596 .level = 2,
597 .size = 4 * MiB,
598 .self_init = 1,
599 .line_size = 64,
600 .associativity = 16,
601 .sets = 4096,
602 .partitions = 1,
603 .no_invd_sharing = true,
604};
605
5e891bf8 606/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 607static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 608 .type = UNIFIED_CACHE,
609 .level = 2,
610 .size = 2 * MiB,
611 .line_size = 64,
612 .associativity = 8,
613};
614
615
5e891bf8 616/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 617static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 618 .type = UNIFIED_CACHE,
619 .level = 2,
620 .size = 512 * KiB,
621 .line_size = 64,
622 .lines_per_tag = 1,
623 .associativity = 16,
624 .sets = 512,
625 .partitions = 1,
626};
5e891bf8 627
14c985cf 628/* Level 3 unified cache: */
ab8f992e 629static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 630 .type = UNIFIED_CACHE,
631 .level = 3,
632 .size = 16 * MiB,
633 .line_size = 64,
634 .associativity = 16,
635 .sets = 16384,
636 .partitions = 1,
637 .lines_per_tag = 1,
638 .self_init = true,
639 .inclusive = true,
640 .complex_indexing = true,
641};
5e891bf8
EH		 642
643/* TLB definitions: */
644
645#define L1_DTLB_2M_ASSOC 1
646#define L1_DTLB_2M_ENTRIES 255
647#define L1_DTLB_4K_ASSOC 1
648#define L1_DTLB_4K_ENTRIES 255
649
650#define L1_ITLB_2M_ASSOC 1
651#define L1_ITLB_2M_ENTRIES 255
652#define L1_ITLB_4K_ASSOC 1
653#define L1_ITLB_4K_ENTRIES 255
654
655#define L2_DTLB_2M_ASSOC 0 /* disabled */
656#define L2_DTLB_2M_ENTRIES 0 /* disabled */
657#define L2_DTLB_4K_ASSOC 4
658#define L2_DTLB_4K_ENTRIES 512
659
660#define L2_ITLB_2M_ASSOC 0 /* disabled */
661#define L2_ITLB_2M_ENTRIES 0 /* disabled */
662#define L2_ITLB_4K_ASSOC 4
663#define L2_ITLB_4K_ENTRIES 512
664
e37a5c7f
CP		 665/* CPUID Leaf 0x14 constants: */
666#define INTEL_PT_MAX_SUBLEAF 0x1
667/*
668 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
669 * MSR can be accessed;
670 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
671 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
672 * of Intel PT MSRs across warm reset;
673 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
674 */
675#define INTEL_PT_MINIMAL_EBX 0xf
676/*
677 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
678 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
679 * accessed;
680 * bit[01]: ToPA tables can hold any number of output entries, up to the
681 * maximum allowed by the MaskOrTableOffset field of
682 * IA32_RTIT_OUTPUT_MASK_PTRS;
683 * bit[02]: Support Single-Range Output scheme;
684 */
685#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 686/* generated packets which contain IP payloads have LIP values */
687#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 688#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
689#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
690#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
691#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
692#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 693
99b88a17
IM		 694static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
695 uint32_t vendor2, uint32_t vendor3)
696{
697 int i;
698 for (i = 0; i < 4; i++) {
699 dst[i] = vendor1 >> (8 * i);
700 dst[i + 4] = vendor2 >> (8 * i);
701 dst[i + 8] = vendor3 >> (8 * i);
702 }
703 dst[CPUID_VENDOR_SZ] = '\0';
704}
705
621626ce
EH		 706#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
707#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
708 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
709#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
710 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
711 CPUID_PSE36 | CPUID_FXSR)
712#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
713#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
714 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
715 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
716 CPUID_PAE | CPUID_SEP | CPUID_APIC)
717
718#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
719 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
720 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
721 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 722 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 723 /* partly implemented:
724 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
725 /* missing:
726 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
727#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
728 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
729 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 730 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 731 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
732 /* missing:
733 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
734 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
735 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 736 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
737 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 738
739#ifdef TARGET_X86_64
740#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
741#else
742#define TCG_EXT2_X86_64_FEATURES 0
743#endif
744
745#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
746 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
747 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
748 TCG_EXT2_X86_64_FEATURES)
749#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
750 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
751#define TCG_EXT4_FEATURES 0
fe441054 752#define TCG_SVM_FEATURES CPUID_SVM_NPT
621626ce
EH		 753#define TCG_KVM_FEATURES 0
754#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 755 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
756 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 757 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
758 CPUID_7_0_EBX_ERMS)
621626ce 759 /* missing:
07929f2a 760 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 761 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 762 CPUID_7_0_EBX_RDSEED */
9ccb9784
EH		 763#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
764 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
6c7c3c21 765 CPUID_7_0_ECX_LA57)
95ea69fb 766#define TCG_7_0_EDX_FEATURES 0
303752a9 767#define TCG_APM_FEATURES 0
28b8e4d0 768#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 769#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
770 /* missing:
771 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 772
07585923
RH		 773typedef enum FeatureWordType {
774 CPUID_FEATURE_WORD,
775 MSR_FEATURE_WORD,
776} FeatureWordType;
777
5ef57876 778typedef struct FeatureWordInfo {
07585923 779 FeatureWordType type;
2d5312da
EH		 780 /* feature flags names are taken from "Intel Processor Identification and
781 * the CPUID Instruction" and AMD's "CPUID Specification".
782 * In cases of disagreement between feature naming conventions,
783 * aliases may be added.
784 */
785 const char *feat_names[32];
07585923
RH		 786 union {
787 /* If type==CPUID_FEATURE_WORD */
788 struct {
789 uint32_t eax; /* Input EAX for CPUID */
790 bool needs_ecx; /* CPUID instruction uses ECX as input */
791 uint32_t ecx; /* Input ECX value for CPUID */
792 int reg; /* output register (R_* constant) */
793 } cpuid;
794 /* If type==MSR_FEATURE_WORD */
795 struct {
796 uint32_t index;
797 struct { /*CPUID that enumerate this MSR*/
798 FeatureWord cpuid_class;
799 uint32_t cpuid_flag;
800 } cpuid_dep;
801 } msr;
802 };
37ce3522 803 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 804 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 805 uint32_t migratable_flags; /* Feature flags known to be migratable */
0d914f39
EH		 806 /* Features that shouldn't be auto-enabled by "-cpu host" */
807 uint32_t no_autoenable_flags;
5ef57876
EH		 808} FeatureWordInfo;
809
810static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 811 [FEAT_1_EDX] = {
07585923 812 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 813 .feat_names = {
814 "fpu", "vme", "de", "pse",
815 "tsc", "msr", "pae", "mce",
816 "cx8", "apic", NULL, "sep",
817 "mtrr", "pge", "mca", "cmov",
818 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
819 NULL, "ds" /* Intel dts */, "acpi", "mmx",
820 "fxsr", "sse", "sse2", "ss",
821 "ht" /* Intel htt */, "tm", "ia64", "pbe",
822 },
07585923 823 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 824 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 825 },
826 [FEAT_1_ECX] = {
07585923 827 .type = CPUID_FEATURE_WORD,
2d5312da 828 .feat_names = {
16d2fcaa 829 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 830 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 831 "tm2", "ssse3", "cid", NULL,
832 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 833 NULL, "pcid", "dca", "sse4.1",
834 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 835 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 836 "avx", "f16c", "rdrand", "hypervisor",
837 },
07585923 838 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 839 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 840 },
2d5312da
EH		 841 /* Feature names that are already defined on feature_name[] but
842 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
843 * names on feat_names below. They are copied automatically
844 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
845 */
bffd67b0 846 [FEAT_8000_0001_EDX] = {
07585923 847 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 848 .feat_names = {
849 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
850 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
851 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
852 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
853 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 854 "nx", NULL, "mmxext", NULL /* mmx */,
855 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
856 NULL, "lm", "3dnowext", "3dnow",
2d5312da 857 },
07585923 858 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 859 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 860 },
861 [FEAT_8000_0001_ECX] = {
07585923 862 .type = CPUID_FEATURE_WORD,
2d5312da 863 .feat_names = {
fc7dfd20 864 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 865 "cr8legacy", "abm", "sse4a", "misalignsse",
866 "3dnowprefetch", "osvw", "ibs", "xop",
867 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 868 "fma4", "tce", NULL, "nodeid-msr",
869 NULL, "tbm", "topoext", "perfctr-core",
870 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 871 NULL, NULL, NULL, NULL,
872 },
07585923 873 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 874 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 875 /*
876 * TOPOEXT is always allowed but can't be enabled blindly by
877 * "-cpu host", as it requires consistent cache topology info
878 * to be provided so it doesn't confuse guests.
879 */
880 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 881 },
89e49c8b 882 [FEAT_C000_0001_EDX] = {
07585923 883 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 884 .feat_names = {
885 NULL, NULL, "xstore", "xstore-en",
886 NULL, NULL, "xcrypt", "xcrypt-en",
887 "ace2", "ace2-en", "phe", "phe-en",
888 "pmm", "pmm-en", NULL, NULL,
889 NULL, NULL, NULL, NULL,
890 NULL, NULL, NULL, NULL,
891 NULL, NULL, NULL, NULL,
892 NULL, NULL, NULL, NULL,
893 },
07585923 894 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 895 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 896 },
bffd67b0 897 [FEAT_KVM] = {
07585923 898 .type = CPUID_FEATURE_WORD,
2d5312da 899 .feat_names = {
fc7dfd20
EH		 900 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
901 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 902 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
2d5312da
EH		 903 NULL, NULL, NULL, NULL,
904 NULL, NULL, NULL, NULL,
905 NULL, NULL, NULL, NULL,
906 "kvmclock-stable-bit", NULL, NULL, NULL,
907 NULL, NULL, NULL, NULL,
908 },
07585923 909 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 910 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 911 },
be777326 912 [FEAT_KVM_HINTS] = {
07585923 913 .type = CPUID_FEATURE_WORD,
be777326
WL		 914 .feat_names = {
915 "kvm-hint-dedicated", NULL, NULL, NULL,
916 NULL, NULL, NULL, NULL,
917 NULL, NULL, NULL, NULL,
918 NULL, NULL, NULL, NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 },
07585923 924 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 925 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 926 /*
927 * KVM hints aren't auto-enabled by -cpu host, they need to be
928 * explicitly enabled in the command-line.
929 */
930 .no_autoenable_flags = ~0U,
be777326 931 },
c35bd19a 932 [FEAT_HYPERV_EAX] = {
07585923 933 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 934 .feat_names = {
935 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
936 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
937 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
938 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
939 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
940 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
ba6a4fd9
VK		 941 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
942 NULL, NULL,
2d5312da
EH		 943 NULL, NULL, NULL, NULL,
944 NULL, NULL, NULL, NULL,
945 NULL, NULL, NULL, NULL,
946 NULL, NULL, NULL, NULL,
947 },
07585923 948 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
c35bd19a
EY		 949 },
950 [FEAT_HYPERV_EBX] = {
07585923 951 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 952 .feat_names = {
953 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
954 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
955 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
956 NULL /* hv_create_port */, NULL /* hv_connect_port */,
957 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
958 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
959 NULL, NULL,
960 NULL, NULL, NULL, NULL,
961 NULL, NULL, NULL, NULL,
962 NULL, NULL, NULL, NULL,
963 NULL, NULL, NULL, NULL,
964 },
07585923 965 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
c35bd19a
EY		 966 },
967 [FEAT_HYPERV_EDX] = {
07585923 968 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 969 .feat_names = {
970 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
971 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
972 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
973 NULL, NULL,
974 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
975 NULL, NULL, NULL, NULL,
976 NULL, NULL, NULL, NULL,
977 NULL, NULL, NULL, NULL,
978 NULL, NULL, NULL, NULL,
979 NULL, NULL, NULL, NULL,
980 },
07585923 981 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
c35bd19a 982 },
bffd67b0 983 [FEAT_SVM] = {
07585923 984 .type = CPUID_FEATURE_WORD,
2d5312da 985 .feat_names = {
fc7dfd20
EH		 986 "npt", "lbrv", "svm-lock", "nrip-save",
987 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
988 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 989 "pfthreshold", NULL, NULL, NULL,
990 NULL, NULL, NULL, NULL,
991 NULL, NULL, NULL, NULL,
992 NULL, NULL, NULL, NULL,
993 NULL, NULL, NULL, NULL,
994 },
07585923 995 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 996 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 997 },
998 [FEAT_7_0_EBX] = {
07585923 999 .type = CPUID_FEATURE_WORD,
2d5312da 1000 .feat_names = {
fc7dfd20 1001 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 1002 "hle", "avx2", NULL, "smep",
1003 "bmi2", "erms", "invpcid", "rtm",
1004 NULL, NULL, "mpx", NULL,
1005 "avx512f", "avx512dq", "rdseed", "adx",
1006 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 1007 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 1008 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 1009 },
07585923
RH		 1010 .cpuid = {
1011 .eax = 7,
1012 .needs_ecx = true, .ecx = 0,
1013 .reg = R_EBX,
1014 },
37ce3522 1015 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 1016 },
f74eefe0 1017 [FEAT_7_0_ECX] = {
07585923 1018 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1019 .feat_names = {
1020 NULL, "avx512vbmi", "umip", "pku",
9ccb9784 1021 NULL /* ospke */, NULL, "avx512vbmi2", NULL,
aff9e6e4
YZ		 1022 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1023 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 1024 "la57", NULL, NULL, NULL,
2d5312da 1025 NULL, NULL, "rdpid", NULL,
0da0fb06 1026 NULL, "cldemote", NULL, NULL,
2d5312da
EH		 1027 NULL, NULL, NULL, NULL,
1028 },
07585923
RH		 1029 .cpuid = {
1030 .eax = 7,
1031 .needs_ecx = true, .ecx = 0,
1032 .reg = R_ECX,
1033 },
f74eefe0
HH		 1034 .tcg_features = TCG_7_0_ECX_FEATURES,
1035 },
95ea69fb 1036 [FEAT_7_0_EDX] = {
07585923 1037 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 1038 .feat_names = {
1039 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1040 NULL, NULL, NULL, NULL,
1041 NULL, NULL, NULL, NULL,
1042 NULL, NULL, NULL, NULL,
5131dc43 1043 NULL, NULL, "pconfig", NULL,
95ea69fb 1044 NULL, NULL, NULL, NULL,
a2381f09 1045 NULL, NULL, "spec-ctrl", NULL,
3fc7c731 1046 NULL, "arch-capabilities", NULL, "ssbd",
95ea69fb 1047 },
07585923
RH		 1048 .cpuid = {
1049 .eax = 7,
1050 .needs_ecx = true, .ecx = 0,
1051 .reg = R_EDX,
1052 },
95ea69fb 1053 .tcg_features = TCG_7_0_EDX_FEATURES,
3fc7c731 1054 .unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES,
95ea69fb 1055 },
303752a9 1056 [FEAT_8000_0007_EDX] = {
07585923 1057 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1058 .feat_names = {
1059 NULL, NULL, NULL, NULL,
1060 NULL, NULL, NULL, NULL,
1061 "invtsc", NULL, NULL, NULL,
1062 NULL, NULL, NULL, NULL,
1063 NULL, NULL, NULL, NULL,
1064 NULL, NULL, NULL, NULL,
1065 NULL, NULL, NULL, NULL,
1066 NULL, NULL, NULL, NULL,
1067 },
07585923 1068 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 1069 .tcg_features = TCG_APM_FEATURES,
1070 .unmigratable_flags = CPUID_APM_INVTSC,
1071 },
1b3420e1 1072 [FEAT_8000_0008_EBX] = {
07585923 1073 .type = CPUID_FEATURE_WORD,
1b3420e1
EH		 1074 .feat_names = {
1075 NULL, NULL, NULL, NULL,
1076 NULL, NULL, NULL, NULL,
59a80a19 1077 NULL, "wbnoinvd", NULL, NULL,
1b3420e1
EH		 1078 "ibpb", NULL, NULL, NULL,
1079 NULL, NULL, NULL, NULL,
1080 NULL, NULL, NULL, NULL,
254790a9 1081 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 1082 NULL, NULL, NULL, NULL,
1083 },
07585923 1084 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 1085 .tcg_features = 0,
1086 .unmigratable_flags = 0,
1087 },
0bb0b2d2 1088 [FEAT_XSAVE] = {
07585923 1089 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1090 .feat_names = {
1091 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1092 NULL, NULL, NULL, NULL,
1093 NULL, NULL, NULL, NULL,
1094 NULL, NULL, NULL, NULL,
1095 NULL, NULL, NULL, NULL,
1096 NULL, NULL, NULL, NULL,
1097 NULL, NULL, NULL, NULL,
1098 NULL, NULL, NULL, NULL,
1099 },
07585923
RH		 1100 .cpuid = {
1101 .eax = 0xd,
1102 .needs_ecx = true, .ecx = 1,
1103 .reg = R_EAX,
1104 },
c9cfe8f9 1105 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 1106 },
28b8e4d0 1107 [FEAT_6_EAX] = {
07585923 1108 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1109 .feat_names = {
1110 NULL, NULL, "arat", NULL,
1111 NULL, NULL, NULL, NULL,
1112 NULL, NULL, NULL, NULL,
1113 NULL, NULL, NULL, NULL,
1114 NULL, NULL, NULL, NULL,
1115 NULL, NULL, NULL, NULL,
1116 NULL, NULL, NULL, NULL,
1117 NULL, NULL, NULL, NULL,
1118 },
07585923 1119 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 1120 .tcg_features = TCG_6_EAX_FEATURES,
1121 },
96193c22 1122 [FEAT_XSAVE_COMP_LO] = {
07585923
RH		 1123 .type = CPUID_FEATURE_WORD,
1124 .cpuid = {
1125 .eax = 0xD,
1126 .needs_ecx = true, .ecx = 0,
1127 .reg = R_EAX,
1128 },
96193c22 1129 .tcg_features = ~0U,
6fb2fff7
EH		 1130 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1131 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1132 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1133 XSTATE_PKRU_MASK,
96193c22
EH		 1134 },
1135 [FEAT_XSAVE_COMP_HI] = {
07585923
RH		 1136 .type = CPUID_FEATURE_WORD,
1137 .cpuid = {
1138 .eax = 0xD,
1139 .needs_ecx = true, .ecx = 0,
1140 .reg = R_EDX,
1141 },
96193c22
EH		 1142 .tcg_features = ~0U,
1143 },
d86f9636
RH		 1144 /*Below are MSR exposed features*/
1145 [FEAT_ARCH_CAPABILITIES] = {
1146 .type = MSR_FEATURE_WORD,
1147 .feat_names = {
1148 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1149 "ssb-no", NULL, NULL, NULL,
1150 NULL, NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 NULL, NULL, NULL, NULL,
1156 },
1157 .msr = {
1158 .index = MSR_IA32_ARCH_CAPABILITIES,
1159 .cpuid_dep = {
1160 FEAT_7_0_EDX,
1161 CPUID_7_0_EDX_ARCH_CAPABILITIES
1162 }
1163 },
1164 },
5ef57876
EH		 1165};
1166
8e8aba50
EH		 1167typedef struct X86RegisterInfo32 {
1168 /* Name of register */
1169 const char *name;
1170 /* QAPI enum value register */
1171 X86CPURegister32 qapi_enum;
1172} X86RegisterInfo32;
1173
1174#define REGISTER(reg) \
5d371f41 1175 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1176static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1177 REGISTER(EAX),
1178 REGISTER(ECX),
1179 REGISTER(EDX),
1180 REGISTER(EBX),
1181 REGISTER(ESP),
1182 REGISTER(EBP),
1183 REGISTER(ESI),
1184 REGISTER(EDI),
1185};
1186#undef REGISTER
1187
3f32bd21
RH		 1188typedef struct ExtSaveArea {
1189 uint32_t feature, bits;
1190 uint32_t offset, size;
1191} ExtSaveArea;
1192
1193static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 1194 [XSTATE_FP_BIT] = {
1195 /* x87 FP state component is always enabled if XSAVE is supported */
1196 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1197 /* x87 state is in the legacy region of the XSAVE area */
1198 .offset = 0,
1199 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1200 },
1201 [XSTATE_SSE_BIT] = {
1202 /* SSE state component is always enabled if XSAVE is supported */
1203 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1204 /* SSE state is in the legacy region of the XSAVE area */
1205 .offset = 0,
1206 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1207 },
cfc3b074
PB		 1208 [XSTATE_YMM_BIT] =
1209 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 1210 .offset = offsetof(X86XSaveArea, avx_state),
1211 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1212 [XSTATE_BNDREGS_BIT] =
1213 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1214 .offset = offsetof(X86XSaveArea, bndreg_state),
1215 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1216 [XSTATE_BNDCSR_BIT] =
1217 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1218 .offset = offsetof(X86XSaveArea, bndcsr_state),
1219 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1220 [XSTATE_OPMASK_BIT] =
1221 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1222 .offset = offsetof(X86XSaveArea, opmask_state),
1223 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1224 [XSTATE_ZMM_Hi256_BIT] =
1225 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1226 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1227 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1228 [XSTATE_Hi16_ZMM_BIT] =
1229 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1230 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1231 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1232 [XSTATE_PKRU_BIT] =
1233 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 1234 .offset = offsetof(X86XSaveArea, pkru_state),
1235 .size = sizeof(XSavePKRU) },
2560f19f 1236};
8e8aba50 1237
1fda6198
EH		 1238static uint32_t xsave_area_size(uint64_t mask)
1239{
1240 int i;
e3c9022b 1241 uint64_t ret = 0;
1fda6198 1242
e3c9022b 1243 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1244 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1245 if ((mask >> i) & 1) {
1246 ret = MAX(ret, esa->offset + esa->size);
1247 }
1248 }
1249 return ret;
1250}
1251
d6dcc558
SAGDR		 1252static inline bool accel_uses_host_cpuid(void)
1253{
1254 return kvm_enabled() || hvf_enabled();
1255}
1256
96193c22
EH		 1257static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1258{
1259 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1260 cpu->env.features[FEAT_XSAVE_COMP_LO];
1261}
1262
8b4beddc
EH		 1263const char *get_register_name_32(unsigned int reg)
1264{
31ccdde2 1265 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1266 return NULL;
1267 }
8e8aba50 1268 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1269}
1270
84f1b92f
EH		 1271/*
1272 * Returns the set of feature flags that are supported and migratable by
1273 * QEMU, for a given FeatureWord.
1274 */
1275static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1276{
1277 FeatureWordInfo *wi = &feature_word_info[w];
1278 uint32_t r = 0;
1279 int i;
1280
1281 for (i = 0; i < 32; i++) {
1282 uint32_t f = 1U << i;
6fb2fff7
EH		 1283
1284 /* If the feature name is known, it is implicitly considered migratable,
1285 * unless it is explicitly set in unmigratable_flags */
1286 if ((wi->migratable_flags & f) ||
1287 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1288 r |= f;
84f1b92f 1289 }
84f1b92f
EH		 1290 }
1291 return r;
1292}
1293
bb44e0d1
JK		 1294void host_cpuid(uint32_t function, uint32_t count,
1295 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1296{
a1fd24af
AL		 1297 uint32_t vec[4];
1298
1299#ifdef __x86_64__
1300 asm volatile("cpuid"
1301 : "=a"(vec[0]), "=b"(vec[1]),
1302 "=c"(vec[2]), "=d"(vec[3])
1303 : "0"(function), "c"(count) : "cc");
c1f41226 1304#elif defined(__i386__)
a1fd24af
AL		 1305 asm volatile("pusha \n\t"
1306 "cpuid \n\t"
1307 "mov %%eax, 0(%2) \n\t"
1308 "mov %%ebx, 4(%2) \n\t"
1309 "mov %%ecx, 8(%2) \n\t"
1310 "mov %%edx, 12(%2) \n\t"
1311 "popa"
1312 : : "a"(function), "c"(count), "S"(vec)
1313 : "memory", "cc");
c1f41226
EH		 1314#else
1315 abort();
a1fd24af
AL		 1316#endif
1317
bdde476a 1318 if (eax)
a1fd24af 1319 *eax = vec[0];
bdde476a 1320 if (ebx)
a1fd24af 1321 *ebx = vec[1];
bdde476a 1322 if (ecx)
a1fd24af 1323 *ecx = vec[2];
bdde476a 1324 if (edx)
a1fd24af 1325 *edx = vec[3];
bdde476a 1326}
c6dc6f63 1327
20271d48
EH		 1328void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1329{
1330 uint32_t eax, ebx, ecx, edx;
1331
1332 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1333 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1334
1335 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1336 if (family) {
1337 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1338 }
1339 if (model) {
1340 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1341 }
1342 if (stepping) {
1343 *stepping = eax & 0x0F;
1344 }
1345}
1346
d940ee9b
EH		 1347/* CPU class name definitions: */
1348
d940ee9b
EH		 1349/* Return type name for a given CPU model name
1350 * Caller is responsible for freeing the returned string.
1351 */
1352static char *x86_cpu_type_name(const char *model_name)
1353{
1354 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1355}
1356
500050d1
AF		 1357static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1358{
d940ee9b 1359 ObjectClass *oc;
99193d8f 1360 char *typename = x86_cpu_type_name(cpu_model);
d940ee9b
EH		 1361 oc = object_class_by_name(typename);
1362 g_free(typename);
1363 return oc;
500050d1
AF		 1364}
1365
104494ea
IM		 1366static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1367{
1368 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1369 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1370 return g_strndup(class_name,
1371 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1372}
1373
d940ee9b 1374struct X86CPUDefinition {
c6dc6f63
AP		 1375 const char *name;
1376 uint32_t level;
90e4b0c3 1377 uint32_t xlevel;
99b88a17
IM		 1378 /* vendor is zero-terminated, 12 character ASCII string */
1379 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1380 int family;
1381 int model;
1382 int stepping;
0514ef2f 1383 FeatureWordArray features;
807e9869 1384 const char *model_id;
6aaeb054 1385 CPUCaches *cache_info;
d940ee9b 1386};
c6dc6f63 1387
fe52acd2 1388static CPUCaches epyc_cache_info = {
a9f27ea9 1389 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1390 .type = DATA_CACHE,
fe52acd2
BM		 1391 .level = 1,
1392 .size = 32 * KiB,
1393 .line_size = 64,
1394 .associativity = 8,
1395 .partitions = 1,
1396 .sets = 64,
1397 .lines_per_tag = 1,
1398 .self_init = 1,
1399 .no_invd_sharing = true,
1400 },
a9f27ea9 1401 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1402 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1403 .level = 1,
1404 .size = 64 * KiB,
1405 .line_size = 64,
1406 .associativity = 4,
1407 .partitions = 1,
1408 .sets = 256,
1409 .lines_per_tag = 1,
1410 .self_init = 1,
1411 .no_invd_sharing = true,
1412 },
a9f27ea9 1413 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1414 .type = UNIFIED_CACHE,
1415 .level = 2,
1416 .size = 512 * KiB,
1417 .line_size = 64,
1418 .associativity = 8,
1419 .partitions = 1,
1420 .sets = 1024,
1421 .lines_per_tag = 1,
1422 },
a9f27ea9 1423 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1424 .type = UNIFIED_CACHE,
1425 .level = 3,
1426 .size = 8 * MiB,
1427 .line_size = 64,
1428 .associativity = 16,
1429 .partitions = 1,
1430 .sets = 8192,
1431 .lines_per_tag = 1,
1432 .self_init = true,
1433 .inclusive = true,
1434 .complex_indexing = true,
1435 },
1436};
1437
9576de75 1438static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1439 {
1440 .name = "qemu64",
3046bb5d 1441 .level = 0xd,
99b88a17 1442 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 1443 .family = 6,
f8e6a11a 1444 .model = 6,
c6dc6f63 1445 .stepping = 3,
0514ef2f 1446 .features[FEAT_1_EDX] =
27861ecc 1447 PPRO_FEATURES |
c6dc6f63 1448 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1449 CPUID_PSE36,
0514ef2f 1450 .features[FEAT_1_ECX] =
6aa91e4a 1451 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1452 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1453 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1454 .features[FEAT_8000_0001_ECX] =
71195672 1455 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1456 .xlevel = 0x8000000A,
9cf2cc3d 1457 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1458 },
1459 {
1460 .name = "phenom",
1461 .level = 5,
99b88a17 1462 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1463 .family = 16,
1464 .model = 2,
1465 .stepping = 3,
b9fc20bc 1466 /* Missing: CPUID_HT */
0514ef2f 1467 .features[FEAT_1_EDX] =
27861ecc 1468 PPRO_FEATURES |
c6dc6f63 1469 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1470 CPUID_PSE36 | CPUID_VME,
0514ef2f 1471 .features[FEAT_1_ECX] =
27861ecc 1472 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1473 CPUID_EXT_POPCNT,
0514ef2f 1474 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1475 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1476 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1477 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1478 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1479 CPUID_EXT3_CR8LEG,
1480 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1481 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1482 .features[FEAT_8000_0001_ECX] =
27861ecc 1483 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1484 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1485 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1486 .features[FEAT_SVM] =
b9fc20bc 1487 CPUID_SVM_NPT,
c6dc6f63
AP		 1488 .xlevel = 0x8000001A,
1489 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1490 },
1491 {
1492 .name = "core2duo",
1493 .level = 10,
99b88a17 1494 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1495 .family = 6,
1496 .model = 15,
1497 .stepping = 11,
b9fc20bc 1498 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1499 .features[FEAT_1_EDX] =
27861ecc 1500 PPRO_FEATURES |
c6dc6f63 1501 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1502 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1503 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1504 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1505 .features[FEAT_1_ECX] =
27861ecc 1506 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1507 CPUID_EXT_CX16,
0514ef2f 1508 .features[FEAT_8000_0001_EDX] =
27861ecc 1509 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1510 .features[FEAT_8000_0001_ECX] =
27861ecc 1511 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 1512 .xlevel = 0x80000008,
1513 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1514 },
1515 {
1516 .name = "kvm64",
3046bb5d 1517 .level = 0xd,
99b88a17 1518 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1519 .family = 15,
1520 .model = 6,
1521 .stepping = 1,
b3a4f0b1 1522 /* Missing: CPUID_HT */
0514ef2f 1523 .features[FEAT_1_EDX] =
b3a4f0b1 1524 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1525 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1526 CPUID_PSE36,
1527 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1528 .features[FEAT_1_ECX] =
27861ecc 1529 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1530 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1531 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1532 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1533 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1534 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1535 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1536 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1537 .features[FEAT_8000_0001_ECX] =
27861ecc 1538 0,
c6dc6f63
AP		 1539 .xlevel = 0x80000008,
1540 .model_id = "Common KVM processor"
1541 },
c6dc6f63
AP		 1542 {
1543 .name = "qemu32",
1544 .level = 4,
99b88a17 1545 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1546 .family = 6,
f8e6a11a 1547 .model = 6,
c6dc6f63 1548 .stepping = 3,
0514ef2f 1549 .features[FEAT_1_EDX] =
27861ecc 1550 PPRO_FEATURES,
0514ef2f 1551 .features[FEAT_1_ECX] =
6aa91e4a 1552 CPUID_EXT_SSE3,
58012d66 1553 .xlevel = 0x80000004,
9cf2cc3d 1554 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1555 },
eafaf1e5
AP		 1556 {
1557 .name = "kvm32",
1558 .level = 5,
99b88a17 1559 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1560 .family = 15,
1561 .model = 6,
1562 .stepping = 1,
0514ef2f 1563 .features[FEAT_1_EDX] =
b3a4f0b1 1564 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1565 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1566 .features[FEAT_1_ECX] =
27861ecc 1567 CPUID_EXT_SSE3,
0514ef2f 1568 .features[FEAT_8000_0001_ECX] =
27861ecc 1569 0,
eafaf1e5
AP		 1570 .xlevel = 0x80000008,
1571 .model_id = "Common 32-bit KVM processor"
1572 },
c6dc6f63
AP		 1573 {
1574 .name = "coreduo",
1575 .level = 10,
99b88a17 1576 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1577 .family = 6,
1578 .model = 14,
1579 .stepping = 8,
b9fc20bc 1580 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1581 .features[FEAT_1_EDX] =
27861ecc 1582 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1583 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1584 CPUID_SS,
1585 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1586 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1587 .features[FEAT_1_ECX] =
e93abc14 1588 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1589 .features[FEAT_8000_0001_EDX] =
27861ecc 1590 CPUID_EXT2_NX,
c6dc6f63
AP		 1591 .xlevel = 0x80000008,
1592 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1593 },
1594 {
1595 .name = "486",
58012d66 1596 .level = 1,
99b88a17 1597 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1598 .family = 4,
b2a856d9 1599 .model = 8,
c6dc6f63 1600 .stepping = 0,
0514ef2f 1601 .features[FEAT_1_EDX] =
27861ecc 1602 I486_FEATURES,
c6dc6f63 1603 .xlevel = 0,
807e9869 1604 .model_id = "",
c6dc6f63
AP		 1605 },
1606 {
1607 .name = "pentium",
1608 .level = 1,
99b88a17 1609 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1610 .family = 5,
1611 .model = 4,
1612 .stepping = 3,
0514ef2f 1613 .features[FEAT_1_EDX] =
27861ecc 1614 PENTIUM_FEATURES,
c6dc6f63 1615 .xlevel = 0,
807e9869 1616 .model_id = "",
c6dc6f63
AP		 1617 },
1618 {
1619 .name = "pentium2",
1620 .level = 2,
99b88a17 1621 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1622 .family = 6,
1623 .model = 5,
1624 .stepping = 2,
0514ef2f 1625 .features[FEAT_1_EDX] =
27861ecc 1626 PENTIUM2_FEATURES,
c6dc6f63 1627 .xlevel = 0,
807e9869 1628 .model_id = "",
c6dc6f63
AP		 1629 },
1630 {
1631 .name = "pentium3",
3046bb5d 1632 .level = 3,
99b88a17 1633 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1634 .family = 6,
1635 .model = 7,
1636 .stepping = 3,
0514ef2f 1637 .features[FEAT_1_EDX] =
27861ecc 1638 PENTIUM3_FEATURES,
c6dc6f63 1639 .xlevel = 0,
807e9869 1640 .model_id = "",
c6dc6f63
AP		 1641 },
1642 {
1643 .name = "athlon",
1644 .level = 2,
99b88a17 1645 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1646 .family = 6,
1647 .model = 2,
1648 .stepping = 3,
0514ef2f 1649 .features[FEAT_1_EDX] =
27861ecc 1650 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 1651 CPUID_MCA,
0514ef2f 1652 .features[FEAT_8000_0001_EDX] =
60032ac0 1653 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 1654 .xlevel = 0x80000008,
9cf2cc3d 1655 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1656 },
1657 {
1658 .name = "n270",
3046bb5d 1659 .level = 10,
99b88a17 1660 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1661 .family = 6,
1662 .model = 28,
1663 .stepping = 2,
b9fc20bc 1664 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1665 .features[FEAT_1_EDX] =
27861ecc 1666 PPRO_FEATURES |
b9fc20bc
EH		 1667 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1668 CPUID_ACPI | CPUID_SS,
c6dc6f63 1669 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1670 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1671 * CPUID_EXT_XTPR */
0514ef2f 1672 .features[FEAT_1_ECX] =
27861ecc 1673 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1674 CPUID_EXT_MOVBE,
0514ef2f 1675 .features[FEAT_8000_0001_EDX] =
60032ac0 1676 CPUID_EXT2_NX,
0514ef2f 1677 .features[FEAT_8000_0001_ECX] =
27861ecc 1678 CPUID_EXT3_LAHF_LM,
3046bb5d 1679 .xlevel = 0x80000008,
c6dc6f63
AP		 1680 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1681 },
3eca4642
EH		 1682 {
1683 .name = "Conroe",
3046bb5d 1684 .level = 10,
99b88a17 1685 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1686 .family = 6,
ffce9ebb 1687 .model = 15,
3eca4642 1688 .stepping = 3,
0514ef2f 1689 .features[FEAT_1_EDX] =
b3a4f0b1 1690 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1691 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1692 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1693 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1694 CPUID_DE | CPUID_FP87,
0514ef2f 1695 .features[FEAT_1_ECX] =
27861ecc 1696 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1697 .features[FEAT_8000_0001_EDX] =
27861ecc 1698 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1699 .features[FEAT_8000_0001_ECX] =
27861ecc 1700 CPUID_EXT3_LAHF_LM,
3046bb5d 1701 .xlevel = 0x80000008,
3eca4642
EH		 1702 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1703 },
1704 {
1705 .name = "Penryn",
3046bb5d 1706 .level = 10,
99b88a17 1707 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1708 .family = 6,
ffce9ebb 1709 .model = 23,
3eca4642 1710 .stepping = 3,
0514ef2f 1711 .features[FEAT_1_EDX] =
b3a4f0b1 1712 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1713 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1714 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1715 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1716 CPUID_DE | CPUID_FP87,
0514ef2f 1717 .features[FEAT_1_ECX] =
27861ecc 1718 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1719 CPUID_EXT_SSE3,
0514ef2f 1720 .features[FEAT_8000_0001_EDX] =
27861ecc 1721 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1722 .features[FEAT_8000_0001_ECX] =
27861ecc 1723 CPUID_EXT3_LAHF_LM,
3046bb5d 1724 .xlevel = 0x80000008,
3eca4642
EH		 1725 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1726 },
1727 {
1728 .name = "Nehalem",
3046bb5d 1729 .level = 11,
99b88a17 1730 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1731 .family = 6,
ffce9ebb 1732 .model = 26,
3eca4642 1733 .stepping = 3,
0514ef2f 1734 .features[FEAT_1_EDX] =
b3a4f0b1 1735 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1736 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1737 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1738 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1739 CPUID_DE | CPUID_FP87,
0514ef2f 1740 .features[FEAT_1_ECX] =
27861ecc 1741 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1742 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1743 .features[FEAT_8000_0001_EDX] =
27861ecc 1744 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1745 .features[FEAT_8000_0001_ECX] =
27861ecc 1746 CPUID_EXT3_LAHF_LM,
3046bb5d 1747 .xlevel = 0x80000008,
3eca4642
EH		 1748 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1749 },
ac96c413
EH		 1750 {
1751 .name = "Nehalem-IBRS",
1752 .level = 11,
1753 .vendor = CPUID_VENDOR_INTEL,
1754 .family = 6,
1755 .model = 26,
1756 .stepping = 3,
1757 .features[FEAT_1_EDX] =
1758 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1759 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1760 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1761 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1762 CPUID_DE | CPUID_FP87,
1763 .features[FEAT_1_ECX] =
1764 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1765 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1766 .features[FEAT_7_0_EDX] =
1767 CPUID_7_0_EDX_SPEC_CTRL,
1768 .features[FEAT_8000_0001_EDX] =
1769 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1770 .features[FEAT_8000_0001_ECX] =
1771 CPUID_EXT3_LAHF_LM,
1772 .xlevel = 0x80000008,
1773 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1774 },
3eca4642
EH		 1775 {
1776 .name = "Westmere",
1777 .level = 11,
99b88a17 1778 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1779 .family = 6,
1780 .model = 44,
1781 .stepping = 1,
0514ef2f 1782 .features[FEAT_1_EDX] =
b3a4f0b1 1783 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1784 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1785 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1786 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1787 CPUID_DE | CPUID_FP87,
0514ef2f 1788 .features[FEAT_1_ECX] =
27861ecc 1789 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1790 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1791 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1792 .features[FEAT_8000_0001_EDX] =
27861ecc 1793 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1794 .features[FEAT_8000_0001_ECX] =
27861ecc 1795 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1796 .features[FEAT_6_EAX] =
1797 CPUID_6_EAX_ARAT,
3046bb5d 1798 .xlevel = 0x80000008,
3eca4642
EH		 1799 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1800 },
ac96c413
EH		 1801 {
1802 .name = "Westmere-IBRS",
1803 .level = 11,
1804 .vendor = CPUID_VENDOR_INTEL,
1805 .family = 6,
1806 .model = 44,
1807 .stepping = 1,
1808 .features[FEAT_1_EDX] =
1809 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1810 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1811 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1812 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1813 CPUID_DE | CPUID_FP87,
1814 .features[FEAT_1_ECX] =
1815 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1816 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1817 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1818 .features[FEAT_8000_0001_EDX] =
1819 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1820 .features[FEAT_8000_0001_ECX] =
1821 CPUID_EXT3_LAHF_LM,
1822 .features[FEAT_7_0_EDX] =
1823 CPUID_7_0_EDX_SPEC_CTRL,
1824 .features[FEAT_6_EAX] =
1825 CPUID_6_EAX_ARAT,
1826 .xlevel = 0x80000008,
1827 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1828 },
3eca4642
EH		 1829 {
1830 .name = "SandyBridge",
1831 .level = 0xd,
99b88a17 1832 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1833 .family = 6,
1834 .model = 42,
1835 .stepping = 1,
0514ef2f 1836 .features[FEAT_1_EDX] =
b3a4f0b1 1837 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1838 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1839 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1840 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1841 CPUID_DE | CPUID_FP87,
0514ef2f 1842 .features[FEAT_1_ECX] =
27861ecc 1843 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1844 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1845 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1846 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1847 CPUID_EXT_SSE3,
0514ef2f 1848 .features[FEAT_8000_0001_EDX] =
27861ecc 1849 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1850 CPUID_EXT2_SYSCALL,
0514ef2f 1851 .features[FEAT_8000_0001_ECX] =
27861ecc 1852 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1853 .features[FEAT_XSAVE] =
1854 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1855 .features[FEAT_6_EAX] =
1856 CPUID_6_EAX_ARAT,
3046bb5d 1857 .xlevel = 0x80000008,
3eca4642
EH		 1858 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1859 },
ac96c413
EH		 1860 {
1861 .name = "SandyBridge-IBRS",
1862 .level = 0xd,
1863 .vendor = CPUID_VENDOR_INTEL,
1864 .family = 6,
1865 .model = 42,
1866 .stepping = 1,
1867 .features[FEAT_1_EDX] =
1868 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1869 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1870 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1871 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1872 CPUID_DE | CPUID_FP87,
1873 .features[FEAT_1_ECX] =
1874 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1875 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1876 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1877 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1878 CPUID_EXT_SSE3,
1879 .features[FEAT_8000_0001_EDX] =
1880 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1881 CPUID_EXT2_SYSCALL,
1882 .features[FEAT_8000_0001_ECX] =
1883 CPUID_EXT3_LAHF_LM,
1884 .features[FEAT_7_0_EDX] =
1885 CPUID_7_0_EDX_SPEC_CTRL,
1886 .features[FEAT_XSAVE] =
1887 CPUID_XSAVE_XSAVEOPT,
1888 .features[FEAT_6_EAX] =
1889 CPUID_6_EAX_ARAT,
1890 .xlevel = 0x80000008,
1891 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1892 },
2f9ac42a
PB		 1893 {
1894 .name = "IvyBridge",
1895 .level = 0xd,
1896 .vendor = CPUID_VENDOR_INTEL,
1897 .family = 6,
1898 .model = 58,
1899 .stepping = 9,
1900 .features[FEAT_1_EDX] =
1901 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1902 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1903 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1904 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1905 CPUID_DE | CPUID_FP87,
1906 .features[FEAT_1_ECX] =
1907 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1908 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1909 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1910 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1911 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1912 .features[FEAT_7_0_EBX] =
1913 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1914 CPUID_7_0_EBX_ERMS,
1915 .features[FEAT_8000_0001_EDX] =
1916 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1917 CPUID_EXT2_SYSCALL,
1918 .features[FEAT_8000_0001_ECX] =
1919 CPUID_EXT3_LAHF_LM,
1920 .features[FEAT_XSAVE] =
1921 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1922 .features[FEAT_6_EAX] =
1923 CPUID_6_EAX_ARAT,
3046bb5d 1924 .xlevel = 0x80000008,
2f9ac42a
PB		 1925 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1926 },
ac96c413
EH		 1927 {
1928 .name = "IvyBridge-IBRS",
1929 .level = 0xd,
1930 .vendor = CPUID_VENDOR_INTEL,
1931 .family = 6,
1932 .model = 58,
1933 .stepping = 9,
1934 .features[FEAT_1_EDX] =
1935 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1936 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1937 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1938 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1939 CPUID_DE | CPUID_FP87,
1940 .features[FEAT_1_ECX] =
1941 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1942 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1943 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1944 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1945 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1946 .features[FEAT_7_0_EBX] =
1947 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1948 CPUID_7_0_EBX_ERMS,
1949 .features[FEAT_8000_0001_EDX] =
1950 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1951 CPUID_EXT2_SYSCALL,
1952 .features[FEAT_8000_0001_ECX] =
1953 CPUID_EXT3_LAHF_LM,
1954 .features[FEAT_7_0_EDX] =
1955 CPUID_7_0_EDX_SPEC_CTRL,
1956 .features[FEAT_XSAVE] =
1957 CPUID_XSAVE_XSAVEOPT,
1958 .features[FEAT_6_EAX] =
1959 CPUID_6_EAX_ARAT,
1960 .xlevel = 0x80000008,
1961 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
1962 },
37507094 1963 {
a356850b
EH		 1964 .name = "Haswell-noTSX",
1965 .level = 0xd,
1966 .vendor = CPUID_VENDOR_INTEL,
1967 .family = 6,
1968 .model = 60,
1969 .stepping = 1,
1970 .features[FEAT_1_EDX] =
1971 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1972 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1973 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1974 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1975 CPUID_DE | CPUID_FP87,
1976 .features[FEAT_1_ECX] =
1977 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1978 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1979 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1980 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1981 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1982 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1983 .features[FEAT_8000_0001_EDX] =
1984 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1985 CPUID_EXT2_SYSCALL,
1986 .features[FEAT_8000_0001_ECX] =
becb6667 1987 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1988 .features[FEAT_7_0_EBX] =
1989 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1990 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1991 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1992 .features[FEAT_XSAVE] =
1993 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1994 .features[FEAT_6_EAX] =
1995 CPUID_6_EAX_ARAT,
3046bb5d 1996 .xlevel = 0x80000008,
a356850b 1997 .model_id = "Intel Core Processor (Haswell, no TSX)",
ac96c413
EH		 1998 },
1999 {
2000 .name = "Haswell-noTSX-IBRS",
2001 .level = 0xd,
2002 .vendor = CPUID_VENDOR_INTEL,
2003 .family = 6,
2004 .model = 60,
2005 .stepping = 1,
2006 .features[FEAT_1_EDX] =
2007 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2008 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2009 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2010 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2011 CPUID_DE | CPUID_FP87,
2012 .features[FEAT_1_ECX] =
2013 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2014 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2015 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2016 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2017 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2018 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2019 .features[FEAT_8000_0001_EDX] =
2020 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2021 CPUID_EXT2_SYSCALL,
2022 .features[FEAT_8000_0001_ECX] =
2023 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2024 .features[FEAT_7_0_EDX] =
2025 CPUID_7_0_EDX_SPEC_CTRL,
2026 .features[FEAT_7_0_EBX] =
2027 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2028 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2029 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2030 .features[FEAT_XSAVE] =
2031 CPUID_XSAVE_XSAVEOPT,
2032 .features[FEAT_6_EAX] =
2033 CPUID_6_EAX_ARAT,
2034 .xlevel = 0x80000008,
2035 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
2036 },
2037 {
37507094
EH		 2038 .name = "Haswell",
2039 .level = 0xd,
99b88a17 2040 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2041 .family = 6,
2042 .model = 60,
ec56a4a7 2043 .stepping = 4,
0514ef2f 2044 .features[FEAT_1_EDX] =
b3a4f0b1 2045 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2046 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2047 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2048 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2049 CPUID_DE | CPUID_FP87,
0514ef2f 2050 .features[FEAT_1_ECX] =
27861ecc 2051 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2052 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2053 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2054 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2055 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2056 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2057 .features[FEAT_8000_0001_EDX] =
27861ecc 2058 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2059 CPUID_EXT2_SYSCALL,
0514ef2f 2060 .features[FEAT_8000_0001_ECX] =
becb6667 2061 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2062 .features[FEAT_7_0_EBX] =
27861ecc 2063 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2064 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2065 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2066 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2067 .features[FEAT_XSAVE] =
2068 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2069 .features[FEAT_6_EAX] =
2070 CPUID_6_EAX_ARAT,
3046bb5d 2071 .xlevel = 0x80000008,
37507094
EH		 2072 .model_id = "Intel Core Processor (Haswell)",
2073 },
ac96c413
EH		 2074 {
2075 .name = "Haswell-IBRS",
2076 .level = 0xd,
2077 .vendor = CPUID_VENDOR_INTEL,
2078 .family = 6,
2079 .model = 60,
2080 .stepping = 4,
2081 .features[FEAT_1_EDX] =
2082 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2083 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2084 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2085 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2086 CPUID_DE | CPUID_FP87,
2087 .features[FEAT_1_ECX] =
2088 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2089 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2090 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2091 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2092 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2093 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2094 .features[FEAT_8000_0001_EDX] =
2095 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2096 CPUID_EXT2_SYSCALL,
2097 .features[FEAT_8000_0001_ECX] =
2098 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2099 .features[FEAT_7_0_EDX] =
2100 CPUID_7_0_EDX_SPEC_CTRL,
2101 .features[FEAT_7_0_EBX] =
2102 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2103 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2104 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2105 CPUID_7_0_EBX_RTM,
2106 .features[FEAT_XSAVE] =
2107 CPUID_XSAVE_XSAVEOPT,
2108 .features[FEAT_6_EAX] =
2109 CPUID_6_EAX_ARAT,
2110 .xlevel = 0x80000008,
2111 .model_id = "Intel Core Processor (Haswell, IBRS)",
2112 },
a356850b
EH		 2113 {
2114 .name = "Broadwell-noTSX",
2115 .level = 0xd,
2116 .vendor = CPUID_VENDOR_INTEL,
2117 .family = 6,
2118 .model = 61,
2119 .stepping = 2,
2120 .features[FEAT_1_EDX] =
2121 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2122 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2123 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2124 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2125 CPUID_DE | CPUID_FP87,
2126 .features[FEAT_1_ECX] =
2127 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2128 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2129 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2130 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2131 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2132 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2133 .features[FEAT_8000_0001_EDX] =
2134 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2135 CPUID_EXT2_SYSCALL,
2136 .features[FEAT_8000_0001_ECX] =
becb6667 2137 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 2138 .features[FEAT_7_0_EBX] =
2139 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2140 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2141 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2142 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2143 CPUID_7_0_EBX_SMAP,
2144 .features[FEAT_XSAVE] =
2145 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2146 .features[FEAT_6_EAX] =
2147 CPUID_6_EAX_ARAT,
3046bb5d 2148 .xlevel = 0x80000008,
a356850b
EH		 2149 .model_id = "Intel Core Processor (Broadwell, no TSX)",
2150 },
ac96c413
EH		 2151 {
2152 .name = "Broadwell-noTSX-IBRS",
2153 .level = 0xd,
2154 .vendor = CPUID_VENDOR_INTEL,
2155 .family = 6,
2156 .model = 61,
2157 .stepping = 2,
2158 .features[FEAT_1_EDX] =
2159 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2160 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2161 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2162 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2163 CPUID_DE | CPUID_FP87,
2164 .features[FEAT_1_ECX] =
2165 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2166 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2167 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2168 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2169 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2170 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2171 .features[FEAT_8000_0001_EDX] =
2172 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2173 CPUID_EXT2_SYSCALL,
2174 .features[FEAT_8000_0001_ECX] =
2175 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2176 .features[FEAT_7_0_EDX] =
2177 CPUID_7_0_EDX_SPEC_CTRL,
2178 .features[FEAT_7_0_EBX] =
2179 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2180 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2181 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2182 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2183 CPUID_7_0_EBX_SMAP,
2184 .features[FEAT_XSAVE] =
2185 CPUID_XSAVE_XSAVEOPT,
2186 .features[FEAT_6_EAX] =
2187 CPUID_6_EAX_ARAT,
2188 .xlevel = 0x80000008,
2189 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
2190 },
ece01354
EH		 2191 {
2192 .name = "Broadwell",
2193 .level = 0xd,
2194 .vendor = CPUID_VENDOR_INTEL,
2195 .family = 6,
2196 .model = 61,
2197 .stepping = 2,
2198 .features[FEAT_1_EDX] =
b3a4f0b1 2199 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2200 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2201 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2202 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2203 CPUID_DE | CPUID_FP87,
2204 .features[FEAT_1_ECX] =
2205 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2206 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2207 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2208 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2209 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2210 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2211 .features[FEAT_8000_0001_EDX] =
2212 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2213 CPUID_EXT2_SYSCALL,
2214 .features[FEAT_8000_0001_ECX] =
becb6667 2215 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2216 .features[FEAT_7_0_EBX] =
2217 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2218 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2219 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2220 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2221 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2222 .features[FEAT_XSAVE] =
2223 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2224 .features[FEAT_6_EAX] =
2225 CPUID_6_EAX_ARAT,
3046bb5d 2226 .xlevel = 0x80000008,
ece01354
EH		 2227 .model_id = "Intel Core Processor (Broadwell)",
2228 },
ac96c413
EH		 2229 {
2230 .name = "Broadwell-IBRS",
2231 .level = 0xd,
2232 .vendor = CPUID_VENDOR_INTEL,
2233 .family = 6,
2234 .model = 61,
2235 .stepping = 2,
2236 .features[FEAT_1_EDX] =
2237 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2238 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2239 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2240 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2241 CPUID_DE | CPUID_FP87,
2242 .features[FEAT_1_ECX] =
2243 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2244 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2245 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2246 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2247 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2248 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2249 .features[FEAT_8000_0001_EDX] =
2250 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2251 CPUID_EXT2_SYSCALL,
2252 .features[FEAT_8000_0001_ECX] =
2253 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2254 .features[FEAT_7_0_EDX] =
2255 CPUID_7_0_EDX_SPEC_CTRL,
2256 .features[FEAT_7_0_EBX] =
2257 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2258 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2259 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2260 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2261 CPUID_7_0_EBX_SMAP,
2262 .features[FEAT_XSAVE] =
2263 CPUID_XSAVE_XSAVEOPT,
2264 .features[FEAT_6_EAX] =
2265 CPUID_6_EAX_ARAT,
2266 .xlevel = 0x80000008,
2267 .model_id = "Intel Core Processor (Broadwell, IBRS)",
2268 },
f6f949e9
EH		 2269 {
2270 .name = "Skylake-Client",
2271 .level = 0xd,
2272 .vendor = CPUID_VENDOR_INTEL,
2273 .family = 6,
2274 .model = 94,
2275 .stepping = 3,
2276 .features[FEAT_1_EDX] =
2277 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2278 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2279 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2280 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2281 CPUID_DE | CPUID_FP87,
2282 .features[FEAT_1_ECX] =
2283 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2284 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2285 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2286 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2287 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2288 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2289 .features[FEAT_8000_0001_EDX] =
2290 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2291 CPUID_EXT2_SYSCALL,
2292 .features[FEAT_8000_0001_ECX] =
2293 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2294 .features[FEAT_7_0_EBX] =
2295 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2296 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2297 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2298 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2299 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
2300 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 2301 * including v4.1 to v4.12).
f6f949e9
EH		 2302 * KVM doesn't yet expose any XSAVES state save component,
2303 * and the only one defined in Skylake (processor tracing)
2304 * probably will block migration anyway.
2305 */
2306 .features[FEAT_XSAVE] =
2307 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2308 CPUID_XSAVE_XGETBV1,
2309 .features[FEAT_6_EAX] =
2310 CPUID_6_EAX_ARAT,
2311 .xlevel = 0x80000008,
2312 .model_id = "Intel Core Processor (Skylake)",
2313 },
ac96c413
EH		 2314 {
2315 .name = "Skylake-Client-IBRS",
2316 .level = 0xd,
2317 .vendor = CPUID_VENDOR_INTEL,
2318 .family = 6,
2319 .model = 94,
2320 .stepping = 3,
2321 .features[FEAT_1_EDX] =
2322 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2323 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2324 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2325 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2326 CPUID_DE | CPUID_FP87,
2327 .features[FEAT_1_ECX] =
2328 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2329 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2330 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2331 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2332 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2333 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2334 .features[FEAT_8000_0001_EDX] =
2335 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2336 CPUID_EXT2_SYSCALL,
2337 .features[FEAT_8000_0001_ECX] =
2338 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2339 .features[FEAT_7_0_EDX] =
2340 CPUID_7_0_EDX_SPEC_CTRL,
2341 .features[FEAT_7_0_EBX] =
2342 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2343 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2344 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2345 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2346 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
2347 /* Missing: XSAVES (not supported by some Linux versions,
2348 * including v4.1 to v4.12).
2349 * KVM doesn't yet expose any XSAVES state save component,
2350 * and the only one defined in Skylake (processor tracing)
2351 * probably will block migration anyway.
2352 */
2353 .features[FEAT_XSAVE] =
2354 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2355 CPUID_XSAVE_XGETBV1,
2356 .features[FEAT_6_EAX] =
2357 CPUID_6_EAX_ARAT,
2358 .xlevel = 0x80000008,
2359 .model_id = "Intel Core Processor (Skylake, IBRS)",
2360 },
53f9a6f4
BF		 2361 {
2362 .name = "Skylake-Server",
2363 .level = 0xd,
2364 .vendor = CPUID_VENDOR_INTEL,
2365 .family = 6,
2366 .model = 85,
2367 .stepping = 4,
2368 .features[FEAT_1_EDX] =
2369 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2370 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2371 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2372 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2373 CPUID_DE | CPUID_FP87,
2374 .features[FEAT_1_ECX] =
2375 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2376 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2377 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2378 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2379 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2380 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2381 .features[FEAT_8000_0001_EDX] =
2382 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2383 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2384 .features[FEAT_8000_0001_ECX] =
2385 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2386 .features[FEAT_7_0_EBX] =
2387 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2388 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2389 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2390 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2391 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2392 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2393 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2394 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
53f9a6f4
BF		 2395 /* Missing: XSAVES (not supported by some Linux versions,
2396 * including v4.1 to v4.12).
2397 * KVM doesn't yet expose any XSAVES state save component,
2398 * and the only one defined in Skylake (processor tracing)
2399 * probably will block migration anyway.
2400 */
2401 .features[FEAT_XSAVE] =
2402 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2403 CPUID_XSAVE_XGETBV1,
2404 .features[FEAT_6_EAX] =
2405 CPUID_6_EAX_ARAT,
2406 .xlevel = 0x80000008,
2407 .model_id = "Intel Xeon Processor (Skylake)",
2408 },
ac96c413
EH		 2409 {
2410 .name = "Skylake-Server-IBRS",
2411 .level = 0xd,
2412 .vendor = CPUID_VENDOR_INTEL,
2413 .family = 6,
2414 .model = 85,
2415 .stepping = 4,
2416 .features[FEAT_1_EDX] =
2417 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2418 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2419 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2420 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2421 CPUID_DE | CPUID_FP87,
2422 .features[FEAT_1_ECX] =
2423 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2424 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2425 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2426 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2427 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2428 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2429 .features[FEAT_8000_0001_EDX] =
2430 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2431 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2432 .features[FEAT_8000_0001_ECX] =
2433 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2434 .features[FEAT_7_0_EDX] =
2435 CPUID_7_0_EDX_SPEC_CTRL,
2436 .features[FEAT_7_0_EBX] =
2437 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2438 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2439 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2440 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2441 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2442 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2443 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2444 CPUID_7_0_EBX_AVX512VL,
2445 /* Missing: XSAVES (not supported by some Linux versions,
2446 * including v4.1 to v4.12).
2447 * KVM doesn't yet expose any XSAVES state save component,
2448 * and the only one defined in Skylake (processor tracing)
2449 * probably will block migration anyway.
2450 */
2451 .features[FEAT_XSAVE] =
2452 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2453 CPUID_XSAVE_XGETBV1,
2454 .features[FEAT_6_EAX] =
2455 CPUID_6_EAX_ARAT,
2456 .xlevel = 0x80000008,
2457 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2458 },
8a11c62d
RH		 2459 {
2460 .name = "Icelake-Client",
2461 .level = 0xd,
2462 .vendor = CPUID_VENDOR_INTEL,
2463 .family = 6,
2464 .model = 126,
2465 .stepping = 0,
2466 .features[FEAT_1_EDX] =
2467 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2468 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2469 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2470 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2471 CPUID_DE | CPUID_FP87,
2472 .features[FEAT_1_ECX] =
2473 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2474 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2475 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2476 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2477 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2478 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2479 .features[FEAT_8000_0001_EDX] =
2480 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2481 CPUID_EXT2_SYSCALL,
2482 .features[FEAT_8000_0001_ECX] =
2483 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2484 .features[FEAT_8000_0008_EBX] =
2485 CPUID_8000_0008_EBX_WBNOINVD,
2486 .features[FEAT_7_0_EBX] =
2487 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2488 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2489 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2490 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2491 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INTEL_PT,
2492 .features[FEAT_7_0_ECX] =
2493 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2494 CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2495 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2496 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2497 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2498 .features[FEAT_7_0_EDX] =
2499 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2500 /* Missing: XSAVES (not supported by some Linux versions,
2501 * including v4.1 to v4.12).
2502 * KVM doesn't yet expose any XSAVES state save component,
2503 * and the only one defined in Skylake (processor tracing)
2504 * probably will block migration anyway.
2505 */
2506 .features[FEAT_XSAVE] =
2507 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2508 CPUID_XSAVE_XGETBV1,
2509 .features[FEAT_6_EAX] =
2510 CPUID_6_EAX_ARAT,
2511 .xlevel = 0x80000008,
2512 .model_id = "Intel Core Processor (Icelake)",
2513 },
2514 {
2515 .name = "Icelake-Server",
2516 .level = 0xd,
2517 .vendor = CPUID_VENDOR_INTEL,
2518 .family = 6,
2519 .model = 134,
2520 .stepping = 0,
2521 .features[FEAT_1_EDX] =
2522 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2523 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2524 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2525 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2526 CPUID_DE | CPUID_FP87,
2527 .features[FEAT_1_ECX] =
2528 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2529 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2530 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2531 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2532 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2533 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2534 .features[FEAT_8000_0001_EDX] =
2535 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2536 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2537 .features[FEAT_8000_0001_ECX] =
2538 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2539 .features[FEAT_8000_0008_EBX] =
2540 CPUID_8000_0008_EBX_WBNOINVD,
2541 .features[FEAT_7_0_EBX] =
2542 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2543 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2544 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2545 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2546 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2547 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2548 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2549 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
2550 CPUID_7_0_EBX_INTEL_PT,
2551 .features[FEAT_7_0_ECX] =
2552 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2553 CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2554 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2555 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2556 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
2557 .features[FEAT_7_0_EDX] =
2558 CPUID_7_0_EDX_PCONFIG | CPUID_7_0_EDX_SPEC_CTRL |
2559 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2560 /* Missing: XSAVES (not supported by some Linux versions,
2561 * including v4.1 to v4.12).
2562 * KVM doesn't yet expose any XSAVES state save component,
2563 * and the only one defined in Skylake (processor tracing)
2564 * probably will block migration anyway.
2565 */
2566 .features[FEAT_XSAVE] =
2567 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2568 CPUID_XSAVE_XGETBV1,
2569 .features[FEAT_6_EAX] =
2570 CPUID_6_EAX_ARAT,
2571 .xlevel = 0x80000008,
2572 .model_id = "Intel Xeon Processor (Icelake)",
2573 },
a1849515
BF		 2574 {
2575 .name = "KnightsMill",
2576 .level = 0xd,
2577 .vendor = CPUID_VENDOR_INTEL,
2578 .family = 6,
2579 .model = 133,
2580 .stepping = 0,
2581 .features[FEAT_1_EDX] =
2582 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2583 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2584 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2585 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2586 CPUID_PSE | CPUID_DE | CPUID_FP87,
2587 .features[FEAT_1_ECX] =
2588 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2589 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2590 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2591 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2592 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2593 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2594 .features[FEAT_8000_0001_EDX] =
2595 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2596 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2597 .features[FEAT_8000_0001_ECX] =
2598 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2599 .features[FEAT_7_0_EBX] =
2600 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2601 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2602 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2603 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2604 CPUID_7_0_EBX_AVX512ER,
2605 .features[FEAT_7_0_ECX] =
2606 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2607 .features[FEAT_7_0_EDX] =
2608 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2609 .features[FEAT_XSAVE] =
2610 CPUID_XSAVE_XSAVEOPT,
2611 .features[FEAT_6_EAX] =
2612 CPUID_6_EAX_ARAT,
2613 .xlevel = 0x80000008,
2614 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2615 },
3eca4642
EH		 2616 {
2617 .name = "Opteron_G1",
2618 .level = 5,
99b88a17 2619 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2620 .family = 15,
2621 .model = 6,
2622 .stepping = 1,
0514ef2f 2623 .features[FEAT_1_EDX] =
b3a4f0b1 2624 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2625 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2626 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2627 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2628 CPUID_DE | CPUID_FP87,
0514ef2f 2629 .features[FEAT_1_ECX] =
27861ecc 2630 CPUID_EXT_SSE3,
0514ef2f 2631 .features[FEAT_8000_0001_EDX] =
2a923a29 2632 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 2633 .xlevel = 0x80000008,
2634 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2635 },
2636 {
2637 .name = "Opteron_G2",
2638 .level = 5,
99b88a17 2639 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2640 .family = 15,
2641 .model = 6,
2642 .stepping = 1,
0514ef2f 2643 .features[FEAT_1_EDX] =
b3a4f0b1 2644 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2645 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2646 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2647 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2648 CPUID_DE | CPUID_FP87,
0514ef2f 2649 .features[FEAT_1_ECX] =
27861ecc 2650 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 2651 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2652 .features[FEAT_8000_0001_EDX] =
2a923a29 2653 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2654 .features[FEAT_8000_0001_ECX] =
27861ecc 2655 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2656 .xlevel = 0x80000008,
2657 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2658 },
2659 {
2660 .name = "Opteron_G3",
2661 .level = 5,
99b88a17 2662 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 2663 .family = 16,
2664 .model = 2,
2665 .stepping = 3,
0514ef2f 2666 .features[FEAT_1_EDX] =
b3a4f0b1 2667 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2668 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2669 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2670 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2671 CPUID_DE | CPUID_FP87,
0514ef2f 2672 .features[FEAT_1_ECX] =
27861ecc 2673 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 2674 CPUID_EXT_SSE3,
33b5e8c0 2675 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2676 .features[FEAT_8000_0001_EDX] =
2a923a29 2677 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2678 .features[FEAT_8000_0001_ECX] =
27861ecc 2679 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 2680 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2681 .xlevel = 0x80000008,
2682 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2683 },
2684 {
2685 .name = "Opteron_G4",
2686 .level = 0xd,
99b88a17 2687 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2688 .family = 21,
2689 .model = 1,
2690 .stepping = 2,
0514ef2f 2691 .features[FEAT_1_EDX] =
b3a4f0b1 2692 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2693 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2694 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2695 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2696 CPUID_DE | CPUID_FP87,
0514ef2f 2697 .features[FEAT_1_ECX] =
27861ecc 2698 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2699 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2700 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2701 CPUID_EXT_SSE3,
33b5e8c0 2702 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2703 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 2704 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2705 CPUID_EXT2_SYSCALL,
0514ef2f 2706 .features[FEAT_8000_0001_ECX] =
27861ecc 2707 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2708 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2709 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2710 CPUID_EXT3_LAHF_LM,
0bb0b2d2 2711 /* no xsaveopt! */
3eca4642
EH		 2712 .xlevel = 0x8000001A,
2713 .model_id = "AMD Opteron 62xx class CPU",
2714 },
021941b9
AP		 2715 {
2716 .name = "Opteron_G5",
2717 .level = 0xd,
99b88a17 2718 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 2719 .family = 21,
2720 .model = 2,
2721 .stepping = 0,
0514ef2f 2722 .features[FEAT_1_EDX] =
b3a4f0b1 2723 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2724 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2725 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2726 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2727 CPUID_DE | CPUID_FP87,
0514ef2f 2728 .features[FEAT_1_ECX] =
27861ecc 2729 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 2730 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2731 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2732 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 2733 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2734 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 2735 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2736 CPUID_EXT2_SYSCALL,
0514ef2f 2737 .features[FEAT_8000_0001_ECX] =
27861ecc 2738 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2739 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2740 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2741 CPUID_EXT3_LAHF_LM,
0bb0b2d2 2742 /* no xsaveopt! */
021941b9
AP		 2743 .xlevel = 0x8000001A,
2744 .model_id = "AMD Opteron 63xx class CPU",
2745 },
2e2efc7d
BS		 2746 {
2747 .name = "EPYC",
2748 .level = 0xd,
2749 .vendor = CPUID_VENDOR_AMD,
2750 .family = 23,
2751 .model = 1,
2752 .stepping = 2,
2753 .features[FEAT_1_EDX] =
2754 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2755 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2756 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2757 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2758 CPUID_VME | CPUID_FP87,
2759 .features[FEAT_1_ECX] =
2760 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2761 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2762 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2763 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2764 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2765 .features[FEAT_8000_0001_EDX] =
2766 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2767 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2768 CPUID_EXT2_SYSCALL,
2769 .features[FEAT_8000_0001_ECX] =
2770 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2771 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2772 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2773 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 2774 .features[FEAT_7_0_EBX] =
2775 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2776 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2777 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2778 CPUID_7_0_EBX_SHA_NI,
2779 /* Missing: XSAVES (not supported by some Linux versions,
2780 * including v4.1 to v4.12).
2781 * KVM doesn't yet expose any XSAVES state save component.
2782 */
2783 .features[FEAT_XSAVE] =
2784 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2785 CPUID_XSAVE_XGETBV1,
2786 .features[FEAT_6_EAX] =
2787 CPUID_6_EAX_ARAT,
e0051647 2788 .xlevel = 0x8000001E,
2e2efc7d 2789 .model_id = "AMD EPYC Processor",
fe52acd2 2790 .cache_info = &epyc_cache_info,
2e2efc7d 2791 },
6cfbc54e
EH		 2792 {
2793 .name = "EPYC-IBPB",
2794 .level = 0xd,
2795 .vendor = CPUID_VENDOR_AMD,
2796 .family = 23,
2797 .model = 1,
2798 .stepping = 2,
2799 .features[FEAT_1_EDX] =
2800 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2801 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2802 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2803 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2804 CPUID_VME | CPUID_FP87,
2805 .features[FEAT_1_ECX] =
2806 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2807 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2808 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2809 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2810 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2811 .features[FEAT_8000_0001_EDX] =
2812 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2813 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2814 CPUID_EXT2_SYSCALL,
2815 .features[FEAT_8000_0001_ECX] =
2816 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2817 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2818 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2819 CPUID_EXT3_TOPOEXT,
6cfbc54e
EH		 2820 .features[FEAT_8000_0008_EBX] =
2821 CPUID_8000_0008_EBX_IBPB,
2822 .features[FEAT_7_0_EBX] =
2823 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2824 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2825 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2826 CPUID_7_0_EBX_SHA_NI,
2827 /* Missing: XSAVES (not supported by some Linux versions,
2828 * including v4.1 to v4.12).
2829 * KVM doesn't yet expose any XSAVES state save component.
2830 */
2831 .features[FEAT_XSAVE] =
2832 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2833 CPUID_XSAVE_XGETBV1,
2834 .features[FEAT_6_EAX] =
2835 CPUID_6_EAX_ARAT,
e0051647 2836 .xlevel = 0x8000001E,
6cfbc54e 2837 .model_id = "AMD EPYC Processor (with IBPB)",
fe52acd2 2838 .cache_info = &epyc_cache_info,
6cfbc54e 2839 },
c6dc6f63
AP		 2840};
2841
5114e842
EH		 2842typedef struct PropValue {
2843 const char *prop, *value;
2844} PropValue;
2845
2846/* KVM-specific features that are automatically added/removed
2847 * from all CPU models when KVM is enabled.
2848 */
2849static PropValue kvm_default_props[] = {
2850 { "kvmclock", "on" },
2851 { "kvm-nopiodelay", "on" },
2852 { "kvm-asyncpf", "on" },
2853 { "kvm-steal-time", "on" },
2854 { "kvm-pv-eoi", "on" },
2855 { "kvmclock-stable-bit", "on" },
2856 { "x2apic", "on" },
2857 { "acpi", "off" },
2858 { "monitor", "off" },
2859 { "svm", "off" },
2860 { NULL, NULL },
2861};
2862
04d99c3c
EH		 2863/* TCG-specific defaults that override all CPU models when using TCG
2864 */
2865static PropValue tcg_default_props[] = {
2866 { "vme", "off" },
2867 { NULL, NULL },
2868};
2869
2870
5114e842
EH		 2871void x86_cpu_change_kvm_default(const char *prop, const char *value)
2872{
2873 PropValue *pv;
2874 for (pv = kvm_default_props; pv->prop; pv++) {
2875 if (!strcmp(pv->prop, prop)) {
2876 pv->value = value;
2877 break;
2878 }
2879 }
2880
2881 /* It is valid to call this function only for properties that
2882 * are already present in the kvm_default_props table.
2883 */
2884 assert(pv->prop);
2885}
2886
4d1b279b
EH		 2887static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2888 bool migratable_only);
2889
40bfe48f
HZ		 2890static bool lmce_supported(void)
2891{
c62f2630 2892 uint64_t mce_cap = 0;
40bfe48f 2893
c62f2630 2894#ifdef CONFIG_KVM
40bfe48f
HZ		 2895 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
2896 return false;
2897 }
c62f2630 2898#endif
40bfe48f
HZ		 2899
2900 return !!(mce_cap & MCG_LMCE_P);
2901}
2902
7d8050b5
EH		 2903#define CPUID_MODEL_ID_SZ 48
2904
2905/**
2906 * cpu_x86_fill_model_id:
2907 * Get CPUID model ID string from host CPU.
2908 *
2909 * @str should have at least CPUID_MODEL_ID_SZ bytes
2910 *
2911 * The function does NOT add a null terminator to the string
2912 * automatically.
2913 */
c6dc6f63
AP		 2914static int cpu_x86_fill_model_id(char *str)
2915{
2916 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2917 int i;
2918
2919 for (i = 0; i < 3; i++) {
2920 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
2921 memcpy(str + i * 16 + 0, &eax, 4);
2922 memcpy(str + i * 16 + 4, &ebx, 4);
2923 memcpy(str + i * 16 + 8, &ecx, 4);
2924 memcpy(str + i * 16 + 12, &edx, 4);
2925 }
2926 return 0;
2927}
2928
c62f2630 2929static Property max_x86_cpu_properties[] = {
120eee7d 2930 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 2931 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 2932 DEFINE_PROP_END_OF_LIST()
2933};
2934
c62f2630 2935static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 2936{
84f1b92f 2937 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 2938 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 2939
f48c8837 2940 xcc->ordering = 9;
6e746f30 2941
ee465a3e 2942 xcc->model_description =
c62f2630 2943 "Enables all features supported by the accelerator in the current host";
d940ee9b 2944
c62f2630 2945 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 2946}
2947
0bacd8b3
EH		 2948static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
2949
c62f2630 2950static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 2951{
2952 X86CPU *cpu = X86_CPU(obj);
2953 CPUX86State *env = &cpu->env;
2954 KVMState *s = kvm_state;
d940ee9b 2955
4d1b279b
EH		 2956 /* We can't fill the features array here because we don't know yet if
2957 * "migratable" is true or false.
2958 */
44bd8e53 2959 cpu->max_features = true;
4d1b279b 2960
d6dcc558 2961 if (accel_uses_host_cpuid()) {
bd182022
EH		 2962 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
2963 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
2964 int family, model, stepping;
d6dcc558
SAGDR		 2965 X86CPUDefinition host_cpudef = { };
2966 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2967
2968 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
2969 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
0bacd8b3 2970
bd182022 2971 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 2972
bd182022 2973 cpu_x86_fill_model_id(model_id);
0bacd8b3 2974
bd182022
EH		 2975 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
2976 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
2977 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
2978 object_property_set_int(OBJECT(cpu), stepping, "stepping",
2979 &error_abort);
2980 object_property_set_str(OBJECT(cpu), model_id, "model-id",
2981 &error_abort);
0bacd8b3 2982
d6dcc558
SAGDR		 2983 if (kvm_enabled()) {
2984 env->cpuid_min_level =
2985 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
2986 env->cpuid_min_xlevel =
2987 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
2988 env->cpuid_min_xlevel2 =
2989 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2990 } else {
2991 env->cpuid_min_level =
2992 hvf_get_supported_cpuid(0x0, 0, R_EAX);
2993 env->cpuid_min_xlevel =
2994 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
2995 env->cpuid_min_xlevel2 =
2996 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
2997 }
40bfe48f
HZ		 2998
2999 if (lmce_supported()) {
3000 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
3001 }
6900d1cc
EH		 3002 } else {
3003 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
3004 "vendor", &error_abort);
3005 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
3006 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
3007 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
3008 object_property_set_str(OBJECT(cpu),
3009 "QEMU TCG CPU version " QEMU_HW_VERSION,
3010 "model-id", &error_abort);
e4356010 3011 }
2a573259 3012
d940ee9b 3013 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 3014}
3015
c62f2630
EH		 3016static const TypeInfo max_x86_cpu_type_info = {
3017 .name = X86_CPU_TYPE_NAME("max"),
3018 .parent = TYPE_X86_CPU,
3019 .instance_init = max_x86_cpu_initfn,
3020 .class_init = max_x86_cpu_class_init,
3021};
3022
d6dcc558 3023#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 3024static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
3025{
3026 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3027
d6dcc558 3028 xcc->host_cpuid_required = true;
c62f2630
EH		 3029 xcc->ordering = 8;
3030
02693cc4
GK		 3031#if defined(CONFIG_KVM)
3032 xcc->model_description =
3033 "KVM processor with all supported host features ";
3034#elif defined(CONFIG_HVF)
3035 xcc->model_description =
3036 "HVF processor with all supported host features ";
3037#endif
c62f2630
EH		 3038}
3039
d940ee9b
EH		 3040static const TypeInfo host_x86_cpu_type_info = {
3041 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 3042 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 3043 .class_init = host_x86_cpu_class_init,
3044};
3045
3046#endif
3047
07585923
RH		 3048static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
3049{
3050 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
3051
3052 switch (f->type) {
3053 case CPUID_FEATURE_WORD:
3054 {
3055 const char *reg = get_register_name_32(f->cpuid.reg);
3056 assert(reg);
3057 return g_strdup_printf("CPUID.%02XH:%s",
3058 f->cpuid.eax, reg);
3059 }
3060 case MSR_FEATURE_WORD:
3061 return g_strdup_printf("MSR(%02XH)",
3062 f->msr.index);
3063 }
3064
3065 return NULL;
3066}
3067
8459e396 3068static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 3069{
8459e396 3070 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63 3071 int i;
07585923 3072 char *feat_word_str;
c6dc6f63 3073
857aee33 3074 for (i = 0; i < 32; ++i) {
72370dc1 3075 if ((1UL << i) & mask) {
07585923
RH		 3076 feat_word_str = feature_word_description(f, i);
3077 warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
d6dcc558 3078 accel_uses_host_cpuid() ? "host" : "TCG",
07585923 3079 feat_word_str,
8297be80
AF		 3080 f->feat_names[i] ? "." : "",
3081 f->feat_names[i] ? f->feat_names[i] : "", i);
07585923 3082 g_free(feat_word_str);
c6dc6f63 3083 }
857aee33 3084 }
c6dc6f63
AP		 3085}
3086
d7bce999
EB		 3087static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
3088 const char *name, void *opaque,
3089 Error **errp)
95b8519d
AF		 3090{
3091 X86CPU *cpu = X86_CPU(obj);
3092 CPUX86State *env = &cpu->env;
3093 int64_t value;
3094
3095 value = (env->cpuid_version >> 8) & 0xf;
3096 if (value == 0xf) {
3097 value += (env->cpuid_version >> 20) & 0xff;
3098 }
51e72bc1 3099 visit_type_int(v, name, &value, errp);
95b8519d
AF		 3100}
3101
d7bce999
EB		 3102static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
3103 const char *name, void *opaque,
3104 Error **errp)
ed5e1ec3 3105{
71ad61d3
AF		 3106 X86CPU *cpu = X86_CPU(obj);
3107 CPUX86State *env = &cpu->env;
3108 const int64_t min = 0;
3109 const int64_t max = 0xff + 0xf;
65cd9064 3110 Error *local_err = NULL;
71ad61d3
AF		 3111 int64_t value;
3112
51e72bc1 3113 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3114 if (local_err) {
3115 error_propagate(errp, local_err);
71ad61d3
AF		 3116 return;
3117 }
3118 if (value < min || value > max) {
c6bd8c70
MA		 3119 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3120 name ? name : "null", value, min, max);
71ad61d3
AF		 3121 return;
3122 }
3123
ed5e1ec3 3124 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 3125 if (value > 0x0f) {
3126 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 3127 } else {
71ad61d3 3128 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 3129 }
3130}
3131
d7bce999
EB		 3132static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
3133 const char *name, void *opaque,
3134 Error **errp)
67e30c83
AF		 3135{
3136 X86CPU *cpu = X86_CPU(obj);
3137 CPUX86State *env = &cpu->env;
3138 int64_t value;
3139
3140 value = (env->cpuid_version >> 4) & 0xf;
3141 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 3142 visit_type_int(v, name, &value, errp);
67e30c83
AF		 3143}
3144
d7bce999
EB		 3145static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
3146 const char *name, void *opaque,
3147 Error **errp)
b0704cbd 3148{
c5291a4f
AF		 3149 X86CPU *cpu = X86_CPU(obj);
3150 CPUX86State *env = &cpu->env;
3151 const int64_t min = 0;
3152 const int64_t max = 0xff;
65cd9064 3153 Error *local_err = NULL;
c5291a4f
AF		 3154 int64_t value;
3155
51e72bc1 3156 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3157 if (local_err) {
3158 error_propagate(errp, local_err);
c5291a4f
AF		 3159 return;
3160 }
3161 if (value < min || value > max) {
c6bd8c70
MA		 3162 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3163 name ? name : "null", value, min, max);
c5291a4f
AF		 3164 return;
3165 }
3166
b0704cbd 3167 env->cpuid_version &= ~0xf00f0;
c5291a4f 3168 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 3169}
3170
35112e41 3171static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 3172 const char *name, void *opaque,
35112e41
AF		 3173 Error **errp)
3174{
3175 X86CPU *cpu = X86_CPU(obj);
3176 CPUX86State *env = &cpu->env;
3177 int64_t value;
3178
3179 value = env->cpuid_version & 0xf;
51e72bc1 3180 visit_type_int(v, name, &value, errp);
35112e41
AF		 3181}
3182
036e2222 3183static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 3184 const char *name, void *opaque,
036e2222 3185 Error **errp)
38c3dc46 3186{
036e2222
AF		 3187 X86CPU *cpu = X86_CPU(obj);
3188 CPUX86State *env = &cpu->env;
3189 const int64_t min = 0;
3190 const int64_t max = 0xf;
65cd9064 3191 Error *local_err = NULL;
036e2222
AF		 3192 int64_t value;
3193
51e72bc1 3194 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3195 if (local_err) {
3196 error_propagate(errp, local_err);
036e2222
AF		 3197 return;
3198 }
3199 if (value < min || value > max) {
c6bd8c70
MA		 3200 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3201 name ? name : "null", value, min, max);
036e2222
AF		 3202 return;
3203 }
3204
38c3dc46 3205 env->cpuid_version &= ~0xf;
036e2222 3206 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 3207}
3208
d480e1af
AF		 3209static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
3210{
3211 X86CPU *cpu = X86_CPU(obj);
3212 CPUX86State *env = &cpu->env;
3213 char *value;
d480e1af 3214
e42a92ae 3215 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 3216 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
3217 env->cpuid_vendor3);
d480e1af
AF		 3218 return value;
3219}
3220
3221static void x86_cpuid_set_vendor(Object *obj, const char *value,
3222 Error **errp)
3223{
3224 X86CPU *cpu = X86_CPU(obj);
3225 CPUX86State *env = &cpu->env;
3226 int i;
3227
9df694ee 3228 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 3229 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 3230 return;
3231 }
3232
3233 env->cpuid_vendor1 = 0;
3234 env->cpuid_vendor2 = 0;
3235 env->cpuid_vendor3 = 0;
3236 for (i = 0; i < 4; i++) {
3237 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
3238 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
3239 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
3240 }
d480e1af
AF		 3241}
3242
63e886eb
AF		 3243static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
3244{
3245 X86CPU *cpu = X86_CPU(obj);
3246 CPUX86State *env = &cpu->env;
3247 char *value;
3248 int i;
3249
3250 value = g_malloc(48 + 1);
3251 for (i = 0; i < 48; i++) {
3252 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
3253 }
3254 value[48] = '\0';
3255 return value;
3256}
3257
938d4c25
AF		 3258static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
3259 Error **errp)
dcce6675 3260{
938d4c25
AF		 3261 X86CPU *cpu = X86_CPU(obj);
3262 CPUX86State *env = &cpu->env;
dcce6675
AF		 3263 int c, len, i;
3264
3265 if (model_id == NULL) {
3266 model_id = "";
3267 }
3268 len = strlen(model_id);
d0a6acf4 3269 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 3270 for (i = 0; i < 48; i++) {
3271 if (i >= len) {
3272 c = '\0';
3273 } else {
3274 c = (uint8_t)model_id[i];
3275 }
3276 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
3277 }
3278}
3279
d7bce999
EB		 3280static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
3281 void *opaque, Error **errp)
89e48965
AF		 3282{
3283 X86CPU *cpu = X86_CPU(obj);
3284 int64_t value;
3285
3286 value = cpu->env.tsc_khz * 1000;
51e72bc1 3287 visit_type_int(v, name, &value, errp);
89e48965
AF		 3288}
3289
d7bce999
EB		 3290static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
3291 void *opaque, Error **errp)
89e48965
AF		 3292{
3293 X86CPU *cpu = X86_CPU(obj);
3294 const int64_t min = 0;
2e84849a 3295 const int64_t max = INT64_MAX;
65cd9064 3296 Error *local_err = NULL;
89e48965
AF		 3297 int64_t value;
3298
51e72bc1 3299 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3300 if (local_err) {
3301 error_propagate(errp, local_err);
89e48965
AF		 3302 return;
3303 }
3304 if (value < min || value > max) {
c6bd8c70
MA		 3305 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3306 name ? name : "null", value, min, max);
89e48965
AF		 3307 return;
3308 }
3309
36f96c4b 3310 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 3311}
3312
7e5292b5 3313/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 3314static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
3315 const char *name, void *opaque,
3316 Error **errp)
8e8aba50 3317{
7e5292b5 3318 uint32_t *array = (uint32_t *)opaque;
8e8aba50 3319 FeatureWord w;
8e8aba50
EH		 3320 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
3321 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
3322 X86CPUFeatureWordInfoList *list = NULL;
3323
3324 for (w = 0; w < FEATURE_WORDS; w++) {
3325 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 3326 /*
3327 * We didn't have MSR features when "feature-words" was
3328 * introduced. Therefore skipped other type entries.
3329 */
3330 if (wi->type != CPUID_FEATURE_WORD) {
3331 continue;
3332 }
8e8aba50 3333 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 3334 qwi->cpuid_input_eax = wi->cpuid.eax;
3335 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
3336 qwi->cpuid_input_ecx = wi->cpuid.ecx;
3337 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 3338 qwi->features = array[w];
8e8aba50
EH		 3339
3340 /* List will be in reverse order, but order shouldn't matter */
3341 list_entries[w].next = list;
3342 list_entries[w].value = &word_infos[w];
3343 list = &list_entries[w];
3344 }
3345
6b62d961 3346 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 3347}
3348
d7bce999
EB		 3349static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3350 void *opaque, Error **errp)
c8f0f88e
IM		 3351{
3352 X86CPU *cpu = X86_CPU(obj);
3353 int64_t value = cpu->hyperv_spinlock_attempts;
3354
51e72bc1 3355 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 3356}
3357
d7bce999
EB		 3358static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3359 void *opaque, Error **errp)
c8f0f88e
IM		 3360{
3361 const int64_t min = 0xFFF;
3362 const int64_t max = UINT_MAX;
3363 X86CPU *cpu = X86_CPU(obj);
3364 Error *err = NULL;
3365 int64_t value;
3366
51e72bc1 3367 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 3368 if (err) {
3369 error_propagate(errp, err);
3370 return;
3371 }
3372
3373 if (value < min || value > max) {
3374 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 3375 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
3376 object_get_typename(obj), name ? name : "null",
3377 value, min, max);
c8f0f88e
IM		 3378 return;
3379 }
3380 cpu->hyperv_spinlock_attempts = value;
3381}
3382
1b6b7d10 3383static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 3384 .name = "int",
3385 .get = x86_get_hv_spinlocks,
3386 .set = x86_set_hv_spinlocks,
3387};
3388
72ac2e87
IM		 3389/* Convert all '_' in a feature string option name to '-', to make feature
3390 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3391 */
3392static inline void feat2prop(char *s)
3393{
3394 while ((s = strchr(s, '_'))) {
3395 *s = '-';
3396 }
3397}
3398
b54c9377
EH		 3399/* Return the feature property name for a feature flag bit */
3400static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
3401{
3402 /* XSAVE components are automatically enabled by other features,
3403 * so return the original feature name instead
3404 */
3405 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
3406 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
3407
3408 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
3409 x86_ext_save_areas[comp].bits) {
3410 w = x86_ext_save_areas[comp].feature;
3411 bitnr = ctz32(x86_ext_save_areas[comp].bits);
3412 }
3413 }
3414
3415 assert(bitnr < 32);
3416 assert(w < FEATURE_WORDS);
3417 return feature_word_info[w].feat_names[bitnr];
3418}
3419
dc15c051
IM		 3420/* Compatibily hack to maintain legacy +-feat semantic,
3421 * where +-feat overwrites any feature set by
3422 * feat=on|feat even if the later is parsed after +-feat
3423 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3424 */
2fae0d96 3425static GList *plus_features, *minus_features;
dc15c051 3426
83a00f60
EH		 3427static gint compare_string(gconstpointer a, gconstpointer b)
3428{
3429 return g_strcmp0(a, b);
3430}
3431
8f961357
EH		 3432/* Parse "+feature,-feature,feature=foo" CPU feature string
3433 */
62a48a2a 3434static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 3435 Error **errp)
8f961357 3436{
8f961357 3437 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 3438 static bool cpu_globals_initialized;
83a00f60 3439 bool ambiguous = false;
62a48a2a
IM		 3440
3441 if (cpu_globals_initialized) {
3442 return;
3443 }
3444 cpu_globals_initialized = true;
8f961357 3445
f6750e95
EH		 3446 if (!features) {
3447 return;
3448 }
3449
3450 for (featurestr = strtok(features, ",");
685479bd 3451 featurestr;
f6750e95
EH		 3452 featurestr = strtok(NULL, ",")) {
3453 const char *name;
3454 const char *val = NULL;
3455 char *eq = NULL;
cf2887c9 3456 char num[32];
62a48a2a 3457 GlobalProperty *prop;
c6dc6f63 3458
f6750e95 3459 /* Compatibility syntax: */
c6dc6f63 3460 if (featurestr[0] == '+') {
2fae0d96
EH		 3461 plus_features = g_list_append(plus_features,
3462 g_strdup(featurestr + 1));
f6750e95 3463 continue;
c6dc6f63 3464 } else if (featurestr[0] == '-') {
2fae0d96
EH		 3465 minus_features = g_list_append(minus_features,
3466 g_strdup(featurestr + 1));
f6750e95
EH		 3467 continue;
3468 }
3469
3470 eq = strchr(featurestr, '=');
3471 if (eq) {
3472 *eq++ = 0;
3473 val = eq;
c6dc6f63 3474 } else {
f6750e95 3475 val = "on";
a91987c2 3476 }
f6750e95
EH		 3477
3478 feat2prop(featurestr);
3479 name = featurestr;
3480
83a00f60 3481 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 3482 warn_report("Ambiguous CPU model string. "
3483 "Don't mix both \"+%s\" and \"%s=%s\"",
3484 name, name, val);
83a00f60
EH		 3485 ambiguous = true;
3486 }
3487 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 3488 warn_report("Ambiguous CPU model string. "
3489 "Don't mix both \"-%s\" and \"%s=%s\"",
3490 name, name, val);
83a00f60
EH		 3491 ambiguous = true;
3492 }
3493
f6750e95
EH		 3494 /* Special case: */
3495 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 3496 int ret;
f46bfdbf 3497 uint64_t tsc_freq;
f6750e95 3498
f17fd4fd 3499 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 3500 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 3501 error_setg(errp, "bad numerical value %s", val);
3502 return;
3503 }
3504 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3505 val = num;
3506 name = "tsc-frequency";
c6dc6f63 3507 }
f6750e95 3508
62a48a2a
IM		 3509 prop = g_new0(typeof(*prop), 1);
3510 prop->driver = typename;
3511 prop->property = g_strdup(name);
3512 prop->value = g_strdup(val);
3513 prop->errp = &error_fatal;
3514 qdev_prop_register_global(prop);
f6750e95
EH		 3515 }
3516
83a00f60 3517 if (ambiguous) {
3dc6f869
AF		 3518 warn_report("Compatibility of ambiguous CPU model "
3519 "strings won't be kept on future QEMU versions");
83a00f60 3520 }
c6dc6f63
AP		 3521}
3522
b8d834a0 3523static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 3524static int x86_cpu_filter_features(X86CPU *cpu);
3525
3526/* Check for missing features that may prevent the CPU class from
3527 * running using the current machine and accelerator.
3528 */
3529static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3530 strList **missing_feats)
3531{
3532 X86CPU *xc;
3533 FeatureWord w;
3534 Error *err = NULL;
3535 strList **next = missing_feats;
3536
d6dcc558 3537 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 3538 strList *new = g_new0(strList, 1);
3c254ab8 3539 new->value = g_strdup("kvm");
b54c9377
EH		 3540 *missing_feats = new;
3541 return;
3542 }
3543
3544 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3545
b8d834a0 3546 x86_cpu_expand_features(xc, &err);
b54c9377 3547 if (err) {
b8d834a0 3548 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 3549 * but in case it does, just report the model as not
3550 * runnable at all using the "type" property.
3551 */
3552 strList *new = g_new0(strList, 1);
3553 new->value = g_strdup("type");
3554 *next = new;
3555 next = &new->next;
3556 }
3557
3558 x86_cpu_filter_features(xc);
3559
3560 for (w = 0; w < FEATURE_WORDS; w++) {
3561 uint32_t filtered = xc->filtered_features[w];
3562 int i;
3563 for (i = 0; i < 32; i++) {
3564 if (filtered & (1UL << i)) {
3565 strList *new = g_new0(strList, 1);
3566 new->value = g_strdup(x86_cpu_feature_name(w, i));
3567 *next = new;
3568 next = &new->next;
3569 }
3570 }
3571 }
3572
3573 object_unref(OBJECT(xc));
3574}
3575
8c3329e5 3576/* Print all cpuid feature names in featureset
c6dc6f63 3577 */
cc643b1e 3578static void listflags(FILE *f, fprintf_function print, GList *features)
0856579c 3579{
cc643b1e
DB		 3580 size_t len = 0;
3581 GList *tmp;
3582
3583 for (tmp = features; tmp; tmp = tmp->next) {
3584 const char *name = tmp->data;
3585 if ((len + strlen(name) + 1) >= 75) {
3586 print(f, "\n");
3587 len = 0;
c6dc6f63 3588 }
cc643b1e
DB		 3589 print(f, "%s%s", len == 0 ? " " : " ", name);
3590 len += strlen(name) + 1;
8c3329e5 3591 }
cc643b1e 3592 print(f, "\n");
c6dc6f63
AP		 3593}
3594
f48c8837 3595/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 3596static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3597{
3598 ObjectClass *class_a = (ObjectClass *)a;
3599 ObjectClass *class_b = (ObjectClass *)b;
3600 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3601 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b
DB		 3602 char *name_a, *name_b;
3603 int ret;
ee465a3e 3604
f48c8837 3605 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 3606 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 3607 } else {
c7dbff4b
DB		 3608 name_a = x86_cpu_class_get_model_name(cc_a);
3609 name_b = x86_cpu_class_get_model_name(cc_b);
3610 ret = strcmp(name_a, name_b);
3611 g_free(name_a);
3612 g_free(name_b);
ee465a3e 3613 }
c7dbff4b 3614 return ret;
ee465a3e
EH		 3615}
3616
3617static GSList *get_sorted_cpu_model_list(void)
3618{
3619 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3620 list = g_slist_sort(list, x86_cpu_list_compare);
3621 return list;
3622}
3623
3624static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3625{
3626 ObjectClass *oc = data;
3627 X86CPUClass *cc = X86_CPU_CLASS(oc);
3628 CPUListState *s = user_data;
3629 char *name = x86_cpu_class_get_model_name(cc);
3630 const char *desc = cc->model_description;
0bacd8b3 3631 if (!desc && cc->cpu_def) {
ee465a3e
EH		 3632 desc = cc->cpu_def->model_id;
3633 }
3634
081492ca 3635 (*s->cpu_fprintf)(s->file, "x86 %-20s %-48s\n",
ee465a3e
EH		 3636 name, desc);
3637 g_free(name);
3638}
3639
3640/* list available CPU models and flags */
e916cbf8 3641void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 3642{
cc643b1e 3643 int i, j;
ee465a3e
EH		 3644 CPUListState s = {
3645 .file = f,
3646 .cpu_fprintf = cpu_fprintf,
3647 };
3648 GSList *list;
cc643b1e 3649 GList *names = NULL;
c6dc6f63 3650
ee465a3e
EH		 3651 (*cpu_fprintf)(f, "Available CPUs:\n");
3652 list = get_sorted_cpu_model_list();
3653 g_slist_foreach(list, x86_cpu_list_entry, &s);
3654 g_slist_free(list);
21ad7789 3655
cc643b1e 3656 names = NULL;
3af60be2
JK		 3657 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3658 FeatureWordInfo *fw = &feature_word_info[i];
cc643b1e
DB		 3659 for (j = 0; j < 32; j++) {
3660 if (fw->feat_names[j]) {
3661 names = g_list_append(names, (gpointer)fw->feat_names[j]);
3662 }
3663 }
3af60be2 3664 }
cc643b1e
DB		 3665
3666 names = g_list_sort(names, (GCompareFunc)strcmp);
3667
3668 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3669 listflags(f, cpu_fprintf, names);
3670 (*cpu_fprintf)(f, "\n");
3671 g_list_free(names);
c6dc6f63
AP		 3672}
3673
ee465a3e
EH		 3674static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3675{
3676 ObjectClass *oc = data;
3677 X86CPUClass *cc = X86_CPU_CLASS(oc);
3678 CpuDefinitionInfoList **cpu_list = user_data;
3679 CpuDefinitionInfoList *entry;
3680 CpuDefinitionInfo *info;
3681
3682 info = g_malloc0(sizeof(*info));
3683 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 3684 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3685 info->has_unavailable_features = true;
8ed877b7 3686 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 3687 info->migration_safe = cc->migration_safe;
3688 info->has_migration_safe = true;
5adbed30 3689 info->q_static = cc->static_model;
ee465a3e
EH		 3690
3691 entry = g_malloc0(sizeof(*entry));
3692 entry->value = info;
3693 entry->next = *cpu_list;
3694 *cpu_list = entry;
3695}
3696
76b64a7a 3697CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 3698{
3699 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 3700 GSList *list = get_sorted_cpu_model_list();
3701 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3702 g_slist_free(list);
e3966126
AL		 3703 return cpu_list;
3704}
3705
84f1b92f
EH		 3706static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3707 bool migratable_only)
27418adf
EH		 3708{
3709 FeatureWordInfo *wi = &feature_word_info[w];
07585923 3710 uint32_t r = 0;
27418adf 3711
fefb41bf 3712 if (kvm_enabled()) {
07585923
RH		 3713 switch (wi->type) {
3714 case CPUID_FEATURE_WORD:
3715 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
3716 wi->cpuid.ecx,
3717 wi->cpuid.reg);
3718 break;
3719 case MSR_FEATURE_WORD:
d86f9636
RH		 3720 r = kvm_arch_get_supported_msr_feature(kvm_state,
3721 wi->msr.index);
07585923
RH		 3722 break;
3723 }
d6dcc558 3724 } else if (hvf_enabled()) {
07585923
RH		 3725 if (wi->type != CPUID_FEATURE_WORD) {
3726 return 0;
3727 }
3728 r = hvf_get_supported_cpuid(wi->cpuid.eax,
3729 wi->cpuid.ecx,
3730 wi->cpuid.reg);
fefb41bf 3731 } else if (tcg_enabled()) {
84f1b92f 3732 r = wi->tcg_features;
fefb41bf
EH		 3733 } else {
3734 return ~0;
3735 }
84f1b92f
EH		 3736 if (migratable_only) {
3737 r &= x86_cpu_get_migratable_flags(w);
3738 }
3739 return r;
27418adf
EH		 3740}
3741
8ca30e86
EH		 3742static void x86_cpu_report_filtered_features(X86CPU *cpu)
3743{
3744 FeatureWord w;
3745
3746 for (w = 0; w < FEATURE_WORDS; w++) {
3747 report_unavailable_features(w, cpu->filtered_features[w]);
3748 }
3749}
3750
5114e842
EH		 3751static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3752{
3753 PropValue *pv;
3754 for (pv = props; pv->prop; pv++) {
3755 if (!pv->value) {
3756 continue;
3757 }
3758 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3759 &error_abort);
3760 }
3761}
3762
f99fd7ca 3763/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 3764 */
d940ee9b 3765static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 3766{
61dcd775 3767 CPUX86State *env = &cpu->env;
74f54bc4
EH		 3768 const char *vendor;
3769 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 3770 FeatureWord w;
c6dc6f63 3771
f99fd7ca
EH		 3772 /*NOTE: any property set by this function should be returned by
3773 * x86_cpu_static_props(), so static expansion of
3774 * query-cpu-model-expansion is always complete.
3775 */
3776
c39c0edf 3777 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 3778 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3779 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 3780
2d64255b
AF		 3781 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3782 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3783 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 3784 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 3785 for (w = 0; w < FEATURE_WORDS; w++) {
3786 env->features[w] = def->features[w];
3787 }
82beb536 3788
a9f27ea9
EH		 3789 /* legacy-cache defaults to 'off' if CPU model provides cache info */
3790 cpu->legacy_cache = !def->cache_info;
ab8f992e 3791
9576de75 3792 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 3793 /* TODO: in-kernel irqchip for hvf */
82beb536 3794 if (kvm_enabled()) {
492a4c94
LT		 3795 if (!kvm_irqchip_in_kernel()) {
3796 x86_cpu_change_kvm_default("x2apic", "off");
3797 }
3798
5114e842 3799 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 3800 } else if (tcg_enabled()) {
3801 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 3802 }
5fcca9ff 3803
82beb536 3804 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 3805
3806 /* sysenter isn't supported in compatibility mode on AMD,
3807 * syscall isn't supported in compatibility mode on Intel.
3808 * Normally we advertise the actual CPU vendor, but you can
3809 * override this using the 'vendor' property if you want to use
3810 * KVM's sysenter/syscall emulation in compatibility mode and
3811 * when doing cross vendor migration
3812 */
74f54bc4 3813 vendor = def->vendor;
d6dcc558 3814 if (accel_uses_host_cpuid()) {
7c08db30
EH		 3815 uint32_t ebx = 0, ecx = 0, edx = 0;
3816 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3817 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3818 vendor = host_vendor;
3819 }
3820
3821 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3822
c6dc6f63
AP		 3823}
3824
f99fd7ca
EH		 3825/* Return a QDict containing keys for all properties that can be included
3826 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3827 * must be included in the dictionary.
3828 */
3829static QDict *x86_cpu_static_props(void)
3830{
3831 FeatureWord w;
3832 int i;
3833 static const char *props[] = {
3834 "min-level",
3835 "min-xlevel",
3836 "family",
3837 "model",
3838 "stepping",
3839 "model-id",
3840 "vendor",
3841 "lmce",
3842 NULL,
3843 };
3844 static QDict *d;
3845
3846 if (d) {
3847 return d;
3848 }
3849
3850 d = qdict_new();
3851 for (i = 0; props[i]; i++) {
0f9afc2a 3852 qdict_put_null(d, props[i]);
f99fd7ca
EH		 3853 }
3854
3855 for (w = 0; w < FEATURE_WORDS; w++) {
3856 FeatureWordInfo *fi = &feature_word_info[w];
3857 int bit;
3858 for (bit = 0; bit < 32; bit++) {
3859 if (!fi->feat_names[bit]) {
3860 continue;
3861 }
0f9afc2a 3862 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 3863 }
3864 }
3865
3866 return d;
3867}
3868
3869/* Add an entry to @props dict, with the value for property. */
3870static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
3871{
3872 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
3873 &error_abort);
3874
3875 qdict_put_obj(props, prop, value);
3876}
3877
3878/* Convert CPU model data from X86CPU object to a property dictionary
3879 * that can recreate exactly the same CPU model.
3880 */
3881static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
3882{
3883 QDict *sprops = x86_cpu_static_props();
3884 const QDictEntry *e;
3885
3886 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
3887 const char *prop = qdict_entry_key(e);
3888 x86_cpu_expand_prop(cpu, props, prop);
3889 }
3890}
3891
b8097deb
EH		 3892/* Convert CPU model data from X86CPU object to a property dictionary
3893 * that can recreate exactly the same CPU model, including every
3894 * writeable QOM property.
3895 */
3896static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
3897{
3898 ObjectPropertyIterator iter;
3899 ObjectProperty *prop;
3900
3901 object_property_iter_init(&iter, OBJECT(cpu));
3902 while ((prop = object_property_iter_next(&iter))) {
3903 /* skip read-only or write-only properties */
3904 if (!prop->get || !prop->set) {
3905 continue;
3906 }
3907
3908 /* "hotplugged" is the only property that is configurable
3909 * on the command-line but will be set differently on CPUs
3910 * created using "-cpu ... -smp ..." and by CPUs created
3911 * on the fly by x86_cpu_from_model() for querying. Skip it.
3912 */
3913 if (!strcmp(prop->name, "hotplugged")) {
3914 continue;
3915 }
3916 x86_cpu_expand_prop(cpu, props, prop->name);
3917 }
3918}
3919
f99fd7ca
EH		 3920static void object_apply_props(Object *obj, QDict *props, Error **errp)
3921{
3922 const QDictEntry *prop;
3923 Error *err = NULL;
3924
3925 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
3926 object_property_set_qobject(obj, qdict_entry_value(prop),
3927 qdict_entry_key(prop), &err);
3928 if (err) {
3929 break;
3930 }
3931 }
3932
3933 error_propagate(errp, err);
3934}
3935
3936/* Create X86CPU object according to model+props specification */
3937static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
3938{
3939 X86CPU *xc = NULL;
3940 X86CPUClass *xcc;
3941 Error *err = NULL;
3942
3943 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
3944 if (xcc == NULL) {
3945 error_setg(&err, "CPU model '%s' not found", model);
3946 goto out;
3947 }
3948
3949 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3950 if (props) {
3951 object_apply_props(OBJECT(xc), props, &err);
3952 if (err) {
3953 goto out;
3954 }
3955 }
3956
3957 x86_cpu_expand_features(xc, &err);
3958 if (err) {
3959 goto out;
3960 }
3961
3962out:
3963 if (err) {
3964 error_propagate(errp, err);
3965 object_unref(OBJECT(xc));
3966 xc = NULL;
3967 }
3968 return xc;
3969}
3970
3971CpuModelExpansionInfo *
3972arch_query_cpu_model_expansion(CpuModelExpansionType type,
3973 CpuModelInfo *model,
3974 Error **errp)
3975{
3976 X86CPU *xc = NULL;
3977 Error *err = NULL;
3978 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
3979 QDict *props = NULL;
3980 const char *base_name;
3981
3982 xc = x86_cpu_from_model(model->name,
3983 model->has_props ?
7dc847eb 3984 qobject_to(QDict, model->props) :
f99fd7ca
EH		 3985 NULL, &err);
3986 if (err) {
3987 goto out;
3988 }
3989
b8097deb 3990 props = qdict_new();
e38bf612
EH		 3991 ret->model = g_new0(CpuModelInfo, 1);
3992 ret->model->props = QOBJECT(props);
3993 ret->model->has_props = true;
f99fd7ca
EH		 3994
3995 switch (type) {
3996 case CPU_MODEL_EXPANSION_TYPE_STATIC:
3997 /* Static expansion will be based on "base" only */
3998 base_name = "base";
b8097deb 3999 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 4000 break;
4001 case CPU_MODEL_EXPANSION_TYPE_FULL:
4002 /* As we don't return every single property, full expansion needs
4003 * to keep the original model name+props, and add extra
4004 * properties on top of that.
4005 */
4006 base_name = model->name;
b8097deb 4007 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 4008 break;
4009 default:
4010 error_setg(&err, "Unsupportted expansion type");
4011 goto out;
4012 }
4013
f99fd7ca
EH		 4014 x86_cpu_to_dict(xc, props);
4015
f99fd7ca 4016 ret->model->name = g_strdup(base_name);
f99fd7ca
EH		 4017
4018out:
4019 object_unref(OBJECT(xc));
4020 if (err) {
4021 error_propagate(errp, err);
4022 qapi_free_CpuModelExpansionInfo(ret);
4023 ret = NULL;
4024 }
4025 return ret;
4026}
4027
00fcd100
AB		 4028static gchar *x86_gdb_arch_name(CPUState *cs)
4029{
4030#ifdef TARGET_X86_64
4031 return g_strdup("i386:x86-64");
4032#else
4033 return g_strdup("i386");
4034#endif
4035}
4036
d940ee9b
EH		 4037static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
4038{
4039 X86CPUDefinition *cpudef = data;
4040 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4041
4042 xcc->cpu_def = cpudef;
bd72159d 4043 xcc->migration_safe = true;
d940ee9b
EH		 4044}
4045
4046static void x86_register_cpudef_type(X86CPUDefinition *def)
4047{
4048 char *typename = x86_cpu_type_name(def->name);
4049 TypeInfo ti = {
4050 .name = typename,
4051 .parent = TYPE_X86_CPU,
4052 .class_init = x86_cpu_cpudef_class_init,
4053 .class_data = def,
4054 };
4055
2a923a29
EH		 4056 /* AMD aliases are handled at runtime based on CPUID vendor, so
4057 * they shouldn't be set on the CPU model table.
4058 */
4059 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 4060 /* catch mistakes instead of silently truncating model_id when too long */
4061 assert(def->model_id && strlen(def->model_id) <= 48);
4062
2a923a29 4063
d940ee9b
EH		 4064 type_register(&ti);
4065 g_free(typename);
4066}
4067
c6dc6f63 4068#if !defined(CONFIG_USER_ONLY)
c6dc6f63 4069
0e26b7b8
BS		 4070void cpu_clear_apic_feature(CPUX86State *env)
4071{
0514ef2f 4072 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 4073}
4074
c6dc6f63
AP		 4075#endif /* !CONFIG_USER_ONLY */
4076
c6dc6f63
AP		 4077void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
4078 uint32_t *eax, uint32_t *ebx,
4079 uint32_t *ecx, uint32_t *edx)
4080{
a60f24b5
AF		 4081 X86CPU *cpu = x86_env_get_cpu(env);
4082 CPUState *cs = CPU(cpu);
14c985cf 4083 uint32_t pkg_offset;
4ed3d478 4084 uint32_t limit;
1ce36bfe 4085 uint32_t signature[3];
a60f24b5 4086
4ed3d478
DB		 4087 /* Calculate & apply limits for different index ranges */
4088 if (index >= 0xC0000000) {
4089 limit = env->cpuid_xlevel2;
4090 } else if (index >= 0x80000000) {
4091 limit = env->cpuid_xlevel;
1ce36bfe
DB		 4092 } else if (index >= 0x40000000) {
4093 limit = 0x40000001;
c6dc6f63 4094 } else {
4ed3d478
DB		 4095 limit = env->cpuid_level;
4096 }
4097
4098 if (index > limit) {
4099 /* Intel documentation states that invalid EAX input will
4100 * return the same information as EAX=cpuid_level
4101 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
4102 */
4103 index = env->cpuid_level;
c6dc6f63
AP		 4104 }
4105
4106 switch(index) {
4107 case 0:
4108 *eax = env->cpuid_level;
5eb2f7a4
EH		 4109 *ebx = env->cpuid_vendor1;
4110 *edx = env->cpuid_vendor2;
4111 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 4112 break;
4113 case 1:
4114 *eax = env->cpuid_version;
7e72a45c
EH		 4115 *ebx = (cpu->apic_id << 24) |
4116 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 4117 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 4118 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
4119 *ecx |= CPUID_EXT_OSXSAVE;
4120 }
0514ef2f 4121 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 4122 if (cs->nr_cores * cs->nr_threads > 1) {
4123 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 4124 *edx |= CPUID_HT;
c6dc6f63
AP		 4125 }
4126 break;
4127 case 2:
4128 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 4129 if (cpu->cache_info_passthrough) {
4130 host_cpuid(index, 0, eax, ebx, ecx, edx);
4131 break;
4132 }
5e891bf8 4133 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 4134 *ebx = 0;
14c985cf
LM		 4135 if (!cpu->enable_l3_cache) {
4136 *ecx = 0;
4137 } else {
a9f27ea9 4138 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 4139 }
a9f27ea9
EH		 4140 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
4141 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
4142 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 4143 break;
4144 case 4:
4145 /* cache info: needed for Core compatibility */
787aaf57
BC		 4146 if (cpu->cache_info_passthrough) {
4147 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 4148 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 4149 *eax &= ~0xFC000000;
7e3482f8
EH		 4150 if ((*eax & 31) && cs->nr_cores > 1) {
4151 *eax |= (cs->nr_cores - 1) << 26;
4152 }
c6dc6f63 4153 } else {
2f7a21c4 4154 *eax = 0;
76c2975a 4155 switch (count) {
c6dc6f63 4156 case 0: /* L1 dcache info */
a9f27ea9
EH		 4157 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
4158 1, cs->nr_cores,
7e3482f8 4159 eax, ebx, ecx, edx);
c6dc6f63
AP		 4160 break;
4161 case 1: /* L1 icache info */
a9f27ea9
EH		 4162 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
4163 1, cs->nr_cores,
7e3482f8 4164 eax, ebx, ecx, edx);
c6dc6f63
AP		 4165 break;
4166 case 2: /* L2 cache info */
a9f27ea9
EH		 4167 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
4168 cs->nr_threads, cs->nr_cores,
7e3482f8 4169 eax, ebx, ecx, edx);
c6dc6f63 4170 break;
14c985cf 4171 case 3: /* L3 cache info */
7e3482f8
EH		 4172 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4173 if (cpu->enable_l3_cache) {
a9f27ea9
EH		 4174 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
4175 (1 << pkg_offset), cs->nr_cores,
7e3482f8 4176 eax, ebx, ecx, edx);
14c985cf
LM		 4177 break;
4178 }
7e3482f8 4179 /* fall through */
c6dc6f63 4180 default: /* end of info */
7e3482f8 4181 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 4182 break;
76c2975a
PB		 4183 }
4184 }
c6dc6f63
AP		 4185 break;
4186 case 5:
2266d443
MT		 4187 /* MONITOR/MWAIT Leaf */
4188 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
4189 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
4190 *ecx = cpu->mwait.ecx; /* flags */
4191 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 4192 break;
4193 case 6:
4194 /* Thermal and Power Leaf */
28b8e4d0 4195 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 4196 *ebx = 0;
4197 *ecx = 0;
4198 *edx = 0;
4199 break;
f7911686 4200 case 7:
13526728
EH		 4201 /* Structured Extended Feature Flags Enumeration Leaf */
4202 if (count == 0) {
4203 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 4204 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 4205 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 4206 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
4207 *ecx |= CPUID_7_0_ECX_OSPKE;
4208 }
95ea69fb 4209 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 4210 } else {
4211 *eax = 0;
4212 *ebx = 0;
4213 *ecx = 0;
4214 *edx = 0;
4215 }
4216 break;
c6dc6f63
AP		 4217 case 9:
4218 /* Direct Cache Access Information Leaf */
4219 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
4220 *ebx = 0;
4221 *ecx = 0;
4222 *edx = 0;
4223 break;
4224 case 0xA:
4225 /* Architectural Performance Monitoring Leaf */
9337e3b6 4226 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 4227 KVMState *s = cs->kvm_state;
a0fa8208
GN		 4228
4229 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
4230 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
4231 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
4232 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 4233 } else if (hvf_enabled() && cpu->enable_pmu) {
4234 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
4235 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
4236 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
4237 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 4238 } else {
4239 *eax = 0;
4240 *ebx = 0;
4241 *ecx = 0;
4242 *edx = 0;
4243 }
c6dc6f63 4244 break;
5232d00a
RK		 4245 case 0xB:
4246 /* Extended Topology Enumeration Leaf */
4247 if (!cpu->enable_cpuid_0xb) {
4248 *eax = *ebx = *ecx = *edx = 0;
4249 break;
4250 }
4251
4252 *ecx = count & 0xff;
4253 *edx = cpu->apic_id;
4254
4255 switch (count) {
4256 case 0:
eab60fb9
MAL		 4257 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
4258 *ebx = cs->nr_threads;
5232d00a
RK		 4259 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
4260 break;
4261 case 1:
eab60fb9
MAL		 4262 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4263 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 4264 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
4265 break;
4266 default:
4267 *eax = 0;
4268 *ebx = 0;
4269 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
4270 }
4271
4272 assert(!(*eax & ~0x1f));
4273 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
4274 break;
2560f19f 4275 case 0xD: {
51e49430 4276 /* Processor Extended State */
2560f19f
PB		 4277 *eax = 0;
4278 *ebx = 0;
4279 *ecx = 0;
4280 *edx = 0;
19dc85db 4281 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 4282 break;
4283 }
4928cd6d 4284
2560f19f 4285 if (count == 0) {
96193c22
EH		 4286 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
4287 *eax = env->features[FEAT_XSAVE_COMP_LO];
4288 *edx = env->features[FEAT_XSAVE_COMP_HI];
de2e68c9 4289 *ebx = xsave_area_size(env->xcr0);
2560f19f 4290 } else if (count == 1) {
0bb0b2d2 4291 *eax = env->features[FEAT_XSAVE];
f4f1110e 4292 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 4293 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
4294 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 4295 *eax = esa->size;
4296 *ebx = esa->offset;
2560f19f 4297 }
51e49430
SY		 4298 }
4299 break;
2560f19f 4300 }
e37a5c7f
CP		 4301 case 0x14: {
4302 /* Intel Processor Trace Enumeration */
4303 *eax = 0;
4304 *ebx = 0;
4305 *ecx = 0;
4306 *edx = 0;
4307 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
4308 !kvm_enabled()) {
4309 break;
4310 }
4311
4312 if (count == 0) {
4313 *eax = INTEL_PT_MAX_SUBLEAF;
4314 *ebx = INTEL_PT_MINIMAL_EBX;
4315 *ecx = INTEL_PT_MINIMAL_ECX;
4316 } else if (count == 1) {
4317 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
4318 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
4319 }
4320 break;
4321 }
1ce36bfe
DB		 4322 case 0x40000000:
4323 /*
4324 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4325 * set here, but we restrict to TCG none the less.
4326 */
4327 if (tcg_enabled() && cpu->expose_tcg) {
4328 memcpy(signature, "TCGTCGTCGTCG", 12);
4329 *eax = 0x40000001;
4330 *ebx = signature[0];
4331 *ecx = signature[1];
4332 *edx = signature[2];
4333 } else {
4334 *eax = 0;
4335 *ebx = 0;
4336 *ecx = 0;
4337 *edx = 0;
4338 }
4339 break;
4340 case 0x40000001:
4341 *eax = 0;
4342 *ebx = 0;
4343 *ecx = 0;
4344 *edx = 0;
4345 break;
c6dc6f63
AP		 4346 case 0x80000000:
4347 *eax = env->cpuid_xlevel;
4348 *ebx = env->cpuid_vendor1;
4349 *edx = env->cpuid_vendor2;
4350 *ecx = env->cpuid_vendor3;
4351 break;
4352 case 0x80000001:
4353 *eax = env->cpuid_version;
4354 *ebx = 0;
0514ef2f
EH		 4355 *ecx = env->features[FEAT_8000_0001_ECX];
4356 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 4357
4358 /* The Linux kernel checks for the CMPLegacy bit and
4359 * discards multiple thread information if it is set.
cb8d4c8f 4360 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 4361 */
ce3960eb 4362 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 4363 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
4364 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
4365 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 4366 *ecx |= 1 << 1; /* CmpLegacy bit */
4367 }
4368 }
c6dc6f63
AP		 4369 break;
4370 case 0x80000002:
4371 case 0x80000003:
4372 case 0x80000004:
4373 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
4374 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
4375 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
4376 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
4377 break;
4378 case 0x80000005:
4379 /* cache info (L1 cache) */
787aaf57
BC		 4380 if (cpu->cache_info_passthrough) {
4381 host_cpuid(index, 0, eax, ebx, ecx, edx);
4382 break;
4383 }
5e891bf8
EH		 4384 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
4385 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
4386 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
4387 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4388 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
4389 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 4390 break;
4391 case 0x80000006:
4392 /* cache info (L2 cache) */
787aaf57
BC		 4393 if (cpu->cache_info_passthrough) {
4394 host_cpuid(index, 0, eax, ebx, ecx, edx);
4395 break;
4396 }
5e891bf8
EH		 4397 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
4398 (L2_DTLB_2M_ENTRIES << 16) | \
4399 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
4400 (L2_ITLB_2M_ENTRIES);
4401 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
4402 (L2_DTLB_4K_ENTRIES << 16) | \
4403 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
4404 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4405 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
4406 cpu->enable_l3_cache ?
4407 env->cache_info_amd.l3_cache : NULL,
4408 ecx, edx);
c6dc6f63 4409 break;
303752a9
MT		 4410 case 0x80000007:
4411 *eax = 0;
4412 *ebx = 0;
4413 *ecx = 0;
4414 *edx = env->features[FEAT_8000_0007_EDX];
4415 break;
c6dc6f63
AP		 4416 case 0x80000008:
4417 /* virtual & phys address size in low 2 bytes. */
0514ef2f 4418 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 4419 /* 64 bit processor */
4420 *eax = cpu->phys_bits; /* configurable physical bits */
4421 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
4422 *eax |= 0x00003900; /* 57 bits virtual */
4423 } else {
4424 *eax |= 0x00003000; /* 48 bits virtual */
4425 }
c6dc6f63 4426 } else {
af45907a 4427 *eax = cpu->phys_bits;
c6dc6f63 4428 }
1b3420e1 4429 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 4430 *ecx = 0;
4431 *edx = 0;
ce3960eb
AF		 4432 if (cs->nr_cores * cs->nr_threads > 1) {
4433 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 4434 }
4435 break;
4436 case 0x8000000A:
0514ef2f 4437 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 4438 *eax = 0x00000001; /* SVM Revision */
4439 *ebx = 0x00000010; /* nr of ASIDs */
4440 *ecx = 0;
0514ef2f 4441 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 4442 } else {
4443 *eax = 0;
4444 *ebx = 0;
4445 *ecx = 0;
4446 *edx = 0;
4447 }
c6dc6f63 4448 break;
8f4202fb
BM		 4449 case 0x8000001D:
4450 *eax = 0;
4451 switch (count) {
4452 case 0: /* L1 dcache info */
4453 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
4454 eax, ebx, ecx, edx);
4455 break;
4456 case 1: /* L1 icache info */
4457 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
4458 eax, ebx, ecx, edx);
4459 break;
4460 case 2: /* L2 cache info */
4461 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
4462 eax, ebx, ecx, edx);
4463 break;
4464 case 3: /* L3 cache info */
4465 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
4466 eax, ebx, ecx, edx);
4467 break;
4468 default: /* end of info */
4469 *eax = *ebx = *ecx = *edx = 0;
4470 break;
4471 }
4472 break;
ed78467a
BM		 4473 case 0x8000001E:
4474 assert(cpu->core_id <= 255);
4475 encode_topo_cpuid8000001e(cs, cpu,
4476 eax, ebx, ecx, edx);
4477 break;
b3baa152
BW		 4478 case 0xC0000000:
4479 *eax = env->cpuid_xlevel2;
4480 *ebx = 0;
4481 *ecx = 0;
4482 *edx = 0;
4483 break;
4484 case 0xC0000001:
4485 /* Support for VIA CPU's CPUID instruction */
4486 *eax = env->cpuid_version;
4487 *ebx = 0;
4488 *ecx = 0;
0514ef2f 4489 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 4490 break;
4491 case 0xC0000002:
4492 case 0xC0000003:
4493 case 0xC0000004:
4494 /* Reserved for the future, and now filled with zero */
4495 *eax = 0;
4496 *ebx = 0;
4497 *ecx = 0;
4498 *edx = 0;
4499 break;
6cb8f2a6
BS		 4500 case 0x8000001F:
4501 *eax = sev_enabled() ? 0x2 : 0;
4502 *ebx = sev_get_cbit_position();
4503 *ebx |= sev_get_reduced_phys_bits() << 6;
4504 *ecx = 0;
4505 *edx = 0;
4506 break;
c6dc6f63
AP		 4507 default:
4508 /* reserved values: zero */
4509 *eax = 0;
4510 *ebx = 0;
4511 *ecx = 0;
4512 *edx = 0;
4513 break;
4514 }
4515}
5fd2087a
AF		 4516
4517/* CPUClass::reset() */
4518static void x86_cpu_reset(CPUState *s)
4519{
4520 X86CPU *cpu = X86_CPU(s);
4521 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
4522 CPUX86State *env = &cpu->env;
a114d25d
RH		 4523 target_ulong cr4;
4524 uint64_t xcr0;
c1958aea
AF		 4525 int i;
4526
5fd2087a
AF		 4527 xcc->parent_reset(s);
4528
5e992a8e 4529 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 4530
c1958aea
AF		 4531 env->old_exception = -1;
4532
4533 /* init to reset state */
4534
c1958aea
AF		 4535 env->hflags2 |= HF2_GIF_MASK;
4536
4537 cpu_x86_update_cr0(env, 0x60000010);
4538 env->a20_mask = ~0x0;
4539 env->smbase = 0x30000;
e13713db 4540 env->msr_smi_count = 0;
c1958aea
AF		 4541
4542 env->idt.limit = 0xffff;
4543 env->gdt.limit = 0xffff;
4544 env->ldt.limit = 0xffff;
4545 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4546 env->tr.limit = 0xffff;
4547 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4548
4549 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4550 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4551 DESC_R_MASK | DESC_A_MASK);
4552 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4553 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4554 DESC_A_MASK);
4555 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4556 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4557 DESC_A_MASK);
4558 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4559 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4560 DESC_A_MASK);
4561 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4562 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4563 DESC_A_MASK);
4564 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4565 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4566 DESC_A_MASK);
4567
4568 env->eip = 0xfff0;
4569 env->regs[R_EDX] = env->cpuid_version;
4570
4571 env->eflags = 0x2;
4572
4573 /* FPU init */
4574 for (i = 0; i < 8; i++) {
4575 env->fptags[i] = 1;
4576 }
5bde1407 4577 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 4578
4579 env->mxcsr = 0x1f80;
a114d25d
RH		 4580 /* All units are in INIT state. */
4581 env->xstate_bv = 0;
c1958aea
AF		 4582
4583 env->pat = 0x0007040600070406ULL;
4584 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4585
4586 memset(env->dr, 0, sizeof(env->dr));
4587 env->dr[6] = DR6_FIXED_1;
4588 env->dr[7] = DR7_FIXED_1;
b3310ab3 4589 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 4590 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 4591
a114d25d 4592 cr4 = 0;
cfc3b074 4593 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 4594
4595#ifdef CONFIG_USER_ONLY
4596 /* Enable all the features for user-mode. */
4597 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 4598 xcr0 |= XSTATE_SSE_MASK;
a114d25d 4599 }
0f70ed47
PB		 4600 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4601 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 4602 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 4603 xcr0 |= 1ull << i;
4604 }
a114d25d 4605 }
0f70ed47 4606
a114d25d
RH		 4607 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4608 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4609 }
07929f2a
RH		 4610 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4611 cr4 |= CR4_FSGSBASE_MASK;
4612 }
a114d25d
RH		 4613#endif
4614
4615 env->xcr0 = xcr0;
4616 cpu_x86_update_cr4(env, cr4);
0522604b 4617
9db2efd9
AW		 4618 /*
4619 * SDM 11.11.5 requires:
4620 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4621 * - IA32_MTRR_PHYSMASKn.V = 0
4622 * All other bits are undefined. For simplification, zero it all.
4623 */
4624 env->mtrr_deftype = 0;
4625 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4626 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4627
b7394c83
SAGDR		 4628 env->interrupt_injected = -1;
4629 env->exception_injected = -1;
4630 env->nmi_injected = false;
dd673288
IM		 4631#if !defined(CONFIG_USER_ONLY)
4632 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 4633 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 4634
259186a7 4635 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 4636
4637 if (kvm_enabled()) {
4638 kvm_arch_reset_vcpu(cpu);
4639 }
d6dcc558
SAGDR		 4640 else if (hvf_enabled()) {
4641 hvf_reset_vcpu(s);
4642 }
dd673288 4643#endif
5fd2087a
AF		 4644}
4645
dd673288
IM		 4646#ifndef CONFIG_USER_ONLY
4647bool cpu_is_bsp(X86CPU *cpu)
4648{
02e51483 4649 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 4650}
65dee380
IM		 4651
4652/* TODO: remove me, when reset over QOM tree is implemented */
4653static void x86_cpu_machine_reset_cb(void *opaque)
4654{
4655 X86CPU *cpu = opaque;
4656 cpu_reset(CPU(cpu));
4657}
dd673288
IM		 4658#endif
4659
de024815
AF		 4660static void mce_init(X86CPU *cpu)
4661{
4662 CPUX86State *cenv = &cpu->env;
4663 unsigned int bank;
4664
4665 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 4666 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 4667 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 4668 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4669 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 4670 cenv->mcg_ctl = ~(uint64_t)0;
4671 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4672 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4673 }
4674 }
4675}
4676
bdeec802 4677#ifndef CONFIG_USER_ONLY
2f114315 4678APICCommonClass *apic_get_class(void)
bdeec802 4679{
bdeec802
IM		 4680 const char *apic_type = "apic";
4681
d6dcc558 4682 /* TODO: in-kernel irqchip for hvf */
15eafc2e 4683 if (kvm_apic_in_kernel()) {
bdeec802
IM		 4684 apic_type = "kvm-apic";
4685 } else if (xen_enabled()) {
4686 apic_type = "xen-apic";
4687 }
4688
2f114315
RK		 4689 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4690}
4691
4692static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4693{
4694 APICCommonState *apic;
4695 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4696
4697 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 4698
6816b1b3
IM		 4699 object_property_add_child(OBJECT(cpu), "lapic",
4700 OBJECT(cpu->apic_state), &error_abort);
67e55caa 4701 object_unref(OBJECT(cpu->apic_state));
6816b1b3 4702
33d7a288 4703 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 4704 /* TODO: convert to link<> */
02e51483 4705 apic = APIC_COMMON(cpu->apic_state);
60671e58 4706 apic->cpu = cpu;
8d42d2d3 4707 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 4708}
4709
4710static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4711{
8d42d2d3
CF		 4712 APICCommonState *apic;
4713 static bool apic_mmio_map_once;
4714
02e51483 4715 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 4716 return;
4717 }
6e8e2651
MA		 4718 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4719 errp);
8d42d2d3
CF		 4720
4721 /* Map APIC MMIO area */
4722 apic = APIC_COMMON(cpu->apic_state);
4723 if (!apic_mmio_map_once) {
4724 memory_region_add_subregion_overlap(get_system_memory(),
4725 apic->apicbase &
4726 MSR_IA32_APICBASE_BASE,
4727 &apic->io_memory,
4728 0x1000);
4729 apic_mmio_map_once = true;
4730 }
bdeec802 4731}
f809c605
PB		 4732
4733static void x86_cpu_machine_done(Notifier *n, void *unused)
4734{
4735 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4736 MemoryRegion *smram =
4737 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4738
4739 if (smram) {
4740 cpu->smram = g_new(MemoryRegion, 1);
4741 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4742 smram, 0, 1ull << 32);
f8c45c65 4743 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 4744 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4745 }
4746}
d3c64d6a
IM		 4747#else
4748static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4749{
4750}
bdeec802
IM		 4751#endif
4752
11f6fee5
DDAG		 4753/* Note: Only safe for use on x86(-64) hosts */
4754static uint32_t x86_host_phys_bits(void)
4755{
4756 uint32_t eax;
4757 uint32_t host_phys_bits;
4758
4759 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4760 if (eax >= 0x80000008) {
4761 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4762 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4763 * at 23:16 that can specify a maximum physical address bits for
4764 * the guest that can override this value; but I've not seen
4765 * anything with that set.
4766 */
4767 host_phys_bits = eax & 0xff;
4768 } else {
4769 /* It's an odd 64 bit machine that doesn't have the leaf for
4770 * physical address bits; fall back to 36 that's most older
4771 * Intel.
4772 */
4773 host_phys_bits = 36;
4774 }
4775
4776 return host_phys_bits;
4777}
e48638fd 4778
c39c0edf
EH		 4779static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4780{
4781 if (*min < value) {
4782 *min = value;
4783 }
4784}
4785
4786/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4787static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4788{
4789 CPUX86State *env = &cpu->env;
4790 FeatureWordInfo *fi = &feature_word_info[w];
07585923 4791 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 4792 uint32_t region = eax & 0xF0000000;
4793
07585923 4794 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 4795 if (!env->features[w]) {
4796 return;
4797 }
4798
4799 switch (region) {
4800 case 0x00000000:
4801 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4802 break;
4803 case 0x80000000:
4804 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4805 break;
4806 case 0xC0000000:
4807 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4808 break;
4809 }
4810}
4811
2ca8a8be
EH		 4812/* Calculate XSAVE components based on the configured CPU feature flags */
4813static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4814{
4815 CPUX86State *env = &cpu->env;
4816 int i;
96193c22 4817 uint64_t mask;
2ca8a8be
EH		 4818
4819 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4820 return;
4821 }
4822
e3c9022b
EH		 4823 mask = 0;
4824 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 4825 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4826 if (env->features[esa->feature] & esa->bits) {
96193c22 4827 mask |= (1ULL << i);
2ca8a8be
EH		 4828 }
4829 }
4830
96193c22
EH		 4831 env->features[FEAT_XSAVE_COMP_LO] = mask;
4832 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 4833}
4834
b8d834a0
EH		 4835/***** Steps involved on loading and filtering CPUID data
4836 *
4837 * When initializing and realizing a CPU object, the steps
4838 * involved in setting up CPUID data are:
4839 *
4840 * 1) Loading CPU model definition (X86CPUDefinition). This is
4841 * implemented by x86_cpu_load_def() and should be completely
4842 * transparent, as it is done automatically by instance_init.
4843 * No code should need to look at X86CPUDefinition structs
4844 * outside instance_init.
4845 *
4846 * 2) CPU expansion. This is done by realize before CPUID
4847 * filtering, and will make sure host/accelerator data is
4848 * loaded for CPU models that depend on host capabilities
4849 * (e.g. "host"). Done by x86_cpu_expand_features().
4850 *
4851 * 3) CPUID filtering. This initializes extra data related to
4852 * CPUID, and checks if the host supports all capabilities
4853 * required by the CPU. Runnability of a CPU model is
4854 * determined at this step. Done by x86_cpu_filter_features().
4855 *
4856 * Some operations don't require all steps to be performed.
4857 * More precisely:
4858 *
4859 * - CPU instance creation (instance_init) will run only CPU
4860 * model loading. CPU expansion can't run at instance_init-time
4861 * because host/accelerator data may be not available yet.
4862 * - CPU realization will perform both CPU model expansion and CPUID
4863 * filtering, and return an error in case one of them fails.
4864 * - query-cpu-definitions needs to run all 3 steps. It needs
4865 * to run CPUID filtering, as the 'unavailable-features'
4866 * field is set based on the filtering results.
4867 * - The query-cpu-model-expansion QMP command only needs to run
4868 * CPU model loading and CPU expansion. It should not filter
4869 * any CPUID data based on host capabilities.
4870 */
4871
4872/* Expand CPU configuration data, based on configured features
4873 * and host/accelerator capabilities when appropriate.
4874 */
4875static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 4876{
b34d12d1 4877 CPUX86State *env = &cpu->env;
dc15c051 4878 FeatureWord w;
2fae0d96 4879 GList *l;
41f3d4d6 4880 Error *local_err = NULL;
9886e834 4881
d4a606b3
EH		 4882 /*TODO: Now cpu->max_features doesn't overwrite features
4883 * set using QOM properties, and we can convert
dc15c051
IM		 4884 * plus_features & minus_features to global properties
4885 * inside x86_cpu_parse_featurestr() too.
4886 */
44bd8e53 4887 if (cpu->max_features) {
dc15c051 4888 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 4889 /* Override only features that weren't set explicitly
4890 * by the user.
4891 */
4892 env->features[w] |=
4893 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
0d914f39
EH		 4894 ~env->user_features[w] & \
4895 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 4896 }
4897 }
4898
2fae0d96
EH		 4899 for (l = plus_features; l; l = l->next) {
4900 const char *prop = l->data;
4901 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
4902 if (local_err) {
4903 goto out;
4904 }
4905 }
4906
4907 for (l = minus_features; l; l = l->next) {
4908 const char *prop = l->data;
4909 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
4910 if (local_err) {
4911 goto out;
4912 }
dc15c051
IM		 4913 }
4914
aec661de
EH		 4915 if (!kvm_enabled() || !cpu->expose_kvm) {
4916 env->features[FEAT_KVM] = 0;
4917 }
4918
2ca8a8be 4919 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 4920
4921 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
4922 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
4923 if (cpu->full_cpuid_auto_level) {
4924 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
4925 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
4926 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
4927 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
4928 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
4929 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
4930 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 4931 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 4932 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
4933 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
4934 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 4935 /* SVM requires CPUID[0x8000000A] */
4936 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
4937 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
4938 }
6cb8f2a6
BS		 4939
4940 /* SEV requires CPUID[0x8000001F] */
4941 if (sev_enabled()) {
4942 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
4943 }
c39c0edf
EH		 4944 }
4945
4946 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
4947 if (env->cpuid_level == UINT32_MAX) {
4948 env->cpuid_level = env->cpuid_min_level;
4949 }
4950 if (env->cpuid_xlevel == UINT32_MAX) {
4951 env->cpuid_xlevel = env->cpuid_min_xlevel;
4952 }
4953 if (env->cpuid_xlevel2 == UINT32_MAX) {
4954 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 4955 }
7a059953 4956
41f3d4d6
EH		 4957out:
4958 if (local_err != NULL) {
4959 error_propagate(errp, local_err);
4960 }
4961}
4962
b8d834a0
EH		 4963/*
4964 * Finishes initialization of CPUID data, filters CPU feature
4965 * words based on host availability of each feature.
4966 *
4967 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
4968 */
4969static int x86_cpu_filter_features(X86CPU *cpu)
4970{
4971 CPUX86State *env = &cpu->env;
4972 FeatureWord w;
4973 int rv = 0;
4974
4975 for (w = 0; w < FEATURE_WORDS; w++) {
4976 uint32_t host_feat =
4977 x86_cpu_get_supported_feature_word(w, false);
4978 uint32_t requested_features = env->features[w];
4979 env->features[w] &= host_feat;
4980 cpu->filtered_features[w] = requested_features & ~env->features[w];
4981 if (cpu->filtered_features[w]) {
4982 rv = 1;
4983 }
4984 }
4985
e37a5c7f
CP		 4986 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
4987 kvm_enabled()) {
4988 KVMState *s = CPU(cpu)->kvm_state;
4989 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
4990 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
4991 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
4992 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
4993 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
4994
4995 if (!eax_0 ||
4996 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
4997 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
4998 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
4999 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
5000 INTEL_PT_ADDR_RANGES_NUM) ||
5001 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96
LK		 5002 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
5003 (ecx_0 & INTEL_PT_IP_LIP)) {
e37a5c7f
CP		 5004 /*
5005 * Processor Trace capabilities aren't configurable, so if the
5006 * host can't emulate the capabilities we report on
5007 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
5008 */
5009 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
5010 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
5011 rv = 1;
5012 }
5013 }
5014
b8d834a0
EH		 5015 return rv;
5016}
5017
41f3d4d6
EH		 5018#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
5019 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
5020 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
5021#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
5022 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
5023 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
5024static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
5025{
5026 CPUState *cs = CPU(dev);
5027 X86CPU *cpu = X86_CPU(dev);
5028 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5029 CPUX86State *env = &cpu->env;
5030 Error *local_err = NULL;
5031 static bool ht_warned;
5032
2266d443
MT		 5033 if (xcc->host_cpuid_required) {
5034 if (!accel_uses_host_cpuid()) {
5035 char *name = x86_cpu_class_get_model_name(xcc);
5036 error_setg(&local_err, "CPU model '%s' requires KVM", name);
5037 g_free(name);
5038 goto out;
5039 }
5040
5041 if (enable_cpu_pm) {
5042 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
5043 &cpu->mwait.ecx, &cpu->mwait.edx);
5044 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
5045 }
41f3d4d6
EH		 5046 }
5047
2266d443
MT		 5048 /* mwait extended info: needed for Core compatibility */
5049 /* We always wake on interrupt even if host does not have the capability */
5050 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
5051
41f3d4d6
EH		 5052 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
5053 error_setg(errp, "apic-id property was not initialized properly");
5054 return;
5055 }
5056
b8d834a0 5057 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 5058 if (local_err) {
5059 goto out;
5060 }
5061
8ca30e86
EH		 5062 if (x86_cpu_filter_features(cpu) &&
5063 (cpu->check_cpuid || cpu->enforce_cpuid)) {
5064 x86_cpu_report_filtered_features(cpu);
5065 if (cpu->enforce_cpuid) {
5066 error_setg(&local_err,
d6dcc558 5067 accel_uses_host_cpuid() ?
8ca30e86
EH		 5068 "Host doesn't support requested features" :
5069 "TCG doesn't support requested features");
5070 goto out;
5071 }
9997cf7b
EH		 5072 }
5073
9b15cd9e
IM		 5074 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
5075 * CPUID[1].EDX.
5076 */
e48638fd 5077 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 5078 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
5079 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 5080 & CPUID_EXT2_AMD_ALIASES);
5081 }
5082
11f6fee5
DDAG		 5083 /* For 64bit systems think about the number of physical bits to present.
5084 * ideally this should be the same as the host; anything other than matching
5085 * the host can cause incorrect guest behaviour.
5086 * QEMU used to pick the magic value of 40 bits that corresponds to
5087 * consumer AMD devices but nothing else.
5088 */
af45907a 5089 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 5090 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 5091 uint32_t host_phys_bits = x86_host_phys_bits();
5092 static bool warned;
5093
5094 if (cpu->host_phys_bits) {
5095 /* The user asked for us to use the host physical bits */
5096 cpu->phys_bits = host_phys_bits;
5097 }
5098
5099 /* Print a warning if the user set it to a value that's not the
5100 * host value.
5101 */
5102 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
5103 !warned) {
3dc6f869
AF		 5104 warn_report("Host physical bits (%u)"
5105 " does not match phys-bits property (%u)",
5106 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 5107 warned = true;
5108 }
5109
5110 if (cpu->phys_bits &&
5111 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
5112 cpu->phys_bits < 32)) {
af45907a
DDAG		 5113 error_setg(errp, "phys-bits should be between 32 and %u "
5114 " (but is %u)",
5115 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
5116 return;
5117 }
5118 } else {
11f6fee5 5119 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 5120 error_setg(errp, "TCG only supports phys-bits=%u",
5121 TCG_PHYS_ADDR_BITS);
5122 return;
5123 }
5124 }
11f6fee5
DDAG		 5125 /* 0 means it was not explicitly set by the user (or by machine
5126 * compat_props or by the host code above). In this case, the default
5127 * is the value used by TCG (40).
5128 */
5129 if (cpu->phys_bits == 0) {
5130 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
5131 }
af45907a
DDAG		 5132 } else {
5133 /* For 32 bit systems don't use the user set value, but keep
5134 * phys_bits consistent with what we tell the guest.
5135 */
5136 if (cpu->phys_bits != 0) {
5137 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
5138 return;
5139 }
fefb41bf 5140
af45907a
DDAG		 5141 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
5142 cpu->phys_bits = 36;
5143 } else {
5144 cpu->phys_bits = 32;
5145 }
5146 }
a9f27ea9
EH		 5147
5148 /* Cache information initialization */
5149 if (!cpu->legacy_cache) {
5150 if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
5151 char *name = x86_cpu_class_get_model_name(xcc);
5152 error_setg(errp,
5153 "CPU model '%s' doesn't support legacy-cache=off", name);
5154 g_free(name);
5155 return;
5156 }
5157 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
5158 *xcc->cpu_def->cache_info;
5159 } else {
5160 /* Build legacy cache information */
5161 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
5162 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
5163 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
5164 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
5165
5166 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
5167 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
5168 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
5169 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
5170
5171 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
5172 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
5173 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
5174 env->cache_info_amd.l3_cache = &legacy_l3_cache;
5175 }
5176
5177
ce5b1bbf
LV		 5178 cpu_exec_realizefn(cs, &local_err);
5179 if (local_err != NULL) {
5180 error_propagate(errp, local_err);
5181 return;
5182 }
42ecabaa 5183
65dee380
IM		 5184#ifndef CONFIG_USER_ONLY
5185 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 5186
0514ef2f 5187 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 5188 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 5189 if (local_err != NULL) {
4dc1f449 5190 goto out;
bdeec802
IM		 5191 }
5192 }
65dee380
IM		 5193#endif
5194
7a059953 5195 mce_init(cpu);
2001d0cd
PB		 5196
5197#ifndef CONFIG_USER_ONLY
5198 if (tcg_enabled()) {
f809c605 5199 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 5200 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 5201
5202 /* Outer container... */
5203 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 5204 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 5205
5206 /* ... with two regions inside: normal system memory with low
5207 * priority, and...
5208 */
5209 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
5210 get_system_memory(), 0, ~0ull);
5211 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
5212 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 5213
5214 cs->num_ases = 2;
80ceb07a
PX		 5215 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
5216 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 5217
5218 /* ... SMRAM with higher priority, linked from /machine/smram. */
5219 cpu->machine_done.notify = x86_cpu_machine_done;
5220 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 5221 }
5222#endif
5223
14a10fc3 5224 qemu_init_vcpu(cs);
d3c64d6a 5225
6b2942f9
BM		 5226 /*
5227 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
5228 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
5229 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 5230 * users a warning.
5231 *
5232 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
5233 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
5234 */
0765691e
MA		 5235 if (IS_AMD_CPU(env) &&
5236 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
5237 cs->nr_threads > 1 && !ht_warned) {
5238 warn_report("This family of AMD CPU doesn't support "
5239 "hyperthreading(%d)",
5240 cs->nr_threads);
5241 error_printf("Please configure -smp options properly"
5242 " or try enabling topoext feature.\n");
5243 ht_warned = true;
e48638fd
WH		 5244 }
5245
d3c64d6a
IM		 5246 x86_cpu_apic_realize(cpu, &local_err);
5247 if (local_err != NULL) {
5248 goto out;
5249 }
14a10fc3 5250 cpu_reset(cs);
2b6f294c 5251
4dc1f449 5252 xcc->parent_realize(dev, &local_err);
2001d0cd 5253
4dc1f449
IM		 5254out:
5255 if (local_err != NULL) {
5256 error_propagate(errp, local_err);
5257 return;
5258 }
7a059953
AF		 5259}
5260
c884776e
IM		 5261static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
5262{
5263 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 5264 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5265 Error *local_err = NULL;
c884776e
IM		 5266
5267#ifndef CONFIG_USER_ONLY
5268 cpu_remove_sync(CPU(dev));
5269 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
5270#endif
5271
5272 if (cpu->apic_state) {
5273 object_unparent(OBJECT(cpu->apic_state));
5274 cpu->apic_state = NULL;
5275 }
7bbc124e
LV		 5276
5277 xcc->parent_unrealize(dev, &local_err);
5278 if (local_err != NULL) {
5279 error_propagate(errp, local_err);
5280 return;
5281 }
c884776e
IM		 5282}
5283
38e5c119 5284typedef struct BitProperty {
a7b0ffac 5285 FeatureWord w;
38e5c119
EH		 5286 uint32_t mask;
5287} BitProperty;
5288
d7bce999
EB		 5289static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
5290 void *opaque, Error **errp)
38e5c119 5291{
a7b0ffac 5292 X86CPU *cpu = X86_CPU(obj);
38e5c119 5293 BitProperty *fp = opaque;
a7b0ffac
EH		 5294 uint32_t f = cpu->env.features[fp->w];
5295 bool value = (f & fp->mask) == fp->mask;
51e72bc1 5296 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 5297}
5298
d7bce999
EB		 5299static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
5300 void *opaque, Error **errp)
38e5c119
EH		 5301{
5302 DeviceState *dev = DEVICE(obj);
a7b0ffac 5303 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 5304 BitProperty *fp = opaque;
5305 Error *local_err = NULL;
5306 bool value;
5307
5308 if (dev->realized) {
5309 qdev_prop_set_after_realize(dev, name, errp);
5310 return;
5311 }
5312
51e72bc1 5313 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 5314 if (local_err) {
5315 error_propagate(errp, local_err);
5316 return;
5317 }
5318
5319 if (value) {
a7b0ffac 5320 cpu->env.features[fp->w] |= fp->mask;
38e5c119 5321 } else {
a7b0ffac 5322 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 5323 }
d4a606b3 5324 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 5325}
5326
5327static void x86_cpu_release_bit_prop(Object *obj, const char *name,
5328 void *opaque)
5329{
5330 BitProperty *prop = opaque;
5331 g_free(prop);
5332}
5333
5334/* Register a boolean property to get/set a single bit in a uint32_t field.
5335 *
5336 * The same property name can be registered multiple times to make it affect
5337 * multiple bits in the same FeatureWord. In that case, the getter will return
5338 * true only if all bits are set.
5339 */
5340static void x86_cpu_register_bit_prop(X86CPU *cpu,
5341 const char *prop_name,
a7b0ffac 5342 FeatureWord w,
38e5c119
EH		 5343 int bitnr)
5344{
5345 BitProperty *fp;
5346 ObjectProperty *op;
5347 uint32_t mask = (1UL << bitnr);
5348
5349 op = object_property_find(OBJECT(cpu), prop_name, NULL);
5350 if (op) {
5351 fp = op->opaque;
a7b0ffac 5352 assert(fp->w == w);
38e5c119
EH		 5353 fp->mask |= mask;
5354 } else {
5355 fp = g_new0(BitProperty, 1);
a7b0ffac 5356 fp->w = w;
38e5c119
EH		 5357 fp->mask = mask;
5358 object_property_add(OBJECT(cpu), prop_name, "bool",
5359 x86_cpu_get_bit_prop,
5360 x86_cpu_set_bit_prop,
5361 x86_cpu_release_bit_prop, fp, &error_abort);
5362 }
5363}
5364
5365static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
5366 FeatureWord w,
5367 int bitnr)
5368{
38e5c119 5369 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 5370 const char *name = fi->feat_names[bitnr];
38e5c119 5371
16d2fcaa 5372 if (!name) {
38e5c119
EH		 5373 return;
5374 }
5375
fc7dfd20
EH		 5376 /* Property names should use "-" instead of "_".
5377 * Old names containing underscores are registered as aliases
5378 * using object_property_add_alias()
5379 */
16d2fcaa
EH		 5380 assert(!strchr(name, '_'));
5381 /* aliases don't use "|" delimiters anymore, they are registered
5382 * manually using object_property_add_alias() */
5383 assert(!strchr(name, '|'));
a7b0ffac 5384 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 5385}
5386
d187e08d
AN		 5387static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
5388{
5389 X86CPU *cpu = X86_CPU(cs);
5390 CPUX86State *env = &cpu->env;
5391 GuestPanicInformation *panic_info = NULL;
5392
5e953812 5393 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 5394 panic_info = g_malloc0(sizeof(GuestPanicInformation));
5395
e8ed97a6 5396 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 5397
5e953812 5398 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 5399 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
5400 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
5401 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
5402 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
5403 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 5404 }
5405
5406 return panic_info;
5407}
5408static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
5409 const char *name, void *opaque,
5410 Error **errp)
5411{
5412 CPUState *cs = CPU(obj);
5413 GuestPanicInformation *panic_info;
5414
5415 if (!cs->crash_occurred) {
5416 error_setg(errp, "No crash occured");
5417 return;
5418 }
5419
5420 panic_info = x86_cpu_get_crash_info(cs);
5421 if (panic_info == NULL) {
5422 error_setg(errp, "No crash information");
5423 return;
5424 }
5425
5426 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
5427 errp);
5428 qapi_free_GuestPanicInformation(panic_info);
5429}
5430
de024815
AF		 5431static void x86_cpu_initfn(Object *obj)
5432{
55e5c285 5433 CPUState *cs = CPU(obj);
de024815 5434 X86CPU *cpu = X86_CPU(obj);
d940ee9b 5435 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 5436 CPUX86State *env = &cpu->env;
38e5c119 5437 FeatureWord w;
de024815 5438
c05efcb1 5439 cs->env_ptr = env;
71ad61d3
AF		 5440
5441 object_property_add(obj, "family", "int",
95b8519d 5442 x86_cpuid_version_get_family,
71ad61d3 5443 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 5444 object_property_add(obj, "model", "int",
67e30c83 5445 x86_cpuid_version_get_model,
c5291a4f 5446 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 5447 object_property_add(obj, "stepping", "int",
35112e41 5448 x86_cpuid_version_get_stepping,
036e2222 5449 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 5450 object_property_add_str(obj, "vendor",
5451 x86_cpuid_get_vendor,
5452 x86_cpuid_set_vendor, NULL);
938d4c25 5453 object_property_add_str(obj, "model-id",
63e886eb 5454 x86_cpuid_get_model_id,
938d4c25 5455 x86_cpuid_set_model_id, NULL);
89e48965
AF		 5456 object_property_add(obj, "tsc-frequency", "int",
5457 x86_cpuid_get_tsc_freq,
5458 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 5459 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
5460 x86_cpu_get_feature_words,
7e5292b5
EH		 5461 NULL, NULL, (void *)env->features, NULL);
5462 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
5463 x86_cpu_get_feature_words,
5464 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 5465
d187e08d
AN		 5466 object_property_add(obj, "crash-information", "GuestPanicInformation",
5467 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
5468
92067bf4 5469 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 5470
38e5c119
EH		 5471 for (w = 0; w < FEATURE_WORDS; w++) {
5472 int bitnr;
5473
5474 for (bitnr = 0; bitnr < 32; bitnr++) {
5475 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
5476 }
5477 }
5478
16d2fcaa
EH		 5479 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
5480 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
5481 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
5482 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
5483 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
5484 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
5485 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
5486
54b8dc7c
EH		 5487 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
5488 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
5489 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
5490 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
5491 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
5492 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
5493 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
5494 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
5495 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
5496 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
5497 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
5498 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
5499 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
5500 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
5501 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
5502 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
5503 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
5504 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
5505 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
5506 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
5507 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
5508
0bacd8b3
EH		 5509 if (xcc->cpu_def) {
5510 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
5511 }
de024815
AF		 5512}
5513
997395d3
IM		 5514static int64_t x86_cpu_get_arch_id(CPUState *cs)
5515{
5516 X86CPU *cpu = X86_CPU(cs);
997395d3 5517
7e72a45c 5518 return cpu->apic_id;
997395d3
IM		 5519}
5520
444d5590
AF		 5521static bool x86_cpu_get_paging_enabled(const CPUState *cs)
5522{
5523 X86CPU *cpu = X86_CPU(cs);
5524
5525 return cpu->env.cr[0] & CR0_PG_MASK;
5526}
5527
f45748f1
AF		 5528static void x86_cpu_set_pc(CPUState *cs, vaddr value)
5529{
5530 X86CPU *cpu = X86_CPU(cs);
5531
5532 cpu->env.eip = value;
5533}
5534
bdf7ae5b
AF		 5535static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
5536{
5537 X86CPU *cpu = X86_CPU(cs);
5538
5539 cpu->env.eip = tb->pc - tb->cs_base;
5540}
5541
92d5f1a4 5542int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 5543{
5544 X86CPU *cpu = X86_CPU(cs);
5545 CPUX86State *env = &cpu->env;
5546
92d5f1a4
PB		 5547#if !defined(CONFIG_USER_ONLY)
5548 if (interrupt_request & CPU_INTERRUPT_POLL) {
5549 return CPU_INTERRUPT_POLL;
5550 }
5551#endif
5552 if (interrupt_request & CPU_INTERRUPT_SIPI) {
5553 return CPU_INTERRUPT_SIPI;
5554 }
5555
5556 if (env->hflags2 & HF2_GIF_MASK) {
5557 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
5558 !(env->hflags & HF_SMM_MASK)) {
5559 return CPU_INTERRUPT_SMI;
5560 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
5561 !(env->hflags2 & HF2_NMI_MASK)) {
5562 return CPU_INTERRUPT_NMI;
5563 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
5564 return CPU_INTERRUPT_MCE;
5565 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
5566 (((env->hflags2 & HF2_VINTR_MASK) &&
5567 (env->hflags2 & HF2_HIF_MASK)) ||
5568 (!(env->hflags2 & HF2_VINTR_MASK) &&
5569 (env->eflags & IF_MASK &&
5570 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
5571 return CPU_INTERRUPT_HARD;
5572#if !defined(CONFIG_USER_ONLY)
5573 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
5574 (env->eflags & IF_MASK) &&
5575 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
5576 return CPU_INTERRUPT_VIRQ;
5577#endif
5578 }
5579 }
5580
5581 return 0;
5582}
5583
5584static bool x86_cpu_has_work(CPUState *cs)
5585{
5586 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 5587}
5588
f50f3dd5
RH		 5589static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
5590{
5591 X86CPU *cpu = X86_CPU(cs);
5592 CPUX86State *env = &cpu->env;
5593
5594 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
5595 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
5596 : bfd_mach_i386_i8086);
5597 info->print_insn = print_insn_i386;
b666d2a4
RH		 5598
5599 info->cap_arch = CS_ARCH_X86;
5600 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
5601 : env->hflags & HF_CS32_MASK ? CS_MODE_32
5602 : CS_MODE_16);
15fa1a0a
RH		 5603 info->cap_insn_unit = 1;
5604 info->cap_insn_split = 8;
f50f3dd5
RH		 5605}
5606
35b1b927
TW		 5607void x86_update_hflags(CPUX86State *env)
5608{
5609 uint32_t hflags;
5610#define HFLAG_COPY_MASK \
5611 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5612 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5613 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5614 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5615
5616 hflags = env->hflags & HFLAG_COPY_MASK;
5617 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5618 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5619 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5620 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5621 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5622
5623 if (env->cr[4] & CR4_OSFXSR_MASK) {
5624 hflags |= HF_OSFXSR_MASK;
5625 }
5626
5627 if (env->efer & MSR_EFER_LMA) {
5628 hflags |= HF_LMA_MASK;
5629 }
5630
5631 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5632 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5633 } else {
5634 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5635 (DESC_B_SHIFT - HF_CS32_SHIFT);
5636 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5637 (DESC_B_SHIFT - HF_SS32_SHIFT);
5638 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5639 !(hflags & HF_CS32_MASK)) {
5640 hflags |= HF_ADDSEG_MASK;
5641 } else {
5642 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5643 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5644 }
5645 }
5646 env->hflags = hflags;
5647}
5648
9337e3b6 5649static Property x86_cpu_properties[] = {
2da00e31
IM		 5650#ifdef CONFIG_USER_ONLY
5651 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5652 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 5653 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5654 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5655 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 5656#else
5657 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 5658 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5659 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5660 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 5661#endif
15f8b142 5662 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 5663 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 5664 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 5665 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 5666 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 5667 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 5668 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 5669 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 5670 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 5671 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 5672 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 5673 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
9445597b 5674 DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
ba6a4fd9 5675 DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment, false),
47512009 5676 DEFINE_PROP_BOOL("hv-tlbflush", X86CPU, hyperv_tlbflush, false),
6b7a9830 5677 DEFINE_PROP_BOOL("hv-ipi", X86CPU, hyperv_ipi, false),
15e41345 5678 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 5679 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 5680 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 5681 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 5682 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 5683 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 5684 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5685 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5686 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5687 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5688 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5689 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5690 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 5691 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 5692 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 5693 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 5694 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 5695 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5696 false),
0b564e6f 5697 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 5698 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 5699 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
5700 true),
ab8f992e 5701 /*
a9f27ea9
EH		 5702 * lecacy_cache defaults to true unless the CPU model provides its
5703 * own cache information (see x86_cpu_load_def()).
ab8f992e 5704 */
a9f27ea9 5705 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 5706
5707 /*
5708 * From "Requirements for Implementing the Microsoft
5709 * Hypervisor Interface":
5710 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5711 *
5712 * "Starting with Windows Server 2012 and Windows 8, if
5713 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5714 * the hypervisor imposes no specific limit to the number of VPs.
5715 * In this case, Windows Server 2012 guest VMs may use more than
5716 * 64 VPs, up to the maximum supported number of processors applicable
5717 * to the specific Windows version being used."
5718 */
5719 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 5720 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
5721 false),
9337e3b6
EH		 5722 DEFINE_PROP_END_OF_LIST()
5723};
5724
5fd2087a
AF		 5725static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5726{
5727 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5728 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 5729 DeviceClass *dc = DEVICE_CLASS(oc);
5730
bf853881
PMD		 5731 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5732 &xcc->parent_realize);
5733 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5734 &xcc->parent_unrealize);
9337e3b6 5735 dc->props = x86_cpu_properties;
5fd2087a
AF		 5736
5737 xcc->parent_reset = cc->reset;
5738 cc->reset = x86_cpu_reset;
91b1df8c 5739 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 5740
500050d1 5741 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 5742 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 5743 cc->has_work = x86_cpu_has_work;
79c664f6 5744#ifdef CONFIG_TCG
97a8ea5a 5745 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 5746 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 5747#endif
878096ee 5748 cc->dump_state = x86_cpu_dump_state;
c86f106b 5749 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 5750 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 5751 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 5752 cc->gdb_read_register = x86_cpu_gdb_read_register;
5753 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 5754 cc->get_arch_id = x86_cpu_get_arch_id;
5755 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 5756#ifdef CONFIG_USER_ONLY
5757 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
5758#else
f8c45c65 5759 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 5760 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 5761 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 5762 cc->write_elf64_note = x86_cpu_write_elf64_note;
5763 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5764 cc->write_elf32_note = x86_cpu_write_elf32_note;
5765 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 5766 cc->vmsd = &vmstate_x86_cpu;
c72bf468 5767#endif
00fcd100
AB		 5768 cc->gdb_arch_name = x86_gdb_arch_name;
5769#ifdef TARGET_X86_64
b8158192
AB		 5770 cc->gdb_core_xml_file = "i386-64bit.xml";
5771 cc->gdb_num_core_regs = 57;
00fcd100 5772#else
b8158192
AB		 5773 cc->gdb_core_xml_file = "i386-32bit.xml";
5774 cc->gdb_num_core_regs = 41;
00fcd100 5775#endif
79c664f6 5776#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 5777 cc->debug_excp_handler = breakpoint_handler;
5778#endif
374e0cd4
RH		 5779 cc->cpu_exec_enter = x86_cpu_exec_enter;
5780 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 5781#ifdef CONFIG_TCG
55c3ceef 5782 cc->tcg_initialize = tcg_x86_init;
74d7fc7f 5783#endif
f50f3dd5 5784 cc->disas_set_info = x86_disas_set_info;
4c315c27 5785
e90f2a8c 5786 dc->user_creatable = true;
5fd2087a
AF		 5787}
5788
5789static const TypeInfo x86_cpu_type_info = {
5790 .name = TYPE_X86_CPU,
5791 .parent = TYPE_CPU,
5792 .instance_size = sizeof(X86CPU),
de024815 5793 .instance_init = x86_cpu_initfn,
d940ee9b 5794 .abstract = true,
5fd2087a
AF		 5795 .class_size = sizeof(X86CPUClass),
5796 .class_init = x86_cpu_common_class_init,
5797};
5798
5adbed30
EH		 5799
5800/* "base" CPU model, used by query-cpu-model-expansion */
5801static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
5802{
5803 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5804
5805 xcc->static_model = true;
5806 xcc->migration_safe = true;
5807 xcc->model_description = "base CPU model type with no features enabled";
5808 xcc->ordering = 8;
5809}
5810
5811static const TypeInfo x86_base_cpu_type_info = {
5812 .name = X86_CPU_TYPE_NAME("base"),
5813 .parent = TYPE_X86_CPU,
5814 .class_init = x86_cpu_base_class_init,
5815};
5816
5fd2087a
AF		 5817static void x86_cpu_register_types(void)
5818{
d940ee9b
EH		 5819 int i;
5820
5fd2087a 5821 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 5822 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
5823 x86_register_cpudef_type(&builtin_x86_defs[i]);
5824 }
c62f2630 5825 type_register_static(&max_x86_cpu_type_info);
5adbed30 5826 type_register_static(&x86_base_cpu_type_info);
d6dcc558 5827#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 5828 type_register_static(&host_x86_cpu_type_info);
5829#endif
5fd2087a
AF		 5830}
5831
5832type_init(x86_cpu_register_types)
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