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x86: Data structure changes to support MSR based features
[mirror_qemu.git] / target / i386 / cpu.c
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c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
631be321 23#include "qemu/bitops.h"
c6dc6f63
AP		 24
25#include "cpu.h"
63c91552 26#include "exec/exec-all.h"
9c17d615 27#include "sysemu/kvm.h"
d6dcc558 28#include "sysemu/hvf.h"
8932cfdf 29#include "sysemu/cpus.h"
50a2c6e5 30#include "kvm_i386.h"
6cb8f2a6 31#include "sev_i386.h"
c6dc6f63 32
d49b6836 33#include "qemu/error-report.h"
1de7afc9
PB		 34#include "qemu/option.h"
35#include "qemu/config-file.h"
e688df6b 36#include "qapi/error.h"
112ed241
MA		 37#include "qapi/qapi-visit-misc.h"
38#include "qapi/qapi-visit-run-state.h"
452fcdbc 39#include "qapi/qmp/qdict.h"
7b1b5d19 40#include "qapi/qmp/qerror.h"
7b1b5d19 41#include "qapi/visitor.h"
f99fd7ca 42#include "qom/qom-qobject.h"
9c17d615 43#include "sysemu/arch_init.h"
71ad61d3 44
1814eab6 45#include "standard-headers/asm-x86/kvm_para.h"
65dee380 46
9c17d615 47#include "sysemu/sysemu.h"
53a89e26 48#include "hw/qdev-properties.h"
5232d00a 49#include "hw/i386/topology.h"
bdeec802 50#ifndef CONFIG_USER_ONLY
2001d0cd 51#include "exec/address-spaces.h"
741da0d3 52#include "hw/hw.h"
0d09e41a 53#include "hw/xen/xen.h"
0d09e41a 54#include "hw/i386/apic_internal.h"
bdeec802
IM		 55#endif
56
b666d2a4
RH		 57#include "disas/capstone.h"
58
7e3482f8
EH		 59/* Helpers for building CPUID[2] descriptors: */
60
61struct CPUID2CacheDescriptorInfo {
62 enum CacheType type;
63 int level;
64 int size;
65 int line_size;
66 int associativity;
67};
5e891bf8 68
7e3482f8
EH		 69/*
70 * Known CPUID 2 cache descriptors.
71 * From Intel SDM Volume 2A, CPUID instruction
72 */
73struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 74 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 75 .associativity = 4, .line_size = 32, },
5f00335a 76 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 77 .associativity = 4, .line_size = 32, },
5f00335a 78 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 79 .associativity = 4, .line_size = 64, },
5f00335a 80 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 81 .associativity = 2, .line_size = 32, },
5f00335a 82 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 83 .associativity = 4, .line_size = 32, },
5f00335a 84 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 85 .associativity = 4, .line_size = 64, },
5f00335a 86 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 87 .associativity = 6, .line_size = 64, },
5f00335a 88 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 89 .associativity = 2, .line_size = 64, },
5f00335a 90 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 91 .associativity = 8, .line_size = 64, },
92 /* lines per sector is not supported cpuid2_cache_descriptor(),
93 * so descriptors 0x22, 0x23 are not included
94 */
5f00335a 95 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 96 .associativity = 16, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x25, 0x20 are not included
99 */
5f00335a 100 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 101 .associativity = 8, .line_size = 64, },
5f00335a 102 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 103 .associativity = 8, .line_size = 64, },
5f00335a 104 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 105 .associativity = 4, .line_size = 32, },
5f00335a 106 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 107 .associativity = 4, .line_size = 32, },
5f00335a 108 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 109 .associativity = 4, .line_size = 32, },
5f00335a 110 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 111 .associativity = 4, .line_size = 32, },
5f00335a 112 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 113 .associativity = 4, .line_size = 32, },
5f00335a 114 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 115 .associativity = 4, .line_size = 64, },
5f00335a 116 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 117 .associativity = 8, .line_size = 64, },
5f00335a 118 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 119 .associativity = 12, .line_size = 64, },
120 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 121 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 122 .associativity = 12, .line_size = 64, },
5f00335a 123 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 124 .associativity = 16, .line_size = 64, },
5f00335a 125 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 126 .associativity = 12, .line_size = 64, },
5f00335a 127 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 128 .associativity = 16, .line_size = 64, },
5f00335a 129 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 130 .associativity = 24, .line_size = 64, },
5f00335a 131 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 132 .associativity = 8, .line_size = 64, },
5f00335a 133 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 134 .associativity = 4, .line_size = 64, },
5f00335a 135 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 136 .associativity = 4, .line_size = 64, },
5f00335a 137 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 138 .associativity = 4, .line_size = 64, },
5f00335a 139 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 140 .associativity = 4, .line_size = 64, },
141 /* lines per sector is not supported cpuid2_cache_descriptor(),
142 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
143 */
5f00335a 144 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 145 .associativity = 8, .line_size = 64, },
5f00335a 146 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 147 .associativity = 2, .line_size = 64, },
5f00335a 148 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 149 .associativity = 8, .line_size = 64, },
5f00335a 150 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 151 .associativity = 8, .line_size = 32, },
5f00335a 152 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 153 .associativity = 8, .line_size = 32, },
5f00335a 154 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 155 .associativity = 8, .line_size = 32, },
5f00335a 156 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 157 .associativity = 8, .line_size = 32, },
5f00335a 158 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 159 .associativity = 4, .line_size = 64, },
5f00335a 160 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 161 .associativity = 8, .line_size = 64, },
5f00335a 162 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 163 .associativity = 4, .line_size = 64, },
5f00335a 164 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 165 .associativity = 4, .line_size = 64, },
5f00335a 166 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 167 .associativity = 4, .line_size = 64, },
5f00335a 168 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 169 .associativity = 8, .line_size = 64, },
5f00335a 170 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 171 .associativity = 8, .line_size = 64, },
5f00335a 172 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 173 .associativity = 8, .line_size = 64, },
5f00335a 174 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 175 .associativity = 12, .line_size = 64, },
5f00335a 176 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 177 .associativity = 12, .line_size = 64, },
5f00335a 178 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 179 .associativity = 12, .line_size = 64, },
5f00335a 180 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 181 .associativity = 16, .line_size = 64, },
5f00335a 182 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 183 .associativity = 16, .line_size = 64, },
5f00335a 184 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 185 .associativity = 16, .line_size = 64, },
5f00335a 186 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 187 .associativity = 24, .line_size = 64, },
5f00335a 188 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 189 .associativity = 24, .line_size = 64, },
5f00335a 190 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 191 .associativity = 24, .line_size = 64, },
192};
193
194/*
195 * "CPUID leaf 2 does not report cache descriptor information,
196 * use CPUID leaf 4 to query cache parameters"
197 */
198#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 199
7e3482f8
EH		 200/*
201 * Return a CPUID 2 cache descriptor for a given cache.
202 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
203 */
204static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
205{
206 int i;
207
208 assert(cache->size > 0);
209 assert(cache->level > 0);
210 assert(cache->line_size > 0);
211 assert(cache->associativity > 0);
212 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
213 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
214 if (d->level == cache->level && d->type == cache->type &&
215 d->size == cache->size && d->line_size == cache->line_size &&
216 d->associativity == cache->associativity) {
217 return i;
218 }
219 }
5e891bf8 220
7e3482f8
EH		 221 return CACHE_DESCRIPTOR_UNAVAILABLE;
222}
5e891bf8
EH		 223
224/* CPUID Leaf 4 constants: */
225
226/* EAX: */
7e3482f8
EH		 227#define CACHE_TYPE_D 1
228#define CACHE_TYPE_I 2
229#define CACHE_TYPE_UNIFIED 3
5e891bf8 230
7e3482f8 231#define CACHE_LEVEL(l) (l << 5)
5e891bf8 232
7e3482f8 233#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 234
235/* EDX: */
7e3482f8
EH		 236#define CACHE_NO_INVD_SHARING (1 << 0)
237#define CACHE_INCLUSIVE (1 << 1)
238#define CACHE_COMPLEX_IDX (1 << 2)
239
240/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 241#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
242 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
243 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
244 0 /* Invalid value */)
7e3482f8
EH		 245
246
247/* Encode cache info for CPUID[4] */
248static void encode_cache_cpuid4(CPUCacheInfo *cache,
249 int num_apic_ids, int num_cores,
250 uint32_t *eax, uint32_t *ebx,
251 uint32_t *ecx, uint32_t *edx)
252{
253 assert(cache->size == cache->line_size * cache->associativity *
254 cache->partitions * cache->sets);
255
256 assert(num_apic_ids > 0);
257 *eax = CACHE_TYPE(cache->type) |
258 CACHE_LEVEL(cache->level) |
259 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
260 ((num_cores - 1) << 26) |
261 ((num_apic_ids - 1) << 14);
262
263 assert(cache->line_size > 0);
264 assert(cache->partitions > 0);
265 assert(cache->associativity > 0);
266 /* We don't implement fully-associative caches */
267 assert(cache->associativity < cache->sets);
268 *ebx = (cache->line_size - 1) |
269 ((cache->partitions - 1) << 12) |
270 ((cache->associativity - 1) << 22);
271
272 assert(cache->sets > 0);
273 *ecx = cache->sets - 1;
274
275 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
276 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
277 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
278}
279
280/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
281static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
282{
283 assert(cache->size % 1024 == 0);
284 assert(cache->lines_per_tag > 0);
285 assert(cache->associativity > 0);
286 assert(cache->line_size > 0);
287 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
288 (cache->lines_per_tag << 8) | (cache->line_size);
289}
5e891bf8
EH		 290
291#define ASSOC_FULL 0xFF
292
293/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
294#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
295 a == 2 ? 0x2 : \
296 a == 4 ? 0x4 : \
297 a == 8 ? 0x6 : \
298 a == 16 ? 0x8 : \
299 a == 32 ? 0xA : \
300 a == 48 ? 0xB : \
301 a == 64 ? 0xC : \
302 a == 96 ? 0xD : \
303 a == 128 ? 0xE : \
304 a == ASSOC_FULL ? 0xF : \
305 0 /* invalid value */)
306
7e3482f8
EH		 307/*
308 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
309 * @l3 can be NULL.
310 */
311static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
312 CPUCacheInfo *l3,
313 uint32_t *ecx, uint32_t *edx)
314{
315 assert(l2->size % 1024 == 0);
316 assert(l2->associativity > 0);
317 assert(l2->lines_per_tag > 0);
318 assert(l2->line_size > 0);
319 *ecx = ((l2->size / 1024) << 16) |
320 (AMD_ENC_ASSOC(l2->associativity) << 12) |
321 (l2->lines_per_tag << 8) | (l2->line_size);
322
323 if (l3) {
324 assert(l3->size % (512 * 1024) == 0);
325 assert(l3->associativity > 0);
326 assert(l3->lines_per_tag > 0);
327 assert(l3->line_size > 0);
328 *edx = ((l3->size / (512 * 1024)) << 18) |
329 (AMD_ENC_ASSOC(l3->associativity) << 12) |
330 (l3->lines_per_tag << 8) | (l3->line_size);
331 } else {
332 *edx = 0;
333 }
334}
5e891bf8 335
8f4202fb
BM		 336/*
337 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
338 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
339 * Define the constants to build the cpu topology. Right now, TOPOEXT
340 * feature is enabled only on EPYC. So, these constants are based on
341 * EPYC supported configurations. We may need to handle the cases if
342 * these values change in future.
343 */
344/* Maximum core complexes in a node */
345#define MAX_CCX 2
346/* Maximum cores in a core complex */
347#define MAX_CORES_IN_CCX 4
348/* Maximum cores in a node */
349#define MAX_CORES_IN_NODE 8
350/* Maximum nodes in a socket */
351#define MAX_NODES_PER_SOCKET 4
352
353/*
354 * Figure out the number of nodes required to build this config.
355 * Max cores in a node is 8
356 */
357static int nodes_in_socket(int nr_cores)
358{
359 int nodes;
360
361 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
362
363 /* Hardware does not support config with 3 nodes, return 4 in that case */
364 return (nodes == 3) ? 4 : nodes;
365}
366
367/*
368 * Decide the number of cores in a core complex with the given nr_cores using
369 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
370 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
371 * L3 cache is shared across all cores in a core complex. So, this will also
372 * tell us how many cores are sharing the L3 cache.
373 */
374static int cores_in_core_complex(int nr_cores)
375{
376 int nodes;
377
378 /* Check if we can fit all the cores in one core complex */
379 if (nr_cores <= MAX_CORES_IN_CCX) {
380 return nr_cores;
381 }
382 /* Get the number of nodes required to build this config */
383 nodes = nodes_in_socket(nr_cores);
384
385 /*
386 * Divide the cores accros all the core complexes
387 * Return rounded up value
388 */
389 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
390}
391
392/* Encode cache info for CPUID[8000001D] */
393static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
394 uint32_t *eax, uint32_t *ebx,
395 uint32_t *ecx, uint32_t *edx)
396{
397 uint32_t l3_cores;
398 assert(cache->size == cache->line_size * cache->associativity *
399 cache->partitions * cache->sets);
400
401 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
402 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
403
404 /* L3 is shared among multiple cores */
405 if (cache->level == 3) {
406 l3_cores = cores_in_core_complex(cs->nr_cores);
407 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
408 } else {
409 *eax |= ((cs->nr_threads - 1) << 14);
410 }
411
412 assert(cache->line_size > 0);
413 assert(cache->partitions > 0);
414 assert(cache->associativity > 0);
415 /* We don't implement fully-associative caches */
416 assert(cache->associativity < cache->sets);
417 *ebx = (cache->line_size - 1) |
418 ((cache->partitions - 1) << 12) |
419 ((cache->associativity - 1) << 22);
420
421 assert(cache->sets > 0);
422 *ecx = cache->sets - 1;
423
424 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
425 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
426 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
427}
428
ed78467a
BM		 429/* Data structure to hold the configuration info for a given core index */
430struct core_topology {
431 /* core complex id of the current core index */
432 int ccx_id;
433 /*
434 * Adjusted core index for this core in the topology
435 * This can be 0,1,2,3 with max 4 cores in a core complex
436 */
437 int core_id;
438 /* Node id for this core index */
439 int node_id;
440 /* Number of nodes in this config */
441 int num_nodes;
442};
443
444/*
445 * Build the configuration closely match the EPYC hardware. Using the EPYC
446 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
447 * right now. This could change in future.
448 * nr_cores : Total number of cores in the config
449 * core_id : Core index of the current CPU
450 * topo : Data structure to hold all the config info for this core index
451 */
452static void build_core_topology(int nr_cores, int core_id,
453 struct core_topology *topo)
454{
455 int nodes, cores_in_ccx;
456
457 /* First get the number of nodes required */
458 nodes = nodes_in_socket(nr_cores);
459
460 cores_in_ccx = cores_in_core_complex(nr_cores);
461
462 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
463 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
464 topo->core_id = core_id % cores_in_ccx;
465 topo->num_nodes = nodes;
466}
467
468/* Encode cache info for CPUID[8000001E] */
469static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
470 uint32_t *eax, uint32_t *ebx,
471 uint32_t *ecx, uint32_t *edx)
472{
473 struct core_topology topo = {0};
631be321
BM		 474 unsigned long nodes;
475 int shift;
ed78467a
BM		 476
477 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
478 *eax = cpu->apic_id;
479 /*
480 * CPUID_Fn8000001E_EBX
481 * 31:16 Reserved
482 * 15:8 Threads per core (The number of threads per core is
483 * Threads per core + 1)
484 * 7:0 Core id (see bit decoding below)
485 * SMT:
486 * 4:3 node id
487 * 2 Core complex id
488 * 1:0 Core id
489 * Non SMT:
490 * 5:4 node id
491 * 3 Core complex id
492 * 1:0 Core id
493 */
494 if (cs->nr_threads - 1) {
495 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
496 (topo.ccx_id << 2) | topo.core_id;
497 } else {
498 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
499 }
500 /*
501 * CPUID_Fn8000001E_ECX
502 * 31:11 Reserved
503 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
504 * 7:0 Node id (see bit decoding below)
505 * 2 Socket id
506 * 1:0 Node id
507 */
631be321
BM		 508 if (topo.num_nodes <= 4) {
509 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
510 topo.node_id;
511 } else {
512 /*
513 * Node id fix up. Actual hardware supports up to 4 nodes. But with
514 * more than 32 cores, we may end up with more than 4 nodes.
515 * Node id is a combination of socket id and node id. Only requirement
516 * here is that this number should be unique accross the system.
517 * Shift the socket id to accommodate more nodes. We dont expect both
518 * socket id and node id to be big number at the same time. This is not
519 * an ideal config but we need to to support it. Max nodes we can have
520 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
521 * 5 bits for nodes. Find the left most set bit to represent the total
522 * number of nodes. find_last_bit returns last set bit(0 based). Left
523 * shift(+1) the socket id to represent all the nodes.
524 */
525 nodes = topo.num_nodes - 1;
526 shift = find_last_bit(&nodes, 8);
527 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
528 topo.node_id;
529 }
ed78467a
BM		 530 *edx = 0;
531}
532
ab8f992e
BM		 533/*
534 * Definitions of the hardcoded cache entries we expose:
535 * These are legacy cache values. If there is a need to change any
536 * of these values please use builtin_x86_defs
537 */
5e891bf8
EH		 538
539/* L1 data cache: */
ab8f992e 540static CPUCacheInfo legacy_l1d_cache = {
5f00335a 541 .type = DATA_CACHE,
7e3482f8
EH		 542 .level = 1,
543 .size = 32 * KiB,
544 .self_init = 1,
545 .line_size = 64,
546 .associativity = 8,
547 .sets = 64,
548 .partitions = 1,
549 .no_invd_sharing = true,
550};
551
5e891bf8 552/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 553static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 554 .type = DATA_CACHE,
7e3482f8
EH		 555 .level = 1,
556 .size = 64 * KiB,
557 .self_init = 1,
558 .line_size = 64,
559 .associativity = 2,
560 .sets = 512,
561 .partitions = 1,
562 .lines_per_tag = 1,
563 .no_invd_sharing = true,
564};
5e891bf8
EH		 565
566/* L1 instruction cache: */
ab8f992e 567static CPUCacheInfo legacy_l1i_cache = {
5f00335a 568 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 569 .level = 1,
570 .size = 32 * KiB,
571 .self_init = 1,
572 .line_size = 64,
573 .associativity = 8,
574 .sets = 64,
575 .partitions = 1,
576 .no_invd_sharing = true,
577};
578
5e891bf8 579/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 580static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 581 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 582 .level = 1,
583 .size = 64 * KiB,
584 .self_init = 1,
585 .line_size = 64,
586 .associativity = 2,
587 .sets = 512,
588 .partitions = 1,
589 .lines_per_tag = 1,
590 .no_invd_sharing = true,
591};
5e891bf8
EH		 592
593/* Level 2 unified cache: */
ab8f992e 594static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 595 .type = UNIFIED_CACHE,
596 .level = 2,
597 .size = 4 * MiB,
598 .self_init = 1,
599 .line_size = 64,
600 .associativity = 16,
601 .sets = 4096,
602 .partitions = 1,
603 .no_invd_sharing = true,
604};
605
5e891bf8 606/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 607static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 608 .type = UNIFIED_CACHE,
609 .level = 2,
610 .size = 2 * MiB,
611 .line_size = 64,
612 .associativity = 8,
613};
614
615
5e891bf8 616/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 617static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 618 .type = UNIFIED_CACHE,
619 .level = 2,
620 .size = 512 * KiB,
621 .line_size = 64,
622 .lines_per_tag = 1,
623 .associativity = 16,
624 .sets = 512,
625 .partitions = 1,
626};
5e891bf8 627
14c985cf 628/* Level 3 unified cache: */
ab8f992e 629static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 630 .type = UNIFIED_CACHE,
631 .level = 3,
632 .size = 16 * MiB,
633 .line_size = 64,
634 .associativity = 16,
635 .sets = 16384,
636 .partitions = 1,
637 .lines_per_tag = 1,
638 .self_init = true,
639 .inclusive = true,
640 .complex_indexing = true,
641};
5e891bf8
EH		 642
643/* TLB definitions: */
644
645#define L1_DTLB_2M_ASSOC 1
646#define L1_DTLB_2M_ENTRIES 255
647#define L1_DTLB_4K_ASSOC 1
648#define L1_DTLB_4K_ENTRIES 255
649
650#define L1_ITLB_2M_ASSOC 1
651#define L1_ITLB_2M_ENTRIES 255
652#define L1_ITLB_4K_ASSOC 1
653#define L1_ITLB_4K_ENTRIES 255
654
655#define L2_DTLB_2M_ASSOC 0 /* disabled */
656#define L2_DTLB_2M_ENTRIES 0 /* disabled */
657#define L2_DTLB_4K_ASSOC 4
658#define L2_DTLB_4K_ENTRIES 512
659
660#define L2_ITLB_2M_ASSOC 0 /* disabled */
661#define L2_ITLB_2M_ENTRIES 0 /* disabled */
662#define L2_ITLB_4K_ASSOC 4
663#define L2_ITLB_4K_ENTRIES 512
664
e37a5c7f
CP		 665/* CPUID Leaf 0x14 constants: */
666#define INTEL_PT_MAX_SUBLEAF 0x1
667/*
668 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
669 * MSR can be accessed;
670 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
671 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
672 * of Intel PT MSRs across warm reset;
673 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
674 */
675#define INTEL_PT_MINIMAL_EBX 0xf
676/*
677 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
678 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
679 * accessed;
680 * bit[01]: ToPA tables can hold any number of output entries, up to the
681 * maximum allowed by the MaskOrTableOffset field of
682 * IA32_RTIT_OUTPUT_MASK_PTRS;
683 * bit[02]: Support Single-Range Output scheme;
684 */
685#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 686/* generated packets which contain IP payloads have LIP values */
687#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 688#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
689#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
690#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
691#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
692#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 693
99b88a17
IM		 694static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
695 uint32_t vendor2, uint32_t vendor3)
696{
697 int i;
698 for (i = 0; i < 4; i++) {
699 dst[i] = vendor1 >> (8 * i);
700 dst[i + 4] = vendor2 >> (8 * i);
701 dst[i + 8] = vendor3 >> (8 * i);
702 }
703 dst[CPUID_VENDOR_SZ] = '\0';
704}
705
621626ce
EH		 706#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
707#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
708 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
709#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
710 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
711 CPUID_PSE36 | CPUID_FXSR)
712#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
713#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
714 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
715 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
716 CPUID_PAE | CPUID_SEP | CPUID_APIC)
717
718#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
719 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
720 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
721 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 722 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 723 /* partly implemented:
724 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
725 /* missing:
726 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
727#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
728 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
729 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 730 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 731 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
732 /* missing:
733 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
734 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
735 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 736 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
737 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 738
739#ifdef TARGET_X86_64
740#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
741#else
742#define TCG_EXT2_X86_64_FEATURES 0
743#endif
744
745#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
746 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
747 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
748 TCG_EXT2_X86_64_FEATURES)
749#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
750 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
751#define TCG_EXT4_FEATURES 0
fe441054 752#define TCG_SVM_FEATURES CPUID_SVM_NPT
621626ce
EH		 753#define TCG_KVM_FEATURES 0
754#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 755 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
756 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 757 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
758 CPUID_7_0_EBX_ERMS)
621626ce 759 /* missing:
07929f2a 760 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 761 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 762 CPUID_7_0_EBX_RDSEED */
9ccb9784
EH		 763#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
764 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
6c7c3c21 765 CPUID_7_0_ECX_LA57)
95ea69fb 766#define TCG_7_0_EDX_FEATURES 0
303752a9 767#define TCG_APM_FEATURES 0
28b8e4d0 768#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 769#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
770 /* missing:
771 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 772
07585923
RH		 773typedef enum FeatureWordType {
774 CPUID_FEATURE_WORD,
775 MSR_FEATURE_WORD,
776} FeatureWordType;
777
5ef57876 778typedef struct FeatureWordInfo {
07585923 779 FeatureWordType type;
2d5312da
EH		 780 /* feature flags names are taken from "Intel Processor Identification and
781 * the CPUID Instruction" and AMD's "CPUID Specification".
782 * In cases of disagreement between feature naming conventions,
783 * aliases may be added.
784 */
785 const char *feat_names[32];
07585923
RH		 786 union {
787 /* If type==CPUID_FEATURE_WORD */
788 struct {
789 uint32_t eax; /* Input EAX for CPUID */
790 bool needs_ecx; /* CPUID instruction uses ECX as input */
791 uint32_t ecx; /* Input ECX value for CPUID */
792 int reg; /* output register (R_* constant) */
793 } cpuid;
794 /* If type==MSR_FEATURE_WORD */
795 struct {
796 uint32_t index;
797 struct { /*CPUID that enumerate this MSR*/
798 FeatureWord cpuid_class;
799 uint32_t cpuid_flag;
800 } cpuid_dep;
801 } msr;
802 };
37ce3522 803 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 804 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 805 uint32_t migratable_flags; /* Feature flags known to be migratable */
0d914f39
EH		 806 /* Features that shouldn't be auto-enabled by "-cpu host" */
807 uint32_t no_autoenable_flags;
5ef57876
EH		 808} FeatureWordInfo;
809
810static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 811 [FEAT_1_EDX] = {
07585923 812 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 813 .feat_names = {
814 "fpu", "vme", "de", "pse",
815 "tsc", "msr", "pae", "mce",
816 "cx8", "apic", NULL, "sep",
817 "mtrr", "pge", "mca", "cmov",
818 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
819 NULL, "ds" /* Intel dts */, "acpi", "mmx",
820 "fxsr", "sse", "sse2", "ss",
821 "ht" /* Intel htt */, "tm", "ia64", "pbe",
822 },
07585923 823 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 824 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 825 },
826 [FEAT_1_ECX] = {
07585923 827 .type = CPUID_FEATURE_WORD,
2d5312da 828 .feat_names = {
16d2fcaa 829 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 830 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 831 "tm2", "ssse3", "cid", NULL,
832 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 833 NULL, "pcid", "dca", "sse4.1",
834 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 835 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 836 "avx", "f16c", "rdrand", "hypervisor",
837 },
07585923 838 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 839 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 840 },
2d5312da
EH		 841 /* Feature names that are already defined on feature_name[] but
842 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
843 * names on feat_names below. They are copied automatically
844 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
845 */
bffd67b0 846 [FEAT_8000_0001_EDX] = {
07585923 847 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 848 .feat_names = {
849 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
850 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
851 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
852 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
853 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 854 "nx", NULL, "mmxext", NULL /* mmx */,
855 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
856 NULL, "lm", "3dnowext", "3dnow",
2d5312da 857 },
07585923 858 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 859 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 860 },
861 [FEAT_8000_0001_ECX] = {
07585923 862 .type = CPUID_FEATURE_WORD,
2d5312da 863 .feat_names = {
fc7dfd20 864 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 865 "cr8legacy", "abm", "sse4a", "misalignsse",
866 "3dnowprefetch", "osvw", "ibs", "xop",
867 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 868 "fma4", "tce", NULL, "nodeid-msr",
869 NULL, "tbm", "topoext", "perfctr-core",
870 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 871 NULL, NULL, NULL, NULL,
872 },
07585923 873 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 874 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 875 /*
876 * TOPOEXT is always allowed but can't be enabled blindly by
877 * "-cpu host", as it requires consistent cache topology info
878 * to be provided so it doesn't confuse guests.
879 */
880 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 881 },
89e49c8b 882 [FEAT_C000_0001_EDX] = {
07585923 883 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 884 .feat_names = {
885 NULL, NULL, "xstore", "xstore-en",
886 NULL, NULL, "xcrypt", "xcrypt-en",
887 "ace2", "ace2-en", "phe", "phe-en",
888 "pmm", "pmm-en", NULL, NULL,
889 NULL, NULL, NULL, NULL,
890 NULL, NULL, NULL, NULL,
891 NULL, NULL, NULL, NULL,
892 NULL, NULL, NULL, NULL,
893 },
07585923 894 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 895 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 896 },
bffd67b0 897 [FEAT_KVM] = {
07585923 898 .type = CPUID_FEATURE_WORD,
2d5312da 899 .feat_names = {
fc7dfd20
EH		 900 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
901 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 902 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
2d5312da
EH		 903 NULL, NULL, NULL, NULL,
904 NULL, NULL, NULL, NULL,
905 NULL, NULL, NULL, NULL,
906 "kvmclock-stable-bit", NULL, NULL, NULL,
907 NULL, NULL, NULL, NULL,
908 },
07585923 909 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 910 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 911 },
be777326 912 [FEAT_KVM_HINTS] = {
07585923 913 .type = CPUID_FEATURE_WORD,
be777326
WL		 914 .feat_names = {
915 "kvm-hint-dedicated", NULL, NULL, NULL,
916 NULL, NULL, NULL, NULL,
917 NULL, NULL, NULL, NULL,
918 NULL, NULL, NULL, NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 },
07585923 924 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 925 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 926 /*
927 * KVM hints aren't auto-enabled by -cpu host, they need to be
928 * explicitly enabled in the command-line.
929 */
930 .no_autoenable_flags = ~0U,
be777326 931 },
c35bd19a 932 [FEAT_HYPERV_EAX] = {
07585923 933 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 934 .feat_names = {
935 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
936 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
937 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
938 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
939 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
940 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
ba6a4fd9
VK		 941 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
942 NULL, NULL,
2d5312da
EH		 943 NULL, NULL, NULL, NULL,
944 NULL, NULL, NULL, NULL,
945 NULL, NULL, NULL, NULL,
946 NULL, NULL, NULL, NULL,
947 },
07585923 948 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
c35bd19a
EY		 949 },
950 [FEAT_HYPERV_EBX] = {
07585923 951 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 952 .feat_names = {
953 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
954 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
955 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
956 NULL /* hv_create_port */, NULL /* hv_connect_port */,
957 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
958 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
959 NULL, NULL,
960 NULL, NULL, NULL, NULL,
961 NULL, NULL, NULL, NULL,
962 NULL, NULL, NULL, NULL,
963 NULL, NULL, NULL, NULL,
964 },
07585923 965 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
c35bd19a
EY		 966 },
967 [FEAT_HYPERV_EDX] = {
07585923 968 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 969 .feat_names = {
970 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
971 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
972 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
973 NULL, NULL,
974 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
975 NULL, NULL, NULL, NULL,
976 NULL, NULL, NULL, NULL,
977 NULL, NULL, NULL, NULL,
978 NULL, NULL, NULL, NULL,
979 NULL, NULL, NULL, NULL,
980 },
07585923 981 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
c35bd19a 982 },
bffd67b0 983 [FEAT_SVM] = {
07585923 984 .type = CPUID_FEATURE_WORD,
2d5312da 985 .feat_names = {
fc7dfd20
EH		 986 "npt", "lbrv", "svm-lock", "nrip-save",
987 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
988 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 989 "pfthreshold", NULL, NULL, NULL,
990 NULL, NULL, NULL, NULL,
991 NULL, NULL, NULL, NULL,
992 NULL, NULL, NULL, NULL,
993 NULL, NULL, NULL, NULL,
994 },
07585923 995 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 996 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 997 },
998 [FEAT_7_0_EBX] = {
07585923 999 .type = CPUID_FEATURE_WORD,
2d5312da 1000 .feat_names = {
fc7dfd20 1001 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 1002 "hle", "avx2", NULL, "smep",
1003 "bmi2", "erms", "invpcid", "rtm",
1004 NULL, NULL, "mpx", NULL,
1005 "avx512f", "avx512dq", "rdseed", "adx",
1006 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 1007 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 1008 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 1009 },
07585923
RH		 1010 .cpuid = {
1011 .eax = 7,
1012 .needs_ecx = true, .ecx = 0,
1013 .reg = R_EBX,
1014 },
37ce3522 1015 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 1016 },
f74eefe0 1017 [FEAT_7_0_ECX] = {
07585923 1018 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1019 .feat_names = {
1020 NULL, "avx512vbmi", "umip", "pku",
9ccb9784 1021 NULL /* ospke */, NULL, "avx512vbmi2", NULL,
aff9e6e4
YZ		 1022 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1023 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 1024 "la57", NULL, NULL, NULL,
2d5312da 1025 NULL, NULL, "rdpid", NULL,
0da0fb06 1026 NULL, "cldemote", NULL, NULL,
2d5312da
EH		 1027 NULL, NULL, NULL, NULL,
1028 },
07585923
RH		 1029 .cpuid = {
1030 .eax = 7,
1031 .needs_ecx = true, .ecx = 0,
1032 .reg = R_ECX,
1033 },
f74eefe0
HH		 1034 .tcg_features = TCG_7_0_ECX_FEATURES,
1035 },
95ea69fb 1036 [FEAT_7_0_EDX] = {
07585923 1037 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 1038 .feat_names = {
1039 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1040 NULL, NULL, NULL, NULL,
1041 NULL, NULL, NULL, NULL,
1042 NULL, NULL, NULL, NULL,
5131dc43 1043 NULL, NULL, "pconfig", NULL,
95ea69fb 1044 NULL, NULL, NULL, NULL,
a2381f09 1045 NULL, NULL, "spec-ctrl", NULL,
3fc7c731 1046 NULL, "arch-capabilities", NULL, "ssbd",
95ea69fb 1047 },
07585923
RH		 1048 .cpuid = {
1049 .eax = 7,
1050 .needs_ecx = true, .ecx = 0,
1051 .reg = R_EDX,
1052 },
95ea69fb 1053 .tcg_features = TCG_7_0_EDX_FEATURES,
3fc7c731 1054 .unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES,
95ea69fb 1055 },
303752a9 1056 [FEAT_8000_0007_EDX] = {
07585923 1057 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1058 .feat_names = {
1059 NULL, NULL, NULL, NULL,
1060 NULL, NULL, NULL, NULL,
1061 "invtsc", NULL, NULL, NULL,
1062 NULL, NULL, NULL, NULL,
1063 NULL, NULL, NULL, NULL,
1064 NULL, NULL, NULL, NULL,
1065 NULL, NULL, NULL, NULL,
1066 NULL, NULL, NULL, NULL,
1067 },
07585923 1068 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 1069 .tcg_features = TCG_APM_FEATURES,
1070 .unmigratable_flags = CPUID_APM_INVTSC,
1071 },
1b3420e1 1072 [FEAT_8000_0008_EBX] = {
07585923 1073 .type = CPUID_FEATURE_WORD,
1b3420e1
EH		 1074 .feat_names = {
1075 NULL, NULL, NULL, NULL,
1076 NULL, NULL, NULL, NULL,
59a80a19 1077 NULL, "wbnoinvd", NULL, NULL,
1b3420e1
EH		 1078 "ibpb", NULL, NULL, NULL,
1079 NULL, NULL, NULL, NULL,
1080 NULL, NULL, NULL, NULL,
254790a9 1081 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 1082 NULL, NULL, NULL, NULL,
1083 },
07585923 1084 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 1085 .tcg_features = 0,
1086 .unmigratable_flags = 0,
1087 },
0bb0b2d2 1088 [FEAT_XSAVE] = {
07585923 1089 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1090 .feat_names = {
1091 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1092 NULL, NULL, NULL, NULL,
1093 NULL, NULL, NULL, NULL,
1094 NULL, NULL, NULL, NULL,
1095 NULL, NULL, NULL, NULL,
1096 NULL, NULL, NULL, NULL,
1097 NULL, NULL, NULL, NULL,
1098 NULL, NULL, NULL, NULL,
1099 },
07585923
RH		 1100 .cpuid = {
1101 .eax = 0xd,
1102 .needs_ecx = true, .ecx = 1,
1103 .reg = R_EAX,
1104 },
c9cfe8f9 1105 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 1106 },
28b8e4d0 1107 [FEAT_6_EAX] = {
07585923 1108 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1109 .feat_names = {
1110 NULL, NULL, "arat", NULL,
1111 NULL, NULL, NULL, NULL,
1112 NULL, NULL, NULL, NULL,
1113 NULL, NULL, NULL, NULL,
1114 NULL, NULL, NULL, NULL,
1115 NULL, NULL, NULL, NULL,
1116 NULL, NULL, NULL, NULL,
1117 NULL, NULL, NULL, NULL,
1118 },
07585923 1119 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 1120 .tcg_features = TCG_6_EAX_FEATURES,
1121 },
96193c22 1122 [FEAT_XSAVE_COMP_LO] = {
07585923
RH		 1123 .type = CPUID_FEATURE_WORD,
1124 .cpuid = {
1125 .eax = 0xD,
1126 .needs_ecx = true, .ecx = 0,
1127 .reg = R_EAX,
1128 },
96193c22 1129 .tcg_features = ~0U,
6fb2fff7
EH		 1130 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1131 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1132 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1133 XSTATE_PKRU_MASK,
96193c22
EH		 1134 },
1135 [FEAT_XSAVE_COMP_HI] = {
07585923
RH		 1136 .type = CPUID_FEATURE_WORD,
1137 .cpuid = {
1138 .eax = 0xD,
1139 .needs_ecx = true, .ecx = 0,
1140 .reg = R_EDX,
1141 },
96193c22
EH		 1142 .tcg_features = ~0U,
1143 },
5ef57876
EH		 1144};
1145
8e8aba50
EH		 1146typedef struct X86RegisterInfo32 {
1147 /* Name of register */
1148 const char *name;
1149 /* QAPI enum value register */
1150 X86CPURegister32 qapi_enum;
1151} X86RegisterInfo32;
1152
1153#define REGISTER(reg) \
5d371f41 1154 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1155static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1156 REGISTER(EAX),
1157 REGISTER(ECX),
1158 REGISTER(EDX),
1159 REGISTER(EBX),
1160 REGISTER(ESP),
1161 REGISTER(EBP),
1162 REGISTER(ESI),
1163 REGISTER(EDI),
1164};
1165#undef REGISTER
1166
3f32bd21
RH		 1167typedef struct ExtSaveArea {
1168 uint32_t feature, bits;
1169 uint32_t offset, size;
1170} ExtSaveArea;
1171
1172static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 1173 [XSTATE_FP_BIT] = {
1174 /* x87 FP state component is always enabled if XSAVE is supported */
1175 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1176 /* x87 state is in the legacy region of the XSAVE area */
1177 .offset = 0,
1178 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1179 },
1180 [XSTATE_SSE_BIT] = {
1181 /* SSE state component is always enabled if XSAVE is supported */
1182 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1183 /* SSE state is in the legacy region of the XSAVE area */
1184 .offset = 0,
1185 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1186 },
cfc3b074
PB		 1187 [XSTATE_YMM_BIT] =
1188 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 1189 .offset = offsetof(X86XSaveArea, avx_state),
1190 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1191 [XSTATE_BNDREGS_BIT] =
1192 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1193 .offset = offsetof(X86XSaveArea, bndreg_state),
1194 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1195 [XSTATE_BNDCSR_BIT] =
1196 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1197 .offset = offsetof(X86XSaveArea, bndcsr_state),
1198 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1199 [XSTATE_OPMASK_BIT] =
1200 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1201 .offset = offsetof(X86XSaveArea, opmask_state),
1202 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1203 [XSTATE_ZMM_Hi256_BIT] =
1204 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1205 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1206 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1207 [XSTATE_Hi16_ZMM_BIT] =
1208 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1209 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1210 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1211 [XSTATE_PKRU_BIT] =
1212 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 1213 .offset = offsetof(X86XSaveArea, pkru_state),
1214 .size = sizeof(XSavePKRU) },
2560f19f 1215};
8e8aba50 1216
1fda6198
EH		 1217static uint32_t xsave_area_size(uint64_t mask)
1218{
1219 int i;
e3c9022b 1220 uint64_t ret = 0;
1fda6198 1221
e3c9022b 1222 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1223 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1224 if ((mask >> i) & 1) {
1225 ret = MAX(ret, esa->offset + esa->size);
1226 }
1227 }
1228 return ret;
1229}
1230
d6dcc558
SAGDR		 1231static inline bool accel_uses_host_cpuid(void)
1232{
1233 return kvm_enabled() || hvf_enabled();
1234}
1235
96193c22
EH		 1236static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1237{
1238 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1239 cpu->env.features[FEAT_XSAVE_COMP_LO];
1240}
1241
8b4beddc
EH		 1242const char *get_register_name_32(unsigned int reg)
1243{
31ccdde2 1244 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1245 return NULL;
1246 }
8e8aba50 1247 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1248}
1249
84f1b92f
EH		 1250/*
1251 * Returns the set of feature flags that are supported and migratable by
1252 * QEMU, for a given FeatureWord.
1253 */
1254static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1255{
1256 FeatureWordInfo *wi = &feature_word_info[w];
1257 uint32_t r = 0;
1258 int i;
1259
1260 for (i = 0; i < 32; i++) {
1261 uint32_t f = 1U << i;
6fb2fff7
EH		 1262
1263 /* If the feature name is known, it is implicitly considered migratable,
1264 * unless it is explicitly set in unmigratable_flags */
1265 if ((wi->migratable_flags & f) ||
1266 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1267 r |= f;
84f1b92f 1268 }
84f1b92f
EH		 1269 }
1270 return r;
1271}
1272
bb44e0d1
JK		 1273void host_cpuid(uint32_t function, uint32_t count,
1274 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1275{
a1fd24af
AL		 1276 uint32_t vec[4];
1277
1278#ifdef __x86_64__
1279 asm volatile("cpuid"
1280 : "=a"(vec[0]), "=b"(vec[1]),
1281 "=c"(vec[2]), "=d"(vec[3])
1282 : "0"(function), "c"(count) : "cc");
c1f41226 1283#elif defined(__i386__)
a1fd24af
AL		 1284 asm volatile("pusha \n\t"
1285 "cpuid \n\t"
1286 "mov %%eax, 0(%2) \n\t"
1287 "mov %%ebx, 4(%2) \n\t"
1288 "mov %%ecx, 8(%2) \n\t"
1289 "mov %%edx, 12(%2) \n\t"
1290 "popa"
1291 : : "a"(function), "c"(count), "S"(vec)
1292 : "memory", "cc");
c1f41226
EH		 1293#else
1294 abort();
a1fd24af
AL		 1295#endif
1296
bdde476a 1297 if (eax)
a1fd24af 1298 *eax = vec[0];
bdde476a 1299 if (ebx)
a1fd24af 1300 *ebx = vec[1];
bdde476a 1301 if (ecx)
a1fd24af 1302 *ecx = vec[2];
bdde476a 1303 if (edx)
a1fd24af 1304 *edx = vec[3];
bdde476a 1305}
c6dc6f63 1306
20271d48
EH		 1307void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1308{
1309 uint32_t eax, ebx, ecx, edx;
1310
1311 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1312 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1313
1314 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1315 if (family) {
1316 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1317 }
1318 if (model) {
1319 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1320 }
1321 if (stepping) {
1322 *stepping = eax & 0x0F;
1323 }
1324}
1325
d940ee9b
EH		 1326/* CPU class name definitions: */
1327
d940ee9b
EH		 1328/* Return type name for a given CPU model name
1329 * Caller is responsible for freeing the returned string.
1330 */
1331static char *x86_cpu_type_name(const char *model_name)
1332{
1333 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1334}
1335
500050d1
AF		 1336static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1337{
d940ee9b 1338 ObjectClass *oc;
99193d8f 1339 char *typename = x86_cpu_type_name(cpu_model);
d940ee9b
EH		 1340 oc = object_class_by_name(typename);
1341 g_free(typename);
1342 return oc;
500050d1
AF		 1343}
1344
104494ea
IM		 1345static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1346{
1347 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1348 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1349 return g_strndup(class_name,
1350 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1351}
1352
d940ee9b 1353struct X86CPUDefinition {
c6dc6f63
AP		 1354 const char *name;
1355 uint32_t level;
90e4b0c3 1356 uint32_t xlevel;
99b88a17
IM		 1357 /* vendor is zero-terminated, 12 character ASCII string */
1358 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1359 int family;
1360 int model;
1361 int stepping;
0514ef2f 1362 FeatureWordArray features;
807e9869 1363 const char *model_id;
6aaeb054 1364 CPUCaches *cache_info;
d940ee9b 1365};
c6dc6f63 1366
fe52acd2 1367static CPUCaches epyc_cache_info = {
a9f27ea9 1368 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1369 .type = DATA_CACHE,
fe52acd2
BM		 1370 .level = 1,
1371 .size = 32 * KiB,
1372 .line_size = 64,
1373 .associativity = 8,
1374 .partitions = 1,
1375 .sets = 64,
1376 .lines_per_tag = 1,
1377 .self_init = 1,
1378 .no_invd_sharing = true,
1379 },
a9f27ea9 1380 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1381 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1382 .level = 1,
1383 .size = 64 * KiB,
1384 .line_size = 64,
1385 .associativity = 4,
1386 .partitions = 1,
1387 .sets = 256,
1388 .lines_per_tag = 1,
1389 .self_init = 1,
1390 .no_invd_sharing = true,
1391 },
a9f27ea9 1392 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1393 .type = UNIFIED_CACHE,
1394 .level = 2,
1395 .size = 512 * KiB,
1396 .line_size = 64,
1397 .associativity = 8,
1398 .partitions = 1,
1399 .sets = 1024,
1400 .lines_per_tag = 1,
1401 },
a9f27ea9 1402 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1403 .type = UNIFIED_CACHE,
1404 .level = 3,
1405 .size = 8 * MiB,
1406 .line_size = 64,
1407 .associativity = 16,
1408 .partitions = 1,
1409 .sets = 8192,
1410 .lines_per_tag = 1,
1411 .self_init = true,
1412 .inclusive = true,
1413 .complex_indexing = true,
1414 },
1415};
1416
9576de75 1417static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1418 {
1419 .name = "qemu64",
3046bb5d 1420 .level = 0xd,
99b88a17 1421 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 1422 .family = 6,
f8e6a11a 1423 .model = 6,
c6dc6f63 1424 .stepping = 3,
0514ef2f 1425 .features[FEAT_1_EDX] =
27861ecc 1426 PPRO_FEATURES |
c6dc6f63 1427 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1428 CPUID_PSE36,
0514ef2f 1429 .features[FEAT_1_ECX] =
6aa91e4a 1430 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1431 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1432 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1433 .features[FEAT_8000_0001_ECX] =
71195672 1434 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1435 .xlevel = 0x8000000A,
9cf2cc3d 1436 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1437 },
1438 {
1439 .name = "phenom",
1440 .level = 5,
99b88a17 1441 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1442 .family = 16,
1443 .model = 2,
1444 .stepping = 3,
b9fc20bc 1445 /* Missing: CPUID_HT */
0514ef2f 1446 .features[FEAT_1_EDX] =
27861ecc 1447 PPRO_FEATURES |
c6dc6f63 1448 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1449 CPUID_PSE36 | CPUID_VME,
0514ef2f 1450 .features[FEAT_1_ECX] =
27861ecc 1451 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1452 CPUID_EXT_POPCNT,
0514ef2f 1453 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1454 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1455 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1456 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1457 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1458 CPUID_EXT3_CR8LEG,
1459 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1460 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1461 .features[FEAT_8000_0001_ECX] =
27861ecc 1462 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1463 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1464 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1465 .features[FEAT_SVM] =
b9fc20bc 1466 CPUID_SVM_NPT,
c6dc6f63
AP		 1467 .xlevel = 0x8000001A,
1468 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1469 },
1470 {
1471 .name = "core2duo",
1472 .level = 10,
99b88a17 1473 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1474 .family = 6,
1475 .model = 15,
1476 .stepping = 11,
b9fc20bc 1477 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1478 .features[FEAT_1_EDX] =
27861ecc 1479 PPRO_FEATURES |
c6dc6f63 1480 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1481 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1482 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1483 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1484 .features[FEAT_1_ECX] =
27861ecc 1485 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1486 CPUID_EXT_CX16,
0514ef2f 1487 .features[FEAT_8000_0001_EDX] =
27861ecc 1488 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1489 .features[FEAT_8000_0001_ECX] =
27861ecc 1490 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 1491 .xlevel = 0x80000008,
1492 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1493 },
1494 {
1495 .name = "kvm64",
3046bb5d 1496 .level = 0xd,
99b88a17 1497 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1498 .family = 15,
1499 .model = 6,
1500 .stepping = 1,
b3a4f0b1 1501 /* Missing: CPUID_HT */
0514ef2f 1502 .features[FEAT_1_EDX] =
b3a4f0b1 1503 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1504 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1505 CPUID_PSE36,
1506 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1507 .features[FEAT_1_ECX] =
27861ecc 1508 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1509 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1510 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1511 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1512 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1513 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1514 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1515 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1516 .features[FEAT_8000_0001_ECX] =
27861ecc 1517 0,
c6dc6f63
AP		 1518 .xlevel = 0x80000008,
1519 .model_id = "Common KVM processor"
1520 },
c6dc6f63
AP		 1521 {
1522 .name = "qemu32",
1523 .level = 4,
99b88a17 1524 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1525 .family = 6,
f8e6a11a 1526 .model = 6,
c6dc6f63 1527 .stepping = 3,
0514ef2f 1528 .features[FEAT_1_EDX] =
27861ecc 1529 PPRO_FEATURES,
0514ef2f 1530 .features[FEAT_1_ECX] =
6aa91e4a 1531 CPUID_EXT_SSE3,
58012d66 1532 .xlevel = 0x80000004,
9cf2cc3d 1533 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1534 },
eafaf1e5
AP		 1535 {
1536 .name = "kvm32",
1537 .level = 5,
99b88a17 1538 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1539 .family = 15,
1540 .model = 6,
1541 .stepping = 1,
0514ef2f 1542 .features[FEAT_1_EDX] =
b3a4f0b1 1543 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1544 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1545 .features[FEAT_1_ECX] =
27861ecc 1546 CPUID_EXT_SSE3,
0514ef2f 1547 .features[FEAT_8000_0001_ECX] =
27861ecc 1548 0,
eafaf1e5
AP		 1549 .xlevel = 0x80000008,
1550 .model_id = "Common 32-bit KVM processor"
1551 },
c6dc6f63
AP		 1552 {
1553 .name = "coreduo",
1554 .level = 10,
99b88a17 1555 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1556 .family = 6,
1557 .model = 14,
1558 .stepping = 8,
b9fc20bc 1559 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1560 .features[FEAT_1_EDX] =
27861ecc 1561 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1562 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1563 CPUID_SS,
1564 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1565 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1566 .features[FEAT_1_ECX] =
e93abc14 1567 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1568 .features[FEAT_8000_0001_EDX] =
27861ecc 1569 CPUID_EXT2_NX,
c6dc6f63
AP		 1570 .xlevel = 0x80000008,
1571 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1572 },
1573 {
1574 .name = "486",
58012d66 1575 .level = 1,
99b88a17 1576 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1577 .family = 4,
b2a856d9 1578 .model = 8,
c6dc6f63 1579 .stepping = 0,
0514ef2f 1580 .features[FEAT_1_EDX] =
27861ecc 1581 I486_FEATURES,
c6dc6f63 1582 .xlevel = 0,
807e9869 1583 .model_id = "",
c6dc6f63
AP		 1584 },
1585 {
1586 .name = "pentium",
1587 .level = 1,
99b88a17 1588 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1589 .family = 5,
1590 .model = 4,
1591 .stepping = 3,
0514ef2f 1592 .features[FEAT_1_EDX] =
27861ecc 1593 PENTIUM_FEATURES,
c6dc6f63 1594 .xlevel = 0,
807e9869 1595 .model_id = "",
c6dc6f63
AP		 1596 },
1597 {
1598 .name = "pentium2",
1599 .level = 2,
99b88a17 1600 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1601 .family = 6,
1602 .model = 5,
1603 .stepping = 2,
0514ef2f 1604 .features[FEAT_1_EDX] =
27861ecc 1605 PENTIUM2_FEATURES,
c6dc6f63 1606 .xlevel = 0,
807e9869 1607 .model_id = "",
c6dc6f63
AP		 1608 },
1609 {
1610 .name = "pentium3",
3046bb5d 1611 .level = 3,
99b88a17 1612 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1613 .family = 6,
1614 .model = 7,
1615 .stepping = 3,
0514ef2f 1616 .features[FEAT_1_EDX] =
27861ecc 1617 PENTIUM3_FEATURES,
c6dc6f63 1618 .xlevel = 0,
807e9869 1619 .model_id = "",
c6dc6f63
AP		 1620 },
1621 {
1622 .name = "athlon",
1623 .level = 2,
99b88a17 1624 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1625 .family = 6,
1626 .model = 2,
1627 .stepping = 3,
0514ef2f 1628 .features[FEAT_1_EDX] =
27861ecc 1629 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 1630 CPUID_MCA,
0514ef2f 1631 .features[FEAT_8000_0001_EDX] =
60032ac0 1632 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 1633 .xlevel = 0x80000008,
9cf2cc3d 1634 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1635 },
1636 {
1637 .name = "n270",
3046bb5d 1638 .level = 10,
99b88a17 1639 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1640 .family = 6,
1641 .model = 28,
1642 .stepping = 2,
b9fc20bc 1643 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1644 .features[FEAT_1_EDX] =
27861ecc 1645 PPRO_FEATURES |
b9fc20bc
EH		 1646 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1647 CPUID_ACPI | CPUID_SS,
c6dc6f63 1648 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1649 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1650 * CPUID_EXT_XTPR */
0514ef2f 1651 .features[FEAT_1_ECX] =
27861ecc 1652 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1653 CPUID_EXT_MOVBE,
0514ef2f 1654 .features[FEAT_8000_0001_EDX] =
60032ac0 1655 CPUID_EXT2_NX,
0514ef2f 1656 .features[FEAT_8000_0001_ECX] =
27861ecc 1657 CPUID_EXT3_LAHF_LM,
3046bb5d 1658 .xlevel = 0x80000008,
c6dc6f63
AP		 1659 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1660 },
3eca4642
EH		 1661 {
1662 .name = "Conroe",
3046bb5d 1663 .level = 10,
99b88a17 1664 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1665 .family = 6,
ffce9ebb 1666 .model = 15,
3eca4642 1667 .stepping = 3,
0514ef2f 1668 .features[FEAT_1_EDX] =
b3a4f0b1 1669 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1670 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1671 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1672 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1673 CPUID_DE | CPUID_FP87,
0514ef2f 1674 .features[FEAT_1_ECX] =
27861ecc 1675 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1676 .features[FEAT_8000_0001_EDX] =
27861ecc 1677 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1678 .features[FEAT_8000_0001_ECX] =
27861ecc 1679 CPUID_EXT3_LAHF_LM,
3046bb5d 1680 .xlevel = 0x80000008,
3eca4642
EH		 1681 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1682 },
1683 {
1684 .name = "Penryn",
3046bb5d 1685 .level = 10,
99b88a17 1686 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1687 .family = 6,
ffce9ebb 1688 .model = 23,
3eca4642 1689 .stepping = 3,
0514ef2f 1690 .features[FEAT_1_EDX] =
b3a4f0b1 1691 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1692 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1693 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1694 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1695 CPUID_DE | CPUID_FP87,
0514ef2f 1696 .features[FEAT_1_ECX] =
27861ecc 1697 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1698 CPUID_EXT_SSE3,
0514ef2f 1699 .features[FEAT_8000_0001_EDX] =
27861ecc 1700 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1701 .features[FEAT_8000_0001_ECX] =
27861ecc 1702 CPUID_EXT3_LAHF_LM,
3046bb5d 1703 .xlevel = 0x80000008,
3eca4642
EH		 1704 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1705 },
1706 {
1707 .name = "Nehalem",
3046bb5d 1708 .level = 11,
99b88a17 1709 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1710 .family = 6,
ffce9ebb 1711 .model = 26,
3eca4642 1712 .stepping = 3,
0514ef2f 1713 .features[FEAT_1_EDX] =
b3a4f0b1 1714 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1715 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1716 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1717 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1718 CPUID_DE | CPUID_FP87,
0514ef2f 1719 .features[FEAT_1_ECX] =
27861ecc 1720 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1721 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1722 .features[FEAT_8000_0001_EDX] =
27861ecc 1723 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1724 .features[FEAT_8000_0001_ECX] =
27861ecc 1725 CPUID_EXT3_LAHF_LM,
3046bb5d 1726 .xlevel = 0x80000008,
3eca4642
EH		 1727 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1728 },
ac96c413
EH		 1729 {
1730 .name = "Nehalem-IBRS",
1731 .level = 11,
1732 .vendor = CPUID_VENDOR_INTEL,
1733 .family = 6,
1734 .model = 26,
1735 .stepping = 3,
1736 .features[FEAT_1_EDX] =
1737 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1738 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1739 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1740 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1741 CPUID_DE | CPUID_FP87,
1742 .features[FEAT_1_ECX] =
1743 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1744 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1745 .features[FEAT_7_0_EDX] =
1746 CPUID_7_0_EDX_SPEC_CTRL,
1747 .features[FEAT_8000_0001_EDX] =
1748 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1749 .features[FEAT_8000_0001_ECX] =
1750 CPUID_EXT3_LAHF_LM,
1751 .xlevel = 0x80000008,
1752 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1753 },
3eca4642
EH		 1754 {
1755 .name = "Westmere",
1756 .level = 11,
99b88a17 1757 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1758 .family = 6,
1759 .model = 44,
1760 .stepping = 1,
0514ef2f 1761 .features[FEAT_1_EDX] =
b3a4f0b1 1762 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1763 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1764 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1765 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1766 CPUID_DE | CPUID_FP87,
0514ef2f 1767 .features[FEAT_1_ECX] =
27861ecc 1768 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1769 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1770 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1771 .features[FEAT_8000_0001_EDX] =
27861ecc 1772 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1773 .features[FEAT_8000_0001_ECX] =
27861ecc 1774 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1775 .features[FEAT_6_EAX] =
1776 CPUID_6_EAX_ARAT,
3046bb5d 1777 .xlevel = 0x80000008,
3eca4642
EH		 1778 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1779 },
ac96c413
EH		 1780 {
1781 .name = "Westmere-IBRS",
1782 .level = 11,
1783 .vendor = CPUID_VENDOR_INTEL,
1784 .family = 6,
1785 .model = 44,
1786 .stepping = 1,
1787 .features[FEAT_1_EDX] =
1788 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1789 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1790 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1791 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1792 CPUID_DE | CPUID_FP87,
1793 .features[FEAT_1_ECX] =
1794 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1795 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1796 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1797 .features[FEAT_8000_0001_EDX] =
1798 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1799 .features[FEAT_8000_0001_ECX] =
1800 CPUID_EXT3_LAHF_LM,
1801 .features[FEAT_7_0_EDX] =
1802 CPUID_7_0_EDX_SPEC_CTRL,
1803 .features[FEAT_6_EAX] =
1804 CPUID_6_EAX_ARAT,
1805 .xlevel = 0x80000008,
1806 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1807 },
3eca4642
EH		 1808 {
1809 .name = "SandyBridge",
1810 .level = 0xd,
99b88a17 1811 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1812 .family = 6,
1813 .model = 42,
1814 .stepping = 1,
0514ef2f 1815 .features[FEAT_1_EDX] =
b3a4f0b1 1816 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1817 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1818 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1819 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1820 CPUID_DE | CPUID_FP87,
0514ef2f 1821 .features[FEAT_1_ECX] =
27861ecc 1822 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1823 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1824 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1825 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1826 CPUID_EXT_SSE3,
0514ef2f 1827 .features[FEAT_8000_0001_EDX] =
27861ecc 1828 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1829 CPUID_EXT2_SYSCALL,
0514ef2f 1830 .features[FEAT_8000_0001_ECX] =
27861ecc 1831 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1832 .features[FEAT_XSAVE] =
1833 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1834 .features[FEAT_6_EAX] =
1835 CPUID_6_EAX_ARAT,
3046bb5d 1836 .xlevel = 0x80000008,
3eca4642
EH		 1837 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1838 },
ac96c413
EH		 1839 {
1840 .name = "SandyBridge-IBRS",
1841 .level = 0xd,
1842 .vendor = CPUID_VENDOR_INTEL,
1843 .family = 6,
1844 .model = 42,
1845 .stepping = 1,
1846 .features[FEAT_1_EDX] =
1847 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1848 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1849 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1850 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1851 CPUID_DE | CPUID_FP87,
1852 .features[FEAT_1_ECX] =
1853 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1854 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1855 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1856 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1857 CPUID_EXT_SSE3,
1858 .features[FEAT_8000_0001_EDX] =
1859 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1860 CPUID_EXT2_SYSCALL,
1861 .features[FEAT_8000_0001_ECX] =
1862 CPUID_EXT3_LAHF_LM,
1863 .features[FEAT_7_0_EDX] =
1864 CPUID_7_0_EDX_SPEC_CTRL,
1865 .features[FEAT_XSAVE] =
1866 CPUID_XSAVE_XSAVEOPT,
1867 .features[FEAT_6_EAX] =
1868 CPUID_6_EAX_ARAT,
1869 .xlevel = 0x80000008,
1870 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1871 },
2f9ac42a
PB		 1872 {
1873 .name = "IvyBridge",
1874 .level = 0xd,
1875 .vendor = CPUID_VENDOR_INTEL,
1876 .family = 6,
1877 .model = 58,
1878 .stepping = 9,
1879 .features[FEAT_1_EDX] =
1880 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1881 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1882 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1883 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1884 CPUID_DE | CPUID_FP87,
1885 .features[FEAT_1_ECX] =
1886 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1887 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1888 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1889 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1890 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1891 .features[FEAT_7_0_EBX] =
1892 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1893 CPUID_7_0_EBX_ERMS,
1894 .features[FEAT_8000_0001_EDX] =
1895 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1896 CPUID_EXT2_SYSCALL,
1897 .features[FEAT_8000_0001_ECX] =
1898 CPUID_EXT3_LAHF_LM,
1899 .features[FEAT_XSAVE] =
1900 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1901 .features[FEAT_6_EAX] =
1902 CPUID_6_EAX_ARAT,
3046bb5d 1903 .xlevel = 0x80000008,
2f9ac42a
PB		 1904 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1905 },
ac96c413
EH		 1906 {
1907 .name = "IvyBridge-IBRS",
1908 .level = 0xd,
1909 .vendor = CPUID_VENDOR_INTEL,
1910 .family = 6,
1911 .model = 58,
1912 .stepping = 9,
1913 .features[FEAT_1_EDX] =
1914 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1915 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1916 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1917 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1918 CPUID_DE | CPUID_FP87,
1919 .features[FEAT_1_ECX] =
1920 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1921 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1922 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1923 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1924 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1925 .features[FEAT_7_0_EBX] =
1926 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1927 CPUID_7_0_EBX_ERMS,
1928 .features[FEAT_8000_0001_EDX] =
1929 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1930 CPUID_EXT2_SYSCALL,
1931 .features[FEAT_8000_0001_ECX] =
1932 CPUID_EXT3_LAHF_LM,
1933 .features[FEAT_7_0_EDX] =
1934 CPUID_7_0_EDX_SPEC_CTRL,
1935 .features[FEAT_XSAVE] =
1936 CPUID_XSAVE_XSAVEOPT,
1937 .features[FEAT_6_EAX] =
1938 CPUID_6_EAX_ARAT,
1939 .xlevel = 0x80000008,
1940 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
1941 },
37507094 1942 {
a356850b
EH		 1943 .name = "Haswell-noTSX",
1944 .level = 0xd,
1945 .vendor = CPUID_VENDOR_INTEL,
1946 .family = 6,
1947 .model = 60,
1948 .stepping = 1,
1949 .features[FEAT_1_EDX] =
1950 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1951 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1952 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1953 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1954 CPUID_DE | CPUID_FP87,
1955 .features[FEAT_1_ECX] =
1956 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1957 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1958 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1959 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1960 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1961 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1962 .features[FEAT_8000_0001_EDX] =
1963 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1964 CPUID_EXT2_SYSCALL,
1965 .features[FEAT_8000_0001_ECX] =
becb6667 1966 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1967 .features[FEAT_7_0_EBX] =
1968 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1969 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1970 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1971 .features[FEAT_XSAVE] =
1972 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1973 .features[FEAT_6_EAX] =
1974 CPUID_6_EAX_ARAT,
3046bb5d 1975 .xlevel = 0x80000008,
a356850b 1976 .model_id = "Intel Core Processor (Haswell, no TSX)",
ac96c413
EH		 1977 },
1978 {
1979 .name = "Haswell-noTSX-IBRS",
1980 .level = 0xd,
1981 .vendor = CPUID_VENDOR_INTEL,
1982 .family = 6,
1983 .model = 60,
1984 .stepping = 1,
1985 .features[FEAT_1_EDX] =
1986 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1987 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1988 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1989 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1990 CPUID_DE | CPUID_FP87,
1991 .features[FEAT_1_ECX] =
1992 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1993 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1994 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1995 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1996 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1997 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1998 .features[FEAT_8000_0001_EDX] =
1999 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2000 CPUID_EXT2_SYSCALL,
2001 .features[FEAT_8000_0001_ECX] =
2002 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2003 .features[FEAT_7_0_EDX] =
2004 CPUID_7_0_EDX_SPEC_CTRL,
2005 .features[FEAT_7_0_EBX] =
2006 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2007 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2008 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2009 .features[FEAT_XSAVE] =
2010 CPUID_XSAVE_XSAVEOPT,
2011 .features[FEAT_6_EAX] =
2012 CPUID_6_EAX_ARAT,
2013 .xlevel = 0x80000008,
2014 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
2015 },
2016 {
37507094
EH		 2017 .name = "Haswell",
2018 .level = 0xd,
99b88a17 2019 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2020 .family = 6,
2021 .model = 60,
ec56a4a7 2022 .stepping = 4,
0514ef2f 2023 .features[FEAT_1_EDX] =
b3a4f0b1 2024 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2025 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2026 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2027 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2028 CPUID_DE | CPUID_FP87,
0514ef2f 2029 .features[FEAT_1_ECX] =
27861ecc 2030 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2031 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2032 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2033 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2034 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2035 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2036 .features[FEAT_8000_0001_EDX] =
27861ecc 2037 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2038 CPUID_EXT2_SYSCALL,
0514ef2f 2039 .features[FEAT_8000_0001_ECX] =
becb6667 2040 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2041 .features[FEAT_7_0_EBX] =
27861ecc 2042 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2043 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2044 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2045 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2046 .features[FEAT_XSAVE] =
2047 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2048 .features[FEAT_6_EAX] =
2049 CPUID_6_EAX_ARAT,
3046bb5d 2050 .xlevel = 0x80000008,
37507094
EH		 2051 .model_id = "Intel Core Processor (Haswell)",
2052 },
ac96c413
EH		 2053 {
2054 .name = "Haswell-IBRS",
2055 .level = 0xd,
2056 .vendor = CPUID_VENDOR_INTEL,
2057 .family = 6,
2058 .model = 60,
2059 .stepping = 4,
2060 .features[FEAT_1_EDX] =
2061 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2062 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2063 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2064 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2065 CPUID_DE | CPUID_FP87,
2066 .features[FEAT_1_ECX] =
2067 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2068 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2069 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2070 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2071 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2072 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2073 .features[FEAT_8000_0001_EDX] =
2074 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2075 CPUID_EXT2_SYSCALL,
2076 .features[FEAT_8000_0001_ECX] =
2077 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2078 .features[FEAT_7_0_EDX] =
2079 CPUID_7_0_EDX_SPEC_CTRL,
2080 .features[FEAT_7_0_EBX] =
2081 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2082 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2083 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2084 CPUID_7_0_EBX_RTM,
2085 .features[FEAT_XSAVE] =
2086 CPUID_XSAVE_XSAVEOPT,
2087 .features[FEAT_6_EAX] =
2088 CPUID_6_EAX_ARAT,
2089 .xlevel = 0x80000008,
2090 .model_id = "Intel Core Processor (Haswell, IBRS)",
2091 },
a356850b
EH		 2092 {
2093 .name = "Broadwell-noTSX",
2094 .level = 0xd,
2095 .vendor = CPUID_VENDOR_INTEL,
2096 .family = 6,
2097 .model = 61,
2098 .stepping = 2,
2099 .features[FEAT_1_EDX] =
2100 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2101 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2102 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2103 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2104 CPUID_DE | CPUID_FP87,
2105 .features[FEAT_1_ECX] =
2106 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2107 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2108 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2109 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2110 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2111 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2112 .features[FEAT_8000_0001_EDX] =
2113 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2114 CPUID_EXT2_SYSCALL,
2115 .features[FEAT_8000_0001_ECX] =
becb6667 2116 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 2117 .features[FEAT_7_0_EBX] =
2118 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2119 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2120 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2121 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2122 CPUID_7_0_EBX_SMAP,
2123 .features[FEAT_XSAVE] =
2124 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2125 .features[FEAT_6_EAX] =
2126 CPUID_6_EAX_ARAT,
3046bb5d 2127 .xlevel = 0x80000008,
a356850b
EH		 2128 .model_id = "Intel Core Processor (Broadwell, no TSX)",
2129 },
ac96c413
EH		 2130 {
2131 .name = "Broadwell-noTSX-IBRS",
2132 .level = 0xd,
2133 .vendor = CPUID_VENDOR_INTEL,
2134 .family = 6,
2135 .model = 61,
2136 .stepping = 2,
2137 .features[FEAT_1_EDX] =
2138 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2139 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2140 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2141 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2142 CPUID_DE | CPUID_FP87,
2143 .features[FEAT_1_ECX] =
2144 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2145 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2146 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2147 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2148 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2149 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2150 .features[FEAT_8000_0001_EDX] =
2151 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2152 CPUID_EXT2_SYSCALL,
2153 .features[FEAT_8000_0001_ECX] =
2154 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2155 .features[FEAT_7_0_EDX] =
2156 CPUID_7_0_EDX_SPEC_CTRL,
2157 .features[FEAT_7_0_EBX] =
2158 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2159 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2160 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2161 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2162 CPUID_7_0_EBX_SMAP,
2163 .features[FEAT_XSAVE] =
2164 CPUID_XSAVE_XSAVEOPT,
2165 .features[FEAT_6_EAX] =
2166 CPUID_6_EAX_ARAT,
2167 .xlevel = 0x80000008,
2168 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
2169 },
ece01354
EH		 2170 {
2171 .name = "Broadwell",
2172 .level = 0xd,
2173 .vendor = CPUID_VENDOR_INTEL,
2174 .family = 6,
2175 .model = 61,
2176 .stepping = 2,
2177 .features[FEAT_1_EDX] =
b3a4f0b1 2178 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2179 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2180 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2181 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2182 CPUID_DE | CPUID_FP87,
2183 .features[FEAT_1_ECX] =
2184 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2185 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2186 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2187 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2188 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2189 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2190 .features[FEAT_8000_0001_EDX] =
2191 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2192 CPUID_EXT2_SYSCALL,
2193 .features[FEAT_8000_0001_ECX] =
becb6667 2194 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2195 .features[FEAT_7_0_EBX] =
2196 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2197 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2198 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2199 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2200 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2201 .features[FEAT_XSAVE] =
2202 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2203 .features[FEAT_6_EAX] =
2204 CPUID_6_EAX_ARAT,
3046bb5d 2205 .xlevel = 0x80000008,
ece01354
EH		 2206 .model_id = "Intel Core Processor (Broadwell)",
2207 },
ac96c413
EH		 2208 {
2209 .name = "Broadwell-IBRS",
2210 .level = 0xd,
2211 .vendor = CPUID_VENDOR_INTEL,
2212 .family = 6,
2213 .model = 61,
2214 .stepping = 2,
2215 .features[FEAT_1_EDX] =
2216 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2217 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2218 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2219 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2220 CPUID_DE | CPUID_FP87,
2221 .features[FEAT_1_ECX] =
2222 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2223 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2224 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2225 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2226 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2227 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2228 .features[FEAT_8000_0001_EDX] =
2229 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2230 CPUID_EXT2_SYSCALL,
2231 .features[FEAT_8000_0001_ECX] =
2232 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2233 .features[FEAT_7_0_EDX] =
2234 CPUID_7_0_EDX_SPEC_CTRL,
2235 .features[FEAT_7_0_EBX] =
2236 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2237 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2238 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2239 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2240 CPUID_7_0_EBX_SMAP,
2241 .features[FEAT_XSAVE] =
2242 CPUID_XSAVE_XSAVEOPT,
2243 .features[FEAT_6_EAX] =
2244 CPUID_6_EAX_ARAT,
2245 .xlevel = 0x80000008,
2246 .model_id = "Intel Core Processor (Broadwell, IBRS)",
2247 },
f6f949e9
EH		 2248 {
2249 .name = "Skylake-Client",
2250 .level = 0xd,
2251 .vendor = CPUID_VENDOR_INTEL,
2252 .family = 6,
2253 .model = 94,
2254 .stepping = 3,
2255 .features[FEAT_1_EDX] =
2256 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2257 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2258 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2259 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2260 CPUID_DE | CPUID_FP87,
2261 .features[FEAT_1_ECX] =
2262 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2263 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2264 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2265 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2266 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2267 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2268 .features[FEAT_8000_0001_EDX] =
2269 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2270 CPUID_EXT2_SYSCALL,
2271 .features[FEAT_8000_0001_ECX] =
2272 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2273 .features[FEAT_7_0_EBX] =
2274 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2275 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2276 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2277 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2278 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
2279 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 2280 * including v4.1 to v4.12).
f6f949e9
EH		 2281 * KVM doesn't yet expose any XSAVES state save component,
2282 * and the only one defined in Skylake (processor tracing)
2283 * probably will block migration anyway.
2284 */
2285 .features[FEAT_XSAVE] =
2286 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2287 CPUID_XSAVE_XGETBV1,
2288 .features[FEAT_6_EAX] =
2289 CPUID_6_EAX_ARAT,
2290 .xlevel = 0x80000008,
2291 .model_id = "Intel Core Processor (Skylake)",
2292 },
ac96c413
EH		 2293 {
2294 .name = "Skylake-Client-IBRS",
2295 .level = 0xd,
2296 .vendor = CPUID_VENDOR_INTEL,
2297 .family = 6,
2298 .model = 94,
2299 .stepping = 3,
2300 .features[FEAT_1_EDX] =
2301 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2302 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2303 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2304 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2305 CPUID_DE | CPUID_FP87,
2306 .features[FEAT_1_ECX] =
2307 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2308 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2309 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2310 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2311 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2312 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2313 .features[FEAT_8000_0001_EDX] =
2314 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2315 CPUID_EXT2_SYSCALL,
2316 .features[FEAT_8000_0001_ECX] =
2317 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2318 .features[FEAT_7_0_EDX] =
2319 CPUID_7_0_EDX_SPEC_CTRL,
2320 .features[FEAT_7_0_EBX] =
2321 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2322 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2323 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2324 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2325 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
2326 /* Missing: XSAVES (not supported by some Linux versions,
2327 * including v4.1 to v4.12).
2328 * KVM doesn't yet expose any XSAVES state save component,
2329 * and the only one defined in Skylake (processor tracing)
2330 * probably will block migration anyway.
2331 */
2332 .features[FEAT_XSAVE] =
2333 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2334 CPUID_XSAVE_XGETBV1,
2335 .features[FEAT_6_EAX] =
2336 CPUID_6_EAX_ARAT,
2337 .xlevel = 0x80000008,
2338 .model_id = "Intel Core Processor (Skylake, IBRS)",
2339 },
53f9a6f4
BF		 2340 {
2341 .name = "Skylake-Server",
2342 .level = 0xd,
2343 .vendor = CPUID_VENDOR_INTEL,
2344 .family = 6,
2345 .model = 85,
2346 .stepping = 4,
2347 .features[FEAT_1_EDX] =
2348 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2349 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2350 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2351 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2352 CPUID_DE | CPUID_FP87,
2353 .features[FEAT_1_ECX] =
2354 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2355 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2356 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2357 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2358 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2359 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2360 .features[FEAT_8000_0001_EDX] =
2361 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2362 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2363 .features[FEAT_8000_0001_ECX] =
2364 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2365 .features[FEAT_7_0_EBX] =
2366 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2367 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2368 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2369 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2370 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2371 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2372 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2373 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
53f9a6f4
BF		 2374 /* Missing: XSAVES (not supported by some Linux versions,
2375 * including v4.1 to v4.12).
2376 * KVM doesn't yet expose any XSAVES state save component,
2377 * and the only one defined in Skylake (processor tracing)
2378 * probably will block migration anyway.
2379 */
2380 .features[FEAT_XSAVE] =
2381 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2382 CPUID_XSAVE_XGETBV1,
2383 .features[FEAT_6_EAX] =
2384 CPUID_6_EAX_ARAT,
2385 .xlevel = 0x80000008,
2386 .model_id = "Intel Xeon Processor (Skylake)",
2387 },
ac96c413
EH		 2388 {
2389 .name = "Skylake-Server-IBRS",
2390 .level = 0xd,
2391 .vendor = CPUID_VENDOR_INTEL,
2392 .family = 6,
2393 .model = 85,
2394 .stepping = 4,
2395 .features[FEAT_1_EDX] =
2396 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2397 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2398 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2399 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2400 CPUID_DE | CPUID_FP87,
2401 .features[FEAT_1_ECX] =
2402 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2403 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2404 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2405 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2406 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2407 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2408 .features[FEAT_8000_0001_EDX] =
2409 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2410 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2411 .features[FEAT_8000_0001_ECX] =
2412 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2413 .features[FEAT_7_0_EDX] =
2414 CPUID_7_0_EDX_SPEC_CTRL,
2415 .features[FEAT_7_0_EBX] =
2416 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2417 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2418 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2419 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2420 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2421 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2422 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2423 CPUID_7_0_EBX_AVX512VL,
2424 /* Missing: XSAVES (not supported by some Linux versions,
2425 * including v4.1 to v4.12).
2426 * KVM doesn't yet expose any XSAVES state save component,
2427 * and the only one defined in Skylake (processor tracing)
2428 * probably will block migration anyway.
2429 */
2430 .features[FEAT_XSAVE] =
2431 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2432 CPUID_XSAVE_XGETBV1,
2433 .features[FEAT_6_EAX] =
2434 CPUID_6_EAX_ARAT,
2435 .xlevel = 0x80000008,
2436 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2437 },
8a11c62d
RH		 2438 {
2439 .name = "Icelake-Client",
2440 .level = 0xd,
2441 .vendor = CPUID_VENDOR_INTEL,
2442 .family = 6,
2443 .model = 126,
2444 .stepping = 0,
2445 .features[FEAT_1_EDX] =
2446 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2447 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2448 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2449 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2450 CPUID_DE | CPUID_FP87,
2451 .features[FEAT_1_ECX] =
2452 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2453 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2454 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2455 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2456 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2457 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2458 .features[FEAT_8000_0001_EDX] =
2459 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2460 CPUID_EXT2_SYSCALL,
2461 .features[FEAT_8000_0001_ECX] =
2462 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2463 .features[FEAT_8000_0008_EBX] =
2464 CPUID_8000_0008_EBX_WBNOINVD,
2465 .features[FEAT_7_0_EBX] =
2466 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2467 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2468 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2469 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2470 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INTEL_PT,
2471 .features[FEAT_7_0_ECX] =
2472 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2473 CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2474 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2475 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2476 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2477 .features[FEAT_7_0_EDX] =
2478 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2479 /* Missing: XSAVES (not supported by some Linux versions,
2480 * including v4.1 to v4.12).
2481 * KVM doesn't yet expose any XSAVES state save component,
2482 * and the only one defined in Skylake (processor tracing)
2483 * probably will block migration anyway.
2484 */
2485 .features[FEAT_XSAVE] =
2486 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2487 CPUID_XSAVE_XGETBV1,
2488 .features[FEAT_6_EAX] =
2489 CPUID_6_EAX_ARAT,
2490 .xlevel = 0x80000008,
2491 .model_id = "Intel Core Processor (Icelake)",
2492 },
2493 {
2494 .name = "Icelake-Server",
2495 .level = 0xd,
2496 .vendor = CPUID_VENDOR_INTEL,
2497 .family = 6,
2498 .model = 134,
2499 .stepping = 0,
2500 .features[FEAT_1_EDX] =
2501 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2502 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2503 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2504 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2505 CPUID_DE | CPUID_FP87,
2506 .features[FEAT_1_ECX] =
2507 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2508 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2509 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2510 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2511 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2512 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2513 .features[FEAT_8000_0001_EDX] =
2514 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2515 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2516 .features[FEAT_8000_0001_ECX] =
2517 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2518 .features[FEAT_8000_0008_EBX] =
2519 CPUID_8000_0008_EBX_WBNOINVD,
2520 .features[FEAT_7_0_EBX] =
2521 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2522 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2523 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2524 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2525 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2526 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2527 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2528 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
2529 CPUID_7_0_EBX_INTEL_PT,
2530 .features[FEAT_7_0_ECX] =
2531 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2532 CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2533 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2534 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2535 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
2536 .features[FEAT_7_0_EDX] =
2537 CPUID_7_0_EDX_PCONFIG | CPUID_7_0_EDX_SPEC_CTRL |
2538 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2539 /* Missing: XSAVES (not supported by some Linux versions,
2540 * including v4.1 to v4.12).
2541 * KVM doesn't yet expose any XSAVES state save component,
2542 * and the only one defined in Skylake (processor tracing)
2543 * probably will block migration anyway.
2544 */
2545 .features[FEAT_XSAVE] =
2546 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2547 CPUID_XSAVE_XGETBV1,
2548 .features[FEAT_6_EAX] =
2549 CPUID_6_EAX_ARAT,
2550 .xlevel = 0x80000008,
2551 .model_id = "Intel Xeon Processor (Icelake)",
2552 },
a1849515
BF		 2553 {
2554 .name = "KnightsMill",
2555 .level = 0xd,
2556 .vendor = CPUID_VENDOR_INTEL,
2557 .family = 6,
2558 .model = 133,
2559 .stepping = 0,
2560 .features[FEAT_1_EDX] =
2561 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2562 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2563 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2564 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2565 CPUID_PSE | CPUID_DE | CPUID_FP87,
2566 .features[FEAT_1_ECX] =
2567 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2568 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2569 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2570 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2571 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2572 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2573 .features[FEAT_8000_0001_EDX] =
2574 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2575 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2576 .features[FEAT_8000_0001_ECX] =
2577 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2578 .features[FEAT_7_0_EBX] =
2579 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2580 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2581 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2582 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2583 CPUID_7_0_EBX_AVX512ER,
2584 .features[FEAT_7_0_ECX] =
2585 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2586 .features[FEAT_7_0_EDX] =
2587 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2588 .features[FEAT_XSAVE] =
2589 CPUID_XSAVE_XSAVEOPT,
2590 .features[FEAT_6_EAX] =
2591 CPUID_6_EAX_ARAT,
2592 .xlevel = 0x80000008,
2593 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2594 },
3eca4642
EH		 2595 {
2596 .name = "Opteron_G1",
2597 .level = 5,
99b88a17 2598 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2599 .family = 15,
2600 .model = 6,
2601 .stepping = 1,
0514ef2f 2602 .features[FEAT_1_EDX] =
b3a4f0b1 2603 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2604 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2605 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2606 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2607 CPUID_DE | CPUID_FP87,
0514ef2f 2608 .features[FEAT_1_ECX] =
27861ecc 2609 CPUID_EXT_SSE3,
0514ef2f 2610 .features[FEAT_8000_0001_EDX] =
2a923a29 2611 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 2612 .xlevel = 0x80000008,
2613 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2614 },
2615 {
2616 .name = "Opteron_G2",
2617 .level = 5,
99b88a17 2618 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2619 .family = 15,
2620 .model = 6,
2621 .stepping = 1,
0514ef2f 2622 .features[FEAT_1_EDX] =
b3a4f0b1 2623 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2624 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2625 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2626 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2627 CPUID_DE | CPUID_FP87,
0514ef2f 2628 .features[FEAT_1_ECX] =
27861ecc 2629 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 2630 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2631 .features[FEAT_8000_0001_EDX] =
2a923a29 2632 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2633 .features[FEAT_8000_0001_ECX] =
27861ecc 2634 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2635 .xlevel = 0x80000008,
2636 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2637 },
2638 {
2639 .name = "Opteron_G3",
2640 .level = 5,
99b88a17 2641 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 2642 .family = 16,
2643 .model = 2,
2644 .stepping = 3,
0514ef2f 2645 .features[FEAT_1_EDX] =
b3a4f0b1 2646 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2647 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2648 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2649 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2650 CPUID_DE | CPUID_FP87,
0514ef2f 2651 .features[FEAT_1_ECX] =
27861ecc 2652 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 2653 CPUID_EXT_SSE3,
33b5e8c0 2654 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2655 .features[FEAT_8000_0001_EDX] =
2a923a29 2656 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2657 .features[FEAT_8000_0001_ECX] =
27861ecc 2658 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 2659 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2660 .xlevel = 0x80000008,
2661 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2662 },
2663 {
2664 .name = "Opteron_G4",
2665 .level = 0xd,
99b88a17 2666 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2667 .family = 21,
2668 .model = 1,
2669 .stepping = 2,
0514ef2f 2670 .features[FEAT_1_EDX] =
b3a4f0b1 2671 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2672 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2673 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2674 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2675 CPUID_DE | CPUID_FP87,
0514ef2f 2676 .features[FEAT_1_ECX] =
27861ecc 2677 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2678 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2679 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2680 CPUID_EXT_SSE3,
33b5e8c0 2681 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2682 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 2683 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2684 CPUID_EXT2_SYSCALL,
0514ef2f 2685 .features[FEAT_8000_0001_ECX] =
27861ecc 2686 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2687 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2688 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2689 CPUID_EXT3_LAHF_LM,
0bb0b2d2 2690 /* no xsaveopt! */
3eca4642
EH		 2691 .xlevel = 0x8000001A,
2692 .model_id = "AMD Opteron 62xx class CPU",
2693 },
021941b9
AP		 2694 {
2695 .name = "Opteron_G5",
2696 .level = 0xd,
99b88a17 2697 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 2698 .family = 21,
2699 .model = 2,
2700 .stepping = 0,
0514ef2f 2701 .features[FEAT_1_EDX] =
b3a4f0b1 2702 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2703 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2704 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2705 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2706 CPUID_DE | CPUID_FP87,
0514ef2f 2707 .features[FEAT_1_ECX] =
27861ecc 2708 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 2709 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2710 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2711 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 2712 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2713 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 2714 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2715 CPUID_EXT2_SYSCALL,
0514ef2f 2716 .features[FEAT_8000_0001_ECX] =
27861ecc 2717 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2718 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2719 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2720 CPUID_EXT3_LAHF_LM,
0bb0b2d2 2721 /* no xsaveopt! */
021941b9
AP		 2722 .xlevel = 0x8000001A,
2723 .model_id = "AMD Opteron 63xx class CPU",
2724 },
2e2efc7d
BS		 2725 {
2726 .name = "EPYC",
2727 .level = 0xd,
2728 .vendor = CPUID_VENDOR_AMD,
2729 .family = 23,
2730 .model = 1,
2731 .stepping = 2,
2732 .features[FEAT_1_EDX] =
2733 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2734 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2735 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2736 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2737 CPUID_VME | CPUID_FP87,
2738 .features[FEAT_1_ECX] =
2739 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2740 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2741 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2742 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2743 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2744 .features[FEAT_8000_0001_EDX] =
2745 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2746 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2747 CPUID_EXT2_SYSCALL,
2748 .features[FEAT_8000_0001_ECX] =
2749 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2750 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2751 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2752 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 2753 .features[FEAT_7_0_EBX] =
2754 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2755 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2756 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2757 CPUID_7_0_EBX_SHA_NI,
2758 /* Missing: XSAVES (not supported by some Linux versions,
2759 * including v4.1 to v4.12).
2760 * KVM doesn't yet expose any XSAVES state save component.
2761 */
2762 .features[FEAT_XSAVE] =
2763 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2764 CPUID_XSAVE_XGETBV1,
2765 .features[FEAT_6_EAX] =
2766 CPUID_6_EAX_ARAT,
e0051647 2767 .xlevel = 0x8000001E,
2e2efc7d 2768 .model_id = "AMD EPYC Processor",
fe52acd2 2769 .cache_info = &epyc_cache_info,
2e2efc7d 2770 },
6cfbc54e
EH		 2771 {
2772 .name = "EPYC-IBPB",
2773 .level = 0xd,
2774 .vendor = CPUID_VENDOR_AMD,
2775 .family = 23,
2776 .model = 1,
2777 .stepping = 2,
2778 .features[FEAT_1_EDX] =
2779 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2780 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2781 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2782 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2783 CPUID_VME | CPUID_FP87,
2784 .features[FEAT_1_ECX] =
2785 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2786 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2787 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2788 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2789 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2790 .features[FEAT_8000_0001_EDX] =
2791 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2792 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2793 CPUID_EXT2_SYSCALL,
2794 .features[FEAT_8000_0001_ECX] =
2795 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2796 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2797 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2798 CPUID_EXT3_TOPOEXT,
6cfbc54e
EH		 2799 .features[FEAT_8000_0008_EBX] =
2800 CPUID_8000_0008_EBX_IBPB,
2801 .features[FEAT_7_0_EBX] =
2802 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2803 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2804 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2805 CPUID_7_0_EBX_SHA_NI,
2806 /* Missing: XSAVES (not supported by some Linux versions,
2807 * including v4.1 to v4.12).
2808 * KVM doesn't yet expose any XSAVES state save component.
2809 */
2810 .features[FEAT_XSAVE] =
2811 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2812 CPUID_XSAVE_XGETBV1,
2813 .features[FEAT_6_EAX] =
2814 CPUID_6_EAX_ARAT,
e0051647 2815 .xlevel = 0x8000001E,
6cfbc54e 2816 .model_id = "AMD EPYC Processor (with IBPB)",
fe52acd2 2817 .cache_info = &epyc_cache_info,
6cfbc54e 2818 },
c6dc6f63
AP		 2819};
2820
5114e842
EH		 2821typedef struct PropValue {
2822 const char *prop, *value;
2823} PropValue;
2824
2825/* KVM-specific features that are automatically added/removed
2826 * from all CPU models when KVM is enabled.
2827 */
2828static PropValue kvm_default_props[] = {
2829 { "kvmclock", "on" },
2830 { "kvm-nopiodelay", "on" },
2831 { "kvm-asyncpf", "on" },
2832 { "kvm-steal-time", "on" },
2833 { "kvm-pv-eoi", "on" },
2834 { "kvmclock-stable-bit", "on" },
2835 { "x2apic", "on" },
2836 { "acpi", "off" },
2837 { "monitor", "off" },
2838 { "svm", "off" },
2839 { NULL, NULL },
2840};
2841
04d99c3c
EH		 2842/* TCG-specific defaults that override all CPU models when using TCG
2843 */
2844static PropValue tcg_default_props[] = {
2845 { "vme", "off" },
2846 { NULL, NULL },
2847};
2848
2849
5114e842
EH		 2850void x86_cpu_change_kvm_default(const char *prop, const char *value)
2851{
2852 PropValue *pv;
2853 for (pv = kvm_default_props; pv->prop; pv++) {
2854 if (!strcmp(pv->prop, prop)) {
2855 pv->value = value;
2856 break;
2857 }
2858 }
2859
2860 /* It is valid to call this function only for properties that
2861 * are already present in the kvm_default_props table.
2862 */
2863 assert(pv->prop);
2864}
2865
4d1b279b
EH		 2866static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2867 bool migratable_only);
2868
40bfe48f
HZ		 2869static bool lmce_supported(void)
2870{
c62f2630 2871 uint64_t mce_cap = 0;
40bfe48f 2872
c62f2630 2873#ifdef CONFIG_KVM
40bfe48f
HZ		 2874 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
2875 return false;
2876 }
c62f2630 2877#endif
40bfe48f
HZ		 2878
2879 return !!(mce_cap & MCG_LMCE_P);
2880}
2881
7d8050b5
EH		 2882#define CPUID_MODEL_ID_SZ 48
2883
2884/**
2885 * cpu_x86_fill_model_id:
2886 * Get CPUID model ID string from host CPU.
2887 *
2888 * @str should have at least CPUID_MODEL_ID_SZ bytes
2889 *
2890 * The function does NOT add a null terminator to the string
2891 * automatically.
2892 */
c6dc6f63
AP		 2893static int cpu_x86_fill_model_id(char *str)
2894{
2895 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2896 int i;
2897
2898 for (i = 0; i < 3; i++) {
2899 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
2900 memcpy(str + i * 16 + 0, &eax, 4);
2901 memcpy(str + i * 16 + 4, &ebx, 4);
2902 memcpy(str + i * 16 + 8, &ecx, 4);
2903 memcpy(str + i * 16 + 12, &edx, 4);
2904 }
2905 return 0;
2906}
2907
c62f2630 2908static Property max_x86_cpu_properties[] = {
120eee7d 2909 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 2910 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 2911 DEFINE_PROP_END_OF_LIST()
2912};
2913
c62f2630 2914static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 2915{
84f1b92f 2916 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 2917 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 2918
f48c8837 2919 xcc->ordering = 9;
6e746f30 2920
ee465a3e 2921 xcc->model_description =
c62f2630 2922 "Enables all features supported by the accelerator in the current host";
d940ee9b 2923
c62f2630 2924 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 2925}
2926
0bacd8b3
EH		 2927static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
2928
c62f2630 2929static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 2930{
2931 X86CPU *cpu = X86_CPU(obj);
2932 CPUX86State *env = &cpu->env;
2933 KVMState *s = kvm_state;
d940ee9b 2934
4d1b279b
EH		 2935 /* We can't fill the features array here because we don't know yet if
2936 * "migratable" is true or false.
2937 */
44bd8e53 2938 cpu->max_features = true;
4d1b279b 2939
d6dcc558 2940 if (accel_uses_host_cpuid()) {
bd182022
EH		 2941 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
2942 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
2943 int family, model, stepping;
d6dcc558
SAGDR		 2944 X86CPUDefinition host_cpudef = { };
2945 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2946
2947 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
2948 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
0bacd8b3 2949
bd182022 2950 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 2951
bd182022 2952 cpu_x86_fill_model_id(model_id);
0bacd8b3 2953
bd182022
EH		 2954 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
2955 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
2956 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
2957 object_property_set_int(OBJECT(cpu), stepping, "stepping",
2958 &error_abort);
2959 object_property_set_str(OBJECT(cpu), model_id, "model-id",
2960 &error_abort);
0bacd8b3 2961
d6dcc558
SAGDR		 2962 if (kvm_enabled()) {
2963 env->cpuid_min_level =
2964 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
2965 env->cpuid_min_xlevel =
2966 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
2967 env->cpuid_min_xlevel2 =
2968 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2969 } else {
2970 env->cpuid_min_level =
2971 hvf_get_supported_cpuid(0x0, 0, R_EAX);
2972 env->cpuid_min_xlevel =
2973 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
2974 env->cpuid_min_xlevel2 =
2975 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
2976 }
40bfe48f
HZ		 2977
2978 if (lmce_supported()) {
2979 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
2980 }
6900d1cc
EH		 2981 } else {
2982 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
2983 "vendor", &error_abort);
2984 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
2985 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
2986 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
2987 object_property_set_str(OBJECT(cpu),
2988 "QEMU TCG CPU version " QEMU_HW_VERSION,
2989 "model-id", &error_abort);
e4356010 2990 }
2a573259 2991
d940ee9b 2992 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 2993}
2994
c62f2630
EH		 2995static const TypeInfo max_x86_cpu_type_info = {
2996 .name = X86_CPU_TYPE_NAME("max"),
2997 .parent = TYPE_X86_CPU,
2998 .instance_init = max_x86_cpu_initfn,
2999 .class_init = max_x86_cpu_class_init,
3000};
3001
d6dcc558 3002#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 3003static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
3004{
3005 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3006
d6dcc558 3007 xcc->host_cpuid_required = true;
c62f2630
EH		 3008 xcc->ordering = 8;
3009
02693cc4
GK		 3010#if defined(CONFIG_KVM)
3011 xcc->model_description =
3012 "KVM processor with all supported host features ";
3013#elif defined(CONFIG_HVF)
3014 xcc->model_description =
3015 "HVF processor with all supported host features ";
3016#endif
c62f2630
EH		 3017}
3018
d940ee9b
EH		 3019static const TypeInfo host_x86_cpu_type_info = {
3020 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 3021 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 3022 .class_init = host_x86_cpu_class_init,
3023};
3024
3025#endif
3026
07585923
RH		 3027static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
3028{
3029 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
3030
3031 switch (f->type) {
3032 case CPUID_FEATURE_WORD:
3033 {
3034 const char *reg = get_register_name_32(f->cpuid.reg);
3035 assert(reg);
3036 return g_strdup_printf("CPUID.%02XH:%s",
3037 f->cpuid.eax, reg);
3038 }
3039 case MSR_FEATURE_WORD:
3040 return g_strdup_printf("MSR(%02XH)",
3041 f->msr.index);
3042 }
3043
3044 return NULL;
3045}
3046
8459e396 3047static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 3048{
8459e396 3049 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63 3050 int i;
07585923 3051 char *feat_word_str;
c6dc6f63 3052
857aee33 3053 for (i = 0; i < 32; ++i) {
72370dc1 3054 if ((1UL << i) & mask) {
07585923
RH		 3055 feat_word_str = feature_word_description(f, i);
3056 warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
d6dcc558 3057 accel_uses_host_cpuid() ? "host" : "TCG",
07585923 3058 feat_word_str,
8297be80
AF		 3059 f->feat_names[i] ? "." : "",
3060 f->feat_names[i] ? f->feat_names[i] : "", i);
07585923 3061 g_free(feat_word_str);
c6dc6f63 3062 }
857aee33 3063 }
c6dc6f63
AP		 3064}
3065
d7bce999
EB		 3066static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
3067 const char *name, void *opaque,
3068 Error **errp)
95b8519d
AF		 3069{
3070 X86CPU *cpu = X86_CPU(obj);
3071 CPUX86State *env = &cpu->env;
3072 int64_t value;
3073
3074 value = (env->cpuid_version >> 8) & 0xf;
3075 if (value == 0xf) {
3076 value += (env->cpuid_version >> 20) & 0xff;
3077 }
51e72bc1 3078 visit_type_int(v, name, &value, errp);
95b8519d
AF		 3079}
3080
d7bce999
EB		 3081static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
3082 const char *name, void *opaque,
3083 Error **errp)
ed5e1ec3 3084{
71ad61d3
AF		 3085 X86CPU *cpu = X86_CPU(obj);
3086 CPUX86State *env = &cpu->env;
3087 const int64_t min = 0;
3088 const int64_t max = 0xff + 0xf;
65cd9064 3089 Error *local_err = NULL;
71ad61d3
AF		 3090 int64_t value;
3091
51e72bc1 3092 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3093 if (local_err) {
3094 error_propagate(errp, local_err);
71ad61d3
AF		 3095 return;
3096 }
3097 if (value < min || value > max) {
c6bd8c70
MA		 3098 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3099 name ? name : "null", value, min, max);
71ad61d3
AF		 3100 return;
3101 }
3102
ed5e1ec3 3103 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 3104 if (value > 0x0f) {
3105 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 3106 } else {
71ad61d3 3107 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 3108 }
3109}
3110
d7bce999
EB		 3111static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
3112 const char *name, void *opaque,
3113 Error **errp)
67e30c83
AF		 3114{
3115 X86CPU *cpu = X86_CPU(obj);
3116 CPUX86State *env = &cpu->env;
3117 int64_t value;
3118
3119 value = (env->cpuid_version >> 4) & 0xf;
3120 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 3121 visit_type_int(v, name, &value, errp);
67e30c83
AF		 3122}
3123
d7bce999
EB		 3124static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
3125 const char *name, void *opaque,
3126 Error **errp)
b0704cbd 3127{
c5291a4f
AF		 3128 X86CPU *cpu = X86_CPU(obj);
3129 CPUX86State *env = &cpu->env;
3130 const int64_t min = 0;
3131 const int64_t max = 0xff;
65cd9064 3132 Error *local_err = NULL;
c5291a4f
AF		 3133 int64_t value;
3134
51e72bc1 3135 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3136 if (local_err) {
3137 error_propagate(errp, local_err);
c5291a4f
AF		 3138 return;
3139 }
3140 if (value < min || value > max) {
c6bd8c70
MA		 3141 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3142 name ? name : "null", value, min, max);
c5291a4f
AF		 3143 return;
3144 }
3145
b0704cbd 3146 env->cpuid_version &= ~0xf00f0;
c5291a4f 3147 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 3148}
3149
35112e41 3150static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 3151 const char *name, void *opaque,
35112e41
AF		 3152 Error **errp)
3153{
3154 X86CPU *cpu = X86_CPU(obj);
3155 CPUX86State *env = &cpu->env;
3156 int64_t value;
3157
3158 value = env->cpuid_version & 0xf;
51e72bc1 3159 visit_type_int(v, name, &value, errp);
35112e41
AF		 3160}
3161
036e2222 3162static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 3163 const char *name, void *opaque,
036e2222 3164 Error **errp)
38c3dc46 3165{
036e2222
AF		 3166 X86CPU *cpu = X86_CPU(obj);
3167 CPUX86State *env = &cpu->env;
3168 const int64_t min = 0;
3169 const int64_t max = 0xf;
65cd9064 3170 Error *local_err = NULL;
036e2222
AF		 3171 int64_t value;
3172
51e72bc1 3173 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3174 if (local_err) {
3175 error_propagate(errp, local_err);
036e2222
AF		 3176 return;
3177 }
3178 if (value < min || value > max) {
c6bd8c70
MA		 3179 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3180 name ? name : "null", value, min, max);
036e2222
AF		 3181 return;
3182 }
3183
38c3dc46 3184 env->cpuid_version &= ~0xf;
036e2222 3185 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 3186}
3187
d480e1af
AF		 3188static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
3189{
3190 X86CPU *cpu = X86_CPU(obj);
3191 CPUX86State *env = &cpu->env;
3192 char *value;
d480e1af 3193
e42a92ae 3194 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 3195 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
3196 env->cpuid_vendor3);
d480e1af
AF		 3197 return value;
3198}
3199
3200static void x86_cpuid_set_vendor(Object *obj, const char *value,
3201 Error **errp)
3202{
3203 X86CPU *cpu = X86_CPU(obj);
3204 CPUX86State *env = &cpu->env;
3205 int i;
3206
9df694ee 3207 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 3208 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 3209 return;
3210 }
3211
3212 env->cpuid_vendor1 = 0;
3213 env->cpuid_vendor2 = 0;
3214 env->cpuid_vendor3 = 0;
3215 for (i = 0; i < 4; i++) {
3216 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
3217 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
3218 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
3219 }
d480e1af
AF		 3220}
3221
63e886eb
AF		 3222static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
3223{
3224 X86CPU *cpu = X86_CPU(obj);
3225 CPUX86State *env = &cpu->env;
3226 char *value;
3227 int i;
3228
3229 value = g_malloc(48 + 1);
3230 for (i = 0; i < 48; i++) {
3231 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
3232 }
3233 value[48] = '\0';
3234 return value;
3235}
3236
938d4c25
AF		 3237static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
3238 Error **errp)
dcce6675 3239{
938d4c25
AF		 3240 X86CPU *cpu = X86_CPU(obj);
3241 CPUX86State *env = &cpu->env;
dcce6675
AF		 3242 int c, len, i;
3243
3244 if (model_id == NULL) {
3245 model_id = "";
3246 }
3247 len = strlen(model_id);
d0a6acf4 3248 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 3249 for (i = 0; i < 48; i++) {
3250 if (i >= len) {
3251 c = '\0';
3252 } else {
3253 c = (uint8_t)model_id[i];
3254 }
3255 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
3256 }
3257}
3258
d7bce999
EB		 3259static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
3260 void *opaque, Error **errp)
89e48965
AF		 3261{
3262 X86CPU *cpu = X86_CPU(obj);
3263 int64_t value;
3264
3265 value = cpu->env.tsc_khz * 1000;
51e72bc1 3266 visit_type_int(v, name, &value, errp);
89e48965
AF		 3267}
3268
d7bce999
EB		 3269static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
3270 void *opaque, Error **errp)
89e48965
AF		 3271{
3272 X86CPU *cpu = X86_CPU(obj);
3273 const int64_t min = 0;
2e84849a 3274 const int64_t max = INT64_MAX;
65cd9064 3275 Error *local_err = NULL;
89e48965
AF		 3276 int64_t value;
3277
51e72bc1 3278 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3279 if (local_err) {
3280 error_propagate(errp, local_err);
89e48965
AF		 3281 return;
3282 }
3283 if (value < min || value > max) {
c6bd8c70
MA		 3284 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3285 name ? name : "null", value, min, max);
89e48965
AF		 3286 return;
3287 }
3288
36f96c4b 3289 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 3290}
3291
7e5292b5 3292/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 3293static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
3294 const char *name, void *opaque,
3295 Error **errp)
8e8aba50 3296{
7e5292b5 3297 uint32_t *array = (uint32_t *)opaque;
8e8aba50 3298 FeatureWord w;
8e8aba50
EH		 3299 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
3300 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
3301 X86CPUFeatureWordInfoList *list = NULL;
3302
3303 for (w = 0; w < FEATURE_WORDS; w++) {
3304 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 3305 /*
3306 * We didn't have MSR features when "feature-words" was
3307 * introduced. Therefore skipped other type entries.
3308 */
3309 if (wi->type != CPUID_FEATURE_WORD) {
3310 continue;
3311 }
8e8aba50 3312 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 3313 qwi->cpuid_input_eax = wi->cpuid.eax;
3314 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
3315 qwi->cpuid_input_ecx = wi->cpuid.ecx;
3316 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 3317 qwi->features = array[w];
8e8aba50
EH		 3318
3319 /* List will be in reverse order, but order shouldn't matter */
3320 list_entries[w].next = list;
3321 list_entries[w].value = &word_infos[w];
3322 list = &list_entries[w];
3323 }
3324
6b62d961 3325 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 3326}
3327
d7bce999
EB		 3328static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3329 void *opaque, Error **errp)
c8f0f88e
IM		 3330{
3331 X86CPU *cpu = X86_CPU(obj);
3332 int64_t value = cpu->hyperv_spinlock_attempts;
3333
51e72bc1 3334 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 3335}
3336
d7bce999
EB		 3337static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3338 void *opaque, Error **errp)
c8f0f88e
IM		 3339{
3340 const int64_t min = 0xFFF;
3341 const int64_t max = UINT_MAX;
3342 X86CPU *cpu = X86_CPU(obj);
3343 Error *err = NULL;
3344 int64_t value;
3345
51e72bc1 3346 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 3347 if (err) {
3348 error_propagate(errp, err);
3349 return;
3350 }
3351
3352 if (value < min || value > max) {
3353 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 3354 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
3355 object_get_typename(obj), name ? name : "null",
3356 value, min, max);
c8f0f88e
IM		 3357 return;
3358 }
3359 cpu->hyperv_spinlock_attempts = value;
3360}
3361
1b6b7d10 3362static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 3363 .name = "int",
3364 .get = x86_get_hv_spinlocks,
3365 .set = x86_set_hv_spinlocks,
3366};
3367
72ac2e87
IM		 3368/* Convert all '_' in a feature string option name to '-', to make feature
3369 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3370 */
3371static inline void feat2prop(char *s)
3372{
3373 while ((s = strchr(s, '_'))) {
3374 *s = '-';
3375 }
3376}
3377
b54c9377
EH		 3378/* Return the feature property name for a feature flag bit */
3379static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
3380{
3381 /* XSAVE components are automatically enabled by other features,
3382 * so return the original feature name instead
3383 */
3384 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
3385 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
3386
3387 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
3388 x86_ext_save_areas[comp].bits) {
3389 w = x86_ext_save_areas[comp].feature;
3390 bitnr = ctz32(x86_ext_save_areas[comp].bits);
3391 }
3392 }
3393
3394 assert(bitnr < 32);
3395 assert(w < FEATURE_WORDS);
3396 return feature_word_info[w].feat_names[bitnr];
3397}
3398
dc15c051
IM		 3399/* Compatibily hack to maintain legacy +-feat semantic,
3400 * where +-feat overwrites any feature set by
3401 * feat=on|feat even if the later is parsed after +-feat
3402 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3403 */
2fae0d96 3404static GList *plus_features, *minus_features;
dc15c051 3405
83a00f60
EH		 3406static gint compare_string(gconstpointer a, gconstpointer b)
3407{
3408 return g_strcmp0(a, b);
3409}
3410
8f961357
EH		 3411/* Parse "+feature,-feature,feature=foo" CPU feature string
3412 */
62a48a2a 3413static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 3414 Error **errp)
8f961357 3415{
8f961357 3416 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 3417 static bool cpu_globals_initialized;
83a00f60 3418 bool ambiguous = false;
62a48a2a
IM		 3419
3420 if (cpu_globals_initialized) {
3421 return;
3422 }
3423 cpu_globals_initialized = true;
8f961357 3424
f6750e95
EH		 3425 if (!features) {
3426 return;
3427 }
3428
3429 for (featurestr = strtok(features, ",");
685479bd 3430 featurestr;
f6750e95
EH		 3431 featurestr = strtok(NULL, ",")) {
3432 const char *name;
3433 const char *val = NULL;
3434 char *eq = NULL;
cf2887c9 3435 char num[32];
62a48a2a 3436 GlobalProperty *prop;
c6dc6f63 3437
f6750e95 3438 /* Compatibility syntax: */
c6dc6f63 3439 if (featurestr[0] == '+') {
2fae0d96
EH		 3440 plus_features = g_list_append(plus_features,
3441 g_strdup(featurestr + 1));
f6750e95 3442 continue;
c6dc6f63 3443 } else if (featurestr[0] == '-') {
2fae0d96
EH		 3444 minus_features = g_list_append(minus_features,
3445 g_strdup(featurestr + 1));
f6750e95
EH		 3446 continue;
3447 }
3448
3449 eq = strchr(featurestr, '=');
3450 if (eq) {
3451 *eq++ = 0;
3452 val = eq;
c6dc6f63 3453 } else {
f6750e95 3454 val = "on";
a91987c2 3455 }
f6750e95
EH		 3456
3457 feat2prop(featurestr);
3458 name = featurestr;
3459
83a00f60 3460 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 3461 warn_report("Ambiguous CPU model string. "
3462 "Don't mix both \"+%s\" and \"%s=%s\"",
3463 name, name, val);
83a00f60
EH		 3464 ambiguous = true;
3465 }
3466 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 3467 warn_report("Ambiguous CPU model string. "
3468 "Don't mix both \"-%s\" and \"%s=%s\"",
3469 name, name, val);
83a00f60
EH		 3470 ambiguous = true;
3471 }
3472
f6750e95
EH		 3473 /* Special case: */
3474 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 3475 int ret;
f46bfdbf 3476 uint64_t tsc_freq;
f6750e95 3477
f17fd4fd 3478 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 3479 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 3480 error_setg(errp, "bad numerical value %s", val);
3481 return;
3482 }
3483 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3484 val = num;
3485 name = "tsc-frequency";
c6dc6f63 3486 }
f6750e95 3487
62a48a2a
IM		 3488 prop = g_new0(typeof(*prop), 1);
3489 prop->driver = typename;
3490 prop->property = g_strdup(name);
3491 prop->value = g_strdup(val);
3492 prop->errp = &error_fatal;
3493 qdev_prop_register_global(prop);
f6750e95
EH		 3494 }
3495
83a00f60 3496 if (ambiguous) {
3dc6f869
AF		 3497 warn_report("Compatibility of ambiguous CPU model "
3498 "strings won't be kept on future QEMU versions");
83a00f60 3499 }
c6dc6f63
AP		 3500}
3501
b8d834a0 3502static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 3503static int x86_cpu_filter_features(X86CPU *cpu);
3504
3505/* Check for missing features that may prevent the CPU class from
3506 * running using the current machine and accelerator.
3507 */
3508static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3509 strList **missing_feats)
3510{
3511 X86CPU *xc;
3512 FeatureWord w;
3513 Error *err = NULL;
3514 strList **next = missing_feats;
3515
d6dcc558 3516 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 3517 strList *new = g_new0(strList, 1);
3c254ab8 3518 new->value = g_strdup("kvm");
b54c9377
EH		 3519 *missing_feats = new;
3520 return;
3521 }
3522
3523 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3524
b8d834a0 3525 x86_cpu_expand_features(xc, &err);
b54c9377 3526 if (err) {
b8d834a0 3527 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 3528 * but in case it does, just report the model as not
3529 * runnable at all using the "type" property.
3530 */
3531 strList *new = g_new0(strList, 1);
3532 new->value = g_strdup("type");
3533 *next = new;
3534 next = &new->next;
3535 }
3536
3537 x86_cpu_filter_features(xc);
3538
3539 for (w = 0; w < FEATURE_WORDS; w++) {
3540 uint32_t filtered = xc->filtered_features[w];
3541 int i;
3542 for (i = 0; i < 32; i++) {
3543 if (filtered & (1UL << i)) {
3544 strList *new = g_new0(strList, 1);
3545 new->value = g_strdup(x86_cpu_feature_name(w, i));
3546 *next = new;
3547 next = &new->next;
3548 }
3549 }
3550 }
3551
3552 object_unref(OBJECT(xc));
3553}
3554
8c3329e5 3555/* Print all cpuid feature names in featureset
c6dc6f63 3556 */
cc643b1e 3557static void listflags(FILE *f, fprintf_function print, GList *features)
0856579c 3558{
cc643b1e
DB		 3559 size_t len = 0;
3560 GList *tmp;
3561
3562 for (tmp = features; tmp; tmp = tmp->next) {
3563 const char *name = tmp->data;
3564 if ((len + strlen(name) + 1) >= 75) {
3565 print(f, "\n");
3566 len = 0;
c6dc6f63 3567 }
cc643b1e
DB		 3568 print(f, "%s%s", len == 0 ? " " : " ", name);
3569 len += strlen(name) + 1;
8c3329e5 3570 }
cc643b1e 3571 print(f, "\n");
c6dc6f63
AP		 3572}
3573
f48c8837 3574/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 3575static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3576{
3577 ObjectClass *class_a = (ObjectClass *)a;
3578 ObjectClass *class_b = (ObjectClass *)b;
3579 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3580 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b
DB		 3581 char *name_a, *name_b;
3582 int ret;
ee465a3e 3583
f48c8837 3584 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 3585 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 3586 } else {
c7dbff4b
DB		 3587 name_a = x86_cpu_class_get_model_name(cc_a);
3588 name_b = x86_cpu_class_get_model_name(cc_b);
3589 ret = strcmp(name_a, name_b);
3590 g_free(name_a);
3591 g_free(name_b);
ee465a3e 3592 }
c7dbff4b 3593 return ret;
ee465a3e
EH		 3594}
3595
3596static GSList *get_sorted_cpu_model_list(void)
3597{
3598 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3599 list = g_slist_sort(list, x86_cpu_list_compare);
3600 return list;
3601}
3602
3603static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3604{
3605 ObjectClass *oc = data;
3606 X86CPUClass *cc = X86_CPU_CLASS(oc);
3607 CPUListState *s = user_data;
3608 char *name = x86_cpu_class_get_model_name(cc);
3609 const char *desc = cc->model_description;
0bacd8b3 3610 if (!desc && cc->cpu_def) {
ee465a3e
EH		 3611 desc = cc->cpu_def->model_id;
3612 }
3613
081492ca 3614 (*s->cpu_fprintf)(s->file, "x86 %-20s %-48s\n",
ee465a3e
EH		 3615 name, desc);
3616 g_free(name);
3617}
3618
3619/* list available CPU models and flags */
e916cbf8 3620void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 3621{
cc643b1e 3622 int i, j;
ee465a3e
EH		 3623 CPUListState s = {
3624 .file = f,
3625 .cpu_fprintf = cpu_fprintf,
3626 };
3627 GSList *list;
cc643b1e 3628 GList *names = NULL;
c6dc6f63 3629
ee465a3e
EH		 3630 (*cpu_fprintf)(f, "Available CPUs:\n");
3631 list = get_sorted_cpu_model_list();
3632 g_slist_foreach(list, x86_cpu_list_entry, &s);
3633 g_slist_free(list);
21ad7789 3634
cc643b1e 3635 names = NULL;
3af60be2
JK		 3636 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3637 FeatureWordInfo *fw = &feature_word_info[i];
cc643b1e
DB		 3638 for (j = 0; j < 32; j++) {
3639 if (fw->feat_names[j]) {
3640 names = g_list_append(names, (gpointer)fw->feat_names[j]);
3641 }
3642 }
3af60be2 3643 }
cc643b1e
DB		 3644
3645 names = g_list_sort(names, (GCompareFunc)strcmp);
3646
3647 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3648 listflags(f, cpu_fprintf, names);
3649 (*cpu_fprintf)(f, "\n");
3650 g_list_free(names);
c6dc6f63
AP		 3651}
3652
ee465a3e
EH		 3653static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3654{
3655 ObjectClass *oc = data;
3656 X86CPUClass *cc = X86_CPU_CLASS(oc);
3657 CpuDefinitionInfoList **cpu_list = user_data;
3658 CpuDefinitionInfoList *entry;
3659 CpuDefinitionInfo *info;
3660
3661 info = g_malloc0(sizeof(*info));
3662 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 3663 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3664 info->has_unavailable_features = true;
8ed877b7 3665 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 3666 info->migration_safe = cc->migration_safe;
3667 info->has_migration_safe = true;
5adbed30 3668 info->q_static = cc->static_model;
ee465a3e
EH		 3669
3670 entry = g_malloc0(sizeof(*entry));
3671 entry->value = info;
3672 entry->next = *cpu_list;
3673 *cpu_list = entry;
3674}
3675
76b64a7a 3676CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 3677{
3678 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 3679 GSList *list = get_sorted_cpu_model_list();
3680 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3681 g_slist_free(list);
e3966126
AL		 3682 return cpu_list;
3683}
3684
84f1b92f
EH		 3685static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3686 bool migratable_only)
27418adf
EH		 3687{
3688 FeatureWordInfo *wi = &feature_word_info[w];
07585923 3689 uint32_t r = 0;
27418adf 3690
fefb41bf 3691 if (kvm_enabled()) {
07585923
RH		 3692 switch (wi->type) {
3693 case CPUID_FEATURE_WORD:
3694 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
3695 wi->cpuid.ecx,
3696 wi->cpuid.reg);
3697 break;
3698 case MSR_FEATURE_WORD:
3699 r = kvm_arch_get_supported_msr_feature(kvm_state, wi->msr.index);
3700 break;
3701 }
d6dcc558 3702 } else if (hvf_enabled()) {
07585923
RH		 3703 if (wi->type != CPUID_FEATURE_WORD) {
3704 return 0;
3705 }
3706 r = hvf_get_supported_cpuid(wi->cpuid.eax,
3707 wi->cpuid.ecx,
3708 wi->cpuid.reg);
fefb41bf 3709 } else if (tcg_enabled()) {
84f1b92f 3710 r = wi->tcg_features;
fefb41bf
EH		 3711 } else {
3712 return ~0;
3713 }
84f1b92f
EH		 3714 if (migratable_only) {
3715 r &= x86_cpu_get_migratable_flags(w);
3716 }
3717 return r;
27418adf
EH		 3718}
3719
8ca30e86
EH		 3720static void x86_cpu_report_filtered_features(X86CPU *cpu)
3721{
3722 FeatureWord w;
3723
3724 for (w = 0; w < FEATURE_WORDS; w++) {
3725 report_unavailable_features(w, cpu->filtered_features[w]);
3726 }
3727}
3728
5114e842
EH		 3729static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3730{
3731 PropValue *pv;
3732 for (pv = props; pv->prop; pv++) {
3733 if (!pv->value) {
3734 continue;
3735 }
3736 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3737 &error_abort);
3738 }
3739}
3740
f99fd7ca 3741/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 3742 */
d940ee9b 3743static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 3744{
61dcd775 3745 CPUX86State *env = &cpu->env;
74f54bc4
EH		 3746 const char *vendor;
3747 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 3748 FeatureWord w;
c6dc6f63 3749
f99fd7ca
EH		 3750 /*NOTE: any property set by this function should be returned by
3751 * x86_cpu_static_props(), so static expansion of
3752 * query-cpu-model-expansion is always complete.
3753 */
3754
c39c0edf 3755 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 3756 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3757 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 3758
2d64255b
AF		 3759 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3760 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3761 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 3762 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 3763 for (w = 0; w < FEATURE_WORDS; w++) {
3764 env->features[w] = def->features[w];
3765 }
82beb536 3766
a9f27ea9
EH		 3767 /* legacy-cache defaults to 'off' if CPU model provides cache info */
3768 cpu->legacy_cache = !def->cache_info;
ab8f992e 3769
9576de75 3770 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 3771 /* TODO: in-kernel irqchip for hvf */
82beb536 3772 if (kvm_enabled()) {
492a4c94
LT		 3773 if (!kvm_irqchip_in_kernel()) {
3774 x86_cpu_change_kvm_default("x2apic", "off");
3775 }
3776
5114e842 3777 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 3778 } else if (tcg_enabled()) {
3779 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 3780 }
5fcca9ff 3781
82beb536 3782 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 3783
3784 /* sysenter isn't supported in compatibility mode on AMD,
3785 * syscall isn't supported in compatibility mode on Intel.
3786 * Normally we advertise the actual CPU vendor, but you can
3787 * override this using the 'vendor' property if you want to use
3788 * KVM's sysenter/syscall emulation in compatibility mode and
3789 * when doing cross vendor migration
3790 */
74f54bc4 3791 vendor = def->vendor;
d6dcc558 3792 if (accel_uses_host_cpuid()) {
7c08db30
EH		 3793 uint32_t ebx = 0, ecx = 0, edx = 0;
3794 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3795 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3796 vendor = host_vendor;
3797 }
3798
3799 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3800
c6dc6f63
AP		 3801}
3802
f99fd7ca
EH		 3803/* Return a QDict containing keys for all properties that can be included
3804 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3805 * must be included in the dictionary.
3806 */
3807static QDict *x86_cpu_static_props(void)
3808{
3809 FeatureWord w;
3810 int i;
3811 static const char *props[] = {
3812 "min-level",
3813 "min-xlevel",
3814 "family",
3815 "model",
3816 "stepping",
3817 "model-id",
3818 "vendor",
3819 "lmce",
3820 NULL,
3821 };
3822 static QDict *d;
3823
3824 if (d) {
3825 return d;
3826 }
3827
3828 d = qdict_new();
3829 for (i = 0; props[i]; i++) {
0f9afc2a 3830 qdict_put_null(d, props[i]);
f99fd7ca
EH		 3831 }
3832
3833 for (w = 0; w < FEATURE_WORDS; w++) {
3834 FeatureWordInfo *fi = &feature_word_info[w];
3835 int bit;
3836 for (bit = 0; bit < 32; bit++) {
3837 if (!fi->feat_names[bit]) {
3838 continue;
3839 }
0f9afc2a 3840 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 3841 }
3842 }
3843
3844 return d;
3845}
3846
3847/* Add an entry to @props dict, with the value for property. */
3848static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
3849{
3850 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
3851 &error_abort);
3852
3853 qdict_put_obj(props, prop, value);
3854}
3855
3856/* Convert CPU model data from X86CPU object to a property dictionary
3857 * that can recreate exactly the same CPU model.
3858 */
3859static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
3860{
3861 QDict *sprops = x86_cpu_static_props();
3862 const QDictEntry *e;
3863
3864 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
3865 const char *prop = qdict_entry_key(e);
3866 x86_cpu_expand_prop(cpu, props, prop);
3867 }
3868}
3869
b8097deb
EH		 3870/* Convert CPU model data from X86CPU object to a property dictionary
3871 * that can recreate exactly the same CPU model, including every
3872 * writeable QOM property.
3873 */
3874static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
3875{
3876 ObjectPropertyIterator iter;
3877 ObjectProperty *prop;
3878
3879 object_property_iter_init(&iter, OBJECT(cpu));
3880 while ((prop = object_property_iter_next(&iter))) {
3881 /* skip read-only or write-only properties */
3882 if (!prop->get || !prop->set) {
3883 continue;
3884 }
3885
3886 /* "hotplugged" is the only property that is configurable
3887 * on the command-line but will be set differently on CPUs
3888 * created using "-cpu ... -smp ..." and by CPUs created
3889 * on the fly by x86_cpu_from_model() for querying. Skip it.
3890 */
3891 if (!strcmp(prop->name, "hotplugged")) {
3892 continue;
3893 }
3894 x86_cpu_expand_prop(cpu, props, prop->name);
3895 }
3896}
3897
f99fd7ca
EH		 3898static void object_apply_props(Object *obj, QDict *props, Error **errp)
3899{
3900 const QDictEntry *prop;
3901 Error *err = NULL;
3902
3903 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
3904 object_property_set_qobject(obj, qdict_entry_value(prop),
3905 qdict_entry_key(prop), &err);
3906 if (err) {
3907 break;
3908 }
3909 }
3910
3911 error_propagate(errp, err);
3912}
3913
3914/* Create X86CPU object according to model+props specification */
3915static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
3916{
3917 X86CPU *xc = NULL;
3918 X86CPUClass *xcc;
3919 Error *err = NULL;
3920
3921 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
3922 if (xcc == NULL) {
3923 error_setg(&err, "CPU model '%s' not found", model);
3924 goto out;
3925 }
3926
3927 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3928 if (props) {
3929 object_apply_props(OBJECT(xc), props, &err);
3930 if (err) {
3931 goto out;
3932 }
3933 }
3934
3935 x86_cpu_expand_features(xc, &err);
3936 if (err) {
3937 goto out;
3938 }
3939
3940out:
3941 if (err) {
3942 error_propagate(errp, err);
3943 object_unref(OBJECT(xc));
3944 xc = NULL;
3945 }
3946 return xc;
3947}
3948
3949CpuModelExpansionInfo *
3950arch_query_cpu_model_expansion(CpuModelExpansionType type,
3951 CpuModelInfo *model,
3952 Error **errp)
3953{
3954 X86CPU *xc = NULL;
3955 Error *err = NULL;
3956 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
3957 QDict *props = NULL;
3958 const char *base_name;
3959
3960 xc = x86_cpu_from_model(model->name,
3961 model->has_props ?
7dc847eb 3962 qobject_to(QDict, model->props) :
f99fd7ca
EH		 3963 NULL, &err);
3964 if (err) {
3965 goto out;
3966 }
3967
b8097deb 3968 props = qdict_new();
e38bf612
EH		 3969 ret->model = g_new0(CpuModelInfo, 1);
3970 ret->model->props = QOBJECT(props);
3971 ret->model->has_props = true;
f99fd7ca
EH		 3972
3973 switch (type) {
3974 case CPU_MODEL_EXPANSION_TYPE_STATIC:
3975 /* Static expansion will be based on "base" only */
3976 base_name = "base";
b8097deb 3977 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 3978 break;
3979 case CPU_MODEL_EXPANSION_TYPE_FULL:
3980 /* As we don't return every single property, full expansion needs
3981 * to keep the original model name+props, and add extra
3982 * properties on top of that.
3983 */
3984 base_name = model->name;
b8097deb 3985 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 3986 break;
3987 default:
3988 error_setg(&err, "Unsupportted expansion type");
3989 goto out;
3990 }
3991
f99fd7ca
EH		 3992 x86_cpu_to_dict(xc, props);
3993
f99fd7ca 3994 ret->model->name = g_strdup(base_name);
f99fd7ca
EH		 3995
3996out:
3997 object_unref(OBJECT(xc));
3998 if (err) {
3999 error_propagate(errp, err);
4000 qapi_free_CpuModelExpansionInfo(ret);
4001 ret = NULL;
4002 }
4003 return ret;
4004}
4005
00fcd100
AB		 4006static gchar *x86_gdb_arch_name(CPUState *cs)
4007{
4008#ifdef TARGET_X86_64
4009 return g_strdup("i386:x86-64");
4010#else
4011 return g_strdup("i386");
4012#endif
4013}
4014
d940ee9b
EH		 4015static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
4016{
4017 X86CPUDefinition *cpudef = data;
4018 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4019
4020 xcc->cpu_def = cpudef;
bd72159d 4021 xcc->migration_safe = true;
d940ee9b
EH		 4022}
4023
4024static void x86_register_cpudef_type(X86CPUDefinition *def)
4025{
4026 char *typename = x86_cpu_type_name(def->name);
4027 TypeInfo ti = {
4028 .name = typename,
4029 .parent = TYPE_X86_CPU,
4030 .class_init = x86_cpu_cpudef_class_init,
4031 .class_data = def,
4032 };
4033
2a923a29
EH		 4034 /* AMD aliases are handled at runtime based on CPUID vendor, so
4035 * they shouldn't be set on the CPU model table.
4036 */
4037 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 4038 /* catch mistakes instead of silently truncating model_id when too long */
4039 assert(def->model_id && strlen(def->model_id) <= 48);
4040
2a923a29 4041
d940ee9b
EH		 4042 type_register(&ti);
4043 g_free(typename);
4044}
4045
c6dc6f63 4046#if !defined(CONFIG_USER_ONLY)
c6dc6f63 4047
0e26b7b8
BS		 4048void cpu_clear_apic_feature(CPUX86State *env)
4049{
0514ef2f 4050 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 4051}
4052
c6dc6f63
AP		 4053#endif /* !CONFIG_USER_ONLY */
4054
c6dc6f63
AP		 4055void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
4056 uint32_t *eax, uint32_t *ebx,
4057 uint32_t *ecx, uint32_t *edx)
4058{
a60f24b5
AF		 4059 X86CPU *cpu = x86_env_get_cpu(env);
4060 CPUState *cs = CPU(cpu);
14c985cf 4061 uint32_t pkg_offset;
4ed3d478 4062 uint32_t limit;
1ce36bfe 4063 uint32_t signature[3];
a60f24b5 4064
4ed3d478
DB		 4065 /* Calculate & apply limits for different index ranges */
4066 if (index >= 0xC0000000) {
4067 limit = env->cpuid_xlevel2;
4068 } else if (index >= 0x80000000) {
4069 limit = env->cpuid_xlevel;
1ce36bfe
DB		 4070 } else if (index >= 0x40000000) {
4071 limit = 0x40000001;
c6dc6f63 4072 } else {
4ed3d478
DB		 4073 limit = env->cpuid_level;
4074 }
4075
4076 if (index > limit) {
4077 /* Intel documentation states that invalid EAX input will
4078 * return the same information as EAX=cpuid_level
4079 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
4080 */
4081 index = env->cpuid_level;
c6dc6f63
AP		 4082 }
4083
4084 switch(index) {
4085 case 0:
4086 *eax = env->cpuid_level;
5eb2f7a4
EH		 4087 *ebx = env->cpuid_vendor1;
4088 *edx = env->cpuid_vendor2;
4089 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 4090 break;
4091 case 1:
4092 *eax = env->cpuid_version;
7e72a45c
EH		 4093 *ebx = (cpu->apic_id << 24) |
4094 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 4095 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 4096 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
4097 *ecx |= CPUID_EXT_OSXSAVE;
4098 }
0514ef2f 4099 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 4100 if (cs->nr_cores * cs->nr_threads > 1) {
4101 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 4102 *edx |= CPUID_HT;
c6dc6f63
AP		 4103 }
4104 break;
4105 case 2:
4106 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 4107 if (cpu->cache_info_passthrough) {
4108 host_cpuid(index, 0, eax, ebx, ecx, edx);
4109 break;
4110 }
5e891bf8 4111 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 4112 *ebx = 0;
14c985cf
LM		 4113 if (!cpu->enable_l3_cache) {
4114 *ecx = 0;
4115 } else {
a9f27ea9 4116 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 4117 }
a9f27ea9
EH		 4118 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
4119 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
4120 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 4121 break;
4122 case 4:
4123 /* cache info: needed for Core compatibility */
787aaf57
BC		 4124 if (cpu->cache_info_passthrough) {
4125 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 4126 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 4127 *eax &= ~0xFC000000;
7e3482f8
EH		 4128 if ((*eax & 31) && cs->nr_cores > 1) {
4129 *eax |= (cs->nr_cores - 1) << 26;
4130 }
c6dc6f63 4131 } else {
2f7a21c4 4132 *eax = 0;
76c2975a 4133 switch (count) {
c6dc6f63 4134 case 0: /* L1 dcache info */
a9f27ea9
EH		 4135 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
4136 1, cs->nr_cores,
7e3482f8 4137 eax, ebx, ecx, edx);
c6dc6f63
AP		 4138 break;
4139 case 1: /* L1 icache info */
a9f27ea9
EH		 4140 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
4141 1, cs->nr_cores,
7e3482f8 4142 eax, ebx, ecx, edx);
c6dc6f63
AP		 4143 break;
4144 case 2: /* L2 cache info */
a9f27ea9
EH		 4145 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
4146 cs->nr_threads, cs->nr_cores,
7e3482f8 4147 eax, ebx, ecx, edx);
c6dc6f63 4148 break;
14c985cf 4149 case 3: /* L3 cache info */
7e3482f8
EH		 4150 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4151 if (cpu->enable_l3_cache) {
a9f27ea9
EH		 4152 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
4153 (1 << pkg_offset), cs->nr_cores,
7e3482f8 4154 eax, ebx, ecx, edx);
14c985cf
LM		 4155 break;
4156 }
7e3482f8 4157 /* fall through */
c6dc6f63 4158 default: /* end of info */
7e3482f8 4159 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 4160 break;
76c2975a
PB		 4161 }
4162 }
c6dc6f63
AP		 4163 break;
4164 case 5:
2266d443
MT		 4165 /* MONITOR/MWAIT Leaf */
4166 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
4167 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
4168 *ecx = cpu->mwait.ecx; /* flags */
4169 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 4170 break;
4171 case 6:
4172 /* Thermal and Power Leaf */
28b8e4d0 4173 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 4174 *ebx = 0;
4175 *ecx = 0;
4176 *edx = 0;
4177 break;
f7911686 4178 case 7:
13526728
EH		 4179 /* Structured Extended Feature Flags Enumeration Leaf */
4180 if (count == 0) {
4181 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 4182 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 4183 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 4184 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
4185 *ecx |= CPUID_7_0_ECX_OSPKE;
4186 }
95ea69fb 4187 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 4188 } else {
4189 *eax = 0;
4190 *ebx = 0;
4191 *ecx = 0;
4192 *edx = 0;
4193 }
4194 break;
c6dc6f63
AP		 4195 case 9:
4196 /* Direct Cache Access Information Leaf */
4197 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
4198 *ebx = 0;
4199 *ecx = 0;
4200 *edx = 0;
4201 break;
4202 case 0xA:
4203 /* Architectural Performance Monitoring Leaf */
9337e3b6 4204 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 4205 KVMState *s = cs->kvm_state;
a0fa8208
GN		 4206
4207 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
4208 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
4209 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
4210 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 4211 } else if (hvf_enabled() && cpu->enable_pmu) {
4212 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
4213 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
4214 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
4215 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 4216 } else {
4217 *eax = 0;
4218 *ebx = 0;
4219 *ecx = 0;
4220 *edx = 0;
4221 }
c6dc6f63 4222 break;
5232d00a
RK		 4223 case 0xB:
4224 /* Extended Topology Enumeration Leaf */
4225 if (!cpu->enable_cpuid_0xb) {
4226 *eax = *ebx = *ecx = *edx = 0;
4227 break;
4228 }
4229
4230 *ecx = count & 0xff;
4231 *edx = cpu->apic_id;
4232
4233 switch (count) {
4234 case 0:
eab60fb9
MAL		 4235 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
4236 *ebx = cs->nr_threads;
5232d00a
RK		 4237 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
4238 break;
4239 case 1:
eab60fb9
MAL		 4240 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4241 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 4242 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
4243 break;
4244 default:
4245 *eax = 0;
4246 *ebx = 0;
4247 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
4248 }
4249
4250 assert(!(*eax & ~0x1f));
4251 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
4252 break;
2560f19f 4253 case 0xD: {
51e49430 4254 /* Processor Extended State */
2560f19f
PB		 4255 *eax = 0;
4256 *ebx = 0;
4257 *ecx = 0;
4258 *edx = 0;
19dc85db 4259 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 4260 break;
4261 }
4928cd6d 4262
2560f19f 4263 if (count == 0) {
96193c22
EH		 4264 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
4265 *eax = env->features[FEAT_XSAVE_COMP_LO];
4266 *edx = env->features[FEAT_XSAVE_COMP_HI];
de2e68c9 4267 *ebx = xsave_area_size(env->xcr0);
2560f19f 4268 } else if (count == 1) {
0bb0b2d2 4269 *eax = env->features[FEAT_XSAVE];
f4f1110e 4270 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 4271 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
4272 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 4273 *eax = esa->size;
4274 *ebx = esa->offset;
2560f19f 4275 }
51e49430
SY		 4276 }
4277 break;
2560f19f 4278 }
e37a5c7f
CP		 4279 case 0x14: {
4280 /* Intel Processor Trace Enumeration */
4281 *eax = 0;
4282 *ebx = 0;
4283 *ecx = 0;
4284 *edx = 0;
4285 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
4286 !kvm_enabled()) {
4287 break;
4288 }
4289
4290 if (count == 0) {
4291 *eax = INTEL_PT_MAX_SUBLEAF;
4292 *ebx = INTEL_PT_MINIMAL_EBX;
4293 *ecx = INTEL_PT_MINIMAL_ECX;
4294 } else if (count == 1) {
4295 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
4296 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
4297 }
4298 break;
4299 }
1ce36bfe
DB		 4300 case 0x40000000:
4301 /*
4302 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4303 * set here, but we restrict to TCG none the less.
4304 */
4305 if (tcg_enabled() && cpu->expose_tcg) {
4306 memcpy(signature, "TCGTCGTCGTCG", 12);
4307 *eax = 0x40000001;
4308 *ebx = signature[0];
4309 *ecx = signature[1];
4310 *edx = signature[2];
4311 } else {
4312 *eax = 0;
4313 *ebx = 0;
4314 *ecx = 0;
4315 *edx = 0;
4316 }
4317 break;
4318 case 0x40000001:
4319 *eax = 0;
4320 *ebx = 0;
4321 *ecx = 0;
4322 *edx = 0;
4323 break;
c6dc6f63
AP		 4324 case 0x80000000:
4325 *eax = env->cpuid_xlevel;
4326 *ebx = env->cpuid_vendor1;
4327 *edx = env->cpuid_vendor2;
4328 *ecx = env->cpuid_vendor3;
4329 break;
4330 case 0x80000001:
4331 *eax = env->cpuid_version;
4332 *ebx = 0;
0514ef2f
EH		 4333 *ecx = env->features[FEAT_8000_0001_ECX];
4334 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 4335
4336 /* The Linux kernel checks for the CMPLegacy bit and
4337 * discards multiple thread information if it is set.
cb8d4c8f 4338 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 4339 */
ce3960eb 4340 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 4341 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
4342 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
4343 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 4344 *ecx |= 1 << 1; /* CmpLegacy bit */
4345 }
4346 }
c6dc6f63
AP		 4347 break;
4348 case 0x80000002:
4349 case 0x80000003:
4350 case 0x80000004:
4351 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
4352 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
4353 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
4354 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
4355 break;
4356 case 0x80000005:
4357 /* cache info (L1 cache) */
787aaf57
BC		 4358 if (cpu->cache_info_passthrough) {
4359 host_cpuid(index, 0, eax, ebx, ecx, edx);
4360 break;
4361 }
5e891bf8
EH		 4362 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
4363 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
4364 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
4365 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4366 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
4367 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 4368 break;
4369 case 0x80000006:
4370 /* cache info (L2 cache) */
787aaf57
BC		 4371 if (cpu->cache_info_passthrough) {
4372 host_cpuid(index, 0, eax, ebx, ecx, edx);
4373 break;
4374 }
5e891bf8
EH		 4375 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
4376 (L2_DTLB_2M_ENTRIES << 16) | \
4377 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
4378 (L2_ITLB_2M_ENTRIES);
4379 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
4380 (L2_DTLB_4K_ENTRIES << 16) | \
4381 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
4382 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4383 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
4384 cpu->enable_l3_cache ?
4385 env->cache_info_amd.l3_cache : NULL,
4386 ecx, edx);
c6dc6f63 4387 break;
303752a9
MT		 4388 case 0x80000007:
4389 *eax = 0;
4390 *ebx = 0;
4391 *ecx = 0;
4392 *edx = env->features[FEAT_8000_0007_EDX];
4393 break;
c6dc6f63
AP		 4394 case 0x80000008:
4395 /* virtual & phys address size in low 2 bytes. */
0514ef2f 4396 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 4397 /* 64 bit processor */
4398 *eax = cpu->phys_bits; /* configurable physical bits */
4399 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
4400 *eax |= 0x00003900; /* 57 bits virtual */
4401 } else {
4402 *eax |= 0x00003000; /* 48 bits virtual */
4403 }
c6dc6f63 4404 } else {
af45907a 4405 *eax = cpu->phys_bits;
c6dc6f63 4406 }
1b3420e1 4407 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 4408 *ecx = 0;
4409 *edx = 0;
ce3960eb
AF		 4410 if (cs->nr_cores * cs->nr_threads > 1) {
4411 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 4412 }
4413 break;
4414 case 0x8000000A:
0514ef2f 4415 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 4416 *eax = 0x00000001; /* SVM Revision */
4417 *ebx = 0x00000010; /* nr of ASIDs */
4418 *ecx = 0;
0514ef2f 4419 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 4420 } else {
4421 *eax = 0;
4422 *ebx = 0;
4423 *ecx = 0;
4424 *edx = 0;
4425 }
c6dc6f63 4426 break;
8f4202fb
BM		 4427 case 0x8000001D:
4428 *eax = 0;
4429 switch (count) {
4430 case 0: /* L1 dcache info */
4431 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
4432 eax, ebx, ecx, edx);
4433 break;
4434 case 1: /* L1 icache info */
4435 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
4436 eax, ebx, ecx, edx);
4437 break;
4438 case 2: /* L2 cache info */
4439 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
4440 eax, ebx, ecx, edx);
4441 break;
4442 case 3: /* L3 cache info */
4443 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
4444 eax, ebx, ecx, edx);
4445 break;
4446 default: /* end of info */
4447 *eax = *ebx = *ecx = *edx = 0;
4448 break;
4449 }
4450 break;
ed78467a
BM		 4451 case 0x8000001E:
4452 assert(cpu->core_id <= 255);
4453 encode_topo_cpuid8000001e(cs, cpu,
4454 eax, ebx, ecx, edx);
4455 break;
b3baa152
BW		 4456 case 0xC0000000:
4457 *eax = env->cpuid_xlevel2;
4458 *ebx = 0;
4459 *ecx = 0;
4460 *edx = 0;
4461 break;
4462 case 0xC0000001:
4463 /* Support for VIA CPU's CPUID instruction */
4464 *eax = env->cpuid_version;
4465 *ebx = 0;
4466 *ecx = 0;
0514ef2f 4467 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 4468 break;
4469 case 0xC0000002:
4470 case 0xC0000003:
4471 case 0xC0000004:
4472 /* Reserved for the future, and now filled with zero */
4473 *eax = 0;
4474 *ebx = 0;
4475 *ecx = 0;
4476 *edx = 0;
4477 break;
6cb8f2a6
BS		 4478 case 0x8000001F:
4479 *eax = sev_enabled() ? 0x2 : 0;
4480 *ebx = sev_get_cbit_position();
4481 *ebx |= sev_get_reduced_phys_bits() << 6;
4482 *ecx = 0;
4483 *edx = 0;
4484 break;
c6dc6f63
AP		 4485 default:
4486 /* reserved values: zero */
4487 *eax = 0;
4488 *ebx = 0;
4489 *ecx = 0;
4490 *edx = 0;
4491 break;
4492 }
4493}
5fd2087a
AF		 4494
4495/* CPUClass::reset() */
4496static void x86_cpu_reset(CPUState *s)
4497{
4498 X86CPU *cpu = X86_CPU(s);
4499 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
4500 CPUX86State *env = &cpu->env;
a114d25d
RH		 4501 target_ulong cr4;
4502 uint64_t xcr0;
c1958aea
AF		 4503 int i;
4504
5fd2087a
AF		 4505 xcc->parent_reset(s);
4506
5e992a8e 4507 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 4508
c1958aea
AF		 4509 env->old_exception = -1;
4510
4511 /* init to reset state */
4512
c1958aea
AF		 4513 env->hflags2 |= HF2_GIF_MASK;
4514
4515 cpu_x86_update_cr0(env, 0x60000010);
4516 env->a20_mask = ~0x0;
4517 env->smbase = 0x30000;
e13713db 4518 env->msr_smi_count = 0;
c1958aea
AF		 4519
4520 env->idt.limit = 0xffff;
4521 env->gdt.limit = 0xffff;
4522 env->ldt.limit = 0xffff;
4523 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4524 env->tr.limit = 0xffff;
4525 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4526
4527 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4528 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4529 DESC_R_MASK | DESC_A_MASK);
4530 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4531 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4532 DESC_A_MASK);
4533 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4534 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4535 DESC_A_MASK);
4536 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4537 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4538 DESC_A_MASK);
4539 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4540 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4541 DESC_A_MASK);
4542 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4543 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4544 DESC_A_MASK);
4545
4546 env->eip = 0xfff0;
4547 env->regs[R_EDX] = env->cpuid_version;
4548
4549 env->eflags = 0x2;
4550
4551 /* FPU init */
4552 for (i = 0; i < 8; i++) {
4553 env->fptags[i] = 1;
4554 }
5bde1407 4555 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 4556
4557 env->mxcsr = 0x1f80;
a114d25d
RH		 4558 /* All units are in INIT state. */
4559 env->xstate_bv = 0;
c1958aea
AF		 4560
4561 env->pat = 0x0007040600070406ULL;
4562 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4563
4564 memset(env->dr, 0, sizeof(env->dr));
4565 env->dr[6] = DR6_FIXED_1;
4566 env->dr[7] = DR7_FIXED_1;
b3310ab3 4567 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 4568 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 4569
a114d25d 4570 cr4 = 0;
cfc3b074 4571 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 4572
4573#ifdef CONFIG_USER_ONLY
4574 /* Enable all the features for user-mode. */
4575 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 4576 xcr0 |= XSTATE_SSE_MASK;
a114d25d 4577 }
0f70ed47
PB		 4578 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4579 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 4580 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 4581 xcr0 |= 1ull << i;
4582 }
a114d25d 4583 }
0f70ed47 4584
a114d25d
RH		 4585 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4586 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4587 }
07929f2a
RH		 4588 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4589 cr4 |= CR4_FSGSBASE_MASK;
4590 }
a114d25d
RH		 4591#endif
4592
4593 env->xcr0 = xcr0;
4594 cpu_x86_update_cr4(env, cr4);
0522604b 4595
9db2efd9
AW		 4596 /*
4597 * SDM 11.11.5 requires:
4598 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4599 * - IA32_MTRR_PHYSMASKn.V = 0
4600 * All other bits are undefined. For simplification, zero it all.
4601 */
4602 env->mtrr_deftype = 0;
4603 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4604 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4605
b7394c83
SAGDR		 4606 env->interrupt_injected = -1;
4607 env->exception_injected = -1;
4608 env->nmi_injected = false;
dd673288
IM		 4609#if !defined(CONFIG_USER_ONLY)
4610 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 4611 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 4612
259186a7 4613 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 4614
4615 if (kvm_enabled()) {
4616 kvm_arch_reset_vcpu(cpu);
4617 }
d6dcc558
SAGDR		 4618 else if (hvf_enabled()) {
4619 hvf_reset_vcpu(s);
4620 }
dd673288 4621#endif
5fd2087a
AF		 4622}
4623
dd673288
IM		 4624#ifndef CONFIG_USER_ONLY
4625bool cpu_is_bsp(X86CPU *cpu)
4626{
02e51483 4627 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 4628}
65dee380
IM		 4629
4630/* TODO: remove me, when reset over QOM tree is implemented */
4631static void x86_cpu_machine_reset_cb(void *opaque)
4632{
4633 X86CPU *cpu = opaque;
4634 cpu_reset(CPU(cpu));
4635}
dd673288
IM		 4636#endif
4637
de024815
AF		 4638static void mce_init(X86CPU *cpu)
4639{
4640 CPUX86State *cenv = &cpu->env;
4641 unsigned int bank;
4642
4643 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 4644 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 4645 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 4646 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4647 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 4648 cenv->mcg_ctl = ~(uint64_t)0;
4649 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4650 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4651 }
4652 }
4653}
4654
bdeec802 4655#ifndef CONFIG_USER_ONLY
2f114315 4656APICCommonClass *apic_get_class(void)
bdeec802 4657{
bdeec802
IM		 4658 const char *apic_type = "apic";
4659
d6dcc558 4660 /* TODO: in-kernel irqchip for hvf */
15eafc2e 4661 if (kvm_apic_in_kernel()) {
bdeec802
IM		 4662 apic_type = "kvm-apic";
4663 } else if (xen_enabled()) {
4664 apic_type = "xen-apic";
4665 }
4666
2f114315
RK		 4667 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4668}
4669
4670static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4671{
4672 APICCommonState *apic;
4673 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4674
4675 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 4676
6816b1b3
IM		 4677 object_property_add_child(OBJECT(cpu), "lapic",
4678 OBJECT(cpu->apic_state), &error_abort);
67e55caa 4679 object_unref(OBJECT(cpu->apic_state));
6816b1b3 4680
33d7a288 4681 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 4682 /* TODO: convert to link<> */
02e51483 4683 apic = APIC_COMMON(cpu->apic_state);
60671e58 4684 apic->cpu = cpu;
8d42d2d3 4685 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 4686}
4687
4688static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4689{
8d42d2d3
CF		 4690 APICCommonState *apic;
4691 static bool apic_mmio_map_once;
4692
02e51483 4693 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 4694 return;
4695 }
6e8e2651
MA		 4696 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4697 errp);
8d42d2d3
CF		 4698
4699 /* Map APIC MMIO area */
4700 apic = APIC_COMMON(cpu->apic_state);
4701 if (!apic_mmio_map_once) {
4702 memory_region_add_subregion_overlap(get_system_memory(),
4703 apic->apicbase &
4704 MSR_IA32_APICBASE_BASE,
4705 &apic->io_memory,
4706 0x1000);
4707 apic_mmio_map_once = true;
4708 }
bdeec802 4709}
f809c605
PB		 4710
4711static void x86_cpu_machine_done(Notifier *n, void *unused)
4712{
4713 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4714 MemoryRegion *smram =
4715 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4716
4717 if (smram) {
4718 cpu->smram = g_new(MemoryRegion, 1);
4719 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4720 smram, 0, 1ull << 32);
f8c45c65 4721 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 4722 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4723 }
4724}
d3c64d6a
IM		 4725#else
4726static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4727{
4728}
bdeec802
IM		 4729#endif
4730
11f6fee5
DDAG		 4731/* Note: Only safe for use on x86(-64) hosts */
4732static uint32_t x86_host_phys_bits(void)
4733{
4734 uint32_t eax;
4735 uint32_t host_phys_bits;
4736
4737 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4738 if (eax >= 0x80000008) {
4739 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4740 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4741 * at 23:16 that can specify a maximum physical address bits for
4742 * the guest that can override this value; but I've not seen
4743 * anything with that set.
4744 */
4745 host_phys_bits = eax & 0xff;
4746 } else {
4747 /* It's an odd 64 bit machine that doesn't have the leaf for
4748 * physical address bits; fall back to 36 that's most older
4749 * Intel.
4750 */
4751 host_phys_bits = 36;
4752 }
4753
4754 return host_phys_bits;
4755}
e48638fd 4756
c39c0edf
EH		 4757static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4758{
4759 if (*min < value) {
4760 *min = value;
4761 }
4762}
4763
4764/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4765static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4766{
4767 CPUX86State *env = &cpu->env;
4768 FeatureWordInfo *fi = &feature_word_info[w];
07585923 4769 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 4770 uint32_t region = eax & 0xF0000000;
4771
07585923 4772 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 4773 if (!env->features[w]) {
4774 return;
4775 }
4776
4777 switch (region) {
4778 case 0x00000000:
4779 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4780 break;
4781 case 0x80000000:
4782 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4783 break;
4784 case 0xC0000000:
4785 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4786 break;
4787 }
4788}
4789
2ca8a8be
EH		 4790/* Calculate XSAVE components based on the configured CPU feature flags */
4791static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4792{
4793 CPUX86State *env = &cpu->env;
4794 int i;
96193c22 4795 uint64_t mask;
2ca8a8be
EH		 4796
4797 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4798 return;
4799 }
4800
e3c9022b
EH		 4801 mask = 0;
4802 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 4803 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4804 if (env->features[esa->feature] & esa->bits) {
96193c22 4805 mask |= (1ULL << i);
2ca8a8be
EH		 4806 }
4807 }
4808
96193c22
EH		 4809 env->features[FEAT_XSAVE_COMP_LO] = mask;
4810 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 4811}
4812
b8d834a0
EH		 4813/***** Steps involved on loading and filtering CPUID data
4814 *
4815 * When initializing and realizing a CPU object, the steps
4816 * involved in setting up CPUID data are:
4817 *
4818 * 1) Loading CPU model definition (X86CPUDefinition). This is
4819 * implemented by x86_cpu_load_def() and should be completely
4820 * transparent, as it is done automatically by instance_init.
4821 * No code should need to look at X86CPUDefinition structs
4822 * outside instance_init.
4823 *
4824 * 2) CPU expansion. This is done by realize before CPUID
4825 * filtering, and will make sure host/accelerator data is
4826 * loaded for CPU models that depend on host capabilities
4827 * (e.g. "host"). Done by x86_cpu_expand_features().
4828 *
4829 * 3) CPUID filtering. This initializes extra data related to
4830 * CPUID, and checks if the host supports all capabilities
4831 * required by the CPU. Runnability of a CPU model is
4832 * determined at this step. Done by x86_cpu_filter_features().
4833 *
4834 * Some operations don't require all steps to be performed.
4835 * More precisely:
4836 *
4837 * - CPU instance creation (instance_init) will run only CPU
4838 * model loading. CPU expansion can't run at instance_init-time
4839 * because host/accelerator data may be not available yet.
4840 * - CPU realization will perform both CPU model expansion and CPUID
4841 * filtering, and return an error in case one of them fails.
4842 * - query-cpu-definitions needs to run all 3 steps. It needs
4843 * to run CPUID filtering, as the 'unavailable-features'
4844 * field is set based on the filtering results.
4845 * - The query-cpu-model-expansion QMP command only needs to run
4846 * CPU model loading and CPU expansion. It should not filter
4847 * any CPUID data based on host capabilities.
4848 */
4849
4850/* Expand CPU configuration data, based on configured features
4851 * and host/accelerator capabilities when appropriate.
4852 */
4853static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 4854{
b34d12d1 4855 CPUX86State *env = &cpu->env;
dc15c051 4856 FeatureWord w;
2fae0d96 4857 GList *l;
41f3d4d6 4858 Error *local_err = NULL;
9886e834 4859
d4a606b3
EH		 4860 /*TODO: Now cpu->max_features doesn't overwrite features
4861 * set using QOM properties, and we can convert
dc15c051
IM		 4862 * plus_features & minus_features to global properties
4863 * inside x86_cpu_parse_featurestr() too.
4864 */
44bd8e53 4865 if (cpu->max_features) {
dc15c051 4866 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 4867 /* Override only features that weren't set explicitly
4868 * by the user.
4869 */
4870 env->features[w] |=
4871 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
0d914f39
EH		 4872 ~env->user_features[w] & \
4873 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 4874 }
4875 }
4876
2fae0d96
EH		 4877 for (l = plus_features; l; l = l->next) {
4878 const char *prop = l->data;
4879 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
4880 if (local_err) {
4881 goto out;
4882 }
4883 }
4884
4885 for (l = minus_features; l; l = l->next) {
4886 const char *prop = l->data;
4887 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
4888 if (local_err) {
4889 goto out;
4890 }
dc15c051
IM		 4891 }
4892
aec661de
EH		 4893 if (!kvm_enabled() || !cpu->expose_kvm) {
4894 env->features[FEAT_KVM] = 0;
4895 }
4896
2ca8a8be 4897 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 4898
4899 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
4900 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
4901 if (cpu->full_cpuid_auto_level) {
4902 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
4903 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
4904 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
4905 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
4906 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
4907 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
4908 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 4909 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 4910 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
4911 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
4912 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 4913 /* SVM requires CPUID[0x8000000A] */
4914 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
4915 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
4916 }
6cb8f2a6
BS		 4917
4918 /* SEV requires CPUID[0x8000001F] */
4919 if (sev_enabled()) {
4920 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
4921 }
c39c0edf
EH		 4922 }
4923
4924 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
4925 if (env->cpuid_level == UINT32_MAX) {
4926 env->cpuid_level = env->cpuid_min_level;
4927 }
4928 if (env->cpuid_xlevel == UINT32_MAX) {
4929 env->cpuid_xlevel = env->cpuid_min_xlevel;
4930 }
4931 if (env->cpuid_xlevel2 == UINT32_MAX) {
4932 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 4933 }
7a059953 4934
41f3d4d6
EH		 4935out:
4936 if (local_err != NULL) {
4937 error_propagate(errp, local_err);
4938 }
4939}
4940
b8d834a0
EH		 4941/*
4942 * Finishes initialization of CPUID data, filters CPU feature
4943 * words based on host availability of each feature.
4944 *
4945 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
4946 */
4947static int x86_cpu_filter_features(X86CPU *cpu)
4948{
4949 CPUX86State *env = &cpu->env;
4950 FeatureWord w;
4951 int rv = 0;
4952
4953 for (w = 0; w < FEATURE_WORDS; w++) {
4954 uint32_t host_feat =
4955 x86_cpu_get_supported_feature_word(w, false);
4956 uint32_t requested_features = env->features[w];
4957 env->features[w] &= host_feat;
4958 cpu->filtered_features[w] = requested_features & ~env->features[w];
4959 if (cpu->filtered_features[w]) {
4960 rv = 1;
4961 }
4962 }
4963
e37a5c7f
CP		 4964 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
4965 kvm_enabled()) {
4966 KVMState *s = CPU(cpu)->kvm_state;
4967 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
4968 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
4969 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
4970 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
4971 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
4972
4973 if (!eax_0 ||
4974 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
4975 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
4976 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
4977 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
4978 INTEL_PT_ADDR_RANGES_NUM) ||
4979 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96
LK		 4980 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
4981 (ecx_0 & INTEL_PT_IP_LIP)) {
e37a5c7f
CP		 4982 /*
4983 * Processor Trace capabilities aren't configurable, so if the
4984 * host can't emulate the capabilities we report on
4985 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
4986 */
4987 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
4988 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
4989 rv = 1;
4990 }
4991 }
4992
b8d834a0
EH		 4993 return rv;
4994}
4995
41f3d4d6
EH		 4996#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
4997 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
4998 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
4999#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
5000 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
5001 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
5002static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
5003{
5004 CPUState *cs = CPU(dev);
5005 X86CPU *cpu = X86_CPU(dev);
5006 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5007 CPUX86State *env = &cpu->env;
5008 Error *local_err = NULL;
5009 static bool ht_warned;
5010
2266d443
MT		 5011 if (xcc->host_cpuid_required) {
5012 if (!accel_uses_host_cpuid()) {
5013 char *name = x86_cpu_class_get_model_name(xcc);
5014 error_setg(&local_err, "CPU model '%s' requires KVM", name);
5015 g_free(name);
5016 goto out;
5017 }
5018
5019 if (enable_cpu_pm) {
5020 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
5021 &cpu->mwait.ecx, &cpu->mwait.edx);
5022 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
5023 }
41f3d4d6
EH		 5024 }
5025
2266d443
MT		 5026 /* mwait extended info: needed for Core compatibility */
5027 /* We always wake on interrupt even if host does not have the capability */
5028 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
5029
41f3d4d6
EH		 5030 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
5031 error_setg(errp, "apic-id property was not initialized properly");
5032 return;
5033 }
5034
b8d834a0 5035 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 5036 if (local_err) {
5037 goto out;
5038 }
5039
8ca30e86
EH		 5040 if (x86_cpu_filter_features(cpu) &&
5041 (cpu->check_cpuid || cpu->enforce_cpuid)) {
5042 x86_cpu_report_filtered_features(cpu);
5043 if (cpu->enforce_cpuid) {
5044 error_setg(&local_err,
d6dcc558 5045 accel_uses_host_cpuid() ?
8ca30e86
EH		 5046 "Host doesn't support requested features" :
5047 "TCG doesn't support requested features");
5048 goto out;
5049 }
9997cf7b
EH		 5050 }
5051
9b15cd9e
IM		 5052 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
5053 * CPUID[1].EDX.
5054 */
e48638fd 5055 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 5056 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
5057 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 5058 & CPUID_EXT2_AMD_ALIASES);
5059 }
5060
11f6fee5
DDAG		 5061 /* For 64bit systems think about the number of physical bits to present.
5062 * ideally this should be the same as the host; anything other than matching
5063 * the host can cause incorrect guest behaviour.
5064 * QEMU used to pick the magic value of 40 bits that corresponds to
5065 * consumer AMD devices but nothing else.
5066 */
af45907a 5067 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 5068 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 5069 uint32_t host_phys_bits = x86_host_phys_bits();
5070 static bool warned;
5071
5072 if (cpu->host_phys_bits) {
5073 /* The user asked for us to use the host physical bits */
5074 cpu->phys_bits = host_phys_bits;
5075 }
5076
5077 /* Print a warning if the user set it to a value that's not the
5078 * host value.
5079 */
5080 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
5081 !warned) {
3dc6f869
AF		 5082 warn_report("Host physical bits (%u)"
5083 " does not match phys-bits property (%u)",
5084 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 5085 warned = true;
5086 }
5087
5088 if (cpu->phys_bits &&
5089 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
5090 cpu->phys_bits < 32)) {
af45907a
DDAG		 5091 error_setg(errp, "phys-bits should be between 32 and %u "
5092 " (but is %u)",
5093 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
5094 return;
5095 }
5096 } else {
11f6fee5 5097 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 5098 error_setg(errp, "TCG only supports phys-bits=%u",
5099 TCG_PHYS_ADDR_BITS);
5100 return;
5101 }
5102 }
11f6fee5
DDAG		 5103 /* 0 means it was not explicitly set by the user (or by machine
5104 * compat_props or by the host code above). In this case, the default
5105 * is the value used by TCG (40).
5106 */
5107 if (cpu->phys_bits == 0) {
5108 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
5109 }
af45907a
DDAG		 5110 } else {
5111 /* For 32 bit systems don't use the user set value, but keep
5112 * phys_bits consistent with what we tell the guest.
5113 */
5114 if (cpu->phys_bits != 0) {
5115 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
5116 return;
5117 }
fefb41bf 5118
af45907a
DDAG		 5119 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
5120 cpu->phys_bits = 36;
5121 } else {
5122 cpu->phys_bits = 32;
5123 }
5124 }
a9f27ea9
EH		 5125
5126 /* Cache information initialization */
5127 if (!cpu->legacy_cache) {
5128 if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
5129 char *name = x86_cpu_class_get_model_name(xcc);
5130 error_setg(errp,
5131 "CPU model '%s' doesn't support legacy-cache=off", name);
5132 g_free(name);
5133 return;
5134 }
5135 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
5136 *xcc->cpu_def->cache_info;
5137 } else {
5138 /* Build legacy cache information */
5139 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
5140 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
5141 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
5142 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
5143
5144 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
5145 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
5146 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
5147 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
5148
5149 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
5150 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
5151 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
5152 env->cache_info_amd.l3_cache = &legacy_l3_cache;
5153 }
5154
5155
ce5b1bbf
LV		 5156 cpu_exec_realizefn(cs, &local_err);
5157 if (local_err != NULL) {
5158 error_propagate(errp, local_err);
5159 return;
5160 }
42ecabaa 5161
65dee380
IM		 5162#ifndef CONFIG_USER_ONLY
5163 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 5164
0514ef2f 5165 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 5166 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 5167 if (local_err != NULL) {
4dc1f449 5168 goto out;
bdeec802
IM		 5169 }
5170 }
65dee380
IM		 5171#endif
5172
7a059953 5173 mce_init(cpu);
2001d0cd
PB		 5174
5175#ifndef CONFIG_USER_ONLY
5176 if (tcg_enabled()) {
f809c605 5177 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 5178 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 5179
5180 /* Outer container... */
5181 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 5182 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 5183
5184 /* ... with two regions inside: normal system memory with low
5185 * priority, and...
5186 */
5187 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
5188 get_system_memory(), 0, ~0ull);
5189 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
5190 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 5191
5192 cs->num_ases = 2;
80ceb07a
PX		 5193 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
5194 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 5195
5196 /* ... SMRAM with higher priority, linked from /machine/smram. */
5197 cpu->machine_done.notify = x86_cpu_machine_done;
5198 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 5199 }
5200#endif
5201
14a10fc3 5202 qemu_init_vcpu(cs);
d3c64d6a 5203
6b2942f9
BM		 5204 /*
5205 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
5206 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
5207 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 5208 * users a warning.
5209 *
5210 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
5211 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
5212 */
0765691e
MA		 5213 if (IS_AMD_CPU(env) &&
5214 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
5215 cs->nr_threads > 1 && !ht_warned) {
5216 warn_report("This family of AMD CPU doesn't support "
5217 "hyperthreading(%d)",
5218 cs->nr_threads);
5219 error_printf("Please configure -smp options properly"
5220 " or try enabling topoext feature.\n");
5221 ht_warned = true;
e48638fd
WH		 5222 }
5223
d3c64d6a
IM		 5224 x86_cpu_apic_realize(cpu, &local_err);
5225 if (local_err != NULL) {
5226 goto out;
5227 }
14a10fc3 5228 cpu_reset(cs);
2b6f294c 5229
4dc1f449 5230 xcc->parent_realize(dev, &local_err);
2001d0cd 5231
4dc1f449
IM		 5232out:
5233 if (local_err != NULL) {
5234 error_propagate(errp, local_err);
5235 return;
5236 }
7a059953
AF		 5237}
5238
c884776e
IM		 5239static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
5240{
5241 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 5242 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5243 Error *local_err = NULL;
c884776e
IM		 5244
5245#ifndef CONFIG_USER_ONLY
5246 cpu_remove_sync(CPU(dev));
5247 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
5248#endif
5249
5250 if (cpu->apic_state) {
5251 object_unparent(OBJECT(cpu->apic_state));
5252 cpu->apic_state = NULL;
5253 }
7bbc124e
LV		 5254
5255 xcc->parent_unrealize(dev, &local_err);
5256 if (local_err != NULL) {
5257 error_propagate(errp, local_err);
5258 return;
5259 }
c884776e
IM		 5260}
5261
38e5c119 5262typedef struct BitProperty {
a7b0ffac 5263 FeatureWord w;
38e5c119
EH		 5264 uint32_t mask;
5265} BitProperty;
5266
d7bce999
EB		 5267static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
5268 void *opaque, Error **errp)
38e5c119 5269{
a7b0ffac 5270 X86CPU *cpu = X86_CPU(obj);
38e5c119 5271 BitProperty *fp = opaque;
a7b0ffac
EH		 5272 uint32_t f = cpu->env.features[fp->w];
5273 bool value = (f & fp->mask) == fp->mask;
51e72bc1 5274 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 5275}
5276
d7bce999
EB		 5277static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
5278 void *opaque, Error **errp)
38e5c119
EH		 5279{
5280 DeviceState *dev = DEVICE(obj);
a7b0ffac 5281 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 5282 BitProperty *fp = opaque;
5283 Error *local_err = NULL;
5284 bool value;
5285
5286 if (dev->realized) {
5287 qdev_prop_set_after_realize(dev, name, errp);
5288 return;
5289 }
5290
51e72bc1 5291 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 5292 if (local_err) {
5293 error_propagate(errp, local_err);
5294 return;
5295 }
5296
5297 if (value) {
a7b0ffac 5298 cpu->env.features[fp->w] |= fp->mask;
38e5c119 5299 } else {
a7b0ffac 5300 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 5301 }
d4a606b3 5302 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 5303}
5304
5305static void x86_cpu_release_bit_prop(Object *obj, const char *name,
5306 void *opaque)
5307{
5308 BitProperty *prop = opaque;
5309 g_free(prop);
5310}
5311
5312/* Register a boolean property to get/set a single bit in a uint32_t field.
5313 *
5314 * The same property name can be registered multiple times to make it affect
5315 * multiple bits in the same FeatureWord. In that case, the getter will return
5316 * true only if all bits are set.
5317 */
5318static void x86_cpu_register_bit_prop(X86CPU *cpu,
5319 const char *prop_name,
a7b0ffac 5320 FeatureWord w,
38e5c119
EH		 5321 int bitnr)
5322{
5323 BitProperty *fp;
5324 ObjectProperty *op;
5325 uint32_t mask = (1UL << bitnr);
5326
5327 op = object_property_find(OBJECT(cpu), prop_name, NULL);
5328 if (op) {
5329 fp = op->opaque;
a7b0ffac 5330 assert(fp->w == w);
38e5c119
EH		 5331 fp->mask |= mask;
5332 } else {
5333 fp = g_new0(BitProperty, 1);
a7b0ffac 5334 fp->w = w;
38e5c119
EH		 5335 fp->mask = mask;
5336 object_property_add(OBJECT(cpu), prop_name, "bool",
5337 x86_cpu_get_bit_prop,
5338 x86_cpu_set_bit_prop,
5339 x86_cpu_release_bit_prop, fp, &error_abort);
5340 }
5341}
5342
5343static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
5344 FeatureWord w,
5345 int bitnr)
5346{
38e5c119 5347 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 5348 const char *name = fi->feat_names[bitnr];
38e5c119 5349
16d2fcaa 5350 if (!name) {
38e5c119
EH		 5351 return;
5352 }
5353
fc7dfd20
EH		 5354 /* Property names should use "-" instead of "_".
5355 * Old names containing underscores are registered as aliases
5356 * using object_property_add_alias()
5357 */
16d2fcaa
EH		 5358 assert(!strchr(name, '_'));
5359 /* aliases don't use "|" delimiters anymore, they are registered
5360 * manually using object_property_add_alias() */
5361 assert(!strchr(name, '|'));
a7b0ffac 5362 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 5363}
5364
d187e08d
AN		 5365static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
5366{
5367 X86CPU *cpu = X86_CPU(cs);
5368 CPUX86State *env = &cpu->env;
5369 GuestPanicInformation *panic_info = NULL;
5370
5e953812 5371 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 5372 panic_info = g_malloc0(sizeof(GuestPanicInformation));
5373
e8ed97a6 5374 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 5375
5e953812 5376 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 5377 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
5378 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
5379 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
5380 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
5381 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 5382 }
5383
5384 return panic_info;
5385}
5386static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
5387 const char *name, void *opaque,
5388 Error **errp)
5389{
5390 CPUState *cs = CPU(obj);
5391 GuestPanicInformation *panic_info;
5392
5393 if (!cs->crash_occurred) {
5394 error_setg(errp, "No crash occured");
5395 return;
5396 }
5397
5398 panic_info = x86_cpu_get_crash_info(cs);
5399 if (panic_info == NULL) {
5400 error_setg(errp, "No crash information");
5401 return;
5402 }
5403
5404 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
5405 errp);
5406 qapi_free_GuestPanicInformation(panic_info);
5407}
5408
de024815
AF		 5409static void x86_cpu_initfn(Object *obj)
5410{
55e5c285 5411 CPUState *cs = CPU(obj);
de024815 5412 X86CPU *cpu = X86_CPU(obj);
d940ee9b 5413 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 5414 CPUX86State *env = &cpu->env;
38e5c119 5415 FeatureWord w;
de024815 5416
c05efcb1 5417 cs->env_ptr = env;
71ad61d3
AF		 5418
5419 object_property_add(obj, "family", "int",
95b8519d 5420 x86_cpuid_version_get_family,
71ad61d3 5421 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 5422 object_property_add(obj, "model", "int",
67e30c83 5423 x86_cpuid_version_get_model,
c5291a4f 5424 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 5425 object_property_add(obj, "stepping", "int",
35112e41 5426 x86_cpuid_version_get_stepping,
036e2222 5427 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 5428 object_property_add_str(obj, "vendor",
5429 x86_cpuid_get_vendor,
5430 x86_cpuid_set_vendor, NULL);
938d4c25 5431 object_property_add_str(obj, "model-id",
63e886eb 5432 x86_cpuid_get_model_id,
938d4c25 5433 x86_cpuid_set_model_id, NULL);
89e48965
AF		 5434 object_property_add(obj, "tsc-frequency", "int",
5435 x86_cpuid_get_tsc_freq,
5436 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 5437 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
5438 x86_cpu_get_feature_words,
7e5292b5
EH		 5439 NULL, NULL, (void *)env->features, NULL);
5440 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
5441 x86_cpu_get_feature_words,
5442 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 5443
d187e08d
AN		 5444 object_property_add(obj, "crash-information", "GuestPanicInformation",
5445 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
5446
92067bf4 5447 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 5448
38e5c119
EH		 5449 for (w = 0; w < FEATURE_WORDS; w++) {
5450 int bitnr;
5451
5452 for (bitnr = 0; bitnr < 32; bitnr++) {
5453 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
5454 }
5455 }
5456
16d2fcaa
EH		 5457 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
5458 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
5459 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
5460 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
5461 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
5462 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
5463 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
5464
54b8dc7c
EH		 5465 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
5466 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
5467 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
5468 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
5469 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
5470 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
5471 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
5472 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
5473 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
5474 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
5475 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
5476 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
5477 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
5478 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
5479 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
5480 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
5481 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
5482 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
5483 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
5484 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
5485 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
5486
0bacd8b3
EH		 5487 if (xcc->cpu_def) {
5488 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
5489 }
de024815
AF		 5490}
5491
997395d3
IM		 5492static int64_t x86_cpu_get_arch_id(CPUState *cs)
5493{
5494 X86CPU *cpu = X86_CPU(cs);
997395d3 5495
7e72a45c 5496 return cpu->apic_id;
997395d3
IM		 5497}
5498
444d5590
AF		 5499static bool x86_cpu_get_paging_enabled(const CPUState *cs)
5500{
5501 X86CPU *cpu = X86_CPU(cs);
5502
5503 return cpu->env.cr[0] & CR0_PG_MASK;
5504}
5505
f45748f1
AF		 5506static void x86_cpu_set_pc(CPUState *cs, vaddr value)
5507{
5508 X86CPU *cpu = X86_CPU(cs);
5509
5510 cpu->env.eip = value;
5511}
5512
bdf7ae5b
AF		 5513static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
5514{
5515 X86CPU *cpu = X86_CPU(cs);
5516
5517 cpu->env.eip = tb->pc - tb->cs_base;
5518}
5519
92d5f1a4 5520int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 5521{
5522 X86CPU *cpu = X86_CPU(cs);
5523 CPUX86State *env = &cpu->env;
5524
92d5f1a4
PB		 5525#if !defined(CONFIG_USER_ONLY)
5526 if (interrupt_request & CPU_INTERRUPT_POLL) {
5527 return CPU_INTERRUPT_POLL;
5528 }
5529#endif
5530 if (interrupt_request & CPU_INTERRUPT_SIPI) {
5531 return CPU_INTERRUPT_SIPI;
5532 }
5533
5534 if (env->hflags2 & HF2_GIF_MASK) {
5535 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
5536 !(env->hflags & HF_SMM_MASK)) {
5537 return CPU_INTERRUPT_SMI;
5538 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
5539 !(env->hflags2 & HF2_NMI_MASK)) {
5540 return CPU_INTERRUPT_NMI;
5541 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
5542 return CPU_INTERRUPT_MCE;
5543 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
5544 (((env->hflags2 & HF2_VINTR_MASK) &&
5545 (env->hflags2 & HF2_HIF_MASK)) ||
5546 (!(env->hflags2 & HF2_VINTR_MASK) &&
5547 (env->eflags & IF_MASK &&
5548 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
5549 return CPU_INTERRUPT_HARD;
5550#if !defined(CONFIG_USER_ONLY)
5551 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
5552 (env->eflags & IF_MASK) &&
5553 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
5554 return CPU_INTERRUPT_VIRQ;
5555#endif
5556 }
5557 }
5558
5559 return 0;
5560}
5561
5562static bool x86_cpu_has_work(CPUState *cs)
5563{
5564 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 5565}
5566
f50f3dd5
RH		 5567static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
5568{
5569 X86CPU *cpu = X86_CPU(cs);
5570 CPUX86State *env = &cpu->env;
5571
5572 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
5573 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
5574 : bfd_mach_i386_i8086);
5575 info->print_insn = print_insn_i386;
b666d2a4
RH		 5576
5577 info->cap_arch = CS_ARCH_X86;
5578 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
5579 : env->hflags & HF_CS32_MASK ? CS_MODE_32
5580 : CS_MODE_16);
15fa1a0a
RH		 5581 info->cap_insn_unit = 1;
5582 info->cap_insn_split = 8;
f50f3dd5
RH		 5583}
5584
35b1b927
TW		 5585void x86_update_hflags(CPUX86State *env)
5586{
5587 uint32_t hflags;
5588#define HFLAG_COPY_MASK \
5589 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5590 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5591 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5592 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5593
5594 hflags = env->hflags & HFLAG_COPY_MASK;
5595 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5596 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5597 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5598 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5599 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5600
5601 if (env->cr[4] & CR4_OSFXSR_MASK) {
5602 hflags |= HF_OSFXSR_MASK;
5603 }
5604
5605 if (env->efer & MSR_EFER_LMA) {
5606 hflags |= HF_LMA_MASK;
5607 }
5608
5609 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5610 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5611 } else {
5612 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5613 (DESC_B_SHIFT - HF_CS32_SHIFT);
5614 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5615 (DESC_B_SHIFT - HF_SS32_SHIFT);
5616 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5617 !(hflags & HF_CS32_MASK)) {
5618 hflags |= HF_ADDSEG_MASK;
5619 } else {
5620 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5621 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5622 }
5623 }
5624 env->hflags = hflags;
5625}
5626
9337e3b6 5627static Property x86_cpu_properties[] = {
2da00e31
IM		 5628#ifdef CONFIG_USER_ONLY
5629 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5630 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 5631 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5632 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5633 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 5634#else
5635 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 5636 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5637 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5638 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 5639#endif
15f8b142 5640 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 5641 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 5642 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 5643 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 5644 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 5645 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 5646 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 5647 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 5648 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 5649 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 5650 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 5651 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
9445597b 5652 DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
ba6a4fd9 5653 DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment, false),
47512009 5654 DEFINE_PROP_BOOL("hv-tlbflush", X86CPU, hyperv_tlbflush, false),
6b7a9830 5655 DEFINE_PROP_BOOL("hv-ipi", X86CPU, hyperv_ipi, false),
15e41345 5656 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 5657 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 5658 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 5659 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 5660 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 5661 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 5662 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5663 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5664 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5665 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5666 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5667 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5668 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 5669 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 5670 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 5671 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 5672 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 5673 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5674 false),
0b564e6f 5675 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 5676 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 5677 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
5678 true),
ab8f992e 5679 /*
a9f27ea9
EH		 5680 * lecacy_cache defaults to true unless the CPU model provides its
5681 * own cache information (see x86_cpu_load_def()).
ab8f992e 5682 */
a9f27ea9 5683 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 5684
5685 /*
5686 * From "Requirements for Implementing the Microsoft
5687 * Hypervisor Interface":
5688 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5689 *
5690 * "Starting with Windows Server 2012 and Windows 8, if
5691 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5692 * the hypervisor imposes no specific limit to the number of VPs.
5693 * In this case, Windows Server 2012 guest VMs may use more than
5694 * 64 VPs, up to the maximum supported number of processors applicable
5695 * to the specific Windows version being used."
5696 */
5697 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 5698 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
5699 false),
9337e3b6
EH		 5700 DEFINE_PROP_END_OF_LIST()
5701};
5702
5fd2087a
AF		 5703static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5704{
5705 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5706 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 5707 DeviceClass *dc = DEVICE_CLASS(oc);
5708
bf853881
PMD		 5709 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5710 &xcc->parent_realize);
5711 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5712 &xcc->parent_unrealize);
9337e3b6 5713 dc->props = x86_cpu_properties;
5fd2087a
AF		 5714
5715 xcc->parent_reset = cc->reset;
5716 cc->reset = x86_cpu_reset;
91b1df8c 5717 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 5718
500050d1 5719 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 5720 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 5721 cc->has_work = x86_cpu_has_work;
79c664f6 5722#ifdef CONFIG_TCG
97a8ea5a 5723 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 5724 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 5725#endif
878096ee 5726 cc->dump_state = x86_cpu_dump_state;
c86f106b 5727 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 5728 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 5729 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 5730 cc->gdb_read_register = x86_cpu_gdb_read_register;
5731 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 5732 cc->get_arch_id = x86_cpu_get_arch_id;
5733 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 5734#ifdef CONFIG_USER_ONLY
5735 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
5736#else
f8c45c65 5737 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 5738 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 5739 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 5740 cc->write_elf64_note = x86_cpu_write_elf64_note;
5741 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5742 cc->write_elf32_note = x86_cpu_write_elf32_note;
5743 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 5744 cc->vmsd = &vmstate_x86_cpu;
c72bf468 5745#endif
00fcd100
AB		 5746 cc->gdb_arch_name = x86_gdb_arch_name;
5747#ifdef TARGET_X86_64
b8158192
AB		 5748 cc->gdb_core_xml_file = "i386-64bit.xml";
5749 cc->gdb_num_core_regs = 57;
00fcd100 5750#else
b8158192
AB		 5751 cc->gdb_core_xml_file = "i386-32bit.xml";
5752 cc->gdb_num_core_regs = 41;
00fcd100 5753#endif
79c664f6 5754#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 5755 cc->debug_excp_handler = breakpoint_handler;
5756#endif
374e0cd4
RH		 5757 cc->cpu_exec_enter = x86_cpu_exec_enter;
5758 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 5759#ifdef CONFIG_TCG
55c3ceef 5760 cc->tcg_initialize = tcg_x86_init;
74d7fc7f 5761#endif
f50f3dd5 5762 cc->disas_set_info = x86_disas_set_info;
4c315c27 5763
e90f2a8c 5764 dc->user_creatable = true;
5fd2087a
AF		 5765}
5766
5767static const TypeInfo x86_cpu_type_info = {
5768 .name = TYPE_X86_CPU,
5769 .parent = TYPE_CPU,
5770 .instance_size = sizeof(X86CPU),
de024815 5771 .instance_init = x86_cpu_initfn,
d940ee9b 5772 .abstract = true,
5fd2087a
AF		 5773 .class_size = sizeof(X86CPUClass),
5774 .class_init = x86_cpu_common_class_init,
5775};
5776
5adbed30
EH		 5777
5778/* "base" CPU model, used by query-cpu-model-expansion */
5779static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
5780{
5781 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5782
5783 xcc->static_model = true;
5784 xcc->migration_safe = true;
5785 xcc->model_description = "base CPU model type with no features enabled";
5786 xcc->ordering = 8;
5787}
5788
5789static const TypeInfo x86_base_cpu_type_info = {
5790 .name = X86_CPU_TYPE_NAME("base"),
5791 .parent = TYPE_X86_CPU,
5792 .class_init = x86_cpu_base_class_init,
5793};
5794
5fd2087a
AF		 5795static void x86_cpu_register_types(void)
5796{
d940ee9b
EH		 5797 int i;
5798
5fd2087a 5799 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 5800 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
5801 x86_register_cpudef_type(&builtin_x86_defs[i]);
5802 }
c62f2630 5803 type_register_static(&max_x86_cpu_type_info);
5adbed30 5804 type_register_static(&x86_base_cpu_type_info);
d6dcc558 5805#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 5806 type_register_static(&host_x86_cpu_type_info);
5807#endif
5fd2087a
AF		 5808}
5809
5810type_init(x86_cpu_register_types)
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