]> git.proxmox.com Git - mirror_qemu.git/blame - target/i386/cpu.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i386: improve sorting of CPU model names
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
f348b6d1 21#include "qemu/cutils.h"
c6dc6f63
AP		 22
23#include "cpu.h"
63c91552 24#include "exec/exec-all.h"
9c17d615 25#include "sysemu/kvm.h"
d6dcc558 26#include "sysemu/hvf.h"
8932cfdf 27#include "sysemu/cpus.h"
50a2c6e5 28#include "kvm_i386.h"
6cb8f2a6 29#include "sev_i386.h"
c6dc6f63 30
d49b6836 31#include "qemu/error-report.h"
1de7afc9
PB		 32#include "qemu/option.h"
33#include "qemu/config-file.h"
e688df6b 34#include "qapi/error.h"
112ed241
MA		 35#include "qapi/qapi-visit-misc.h"
36#include "qapi/qapi-visit-run-state.h"
452fcdbc 37#include "qapi/qmp/qdict.h"
7b1b5d19 38#include "qapi/qmp/qerror.h"
7b1b5d19 39#include "qapi/visitor.h"
f99fd7ca 40#include "qom/qom-qobject.h"
9c17d615 41#include "sysemu/arch_init.h"
71ad61d3 42
1814eab6 43#include "standard-headers/asm-x86/kvm_para.h"
65dee380 44
9c17d615 45#include "sysemu/sysemu.h"
53a89e26 46#include "hw/qdev-properties.h"
5232d00a 47#include "hw/i386/topology.h"
bdeec802 48#ifndef CONFIG_USER_ONLY
2001d0cd 49#include "exec/address-spaces.h"
741da0d3 50#include "hw/hw.h"
0d09e41a 51#include "hw/xen/xen.h"
0d09e41a 52#include "hw/i386/apic_internal.h"
bdeec802
IM		 53#endif
54
b666d2a4
RH		 55#include "disas/capstone.h"
56
7e3482f8
EH		 57/* Helpers for building CPUID[2] descriptors: */
58
59struct CPUID2CacheDescriptorInfo {
60 enum CacheType type;
61 int level;
62 int size;
63 int line_size;
64 int associativity;
65};
5e891bf8 66
7e3482f8
EH		 67#define KiB 1024
68#define MiB (1024 * 1024)
5e891bf8 69
7e3482f8
EH		 70/*
71 * Known CPUID 2 cache descriptors.
72 * From Intel SDM Volume 2A, CPUID instruction
73 */
74struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
75 [0x06] = { .level = 1, .type = ICACHE, .size = 8 * KiB,
76 .associativity = 4, .line_size = 32, },
77 [0x08] = { .level = 1, .type = ICACHE, .size = 16 * KiB,
78 .associativity = 4, .line_size = 32, },
79 [0x09] = { .level = 1, .type = ICACHE, .size = 32 * KiB,
80 .associativity = 4, .line_size = 64, },
81 [0x0A] = { .level = 1, .type = DCACHE, .size = 8 * KiB,
82 .associativity = 2, .line_size = 32, },
83 [0x0C] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
84 .associativity = 4, .line_size = 32, },
85 [0x0D] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
86 .associativity = 4, .line_size = 64, },
87 [0x0E] = { .level = 1, .type = DCACHE, .size = 24 * KiB,
88 .associativity = 6, .line_size = 64, },
89 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
90 .associativity = 2, .line_size = 64, },
91 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
92 .associativity = 8, .line_size = 64, },
93 /* lines per sector is not supported cpuid2_cache_descriptor(),
94 * so descriptors 0x22, 0x23 are not included
95 */
96 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
97 .associativity = 16, .line_size = 64, },
98 /* lines per sector is not supported cpuid2_cache_descriptor(),
99 * so descriptors 0x25, 0x20 are not included
100 */
101 [0x2C] = { .level = 1, .type = DCACHE, .size = 32 * KiB,
102 .associativity = 8, .line_size = 64, },
103 [0x30] = { .level = 1, .type = ICACHE, .size = 32 * KiB,
104 .associativity = 8, .line_size = 64, },
105 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
106 .associativity = 4, .line_size = 32, },
107 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
108 .associativity = 4, .line_size = 32, },
109 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
110 .associativity = 4, .line_size = 32, },
111 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
112 .associativity = 4, .line_size = 32, },
113 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
114 .associativity = 4, .line_size = 32, },
115 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
116 .associativity = 4, .line_size = 64, },
117 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
118 .associativity = 8, .line_size = 64, },
119 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
120 .associativity = 12, .line_size = 64, },
121 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
122 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
123 .associativity = 12, .line_size = 64, },
124 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
125 .associativity = 16, .line_size = 64, },
126 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
127 .associativity = 12, .line_size = 64, },
128 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
129 .associativity = 16, .line_size = 64, },
130 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
131 .associativity = 24, .line_size = 64, },
132 [0x60] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
133 .associativity = 8, .line_size = 64, },
134 [0x66] = { .level = 1, .type = DCACHE, .size = 8 * KiB,
135 .associativity = 4, .line_size = 64, },
136 [0x67] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
137 .associativity = 4, .line_size = 64, },
138 [0x68] = { .level = 1, .type = DCACHE, .size = 32 * KiB,
139 .associativity = 4, .line_size = 64, },
140 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
141 .associativity = 4, .line_size = 64, },
142 /* lines per sector is not supported cpuid2_cache_descriptor(),
143 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
144 */
145 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
146 .associativity = 8, .line_size = 64, },
147 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
148 .associativity = 2, .line_size = 64, },
149 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
150 .associativity = 8, .line_size = 64, },
151 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
152 .associativity = 8, .line_size = 32, },
153 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
154 .associativity = 8, .line_size = 32, },
155 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
156 .associativity = 8, .line_size = 32, },
157 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
158 .associativity = 8, .line_size = 32, },
159 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
160 .associativity = 4, .line_size = 64, },
161 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
162 .associativity = 8, .line_size = 64, },
163 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
164 .associativity = 4, .line_size = 64, },
165 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
166 .associativity = 4, .line_size = 64, },
167 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
168 .associativity = 4, .line_size = 64, },
169 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
170 .associativity = 8, .line_size = 64, },
171 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
172 .associativity = 8, .line_size = 64, },
173 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
174 .associativity = 8, .line_size = 64, },
175 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
176 .associativity = 12, .line_size = 64, },
177 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
178 .associativity = 12, .line_size = 64, },
179 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
180 .associativity = 12, .line_size = 64, },
181 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
182 .associativity = 16, .line_size = 64, },
183 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
184 .associativity = 16, .line_size = 64, },
185 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
186 .associativity = 16, .line_size = 64, },
187 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
188 .associativity = 24, .line_size = 64, },
189 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
190 .associativity = 24, .line_size = 64, },
191 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
192 .associativity = 24, .line_size = 64, },
193};
194
195/*
196 * "CPUID leaf 2 does not report cache descriptor information,
197 * use CPUID leaf 4 to query cache parameters"
198 */
199#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 200
7e3482f8
EH		 201/*
202 * Return a CPUID 2 cache descriptor for a given cache.
203 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
204 */
205static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
206{
207 int i;
208
209 assert(cache->size > 0);
210 assert(cache->level > 0);
211 assert(cache->line_size > 0);
212 assert(cache->associativity > 0);
213 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
214 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
215 if (d->level == cache->level && d->type == cache->type &&
216 d->size == cache->size && d->line_size == cache->line_size &&
217 d->associativity == cache->associativity) {
218 return i;
219 }
220 }
5e891bf8 221
7e3482f8
EH		 222 return CACHE_DESCRIPTOR_UNAVAILABLE;
223}
5e891bf8
EH		 224
225/* CPUID Leaf 4 constants: */
226
227/* EAX: */
7e3482f8
EH		 228#define CACHE_TYPE_D 1
229#define CACHE_TYPE_I 2
230#define CACHE_TYPE_UNIFIED 3
5e891bf8 231
7e3482f8 232#define CACHE_LEVEL(l) (l << 5)
5e891bf8 233
7e3482f8 234#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 235
236/* EDX: */
7e3482f8
EH		 237#define CACHE_NO_INVD_SHARING (1 << 0)
238#define CACHE_INCLUSIVE (1 << 1)
239#define CACHE_COMPLEX_IDX (1 << 2)
240
241/* Encode CacheType for CPUID[4].EAX */
242#define CACHE_TYPE(t) (((t) == DCACHE) ? CACHE_TYPE_D : \
243 ((t) == ICACHE) ? CACHE_TYPE_I : \
244 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
245 0 /* Invalid value */)
246
247
248/* Encode cache info for CPUID[4] */
249static void encode_cache_cpuid4(CPUCacheInfo *cache,
250 int num_apic_ids, int num_cores,
251 uint32_t *eax, uint32_t *ebx,
252 uint32_t *ecx, uint32_t *edx)
253{
254 assert(cache->size == cache->line_size * cache->associativity *
255 cache->partitions * cache->sets);
256
257 assert(num_apic_ids > 0);
258 *eax = CACHE_TYPE(cache->type) |
259 CACHE_LEVEL(cache->level) |
260 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
261 ((num_cores - 1) << 26) |
262 ((num_apic_ids - 1) << 14);
263
264 assert(cache->line_size > 0);
265 assert(cache->partitions > 0);
266 assert(cache->associativity > 0);
267 /* We don't implement fully-associative caches */
268 assert(cache->associativity < cache->sets);
269 *ebx = (cache->line_size - 1) |
270 ((cache->partitions - 1) << 12) |
271 ((cache->associativity - 1) << 22);
272
273 assert(cache->sets > 0);
274 *ecx = cache->sets - 1;
275
276 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
277 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
278 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
279}
280
281/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
282static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
283{
284 assert(cache->size % 1024 == 0);
285 assert(cache->lines_per_tag > 0);
286 assert(cache->associativity > 0);
287 assert(cache->line_size > 0);
288 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
289 (cache->lines_per_tag << 8) | (cache->line_size);
290}
5e891bf8
EH		 291
292#define ASSOC_FULL 0xFF
293
294/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
295#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
296 a == 2 ? 0x2 : \
297 a == 4 ? 0x4 : \
298 a == 8 ? 0x6 : \
299 a == 16 ? 0x8 : \
300 a == 32 ? 0xA : \
301 a == 48 ? 0xB : \
302 a == 64 ? 0xC : \
303 a == 96 ? 0xD : \
304 a == 128 ? 0xE : \
305 a == ASSOC_FULL ? 0xF : \
306 0 /* invalid value */)
307
7e3482f8
EH		 308/*
309 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
310 * @l3 can be NULL.
311 */
312static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
313 CPUCacheInfo *l3,
314 uint32_t *ecx, uint32_t *edx)
315{
316 assert(l2->size % 1024 == 0);
317 assert(l2->associativity > 0);
318 assert(l2->lines_per_tag > 0);
319 assert(l2->line_size > 0);
320 *ecx = ((l2->size / 1024) << 16) |
321 (AMD_ENC_ASSOC(l2->associativity) << 12) |
322 (l2->lines_per_tag << 8) | (l2->line_size);
323
324 if (l3) {
325 assert(l3->size % (512 * 1024) == 0);
326 assert(l3->associativity > 0);
327 assert(l3->lines_per_tag > 0);
328 assert(l3->line_size > 0);
329 *edx = ((l3->size / (512 * 1024)) << 18) |
330 (AMD_ENC_ASSOC(l3->associativity) << 12) |
331 (l3->lines_per_tag << 8) | (l3->line_size);
332 } else {
333 *edx = 0;
334 }
335}
5e891bf8 336
8f4202fb
BM		 337/*
338 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
339 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
340 * Define the constants to build the cpu topology. Right now, TOPOEXT
341 * feature is enabled only on EPYC. So, these constants are based on
342 * EPYC supported configurations. We may need to handle the cases if
343 * these values change in future.
344 */
345/* Maximum core complexes in a node */
346#define MAX_CCX 2
347/* Maximum cores in a core complex */
348#define MAX_CORES_IN_CCX 4
349/* Maximum cores in a node */
350#define MAX_CORES_IN_NODE 8
351/* Maximum nodes in a socket */
352#define MAX_NODES_PER_SOCKET 4
353
354/*
355 * Figure out the number of nodes required to build this config.
356 * Max cores in a node is 8
357 */
358static int nodes_in_socket(int nr_cores)
359{
360 int nodes;
361
362 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
363
364 /* Hardware does not support config with 3 nodes, return 4 in that case */
365 return (nodes == 3) ? 4 : nodes;
366}
367
368/*
369 * Decide the number of cores in a core complex with the given nr_cores using
370 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
371 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
372 * L3 cache is shared across all cores in a core complex. So, this will also
373 * tell us how many cores are sharing the L3 cache.
374 */
375static int cores_in_core_complex(int nr_cores)
376{
377 int nodes;
378
379 /* Check if we can fit all the cores in one core complex */
380 if (nr_cores <= MAX_CORES_IN_CCX) {
381 return nr_cores;
382 }
383 /* Get the number of nodes required to build this config */
384 nodes = nodes_in_socket(nr_cores);
385
386 /*
387 * Divide the cores accros all the core complexes
388 * Return rounded up value
389 */
390 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
391}
392
393/* Encode cache info for CPUID[8000001D] */
394static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
395 uint32_t *eax, uint32_t *ebx,
396 uint32_t *ecx, uint32_t *edx)
397{
398 uint32_t l3_cores;
399 assert(cache->size == cache->line_size * cache->associativity *
400 cache->partitions * cache->sets);
401
402 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
403 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
404
405 /* L3 is shared among multiple cores */
406 if (cache->level == 3) {
407 l3_cores = cores_in_core_complex(cs->nr_cores);
408 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
409 } else {
410 *eax |= ((cs->nr_threads - 1) << 14);
411 }
412
413 assert(cache->line_size > 0);
414 assert(cache->partitions > 0);
415 assert(cache->associativity > 0);
416 /* We don't implement fully-associative caches */
417 assert(cache->associativity < cache->sets);
418 *ebx = (cache->line_size - 1) |
419 ((cache->partitions - 1) << 12) |
420 ((cache->associativity - 1) << 22);
421
422 assert(cache->sets > 0);
423 *ecx = cache->sets - 1;
424
425 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
426 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
427 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
428}
429
ed78467a
BM		 430/* Data structure to hold the configuration info for a given core index */
431struct core_topology {
432 /* core complex id of the current core index */
433 int ccx_id;
434 /*
435 * Adjusted core index for this core in the topology
436 * This can be 0,1,2,3 with max 4 cores in a core complex
437 */
438 int core_id;
439 /* Node id for this core index */
440 int node_id;
441 /* Number of nodes in this config */
442 int num_nodes;
443};
444
445/*
446 * Build the configuration closely match the EPYC hardware. Using the EPYC
447 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
448 * right now. This could change in future.
449 * nr_cores : Total number of cores in the config
450 * core_id : Core index of the current CPU
451 * topo : Data structure to hold all the config info for this core index
452 */
453static void build_core_topology(int nr_cores, int core_id,
454 struct core_topology *topo)
455{
456 int nodes, cores_in_ccx;
457
458 /* First get the number of nodes required */
459 nodes = nodes_in_socket(nr_cores);
460
461 cores_in_ccx = cores_in_core_complex(nr_cores);
462
463 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
464 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
465 topo->core_id = core_id % cores_in_ccx;
466 topo->num_nodes = nodes;
467}
468
469/* Encode cache info for CPUID[8000001E] */
470static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
471 uint32_t *eax, uint32_t *ebx,
472 uint32_t *ecx, uint32_t *edx)
473{
474 struct core_topology topo = {0};
475
476 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
477 *eax = cpu->apic_id;
478 /*
479 * CPUID_Fn8000001E_EBX
480 * 31:16 Reserved
481 * 15:8 Threads per core (The number of threads per core is
482 * Threads per core + 1)
483 * 7:0 Core id (see bit decoding below)
484 * SMT:
485 * 4:3 node id
486 * 2 Core complex id
487 * 1:0 Core id
488 * Non SMT:
489 * 5:4 node id
490 * 3 Core complex id
491 * 1:0 Core id
492 */
493 if (cs->nr_threads - 1) {
494 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
495 (topo.ccx_id << 2) | topo.core_id;
496 } else {
497 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
498 }
499 /*
500 * CPUID_Fn8000001E_ECX
501 * 31:11 Reserved
502 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
503 * 7:0 Node id (see bit decoding below)
504 * 2 Socket id
505 * 1:0 Node id
506 */
507 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) | topo.node_id;
508 *edx = 0;
509}
510
ab8f992e
BM		 511/*
512 * Definitions of the hardcoded cache entries we expose:
513 * These are legacy cache values. If there is a need to change any
514 * of these values please use builtin_x86_defs
515 */
5e891bf8
EH		 516
517/* L1 data cache: */
ab8f992e 518static CPUCacheInfo legacy_l1d_cache = {
7e3482f8
EH		 519 .type = DCACHE,
520 .level = 1,
521 .size = 32 * KiB,
522 .self_init = 1,
523 .line_size = 64,
524 .associativity = 8,
525 .sets = 64,
526 .partitions = 1,
527 .no_invd_sharing = true,
528};
529
5e891bf8 530/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 531static CPUCacheInfo legacy_l1d_cache_amd = {
7e3482f8
EH		 532 .type = DCACHE,
533 .level = 1,
534 .size = 64 * KiB,
535 .self_init = 1,
536 .line_size = 64,
537 .associativity = 2,
538 .sets = 512,
539 .partitions = 1,
540 .lines_per_tag = 1,
541 .no_invd_sharing = true,
542};
5e891bf8
EH		 543
544/* L1 instruction cache: */
ab8f992e 545static CPUCacheInfo legacy_l1i_cache = {
7e3482f8
EH		 546 .type = ICACHE,
547 .level = 1,
548 .size = 32 * KiB,
549 .self_init = 1,
550 .line_size = 64,
551 .associativity = 8,
552 .sets = 64,
553 .partitions = 1,
554 .no_invd_sharing = true,
555};
556
5e891bf8 557/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 558static CPUCacheInfo legacy_l1i_cache_amd = {
7e3482f8
EH		 559 .type = ICACHE,
560 .level = 1,
561 .size = 64 * KiB,
562 .self_init = 1,
563 .line_size = 64,
564 .associativity = 2,
565 .sets = 512,
566 .partitions = 1,
567 .lines_per_tag = 1,
568 .no_invd_sharing = true,
569};
5e891bf8
EH		 570
571/* Level 2 unified cache: */
ab8f992e 572static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 573 .type = UNIFIED_CACHE,
574 .level = 2,
575 .size = 4 * MiB,
576 .self_init = 1,
577 .line_size = 64,
578 .associativity = 16,
579 .sets = 4096,
580 .partitions = 1,
581 .no_invd_sharing = true,
582};
583
5e891bf8 584/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 585static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 586 .type = UNIFIED_CACHE,
587 .level = 2,
588 .size = 2 * MiB,
589 .line_size = 64,
590 .associativity = 8,
591};
592
593
5e891bf8 594/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 595static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 596 .type = UNIFIED_CACHE,
597 .level = 2,
598 .size = 512 * KiB,
599 .line_size = 64,
600 .lines_per_tag = 1,
601 .associativity = 16,
602 .sets = 512,
603 .partitions = 1,
604};
5e891bf8 605
14c985cf 606/* Level 3 unified cache: */
ab8f992e 607static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 608 .type = UNIFIED_CACHE,
609 .level = 3,
610 .size = 16 * MiB,
611 .line_size = 64,
612 .associativity = 16,
613 .sets = 16384,
614 .partitions = 1,
615 .lines_per_tag = 1,
616 .self_init = true,
617 .inclusive = true,
618 .complex_indexing = true,
619};
5e891bf8
EH		 620
621/* TLB definitions: */
622
623#define L1_DTLB_2M_ASSOC 1
624#define L1_DTLB_2M_ENTRIES 255
625#define L1_DTLB_4K_ASSOC 1
626#define L1_DTLB_4K_ENTRIES 255
627
628#define L1_ITLB_2M_ASSOC 1
629#define L1_ITLB_2M_ENTRIES 255
630#define L1_ITLB_4K_ASSOC 1
631#define L1_ITLB_4K_ENTRIES 255
632
633#define L2_DTLB_2M_ASSOC 0 /* disabled */
634#define L2_DTLB_2M_ENTRIES 0 /* disabled */
635#define L2_DTLB_4K_ASSOC 4
636#define L2_DTLB_4K_ENTRIES 512
637
638#define L2_ITLB_2M_ASSOC 0 /* disabled */
639#define L2_ITLB_2M_ENTRIES 0 /* disabled */
640#define L2_ITLB_4K_ASSOC 4
641#define L2_ITLB_4K_ENTRIES 512
642
e37a5c7f
CP		 643/* CPUID Leaf 0x14 constants: */
644#define INTEL_PT_MAX_SUBLEAF 0x1
645/*
646 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
647 * MSR can be accessed;
648 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
649 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
650 * of Intel PT MSRs across warm reset;
651 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
652 */
653#define INTEL_PT_MINIMAL_EBX 0xf
654/*
655 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
656 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
657 * accessed;
658 * bit[01]: ToPA tables can hold any number of output entries, up to the
659 * maximum allowed by the MaskOrTableOffset field of
660 * IA32_RTIT_OUTPUT_MASK_PTRS;
661 * bit[02]: Support Single-Range Output scheme;
662 */
663#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 664/* generated packets which contain IP payloads have LIP values */
665#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 666#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
667#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
668#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
669#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
670#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 671
99b88a17
IM		 672static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
673 uint32_t vendor2, uint32_t vendor3)
674{
675 int i;
676 for (i = 0; i < 4; i++) {
677 dst[i] = vendor1 >> (8 * i);
678 dst[i + 4] = vendor2 >> (8 * i);
679 dst[i + 8] = vendor3 >> (8 * i);
680 }
681 dst[CPUID_VENDOR_SZ] = '\0';
682}
683
621626ce
EH		 684#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
685#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
686 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
687#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
688 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
689 CPUID_PSE36 | CPUID_FXSR)
690#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
691#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
692 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
693 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
694 CPUID_PAE | CPUID_SEP | CPUID_APIC)
695
696#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
697 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
698 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
699 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 700 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 701 /* partly implemented:
702 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
703 /* missing:
704 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
705#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
706 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
707 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 708 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 709 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
710 /* missing:
711 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
712 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
713 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 714 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
715 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 716
717#ifdef TARGET_X86_64
718#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
719#else
720#define TCG_EXT2_X86_64_FEATURES 0
721#endif
722
723#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
724 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
725 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
726 TCG_EXT2_X86_64_FEATURES)
727#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
728 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
729#define TCG_EXT4_FEATURES 0
730#define TCG_SVM_FEATURES 0
731#define TCG_KVM_FEATURES 0
732#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 733 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
734 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 735 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
736 CPUID_7_0_EBX_ERMS)
621626ce 737 /* missing:
07929f2a 738 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 739 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 740 CPUID_7_0_EBX_RDSEED */
6c7c3c21
KS		 741#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
742 CPUID_7_0_ECX_LA57)
95ea69fb 743#define TCG_7_0_EDX_FEATURES 0
303752a9 744#define TCG_APM_FEATURES 0
28b8e4d0 745#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 746#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
747 /* missing:
748 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 749
5ef57876 750typedef struct FeatureWordInfo {
2d5312da
EH		 751 /* feature flags names are taken from "Intel Processor Identification and
752 * the CPUID Instruction" and AMD's "CPUID Specification".
753 * In cases of disagreement between feature naming conventions,
754 * aliases may be added.
755 */
756 const char *feat_names[32];
04d104b6
EH		 757 uint32_t cpuid_eax; /* Input EAX for CPUID */
758 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
759 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
760 int cpuid_reg; /* output register (R_* constant) */
37ce3522 761 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 762 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 763 uint32_t migratable_flags; /* Feature flags known to be migratable */
0d914f39
EH		 764 /* Features that shouldn't be auto-enabled by "-cpu host" */
765 uint32_t no_autoenable_flags;
5ef57876
EH		 766} FeatureWordInfo;
767
768static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 769 [FEAT_1_EDX] = {
2d5312da
EH		 770 .feat_names = {
771 "fpu", "vme", "de", "pse",
772 "tsc", "msr", "pae", "mce",
773 "cx8", "apic", NULL, "sep",
774 "mtrr", "pge", "mca", "cmov",
775 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
776 NULL, "ds" /* Intel dts */, "acpi", "mmx",
777 "fxsr", "sse", "sse2", "ss",
778 "ht" /* Intel htt */, "tm", "ia64", "pbe",
779 },
bffd67b0 780 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 781 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 782 },
783 [FEAT_1_ECX] = {
2d5312da 784 .feat_names = {
16d2fcaa 785 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 786 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 787 "tm2", "ssse3", "cid", NULL,
788 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 789 NULL, "pcid", "dca", "sse4.1",
790 "sse4.2", "x2apic", "movbe", "popcnt",
2d5312da
EH		 791 "tsc-deadline", "aes", "xsave", "osxsave",
792 "avx", "f16c", "rdrand", "hypervisor",
793 },
bffd67b0 794 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 795 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 796 },
2d5312da
EH		 797 /* Feature names that are already defined on feature_name[] but
798 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
799 * names on feat_names below. They are copied automatically
800 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
801 */
bffd67b0 802 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 803 .feat_names = {
804 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
805 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
806 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
807 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
808 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 809 "nx", NULL, "mmxext", NULL /* mmx */,
810 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
811 NULL, "lm", "3dnowext", "3dnow",
2d5312da 812 },
bffd67b0 813 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 814 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 815 },
816 [FEAT_8000_0001_ECX] = {
2d5312da 817 .feat_names = {
fc7dfd20 818 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 819 "cr8legacy", "abm", "sse4a", "misalignsse",
820 "3dnowprefetch", "osvw", "ibs", "xop",
821 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 822 "fma4", "tce", NULL, "nodeid-msr",
823 NULL, "tbm", "topoext", "perfctr-core",
824 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 825 NULL, NULL, NULL, NULL,
826 },
bffd67b0 827 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 828 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 829 },
89e49c8b 830 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 831 .feat_names = {
832 NULL, NULL, "xstore", "xstore-en",
833 NULL, NULL, "xcrypt", "xcrypt-en",
834 "ace2", "ace2-en", "phe", "phe-en",
835 "pmm", "pmm-en", NULL, NULL,
836 NULL, NULL, NULL, NULL,
837 NULL, NULL, NULL, NULL,
838 NULL, NULL, NULL, NULL,
839 NULL, NULL, NULL, NULL,
840 },
89e49c8b 841 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 842 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 843 },
bffd67b0 844 [FEAT_KVM] = {
2d5312da 845 .feat_names = {
fc7dfd20
EH		 846 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
847 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
6976af66 848 NULL, "kvm-pv-tlb-flush", NULL, NULL,
2d5312da
EH		 849 NULL, NULL, NULL, NULL,
850 NULL, NULL, NULL, NULL,
851 NULL, NULL, NULL, NULL,
852 "kvmclock-stable-bit", NULL, NULL, NULL,
853 NULL, NULL, NULL, NULL,
854 },
bffd67b0 855 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 856 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 857 },
be777326
WL		 858 [FEAT_KVM_HINTS] = {
859 .feat_names = {
860 "kvm-hint-dedicated", NULL, NULL, NULL,
861 NULL, NULL, NULL, NULL,
862 NULL, NULL, NULL, NULL,
863 NULL, NULL, NULL, NULL,
864 NULL, NULL, NULL, NULL,
865 NULL, NULL, NULL, NULL,
866 NULL, NULL, NULL, NULL,
867 NULL, NULL, NULL, NULL,
868 },
869 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EDX,
870 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 871 /*
872 * KVM hints aren't auto-enabled by -cpu host, they need to be
873 * explicitly enabled in the command-line.
874 */
875 .no_autoenable_flags = ~0U,
be777326 876 },
c35bd19a 877 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 878 .feat_names = {
879 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
880 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
881 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
882 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
883 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
884 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
ba6a4fd9
VK		 885 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
886 NULL, NULL,
2d5312da
EH		 887 NULL, NULL, NULL, NULL,
888 NULL, NULL, NULL, NULL,
889 NULL, NULL, NULL, NULL,
890 NULL, NULL, NULL, NULL,
891 },
c35bd19a
EY		 892 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
893 },
894 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 895 .feat_names = {
896 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
897 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
898 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
899 NULL /* hv_create_port */, NULL /* hv_connect_port */,
900 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
901 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
902 NULL, NULL,
903 NULL, NULL, NULL, NULL,
904 NULL, NULL, NULL, NULL,
905 NULL, NULL, NULL, NULL,
906 NULL, NULL, NULL, NULL,
907 },
c35bd19a
EY		 908 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
909 },
910 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 911 .feat_names = {
912 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
913 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
914 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
915 NULL, NULL,
916 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
917 NULL, NULL, NULL, NULL,
918 NULL, NULL, NULL, NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 },
c35bd19a
EY		 923 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
924 },
bffd67b0 925 [FEAT_SVM] = {
2d5312da 926 .feat_names = {
fc7dfd20
EH		 927 "npt", "lbrv", "svm-lock", "nrip-save",
928 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
929 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 930 "pfthreshold", NULL, NULL, NULL,
931 NULL, NULL, NULL, NULL,
932 NULL, NULL, NULL, NULL,
933 NULL, NULL, NULL, NULL,
934 NULL, NULL, NULL, NULL,
935 },
bffd67b0 936 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 937 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 938 },
939 [FEAT_7_0_EBX] = {
2d5312da 940 .feat_names = {
fc7dfd20 941 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 942 "hle", "avx2", NULL, "smep",
943 "bmi2", "erms", "invpcid", "rtm",
944 NULL, NULL, "mpx", NULL,
945 "avx512f", "avx512dq", "rdseed", "adx",
946 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 947 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 948 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 949 },
04d104b6
EH		 950 .cpuid_eax = 7,
951 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
952 .cpuid_reg = R_EBX,
37ce3522 953 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 954 },
f74eefe0 955 [FEAT_7_0_ECX] = {
2d5312da
EH		 956 .feat_names = {
957 NULL, "avx512vbmi", "umip", "pku",
aff9e6e4
YZ		 958 "ospke", NULL, "avx512vbmi2", NULL,
959 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
960 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 961 "la57", NULL, NULL, NULL,
2d5312da 962 NULL, NULL, "rdpid", NULL,
0da0fb06 963 NULL, "cldemote", NULL, NULL,
2d5312da
EH		 964 NULL, NULL, NULL, NULL,
965 },
f74eefe0
HH		 966 .cpuid_eax = 7,
967 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
968 .cpuid_reg = R_ECX,
969 .tcg_features = TCG_7_0_ECX_FEATURES,
970 },
95ea69fb
LK		 971 [FEAT_7_0_EDX] = {
972 .feat_names = {
973 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
974 NULL, NULL, NULL, NULL,
975 NULL, NULL, NULL, NULL,
976 NULL, NULL, NULL, NULL,
977 NULL, NULL, NULL, NULL,
978 NULL, NULL, NULL, NULL,
a2381f09 979 NULL, NULL, "spec-ctrl", NULL,
d19d1f96 980 NULL, NULL, NULL, "ssbd",
95ea69fb
LK		 981 },
982 .cpuid_eax = 7,
983 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
984 .cpuid_reg = R_EDX,
985 .tcg_features = TCG_7_0_EDX_FEATURES,
986 },
303752a9 987 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 988 .feat_names = {
989 NULL, NULL, NULL, NULL,
990 NULL, NULL, NULL, NULL,
991 "invtsc", NULL, NULL, NULL,
992 NULL, NULL, NULL, NULL,
993 NULL, NULL, NULL, NULL,
994 NULL, NULL, NULL, NULL,
995 NULL, NULL, NULL, NULL,
996 NULL, NULL, NULL, NULL,
997 },
303752a9
MT		 998 .cpuid_eax = 0x80000007,
999 .cpuid_reg = R_EDX,
1000 .tcg_features = TCG_APM_FEATURES,
1001 .unmigratable_flags = CPUID_APM_INVTSC,
1002 },
1b3420e1
EH		 1003 [FEAT_8000_0008_EBX] = {
1004 .feat_names = {
1005 NULL, NULL, NULL, NULL,
1006 NULL, NULL, NULL, NULL,
1007 NULL, NULL, NULL, NULL,
1008 "ibpb", NULL, NULL, NULL,
1009 NULL, NULL, NULL, NULL,
1010 NULL, NULL, NULL, NULL,
403503b1 1011 NULL, "virt-ssbd", NULL, NULL,
1b3420e1
EH		 1012 NULL, NULL, NULL, NULL,
1013 },
1014 .cpuid_eax = 0x80000008,
1015 .cpuid_reg = R_EBX,
1016 .tcg_features = 0,
1017 .unmigratable_flags = 0,
1018 },
0bb0b2d2 1019 [FEAT_XSAVE] = {
2d5312da
EH		 1020 .feat_names = {
1021 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1022 NULL, NULL, NULL, NULL,
1023 NULL, NULL, NULL, NULL,
1024 NULL, NULL, NULL, NULL,
1025 NULL, NULL, NULL, NULL,
1026 NULL, NULL, NULL, NULL,
1027 NULL, NULL, NULL, NULL,
1028 NULL, NULL, NULL, NULL,
1029 },
0bb0b2d2
PB		 1030 .cpuid_eax = 0xd,
1031 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
1032 .cpuid_reg = R_EAX,
c9cfe8f9 1033 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 1034 },
28b8e4d0 1035 [FEAT_6_EAX] = {
2d5312da
EH		 1036 .feat_names = {
1037 NULL, NULL, "arat", NULL,
1038 NULL, NULL, NULL, NULL,
1039 NULL, NULL, NULL, NULL,
1040 NULL, NULL, NULL, NULL,
1041 NULL, NULL, NULL, NULL,
1042 NULL, NULL, NULL, NULL,
1043 NULL, NULL, NULL, NULL,
1044 NULL, NULL, NULL, NULL,
1045 },
28b8e4d0
JK		 1046 .cpuid_eax = 6, .cpuid_reg = R_EAX,
1047 .tcg_features = TCG_6_EAX_FEATURES,
1048 },
96193c22
EH		 1049 [FEAT_XSAVE_COMP_LO] = {
1050 .cpuid_eax = 0xD,
1051 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
1052 .cpuid_reg = R_EAX,
1053 .tcg_features = ~0U,
6fb2fff7
EH		 1054 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1055 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1056 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1057 XSTATE_PKRU_MASK,
96193c22
EH		 1058 },
1059 [FEAT_XSAVE_COMP_HI] = {
1060 .cpuid_eax = 0xD,
1061 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
1062 .cpuid_reg = R_EDX,
1063 .tcg_features = ~0U,
1064 },
5ef57876
EH		 1065};
1066
8e8aba50
EH		 1067typedef struct X86RegisterInfo32 {
1068 /* Name of register */
1069 const char *name;
1070 /* QAPI enum value register */
1071 X86CPURegister32 qapi_enum;
1072} X86RegisterInfo32;
1073
1074#define REGISTER(reg) \
5d371f41 1075 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1076static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1077 REGISTER(EAX),
1078 REGISTER(ECX),
1079 REGISTER(EDX),
1080 REGISTER(EBX),
1081 REGISTER(ESP),
1082 REGISTER(EBP),
1083 REGISTER(ESI),
1084 REGISTER(EDI),
1085};
1086#undef REGISTER
1087
3f32bd21
RH		 1088typedef struct ExtSaveArea {
1089 uint32_t feature, bits;
1090 uint32_t offset, size;
1091} ExtSaveArea;
1092
1093static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 1094 [XSTATE_FP_BIT] = {
1095 /* x87 FP state component is always enabled if XSAVE is supported */
1096 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1097 /* x87 state is in the legacy region of the XSAVE area */
1098 .offset = 0,
1099 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1100 },
1101 [XSTATE_SSE_BIT] = {
1102 /* SSE state component is always enabled if XSAVE is supported */
1103 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1104 /* SSE state is in the legacy region of the XSAVE area */
1105 .offset = 0,
1106 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1107 },
cfc3b074
PB		 1108 [XSTATE_YMM_BIT] =
1109 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 1110 .offset = offsetof(X86XSaveArea, avx_state),
1111 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1112 [XSTATE_BNDREGS_BIT] =
1113 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1114 .offset = offsetof(X86XSaveArea, bndreg_state),
1115 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1116 [XSTATE_BNDCSR_BIT] =
1117 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1118 .offset = offsetof(X86XSaveArea, bndcsr_state),
1119 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1120 [XSTATE_OPMASK_BIT] =
1121 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1122 .offset = offsetof(X86XSaveArea, opmask_state),
1123 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1124 [XSTATE_ZMM_Hi256_BIT] =
1125 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1126 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1127 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1128 [XSTATE_Hi16_ZMM_BIT] =
1129 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1130 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1131 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1132 [XSTATE_PKRU_BIT] =
1133 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 1134 .offset = offsetof(X86XSaveArea, pkru_state),
1135 .size = sizeof(XSavePKRU) },
2560f19f 1136};
8e8aba50 1137
1fda6198
EH		 1138static uint32_t xsave_area_size(uint64_t mask)
1139{
1140 int i;
e3c9022b 1141 uint64_t ret = 0;
1fda6198 1142
e3c9022b 1143 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1144 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1145 if ((mask >> i) & 1) {
1146 ret = MAX(ret, esa->offset + esa->size);
1147 }
1148 }
1149 return ret;
1150}
1151
d6dcc558
SAGDR		 1152static inline bool accel_uses_host_cpuid(void)
1153{
1154 return kvm_enabled() || hvf_enabled();
1155}
1156
96193c22
EH		 1157static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1158{
1159 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1160 cpu->env.features[FEAT_XSAVE_COMP_LO];
1161}
1162
8b4beddc
EH		 1163const char *get_register_name_32(unsigned int reg)
1164{
31ccdde2 1165 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1166 return NULL;
1167 }
8e8aba50 1168 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1169}
1170
84f1b92f
EH		 1171/*
1172 * Returns the set of feature flags that are supported and migratable by
1173 * QEMU, for a given FeatureWord.
1174 */
1175static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1176{
1177 FeatureWordInfo *wi = &feature_word_info[w];
1178 uint32_t r = 0;
1179 int i;
1180
1181 for (i = 0; i < 32; i++) {
1182 uint32_t f = 1U << i;
6fb2fff7
EH		 1183
1184 /* If the feature name is known, it is implicitly considered migratable,
1185 * unless it is explicitly set in unmigratable_flags */
1186 if ((wi->migratable_flags & f) ||
1187 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1188 r |= f;
84f1b92f 1189 }
84f1b92f
EH		 1190 }
1191 return r;
1192}
1193
bb44e0d1
JK		 1194void host_cpuid(uint32_t function, uint32_t count,
1195 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1196{
a1fd24af
AL		 1197 uint32_t vec[4];
1198
1199#ifdef __x86_64__
1200 asm volatile("cpuid"
1201 : "=a"(vec[0]), "=b"(vec[1]),
1202 "=c"(vec[2]), "=d"(vec[3])
1203 : "0"(function), "c"(count) : "cc");
c1f41226 1204#elif defined(__i386__)
a1fd24af
AL		 1205 asm volatile("pusha \n\t"
1206 "cpuid \n\t"
1207 "mov %%eax, 0(%2) \n\t"
1208 "mov %%ebx, 4(%2) \n\t"
1209 "mov %%ecx, 8(%2) \n\t"
1210 "mov %%edx, 12(%2) \n\t"
1211 "popa"
1212 : : "a"(function), "c"(count), "S"(vec)
1213 : "memory", "cc");
c1f41226
EH		 1214#else
1215 abort();
a1fd24af
AL		 1216#endif
1217
bdde476a 1218 if (eax)
a1fd24af 1219 *eax = vec[0];
bdde476a 1220 if (ebx)
a1fd24af 1221 *ebx = vec[1];
bdde476a 1222 if (ecx)
a1fd24af 1223 *ecx = vec[2];
bdde476a 1224 if (edx)
a1fd24af 1225 *edx = vec[3];
bdde476a 1226}
c6dc6f63 1227
20271d48
EH		 1228void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1229{
1230 uint32_t eax, ebx, ecx, edx;
1231
1232 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1233 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1234
1235 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1236 if (family) {
1237 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1238 }
1239 if (model) {
1240 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1241 }
1242 if (stepping) {
1243 *stepping = eax & 0x0F;
1244 }
1245}
1246
d940ee9b
EH		 1247/* CPU class name definitions: */
1248
d940ee9b
EH		 1249/* Return type name for a given CPU model name
1250 * Caller is responsible for freeing the returned string.
1251 */
1252static char *x86_cpu_type_name(const char *model_name)
1253{
1254 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1255}
1256
500050d1
AF		 1257static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1258{
d940ee9b 1259 ObjectClass *oc;
99193d8f 1260 char *typename = x86_cpu_type_name(cpu_model);
d940ee9b
EH		 1261 oc = object_class_by_name(typename);
1262 g_free(typename);
1263 return oc;
500050d1
AF		 1264}
1265
104494ea
IM		 1266static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1267{
1268 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1269 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1270 return g_strndup(class_name,
1271 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1272}
1273
d940ee9b 1274struct X86CPUDefinition {
c6dc6f63
AP		 1275 const char *name;
1276 uint32_t level;
90e4b0c3 1277 uint32_t xlevel;
99b88a17
IM		 1278 /* vendor is zero-terminated, 12 character ASCII string */
1279 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1280 int family;
1281 int model;
1282 int stepping;
0514ef2f 1283 FeatureWordArray features;
807e9869 1284 const char *model_id;
6aaeb054 1285 CPUCaches *cache_info;
d940ee9b 1286};
c6dc6f63 1287
fe52acd2 1288static CPUCaches epyc_cache_info = {
a9f27ea9 1289 .l1d_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1290 .type = DCACHE,
1291 .level = 1,
1292 .size = 32 * KiB,
1293 .line_size = 64,
1294 .associativity = 8,
1295 .partitions = 1,
1296 .sets = 64,
1297 .lines_per_tag = 1,
1298 .self_init = 1,
1299 .no_invd_sharing = true,
1300 },
a9f27ea9 1301 .l1i_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1302 .type = ICACHE,
1303 .level = 1,
1304 .size = 64 * KiB,
1305 .line_size = 64,
1306 .associativity = 4,
1307 .partitions = 1,
1308 .sets = 256,
1309 .lines_per_tag = 1,
1310 .self_init = 1,
1311 .no_invd_sharing = true,
1312 },
a9f27ea9 1313 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1314 .type = UNIFIED_CACHE,
1315 .level = 2,
1316 .size = 512 * KiB,
1317 .line_size = 64,
1318 .associativity = 8,
1319 .partitions = 1,
1320 .sets = 1024,
1321 .lines_per_tag = 1,
1322 },
a9f27ea9 1323 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1324 .type = UNIFIED_CACHE,
1325 .level = 3,
1326 .size = 8 * MiB,
1327 .line_size = 64,
1328 .associativity = 16,
1329 .partitions = 1,
1330 .sets = 8192,
1331 .lines_per_tag = 1,
1332 .self_init = true,
1333 .inclusive = true,
1334 .complex_indexing = true,
1335 },
1336};
1337
9576de75 1338static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1339 {
1340 .name = "qemu64",
3046bb5d 1341 .level = 0xd,
99b88a17 1342 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 1343 .family = 6,
f8e6a11a 1344 .model = 6,
c6dc6f63 1345 .stepping = 3,
0514ef2f 1346 .features[FEAT_1_EDX] =
27861ecc 1347 PPRO_FEATURES |
c6dc6f63 1348 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1349 CPUID_PSE36,
0514ef2f 1350 .features[FEAT_1_ECX] =
6aa91e4a 1351 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1352 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1353 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1354 .features[FEAT_8000_0001_ECX] =
71195672 1355 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1356 .xlevel = 0x8000000A,
9cf2cc3d 1357 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1358 },
1359 {
1360 .name = "phenom",
1361 .level = 5,
99b88a17 1362 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1363 .family = 16,
1364 .model = 2,
1365 .stepping = 3,
b9fc20bc 1366 /* Missing: CPUID_HT */
0514ef2f 1367 .features[FEAT_1_EDX] =
27861ecc 1368 PPRO_FEATURES |
c6dc6f63 1369 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1370 CPUID_PSE36 | CPUID_VME,
0514ef2f 1371 .features[FEAT_1_ECX] =
27861ecc 1372 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1373 CPUID_EXT_POPCNT,
0514ef2f 1374 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1375 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1376 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1377 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1378 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1379 CPUID_EXT3_CR8LEG,
1380 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1381 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1382 .features[FEAT_8000_0001_ECX] =
27861ecc 1383 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1384 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1385 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1386 .features[FEAT_SVM] =
b9fc20bc 1387 CPUID_SVM_NPT,
c6dc6f63
AP		 1388 .xlevel = 0x8000001A,
1389 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1390 },
1391 {
1392 .name = "core2duo",
1393 .level = 10,
99b88a17 1394 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1395 .family = 6,
1396 .model = 15,
1397 .stepping = 11,
b9fc20bc 1398 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1399 .features[FEAT_1_EDX] =
27861ecc 1400 PPRO_FEATURES |
c6dc6f63 1401 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1402 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1403 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1404 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1405 .features[FEAT_1_ECX] =
27861ecc 1406 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1407 CPUID_EXT_CX16,
0514ef2f 1408 .features[FEAT_8000_0001_EDX] =
27861ecc 1409 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1410 .features[FEAT_8000_0001_ECX] =
27861ecc 1411 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 1412 .xlevel = 0x80000008,
1413 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1414 },
1415 {
1416 .name = "kvm64",
3046bb5d 1417 .level = 0xd,
99b88a17 1418 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1419 .family = 15,
1420 .model = 6,
1421 .stepping = 1,
b3a4f0b1 1422 /* Missing: CPUID_HT */
0514ef2f 1423 .features[FEAT_1_EDX] =
b3a4f0b1 1424 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1425 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1426 CPUID_PSE36,
1427 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1428 .features[FEAT_1_ECX] =
27861ecc 1429 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1430 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1431 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1432 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1433 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1434 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1435 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1436 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1437 .features[FEAT_8000_0001_ECX] =
27861ecc 1438 0,
c6dc6f63
AP		 1439 .xlevel = 0x80000008,
1440 .model_id = "Common KVM processor"
1441 },
c6dc6f63
AP		 1442 {
1443 .name = "qemu32",
1444 .level = 4,
99b88a17 1445 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1446 .family = 6,
f8e6a11a 1447 .model = 6,
c6dc6f63 1448 .stepping = 3,
0514ef2f 1449 .features[FEAT_1_EDX] =
27861ecc 1450 PPRO_FEATURES,
0514ef2f 1451 .features[FEAT_1_ECX] =
6aa91e4a 1452 CPUID_EXT_SSE3,
58012d66 1453 .xlevel = 0x80000004,
9cf2cc3d 1454 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1455 },
eafaf1e5
AP		 1456 {
1457 .name = "kvm32",
1458 .level = 5,
99b88a17 1459 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1460 .family = 15,
1461 .model = 6,
1462 .stepping = 1,
0514ef2f 1463 .features[FEAT_1_EDX] =
b3a4f0b1 1464 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1465 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1466 .features[FEAT_1_ECX] =
27861ecc 1467 CPUID_EXT_SSE3,
0514ef2f 1468 .features[FEAT_8000_0001_ECX] =
27861ecc 1469 0,
eafaf1e5
AP		 1470 .xlevel = 0x80000008,
1471 .model_id = "Common 32-bit KVM processor"
1472 },
c6dc6f63
AP		 1473 {
1474 .name = "coreduo",
1475 .level = 10,
99b88a17 1476 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1477 .family = 6,
1478 .model = 14,
1479 .stepping = 8,
b9fc20bc 1480 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1481 .features[FEAT_1_EDX] =
27861ecc 1482 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1483 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1484 CPUID_SS,
1485 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1486 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1487 .features[FEAT_1_ECX] =
e93abc14 1488 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1489 .features[FEAT_8000_0001_EDX] =
27861ecc 1490 CPUID_EXT2_NX,
c6dc6f63
AP		 1491 .xlevel = 0x80000008,
1492 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1493 },
1494 {
1495 .name = "486",
58012d66 1496 .level = 1,
99b88a17 1497 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1498 .family = 4,
b2a856d9 1499 .model = 8,
c6dc6f63 1500 .stepping = 0,
0514ef2f 1501 .features[FEAT_1_EDX] =
27861ecc 1502 I486_FEATURES,
c6dc6f63 1503 .xlevel = 0,
807e9869 1504 .model_id = "",
c6dc6f63
AP		 1505 },
1506 {
1507 .name = "pentium",
1508 .level = 1,
99b88a17 1509 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1510 .family = 5,
1511 .model = 4,
1512 .stepping = 3,
0514ef2f 1513 .features[FEAT_1_EDX] =
27861ecc 1514 PENTIUM_FEATURES,
c6dc6f63 1515 .xlevel = 0,
807e9869 1516 .model_id = "",
c6dc6f63
AP		 1517 },
1518 {
1519 .name = "pentium2",
1520 .level = 2,
99b88a17 1521 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1522 .family = 6,
1523 .model = 5,
1524 .stepping = 2,
0514ef2f 1525 .features[FEAT_1_EDX] =
27861ecc 1526 PENTIUM2_FEATURES,
c6dc6f63 1527 .xlevel = 0,
807e9869 1528 .model_id = "",
c6dc6f63
AP		 1529 },
1530 {
1531 .name = "pentium3",
3046bb5d 1532 .level = 3,
99b88a17 1533 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1534 .family = 6,
1535 .model = 7,
1536 .stepping = 3,
0514ef2f 1537 .features[FEAT_1_EDX] =
27861ecc 1538 PENTIUM3_FEATURES,
c6dc6f63 1539 .xlevel = 0,
807e9869 1540 .model_id = "",
c6dc6f63
AP		 1541 },
1542 {
1543 .name = "athlon",
1544 .level = 2,
99b88a17 1545 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1546 .family = 6,
1547 .model = 2,
1548 .stepping = 3,
0514ef2f 1549 .features[FEAT_1_EDX] =
27861ecc 1550 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 1551 CPUID_MCA,
0514ef2f 1552 .features[FEAT_8000_0001_EDX] =
60032ac0 1553 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 1554 .xlevel = 0x80000008,
9cf2cc3d 1555 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1556 },
1557 {
1558 .name = "n270",
3046bb5d 1559 .level = 10,
99b88a17 1560 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1561 .family = 6,
1562 .model = 28,
1563 .stepping = 2,
b9fc20bc 1564 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1565 .features[FEAT_1_EDX] =
27861ecc 1566 PPRO_FEATURES |
b9fc20bc
EH		 1567 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1568 CPUID_ACPI | CPUID_SS,
c6dc6f63 1569 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1570 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1571 * CPUID_EXT_XTPR */
0514ef2f 1572 .features[FEAT_1_ECX] =
27861ecc 1573 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1574 CPUID_EXT_MOVBE,
0514ef2f 1575 .features[FEAT_8000_0001_EDX] =
60032ac0 1576 CPUID_EXT2_NX,
0514ef2f 1577 .features[FEAT_8000_0001_ECX] =
27861ecc 1578 CPUID_EXT3_LAHF_LM,
3046bb5d 1579 .xlevel = 0x80000008,
c6dc6f63
AP		 1580 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1581 },
3eca4642
EH		 1582 {
1583 .name = "Conroe",
3046bb5d 1584 .level = 10,
99b88a17 1585 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1586 .family = 6,
ffce9ebb 1587 .model = 15,
3eca4642 1588 .stepping = 3,
0514ef2f 1589 .features[FEAT_1_EDX] =
b3a4f0b1 1590 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1591 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1592 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1593 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1594 CPUID_DE | CPUID_FP87,
0514ef2f 1595 .features[FEAT_1_ECX] =
27861ecc 1596 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1597 .features[FEAT_8000_0001_EDX] =
27861ecc 1598 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1599 .features[FEAT_8000_0001_ECX] =
27861ecc 1600 CPUID_EXT3_LAHF_LM,
3046bb5d 1601 .xlevel = 0x80000008,
3eca4642
EH		 1602 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1603 },
1604 {
1605 .name = "Penryn",
3046bb5d 1606 .level = 10,
99b88a17 1607 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1608 .family = 6,
ffce9ebb 1609 .model = 23,
3eca4642 1610 .stepping = 3,
0514ef2f 1611 .features[FEAT_1_EDX] =
b3a4f0b1 1612 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1613 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1614 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1615 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1616 CPUID_DE | CPUID_FP87,
0514ef2f 1617 .features[FEAT_1_ECX] =
27861ecc 1618 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1619 CPUID_EXT_SSE3,
0514ef2f 1620 .features[FEAT_8000_0001_EDX] =
27861ecc 1621 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1622 .features[FEAT_8000_0001_ECX] =
27861ecc 1623 CPUID_EXT3_LAHF_LM,
3046bb5d 1624 .xlevel = 0x80000008,
3eca4642
EH		 1625 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1626 },
1627 {
1628 .name = "Nehalem",
3046bb5d 1629 .level = 11,
99b88a17 1630 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1631 .family = 6,
ffce9ebb 1632 .model = 26,
3eca4642 1633 .stepping = 3,
0514ef2f 1634 .features[FEAT_1_EDX] =
b3a4f0b1 1635 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1636 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1637 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1638 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1639 CPUID_DE | CPUID_FP87,
0514ef2f 1640 .features[FEAT_1_ECX] =
27861ecc 1641 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1642 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1643 .features[FEAT_8000_0001_EDX] =
27861ecc 1644 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1645 .features[FEAT_8000_0001_ECX] =
27861ecc 1646 CPUID_EXT3_LAHF_LM,
3046bb5d 1647 .xlevel = 0x80000008,
3eca4642
EH		 1648 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1649 },
ac96c413
EH		 1650 {
1651 .name = "Nehalem-IBRS",
1652 .level = 11,
1653 .vendor = CPUID_VENDOR_INTEL,
1654 .family = 6,
1655 .model = 26,
1656 .stepping = 3,
1657 .features[FEAT_1_EDX] =
1658 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1659 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1660 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1661 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1662 CPUID_DE | CPUID_FP87,
1663 .features[FEAT_1_ECX] =
1664 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1665 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1666 .features[FEAT_7_0_EDX] =
1667 CPUID_7_0_EDX_SPEC_CTRL,
1668 .features[FEAT_8000_0001_EDX] =
1669 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1670 .features[FEAT_8000_0001_ECX] =
1671 CPUID_EXT3_LAHF_LM,
1672 .xlevel = 0x80000008,
1673 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1674 },
3eca4642
EH		 1675 {
1676 .name = "Westmere",
1677 .level = 11,
99b88a17 1678 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1679 .family = 6,
1680 .model = 44,
1681 .stepping = 1,
0514ef2f 1682 .features[FEAT_1_EDX] =
b3a4f0b1 1683 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1684 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1685 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1686 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1687 CPUID_DE | CPUID_FP87,
0514ef2f 1688 .features[FEAT_1_ECX] =
27861ecc 1689 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1690 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1691 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1692 .features[FEAT_8000_0001_EDX] =
27861ecc 1693 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1694 .features[FEAT_8000_0001_ECX] =
27861ecc 1695 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1696 .features[FEAT_6_EAX] =
1697 CPUID_6_EAX_ARAT,
3046bb5d 1698 .xlevel = 0x80000008,
3eca4642
EH		 1699 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1700 },
ac96c413
EH		 1701 {
1702 .name = "Westmere-IBRS",
1703 .level = 11,
1704 .vendor = CPUID_VENDOR_INTEL,
1705 .family = 6,
1706 .model = 44,
1707 .stepping = 1,
1708 .features[FEAT_1_EDX] =
1709 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1710 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1711 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1712 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1713 CPUID_DE | CPUID_FP87,
1714 .features[FEAT_1_ECX] =
1715 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1716 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1717 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1718 .features[FEAT_8000_0001_EDX] =
1719 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1720 .features[FEAT_8000_0001_ECX] =
1721 CPUID_EXT3_LAHF_LM,
1722 .features[FEAT_7_0_EDX] =
1723 CPUID_7_0_EDX_SPEC_CTRL,
1724 .features[FEAT_6_EAX] =
1725 CPUID_6_EAX_ARAT,
1726 .xlevel = 0x80000008,
1727 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1728 },
3eca4642
EH		 1729 {
1730 .name = "SandyBridge",
1731 .level = 0xd,
99b88a17 1732 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1733 .family = 6,
1734 .model = 42,
1735 .stepping = 1,
0514ef2f 1736 .features[FEAT_1_EDX] =
b3a4f0b1 1737 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1738 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1739 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1740 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1741 CPUID_DE | CPUID_FP87,
0514ef2f 1742 .features[FEAT_1_ECX] =
27861ecc 1743 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1744 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1745 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1746 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1747 CPUID_EXT_SSE3,
0514ef2f 1748 .features[FEAT_8000_0001_EDX] =
27861ecc 1749 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1750 CPUID_EXT2_SYSCALL,
0514ef2f 1751 .features[FEAT_8000_0001_ECX] =
27861ecc 1752 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1753 .features[FEAT_XSAVE] =
1754 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1755 .features[FEAT_6_EAX] =
1756 CPUID_6_EAX_ARAT,
3046bb5d 1757 .xlevel = 0x80000008,
3eca4642
EH		 1758 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1759 },
ac96c413
EH		 1760 {
1761 .name = "SandyBridge-IBRS",
1762 .level = 0xd,
1763 .vendor = CPUID_VENDOR_INTEL,
1764 .family = 6,
1765 .model = 42,
1766 .stepping = 1,
1767 .features[FEAT_1_EDX] =
1768 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1769 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1770 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1771 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1772 CPUID_DE | CPUID_FP87,
1773 .features[FEAT_1_ECX] =
1774 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1775 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1776 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1777 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1778 CPUID_EXT_SSE3,
1779 .features[FEAT_8000_0001_EDX] =
1780 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1781 CPUID_EXT2_SYSCALL,
1782 .features[FEAT_8000_0001_ECX] =
1783 CPUID_EXT3_LAHF_LM,
1784 .features[FEAT_7_0_EDX] =
1785 CPUID_7_0_EDX_SPEC_CTRL,
1786 .features[FEAT_XSAVE] =
1787 CPUID_XSAVE_XSAVEOPT,
1788 .features[FEAT_6_EAX] =
1789 CPUID_6_EAX_ARAT,
1790 .xlevel = 0x80000008,
1791 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1792 },
2f9ac42a
PB		 1793 {
1794 .name = "IvyBridge",
1795 .level = 0xd,
1796 .vendor = CPUID_VENDOR_INTEL,
1797 .family = 6,
1798 .model = 58,
1799 .stepping = 9,
1800 .features[FEAT_1_EDX] =
1801 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1802 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1803 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1804 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1805 CPUID_DE | CPUID_FP87,
1806 .features[FEAT_1_ECX] =
1807 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1808 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1809 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1810 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1811 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1812 .features[FEAT_7_0_EBX] =
1813 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1814 CPUID_7_0_EBX_ERMS,
1815 .features[FEAT_8000_0001_EDX] =
1816 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1817 CPUID_EXT2_SYSCALL,
1818 .features[FEAT_8000_0001_ECX] =
1819 CPUID_EXT3_LAHF_LM,
1820 .features[FEAT_XSAVE] =
1821 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1822 .features[FEAT_6_EAX] =
1823 CPUID_6_EAX_ARAT,
3046bb5d 1824 .xlevel = 0x80000008,
2f9ac42a
PB		 1825 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1826 },
ac96c413
EH		 1827 {
1828 .name = "IvyBridge-IBRS",
1829 .level = 0xd,
1830 .vendor = CPUID_VENDOR_INTEL,
1831 .family = 6,
1832 .model = 58,
1833 .stepping = 9,
1834 .features[FEAT_1_EDX] =
1835 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1836 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1837 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1838 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1839 CPUID_DE | CPUID_FP87,
1840 .features[FEAT_1_ECX] =
1841 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1842 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1843 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1844 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1845 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1846 .features[FEAT_7_0_EBX] =
1847 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1848 CPUID_7_0_EBX_ERMS,
1849 .features[FEAT_8000_0001_EDX] =
1850 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1851 CPUID_EXT2_SYSCALL,
1852 .features[FEAT_8000_0001_ECX] =
1853 CPUID_EXT3_LAHF_LM,
1854 .features[FEAT_7_0_EDX] =
1855 CPUID_7_0_EDX_SPEC_CTRL,
1856 .features[FEAT_XSAVE] =
1857 CPUID_XSAVE_XSAVEOPT,
1858 .features[FEAT_6_EAX] =
1859 CPUID_6_EAX_ARAT,
1860 .xlevel = 0x80000008,
1861 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
1862 },
37507094 1863 {
a356850b
EH		 1864 .name = "Haswell-noTSX",
1865 .level = 0xd,
1866 .vendor = CPUID_VENDOR_INTEL,
1867 .family = 6,
1868 .model = 60,
1869 .stepping = 1,
1870 .features[FEAT_1_EDX] =
1871 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1872 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1873 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1874 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1875 CPUID_DE | CPUID_FP87,
1876 .features[FEAT_1_ECX] =
1877 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1878 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1879 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1880 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1881 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1882 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1883 .features[FEAT_8000_0001_EDX] =
1884 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1885 CPUID_EXT2_SYSCALL,
1886 .features[FEAT_8000_0001_ECX] =
becb6667 1887 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1888 .features[FEAT_7_0_EBX] =
1889 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1890 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1891 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1892 .features[FEAT_XSAVE] =
1893 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1894 .features[FEAT_6_EAX] =
1895 CPUID_6_EAX_ARAT,
3046bb5d 1896 .xlevel = 0x80000008,
a356850b 1897 .model_id = "Intel Core Processor (Haswell, no TSX)",
ac96c413
EH		 1898 },
1899 {
1900 .name = "Haswell-noTSX-IBRS",
1901 .level = 0xd,
1902 .vendor = CPUID_VENDOR_INTEL,
1903 .family = 6,
1904 .model = 60,
1905 .stepping = 1,
1906 .features[FEAT_1_EDX] =
1907 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1908 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1909 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1910 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1911 CPUID_DE | CPUID_FP87,
1912 .features[FEAT_1_ECX] =
1913 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1914 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1915 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1916 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1917 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1918 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1919 .features[FEAT_8000_0001_EDX] =
1920 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1921 CPUID_EXT2_SYSCALL,
1922 .features[FEAT_8000_0001_ECX] =
1923 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1924 .features[FEAT_7_0_EDX] =
1925 CPUID_7_0_EDX_SPEC_CTRL,
1926 .features[FEAT_7_0_EBX] =
1927 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1928 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1929 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1930 .features[FEAT_XSAVE] =
1931 CPUID_XSAVE_XSAVEOPT,
1932 .features[FEAT_6_EAX] =
1933 CPUID_6_EAX_ARAT,
1934 .xlevel = 0x80000008,
1935 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
1936 },
1937 {
37507094
EH		 1938 .name = "Haswell",
1939 .level = 0xd,
99b88a17 1940 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1941 .family = 6,
1942 .model = 60,
ec56a4a7 1943 .stepping = 4,
0514ef2f 1944 .features[FEAT_1_EDX] =
b3a4f0b1 1945 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1946 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1947 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1948 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1949 CPUID_DE | CPUID_FP87,
0514ef2f 1950 .features[FEAT_1_ECX] =
27861ecc 1951 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1952 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1953 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1954 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1955 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1956 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1957 .features[FEAT_8000_0001_EDX] =
27861ecc 1958 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1959 CPUID_EXT2_SYSCALL,
0514ef2f 1960 .features[FEAT_8000_0001_ECX] =
becb6667 1961 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1962 .features[FEAT_7_0_EBX] =
27861ecc 1963 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1964 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1965 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1966 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1967 .features[FEAT_XSAVE] =
1968 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1969 .features[FEAT_6_EAX] =
1970 CPUID_6_EAX_ARAT,
3046bb5d 1971 .xlevel = 0x80000008,
37507094
EH		 1972 .model_id = "Intel Core Processor (Haswell)",
1973 },
ac96c413
EH		 1974 {
1975 .name = "Haswell-IBRS",
1976 .level = 0xd,
1977 .vendor = CPUID_VENDOR_INTEL,
1978 .family = 6,
1979 .model = 60,
1980 .stepping = 4,
1981 .features[FEAT_1_EDX] =
1982 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1983 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1984 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1985 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1986 CPUID_DE | CPUID_FP87,
1987 .features[FEAT_1_ECX] =
1988 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1989 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1990 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1991 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1992 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1993 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1994 .features[FEAT_8000_0001_EDX] =
1995 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1996 CPUID_EXT2_SYSCALL,
1997 .features[FEAT_8000_0001_ECX] =
1998 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1999 .features[FEAT_7_0_EDX] =
2000 CPUID_7_0_EDX_SPEC_CTRL,
2001 .features[FEAT_7_0_EBX] =
2002 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2003 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2004 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2005 CPUID_7_0_EBX_RTM,
2006 .features[FEAT_XSAVE] =
2007 CPUID_XSAVE_XSAVEOPT,
2008 .features[FEAT_6_EAX] =
2009 CPUID_6_EAX_ARAT,
2010 .xlevel = 0x80000008,
2011 .model_id = "Intel Core Processor (Haswell, IBRS)",
2012 },
a356850b
EH		 2013 {
2014 .name = "Broadwell-noTSX",
2015 .level = 0xd,
2016 .vendor = CPUID_VENDOR_INTEL,
2017 .family = 6,
2018 .model = 61,
2019 .stepping = 2,
2020 .features[FEAT_1_EDX] =
2021 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2022 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2023 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2024 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2025 CPUID_DE | CPUID_FP87,
2026 .features[FEAT_1_ECX] =
2027 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2028 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2029 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2030 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2031 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2032 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2033 .features[FEAT_8000_0001_EDX] =
2034 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2035 CPUID_EXT2_SYSCALL,
2036 .features[FEAT_8000_0001_ECX] =
becb6667 2037 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 2038 .features[FEAT_7_0_EBX] =
2039 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2040 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2041 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2042 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2043 CPUID_7_0_EBX_SMAP,
2044 .features[FEAT_XSAVE] =
2045 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2046 .features[FEAT_6_EAX] =
2047 CPUID_6_EAX_ARAT,
3046bb5d 2048 .xlevel = 0x80000008,
a356850b
EH		 2049 .model_id = "Intel Core Processor (Broadwell, no TSX)",
2050 },
ac96c413
EH		 2051 {
2052 .name = "Broadwell-noTSX-IBRS",
2053 .level = 0xd,
2054 .vendor = CPUID_VENDOR_INTEL,
2055 .family = 6,
2056 .model = 61,
2057 .stepping = 2,
2058 .features[FEAT_1_EDX] =
2059 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2060 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2061 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2062 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2063 CPUID_DE | CPUID_FP87,
2064 .features[FEAT_1_ECX] =
2065 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2066 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2067 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2068 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2069 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2070 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2071 .features[FEAT_8000_0001_EDX] =
2072 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2073 CPUID_EXT2_SYSCALL,
2074 .features[FEAT_8000_0001_ECX] =
2075 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2076 .features[FEAT_7_0_EDX] =
2077 CPUID_7_0_EDX_SPEC_CTRL,
2078 .features[FEAT_7_0_EBX] =
2079 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2080 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2081 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2082 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2083 CPUID_7_0_EBX_SMAP,
2084 .features[FEAT_XSAVE] =
2085 CPUID_XSAVE_XSAVEOPT,
2086 .features[FEAT_6_EAX] =
2087 CPUID_6_EAX_ARAT,
2088 .xlevel = 0x80000008,
2089 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
2090 },
ece01354
EH		 2091 {
2092 .name = "Broadwell",
2093 .level = 0xd,
2094 .vendor = CPUID_VENDOR_INTEL,
2095 .family = 6,
2096 .model = 61,
2097 .stepping = 2,
2098 .features[FEAT_1_EDX] =
b3a4f0b1 2099 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2100 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2101 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2102 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2103 CPUID_DE | CPUID_FP87,
2104 .features[FEAT_1_ECX] =
2105 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2106 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2107 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2108 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2109 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2110 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2111 .features[FEAT_8000_0001_EDX] =
2112 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2113 CPUID_EXT2_SYSCALL,
2114 .features[FEAT_8000_0001_ECX] =
becb6667 2115 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2116 .features[FEAT_7_0_EBX] =
2117 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2118 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2119 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2120 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2121 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2122 .features[FEAT_XSAVE] =
2123 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2124 .features[FEAT_6_EAX] =
2125 CPUID_6_EAX_ARAT,
3046bb5d 2126 .xlevel = 0x80000008,
ece01354
EH		 2127 .model_id = "Intel Core Processor (Broadwell)",
2128 },
ac96c413
EH		 2129 {
2130 .name = "Broadwell-IBRS",
2131 .level = 0xd,
2132 .vendor = CPUID_VENDOR_INTEL,
2133 .family = 6,
2134 .model = 61,
2135 .stepping = 2,
2136 .features[FEAT_1_EDX] =
2137 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2138 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2139 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2140 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2141 CPUID_DE | CPUID_FP87,
2142 .features[FEAT_1_ECX] =
2143 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2144 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2145 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2146 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2147 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2148 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2149 .features[FEAT_8000_0001_EDX] =
2150 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2151 CPUID_EXT2_SYSCALL,
2152 .features[FEAT_8000_0001_ECX] =
2153 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2154 .features[FEAT_7_0_EDX] =
2155 CPUID_7_0_EDX_SPEC_CTRL,
2156 .features[FEAT_7_0_EBX] =
2157 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2158 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2159 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2160 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2161 CPUID_7_0_EBX_SMAP,
2162 .features[FEAT_XSAVE] =
2163 CPUID_XSAVE_XSAVEOPT,
2164 .features[FEAT_6_EAX] =
2165 CPUID_6_EAX_ARAT,
2166 .xlevel = 0x80000008,
2167 .model_id = "Intel Core Processor (Broadwell, IBRS)",
2168 },
f6f949e9
EH		 2169 {
2170 .name = "Skylake-Client",
2171 .level = 0xd,
2172 .vendor = CPUID_VENDOR_INTEL,
2173 .family = 6,
2174 .model = 94,
2175 .stepping = 3,
2176 .features[FEAT_1_EDX] =
2177 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2178 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2179 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2180 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2181 CPUID_DE | CPUID_FP87,
2182 .features[FEAT_1_ECX] =
2183 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2184 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2185 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2186 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2187 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2188 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2189 .features[FEAT_8000_0001_EDX] =
2190 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2191 CPUID_EXT2_SYSCALL,
2192 .features[FEAT_8000_0001_ECX] =
2193 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2194 .features[FEAT_7_0_EBX] =
2195 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2196 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2197 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2198 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2199 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
2200 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 2201 * including v4.1 to v4.12).
f6f949e9
EH		 2202 * KVM doesn't yet expose any XSAVES state save component,
2203 * and the only one defined in Skylake (processor tracing)
2204 * probably will block migration anyway.
2205 */
2206 .features[FEAT_XSAVE] =
2207 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2208 CPUID_XSAVE_XGETBV1,
2209 .features[FEAT_6_EAX] =
2210 CPUID_6_EAX_ARAT,
2211 .xlevel = 0x80000008,
2212 .model_id = "Intel Core Processor (Skylake)",
2213 },
ac96c413
EH		 2214 {
2215 .name = "Skylake-Client-IBRS",
2216 .level = 0xd,
2217 .vendor = CPUID_VENDOR_INTEL,
2218 .family = 6,
2219 .model = 94,
2220 .stepping = 3,
2221 .features[FEAT_1_EDX] =
2222 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2223 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2224 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2225 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2226 CPUID_DE | CPUID_FP87,
2227 .features[FEAT_1_ECX] =
2228 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2229 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2230 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2231 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2232 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2233 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2234 .features[FEAT_8000_0001_EDX] =
2235 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2236 CPUID_EXT2_SYSCALL,
2237 .features[FEAT_8000_0001_ECX] =
2238 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2239 .features[FEAT_7_0_EDX] =
2240 CPUID_7_0_EDX_SPEC_CTRL,
2241 .features[FEAT_7_0_EBX] =
2242 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2243 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2244 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2245 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2246 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
2247 /* Missing: XSAVES (not supported by some Linux versions,
2248 * including v4.1 to v4.12).
2249 * KVM doesn't yet expose any XSAVES state save component,
2250 * and the only one defined in Skylake (processor tracing)
2251 * probably will block migration anyway.
2252 */
2253 .features[FEAT_XSAVE] =
2254 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2255 CPUID_XSAVE_XGETBV1,
2256 .features[FEAT_6_EAX] =
2257 CPUID_6_EAX_ARAT,
2258 .xlevel = 0x80000008,
2259 .model_id = "Intel Core Processor (Skylake, IBRS)",
2260 },
53f9a6f4
BF		 2261 {
2262 .name = "Skylake-Server",
2263 .level = 0xd,
2264 .vendor = CPUID_VENDOR_INTEL,
2265 .family = 6,
2266 .model = 85,
2267 .stepping = 4,
2268 .features[FEAT_1_EDX] =
2269 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2270 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2271 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2272 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2273 CPUID_DE | CPUID_FP87,
2274 .features[FEAT_1_ECX] =
2275 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2276 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2277 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2278 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2279 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2280 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2281 .features[FEAT_8000_0001_EDX] =
2282 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2283 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2284 .features[FEAT_8000_0001_ECX] =
2285 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2286 .features[FEAT_7_0_EBX] =
2287 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2288 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2289 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2290 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2291 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2292 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2293 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2294 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
53f9a6f4
BF		 2295 /* Missing: XSAVES (not supported by some Linux versions,
2296 * including v4.1 to v4.12).
2297 * KVM doesn't yet expose any XSAVES state save component,
2298 * and the only one defined in Skylake (processor tracing)
2299 * probably will block migration anyway.
2300 */
2301 .features[FEAT_XSAVE] =
2302 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2303 CPUID_XSAVE_XGETBV1,
2304 .features[FEAT_6_EAX] =
2305 CPUID_6_EAX_ARAT,
2306 .xlevel = 0x80000008,
2307 .model_id = "Intel Xeon Processor (Skylake)",
2308 },
ac96c413
EH		 2309 {
2310 .name = "Skylake-Server-IBRS",
2311 .level = 0xd,
2312 .vendor = CPUID_VENDOR_INTEL,
2313 .family = 6,
2314 .model = 85,
2315 .stepping = 4,
2316 .features[FEAT_1_EDX] =
2317 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2318 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2319 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2320 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2321 CPUID_DE | CPUID_FP87,
2322 .features[FEAT_1_ECX] =
2323 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2324 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2325 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2326 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2327 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2328 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2329 .features[FEAT_8000_0001_EDX] =
2330 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2331 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2332 .features[FEAT_8000_0001_ECX] =
2333 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2334 .features[FEAT_7_0_EDX] =
2335 CPUID_7_0_EDX_SPEC_CTRL,
2336 .features[FEAT_7_0_EBX] =
2337 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2338 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2339 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2340 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2341 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2342 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2343 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2344 CPUID_7_0_EBX_AVX512VL,
2345 /* Missing: XSAVES (not supported by some Linux versions,
2346 * including v4.1 to v4.12).
2347 * KVM doesn't yet expose any XSAVES state save component,
2348 * and the only one defined in Skylake (processor tracing)
2349 * probably will block migration anyway.
2350 */
2351 .features[FEAT_XSAVE] =
2352 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2353 CPUID_XSAVE_XGETBV1,
2354 .features[FEAT_6_EAX] =
2355 CPUID_6_EAX_ARAT,
2356 .xlevel = 0x80000008,
2357 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2358 },
a1849515
BF		 2359 {
2360 .name = "KnightsMill",
2361 .level = 0xd,
2362 .vendor = CPUID_VENDOR_INTEL,
2363 .family = 6,
2364 .model = 133,
2365 .stepping = 0,
2366 .features[FEAT_1_EDX] =
2367 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2368 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2369 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2370 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2371 CPUID_PSE | CPUID_DE | CPUID_FP87,
2372 .features[FEAT_1_ECX] =
2373 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2374 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2375 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2376 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2377 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2378 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2379 .features[FEAT_8000_0001_EDX] =
2380 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2381 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2382 .features[FEAT_8000_0001_ECX] =
2383 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2384 .features[FEAT_7_0_EBX] =
2385 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2386 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2387 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2388 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2389 CPUID_7_0_EBX_AVX512ER,
2390 .features[FEAT_7_0_ECX] =
2391 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2392 .features[FEAT_7_0_EDX] =
2393 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2394 .features[FEAT_XSAVE] =
2395 CPUID_XSAVE_XSAVEOPT,
2396 .features[FEAT_6_EAX] =
2397 CPUID_6_EAX_ARAT,
2398 .xlevel = 0x80000008,
2399 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2400 },
3eca4642
EH		 2401 {
2402 .name = "Opteron_G1",
2403 .level = 5,
99b88a17 2404 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2405 .family = 15,
2406 .model = 6,
2407 .stepping = 1,
0514ef2f 2408 .features[FEAT_1_EDX] =
b3a4f0b1 2409 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2410 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2411 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2412 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2413 CPUID_DE | CPUID_FP87,
0514ef2f 2414 .features[FEAT_1_ECX] =
27861ecc 2415 CPUID_EXT_SSE3,
0514ef2f 2416 .features[FEAT_8000_0001_EDX] =
2a923a29 2417 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 2418 .xlevel = 0x80000008,
2419 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2420 },
2421 {
2422 .name = "Opteron_G2",
2423 .level = 5,
99b88a17 2424 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2425 .family = 15,
2426 .model = 6,
2427 .stepping = 1,
0514ef2f 2428 .features[FEAT_1_EDX] =
b3a4f0b1 2429 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2430 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2431 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2432 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2433 CPUID_DE | CPUID_FP87,
0514ef2f 2434 .features[FEAT_1_ECX] =
27861ecc 2435 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 2436 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2437 .features[FEAT_8000_0001_EDX] =
2a923a29 2438 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2439 .features[FEAT_8000_0001_ECX] =
27861ecc 2440 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2441 .xlevel = 0x80000008,
2442 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2443 },
2444 {
2445 .name = "Opteron_G3",
2446 .level = 5,
99b88a17 2447 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 2448 .family = 16,
2449 .model = 2,
2450 .stepping = 3,
0514ef2f 2451 .features[FEAT_1_EDX] =
b3a4f0b1 2452 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2453 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2454 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2455 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2456 CPUID_DE | CPUID_FP87,
0514ef2f 2457 .features[FEAT_1_ECX] =
27861ecc 2458 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 2459 CPUID_EXT_SSE3,
33b5e8c0 2460 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2461 .features[FEAT_8000_0001_EDX] =
2a923a29 2462 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2463 .features[FEAT_8000_0001_ECX] =
27861ecc 2464 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 2465 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2466 .xlevel = 0x80000008,
2467 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2468 },
2469 {
2470 .name = "Opteron_G4",
2471 .level = 0xd,
99b88a17 2472 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2473 .family = 21,
2474 .model = 1,
2475 .stepping = 2,
0514ef2f 2476 .features[FEAT_1_EDX] =
b3a4f0b1 2477 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2478 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2479 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2480 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2481 CPUID_DE | CPUID_FP87,
0514ef2f 2482 .features[FEAT_1_ECX] =
27861ecc 2483 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2484 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2485 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2486 CPUID_EXT_SSE3,
33b5e8c0 2487 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2488 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 2489 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2490 CPUID_EXT2_SYSCALL,
0514ef2f 2491 .features[FEAT_8000_0001_ECX] =
27861ecc 2492 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2493 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2494 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2495 CPUID_EXT3_LAHF_LM,
0bb0b2d2 2496 /* no xsaveopt! */
3eca4642
EH		 2497 .xlevel = 0x8000001A,
2498 .model_id = "AMD Opteron 62xx class CPU",
2499 },
021941b9
AP		 2500 {
2501 .name = "Opteron_G5",
2502 .level = 0xd,
99b88a17 2503 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 2504 .family = 21,
2505 .model = 2,
2506 .stepping = 0,
0514ef2f 2507 .features[FEAT_1_EDX] =
b3a4f0b1 2508 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2509 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2510 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2511 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2512 CPUID_DE | CPUID_FP87,
0514ef2f 2513 .features[FEAT_1_ECX] =
27861ecc 2514 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 2515 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2516 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2517 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 2518 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2519 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 2520 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2521 CPUID_EXT2_SYSCALL,
0514ef2f 2522 .features[FEAT_8000_0001_ECX] =
27861ecc 2523 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2524 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2525 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2526 CPUID_EXT3_LAHF_LM,
0bb0b2d2 2527 /* no xsaveopt! */
021941b9
AP		 2528 .xlevel = 0x8000001A,
2529 .model_id = "AMD Opteron 63xx class CPU",
2530 },
2e2efc7d
BS		 2531 {
2532 .name = "EPYC",
2533 .level = 0xd,
2534 .vendor = CPUID_VENDOR_AMD,
2535 .family = 23,
2536 .model = 1,
2537 .stepping = 2,
2538 .features[FEAT_1_EDX] =
2539 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2540 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2541 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2542 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2543 CPUID_VME | CPUID_FP87,
2544 .features[FEAT_1_ECX] =
2545 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2546 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2547 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2548 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2549 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2550 .features[FEAT_8000_0001_EDX] =
2551 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2552 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2553 CPUID_EXT2_SYSCALL,
2554 .features[FEAT_8000_0001_ECX] =
2555 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2556 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2557 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2558 .features[FEAT_7_0_EBX] =
2559 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2560 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2561 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2562 CPUID_7_0_EBX_SHA_NI,
2563 /* Missing: XSAVES (not supported by some Linux versions,
2564 * including v4.1 to v4.12).
2565 * KVM doesn't yet expose any XSAVES state save component.
2566 */
2567 .features[FEAT_XSAVE] =
2568 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2569 CPUID_XSAVE_XGETBV1,
2570 .features[FEAT_6_EAX] =
2571 CPUID_6_EAX_ARAT,
2572 .xlevel = 0x8000000A,
2573 .model_id = "AMD EPYC Processor",
fe52acd2 2574 .cache_info = &epyc_cache_info,
2e2efc7d 2575 },
6cfbc54e
EH		 2576 {
2577 .name = "EPYC-IBPB",
2578 .level = 0xd,
2579 .vendor = CPUID_VENDOR_AMD,
2580 .family = 23,
2581 .model = 1,
2582 .stepping = 2,
2583 .features[FEAT_1_EDX] =
2584 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2585 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2586 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2587 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2588 CPUID_VME | CPUID_FP87,
2589 .features[FEAT_1_ECX] =
2590 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2591 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2592 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2593 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2594 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2595 .features[FEAT_8000_0001_EDX] =
2596 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2597 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2598 CPUID_EXT2_SYSCALL,
2599 .features[FEAT_8000_0001_ECX] =
2600 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2601 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2602 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2603 .features[FEAT_8000_0008_EBX] =
2604 CPUID_8000_0008_EBX_IBPB,
2605 .features[FEAT_7_0_EBX] =
2606 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2607 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2608 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2609 CPUID_7_0_EBX_SHA_NI,
2610 /* Missing: XSAVES (not supported by some Linux versions,
2611 * including v4.1 to v4.12).
2612 * KVM doesn't yet expose any XSAVES state save component.
2613 */
2614 .features[FEAT_XSAVE] =
2615 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2616 CPUID_XSAVE_XGETBV1,
2617 .features[FEAT_6_EAX] =
2618 CPUID_6_EAX_ARAT,
2619 .xlevel = 0x8000000A,
2620 .model_id = "AMD EPYC Processor (with IBPB)",
fe52acd2 2621 .cache_info = &epyc_cache_info,
6cfbc54e 2622 },
c6dc6f63
AP		 2623};
2624
5114e842
EH		 2625typedef struct PropValue {
2626 const char *prop, *value;
2627} PropValue;
2628
2629/* KVM-specific features that are automatically added/removed
2630 * from all CPU models when KVM is enabled.
2631 */
2632static PropValue kvm_default_props[] = {
2633 { "kvmclock", "on" },
2634 { "kvm-nopiodelay", "on" },
2635 { "kvm-asyncpf", "on" },
2636 { "kvm-steal-time", "on" },
2637 { "kvm-pv-eoi", "on" },
2638 { "kvmclock-stable-bit", "on" },
2639 { "x2apic", "on" },
2640 { "acpi", "off" },
2641 { "monitor", "off" },
2642 { "svm", "off" },
2643 { NULL, NULL },
2644};
2645
04d99c3c
EH		 2646/* TCG-specific defaults that override all CPU models when using TCG
2647 */
2648static PropValue tcg_default_props[] = {
2649 { "vme", "off" },
2650 { NULL, NULL },
2651};
2652
2653
5114e842
EH		 2654void x86_cpu_change_kvm_default(const char *prop, const char *value)
2655{
2656 PropValue *pv;
2657 for (pv = kvm_default_props; pv->prop; pv++) {
2658 if (!strcmp(pv->prop, prop)) {
2659 pv->value = value;
2660 break;
2661 }
2662 }
2663
2664 /* It is valid to call this function only for properties that
2665 * are already present in the kvm_default_props table.
2666 */
2667 assert(pv->prop);
2668}
2669
4d1b279b
EH		 2670static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2671 bool migratable_only);
2672
40bfe48f
HZ		 2673static bool lmce_supported(void)
2674{
c62f2630 2675 uint64_t mce_cap = 0;
40bfe48f 2676
c62f2630 2677#ifdef CONFIG_KVM
40bfe48f
HZ		 2678 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
2679 return false;
2680 }
c62f2630 2681#endif
40bfe48f
HZ		 2682
2683 return !!(mce_cap & MCG_LMCE_P);
2684}
2685
7d8050b5
EH		 2686#define CPUID_MODEL_ID_SZ 48
2687
2688/**
2689 * cpu_x86_fill_model_id:
2690 * Get CPUID model ID string from host CPU.
2691 *
2692 * @str should have at least CPUID_MODEL_ID_SZ bytes
2693 *
2694 * The function does NOT add a null terminator to the string
2695 * automatically.
2696 */
c6dc6f63
AP		 2697static int cpu_x86_fill_model_id(char *str)
2698{
2699 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2700 int i;
2701
2702 for (i = 0; i < 3; i++) {
2703 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
2704 memcpy(str + i * 16 + 0, &eax, 4);
2705 memcpy(str + i * 16 + 4, &ebx, 4);
2706 memcpy(str + i * 16 + 8, &ecx, 4);
2707 memcpy(str + i * 16 + 12, &edx, 4);
2708 }
2709 return 0;
2710}
2711
c62f2630 2712static Property max_x86_cpu_properties[] = {
120eee7d 2713 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 2714 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 2715 DEFINE_PROP_END_OF_LIST()
2716};
2717
c62f2630 2718static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 2719{
84f1b92f 2720 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 2721 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 2722
f48c8837 2723 xcc->ordering = 9;
6e746f30 2724
ee465a3e 2725 xcc->model_description =
c62f2630 2726 "Enables all features supported by the accelerator in the current host";
d940ee9b 2727
c62f2630 2728 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 2729}
2730
0bacd8b3
EH		 2731static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
2732
c62f2630 2733static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 2734{
2735 X86CPU *cpu = X86_CPU(obj);
2736 CPUX86State *env = &cpu->env;
2737 KVMState *s = kvm_state;
d940ee9b 2738
4d1b279b
EH		 2739 /* We can't fill the features array here because we don't know yet if
2740 * "migratable" is true or false.
2741 */
44bd8e53 2742 cpu->max_features = true;
4d1b279b 2743
d6dcc558 2744 if (accel_uses_host_cpuid()) {
bd182022
EH		 2745 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
2746 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
2747 int family, model, stepping;
d6dcc558
SAGDR		 2748 X86CPUDefinition host_cpudef = { };
2749 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2750
2751 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
2752 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
0bacd8b3 2753
bd182022 2754 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 2755
bd182022 2756 cpu_x86_fill_model_id(model_id);
0bacd8b3 2757
bd182022
EH		 2758 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
2759 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
2760 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
2761 object_property_set_int(OBJECT(cpu), stepping, "stepping",
2762 &error_abort);
2763 object_property_set_str(OBJECT(cpu), model_id, "model-id",
2764 &error_abort);
0bacd8b3 2765
d6dcc558
SAGDR		 2766 if (kvm_enabled()) {
2767 env->cpuid_min_level =
2768 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
2769 env->cpuid_min_xlevel =
2770 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
2771 env->cpuid_min_xlevel2 =
2772 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2773 } else {
2774 env->cpuid_min_level =
2775 hvf_get_supported_cpuid(0x0, 0, R_EAX);
2776 env->cpuid_min_xlevel =
2777 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
2778 env->cpuid_min_xlevel2 =
2779 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
2780 }
40bfe48f
HZ		 2781
2782 if (lmce_supported()) {
2783 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
2784 }
6900d1cc
EH		 2785 } else {
2786 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
2787 "vendor", &error_abort);
2788 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
2789 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
2790 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
2791 object_property_set_str(OBJECT(cpu),
2792 "QEMU TCG CPU version " QEMU_HW_VERSION,
2793 "model-id", &error_abort);
e4356010 2794 }
2a573259 2795
d940ee9b 2796 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 2797}
2798
c62f2630
EH		 2799static const TypeInfo max_x86_cpu_type_info = {
2800 .name = X86_CPU_TYPE_NAME("max"),
2801 .parent = TYPE_X86_CPU,
2802 .instance_init = max_x86_cpu_initfn,
2803 .class_init = max_x86_cpu_class_init,
2804};
2805
d6dcc558 2806#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 2807static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
2808{
2809 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2810
d6dcc558 2811 xcc->host_cpuid_required = true;
c62f2630
EH		 2812 xcc->ordering = 8;
2813
d6dcc558
SAGDR		 2814 if (kvm_enabled()) {
2815 xcc->model_description =
2816 "KVM processor with all supported host features ";
2817 } else if (hvf_enabled()) {
2818 xcc->model_description =
2819 "HVF processor with all supported host features ";
2820 }
c62f2630
EH		 2821}
2822
d940ee9b
EH		 2823static const TypeInfo host_x86_cpu_type_info = {
2824 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 2825 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 2826 .class_init = host_x86_cpu_class_init,
2827};
2828
2829#endif
2830
8459e396 2831static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 2832{
8459e396 2833 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 2834 int i;
2835
857aee33 2836 for (i = 0; i < 32; ++i) {
72370dc1 2837 if ((1UL << i) & mask) {
bffd67b0 2838 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 2839 assert(reg);
8297be80
AF		 2840 warn_report("%s doesn't support requested feature: "
2841 "CPUID.%02XH:%s%s%s [bit %d]",
d6dcc558 2842 accel_uses_host_cpuid() ? "host" : "TCG",
8297be80
AF		 2843 f->cpuid_eax, reg,
2844 f->feat_names[i] ? "." : "",
2845 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 2846 }
857aee33 2847 }
c6dc6f63
AP		 2848}
2849
d7bce999
EB		 2850static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
2851 const char *name, void *opaque,
2852 Error **errp)
95b8519d
AF		 2853{
2854 X86CPU *cpu = X86_CPU(obj);
2855 CPUX86State *env = &cpu->env;
2856 int64_t value;
2857
2858 value = (env->cpuid_version >> 8) & 0xf;
2859 if (value == 0xf) {
2860 value += (env->cpuid_version >> 20) & 0xff;
2861 }
51e72bc1 2862 visit_type_int(v, name, &value, errp);
95b8519d
AF		 2863}
2864
d7bce999
EB		 2865static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
2866 const char *name, void *opaque,
2867 Error **errp)
ed5e1ec3 2868{
71ad61d3
AF		 2869 X86CPU *cpu = X86_CPU(obj);
2870 CPUX86State *env = &cpu->env;
2871 const int64_t min = 0;
2872 const int64_t max = 0xff + 0xf;
65cd9064 2873 Error *local_err = NULL;
71ad61d3
AF		 2874 int64_t value;
2875
51e72bc1 2876 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2877 if (local_err) {
2878 error_propagate(errp, local_err);
71ad61d3
AF		 2879 return;
2880 }
2881 if (value < min || value > max) {
c6bd8c70
MA		 2882 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2883 name ? name : "null", value, min, max);
71ad61d3
AF		 2884 return;
2885 }
2886
ed5e1ec3 2887 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 2888 if (value > 0x0f) {
2889 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 2890 } else {
71ad61d3 2891 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 2892 }
2893}
2894
d7bce999
EB		 2895static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
2896 const char *name, void *opaque,
2897 Error **errp)
67e30c83
AF		 2898{
2899 X86CPU *cpu = X86_CPU(obj);
2900 CPUX86State *env = &cpu->env;
2901 int64_t value;
2902
2903 value = (env->cpuid_version >> 4) & 0xf;
2904 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 2905 visit_type_int(v, name, &value, errp);
67e30c83
AF		 2906}
2907
d7bce999
EB		 2908static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
2909 const char *name, void *opaque,
2910 Error **errp)
b0704cbd 2911{
c5291a4f
AF		 2912 X86CPU *cpu = X86_CPU(obj);
2913 CPUX86State *env = &cpu->env;
2914 const int64_t min = 0;
2915 const int64_t max = 0xff;
65cd9064 2916 Error *local_err = NULL;
c5291a4f
AF		 2917 int64_t value;
2918
51e72bc1 2919 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2920 if (local_err) {
2921 error_propagate(errp, local_err);
c5291a4f
AF		 2922 return;
2923 }
2924 if (value < min || value > max) {
c6bd8c70
MA		 2925 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2926 name ? name : "null", value, min, max);
c5291a4f
AF		 2927 return;
2928 }
2929
b0704cbd 2930 env->cpuid_version &= ~0xf00f0;
c5291a4f 2931 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 2932}
2933
35112e41 2934static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 2935 const char *name, void *opaque,
35112e41
AF		 2936 Error **errp)
2937{
2938 X86CPU *cpu = X86_CPU(obj);
2939 CPUX86State *env = &cpu->env;
2940 int64_t value;
2941
2942 value = env->cpuid_version & 0xf;
51e72bc1 2943 visit_type_int(v, name, &value, errp);
35112e41
AF		 2944}
2945
036e2222 2946static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 2947 const char *name, void *opaque,
036e2222 2948 Error **errp)
38c3dc46 2949{
036e2222
AF		 2950 X86CPU *cpu = X86_CPU(obj);
2951 CPUX86State *env = &cpu->env;
2952 const int64_t min = 0;
2953 const int64_t max = 0xf;
65cd9064 2954 Error *local_err = NULL;
036e2222
AF		 2955 int64_t value;
2956
51e72bc1 2957 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2958 if (local_err) {
2959 error_propagate(errp, local_err);
036e2222
AF		 2960 return;
2961 }
2962 if (value < min || value > max) {
c6bd8c70
MA		 2963 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2964 name ? name : "null", value, min, max);
036e2222
AF		 2965 return;
2966 }
2967
38c3dc46 2968 env->cpuid_version &= ~0xf;
036e2222 2969 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 2970}
2971
d480e1af
AF		 2972static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
2973{
2974 X86CPU *cpu = X86_CPU(obj);
2975 CPUX86State *env = &cpu->env;
2976 char *value;
d480e1af 2977
e42a92ae 2978 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 2979 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
2980 env->cpuid_vendor3);
d480e1af
AF		 2981 return value;
2982}
2983
2984static void x86_cpuid_set_vendor(Object *obj, const char *value,
2985 Error **errp)
2986{
2987 X86CPU *cpu = X86_CPU(obj);
2988 CPUX86State *env = &cpu->env;
2989 int i;
2990
9df694ee 2991 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 2992 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 2993 return;
2994 }
2995
2996 env->cpuid_vendor1 = 0;
2997 env->cpuid_vendor2 = 0;
2998 env->cpuid_vendor3 = 0;
2999 for (i = 0; i < 4; i++) {
3000 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
3001 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
3002 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
3003 }
d480e1af
AF		 3004}
3005
63e886eb
AF		 3006static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
3007{
3008 X86CPU *cpu = X86_CPU(obj);
3009 CPUX86State *env = &cpu->env;
3010 char *value;
3011 int i;
3012
3013 value = g_malloc(48 + 1);
3014 for (i = 0; i < 48; i++) {
3015 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
3016 }
3017 value[48] = '\0';
3018 return value;
3019}
3020
938d4c25
AF		 3021static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
3022 Error **errp)
dcce6675 3023{
938d4c25
AF		 3024 X86CPU *cpu = X86_CPU(obj);
3025 CPUX86State *env = &cpu->env;
dcce6675
AF		 3026 int c, len, i;
3027
3028 if (model_id == NULL) {
3029 model_id = "";
3030 }
3031 len = strlen(model_id);
d0a6acf4 3032 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 3033 for (i = 0; i < 48; i++) {
3034 if (i >= len) {
3035 c = '\0';
3036 } else {
3037 c = (uint8_t)model_id[i];
3038 }
3039 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
3040 }
3041}
3042
d7bce999
EB		 3043static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
3044 void *opaque, Error **errp)
89e48965
AF		 3045{
3046 X86CPU *cpu = X86_CPU(obj);
3047 int64_t value;
3048
3049 value = cpu->env.tsc_khz * 1000;
51e72bc1 3050 visit_type_int(v, name, &value, errp);
89e48965
AF		 3051}
3052
d7bce999
EB		 3053static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
3054 void *opaque, Error **errp)
89e48965
AF		 3055{
3056 X86CPU *cpu = X86_CPU(obj);
3057 const int64_t min = 0;
2e84849a 3058 const int64_t max = INT64_MAX;
65cd9064 3059 Error *local_err = NULL;
89e48965
AF		 3060 int64_t value;
3061
51e72bc1 3062 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3063 if (local_err) {
3064 error_propagate(errp, local_err);
89e48965
AF		 3065 return;
3066 }
3067 if (value < min || value > max) {
c6bd8c70
MA		 3068 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3069 name ? name : "null", value, min, max);
89e48965
AF		 3070 return;
3071 }
3072
36f96c4b 3073 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 3074}
3075
7e5292b5 3076/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 3077static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
3078 const char *name, void *opaque,
3079 Error **errp)
8e8aba50 3080{
7e5292b5 3081 uint32_t *array = (uint32_t *)opaque;
8e8aba50 3082 FeatureWord w;
8e8aba50
EH		 3083 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
3084 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
3085 X86CPUFeatureWordInfoList *list = NULL;
3086
3087 for (w = 0; w < FEATURE_WORDS; w++) {
3088 FeatureWordInfo *wi = &feature_word_info[w];
3089 X86CPUFeatureWordInfo *qwi = &word_infos[w];
3090 qwi->cpuid_input_eax = wi->cpuid_eax;
3091 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
3092 qwi->cpuid_input_ecx = wi->cpuid_ecx;
3093 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 3094 qwi->features = array[w];
8e8aba50
EH		 3095
3096 /* List will be in reverse order, but order shouldn't matter */
3097 list_entries[w].next = list;
3098 list_entries[w].value = &word_infos[w];
3099 list = &list_entries[w];
3100 }
3101
6b62d961 3102 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 3103}
3104
d7bce999
EB		 3105static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3106 void *opaque, Error **errp)
c8f0f88e
IM		 3107{
3108 X86CPU *cpu = X86_CPU(obj);
3109 int64_t value = cpu->hyperv_spinlock_attempts;
3110
51e72bc1 3111 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 3112}
3113
d7bce999
EB		 3114static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3115 void *opaque, Error **errp)
c8f0f88e
IM		 3116{
3117 const int64_t min = 0xFFF;
3118 const int64_t max = UINT_MAX;
3119 X86CPU *cpu = X86_CPU(obj);
3120 Error *err = NULL;
3121 int64_t value;
3122
51e72bc1 3123 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 3124 if (err) {
3125 error_propagate(errp, err);
3126 return;
3127 }
3128
3129 if (value < min || value > max) {
3130 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 3131 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
3132 object_get_typename(obj), name ? name : "null",
3133 value, min, max);
c8f0f88e
IM		 3134 return;
3135 }
3136 cpu->hyperv_spinlock_attempts = value;
3137}
3138
1b6b7d10 3139static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 3140 .name = "int",
3141 .get = x86_get_hv_spinlocks,
3142 .set = x86_set_hv_spinlocks,
3143};
3144
72ac2e87
IM		 3145/* Convert all '_' in a feature string option name to '-', to make feature
3146 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3147 */
3148static inline void feat2prop(char *s)
3149{
3150 while ((s = strchr(s, '_'))) {
3151 *s = '-';
3152 }
3153}
3154
b54c9377
EH		 3155/* Return the feature property name for a feature flag bit */
3156static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
3157{
3158 /* XSAVE components are automatically enabled by other features,
3159 * so return the original feature name instead
3160 */
3161 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
3162 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
3163
3164 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
3165 x86_ext_save_areas[comp].bits) {
3166 w = x86_ext_save_areas[comp].feature;
3167 bitnr = ctz32(x86_ext_save_areas[comp].bits);
3168 }
3169 }
3170
3171 assert(bitnr < 32);
3172 assert(w < FEATURE_WORDS);
3173 return feature_word_info[w].feat_names[bitnr];
3174}
3175
dc15c051
IM		 3176/* Compatibily hack to maintain legacy +-feat semantic,
3177 * where +-feat overwrites any feature set by
3178 * feat=on|feat even if the later is parsed after +-feat
3179 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3180 */
2fae0d96 3181static GList *plus_features, *minus_features;
dc15c051 3182
83a00f60
EH		 3183static gint compare_string(gconstpointer a, gconstpointer b)
3184{
3185 return g_strcmp0(a, b);
3186}
3187
8f961357
EH		 3188/* Parse "+feature,-feature,feature=foo" CPU feature string
3189 */
62a48a2a 3190static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 3191 Error **errp)
8f961357 3192{
8f961357 3193 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 3194 static bool cpu_globals_initialized;
83a00f60 3195 bool ambiguous = false;
62a48a2a
IM		 3196
3197 if (cpu_globals_initialized) {
3198 return;
3199 }
3200 cpu_globals_initialized = true;
8f961357 3201
f6750e95
EH		 3202 if (!features) {
3203 return;
3204 }
3205
3206 for (featurestr = strtok(features, ",");
685479bd 3207 featurestr;
f6750e95
EH		 3208 featurestr = strtok(NULL, ",")) {
3209 const char *name;
3210 const char *val = NULL;
3211 char *eq = NULL;
cf2887c9 3212 char num[32];
62a48a2a 3213 GlobalProperty *prop;
c6dc6f63 3214
f6750e95 3215 /* Compatibility syntax: */
c6dc6f63 3216 if (featurestr[0] == '+') {
2fae0d96
EH		 3217 plus_features = g_list_append(plus_features,
3218 g_strdup(featurestr + 1));
f6750e95 3219 continue;
c6dc6f63 3220 } else if (featurestr[0] == '-') {
2fae0d96
EH		 3221 minus_features = g_list_append(minus_features,
3222 g_strdup(featurestr + 1));
f6750e95
EH		 3223 continue;
3224 }
3225
3226 eq = strchr(featurestr, '=');
3227 if (eq) {
3228 *eq++ = 0;
3229 val = eq;
c6dc6f63 3230 } else {
f6750e95 3231 val = "on";
a91987c2 3232 }
f6750e95
EH		 3233
3234 feat2prop(featurestr);
3235 name = featurestr;
3236
83a00f60 3237 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 3238 warn_report("Ambiguous CPU model string. "
3239 "Don't mix both \"+%s\" and \"%s=%s\"",
3240 name, name, val);
83a00f60
EH		 3241 ambiguous = true;
3242 }
3243 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 3244 warn_report("Ambiguous CPU model string. "
3245 "Don't mix both \"-%s\" and \"%s=%s\"",
3246 name, name, val);
83a00f60
EH		 3247 ambiguous = true;
3248 }
3249
f6750e95
EH		 3250 /* Special case: */
3251 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 3252 int ret;
f46bfdbf 3253 uint64_t tsc_freq;
f6750e95 3254
f17fd4fd 3255 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 3256 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 3257 error_setg(errp, "bad numerical value %s", val);
3258 return;
3259 }
3260 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3261 val = num;
3262 name = "tsc-frequency";
c6dc6f63 3263 }
f6750e95 3264
62a48a2a
IM		 3265 prop = g_new0(typeof(*prop), 1);
3266 prop->driver = typename;
3267 prop->property = g_strdup(name);
3268 prop->value = g_strdup(val);
3269 prop->errp = &error_fatal;
3270 qdev_prop_register_global(prop);
f6750e95
EH		 3271 }
3272
83a00f60 3273 if (ambiguous) {
3dc6f869
AF		 3274 warn_report("Compatibility of ambiguous CPU model "
3275 "strings won't be kept on future QEMU versions");
83a00f60 3276 }
c6dc6f63
AP		 3277}
3278
b8d834a0 3279static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 3280static int x86_cpu_filter_features(X86CPU *cpu);
3281
3282/* Check for missing features that may prevent the CPU class from
3283 * running using the current machine and accelerator.
3284 */
3285static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3286 strList **missing_feats)
3287{
3288 X86CPU *xc;
3289 FeatureWord w;
3290 Error *err = NULL;
3291 strList **next = missing_feats;
3292
d6dcc558 3293 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 3294 strList *new = g_new0(strList, 1);
3c254ab8 3295 new->value = g_strdup("kvm");
b54c9377
EH		 3296 *missing_feats = new;
3297 return;
3298 }
3299
3300 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3301
b8d834a0 3302 x86_cpu_expand_features(xc, &err);
b54c9377 3303 if (err) {
b8d834a0 3304 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 3305 * but in case it does, just report the model as not
3306 * runnable at all using the "type" property.
3307 */
3308 strList *new = g_new0(strList, 1);
3309 new->value = g_strdup("type");
3310 *next = new;
3311 next = &new->next;
3312 }
3313
3314 x86_cpu_filter_features(xc);
3315
3316 for (w = 0; w < FEATURE_WORDS; w++) {
3317 uint32_t filtered = xc->filtered_features[w];
3318 int i;
3319 for (i = 0; i < 32; i++) {
3320 if (filtered & (1UL << i)) {
3321 strList *new = g_new0(strList, 1);
3322 new->value = g_strdup(x86_cpu_feature_name(w, i));
3323 *next = new;
3324 next = &new->next;
3325 }
3326 }
3327 }
3328
3329 object_unref(OBJECT(xc));
3330}
3331
8c3329e5 3332/* Print all cpuid feature names in featureset
c6dc6f63 3333 */
8c3329e5 3334static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 3335{
8c3329e5
EH		 3336 int bit;
3337 bool first = true;
3338
3339 for (bit = 0; bit < 32; bit++) {
3340 if (featureset[bit]) {
3341 print(f, "%s%s", first ? "" : " ", featureset[bit]);
3342 first = false;
c6dc6f63 3343 }
8c3329e5 3344 }
c6dc6f63
AP		 3345}
3346
f48c8837 3347/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 3348static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3349{
3350 ObjectClass *class_a = (ObjectClass *)a;
3351 ObjectClass *class_b = (ObjectClass *)b;
3352 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3353 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b
DB		 3354 char *name_a, *name_b;
3355 int ret;
ee465a3e 3356
f48c8837 3357 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 3358 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 3359 } else {
c7dbff4b
DB		 3360 name_a = x86_cpu_class_get_model_name(cc_a);
3361 name_b = x86_cpu_class_get_model_name(cc_b);
3362 ret = strcmp(name_a, name_b);
3363 g_free(name_a);
3364 g_free(name_b);
ee465a3e 3365 }
c7dbff4b 3366 return ret;
ee465a3e
EH		 3367}
3368
3369static GSList *get_sorted_cpu_model_list(void)
3370{
3371 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3372 list = g_slist_sort(list, x86_cpu_list_compare);
3373 return list;
3374}
3375
3376static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3377{
3378 ObjectClass *oc = data;
3379 X86CPUClass *cc = X86_CPU_CLASS(oc);
3380 CPUListState *s = user_data;
3381 char *name = x86_cpu_class_get_model_name(cc);
3382 const char *desc = cc->model_description;
0bacd8b3 3383 if (!desc && cc->cpu_def) {
ee465a3e
EH		 3384 desc = cc->cpu_def->model_id;
3385 }
3386
081492ca 3387 (*s->cpu_fprintf)(s->file, "x86 %-20s %-48s\n",
ee465a3e
EH		 3388 name, desc);
3389 g_free(name);
3390}
3391
3392/* list available CPU models and flags */
e916cbf8 3393void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 3394{
7fc9b714 3395 int i;
ee465a3e
EH		 3396 CPUListState s = {
3397 .file = f,
3398 .cpu_fprintf = cpu_fprintf,
3399 };
3400 GSList *list;
c6dc6f63 3401
ee465a3e
EH		 3402 (*cpu_fprintf)(f, "Available CPUs:\n");
3403 list = get_sorted_cpu_model_list();
3404 g_slist_foreach(list, x86_cpu_list_entry, &s);
3405 g_slist_free(list);
21ad7789 3406
6cdf8854 3407 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 3408 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3409 FeatureWordInfo *fw = &feature_word_info[i];
3410
8c3329e5
EH		 3411 (*cpu_fprintf)(f, " ");
3412 listflags(f, cpu_fprintf, fw->feat_names);
3413 (*cpu_fprintf)(f, "\n");
3af60be2 3414 }
c6dc6f63
AP		 3415}
3416
ee465a3e
EH		 3417static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3418{
3419 ObjectClass *oc = data;
3420 X86CPUClass *cc = X86_CPU_CLASS(oc);
3421 CpuDefinitionInfoList **cpu_list = user_data;
3422 CpuDefinitionInfoList *entry;
3423 CpuDefinitionInfo *info;
3424
3425 info = g_malloc0(sizeof(*info));
3426 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 3427 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3428 info->has_unavailable_features = true;
8ed877b7 3429 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 3430 info->migration_safe = cc->migration_safe;
3431 info->has_migration_safe = true;
5adbed30 3432 info->q_static = cc->static_model;
ee465a3e
EH		 3433
3434 entry = g_malloc0(sizeof(*entry));
3435 entry->value = info;
3436 entry->next = *cpu_list;
3437 *cpu_list = entry;
3438}
3439
76b64a7a 3440CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 3441{
3442 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 3443 GSList *list = get_sorted_cpu_model_list();
3444 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3445 g_slist_free(list);
e3966126
AL		 3446 return cpu_list;
3447}
3448
84f1b92f
EH		 3449static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3450 bool migratable_only)
27418adf
EH		 3451{
3452 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 3453 uint32_t r;
27418adf 3454
fefb41bf 3455 if (kvm_enabled()) {
84f1b92f
EH		 3456 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
3457 wi->cpuid_ecx,
3458 wi->cpuid_reg);
d6dcc558
SAGDR		 3459 } else if (hvf_enabled()) {
3460 r = hvf_get_supported_cpuid(wi->cpuid_eax,
3461 wi->cpuid_ecx,
3462 wi->cpuid_reg);
fefb41bf 3463 } else if (tcg_enabled()) {
84f1b92f 3464 r = wi->tcg_features;
fefb41bf
EH		 3465 } else {
3466 return ~0;
3467 }
84f1b92f
EH		 3468 if (migratable_only) {
3469 r &= x86_cpu_get_migratable_flags(w);
3470 }
3471 return r;
27418adf
EH		 3472}
3473
8ca30e86
EH		 3474static void x86_cpu_report_filtered_features(X86CPU *cpu)
3475{
3476 FeatureWord w;
3477
3478 for (w = 0; w < FEATURE_WORDS; w++) {
3479 report_unavailable_features(w, cpu->filtered_features[w]);
3480 }
3481}
3482
5114e842
EH		 3483static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3484{
3485 PropValue *pv;
3486 for (pv = props; pv->prop; pv++) {
3487 if (!pv->value) {
3488 continue;
3489 }
3490 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3491 &error_abort);
3492 }
3493}
3494
f99fd7ca 3495/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 3496 */
d940ee9b 3497static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 3498{
61dcd775 3499 CPUX86State *env = &cpu->env;
74f54bc4
EH		 3500 const char *vendor;
3501 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 3502 FeatureWord w;
c6dc6f63 3503
f99fd7ca
EH		 3504 /*NOTE: any property set by this function should be returned by
3505 * x86_cpu_static_props(), so static expansion of
3506 * query-cpu-model-expansion is always complete.
3507 */
3508
c39c0edf 3509 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 3510 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3511 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 3512
2d64255b
AF		 3513 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3514 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3515 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 3516 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 3517 for (w = 0; w < FEATURE_WORDS; w++) {
3518 env->features[w] = def->features[w];
3519 }
82beb536 3520
a9f27ea9
EH		 3521 /* legacy-cache defaults to 'off' if CPU model provides cache info */
3522 cpu->legacy_cache = !def->cache_info;
ab8f992e 3523
9576de75 3524 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 3525 /* TODO: in-kernel irqchip for hvf */
82beb536 3526 if (kvm_enabled()) {
492a4c94
LT		 3527 if (!kvm_irqchip_in_kernel()) {
3528 x86_cpu_change_kvm_default("x2apic", "off");
3529 }
3530
5114e842 3531 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 3532 } else if (tcg_enabled()) {
3533 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 3534 }
5fcca9ff 3535
82beb536 3536 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 3537
3538 /* sysenter isn't supported in compatibility mode on AMD,
3539 * syscall isn't supported in compatibility mode on Intel.
3540 * Normally we advertise the actual CPU vendor, but you can
3541 * override this using the 'vendor' property if you want to use
3542 * KVM's sysenter/syscall emulation in compatibility mode and
3543 * when doing cross vendor migration
3544 */
74f54bc4 3545 vendor = def->vendor;
d6dcc558 3546 if (accel_uses_host_cpuid()) {
7c08db30
EH		 3547 uint32_t ebx = 0, ecx = 0, edx = 0;
3548 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3549 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3550 vendor = host_vendor;
3551 }
3552
3553 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3554
c6dc6f63
AP		 3555}
3556
f99fd7ca
EH		 3557/* Return a QDict containing keys for all properties that can be included
3558 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3559 * must be included in the dictionary.
3560 */
3561static QDict *x86_cpu_static_props(void)
3562{
3563 FeatureWord w;
3564 int i;
3565 static const char *props[] = {
3566 "min-level",
3567 "min-xlevel",
3568 "family",
3569 "model",
3570 "stepping",
3571 "model-id",
3572 "vendor",
3573 "lmce",
3574 NULL,
3575 };
3576 static QDict *d;
3577
3578 if (d) {
3579 return d;
3580 }
3581
3582 d = qdict_new();
3583 for (i = 0; props[i]; i++) {
0f9afc2a 3584 qdict_put_null(d, props[i]);
f99fd7ca
EH		 3585 }
3586
3587 for (w = 0; w < FEATURE_WORDS; w++) {
3588 FeatureWordInfo *fi = &feature_word_info[w];
3589 int bit;
3590 for (bit = 0; bit < 32; bit++) {
3591 if (!fi->feat_names[bit]) {
3592 continue;
3593 }
0f9afc2a 3594 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 3595 }
3596 }
3597
3598 return d;
3599}
3600
3601/* Add an entry to @props dict, with the value for property. */
3602static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
3603{
3604 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
3605 &error_abort);
3606
3607 qdict_put_obj(props, prop, value);
3608}
3609
3610/* Convert CPU model data from X86CPU object to a property dictionary
3611 * that can recreate exactly the same CPU model.
3612 */
3613static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
3614{
3615 QDict *sprops = x86_cpu_static_props();
3616 const QDictEntry *e;
3617
3618 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
3619 const char *prop = qdict_entry_key(e);
3620 x86_cpu_expand_prop(cpu, props, prop);
3621 }
3622}
3623
b8097deb
EH		 3624/* Convert CPU model data from X86CPU object to a property dictionary
3625 * that can recreate exactly the same CPU model, including every
3626 * writeable QOM property.
3627 */
3628static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
3629{
3630 ObjectPropertyIterator iter;
3631 ObjectProperty *prop;
3632
3633 object_property_iter_init(&iter, OBJECT(cpu));
3634 while ((prop = object_property_iter_next(&iter))) {
3635 /* skip read-only or write-only properties */
3636 if (!prop->get || !prop->set) {
3637 continue;
3638 }
3639
3640 /* "hotplugged" is the only property that is configurable
3641 * on the command-line but will be set differently on CPUs
3642 * created using "-cpu ... -smp ..." and by CPUs created
3643 * on the fly by x86_cpu_from_model() for querying. Skip it.
3644 */
3645 if (!strcmp(prop->name, "hotplugged")) {
3646 continue;
3647 }
3648 x86_cpu_expand_prop(cpu, props, prop->name);
3649 }
3650}
3651
f99fd7ca
EH		 3652static void object_apply_props(Object *obj, QDict *props, Error **errp)
3653{
3654 const QDictEntry *prop;
3655 Error *err = NULL;
3656
3657 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
3658 object_property_set_qobject(obj, qdict_entry_value(prop),
3659 qdict_entry_key(prop), &err);
3660 if (err) {
3661 break;
3662 }
3663 }
3664
3665 error_propagate(errp, err);
3666}
3667
3668/* Create X86CPU object according to model+props specification */
3669static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
3670{
3671 X86CPU *xc = NULL;
3672 X86CPUClass *xcc;
3673 Error *err = NULL;
3674
3675 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
3676 if (xcc == NULL) {
3677 error_setg(&err, "CPU model '%s' not found", model);
3678 goto out;
3679 }
3680
3681 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3682 if (props) {
3683 object_apply_props(OBJECT(xc), props, &err);
3684 if (err) {
3685 goto out;
3686 }
3687 }
3688
3689 x86_cpu_expand_features(xc, &err);
3690 if (err) {
3691 goto out;
3692 }
3693
3694out:
3695 if (err) {
3696 error_propagate(errp, err);
3697 object_unref(OBJECT(xc));
3698 xc = NULL;
3699 }
3700 return xc;
3701}
3702
3703CpuModelExpansionInfo *
3704arch_query_cpu_model_expansion(CpuModelExpansionType type,
3705 CpuModelInfo *model,
3706 Error **errp)
3707{
3708 X86CPU *xc = NULL;
3709 Error *err = NULL;
3710 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
3711 QDict *props = NULL;
3712 const char *base_name;
3713
3714 xc = x86_cpu_from_model(model->name,
3715 model->has_props ?
7dc847eb 3716 qobject_to(QDict, model->props) :
f99fd7ca
EH		 3717 NULL, &err);
3718 if (err) {
3719 goto out;
3720 }
3721
b8097deb 3722 props = qdict_new();
f99fd7ca
EH		 3723
3724 switch (type) {
3725 case CPU_MODEL_EXPANSION_TYPE_STATIC:
3726 /* Static expansion will be based on "base" only */
3727 base_name = "base";
b8097deb 3728 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 3729 break;
3730 case CPU_MODEL_EXPANSION_TYPE_FULL:
3731 /* As we don't return every single property, full expansion needs
3732 * to keep the original model name+props, and add extra
3733 * properties on top of that.
3734 */
3735 base_name = model->name;
b8097deb 3736 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 3737 break;
3738 default:
3739 error_setg(&err, "Unsupportted expansion type");
3740 goto out;
3741 }
3742
3743 if (!props) {
3744 props = qdict_new();
3745 }
3746 x86_cpu_to_dict(xc, props);
3747
3748 ret->model = g_new0(CpuModelInfo, 1);
3749 ret->model->name = g_strdup(base_name);
3750 ret->model->props = QOBJECT(props);
3751 ret->model->has_props = true;
3752
3753out:
3754 object_unref(OBJECT(xc));
3755 if (err) {
3756 error_propagate(errp, err);
3757 qapi_free_CpuModelExpansionInfo(ret);
3758 ret = NULL;
3759 }
3760 return ret;
3761}
3762
00fcd100
AB		 3763static gchar *x86_gdb_arch_name(CPUState *cs)
3764{
3765#ifdef TARGET_X86_64
3766 return g_strdup("i386:x86-64");
3767#else
3768 return g_strdup("i386");
3769#endif
3770}
3771
d940ee9b
EH		 3772static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
3773{
3774 X86CPUDefinition *cpudef = data;
3775 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3776
3777 xcc->cpu_def = cpudef;
bd72159d 3778 xcc->migration_safe = true;
d940ee9b
EH		 3779}
3780
3781static void x86_register_cpudef_type(X86CPUDefinition *def)
3782{
3783 char *typename = x86_cpu_type_name(def->name);
3784 TypeInfo ti = {
3785 .name = typename,
3786 .parent = TYPE_X86_CPU,
3787 .class_init = x86_cpu_cpudef_class_init,
3788 .class_data = def,
3789 };
3790
2a923a29
EH		 3791 /* AMD aliases are handled at runtime based on CPUID vendor, so
3792 * they shouldn't be set on the CPU model table.
3793 */
3794 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 3795 /* catch mistakes instead of silently truncating model_id when too long */
3796 assert(def->model_id && strlen(def->model_id) <= 48);
3797
2a923a29 3798
d940ee9b
EH		 3799 type_register(&ti);
3800 g_free(typename);
3801}
3802
c6dc6f63 3803#if !defined(CONFIG_USER_ONLY)
c6dc6f63 3804
0e26b7b8
BS		 3805void cpu_clear_apic_feature(CPUX86State *env)
3806{
0514ef2f 3807 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 3808}
3809
c6dc6f63
AP		 3810#endif /* !CONFIG_USER_ONLY */
3811
c6dc6f63
AP		 3812void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
3813 uint32_t *eax, uint32_t *ebx,
3814 uint32_t *ecx, uint32_t *edx)
3815{
a60f24b5
AF		 3816 X86CPU *cpu = x86_env_get_cpu(env);
3817 CPUState *cs = CPU(cpu);
14c985cf 3818 uint32_t pkg_offset;
4ed3d478 3819 uint32_t limit;
1ce36bfe 3820 uint32_t signature[3];
a60f24b5 3821
4ed3d478
DB		 3822 /* Calculate & apply limits for different index ranges */
3823 if (index >= 0xC0000000) {
3824 limit = env->cpuid_xlevel2;
3825 } else if (index >= 0x80000000) {
3826 limit = env->cpuid_xlevel;
1ce36bfe
DB		 3827 } else if (index >= 0x40000000) {
3828 limit = 0x40000001;
c6dc6f63 3829 } else {
4ed3d478
DB		 3830 limit = env->cpuid_level;
3831 }
3832
3833 if (index > limit) {
3834 /* Intel documentation states that invalid EAX input will
3835 * return the same information as EAX=cpuid_level
3836 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
3837 */
3838 index = env->cpuid_level;
c6dc6f63
AP		 3839 }
3840
3841 switch(index) {
3842 case 0:
3843 *eax = env->cpuid_level;
5eb2f7a4
EH		 3844 *ebx = env->cpuid_vendor1;
3845 *edx = env->cpuid_vendor2;
3846 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 3847 break;
3848 case 1:
3849 *eax = env->cpuid_version;
7e72a45c
EH		 3850 *ebx = (cpu->apic_id << 24) |
3851 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 3852 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 3853 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
3854 *ecx |= CPUID_EXT_OSXSAVE;
3855 }
0514ef2f 3856 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 3857 if (cs->nr_cores * cs->nr_threads > 1) {
3858 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 3859 *edx |= CPUID_HT;
c6dc6f63
AP		 3860 }
3861 break;
3862 case 2:
3863 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 3864 if (cpu->cache_info_passthrough) {
3865 host_cpuid(index, 0, eax, ebx, ecx, edx);
3866 break;
3867 }
5e891bf8 3868 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 3869 *ebx = 0;
14c985cf
LM		 3870 if (!cpu->enable_l3_cache) {
3871 *ecx = 0;
3872 } else {
a9f27ea9 3873 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 3874 }
a9f27ea9
EH		 3875 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
3876 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
3877 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 3878 break;
3879 case 4:
3880 /* cache info: needed for Core compatibility */
787aaf57
BC		 3881 if (cpu->cache_info_passthrough) {
3882 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 3883 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 3884 *eax &= ~0xFC000000;
7e3482f8
EH		 3885 if ((*eax & 31) && cs->nr_cores > 1) {
3886 *eax |= (cs->nr_cores - 1) << 26;
3887 }
c6dc6f63 3888 } else {
2f7a21c4 3889 *eax = 0;
76c2975a 3890 switch (count) {
c6dc6f63 3891 case 0: /* L1 dcache info */
a9f27ea9
EH		 3892 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
3893 1, cs->nr_cores,
7e3482f8 3894 eax, ebx, ecx, edx);
c6dc6f63
AP		 3895 break;
3896 case 1: /* L1 icache info */
a9f27ea9
EH		 3897 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
3898 1, cs->nr_cores,
7e3482f8 3899 eax, ebx, ecx, edx);
c6dc6f63
AP		 3900 break;
3901 case 2: /* L2 cache info */
a9f27ea9
EH		 3902 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
3903 cs->nr_threads, cs->nr_cores,
7e3482f8 3904 eax, ebx, ecx, edx);
c6dc6f63 3905 break;
14c985cf 3906 case 3: /* L3 cache info */
7e3482f8
EH		 3907 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
3908 if (cpu->enable_l3_cache) {
a9f27ea9
EH		 3909 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
3910 (1 << pkg_offset), cs->nr_cores,
7e3482f8 3911 eax, ebx, ecx, edx);
14c985cf
LM		 3912 break;
3913 }
7e3482f8 3914 /* fall through */
c6dc6f63 3915 default: /* end of info */
7e3482f8 3916 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 3917 break;
76c2975a
PB		 3918 }
3919 }
c6dc6f63
AP		 3920 break;
3921 case 5:
3922 /* mwait info: needed for Core compatibility */
3923 *eax = 0; /* Smallest monitor-line size in bytes */
3924 *ebx = 0; /* Largest monitor-line size in bytes */
3925 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
3926 *edx = 0;
3927 break;
3928 case 6:
3929 /* Thermal and Power Leaf */
28b8e4d0 3930 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 3931 *ebx = 0;
3932 *ecx = 0;
3933 *edx = 0;
3934 break;
f7911686 3935 case 7:
13526728
EH		 3936 /* Structured Extended Feature Flags Enumeration Leaf */
3937 if (count == 0) {
3938 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 3939 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 3940 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 3941 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
3942 *ecx |= CPUID_7_0_ECX_OSPKE;
3943 }
95ea69fb 3944 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 3945 } else {
3946 *eax = 0;
3947 *ebx = 0;
3948 *ecx = 0;
3949 *edx = 0;
3950 }
3951 break;
c6dc6f63
AP		 3952 case 9:
3953 /* Direct Cache Access Information Leaf */
3954 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
3955 *ebx = 0;
3956 *ecx = 0;
3957 *edx = 0;
3958 break;
3959 case 0xA:
3960 /* Architectural Performance Monitoring Leaf */
9337e3b6 3961 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 3962 KVMState *s = cs->kvm_state;
a0fa8208
GN		 3963
3964 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
3965 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
3966 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
3967 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 3968 } else if (hvf_enabled() && cpu->enable_pmu) {
3969 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
3970 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
3971 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
3972 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 3973 } else {
3974 *eax = 0;
3975 *ebx = 0;
3976 *ecx = 0;
3977 *edx = 0;
3978 }
c6dc6f63 3979 break;
5232d00a
RK		 3980 case 0xB:
3981 /* Extended Topology Enumeration Leaf */
3982 if (!cpu->enable_cpuid_0xb) {
3983 *eax = *ebx = *ecx = *edx = 0;
3984 break;
3985 }
3986
3987 *ecx = count & 0xff;
3988 *edx = cpu->apic_id;
3989
3990 switch (count) {
3991 case 0:
eab60fb9
MAL		 3992 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
3993 *ebx = cs->nr_threads;
5232d00a
RK		 3994 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
3995 break;
3996 case 1:
eab60fb9
MAL		 3997 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
3998 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 3999 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
4000 break;
4001 default:
4002 *eax = 0;
4003 *ebx = 0;
4004 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
4005 }
4006
4007 assert(!(*eax & ~0x1f));
4008 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
4009 break;
2560f19f 4010 case 0xD: {
51e49430 4011 /* Processor Extended State */
2560f19f
PB		 4012 *eax = 0;
4013 *ebx = 0;
4014 *ecx = 0;
4015 *edx = 0;
19dc85db 4016 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 4017 break;
4018 }
4928cd6d 4019
2560f19f 4020 if (count == 0) {
96193c22
EH		 4021 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
4022 *eax = env->features[FEAT_XSAVE_COMP_LO];
4023 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 4024 *ebx = *ecx;
4025 } else if (count == 1) {
0bb0b2d2 4026 *eax = env->features[FEAT_XSAVE];
f4f1110e 4027 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 4028 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
4029 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 4030 *eax = esa->size;
4031 *ebx = esa->offset;
2560f19f 4032 }
51e49430
SY		 4033 }
4034 break;
2560f19f 4035 }
e37a5c7f
CP		 4036 case 0x14: {
4037 /* Intel Processor Trace Enumeration */
4038 *eax = 0;
4039 *ebx = 0;
4040 *ecx = 0;
4041 *edx = 0;
4042 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
4043 !kvm_enabled()) {
4044 break;
4045 }
4046
4047 if (count == 0) {
4048 *eax = INTEL_PT_MAX_SUBLEAF;
4049 *ebx = INTEL_PT_MINIMAL_EBX;
4050 *ecx = INTEL_PT_MINIMAL_ECX;
4051 } else if (count == 1) {
4052 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
4053 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
4054 }
4055 break;
4056 }
1ce36bfe
DB		 4057 case 0x40000000:
4058 /*
4059 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4060 * set here, but we restrict to TCG none the less.
4061 */
4062 if (tcg_enabled() && cpu->expose_tcg) {
4063 memcpy(signature, "TCGTCGTCGTCG", 12);
4064 *eax = 0x40000001;
4065 *ebx = signature[0];
4066 *ecx = signature[1];
4067 *edx = signature[2];
4068 } else {
4069 *eax = 0;
4070 *ebx = 0;
4071 *ecx = 0;
4072 *edx = 0;
4073 }
4074 break;
4075 case 0x40000001:
4076 *eax = 0;
4077 *ebx = 0;
4078 *ecx = 0;
4079 *edx = 0;
4080 break;
c6dc6f63
AP		 4081 case 0x80000000:
4082 *eax = env->cpuid_xlevel;
4083 *ebx = env->cpuid_vendor1;
4084 *edx = env->cpuid_vendor2;
4085 *ecx = env->cpuid_vendor3;
4086 break;
4087 case 0x80000001:
4088 *eax = env->cpuid_version;
4089 *ebx = 0;
0514ef2f
EH		 4090 *ecx = env->features[FEAT_8000_0001_ECX];
4091 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 4092
4093 /* The Linux kernel checks for the CMPLegacy bit and
4094 * discards multiple thread information if it is set.
cb8d4c8f 4095 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 4096 */
ce3960eb 4097 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 4098 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
4099 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
4100 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 4101 *ecx |= 1 << 1; /* CmpLegacy bit */
4102 }
4103 }
c6dc6f63
AP		 4104 break;
4105 case 0x80000002:
4106 case 0x80000003:
4107 case 0x80000004:
4108 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
4109 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
4110 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
4111 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
4112 break;
4113 case 0x80000005:
4114 /* cache info (L1 cache) */
787aaf57
BC		 4115 if (cpu->cache_info_passthrough) {
4116 host_cpuid(index, 0, eax, ebx, ecx, edx);
4117 break;
4118 }
5e891bf8
EH		 4119 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
4120 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
4121 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
4122 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4123 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
4124 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 4125 break;
4126 case 0x80000006:
4127 /* cache info (L2 cache) */
787aaf57
BC		 4128 if (cpu->cache_info_passthrough) {
4129 host_cpuid(index, 0, eax, ebx, ecx, edx);
4130 break;
4131 }
5e891bf8
EH		 4132 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
4133 (L2_DTLB_2M_ENTRIES << 16) | \
4134 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
4135 (L2_ITLB_2M_ENTRIES);
4136 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
4137 (L2_DTLB_4K_ENTRIES << 16) | \
4138 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
4139 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4140 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
4141 cpu->enable_l3_cache ?
4142 env->cache_info_amd.l3_cache : NULL,
4143 ecx, edx);
c6dc6f63 4144 break;
303752a9
MT		 4145 case 0x80000007:
4146 *eax = 0;
4147 *ebx = 0;
4148 *ecx = 0;
4149 *edx = env->features[FEAT_8000_0007_EDX];
4150 break;
c6dc6f63
AP		 4151 case 0x80000008:
4152 /* virtual & phys address size in low 2 bytes. */
0514ef2f 4153 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 4154 /* 64 bit processor */
4155 *eax = cpu->phys_bits; /* configurable physical bits */
4156 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
4157 *eax |= 0x00003900; /* 57 bits virtual */
4158 } else {
4159 *eax |= 0x00003000; /* 48 bits virtual */
4160 }
c6dc6f63 4161 } else {
af45907a 4162 *eax = cpu->phys_bits;
c6dc6f63 4163 }
1b3420e1 4164 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 4165 *ecx = 0;
4166 *edx = 0;
ce3960eb
AF		 4167 if (cs->nr_cores * cs->nr_threads > 1) {
4168 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 4169 }
4170 break;
4171 case 0x8000000A:
0514ef2f 4172 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 4173 *eax = 0x00000001; /* SVM Revision */
4174 *ebx = 0x00000010; /* nr of ASIDs */
4175 *ecx = 0;
0514ef2f 4176 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 4177 } else {
4178 *eax = 0;
4179 *ebx = 0;
4180 *ecx = 0;
4181 *edx = 0;
4182 }
c6dc6f63 4183 break;
8f4202fb
BM		 4184 case 0x8000001D:
4185 *eax = 0;
4186 switch (count) {
4187 case 0: /* L1 dcache info */
4188 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
4189 eax, ebx, ecx, edx);
4190 break;
4191 case 1: /* L1 icache info */
4192 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
4193 eax, ebx, ecx, edx);
4194 break;
4195 case 2: /* L2 cache info */
4196 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
4197 eax, ebx, ecx, edx);
4198 break;
4199 case 3: /* L3 cache info */
4200 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
4201 eax, ebx, ecx, edx);
4202 break;
4203 default: /* end of info */
4204 *eax = *ebx = *ecx = *edx = 0;
4205 break;
4206 }
4207 break;
ed78467a
BM		 4208 case 0x8000001E:
4209 assert(cpu->core_id <= 255);
4210 encode_topo_cpuid8000001e(cs, cpu,
4211 eax, ebx, ecx, edx);
4212 break;
b3baa152
BW		 4213 case 0xC0000000:
4214 *eax = env->cpuid_xlevel2;
4215 *ebx = 0;
4216 *ecx = 0;
4217 *edx = 0;
4218 break;
4219 case 0xC0000001:
4220 /* Support for VIA CPU's CPUID instruction */
4221 *eax = env->cpuid_version;
4222 *ebx = 0;
4223 *ecx = 0;
0514ef2f 4224 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 4225 break;
4226 case 0xC0000002:
4227 case 0xC0000003:
4228 case 0xC0000004:
4229 /* Reserved for the future, and now filled with zero */
4230 *eax = 0;
4231 *ebx = 0;
4232 *ecx = 0;
4233 *edx = 0;
4234 break;
6cb8f2a6
BS		 4235 case 0x8000001F:
4236 *eax = sev_enabled() ? 0x2 : 0;
4237 *ebx = sev_get_cbit_position();
4238 *ebx |= sev_get_reduced_phys_bits() << 6;
4239 *ecx = 0;
4240 *edx = 0;
4241 break;
c6dc6f63
AP		 4242 default:
4243 /* reserved values: zero */
4244 *eax = 0;
4245 *ebx = 0;
4246 *ecx = 0;
4247 *edx = 0;
4248 break;
4249 }
4250}
5fd2087a
AF		 4251
4252/* CPUClass::reset() */
4253static void x86_cpu_reset(CPUState *s)
4254{
4255 X86CPU *cpu = X86_CPU(s);
4256 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
4257 CPUX86State *env = &cpu->env;
a114d25d
RH		 4258 target_ulong cr4;
4259 uint64_t xcr0;
c1958aea
AF		 4260 int i;
4261
5fd2087a
AF		 4262 xcc->parent_reset(s);
4263
5e992a8e 4264 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 4265
c1958aea
AF		 4266 env->old_exception = -1;
4267
4268 /* init to reset state */
4269
c1958aea
AF		 4270 env->hflags2 |= HF2_GIF_MASK;
4271
4272 cpu_x86_update_cr0(env, 0x60000010);
4273 env->a20_mask = ~0x0;
4274 env->smbase = 0x30000;
e13713db 4275 env->msr_smi_count = 0;
c1958aea
AF		 4276
4277 env->idt.limit = 0xffff;
4278 env->gdt.limit = 0xffff;
4279 env->ldt.limit = 0xffff;
4280 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4281 env->tr.limit = 0xffff;
4282 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4283
4284 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4285 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4286 DESC_R_MASK | DESC_A_MASK);
4287 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4288 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4289 DESC_A_MASK);
4290 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4291 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4292 DESC_A_MASK);
4293 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4294 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4295 DESC_A_MASK);
4296 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4297 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4298 DESC_A_MASK);
4299 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4300 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4301 DESC_A_MASK);
4302
4303 env->eip = 0xfff0;
4304 env->regs[R_EDX] = env->cpuid_version;
4305
4306 env->eflags = 0x2;
4307
4308 /* FPU init */
4309 for (i = 0; i < 8; i++) {
4310 env->fptags[i] = 1;
4311 }
5bde1407 4312 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 4313
4314 env->mxcsr = 0x1f80;
a114d25d
RH		 4315 /* All units are in INIT state. */
4316 env->xstate_bv = 0;
c1958aea
AF		 4317
4318 env->pat = 0x0007040600070406ULL;
4319 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4320
4321 memset(env->dr, 0, sizeof(env->dr));
4322 env->dr[6] = DR6_FIXED_1;
4323 env->dr[7] = DR7_FIXED_1;
b3310ab3 4324 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 4325 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 4326
a114d25d 4327 cr4 = 0;
cfc3b074 4328 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 4329
4330#ifdef CONFIG_USER_ONLY
4331 /* Enable all the features for user-mode. */
4332 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 4333 xcr0 |= XSTATE_SSE_MASK;
a114d25d 4334 }
0f70ed47
PB		 4335 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4336 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 4337 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 4338 xcr0 |= 1ull << i;
4339 }
a114d25d 4340 }
0f70ed47 4341
a114d25d
RH		 4342 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4343 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4344 }
07929f2a
RH		 4345 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4346 cr4 |= CR4_FSGSBASE_MASK;
4347 }
a114d25d
RH		 4348#endif
4349
4350 env->xcr0 = xcr0;
4351 cpu_x86_update_cr4(env, cr4);
0522604b 4352
9db2efd9
AW		 4353 /*
4354 * SDM 11.11.5 requires:
4355 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4356 * - IA32_MTRR_PHYSMASKn.V = 0
4357 * All other bits are undefined. For simplification, zero it all.
4358 */
4359 env->mtrr_deftype = 0;
4360 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4361 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4362
b7394c83
SAGDR		 4363 env->interrupt_injected = -1;
4364 env->exception_injected = -1;
4365 env->nmi_injected = false;
dd673288
IM		 4366#if !defined(CONFIG_USER_ONLY)
4367 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 4368 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 4369
259186a7 4370 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 4371
4372 if (kvm_enabled()) {
4373 kvm_arch_reset_vcpu(cpu);
4374 }
d6dcc558
SAGDR		 4375 else if (hvf_enabled()) {
4376 hvf_reset_vcpu(s);
4377 }
dd673288 4378#endif
5fd2087a
AF		 4379}
4380
dd673288
IM		 4381#ifndef CONFIG_USER_ONLY
4382bool cpu_is_bsp(X86CPU *cpu)
4383{
02e51483 4384 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 4385}
65dee380
IM		 4386
4387/* TODO: remove me, when reset over QOM tree is implemented */
4388static void x86_cpu_machine_reset_cb(void *opaque)
4389{
4390 X86CPU *cpu = opaque;
4391 cpu_reset(CPU(cpu));
4392}
dd673288
IM		 4393#endif
4394
de024815
AF		 4395static void mce_init(X86CPU *cpu)
4396{
4397 CPUX86State *cenv = &cpu->env;
4398 unsigned int bank;
4399
4400 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 4401 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 4402 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 4403 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4404 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 4405 cenv->mcg_ctl = ~(uint64_t)0;
4406 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4407 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4408 }
4409 }
4410}
4411
bdeec802 4412#ifndef CONFIG_USER_ONLY
2f114315 4413APICCommonClass *apic_get_class(void)
bdeec802 4414{
bdeec802
IM		 4415 const char *apic_type = "apic";
4416
d6dcc558 4417 /* TODO: in-kernel irqchip for hvf */
15eafc2e 4418 if (kvm_apic_in_kernel()) {
bdeec802
IM		 4419 apic_type = "kvm-apic";
4420 } else if (xen_enabled()) {
4421 apic_type = "xen-apic";
4422 }
4423
2f114315
RK		 4424 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4425}
4426
4427static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4428{
4429 APICCommonState *apic;
4430 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4431
4432 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 4433
6816b1b3
IM		 4434 object_property_add_child(OBJECT(cpu), "lapic",
4435 OBJECT(cpu->apic_state), &error_abort);
67e55caa 4436 object_unref(OBJECT(cpu->apic_state));
6816b1b3 4437
33d7a288 4438 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 4439 /* TODO: convert to link<> */
02e51483 4440 apic = APIC_COMMON(cpu->apic_state);
60671e58 4441 apic->cpu = cpu;
8d42d2d3 4442 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 4443}
4444
4445static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4446{
8d42d2d3
CF		 4447 APICCommonState *apic;
4448 static bool apic_mmio_map_once;
4449
02e51483 4450 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 4451 return;
4452 }
6e8e2651
MA		 4453 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4454 errp);
8d42d2d3
CF		 4455
4456 /* Map APIC MMIO area */
4457 apic = APIC_COMMON(cpu->apic_state);
4458 if (!apic_mmio_map_once) {
4459 memory_region_add_subregion_overlap(get_system_memory(),
4460 apic->apicbase &
4461 MSR_IA32_APICBASE_BASE,
4462 &apic->io_memory,
4463 0x1000);
4464 apic_mmio_map_once = true;
4465 }
bdeec802 4466}
f809c605
PB		 4467
4468static void x86_cpu_machine_done(Notifier *n, void *unused)
4469{
4470 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4471 MemoryRegion *smram =
4472 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4473
4474 if (smram) {
4475 cpu->smram = g_new(MemoryRegion, 1);
4476 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4477 smram, 0, 1ull << 32);
f8c45c65 4478 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 4479 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4480 }
4481}
d3c64d6a
IM		 4482#else
4483static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4484{
4485}
bdeec802
IM		 4486#endif
4487
11f6fee5
DDAG		 4488/* Note: Only safe for use on x86(-64) hosts */
4489static uint32_t x86_host_phys_bits(void)
4490{
4491 uint32_t eax;
4492 uint32_t host_phys_bits;
4493
4494 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4495 if (eax >= 0x80000008) {
4496 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4497 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4498 * at 23:16 that can specify a maximum physical address bits for
4499 * the guest that can override this value; but I've not seen
4500 * anything with that set.
4501 */
4502 host_phys_bits = eax & 0xff;
4503 } else {
4504 /* It's an odd 64 bit machine that doesn't have the leaf for
4505 * physical address bits; fall back to 36 that's most older
4506 * Intel.
4507 */
4508 host_phys_bits = 36;
4509 }
4510
4511 return host_phys_bits;
4512}
e48638fd 4513
c39c0edf
EH		 4514static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4515{
4516 if (*min < value) {
4517 *min = value;
4518 }
4519}
4520
4521/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4522static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4523{
4524 CPUX86State *env = &cpu->env;
4525 FeatureWordInfo *fi = &feature_word_info[w];
4526 uint32_t eax = fi->cpuid_eax;
4527 uint32_t region = eax & 0xF0000000;
4528
4529 if (!env->features[w]) {
4530 return;
4531 }
4532
4533 switch (region) {
4534 case 0x00000000:
4535 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4536 break;
4537 case 0x80000000:
4538 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4539 break;
4540 case 0xC0000000:
4541 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4542 break;
4543 }
4544}
4545
2ca8a8be
EH		 4546/* Calculate XSAVE components based on the configured CPU feature flags */
4547static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4548{
4549 CPUX86State *env = &cpu->env;
4550 int i;
96193c22 4551 uint64_t mask;
2ca8a8be
EH		 4552
4553 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4554 return;
4555 }
4556
e3c9022b
EH		 4557 mask = 0;
4558 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 4559 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4560 if (env->features[esa->feature] & esa->bits) {
96193c22 4561 mask |= (1ULL << i);
2ca8a8be
EH		 4562 }
4563 }
4564
96193c22
EH		 4565 env->features[FEAT_XSAVE_COMP_LO] = mask;
4566 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 4567}
4568
b8d834a0
EH		 4569/***** Steps involved on loading and filtering CPUID data
4570 *
4571 * When initializing and realizing a CPU object, the steps
4572 * involved in setting up CPUID data are:
4573 *
4574 * 1) Loading CPU model definition (X86CPUDefinition). This is
4575 * implemented by x86_cpu_load_def() and should be completely
4576 * transparent, as it is done automatically by instance_init.
4577 * No code should need to look at X86CPUDefinition structs
4578 * outside instance_init.
4579 *
4580 * 2) CPU expansion. This is done by realize before CPUID
4581 * filtering, and will make sure host/accelerator data is
4582 * loaded for CPU models that depend on host capabilities
4583 * (e.g. "host"). Done by x86_cpu_expand_features().
4584 *
4585 * 3) CPUID filtering. This initializes extra data related to
4586 * CPUID, and checks if the host supports all capabilities
4587 * required by the CPU. Runnability of a CPU model is
4588 * determined at this step. Done by x86_cpu_filter_features().
4589 *
4590 * Some operations don't require all steps to be performed.
4591 * More precisely:
4592 *
4593 * - CPU instance creation (instance_init) will run only CPU
4594 * model loading. CPU expansion can't run at instance_init-time
4595 * because host/accelerator data may be not available yet.
4596 * - CPU realization will perform both CPU model expansion and CPUID
4597 * filtering, and return an error in case one of them fails.
4598 * - query-cpu-definitions needs to run all 3 steps. It needs
4599 * to run CPUID filtering, as the 'unavailable-features'
4600 * field is set based on the filtering results.
4601 * - The query-cpu-model-expansion QMP command only needs to run
4602 * CPU model loading and CPU expansion. It should not filter
4603 * any CPUID data based on host capabilities.
4604 */
4605
4606/* Expand CPU configuration data, based on configured features
4607 * and host/accelerator capabilities when appropriate.
4608 */
4609static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 4610{
b34d12d1 4611 CPUX86State *env = &cpu->env;
dc15c051 4612 FeatureWord w;
2fae0d96 4613 GList *l;
41f3d4d6 4614 Error *local_err = NULL;
9886e834 4615
d4a606b3
EH		 4616 /*TODO: Now cpu->max_features doesn't overwrite features
4617 * set using QOM properties, and we can convert
dc15c051
IM		 4618 * plus_features & minus_features to global properties
4619 * inside x86_cpu_parse_featurestr() too.
4620 */
44bd8e53 4621 if (cpu->max_features) {
dc15c051 4622 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 4623 /* Override only features that weren't set explicitly
4624 * by the user.
4625 */
4626 env->features[w] |=
4627 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
0d914f39
EH		 4628 ~env->user_features[w] & \
4629 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 4630 }
4631 }
4632
2fae0d96
EH		 4633 for (l = plus_features; l; l = l->next) {
4634 const char *prop = l->data;
4635 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
4636 if (local_err) {
4637 goto out;
4638 }
4639 }
4640
4641 for (l = minus_features; l; l = l->next) {
4642 const char *prop = l->data;
4643 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
4644 if (local_err) {
4645 goto out;
4646 }
dc15c051
IM		 4647 }
4648
aec661de
EH		 4649 if (!kvm_enabled() || !cpu->expose_kvm) {
4650 env->features[FEAT_KVM] = 0;
4651 }
4652
2ca8a8be 4653 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 4654
4655 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
4656 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
4657 if (cpu->full_cpuid_auto_level) {
4658 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
4659 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
4660 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
4661 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
4662 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
4663 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
4664 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 4665 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 4666 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
4667 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
4668 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 4669 /* SVM requires CPUID[0x8000000A] */
4670 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
4671 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
4672 }
6cb8f2a6
BS		 4673
4674 /* SEV requires CPUID[0x8000001F] */
4675 if (sev_enabled()) {
4676 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
4677 }
c39c0edf
EH		 4678 }
4679
4680 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
4681 if (env->cpuid_level == UINT32_MAX) {
4682 env->cpuid_level = env->cpuid_min_level;
4683 }
4684 if (env->cpuid_xlevel == UINT32_MAX) {
4685 env->cpuid_xlevel = env->cpuid_min_xlevel;
4686 }
4687 if (env->cpuid_xlevel2 == UINT32_MAX) {
4688 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 4689 }
7a059953 4690
41f3d4d6
EH		 4691out:
4692 if (local_err != NULL) {
4693 error_propagate(errp, local_err);
4694 }
4695}
4696
b8d834a0
EH		 4697/*
4698 * Finishes initialization of CPUID data, filters CPU feature
4699 * words based on host availability of each feature.
4700 *
4701 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
4702 */
4703static int x86_cpu_filter_features(X86CPU *cpu)
4704{
4705 CPUX86State *env = &cpu->env;
4706 FeatureWord w;
4707 int rv = 0;
4708
4709 for (w = 0; w < FEATURE_WORDS; w++) {
4710 uint32_t host_feat =
4711 x86_cpu_get_supported_feature_word(w, false);
4712 uint32_t requested_features = env->features[w];
4713 env->features[w] &= host_feat;
4714 cpu->filtered_features[w] = requested_features & ~env->features[w];
4715 if (cpu->filtered_features[w]) {
4716 rv = 1;
4717 }
4718 }
4719
e37a5c7f
CP		 4720 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
4721 kvm_enabled()) {
4722 KVMState *s = CPU(cpu)->kvm_state;
4723 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
4724 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
4725 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
4726 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
4727 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
4728
4729 if (!eax_0 ||
4730 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
4731 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
4732 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
4733 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
4734 INTEL_PT_ADDR_RANGES_NUM) ||
4735 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96
LK		 4736 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
4737 (ecx_0 & INTEL_PT_IP_LIP)) {
e37a5c7f
CP		 4738 /*
4739 * Processor Trace capabilities aren't configurable, so if the
4740 * host can't emulate the capabilities we report on
4741 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
4742 */
4743 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
4744 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
4745 rv = 1;
4746 }
4747 }
4748
b8d834a0
EH		 4749 return rv;
4750}
4751
41f3d4d6
EH		 4752#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
4753 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
4754 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
4755#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
4756 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
4757 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
4758static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
4759{
4760 CPUState *cs = CPU(dev);
4761 X86CPU *cpu = X86_CPU(dev);
4762 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
4763 CPUX86State *env = &cpu->env;
4764 Error *local_err = NULL;
4765 static bool ht_warned;
4766
d6dcc558 4767 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
41f3d4d6
EH		 4768 char *name = x86_cpu_class_get_model_name(xcc);
4769 error_setg(&local_err, "CPU model '%s' requires KVM", name);
4770 g_free(name);
4771 goto out;
4772 }
4773
4774 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
4775 error_setg(errp, "apic-id property was not initialized properly");
4776 return;
4777 }
4778
b8d834a0 4779 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 4780 if (local_err) {
4781 goto out;
4782 }
4783
8ca30e86
EH		 4784 if (x86_cpu_filter_features(cpu) &&
4785 (cpu->check_cpuid || cpu->enforce_cpuid)) {
4786 x86_cpu_report_filtered_features(cpu);
4787 if (cpu->enforce_cpuid) {
4788 error_setg(&local_err,
d6dcc558 4789 accel_uses_host_cpuid() ?
8ca30e86
EH		 4790 "Host doesn't support requested features" :
4791 "TCG doesn't support requested features");
4792 goto out;
4793 }
9997cf7b
EH		 4794 }
4795
9b15cd9e
IM		 4796 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
4797 * CPUID[1].EDX.
4798 */
e48638fd 4799 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 4800 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
4801 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 4802 & CPUID_EXT2_AMD_ALIASES);
4803 }
4804
11f6fee5
DDAG		 4805 /* For 64bit systems think about the number of physical bits to present.
4806 * ideally this should be the same as the host; anything other than matching
4807 * the host can cause incorrect guest behaviour.
4808 * QEMU used to pick the magic value of 40 bits that corresponds to
4809 * consumer AMD devices but nothing else.
4810 */
af45907a 4811 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 4812 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 4813 uint32_t host_phys_bits = x86_host_phys_bits();
4814 static bool warned;
4815
4816 if (cpu->host_phys_bits) {
4817 /* The user asked for us to use the host physical bits */
4818 cpu->phys_bits = host_phys_bits;
4819 }
4820
4821 /* Print a warning if the user set it to a value that's not the
4822 * host value.
4823 */
4824 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
4825 !warned) {
3dc6f869
AF		 4826 warn_report("Host physical bits (%u)"
4827 " does not match phys-bits property (%u)",
4828 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 4829 warned = true;
4830 }
4831
4832 if (cpu->phys_bits &&
4833 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
4834 cpu->phys_bits < 32)) {
af45907a
DDAG		 4835 error_setg(errp, "phys-bits should be between 32 and %u "
4836 " (but is %u)",
4837 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
4838 return;
4839 }
4840 } else {
11f6fee5 4841 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 4842 error_setg(errp, "TCG only supports phys-bits=%u",
4843 TCG_PHYS_ADDR_BITS);
4844 return;
4845 }
4846 }
11f6fee5
DDAG		 4847 /* 0 means it was not explicitly set by the user (or by machine
4848 * compat_props or by the host code above). In this case, the default
4849 * is the value used by TCG (40).
4850 */
4851 if (cpu->phys_bits == 0) {
4852 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
4853 }
af45907a
DDAG		 4854 } else {
4855 /* For 32 bit systems don't use the user set value, but keep
4856 * phys_bits consistent with what we tell the guest.
4857 */
4858 if (cpu->phys_bits != 0) {
4859 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
4860 return;
4861 }
fefb41bf 4862
af45907a
DDAG		 4863 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
4864 cpu->phys_bits = 36;
4865 } else {
4866 cpu->phys_bits = 32;
4867 }
4868 }
a9f27ea9
EH		 4869
4870 /* Cache information initialization */
4871 if (!cpu->legacy_cache) {
4872 if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
4873 char *name = x86_cpu_class_get_model_name(xcc);
4874 error_setg(errp,
4875 "CPU model '%s' doesn't support legacy-cache=off", name);
4876 g_free(name);
4877 return;
4878 }
4879 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
4880 *xcc->cpu_def->cache_info;
4881 } else {
4882 /* Build legacy cache information */
4883 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
4884 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
4885 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
4886 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
4887
4888 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
4889 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
4890 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
4891 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
4892
4893 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
4894 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
4895 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
4896 env->cache_info_amd.l3_cache = &legacy_l3_cache;
4897 }
4898
4899
ce5b1bbf
LV		 4900 cpu_exec_realizefn(cs, &local_err);
4901 if (local_err != NULL) {
4902 error_propagate(errp, local_err);
4903 return;
4904 }
42ecabaa 4905
65dee380
IM		 4906#ifndef CONFIG_USER_ONLY
4907 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 4908
0514ef2f 4909 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 4910 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 4911 if (local_err != NULL) {
4dc1f449 4912 goto out;
bdeec802
IM		 4913 }
4914 }
65dee380
IM		 4915#endif
4916
7a059953 4917 mce_init(cpu);
2001d0cd
PB		 4918
4919#ifndef CONFIG_USER_ONLY
4920 if (tcg_enabled()) {
f809c605 4921 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 4922 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 4923
4924 /* Outer container... */
4925 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 4926 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 4927
4928 /* ... with two regions inside: normal system memory with low
4929 * priority, and...
4930 */
4931 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
4932 get_system_memory(), 0, ~0ull);
4933 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
4934 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 4935
4936 cs->num_ases = 2;
80ceb07a
PX		 4937 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
4938 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 4939
4940 /* ... SMRAM with higher priority, linked from /machine/smram. */
4941 cpu->machine_done.notify = x86_cpu_machine_done;
4942 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 4943 }
4944#endif
4945
14a10fc3 4946 qemu_init_vcpu(cs);
d3c64d6a 4947
e48638fd
WH		 4948 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
4949 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
4950 * based on inputs (sockets,cores,threads), it is still better to gives
4951 * users a warning.
4952 *
4953 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
4954 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
4955 */
4956 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
4957 error_report("AMD CPU doesn't support hyperthreading. Please configure"
4958 " -smp options properly.");
4959 ht_warned = true;
4960 }
4961
d3c64d6a
IM		 4962 x86_cpu_apic_realize(cpu, &local_err);
4963 if (local_err != NULL) {
4964 goto out;
4965 }
14a10fc3 4966 cpu_reset(cs);
2b6f294c 4967
4dc1f449 4968 xcc->parent_realize(dev, &local_err);
2001d0cd 4969
4dc1f449
IM		 4970out:
4971 if (local_err != NULL) {
4972 error_propagate(errp, local_err);
4973 return;
4974 }
7a059953
AF		 4975}
4976
c884776e
IM		 4977static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
4978{
4979 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 4980 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
4981 Error *local_err = NULL;
c884776e
IM		 4982
4983#ifndef CONFIG_USER_ONLY
4984 cpu_remove_sync(CPU(dev));
4985 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
4986#endif
4987
4988 if (cpu->apic_state) {
4989 object_unparent(OBJECT(cpu->apic_state));
4990 cpu->apic_state = NULL;
4991 }
7bbc124e
LV		 4992
4993 xcc->parent_unrealize(dev, &local_err);
4994 if (local_err != NULL) {
4995 error_propagate(errp, local_err);
4996 return;
4997 }
c884776e
IM		 4998}
4999
38e5c119 5000typedef struct BitProperty {
a7b0ffac 5001 FeatureWord w;
38e5c119
EH		 5002 uint32_t mask;
5003} BitProperty;
5004
d7bce999
EB		 5005static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
5006 void *opaque, Error **errp)
38e5c119 5007{
a7b0ffac 5008 X86CPU *cpu = X86_CPU(obj);
38e5c119 5009 BitProperty *fp = opaque;
a7b0ffac
EH		 5010 uint32_t f = cpu->env.features[fp->w];
5011 bool value = (f & fp->mask) == fp->mask;
51e72bc1 5012 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 5013}
5014
d7bce999
EB		 5015static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
5016 void *opaque, Error **errp)
38e5c119
EH		 5017{
5018 DeviceState *dev = DEVICE(obj);
a7b0ffac 5019 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 5020 BitProperty *fp = opaque;
5021 Error *local_err = NULL;
5022 bool value;
5023
5024 if (dev->realized) {
5025 qdev_prop_set_after_realize(dev, name, errp);
5026 return;
5027 }
5028
51e72bc1 5029 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 5030 if (local_err) {
5031 error_propagate(errp, local_err);
5032 return;
5033 }
5034
5035 if (value) {
a7b0ffac 5036 cpu->env.features[fp->w] |= fp->mask;
38e5c119 5037 } else {
a7b0ffac 5038 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 5039 }
d4a606b3 5040 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 5041}
5042
5043static void x86_cpu_release_bit_prop(Object *obj, const char *name,
5044 void *opaque)
5045{
5046 BitProperty *prop = opaque;
5047 g_free(prop);
5048}
5049
5050/* Register a boolean property to get/set a single bit in a uint32_t field.
5051 *
5052 * The same property name can be registered multiple times to make it affect
5053 * multiple bits in the same FeatureWord. In that case, the getter will return
5054 * true only if all bits are set.
5055 */
5056static void x86_cpu_register_bit_prop(X86CPU *cpu,
5057 const char *prop_name,
a7b0ffac 5058 FeatureWord w,
38e5c119
EH		 5059 int bitnr)
5060{
5061 BitProperty *fp;
5062 ObjectProperty *op;
5063 uint32_t mask = (1UL << bitnr);
5064
5065 op = object_property_find(OBJECT(cpu), prop_name, NULL);
5066 if (op) {
5067 fp = op->opaque;
a7b0ffac 5068 assert(fp->w == w);
38e5c119
EH		 5069 fp->mask |= mask;
5070 } else {
5071 fp = g_new0(BitProperty, 1);
a7b0ffac 5072 fp->w = w;
38e5c119
EH		 5073 fp->mask = mask;
5074 object_property_add(OBJECT(cpu), prop_name, "bool",
5075 x86_cpu_get_bit_prop,
5076 x86_cpu_set_bit_prop,
5077 x86_cpu_release_bit_prop, fp, &error_abort);
5078 }
5079}
5080
5081static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
5082 FeatureWord w,
5083 int bitnr)
5084{
38e5c119 5085 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 5086 const char *name = fi->feat_names[bitnr];
38e5c119 5087
16d2fcaa 5088 if (!name) {
38e5c119
EH		 5089 return;
5090 }
5091
fc7dfd20
EH		 5092 /* Property names should use "-" instead of "_".
5093 * Old names containing underscores are registered as aliases
5094 * using object_property_add_alias()
5095 */
16d2fcaa
EH		 5096 assert(!strchr(name, '_'));
5097 /* aliases don't use "|" delimiters anymore, they are registered
5098 * manually using object_property_add_alias() */
5099 assert(!strchr(name, '|'));
a7b0ffac 5100 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 5101}
5102
d187e08d
AN		 5103static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
5104{
5105 X86CPU *cpu = X86_CPU(cs);
5106 CPUX86State *env = &cpu->env;
5107 GuestPanicInformation *panic_info = NULL;
5108
5e953812 5109 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 5110 panic_info = g_malloc0(sizeof(GuestPanicInformation));
5111
e8ed97a6 5112 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 5113
5e953812 5114 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 5115 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
5116 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
5117 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
5118 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
5119 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 5120 }
5121
5122 return panic_info;
5123}
5124static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
5125 const char *name, void *opaque,
5126 Error **errp)
5127{
5128 CPUState *cs = CPU(obj);
5129 GuestPanicInformation *panic_info;
5130
5131 if (!cs->crash_occurred) {
5132 error_setg(errp, "No crash occured");
5133 return;
5134 }
5135
5136 panic_info = x86_cpu_get_crash_info(cs);
5137 if (panic_info == NULL) {
5138 error_setg(errp, "No crash information");
5139 return;
5140 }
5141
5142 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
5143 errp);
5144 qapi_free_GuestPanicInformation(panic_info);
5145}
5146
de024815
AF		 5147static void x86_cpu_initfn(Object *obj)
5148{
55e5c285 5149 CPUState *cs = CPU(obj);
de024815 5150 X86CPU *cpu = X86_CPU(obj);
d940ee9b 5151 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 5152 CPUX86State *env = &cpu->env;
38e5c119 5153 FeatureWord w;
de024815 5154
c05efcb1 5155 cs->env_ptr = env;
71ad61d3
AF		 5156
5157 object_property_add(obj, "family", "int",
95b8519d 5158 x86_cpuid_version_get_family,
71ad61d3 5159 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 5160 object_property_add(obj, "model", "int",
67e30c83 5161 x86_cpuid_version_get_model,
c5291a4f 5162 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 5163 object_property_add(obj, "stepping", "int",
35112e41 5164 x86_cpuid_version_get_stepping,
036e2222 5165 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 5166 object_property_add_str(obj, "vendor",
5167 x86_cpuid_get_vendor,
5168 x86_cpuid_set_vendor, NULL);
938d4c25 5169 object_property_add_str(obj, "model-id",
63e886eb 5170 x86_cpuid_get_model_id,
938d4c25 5171 x86_cpuid_set_model_id, NULL);
89e48965
AF		 5172 object_property_add(obj, "tsc-frequency", "int",
5173 x86_cpuid_get_tsc_freq,
5174 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 5175 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
5176 x86_cpu_get_feature_words,
7e5292b5
EH		 5177 NULL, NULL, (void *)env->features, NULL);
5178 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
5179 x86_cpu_get_feature_words,
5180 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 5181
d187e08d
AN		 5182 object_property_add(obj, "crash-information", "GuestPanicInformation",
5183 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
5184
92067bf4 5185 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 5186
38e5c119
EH		 5187 for (w = 0; w < FEATURE_WORDS; w++) {
5188 int bitnr;
5189
5190 for (bitnr = 0; bitnr < 32; bitnr++) {
5191 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
5192 }
5193 }
5194
16d2fcaa
EH		 5195 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
5196 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
5197 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
5198 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
5199 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
5200 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
5201 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
5202
54b8dc7c
EH		 5203 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
5204 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
5205 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
5206 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
5207 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
5208 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
5209 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
5210 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
5211 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
5212 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
5213 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
5214 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
5215 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
5216 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
5217 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
5218 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
5219 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
5220 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
5221 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
5222 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
5223 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
5224
0bacd8b3
EH		 5225 if (xcc->cpu_def) {
5226 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
5227 }
de024815
AF		 5228}
5229
997395d3
IM		 5230static int64_t x86_cpu_get_arch_id(CPUState *cs)
5231{
5232 X86CPU *cpu = X86_CPU(cs);
997395d3 5233
7e72a45c 5234 return cpu->apic_id;
997395d3
IM		 5235}
5236
444d5590
AF		 5237static bool x86_cpu_get_paging_enabled(const CPUState *cs)
5238{
5239 X86CPU *cpu = X86_CPU(cs);
5240
5241 return cpu->env.cr[0] & CR0_PG_MASK;
5242}
5243
f45748f1
AF		 5244static void x86_cpu_set_pc(CPUState *cs, vaddr value)
5245{
5246 X86CPU *cpu = X86_CPU(cs);
5247
5248 cpu->env.eip = value;
5249}
5250
bdf7ae5b
AF		 5251static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
5252{
5253 X86CPU *cpu = X86_CPU(cs);
5254
5255 cpu->env.eip = tb->pc - tb->cs_base;
5256}
5257
8c2e1b00
AF		 5258static bool x86_cpu_has_work(CPUState *cs)
5259{
5260 X86CPU *cpu = X86_CPU(cs);
5261 CPUX86State *env = &cpu->env;
5262
6220e900
PD		 5263 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
5264 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 5265 (env->eflags & IF_MASK)) ||
5266 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
5267 CPU_INTERRUPT_INIT |
5268 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 5269 CPU_INTERRUPT_MCE)) ||
5270 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
5271 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 5272}
5273
f50f3dd5
RH		 5274static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
5275{
5276 X86CPU *cpu = X86_CPU(cs);
5277 CPUX86State *env = &cpu->env;
5278
5279 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
5280 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
5281 : bfd_mach_i386_i8086);
5282 info->print_insn = print_insn_i386;
b666d2a4
RH		 5283
5284 info->cap_arch = CS_ARCH_X86;
5285 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
5286 : env->hflags & HF_CS32_MASK ? CS_MODE_32
5287 : CS_MODE_16);
15fa1a0a
RH		 5288 info->cap_insn_unit = 1;
5289 info->cap_insn_split = 8;
f50f3dd5
RH		 5290}
5291
35b1b927
TW		 5292void x86_update_hflags(CPUX86State *env)
5293{
5294 uint32_t hflags;
5295#define HFLAG_COPY_MASK \
5296 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5297 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5298 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5299 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5300
5301 hflags = env->hflags & HFLAG_COPY_MASK;
5302 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5303 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5304 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5305 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5306 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5307
5308 if (env->cr[4] & CR4_OSFXSR_MASK) {
5309 hflags |= HF_OSFXSR_MASK;
5310 }
5311
5312 if (env->efer & MSR_EFER_LMA) {
5313 hflags |= HF_LMA_MASK;
5314 }
5315
5316 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5317 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5318 } else {
5319 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5320 (DESC_B_SHIFT - HF_CS32_SHIFT);
5321 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5322 (DESC_B_SHIFT - HF_SS32_SHIFT);
5323 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5324 !(hflags & HF_CS32_MASK)) {
5325 hflags |= HF_ADDSEG_MASK;
5326 } else {
5327 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5328 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5329 }
5330 }
5331 env->hflags = hflags;
5332}
5333
9337e3b6 5334static Property x86_cpu_properties[] = {
2da00e31
IM		 5335#ifdef CONFIG_USER_ONLY
5336 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5337 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 5338 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5339 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5340 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 5341#else
5342 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 5343 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5344 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5345 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 5346#endif
15f8b142 5347 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 5348 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 5349 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 5350 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 5351 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 5352 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 5353 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 5354 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 5355 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 5356 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 5357 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 5358 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
9445597b 5359 DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
ba6a4fd9 5360 DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment, false),
15e41345 5361 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 5362 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 5363 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 5364 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 5365 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 5366 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 5367 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5368 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5369 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5370 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5371 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5372 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5373 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 5374 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 5375 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 5376 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 5377 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 5378 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5379 false),
0b564e6f 5380 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 5381 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
ab8f992e 5382 /*
a9f27ea9
EH		 5383 * lecacy_cache defaults to true unless the CPU model provides its
5384 * own cache information (see x86_cpu_load_def()).
ab8f992e 5385 */
a9f27ea9 5386 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 5387
5388 /*
5389 * From "Requirements for Implementing the Microsoft
5390 * Hypervisor Interface":
5391 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5392 *
5393 * "Starting with Windows Server 2012 and Windows 8, if
5394 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5395 * the hypervisor imposes no specific limit to the number of VPs.
5396 * In this case, Windows Server 2012 guest VMs may use more than
5397 * 64 VPs, up to the maximum supported number of processors applicable
5398 * to the specific Windows version being used."
5399 */
5400 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9337e3b6
EH		 5401 DEFINE_PROP_END_OF_LIST()
5402};
5403
5fd2087a
AF		 5404static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5405{
5406 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5407 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 5408 DeviceClass *dc = DEVICE_CLASS(oc);
5409
bf853881
PMD		 5410 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5411 &xcc->parent_realize);
5412 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5413 &xcc->parent_unrealize);
9337e3b6 5414 dc->props = x86_cpu_properties;
5fd2087a
AF		 5415
5416 xcc->parent_reset = cc->reset;
5417 cc->reset = x86_cpu_reset;
91b1df8c 5418 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 5419
500050d1 5420 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 5421 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 5422 cc->has_work = x86_cpu_has_work;
79c664f6 5423#ifdef CONFIG_TCG
97a8ea5a 5424 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 5425 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 5426#endif
878096ee 5427 cc->dump_state = x86_cpu_dump_state;
c86f106b 5428 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 5429 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 5430 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 5431 cc->gdb_read_register = x86_cpu_gdb_read_register;
5432 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 5433 cc->get_arch_id = x86_cpu_get_arch_id;
5434 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 5435#ifdef CONFIG_USER_ONLY
5436 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
5437#else
f8c45c65 5438 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 5439 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 5440 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 5441 cc->write_elf64_note = x86_cpu_write_elf64_note;
5442 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5443 cc->write_elf32_note = x86_cpu_write_elf32_note;
5444 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 5445 cc->vmsd = &vmstate_x86_cpu;
c72bf468 5446#endif
00fcd100
AB		 5447 cc->gdb_arch_name = x86_gdb_arch_name;
5448#ifdef TARGET_X86_64
b8158192
AB		 5449 cc->gdb_core_xml_file = "i386-64bit.xml";
5450 cc->gdb_num_core_regs = 57;
00fcd100 5451#else
b8158192
AB		 5452 cc->gdb_core_xml_file = "i386-32bit.xml";
5453 cc->gdb_num_core_regs = 41;
00fcd100 5454#endif
79c664f6 5455#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 5456 cc->debug_excp_handler = breakpoint_handler;
5457#endif
374e0cd4
RH		 5458 cc->cpu_exec_enter = x86_cpu_exec_enter;
5459 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 5460#ifdef CONFIG_TCG
55c3ceef 5461 cc->tcg_initialize = tcg_x86_init;
74d7fc7f 5462#endif
f50f3dd5 5463 cc->disas_set_info = x86_disas_set_info;
4c315c27 5464
e90f2a8c 5465 dc->user_creatable = true;
5fd2087a
AF		 5466}
5467
5468static const TypeInfo x86_cpu_type_info = {
5469 .name = TYPE_X86_CPU,
5470 .parent = TYPE_CPU,
5471 .instance_size = sizeof(X86CPU),
de024815 5472 .instance_init = x86_cpu_initfn,
d940ee9b 5473 .abstract = true,
5fd2087a
AF		 5474 .class_size = sizeof(X86CPUClass),
5475 .class_init = x86_cpu_common_class_init,
5476};
5477
5adbed30
EH		 5478
5479/* "base" CPU model, used by query-cpu-model-expansion */
5480static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
5481{
5482 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5483
5484 xcc->static_model = true;
5485 xcc->migration_safe = true;
5486 xcc->model_description = "base CPU model type with no features enabled";
5487 xcc->ordering = 8;
5488}
5489
5490static const TypeInfo x86_base_cpu_type_info = {
5491 .name = X86_CPU_TYPE_NAME("base"),
5492 .parent = TYPE_X86_CPU,
5493 .class_init = x86_cpu_base_class_init,
5494};
5495
5fd2087a
AF		 5496static void x86_cpu_register_types(void)
5497{
d940ee9b
EH		 5498 int i;
5499
5fd2087a 5500 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 5501 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
5502 x86_register_cpudef_type(&builtin_x86_defs[i]);
5503 }
c62f2630 5504 type_register_static(&max_x86_cpu_type_info);
5adbed30 5505 type_register_static(&x86_base_cpu_type_info);
d6dcc558 5506#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 5507 type_register_static(&host_x86_cpu_type_info);
5508#endif
5fd2087a
AF		 5509}
5510
5511type_init(x86_cpu_register_types)
QEMU mirror