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i386: Add cache information in X86CPUDefinition
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
f348b6d1 21#include "qemu/cutils.h"
c6dc6f63
AP		 22
23#include "cpu.h"
63c91552 24#include "exec/exec-all.h"
9c17d615 25#include "sysemu/kvm.h"
d6dcc558 26#include "sysemu/hvf.h"
8932cfdf 27#include "sysemu/cpus.h"
50a2c6e5 28#include "kvm_i386.h"
6cb8f2a6 29#include "sev_i386.h"
c6dc6f63 30
d49b6836 31#include "qemu/error-report.h"
1de7afc9
PB		 32#include "qemu/option.h"
33#include "qemu/config-file.h"
e688df6b 34#include "qapi/error.h"
112ed241
MA		 35#include "qapi/qapi-visit-misc.h"
36#include "qapi/qapi-visit-run-state.h"
452fcdbc 37#include "qapi/qmp/qdict.h"
7b1b5d19 38#include "qapi/qmp/qerror.h"
7b1b5d19 39#include "qapi/visitor.h"
f99fd7ca 40#include "qom/qom-qobject.h"
9c17d615 41#include "sysemu/arch_init.h"
71ad61d3 42
b834b508 43#if defined(CONFIG_KVM)
ef8621b1 44#include <linux/kvm_para.h>
b834b508 45#endif
65dee380 46
9c17d615 47#include "sysemu/sysemu.h"
53a89e26 48#include "hw/qdev-properties.h"
5232d00a 49#include "hw/i386/topology.h"
bdeec802 50#ifndef CONFIG_USER_ONLY
2001d0cd 51#include "exec/address-spaces.h"
741da0d3 52#include "hw/hw.h"
0d09e41a 53#include "hw/xen/xen.h"
0d09e41a 54#include "hw/i386/apic_internal.h"
bdeec802
IM		 55#endif
56
b666d2a4
RH		 57#include "disas/capstone.h"
58
7e3482f8
EH		 59/* Helpers for building CPUID[2] descriptors: */
60
61struct CPUID2CacheDescriptorInfo {
62 enum CacheType type;
63 int level;
64 int size;
65 int line_size;
66 int associativity;
67};
5e891bf8 68
7e3482f8
EH		 69#define KiB 1024
70#define MiB (1024 * 1024)
5e891bf8 71
7e3482f8
EH		 72/*
73 * Known CPUID 2 cache descriptors.
74 * From Intel SDM Volume 2A, CPUID instruction
75 */
76struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
77 [0x06] = { .level = 1, .type = ICACHE, .size = 8 * KiB,
78 .associativity = 4, .line_size = 32, },
79 [0x08] = { .level = 1, .type = ICACHE, .size = 16 * KiB,
80 .associativity = 4, .line_size = 32, },
81 [0x09] = { .level = 1, .type = ICACHE, .size = 32 * KiB,
82 .associativity = 4, .line_size = 64, },
83 [0x0A] = { .level = 1, .type = DCACHE, .size = 8 * KiB,
84 .associativity = 2, .line_size = 32, },
85 [0x0C] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
86 .associativity = 4, .line_size = 32, },
87 [0x0D] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
88 .associativity = 4, .line_size = 64, },
89 [0x0E] = { .level = 1, .type = DCACHE, .size = 24 * KiB,
90 .associativity = 6, .line_size = 64, },
91 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
92 .associativity = 2, .line_size = 64, },
93 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
94 .associativity = 8, .line_size = 64, },
95 /* lines per sector is not supported cpuid2_cache_descriptor(),
96 * so descriptors 0x22, 0x23 are not included
97 */
98 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
99 .associativity = 16, .line_size = 64, },
100 /* lines per sector is not supported cpuid2_cache_descriptor(),
101 * so descriptors 0x25, 0x20 are not included
102 */
103 [0x2C] = { .level = 1, .type = DCACHE, .size = 32 * KiB,
104 .associativity = 8, .line_size = 64, },
105 [0x30] = { .level = 1, .type = ICACHE, .size = 32 * KiB,
106 .associativity = 8, .line_size = 64, },
107 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
108 .associativity = 4, .line_size = 32, },
109 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
110 .associativity = 4, .line_size = 32, },
111 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
112 .associativity = 4, .line_size = 32, },
113 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
114 .associativity = 4, .line_size = 32, },
115 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
116 .associativity = 4, .line_size = 32, },
117 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
118 .associativity = 4, .line_size = 64, },
119 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
120 .associativity = 8, .line_size = 64, },
121 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
122 .associativity = 12, .line_size = 64, },
123 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
124 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
125 .associativity = 12, .line_size = 64, },
126 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
127 .associativity = 16, .line_size = 64, },
128 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
129 .associativity = 12, .line_size = 64, },
130 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
131 .associativity = 16, .line_size = 64, },
132 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
133 .associativity = 24, .line_size = 64, },
134 [0x60] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
135 .associativity = 8, .line_size = 64, },
136 [0x66] = { .level = 1, .type = DCACHE, .size = 8 * KiB,
137 .associativity = 4, .line_size = 64, },
138 [0x67] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
139 .associativity = 4, .line_size = 64, },
140 [0x68] = { .level = 1, .type = DCACHE, .size = 32 * KiB,
141 .associativity = 4, .line_size = 64, },
142 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
143 .associativity = 4, .line_size = 64, },
144 /* lines per sector is not supported cpuid2_cache_descriptor(),
145 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
146 */
147 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
148 .associativity = 8, .line_size = 64, },
149 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
150 .associativity = 2, .line_size = 64, },
151 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
152 .associativity = 8, .line_size = 64, },
153 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
154 .associativity = 8, .line_size = 32, },
155 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
156 .associativity = 8, .line_size = 32, },
157 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
158 .associativity = 8, .line_size = 32, },
159 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
160 .associativity = 8, .line_size = 32, },
161 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
162 .associativity = 4, .line_size = 64, },
163 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
164 .associativity = 8, .line_size = 64, },
165 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
166 .associativity = 4, .line_size = 64, },
167 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
168 .associativity = 4, .line_size = 64, },
169 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
170 .associativity = 4, .line_size = 64, },
171 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
172 .associativity = 8, .line_size = 64, },
173 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
174 .associativity = 8, .line_size = 64, },
175 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
176 .associativity = 8, .line_size = 64, },
177 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
178 .associativity = 12, .line_size = 64, },
179 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
180 .associativity = 12, .line_size = 64, },
181 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
182 .associativity = 12, .line_size = 64, },
183 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
184 .associativity = 16, .line_size = 64, },
185 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
186 .associativity = 16, .line_size = 64, },
187 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
188 .associativity = 16, .line_size = 64, },
189 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
190 .associativity = 24, .line_size = 64, },
191 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
192 .associativity = 24, .line_size = 64, },
193 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
194 .associativity = 24, .line_size = 64, },
195};
196
197/*
198 * "CPUID leaf 2 does not report cache descriptor information,
199 * use CPUID leaf 4 to query cache parameters"
200 */
201#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 202
7e3482f8
EH		 203/*
204 * Return a CPUID 2 cache descriptor for a given cache.
205 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
206 */
207static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
208{
209 int i;
210
211 assert(cache->size > 0);
212 assert(cache->level > 0);
213 assert(cache->line_size > 0);
214 assert(cache->associativity > 0);
215 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
216 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
217 if (d->level == cache->level && d->type == cache->type &&
218 d->size == cache->size && d->line_size == cache->line_size &&
219 d->associativity == cache->associativity) {
220 return i;
221 }
222 }
5e891bf8 223
7e3482f8
EH		 224 return CACHE_DESCRIPTOR_UNAVAILABLE;
225}
5e891bf8
EH		 226
227/* CPUID Leaf 4 constants: */
228
229/* EAX: */
7e3482f8
EH		 230#define CACHE_TYPE_D 1
231#define CACHE_TYPE_I 2
232#define CACHE_TYPE_UNIFIED 3
5e891bf8 233
7e3482f8 234#define CACHE_LEVEL(l) (l << 5)
5e891bf8 235
7e3482f8 236#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 237
238/* EDX: */
7e3482f8
EH		 239#define CACHE_NO_INVD_SHARING (1 << 0)
240#define CACHE_INCLUSIVE (1 << 1)
241#define CACHE_COMPLEX_IDX (1 << 2)
242
243/* Encode CacheType for CPUID[4].EAX */
244#define CACHE_TYPE(t) (((t) == DCACHE) ? CACHE_TYPE_D : \
245 ((t) == ICACHE) ? CACHE_TYPE_I : \
246 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
247 0 /* Invalid value */)
248
249
250/* Encode cache info for CPUID[4] */
251static void encode_cache_cpuid4(CPUCacheInfo *cache,
252 int num_apic_ids, int num_cores,
253 uint32_t *eax, uint32_t *ebx,
254 uint32_t *ecx, uint32_t *edx)
255{
256 assert(cache->size == cache->line_size * cache->associativity *
257 cache->partitions * cache->sets);
258
259 assert(num_apic_ids > 0);
260 *eax = CACHE_TYPE(cache->type) |
261 CACHE_LEVEL(cache->level) |
262 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
263 ((num_cores - 1) << 26) |
264 ((num_apic_ids - 1) << 14);
265
266 assert(cache->line_size > 0);
267 assert(cache->partitions > 0);
268 assert(cache->associativity > 0);
269 /* We don't implement fully-associative caches */
270 assert(cache->associativity < cache->sets);
271 *ebx = (cache->line_size - 1) |
272 ((cache->partitions - 1) << 12) |
273 ((cache->associativity - 1) << 22);
274
275 assert(cache->sets > 0);
276 *ecx = cache->sets - 1;
277
278 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
279 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
280 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
281}
282
283/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
284static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
285{
286 assert(cache->size % 1024 == 0);
287 assert(cache->lines_per_tag > 0);
288 assert(cache->associativity > 0);
289 assert(cache->line_size > 0);
290 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
291 (cache->lines_per_tag << 8) | (cache->line_size);
292}
5e891bf8
EH		 293
294#define ASSOC_FULL 0xFF
295
296/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
297#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
298 a == 2 ? 0x2 : \
299 a == 4 ? 0x4 : \
300 a == 8 ? 0x6 : \
301 a == 16 ? 0x8 : \
302 a == 32 ? 0xA : \
303 a == 48 ? 0xB : \
304 a == 64 ? 0xC : \
305 a == 96 ? 0xD : \
306 a == 128 ? 0xE : \
307 a == ASSOC_FULL ? 0xF : \
308 0 /* invalid value */)
309
7e3482f8
EH		 310/*
311 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
312 * @l3 can be NULL.
313 */
314static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
315 CPUCacheInfo *l3,
316 uint32_t *ecx, uint32_t *edx)
317{
318 assert(l2->size % 1024 == 0);
319 assert(l2->associativity > 0);
320 assert(l2->lines_per_tag > 0);
321 assert(l2->line_size > 0);
322 *ecx = ((l2->size / 1024) << 16) |
323 (AMD_ENC_ASSOC(l2->associativity) << 12) |
324 (l2->lines_per_tag << 8) | (l2->line_size);
325
326 if (l3) {
327 assert(l3->size % (512 * 1024) == 0);
328 assert(l3->associativity > 0);
329 assert(l3->lines_per_tag > 0);
330 assert(l3->line_size > 0);
331 *edx = ((l3->size / (512 * 1024)) << 18) |
332 (AMD_ENC_ASSOC(l3->associativity) << 12) |
333 (l3->lines_per_tag << 8) | (l3->line_size);
334 } else {
335 *edx = 0;
336 }
337}
5e891bf8
EH		 338
339/* Definitions of the hardcoded cache entries we expose: */
340
341/* L1 data cache: */
7e3482f8
EH		 342static CPUCacheInfo l1d_cache = {
343 .type = DCACHE,
344 .level = 1,
345 .size = 32 * KiB,
346 .self_init = 1,
347 .line_size = 64,
348 .associativity = 8,
349 .sets = 64,
350 .partitions = 1,
351 .no_invd_sharing = true,
352};
353
5e891bf8 354/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
7e3482f8
EH		 355static CPUCacheInfo l1d_cache_amd = {
356 .type = DCACHE,
357 .level = 1,
358 .size = 64 * KiB,
359 .self_init = 1,
360 .line_size = 64,
361 .associativity = 2,
362 .sets = 512,
363 .partitions = 1,
364 .lines_per_tag = 1,
365 .no_invd_sharing = true,
366};
5e891bf8
EH		 367
368/* L1 instruction cache: */
7e3482f8
EH		 369static CPUCacheInfo l1i_cache = {
370 .type = ICACHE,
371 .level = 1,
372 .size = 32 * KiB,
373 .self_init = 1,
374 .line_size = 64,
375 .associativity = 8,
376 .sets = 64,
377 .partitions = 1,
378 .no_invd_sharing = true,
379};
380
5e891bf8 381/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
7e3482f8
EH		 382static CPUCacheInfo l1i_cache_amd = {
383 .type = ICACHE,
384 .level = 1,
385 .size = 64 * KiB,
386 .self_init = 1,
387 .line_size = 64,
388 .associativity = 2,
389 .sets = 512,
390 .partitions = 1,
391 .lines_per_tag = 1,
392 .no_invd_sharing = true,
393};
5e891bf8
EH		 394
395/* Level 2 unified cache: */
7e3482f8
EH		 396static CPUCacheInfo l2_cache = {
397 .type = UNIFIED_CACHE,
398 .level = 2,
399 .size = 4 * MiB,
400 .self_init = 1,
401 .line_size = 64,
402 .associativity = 16,
403 .sets = 4096,
404 .partitions = 1,
405 .no_invd_sharing = true,
406};
407
5e891bf8 408/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
7e3482f8
EH		 409static CPUCacheInfo l2_cache_cpuid2 = {
410 .type = UNIFIED_CACHE,
411 .level = 2,
412 .size = 2 * MiB,
413 .line_size = 64,
414 .associativity = 8,
415};
416
417
5e891bf8 418/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
7e3482f8
EH		 419static CPUCacheInfo l2_cache_amd = {
420 .type = UNIFIED_CACHE,
421 .level = 2,
422 .size = 512 * KiB,
423 .line_size = 64,
424 .lines_per_tag = 1,
425 .associativity = 16,
426 .sets = 512,
427 .partitions = 1,
428};
5e891bf8 429
14c985cf 430/* Level 3 unified cache: */
7e3482f8
EH		 431static CPUCacheInfo l3_cache = {
432 .type = UNIFIED_CACHE,
433 .level = 3,
434 .size = 16 * MiB,
435 .line_size = 64,
436 .associativity = 16,
437 .sets = 16384,
438 .partitions = 1,
439 .lines_per_tag = 1,
440 .self_init = true,
441 .inclusive = true,
442 .complex_indexing = true,
443};
5e891bf8
EH		 444
445/* TLB definitions: */
446
447#define L1_DTLB_2M_ASSOC 1
448#define L1_DTLB_2M_ENTRIES 255
449#define L1_DTLB_4K_ASSOC 1
450#define L1_DTLB_4K_ENTRIES 255
451
452#define L1_ITLB_2M_ASSOC 1
453#define L1_ITLB_2M_ENTRIES 255
454#define L1_ITLB_4K_ASSOC 1
455#define L1_ITLB_4K_ENTRIES 255
456
457#define L2_DTLB_2M_ASSOC 0 /* disabled */
458#define L2_DTLB_2M_ENTRIES 0 /* disabled */
459#define L2_DTLB_4K_ASSOC 4
460#define L2_DTLB_4K_ENTRIES 512
461
462#define L2_ITLB_2M_ASSOC 0 /* disabled */
463#define L2_ITLB_2M_ENTRIES 0 /* disabled */
464#define L2_ITLB_4K_ASSOC 4
465#define L2_ITLB_4K_ENTRIES 512
466
e37a5c7f
CP		 467/* CPUID Leaf 0x14 constants: */
468#define INTEL_PT_MAX_SUBLEAF 0x1
469/*
470 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
471 * MSR can be accessed;
472 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
473 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
474 * of Intel PT MSRs across warm reset;
475 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
476 */
477#define INTEL_PT_MINIMAL_EBX 0xf
478/*
479 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
480 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
481 * accessed;
482 * bit[01]: ToPA tables can hold any number of output entries, up to the
483 * maximum allowed by the MaskOrTableOffset field of
484 * IA32_RTIT_OUTPUT_MASK_PTRS;
485 * bit[02]: Support Single-Range Output scheme;
486 */
487#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 488/* generated packets which contain IP payloads have LIP values */
489#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 490#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
491#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
492#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
493#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
494#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 495
99b88a17
IM		 496static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
497 uint32_t vendor2, uint32_t vendor3)
498{
499 int i;
500 for (i = 0; i < 4; i++) {
501 dst[i] = vendor1 >> (8 * i);
502 dst[i + 4] = vendor2 >> (8 * i);
503 dst[i + 8] = vendor3 >> (8 * i);
504 }
505 dst[CPUID_VENDOR_SZ] = '\0';
506}
507
621626ce
EH		 508#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
509#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
510 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
511#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
512 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
513 CPUID_PSE36 | CPUID_FXSR)
514#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
515#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
516 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
517 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
518 CPUID_PAE | CPUID_SEP | CPUID_APIC)
519
520#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
521 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
522 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
523 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 524 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 525 /* partly implemented:
526 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
527 /* missing:
528 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
529#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
530 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
531 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 532 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 533 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
534 /* missing:
535 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
536 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
537 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 538 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
539 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 540
541#ifdef TARGET_X86_64
542#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
543#else
544#define TCG_EXT2_X86_64_FEATURES 0
545#endif
546
547#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
548 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
549 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
550 TCG_EXT2_X86_64_FEATURES)
551#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
552 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
553#define TCG_EXT4_FEATURES 0
554#define TCG_SVM_FEATURES 0
555#define TCG_KVM_FEATURES 0
556#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 557 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
558 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 559 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
560 CPUID_7_0_EBX_ERMS)
621626ce 561 /* missing:
07929f2a 562 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 563 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 564 CPUID_7_0_EBX_RDSEED */
6c7c3c21
KS		 565#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
566 CPUID_7_0_ECX_LA57)
95ea69fb 567#define TCG_7_0_EDX_FEATURES 0
303752a9 568#define TCG_APM_FEATURES 0
28b8e4d0 569#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 570#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
571 /* missing:
572 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 573
5ef57876 574typedef struct FeatureWordInfo {
2d5312da
EH		 575 /* feature flags names are taken from "Intel Processor Identification and
576 * the CPUID Instruction" and AMD's "CPUID Specification".
577 * In cases of disagreement between feature naming conventions,
578 * aliases may be added.
579 */
580 const char *feat_names[32];
04d104b6
EH		 581 uint32_t cpuid_eax; /* Input EAX for CPUID */
582 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
583 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
584 int cpuid_reg; /* output register (R_* constant) */
37ce3522 585 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 586 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 587 uint32_t migratable_flags; /* Feature flags known to be migratable */
0d914f39
EH		 588 /* Features that shouldn't be auto-enabled by "-cpu host" */
589 uint32_t no_autoenable_flags;
5ef57876
EH		 590} FeatureWordInfo;
591
592static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 593 [FEAT_1_EDX] = {
2d5312da
EH		 594 .feat_names = {
595 "fpu", "vme", "de", "pse",
596 "tsc", "msr", "pae", "mce",
597 "cx8", "apic", NULL, "sep",
598 "mtrr", "pge", "mca", "cmov",
599 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
600 NULL, "ds" /* Intel dts */, "acpi", "mmx",
601 "fxsr", "sse", "sse2", "ss",
602 "ht" /* Intel htt */, "tm", "ia64", "pbe",
603 },
bffd67b0 604 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 605 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 606 },
607 [FEAT_1_ECX] = {
2d5312da 608 .feat_names = {
16d2fcaa 609 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 610 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 611 "tm2", "ssse3", "cid", NULL,
612 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 613 NULL, "pcid", "dca", "sse4.1",
614 "sse4.2", "x2apic", "movbe", "popcnt",
2d5312da
EH		 615 "tsc-deadline", "aes", "xsave", "osxsave",
616 "avx", "f16c", "rdrand", "hypervisor",
617 },
bffd67b0 618 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 619 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 620 },
2d5312da
EH		 621 /* Feature names that are already defined on feature_name[] but
622 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
623 * names on feat_names below. They are copied automatically
624 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
625 */
bffd67b0 626 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 627 .feat_names = {
628 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
629 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
630 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
631 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
632 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 633 "nx", NULL, "mmxext", NULL /* mmx */,
634 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
635 NULL, "lm", "3dnowext", "3dnow",
2d5312da 636 },
bffd67b0 637 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 638 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 639 },
640 [FEAT_8000_0001_ECX] = {
2d5312da 641 .feat_names = {
fc7dfd20 642 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 643 "cr8legacy", "abm", "sse4a", "misalignsse",
644 "3dnowprefetch", "osvw", "ibs", "xop",
645 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 646 "fma4", "tce", NULL, "nodeid-msr",
647 NULL, "tbm", "topoext", "perfctr-core",
648 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 649 NULL, NULL, NULL, NULL,
650 },
bffd67b0 651 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 652 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 653 },
89e49c8b 654 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 655 .feat_names = {
656 NULL, NULL, "xstore", "xstore-en",
657 NULL, NULL, "xcrypt", "xcrypt-en",
658 "ace2", "ace2-en", "phe", "phe-en",
659 "pmm", "pmm-en", NULL, NULL,
660 NULL, NULL, NULL, NULL,
661 NULL, NULL, NULL, NULL,
662 NULL, NULL, NULL, NULL,
663 NULL, NULL, NULL, NULL,
664 },
89e49c8b 665 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 666 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 667 },
bffd67b0 668 [FEAT_KVM] = {
2d5312da 669 .feat_names = {
fc7dfd20
EH		 670 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
671 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
6976af66 672 NULL, "kvm-pv-tlb-flush", NULL, NULL,
2d5312da
EH		 673 NULL, NULL, NULL, NULL,
674 NULL, NULL, NULL, NULL,
675 NULL, NULL, NULL, NULL,
676 "kvmclock-stable-bit", NULL, NULL, NULL,
677 NULL, NULL, NULL, NULL,
678 },
bffd67b0 679 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 680 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 681 },
be777326
WL		 682 [FEAT_KVM_HINTS] = {
683 .feat_names = {
684 "kvm-hint-dedicated", NULL, NULL, NULL,
685 NULL, NULL, NULL, NULL,
686 NULL, NULL, NULL, NULL,
687 NULL, NULL, NULL, NULL,
688 NULL, NULL, NULL, NULL,
689 NULL, NULL, NULL, NULL,
690 NULL, NULL, NULL, NULL,
691 NULL, NULL, NULL, NULL,
692 },
693 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EDX,
694 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 695 /*
696 * KVM hints aren't auto-enabled by -cpu host, they need to be
697 * explicitly enabled in the command-line.
698 */
699 .no_autoenable_flags = ~0U,
be777326 700 },
c35bd19a 701 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 702 .feat_names = {
703 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
704 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
705 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
706 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
707 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
708 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
ba6a4fd9
VK		 709 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
710 NULL, NULL,
2d5312da
EH		 711 NULL, NULL, NULL, NULL,
712 NULL, NULL, NULL, NULL,
713 NULL, NULL, NULL, NULL,
714 NULL, NULL, NULL, NULL,
715 },
c35bd19a
EY		 716 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
717 },
718 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 719 .feat_names = {
720 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
721 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
722 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
723 NULL /* hv_create_port */, NULL /* hv_connect_port */,
724 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
725 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
726 NULL, NULL,
727 NULL, NULL, NULL, NULL,
728 NULL, NULL, NULL, NULL,
729 NULL, NULL, NULL, NULL,
730 NULL, NULL, NULL, NULL,
731 },
c35bd19a
EY		 732 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
733 },
734 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 735 .feat_names = {
736 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
737 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
738 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
739 NULL, NULL,
740 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
741 NULL, NULL, NULL, NULL,
742 NULL, NULL, NULL, NULL,
743 NULL, NULL, NULL, NULL,
744 NULL, NULL, NULL, NULL,
745 NULL, NULL, NULL, NULL,
746 },
c35bd19a
EY		 747 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
748 },
bffd67b0 749 [FEAT_SVM] = {
2d5312da 750 .feat_names = {
fc7dfd20
EH		 751 "npt", "lbrv", "svm-lock", "nrip-save",
752 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
753 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 754 "pfthreshold", NULL, NULL, NULL,
755 NULL, NULL, NULL, NULL,
756 NULL, NULL, NULL, NULL,
757 NULL, NULL, NULL, NULL,
758 NULL, NULL, NULL, NULL,
759 },
bffd67b0 760 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 761 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 762 },
763 [FEAT_7_0_EBX] = {
2d5312da 764 .feat_names = {
fc7dfd20 765 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 766 "hle", "avx2", NULL, "smep",
767 "bmi2", "erms", "invpcid", "rtm",
768 NULL, NULL, "mpx", NULL,
769 "avx512f", "avx512dq", "rdseed", "adx",
770 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 771 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 772 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 773 },
04d104b6
EH		 774 .cpuid_eax = 7,
775 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
776 .cpuid_reg = R_EBX,
37ce3522 777 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 778 },
f74eefe0 779 [FEAT_7_0_ECX] = {
2d5312da
EH		 780 .feat_names = {
781 NULL, "avx512vbmi", "umip", "pku",
aff9e6e4
YZ		 782 "ospke", NULL, "avx512vbmi2", NULL,
783 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
784 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 785 "la57", NULL, NULL, NULL,
2d5312da 786 NULL, NULL, "rdpid", NULL,
0da0fb06 787 NULL, "cldemote", NULL, NULL,
2d5312da
EH		 788 NULL, NULL, NULL, NULL,
789 },
f74eefe0
HH		 790 .cpuid_eax = 7,
791 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
792 .cpuid_reg = R_ECX,
793 .tcg_features = TCG_7_0_ECX_FEATURES,
794 },
95ea69fb
LK		 795 [FEAT_7_0_EDX] = {
796 .feat_names = {
797 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
798 NULL, NULL, NULL, NULL,
799 NULL, NULL, NULL, NULL,
800 NULL, NULL, NULL, NULL,
801 NULL, NULL, NULL, NULL,
802 NULL, NULL, NULL, NULL,
a2381f09 803 NULL, NULL, "spec-ctrl", NULL,
95ea69fb
LK		 804 NULL, NULL, NULL, NULL,
805 },
806 .cpuid_eax = 7,
807 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
808 .cpuid_reg = R_EDX,
809 .tcg_features = TCG_7_0_EDX_FEATURES,
810 },
303752a9 811 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 812 .feat_names = {
813 NULL, NULL, NULL, NULL,
814 NULL, NULL, NULL, NULL,
815 "invtsc", NULL, NULL, NULL,
816 NULL, NULL, NULL, NULL,
817 NULL, NULL, NULL, NULL,
818 NULL, NULL, NULL, NULL,
819 NULL, NULL, NULL, NULL,
820 NULL, NULL, NULL, NULL,
821 },
303752a9
MT		 822 .cpuid_eax = 0x80000007,
823 .cpuid_reg = R_EDX,
824 .tcg_features = TCG_APM_FEATURES,
825 .unmigratable_flags = CPUID_APM_INVTSC,
826 },
1b3420e1
EH		 827 [FEAT_8000_0008_EBX] = {
828 .feat_names = {
829 NULL, NULL, NULL, NULL,
830 NULL, NULL, NULL, NULL,
831 NULL, NULL, NULL, NULL,
832 "ibpb", NULL, NULL, NULL,
833 NULL, NULL, NULL, NULL,
834 NULL, NULL, NULL, NULL,
835 NULL, NULL, NULL, NULL,
836 NULL, NULL, NULL, NULL,
837 },
838 .cpuid_eax = 0x80000008,
839 .cpuid_reg = R_EBX,
840 .tcg_features = 0,
841 .unmigratable_flags = 0,
842 },
0bb0b2d2 843 [FEAT_XSAVE] = {
2d5312da
EH		 844 .feat_names = {
845 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
846 NULL, NULL, NULL, NULL,
847 NULL, NULL, NULL, NULL,
848 NULL, NULL, NULL, NULL,
849 NULL, NULL, NULL, NULL,
850 NULL, NULL, NULL, NULL,
851 NULL, NULL, NULL, NULL,
852 NULL, NULL, NULL, NULL,
853 },
0bb0b2d2
PB		 854 .cpuid_eax = 0xd,
855 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
856 .cpuid_reg = R_EAX,
c9cfe8f9 857 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 858 },
28b8e4d0 859 [FEAT_6_EAX] = {
2d5312da
EH		 860 .feat_names = {
861 NULL, NULL, "arat", NULL,
862 NULL, NULL, NULL, NULL,
863 NULL, NULL, NULL, NULL,
864 NULL, NULL, NULL, NULL,
865 NULL, NULL, NULL, NULL,
866 NULL, NULL, NULL, NULL,
867 NULL, NULL, NULL, NULL,
868 NULL, NULL, NULL, NULL,
869 },
28b8e4d0
JK		 870 .cpuid_eax = 6, .cpuid_reg = R_EAX,
871 .tcg_features = TCG_6_EAX_FEATURES,
872 },
96193c22
EH		 873 [FEAT_XSAVE_COMP_LO] = {
874 .cpuid_eax = 0xD,
875 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
876 .cpuid_reg = R_EAX,
877 .tcg_features = ~0U,
6fb2fff7
EH		 878 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
879 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
880 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
881 XSTATE_PKRU_MASK,
96193c22
EH		 882 },
883 [FEAT_XSAVE_COMP_HI] = {
884 .cpuid_eax = 0xD,
885 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
886 .cpuid_reg = R_EDX,
887 .tcg_features = ~0U,
888 },
5ef57876
EH		 889};
890
8e8aba50
EH		 891typedef struct X86RegisterInfo32 {
892 /* Name of register */
893 const char *name;
894 /* QAPI enum value register */
895 X86CPURegister32 qapi_enum;
896} X86RegisterInfo32;
897
898#define REGISTER(reg) \
5d371f41 899 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 900static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 901 REGISTER(EAX),
902 REGISTER(ECX),
903 REGISTER(EDX),
904 REGISTER(EBX),
905 REGISTER(ESP),
906 REGISTER(EBP),
907 REGISTER(ESI),
908 REGISTER(EDI),
909};
910#undef REGISTER
911
3f32bd21
RH		 912typedef struct ExtSaveArea {
913 uint32_t feature, bits;
914 uint32_t offset, size;
915} ExtSaveArea;
916
917static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 918 [XSTATE_FP_BIT] = {
919 /* x87 FP state component is always enabled if XSAVE is supported */
920 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
921 /* x87 state is in the legacy region of the XSAVE area */
922 .offset = 0,
923 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
924 },
925 [XSTATE_SSE_BIT] = {
926 /* SSE state component is always enabled if XSAVE is supported */
927 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
928 /* SSE state is in the legacy region of the XSAVE area */
929 .offset = 0,
930 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
931 },
cfc3b074
PB		 932 [XSTATE_YMM_BIT] =
933 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 934 .offset = offsetof(X86XSaveArea, avx_state),
935 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 936 [XSTATE_BNDREGS_BIT] =
937 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 938 .offset = offsetof(X86XSaveArea, bndreg_state),
939 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 940 [XSTATE_BNDCSR_BIT] =
941 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 942 .offset = offsetof(X86XSaveArea, bndcsr_state),
943 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 944 [XSTATE_OPMASK_BIT] =
945 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 946 .offset = offsetof(X86XSaveArea, opmask_state),
947 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 948 [XSTATE_ZMM_Hi256_BIT] =
949 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 950 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
951 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 952 [XSTATE_Hi16_ZMM_BIT] =
953 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 954 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
955 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 956 [XSTATE_PKRU_BIT] =
957 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 958 .offset = offsetof(X86XSaveArea, pkru_state),
959 .size = sizeof(XSavePKRU) },
2560f19f 960};
8e8aba50 961
1fda6198
EH		 962static uint32_t xsave_area_size(uint64_t mask)
963{
964 int i;
e3c9022b 965 uint64_t ret = 0;
1fda6198 966
e3c9022b 967 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 968 const ExtSaveArea *esa = &x86_ext_save_areas[i];
969 if ((mask >> i) & 1) {
970 ret = MAX(ret, esa->offset + esa->size);
971 }
972 }
973 return ret;
974}
975
d6dcc558
SAGDR		 976static inline bool accel_uses_host_cpuid(void)
977{
978 return kvm_enabled() || hvf_enabled();
979}
980
96193c22
EH		 981static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
982{
983 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
984 cpu->env.features[FEAT_XSAVE_COMP_LO];
985}
986
8b4beddc
EH		 987const char *get_register_name_32(unsigned int reg)
988{
31ccdde2 989 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 990 return NULL;
991 }
8e8aba50 992 return x86_reg_info_32[reg].name;
8b4beddc
EH		 993}
994
84f1b92f
EH		 995/*
996 * Returns the set of feature flags that are supported and migratable by
997 * QEMU, for a given FeatureWord.
998 */
999static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1000{
1001 FeatureWordInfo *wi = &feature_word_info[w];
1002 uint32_t r = 0;
1003 int i;
1004
1005 for (i = 0; i < 32; i++) {
1006 uint32_t f = 1U << i;
6fb2fff7
EH		 1007
1008 /* If the feature name is known, it is implicitly considered migratable,
1009 * unless it is explicitly set in unmigratable_flags */
1010 if ((wi->migratable_flags & f) ||
1011 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1012 r |= f;
84f1b92f 1013 }
84f1b92f
EH		 1014 }
1015 return r;
1016}
1017
bb44e0d1
JK		 1018void host_cpuid(uint32_t function, uint32_t count,
1019 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1020{
a1fd24af
AL		 1021 uint32_t vec[4];
1022
1023#ifdef __x86_64__
1024 asm volatile("cpuid"
1025 : "=a"(vec[0]), "=b"(vec[1]),
1026 "=c"(vec[2]), "=d"(vec[3])
1027 : "0"(function), "c"(count) : "cc");
c1f41226 1028#elif defined(__i386__)
a1fd24af
AL		 1029 asm volatile("pusha \n\t"
1030 "cpuid \n\t"
1031 "mov %%eax, 0(%2) \n\t"
1032 "mov %%ebx, 4(%2) \n\t"
1033 "mov %%ecx, 8(%2) \n\t"
1034 "mov %%edx, 12(%2) \n\t"
1035 "popa"
1036 : : "a"(function), "c"(count), "S"(vec)
1037 : "memory", "cc");
c1f41226
EH		 1038#else
1039 abort();
a1fd24af
AL		 1040#endif
1041
bdde476a 1042 if (eax)
a1fd24af 1043 *eax = vec[0];
bdde476a 1044 if (ebx)
a1fd24af 1045 *ebx = vec[1];
bdde476a 1046 if (ecx)
a1fd24af 1047 *ecx = vec[2];
bdde476a 1048 if (edx)
a1fd24af 1049 *edx = vec[3];
bdde476a 1050}
c6dc6f63 1051
20271d48
EH		 1052void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1053{
1054 uint32_t eax, ebx, ecx, edx;
1055
1056 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1057 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1058
1059 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1060 if (family) {
1061 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1062 }
1063 if (model) {
1064 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1065 }
1066 if (stepping) {
1067 *stepping = eax & 0x0F;
1068 }
1069}
1070
d940ee9b
EH		 1071/* CPU class name definitions: */
1072
d940ee9b
EH		 1073/* Return type name for a given CPU model name
1074 * Caller is responsible for freeing the returned string.
1075 */
1076static char *x86_cpu_type_name(const char *model_name)
1077{
1078 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1079}
1080
500050d1
AF		 1081static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1082{
d940ee9b 1083 ObjectClass *oc;
99193d8f 1084 char *typename = x86_cpu_type_name(cpu_model);
d940ee9b
EH		 1085 oc = object_class_by_name(typename);
1086 g_free(typename);
1087 return oc;
500050d1
AF		 1088}
1089
104494ea
IM		 1090static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1091{
1092 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1093 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1094 return g_strndup(class_name,
1095 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1096}
1097
d940ee9b 1098struct X86CPUDefinition {
c6dc6f63
AP		 1099 const char *name;
1100 uint32_t level;
90e4b0c3 1101 uint32_t xlevel;
99b88a17
IM		 1102 /* vendor is zero-terminated, 12 character ASCII string */
1103 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1104 int family;
1105 int model;
1106 int stepping;
0514ef2f 1107 FeatureWordArray features;
807e9869 1108 const char *model_id;
6aaeb054 1109 CPUCaches *cache_info;
d940ee9b 1110};
c6dc6f63 1111
9576de75 1112static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1113 {
1114 .name = "qemu64",
3046bb5d 1115 .level = 0xd,
99b88a17 1116 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 1117 .family = 6,
f8e6a11a 1118 .model = 6,
c6dc6f63 1119 .stepping = 3,
0514ef2f 1120 .features[FEAT_1_EDX] =
27861ecc 1121 PPRO_FEATURES |
c6dc6f63 1122 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1123 CPUID_PSE36,
0514ef2f 1124 .features[FEAT_1_ECX] =
6aa91e4a 1125 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1126 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1127 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1128 .features[FEAT_8000_0001_ECX] =
71195672 1129 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1130 .xlevel = 0x8000000A,
9cf2cc3d 1131 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1132 },
1133 {
1134 .name = "phenom",
1135 .level = 5,
99b88a17 1136 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1137 .family = 16,
1138 .model = 2,
1139 .stepping = 3,
b9fc20bc 1140 /* Missing: CPUID_HT */
0514ef2f 1141 .features[FEAT_1_EDX] =
27861ecc 1142 PPRO_FEATURES |
c6dc6f63 1143 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1144 CPUID_PSE36 | CPUID_VME,
0514ef2f 1145 .features[FEAT_1_ECX] =
27861ecc 1146 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1147 CPUID_EXT_POPCNT,
0514ef2f 1148 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1149 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1150 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1151 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1152 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1153 CPUID_EXT3_CR8LEG,
1154 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1155 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1156 .features[FEAT_8000_0001_ECX] =
27861ecc 1157 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1158 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1159 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1160 .features[FEAT_SVM] =
b9fc20bc 1161 CPUID_SVM_NPT,
c6dc6f63
AP		 1162 .xlevel = 0x8000001A,
1163 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1164 },
1165 {
1166 .name = "core2duo",
1167 .level = 10,
99b88a17 1168 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1169 .family = 6,
1170 .model = 15,
1171 .stepping = 11,
b9fc20bc 1172 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1173 .features[FEAT_1_EDX] =
27861ecc 1174 PPRO_FEATURES |
c6dc6f63 1175 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1176 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1177 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1178 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1179 .features[FEAT_1_ECX] =
27861ecc 1180 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1181 CPUID_EXT_CX16,
0514ef2f 1182 .features[FEAT_8000_0001_EDX] =
27861ecc 1183 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1184 .features[FEAT_8000_0001_ECX] =
27861ecc 1185 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 1186 .xlevel = 0x80000008,
1187 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1188 },
1189 {
1190 .name = "kvm64",
3046bb5d 1191 .level = 0xd,
99b88a17 1192 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1193 .family = 15,
1194 .model = 6,
1195 .stepping = 1,
b3a4f0b1 1196 /* Missing: CPUID_HT */
0514ef2f 1197 .features[FEAT_1_EDX] =
b3a4f0b1 1198 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1199 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1200 CPUID_PSE36,
1201 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1202 .features[FEAT_1_ECX] =
27861ecc 1203 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1204 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1205 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1206 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1207 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1208 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1209 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1210 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1211 .features[FEAT_8000_0001_ECX] =
27861ecc 1212 0,
c6dc6f63
AP		 1213 .xlevel = 0x80000008,
1214 .model_id = "Common KVM processor"
1215 },
c6dc6f63
AP		 1216 {
1217 .name = "qemu32",
1218 .level = 4,
99b88a17 1219 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1220 .family = 6,
f8e6a11a 1221 .model = 6,
c6dc6f63 1222 .stepping = 3,
0514ef2f 1223 .features[FEAT_1_EDX] =
27861ecc 1224 PPRO_FEATURES,
0514ef2f 1225 .features[FEAT_1_ECX] =
6aa91e4a 1226 CPUID_EXT_SSE3,
58012d66 1227 .xlevel = 0x80000004,
9cf2cc3d 1228 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1229 },
eafaf1e5
AP		 1230 {
1231 .name = "kvm32",
1232 .level = 5,
99b88a17 1233 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1234 .family = 15,
1235 .model = 6,
1236 .stepping = 1,
0514ef2f 1237 .features[FEAT_1_EDX] =
b3a4f0b1 1238 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1239 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1240 .features[FEAT_1_ECX] =
27861ecc 1241 CPUID_EXT_SSE3,
0514ef2f 1242 .features[FEAT_8000_0001_ECX] =
27861ecc 1243 0,
eafaf1e5
AP		 1244 .xlevel = 0x80000008,
1245 .model_id = "Common 32-bit KVM processor"
1246 },
c6dc6f63
AP		 1247 {
1248 .name = "coreduo",
1249 .level = 10,
99b88a17 1250 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1251 .family = 6,
1252 .model = 14,
1253 .stepping = 8,
b9fc20bc 1254 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1255 .features[FEAT_1_EDX] =
27861ecc 1256 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1257 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1258 CPUID_SS,
1259 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1260 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1261 .features[FEAT_1_ECX] =
e93abc14 1262 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1263 .features[FEAT_8000_0001_EDX] =
27861ecc 1264 CPUID_EXT2_NX,
c6dc6f63
AP		 1265 .xlevel = 0x80000008,
1266 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1267 },
1268 {
1269 .name = "486",
58012d66 1270 .level = 1,
99b88a17 1271 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1272 .family = 4,
b2a856d9 1273 .model = 8,
c6dc6f63 1274 .stepping = 0,
0514ef2f 1275 .features[FEAT_1_EDX] =
27861ecc 1276 I486_FEATURES,
c6dc6f63 1277 .xlevel = 0,
807e9869 1278 .model_id = "",
c6dc6f63
AP		 1279 },
1280 {
1281 .name = "pentium",
1282 .level = 1,
99b88a17 1283 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1284 .family = 5,
1285 .model = 4,
1286 .stepping = 3,
0514ef2f 1287 .features[FEAT_1_EDX] =
27861ecc 1288 PENTIUM_FEATURES,
c6dc6f63 1289 .xlevel = 0,
807e9869 1290 .model_id = "",
c6dc6f63
AP		 1291 },
1292 {
1293 .name = "pentium2",
1294 .level = 2,
99b88a17 1295 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1296 .family = 6,
1297 .model = 5,
1298 .stepping = 2,
0514ef2f 1299 .features[FEAT_1_EDX] =
27861ecc 1300 PENTIUM2_FEATURES,
c6dc6f63 1301 .xlevel = 0,
807e9869 1302 .model_id = "",
c6dc6f63
AP		 1303 },
1304 {
1305 .name = "pentium3",
3046bb5d 1306 .level = 3,
99b88a17 1307 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1308 .family = 6,
1309 .model = 7,
1310 .stepping = 3,
0514ef2f 1311 .features[FEAT_1_EDX] =
27861ecc 1312 PENTIUM3_FEATURES,
c6dc6f63 1313 .xlevel = 0,
807e9869 1314 .model_id = "",
c6dc6f63
AP		 1315 },
1316 {
1317 .name = "athlon",
1318 .level = 2,
99b88a17 1319 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1320 .family = 6,
1321 .model = 2,
1322 .stepping = 3,
0514ef2f 1323 .features[FEAT_1_EDX] =
27861ecc 1324 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 1325 CPUID_MCA,
0514ef2f 1326 .features[FEAT_8000_0001_EDX] =
60032ac0 1327 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 1328 .xlevel = 0x80000008,
9cf2cc3d 1329 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1330 },
1331 {
1332 .name = "n270",
3046bb5d 1333 .level = 10,
99b88a17 1334 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1335 .family = 6,
1336 .model = 28,
1337 .stepping = 2,
b9fc20bc 1338 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1339 .features[FEAT_1_EDX] =
27861ecc 1340 PPRO_FEATURES |
b9fc20bc
EH		 1341 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1342 CPUID_ACPI | CPUID_SS,
c6dc6f63 1343 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1344 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1345 * CPUID_EXT_XTPR */
0514ef2f 1346 .features[FEAT_1_ECX] =
27861ecc 1347 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1348 CPUID_EXT_MOVBE,
0514ef2f 1349 .features[FEAT_8000_0001_EDX] =
60032ac0 1350 CPUID_EXT2_NX,
0514ef2f 1351 .features[FEAT_8000_0001_ECX] =
27861ecc 1352 CPUID_EXT3_LAHF_LM,
3046bb5d 1353 .xlevel = 0x80000008,
c6dc6f63
AP		 1354 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1355 },
3eca4642
EH		 1356 {
1357 .name = "Conroe",
3046bb5d 1358 .level = 10,
99b88a17 1359 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1360 .family = 6,
ffce9ebb 1361 .model = 15,
3eca4642 1362 .stepping = 3,
0514ef2f 1363 .features[FEAT_1_EDX] =
b3a4f0b1 1364 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1365 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1366 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1367 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1368 CPUID_DE | CPUID_FP87,
0514ef2f 1369 .features[FEAT_1_ECX] =
27861ecc 1370 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1371 .features[FEAT_8000_0001_EDX] =
27861ecc 1372 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1373 .features[FEAT_8000_0001_ECX] =
27861ecc 1374 CPUID_EXT3_LAHF_LM,
3046bb5d 1375 .xlevel = 0x80000008,
3eca4642
EH		 1376 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1377 },
1378 {
1379 .name = "Penryn",
3046bb5d 1380 .level = 10,
99b88a17 1381 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1382 .family = 6,
ffce9ebb 1383 .model = 23,
3eca4642 1384 .stepping = 3,
0514ef2f 1385 .features[FEAT_1_EDX] =
b3a4f0b1 1386 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1387 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1388 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1389 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1390 CPUID_DE | CPUID_FP87,
0514ef2f 1391 .features[FEAT_1_ECX] =
27861ecc 1392 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1393 CPUID_EXT_SSE3,
0514ef2f 1394 .features[FEAT_8000_0001_EDX] =
27861ecc 1395 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1396 .features[FEAT_8000_0001_ECX] =
27861ecc 1397 CPUID_EXT3_LAHF_LM,
3046bb5d 1398 .xlevel = 0x80000008,
3eca4642
EH		 1399 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1400 },
1401 {
1402 .name = "Nehalem",
3046bb5d 1403 .level = 11,
99b88a17 1404 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1405 .family = 6,
ffce9ebb 1406 .model = 26,
3eca4642 1407 .stepping = 3,
0514ef2f 1408 .features[FEAT_1_EDX] =
b3a4f0b1 1409 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1410 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1411 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1412 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1413 CPUID_DE | CPUID_FP87,
0514ef2f 1414 .features[FEAT_1_ECX] =
27861ecc 1415 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1416 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1417 .features[FEAT_8000_0001_EDX] =
27861ecc 1418 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1419 .features[FEAT_8000_0001_ECX] =
27861ecc 1420 CPUID_EXT3_LAHF_LM,
3046bb5d 1421 .xlevel = 0x80000008,
3eca4642
EH		 1422 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1423 },
ac96c413
EH		 1424 {
1425 .name = "Nehalem-IBRS",
1426 .level = 11,
1427 .vendor = CPUID_VENDOR_INTEL,
1428 .family = 6,
1429 .model = 26,
1430 .stepping = 3,
1431 .features[FEAT_1_EDX] =
1432 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1433 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1434 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1435 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1436 CPUID_DE | CPUID_FP87,
1437 .features[FEAT_1_ECX] =
1438 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1439 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1440 .features[FEAT_7_0_EDX] =
1441 CPUID_7_0_EDX_SPEC_CTRL,
1442 .features[FEAT_8000_0001_EDX] =
1443 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1444 .features[FEAT_8000_0001_ECX] =
1445 CPUID_EXT3_LAHF_LM,
1446 .xlevel = 0x80000008,
1447 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1448 },
3eca4642
EH		 1449 {
1450 .name = "Westmere",
1451 .level = 11,
99b88a17 1452 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1453 .family = 6,
1454 .model = 44,
1455 .stepping = 1,
0514ef2f 1456 .features[FEAT_1_EDX] =
b3a4f0b1 1457 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1458 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1459 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1460 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1461 CPUID_DE | CPUID_FP87,
0514ef2f 1462 .features[FEAT_1_ECX] =
27861ecc 1463 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1464 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1465 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1466 .features[FEAT_8000_0001_EDX] =
27861ecc 1467 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1468 .features[FEAT_8000_0001_ECX] =
27861ecc 1469 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1470 .features[FEAT_6_EAX] =
1471 CPUID_6_EAX_ARAT,
3046bb5d 1472 .xlevel = 0x80000008,
3eca4642
EH		 1473 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1474 },
ac96c413
EH		 1475 {
1476 .name = "Westmere-IBRS",
1477 .level = 11,
1478 .vendor = CPUID_VENDOR_INTEL,
1479 .family = 6,
1480 .model = 44,
1481 .stepping = 1,
1482 .features[FEAT_1_EDX] =
1483 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1484 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1485 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1486 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1487 CPUID_DE | CPUID_FP87,
1488 .features[FEAT_1_ECX] =
1489 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1490 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1491 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1492 .features[FEAT_8000_0001_EDX] =
1493 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1494 .features[FEAT_8000_0001_ECX] =
1495 CPUID_EXT3_LAHF_LM,
1496 .features[FEAT_7_0_EDX] =
1497 CPUID_7_0_EDX_SPEC_CTRL,
1498 .features[FEAT_6_EAX] =
1499 CPUID_6_EAX_ARAT,
1500 .xlevel = 0x80000008,
1501 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1502 },
3eca4642
EH		 1503 {
1504 .name = "SandyBridge",
1505 .level = 0xd,
99b88a17 1506 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1507 .family = 6,
1508 .model = 42,
1509 .stepping = 1,
0514ef2f 1510 .features[FEAT_1_EDX] =
b3a4f0b1 1511 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1512 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1513 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1514 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1515 CPUID_DE | CPUID_FP87,
0514ef2f 1516 .features[FEAT_1_ECX] =
27861ecc 1517 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1518 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1519 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1520 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1521 CPUID_EXT_SSE3,
0514ef2f 1522 .features[FEAT_8000_0001_EDX] =
27861ecc 1523 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1524 CPUID_EXT2_SYSCALL,
0514ef2f 1525 .features[FEAT_8000_0001_ECX] =
27861ecc 1526 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1527 .features[FEAT_XSAVE] =
1528 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1529 .features[FEAT_6_EAX] =
1530 CPUID_6_EAX_ARAT,
3046bb5d 1531 .xlevel = 0x80000008,
3eca4642
EH		 1532 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1533 },
ac96c413
EH		 1534 {
1535 .name = "SandyBridge-IBRS",
1536 .level = 0xd,
1537 .vendor = CPUID_VENDOR_INTEL,
1538 .family = 6,
1539 .model = 42,
1540 .stepping = 1,
1541 .features[FEAT_1_EDX] =
1542 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1543 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1544 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1545 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1546 CPUID_DE | CPUID_FP87,
1547 .features[FEAT_1_ECX] =
1548 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1549 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1550 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1551 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1552 CPUID_EXT_SSE3,
1553 .features[FEAT_8000_0001_EDX] =
1554 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1555 CPUID_EXT2_SYSCALL,
1556 .features[FEAT_8000_0001_ECX] =
1557 CPUID_EXT3_LAHF_LM,
1558 .features[FEAT_7_0_EDX] =
1559 CPUID_7_0_EDX_SPEC_CTRL,
1560 .features[FEAT_XSAVE] =
1561 CPUID_XSAVE_XSAVEOPT,
1562 .features[FEAT_6_EAX] =
1563 CPUID_6_EAX_ARAT,
1564 .xlevel = 0x80000008,
1565 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1566 },
2f9ac42a
PB		 1567 {
1568 .name = "IvyBridge",
1569 .level = 0xd,
1570 .vendor = CPUID_VENDOR_INTEL,
1571 .family = 6,
1572 .model = 58,
1573 .stepping = 9,
1574 .features[FEAT_1_EDX] =
1575 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1576 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1577 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1578 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1579 CPUID_DE | CPUID_FP87,
1580 .features[FEAT_1_ECX] =
1581 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1582 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1583 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1584 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1585 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1586 .features[FEAT_7_0_EBX] =
1587 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1588 CPUID_7_0_EBX_ERMS,
1589 .features[FEAT_8000_0001_EDX] =
1590 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1591 CPUID_EXT2_SYSCALL,
1592 .features[FEAT_8000_0001_ECX] =
1593 CPUID_EXT3_LAHF_LM,
1594 .features[FEAT_XSAVE] =
1595 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1596 .features[FEAT_6_EAX] =
1597 CPUID_6_EAX_ARAT,
3046bb5d 1598 .xlevel = 0x80000008,
2f9ac42a
PB		 1599 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1600 },
ac96c413
EH		 1601 {
1602 .name = "IvyBridge-IBRS",
1603 .level = 0xd,
1604 .vendor = CPUID_VENDOR_INTEL,
1605 .family = 6,
1606 .model = 58,
1607 .stepping = 9,
1608 .features[FEAT_1_EDX] =
1609 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1610 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1611 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1612 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1613 CPUID_DE | CPUID_FP87,
1614 .features[FEAT_1_ECX] =
1615 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1616 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1617 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1618 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1619 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1620 .features[FEAT_7_0_EBX] =
1621 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1622 CPUID_7_0_EBX_ERMS,
1623 .features[FEAT_8000_0001_EDX] =
1624 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1625 CPUID_EXT2_SYSCALL,
1626 .features[FEAT_8000_0001_ECX] =
1627 CPUID_EXT3_LAHF_LM,
1628 .features[FEAT_7_0_EDX] =
1629 CPUID_7_0_EDX_SPEC_CTRL,
1630 .features[FEAT_XSAVE] =
1631 CPUID_XSAVE_XSAVEOPT,
1632 .features[FEAT_6_EAX] =
1633 CPUID_6_EAX_ARAT,
1634 .xlevel = 0x80000008,
1635 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
1636 },
37507094 1637 {
a356850b
EH		 1638 .name = "Haswell-noTSX",
1639 .level = 0xd,
1640 .vendor = CPUID_VENDOR_INTEL,
1641 .family = 6,
1642 .model = 60,
1643 .stepping = 1,
1644 .features[FEAT_1_EDX] =
1645 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1646 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1647 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1648 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1649 CPUID_DE | CPUID_FP87,
1650 .features[FEAT_1_ECX] =
1651 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1652 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1653 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1654 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1655 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1656 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1657 .features[FEAT_8000_0001_EDX] =
1658 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1659 CPUID_EXT2_SYSCALL,
1660 .features[FEAT_8000_0001_ECX] =
becb6667 1661 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1662 .features[FEAT_7_0_EBX] =
1663 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1664 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1665 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1666 .features[FEAT_XSAVE] =
1667 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1668 .features[FEAT_6_EAX] =
1669 CPUID_6_EAX_ARAT,
3046bb5d 1670 .xlevel = 0x80000008,
a356850b 1671 .model_id = "Intel Core Processor (Haswell, no TSX)",
ac96c413
EH		 1672 },
1673 {
1674 .name = "Haswell-noTSX-IBRS",
1675 .level = 0xd,
1676 .vendor = CPUID_VENDOR_INTEL,
1677 .family = 6,
1678 .model = 60,
1679 .stepping = 1,
1680 .features[FEAT_1_EDX] =
1681 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1682 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1683 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1684 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1685 CPUID_DE | CPUID_FP87,
1686 .features[FEAT_1_ECX] =
1687 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1688 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1689 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1690 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1691 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1692 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1693 .features[FEAT_8000_0001_EDX] =
1694 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1695 CPUID_EXT2_SYSCALL,
1696 .features[FEAT_8000_0001_ECX] =
1697 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1698 .features[FEAT_7_0_EDX] =
1699 CPUID_7_0_EDX_SPEC_CTRL,
1700 .features[FEAT_7_0_EBX] =
1701 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1702 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1703 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1704 .features[FEAT_XSAVE] =
1705 CPUID_XSAVE_XSAVEOPT,
1706 .features[FEAT_6_EAX] =
1707 CPUID_6_EAX_ARAT,
1708 .xlevel = 0x80000008,
1709 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
1710 },
1711 {
37507094
EH		 1712 .name = "Haswell",
1713 .level = 0xd,
99b88a17 1714 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1715 .family = 6,
1716 .model = 60,
ec56a4a7 1717 .stepping = 4,
0514ef2f 1718 .features[FEAT_1_EDX] =
b3a4f0b1 1719 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1720 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1721 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1722 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1723 CPUID_DE | CPUID_FP87,
0514ef2f 1724 .features[FEAT_1_ECX] =
27861ecc 1725 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1726 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1727 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1728 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1729 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1730 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1731 .features[FEAT_8000_0001_EDX] =
27861ecc 1732 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1733 CPUID_EXT2_SYSCALL,
0514ef2f 1734 .features[FEAT_8000_0001_ECX] =
becb6667 1735 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1736 .features[FEAT_7_0_EBX] =
27861ecc 1737 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1738 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1739 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1740 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1741 .features[FEAT_XSAVE] =
1742 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1743 .features[FEAT_6_EAX] =
1744 CPUID_6_EAX_ARAT,
3046bb5d 1745 .xlevel = 0x80000008,
37507094
EH		 1746 .model_id = "Intel Core Processor (Haswell)",
1747 },
ac96c413
EH		 1748 {
1749 .name = "Haswell-IBRS",
1750 .level = 0xd,
1751 .vendor = CPUID_VENDOR_INTEL,
1752 .family = 6,
1753 .model = 60,
1754 .stepping = 4,
1755 .features[FEAT_1_EDX] =
1756 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1757 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1758 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1759 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1760 CPUID_DE | CPUID_FP87,
1761 .features[FEAT_1_ECX] =
1762 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1763 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1764 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1765 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1766 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1767 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1768 .features[FEAT_8000_0001_EDX] =
1769 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1770 CPUID_EXT2_SYSCALL,
1771 .features[FEAT_8000_0001_ECX] =
1772 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1773 .features[FEAT_7_0_EDX] =
1774 CPUID_7_0_EDX_SPEC_CTRL,
1775 .features[FEAT_7_0_EBX] =
1776 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1777 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1778 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1779 CPUID_7_0_EBX_RTM,
1780 .features[FEAT_XSAVE] =
1781 CPUID_XSAVE_XSAVEOPT,
1782 .features[FEAT_6_EAX] =
1783 CPUID_6_EAX_ARAT,
1784 .xlevel = 0x80000008,
1785 .model_id = "Intel Core Processor (Haswell, IBRS)",
1786 },
a356850b
EH		 1787 {
1788 .name = "Broadwell-noTSX",
1789 .level = 0xd,
1790 .vendor = CPUID_VENDOR_INTEL,
1791 .family = 6,
1792 .model = 61,
1793 .stepping = 2,
1794 .features[FEAT_1_EDX] =
1795 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1796 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1797 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1798 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1799 CPUID_DE | CPUID_FP87,
1800 .features[FEAT_1_ECX] =
1801 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1802 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1803 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1804 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1805 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1806 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1807 .features[FEAT_8000_0001_EDX] =
1808 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1809 CPUID_EXT2_SYSCALL,
1810 .features[FEAT_8000_0001_ECX] =
becb6667 1811 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1812 .features[FEAT_7_0_EBX] =
1813 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1814 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1815 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1816 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1817 CPUID_7_0_EBX_SMAP,
1818 .features[FEAT_XSAVE] =
1819 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1820 .features[FEAT_6_EAX] =
1821 CPUID_6_EAX_ARAT,
3046bb5d 1822 .xlevel = 0x80000008,
a356850b
EH		 1823 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1824 },
ac96c413
EH		 1825 {
1826 .name = "Broadwell-noTSX-IBRS",
1827 .level = 0xd,
1828 .vendor = CPUID_VENDOR_INTEL,
1829 .family = 6,
1830 .model = 61,
1831 .stepping = 2,
1832 .features[FEAT_1_EDX] =
1833 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1834 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1835 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1836 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1837 CPUID_DE | CPUID_FP87,
1838 .features[FEAT_1_ECX] =
1839 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1840 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1841 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1842 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1843 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1844 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1845 .features[FEAT_8000_0001_EDX] =
1846 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1847 CPUID_EXT2_SYSCALL,
1848 .features[FEAT_8000_0001_ECX] =
1849 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1850 .features[FEAT_7_0_EDX] =
1851 CPUID_7_0_EDX_SPEC_CTRL,
1852 .features[FEAT_7_0_EBX] =
1853 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1854 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1855 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1856 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1857 CPUID_7_0_EBX_SMAP,
1858 .features[FEAT_XSAVE] =
1859 CPUID_XSAVE_XSAVEOPT,
1860 .features[FEAT_6_EAX] =
1861 CPUID_6_EAX_ARAT,
1862 .xlevel = 0x80000008,
1863 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
1864 },
ece01354
EH		 1865 {
1866 .name = "Broadwell",
1867 .level = 0xd,
1868 .vendor = CPUID_VENDOR_INTEL,
1869 .family = 6,
1870 .model = 61,
1871 .stepping = 2,
1872 .features[FEAT_1_EDX] =
b3a4f0b1 1873 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1874 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1875 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1876 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1877 CPUID_DE | CPUID_FP87,
1878 .features[FEAT_1_ECX] =
1879 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1880 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1881 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1882 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1883 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1884 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1885 .features[FEAT_8000_0001_EDX] =
1886 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1887 CPUID_EXT2_SYSCALL,
1888 .features[FEAT_8000_0001_ECX] =
becb6667 1889 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1890 .features[FEAT_7_0_EBX] =
1891 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1892 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1893 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1894 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1895 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1896 .features[FEAT_XSAVE] =
1897 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1898 .features[FEAT_6_EAX] =
1899 CPUID_6_EAX_ARAT,
3046bb5d 1900 .xlevel = 0x80000008,
ece01354
EH		 1901 .model_id = "Intel Core Processor (Broadwell)",
1902 },
ac96c413
EH		 1903 {
1904 .name = "Broadwell-IBRS",
1905 .level = 0xd,
1906 .vendor = CPUID_VENDOR_INTEL,
1907 .family = 6,
1908 .model = 61,
1909 .stepping = 2,
1910 .features[FEAT_1_EDX] =
1911 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1912 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1913 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1914 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1915 CPUID_DE | CPUID_FP87,
1916 .features[FEAT_1_ECX] =
1917 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1918 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1919 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1920 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1921 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1922 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1923 .features[FEAT_8000_0001_EDX] =
1924 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1925 CPUID_EXT2_SYSCALL,
1926 .features[FEAT_8000_0001_ECX] =
1927 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1928 .features[FEAT_7_0_EDX] =
1929 CPUID_7_0_EDX_SPEC_CTRL,
1930 .features[FEAT_7_0_EBX] =
1931 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1932 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1933 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1934 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1935 CPUID_7_0_EBX_SMAP,
1936 .features[FEAT_XSAVE] =
1937 CPUID_XSAVE_XSAVEOPT,
1938 .features[FEAT_6_EAX] =
1939 CPUID_6_EAX_ARAT,
1940 .xlevel = 0x80000008,
1941 .model_id = "Intel Core Processor (Broadwell, IBRS)",
1942 },
f6f949e9
EH		 1943 {
1944 .name = "Skylake-Client",
1945 .level = 0xd,
1946 .vendor = CPUID_VENDOR_INTEL,
1947 .family = 6,
1948 .model = 94,
1949 .stepping = 3,
1950 .features[FEAT_1_EDX] =
1951 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1952 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1953 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1954 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1955 CPUID_DE | CPUID_FP87,
1956 .features[FEAT_1_ECX] =
1957 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1958 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1959 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1960 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1961 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1962 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1963 .features[FEAT_8000_0001_EDX] =
1964 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1965 CPUID_EXT2_SYSCALL,
1966 .features[FEAT_8000_0001_ECX] =
1967 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1968 .features[FEAT_7_0_EBX] =
1969 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1970 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1971 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1972 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1973 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1974 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 1975 * including v4.1 to v4.12).
f6f949e9
EH		 1976 * KVM doesn't yet expose any XSAVES state save component,
1977 * and the only one defined in Skylake (processor tracing)
1978 * probably will block migration anyway.
1979 */
1980 .features[FEAT_XSAVE] =
1981 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1982 CPUID_XSAVE_XGETBV1,
1983 .features[FEAT_6_EAX] =
1984 CPUID_6_EAX_ARAT,
1985 .xlevel = 0x80000008,
1986 .model_id = "Intel Core Processor (Skylake)",
1987 },
ac96c413
EH		 1988 {
1989 .name = "Skylake-Client-IBRS",
1990 .level = 0xd,
1991 .vendor = CPUID_VENDOR_INTEL,
1992 .family = 6,
1993 .model = 94,
1994 .stepping = 3,
1995 .features[FEAT_1_EDX] =
1996 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1997 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1998 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1999 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2000 CPUID_DE | CPUID_FP87,
2001 .features[FEAT_1_ECX] =
2002 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2003 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2004 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2005 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2006 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2007 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2008 .features[FEAT_8000_0001_EDX] =
2009 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2010 CPUID_EXT2_SYSCALL,
2011 .features[FEAT_8000_0001_ECX] =
2012 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2013 .features[FEAT_7_0_EDX] =
2014 CPUID_7_0_EDX_SPEC_CTRL,
2015 .features[FEAT_7_0_EBX] =
2016 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2017 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2018 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2019 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2020 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
2021 /* Missing: XSAVES (not supported by some Linux versions,
2022 * including v4.1 to v4.12).
2023 * KVM doesn't yet expose any XSAVES state save component,
2024 * and the only one defined in Skylake (processor tracing)
2025 * probably will block migration anyway.
2026 */
2027 .features[FEAT_XSAVE] =
2028 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2029 CPUID_XSAVE_XGETBV1,
2030 .features[FEAT_6_EAX] =
2031 CPUID_6_EAX_ARAT,
2032 .xlevel = 0x80000008,
2033 .model_id = "Intel Core Processor (Skylake, IBRS)",
2034 },
53f9a6f4
BF		 2035 {
2036 .name = "Skylake-Server",
2037 .level = 0xd,
2038 .vendor = CPUID_VENDOR_INTEL,
2039 .family = 6,
2040 .model = 85,
2041 .stepping = 4,
2042 .features[FEAT_1_EDX] =
2043 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2044 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2045 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2046 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2047 CPUID_DE | CPUID_FP87,
2048 .features[FEAT_1_ECX] =
2049 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2050 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2051 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2052 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2053 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2054 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2055 .features[FEAT_8000_0001_EDX] =
2056 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2057 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2058 .features[FEAT_8000_0001_ECX] =
2059 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2060 .features[FEAT_7_0_EBX] =
2061 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2062 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2063 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2064 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2065 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2066 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2067 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2068 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
53f9a6f4
BF		 2069 /* Missing: XSAVES (not supported by some Linux versions,
2070 * including v4.1 to v4.12).
2071 * KVM doesn't yet expose any XSAVES state save component,
2072 * and the only one defined in Skylake (processor tracing)
2073 * probably will block migration anyway.
2074 */
2075 .features[FEAT_XSAVE] =
2076 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2077 CPUID_XSAVE_XGETBV1,
2078 .features[FEAT_6_EAX] =
2079 CPUID_6_EAX_ARAT,
2080 .xlevel = 0x80000008,
2081 .model_id = "Intel Xeon Processor (Skylake)",
2082 },
ac96c413
EH		 2083 {
2084 .name = "Skylake-Server-IBRS",
2085 .level = 0xd,
2086 .vendor = CPUID_VENDOR_INTEL,
2087 .family = 6,
2088 .model = 85,
2089 .stepping = 4,
2090 .features[FEAT_1_EDX] =
2091 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2092 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2093 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2094 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2095 CPUID_DE | CPUID_FP87,
2096 .features[FEAT_1_ECX] =
2097 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2098 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2099 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2100 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2101 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2102 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2103 .features[FEAT_8000_0001_EDX] =
2104 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2105 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2106 .features[FEAT_8000_0001_ECX] =
2107 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2108 .features[FEAT_7_0_EDX] =
2109 CPUID_7_0_EDX_SPEC_CTRL,
2110 .features[FEAT_7_0_EBX] =
2111 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2112 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2113 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2114 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2115 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2116 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2117 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2118 CPUID_7_0_EBX_AVX512VL,
2119 /* Missing: XSAVES (not supported by some Linux versions,
2120 * including v4.1 to v4.12).
2121 * KVM doesn't yet expose any XSAVES state save component,
2122 * and the only one defined in Skylake (processor tracing)
2123 * probably will block migration anyway.
2124 */
2125 .features[FEAT_XSAVE] =
2126 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2127 CPUID_XSAVE_XGETBV1,
2128 .features[FEAT_6_EAX] =
2129 CPUID_6_EAX_ARAT,
2130 .xlevel = 0x80000008,
2131 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2132 },
a1849515
BF		 2133 {
2134 .name = "KnightsMill",
2135 .level = 0xd,
2136 .vendor = CPUID_VENDOR_INTEL,
2137 .family = 6,
2138 .model = 133,
2139 .stepping = 0,
2140 .features[FEAT_1_EDX] =
2141 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2142 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2143 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2144 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2145 CPUID_PSE | CPUID_DE | CPUID_FP87,
2146 .features[FEAT_1_ECX] =
2147 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2148 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2149 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2150 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2151 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2152 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2153 .features[FEAT_8000_0001_EDX] =
2154 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2155 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2156 .features[FEAT_8000_0001_ECX] =
2157 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2158 .features[FEAT_7_0_EBX] =
2159 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2160 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2161 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2162 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2163 CPUID_7_0_EBX_AVX512ER,
2164 .features[FEAT_7_0_ECX] =
2165 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2166 .features[FEAT_7_0_EDX] =
2167 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2168 .features[FEAT_XSAVE] =
2169 CPUID_XSAVE_XSAVEOPT,
2170 .features[FEAT_6_EAX] =
2171 CPUID_6_EAX_ARAT,
2172 .xlevel = 0x80000008,
2173 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2174 },
3eca4642
EH		 2175 {
2176 .name = "Opteron_G1",
2177 .level = 5,
99b88a17 2178 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2179 .family = 15,
2180 .model = 6,
2181 .stepping = 1,
0514ef2f 2182 .features[FEAT_1_EDX] =
b3a4f0b1 2183 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2184 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2185 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2186 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2187 CPUID_DE | CPUID_FP87,
0514ef2f 2188 .features[FEAT_1_ECX] =
27861ecc 2189 CPUID_EXT_SSE3,
0514ef2f 2190 .features[FEAT_8000_0001_EDX] =
2a923a29 2191 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 2192 .xlevel = 0x80000008,
2193 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2194 },
2195 {
2196 .name = "Opteron_G2",
2197 .level = 5,
99b88a17 2198 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2199 .family = 15,
2200 .model = 6,
2201 .stepping = 1,
0514ef2f 2202 .features[FEAT_1_EDX] =
b3a4f0b1 2203 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2204 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2205 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2206 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2207 CPUID_DE | CPUID_FP87,
0514ef2f 2208 .features[FEAT_1_ECX] =
27861ecc 2209 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 2210 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2211 .features[FEAT_8000_0001_EDX] =
2a923a29 2212 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2213 .features[FEAT_8000_0001_ECX] =
27861ecc 2214 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2215 .xlevel = 0x80000008,
2216 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2217 },
2218 {
2219 .name = "Opteron_G3",
2220 .level = 5,
99b88a17 2221 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 2222 .family = 16,
2223 .model = 2,
2224 .stepping = 3,
0514ef2f 2225 .features[FEAT_1_EDX] =
b3a4f0b1 2226 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2227 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2228 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2229 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2230 CPUID_DE | CPUID_FP87,
0514ef2f 2231 .features[FEAT_1_ECX] =
27861ecc 2232 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 2233 CPUID_EXT_SSE3,
33b5e8c0 2234 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2235 .features[FEAT_8000_0001_EDX] =
2a923a29 2236 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2237 .features[FEAT_8000_0001_ECX] =
27861ecc 2238 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 2239 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2240 .xlevel = 0x80000008,
2241 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2242 },
2243 {
2244 .name = "Opteron_G4",
2245 .level = 0xd,
99b88a17 2246 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2247 .family = 21,
2248 .model = 1,
2249 .stepping = 2,
0514ef2f 2250 .features[FEAT_1_EDX] =
b3a4f0b1 2251 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2252 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2253 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2254 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2255 CPUID_DE | CPUID_FP87,
0514ef2f 2256 .features[FEAT_1_ECX] =
27861ecc 2257 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2258 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2259 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2260 CPUID_EXT_SSE3,
33b5e8c0 2261 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2262 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 2263 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2264 CPUID_EXT2_SYSCALL,
0514ef2f 2265 .features[FEAT_8000_0001_ECX] =
27861ecc 2266 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2267 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2268 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2269 CPUID_EXT3_LAHF_LM,
0bb0b2d2 2270 /* no xsaveopt! */
3eca4642
EH		 2271 .xlevel = 0x8000001A,
2272 .model_id = "AMD Opteron 62xx class CPU",
2273 },
021941b9
AP		 2274 {
2275 .name = "Opteron_G5",
2276 .level = 0xd,
99b88a17 2277 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 2278 .family = 21,
2279 .model = 2,
2280 .stepping = 0,
0514ef2f 2281 .features[FEAT_1_EDX] =
b3a4f0b1 2282 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2283 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2284 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2285 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2286 CPUID_DE | CPUID_FP87,
0514ef2f 2287 .features[FEAT_1_ECX] =
27861ecc 2288 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 2289 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2290 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2291 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 2292 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2293 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 2294 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2295 CPUID_EXT2_SYSCALL,
0514ef2f 2296 .features[FEAT_8000_0001_ECX] =
27861ecc 2297 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2298 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2299 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2300 CPUID_EXT3_LAHF_LM,
0bb0b2d2 2301 /* no xsaveopt! */
021941b9
AP		 2302 .xlevel = 0x8000001A,
2303 .model_id = "AMD Opteron 63xx class CPU",
2304 },
2e2efc7d
BS		 2305 {
2306 .name = "EPYC",
2307 .level = 0xd,
2308 .vendor = CPUID_VENDOR_AMD,
2309 .family = 23,
2310 .model = 1,
2311 .stepping = 2,
2312 .features[FEAT_1_EDX] =
2313 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2314 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2315 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2316 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2317 CPUID_VME | CPUID_FP87,
2318 .features[FEAT_1_ECX] =
2319 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2320 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2321 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2322 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2323 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2324 .features[FEAT_8000_0001_EDX] =
2325 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2326 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2327 CPUID_EXT2_SYSCALL,
2328 .features[FEAT_8000_0001_ECX] =
2329 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2330 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2331 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2332 .features[FEAT_7_0_EBX] =
2333 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2334 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2335 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2336 CPUID_7_0_EBX_SHA_NI,
2337 /* Missing: XSAVES (not supported by some Linux versions,
2338 * including v4.1 to v4.12).
2339 * KVM doesn't yet expose any XSAVES state save component.
2340 */
2341 .features[FEAT_XSAVE] =
2342 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2343 CPUID_XSAVE_XGETBV1,
2344 .features[FEAT_6_EAX] =
2345 CPUID_6_EAX_ARAT,
2346 .xlevel = 0x8000000A,
2347 .model_id = "AMD EPYC Processor",
2348 },
6cfbc54e
EH		 2349 {
2350 .name = "EPYC-IBPB",
2351 .level = 0xd,
2352 .vendor = CPUID_VENDOR_AMD,
2353 .family = 23,
2354 .model = 1,
2355 .stepping = 2,
2356 .features[FEAT_1_EDX] =
2357 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2358 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2359 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2360 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2361 CPUID_VME | CPUID_FP87,
2362 .features[FEAT_1_ECX] =
2363 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2364 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2365 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2366 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2367 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2368 .features[FEAT_8000_0001_EDX] =
2369 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2370 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2371 CPUID_EXT2_SYSCALL,
2372 .features[FEAT_8000_0001_ECX] =
2373 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2374 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2375 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2376 .features[FEAT_8000_0008_EBX] =
2377 CPUID_8000_0008_EBX_IBPB,
2378 .features[FEAT_7_0_EBX] =
2379 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2380 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2381 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2382 CPUID_7_0_EBX_SHA_NI,
2383 /* Missing: XSAVES (not supported by some Linux versions,
2384 * including v4.1 to v4.12).
2385 * KVM doesn't yet expose any XSAVES state save component.
2386 */
2387 .features[FEAT_XSAVE] =
2388 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2389 CPUID_XSAVE_XGETBV1,
2390 .features[FEAT_6_EAX] =
2391 CPUID_6_EAX_ARAT,
2392 .xlevel = 0x8000000A,
2393 .model_id = "AMD EPYC Processor (with IBPB)",
2394 },
c6dc6f63
AP		 2395};
2396
5114e842
EH		 2397typedef struct PropValue {
2398 const char *prop, *value;
2399} PropValue;
2400
2401/* KVM-specific features that are automatically added/removed
2402 * from all CPU models when KVM is enabled.
2403 */
2404static PropValue kvm_default_props[] = {
2405 { "kvmclock", "on" },
2406 { "kvm-nopiodelay", "on" },
2407 { "kvm-asyncpf", "on" },
2408 { "kvm-steal-time", "on" },
2409 { "kvm-pv-eoi", "on" },
2410 { "kvmclock-stable-bit", "on" },
2411 { "x2apic", "on" },
2412 { "acpi", "off" },
2413 { "monitor", "off" },
2414 { "svm", "off" },
2415 { NULL, NULL },
2416};
2417
04d99c3c
EH		 2418/* TCG-specific defaults that override all CPU models when using TCG
2419 */
2420static PropValue tcg_default_props[] = {
2421 { "vme", "off" },
2422 { NULL, NULL },
2423};
2424
2425
5114e842
EH		 2426void x86_cpu_change_kvm_default(const char *prop, const char *value)
2427{
2428 PropValue *pv;
2429 for (pv = kvm_default_props; pv->prop; pv++) {
2430 if (!strcmp(pv->prop, prop)) {
2431 pv->value = value;
2432 break;
2433 }
2434 }
2435
2436 /* It is valid to call this function only for properties that
2437 * are already present in the kvm_default_props table.
2438 */
2439 assert(pv->prop);
2440}
2441
4d1b279b
EH		 2442static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2443 bool migratable_only);
2444
40bfe48f
HZ		 2445static bool lmce_supported(void)
2446{
c62f2630 2447 uint64_t mce_cap = 0;
40bfe48f 2448
c62f2630 2449#ifdef CONFIG_KVM
40bfe48f
HZ		 2450 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
2451 return false;
2452 }
c62f2630 2453#endif
40bfe48f
HZ		 2454
2455 return !!(mce_cap & MCG_LMCE_P);
2456}
2457
7d8050b5
EH		 2458#define CPUID_MODEL_ID_SZ 48
2459
2460/**
2461 * cpu_x86_fill_model_id:
2462 * Get CPUID model ID string from host CPU.
2463 *
2464 * @str should have at least CPUID_MODEL_ID_SZ bytes
2465 *
2466 * The function does NOT add a null terminator to the string
2467 * automatically.
2468 */
c6dc6f63
AP		 2469static int cpu_x86_fill_model_id(char *str)
2470{
2471 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2472 int i;
2473
2474 for (i = 0; i < 3; i++) {
2475 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
2476 memcpy(str + i * 16 + 0, &eax, 4);
2477 memcpy(str + i * 16 + 4, &ebx, 4);
2478 memcpy(str + i * 16 + 8, &ecx, 4);
2479 memcpy(str + i * 16 + 12, &edx, 4);
2480 }
2481 return 0;
2482}
2483
c62f2630 2484static Property max_x86_cpu_properties[] = {
120eee7d 2485 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 2486 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 2487 DEFINE_PROP_END_OF_LIST()
2488};
2489
c62f2630 2490static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 2491{
84f1b92f 2492 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 2493 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 2494
f48c8837 2495 xcc->ordering = 9;
6e746f30 2496
ee465a3e 2497 xcc->model_description =
c62f2630 2498 "Enables all features supported by the accelerator in the current host";
d940ee9b 2499
c62f2630 2500 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 2501}
2502
0bacd8b3
EH		 2503static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
2504
c62f2630 2505static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 2506{
2507 X86CPU *cpu = X86_CPU(obj);
2508 CPUX86State *env = &cpu->env;
2509 KVMState *s = kvm_state;
d940ee9b 2510
4d1b279b
EH		 2511 /* We can't fill the features array here because we don't know yet if
2512 * "migratable" is true or false.
2513 */
44bd8e53 2514 cpu->max_features = true;
4d1b279b 2515
d6dcc558 2516 if (accel_uses_host_cpuid()) {
bd182022
EH		 2517 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
2518 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
2519 int family, model, stepping;
d6dcc558
SAGDR		 2520 X86CPUDefinition host_cpudef = { };
2521 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2522
2523 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
2524 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
0bacd8b3 2525
bd182022 2526 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 2527
bd182022 2528 cpu_x86_fill_model_id(model_id);
0bacd8b3 2529
bd182022
EH		 2530 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
2531 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
2532 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
2533 object_property_set_int(OBJECT(cpu), stepping, "stepping",
2534 &error_abort);
2535 object_property_set_str(OBJECT(cpu), model_id, "model-id",
2536 &error_abort);
0bacd8b3 2537
d6dcc558
SAGDR		 2538 if (kvm_enabled()) {
2539 env->cpuid_min_level =
2540 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
2541 env->cpuid_min_xlevel =
2542 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
2543 env->cpuid_min_xlevel2 =
2544 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2545 } else {
2546 env->cpuid_min_level =
2547 hvf_get_supported_cpuid(0x0, 0, R_EAX);
2548 env->cpuid_min_xlevel =
2549 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
2550 env->cpuid_min_xlevel2 =
2551 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
2552 }
40bfe48f
HZ		 2553
2554 if (lmce_supported()) {
2555 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
2556 }
6900d1cc
EH		 2557 } else {
2558 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
2559 "vendor", &error_abort);
2560 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
2561 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
2562 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
2563 object_property_set_str(OBJECT(cpu),
2564 "QEMU TCG CPU version " QEMU_HW_VERSION,
2565 "model-id", &error_abort);
e4356010 2566 }
2a573259 2567
d940ee9b 2568 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 2569}
2570
c62f2630
EH		 2571static const TypeInfo max_x86_cpu_type_info = {
2572 .name = X86_CPU_TYPE_NAME("max"),
2573 .parent = TYPE_X86_CPU,
2574 .instance_init = max_x86_cpu_initfn,
2575 .class_init = max_x86_cpu_class_init,
2576};
2577
d6dcc558 2578#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 2579static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
2580{
2581 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2582
d6dcc558 2583 xcc->host_cpuid_required = true;
c62f2630
EH		 2584 xcc->ordering = 8;
2585
d6dcc558
SAGDR		 2586 if (kvm_enabled()) {
2587 xcc->model_description =
2588 "KVM processor with all supported host features ";
2589 } else if (hvf_enabled()) {
2590 xcc->model_description =
2591 "HVF processor with all supported host features ";
2592 }
c62f2630
EH		 2593}
2594
d940ee9b
EH		 2595static const TypeInfo host_x86_cpu_type_info = {
2596 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 2597 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 2598 .class_init = host_x86_cpu_class_init,
2599};
2600
2601#endif
2602
8459e396 2603static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 2604{
8459e396 2605 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 2606 int i;
2607
857aee33 2608 for (i = 0; i < 32; ++i) {
72370dc1 2609 if ((1UL << i) & mask) {
bffd67b0 2610 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 2611 assert(reg);
8297be80
AF		 2612 warn_report("%s doesn't support requested feature: "
2613 "CPUID.%02XH:%s%s%s [bit %d]",
d6dcc558 2614 accel_uses_host_cpuid() ? "host" : "TCG",
8297be80
AF		 2615 f->cpuid_eax, reg,
2616 f->feat_names[i] ? "." : "",
2617 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 2618 }
857aee33 2619 }
c6dc6f63
AP		 2620}
2621
d7bce999
EB		 2622static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
2623 const char *name, void *opaque,
2624 Error **errp)
95b8519d
AF		 2625{
2626 X86CPU *cpu = X86_CPU(obj);
2627 CPUX86State *env = &cpu->env;
2628 int64_t value;
2629
2630 value = (env->cpuid_version >> 8) & 0xf;
2631 if (value == 0xf) {
2632 value += (env->cpuid_version >> 20) & 0xff;
2633 }
51e72bc1 2634 visit_type_int(v, name, &value, errp);
95b8519d
AF		 2635}
2636
d7bce999
EB		 2637static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
2638 const char *name, void *opaque,
2639 Error **errp)
ed5e1ec3 2640{
71ad61d3
AF		 2641 X86CPU *cpu = X86_CPU(obj);
2642 CPUX86State *env = &cpu->env;
2643 const int64_t min = 0;
2644 const int64_t max = 0xff + 0xf;
65cd9064 2645 Error *local_err = NULL;
71ad61d3
AF		 2646 int64_t value;
2647
51e72bc1 2648 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2649 if (local_err) {
2650 error_propagate(errp, local_err);
71ad61d3
AF		 2651 return;
2652 }
2653 if (value < min || value > max) {
c6bd8c70
MA		 2654 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2655 name ? name : "null", value, min, max);
71ad61d3
AF		 2656 return;
2657 }
2658
ed5e1ec3 2659 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 2660 if (value > 0x0f) {
2661 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 2662 } else {
71ad61d3 2663 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 2664 }
2665}
2666
d7bce999
EB		 2667static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
2668 const char *name, void *opaque,
2669 Error **errp)
67e30c83
AF		 2670{
2671 X86CPU *cpu = X86_CPU(obj);
2672 CPUX86State *env = &cpu->env;
2673 int64_t value;
2674
2675 value = (env->cpuid_version >> 4) & 0xf;
2676 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 2677 visit_type_int(v, name, &value, errp);
67e30c83
AF		 2678}
2679
d7bce999
EB		 2680static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
2681 const char *name, void *opaque,
2682 Error **errp)
b0704cbd 2683{
c5291a4f
AF		 2684 X86CPU *cpu = X86_CPU(obj);
2685 CPUX86State *env = &cpu->env;
2686 const int64_t min = 0;
2687 const int64_t max = 0xff;
65cd9064 2688 Error *local_err = NULL;
c5291a4f
AF		 2689 int64_t value;
2690
51e72bc1 2691 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2692 if (local_err) {
2693 error_propagate(errp, local_err);
c5291a4f
AF		 2694 return;
2695 }
2696 if (value < min || value > max) {
c6bd8c70
MA		 2697 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2698 name ? name : "null", value, min, max);
c5291a4f
AF		 2699 return;
2700 }
2701
b0704cbd 2702 env->cpuid_version &= ~0xf00f0;
c5291a4f 2703 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 2704}
2705
35112e41 2706static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 2707 const char *name, void *opaque,
35112e41
AF		 2708 Error **errp)
2709{
2710 X86CPU *cpu = X86_CPU(obj);
2711 CPUX86State *env = &cpu->env;
2712 int64_t value;
2713
2714 value = env->cpuid_version & 0xf;
51e72bc1 2715 visit_type_int(v, name, &value, errp);
35112e41
AF		 2716}
2717
036e2222 2718static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 2719 const char *name, void *opaque,
036e2222 2720 Error **errp)
38c3dc46 2721{
036e2222
AF		 2722 X86CPU *cpu = X86_CPU(obj);
2723 CPUX86State *env = &cpu->env;
2724 const int64_t min = 0;
2725 const int64_t max = 0xf;
65cd9064 2726 Error *local_err = NULL;
036e2222
AF		 2727 int64_t value;
2728
51e72bc1 2729 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2730 if (local_err) {
2731 error_propagate(errp, local_err);
036e2222
AF		 2732 return;
2733 }
2734 if (value < min || value > max) {
c6bd8c70
MA		 2735 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2736 name ? name : "null", value, min, max);
036e2222
AF		 2737 return;
2738 }
2739
38c3dc46 2740 env->cpuid_version &= ~0xf;
036e2222 2741 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 2742}
2743
d480e1af
AF		 2744static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
2745{
2746 X86CPU *cpu = X86_CPU(obj);
2747 CPUX86State *env = &cpu->env;
2748 char *value;
d480e1af 2749
e42a92ae 2750 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 2751 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
2752 env->cpuid_vendor3);
d480e1af
AF		 2753 return value;
2754}
2755
2756static void x86_cpuid_set_vendor(Object *obj, const char *value,
2757 Error **errp)
2758{
2759 X86CPU *cpu = X86_CPU(obj);
2760 CPUX86State *env = &cpu->env;
2761 int i;
2762
9df694ee 2763 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 2764 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 2765 return;
2766 }
2767
2768 env->cpuid_vendor1 = 0;
2769 env->cpuid_vendor2 = 0;
2770 env->cpuid_vendor3 = 0;
2771 for (i = 0; i < 4; i++) {
2772 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
2773 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
2774 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
2775 }
d480e1af
AF		 2776}
2777
63e886eb
AF		 2778static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
2779{
2780 X86CPU *cpu = X86_CPU(obj);
2781 CPUX86State *env = &cpu->env;
2782 char *value;
2783 int i;
2784
2785 value = g_malloc(48 + 1);
2786 for (i = 0; i < 48; i++) {
2787 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
2788 }
2789 value[48] = '\0';
2790 return value;
2791}
2792
938d4c25
AF		 2793static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
2794 Error **errp)
dcce6675 2795{
938d4c25
AF		 2796 X86CPU *cpu = X86_CPU(obj);
2797 CPUX86State *env = &cpu->env;
dcce6675
AF		 2798 int c, len, i;
2799
2800 if (model_id == NULL) {
2801 model_id = "";
2802 }
2803 len = strlen(model_id);
d0a6acf4 2804 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 2805 for (i = 0; i < 48; i++) {
2806 if (i >= len) {
2807 c = '\0';
2808 } else {
2809 c = (uint8_t)model_id[i];
2810 }
2811 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
2812 }
2813}
2814
d7bce999
EB		 2815static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
2816 void *opaque, Error **errp)
89e48965
AF		 2817{
2818 X86CPU *cpu = X86_CPU(obj);
2819 int64_t value;
2820
2821 value = cpu->env.tsc_khz * 1000;
51e72bc1 2822 visit_type_int(v, name, &value, errp);
89e48965
AF		 2823}
2824
d7bce999
EB		 2825static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
2826 void *opaque, Error **errp)
89e48965
AF		 2827{
2828 X86CPU *cpu = X86_CPU(obj);
2829 const int64_t min = 0;
2e84849a 2830 const int64_t max = INT64_MAX;
65cd9064 2831 Error *local_err = NULL;
89e48965
AF		 2832 int64_t value;
2833
51e72bc1 2834 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2835 if (local_err) {
2836 error_propagate(errp, local_err);
89e48965
AF		 2837 return;
2838 }
2839 if (value < min || value > max) {
c6bd8c70
MA		 2840 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2841 name ? name : "null", value, min, max);
89e48965
AF		 2842 return;
2843 }
2844
36f96c4b 2845 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 2846}
2847
7e5292b5 2848/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 2849static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
2850 const char *name, void *opaque,
2851 Error **errp)
8e8aba50 2852{
7e5292b5 2853 uint32_t *array = (uint32_t *)opaque;
8e8aba50 2854 FeatureWord w;
8e8aba50
EH		 2855 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
2856 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
2857 X86CPUFeatureWordInfoList *list = NULL;
2858
2859 for (w = 0; w < FEATURE_WORDS; w++) {
2860 FeatureWordInfo *wi = &feature_word_info[w];
2861 X86CPUFeatureWordInfo *qwi = &word_infos[w];
2862 qwi->cpuid_input_eax = wi->cpuid_eax;
2863 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
2864 qwi->cpuid_input_ecx = wi->cpuid_ecx;
2865 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 2866 qwi->features = array[w];
8e8aba50
EH		 2867
2868 /* List will be in reverse order, but order shouldn't matter */
2869 list_entries[w].next = list;
2870 list_entries[w].value = &word_infos[w];
2871 list = &list_entries[w];
2872 }
2873
6b62d961 2874 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 2875}
2876
d7bce999
EB		 2877static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
2878 void *opaque, Error **errp)
c8f0f88e
IM		 2879{
2880 X86CPU *cpu = X86_CPU(obj);
2881 int64_t value = cpu->hyperv_spinlock_attempts;
2882
51e72bc1 2883 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 2884}
2885
d7bce999
EB		 2886static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
2887 void *opaque, Error **errp)
c8f0f88e
IM		 2888{
2889 const int64_t min = 0xFFF;
2890 const int64_t max = UINT_MAX;
2891 X86CPU *cpu = X86_CPU(obj);
2892 Error *err = NULL;
2893 int64_t value;
2894
51e72bc1 2895 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 2896 if (err) {
2897 error_propagate(errp, err);
2898 return;
2899 }
2900
2901 if (value < min || value > max) {
2902 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 2903 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
2904 object_get_typename(obj), name ? name : "null",
2905 value, min, max);
c8f0f88e
IM		 2906 return;
2907 }
2908 cpu->hyperv_spinlock_attempts = value;
2909}
2910
1b6b7d10 2911static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 2912 .name = "int",
2913 .get = x86_get_hv_spinlocks,
2914 .set = x86_set_hv_spinlocks,
2915};
2916
72ac2e87
IM		 2917/* Convert all '_' in a feature string option name to '-', to make feature
2918 * name conform to QOM property naming rule, which uses '-' instead of '_'.
2919 */
2920static inline void feat2prop(char *s)
2921{
2922 while ((s = strchr(s, '_'))) {
2923 *s = '-';
2924 }
2925}
2926
b54c9377
EH		 2927/* Return the feature property name for a feature flag bit */
2928static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
2929{
2930 /* XSAVE components are automatically enabled by other features,
2931 * so return the original feature name instead
2932 */
2933 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
2934 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
2935
2936 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
2937 x86_ext_save_areas[comp].bits) {
2938 w = x86_ext_save_areas[comp].feature;
2939 bitnr = ctz32(x86_ext_save_areas[comp].bits);
2940 }
2941 }
2942
2943 assert(bitnr < 32);
2944 assert(w < FEATURE_WORDS);
2945 return feature_word_info[w].feat_names[bitnr];
2946}
2947
dc15c051
IM		 2948/* Compatibily hack to maintain legacy +-feat semantic,
2949 * where +-feat overwrites any feature set by
2950 * feat=on|feat even if the later is parsed after +-feat
2951 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2952 */
2fae0d96 2953static GList *plus_features, *minus_features;
dc15c051 2954
83a00f60
EH		 2955static gint compare_string(gconstpointer a, gconstpointer b)
2956{
2957 return g_strcmp0(a, b);
2958}
2959
8f961357
EH		 2960/* Parse "+feature,-feature,feature=foo" CPU feature string
2961 */
62a48a2a 2962static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 2963 Error **errp)
8f961357 2964{
8f961357 2965 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 2966 static bool cpu_globals_initialized;
83a00f60 2967 bool ambiguous = false;
62a48a2a
IM		 2968
2969 if (cpu_globals_initialized) {
2970 return;
2971 }
2972 cpu_globals_initialized = true;
8f961357 2973
f6750e95
EH		 2974 if (!features) {
2975 return;
2976 }
2977
2978 for (featurestr = strtok(features, ",");
685479bd 2979 featurestr;
f6750e95
EH		 2980 featurestr = strtok(NULL, ",")) {
2981 const char *name;
2982 const char *val = NULL;
2983 char *eq = NULL;
cf2887c9 2984 char num[32];
62a48a2a 2985 GlobalProperty *prop;
c6dc6f63 2986
f6750e95 2987 /* Compatibility syntax: */
c6dc6f63 2988 if (featurestr[0] == '+') {
2fae0d96
EH		 2989 plus_features = g_list_append(plus_features,
2990 g_strdup(featurestr + 1));
f6750e95 2991 continue;
c6dc6f63 2992 } else if (featurestr[0] == '-') {
2fae0d96
EH		 2993 minus_features = g_list_append(minus_features,
2994 g_strdup(featurestr + 1));
f6750e95
EH		 2995 continue;
2996 }
2997
2998 eq = strchr(featurestr, '=');
2999 if (eq) {
3000 *eq++ = 0;
3001 val = eq;
c6dc6f63 3002 } else {
f6750e95 3003 val = "on";
a91987c2 3004 }
f6750e95
EH		 3005
3006 feat2prop(featurestr);
3007 name = featurestr;
3008
83a00f60 3009 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 3010 warn_report("Ambiguous CPU model string. "
3011 "Don't mix both \"+%s\" and \"%s=%s\"",
3012 name, name, val);
83a00f60
EH		 3013 ambiguous = true;
3014 }
3015 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 3016 warn_report("Ambiguous CPU model string. "
3017 "Don't mix both \"-%s\" and \"%s=%s\"",
3018 name, name, val);
83a00f60
EH		 3019 ambiguous = true;
3020 }
3021
f6750e95
EH		 3022 /* Special case: */
3023 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 3024 int ret;
f46bfdbf 3025 uint64_t tsc_freq;
f6750e95 3026
f17fd4fd 3027 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 3028 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 3029 error_setg(errp, "bad numerical value %s", val);
3030 return;
3031 }
3032 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3033 val = num;
3034 name = "tsc-frequency";
c6dc6f63 3035 }
f6750e95 3036
62a48a2a
IM		 3037 prop = g_new0(typeof(*prop), 1);
3038 prop->driver = typename;
3039 prop->property = g_strdup(name);
3040 prop->value = g_strdup(val);
3041 prop->errp = &error_fatal;
3042 qdev_prop_register_global(prop);
f6750e95
EH		 3043 }
3044
83a00f60 3045 if (ambiguous) {
3dc6f869
AF		 3046 warn_report("Compatibility of ambiguous CPU model "
3047 "strings won't be kept on future QEMU versions");
83a00f60 3048 }
c6dc6f63
AP		 3049}
3050
b8d834a0 3051static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 3052static int x86_cpu_filter_features(X86CPU *cpu);
3053
3054/* Check for missing features that may prevent the CPU class from
3055 * running using the current machine and accelerator.
3056 */
3057static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3058 strList **missing_feats)
3059{
3060 X86CPU *xc;
3061 FeatureWord w;
3062 Error *err = NULL;
3063 strList **next = missing_feats;
3064
d6dcc558 3065 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 3066 strList *new = g_new0(strList, 1);
3c254ab8 3067 new->value = g_strdup("kvm");
b54c9377
EH		 3068 *missing_feats = new;
3069 return;
3070 }
3071
3072 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3073
b8d834a0 3074 x86_cpu_expand_features(xc, &err);
b54c9377 3075 if (err) {
b8d834a0 3076 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 3077 * but in case it does, just report the model as not
3078 * runnable at all using the "type" property.
3079 */
3080 strList *new = g_new0(strList, 1);
3081 new->value = g_strdup("type");
3082 *next = new;
3083 next = &new->next;
3084 }
3085
3086 x86_cpu_filter_features(xc);
3087
3088 for (w = 0; w < FEATURE_WORDS; w++) {
3089 uint32_t filtered = xc->filtered_features[w];
3090 int i;
3091 for (i = 0; i < 32; i++) {
3092 if (filtered & (1UL << i)) {
3093 strList *new = g_new0(strList, 1);
3094 new->value = g_strdup(x86_cpu_feature_name(w, i));
3095 *next = new;
3096 next = &new->next;
3097 }
3098 }
3099 }
3100
3101 object_unref(OBJECT(xc));
3102}
3103
8c3329e5 3104/* Print all cpuid feature names in featureset
c6dc6f63 3105 */
8c3329e5 3106static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 3107{
8c3329e5
EH		 3108 int bit;
3109 bool first = true;
3110
3111 for (bit = 0; bit < 32; bit++) {
3112 if (featureset[bit]) {
3113 print(f, "%s%s", first ? "" : " ", featureset[bit]);
3114 first = false;
c6dc6f63 3115 }
8c3329e5 3116 }
c6dc6f63
AP		 3117}
3118
f48c8837 3119/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 3120static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3121{
3122 ObjectClass *class_a = (ObjectClass *)a;
3123 ObjectClass *class_b = (ObjectClass *)b;
3124 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3125 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
3126 const char *name_a, *name_b;
3127
f48c8837
EH		 3128 if (cc_a->ordering != cc_b->ordering) {
3129 return cc_a->ordering - cc_b->ordering;
ee465a3e
EH		 3130 } else {
3131 name_a = object_class_get_name(class_a);
3132 name_b = object_class_get_name(class_b);
3133 return strcmp(name_a, name_b);
3134 }
3135}
3136
3137static GSList *get_sorted_cpu_model_list(void)
3138{
3139 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3140 list = g_slist_sort(list, x86_cpu_list_compare);
3141 return list;
3142}
3143
3144static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3145{
3146 ObjectClass *oc = data;
3147 X86CPUClass *cc = X86_CPU_CLASS(oc);
3148 CPUListState *s = user_data;
3149 char *name = x86_cpu_class_get_model_name(cc);
3150 const char *desc = cc->model_description;
0bacd8b3 3151 if (!desc && cc->cpu_def) {
ee465a3e
EH		 3152 desc = cc->cpu_def->model_id;
3153 }
3154
3155 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
3156 name, desc);
3157 g_free(name);
3158}
3159
3160/* list available CPU models and flags */
e916cbf8 3161void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 3162{
7fc9b714 3163 int i;
ee465a3e
EH		 3164 CPUListState s = {
3165 .file = f,
3166 .cpu_fprintf = cpu_fprintf,
3167 };
3168 GSList *list;
c6dc6f63 3169
ee465a3e
EH		 3170 (*cpu_fprintf)(f, "Available CPUs:\n");
3171 list = get_sorted_cpu_model_list();
3172 g_slist_foreach(list, x86_cpu_list_entry, &s);
3173 g_slist_free(list);
21ad7789 3174
6cdf8854 3175 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 3176 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3177 FeatureWordInfo *fw = &feature_word_info[i];
3178
8c3329e5
EH		 3179 (*cpu_fprintf)(f, " ");
3180 listflags(f, cpu_fprintf, fw->feat_names);
3181 (*cpu_fprintf)(f, "\n");
3af60be2 3182 }
c6dc6f63
AP		 3183}
3184
ee465a3e
EH		 3185static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3186{
3187 ObjectClass *oc = data;
3188 X86CPUClass *cc = X86_CPU_CLASS(oc);
3189 CpuDefinitionInfoList **cpu_list = user_data;
3190 CpuDefinitionInfoList *entry;
3191 CpuDefinitionInfo *info;
3192
3193 info = g_malloc0(sizeof(*info));
3194 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 3195 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3196 info->has_unavailable_features = true;
8ed877b7 3197 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 3198 info->migration_safe = cc->migration_safe;
3199 info->has_migration_safe = true;
5adbed30 3200 info->q_static = cc->static_model;
ee465a3e
EH		 3201
3202 entry = g_malloc0(sizeof(*entry));
3203 entry->value = info;
3204 entry->next = *cpu_list;
3205 *cpu_list = entry;
3206}
3207
76b64a7a 3208CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 3209{
3210 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 3211 GSList *list = get_sorted_cpu_model_list();
3212 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3213 g_slist_free(list);
e3966126
AL		 3214 return cpu_list;
3215}
3216
84f1b92f
EH		 3217static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3218 bool migratable_only)
27418adf
EH		 3219{
3220 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 3221 uint32_t r;
27418adf 3222
fefb41bf 3223 if (kvm_enabled()) {
84f1b92f
EH		 3224 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
3225 wi->cpuid_ecx,
3226 wi->cpuid_reg);
d6dcc558
SAGDR		 3227 } else if (hvf_enabled()) {
3228 r = hvf_get_supported_cpuid(wi->cpuid_eax,
3229 wi->cpuid_ecx,
3230 wi->cpuid_reg);
fefb41bf 3231 } else if (tcg_enabled()) {
84f1b92f 3232 r = wi->tcg_features;
fefb41bf
EH		 3233 } else {
3234 return ~0;
3235 }
84f1b92f
EH		 3236 if (migratable_only) {
3237 r &= x86_cpu_get_migratable_flags(w);
3238 }
3239 return r;
27418adf
EH		 3240}
3241
8ca30e86
EH		 3242static void x86_cpu_report_filtered_features(X86CPU *cpu)
3243{
3244 FeatureWord w;
3245
3246 for (w = 0; w < FEATURE_WORDS; w++) {
3247 report_unavailable_features(w, cpu->filtered_features[w]);
3248 }
3249}
3250
5114e842
EH		 3251static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3252{
3253 PropValue *pv;
3254 for (pv = props; pv->prop; pv++) {
3255 if (!pv->value) {
3256 continue;
3257 }
3258 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3259 &error_abort);
3260 }
3261}
3262
f99fd7ca 3263/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 3264 */
d940ee9b 3265static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 3266{
61dcd775 3267 CPUX86State *env = &cpu->env;
74f54bc4
EH		 3268 const char *vendor;
3269 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 3270 FeatureWord w;
c6dc6f63 3271
f99fd7ca
EH		 3272 /*NOTE: any property set by this function should be returned by
3273 * x86_cpu_static_props(), so static expansion of
3274 * query-cpu-model-expansion is always complete.
3275 */
3276
c39c0edf 3277 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 3278 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3279 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 3280
2d64255b
AF		 3281 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3282 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3283 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 3284 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 3285 for (w = 0; w < FEATURE_WORDS; w++) {
3286 env->features[w] = def->features[w];
3287 }
82beb536 3288
9576de75 3289 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 3290 /* TODO: in-kernel irqchip for hvf */
82beb536 3291 if (kvm_enabled()) {
492a4c94
LT		 3292 if (!kvm_irqchip_in_kernel()) {
3293 x86_cpu_change_kvm_default("x2apic", "off");
3294 }
3295
5114e842 3296 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 3297 } else if (tcg_enabled()) {
3298 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 3299 }
5fcca9ff 3300
82beb536 3301 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 3302
3303 /* sysenter isn't supported in compatibility mode on AMD,
3304 * syscall isn't supported in compatibility mode on Intel.
3305 * Normally we advertise the actual CPU vendor, but you can
3306 * override this using the 'vendor' property if you want to use
3307 * KVM's sysenter/syscall emulation in compatibility mode and
3308 * when doing cross vendor migration
3309 */
74f54bc4 3310 vendor = def->vendor;
d6dcc558 3311 if (accel_uses_host_cpuid()) {
7c08db30
EH		 3312 uint32_t ebx = 0, ecx = 0, edx = 0;
3313 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3314 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3315 vendor = host_vendor;
3316 }
3317
3318 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3319
c6dc6f63
AP		 3320}
3321
f99fd7ca
EH		 3322/* Return a QDict containing keys for all properties that can be included
3323 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3324 * must be included in the dictionary.
3325 */
3326static QDict *x86_cpu_static_props(void)
3327{
3328 FeatureWord w;
3329 int i;
3330 static const char *props[] = {
3331 "min-level",
3332 "min-xlevel",
3333 "family",
3334 "model",
3335 "stepping",
3336 "model-id",
3337 "vendor",
3338 "lmce",
3339 NULL,
3340 };
3341 static QDict *d;
3342
3343 if (d) {
3344 return d;
3345 }
3346
3347 d = qdict_new();
3348 for (i = 0; props[i]; i++) {
0f9afc2a 3349 qdict_put_null(d, props[i]);
f99fd7ca
EH		 3350 }
3351
3352 for (w = 0; w < FEATURE_WORDS; w++) {
3353 FeatureWordInfo *fi = &feature_word_info[w];
3354 int bit;
3355 for (bit = 0; bit < 32; bit++) {
3356 if (!fi->feat_names[bit]) {
3357 continue;
3358 }
0f9afc2a 3359 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 3360 }
3361 }
3362
3363 return d;
3364}
3365
3366/* Add an entry to @props dict, with the value for property. */
3367static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
3368{
3369 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
3370 &error_abort);
3371
3372 qdict_put_obj(props, prop, value);
3373}
3374
3375/* Convert CPU model data from X86CPU object to a property dictionary
3376 * that can recreate exactly the same CPU model.
3377 */
3378static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
3379{
3380 QDict *sprops = x86_cpu_static_props();
3381 const QDictEntry *e;
3382
3383 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
3384 const char *prop = qdict_entry_key(e);
3385 x86_cpu_expand_prop(cpu, props, prop);
3386 }
3387}
3388
b8097deb
EH		 3389/* Convert CPU model data from X86CPU object to a property dictionary
3390 * that can recreate exactly the same CPU model, including every
3391 * writeable QOM property.
3392 */
3393static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
3394{
3395 ObjectPropertyIterator iter;
3396 ObjectProperty *prop;
3397
3398 object_property_iter_init(&iter, OBJECT(cpu));
3399 while ((prop = object_property_iter_next(&iter))) {
3400 /* skip read-only or write-only properties */
3401 if (!prop->get || !prop->set) {
3402 continue;
3403 }
3404
3405 /* "hotplugged" is the only property that is configurable
3406 * on the command-line but will be set differently on CPUs
3407 * created using "-cpu ... -smp ..." and by CPUs created
3408 * on the fly by x86_cpu_from_model() for querying. Skip it.
3409 */
3410 if (!strcmp(prop->name, "hotplugged")) {
3411 continue;
3412 }
3413 x86_cpu_expand_prop(cpu, props, prop->name);
3414 }
3415}
3416
f99fd7ca
EH		 3417static void object_apply_props(Object *obj, QDict *props, Error **errp)
3418{
3419 const QDictEntry *prop;
3420 Error *err = NULL;
3421
3422 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
3423 object_property_set_qobject(obj, qdict_entry_value(prop),
3424 qdict_entry_key(prop), &err);
3425 if (err) {
3426 break;
3427 }
3428 }
3429
3430 error_propagate(errp, err);
3431}
3432
3433/* Create X86CPU object according to model+props specification */
3434static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
3435{
3436 X86CPU *xc = NULL;
3437 X86CPUClass *xcc;
3438 Error *err = NULL;
3439
3440 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
3441 if (xcc == NULL) {
3442 error_setg(&err, "CPU model '%s' not found", model);
3443 goto out;
3444 }
3445
3446 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3447 if (props) {
3448 object_apply_props(OBJECT(xc), props, &err);
3449 if (err) {
3450 goto out;
3451 }
3452 }
3453
3454 x86_cpu_expand_features(xc, &err);
3455 if (err) {
3456 goto out;
3457 }
3458
3459out:
3460 if (err) {
3461 error_propagate(errp, err);
3462 object_unref(OBJECT(xc));
3463 xc = NULL;
3464 }
3465 return xc;
3466}
3467
3468CpuModelExpansionInfo *
3469arch_query_cpu_model_expansion(CpuModelExpansionType type,
3470 CpuModelInfo *model,
3471 Error **errp)
3472{
3473 X86CPU *xc = NULL;
3474 Error *err = NULL;
3475 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
3476 QDict *props = NULL;
3477 const char *base_name;
3478
3479 xc = x86_cpu_from_model(model->name,
3480 model->has_props ?
7dc847eb 3481 qobject_to(QDict, model->props) :
f99fd7ca
EH		 3482 NULL, &err);
3483 if (err) {
3484 goto out;
3485 }
3486
b8097deb 3487 props = qdict_new();
f99fd7ca
EH		 3488
3489 switch (type) {
3490 case CPU_MODEL_EXPANSION_TYPE_STATIC:
3491 /* Static expansion will be based on "base" only */
3492 base_name = "base";
b8097deb 3493 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 3494 break;
3495 case CPU_MODEL_EXPANSION_TYPE_FULL:
3496 /* As we don't return every single property, full expansion needs
3497 * to keep the original model name+props, and add extra
3498 * properties on top of that.
3499 */
3500 base_name = model->name;
b8097deb 3501 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 3502 break;
3503 default:
3504 error_setg(&err, "Unsupportted expansion type");
3505 goto out;
3506 }
3507
3508 if (!props) {
3509 props = qdict_new();
3510 }
3511 x86_cpu_to_dict(xc, props);
3512
3513 ret->model = g_new0(CpuModelInfo, 1);
3514 ret->model->name = g_strdup(base_name);
3515 ret->model->props = QOBJECT(props);
3516 ret->model->has_props = true;
3517
3518out:
3519 object_unref(OBJECT(xc));
3520 if (err) {
3521 error_propagate(errp, err);
3522 qapi_free_CpuModelExpansionInfo(ret);
3523 ret = NULL;
3524 }
3525 return ret;
3526}
3527
00fcd100
AB		 3528static gchar *x86_gdb_arch_name(CPUState *cs)
3529{
3530#ifdef TARGET_X86_64
3531 return g_strdup("i386:x86-64");
3532#else
3533 return g_strdup("i386");
3534#endif
3535}
3536
d940ee9b
EH		 3537static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
3538{
3539 X86CPUDefinition *cpudef = data;
3540 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3541
3542 xcc->cpu_def = cpudef;
bd72159d 3543 xcc->migration_safe = true;
d940ee9b
EH		 3544}
3545
3546static void x86_register_cpudef_type(X86CPUDefinition *def)
3547{
3548 char *typename = x86_cpu_type_name(def->name);
3549 TypeInfo ti = {
3550 .name = typename,
3551 .parent = TYPE_X86_CPU,
3552 .class_init = x86_cpu_cpudef_class_init,
3553 .class_data = def,
3554 };
3555
2a923a29
EH		 3556 /* AMD aliases are handled at runtime based on CPUID vendor, so
3557 * they shouldn't be set on the CPU model table.
3558 */
3559 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 3560 /* catch mistakes instead of silently truncating model_id when too long */
3561 assert(def->model_id && strlen(def->model_id) <= 48);
3562
2a923a29 3563
d940ee9b
EH		 3564 type_register(&ti);
3565 g_free(typename);
3566}
3567
c6dc6f63 3568#if !defined(CONFIG_USER_ONLY)
c6dc6f63 3569
0e26b7b8
BS		 3570void cpu_clear_apic_feature(CPUX86State *env)
3571{
0514ef2f 3572 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 3573}
3574
c6dc6f63
AP		 3575#endif /* !CONFIG_USER_ONLY */
3576
c6dc6f63
AP		 3577void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
3578 uint32_t *eax, uint32_t *ebx,
3579 uint32_t *ecx, uint32_t *edx)
3580{
a60f24b5
AF		 3581 X86CPU *cpu = x86_env_get_cpu(env);
3582 CPUState *cs = CPU(cpu);
14c985cf 3583 uint32_t pkg_offset;
4ed3d478 3584 uint32_t limit;
1ce36bfe 3585 uint32_t signature[3];
a60f24b5 3586
4ed3d478
DB		 3587 /* Calculate & apply limits for different index ranges */
3588 if (index >= 0xC0000000) {
3589 limit = env->cpuid_xlevel2;
3590 } else if (index >= 0x80000000) {
3591 limit = env->cpuid_xlevel;
1ce36bfe
DB		 3592 } else if (index >= 0x40000000) {
3593 limit = 0x40000001;
c6dc6f63 3594 } else {
4ed3d478
DB		 3595 limit = env->cpuid_level;
3596 }
3597
3598 if (index > limit) {
3599 /* Intel documentation states that invalid EAX input will
3600 * return the same information as EAX=cpuid_level
3601 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
3602 */
3603 index = env->cpuid_level;
c6dc6f63
AP		 3604 }
3605
3606 switch(index) {
3607 case 0:
3608 *eax = env->cpuid_level;
5eb2f7a4
EH		 3609 *ebx = env->cpuid_vendor1;
3610 *edx = env->cpuid_vendor2;
3611 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 3612 break;
3613 case 1:
3614 *eax = env->cpuid_version;
7e72a45c
EH		 3615 *ebx = (cpu->apic_id << 24) |
3616 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 3617 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 3618 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
3619 *ecx |= CPUID_EXT_OSXSAVE;
3620 }
0514ef2f 3621 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 3622 if (cs->nr_cores * cs->nr_threads > 1) {
3623 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 3624 *edx |= CPUID_HT;
c6dc6f63
AP		 3625 }
3626 break;
3627 case 2:
3628 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 3629 if (cpu->cache_info_passthrough) {
3630 host_cpuid(index, 0, eax, ebx, ecx, edx);
3631 break;
3632 }
5e891bf8 3633 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 3634 *ebx = 0;
14c985cf
LM		 3635 if (!cpu->enable_l3_cache) {
3636 *ecx = 0;
3637 } else {
7e3482f8 3638 *ecx = cpuid2_cache_descriptor(&l3_cache);
14c985cf 3639 }
7e3482f8
EH		 3640 *edx = (cpuid2_cache_descriptor(&l1d_cache) << 16) |
3641 (cpuid2_cache_descriptor(&l1i_cache) << 8) |
3642 (cpuid2_cache_descriptor(&l2_cache_cpuid2));
c6dc6f63
AP		 3643 break;
3644 case 4:
3645 /* cache info: needed for Core compatibility */
787aaf57
BC		 3646 if (cpu->cache_info_passthrough) {
3647 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 3648 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 3649 *eax &= ~0xFC000000;
7e3482f8
EH		 3650 if ((*eax & 31) && cs->nr_cores > 1) {
3651 *eax |= (cs->nr_cores - 1) << 26;
3652 }
c6dc6f63 3653 } else {
2f7a21c4 3654 *eax = 0;
76c2975a 3655 switch (count) {
c6dc6f63 3656 case 0: /* L1 dcache info */
7e3482f8
EH		 3657 encode_cache_cpuid4(&l1d_cache,
3658 1, cs->nr_cores,
3659 eax, ebx, ecx, edx);
c6dc6f63
AP		 3660 break;
3661 case 1: /* L1 icache info */
7e3482f8
EH		 3662 encode_cache_cpuid4(&l1i_cache,
3663 1, cs->nr_cores,
3664 eax, ebx, ecx, edx);
c6dc6f63
AP		 3665 break;
3666 case 2: /* L2 cache info */
7e3482f8
EH		 3667 encode_cache_cpuid4(&l2_cache,
3668 cs->nr_threads, cs->nr_cores,
3669 eax, ebx, ecx, edx);
c6dc6f63 3670 break;
14c985cf 3671 case 3: /* L3 cache info */
7e3482f8
EH		 3672 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
3673 if (cpu->enable_l3_cache) {
3674 encode_cache_cpuid4(&l3_cache,
3675 (1 << pkg_offset), cs->nr_cores,
3676 eax, ebx, ecx, edx);
14c985cf
LM		 3677 break;
3678 }
7e3482f8 3679 /* fall through */
c6dc6f63 3680 default: /* end of info */
7e3482f8 3681 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 3682 break;
76c2975a
PB		 3683 }
3684 }
c6dc6f63
AP		 3685 break;
3686 case 5:
3687 /* mwait info: needed for Core compatibility */
3688 *eax = 0; /* Smallest monitor-line size in bytes */
3689 *ebx = 0; /* Largest monitor-line size in bytes */
3690 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
3691 *edx = 0;
3692 break;
3693 case 6:
3694 /* Thermal and Power Leaf */
28b8e4d0 3695 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 3696 *ebx = 0;
3697 *ecx = 0;
3698 *edx = 0;
3699 break;
f7911686 3700 case 7:
13526728
EH		 3701 /* Structured Extended Feature Flags Enumeration Leaf */
3702 if (count == 0) {
3703 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 3704 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 3705 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 3706 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
3707 *ecx |= CPUID_7_0_ECX_OSPKE;
3708 }
95ea69fb 3709 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 3710 } else {
3711 *eax = 0;
3712 *ebx = 0;
3713 *ecx = 0;
3714 *edx = 0;
3715 }
3716 break;
c6dc6f63
AP		 3717 case 9:
3718 /* Direct Cache Access Information Leaf */
3719 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
3720 *ebx = 0;
3721 *ecx = 0;
3722 *edx = 0;
3723 break;
3724 case 0xA:
3725 /* Architectural Performance Monitoring Leaf */
9337e3b6 3726 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 3727 KVMState *s = cs->kvm_state;
a0fa8208
GN		 3728
3729 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
3730 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
3731 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
3732 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 3733 } else if (hvf_enabled() && cpu->enable_pmu) {
3734 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
3735 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
3736 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
3737 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 3738 } else {
3739 *eax = 0;
3740 *ebx = 0;
3741 *ecx = 0;
3742 *edx = 0;
3743 }
c6dc6f63 3744 break;
5232d00a
RK		 3745 case 0xB:
3746 /* Extended Topology Enumeration Leaf */
3747 if (!cpu->enable_cpuid_0xb) {
3748 *eax = *ebx = *ecx = *edx = 0;
3749 break;
3750 }
3751
3752 *ecx = count & 0xff;
3753 *edx = cpu->apic_id;
3754
3755 switch (count) {
3756 case 0:
eab60fb9
MAL		 3757 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
3758 *ebx = cs->nr_threads;
5232d00a
RK		 3759 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
3760 break;
3761 case 1:
eab60fb9
MAL		 3762 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
3763 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 3764 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
3765 break;
3766 default:
3767 *eax = 0;
3768 *ebx = 0;
3769 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
3770 }
3771
3772 assert(!(*eax & ~0x1f));
3773 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
3774 break;
2560f19f 3775 case 0xD: {
51e49430 3776 /* Processor Extended State */
2560f19f
PB		 3777 *eax = 0;
3778 *ebx = 0;
3779 *ecx = 0;
3780 *edx = 0;
19dc85db 3781 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 3782 break;
3783 }
4928cd6d 3784
2560f19f 3785 if (count == 0) {
96193c22
EH		 3786 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
3787 *eax = env->features[FEAT_XSAVE_COMP_LO];
3788 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 3789 *ebx = *ecx;
3790 } else if (count == 1) {
0bb0b2d2 3791 *eax = env->features[FEAT_XSAVE];
f4f1110e 3792 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 3793 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
3794 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 3795 *eax = esa->size;
3796 *ebx = esa->offset;
2560f19f 3797 }
51e49430
SY		 3798 }
3799 break;
2560f19f 3800 }
e37a5c7f
CP		 3801 case 0x14: {
3802 /* Intel Processor Trace Enumeration */
3803 *eax = 0;
3804 *ebx = 0;
3805 *ecx = 0;
3806 *edx = 0;
3807 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
3808 !kvm_enabled()) {
3809 break;
3810 }
3811
3812 if (count == 0) {
3813 *eax = INTEL_PT_MAX_SUBLEAF;
3814 *ebx = INTEL_PT_MINIMAL_EBX;
3815 *ecx = INTEL_PT_MINIMAL_ECX;
3816 } else if (count == 1) {
3817 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
3818 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
3819 }
3820 break;
3821 }
1ce36bfe
DB		 3822 case 0x40000000:
3823 /*
3824 * CPUID code in kvm_arch_init_vcpu() ignores stuff
3825 * set here, but we restrict to TCG none the less.
3826 */
3827 if (tcg_enabled() && cpu->expose_tcg) {
3828 memcpy(signature, "TCGTCGTCGTCG", 12);
3829 *eax = 0x40000001;
3830 *ebx = signature[0];
3831 *ecx = signature[1];
3832 *edx = signature[2];
3833 } else {
3834 *eax = 0;
3835 *ebx = 0;
3836 *ecx = 0;
3837 *edx = 0;
3838 }
3839 break;
3840 case 0x40000001:
3841 *eax = 0;
3842 *ebx = 0;
3843 *ecx = 0;
3844 *edx = 0;
3845 break;
c6dc6f63
AP		 3846 case 0x80000000:
3847 *eax = env->cpuid_xlevel;
3848 *ebx = env->cpuid_vendor1;
3849 *edx = env->cpuid_vendor2;
3850 *ecx = env->cpuid_vendor3;
3851 break;
3852 case 0x80000001:
3853 *eax = env->cpuid_version;
3854 *ebx = 0;
0514ef2f
EH		 3855 *ecx = env->features[FEAT_8000_0001_ECX];
3856 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 3857
3858 /* The Linux kernel checks for the CMPLegacy bit and
3859 * discards multiple thread information if it is set.
cb8d4c8f 3860 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 3861 */
ce3960eb 3862 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 3863 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
3864 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
3865 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 3866 *ecx |= 1 << 1; /* CmpLegacy bit */
3867 }
3868 }
c6dc6f63
AP		 3869 break;
3870 case 0x80000002:
3871 case 0x80000003:
3872 case 0x80000004:
3873 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
3874 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
3875 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
3876 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
3877 break;
3878 case 0x80000005:
3879 /* cache info (L1 cache) */
787aaf57
BC		 3880 if (cpu->cache_info_passthrough) {
3881 host_cpuid(index, 0, eax, ebx, ecx, edx);
3882 break;
3883 }
5e891bf8
EH		 3884 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
3885 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
3886 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
3887 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
7e3482f8
EH		 3888 *ecx = encode_cache_cpuid80000005(&l1d_cache_amd);
3889 *edx = encode_cache_cpuid80000005(&l1i_cache_amd);
c6dc6f63
AP		 3890 break;
3891 case 0x80000006:
3892 /* cache info (L2 cache) */
787aaf57
BC		 3893 if (cpu->cache_info_passthrough) {
3894 host_cpuid(index, 0, eax, ebx, ecx, edx);
3895 break;
3896 }
5e891bf8
EH		 3897 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
3898 (L2_DTLB_2M_ENTRIES << 16) | \
3899 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
3900 (L2_ITLB_2M_ENTRIES);
3901 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
3902 (L2_DTLB_4K_ENTRIES << 16) | \
3903 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
3904 (L2_ITLB_4K_ENTRIES);
7e3482f8
EH		 3905 encode_cache_cpuid80000006(&l2_cache_amd,
3906 cpu->enable_l3_cache ? &l3_cache : NULL,
3907 ecx, edx);
c6dc6f63 3908 break;
303752a9
MT		 3909 case 0x80000007:
3910 *eax = 0;
3911 *ebx = 0;
3912 *ecx = 0;
3913 *edx = env->features[FEAT_8000_0007_EDX];
3914 break;
c6dc6f63
AP		 3915 case 0x80000008:
3916 /* virtual & phys address size in low 2 bytes. */
0514ef2f 3917 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 3918 /* 64 bit processor */
3919 *eax = cpu->phys_bits; /* configurable physical bits */
3920 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
3921 *eax |= 0x00003900; /* 57 bits virtual */
3922 } else {
3923 *eax |= 0x00003000; /* 48 bits virtual */
3924 }
c6dc6f63 3925 } else {
af45907a 3926 *eax = cpu->phys_bits;
c6dc6f63 3927 }
1b3420e1 3928 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 3929 *ecx = 0;
3930 *edx = 0;
ce3960eb
AF		 3931 if (cs->nr_cores * cs->nr_threads > 1) {
3932 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 3933 }
3934 break;
3935 case 0x8000000A:
0514ef2f 3936 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 3937 *eax = 0x00000001; /* SVM Revision */
3938 *ebx = 0x00000010; /* nr of ASIDs */
3939 *ecx = 0;
0514ef2f 3940 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 3941 } else {
3942 *eax = 0;
3943 *ebx = 0;
3944 *ecx = 0;
3945 *edx = 0;
3946 }
c6dc6f63 3947 break;
b3baa152
BW		 3948 case 0xC0000000:
3949 *eax = env->cpuid_xlevel2;
3950 *ebx = 0;
3951 *ecx = 0;
3952 *edx = 0;
3953 break;
3954 case 0xC0000001:
3955 /* Support for VIA CPU's CPUID instruction */
3956 *eax = env->cpuid_version;
3957 *ebx = 0;
3958 *ecx = 0;
0514ef2f 3959 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 3960 break;
3961 case 0xC0000002:
3962 case 0xC0000003:
3963 case 0xC0000004:
3964 /* Reserved for the future, and now filled with zero */
3965 *eax = 0;
3966 *ebx = 0;
3967 *ecx = 0;
3968 *edx = 0;
3969 break;
6cb8f2a6
BS		 3970 case 0x8000001F:
3971 *eax = sev_enabled() ? 0x2 : 0;
3972 *ebx = sev_get_cbit_position();
3973 *ebx |= sev_get_reduced_phys_bits() << 6;
3974 *ecx = 0;
3975 *edx = 0;
3976 break;
c6dc6f63
AP		 3977 default:
3978 /* reserved values: zero */
3979 *eax = 0;
3980 *ebx = 0;
3981 *ecx = 0;
3982 *edx = 0;
3983 break;
3984 }
3985}
5fd2087a
AF		 3986
3987/* CPUClass::reset() */
3988static void x86_cpu_reset(CPUState *s)
3989{
3990 X86CPU *cpu = X86_CPU(s);
3991 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
3992 CPUX86State *env = &cpu->env;
a114d25d
RH		 3993 target_ulong cr4;
3994 uint64_t xcr0;
c1958aea
AF		 3995 int i;
3996
5fd2087a
AF		 3997 xcc->parent_reset(s);
3998
5e992a8e 3999 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 4000
c1958aea
AF		 4001 env->old_exception = -1;
4002
4003 /* init to reset state */
4004
c1958aea
AF		 4005 env->hflags2 |= HF2_GIF_MASK;
4006
4007 cpu_x86_update_cr0(env, 0x60000010);
4008 env->a20_mask = ~0x0;
4009 env->smbase = 0x30000;
e13713db 4010 env->msr_smi_count = 0;
c1958aea
AF		 4011
4012 env->idt.limit = 0xffff;
4013 env->gdt.limit = 0xffff;
4014 env->ldt.limit = 0xffff;
4015 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4016 env->tr.limit = 0xffff;
4017 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4018
4019 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4020 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4021 DESC_R_MASK | DESC_A_MASK);
4022 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4023 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4024 DESC_A_MASK);
4025 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4026 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4027 DESC_A_MASK);
4028 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4029 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4030 DESC_A_MASK);
4031 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4032 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4033 DESC_A_MASK);
4034 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4035 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4036 DESC_A_MASK);
4037
4038 env->eip = 0xfff0;
4039 env->regs[R_EDX] = env->cpuid_version;
4040
4041 env->eflags = 0x2;
4042
4043 /* FPU init */
4044 for (i = 0; i < 8; i++) {
4045 env->fptags[i] = 1;
4046 }
5bde1407 4047 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 4048
4049 env->mxcsr = 0x1f80;
a114d25d
RH		 4050 /* All units are in INIT state. */
4051 env->xstate_bv = 0;
c1958aea
AF		 4052
4053 env->pat = 0x0007040600070406ULL;
4054 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4055
4056 memset(env->dr, 0, sizeof(env->dr));
4057 env->dr[6] = DR6_FIXED_1;
4058 env->dr[7] = DR7_FIXED_1;
b3310ab3 4059 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 4060 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 4061
a114d25d 4062 cr4 = 0;
cfc3b074 4063 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 4064
4065#ifdef CONFIG_USER_ONLY
4066 /* Enable all the features for user-mode. */
4067 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 4068 xcr0 |= XSTATE_SSE_MASK;
a114d25d 4069 }
0f70ed47
PB		 4070 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4071 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 4072 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 4073 xcr0 |= 1ull << i;
4074 }
a114d25d 4075 }
0f70ed47 4076
a114d25d
RH		 4077 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4078 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4079 }
07929f2a
RH		 4080 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4081 cr4 |= CR4_FSGSBASE_MASK;
4082 }
a114d25d
RH		 4083#endif
4084
4085 env->xcr0 = xcr0;
4086 cpu_x86_update_cr4(env, cr4);
0522604b 4087
9db2efd9
AW		 4088 /*
4089 * SDM 11.11.5 requires:
4090 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4091 * - IA32_MTRR_PHYSMASKn.V = 0
4092 * All other bits are undefined. For simplification, zero it all.
4093 */
4094 env->mtrr_deftype = 0;
4095 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4096 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4097
b7394c83
SAGDR		 4098 env->interrupt_injected = -1;
4099 env->exception_injected = -1;
4100 env->nmi_injected = false;
dd673288
IM		 4101#if !defined(CONFIG_USER_ONLY)
4102 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 4103 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 4104
259186a7 4105 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 4106
4107 if (kvm_enabled()) {
4108 kvm_arch_reset_vcpu(cpu);
4109 }
d6dcc558
SAGDR		 4110 else if (hvf_enabled()) {
4111 hvf_reset_vcpu(s);
4112 }
dd673288 4113#endif
5fd2087a
AF		 4114}
4115
dd673288
IM		 4116#ifndef CONFIG_USER_ONLY
4117bool cpu_is_bsp(X86CPU *cpu)
4118{
02e51483 4119 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 4120}
65dee380
IM		 4121
4122/* TODO: remove me, when reset over QOM tree is implemented */
4123static void x86_cpu_machine_reset_cb(void *opaque)
4124{
4125 X86CPU *cpu = opaque;
4126 cpu_reset(CPU(cpu));
4127}
dd673288
IM		 4128#endif
4129
de024815
AF		 4130static void mce_init(X86CPU *cpu)
4131{
4132 CPUX86State *cenv = &cpu->env;
4133 unsigned int bank;
4134
4135 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 4136 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 4137 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 4138 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4139 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 4140 cenv->mcg_ctl = ~(uint64_t)0;
4141 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4142 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4143 }
4144 }
4145}
4146
bdeec802 4147#ifndef CONFIG_USER_ONLY
2f114315 4148APICCommonClass *apic_get_class(void)
bdeec802 4149{
bdeec802
IM		 4150 const char *apic_type = "apic";
4151
d6dcc558 4152 /* TODO: in-kernel irqchip for hvf */
15eafc2e 4153 if (kvm_apic_in_kernel()) {
bdeec802
IM		 4154 apic_type = "kvm-apic";
4155 } else if (xen_enabled()) {
4156 apic_type = "xen-apic";
4157 }
4158
2f114315
RK		 4159 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4160}
4161
4162static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4163{
4164 APICCommonState *apic;
4165 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4166
4167 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 4168
6816b1b3
IM		 4169 object_property_add_child(OBJECT(cpu), "lapic",
4170 OBJECT(cpu->apic_state), &error_abort);
67e55caa 4171 object_unref(OBJECT(cpu->apic_state));
6816b1b3 4172
33d7a288 4173 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 4174 /* TODO: convert to link<> */
02e51483 4175 apic = APIC_COMMON(cpu->apic_state);
60671e58 4176 apic->cpu = cpu;
8d42d2d3 4177 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 4178}
4179
4180static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4181{
8d42d2d3
CF		 4182 APICCommonState *apic;
4183 static bool apic_mmio_map_once;
4184
02e51483 4185 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 4186 return;
4187 }
6e8e2651
MA		 4188 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4189 errp);
8d42d2d3
CF		 4190
4191 /* Map APIC MMIO area */
4192 apic = APIC_COMMON(cpu->apic_state);
4193 if (!apic_mmio_map_once) {
4194 memory_region_add_subregion_overlap(get_system_memory(),
4195 apic->apicbase &
4196 MSR_IA32_APICBASE_BASE,
4197 &apic->io_memory,
4198 0x1000);
4199 apic_mmio_map_once = true;
4200 }
bdeec802 4201}
f809c605
PB		 4202
4203static void x86_cpu_machine_done(Notifier *n, void *unused)
4204{
4205 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4206 MemoryRegion *smram =
4207 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4208
4209 if (smram) {
4210 cpu->smram = g_new(MemoryRegion, 1);
4211 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4212 smram, 0, 1ull << 32);
f8c45c65 4213 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 4214 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4215 }
4216}
d3c64d6a
IM		 4217#else
4218static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4219{
4220}
bdeec802
IM		 4221#endif
4222
11f6fee5
DDAG		 4223/* Note: Only safe for use on x86(-64) hosts */
4224static uint32_t x86_host_phys_bits(void)
4225{
4226 uint32_t eax;
4227 uint32_t host_phys_bits;
4228
4229 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4230 if (eax >= 0x80000008) {
4231 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4232 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4233 * at 23:16 that can specify a maximum physical address bits for
4234 * the guest that can override this value; but I've not seen
4235 * anything with that set.
4236 */
4237 host_phys_bits = eax & 0xff;
4238 } else {
4239 /* It's an odd 64 bit machine that doesn't have the leaf for
4240 * physical address bits; fall back to 36 that's most older
4241 * Intel.
4242 */
4243 host_phys_bits = 36;
4244 }
4245
4246 return host_phys_bits;
4247}
e48638fd 4248
c39c0edf
EH		 4249static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4250{
4251 if (*min < value) {
4252 *min = value;
4253 }
4254}
4255
4256/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4257static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4258{
4259 CPUX86State *env = &cpu->env;
4260 FeatureWordInfo *fi = &feature_word_info[w];
4261 uint32_t eax = fi->cpuid_eax;
4262 uint32_t region = eax & 0xF0000000;
4263
4264 if (!env->features[w]) {
4265 return;
4266 }
4267
4268 switch (region) {
4269 case 0x00000000:
4270 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4271 break;
4272 case 0x80000000:
4273 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4274 break;
4275 case 0xC0000000:
4276 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4277 break;
4278 }
4279}
4280
2ca8a8be
EH		 4281/* Calculate XSAVE components based on the configured CPU feature flags */
4282static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4283{
4284 CPUX86State *env = &cpu->env;
4285 int i;
96193c22 4286 uint64_t mask;
2ca8a8be
EH		 4287
4288 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4289 return;
4290 }
4291
e3c9022b
EH		 4292 mask = 0;
4293 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 4294 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4295 if (env->features[esa->feature] & esa->bits) {
96193c22 4296 mask |= (1ULL << i);
2ca8a8be
EH		 4297 }
4298 }
4299
96193c22
EH		 4300 env->features[FEAT_XSAVE_COMP_LO] = mask;
4301 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 4302}
4303
b8d834a0
EH		 4304/***** Steps involved on loading and filtering CPUID data
4305 *
4306 * When initializing and realizing a CPU object, the steps
4307 * involved in setting up CPUID data are:
4308 *
4309 * 1) Loading CPU model definition (X86CPUDefinition). This is
4310 * implemented by x86_cpu_load_def() and should be completely
4311 * transparent, as it is done automatically by instance_init.
4312 * No code should need to look at X86CPUDefinition structs
4313 * outside instance_init.
4314 *
4315 * 2) CPU expansion. This is done by realize before CPUID
4316 * filtering, and will make sure host/accelerator data is
4317 * loaded for CPU models that depend on host capabilities
4318 * (e.g. "host"). Done by x86_cpu_expand_features().
4319 *
4320 * 3) CPUID filtering. This initializes extra data related to
4321 * CPUID, and checks if the host supports all capabilities
4322 * required by the CPU. Runnability of a CPU model is
4323 * determined at this step. Done by x86_cpu_filter_features().
4324 *
4325 * Some operations don't require all steps to be performed.
4326 * More precisely:
4327 *
4328 * - CPU instance creation (instance_init) will run only CPU
4329 * model loading. CPU expansion can't run at instance_init-time
4330 * because host/accelerator data may be not available yet.
4331 * - CPU realization will perform both CPU model expansion and CPUID
4332 * filtering, and return an error in case one of them fails.
4333 * - query-cpu-definitions needs to run all 3 steps. It needs
4334 * to run CPUID filtering, as the 'unavailable-features'
4335 * field is set based on the filtering results.
4336 * - The query-cpu-model-expansion QMP command only needs to run
4337 * CPU model loading and CPU expansion. It should not filter
4338 * any CPUID data based on host capabilities.
4339 */
4340
4341/* Expand CPU configuration data, based on configured features
4342 * and host/accelerator capabilities when appropriate.
4343 */
4344static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 4345{
b34d12d1 4346 CPUX86State *env = &cpu->env;
dc15c051 4347 FeatureWord w;
2fae0d96 4348 GList *l;
41f3d4d6 4349 Error *local_err = NULL;
9886e834 4350
d4a606b3
EH		 4351 /*TODO: Now cpu->max_features doesn't overwrite features
4352 * set using QOM properties, and we can convert
dc15c051
IM		 4353 * plus_features & minus_features to global properties
4354 * inside x86_cpu_parse_featurestr() too.
4355 */
44bd8e53 4356 if (cpu->max_features) {
dc15c051 4357 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 4358 /* Override only features that weren't set explicitly
4359 * by the user.
4360 */
4361 env->features[w] |=
4362 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
0d914f39
EH		 4363 ~env->user_features[w] & \
4364 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 4365 }
4366 }
4367
2fae0d96
EH		 4368 for (l = plus_features; l; l = l->next) {
4369 const char *prop = l->data;
4370 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
4371 if (local_err) {
4372 goto out;
4373 }
4374 }
4375
4376 for (l = minus_features; l; l = l->next) {
4377 const char *prop = l->data;
4378 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
4379 if (local_err) {
4380 goto out;
4381 }
dc15c051
IM		 4382 }
4383
aec661de
EH		 4384 if (!kvm_enabled() || !cpu->expose_kvm) {
4385 env->features[FEAT_KVM] = 0;
4386 }
4387
2ca8a8be 4388 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 4389
4390 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
4391 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
4392 if (cpu->full_cpuid_auto_level) {
4393 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
4394 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
4395 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
4396 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
4397 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
4398 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
4399 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 4400 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 4401 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
4402 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
4403 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 4404 /* SVM requires CPUID[0x8000000A] */
4405 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
4406 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
4407 }
6cb8f2a6
BS		 4408
4409 /* SEV requires CPUID[0x8000001F] */
4410 if (sev_enabled()) {
4411 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
4412 }
c39c0edf
EH		 4413 }
4414
4415 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
4416 if (env->cpuid_level == UINT32_MAX) {
4417 env->cpuid_level = env->cpuid_min_level;
4418 }
4419 if (env->cpuid_xlevel == UINT32_MAX) {
4420 env->cpuid_xlevel = env->cpuid_min_xlevel;
4421 }
4422 if (env->cpuid_xlevel2 == UINT32_MAX) {
4423 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 4424 }
7a059953 4425
41f3d4d6
EH		 4426out:
4427 if (local_err != NULL) {
4428 error_propagate(errp, local_err);
4429 }
4430}
4431
b8d834a0
EH		 4432/*
4433 * Finishes initialization of CPUID data, filters CPU feature
4434 * words based on host availability of each feature.
4435 *
4436 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
4437 */
4438static int x86_cpu_filter_features(X86CPU *cpu)
4439{
4440 CPUX86State *env = &cpu->env;
4441 FeatureWord w;
4442 int rv = 0;
4443
4444 for (w = 0; w < FEATURE_WORDS; w++) {
4445 uint32_t host_feat =
4446 x86_cpu_get_supported_feature_word(w, false);
4447 uint32_t requested_features = env->features[w];
4448 env->features[w] &= host_feat;
4449 cpu->filtered_features[w] = requested_features & ~env->features[w];
4450 if (cpu->filtered_features[w]) {
4451 rv = 1;
4452 }
4453 }
4454
e37a5c7f
CP		 4455 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
4456 kvm_enabled()) {
4457 KVMState *s = CPU(cpu)->kvm_state;
4458 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
4459 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
4460 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
4461 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
4462 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
4463
4464 if (!eax_0 ||
4465 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
4466 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
4467 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
4468 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
4469 INTEL_PT_ADDR_RANGES_NUM) ||
4470 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96
LK		 4471 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
4472 (ecx_0 & INTEL_PT_IP_LIP)) {
e37a5c7f
CP		 4473 /*
4474 * Processor Trace capabilities aren't configurable, so if the
4475 * host can't emulate the capabilities we report on
4476 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
4477 */
4478 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
4479 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
4480 rv = 1;
4481 }
4482 }
4483
b8d834a0
EH		 4484 return rv;
4485}
4486
41f3d4d6
EH		 4487#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
4488 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
4489 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
4490#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
4491 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
4492 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
4493static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
4494{
4495 CPUState *cs = CPU(dev);
4496 X86CPU *cpu = X86_CPU(dev);
4497 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
4498 CPUX86State *env = &cpu->env;
4499 Error *local_err = NULL;
4500 static bool ht_warned;
4501
d6dcc558 4502 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
41f3d4d6
EH		 4503 char *name = x86_cpu_class_get_model_name(xcc);
4504 error_setg(&local_err, "CPU model '%s' requires KVM", name);
4505 g_free(name);
4506 goto out;
4507 }
4508
4509 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
4510 error_setg(errp, "apic-id property was not initialized properly");
4511 return;
4512 }
4513
b8d834a0 4514 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 4515 if (local_err) {
4516 goto out;
4517 }
4518
8ca30e86
EH		 4519 if (x86_cpu_filter_features(cpu) &&
4520 (cpu->check_cpuid || cpu->enforce_cpuid)) {
4521 x86_cpu_report_filtered_features(cpu);
4522 if (cpu->enforce_cpuid) {
4523 error_setg(&local_err,
d6dcc558 4524 accel_uses_host_cpuid() ?
8ca30e86
EH		 4525 "Host doesn't support requested features" :
4526 "TCG doesn't support requested features");
4527 goto out;
4528 }
9997cf7b
EH		 4529 }
4530
9b15cd9e
IM		 4531 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
4532 * CPUID[1].EDX.
4533 */
e48638fd 4534 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 4535 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
4536 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 4537 & CPUID_EXT2_AMD_ALIASES);
4538 }
4539
11f6fee5
DDAG		 4540 /* For 64bit systems think about the number of physical bits to present.
4541 * ideally this should be the same as the host; anything other than matching
4542 * the host can cause incorrect guest behaviour.
4543 * QEMU used to pick the magic value of 40 bits that corresponds to
4544 * consumer AMD devices but nothing else.
4545 */
af45907a 4546 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 4547 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 4548 uint32_t host_phys_bits = x86_host_phys_bits();
4549 static bool warned;
4550
4551 if (cpu->host_phys_bits) {
4552 /* The user asked for us to use the host physical bits */
4553 cpu->phys_bits = host_phys_bits;
4554 }
4555
4556 /* Print a warning if the user set it to a value that's not the
4557 * host value.
4558 */
4559 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
4560 !warned) {
3dc6f869
AF		 4561 warn_report("Host physical bits (%u)"
4562 " does not match phys-bits property (%u)",
4563 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 4564 warned = true;
4565 }
4566
4567 if (cpu->phys_bits &&
4568 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
4569 cpu->phys_bits < 32)) {
af45907a
DDAG		 4570 error_setg(errp, "phys-bits should be between 32 and %u "
4571 " (but is %u)",
4572 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
4573 return;
4574 }
4575 } else {
11f6fee5 4576 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 4577 error_setg(errp, "TCG only supports phys-bits=%u",
4578 TCG_PHYS_ADDR_BITS);
4579 return;
4580 }
4581 }
11f6fee5
DDAG		 4582 /* 0 means it was not explicitly set by the user (or by machine
4583 * compat_props or by the host code above). In this case, the default
4584 * is the value used by TCG (40).
4585 */
4586 if (cpu->phys_bits == 0) {
4587 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
4588 }
af45907a
DDAG		 4589 } else {
4590 /* For 32 bit systems don't use the user set value, but keep
4591 * phys_bits consistent with what we tell the guest.
4592 */
4593 if (cpu->phys_bits != 0) {
4594 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
4595 return;
4596 }
fefb41bf 4597
af45907a
DDAG		 4598 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
4599 cpu->phys_bits = 36;
4600 } else {
4601 cpu->phys_bits = 32;
4602 }
4603 }
ce5b1bbf
LV		 4604 cpu_exec_realizefn(cs, &local_err);
4605 if (local_err != NULL) {
4606 error_propagate(errp, local_err);
4607 return;
4608 }
42ecabaa 4609
65dee380
IM		 4610#ifndef CONFIG_USER_ONLY
4611 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 4612
0514ef2f 4613 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 4614 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 4615 if (local_err != NULL) {
4dc1f449 4616 goto out;
bdeec802
IM		 4617 }
4618 }
65dee380
IM		 4619#endif
4620
7a059953 4621 mce_init(cpu);
2001d0cd
PB		 4622
4623#ifndef CONFIG_USER_ONLY
4624 if (tcg_enabled()) {
f809c605 4625 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 4626 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 4627
4628 /* Outer container... */
4629 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 4630 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 4631
4632 /* ... with two regions inside: normal system memory with low
4633 * priority, and...
4634 */
4635 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
4636 get_system_memory(), 0, ~0ull);
4637 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
4638 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 4639
4640 cs->num_ases = 2;
80ceb07a
PX		 4641 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
4642 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 4643
4644 /* ... SMRAM with higher priority, linked from /machine/smram. */
4645 cpu->machine_done.notify = x86_cpu_machine_done;
4646 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 4647 }
4648#endif
4649
14a10fc3 4650 qemu_init_vcpu(cs);
d3c64d6a 4651
e48638fd
WH		 4652 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
4653 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
4654 * based on inputs (sockets,cores,threads), it is still better to gives
4655 * users a warning.
4656 *
4657 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
4658 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
4659 */
4660 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
4661 error_report("AMD CPU doesn't support hyperthreading. Please configure"
4662 " -smp options properly.");
4663 ht_warned = true;
4664 }
4665
d3c64d6a
IM		 4666 x86_cpu_apic_realize(cpu, &local_err);
4667 if (local_err != NULL) {
4668 goto out;
4669 }
14a10fc3 4670 cpu_reset(cs);
2b6f294c 4671
4dc1f449 4672 xcc->parent_realize(dev, &local_err);
2001d0cd 4673
4dc1f449
IM		 4674out:
4675 if (local_err != NULL) {
4676 error_propagate(errp, local_err);
4677 return;
4678 }
7a059953
AF		 4679}
4680
c884776e
IM		 4681static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
4682{
4683 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 4684 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
4685 Error *local_err = NULL;
c884776e
IM		 4686
4687#ifndef CONFIG_USER_ONLY
4688 cpu_remove_sync(CPU(dev));
4689 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
4690#endif
4691
4692 if (cpu->apic_state) {
4693 object_unparent(OBJECT(cpu->apic_state));
4694 cpu->apic_state = NULL;
4695 }
7bbc124e
LV		 4696
4697 xcc->parent_unrealize(dev, &local_err);
4698 if (local_err != NULL) {
4699 error_propagate(errp, local_err);
4700 return;
4701 }
c884776e
IM		 4702}
4703
38e5c119 4704typedef struct BitProperty {
a7b0ffac 4705 FeatureWord w;
38e5c119
EH		 4706 uint32_t mask;
4707} BitProperty;
4708
d7bce999
EB		 4709static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
4710 void *opaque, Error **errp)
38e5c119 4711{
a7b0ffac 4712 X86CPU *cpu = X86_CPU(obj);
38e5c119 4713 BitProperty *fp = opaque;
a7b0ffac
EH		 4714 uint32_t f = cpu->env.features[fp->w];
4715 bool value = (f & fp->mask) == fp->mask;
51e72bc1 4716 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 4717}
4718
d7bce999
EB		 4719static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
4720 void *opaque, Error **errp)
38e5c119
EH		 4721{
4722 DeviceState *dev = DEVICE(obj);
a7b0ffac 4723 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 4724 BitProperty *fp = opaque;
4725 Error *local_err = NULL;
4726 bool value;
4727
4728 if (dev->realized) {
4729 qdev_prop_set_after_realize(dev, name, errp);
4730 return;
4731 }
4732
51e72bc1 4733 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 4734 if (local_err) {
4735 error_propagate(errp, local_err);
4736 return;
4737 }
4738
4739 if (value) {
a7b0ffac 4740 cpu->env.features[fp->w] |= fp->mask;
38e5c119 4741 } else {
a7b0ffac 4742 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 4743 }
d4a606b3 4744 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 4745}
4746
4747static void x86_cpu_release_bit_prop(Object *obj, const char *name,
4748 void *opaque)
4749{
4750 BitProperty *prop = opaque;
4751 g_free(prop);
4752}
4753
4754/* Register a boolean property to get/set a single bit in a uint32_t field.
4755 *
4756 * The same property name can be registered multiple times to make it affect
4757 * multiple bits in the same FeatureWord. In that case, the getter will return
4758 * true only if all bits are set.
4759 */
4760static void x86_cpu_register_bit_prop(X86CPU *cpu,
4761 const char *prop_name,
a7b0ffac 4762 FeatureWord w,
38e5c119
EH		 4763 int bitnr)
4764{
4765 BitProperty *fp;
4766 ObjectProperty *op;
4767 uint32_t mask = (1UL << bitnr);
4768
4769 op = object_property_find(OBJECT(cpu), prop_name, NULL);
4770 if (op) {
4771 fp = op->opaque;
a7b0ffac 4772 assert(fp->w == w);
38e5c119
EH		 4773 fp->mask |= mask;
4774 } else {
4775 fp = g_new0(BitProperty, 1);
a7b0ffac 4776 fp->w = w;
38e5c119
EH		 4777 fp->mask = mask;
4778 object_property_add(OBJECT(cpu), prop_name, "bool",
4779 x86_cpu_get_bit_prop,
4780 x86_cpu_set_bit_prop,
4781 x86_cpu_release_bit_prop, fp, &error_abort);
4782 }
4783}
4784
4785static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
4786 FeatureWord w,
4787 int bitnr)
4788{
38e5c119 4789 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 4790 const char *name = fi->feat_names[bitnr];
38e5c119 4791
16d2fcaa 4792 if (!name) {
38e5c119
EH		 4793 return;
4794 }
4795
fc7dfd20
EH		 4796 /* Property names should use "-" instead of "_".
4797 * Old names containing underscores are registered as aliases
4798 * using object_property_add_alias()
4799 */
16d2fcaa
EH		 4800 assert(!strchr(name, '_'));
4801 /* aliases don't use "|" delimiters anymore, they are registered
4802 * manually using object_property_add_alias() */
4803 assert(!strchr(name, '|'));
a7b0ffac 4804 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 4805}
4806
d187e08d
AN		 4807static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
4808{
4809 X86CPU *cpu = X86_CPU(cs);
4810 CPUX86State *env = &cpu->env;
4811 GuestPanicInformation *panic_info = NULL;
4812
5e953812 4813 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 4814 panic_info = g_malloc0(sizeof(GuestPanicInformation));
4815
e8ed97a6 4816 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 4817
5e953812 4818 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 4819 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
4820 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
4821 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
4822 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
4823 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 4824 }
4825
4826 return panic_info;
4827}
4828static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
4829 const char *name, void *opaque,
4830 Error **errp)
4831{
4832 CPUState *cs = CPU(obj);
4833 GuestPanicInformation *panic_info;
4834
4835 if (!cs->crash_occurred) {
4836 error_setg(errp, "No crash occured");
4837 return;
4838 }
4839
4840 panic_info = x86_cpu_get_crash_info(cs);
4841 if (panic_info == NULL) {
4842 error_setg(errp, "No crash information");
4843 return;
4844 }
4845
4846 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
4847 errp);
4848 qapi_free_GuestPanicInformation(panic_info);
4849}
4850
de024815
AF		 4851static void x86_cpu_initfn(Object *obj)
4852{
55e5c285 4853 CPUState *cs = CPU(obj);
de024815 4854 X86CPU *cpu = X86_CPU(obj);
d940ee9b 4855 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 4856 CPUX86State *env = &cpu->env;
38e5c119 4857 FeatureWord w;
de024815 4858
c05efcb1 4859 cs->env_ptr = env;
71ad61d3
AF		 4860
4861 object_property_add(obj, "family", "int",
95b8519d 4862 x86_cpuid_version_get_family,
71ad61d3 4863 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 4864 object_property_add(obj, "model", "int",
67e30c83 4865 x86_cpuid_version_get_model,
c5291a4f 4866 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 4867 object_property_add(obj, "stepping", "int",
35112e41 4868 x86_cpuid_version_get_stepping,
036e2222 4869 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 4870 object_property_add_str(obj, "vendor",
4871 x86_cpuid_get_vendor,
4872 x86_cpuid_set_vendor, NULL);
938d4c25 4873 object_property_add_str(obj, "model-id",
63e886eb 4874 x86_cpuid_get_model_id,
938d4c25 4875 x86_cpuid_set_model_id, NULL);
89e48965
AF		 4876 object_property_add(obj, "tsc-frequency", "int",
4877 x86_cpuid_get_tsc_freq,
4878 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 4879 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
4880 x86_cpu_get_feature_words,
7e5292b5
EH		 4881 NULL, NULL, (void *)env->features, NULL);
4882 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
4883 x86_cpu_get_feature_words,
4884 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 4885
d187e08d
AN		 4886 object_property_add(obj, "crash-information", "GuestPanicInformation",
4887 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
4888
92067bf4 4889 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 4890
38e5c119
EH		 4891 for (w = 0; w < FEATURE_WORDS; w++) {
4892 int bitnr;
4893
4894 for (bitnr = 0; bitnr < 32; bitnr++) {
4895 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
4896 }
4897 }
4898
16d2fcaa
EH		 4899 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
4900 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
4901 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
4902 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
4903 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
4904 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
4905 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
4906
54b8dc7c
EH		 4907 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
4908 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
4909 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
4910 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
4911 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
4912 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
4913 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
4914 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
4915 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
4916 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
4917 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
4918 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
4919 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
4920 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
4921 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
4922 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
4923 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
4924 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
4925 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
4926 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
4927 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
4928
0bacd8b3
EH		 4929 if (xcc->cpu_def) {
4930 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
4931 }
de024815
AF		 4932}
4933
997395d3
IM		 4934static int64_t x86_cpu_get_arch_id(CPUState *cs)
4935{
4936 X86CPU *cpu = X86_CPU(cs);
997395d3 4937
7e72a45c 4938 return cpu->apic_id;
997395d3
IM		 4939}
4940
444d5590
AF		 4941static bool x86_cpu_get_paging_enabled(const CPUState *cs)
4942{
4943 X86CPU *cpu = X86_CPU(cs);
4944
4945 return cpu->env.cr[0] & CR0_PG_MASK;
4946}
4947
f45748f1
AF		 4948static void x86_cpu_set_pc(CPUState *cs, vaddr value)
4949{
4950 X86CPU *cpu = X86_CPU(cs);
4951
4952 cpu->env.eip = value;
4953}
4954
bdf7ae5b
AF		 4955static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
4956{
4957 X86CPU *cpu = X86_CPU(cs);
4958
4959 cpu->env.eip = tb->pc - tb->cs_base;
4960}
4961
8c2e1b00
AF		 4962static bool x86_cpu_has_work(CPUState *cs)
4963{
4964 X86CPU *cpu = X86_CPU(cs);
4965 CPUX86State *env = &cpu->env;
4966
6220e900
PD		 4967 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
4968 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 4969 (env->eflags & IF_MASK)) ||
4970 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
4971 CPU_INTERRUPT_INIT |
4972 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 4973 CPU_INTERRUPT_MCE)) ||
4974 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
4975 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 4976}
4977
f50f3dd5
RH		 4978static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
4979{
4980 X86CPU *cpu = X86_CPU(cs);
4981 CPUX86State *env = &cpu->env;
4982
4983 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
4984 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
4985 : bfd_mach_i386_i8086);
4986 info->print_insn = print_insn_i386;
b666d2a4
RH		 4987
4988 info->cap_arch = CS_ARCH_X86;
4989 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
4990 : env->hflags & HF_CS32_MASK ? CS_MODE_32
4991 : CS_MODE_16);
15fa1a0a
RH		 4992 info->cap_insn_unit = 1;
4993 info->cap_insn_split = 8;
f50f3dd5
RH		 4994}
4995
35b1b927
TW		 4996void x86_update_hflags(CPUX86State *env)
4997{
4998 uint32_t hflags;
4999#define HFLAG_COPY_MASK \
5000 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5001 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5002 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5003 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5004
5005 hflags = env->hflags & HFLAG_COPY_MASK;
5006 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5007 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5008 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5009 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5010 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5011
5012 if (env->cr[4] & CR4_OSFXSR_MASK) {
5013 hflags |= HF_OSFXSR_MASK;
5014 }
5015
5016 if (env->efer & MSR_EFER_LMA) {
5017 hflags |= HF_LMA_MASK;
5018 }
5019
5020 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5021 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5022 } else {
5023 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5024 (DESC_B_SHIFT - HF_CS32_SHIFT);
5025 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5026 (DESC_B_SHIFT - HF_SS32_SHIFT);
5027 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5028 !(hflags & HF_CS32_MASK)) {
5029 hflags |= HF_ADDSEG_MASK;
5030 } else {
5031 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5032 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5033 }
5034 }
5035 env->hflags = hflags;
5036}
5037
9337e3b6 5038static Property x86_cpu_properties[] = {
2da00e31
IM		 5039#ifdef CONFIG_USER_ONLY
5040 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5041 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 5042 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5043 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5044 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 5045#else
5046 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 5047 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5048 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5049 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 5050#endif
15f8b142 5051 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 5052 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 5053 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 5054 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 5055 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 5056 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 5057 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 5058 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 5059 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 5060 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 5061 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 5062 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
9445597b 5063 DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
ba6a4fd9 5064 DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment, false),
15e41345 5065 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 5066 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 5067 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 5068 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 5069 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 5070 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 5071 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5072 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5073 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5074 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5075 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5076 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5077 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 5078 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 5079 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 5080 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 5081 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 5082 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5083 false),
0b564e6f 5084 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 5085 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
6c69dfb6
GA		 5086
5087 /*
5088 * From "Requirements for Implementing the Microsoft
5089 * Hypervisor Interface":
5090 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5091 *
5092 * "Starting with Windows Server 2012 and Windows 8, if
5093 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5094 * the hypervisor imposes no specific limit to the number of VPs.
5095 * In this case, Windows Server 2012 guest VMs may use more than
5096 * 64 VPs, up to the maximum supported number of processors applicable
5097 * to the specific Windows version being used."
5098 */
5099 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9337e3b6
EH		 5100 DEFINE_PROP_END_OF_LIST()
5101};
5102
5fd2087a
AF		 5103static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5104{
5105 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5106 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 5107 DeviceClass *dc = DEVICE_CLASS(oc);
5108
bf853881
PMD		 5109 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5110 &xcc->parent_realize);
5111 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5112 &xcc->parent_unrealize);
9337e3b6 5113 dc->props = x86_cpu_properties;
5fd2087a
AF		 5114
5115 xcc->parent_reset = cc->reset;
5116 cc->reset = x86_cpu_reset;
91b1df8c 5117 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 5118
500050d1 5119 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 5120 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 5121 cc->has_work = x86_cpu_has_work;
79c664f6 5122#ifdef CONFIG_TCG
97a8ea5a 5123 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 5124 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 5125#endif
878096ee 5126 cc->dump_state = x86_cpu_dump_state;
c86f106b 5127 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 5128 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 5129 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 5130 cc->gdb_read_register = x86_cpu_gdb_read_register;
5131 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 5132 cc->get_arch_id = x86_cpu_get_arch_id;
5133 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 5134#ifdef CONFIG_USER_ONLY
5135 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
5136#else
f8c45c65 5137 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 5138 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 5139 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 5140 cc->write_elf64_note = x86_cpu_write_elf64_note;
5141 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5142 cc->write_elf32_note = x86_cpu_write_elf32_note;
5143 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 5144 cc->vmsd = &vmstate_x86_cpu;
c72bf468 5145#endif
00fcd100
AB		 5146 cc->gdb_arch_name = x86_gdb_arch_name;
5147#ifdef TARGET_X86_64
b8158192
AB		 5148 cc->gdb_core_xml_file = "i386-64bit.xml";
5149 cc->gdb_num_core_regs = 57;
00fcd100 5150#else
b8158192
AB		 5151 cc->gdb_core_xml_file = "i386-32bit.xml";
5152 cc->gdb_num_core_regs = 41;
00fcd100 5153#endif
79c664f6 5154#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 5155 cc->debug_excp_handler = breakpoint_handler;
5156#endif
374e0cd4
RH		 5157 cc->cpu_exec_enter = x86_cpu_exec_enter;
5158 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 5159#ifdef CONFIG_TCG
55c3ceef 5160 cc->tcg_initialize = tcg_x86_init;
74d7fc7f 5161#endif
f50f3dd5 5162 cc->disas_set_info = x86_disas_set_info;
4c315c27 5163
e90f2a8c 5164 dc->user_creatable = true;
5fd2087a
AF		 5165}
5166
5167static const TypeInfo x86_cpu_type_info = {
5168 .name = TYPE_X86_CPU,
5169 .parent = TYPE_CPU,
5170 .instance_size = sizeof(X86CPU),
de024815 5171 .instance_init = x86_cpu_initfn,
d940ee9b 5172 .abstract = true,
5fd2087a
AF		 5173 .class_size = sizeof(X86CPUClass),
5174 .class_init = x86_cpu_common_class_init,
5175};
5176
5adbed30
EH		 5177
5178/* "base" CPU model, used by query-cpu-model-expansion */
5179static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
5180{
5181 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5182
5183 xcc->static_model = true;
5184 xcc->migration_safe = true;
5185 xcc->model_description = "base CPU model type with no features enabled";
5186 xcc->ordering = 8;
5187}
5188
5189static const TypeInfo x86_base_cpu_type_info = {
5190 .name = X86_CPU_TYPE_NAME("base"),
5191 .parent = TYPE_X86_CPU,
5192 .class_init = x86_cpu_base_class_init,
5193};
5194
5fd2087a
AF		 5195static void x86_cpu_register_types(void)
5196{
d940ee9b
EH		 5197 int i;
5198
5fd2087a 5199 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 5200 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
5201 x86_register_cpudef_type(&builtin_x86_defs[i]);
5202 }
c62f2630 5203 type_register_static(&max_x86_cpu_type_info);
5adbed30 5204 type_register_static(&x86_base_cpu_type_info);
d6dcc558 5205#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 5206 type_register_static(&host_x86_cpu_type_info);
5207#endif
5fd2087a
AF		 5208}
5209
5210type_init(x86_cpu_register_types)
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