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i386: Helpers to encode cache information consistently
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
f348b6d1 21#include "qemu/cutils.h"
c6dc6f63
AP		 22
23#include "cpu.h"
63c91552 24#include "exec/exec-all.h"
9c17d615 25#include "sysemu/kvm.h"
d6dcc558 26#include "sysemu/hvf.h"
8932cfdf 27#include "sysemu/cpus.h"
50a2c6e5 28#include "kvm_i386.h"
6cb8f2a6 29#include "sev_i386.h"
c6dc6f63 30
d49b6836 31#include "qemu/error-report.h"
1de7afc9
PB		 32#include "qemu/option.h"
33#include "qemu/config-file.h"
e688df6b 34#include "qapi/error.h"
112ed241
MA		 35#include "qapi/qapi-visit-misc.h"
36#include "qapi/qapi-visit-run-state.h"
452fcdbc 37#include "qapi/qmp/qdict.h"
7b1b5d19 38#include "qapi/qmp/qerror.h"
7b1b5d19 39#include "qapi/visitor.h"
f99fd7ca 40#include "qom/qom-qobject.h"
9c17d615 41#include "sysemu/arch_init.h"
71ad61d3 42
b834b508 43#if defined(CONFIG_KVM)
ef8621b1 44#include <linux/kvm_para.h>
b834b508 45#endif
65dee380 46
9c17d615 47#include "sysemu/sysemu.h"
53a89e26 48#include "hw/qdev-properties.h"
5232d00a 49#include "hw/i386/topology.h"
bdeec802 50#ifndef CONFIG_USER_ONLY
2001d0cd 51#include "exec/address-spaces.h"
741da0d3 52#include "hw/hw.h"
0d09e41a 53#include "hw/xen/xen.h"
0d09e41a 54#include "hw/i386/apic_internal.h"
bdeec802
IM		 55#endif
56
b666d2a4
RH		 57#include "disas/capstone.h"
58
7e3482f8
EH		 59/* Helpers for building CPUID[2] descriptors: */
60
61struct CPUID2CacheDescriptorInfo {
62 enum CacheType type;
63 int level;
64 int size;
65 int line_size;
66 int associativity;
67};
5e891bf8 68
7e3482f8
EH		 69#define KiB 1024
70#define MiB (1024 * 1024)
5e891bf8 71
7e3482f8
EH		 72/*
73 * Known CPUID 2 cache descriptors.
74 * From Intel SDM Volume 2A, CPUID instruction
75 */
76struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
77 [0x06] = { .level = 1, .type = ICACHE, .size = 8 * KiB,
78 .associativity = 4, .line_size = 32, },
79 [0x08] = { .level = 1, .type = ICACHE, .size = 16 * KiB,
80 .associativity = 4, .line_size = 32, },
81 [0x09] = { .level = 1, .type = ICACHE, .size = 32 * KiB,
82 .associativity = 4, .line_size = 64, },
83 [0x0A] = { .level = 1, .type = DCACHE, .size = 8 * KiB,
84 .associativity = 2, .line_size = 32, },
85 [0x0C] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
86 .associativity = 4, .line_size = 32, },
87 [0x0D] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
88 .associativity = 4, .line_size = 64, },
89 [0x0E] = { .level = 1, .type = DCACHE, .size = 24 * KiB,
90 .associativity = 6, .line_size = 64, },
91 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
92 .associativity = 2, .line_size = 64, },
93 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
94 .associativity = 8, .line_size = 64, },
95 /* lines per sector is not supported cpuid2_cache_descriptor(),
96 * so descriptors 0x22, 0x23 are not included
97 */
98 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
99 .associativity = 16, .line_size = 64, },
100 /* lines per sector is not supported cpuid2_cache_descriptor(),
101 * so descriptors 0x25, 0x20 are not included
102 */
103 [0x2C] = { .level = 1, .type = DCACHE, .size = 32 * KiB,
104 .associativity = 8, .line_size = 64, },
105 [0x30] = { .level = 1, .type = ICACHE, .size = 32 * KiB,
106 .associativity = 8, .line_size = 64, },
107 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
108 .associativity = 4, .line_size = 32, },
109 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
110 .associativity = 4, .line_size = 32, },
111 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
112 .associativity = 4, .line_size = 32, },
113 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
114 .associativity = 4, .line_size = 32, },
115 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
116 .associativity = 4, .line_size = 32, },
117 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
118 .associativity = 4, .line_size = 64, },
119 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
120 .associativity = 8, .line_size = 64, },
121 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
122 .associativity = 12, .line_size = 64, },
123 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
124 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
125 .associativity = 12, .line_size = 64, },
126 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
127 .associativity = 16, .line_size = 64, },
128 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
129 .associativity = 12, .line_size = 64, },
130 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
131 .associativity = 16, .line_size = 64, },
132 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
133 .associativity = 24, .line_size = 64, },
134 [0x60] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
135 .associativity = 8, .line_size = 64, },
136 [0x66] = { .level = 1, .type = DCACHE, .size = 8 * KiB,
137 .associativity = 4, .line_size = 64, },
138 [0x67] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
139 .associativity = 4, .line_size = 64, },
140 [0x68] = { .level = 1, .type = DCACHE, .size = 32 * KiB,
141 .associativity = 4, .line_size = 64, },
142 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
143 .associativity = 4, .line_size = 64, },
144 /* lines per sector is not supported cpuid2_cache_descriptor(),
145 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
146 */
147 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
148 .associativity = 8, .line_size = 64, },
149 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
150 .associativity = 2, .line_size = 64, },
151 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
152 .associativity = 8, .line_size = 64, },
153 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
154 .associativity = 8, .line_size = 32, },
155 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
156 .associativity = 8, .line_size = 32, },
157 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
158 .associativity = 8, .line_size = 32, },
159 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
160 .associativity = 8, .line_size = 32, },
161 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
162 .associativity = 4, .line_size = 64, },
163 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
164 .associativity = 8, .line_size = 64, },
165 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
166 .associativity = 4, .line_size = 64, },
167 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
168 .associativity = 4, .line_size = 64, },
169 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
170 .associativity = 4, .line_size = 64, },
171 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
172 .associativity = 8, .line_size = 64, },
173 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
174 .associativity = 8, .line_size = 64, },
175 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
176 .associativity = 8, .line_size = 64, },
177 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
178 .associativity = 12, .line_size = 64, },
179 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
180 .associativity = 12, .line_size = 64, },
181 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
182 .associativity = 12, .line_size = 64, },
183 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
184 .associativity = 16, .line_size = 64, },
185 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
186 .associativity = 16, .line_size = 64, },
187 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
188 .associativity = 16, .line_size = 64, },
189 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
190 .associativity = 24, .line_size = 64, },
191 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
192 .associativity = 24, .line_size = 64, },
193 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
194 .associativity = 24, .line_size = 64, },
195};
196
197/*
198 * "CPUID leaf 2 does not report cache descriptor information,
199 * use CPUID leaf 4 to query cache parameters"
200 */
201#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 202
7e3482f8
EH		 203/*
204 * Return a CPUID 2 cache descriptor for a given cache.
205 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
206 */
207static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
208{
209 int i;
210
211 assert(cache->size > 0);
212 assert(cache->level > 0);
213 assert(cache->line_size > 0);
214 assert(cache->associativity > 0);
215 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
216 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
217 if (d->level == cache->level && d->type == cache->type &&
218 d->size == cache->size && d->line_size == cache->line_size &&
219 d->associativity == cache->associativity) {
220 return i;
221 }
222 }
5e891bf8 223
7e3482f8
EH		 224 return CACHE_DESCRIPTOR_UNAVAILABLE;
225}
5e891bf8
EH		 226
227/* CPUID Leaf 4 constants: */
228
229/* EAX: */
7e3482f8
EH		 230#define CACHE_TYPE_D 1
231#define CACHE_TYPE_I 2
232#define CACHE_TYPE_UNIFIED 3
5e891bf8 233
7e3482f8 234#define CACHE_LEVEL(l) (l << 5)
5e891bf8 235
7e3482f8 236#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 237
238/* EDX: */
7e3482f8
EH		 239#define CACHE_NO_INVD_SHARING (1 << 0)
240#define CACHE_INCLUSIVE (1 << 1)
241#define CACHE_COMPLEX_IDX (1 << 2)
242
243/* Encode CacheType for CPUID[4].EAX */
244#define CACHE_TYPE(t) (((t) == DCACHE) ? CACHE_TYPE_D : \
245 ((t) == ICACHE) ? CACHE_TYPE_I : \
246 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
247 0 /* Invalid value */)
248
249
250/* Encode cache info for CPUID[4] */
251static void encode_cache_cpuid4(CPUCacheInfo *cache,
252 int num_apic_ids, int num_cores,
253 uint32_t *eax, uint32_t *ebx,
254 uint32_t *ecx, uint32_t *edx)
255{
256 assert(cache->size == cache->line_size * cache->associativity *
257 cache->partitions * cache->sets);
258
259 assert(num_apic_ids > 0);
260 *eax = CACHE_TYPE(cache->type) |
261 CACHE_LEVEL(cache->level) |
262 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
263 ((num_cores - 1) << 26) |
264 ((num_apic_ids - 1) << 14);
265
266 assert(cache->line_size > 0);
267 assert(cache->partitions > 0);
268 assert(cache->associativity > 0);
269 /* We don't implement fully-associative caches */
270 assert(cache->associativity < cache->sets);
271 *ebx = (cache->line_size - 1) |
272 ((cache->partitions - 1) << 12) |
273 ((cache->associativity - 1) << 22);
274
275 assert(cache->sets > 0);
276 *ecx = cache->sets - 1;
277
278 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
279 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
280 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
281}
282
283/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
284static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
285{
286 assert(cache->size % 1024 == 0);
287 assert(cache->lines_per_tag > 0);
288 assert(cache->associativity > 0);
289 assert(cache->line_size > 0);
290 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
291 (cache->lines_per_tag << 8) | (cache->line_size);
292}
5e891bf8
EH		 293
294#define ASSOC_FULL 0xFF
295
296/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
297#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
298 a == 2 ? 0x2 : \
299 a == 4 ? 0x4 : \
300 a == 8 ? 0x6 : \
301 a == 16 ? 0x8 : \
302 a == 32 ? 0xA : \
303 a == 48 ? 0xB : \
304 a == 64 ? 0xC : \
305 a == 96 ? 0xD : \
306 a == 128 ? 0xE : \
307 a == ASSOC_FULL ? 0xF : \
308 0 /* invalid value */)
309
7e3482f8
EH		 310/*
311 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
312 * @l3 can be NULL.
313 */
314static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
315 CPUCacheInfo *l3,
316 uint32_t *ecx, uint32_t *edx)
317{
318 assert(l2->size % 1024 == 0);
319 assert(l2->associativity > 0);
320 assert(l2->lines_per_tag > 0);
321 assert(l2->line_size > 0);
322 *ecx = ((l2->size / 1024) << 16) |
323 (AMD_ENC_ASSOC(l2->associativity) << 12) |
324 (l2->lines_per_tag << 8) | (l2->line_size);
325
326 if (l3) {
327 assert(l3->size % (512 * 1024) == 0);
328 assert(l3->associativity > 0);
329 assert(l3->lines_per_tag > 0);
330 assert(l3->line_size > 0);
331 *edx = ((l3->size / (512 * 1024)) << 18) |
332 (AMD_ENC_ASSOC(l3->associativity) << 12) |
333 (l3->lines_per_tag << 8) | (l3->line_size);
334 } else {
335 *edx = 0;
336 }
337}
5e891bf8
EH		 338
339/* Definitions of the hardcoded cache entries we expose: */
340
341/* L1 data cache: */
7e3482f8
EH		 342static CPUCacheInfo l1d_cache = {
343 .type = DCACHE,
344 .level = 1,
345 .size = 32 * KiB,
346 .self_init = 1,
347 .line_size = 64,
348 .associativity = 8,
349 .sets = 64,
350 .partitions = 1,
351 .no_invd_sharing = true,
352};
353
5e891bf8 354/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
7e3482f8
EH		 355static CPUCacheInfo l1d_cache_amd = {
356 .type = DCACHE,
357 .level = 1,
358 .size = 64 * KiB,
359 .self_init = 1,
360 .line_size = 64,
361 .associativity = 2,
362 .sets = 512,
363 .partitions = 1,
364 .lines_per_tag = 1,
365 .no_invd_sharing = true,
366};
5e891bf8
EH		 367
368/* L1 instruction cache: */
7e3482f8
EH		 369static CPUCacheInfo l1i_cache = {
370 .type = ICACHE,
371 .level = 1,
372 .size = 32 * KiB,
373 .self_init = 1,
374 .line_size = 64,
375 .associativity = 8,
376 .sets = 64,
377 .partitions = 1,
378 .no_invd_sharing = true,
379};
380
5e891bf8 381/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
7e3482f8
EH		 382static CPUCacheInfo l1i_cache_amd = {
383 .type = ICACHE,
384 .level = 1,
385 .size = 64 * KiB,
386 .self_init = 1,
387 .line_size = 64,
388 .associativity = 2,
389 .sets = 512,
390 .partitions = 1,
391 .lines_per_tag = 1,
392 .no_invd_sharing = true,
393};
5e891bf8
EH		 394
395/* Level 2 unified cache: */
7e3482f8
EH		 396static CPUCacheInfo l2_cache = {
397 .type = UNIFIED_CACHE,
398 .level = 2,
399 .size = 4 * MiB,
400 .self_init = 1,
401 .line_size = 64,
402 .associativity = 16,
403 .sets = 4096,
404 .partitions = 1,
405 .no_invd_sharing = true,
406};
407
5e891bf8 408/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
7e3482f8
EH		 409static CPUCacheInfo l2_cache_cpuid2 = {
410 .type = UNIFIED_CACHE,
411 .level = 2,
412 .size = 2 * MiB,
413 .line_size = 64,
414 .associativity = 8,
415};
416
417
5e891bf8 418/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
7e3482f8
EH		 419static CPUCacheInfo l2_cache_amd = {
420 .type = UNIFIED_CACHE,
421 .level = 2,
422 .size = 512 * KiB,
423 .line_size = 64,
424 .lines_per_tag = 1,
425 .associativity = 16,
426 .sets = 512,
427 .partitions = 1,
428};
5e891bf8 429
14c985cf 430/* Level 3 unified cache: */
7e3482f8
EH		 431static CPUCacheInfo l3_cache = {
432 .type = UNIFIED_CACHE,
433 .level = 3,
434 .size = 16 * MiB,
435 .line_size = 64,
436 .associativity = 16,
437 .sets = 16384,
438 .partitions = 1,
439 .lines_per_tag = 1,
440 .self_init = true,
441 .inclusive = true,
442 .complex_indexing = true,
443};
5e891bf8
EH		 444
445/* TLB definitions: */
446
447#define L1_DTLB_2M_ASSOC 1
448#define L1_DTLB_2M_ENTRIES 255
449#define L1_DTLB_4K_ASSOC 1
450#define L1_DTLB_4K_ENTRIES 255
451
452#define L1_ITLB_2M_ASSOC 1
453#define L1_ITLB_2M_ENTRIES 255
454#define L1_ITLB_4K_ASSOC 1
455#define L1_ITLB_4K_ENTRIES 255
456
457#define L2_DTLB_2M_ASSOC 0 /* disabled */
458#define L2_DTLB_2M_ENTRIES 0 /* disabled */
459#define L2_DTLB_4K_ASSOC 4
460#define L2_DTLB_4K_ENTRIES 512
461
462#define L2_ITLB_2M_ASSOC 0 /* disabled */
463#define L2_ITLB_2M_ENTRIES 0 /* disabled */
464#define L2_ITLB_4K_ASSOC 4
465#define L2_ITLB_4K_ENTRIES 512
466
e37a5c7f
CP		 467/* CPUID Leaf 0x14 constants: */
468#define INTEL_PT_MAX_SUBLEAF 0x1
469/*
470 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
471 * MSR can be accessed;
472 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
473 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
474 * of Intel PT MSRs across warm reset;
475 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
476 */
477#define INTEL_PT_MINIMAL_EBX 0xf
478/*
479 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
480 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
481 * accessed;
482 * bit[01]: ToPA tables can hold any number of output entries, up to the
483 * maximum allowed by the MaskOrTableOffset field of
484 * IA32_RTIT_OUTPUT_MASK_PTRS;
485 * bit[02]: Support Single-Range Output scheme;
486 */
487#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 488/* generated packets which contain IP payloads have LIP values */
489#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 490#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
491#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
492#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
493#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
494#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 495
99b88a17
IM		 496static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
497 uint32_t vendor2, uint32_t vendor3)
498{
499 int i;
500 for (i = 0; i < 4; i++) {
501 dst[i] = vendor1 >> (8 * i);
502 dst[i + 4] = vendor2 >> (8 * i);
503 dst[i + 8] = vendor3 >> (8 * i);
504 }
505 dst[CPUID_VENDOR_SZ] = '\0';
506}
507
621626ce
EH		 508#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
509#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
510 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
511#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
512 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
513 CPUID_PSE36 | CPUID_FXSR)
514#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
515#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
516 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
517 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
518 CPUID_PAE | CPUID_SEP | CPUID_APIC)
519
520#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
521 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
522 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
523 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 524 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 525 /* partly implemented:
526 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
527 /* missing:
528 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
529#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
530 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
531 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 532 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 533 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
534 /* missing:
535 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
536 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
537 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 538 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
539 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 540
541#ifdef TARGET_X86_64
542#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
543#else
544#define TCG_EXT2_X86_64_FEATURES 0
545#endif
546
547#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
548 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
549 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
550 TCG_EXT2_X86_64_FEATURES)
551#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
552 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
553#define TCG_EXT4_FEATURES 0
554#define TCG_SVM_FEATURES 0
555#define TCG_KVM_FEATURES 0
556#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 557 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
558 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 559 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
560 CPUID_7_0_EBX_ERMS)
621626ce 561 /* missing:
07929f2a 562 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 563 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 564 CPUID_7_0_EBX_RDSEED */
6c7c3c21
KS		 565#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
566 CPUID_7_0_ECX_LA57)
95ea69fb 567#define TCG_7_0_EDX_FEATURES 0
303752a9 568#define TCG_APM_FEATURES 0
28b8e4d0 569#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 570#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
571 /* missing:
572 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 573
5ef57876 574typedef struct FeatureWordInfo {
2d5312da
EH		 575 /* feature flags names are taken from "Intel Processor Identification and
576 * the CPUID Instruction" and AMD's "CPUID Specification".
577 * In cases of disagreement between feature naming conventions,
578 * aliases may be added.
579 */
580 const char *feat_names[32];
04d104b6
EH		 581 uint32_t cpuid_eax; /* Input EAX for CPUID */
582 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
583 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
584 int cpuid_reg; /* output register (R_* constant) */
37ce3522 585 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 586 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 587 uint32_t migratable_flags; /* Feature flags known to be migratable */
0d914f39
EH		 588 /* Features that shouldn't be auto-enabled by "-cpu host" */
589 uint32_t no_autoenable_flags;
5ef57876
EH		 590} FeatureWordInfo;
591
592static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 593 [FEAT_1_EDX] = {
2d5312da
EH		 594 .feat_names = {
595 "fpu", "vme", "de", "pse",
596 "tsc", "msr", "pae", "mce",
597 "cx8", "apic", NULL, "sep",
598 "mtrr", "pge", "mca", "cmov",
599 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
600 NULL, "ds" /* Intel dts */, "acpi", "mmx",
601 "fxsr", "sse", "sse2", "ss",
602 "ht" /* Intel htt */, "tm", "ia64", "pbe",
603 },
bffd67b0 604 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 605 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 606 },
607 [FEAT_1_ECX] = {
2d5312da 608 .feat_names = {
16d2fcaa 609 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 610 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 611 "tm2", "ssse3", "cid", NULL,
612 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 613 NULL, "pcid", "dca", "sse4.1",
614 "sse4.2", "x2apic", "movbe", "popcnt",
2d5312da
EH		 615 "tsc-deadline", "aes", "xsave", "osxsave",
616 "avx", "f16c", "rdrand", "hypervisor",
617 },
bffd67b0 618 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 619 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 620 },
2d5312da
EH		 621 /* Feature names that are already defined on feature_name[] but
622 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
623 * names on feat_names below. They are copied automatically
624 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
625 */
bffd67b0 626 [FEAT_8000_0001_EDX] = {
2d5312da
EH		 627 .feat_names = {
628 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
629 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
630 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
631 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
632 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 633 "nx", NULL, "mmxext", NULL /* mmx */,
634 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
635 NULL, "lm", "3dnowext", "3dnow",
2d5312da 636 },
bffd67b0 637 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 638 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 639 },
640 [FEAT_8000_0001_ECX] = {
2d5312da 641 .feat_names = {
fc7dfd20 642 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 643 "cr8legacy", "abm", "sse4a", "misalignsse",
644 "3dnowprefetch", "osvw", "ibs", "xop",
645 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 646 "fma4", "tce", NULL, "nodeid-msr",
647 NULL, "tbm", "topoext", "perfctr-core",
648 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 649 NULL, NULL, NULL, NULL,
650 },
bffd67b0 651 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 652 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 653 },
89e49c8b 654 [FEAT_C000_0001_EDX] = {
2d5312da
EH		 655 .feat_names = {
656 NULL, NULL, "xstore", "xstore-en",
657 NULL, NULL, "xcrypt", "xcrypt-en",
658 "ace2", "ace2-en", "phe", "phe-en",
659 "pmm", "pmm-en", NULL, NULL,
660 NULL, NULL, NULL, NULL,
661 NULL, NULL, NULL, NULL,
662 NULL, NULL, NULL, NULL,
663 NULL, NULL, NULL, NULL,
664 },
89e49c8b 665 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 666 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 667 },
bffd67b0 668 [FEAT_KVM] = {
2d5312da 669 .feat_names = {
fc7dfd20
EH		 670 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
671 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
6976af66 672 NULL, "kvm-pv-tlb-flush", NULL, NULL,
2d5312da
EH		 673 NULL, NULL, NULL, NULL,
674 NULL, NULL, NULL, NULL,
675 NULL, NULL, NULL, NULL,
676 "kvmclock-stable-bit", NULL, NULL, NULL,
677 NULL, NULL, NULL, NULL,
678 },
bffd67b0 679 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 680 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 681 },
be777326
WL		 682 [FEAT_KVM_HINTS] = {
683 .feat_names = {
684 "kvm-hint-dedicated", NULL, NULL, NULL,
685 NULL, NULL, NULL, NULL,
686 NULL, NULL, NULL, NULL,
687 NULL, NULL, NULL, NULL,
688 NULL, NULL, NULL, NULL,
689 NULL, NULL, NULL, NULL,
690 NULL, NULL, NULL, NULL,
691 NULL, NULL, NULL, NULL,
692 },
693 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EDX,
694 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 695 /*
696 * KVM hints aren't auto-enabled by -cpu host, they need to be
697 * explicitly enabled in the command-line.
698 */
699 .no_autoenable_flags = ~0U,
be777326 700 },
c35bd19a 701 [FEAT_HYPERV_EAX] = {
2d5312da
EH		 702 .feat_names = {
703 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
704 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
705 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
706 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
707 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
708 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
ba6a4fd9
VK		 709 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
710 NULL, NULL,
2d5312da
EH		 711 NULL, NULL, NULL, NULL,
712 NULL, NULL, NULL, NULL,
713 NULL, NULL, NULL, NULL,
714 NULL, NULL, NULL, NULL,
715 },
c35bd19a
EY		 716 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
717 },
718 [FEAT_HYPERV_EBX] = {
2d5312da
EH		 719 .feat_names = {
720 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
721 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
722 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
723 NULL /* hv_create_port */, NULL /* hv_connect_port */,
724 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
725 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
726 NULL, NULL,
727 NULL, NULL, NULL, NULL,
728 NULL, NULL, NULL, NULL,
729 NULL, NULL, NULL, NULL,
730 NULL, NULL, NULL, NULL,
731 },
c35bd19a
EY		 732 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
733 },
734 [FEAT_HYPERV_EDX] = {
2d5312da
EH		 735 .feat_names = {
736 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
737 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
738 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
739 NULL, NULL,
740 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
741 NULL, NULL, NULL, NULL,
742 NULL, NULL, NULL, NULL,
743 NULL, NULL, NULL, NULL,
744 NULL, NULL, NULL, NULL,
745 NULL, NULL, NULL, NULL,
746 },
c35bd19a
EY		 747 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
748 },
bffd67b0 749 [FEAT_SVM] = {
2d5312da 750 .feat_names = {
fc7dfd20
EH		 751 "npt", "lbrv", "svm-lock", "nrip-save",
752 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
753 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 754 "pfthreshold", NULL, NULL, NULL,
755 NULL, NULL, NULL, NULL,
756 NULL, NULL, NULL, NULL,
757 NULL, NULL, NULL, NULL,
758 NULL, NULL, NULL, NULL,
759 },
bffd67b0 760 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 761 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 762 },
763 [FEAT_7_0_EBX] = {
2d5312da 764 .feat_names = {
fc7dfd20 765 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 766 "hle", "avx2", NULL, "smep",
767 "bmi2", "erms", "invpcid", "rtm",
768 NULL, NULL, "mpx", NULL,
769 "avx512f", "avx512dq", "rdseed", "adx",
770 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 771 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 772 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 773 },
04d104b6
EH		 774 .cpuid_eax = 7,
775 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
776 .cpuid_reg = R_EBX,
37ce3522 777 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 778 },
f74eefe0 779 [FEAT_7_0_ECX] = {
2d5312da
EH		 780 .feat_names = {
781 NULL, "avx512vbmi", "umip", "pku",
aff9e6e4
YZ		 782 "ospke", NULL, "avx512vbmi2", NULL,
783 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
784 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 785 "la57", NULL, NULL, NULL,
2d5312da 786 NULL, NULL, "rdpid", NULL,
0da0fb06 787 NULL, "cldemote", NULL, NULL,
2d5312da
EH		 788 NULL, NULL, NULL, NULL,
789 },
f74eefe0
HH		 790 .cpuid_eax = 7,
791 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
792 .cpuid_reg = R_ECX,
793 .tcg_features = TCG_7_0_ECX_FEATURES,
794 },
95ea69fb
LK		 795 [FEAT_7_0_EDX] = {
796 .feat_names = {
797 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
798 NULL, NULL, NULL, NULL,
799 NULL, NULL, NULL, NULL,
800 NULL, NULL, NULL, NULL,
801 NULL, NULL, NULL, NULL,
802 NULL, NULL, NULL, NULL,
a2381f09 803 NULL, NULL, "spec-ctrl", NULL,
95ea69fb
LK		 804 NULL, NULL, NULL, NULL,
805 },
806 .cpuid_eax = 7,
807 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
808 .cpuid_reg = R_EDX,
809 .tcg_features = TCG_7_0_EDX_FEATURES,
810 },
303752a9 811 [FEAT_8000_0007_EDX] = {
2d5312da
EH		 812 .feat_names = {
813 NULL, NULL, NULL, NULL,
814 NULL, NULL, NULL, NULL,
815 "invtsc", NULL, NULL, NULL,
816 NULL, NULL, NULL, NULL,
817 NULL, NULL, NULL, NULL,
818 NULL, NULL, NULL, NULL,
819 NULL, NULL, NULL, NULL,
820 NULL, NULL, NULL, NULL,
821 },
303752a9
MT		 822 .cpuid_eax = 0x80000007,
823 .cpuid_reg = R_EDX,
824 .tcg_features = TCG_APM_FEATURES,
825 .unmigratable_flags = CPUID_APM_INVTSC,
826 },
1b3420e1
EH		 827 [FEAT_8000_0008_EBX] = {
828 .feat_names = {
829 NULL, NULL, NULL, NULL,
830 NULL, NULL, NULL, NULL,
831 NULL, NULL, NULL, NULL,
832 "ibpb", NULL, NULL, NULL,
833 NULL, NULL, NULL, NULL,
834 NULL, NULL, NULL, NULL,
835 NULL, NULL, NULL, NULL,
836 NULL, NULL, NULL, NULL,
837 },
838 .cpuid_eax = 0x80000008,
839 .cpuid_reg = R_EBX,
840 .tcg_features = 0,
841 .unmigratable_flags = 0,
842 },
0bb0b2d2 843 [FEAT_XSAVE] = {
2d5312da
EH		 844 .feat_names = {
845 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
846 NULL, NULL, NULL, NULL,
847 NULL, NULL, NULL, NULL,
848 NULL, NULL, NULL, NULL,
849 NULL, NULL, NULL, NULL,
850 NULL, NULL, NULL, NULL,
851 NULL, NULL, NULL, NULL,
852 NULL, NULL, NULL, NULL,
853 },
0bb0b2d2
PB		 854 .cpuid_eax = 0xd,
855 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
856 .cpuid_reg = R_EAX,
c9cfe8f9 857 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 858 },
28b8e4d0 859 [FEAT_6_EAX] = {
2d5312da
EH		 860 .feat_names = {
861 NULL, NULL, "arat", NULL,
862 NULL, NULL, NULL, NULL,
863 NULL, NULL, NULL, NULL,
864 NULL, NULL, NULL, NULL,
865 NULL, NULL, NULL, NULL,
866 NULL, NULL, NULL, NULL,
867 NULL, NULL, NULL, NULL,
868 NULL, NULL, NULL, NULL,
869 },
28b8e4d0
JK		 870 .cpuid_eax = 6, .cpuid_reg = R_EAX,
871 .tcg_features = TCG_6_EAX_FEATURES,
872 },
96193c22
EH		 873 [FEAT_XSAVE_COMP_LO] = {
874 .cpuid_eax = 0xD,
875 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
876 .cpuid_reg = R_EAX,
877 .tcg_features = ~0U,
6fb2fff7
EH		 878 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
879 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
880 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
881 XSTATE_PKRU_MASK,
96193c22
EH		 882 },
883 [FEAT_XSAVE_COMP_HI] = {
884 .cpuid_eax = 0xD,
885 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
886 .cpuid_reg = R_EDX,
887 .tcg_features = ~0U,
888 },
5ef57876
EH		 889};
890
8e8aba50
EH		 891typedef struct X86RegisterInfo32 {
892 /* Name of register */
893 const char *name;
894 /* QAPI enum value register */
895 X86CPURegister32 qapi_enum;
896} X86RegisterInfo32;
897
898#define REGISTER(reg) \
5d371f41 899 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 900static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 901 REGISTER(EAX),
902 REGISTER(ECX),
903 REGISTER(EDX),
904 REGISTER(EBX),
905 REGISTER(ESP),
906 REGISTER(EBP),
907 REGISTER(ESI),
908 REGISTER(EDI),
909};
910#undef REGISTER
911
3f32bd21
RH		 912typedef struct ExtSaveArea {
913 uint32_t feature, bits;
914 uint32_t offset, size;
915} ExtSaveArea;
916
917static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 918 [XSTATE_FP_BIT] = {
919 /* x87 FP state component is always enabled if XSAVE is supported */
920 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
921 /* x87 state is in the legacy region of the XSAVE area */
922 .offset = 0,
923 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
924 },
925 [XSTATE_SSE_BIT] = {
926 /* SSE state component is always enabled if XSAVE is supported */
927 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
928 /* SSE state is in the legacy region of the XSAVE area */
929 .offset = 0,
930 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
931 },
cfc3b074
PB		 932 [XSTATE_YMM_BIT] =
933 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 934 .offset = offsetof(X86XSaveArea, avx_state),
935 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 936 [XSTATE_BNDREGS_BIT] =
937 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 938 .offset = offsetof(X86XSaveArea, bndreg_state),
939 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 940 [XSTATE_BNDCSR_BIT] =
941 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 942 .offset = offsetof(X86XSaveArea, bndcsr_state),
943 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 944 [XSTATE_OPMASK_BIT] =
945 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 946 .offset = offsetof(X86XSaveArea, opmask_state),
947 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 948 [XSTATE_ZMM_Hi256_BIT] =
949 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 950 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
951 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 952 [XSTATE_Hi16_ZMM_BIT] =
953 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 954 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
955 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 956 [XSTATE_PKRU_BIT] =
957 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 958 .offset = offsetof(X86XSaveArea, pkru_state),
959 .size = sizeof(XSavePKRU) },
2560f19f 960};
8e8aba50 961
1fda6198
EH		 962static uint32_t xsave_area_size(uint64_t mask)
963{
964 int i;
e3c9022b 965 uint64_t ret = 0;
1fda6198 966
e3c9022b 967 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 968 const ExtSaveArea *esa = &x86_ext_save_areas[i];
969 if ((mask >> i) & 1) {
970 ret = MAX(ret, esa->offset + esa->size);
971 }
972 }
973 return ret;
974}
975
d6dcc558
SAGDR		 976static inline bool accel_uses_host_cpuid(void)
977{
978 return kvm_enabled() || hvf_enabled();
979}
980
96193c22
EH		 981static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
982{
983 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
984 cpu->env.features[FEAT_XSAVE_COMP_LO];
985}
986
8b4beddc
EH		 987const char *get_register_name_32(unsigned int reg)
988{
31ccdde2 989 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 990 return NULL;
991 }
8e8aba50 992 return x86_reg_info_32[reg].name;
8b4beddc
EH		 993}
994
84f1b92f
EH		 995/*
996 * Returns the set of feature flags that are supported and migratable by
997 * QEMU, for a given FeatureWord.
998 */
999static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1000{
1001 FeatureWordInfo *wi = &feature_word_info[w];
1002 uint32_t r = 0;
1003 int i;
1004
1005 for (i = 0; i < 32; i++) {
1006 uint32_t f = 1U << i;
6fb2fff7
EH		 1007
1008 /* If the feature name is known, it is implicitly considered migratable,
1009 * unless it is explicitly set in unmigratable_flags */
1010 if ((wi->migratable_flags & f) ||
1011 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1012 r |= f;
84f1b92f 1013 }
84f1b92f
EH		 1014 }
1015 return r;
1016}
1017
bb44e0d1
JK		 1018void host_cpuid(uint32_t function, uint32_t count,
1019 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1020{
a1fd24af
AL		 1021 uint32_t vec[4];
1022
1023#ifdef __x86_64__
1024 asm volatile("cpuid"
1025 : "=a"(vec[0]), "=b"(vec[1]),
1026 "=c"(vec[2]), "=d"(vec[3])
1027 : "0"(function), "c"(count) : "cc");
c1f41226 1028#elif defined(__i386__)
a1fd24af
AL		 1029 asm volatile("pusha \n\t"
1030 "cpuid \n\t"
1031 "mov %%eax, 0(%2) \n\t"
1032 "mov %%ebx, 4(%2) \n\t"
1033 "mov %%ecx, 8(%2) \n\t"
1034 "mov %%edx, 12(%2) \n\t"
1035 "popa"
1036 : : "a"(function), "c"(count), "S"(vec)
1037 : "memory", "cc");
c1f41226
EH		 1038#else
1039 abort();
a1fd24af
AL		 1040#endif
1041
bdde476a 1042 if (eax)
a1fd24af 1043 *eax = vec[0];
bdde476a 1044 if (ebx)
a1fd24af 1045 *ebx = vec[1];
bdde476a 1046 if (ecx)
a1fd24af 1047 *ecx = vec[2];
bdde476a 1048 if (edx)
a1fd24af 1049 *edx = vec[3];
bdde476a 1050}
c6dc6f63 1051
20271d48
EH		 1052void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1053{
1054 uint32_t eax, ebx, ecx, edx;
1055
1056 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1057 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1058
1059 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1060 if (family) {
1061 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1062 }
1063 if (model) {
1064 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1065 }
1066 if (stepping) {
1067 *stepping = eax & 0x0F;
1068 }
1069}
1070
d940ee9b
EH		 1071/* CPU class name definitions: */
1072
d940ee9b
EH		 1073/* Return type name for a given CPU model name
1074 * Caller is responsible for freeing the returned string.
1075 */
1076static char *x86_cpu_type_name(const char *model_name)
1077{
1078 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1079}
1080
500050d1
AF		 1081static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1082{
d940ee9b 1083 ObjectClass *oc;
99193d8f 1084 char *typename = x86_cpu_type_name(cpu_model);
d940ee9b
EH		 1085 oc = object_class_by_name(typename);
1086 g_free(typename);
1087 return oc;
500050d1
AF		 1088}
1089
104494ea
IM		 1090static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1091{
1092 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1093 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1094 return g_strndup(class_name,
1095 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1096}
1097
d940ee9b 1098struct X86CPUDefinition {
c6dc6f63
AP		 1099 const char *name;
1100 uint32_t level;
90e4b0c3 1101 uint32_t xlevel;
99b88a17
IM		 1102 /* vendor is zero-terminated, 12 character ASCII string */
1103 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1104 int family;
1105 int model;
1106 int stepping;
0514ef2f 1107 FeatureWordArray features;
807e9869 1108 const char *model_id;
d940ee9b 1109};
c6dc6f63 1110
9576de75 1111static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1112 {
1113 .name = "qemu64",
3046bb5d 1114 .level = 0xd,
99b88a17 1115 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 1116 .family = 6,
f8e6a11a 1117 .model = 6,
c6dc6f63 1118 .stepping = 3,
0514ef2f 1119 .features[FEAT_1_EDX] =
27861ecc 1120 PPRO_FEATURES |
c6dc6f63 1121 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1122 CPUID_PSE36,
0514ef2f 1123 .features[FEAT_1_ECX] =
6aa91e4a 1124 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1125 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1126 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1127 .features[FEAT_8000_0001_ECX] =
71195672 1128 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1129 .xlevel = 0x8000000A,
9cf2cc3d 1130 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1131 },
1132 {
1133 .name = "phenom",
1134 .level = 5,
99b88a17 1135 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1136 .family = 16,
1137 .model = 2,
1138 .stepping = 3,
b9fc20bc 1139 /* Missing: CPUID_HT */
0514ef2f 1140 .features[FEAT_1_EDX] =
27861ecc 1141 PPRO_FEATURES |
c6dc6f63 1142 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1143 CPUID_PSE36 | CPUID_VME,
0514ef2f 1144 .features[FEAT_1_ECX] =
27861ecc 1145 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1146 CPUID_EXT_POPCNT,
0514ef2f 1147 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1148 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1149 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1150 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1151 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1152 CPUID_EXT3_CR8LEG,
1153 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1154 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1155 .features[FEAT_8000_0001_ECX] =
27861ecc 1156 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1157 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1158 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1159 .features[FEAT_SVM] =
b9fc20bc 1160 CPUID_SVM_NPT,
c6dc6f63
AP		 1161 .xlevel = 0x8000001A,
1162 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1163 },
1164 {
1165 .name = "core2duo",
1166 .level = 10,
99b88a17 1167 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1168 .family = 6,
1169 .model = 15,
1170 .stepping = 11,
b9fc20bc 1171 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1172 .features[FEAT_1_EDX] =
27861ecc 1173 PPRO_FEATURES |
c6dc6f63 1174 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1175 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1176 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1177 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1178 .features[FEAT_1_ECX] =
27861ecc 1179 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1180 CPUID_EXT_CX16,
0514ef2f 1181 .features[FEAT_8000_0001_EDX] =
27861ecc 1182 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1183 .features[FEAT_8000_0001_ECX] =
27861ecc 1184 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 1185 .xlevel = 0x80000008,
1186 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1187 },
1188 {
1189 .name = "kvm64",
3046bb5d 1190 .level = 0xd,
99b88a17 1191 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1192 .family = 15,
1193 .model = 6,
1194 .stepping = 1,
b3a4f0b1 1195 /* Missing: CPUID_HT */
0514ef2f 1196 .features[FEAT_1_EDX] =
b3a4f0b1 1197 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1198 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1199 CPUID_PSE36,
1200 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1201 .features[FEAT_1_ECX] =
27861ecc 1202 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1203 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1204 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1205 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1206 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1207 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1208 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1209 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1210 .features[FEAT_8000_0001_ECX] =
27861ecc 1211 0,
c6dc6f63
AP		 1212 .xlevel = 0x80000008,
1213 .model_id = "Common KVM processor"
1214 },
c6dc6f63
AP		 1215 {
1216 .name = "qemu32",
1217 .level = 4,
99b88a17 1218 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1219 .family = 6,
f8e6a11a 1220 .model = 6,
c6dc6f63 1221 .stepping = 3,
0514ef2f 1222 .features[FEAT_1_EDX] =
27861ecc 1223 PPRO_FEATURES,
0514ef2f 1224 .features[FEAT_1_ECX] =
6aa91e4a 1225 CPUID_EXT_SSE3,
58012d66 1226 .xlevel = 0x80000004,
9cf2cc3d 1227 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1228 },
eafaf1e5
AP		 1229 {
1230 .name = "kvm32",
1231 .level = 5,
99b88a17 1232 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1233 .family = 15,
1234 .model = 6,
1235 .stepping = 1,
0514ef2f 1236 .features[FEAT_1_EDX] =
b3a4f0b1 1237 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1238 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1239 .features[FEAT_1_ECX] =
27861ecc 1240 CPUID_EXT_SSE3,
0514ef2f 1241 .features[FEAT_8000_0001_ECX] =
27861ecc 1242 0,
eafaf1e5
AP		 1243 .xlevel = 0x80000008,
1244 .model_id = "Common 32-bit KVM processor"
1245 },
c6dc6f63
AP		 1246 {
1247 .name = "coreduo",
1248 .level = 10,
99b88a17 1249 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1250 .family = 6,
1251 .model = 14,
1252 .stepping = 8,
b9fc20bc 1253 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1254 .features[FEAT_1_EDX] =
27861ecc 1255 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1256 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1257 CPUID_SS,
1258 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1259 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1260 .features[FEAT_1_ECX] =
e93abc14 1261 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1262 .features[FEAT_8000_0001_EDX] =
27861ecc 1263 CPUID_EXT2_NX,
c6dc6f63
AP		 1264 .xlevel = 0x80000008,
1265 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1266 },
1267 {
1268 .name = "486",
58012d66 1269 .level = 1,
99b88a17 1270 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1271 .family = 4,
b2a856d9 1272 .model = 8,
c6dc6f63 1273 .stepping = 0,
0514ef2f 1274 .features[FEAT_1_EDX] =
27861ecc 1275 I486_FEATURES,
c6dc6f63 1276 .xlevel = 0,
807e9869 1277 .model_id = "",
c6dc6f63
AP		 1278 },
1279 {
1280 .name = "pentium",
1281 .level = 1,
99b88a17 1282 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1283 .family = 5,
1284 .model = 4,
1285 .stepping = 3,
0514ef2f 1286 .features[FEAT_1_EDX] =
27861ecc 1287 PENTIUM_FEATURES,
c6dc6f63 1288 .xlevel = 0,
807e9869 1289 .model_id = "",
c6dc6f63
AP		 1290 },
1291 {
1292 .name = "pentium2",
1293 .level = 2,
99b88a17 1294 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1295 .family = 6,
1296 .model = 5,
1297 .stepping = 2,
0514ef2f 1298 .features[FEAT_1_EDX] =
27861ecc 1299 PENTIUM2_FEATURES,
c6dc6f63 1300 .xlevel = 0,
807e9869 1301 .model_id = "",
c6dc6f63
AP		 1302 },
1303 {
1304 .name = "pentium3",
3046bb5d 1305 .level = 3,
99b88a17 1306 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1307 .family = 6,
1308 .model = 7,
1309 .stepping = 3,
0514ef2f 1310 .features[FEAT_1_EDX] =
27861ecc 1311 PENTIUM3_FEATURES,
c6dc6f63 1312 .xlevel = 0,
807e9869 1313 .model_id = "",
c6dc6f63
AP		 1314 },
1315 {
1316 .name = "athlon",
1317 .level = 2,
99b88a17 1318 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1319 .family = 6,
1320 .model = 2,
1321 .stepping = 3,
0514ef2f 1322 .features[FEAT_1_EDX] =
27861ecc 1323 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 1324 CPUID_MCA,
0514ef2f 1325 .features[FEAT_8000_0001_EDX] =
60032ac0 1326 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 1327 .xlevel = 0x80000008,
9cf2cc3d 1328 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1329 },
1330 {
1331 .name = "n270",
3046bb5d 1332 .level = 10,
99b88a17 1333 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1334 .family = 6,
1335 .model = 28,
1336 .stepping = 2,
b9fc20bc 1337 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1338 .features[FEAT_1_EDX] =
27861ecc 1339 PPRO_FEATURES |
b9fc20bc
EH		 1340 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1341 CPUID_ACPI | CPUID_SS,
c6dc6f63 1342 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1343 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1344 * CPUID_EXT_XTPR */
0514ef2f 1345 .features[FEAT_1_ECX] =
27861ecc 1346 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1347 CPUID_EXT_MOVBE,
0514ef2f 1348 .features[FEAT_8000_0001_EDX] =
60032ac0 1349 CPUID_EXT2_NX,
0514ef2f 1350 .features[FEAT_8000_0001_ECX] =
27861ecc 1351 CPUID_EXT3_LAHF_LM,
3046bb5d 1352 .xlevel = 0x80000008,
c6dc6f63
AP		 1353 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1354 },
3eca4642
EH		 1355 {
1356 .name = "Conroe",
3046bb5d 1357 .level = 10,
99b88a17 1358 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1359 .family = 6,
ffce9ebb 1360 .model = 15,
3eca4642 1361 .stepping = 3,
0514ef2f 1362 .features[FEAT_1_EDX] =
b3a4f0b1 1363 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1364 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1365 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1366 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1367 CPUID_DE | CPUID_FP87,
0514ef2f 1368 .features[FEAT_1_ECX] =
27861ecc 1369 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1370 .features[FEAT_8000_0001_EDX] =
27861ecc 1371 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1372 .features[FEAT_8000_0001_ECX] =
27861ecc 1373 CPUID_EXT3_LAHF_LM,
3046bb5d 1374 .xlevel = 0x80000008,
3eca4642
EH		 1375 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1376 },
1377 {
1378 .name = "Penryn",
3046bb5d 1379 .level = 10,
99b88a17 1380 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1381 .family = 6,
ffce9ebb 1382 .model = 23,
3eca4642 1383 .stepping = 3,
0514ef2f 1384 .features[FEAT_1_EDX] =
b3a4f0b1 1385 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1386 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1387 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1388 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1389 CPUID_DE | CPUID_FP87,
0514ef2f 1390 .features[FEAT_1_ECX] =
27861ecc 1391 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1392 CPUID_EXT_SSE3,
0514ef2f 1393 .features[FEAT_8000_0001_EDX] =
27861ecc 1394 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1395 .features[FEAT_8000_0001_ECX] =
27861ecc 1396 CPUID_EXT3_LAHF_LM,
3046bb5d 1397 .xlevel = 0x80000008,
3eca4642
EH		 1398 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1399 },
1400 {
1401 .name = "Nehalem",
3046bb5d 1402 .level = 11,
99b88a17 1403 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1404 .family = 6,
ffce9ebb 1405 .model = 26,
3eca4642 1406 .stepping = 3,
0514ef2f 1407 .features[FEAT_1_EDX] =
b3a4f0b1 1408 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1409 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1410 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1411 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1412 CPUID_DE | CPUID_FP87,
0514ef2f 1413 .features[FEAT_1_ECX] =
27861ecc 1414 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1415 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1416 .features[FEAT_8000_0001_EDX] =
27861ecc 1417 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1418 .features[FEAT_8000_0001_ECX] =
27861ecc 1419 CPUID_EXT3_LAHF_LM,
3046bb5d 1420 .xlevel = 0x80000008,
3eca4642
EH		 1421 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1422 },
ac96c413
EH		 1423 {
1424 .name = "Nehalem-IBRS",
1425 .level = 11,
1426 .vendor = CPUID_VENDOR_INTEL,
1427 .family = 6,
1428 .model = 26,
1429 .stepping = 3,
1430 .features[FEAT_1_EDX] =
1431 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1432 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1433 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1434 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1435 CPUID_DE | CPUID_FP87,
1436 .features[FEAT_1_ECX] =
1437 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1438 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1439 .features[FEAT_7_0_EDX] =
1440 CPUID_7_0_EDX_SPEC_CTRL,
1441 .features[FEAT_8000_0001_EDX] =
1442 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1443 .features[FEAT_8000_0001_ECX] =
1444 CPUID_EXT3_LAHF_LM,
1445 .xlevel = 0x80000008,
1446 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1447 },
3eca4642
EH		 1448 {
1449 .name = "Westmere",
1450 .level = 11,
99b88a17 1451 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1452 .family = 6,
1453 .model = 44,
1454 .stepping = 1,
0514ef2f 1455 .features[FEAT_1_EDX] =
b3a4f0b1 1456 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1457 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1458 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1459 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1460 CPUID_DE | CPUID_FP87,
0514ef2f 1461 .features[FEAT_1_ECX] =
27861ecc 1462 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1463 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1464 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1465 .features[FEAT_8000_0001_EDX] =
27861ecc 1466 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1467 .features[FEAT_8000_0001_ECX] =
27861ecc 1468 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1469 .features[FEAT_6_EAX] =
1470 CPUID_6_EAX_ARAT,
3046bb5d 1471 .xlevel = 0x80000008,
3eca4642
EH		 1472 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1473 },
ac96c413
EH		 1474 {
1475 .name = "Westmere-IBRS",
1476 .level = 11,
1477 .vendor = CPUID_VENDOR_INTEL,
1478 .family = 6,
1479 .model = 44,
1480 .stepping = 1,
1481 .features[FEAT_1_EDX] =
1482 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1483 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1484 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1485 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1486 CPUID_DE | CPUID_FP87,
1487 .features[FEAT_1_ECX] =
1488 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1489 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1490 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1491 .features[FEAT_8000_0001_EDX] =
1492 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1493 .features[FEAT_8000_0001_ECX] =
1494 CPUID_EXT3_LAHF_LM,
1495 .features[FEAT_7_0_EDX] =
1496 CPUID_7_0_EDX_SPEC_CTRL,
1497 .features[FEAT_6_EAX] =
1498 CPUID_6_EAX_ARAT,
1499 .xlevel = 0x80000008,
1500 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1501 },
3eca4642
EH		 1502 {
1503 .name = "SandyBridge",
1504 .level = 0xd,
99b88a17 1505 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1506 .family = 6,
1507 .model = 42,
1508 .stepping = 1,
0514ef2f 1509 .features[FEAT_1_EDX] =
b3a4f0b1 1510 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1511 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1512 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1513 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1514 CPUID_DE | CPUID_FP87,
0514ef2f 1515 .features[FEAT_1_ECX] =
27861ecc 1516 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1517 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1518 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1519 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1520 CPUID_EXT_SSE3,
0514ef2f 1521 .features[FEAT_8000_0001_EDX] =
27861ecc 1522 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1523 CPUID_EXT2_SYSCALL,
0514ef2f 1524 .features[FEAT_8000_0001_ECX] =
27861ecc 1525 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1526 .features[FEAT_XSAVE] =
1527 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1528 .features[FEAT_6_EAX] =
1529 CPUID_6_EAX_ARAT,
3046bb5d 1530 .xlevel = 0x80000008,
3eca4642
EH		 1531 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1532 },
ac96c413
EH		 1533 {
1534 .name = "SandyBridge-IBRS",
1535 .level = 0xd,
1536 .vendor = CPUID_VENDOR_INTEL,
1537 .family = 6,
1538 .model = 42,
1539 .stepping = 1,
1540 .features[FEAT_1_EDX] =
1541 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1542 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1543 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1544 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1545 CPUID_DE | CPUID_FP87,
1546 .features[FEAT_1_ECX] =
1547 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1548 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1549 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1550 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1551 CPUID_EXT_SSE3,
1552 .features[FEAT_8000_0001_EDX] =
1553 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1554 CPUID_EXT2_SYSCALL,
1555 .features[FEAT_8000_0001_ECX] =
1556 CPUID_EXT3_LAHF_LM,
1557 .features[FEAT_7_0_EDX] =
1558 CPUID_7_0_EDX_SPEC_CTRL,
1559 .features[FEAT_XSAVE] =
1560 CPUID_XSAVE_XSAVEOPT,
1561 .features[FEAT_6_EAX] =
1562 CPUID_6_EAX_ARAT,
1563 .xlevel = 0x80000008,
1564 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1565 },
2f9ac42a
PB		 1566 {
1567 .name = "IvyBridge",
1568 .level = 0xd,
1569 .vendor = CPUID_VENDOR_INTEL,
1570 .family = 6,
1571 .model = 58,
1572 .stepping = 9,
1573 .features[FEAT_1_EDX] =
1574 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1575 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1576 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1577 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1578 CPUID_DE | CPUID_FP87,
1579 .features[FEAT_1_ECX] =
1580 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1581 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1582 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1583 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1584 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1585 .features[FEAT_7_0_EBX] =
1586 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1587 CPUID_7_0_EBX_ERMS,
1588 .features[FEAT_8000_0001_EDX] =
1589 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1590 CPUID_EXT2_SYSCALL,
1591 .features[FEAT_8000_0001_ECX] =
1592 CPUID_EXT3_LAHF_LM,
1593 .features[FEAT_XSAVE] =
1594 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1595 .features[FEAT_6_EAX] =
1596 CPUID_6_EAX_ARAT,
3046bb5d 1597 .xlevel = 0x80000008,
2f9ac42a
PB		 1598 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1599 },
ac96c413
EH		 1600 {
1601 .name = "IvyBridge-IBRS",
1602 .level = 0xd,
1603 .vendor = CPUID_VENDOR_INTEL,
1604 .family = 6,
1605 .model = 58,
1606 .stepping = 9,
1607 .features[FEAT_1_EDX] =
1608 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1609 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1610 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1611 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1612 CPUID_DE | CPUID_FP87,
1613 .features[FEAT_1_ECX] =
1614 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1615 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1616 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1617 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1618 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1619 .features[FEAT_7_0_EBX] =
1620 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1621 CPUID_7_0_EBX_ERMS,
1622 .features[FEAT_8000_0001_EDX] =
1623 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1624 CPUID_EXT2_SYSCALL,
1625 .features[FEAT_8000_0001_ECX] =
1626 CPUID_EXT3_LAHF_LM,
1627 .features[FEAT_7_0_EDX] =
1628 CPUID_7_0_EDX_SPEC_CTRL,
1629 .features[FEAT_XSAVE] =
1630 CPUID_XSAVE_XSAVEOPT,
1631 .features[FEAT_6_EAX] =
1632 CPUID_6_EAX_ARAT,
1633 .xlevel = 0x80000008,
1634 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
1635 },
37507094 1636 {
a356850b
EH		 1637 .name = "Haswell-noTSX",
1638 .level = 0xd,
1639 .vendor = CPUID_VENDOR_INTEL,
1640 .family = 6,
1641 .model = 60,
1642 .stepping = 1,
1643 .features[FEAT_1_EDX] =
1644 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1645 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1646 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1647 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1648 CPUID_DE | CPUID_FP87,
1649 .features[FEAT_1_ECX] =
1650 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1651 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1652 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1653 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1654 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1655 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1656 .features[FEAT_8000_0001_EDX] =
1657 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1658 CPUID_EXT2_SYSCALL,
1659 .features[FEAT_8000_0001_ECX] =
becb6667 1660 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1661 .features[FEAT_7_0_EBX] =
1662 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1663 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1664 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1665 .features[FEAT_XSAVE] =
1666 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1667 .features[FEAT_6_EAX] =
1668 CPUID_6_EAX_ARAT,
3046bb5d 1669 .xlevel = 0x80000008,
a356850b 1670 .model_id = "Intel Core Processor (Haswell, no TSX)",
ac96c413
EH		 1671 },
1672 {
1673 .name = "Haswell-noTSX-IBRS",
1674 .level = 0xd,
1675 .vendor = CPUID_VENDOR_INTEL,
1676 .family = 6,
1677 .model = 60,
1678 .stepping = 1,
1679 .features[FEAT_1_EDX] =
1680 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1681 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1682 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1683 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1684 CPUID_DE | CPUID_FP87,
1685 .features[FEAT_1_ECX] =
1686 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1687 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1688 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1689 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1690 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1691 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1692 .features[FEAT_8000_0001_EDX] =
1693 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1694 CPUID_EXT2_SYSCALL,
1695 .features[FEAT_8000_0001_ECX] =
1696 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1697 .features[FEAT_7_0_EDX] =
1698 CPUID_7_0_EDX_SPEC_CTRL,
1699 .features[FEAT_7_0_EBX] =
1700 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1701 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1702 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1703 .features[FEAT_XSAVE] =
1704 CPUID_XSAVE_XSAVEOPT,
1705 .features[FEAT_6_EAX] =
1706 CPUID_6_EAX_ARAT,
1707 .xlevel = 0x80000008,
1708 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
1709 },
1710 {
37507094
EH		 1711 .name = "Haswell",
1712 .level = 0xd,
99b88a17 1713 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1714 .family = 6,
1715 .model = 60,
ec56a4a7 1716 .stepping = 4,
0514ef2f 1717 .features[FEAT_1_EDX] =
b3a4f0b1 1718 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1719 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1720 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1721 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1722 CPUID_DE | CPUID_FP87,
0514ef2f 1723 .features[FEAT_1_ECX] =
27861ecc 1724 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1725 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1726 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1727 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1728 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1729 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1730 .features[FEAT_8000_0001_EDX] =
27861ecc 1731 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1732 CPUID_EXT2_SYSCALL,
0514ef2f 1733 .features[FEAT_8000_0001_ECX] =
becb6667 1734 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1735 .features[FEAT_7_0_EBX] =
27861ecc 1736 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1737 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1738 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1739 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1740 .features[FEAT_XSAVE] =
1741 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1742 .features[FEAT_6_EAX] =
1743 CPUID_6_EAX_ARAT,
3046bb5d 1744 .xlevel = 0x80000008,
37507094
EH		 1745 .model_id = "Intel Core Processor (Haswell)",
1746 },
ac96c413
EH		 1747 {
1748 .name = "Haswell-IBRS",
1749 .level = 0xd,
1750 .vendor = CPUID_VENDOR_INTEL,
1751 .family = 6,
1752 .model = 60,
1753 .stepping = 4,
1754 .features[FEAT_1_EDX] =
1755 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1756 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1757 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1758 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1759 CPUID_DE | CPUID_FP87,
1760 .features[FEAT_1_ECX] =
1761 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1762 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1763 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1764 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1765 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1766 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1767 .features[FEAT_8000_0001_EDX] =
1768 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1769 CPUID_EXT2_SYSCALL,
1770 .features[FEAT_8000_0001_ECX] =
1771 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1772 .features[FEAT_7_0_EDX] =
1773 CPUID_7_0_EDX_SPEC_CTRL,
1774 .features[FEAT_7_0_EBX] =
1775 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1776 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1777 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1778 CPUID_7_0_EBX_RTM,
1779 .features[FEAT_XSAVE] =
1780 CPUID_XSAVE_XSAVEOPT,
1781 .features[FEAT_6_EAX] =
1782 CPUID_6_EAX_ARAT,
1783 .xlevel = 0x80000008,
1784 .model_id = "Intel Core Processor (Haswell, IBRS)",
1785 },
a356850b
EH		 1786 {
1787 .name = "Broadwell-noTSX",
1788 .level = 0xd,
1789 .vendor = CPUID_VENDOR_INTEL,
1790 .family = 6,
1791 .model = 61,
1792 .stepping = 2,
1793 .features[FEAT_1_EDX] =
1794 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1795 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1796 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1797 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1798 CPUID_DE | CPUID_FP87,
1799 .features[FEAT_1_ECX] =
1800 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1801 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1802 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1803 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1804 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1805 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1806 .features[FEAT_8000_0001_EDX] =
1807 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1808 CPUID_EXT2_SYSCALL,
1809 .features[FEAT_8000_0001_ECX] =
becb6667 1810 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1811 .features[FEAT_7_0_EBX] =
1812 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1813 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1814 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1815 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1816 CPUID_7_0_EBX_SMAP,
1817 .features[FEAT_XSAVE] =
1818 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1819 .features[FEAT_6_EAX] =
1820 CPUID_6_EAX_ARAT,
3046bb5d 1821 .xlevel = 0x80000008,
a356850b
EH		 1822 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1823 },
ac96c413
EH		 1824 {
1825 .name = "Broadwell-noTSX-IBRS",
1826 .level = 0xd,
1827 .vendor = CPUID_VENDOR_INTEL,
1828 .family = 6,
1829 .model = 61,
1830 .stepping = 2,
1831 .features[FEAT_1_EDX] =
1832 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1833 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1834 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1835 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1836 CPUID_DE | CPUID_FP87,
1837 .features[FEAT_1_ECX] =
1838 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1839 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1840 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1841 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1842 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1843 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1844 .features[FEAT_8000_0001_EDX] =
1845 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1846 CPUID_EXT2_SYSCALL,
1847 .features[FEAT_8000_0001_ECX] =
1848 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1849 .features[FEAT_7_0_EDX] =
1850 CPUID_7_0_EDX_SPEC_CTRL,
1851 .features[FEAT_7_0_EBX] =
1852 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1853 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1854 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1855 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1856 CPUID_7_0_EBX_SMAP,
1857 .features[FEAT_XSAVE] =
1858 CPUID_XSAVE_XSAVEOPT,
1859 .features[FEAT_6_EAX] =
1860 CPUID_6_EAX_ARAT,
1861 .xlevel = 0x80000008,
1862 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
1863 },
ece01354
EH		 1864 {
1865 .name = "Broadwell",
1866 .level = 0xd,
1867 .vendor = CPUID_VENDOR_INTEL,
1868 .family = 6,
1869 .model = 61,
1870 .stepping = 2,
1871 .features[FEAT_1_EDX] =
b3a4f0b1 1872 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1873 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1874 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1875 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1876 CPUID_DE | CPUID_FP87,
1877 .features[FEAT_1_ECX] =
1878 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1879 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1880 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1881 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1882 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1883 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1884 .features[FEAT_8000_0001_EDX] =
1885 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1886 CPUID_EXT2_SYSCALL,
1887 .features[FEAT_8000_0001_ECX] =
becb6667 1888 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1889 .features[FEAT_7_0_EBX] =
1890 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1891 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1892 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1893 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1894 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1895 .features[FEAT_XSAVE] =
1896 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1897 .features[FEAT_6_EAX] =
1898 CPUID_6_EAX_ARAT,
3046bb5d 1899 .xlevel = 0x80000008,
ece01354
EH		 1900 .model_id = "Intel Core Processor (Broadwell)",
1901 },
ac96c413
EH		 1902 {
1903 .name = "Broadwell-IBRS",
1904 .level = 0xd,
1905 .vendor = CPUID_VENDOR_INTEL,
1906 .family = 6,
1907 .model = 61,
1908 .stepping = 2,
1909 .features[FEAT_1_EDX] =
1910 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1911 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1912 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1913 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1914 CPUID_DE | CPUID_FP87,
1915 .features[FEAT_1_ECX] =
1916 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1917 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1918 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1919 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1920 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1921 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1922 .features[FEAT_8000_0001_EDX] =
1923 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1924 CPUID_EXT2_SYSCALL,
1925 .features[FEAT_8000_0001_ECX] =
1926 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1927 .features[FEAT_7_0_EDX] =
1928 CPUID_7_0_EDX_SPEC_CTRL,
1929 .features[FEAT_7_0_EBX] =
1930 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1931 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1932 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1933 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1934 CPUID_7_0_EBX_SMAP,
1935 .features[FEAT_XSAVE] =
1936 CPUID_XSAVE_XSAVEOPT,
1937 .features[FEAT_6_EAX] =
1938 CPUID_6_EAX_ARAT,
1939 .xlevel = 0x80000008,
1940 .model_id = "Intel Core Processor (Broadwell, IBRS)",
1941 },
f6f949e9
EH		 1942 {
1943 .name = "Skylake-Client",
1944 .level = 0xd,
1945 .vendor = CPUID_VENDOR_INTEL,
1946 .family = 6,
1947 .model = 94,
1948 .stepping = 3,
1949 .features[FEAT_1_EDX] =
1950 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1951 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1952 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1953 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1954 CPUID_DE | CPUID_FP87,
1955 .features[FEAT_1_ECX] =
1956 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1957 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1958 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1959 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1960 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1961 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1962 .features[FEAT_8000_0001_EDX] =
1963 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1964 CPUID_EXT2_SYSCALL,
1965 .features[FEAT_8000_0001_ECX] =
1966 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1967 .features[FEAT_7_0_EBX] =
1968 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1969 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1970 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1971 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1972 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1973 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 1974 * including v4.1 to v4.12).
f6f949e9
EH		 1975 * KVM doesn't yet expose any XSAVES state save component,
1976 * and the only one defined in Skylake (processor tracing)
1977 * probably will block migration anyway.
1978 */
1979 .features[FEAT_XSAVE] =
1980 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1981 CPUID_XSAVE_XGETBV1,
1982 .features[FEAT_6_EAX] =
1983 CPUID_6_EAX_ARAT,
1984 .xlevel = 0x80000008,
1985 .model_id = "Intel Core Processor (Skylake)",
1986 },
ac96c413
EH		 1987 {
1988 .name = "Skylake-Client-IBRS",
1989 .level = 0xd,
1990 .vendor = CPUID_VENDOR_INTEL,
1991 .family = 6,
1992 .model = 94,
1993 .stepping = 3,
1994 .features[FEAT_1_EDX] =
1995 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1996 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1997 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1998 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1999 CPUID_DE | CPUID_FP87,
2000 .features[FEAT_1_ECX] =
2001 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2002 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2003 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2004 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2005 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2006 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2007 .features[FEAT_8000_0001_EDX] =
2008 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2009 CPUID_EXT2_SYSCALL,
2010 .features[FEAT_8000_0001_ECX] =
2011 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2012 .features[FEAT_7_0_EDX] =
2013 CPUID_7_0_EDX_SPEC_CTRL,
2014 .features[FEAT_7_0_EBX] =
2015 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2016 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2017 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2018 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2019 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
2020 /* Missing: XSAVES (not supported by some Linux versions,
2021 * including v4.1 to v4.12).
2022 * KVM doesn't yet expose any XSAVES state save component,
2023 * and the only one defined in Skylake (processor tracing)
2024 * probably will block migration anyway.
2025 */
2026 .features[FEAT_XSAVE] =
2027 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2028 CPUID_XSAVE_XGETBV1,
2029 .features[FEAT_6_EAX] =
2030 CPUID_6_EAX_ARAT,
2031 .xlevel = 0x80000008,
2032 .model_id = "Intel Core Processor (Skylake, IBRS)",
2033 },
53f9a6f4
BF		 2034 {
2035 .name = "Skylake-Server",
2036 .level = 0xd,
2037 .vendor = CPUID_VENDOR_INTEL,
2038 .family = 6,
2039 .model = 85,
2040 .stepping = 4,
2041 .features[FEAT_1_EDX] =
2042 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2043 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2044 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2045 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2046 CPUID_DE | CPUID_FP87,
2047 .features[FEAT_1_ECX] =
2048 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2049 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2050 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2051 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2052 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2053 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2054 .features[FEAT_8000_0001_EDX] =
2055 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2056 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2057 .features[FEAT_8000_0001_ECX] =
2058 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2059 .features[FEAT_7_0_EBX] =
2060 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2061 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2062 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2063 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2064 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2065 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2066 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2067 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
53f9a6f4
BF		 2068 /* Missing: XSAVES (not supported by some Linux versions,
2069 * including v4.1 to v4.12).
2070 * KVM doesn't yet expose any XSAVES state save component,
2071 * and the only one defined in Skylake (processor tracing)
2072 * probably will block migration anyway.
2073 */
2074 .features[FEAT_XSAVE] =
2075 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2076 CPUID_XSAVE_XGETBV1,
2077 .features[FEAT_6_EAX] =
2078 CPUID_6_EAX_ARAT,
2079 .xlevel = 0x80000008,
2080 .model_id = "Intel Xeon Processor (Skylake)",
2081 },
ac96c413
EH		 2082 {
2083 .name = "Skylake-Server-IBRS",
2084 .level = 0xd,
2085 .vendor = CPUID_VENDOR_INTEL,
2086 .family = 6,
2087 .model = 85,
2088 .stepping = 4,
2089 .features[FEAT_1_EDX] =
2090 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2091 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2092 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2093 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2094 CPUID_DE | CPUID_FP87,
2095 .features[FEAT_1_ECX] =
2096 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2097 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2098 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2099 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2100 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2101 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2102 .features[FEAT_8000_0001_EDX] =
2103 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2104 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2105 .features[FEAT_8000_0001_ECX] =
2106 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2107 .features[FEAT_7_0_EDX] =
2108 CPUID_7_0_EDX_SPEC_CTRL,
2109 .features[FEAT_7_0_EBX] =
2110 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2111 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2112 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2113 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2114 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2115 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2116 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2117 CPUID_7_0_EBX_AVX512VL,
2118 /* Missing: XSAVES (not supported by some Linux versions,
2119 * including v4.1 to v4.12).
2120 * KVM doesn't yet expose any XSAVES state save component,
2121 * and the only one defined in Skylake (processor tracing)
2122 * probably will block migration anyway.
2123 */
2124 .features[FEAT_XSAVE] =
2125 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2126 CPUID_XSAVE_XGETBV1,
2127 .features[FEAT_6_EAX] =
2128 CPUID_6_EAX_ARAT,
2129 .xlevel = 0x80000008,
2130 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2131 },
a1849515
BF		 2132 {
2133 .name = "KnightsMill",
2134 .level = 0xd,
2135 .vendor = CPUID_VENDOR_INTEL,
2136 .family = 6,
2137 .model = 133,
2138 .stepping = 0,
2139 .features[FEAT_1_EDX] =
2140 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2141 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2142 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2143 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2144 CPUID_PSE | CPUID_DE | CPUID_FP87,
2145 .features[FEAT_1_ECX] =
2146 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2147 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2148 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2149 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2150 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2151 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2152 .features[FEAT_8000_0001_EDX] =
2153 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2154 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2155 .features[FEAT_8000_0001_ECX] =
2156 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2157 .features[FEAT_7_0_EBX] =
2158 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2159 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2160 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2161 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2162 CPUID_7_0_EBX_AVX512ER,
2163 .features[FEAT_7_0_ECX] =
2164 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2165 .features[FEAT_7_0_EDX] =
2166 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2167 .features[FEAT_XSAVE] =
2168 CPUID_XSAVE_XSAVEOPT,
2169 .features[FEAT_6_EAX] =
2170 CPUID_6_EAX_ARAT,
2171 .xlevel = 0x80000008,
2172 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2173 },
3eca4642
EH		 2174 {
2175 .name = "Opteron_G1",
2176 .level = 5,
99b88a17 2177 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2178 .family = 15,
2179 .model = 6,
2180 .stepping = 1,
0514ef2f 2181 .features[FEAT_1_EDX] =
b3a4f0b1 2182 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2183 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2184 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2185 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2186 CPUID_DE | CPUID_FP87,
0514ef2f 2187 .features[FEAT_1_ECX] =
27861ecc 2188 CPUID_EXT_SSE3,
0514ef2f 2189 .features[FEAT_8000_0001_EDX] =
2a923a29 2190 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 2191 .xlevel = 0x80000008,
2192 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2193 },
2194 {
2195 .name = "Opteron_G2",
2196 .level = 5,
99b88a17 2197 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2198 .family = 15,
2199 .model = 6,
2200 .stepping = 1,
0514ef2f 2201 .features[FEAT_1_EDX] =
b3a4f0b1 2202 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2203 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2204 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2205 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2206 CPUID_DE | CPUID_FP87,
0514ef2f 2207 .features[FEAT_1_ECX] =
27861ecc 2208 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 2209 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2210 .features[FEAT_8000_0001_EDX] =
2a923a29 2211 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2212 .features[FEAT_8000_0001_ECX] =
27861ecc 2213 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2214 .xlevel = 0x80000008,
2215 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2216 },
2217 {
2218 .name = "Opteron_G3",
2219 .level = 5,
99b88a17 2220 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 2221 .family = 16,
2222 .model = 2,
2223 .stepping = 3,
0514ef2f 2224 .features[FEAT_1_EDX] =
b3a4f0b1 2225 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2226 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2227 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2228 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2229 CPUID_DE | CPUID_FP87,
0514ef2f 2230 .features[FEAT_1_ECX] =
27861ecc 2231 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 2232 CPUID_EXT_SSE3,
33b5e8c0 2233 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2234 .features[FEAT_8000_0001_EDX] =
2a923a29 2235 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2236 .features[FEAT_8000_0001_ECX] =
27861ecc 2237 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 2238 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2239 .xlevel = 0x80000008,
2240 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2241 },
2242 {
2243 .name = "Opteron_G4",
2244 .level = 0xd,
99b88a17 2245 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2246 .family = 21,
2247 .model = 1,
2248 .stepping = 2,
0514ef2f 2249 .features[FEAT_1_EDX] =
b3a4f0b1 2250 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2251 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2252 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2253 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2254 CPUID_DE | CPUID_FP87,
0514ef2f 2255 .features[FEAT_1_ECX] =
27861ecc 2256 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2257 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2258 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2259 CPUID_EXT_SSE3,
33b5e8c0 2260 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2261 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 2262 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2263 CPUID_EXT2_SYSCALL,
0514ef2f 2264 .features[FEAT_8000_0001_ECX] =
27861ecc 2265 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2266 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2267 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2268 CPUID_EXT3_LAHF_LM,
0bb0b2d2 2269 /* no xsaveopt! */
3eca4642
EH		 2270 .xlevel = 0x8000001A,
2271 .model_id = "AMD Opteron 62xx class CPU",
2272 },
021941b9
AP		 2273 {
2274 .name = "Opteron_G5",
2275 .level = 0xd,
99b88a17 2276 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 2277 .family = 21,
2278 .model = 2,
2279 .stepping = 0,
0514ef2f 2280 .features[FEAT_1_EDX] =
b3a4f0b1 2281 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2282 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2283 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2284 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2285 CPUID_DE | CPUID_FP87,
0514ef2f 2286 .features[FEAT_1_ECX] =
27861ecc 2287 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 2288 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2289 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2290 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 2291 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2292 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 2293 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2294 CPUID_EXT2_SYSCALL,
0514ef2f 2295 .features[FEAT_8000_0001_ECX] =
27861ecc 2296 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2297 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2298 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2299 CPUID_EXT3_LAHF_LM,
0bb0b2d2 2300 /* no xsaveopt! */
021941b9
AP		 2301 .xlevel = 0x8000001A,
2302 .model_id = "AMD Opteron 63xx class CPU",
2303 },
2e2efc7d
BS		 2304 {
2305 .name = "EPYC",
2306 .level = 0xd,
2307 .vendor = CPUID_VENDOR_AMD,
2308 .family = 23,
2309 .model = 1,
2310 .stepping = 2,
2311 .features[FEAT_1_EDX] =
2312 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2313 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2314 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2315 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2316 CPUID_VME | CPUID_FP87,
2317 .features[FEAT_1_ECX] =
2318 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2319 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2320 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2321 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2322 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2323 .features[FEAT_8000_0001_EDX] =
2324 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2325 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2326 CPUID_EXT2_SYSCALL,
2327 .features[FEAT_8000_0001_ECX] =
2328 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2329 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2330 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2331 .features[FEAT_7_0_EBX] =
2332 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2333 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2334 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2335 CPUID_7_0_EBX_SHA_NI,
2336 /* Missing: XSAVES (not supported by some Linux versions,
2337 * including v4.1 to v4.12).
2338 * KVM doesn't yet expose any XSAVES state save component.
2339 */
2340 .features[FEAT_XSAVE] =
2341 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2342 CPUID_XSAVE_XGETBV1,
2343 .features[FEAT_6_EAX] =
2344 CPUID_6_EAX_ARAT,
2345 .xlevel = 0x8000000A,
2346 .model_id = "AMD EPYC Processor",
2347 },
6cfbc54e
EH		 2348 {
2349 .name = "EPYC-IBPB",
2350 .level = 0xd,
2351 .vendor = CPUID_VENDOR_AMD,
2352 .family = 23,
2353 .model = 1,
2354 .stepping = 2,
2355 .features[FEAT_1_EDX] =
2356 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2357 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2358 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2359 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2360 CPUID_VME | CPUID_FP87,
2361 .features[FEAT_1_ECX] =
2362 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2363 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2364 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2365 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2366 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2367 .features[FEAT_8000_0001_EDX] =
2368 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2369 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2370 CPUID_EXT2_SYSCALL,
2371 .features[FEAT_8000_0001_ECX] =
2372 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2373 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2374 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2375 .features[FEAT_8000_0008_EBX] =
2376 CPUID_8000_0008_EBX_IBPB,
2377 .features[FEAT_7_0_EBX] =
2378 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2379 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2380 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2381 CPUID_7_0_EBX_SHA_NI,
2382 /* Missing: XSAVES (not supported by some Linux versions,
2383 * including v4.1 to v4.12).
2384 * KVM doesn't yet expose any XSAVES state save component.
2385 */
2386 .features[FEAT_XSAVE] =
2387 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2388 CPUID_XSAVE_XGETBV1,
2389 .features[FEAT_6_EAX] =
2390 CPUID_6_EAX_ARAT,
2391 .xlevel = 0x8000000A,
2392 .model_id = "AMD EPYC Processor (with IBPB)",
2393 },
c6dc6f63
AP		 2394};
2395
5114e842
EH		 2396typedef struct PropValue {
2397 const char *prop, *value;
2398} PropValue;
2399
2400/* KVM-specific features that are automatically added/removed
2401 * from all CPU models when KVM is enabled.
2402 */
2403static PropValue kvm_default_props[] = {
2404 { "kvmclock", "on" },
2405 { "kvm-nopiodelay", "on" },
2406 { "kvm-asyncpf", "on" },
2407 { "kvm-steal-time", "on" },
2408 { "kvm-pv-eoi", "on" },
2409 { "kvmclock-stable-bit", "on" },
2410 { "x2apic", "on" },
2411 { "acpi", "off" },
2412 { "monitor", "off" },
2413 { "svm", "off" },
2414 { NULL, NULL },
2415};
2416
04d99c3c
EH		 2417/* TCG-specific defaults that override all CPU models when using TCG
2418 */
2419static PropValue tcg_default_props[] = {
2420 { "vme", "off" },
2421 { NULL, NULL },
2422};
2423
2424
5114e842
EH		 2425void x86_cpu_change_kvm_default(const char *prop, const char *value)
2426{
2427 PropValue *pv;
2428 for (pv = kvm_default_props; pv->prop; pv++) {
2429 if (!strcmp(pv->prop, prop)) {
2430 pv->value = value;
2431 break;
2432 }
2433 }
2434
2435 /* It is valid to call this function only for properties that
2436 * are already present in the kvm_default_props table.
2437 */
2438 assert(pv->prop);
2439}
2440
4d1b279b
EH		 2441static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2442 bool migratable_only);
2443
40bfe48f
HZ		 2444static bool lmce_supported(void)
2445{
c62f2630 2446 uint64_t mce_cap = 0;
40bfe48f 2447
c62f2630 2448#ifdef CONFIG_KVM
40bfe48f
HZ		 2449 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
2450 return false;
2451 }
c62f2630 2452#endif
40bfe48f
HZ		 2453
2454 return !!(mce_cap & MCG_LMCE_P);
2455}
2456
7d8050b5
EH		 2457#define CPUID_MODEL_ID_SZ 48
2458
2459/**
2460 * cpu_x86_fill_model_id:
2461 * Get CPUID model ID string from host CPU.
2462 *
2463 * @str should have at least CPUID_MODEL_ID_SZ bytes
2464 *
2465 * The function does NOT add a null terminator to the string
2466 * automatically.
2467 */
c6dc6f63
AP		 2468static int cpu_x86_fill_model_id(char *str)
2469{
2470 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2471 int i;
2472
2473 for (i = 0; i < 3; i++) {
2474 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
2475 memcpy(str + i * 16 + 0, &eax, 4);
2476 memcpy(str + i * 16 + 4, &ebx, 4);
2477 memcpy(str + i * 16 + 8, &ecx, 4);
2478 memcpy(str + i * 16 + 12, &edx, 4);
2479 }
2480 return 0;
2481}
2482
c62f2630 2483static Property max_x86_cpu_properties[] = {
120eee7d 2484 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 2485 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 2486 DEFINE_PROP_END_OF_LIST()
2487};
2488
c62f2630 2489static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 2490{
84f1b92f 2491 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 2492 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 2493
f48c8837 2494 xcc->ordering = 9;
6e746f30 2495
ee465a3e 2496 xcc->model_description =
c62f2630 2497 "Enables all features supported by the accelerator in the current host";
d940ee9b 2498
c62f2630 2499 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 2500}
2501
0bacd8b3
EH		 2502static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
2503
c62f2630 2504static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 2505{
2506 X86CPU *cpu = X86_CPU(obj);
2507 CPUX86State *env = &cpu->env;
2508 KVMState *s = kvm_state;
d940ee9b 2509
4d1b279b
EH		 2510 /* We can't fill the features array here because we don't know yet if
2511 * "migratable" is true or false.
2512 */
44bd8e53 2513 cpu->max_features = true;
4d1b279b 2514
d6dcc558 2515 if (accel_uses_host_cpuid()) {
bd182022
EH		 2516 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
2517 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
2518 int family, model, stepping;
d6dcc558
SAGDR		 2519 X86CPUDefinition host_cpudef = { };
2520 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2521
2522 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
2523 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
0bacd8b3 2524
bd182022 2525 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 2526
bd182022 2527 cpu_x86_fill_model_id(model_id);
0bacd8b3 2528
bd182022
EH		 2529 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
2530 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
2531 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
2532 object_property_set_int(OBJECT(cpu), stepping, "stepping",
2533 &error_abort);
2534 object_property_set_str(OBJECT(cpu), model_id, "model-id",
2535 &error_abort);
0bacd8b3 2536
d6dcc558
SAGDR		 2537 if (kvm_enabled()) {
2538 env->cpuid_min_level =
2539 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
2540 env->cpuid_min_xlevel =
2541 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
2542 env->cpuid_min_xlevel2 =
2543 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2544 } else {
2545 env->cpuid_min_level =
2546 hvf_get_supported_cpuid(0x0, 0, R_EAX);
2547 env->cpuid_min_xlevel =
2548 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
2549 env->cpuid_min_xlevel2 =
2550 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
2551 }
40bfe48f
HZ		 2552
2553 if (lmce_supported()) {
2554 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
2555 }
6900d1cc
EH		 2556 } else {
2557 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
2558 "vendor", &error_abort);
2559 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
2560 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
2561 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
2562 object_property_set_str(OBJECT(cpu),
2563 "QEMU TCG CPU version " QEMU_HW_VERSION,
2564 "model-id", &error_abort);
e4356010 2565 }
2a573259 2566
d940ee9b 2567 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 2568}
2569
c62f2630
EH		 2570static const TypeInfo max_x86_cpu_type_info = {
2571 .name = X86_CPU_TYPE_NAME("max"),
2572 .parent = TYPE_X86_CPU,
2573 .instance_init = max_x86_cpu_initfn,
2574 .class_init = max_x86_cpu_class_init,
2575};
2576
d6dcc558 2577#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 2578static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
2579{
2580 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2581
d6dcc558 2582 xcc->host_cpuid_required = true;
c62f2630
EH		 2583 xcc->ordering = 8;
2584
d6dcc558
SAGDR		 2585 if (kvm_enabled()) {
2586 xcc->model_description =
2587 "KVM processor with all supported host features ";
2588 } else if (hvf_enabled()) {
2589 xcc->model_description =
2590 "HVF processor with all supported host features ";
2591 }
c62f2630
EH		 2592}
2593
d940ee9b
EH		 2594static const TypeInfo host_x86_cpu_type_info = {
2595 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 2596 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 2597 .class_init = host_x86_cpu_class_init,
2598};
2599
2600#endif
2601
8459e396 2602static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 2603{
8459e396 2604 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 2605 int i;
2606
857aee33 2607 for (i = 0; i < 32; ++i) {
72370dc1 2608 if ((1UL << i) & mask) {
bffd67b0 2609 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 2610 assert(reg);
8297be80
AF		 2611 warn_report("%s doesn't support requested feature: "
2612 "CPUID.%02XH:%s%s%s [bit %d]",
d6dcc558 2613 accel_uses_host_cpuid() ? "host" : "TCG",
8297be80
AF		 2614 f->cpuid_eax, reg,
2615 f->feat_names[i] ? "." : "",
2616 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 2617 }
857aee33 2618 }
c6dc6f63
AP		 2619}
2620
d7bce999
EB		 2621static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
2622 const char *name, void *opaque,
2623 Error **errp)
95b8519d
AF		 2624{
2625 X86CPU *cpu = X86_CPU(obj);
2626 CPUX86State *env = &cpu->env;
2627 int64_t value;
2628
2629 value = (env->cpuid_version >> 8) & 0xf;
2630 if (value == 0xf) {
2631 value += (env->cpuid_version >> 20) & 0xff;
2632 }
51e72bc1 2633 visit_type_int(v, name, &value, errp);
95b8519d
AF		 2634}
2635
d7bce999
EB		 2636static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
2637 const char *name, void *opaque,
2638 Error **errp)
ed5e1ec3 2639{
71ad61d3
AF		 2640 X86CPU *cpu = X86_CPU(obj);
2641 CPUX86State *env = &cpu->env;
2642 const int64_t min = 0;
2643 const int64_t max = 0xff + 0xf;
65cd9064 2644 Error *local_err = NULL;
71ad61d3
AF		 2645 int64_t value;
2646
51e72bc1 2647 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2648 if (local_err) {
2649 error_propagate(errp, local_err);
71ad61d3
AF		 2650 return;
2651 }
2652 if (value < min || value > max) {
c6bd8c70
MA		 2653 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2654 name ? name : "null", value, min, max);
71ad61d3
AF		 2655 return;
2656 }
2657
ed5e1ec3 2658 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 2659 if (value > 0x0f) {
2660 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 2661 } else {
71ad61d3 2662 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 2663 }
2664}
2665
d7bce999
EB		 2666static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
2667 const char *name, void *opaque,
2668 Error **errp)
67e30c83
AF		 2669{
2670 X86CPU *cpu = X86_CPU(obj);
2671 CPUX86State *env = &cpu->env;
2672 int64_t value;
2673
2674 value = (env->cpuid_version >> 4) & 0xf;
2675 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 2676 visit_type_int(v, name, &value, errp);
67e30c83
AF		 2677}
2678
d7bce999
EB		 2679static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
2680 const char *name, void *opaque,
2681 Error **errp)
b0704cbd 2682{
c5291a4f
AF		 2683 X86CPU *cpu = X86_CPU(obj);
2684 CPUX86State *env = &cpu->env;
2685 const int64_t min = 0;
2686 const int64_t max = 0xff;
65cd9064 2687 Error *local_err = NULL;
c5291a4f
AF		 2688 int64_t value;
2689
51e72bc1 2690 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2691 if (local_err) {
2692 error_propagate(errp, local_err);
c5291a4f
AF		 2693 return;
2694 }
2695 if (value < min || value > max) {
c6bd8c70
MA		 2696 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2697 name ? name : "null", value, min, max);
c5291a4f
AF		 2698 return;
2699 }
2700
b0704cbd 2701 env->cpuid_version &= ~0xf00f0;
c5291a4f 2702 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 2703}
2704
35112e41 2705static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 2706 const char *name, void *opaque,
35112e41
AF		 2707 Error **errp)
2708{
2709 X86CPU *cpu = X86_CPU(obj);
2710 CPUX86State *env = &cpu->env;
2711 int64_t value;
2712
2713 value = env->cpuid_version & 0xf;
51e72bc1 2714 visit_type_int(v, name, &value, errp);
35112e41
AF		 2715}
2716
036e2222 2717static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 2718 const char *name, void *opaque,
036e2222 2719 Error **errp)
38c3dc46 2720{
036e2222
AF		 2721 X86CPU *cpu = X86_CPU(obj);
2722 CPUX86State *env = &cpu->env;
2723 const int64_t min = 0;
2724 const int64_t max = 0xf;
65cd9064 2725 Error *local_err = NULL;
036e2222
AF		 2726 int64_t value;
2727
51e72bc1 2728 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2729 if (local_err) {
2730 error_propagate(errp, local_err);
036e2222
AF		 2731 return;
2732 }
2733 if (value < min || value > max) {
c6bd8c70
MA		 2734 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2735 name ? name : "null", value, min, max);
036e2222
AF		 2736 return;
2737 }
2738
38c3dc46 2739 env->cpuid_version &= ~0xf;
036e2222 2740 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 2741}
2742
d480e1af
AF		 2743static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
2744{
2745 X86CPU *cpu = X86_CPU(obj);
2746 CPUX86State *env = &cpu->env;
2747 char *value;
d480e1af 2748
e42a92ae 2749 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 2750 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
2751 env->cpuid_vendor3);
d480e1af
AF		 2752 return value;
2753}
2754
2755static void x86_cpuid_set_vendor(Object *obj, const char *value,
2756 Error **errp)
2757{
2758 X86CPU *cpu = X86_CPU(obj);
2759 CPUX86State *env = &cpu->env;
2760 int i;
2761
9df694ee 2762 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 2763 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 2764 return;
2765 }
2766
2767 env->cpuid_vendor1 = 0;
2768 env->cpuid_vendor2 = 0;
2769 env->cpuid_vendor3 = 0;
2770 for (i = 0; i < 4; i++) {
2771 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
2772 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
2773 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
2774 }
d480e1af
AF		 2775}
2776
63e886eb
AF		 2777static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
2778{
2779 X86CPU *cpu = X86_CPU(obj);
2780 CPUX86State *env = &cpu->env;
2781 char *value;
2782 int i;
2783
2784 value = g_malloc(48 + 1);
2785 for (i = 0; i < 48; i++) {
2786 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
2787 }
2788 value[48] = '\0';
2789 return value;
2790}
2791
938d4c25
AF		 2792static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
2793 Error **errp)
dcce6675 2794{
938d4c25
AF		 2795 X86CPU *cpu = X86_CPU(obj);
2796 CPUX86State *env = &cpu->env;
dcce6675
AF		 2797 int c, len, i;
2798
2799 if (model_id == NULL) {
2800 model_id = "";
2801 }
2802 len = strlen(model_id);
d0a6acf4 2803 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 2804 for (i = 0; i < 48; i++) {
2805 if (i >= len) {
2806 c = '\0';
2807 } else {
2808 c = (uint8_t)model_id[i];
2809 }
2810 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
2811 }
2812}
2813
d7bce999
EB		 2814static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
2815 void *opaque, Error **errp)
89e48965
AF		 2816{
2817 X86CPU *cpu = X86_CPU(obj);
2818 int64_t value;
2819
2820 value = cpu->env.tsc_khz * 1000;
51e72bc1 2821 visit_type_int(v, name, &value, errp);
89e48965
AF		 2822}
2823
d7bce999
EB		 2824static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
2825 void *opaque, Error **errp)
89e48965
AF		 2826{
2827 X86CPU *cpu = X86_CPU(obj);
2828 const int64_t min = 0;
2e84849a 2829 const int64_t max = INT64_MAX;
65cd9064 2830 Error *local_err = NULL;
89e48965
AF		 2831 int64_t value;
2832
51e72bc1 2833 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 2834 if (local_err) {
2835 error_propagate(errp, local_err);
89e48965
AF		 2836 return;
2837 }
2838 if (value < min || value > max) {
c6bd8c70
MA		 2839 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
2840 name ? name : "null", value, min, max);
89e48965
AF		 2841 return;
2842 }
2843
36f96c4b 2844 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 2845}
2846
7e5292b5 2847/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 2848static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
2849 const char *name, void *opaque,
2850 Error **errp)
8e8aba50 2851{
7e5292b5 2852 uint32_t *array = (uint32_t *)opaque;
8e8aba50 2853 FeatureWord w;
8e8aba50
EH		 2854 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
2855 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
2856 X86CPUFeatureWordInfoList *list = NULL;
2857
2858 for (w = 0; w < FEATURE_WORDS; w++) {
2859 FeatureWordInfo *wi = &feature_word_info[w];
2860 X86CPUFeatureWordInfo *qwi = &word_infos[w];
2861 qwi->cpuid_input_eax = wi->cpuid_eax;
2862 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
2863 qwi->cpuid_input_ecx = wi->cpuid_ecx;
2864 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 2865 qwi->features = array[w];
8e8aba50
EH		 2866
2867 /* List will be in reverse order, but order shouldn't matter */
2868 list_entries[w].next = list;
2869 list_entries[w].value = &word_infos[w];
2870 list = &list_entries[w];
2871 }
2872
6b62d961 2873 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 2874}
2875
d7bce999
EB		 2876static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
2877 void *opaque, Error **errp)
c8f0f88e
IM		 2878{
2879 X86CPU *cpu = X86_CPU(obj);
2880 int64_t value = cpu->hyperv_spinlock_attempts;
2881
51e72bc1 2882 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 2883}
2884
d7bce999
EB		 2885static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
2886 void *opaque, Error **errp)
c8f0f88e
IM		 2887{
2888 const int64_t min = 0xFFF;
2889 const int64_t max = UINT_MAX;
2890 X86CPU *cpu = X86_CPU(obj);
2891 Error *err = NULL;
2892 int64_t value;
2893
51e72bc1 2894 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 2895 if (err) {
2896 error_propagate(errp, err);
2897 return;
2898 }
2899
2900 if (value < min || value > max) {
2901 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 2902 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
2903 object_get_typename(obj), name ? name : "null",
2904 value, min, max);
c8f0f88e
IM		 2905 return;
2906 }
2907 cpu->hyperv_spinlock_attempts = value;
2908}
2909
1b6b7d10 2910static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 2911 .name = "int",
2912 .get = x86_get_hv_spinlocks,
2913 .set = x86_set_hv_spinlocks,
2914};
2915
72ac2e87
IM		 2916/* Convert all '_' in a feature string option name to '-', to make feature
2917 * name conform to QOM property naming rule, which uses '-' instead of '_'.
2918 */
2919static inline void feat2prop(char *s)
2920{
2921 while ((s = strchr(s, '_'))) {
2922 *s = '-';
2923 }
2924}
2925
b54c9377
EH		 2926/* Return the feature property name for a feature flag bit */
2927static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
2928{
2929 /* XSAVE components are automatically enabled by other features,
2930 * so return the original feature name instead
2931 */
2932 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
2933 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
2934
2935 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
2936 x86_ext_save_areas[comp].bits) {
2937 w = x86_ext_save_areas[comp].feature;
2938 bitnr = ctz32(x86_ext_save_areas[comp].bits);
2939 }
2940 }
2941
2942 assert(bitnr < 32);
2943 assert(w < FEATURE_WORDS);
2944 return feature_word_info[w].feat_names[bitnr];
2945}
2946
dc15c051
IM		 2947/* Compatibily hack to maintain legacy +-feat semantic,
2948 * where +-feat overwrites any feature set by
2949 * feat=on|feat even if the later is parsed after +-feat
2950 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2951 */
2fae0d96 2952static GList *plus_features, *minus_features;
dc15c051 2953
83a00f60
EH		 2954static gint compare_string(gconstpointer a, gconstpointer b)
2955{
2956 return g_strcmp0(a, b);
2957}
2958
8f961357
EH		 2959/* Parse "+feature,-feature,feature=foo" CPU feature string
2960 */
62a48a2a 2961static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 2962 Error **errp)
8f961357 2963{
8f961357 2964 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 2965 static bool cpu_globals_initialized;
83a00f60 2966 bool ambiguous = false;
62a48a2a
IM		 2967
2968 if (cpu_globals_initialized) {
2969 return;
2970 }
2971 cpu_globals_initialized = true;
8f961357 2972
f6750e95
EH		 2973 if (!features) {
2974 return;
2975 }
2976
2977 for (featurestr = strtok(features, ",");
685479bd 2978 featurestr;
f6750e95
EH		 2979 featurestr = strtok(NULL, ",")) {
2980 const char *name;
2981 const char *val = NULL;
2982 char *eq = NULL;
cf2887c9 2983 char num[32];
62a48a2a 2984 GlobalProperty *prop;
c6dc6f63 2985
f6750e95 2986 /* Compatibility syntax: */
c6dc6f63 2987 if (featurestr[0] == '+') {
2fae0d96
EH		 2988 plus_features = g_list_append(plus_features,
2989 g_strdup(featurestr + 1));
f6750e95 2990 continue;
c6dc6f63 2991 } else if (featurestr[0] == '-') {
2fae0d96
EH		 2992 minus_features = g_list_append(minus_features,
2993 g_strdup(featurestr + 1));
f6750e95
EH		 2994 continue;
2995 }
2996
2997 eq = strchr(featurestr, '=');
2998 if (eq) {
2999 *eq++ = 0;
3000 val = eq;
c6dc6f63 3001 } else {
f6750e95 3002 val = "on";
a91987c2 3003 }
f6750e95
EH		 3004
3005 feat2prop(featurestr);
3006 name = featurestr;
3007
83a00f60 3008 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 3009 warn_report("Ambiguous CPU model string. "
3010 "Don't mix both \"+%s\" and \"%s=%s\"",
3011 name, name, val);
83a00f60
EH		 3012 ambiguous = true;
3013 }
3014 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 3015 warn_report("Ambiguous CPU model string. "
3016 "Don't mix both \"-%s\" and \"%s=%s\"",
3017 name, name, val);
83a00f60
EH		 3018 ambiguous = true;
3019 }
3020
f6750e95
EH		 3021 /* Special case: */
3022 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 3023 int ret;
f46bfdbf 3024 uint64_t tsc_freq;
f6750e95 3025
f17fd4fd 3026 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 3027 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 3028 error_setg(errp, "bad numerical value %s", val);
3029 return;
3030 }
3031 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3032 val = num;
3033 name = "tsc-frequency";
c6dc6f63 3034 }
f6750e95 3035
62a48a2a
IM		 3036 prop = g_new0(typeof(*prop), 1);
3037 prop->driver = typename;
3038 prop->property = g_strdup(name);
3039 prop->value = g_strdup(val);
3040 prop->errp = &error_fatal;
3041 qdev_prop_register_global(prop);
f6750e95
EH		 3042 }
3043
83a00f60 3044 if (ambiguous) {
3dc6f869
AF		 3045 warn_report("Compatibility of ambiguous CPU model "
3046 "strings won't be kept on future QEMU versions");
83a00f60 3047 }
c6dc6f63
AP		 3048}
3049
b8d834a0 3050static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 3051static int x86_cpu_filter_features(X86CPU *cpu);
3052
3053/* Check for missing features that may prevent the CPU class from
3054 * running using the current machine and accelerator.
3055 */
3056static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3057 strList **missing_feats)
3058{
3059 X86CPU *xc;
3060 FeatureWord w;
3061 Error *err = NULL;
3062 strList **next = missing_feats;
3063
d6dcc558 3064 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 3065 strList *new = g_new0(strList, 1);
3c254ab8 3066 new->value = g_strdup("kvm");
b54c9377
EH		 3067 *missing_feats = new;
3068 return;
3069 }
3070
3071 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3072
b8d834a0 3073 x86_cpu_expand_features(xc, &err);
b54c9377 3074 if (err) {
b8d834a0 3075 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 3076 * but in case it does, just report the model as not
3077 * runnable at all using the "type" property.
3078 */
3079 strList *new = g_new0(strList, 1);
3080 new->value = g_strdup("type");
3081 *next = new;
3082 next = &new->next;
3083 }
3084
3085 x86_cpu_filter_features(xc);
3086
3087 for (w = 0; w < FEATURE_WORDS; w++) {
3088 uint32_t filtered = xc->filtered_features[w];
3089 int i;
3090 for (i = 0; i < 32; i++) {
3091 if (filtered & (1UL << i)) {
3092 strList *new = g_new0(strList, 1);
3093 new->value = g_strdup(x86_cpu_feature_name(w, i));
3094 *next = new;
3095 next = &new->next;
3096 }
3097 }
3098 }
3099
3100 object_unref(OBJECT(xc));
3101}
3102
8c3329e5 3103/* Print all cpuid feature names in featureset
c6dc6f63 3104 */
8c3329e5 3105static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 3106{
8c3329e5
EH		 3107 int bit;
3108 bool first = true;
3109
3110 for (bit = 0; bit < 32; bit++) {
3111 if (featureset[bit]) {
3112 print(f, "%s%s", first ? "" : " ", featureset[bit]);
3113 first = false;
c6dc6f63 3114 }
8c3329e5 3115 }
c6dc6f63
AP		 3116}
3117
f48c8837 3118/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 3119static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3120{
3121 ObjectClass *class_a = (ObjectClass *)a;
3122 ObjectClass *class_b = (ObjectClass *)b;
3123 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3124 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
3125 const char *name_a, *name_b;
3126
f48c8837
EH		 3127 if (cc_a->ordering != cc_b->ordering) {
3128 return cc_a->ordering - cc_b->ordering;
ee465a3e
EH		 3129 } else {
3130 name_a = object_class_get_name(class_a);
3131 name_b = object_class_get_name(class_b);
3132 return strcmp(name_a, name_b);
3133 }
3134}
3135
3136static GSList *get_sorted_cpu_model_list(void)
3137{
3138 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3139 list = g_slist_sort(list, x86_cpu_list_compare);
3140 return list;
3141}
3142
3143static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3144{
3145 ObjectClass *oc = data;
3146 X86CPUClass *cc = X86_CPU_CLASS(oc);
3147 CPUListState *s = user_data;
3148 char *name = x86_cpu_class_get_model_name(cc);
3149 const char *desc = cc->model_description;
0bacd8b3 3150 if (!desc && cc->cpu_def) {
ee465a3e
EH		 3151 desc = cc->cpu_def->model_id;
3152 }
3153
3154 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
3155 name, desc);
3156 g_free(name);
3157}
3158
3159/* list available CPU models and flags */
e916cbf8 3160void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 3161{
7fc9b714 3162 int i;
ee465a3e
EH		 3163 CPUListState s = {
3164 .file = f,
3165 .cpu_fprintf = cpu_fprintf,
3166 };
3167 GSList *list;
c6dc6f63 3168
ee465a3e
EH		 3169 (*cpu_fprintf)(f, "Available CPUs:\n");
3170 list = get_sorted_cpu_model_list();
3171 g_slist_foreach(list, x86_cpu_list_entry, &s);
3172 g_slist_free(list);
21ad7789 3173
6cdf8854 3174 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 3175 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3176 FeatureWordInfo *fw = &feature_word_info[i];
3177
8c3329e5
EH		 3178 (*cpu_fprintf)(f, " ");
3179 listflags(f, cpu_fprintf, fw->feat_names);
3180 (*cpu_fprintf)(f, "\n");
3af60be2 3181 }
c6dc6f63
AP		 3182}
3183
ee465a3e
EH		 3184static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3185{
3186 ObjectClass *oc = data;
3187 X86CPUClass *cc = X86_CPU_CLASS(oc);
3188 CpuDefinitionInfoList **cpu_list = user_data;
3189 CpuDefinitionInfoList *entry;
3190 CpuDefinitionInfo *info;
3191
3192 info = g_malloc0(sizeof(*info));
3193 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 3194 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3195 info->has_unavailable_features = true;
8ed877b7 3196 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 3197 info->migration_safe = cc->migration_safe;
3198 info->has_migration_safe = true;
5adbed30 3199 info->q_static = cc->static_model;
ee465a3e
EH		 3200
3201 entry = g_malloc0(sizeof(*entry));
3202 entry->value = info;
3203 entry->next = *cpu_list;
3204 *cpu_list = entry;
3205}
3206
76b64a7a 3207CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 3208{
3209 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 3210 GSList *list = get_sorted_cpu_model_list();
3211 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3212 g_slist_free(list);
e3966126
AL		 3213 return cpu_list;
3214}
3215
84f1b92f
EH		 3216static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3217 bool migratable_only)
27418adf
EH		 3218{
3219 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 3220 uint32_t r;
27418adf 3221
fefb41bf 3222 if (kvm_enabled()) {
84f1b92f
EH		 3223 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
3224 wi->cpuid_ecx,
3225 wi->cpuid_reg);
d6dcc558
SAGDR		 3226 } else if (hvf_enabled()) {
3227 r = hvf_get_supported_cpuid(wi->cpuid_eax,
3228 wi->cpuid_ecx,
3229 wi->cpuid_reg);
fefb41bf 3230 } else if (tcg_enabled()) {
84f1b92f 3231 r = wi->tcg_features;
fefb41bf
EH		 3232 } else {
3233 return ~0;
3234 }
84f1b92f
EH		 3235 if (migratable_only) {
3236 r &= x86_cpu_get_migratable_flags(w);
3237 }
3238 return r;
27418adf
EH		 3239}
3240
8ca30e86
EH		 3241static void x86_cpu_report_filtered_features(X86CPU *cpu)
3242{
3243 FeatureWord w;
3244
3245 for (w = 0; w < FEATURE_WORDS; w++) {
3246 report_unavailable_features(w, cpu->filtered_features[w]);
3247 }
3248}
3249
5114e842
EH		 3250static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3251{
3252 PropValue *pv;
3253 for (pv = props; pv->prop; pv++) {
3254 if (!pv->value) {
3255 continue;
3256 }
3257 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3258 &error_abort);
3259 }
3260}
3261
f99fd7ca 3262/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 3263 */
d940ee9b 3264static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 3265{
61dcd775 3266 CPUX86State *env = &cpu->env;
74f54bc4
EH		 3267 const char *vendor;
3268 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 3269 FeatureWord w;
c6dc6f63 3270
f99fd7ca
EH		 3271 /*NOTE: any property set by this function should be returned by
3272 * x86_cpu_static_props(), so static expansion of
3273 * query-cpu-model-expansion is always complete.
3274 */
3275
c39c0edf 3276 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 3277 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3278 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 3279
2d64255b
AF		 3280 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3281 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3282 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 3283 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 3284 for (w = 0; w < FEATURE_WORDS; w++) {
3285 env->features[w] = def->features[w];
3286 }
82beb536 3287
9576de75 3288 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 3289 /* TODO: in-kernel irqchip for hvf */
82beb536 3290 if (kvm_enabled()) {
492a4c94
LT		 3291 if (!kvm_irqchip_in_kernel()) {
3292 x86_cpu_change_kvm_default("x2apic", "off");
3293 }
3294
5114e842 3295 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 3296 } else if (tcg_enabled()) {
3297 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 3298 }
5fcca9ff 3299
82beb536 3300 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 3301
3302 /* sysenter isn't supported in compatibility mode on AMD,
3303 * syscall isn't supported in compatibility mode on Intel.
3304 * Normally we advertise the actual CPU vendor, but you can
3305 * override this using the 'vendor' property if you want to use
3306 * KVM's sysenter/syscall emulation in compatibility mode and
3307 * when doing cross vendor migration
3308 */
74f54bc4 3309 vendor = def->vendor;
d6dcc558 3310 if (accel_uses_host_cpuid()) {
7c08db30
EH		 3311 uint32_t ebx = 0, ecx = 0, edx = 0;
3312 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3313 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3314 vendor = host_vendor;
3315 }
3316
3317 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3318
c6dc6f63
AP		 3319}
3320
f99fd7ca
EH		 3321/* Return a QDict containing keys for all properties that can be included
3322 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3323 * must be included in the dictionary.
3324 */
3325static QDict *x86_cpu_static_props(void)
3326{
3327 FeatureWord w;
3328 int i;
3329 static const char *props[] = {
3330 "min-level",
3331 "min-xlevel",
3332 "family",
3333 "model",
3334 "stepping",
3335 "model-id",
3336 "vendor",
3337 "lmce",
3338 NULL,
3339 };
3340 static QDict *d;
3341
3342 if (d) {
3343 return d;
3344 }
3345
3346 d = qdict_new();
3347 for (i = 0; props[i]; i++) {
0f9afc2a 3348 qdict_put_null(d, props[i]);
f99fd7ca
EH		 3349 }
3350
3351 for (w = 0; w < FEATURE_WORDS; w++) {
3352 FeatureWordInfo *fi = &feature_word_info[w];
3353 int bit;
3354 for (bit = 0; bit < 32; bit++) {
3355 if (!fi->feat_names[bit]) {
3356 continue;
3357 }
0f9afc2a 3358 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 3359 }
3360 }
3361
3362 return d;
3363}
3364
3365/* Add an entry to @props dict, with the value for property. */
3366static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
3367{
3368 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
3369 &error_abort);
3370
3371 qdict_put_obj(props, prop, value);
3372}
3373
3374/* Convert CPU model data from X86CPU object to a property dictionary
3375 * that can recreate exactly the same CPU model.
3376 */
3377static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
3378{
3379 QDict *sprops = x86_cpu_static_props();
3380 const QDictEntry *e;
3381
3382 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
3383 const char *prop = qdict_entry_key(e);
3384 x86_cpu_expand_prop(cpu, props, prop);
3385 }
3386}
3387
b8097deb
EH		 3388/* Convert CPU model data from X86CPU object to a property dictionary
3389 * that can recreate exactly the same CPU model, including every
3390 * writeable QOM property.
3391 */
3392static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
3393{
3394 ObjectPropertyIterator iter;
3395 ObjectProperty *prop;
3396
3397 object_property_iter_init(&iter, OBJECT(cpu));
3398 while ((prop = object_property_iter_next(&iter))) {
3399 /* skip read-only or write-only properties */
3400 if (!prop->get || !prop->set) {
3401 continue;
3402 }
3403
3404 /* "hotplugged" is the only property that is configurable
3405 * on the command-line but will be set differently on CPUs
3406 * created using "-cpu ... -smp ..." and by CPUs created
3407 * on the fly by x86_cpu_from_model() for querying. Skip it.
3408 */
3409 if (!strcmp(prop->name, "hotplugged")) {
3410 continue;
3411 }
3412 x86_cpu_expand_prop(cpu, props, prop->name);
3413 }
3414}
3415
f99fd7ca
EH		 3416static void object_apply_props(Object *obj, QDict *props, Error **errp)
3417{
3418 const QDictEntry *prop;
3419 Error *err = NULL;
3420
3421 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
3422 object_property_set_qobject(obj, qdict_entry_value(prop),
3423 qdict_entry_key(prop), &err);
3424 if (err) {
3425 break;
3426 }
3427 }
3428
3429 error_propagate(errp, err);
3430}
3431
3432/* Create X86CPU object according to model+props specification */
3433static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
3434{
3435 X86CPU *xc = NULL;
3436 X86CPUClass *xcc;
3437 Error *err = NULL;
3438
3439 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
3440 if (xcc == NULL) {
3441 error_setg(&err, "CPU model '%s' not found", model);
3442 goto out;
3443 }
3444
3445 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3446 if (props) {
3447 object_apply_props(OBJECT(xc), props, &err);
3448 if (err) {
3449 goto out;
3450 }
3451 }
3452
3453 x86_cpu_expand_features(xc, &err);
3454 if (err) {
3455 goto out;
3456 }
3457
3458out:
3459 if (err) {
3460 error_propagate(errp, err);
3461 object_unref(OBJECT(xc));
3462 xc = NULL;
3463 }
3464 return xc;
3465}
3466
3467CpuModelExpansionInfo *
3468arch_query_cpu_model_expansion(CpuModelExpansionType type,
3469 CpuModelInfo *model,
3470 Error **errp)
3471{
3472 X86CPU *xc = NULL;
3473 Error *err = NULL;
3474 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
3475 QDict *props = NULL;
3476 const char *base_name;
3477
3478 xc = x86_cpu_from_model(model->name,
3479 model->has_props ?
7dc847eb 3480 qobject_to(QDict, model->props) :
f99fd7ca
EH		 3481 NULL, &err);
3482 if (err) {
3483 goto out;
3484 }
3485
b8097deb 3486 props = qdict_new();
f99fd7ca
EH		 3487
3488 switch (type) {
3489 case CPU_MODEL_EXPANSION_TYPE_STATIC:
3490 /* Static expansion will be based on "base" only */
3491 base_name = "base";
b8097deb 3492 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 3493 break;
3494 case CPU_MODEL_EXPANSION_TYPE_FULL:
3495 /* As we don't return every single property, full expansion needs
3496 * to keep the original model name+props, and add extra
3497 * properties on top of that.
3498 */
3499 base_name = model->name;
b8097deb 3500 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 3501 break;
3502 default:
3503 error_setg(&err, "Unsupportted expansion type");
3504 goto out;
3505 }
3506
3507 if (!props) {
3508 props = qdict_new();
3509 }
3510 x86_cpu_to_dict(xc, props);
3511
3512 ret->model = g_new0(CpuModelInfo, 1);
3513 ret->model->name = g_strdup(base_name);
3514 ret->model->props = QOBJECT(props);
3515 ret->model->has_props = true;
3516
3517out:
3518 object_unref(OBJECT(xc));
3519 if (err) {
3520 error_propagate(errp, err);
3521 qapi_free_CpuModelExpansionInfo(ret);
3522 ret = NULL;
3523 }
3524 return ret;
3525}
3526
00fcd100
AB		 3527static gchar *x86_gdb_arch_name(CPUState *cs)
3528{
3529#ifdef TARGET_X86_64
3530 return g_strdup("i386:x86-64");
3531#else
3532 return g_strdup("i386");
3533#endif
3534}
3535
d940ee9b
EH		 3536static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
3537{
3538 X86CPUDefinition *cpudef = data;
3539 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3540
3541 xcc->cpu_def = cpudef;
bd72159d 3542 xcc->migration_safe = true;
d940ee9b
EH		 3543}
3544
3545static void x86_register_cpudef_type(X86CPUDefinition *def)
3546{
3547 char *typename = x86_cpu_type_name(def->name);
3548 TypeInfo ti = {
3549 .name = typename,
3550 .parent = TYPE_X86_CPU,
3551 .class_init = x86_cpu_cpudef_class_init,
3552 .class_data = def,
3553 };
3554
2a923a29
EH		 3555 /* AMD aliases are handled at runtime based on CPUID vendor, so
3556 * they shouldn't be set on the CPU model table.
3557 */
3558 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 3559 /* catch mistakes instead of silently truncating model_id when too long */
3560 assert(def->model_id && strlen(def->model_id) <= 48);
3561
2a923a29 3562
d940ee9b
EH		 3563 type_register(&ti);
3564 g_free(typename);
3565}
3566
c6dc6f63 3567#if !defined(CONFIG_USER_ONLY)
c6dc6f63 3568
0e26b7b8
BS		 3569void cpu_clear_apic_feature(CPUX86State *env)
3570{
0514ef2f 3571 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 3572}
3573
c6dc6f63
AP		 3574#endif /* !CONFIG_USER_ONLY */
3575
c6dc6f63
AP		 3576void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
3577 uint32_t *eax, uint32_t *ebx,
3578 uint32_t *ecx, uint32_t *edx)
3579{
a60f24b5
AF		 3580 X86CPU *cpu = x86_env_get_cpu(env);
3581 CPUState *cs = CPU(cpu);
14c985cf 3582 uint32_t pkg_offset;
4ed3d478 3583 uint32_t limit;
1ce36bfe 3584 uint32_t signature[3];
a60f24b5 3585
4ed3d478
DB		 3586 /* Calculate & apply limits for different index ranges */
3587 if (index >= 0xC0000000) {
3588 limit = env->cpuid_xlevel2;
3589 } else if (index >= 0x80000000) {
3590 limit = env->cpuid_xlevel;
1ce36bfe
DB		 3591 } else if (index >= 0x40000000) {
3592 limit = 0x40000001;
c6dc6f63 3593 } else {
4ed3d478
DB		 3594 limit = env->cpuid_level;
3595 }
3596
3597 if (index > limit) {
3598 /* Intel documentation states that invalid EAX input will
3599 * return the same information as EAX=cpuid_level
3600 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
3601 */
3602 index = env->cpuid_level;
c6dc6f63
AP		 3603 }
3604
3605 switch(index) {
3606 case 0:
3607 *eax = env->cpuid_level;
5eb2f7a4
EH		 3608 *ebx = env->cpuid_vendor1;
3609 *edx = env->cpuid_vendor2;
3610 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 3611 break;
3612 case 1:
3613 *eax = env->cpuid_version;
7e72a45c
EH		 3614 *ebx = (cpu->apic_id << 24) |
3615 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 3616 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 3617 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
3618 *ecx |= CPUID_EXT_OSXSAVE;
3619 }
0514ef2f 3620 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 3621 if (cs->nr_cores * cs->nr_threads > 1) {
3622 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 3623 *edx |= CPUID_HT;
c6dc6f63
AP		 3624 }
3625 break;
3626 case 2:
3627 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 3628 if (cpu->cache_info_passthrough) {
3629 host_cpuid(index, 0, eax, ebx, ecx, edx);
3630 break;
3631 }
5e891bf8 3632 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 3633 *ebx = 0;
14c985cf
LM		 3634 if (!cpu->enable_l3_cache) {
3635 *ecx = 0;
3636 } else {
7e3482f8 3637 *ecx = cpuid2_cache_descriptor(&l3_cache);
14c985cf 3638 }
7e3482f8
EH		 3639 *edx = (cpuid2_cache_descriptor(&l1d_cache) << 16) |
3640 (cpuid2_cache_descriptor(&l1i_cache) << 8) |
3641 (cpuid2_cache_descriptor(&l2_cache_cpuid2));
c6dc6f63
AP		 3642 break;
3643 case 4:
3644 /* cache info: needed for Core compatibility */
787aaf57
BC		 3645 if (cpu->cache_info_passthrough) {
3646 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 3647 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 3648 *eax &= ~0xFC000000;
7e3482f8
EH		 3649 if ((*eax & 31) && cs->nr_cores > 1) {
3650 *eax |= (cs->nr_cores - 1) << 26;
3651 }
c6dc6f63 3652 } else {
2f7a21c4 3653 *eax = 0;
76c2975a 3654 switch (count) {
c6dc6f63 3655 case 0: /* L1 dcache info */
7e3482f8
EH		 3656 encode_cache_cpuid4(&l1d_cache,
3657 1, cs->nr_cores,
3658 eax, ebx, ecx, edx);
c6dc6f63
AP		 3659 break;
3660 case 1: /* L1 icache info */
7e3482f8
EH		 3661 encode_cache_cpuid4(&l1i_cache,
3662 1, cs->nr_cores,
3663 eax, ebx, ecx, edx);
c6dc6f63
AP		 3664 break;
3665 case 2: /* L2 cache info */
7e3482f8
EH		 3666 encode_cache_cpuid4(&l2_cache,
3667 cs->nr_threads, cs->nr_cores,
3668 eax, ebx, ecx, edx);
c6dc6f63 3669 break;
14c985cf 3670 case 3: /* L3 cache info */
7e3482f8
EH		 3671 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
3672 if (cpu->enable_l3_cache) {
3673 encode_cache_cpuid4(&l3_cache,
3674 (1 << pkg_offset), cs->nr_cores,
3675 eax, ebx, ecx, edx);
14c985cf
LM		 3676 break;
3677 }
7e3482f8 3678 /* fall through */
c6dc6f63 3679 default: /* end of info */
7e3482f8 3680 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 3681 break;
76c2975a
PB		 3682 }
3683 }
c6dc6f63
AP		 3684 break;
3685 case 5:
3686 /* mwait info: needed for Core compatibility */
3687 *eax = 0; /* Smallest monitor-line size in bytes */
3688 *ebx = 0; /* Largest monitor-line size in bytes */
3689 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
3690 *edx = 0;
3691 break;
3692 case 6:
3693 /* Thermal and Power Leaf */
28b8e4d0 3694 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 3695 *ebx = 0;
3696 *ecx = 0;
3697 *edx = 0;
3698 break;
f7911686 3699 case 7:
13526728
EH		 3700 /* Structured Extended Feature Flags Enumeration Leaf */
3701 if (count == 0) {
3702 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 3703 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 3704 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 3705 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
3706 *ecx |= CPUID_7_0_ECX_OSPKE;
3707 }
95ea69fb 3708 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 3709 } else {
3710 *eax = 0;
3711 *ebx = 0;
3712 *ecx = 0;
3713 *edx = 0;
3714 }
3715 break;
c6dc6f63
AP		 3716 case 9:
3717 /* Direct Cache Access Information Leaf */
3718 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
3719 *ebx = 0;
3720 *ecx = 0;
3721 *edx = 0;
3722 break;
3723 case 0xA:
3724 /* Architectural Performance Monitoring Leaf */
9337e3b6 3725 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 3726 KVMState *s = cs->kvm_state;
a0fa8208
GN		 3727
3728 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
3729 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
3730 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
3731 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 3732 } else if (hvf_enabled() && cpu->enable_pmu) {
3733 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
3734 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
3735 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
3736 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 3737 } else {
3738 *eax = 0;
3739 *ebx = 0;
3740 *ecx = 0;
3741 *edx = 0;
3742 }
c6dc6f63 3743 break;
5232d00a
RK		 3744 case 0xB:
3745 /* Extended Topology Enumeration Leaf */
3746 if (!cpu->enable_cpuid_0xb) {
3747 *eax = *ebx = *ecx = *edx = 0;
3748 break;
3749 }
3750
3751 *ecx = count & 0xff;
3752 *edx = cpu->apic_id;
3753
3754 switch (count) {
3755 case 0:
eab60fb9
MAL		 3756 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
3757 *ebx = cs->nr_threads;
5232d00a
RK		 3758 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
3759 break;
3760 case 1:
eab60fb9
MAL		 3761 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
3762 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 3763 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
3764 break;
3765 default:
3766 *eax = 0;
3767 *ebx = 0;
3768 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
3769 }
3770
3771 assert(!(*eax & ~0x1f));
3772 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
3773 break;
2560f19f 3774 case 0xD: {
51e49430 3775 /* Processor Extended State */
2560f19f
PB		 3776 *eax = 0;
3777 *ebx = 0;
3778 *ecx = 0;
3779 *edx = 0;
19dc85db 3780 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 3781 break;
3782 }
4928cd6d 3783
2560f19f 3784 if (count == 0) {
96193c22
EH		 3785 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
3786 *eax = env->features[FEAT_XSAVE_COMP_LO];
3787 *edx = env->features[FEAT_XSAVE_COMP_HI];
2560f19f
PB		 3788 *ebx = *ecx;
3789 } else if (count == 1) {
0bb0b2d2 3790 *eax = env->features[FEAT_XSAVE];
f4f1110e 3791 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 3792 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
3793 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 3794 *eax = esa->size;
3795 *ebx = esa->offset;
2560f19f 3796 }
51e49430
SY		 3797 }
3798 break;
2560f19f 3799 }
e37a5c7f
CP		 3800 case 0x14: {
3801 /* Intel Processor Trace Enumeration */
3802 *eax = 0;
3803 *ebx = 0;
3804 *ecx = 0;
3805 *edx = 0;
3806 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
3807 !kvm_enabled()) {
3808 break;
3809 }
3810
3811 if (count == 0) {
3812 *eax = INTEL_PT_MAX_SUBLEAF;
3813 *ebx = INTEL_PT_MINIMAL_EBX;
3814 *ecx = INTEL_PT_MINIMAL_ECX;
3815 } else if (count == 1) {
3816 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
3817 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
3818 }
3819 break;
3820 }
1ce36bfe
DB		 3821 case 0x40000000:
3822 /*
3823 * CPUID code in kvm_arch_init_vcpu() ignores stuff
3824 * set here, but we restrict to TCG none the less.
3825 */
3826 if (tcg_enabled() && cpu->expose_tcg) {
3827 memcpy(signature, "TCGTCGTCGTCG", 12);
3828 *eax = 0x40000001;
3829 *ebx = signature[0];
3830 *ecx = signature[1];
3831 *edx = signature[2];
3832 } else {
3833 *eax = 0;
3834 *ebx = 0;
3835 *ecx = 0;
3836 *edx = 0;
3837 }
3838 break;
3839 case 0x40000001:
3840 *eax = 0;
3841 *ebx = 0;
3842 *ecx = 0;
3843 *edx = 0;
3844 break;
c6dc6f63
AP		 3845 case 0x80000000:
3846 *eax = env->cpuid_xlevel;
3847 *ebx = env->cpuid_vendor1;
3848 *edx = env->cpuid_vendor2;
3849 *ecx = env->cpuid_vendor3;
3850 break;
3851 case 0x80000001:
3852 *eax = env->cpuid_version;
3853 *ebx = 0;
0514ef2f
EH		 3854 *ecx = env->features[FEAT_8000_0001_ECX];
3855 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 3856
3857 /* The Linux kernel checks for the CMPLegacy bit and
3858 * discards multiple thread information if it is set.
cb8d4c8f 3859 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 3860 */
ce3960eb 3861 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 3862 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
3863 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
3864 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 3865 *ecx |= 1 << 1; /* CmpLegacy bit */
3866 }
3867 }
c6dc6f63
AP		 3868 break;
3869 case 0x80000002:
3870 case 0x80000003:
3871 case 0x80000004:
3872 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
3873 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
3874 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
3875 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
3876 break;
3877 case 0x80000005:
3878 /* cache info (L1 cache) */
787aaf57
BC		 3879 if (cpu->cache_info_passthrough) {
3880 host_cpuid(index, 0, eax, ebx, ecx, edx);
3881 break;
3882 }
5e891bf8
EH		 3883 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
3884 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
3885 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
3886 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
7e3482f8
EH		 3887 *ecx = encode_cache_cpuid80000005(&l1d_cache_amd);
3888 *edx = encode_cache_cpuid80000005(&l1i_cache_amd);
c6dc6f63
AP		 3889 break;
3890 case 0x80000006:
3891 /* cache info (L2 cache) */
787aaf57
BC		 3892 if (cpu->cache_info_passthrough) {
3893 host_cpuid(index, 0, eax, ebx, ecx, edx);
3894 break;
3895 }
5e891bf8
EH		 3896 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
3897 (L2_DTLB_2M_ENTRIES << 16) | \
3898 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
3899 (L2_ITLB_2M_ENTRIES);
3900 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
3901 (L2_DTLB_4K_ENTRIES << 16) | \
3902 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
3903 (L2_ITLB_4K_ENTRIES);
7e3482f8
EH		 3904 encode_cache_cpuid80000006(&l2_cache_amd,
3905 cpu->enable_l3_cache ? &l3_cache : NULL,
3906 ecx, edx);
c6dc6f63 3907 break;
303752a9
MT		 3908 case 0x80000007:
3909 *eax = 0;
3910 *ebx = 0;
3911 *ecx = 0;
3912 *edx = env->features[FEAT_8000_0007_EDX];
3913 break;
c6dc6f63
AP		 3914 case 0x80000008:
3915 /* virtual & phys address size in low 2 bytes. */
0514ef2f 3916 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 3917 /* 64 bit processor */
3918 *eax = cpu->phys_bits; /* configurable physical bits */
3919 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
3920 *eax |= 0x00003900; /* 57 bits virtual */
3921 } else {
3922 *eax |= 0x00003000; /* 48 bits virtual */
3923 }
c6dc6f63 3924 } else {
af45907a 3925 *eax = cpu->phys_bits;
c6dc6f63 3926 }
1b3420e1 3927 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 3928 *ecx = 0;
3929 *edx = 0;
ce3960eb
AF		 3930 if (cs->nr_cores * cs->nr_threads > 1) {
3931 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 3932 }
3933 break;
3934 case 0x8000000A:
0514ef2f 3935 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 3936 *eax = 0x00000001; /* SVM Revision */
3937 *ebx = 0x00000010; /* nr of ASIDs */
3938 *ecx = 0;
0514ef2f 3939 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 3940 } else {
3941 *eax = 0;
3942 *ebx = 0;
3943 *ecx = 0;
3944 *edx = 0;
3945 }
c6dc6f63 3946 break;
b3baa152
BW		 3947 case 0xC0000000:
3948 *eax = env->cpuid_xlevel2;
3949 *ebx = 0;
3950 *ecx = 0;
3951 *edx = 0;
3952 break;
3953 case 0xC0000001:
3954 /* Support for VIA CPU's CPUID instruction */
3955 *eax = env->cpuid_version;
3956 *ebx = 0;
3957 *ecx = 0;
0514ef2f 3958 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 3959 break;
3960 case 0xC0000002:
3961 case 0xC0000003:
3962 case 0xC0000004:
3963 /* Reserved for the future, and now filled with zero */
3964 *eax = 0;
3965 *ebx = 0;
3966 *ecx = 0;
3967 *edx = 0;
3968 break;
6cb8f2a6
BS		 3969 case 0x8000001F:
3970 *eax = sev_enabled() ? 0x2 : 0;
3971 *ebx = sev_get_cbit_position();
3972 *ebx |= sev_get_reduced_phys_bits() << 6;
3973 *ecx = 0;
3974 *edx = 0;
3975 break;
c6dc6f63
AP		 3976 default:
3977 /* reserved values: zero */
3978 *eax = 0;
3979 *ebx = 0;
3980 *ecx = 0;
3981 *edx = 0;
3982 break;
3983 }
3984}
5fd2087a
AF		 3985
3986/* CPUClass::reset() */
3987static void x86_cpu_reset(CPUState *s)
3988{
3989 X86CPU *cpu = X86_CPU(s);
3990 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
3991 CPUX86State *env = &cpu->env;
a114d25d
RH		 3992 target_ulong cr4;
3993 uint64_t xcr0;
c1958aea
AF		 3994 int i;
3995
5fd2087a
AF		 3996 xcc->parent_reset(s);
3997
5e992a8e 3998 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 3999
c1958aea
AF		 4000 env->old_exception = -1;
4001
4002 /* init to reset state */
4003
c1958aea
AF		 4004 env->hflags2 |= HF2_GIF_MASK;
4005
4006 cpu_x86_update_cr0(env, 0x60000010);
4007 env->a20_mask = ~0x0;
4008 env->smbase = 0x30000;
e13713db 4009 env->msr_smi_count = 0;
c1958aea
AF		 4010
4011 env->idt.limit = 0xffff;
4012 env->gdt.limit = 0xffff;
4013 env->ldt.limit = 0xffff;
4014 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4015 env->tr.limit = 0xffff;
4016 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4017
4018 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4019 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4020 DESC_R_MASK | DESC_A_MASK);
4021 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4022 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4023 DESC_A_MASK);
4024 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4025 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4026 DESC_A_MASK);
4027 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4028 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4029 DESC_A_MASK);
4030 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4031 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4032 DESC_A_MASK);
4033 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4034 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4035 DESC_A_MASK);
4036
4037 env->eip = 0xfff0;
4038 env->regs[R_EDX] = env->cpuid_version;
4039
4040 env->eflags = 0x2;
4041
4042 /* FPU init */
4043 for (i = 0; i < 8; i++) {
4044 env->fptags[i] = 1;
4045 }
5bde1407 4046 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 4047
4048 env->mxcsr = 0x1f80;
a114d25d
RH		 4049 /* All units are in INIT state. */
4050 env->xstate_bv = 0;
c1958aea
AF		 4051
4052 env->pat = 0x0007040600070406ULL;
4053 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4054
4055 memset(env->dr, 0, sizeof(env->dr));
4056 env->dr[6] = DR6_FIXED_1;
4057 env->dr[7] = DR7_FIXED_1;
b3310ab3 4058 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 4059 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 4060
a114d25d 4061 cr4 = 0;
cfc3b074 4062 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 4063
4064#ifdef CONFIG_USER_ONLY
4065 /* Enable all the features for user-mode. */
4066 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 4067 xcr0 |= XSTATE_SSE_MASK;
a114d25d 4068 }
0f70ed47
PB		 4069 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4070 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 4071 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 4072 xcr0 |= 1ull << i;
4073 }
a114d25d 4074 }
0f70ed47 4075
a114d25d
RH		 4076 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4077 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4078 }
07929f2a
RH		 4079 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4080 cr4 |= CR4_FSGSBASE_MASK;
4081 }
a114d25d
RH		 4082#endif
4083
4084 env->xcr0 = xcr0;
4085 cpu_x86_update_cr4(env, cr4);
0522604b 4086
9db2efd9
AW		 4087 /*
4088 * SDM 11.11.5 requires:
4089 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4090 * - IA32_MTRR_PHYSMASKn.V = 0
4091 * All other bits are undefined. For simplification, zero it all.
4092 */
4093 env->mtrr_deftype = 0;
4094 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4095 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4096
b7394c83
SAGDR		 4097 env->interrupt_injected = -1;
4098 env->exception_injected = -1;
4099 env->nmi_injected = false;
dd673288
IM		 4100#if !defined(CONFIG_USER_ONLY)
4101 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 4102 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 4103
259186a7 4104 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 4105
4106 if (kvm_enabled()) {
4107 kvm_arch_reset_vcpu(cpu);
4108 }
d6dcc558
SAGDR		 4109 else if (hvf_enabled()) {
4110 hvf_reset_vcpu(s);
4111 }
dd673288 4112#endif
5fd2087a
AF		 4113}
4114
dd673288
IM		 4115#ifndef CONFIG_USER_ONLY
4116bool cpu_is_bsp(X86CPU *cpu)
4117{
02e51483 4118 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 4119}
65dee380
IM		 4120
4121/* TODO: remove me, when reset over QOM tree is implemented */
4122static void x86_cpu_machine_reset_cb(void *opaque)
4123{
4124 X86CPU *cpu = opaque;
4125 cpu_reset(CPU(cpu));
4126}
dd673288
IM		 4127#endif
4128
de024815
AF		 4129static void mce_init(X86CPU *cpu)
4130{
4131 CPUX86State *cenv = &cpu->env;
4132 unsigned int bank;
4133
4134 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 4135 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 4136 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 4137 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4138 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 4139 cenv->mcg_ctl = ~(uint64_t)0;
4140 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4141 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4142 }
4143 }
4144}
4145
bdeec802 4146#ifndef CONFIG_USER_ONLY
2f114315 4147APICCommonClass *apic_get_class(void)
bdeec802 4148{
bdeec802
IM		 4149 const char *apic_type = "apic";
4150
d6dcc558 4151 /* TODO: in-kernel irqchip for hvf */
15eafc2e 4152 if (kvm_apic_in_kernel()) {
bdeec802
IM		 4153 apic_type = "kvm-apic";
4154 } else if (xen_enabled()) {
4155 apic_type = "xen-apic";
4156 }
4157
2f114315
RK		 4158 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4159}
4160
4161static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4162{
4163 APICCommonState *apic;
4164 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4165
4166 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 4167
6816b1b3
IM		 4168 object_property_add_child(OBJECT(cpu), "lapic",
4169 OBJECT(cpu->apic_state), &error_abort);
67e55caa 4170 object_unref(OBJECT(cpu->apic_state));
6816b1b3 4171
33d7a288 4172 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 4173 /* TODO: convert to link<> */
02e51483 4174 apic = APIC_COMMON(cpu->apic_state);
60671e58 4175 apic->cpu = cpu;
8d42d2d3 4176 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 4177}
4178
4179static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4180{
8d42d2d3
CF		 4181 APICCommonState *apic;
4182 static bool apic_mmio_map_once;
4183
02e51483 4184 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 4185 return;
4186 }
6e8e2651
MA		 4187 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4188 errp);
8d42d2d3
CF		 4189
4190 /* Map APIC MMIO area */
4191 apic = APIC_COMMON(cpu->apic_state);
4192 if (!apic_mmio_map_once) {
4193 memory_region_add_subregion_overlap(get_system_memory(),
4194 apic->apicbase &
4195 MSR_IA32_APICBASE_BASE,
4196 &apic->io_memory,
4197 0x1000);
4198 apic_mmio_map_once = true;
4199 }
bdeec802 4200}
f809c605
PB		 4201
4202static void x86_cpu_machine_done(Notifier *n, void *unused)
4203{
4204 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4205 MemoryRegion *smram =
4206 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4207
4208 if (smram) {
4209 cpu->smram = g_new(MemoryRegion, 1);
4210 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4211 smram, 0, 1ull << 32);
f8c45c65 4212 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 4213 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4214 }
4215}
d3c64d6a
IM		 4216#else
4217static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4218{
4219}
bdeec802
IM		 4220#endif
4221
11f6fee5
DDAG		 4222/* Note: Only safe for use on x86(-64) hosts */
4223static uint32_t x86_host_phys_bits(void)
4224{
4225 uint32_t eax;
4226 uint32_t host_phys_bits;
4227
4228 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4229 if (eax >= 0x80000008) {
4230 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4231 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4232 * at 23:16 that can specify a maximum physical address bits for
4233 * the guest that can override this value; but I've not seen
4234 * anything with that set.
4235 */
4236 host_phys_bits = eax & 0xff;
4237 } else {
4238 /* It's an odd 64 bit machine that doesn't have the leaf for
4239 * physical address bits; fall back to 36 that's most older
4240 * Intel.
4241 */
4242 host_phys_bits = 36;
4243 }
4244
4245 return host_phys_bits;
4246}
e48638fd 4247
c39c0edf
EH		 4248static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4249{
4250 if (*min < value) {
4251 *min = value;
4252 }
4253}
4254
4255/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4256static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4257{
4258 CPUX86State *env = &cpu->env;
4259 FeatureWordInfo *fi = &feature_word_info[w];
4260 uint32_t eax = fi->cpuid_eax;
4261 uint32_t region = eax & 0xF0000000;
4262
4263 if (!env->features[w]) {
4264 return;
4265 }
4266
4267 switch (region) {
4268 case 0x00000000:
4269 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4270 break;
4271 case 0x80000000:
4272 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4273 break;
4274 case 0xC0000000:
4275 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4276 break;
4277 }
4278}
4279
2ca8a8be
EH		 4280/* Calculate XSAVE components based on the configured CPU feature flags */
4281static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4282{
4283 CPUX86State *env = &cpu->env;
4284 int i;
96193c22 4285 uint64_t mask;
2ca8a8be
EH		 4286
4287 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4288 return;
4289 }
4290
e3c9022b
EH		 4291 mask = 0;
4292 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 4293 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4294 if (env->features[esa->feature] & esa->bits) {
96193c22 4295 mask |= (1ULL << i);
2ca8a8be
EH		 4296 }
4297 }
4298
96193c22
EH		 4299 env->features[FEAT_XSAVE_COMP_LO] = mask;
4300 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 4301}
4302
b8d834a0
EH		 4303/***** Steps involved on loading and filtering CPUID data
4304 *
4305 * When initializing and realizing a CPU object, the steps
4306 * involved in setting up CPUID data are:
4307 *
4308 * 1) Loading CPU model definition (X86CPUDefinition). This is
4309 * implemented by x86_cpu_load_def() and should be completely
4310 * transparent, as it is done automatically by instance_init.
4311 * No code should need to look at X86CPUDefinition structs
4312 * outside instance_init.
4313 *
4314 * 2) CPU expansion. This is done by realize before CPUID
4315 * filtering, and will make sure host/accelerator data is
4316 * loaded for CPU models that depend on host capabilities
4317 * (e.g. "host"). Done by x86_cpu_expand_features().
4318 *
4319 * 3) CPUID filtering. This initializes extra data related to
4320 * CPUID, and checks if the host supports all capabilities
4321 * required by the CPU. Runnability of a CPU model is
4322 * determined at this step. Done by x86_cpu_filter_features().
4323 *
4324 * Some operations don't require all steps to be performed.
4325 * More precisely:
4326 *
4327 * - CPU instance creation (instance_init) will run only CPU
4328 * model loading. CPU expansion can't run at instance_init-time
4329 * because host/accelerator data may be not available yet.
4330 * - CPU realization will perform both CPU model expansion and CPUID
4331 * filtering, and return an error in case one of them fails.
4332 * - query-cpu-definitions needs to run all 3 steps. It needs
4333 * to run CPUID filtering, as the 'unavailable-features'
4334 * field is set based on the filtering results.
4335 * - The query-cpu-model-expansion QMP command only needs to run
4336 * CPU model loading and CPU expansion. It should not filter
4337 * any CPUID data based on host capabilities.
4338 */
4339
4340/* Expand CPU configuration data, based on configured features
4341 * and host/accelerator capabilities when appropriate.
4342 */
4343static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 4344{
b34d12d1 4345 CPUX86State *env = &cpu->env;
dc15c051 4346 FeatureWord w;
2fae0d96 4347 GList *l;
41f3d4d6 4348 Error *local_err = NULL;
9886e834 4349
d4a606b3
EH		 4350 /*TODO: Now cpu->max_features doesn't overwrite features
4351 * set using QOM properties, and we can convert
dc15c051
IM		 4352 * plus_features & minus_features to global properties
4353 * inside x86_cpu_parse_featurestr() too.
4354 */
44bd8e53 4355 if (cpu->max_features) {
dc15c051 4356 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 4357 /* Override only features that weren't set explicitly
4358 * by the user.
4359 */
4360 env->features[w] |=
4361 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
0d914f39
EH		 4362 ~env->user_features[w] & \
4363 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 4364 }
4365 }
4366
2fae0d96
EH		 4367 for (l = plus_features; l; l = l->next) {
4368 const char *prop = l->data;
4369 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
4370 if (local_err) {
4371 goto out;
4372 }
4373 }
4374
4375 for (l = minus_features; l; l = l->next) {
4376 const char *prop = l->data;
4377 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
4378 if (local_err) {
4379 goto out;
4380 }
dc15c051
IM		 4381 }
4382
aec661de
EH		 4383 if (!kvm_enabled() || !cpu->expose_kvm) {
4384 env->features[FEAT_KVM] = 0;
4385 }
4386
2ca8a8be 4387 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 4388
4389 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
4390 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
4391 if (cpu->full_cpuid_auto_level) {
4392 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
4393 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
4394 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
4395 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
4396 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
4397 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
4398 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 4399 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 4400 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
4401 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
4402 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 4403 /* SVM requires CPUID[0x8000000A] */
4404 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
4405 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
4406 }
6cb8f2a6
BS		 4407
4408 /* SEV requires CPUID[0x8000001F] */
4409 if (sev_enabled()) {
4410 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
4411 }
c39c0edf
EH		 4412 }
4413
4414 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
4415 if (env->cpuid_level == UINT32_MAX) {
4416 env->cpuid_level = env->cpuid_min_level;
4417 }
4418 if (env->cpuid_xlevel == UINT32_MAX) {
4419 env->cpuid_xlevel = env->cpuid_min_xlevel;
4420 }
4421 if (env->cpuid_xlevel2 == UINT32_MAX) {
4422 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 4423 }
7a059953 4424
41f3d4d6
EH		 4425out:
4426 if (local_err != NULL) {
4427 error_propagate(errp, local_err);
4428 }
4429}
4430
b8d834a0
EH		 4431/*
4432 * Finishes initialization of CPUID data, filters CPU feature
4433 * words based on host availability of each feature.
4434 *
4435 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
4436 */
4437static int x86_cpu_filter_features(X86CPU *cpu)
4438{
4439 CPUX86State *env = &cpu->env;
4440 FeatureWord w;
4441 int rv = 0;
4442
4443 for (w = 0; w < FEATURE_WORDS; w++) {
4444 uint32_t host_feat =
4445 x86_cpu_get_supported_feature_word(w, false);
4446 uint32_t requested_features = env->features[w];
4447 env->features[w] &= host_feat;
4448 cpu->filtered_features[w] = requested_features & ~env->features[w];
4449 if (cpu->filtered_features[w]) {
4450 rv = 1;
4451 }
4452 }
4453
e37a5c7f
CP		 4454 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
4455 kvm_enabled()) {
4456 KVMState *s = CPU(cpu)->kvm_state;
4457 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
4458 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
4459 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
4460 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
4461 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
4462
4463 if (!eax_0 ||
4464 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
4465 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
4466 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
4467 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
4468 INTEL_PT_ADDR_RANGES_NUM) ||
4469 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96
LK		 4470 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
4471 (ecx_0 & INTEL_PT_IP_LIP)) {
e37a5c7f
CP		 4472 /*
4473 * Processor Trace capabilities aren't configurable, so if the
4474 * host can't emulate the capabilities we report on
4475 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
4476 */
4477 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
4478 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
4479 rv = 1;
4480 }
4481 }
4482
b8d834a0
EH		 4483 return rv;
4484}
4485
41f3d4d6
EH		 4486#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
4487 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
4488 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
4489#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
4490 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
4491 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
4492static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
4493{
4494 CPUState *cs = CPU(dev);
4495 X86CPU *cpu = X86_CPU(dev);
4496 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
4497 CPUX86State *env = &cpu->env;
4498 Error *local_err = NULL;
4499 static bool ht_warned;
4500
d6dcc558 4501 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
41f3d4d6
EH		 4502 char *name = x86_cpu_class_get_model_name(xcc);
4503 error_setg(&local_err, "CPU model '%s' requires KVM", name);
4504 g_free(name);
4505 goto out;
4506 }
4507
4508 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
4509 error_setg(errp, "apic-id property was not initialized properly");
4510 return;
4511 }
4512
b8d834a0 4513 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 4514 if (local_err) {
4515 goto out;
4516 }
4517
8ca30e86
EH		 4518 if (x86_cpu_filter_features(cpu) &&
4519 (cpu->check_cpuid || cpu->enforce_cpuid)) {
4520 x86_cpu_report_filtered_features(cpu);
4521 if (cpu->enforce_cpuid) {
4522 error_setg(&local_err,
d6dcc558 4523 accel_uses_host_cpuid() ?
8ca30e86
EH		 4524 "Host doesn't support requested features" :
4525 "TCG doesn't support requested features");
4526 goto out;
4527 }
9997cf7b
EH		 4528 }
4529
9b15cd9e
IM		 4530 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
4531 * CPUID[1].EDX.
4532 */
e48638fd 4533 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 4534 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
4535 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 4536 & CPUID_EXT2_AMD_ALIASES);
4537 }
4538
11f6fee5
DDAG		 4539 /* For 64bit systems think about the number of physical bits to present.
4540 * ideally this should be the same as the host; anything other than matching
4541 * the host can cause incorrect guest behaviour.
4542 * QEMU used to pick the magic value of 40 bits that corresponds to
4543 * consumer AMD devices but nothing else.
4544 */
af45907a 4545 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 4546 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 4547 uint32_t host_phys_bits = x86_host_phys_bits();
4548 static bool warned;
4549
4550 if (cpu->host_phys_bits) {
4551 /* The user asked for us to use the host physical bits */
4552 cpu->phys_bits = host_phys_bits;
4553 }
4554
4555 /* Print a warning if the user set it to a value that's not the
4556 * host value.
4557 */
4558 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
4559 !warned) {
3dc6f869
AF		 4560 warn_report("Host physical bits (%u)"
4561 " does not match phys-bits property (%u)",
4562 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 4563 warned = true;
4564 }
4565
4566 if (cpu->phys_bits &&
4567 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
4568 cpu->phys_bits < 32)) {
af45907a
DDAG		 4569 error_setg(errp, "phys-bits should be between 32 and %u "
4570 " (but is %u)",
4571 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
4572 return;
4573 }
4574 } else {
11f6fee5 4575 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 4576 error_setg(errp, "TCG only supports phys-bits=%u",
4577 TCG_PHYS_ADDR_BITS);
4578 return;
4579 }
4580 }
11f6fee5
DDAG		 4581 /* 0 means it was not explicitly set by the user (or by machine
4582 * compat_props or by the host code above). In this case, the default
4583 * is the value used by TCG (40).
4584 */
4585 if (cpu->phys_bits == 0) {
4586 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
4587 }
af45907a
DDAG		 4588 } else {
4589 /* For 32 bit systems don't use the user set value, but keep
4590 * phys_bits consistent with what we tell the guest.
4591 */
4592 if (cpu->phys_bits != 0) {
4593 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
4594 return;
4595 }
fefb41bf 4596
af45907a
DDAG		 4597 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
4598 cpu->phys_bits = 36;
4599 } else {
4600 cpu->phys_bits = 32;
4601 }
4602 }
ce5b1bbf
LV		 4603 cpu_exec_realizefn(cs, &local_err);
4604 if (local_err != NULL) {
4605 error_propagate(errp, local_err);
4606 return;
4607 }
42ecabaa 4608
65dee380
IM		 4609#ifndef CONFIG_USER_ONLY
4610 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 4611
0514ef2f 4612 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 4613 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 4614 if (local_err != NULL) {
4dc1f449 4615 goto out;
bdeec802
IM		 4616 }
4617 }
65dee380
IM		 4618#endif
4619
7a059953 4620 mce_init(cpu);
2001d0cd
PB		 4621
4622#ifndef CONFIG_USER_ONLY
4623 if (tcg_enabled()) {
f809c605 4624 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 4625 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 4626
4627 /* Outer container... */
4628 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 4629 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 4630
4631 /* ... with two regions inside: normal system memory with low
4632 * priority, and...
4633 */
4634 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
4635 get_system_memory(), 0, ~0ull);
4636 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
4637 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 4638
4639 cs->num_ases = 2;
80ceb07a
PX		 4640 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
4641 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 4642
4643 /* ... SMRAM with higher priority, linked from /machine/smram. */
4644 cpu->machine_done.notify = x86_cpu_machine_done;
4645 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 4646 }
4647#endif
4648
14a10fc3 4649 qemu_init_vcpu(cs);
d3c64d6a 4650
e48638fd
WH		 4651 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
4652 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
4653 * based on inputs (sockets,cores,threads), it is still better to gives
4654 * users a warning.
4655 *
4656 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
4657 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
4658 */
4659 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
4660 error_report("AMD CPU doesn't support hyperthreading. Please configure"
4661 " -smp options properly.");
4662 ht_warned = true;
4663 }
4664
d3c64d6a
IM		 4665 x86_cpu_apic_realize(cpu, &local_err);
4666 if (local_err != NULL) {
4667 goto out;
4668 }
14a10fc3 4669 cpu_reset(cs);
2b6f294c 4670
4dc1f449 4671 xcc->parent_realize(dev, &local_err);
2001d0cd 4672
4dc1f449
IM		 4673out:
4674 if (local_err != NULL) {
4675 error_propagate(errp, local_err);
4676 return;
4677 }
7a059953
AF		 4678}
4679
c884776e
IM		 4680static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
4681{
4682 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 4683 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
4684 Error *local_err = NULL;
c884776e
IM		 4685
4686#ifndef CONFIG_USER_ONLY
4687 cpu_remove_sync(CPU(dev));
4688 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
4689#endif
4690
4691 if (cpu->apic_state) {
4692 object_unparent(OBJECT(cpu->apic_state));
4693 cpu->apic_state = NULL;
4694 }
7bbc124e
LV		 4695
4696 xcc->parent_unrealize(dev, &local_err);
4697 if (local_err != NULL) {
4698 error_propagate(errp, local_err);
4699 return;
4700 }
c884776e
IM		 4701}
4702
38e5c119 4703typedef struct BitProperty {
a7b0ffac 4704 FeatureWord w;
38e5c119
EH		 4705 uint32_t mask;
4706} BitProperty;
4707
d7bce999
EB		 4708static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
4709 void *opaque, Error **errp)
38e5c119 4710{
a7b0ffac 4711 X86CPU *cpu = X86_CPU(obj);
38e5c119 4712 BitProperty *fp = opaque;
a7b0ffac
EH		 4713 uint32_t f = cpu->env.features[fp->w];
4714 bool value = (f & fp->mask) == fp->mask;
51e72bc1 4715 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 4716}
4717
d7bce999
EB		 4718static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
4719 void *opaque, Error **errp)
38e5c119
EH		 4720{
4721 DeviceState *dev = DEVICE(obj);
a7b0ffac 4722 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 4723 BitProperty *fp = opaque;
4724 Error *local_err = NULL;
4725 bool value;
4726
4727 if (dev->realized) {
4728 qdev_prop_set_after_realize(dev, name, errp);
4729 return;
4730 }
4731
51e72bc1 4732 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 4733 if (local_err) {
4734 error_propagate(errp, local_err);
4735 return;
4736 }
4737
4738 if (value) {
a7b0ffac 4739 cpu->env.features[fp->w] |= fp->mask;
38e5c119 4740 } else {
a7b0ffac 4741 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 4742 }
d4a606b3 4743 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 4744}
4745
4746static void x86_cpu_release_bit_prop(Object *obj, const char *name,
4747 void *opaque)
4748{
4749 BitProperty *prop = opaque;
4750 g_free(prop);
4751}
4752
4753/* Register a boolean property to get/set a single bit in a uint32_t field.
4754 *
4755 * The same property name can be registered multiple times to make it affect
4756 * multiple bits in the same FeatureWord. In that case, the getter will return
4757 * true only if all bits are set.
4758 */
4759static void x86_cpu_register_bit_prop(X86CPU *cpu,
4760 const char *prop_name,
a7b0ffac 4761 FeatureWord w,
38e5c119
EH		 4762 int bitnr)
4763{
4764 BitProperty *fp;
4765 ObjectProperty *op;
4766 uint32_t mask = (1UL << bitnr);
4767
4768 op = object_property_find(OBJECT(cpu), prop_name, NULL);
4769 if (op) {
4770 fp = op->opaque;
a7b0ffac 4771 assert(fp->w == w);
38e5c119
EH		 4772 fp->mask |= mask;
4773 } else {
4774 fp = g_new0(BitProperty, 1);
a7b0ffac 4775 fp->w = w;
38e5c119
EH		 4776 fp->mask = mask;
4777 object_property_add(OBJECT(cpu), prop_name, "bool",
4778 x86_cpu_get_bit_prop,
4779 x86_cpu_set_bit_prop,
4780 x86_cpu_release_bit_prop, fp, &error_abort);
4781 }
4782}
4783
4784static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
4785 FeatureWord w,
4786 int bitnr)
4787{
38e5c119 4788 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 4789 const char *name = fi->feat_names[bitnr];
38e5c119 4790
16d2fcaa 4791 if (!name) {
38e5c119
EH		 4792 return;
4793 }
4794
fc7dfd20
EH		 4795 /* Property names should use "-" instead of "_".
4796 * Old names containing underscores are registered as aliases
4797 * using object_property_add_alias()
4798 */
16d2fcaa
EH		 4799 assert(!strchr(name, '_'));
4800 /* aliases don't use "|" delimiters anymore, they are registered
4801 * manually using object_property_add_alias() */
4802 assert(!strchr(name, '|'));
a7b0ffac 4803 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 4804}
4805
d187e08d
AN		 4806static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
4807{
4808 X86CPU *cpu = X86_CPU(cs);
4809 CPUX86State *env = &cpu->env;
4810 GuestPanicInformation *panic_info = NULL;
4811
5e953812 4812 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 4813 panic_info = g_malloc0(sizeof(GuestPanicInformation));
4814
e8ed97a6 4815 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 4816
5e953812 4817 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 4818 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
4819 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
4820 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
4821 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
4822 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 4823 }
4824
4825 return panic_info;
4826}
4827static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
4828 const char *name, void *opaque,
4829 Error **errp)
4830{
4831 CPUState *cs = CPU(obj);
4832 GuestPanicInformation *panic_info;
4833
4834 if (!cs->crash_occurred) {
4835 error_setg(errp, "No crash occured");
4836 return;
4837 }
4838
4839 panic_info = x86_cpu_get_crash_info(cs);
4840 if (panic_info == NULL) {
4841 error_setg(errp, "No crash information");
4842 return;
4843 }
4844
4845 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
4846 errp);
4847 qapi_free_GuestPanicInformation(panic_info);
4848}
4849
de024815
AF		 4850static void x86_cpu_initfn(Object *obj)
4851{
55e5c285 4852 CPUState *cs = CPU(obj);
de024815 4853 X86CPU *cpu = X86_CPU(obj);
d940ee9b 4854 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 4855 CPUX86State *env = &cpu->env;
38e5c119 4856 FeatureWord w;
de024815 4857
c05efcb1 4858 cs->env_ptr = env;
71ad61d3
AF		 4859
4860 object_property_add(obj, "family", "int",
95b8519d 4861 x86_cpuid_version_get_family,
71ad61d3 4862 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 4863 object_property_add(obj, "model", "int",
67e30c83 4864 x86_cpuid_version_get_model,
c5291a4f 4865 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 4866 object_property_add(obj, "stepping", "int",
35112e41 4867 x86_cpuid_version_get_stepping,
036e2222 4868 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 4869 object_property_add_str(obj, "vendor",
4870 x86_cpuid_get_vendor,
4871 x86_cpuid_set_vendor, NULL);
938d4c25 4872 object_property_add_str(obj, "model-id",
63e886eb 4873 x86_cpuid_get_model_id,
938d4c25 4874 x86_cpuid_set_model_id, NULL);
89e48965
AF		 4875 object_property_add(obj, "tsc-frequency", "int",
4876 x86_cpuid_get_tsc_freq,
4877 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 4878 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
4879 x86_cpu_get_feature_words,
7e5292b5
EH		 4880 NULL, NULL, (void *)env->features, NULL);
4881 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
4882 x86_cpu_get_feature_words,
4883 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 4884
d187e08d
AN		 4885 object_property_add(obj, "crash-information", "GuestPanicInformation",
4886 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
4887
92067bf4 4888 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 4889
38e5c119
EH		 4890 for (w = 0; w < FEATURE_WORDS; w++) {
4891 int bitnr;
4892
4893 for (bitnr = 0; bitnr < 32; bitnr++) {
4894 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
4895 }
4896 }
4897
16d2fcaa
EH		 4898 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
4899 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
4900 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
4901 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
4902 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
4903 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
4904 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
4905
54b8dc7c
EH		 4906 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
4907 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
4908 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
4909 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
4910 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
4911 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
4912 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
4913 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
4914 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
4915 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
4916 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
4917 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
4918 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
4919 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
4920 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
4921 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
4922 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
4923 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
4924 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
4925 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
4926 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
4927
0bacd8b3
EH		 4928 if (xcc->cpu_def) {
4929 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
4930 }
de024815
AF		 4931}
4932
997395d3
IM		 4933static int64_t x86_cpu_get_arch_id(CPUState *cs)
4934{
4935 X86CPU *cpu = X86_CPU(cs);
997395d3 4936
7e72a45c 4937 return cpu->apic_id;
997395d3
IM		 4938}
4939
444d5590
AF		 4940static bool x86_cpu_get_paging_enabled(const CPUState *cs)
4941{
4942 X86CPU *cpu = X86_CPU(cs);
4943
4944 return cpu->env.cr[0] & CR0_PG_MASK;
4945}
4946
f45748f1
AF		 4947static void x86_cpu_set_pc(CPUState *cs, vaddr value)
4948{
4949 X86CPU *cpu = X86_CPU(cs);
4950
4951 cpu->env.eip = value;
4952}
4953
bdf7ae5b
AF		 4954static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
4955{
4956 X86CPU *cpu = X86_CPU(cs);
4957
4958 cpu->env.eip = tb->pc - tb->cs_base;
4959}
4960
8c2e1b00
AF		 4961static bool x86_cpu_has_work(CPUState *cs)
4962{
4963 X86CPU *cpu = X86_CPU(cs);
4964 CPUX86State *env = &cpu->env;
4965
6220e900
PD		 4966 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
4967 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 4968 (env->eflags & IF_MASK)) ||
4969 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
4970 CPU_INTERRUPT_INIT |
4971 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 4972 CPU_INTERRUPT_MCE)) ||
4973 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
4974 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 4975}
4976
f50f3dd5
RH		 4977static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
4978{
4979 X86CPU *cpu = X86_CPU(cs);
4980 CPUX86State *env = &cpu->env;
4981
4982 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
4983 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
4984 : bfd_mach_i386_i8086);
4985 info->print_insn = print_insn_i386;
b666d2a4
RH		 4986
4987 info->cap_arch = CS_ARCH_X86;
4988 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
4989 : env->hflags & HF_CS32_MASK ? CS_MODE_32
4990 : CS_MODE_16);
15fa1a0a
RH		 4991 info->cap_insn_unit = 1;
4992 info->cap_insn_split = 8;
f50f3dd5
RH		 4993}
4994
35b1b927
TW		 4995void x86_update_hflags(CPUX86State *env)
4996{
4997 uint32_t hflags;
4998#define HFLAG_COPY_MASK \
4999 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5000 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5001 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5002 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5003
5004 hflags = env->hflags & HFLAG_COPY_MASK;
5005 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5006 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5007 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5008 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5009 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5010
5011 if (env->cr[4] & CR4_OSFXSR_MASK) {
5012 hflags |= HF_OSFXSR_MASK;
5013 }
5014
5015 if (env->efer & MSR_EFER_LMA) {
5016 hflags |= HF_LMA_MASK;
5017 }
5018
5019 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5020 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5021 } else {
5022 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5023 (DESC_B_SHIFT - HF_CS32_SHIFT);
5024 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5025 (DESC_B_SHIFT - HF_SS32_SHIFT);
5026 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5027 !(hflags & HF_CS32_MASK)) {
5028 hflags |= HF_ADDSEG_MASK;
5029 } else {
5030 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5031 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5032 }
5033 }
5034 env->hflags = hflags;
5035}
5036
9337e3b6 5037static Property x86_cpu_properties[] = {
2da00e31
IM		 5038#ifdef CONFIG_USER_ONLY
5039 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5040 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 5041 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5042 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5043 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 5044#else
5045 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 5046 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5047 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5048 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 5049#endif
15f8b142 5050 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 5051 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 5052 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 5053 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 5054 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 5055 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 5056 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 5057 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 5058 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 5059 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 5060 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 5061 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
9445597b 5062 DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
ba6a4fd9 5063 DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment, false),
15e41345 5064 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 5065 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 5066 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 5067 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 5068 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 5069 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 5070 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5071 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5072 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5073 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5074 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5075 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5076 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 5077 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 5078 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 5079 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 5080 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 5081 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5082 false),
0b564e6f 5083 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 5084 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
6c69dfb6
GA		 5085
5086 /*
5087 * From "Requirements for Implementing the Microsoft
5088 * Hypervisor Interface":
5089 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5090 *
5091 * "Starting with Windows Server 2012 and Windows 8, if
5092 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5093 * the hypervisor imposes no specific limit to the number of VPs.
5094 * In this case, Windows Server 2012 guest VMs may use more than
5095 * 64 VPs, up to the maximum supported number of processors applicable
5096 * to the specific Windows version being used."
5097 */
5098 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9337e3b6
EH		 5099 DEFINE_PROP_END_OF_LIST()
5100};
5101
5fd2087a
AF		 5102static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5103{
5104 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5105 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 5106 DeviceClass *dc = DEVICE_CLASS(oc);
5107
bf853881
PMD		 5108 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5109 &xcc->parent_realize);
5110 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5111 &xcc->parent_unrealize);
9337e3b6 5112 dc->props = x86_cpu_properties;
5fd2087a
AF		 5113
5114 xcc->parent_reset = cc->reset;
5115 cc->reset = x86_cpu_reset;
91b1df8c 5116 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 5117
500050d1 5118 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 5119 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 5120 cc->has_work = x86_cpu_has_work;
79c664f6 5121#ifdef CONFIG_TCG
97a8ea5a 5122 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 5123 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 5124#endif
878096ee 5125 cc->dump_state = x86_cpu_dump_state;
c86f106b 5126 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 5127 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 5128 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 5129 cc->gdb_read_register = x86_cpu_gdb_read_register;
5130 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 5131 cc->get_arch_id = x86_cpu_get_arch_id;
5132 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 5133#ifdef CONFIG_USER_ONLY
5134 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
5135#else
f8c45c65 5136 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 5137 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 5138 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 5139 cc->write_elf64_note = x86_cpu_write_elf64_note;
5140 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5141 cc->write_elf32_note = x86_cpu_write_elf32_note;
5142 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 5143 cc->vmsd = &vmstate_x86_cpu;
c72bf468 5144#endif
00fcd100
AB		 5145 cc->gdb_arch_name = x86_gdb_arch_name;
5146#ifdef TARGET_X86_64
b8158192
AB		 5147 cc->gdb_core_xml_file = "i386-64bit.xml";
5148 cc->gdb_num_core_regs = 57;
00fcd100 5149#else
b8158192
AB		 5150 cc->gdb_core_xml_file = "i386-32bit.xml";
5151 cc->gdb_num_core_regs = 41;
00fcd100 5152#endif
79c664f6 5153#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 5154 cc->debug_excp_handler = breakpoint_handler;
5155#endif
374e0cd4
RH		 5156 cc->cpu_exec_enter = x86_cpu_exec_enter;
5157 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 5158#ifdef CONFIG_TCG
55c3ceef 5159 cc->tcg_initialize = tcg_x86_init;
74d7fc7f 5160#endif
f50f3dd5 5161 cc->disas_set_info = x86_disas_set_info;
4c315c27 5162
e90f2a8c 5163 dc->user_creatable = true;
5fd2087a
AF		 5164}
5165
5166static const TypeInfo x86_cpu_type_info = {
5167 .name = TYPE_X86_CPU,
5168 .parent = TYPE_CPU,
5169 .instance_size = sizeof(X86CPU),
de024815 5170 .instance_init = x86_cpu_initfn,
d940ee9b 5171 .abstract = true,
5fd2087a
AF		 5172 .class_size = sizeof(X86CPUClass),
5173 .class_init = x86_cpu_common_class_init,
5174};
5175
5adbed30
EH		 5176
5177/* "base" CPU model, used by query-cpu-model-expansion */
5178static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
5179{
5180 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5181
5182 xcc->static_model = true;
5183 xcc->migration_safe = true;
5184 xcc->model_description = "base CPU model type with no features enabled";
5185 xcc->ordering = 8;
5186}
5187
5188static const TypeInfo x86_base_cpu_type_info = {
5189 .name = X86_CPU_TYPE_NAME("base"),
5190 .parent = TYPE_X86_CPU,
5191 .class_init = x86_cpu_base_class_init,
5192};
5193
5fd2087a
AF		 5194static void x86_cpu_register_types(void)
5195{
d940ee9b
EH		 5196 int i;
5197
5fd2087a 5198 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 5199 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
5200 x86_register_cpudef_type(&builtin_x86_defs[i]);
5201 }
c62f2630 5202 type_register_static(&max_x86_cpu_type_info);
5adbed30 5203 type_register_static(&x86_base_cpu_type_info);
d6dcc558 5204#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 5205 type_register_static(&host_x86_cpu_type_info);
5206#endif
5fd2087a
AF		 5207}
5208
5209type_init(x86_cpu_register_types)
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