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i386: Add new model of Cascadelake-Server
[mirror_qemu.git] / target / i386 / cpu.c
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c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
631be321 23#include "qemu/bitops.h"
c6dc6f63
AP		 24
25#include "cpu.h"
63c91552 26#include "exec/exec-all.h"
9c17d615 27#include "sysemu/kvm.h"
d6dcc558 28#include "sysemu/hvf.h"
8932cfdf 29#include "sysemu/cpus.h"
50a2c6e5 30#include "kvm_i386.h"
6cb8f2a6 31#include "sev_i386.h"
c6dc6f63 32
d49b6836 33#include "qemu/error-report.h"
1de7afc9
PB		 34#include "qemu/option.h"
35#include "qemu/config-file.h"
e688df6b 36#include "qapi/error.h"
112ed241
MA		 37#include "qapi/qapi-visit-misc.h"
38#include "qapi/qapi-visit-run-state.h"
452fcdbc 39#include "qapi/qmp/qdict.h"
7b1b5d19 40#include "qapi/qmp/qerror.h"
7b1b5d19 41#include "qapi/visitor.h"
f99fd7ca 42#include "qom/qom-qobject.h"
9c17d615 43#include "sysemu/arch_init.h"
71ad61d3 44
1814eab6 45#include "standard-headers/asm-x86/kvm_para.h"
65dee380 46
9c17d615 47#include "sysemu/sysemu.h"
53a89e26 48#include "hw/qdev-properties.h"
5232d00a 49#include "hw/i386/topology.h"
bdeec802 50#ifndef CONFIG_USER_ONLY
2001d0cd 51#include "exec/address-spaces.h"
741da0d3 52#include "hw/hw.h"
0d09e41a 53#include "hw/xen/xen.h"
0d09e41a 54#include "hw/i386/apic_internal.h"
bdeec802
IM		 55#endif
56
b666d2a4
RH		 57#include "disas/capstone.h"
58
7e3482f8
EH		 59/* Helpers for building CPUID[2] descriptors: */
60
61struct CPUID2CacheDescriptorInfo {
62 enum CacheType type;
63 int level;
64 int size;
65 int line_size;
66 int associativity;
67};
5e891bf8 68
7e3482f8
EH		 69/*
70 * Known CPUID 2 cache descriptors.
71 * From Intel SDM Volume 2A, CPUID instruction
72 */
73struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 74 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 75 .associativity = 4, .line_size = 32, },
5f00335a 76 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 77 .associativity = 4, .line_size = 32, },
5f00335a 78 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 79 .associativity = 4, .line_size = 64, },
5f00335a 80 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 81 .associativity = 2, .line_size = 32, },
5f00335a 82 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 83 .associativity = 4, .line_size = 32, },
5f00335a 84 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 85 .associativity = 4, .line_size = 64, },
5f00335a 86 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 87 .associativity = 6, .line_size = 64, },
5f00335a 88 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 89 .associativity = 2, .line_size = 64, },
5f00335a 90 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 91 .associativity = 8, .line_size = 64, },
92 /* lines per sector is not supported cpuid2_cache_descriptor(),
93 * so descriptors 0x22, 0x23 are not included
94 */
5f00335a 95 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 96 .associativity = 16, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x25, 0x20 are not included
99 */
5f00335a 100 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 101 .associativity = 8, .line_size = 64, },
5f00335a 102 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 103 .associativity = 8, .line_size = 64, },
5f00335a 104 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 105 .associativity = 4, .line_size = 32, },
5f00335a 106 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 107 .associativity = 4, .line_size = 32, },
5f00335a 108 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 109 .associativity = 4, .line_size = 32, },
5f00335a 110 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 111 .associativity = 4, .line_size = 32, },
5f00335a 112 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 113 .associativity = 4, .line_size = 32, },
5f00335a 114 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 115 .associativity = 4, .line_size = 64, },
5f00335a 116 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 117 .associativity = 8, .line_size = 64, },
5f00335a 118 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 119 .associativity = 12, .line_size = 64, },
120 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 121 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 122 .associativity = 12, .line_size = 64, },
5f00335a 123 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 124 .associativity = 16, .line_size = 64, },
5f00335a 125 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 126 .associativity = 12, .line_size = 64, },
5f00335a 127 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 128 .associativity = 16, .line_size = 64, },
5f00335a 129 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 130 .associativity = 24, .line_size = 64, },
5f00335a 131 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 132 .associativity = 8, .line_size = 64, },
5f00335a 133 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 134 .associativity = 4, .line_size = 64, },
5f00335a 135 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 136 .associativity = 4, .line_size = 64, },
5f00335a 137 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 138 .associativity = 4, .line_size = 64, },
5f00335a 139 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 140 .associativity = 4, .line_size = 64, },
141 /* lines per sector is not supported cpuid2_cache_descriptor(),
142 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
143 */
5f00335a 144 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 145 .associativity = 8, .line_size = 64, },
5f00335a 146 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 147 .associativity = 2, .line_size = 64, },
5f00335a 148 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 149 .associativity = 8, .line_size = 64, },
5f00335a 150 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 151 .associativity = 8, .line_size = 32, },
5f00335a 152 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 153 .associativity = 8, .line_size = 32, },
5f00335a 154 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 155 .associativity = 8, .line_size = 32, },
5f00335a 156 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 157 .associativity = 8, .line_size = 32, },
5f00335a 158 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 159 .associativity = 4, .line_size = 64, },
5f00335a 160 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 161 .associativity = 8, .line_size = 64, },
5f00335a 162 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 163 .associativity = 4, .line_size = 64, },
5f00335a 164 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 165 .associativity = 4, .line_size = 64, },
5f00335a 166 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 167 .associativity = 4, .line_size = 64, },
5f00335a 168 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 169 .associativity = 8, .line_size = 64, },
5f00335a 170 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 171 .associativity = 8, .line_size = 64, },
5f00335a 172 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 173 .associativity = 8, .line_size = 64, },
5f00335a 174 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 175 .associativity = 12, .line_size = 64, },
5f00335a 176 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 177 .associativity = 12, .line_size = 64, },
5f00335a 178 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 179 .associativity = 12, .line_size = 64, },
5f00335a 180 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 181 .associativity = 16, .line_size = 64, },
5f00335a 182 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 183 .associativity = 16, .line_size = 64, },
5f00335a 184 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 185 .associativity = 16, .line_size = 64, },
5f00335a 186 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 187 .associativity = 24, .line_size = 64, },
5f00335a 188 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 189 .associativity = 24, .line_size = 64, },
5f00335a 190 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 191 .associativity = 24, .line_size = 64, },
192};
193
194/*
195 * "CPUID leaf 2 does not report cache descriptor information,
196 * use CPUID leaf 4 to query cache parameters"
197 */
198#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 199
7e3482f8
EH		 200/*
201 * Return a CPUID 2 cache descriptor for a given cache.
202 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
203 */
204static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
205{
206 int i;
207
208 assert(cache->size > 0);
209 assert(cache->level > 0);
210 assert(cache->line_size > 0);
211 assert(cache->associativity > 0);
212 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
213 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
214 if (d->level == cache->level && d->type == cache->type &&
215 d->size == cache->size && d->line_size == cache->line_size &&
216 d->associativity == cache->associativity) {
217 return i;
218 }
219 }
5e891bf8 220
7e3482f8
EH		 221 return CACHE_DESCRIPTOR_UNAVAILABLE;
222}
5e891bf8
EH		 223
224/* CPUID Leaf 4 constants: */
225
226/* EAX: */
7e3482f8
EH		 227#define CACHE_TYPE_D 1
228#define CACHE_TYPE_I 2
229#define CACHE_TYPE_UNIFIED 3
5e891bf8 230
7e3482f8 231#define CACHE_LEVEL(l) (l << 5)
5e891bf8 232
7e3482f8 233#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 234
235/* EDX: */
7e3482f8
EH		 236#define CACHE_NO_INVD_SHARING (1 << 0)
237#define CACHE_INCLUSIVE (1 << 1)
238#define CACHE_COMPLEX_IDX (1 << 2)
239
240/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 241#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
242 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
243 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
244 0 /* Invalid value */)
7e3482f8
EH		 245
246
247/* Encode cache info for CPUID[4] */
248static void encode_cache_cpuid4(CPUCacheInfo *cache,
249 int num_apic_ids, int num_cores,
250 uint32_t *eax, uint32_t *ebx,
251 uint32_t *ecx, uint32_t *edx)
252{
253 assert(cache->size == cache->line_size * cache->associativity *
254 cache->partitions * cache->sets);
255
256 assert(num_apic_ids > 0);
257 *eax = CACHE_TYPE(cache->type) |
258 CACHE_LEVEL(cache->level) |
259 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
260 ((num_cores - 1) << 26) |
261 ((num_apic_ids - 1) << 14);
262
263 assert(cache->line_size > 0);
264 assert(cache->partitions > 0);
265 assert(cache->associativity > 0);
266 /* We don't implement fully-associative caches */
267 assert(cache->associativity < cache->sets);
268 *ebx = (cache->line_size - 1) |
269 ((cache->partitions - 1) << 12) |
270 ((cache->associativity - 1) << 22);
271
272 assert(cache->sets > 0);
273 *ecx = cache->sets - 1;
274
275 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
276 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
277 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
278}
279
280/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
281static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
282{
283 assert(cache->size % 1024 == 0);
284 assert(cache->lines_per_tag > 0);
285 assert(cache->associativity > 0);
286 assert(cache->line_size > 0);
287 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
288 (cache->lines_per_tag << 8) | (cache->line_size);
289}
5e891bf8
EH		 290
291#define ASSOC_FULL 0xFF
292
293/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
294#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
295 a == 2 ? 0x2 : \
296 a == 4 ? 0x4 : \
297 a == 8 ? 0x6 : \
298 a == 16 ? 0x8 : \
299 a == 32 ? 0xA : \
300 a == 48 ? 0xB : \
301 a == 64 ? 0xC : \
302 a == 96 ? 0xD : \
303 a == 128 ? 0xE : \
304 a == ASSOC_FULL ? 0xF : \
305 0 /* invalid value */)
306
7e3482f8
EH		 307/*
308 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
309 * @l3 can be NULL.
310 */
311static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
312 CPUCacheInfo *l3,
313 uint32_t *ecx, uint32_t *edx)
314{
315 assert(l2->size % 1024 == 0);
316 assert(l2->associativity > 0);
317 assert(l2->lines_per_tag > 0);
318 assert(l2->line_size > 0);
319 *ecx = ((l2->size / 1024) << 16) |
320 (AMD_ENC_ASSOC(l2->associativity) << 12) |
321 (l2->lines_per_tag << 8) | (l2->line_size);
322
323 if (l3) {
324 assert(l3->size % (512 * 1024) == 0);
325 assert(l3->associativity > 0);
326 assert(l3->lines_per_tag > 0);
327 assert(l3->line_size > 0);
328 *edx = ((l3->size / (512 * 1024)) << 18) |
329 (AMD_ENC_ASSOC(l3->associativity) << 12) |
330 (l3->lines_per_tag << 8) | (l3->line_size);
331 } else {
332 *edx = 0;
333 }
334}
5e891bf8 335
8f4202fb
BM		 336/*
337 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
338 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
339 * Define the constants to build the cpu topology. Right now, TOPOEXT
340 * feature is enabled only on EPYC. So, these constants are based on
341 * EPYC supported configurations. We may need to handle the cases if
342 * these values change in future.
343 */
344/* Maximum core complexes in a node */
345#define MAX_CCX 2
346/* Maximum cores in a core complex */
347#define MAX_CORES_IN_CCX 4
348/* Maximum cores in a node */
349#define MAX_CORES_IN_NODE 8
350/* Maximum nodes in a socket */
351#define MAX_NODES_PER_SOCKET 4
352
353/*
354 * Figure out the number of nodes required to build this config.
355 * Max cores in a node is 8
356 */
357static int nodes_in_socket(int nr_cores)
358{
359 int nodes;
360
361 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
362
363 /* Hardware does not support config with 3 nodes, return 4 in that case */
364 return (nodes == 3) ? 4 : nodes;
365}
366
367/*
368 * Decide the number of cores in a core complex with the given nr_cores using
369 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
370 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
371 * L3 cache is shared across all cores in a core complex. So, this will also
372 * tell us how many cores are sharing the L3 cache.
373 */
374static int cores_in_core_complex(int nr_cores)
375{
376 int nodes;
377
378 /* Check if we can fit all the cores in one core complex */
379 if (nr_cores <= MAX_CORES_IN_CCX) {
380 return nr_cores;
381 }
382 /* Get the number of nodes required to build this config */
383 nodes = nodes_in_socket(nr_cores);
384
385 /*
386 * Divide the cores accros all the core complexes
387 * Return rounded up value
388 */
389 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
390}
391
392/* Encode cache info for CPUID[8000001D] */
393static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
394 uint32_t *eax, uint32_t *ebx,
395 uint32_t *ecx, uint32_t *edx)
396{
397 uint32_t l3_cores;
398 assert(cache->size == cache->line_size * cache->associativity *
399 cache->partitions * cache->sets);
400
401 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
402 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
403
404 /* L3 is shared among multiple cores */
405 if (cache->level == 3) {
406 l3_cores = cores_in_core_complex(cs->nr_cores);
407 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
408 } else {
409 *eax |= ((cs->nr_threads - 1) << 14);
410 }
411
412 assert(cache->line_size > 0);
413 assert(cache->partitions > 0);
414 assert(cache->associativity > 0);
415 /* We don't implement fully-associative caches */
416 assert(cache->associativity < cache->sets);
417 *ebx = (cache->line_size - 1) |
418 ((cache->partitions - 1) << 12) |
419 ((cache->associativity - 1) << 22);
420
421 assert(cache->sets > 0);
422 *ecx = cache->sets - 1;
423
424 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
425 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
426 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
427}
428
ed78467a
BM		 429/* Data structure to hold the configuration info for a given core index */
430struct core_topology {
431 /* core complex id of the current core index */
432 int ccx_id;
433 /*
434 * Adjusted core index for this core in the topology
435 * This can be 0,1,2,3 with max 4 cores in a core complex
436 */
437 int core_id;
438 /* Node id for this core index */
439 int node_id;
440 /* Number of nodes in this config */
441 int num_nodes;
442};
443
444/*
445 * Build the configuration closely match the EPYC hardware. Using the EPYC
446 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
447 * right now. This could change in future.
448 * nr_cores : Total number of cores in the config
449 * core_id : Core index of the current CPU
450 * topo : Data structure to hold all the config info for this core index
451 */
452static void build_core_topology(int nr_cores, int core_id,
453 struct core_topology *topo)
454{
455 int nodes, cores_in_ccx;
456
457 /* First get the number of nodes required */
458 nodes = nodes_in_socket(nr_cores);
459
460 cores_in_ccx = cores_in_core_complex(nr_cores);
461
462 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
463 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
464 topo->core_id = core_id % cores_in_ccx;
465 topo->num_nodes = nodes;
466}
467
468/* Encode cache info for CPUID[8000001E] */
469static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
470 uint32_t *eax, uint32_t *ebx,
471 uint32_t *ecx, uint32_t *edx)
472{
473 struct core_topology topo = {0};
631be321
BM		 474 unsigned long nodes;
475 int shift;
ed78467a
BM		 476
477 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
478 *eax = cpu->apic_id;
479 /*
480 * CPUID_Fn8000001E_EBX
481 * 31:16 Reserved
482 * 15:8 Threads per core (The number of threads per core is
483 * Threads per core + 1)
484 * 7:0 Core id (see bit decoding below)
485 * SMT:
486 * 4:3 node id
487 * 2 Core complex id
488 * 1:0 Core id
489 * Non SMT:
490 * 5:4 node id
491 * 3 Core complex id
492 * 1:0 Core id
493 */
494 if (cs->nr_threads - 1) {
495 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
496 (topo.ccx_id << 2) | topo.core_id;
497 } else {
498 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
499 }
500 /*
501 * CPUID_Fn8000001E_ECX
502 * 31:11 Reserved
503 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
504 * 7:0 Node id (see bit decoding below)
505 * 2 Socket id
506 * 1:0 Node id
507 */
631be321
BM		 508 if (topo.num_nodes <= 4) {
509 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
510 topo.node_id;
511 } else {
512 /*
513 * Node id fix up. Actual hardware supports up to 4 nodes. But with
514 * more than 32 cores, we may end up with more than 4 nodes.
515 * Node id is a combination of socket id and node id. Only requirement
516 * here is that this number should be unique accross the system.
517 * Shift the socket id to accommodate more nodes. We dont expect both
518 * socket id and node id to be big number at the same time. This is not
519 * an ideal config but we need to to support it. Max nodes we can have
520 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
521 * 5 bits for nodes. Find the left most set bit to represent the total
522 * number of nodes. find_last_bit returns last set bit(0 based). Left
523 * shift(+1) the socket id to represent all the nodes.
524 */
525 nodes = topo.num_nodes - 1;
526 shift = find_last_bit(&nodes, 8);
527 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
528 topo.node_id;
529 }
ed78467a
BM		 530 *edx = 0;
531}
532
ab8f992e
BM		 533/*
534 * Definitions of the hardcoded cache entries we expose:
535 * These are legacy cache values. If there is a need to change any
536 * of these values please use builtin_x86_defs
537 */
5e891bf8
EH		 538
539/* L1 data cache: */
ab8f992e 540static CPUCacheInfo legacy_l1d_cache = {
5f00335a 541 .type = DATA_CACHE,
7e3482f8
EH		 542 .level = 1,
543 .size = 32 * KiB,
544 .self_init = 1,
545 .line_size = 64,
546 .associativity = 8,
547 .sets = 64,
548 .partitions = 1,
549 .no_invd_sharing = true,
550};
551
5e891bf8 552/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 553static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 554 .type = DATA_CACHE,
7e3482f8
EH		 555 .level = 1,
556 .size = 64 * KiB,
557 .self_init = 1,
558 .line_size = 64,
559 .associativity = 2,
560 .sets = 512,
561 .partitions = 1,
562 .lines_per_tag = 1,
563 .no_invd_sharing = true,
564};
5e891bf8
EH		 565
566/* L1 instruction cache: */
ab8f992e 567static CPUCacheInfo legacy_l1i_cache = {
5f00335a 568 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 569 .level = 1,
570 .size = 32 * KiB,
571 .self_init = 1,
572 .line_size = 64,
573 .associativity = 8,
574 .sets = 64,
575 .partitions = 1,
576 .no_invd_sharing = true,
577};
578
5e891bf8 579/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 580static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 581 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 582 .level = 1,
583 .size = 64 * KiB,
584 .self_init = 1,
585 .line_size = 64,
586 .associativity = 2,
587 .sets = 512,
588 .partitions = 1,
589 .lines_per_tag = 1,
590 .no_invd_sharing = true,
591};
5e891bf8
EH		 592
593/* Level 2 unified cache: */
ab8f992e 594static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 595 .type = UNIFIED_CACHE,
596 .level = 2,
597 .size = 4 * MiB,
598 .self_init = 1,
599 .line_size = 64,
600 .associativity = 16,
601 .sets = 4096,
602 .partitions = 1,
603 .no_invd_sharing = true,
604};
605
5e891bf8 606/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 607static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 608 .type = UNIFIED_CACHE,
609 .level = 2,
610 .size = 2 * MiB,
611 .line_size = 64,
612 .associativity = 8,
613};
614
615
5e891bf8 616/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 617static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 618 .type = UNIFIED_CACHE,
619 .level = 2,
620 .size = 512 * KiB,
621 .line_size = 64,
622 .lines_per_tag = 1,
623 .associativity = 16,
624 .sets = 512,
625 .partitions = 1,
626};
5e891bf8 627
14c985cf 628/* Level 3 unified cache: */
ab8f992e 629static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 630 .type = UNIFIED_CACHE,
631 .level = 3,
632 .size = 16 * MiB,
633 .line_size = 64,
634 .associativity = 16,
635 .sets = 16384,
636 .partitions = 1,
637 .lines_per_tag = 1,
638 .self_init = true,
639 .inclusive = true,
640 .complex_indexing = true,
641};
5e891bf8
EH		 642
643/* TLB definitions: */
644
645#define L1_DTLB_2M_ASSOC 1
646#define L1_DTLB_2M_ENTRIES 255
647#define L1_DTLB_4K_ASSOC 1
648#define L1_DTLB_4K_ENTRIES 255
649
650#define L1_ITLB_2M_ASSOC 1
651#define L1_ITLB_2M_ENTRIES 255
652#define L1_ITLB_4K_ASSOC 1
653#define L1_ITLB_4K_ENTRIES 255
654
655#define L2_DTLB_2M_ASSOC 0 /* disabled */
656#define L2_DTLB_2M_ENTRIES 0 /* disabled */
657#define L2_DTLB_4K_ASSOC 4
658#define L2_DTLB_4K_ENTRIES 512
659
660#define L2_ITLB_2M_ASSOC 0 /* disabled */
661#define L2_ITLB_2M_ENTRIES 0 /* disabled */
662#define L2_ITLB_4K_ASSOC 4
663#define L2_ITLB_4K_ENTRIES 512
664
e37a5c7f
CP		 665/* CPUID Leaf 0x14 constants: */
666#define INTEL_PT_MAX_SUBLEAF 0x1
667/*
668 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
669 * MSR can be accessed;
670 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
671 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
672 * of Intel PT MSRs across warm reset;
673 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
674 */
675#define INTEL_PT_MINIMAL_EBX 0xf
676/*
677 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
678 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
679 * accessed;
680 * bit[01]: ToPA tables can hold any number of output entries, up to the
681 * maximum allowed by the MaskOrTableOffset field of
682 * IA32_RTIT_OUTPUT_MASK_PTRS;
683 * bit[02]: Support Single-Range Output scheme;
684 */
685#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 686/* generated packets which contain IP payloads have LIP values */
687#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 688#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
689#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
690#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
691#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
692#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 693
99b88a17
IM		 694static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
695 uint32_t vendor2, uint32_t vendor3)
696{
697 int i;
698 for (i = 0; i < 4; i++) {
699 dst[i] = vendor1 >> (8 * i);
700 dst[i + 4] = vendor2 >> (8 * i);
701 dst[i + 8] = vendor3 >> (8 * i);
702 }
703 dst[CPUID_VENDOR_SZ] = '\0';
704}
705
621626ce
EH		 706#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
707#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
708 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
709#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
710 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
711 CPUID_PSE36 | CPUID_FXSR)
712#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
713#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
714 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
715 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
716 CPUID_PAE | CPUID_SEP | CPUID_APIC)
717
718#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
719 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
720 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
721 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 722 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 723 /* partly implemented:
724 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
725 /* missing:
726 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
727#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
728 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
729 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 730 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 731 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
732 /* missing:
733 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
734 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
735 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 736 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
737 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 738
739#ifdef TARGET_X86_64
740#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
741#else
742#define TCG_EXT2_X86_64_FEATURES 0
743#endif
744
745#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
746 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
747 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
748 TCG_EXT2_X86_64_FEATURES)
749#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
750 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
751#define TCG_EXT4_FEATURES 0
fe441054 752#define TCG_SVM_FEATURES CPUID_SVM_NPT
621626ce
EH		 753#define TCG_KVM_FEATURES 0
754#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 755 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
756 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 757 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
758 CPUID_7_0_EBX_ERMS)
621626ce 759 /* missing:
07929f2a 760 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 761 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 762 CPUID_7_0_EBX_RDSEED */
9ccb9784
EH		 763#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
764 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
6c7c3c21 765 CPUID_7_0_ECX_LA57)
95ea69fb 766#define TCG_7_0_EDX_FEATURES 0
303752a9 767#define TCG_APM_FEATURES 0
28b8e4d0 768#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 769#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
770 /* missing:
771 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 772
07585923
RH		 773typedef enum FeatureWordType {
774 CPUID_FEATURE_WORD,
775 MSR_FEATURE_WORD,
776} FeatureWordType;
777
5ef57876 778typedef struct FeatureWordInfo {
07585923 779 FeatureWordType type;
2d5312da
EH		 780 /* feature flags names are taken from "Intel Processor Identification and
781 * the CPUID Instruction" and AMD's "CPUID Specification".
782 * In cases of disagreement between feature naming conventions,
783 * aliases may be added.
784 */
785 const char *feat_names[32];
07585923
RH		 786 union {
787 /* If type==CPUID_FEATURE_WORD */
788 struct {
789 uint32_t eax; /* Input EAX for CPUID */
790 bool needs_ecx; /* CPUID instruction uses ECX as input */
791 uint32_t ecx; /* Input ECX value for CPUID */
792 int reg; /* output register (R_* constant) */
793 } cpuid;
794 /* If type==MSR_FEATURE_WORD */
795 struct {
796 uint32_t index;
797 struct { /*CPUID that enumerate this MSR*/
798 FeatureWord cpuid_class;
799 uint32_t cpuid_flag;
800 } cpuid_dep;
801 } msr;
802 };
37ce3522 803 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 804 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 805 uint32_t migratable_flags; /* Feature flags known to be migratable */
0d914f39
EH		 806 /* Features that shouldn't be auto-enabled by "-cpu host" */
807 uint32_t no_autoenable_flags;
5ef57876
EH		 808} FeatureWordInfo;
809
810static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 811 [FEAT_1_EDX] = {
07585923 812 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 813 .feat_names = {
814 "fpu", "vme", "de", "pse",
815 "tsc", "msr", "pae", "mce",
816 "cx8", "apic", NULL, "sep",
817 "mtrr", "pge", "mca", "cmov",
818 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
819 NULL, "ds" /* Intel dts */, "acpi", "mmx",
820 "fxsr", "sse", "sse2", "ss",
821 "ht" /* Intel htt */, "tm", "ia64", "pbe",
822 },
07585923 823 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 824 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 825 },
826 [FEAT_1_ECX] = {
07585923 827 .type = CPUID_FEATURE_WORD,
2d5312da 828 .feat_names = {
16d2fcaa 829 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 830 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 831 "tm2", "ssse3", "cid", NULL,
832 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 833 NULL, "pcid", "dca", "sse4.1",
834 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 835 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 836 "avx", "f16c", "rdrand", "hypervisor",
837 },
07585923 838 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 839 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 840 },
2d5312da
EH		 841 /* Feature names that are already defined on feature_name[] but
842 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
843 * names on feat_names below. They are copied automatically
844 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
845 */
bffd67b0 846 [FEAT_8000_0001_EDX] = {
07585923 847 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 848 .feat_names = {
849 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
850 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
851 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
852 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
853 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 854 "nx", NULL, "mmxext", NULL /* mmx */,
855 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
856 NULL, "lm", "3dnowext", "3dnow",
2d5312da 857 },
07585923 858 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 859 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 860 },
861 [FEAT_8000_0001_ECX] = {
07585923 862 .type = CPUID_FEATURE_WORD,
2d5312da 863 .feat_names = {
fc7dfd20 864 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 865 "cr8legacy", "abm", "sse4a", "misalignsse",
866 "3dnowprefetch", "osvw", "ibs", "xop",
867 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 868 "fma4", "tce", NULL, "nodeid-msr",
869 NULL, "tbm", "topoext", "perfctr-core",
870 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 871 NULL, NULL, NULL, NULL,
872 },
07585923 873 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 874 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 875 /*
876 * TOPOEXT is always allowed but can't be enabled blindly by
877 * "-cpu host", as it requires consistent cache topology info
878 * to be provided so it doesn't confuse guests.
879 */
880 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 881 },
89e49c8b 882 [FEAT_C000_0001_EDX] = {
07585923 883 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 884 .feat_names = {
885 NULL, NULL, "xstore", "xstore-en",
886 NULL, NULL, "xcrypt", "xcrypt-en",
887 "ace2", "ace2-en", "phe", "phe-en",
888 "pmm", "pmm-en", NULL, NULL,
889 NULL, NULL, NULL, NULL,
890 NULL, NULL, NULL, NULL,
891 NULL, NULL, NULL, NULL,
892 NULL, NULL, NULL, NULL,
893 },
07585923 894 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 895 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 896 },
bffd67b0 897 [FEAT_KVM] = {
07585923 898 .type = CPUID_FEATURE_WORD,
2d5312da 899 .feat_names = {
fc7dfd20
EH		 900 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
901 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 902 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
2d5312da
EH		 903 NULL, NULL, NULL, NULL,
904 NULL, NULL, NULL, NULL,
905 NULL, NULL, NULL, NULL,
906 "kvmclock-stable-bit", NULL, NULL, NULL,
907 NULL, NULL, NULL, NULL,
908 },
07585923 909 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 910 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 911 },
be777326 912 [FEAT_KVM_HINTS] = {
07585923 913 .type = CPUID_FEATURE_WORD,
be777326
WL		 914 .feat_names = {
915 "kvm-hint-dedicated", NULL, NULL, NULL,
916 NULL, NULL, NULL, NULL,
917 NULL, NULL, NULL, NULL,
918 NULL, NULL, NULL, NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 },
07585923 924 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 925 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 926 /*
927 * KVM hints aren't auto-enabled by -cpu host, they need to be
928 * explicitly enabled in the command-line.
929 */
930 .no_autoenable_flags = ~0U,
be777326 931 },
c35bd19a 932 [FEAT_HYPERV_EAX] = {
07585923 933 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 934 .feat_names = {
935 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
936 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
937 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
938 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
939 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
940 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
ba6a4fd9
VK		 941 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
942 NULL, NULL,
2d5312da
EH		 943 NULL, NULL, NULL, NULL,
944 NULL, NULL, NULL, NULL,
945 NULL, NULL, NULL, NULL,
946 NULL, NULL, NULL, NULL,
947 },
07585923 948 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
c35bd19a
EY		 949 },
950 [FEAT_HYPERV_EBX] = {
07585923 951 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 952 .feat_names = {
953 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
954 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
955 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
956 NULL /* hv_create_port */, NULL /* hv_connect_port */,
957 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
958 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
959 NULL, NULL,
960 NULL, NULL, NULL, NULL,
961 NULL, NULL, NULL, NULL,
962 NULL, NULL, NULL, NULL,
963 NULL, NULL, NULL, NULL,
964 },
07585923 965 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
c35bd19a
EY		 966 },
967 [FEAT_HYPERV_EDX] = {
07585923 968 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 969 .feat_names = {
970 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
971 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
972 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
973 NULL, NULL,
974 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
975 NULL, NULL, NULL, NULL,
976 NULL, NULL, NULL, NULL,
977 NULL, NULL, NULL, NULL,
978 NULL, NULL, NULL, NULL,
979 NULL, NULL, NULL, NULL,
980 },
07585923 981 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
c35bd19a 982 },
bffd67b0 983 [FEAT_SVM] = {
07585923 984 .type = CPUID_FEATURE_WORD,
2d5312da 985 .feat_names = {
fc7dfd20
EH		 986 "npt", "lbrv", "svm-lock", "nrip-save",
987 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
988 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 989 "pfthreshold", NULL, NULL, NULL,
990 NULL, NULL, NULL, NULL,
991 NULL, NULL, NULL, NULL,
992 NULL, NULL, NULL, NULL,
993 NULL, NULL, NULL, NULL,
994 },
07585923 995 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 996 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 997 },
998 [FEAT_7_0_EBX] = {
07585923 999 .type = CPUID_FEATURE_WORD,
2d5312da 1000 .feat_names = {
fc7dfd20 1001 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 1002 "hle", "avx2", NULL, "smep",
1003 "bmi2", "erms", "invpcid", "rtm",
1004 NULL, NULL, "mpx", NULL,
1005 "avx512f", "avx512dq", "rdseed", "adx",
1006 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 1007 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 1008 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 1009 },
07585923
RH		 1010 .cpuid = {
1011 .eax = 7,
1012 .needs_ecx = true, .ecx = 0,
1013 .reg = R_EBX,
1014 },
37ce3522 1015 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 1016 },
f74eefe0 1017 [FEAT_7_0_ECX] = {
07585923 1018 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1019 .feat_names = {
1020 NULL, "avx512vbmi", "umip", "pku",
9ccb9784 1021 NULL /* ospke */, NULL, "avx512vbmi2", NULL,
aff9e6e4
YZ		 1022 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1023 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 1024 "la57", NULL, NULL, NULL,
2d5312da 1025 NULL, NULL, "rdpid", NULL,
0da0fb06 1026 NULL, "cldemote", NULL, NULL,
2d5312da
EH		 1027 NULL, NULL, NULL, NULL,
1028 },
07585923
RH		 1029 .cpuid = {
1030 .eax = 7,
1031 .needs_ecx = true, .ecx = 0,
1032 .reg = R_ECX,
1033 },
f74eefe0
HH		 1034 .tcg_features = TCG_7_0_ECX_FEATURES,
1035 },
95ea69fb 1036 [FEAT_7_0_EDX] = {
07585923 1037 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 1038 .feat_names = {
1039 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1040 NULL, NULL, NULL, NULL,
1041 NULL, NULL, NULL, NULL,
1042 NULL, NULL, NULL, NULL,
5131dc43 1043 NULL, NULL, "pconfig", NULL,
95ea69fb 1044 NULL, NULL, NULL, NULL,
a2381f09 1045 NULL, NULL, "spec-ctrl", NULL,
3fc7c731 1046 NULL, "arch-capabilities", NULL, "ssbd",
95ea69fb 1047 },
07585923
RH		 1048 .cpuid = {
1049 .eax = 7,
1050 .needs_ecx = true, .ecx = 0,
1051 .reg = R_EDX,
1052 },
95ea69fb 1053 .tcg_features = TCG_7_0_EDX_FEATURES,
3fc7c731 1054 .unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES,
95ea69fb 1055 },
303752a9 1056 [FEAT_8000_0007_EDX] = {
07585923 1057 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1058 .feat_names = {
1059 NULL, NULL, NULL, NULL,
1060 NULL, NULL, NULL, NULL,
1061 "invtsc", NULL, NULL, NULL,
1062 NULL, NULL, NULL, NULL,
1063 NULL, NULL, NULL, NULL,
1064 NULL, NULL, NULL, NULL,
1065 NULL, NULL, NULL, NULL,
1066 NULL, NULL, NULL, NULL,
1067 },
07585923 1068 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 1069 .tcg_features = TCG_APM_FEATURES,
1070 .unmigratable_flags = CPUID_APM_INVTSC,
1071 },
1b3420e1 1072 [FEAT_8000_0008_EBX] = {
07585923 1073 .type = CPUID_FEATURE_WORD,
1b3420e1
EH		 1074 .feat_names = {
1075 NULL, NULL, NULL, NULL,
1076 NULL, NULL, NULL, NULL,
59a80a19 1077 NULL, "wbnoinvd", NULL, NULL,
1b3420e1
EH		 1078 "ibpb", NULL, NULL, NULL,
1079 NULL, NULL, NULL, NULL,
1080 NULL, NULL, NULL, NULL,
254790a9 1081 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 1082 NULL, NULL, NULL, NULL,
1083 },
07585923 1084 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 1085 .tcg_features = 0,
1086 .unmigratable_flags = 0,
1087 },
0bb0b2d2 1088 [FEAT_XSAVE] = {
07585923 1089 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1090 .feat_names = {
1091 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1092 NULL, NULL, NULL, NULL,
1093 NULL, NULL, NULL, NULL,
1094 NULL, NULL, NULL, NULL,
1095 NULL, NULL, NULL, NULL,
1096 NULL, NULL, NULL, NULL,
1097 NULL, NULL, NULL, NULL,
1098 NULL, NULL, NULL, NULL,
1099 },
07585923
RH		 1100 .cpuid = {
1101 .eax = 0xd,
1102 .needs_ecx = true, .ecx = 1,
1103 .reg = R_EAX,
1104 },
c9cfe8f9 1105 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 1106 },
28b8e4d0 1107 [FEAT_6_EAX] = {
07585923 1108 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1109 .feat_names = {
1110 NULL, NULL, "arat", NULL,
1111 NULL, NULL, NULL, NULL,
1112 NULL, NULL, NULL, NULL,
1113 NULL, NULL, NULL, NULL,
1114 NULL, NULL, NULL, NULL,
1115 NULL, NULL, NULL, NULL,
1116 NULL, NULL, NULL, NULL,
1117 NULL, NULL, NULL, NULL,
1118 },
07585923 1119 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 1120 .tcg_features = TCG_6_EAX_FEATURES,
1121 },
96193c22 1122 [FEAT_XSAVE_COMP_LO] = {
07585923
RH		 1123 .type = CPUID_FEATURE_WORD,
1124 .cpuid = {
1125 .eax = 0xD,
1126 .needs_ecx = true, .ecx = 0,
1127 .reg = R_EAX,
1128 },
96193c22 1129 .tcg_features = ~0U,
6fb2fff7
EH		 1130 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1131 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1132 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1133 XSTATE_PKRU_MASK,
96193c22
EH		 1134 },
1135 [FEAT_XSAVE_COMP_HI] = {
07585923
RH		 1136 .type = CPUID_FEATURE_WORD,
1137 .cpuid = {
1138 .eax = 0xD,
1139 .needs_ecx = true, .ecx = 0,
1140 .reg = R_EDX,
1141 },
96193c22
EH		 1142 .tcg_features = ~0U,
1143 },
d86f9636
RH		 1144 /*Below are MSR exposed features*/
1145 [FEAT_ARCH_CAPABILITIES] = {
1146 .type = MSR_FEATURE_WORD,
1147 .feat_names = {
1148 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1149 "ssb-no", NULL, NULL, NULL,
1150 NULL, NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 NULL, NULL, NULL, NULL,
1156 },
1157 .msr = {
1158 .index = MSR_IA32_ARCH_CAPABILITIES,
1159 .cpuid_dep = {
1160 FEAT_7_0_EDX,
1161 CPUID_7_0_EDX_ARCH_CAPABILITIES
1162 }
1163 },
1164 },
5ef57876
EH		 1165};
1166
8e8aba50
EH		 1167typedef struct X86RegisterInfo32 {
1168 /* Name of register */
1169 const char *name;
1170 /* QAPI enum value register */
1171 X86CPURegister32 qapi_enum;
1172} X86RegisterInfo32;
1173
1174#define REGISTER(reg) \
5d371f41 1175 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1176static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1177 REGISTER(EAX),
1178 REGISTER(ECX),
1179 REGISTER(EDX),
1180 REGISTER(EBX),
1181 REGISTER(ESP),
1182 REGISTER(EBP),
1183 REGISTER(ESI),
1184 REGISTER(EDI),
1185};
1186#undef REGISTER
1187
3f32bd21
RH		 1188typedef struct ExtSaveArea {
1189 uint32_t feature, bits;
1190 uint32_t offset, size;
1191} ExtSaveArea;
1192
1193static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 1194 [XSTATE_FP_BIT] = {
1195 /* x87 FP state component is always enabled if XSAVE is supported */
1196 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1197 /* x87 state is in the legacy region of the XSAVE area */
1198 .offset = 0,
1199 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1200 },
1201 [XSTATE_SSE_BIT] = {
1202 /* SSE state component is always enabled if XSAVE is supported */
1203 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1204 /* SSE state is in the legacy region of the XSAVE area */
1205 .offset = 0,
1206 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1207 },
cfc3b074
PB		 1208 [XSTATE_YMM_BIT] =
1209 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 1210 .offset = offsetof(X86XSaveArea, avx_state),
1211 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1212 [XSTATE_BNDREGS_BIT] =
1213 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1214 .offset = offsetof(X86XSaveArea, bndreg_state),
1215 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1216 [XSTATE_BNDCSR_BIT] =
1217 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1218 .offset = offsetof(X86XSaveArea, bndcsr_state),
1219 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1220 [XSTATE_OPMASK_BIT] =
1221 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1222 .offset = offsetof(X86XSaveArea, opmask_state),
1223 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1224 [XSTATE_ZMM_Hi256_BIT] =
1225 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1226 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1227 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1228 [XSTATE_Hi16_ZMM_BIT] =
1229 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1230 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1231 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1232 [XSTATE_PKRU_BIT] =
1233 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 1234 .offset = offsetof(X86XSaveArea, pkru_state),
1235 .size = sizeof(XSavePKRU) },
2560f19f 1236};
8e8aba50 1237
1fda6198
EH		 1238static uint32_t xsave_area_size(uint64_t mask)
1239{
1240 int i;
e3c9022b 1241 uint64_t ret = 0;
1fda6198 1242
e3c9022b 1243 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1244 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1245 if ((mask >> i) & 1) {
1246 ret = MAX(ret, esa->offset + esa->size);
1247 }
1248 }
1249 return ret;
1250}
1251
d6dcc558
SAGDR		 1252static inline bool accel_uses_host_cpuid(void)
1253{
1254 return kvm_enabled() || hvf_enabled();
1255}
1256
96193c22
EH		 1257static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1258{
1259 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1260 cpu->env.features[FEAT_XSAVE_COMP_LO];
1261}
1262
8b4beddc
EH		 1263const char *get_register_name_32(unsigned int reg)
1264{
31ccdde2 1265 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1266 return NULL;
1267 }
8e8aba50 1268 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1269}
1270
84f1b92f
EH		 1271/*
1272 * Returns the set of feature flags that are supported and migratable by
1273 * QEMU, for a given FeatureWord.
1274 */
1275static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1276{
1277 FeatureWordInfo *wi = &feature_word_info[w];
1278 uint32_t r = 0;
1279 int i;
1280
1281 for (i = 0; i < 32; i++) {
1282 uint32_t f = 1U << i;
6fb2fff7
EH		 1283
1284 /* If the feature name is known, it is implicitly considered migratable,
1285 * unless it is explicitly set in unmigratable_flags */
1286 if ((wi->migratable_flags & f) ||
1287 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1288 r |= f;
84f1b92f 1289 }
84f1b92f
EH		 1290 }
1291 return r;
1292}
1293
bb44e0d1
JK		 1294void host_cpuid(uint32_t function, uint32_t count,
1295 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1296{
a1fd24af
AL		 1297 uint32_t vec[4];
1298
1299#ifdef __x86_64__
1300 asm volatile("cpuid"
1301 : "=a"(vec[0]), "=b"(vec[1]),
1302 "=c"(vec[2]), "=d"(vec[3])
1303 : "0"(function), "c"(count) : "cc");
c1f41226 1304#elif defined(__i386__)
a1fd24af
AL		 1305 asm volatile("pusha \n\t"
1306 "cpuid \n\t"
1307 "mov %%eax, 0(%2) \n\t"
1308 "mov %%ebx, 4(%2) \n\t"
1309 "mov %%ecx, 8(%2) \n\t"
1310 "mov %%edx, 12(%2) \n\t"
1311 "popa"
1312 : : "a"(function), "c"(count), "S"(vec)
1313 : "memory", "cc");
c1f41226
EH		 1314#else
1315 abort();
a1fd24af
AL		 1316#endif
1317
bdde476a 1318 if (eax)
a1fd24af 1319 *eax = vec[0];
bdde476a 1320 if (ebx)
a1fd24af 1321 *ebx = vec[1];
bdde476a 1322 if (ecx)
a1fd24af 1323 *ecx = vec[2];
bdde476a 1324 if (edx)
a1fd24af 1325 *edx = vec[3];
bdde476a 1326}
c6dc6f63 1327
20271d48
EH		 1328void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1329{
1330 uint32_t eax, ebx, ecx, edx;
1331
1332 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1333 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1334
1335 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1336 if (family) {
1337 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1338 }
1339 if (model) {
1340 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1341 }
1342 if (stepping) {
1343 *stepping = eax & 0x0F;
1344 }
1345}
1346
d940ee9b
EH		 1347/* CPU class name definitions: */
1348
d940ee9b
EH		 1349/* Return type name for a given CPU model name
1350 * Caller is responsible for freeing the returned string.
1351 */
1352static char *x86_cpu_type_name(const char *model_name)
1353{
1354 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1355}
1356
500050d1
AF		 1357static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1358{
d940ee9b 1359 ObjectClass *oc;
99193d8f 1360 char *typename = x86_cpu_type_name(cpu_model);
d940ee9b
EH		 1361 oc = object_class_by_name(typename);
1362 g_free(typename);
1363 return oc;
500050d1
AF		 1364}
1365
104494ea
IM		 1366static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1367{
1368 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1369 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1370 return g_strndup(class_name,
1371 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1372}
1373
d940ee9b 1374struct X86CPUDefinition {
c6dc6f63
AP		 1375 const char *name;
1376 uint32_t level;
90e4b0c3 1377 uint32_t xlevel;
99b88a17
IM		 1378 /* vendor is zero-terminated, 12 character ASCII string */
1379 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1380 int family;
1381 int model;
1382 int stepping;
0514ef2f 1383 FeatureWordArray features;
807e9869 1384 const char *model_id;
6aaeb054 1385 CPUCaches *cache_info;
d940ee9b 1386};
c6dc6f63 1387
fe52acd2 1388static CPUCaches epyc_cache_info = {
a9f27ea9 1389 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1390 .type = DATA_CACHE,
fe52acd2
BM		 1391 .level = 1,
1392 .size = 32 * KiB,
1393 .line_size = 64,
1394 .associativity = 8,
1395 .partitions = 1,
1396 .sets = 64,
1397 .lines_per_tag = 1,
1398 .self_init = 1,
1399 .no_invd_sharing = true,
1400 },
a9f27ea9 1401 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1402 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1403 .level = 1,
1404 .size = 64 * KiB,
1405 .line_size = 64,
1406 .associativity = 4,
1407 .partitions = 1,
1408 .sets = 256,
1409 .lines_per_tag = 1,
1410 .self_init = 1,
1411 .no_invd_sharing = true,
1412 },
a9f27ea9 1413 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1414 .type = UNIFIED_CACHE,
1415 .level = 2,
1416 .size = 512 * KiB,
1417 .line_size = 64,
1418 .associativity = 8,
1419 .partitions = 1,
1420 .sets = 1024,
1421 .lines_per_tag = 1,
1422 },
a9f27ea9 1423 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1424 .type = UNIFIED_CACHE,
1425 .level = 3,
1426 .size = 8 * MiB,
1427 .line_size = 64,
1428 .associativity = 16,
1429 .partitions = 1,
1430 .sets = 8192,
1431 .lines_per_tag = 1,
1432 .self_init = true,
1433 .inclusive = true,
1434 .complex_indexing = true,
1435 },
1436};
1437
9576de75 1438static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1439 {
1440 .name = "qemu64",
3046bb5d 1441 .level = 0xd,
99b88a17 1442 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 1443 .family = 6,
f8e6a11a 1444 .model = 6,
c6dc6f63 1445 .stepping = 3,
0514ef2f 1446 .features[FEAT_1_EDX] =
27861ecc 1447 PPRO_FEATURES |
c6dc6f63 1448 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1449 CPUID_PSE36,
0514ef2f 1450 .features[FEAT_1_ECX] =
6aa91e4a 1451 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1452 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1453 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1454 .features[FEAT_8000_0001_ECX] =
71195672 1455 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1456 .xlevel = 0x8000000A,
9cf2cc3d 1457 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1458 },
1459 {
1460 .name = "phenom",
1461 .level = 5,
99b88a17 1462 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1463 .family = 16,
1464 .model = 2,
1465 .stepping = 3,
b9fc20bc 1466 /* Missing: CPUID_HT */
0514ef2f 1467 .features[FEAT_1_EDX] =
27861ecc 1468 PPRO_FEATURES |
c6dc6f63 1469 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1470 CPUID_PSE36 | CPUID_VME,
0514ef2f 1471 .features[FEAT_1_ECX] =
27861ecc 1472 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1473 CPUID_EXT_POPCNT,
0514ef2f 1474 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1475 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1476 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1477 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1478 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1479 CPUID_EXT3_CR8LEG,
1480 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1481 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1482 .features[FEAT_8000_0001_ECX] =
27861ecc 1483 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1484 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1485 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1486 .features[FEAT_SVM] =
b9fc20bc 1487 CPUID_SVM_NPT,
c6dc6f63
AP		 1488 .xlevel = 0x8000001A,
1489 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1490 },
1491 {
1492 .name = "core2duo",
1493 .level = 10,
99b88a17 1494 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1495 .family = 6,
1496 .model = 15,
1497 .stepping = 11,
b9fc20bc 1498 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1499 .features[FEAT_1_EDX] =
27861ecc 1500 PPRO_FEATURES |
c6dc6f63 1501 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1502 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1503 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1504 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1505 .features[FEAT_1_ECX] =
27861ecc 1506 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1507 CPUID_EXT_CX16,
0514ef2f 1508 .features[FEAT_8000_0001_EDX] =
27861ecc 1509 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1510 .features[FEAT_8000_0001_ECX] =
27861ecc 1511 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 1512 .xlevel = 0x80000008,
1513 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1514 },
1515 {
1516 .name = "kvm64",
3046bb5d 1517 .level = 0xd,
99b88a17 1518 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1519 .family = 15,
1520 .model = 6,
1521 .stepping = 1,
b3a4f0b1 1522 /* Missing: CPUID_HT */
0514ef2f 1523 .features[FEAT_1_EDX] =
b3a4f0b1 1524 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1525 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1526 CPUID_PSE36,
1527 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1528 .features[FEAT_1_ECX] =
27861ecc 1529 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1530 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1531 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1532 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1533 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1534 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1535 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1536 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1537 .features[FEAT_8000_0001_ECX] =
27861ecc 1538 0,
c6dc6f63
AP		 1539 .xlevel = 0x80000008,
1540 .model_id = "Common KVM processor"
1541 },
c6dc6f63
AP		 1542 {
1543 .name = "qemu32",
1544 .level = 4,
99b88a17 1545 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1546 .family = 6,
f8e6a11a 1547 .model = 6,
c6dc6f63 1548 .stepping = 3,
0514ef2f 1549 .features[FEAT_1_EDX] =
27861ecc 1550 PPRO_FEATURES,
0514ef2f 1551 .features[FEAT_1_ECX] =
6aa91e4a 1552 CPUID_EXT_SSE3,
58012d66 1553 .xlevel = 0x80000004,
9cf2cc3d 1554 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1555 },
eafaf1e5
AP		 1556 {
1557 .name = "kvm32",
1558 .level = 5,
99b88a17 1559 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1560 .family = 15,
1561 .model = 6,
1562 .stepping = 1,
0514ef2f 1563 .features[FEAT_1_EDX] =
b3a4f0b1 1564 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1565 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1566 .features[FEAT_1_ECX] =
27861ecc 1567 CPUID_EXT_SSE3,
0514ef2f 1568 .features[FEAT_8000_0001_ECX] =
27861ecc 1569 0,
eafaf1e5
AP		 1570 .xlevel = 0x80000008,
1571 .model_id = "Common 32-bit KVM processor"
1572 },
c6dc6f63
AP		 1573 {
1574 .name = "coreduo",
1575 .level = 10,
99b88a17 1576 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1577 .family = 6,
1578 .model = 14,
1579 .stepping = 8,
b9fc20bc 1580 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1581 .features[FEAT_1_EDX] =
27861ecc 1582 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1583 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1584 CPUID_SS,
1585 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1586 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1587 .features[FEAT_1_ECX] =
e93abc14 1588 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1589 .features[FEAT_8000_0001_EDX] =
27861ecc 1590 CPUID_EXT2_NX,
c6dc6f63
AP		 1591 .xlevel = 0x80000008,
1592 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1593 },
1594 {
1595 .name = "486",
58012d66 1596 .level = 1,
99b88a17 1597 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1598 .family = 4,
b2a856d9 1599 .model = 8,
c6dc6f63 1600 .stepping = 0,
0514ef2f 1601 .features[FEAT_1_EDX] =
27861ecc 1602 I486_FEATURES,
c6dc6f63 1603 .xlevel = 0,
807e9869 1604 .model_id = "",
c6dc6f63
AP		 1605 },
1606 {
1607 .name = "pentium",
1608 .level = 1,
99b88a17 1609 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1610 .family = 5,
1611 .model = 4,
1612 .stepping = 3,
0514ef2f 1613 .features[FEAT_1_EDX] =
27861ecc 1614 PENTIUM_FEATURES,
c6dc6f63 1615 .xlevel = 0,
807e9869 1616 .model_id = "",
c6dc6f63
AP		 1617 },
1618 {
1619 .name = "pentium2",
1620 .level = 2,
99b88a17 1621 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1622 .family = 6,
1623 .model = 5,
1624 .stepping = 2,
0514ef2f 1625 .features[FEAT_1_EDX] =
27861ecc 1626 PENTIUM2_FEATURES,
c6dc6f63 1627 .xlevel = 0,
807e9869 1628 .model_id = "",
c6dc6f63
AP		 1629 },
1630 {
1631 .name = "pentium3",
3046bb5d 1632 .level = 3,
99b88a17 1633 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1634 .family = 6,
1635 .model = 7,
1636 .stepping = 3,
0514ef2f 1637 .features[FEAT_1_EDX] =
27861ecc 1638 PENTIUM3_FEATURES,
c6dc6f63 1639 .xlevel = 0,
807e9869 1640 .model_id = "",
c6dc6f63
AP		 1641 },
1642 {
1643 .name = "athlon",
1644 .level = 2,
99b88a17 1645 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1646 .family = 6,
1647 .model = 2,
1648 .stepping = 3,
0514ef2f 1649 .features[FEAT_1_EDX] =
27861ecc 1650 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 1651 CPUID_MCA,
0514ef2f 1652 .features[FEAT_8000_0001_EDX] =
60032ac0 1653 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 1654 .xlevel = 0x80000008,
9cf2cc3d 1655 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1656 },
1657 {
1658 .name = "n270",
3046bb5d 1659 .level = 10,
99b88a17 1660 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1661 .family = 6,
1662 .model = 28,
1663 .stepping = 2,
b9fc20bc 1664 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1665 .features[FEAT_1_EDX] =
27861ecc 1666 PPRO_FEATURES |
b9fc20bc
EH		 1667 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1668 CPUID_ACPI | CPUID_SS,
c6dc6f63 1669 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1670 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1671 * CPUID_EXT_XTPR */
0514ef2f 1672 .features[FEAT_1_ECX] =
27861ecc 1673 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1674 CPUID_EXT_MOVBE,
0514ef2f 1675 .features[FEAT_8000_0001_EDX] =
60032ac0 1676 CPUID_EXT2_NX,
0514ef2f 1677 .features[FEAT_8000_0001_ECX] =
27861ecc 1678 CPUID_EXT3_LAHF_LM,
3046bb5d 1679 .xlevel = 0x80000008,
c6dc6f63
AP		 1680 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1681 },
3eca4642
EH		 1682 {
1683 .name = "Conroe",
3046bb5d 1684 .level = 10,
99b88a17 1685 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1686 .family = 6,
ffce9ebb 1687 .model = 15,
3eca4642 1688 .stepping = 3,
0514ef2f 1689 .features[FEAT_1_EDX] =
b3a4f0b1 1690 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1691 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1692 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1693 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1694 CPUID_DE | CPUID_FP87,
0514ef2f 1695 .features[FEAT_1_ECX] =
27861ecc 1696 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1697 .features[FEAT_8000_0001_EDX] =
27861ecc 1698 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1699 .features[FEAT_8000_0001_ECX] =
27861ecc 1700 CPUID_EXT3_LAHF_LM,
3046bb5d 1701 .xlevel = 0x80000008,
3eca4642
EH		 1702 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1703 },
1704 {
1705 .name = "Penryn",
3046bb5d 1706 .level = 10,
99b88a17 1707 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1708 .family = 6,
ffce9ebb 1709 .model = 23,
3eca4642 1710 .stepping = 3,
0514ef2f 1711 .features[FEAT_1_EDX] =
b3a4f0b1 1712 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1713 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1714 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1715 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1716 CPUID_DE | CPUID_FP87,
0514ef2f 1717 .features[FEAT_1_ECX] =
27861ecc 1718 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1719 CPUID_EXT_SSE3,
0514ef2f 1720 .features[FEAT_8000_0001_EDX] =
27861ecc 1721 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1722 .features[FEAT_8000_0001_ECX] =
27861ecc 1723 CPUID_EXT3_LAHF_LM,
3046bb5d 1724 .xlevel = 0x80000008,
3eca4642
EH		 1725 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1726 },
1727 {
1728 .name = "Nehalem",
3046bb5d 1729 .level = 11,
99b88a17 1730 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1731 .family = 6,
ffce9ebb 1732 .model = 26,
3eca4642 1733 .stepping = 3,
0514ef2f 1734 .features[FEAT_1_EDX] =
b3a4f0b1 1735 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1736 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1737 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1738 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1739 CPUID_DE | CPUID_FP87,
0514ef2f 1740 .features[FEAT_1_ECX] =
27861ecc 1741 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1742 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1743 .features[FEAT_8000_0001_EDX] =
27861ecc 1744 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1745 .features[FEAT_8000_0001_ECX] =
27861ecc 1746 CPUID_EXT3_LAHF_LM,
3046bb5d 1747 .xlevel = 0x80000008,
3eca4642
EH		 1748 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1749 },
ac96c413
EH		 1750 {
1751 .name = "Nehalem-IBRS",
1752 .level = 11,
1753 .vendor = CPUID_VENDOR_INTEL,
1754 .family = 6,
1755 .model = 26,
1756 .stepping = 3,
1757 .features[FEAT_1_EDX] =
1758 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1759 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1760 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1761 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1762 CPUID_DE | CPUID_FP87,
1763 .features[FEAT_1_ECX] =
1764 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1765 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1766 .features[FEAT_7_0_EDX] =
1767 CPUID_7_0_EDX_SPEC_CTRL,
1768 .features[FEAT_8000_0001_EDX] =
1769 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1770 .features[FEAT_8000_0001_ECX] =
1771 CPUID_EXT3_LAHF_LM,
1772 .xlevel = 0x80000008,
1773 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1774 },
3eca4642
EH		 1775 {
1776 .name = "Westmere",
1777 .level = 11,
99b88a17 1778 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1779 .family = 6,
1780 .model = 44,
1781 .stepping = 1,
0514ef2f 1782 .features[FEAT_1_EDX] =
b3a4f0b1 1783 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1784 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1785 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1786 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1787 CPUID_DE | CPUID_FP87,
0514ef2f 1788 .features[FEAT_1_ECX] =
27861ecc 1789 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1790 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1791 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1792 .features[FEAT_8000_0001_EDX] =
27861ecc 1793 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1794 .features[FEAT_8000_0001_ECX] =
27861ecc 1795 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1796 .features[FEAT_6_EAX] =
1797 CPUID_6_EAX_ARAT,
3046bb5d 1798 .xlevel = 0x80000008,
3eca4642
EH		 1799 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1800 },
ac96c413
EH		 1801 {
1802 .name = "Westmere-IBRS",
1803 .level = 11,
1804 .vendor = CPUID_VENDOR_INTEL,
1805 .family = 6,
1806 .model = 44,
1807 .stepping = 1,
1808 .features[FEAT_1_EDX] =
1809 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1810 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1811 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1812 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1813 CPUID_DE | CPUID_FP87,
1814 .features[FEAT_1_ECX] =
1815 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1816 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1817 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1818 .features[FEAT_8000_0001_EDX] =
1819 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1820 .features[FEAT_8000_0001_ECX] =
1821 CPUID_EXT3_LAHF_LM,
1822 .features[FEAT_7_0_EDX] =
1823 CPUID_7_0_EDX_SPEC_CTRL,
1824 .features[FEAT_6_EAX] =
1825 CPUID_6_EAX_ARAT,
1826 .xlevel = 0x80000008,
1827 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1828 },
3eca4642
EH		 1829 {
1830 .name = "SandyBridge",
1831 .level = 0xd,
99b88a17 1832 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1833 .family = 6,
1834 .model = 42,
1835 .stepping = 1,
0514ef2f 1836 .features[FEAT_1_EDX] =
b3a4f0b1 1837 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1838 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1839 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1840 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1841 CPUID_DE | CPUID_FP87,
0514ef2f 1842 .features[FEAT_1_ECX] =
27861ecc 1843 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1844 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1845 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1846 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1847 CPUID_EXT_SSE3,
0514ef2f 1848 .features[FEAT_8000_0001_EDX] =
27861ecc 1849 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1850 CPUID_EXT2_SYSCALL,
0514ef2f 1851 .features[FEAT_8000_0001_ECX] =
27861ecc 1852 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1853 .features[FEAT_XSAVE] =
1854 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1855 .features[FEAT_6_EAX] =
1856 CPUID_6_EAX_ARAT,
3046bb5d 1857 .xlevel = 0x80000008,
3eca4642
EH		 1858 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1859 },
ac96c413
EH		 1860 {
1861 .name = "SandyBridge-IBRS",
1862 .level = 0xd,
1863 .vendor = CPUID_VENDOR_INTEL,
1864 .family = 6,
1865 .model = 42,
1866 .stepping = 1,
1867 .features[FEAT_1_EDX] =
1868 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1869 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1870 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1871 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1872 CPUID_DE | CPUID_FP87,
1873 .features[FEAT_1_ECX] =
1874 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1875 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1876 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1877 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1878 CPUID_EXT_SSE3,
1879 .features[FEAT_8000_0001_EDX] =
1880 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1881 CPUID_EXT2_SYSCALL,
1882 .features[FEAT_8000_0001_ECX] =
1883 CPUID_EXT3_LAHF_LM,
1884 .features[FEAT_7_0_EDX] =
1885 CPUID_7_0_EDX_SPEC_CTRL,
1886 .features[FEAT_XSAVE] =
1887 CPUID_XSAVE_XSAVEOPT,
1888 .features[FEAT_6_EAX] =
1889 CPUID_6_EAX_ARAT,
1890 .xlevel = 0x80000008,
1891 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1892 },
2f9ac42a
PB		 1893 {
1894 .name = "IvyBridge",
1895 .level = 0xd,
1896 .vendor = CPUID_VENDOR_INTEL,
1897 .family = 6,
1898 .model = 58,
1899 .stepping = 9,
1900 .features[FEAT_1_EDX] =
1901 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1902 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1903 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1904 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1905 CPUID_DE | CPUID_FP87,
1906 .features[FEAT_1_ECX] =
1907 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1908 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1909 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1910 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1911 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1912 .features[FEAT_7_0_EBX] =
1913 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1914 CPUID_7_0_EBX_ERMS,
1915 .features[FEAT_8000_0001_EDX] =
1916 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1917 CPUID_EXT2_SYSCALL,
1918 .features[FEAT_8000_0001_ECX] =
1919 CPUID_EXT3_LAHF_LM,
1920 .features[FEAT_XSAVE] =
1921 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1922 .features[FEAT_6_EAX] =
1923 CPUID_6_EAX_ARAT,
3046bb5d 1924 .xlevel = 0x80000008,
2f9ac42a
PB		 1925 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1926 },
ac96c413
EH		 1927 {
1928 .name = "IvyBridge-IBRS",
1929 .level = 0xd,
1930 .vendor = CPUID_VENDOR_INTEL,
1931 .family = 6,
1932 .model = 58,
1933 .stepping = 9,
1934 .features[FEAT_1_EDX] =
1935 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1936 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1937 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1938 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1939 CPUID_DE | CPUID_FP87,
1940 .features[FEAT_1_ECX] =
1941 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1942 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1943 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1944 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1945 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1946 .features[FEAT_7_0_EBX] =
1947 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1948 CPUID_7_0_EBX_ERMS,
1949 .features[FEAT_8000_0001_EDX] =
1950 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1951 CPUID_EXT2_SYSCALL,
1952 .features[FEAT_8000_0001_ECX] =
1953 CPUID_EXT3_LAHF_LM,
1954 .features[FEAT_7_0_EDX] =
1955 CPUID_7_0_EDX_SPEC_CTRL,
1956 .features[FEAT_XSAVE] =
1957 CPUID_XSAVE_XSAVEOPT,
1958 .features[FEAT_6_EAX] =
1959 CPUID_6_EAX_ARAT,
1960 .xlevel = 0x80000008,
1961 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
1962 },
37507094 1963 {
a356850b
EH		 1964 .name = "Haswell-noTSX",
1965 .level = 0xd,
1966 .vendor = CPUID_VENDOR_INTEL,
1967 .family = 6,
1968 .model = 60,
1969 .stepping = 1,
1970 .features[FEAT_1_EDX] =
1971 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1972 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1973 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1974 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1975 CPUID_DE | CPUID_FP87,
1976 .features[FEAT_1_ECX] =
1977 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1978 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1979 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1980 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1981 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1982 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1983 .features[FEAT_8000_0001_EDX] =
1984 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1985 CPUID_EXT2_SYSCALL,
1986 .features[FEAT_8000_0001_ECX] =
becb6667 1987 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1988 .features[FEAT_7_0_EBX] =
1989 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1990 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1991 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1992 .features[FEAT_XSAVE] =
1993 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1994 .features[FEAT_6_EAX] =
1995 CPUID_6_EAX_ARAT,
3046bb5d 1996 .xlevel = 0x80000008,
a356850b 1997 .model_id = "Intel Core Processor (Haswell, no TSX)",
ac96c413
EH		 1998 },
1999 {
2000 .name = "Haswell-noTSX-IBRS",
2001 .level = 0xd,
2002 .vendor = CPUID_VENDOR_INTEL,
2003 .family = 6,
2004 .model = 60,
2005 .stepping = 1,
2006 .features[FEAT_1_EDX] =
2007 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2008 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2009 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2010 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2011 CPUID_DE | CPUID_FP87,
2012 .features[FEAT_1_ECX] =
2013 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2014 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2015 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2016 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2017 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2018 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2019 .features[FEAT_8000_0001_EDX] =
2020 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2021 CPUID_EXT2_SYSCALL,
2022 .features[FEAT_8000_0001_ECX] =
2023 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2024 .features[FEAT_7_0_EDX] =
2025 CPUID_7_0_EDX_SPEC_CTRL,
2026 .features[FEAT_7_0_EBX] =
2027 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2028 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2029 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2030 .features[FEAT_XSAVE] =
2031 CPUID_XSAVE_XSAVEOPT,
2032 .features[FEAT_6_EAX] =
2033 CPUID_6_EAX_ARAT,
2034 .xlevel = 0x80000008,
2035 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
2036 },
2037 {
37507094
EH		 2038 .name = "Haswell",
2039 .level = 0xd,
99b88a17 2040 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2041 .family = 6,
2042 .model = 60,
ec56a4a7 2043 .stepping = 4,
0514ef2f 2044 .features[FEAT_1_EDX] =
b3a4f0b1 2045 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2046 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2047 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2048 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2049 CPUID_DE | CPUID_FP87,
0514ef2f 2050 .features[FEAT_1_ECX] =
27861ecc 2051 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2052 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2053 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2054 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2055 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2056 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2057 .features[FEAT_8000_0001_EDX] =
27861ecc 2058 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2059 CPUID_EXT2_SYSCALL,
0514ef2f 2060 .features[FEAT_8000_0001_ECX] =
becb6667 2061 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2062 .features[FEAT_7_0_EBX] =
27861ecc 2063 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2064 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2065 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2066 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2067 .features[FEAT_XSAVE] =
2068 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2069 .features[FEAT_6_EAX] =
2070 CPUID_6_EAX_ARAT,
3046bb5d 2071 .xlevel = 0x80000008,
37507094
EH		 2072 .model_id = "Intel Core Processor (Haswell)",
2073 },
ac96c413
EH		 2074 {
2075 .name = "Haswell-IBRS",
2076 .level = 0xd,
2077 .vendor = CPUID_VENDOR_INTEL,
2078 .family = 6,
2079 .model = 60,
2080 .stepping = 4,
2081 .features[FEAT_1_EDX] =
2082 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2083 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2084 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2085 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2086 CPUID_DE | CPUID_FP87,
2087 .features[FEAT_1_ECX] =
2088 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2089 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2090 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2091 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2092 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2093 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2094 .features[FEAT_8000_0001_EDX] =
2095 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2096 CPUID_EXT2_SYSCALL,
2097 .features[FEAT_8000_0001_ECX] =
2098 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2099 .features[FEAT_7_0_EDX] =
2100 CPUID_7_0_EDX_SPEC_CTRL,
2101 .features[FEAT_7_0_EBX] =
2102 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2103 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2104 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2105 CPUID_7_0_EBX_RTM,
2106 .features[FEAT_XSAVE] =
2107 CPUID_XSAVE_XSAVEOPT,
2108 .features[FEAT_6_EAX] =
2109 CPUID_6_EAX_ARAT,
2110 .xlevel = 0x80000008,
2111 .model_id = "Intel Core Processor (Haswell, IBRS)",
2112 },
a356850b
EH		 2113 {
2114 .name = "Broadwell-noTSX",
2115 .level = 0xd,
2116 .vendor = CPUID_VENDOR_INTEL,
2117 .family = 6,
2118 .model = 61,
2119 .stepping = 2,
2120 .features[FEAT_1_EDX] =
2121 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2122 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2123 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2124 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2125 CPUID_DE | CPUID_FP87,
2126 .features[FEAT_1_ECX] =
2127 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2128 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2129 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2130 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2131 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2132 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2133 .features[FEAT_8000_0001_EDX] =
2134 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2135 CPUID_EXT2_SYSCALL,
2136 .features[FEAT_8000_0001_ECX] =
becb6667 2137 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 2138 .features[FEAT_7_0_EBX] =
2139 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2140 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2141 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2142 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2143 CPUID_7_0_EBX_SMAP,
2144 .features[FEAT_XSAVE] =
2145 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2146 .features[FEAT_6_EAX] =
2147 CPUID_6_EAX_ARAT,
3046bb5d 2148 .xlevel = 0x80000008,
a356850b
EH		 2149 .model_id = "Intel Core Processor (Broadwell, no TSX)",
2150 },
ac96c413
EH		 2151 {
2152 .name = "Broadwell-noTSX-IBRS",
2153 .level = 0xd,
2154 .vendor = CPUID_VENDOR_INTEL,
2155 .family = 6,
2156 .model = 61,
2157 .stepping = 2,
2158 .features[FEAT_1_EDX] =
2159 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2160 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2161 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2162 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2163 CPUID_DE | CPUID_FP87,
2164 .features[FEAT_1_ECX] =
2165 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2166 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2167 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2168 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2169 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2170 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2171 .features[FEAT_8000_0001_EDX] =
2172 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2173 CPUID_EXT2_SYSCALL,
2174 .features[FEAT_8000_0001_ECX] =
2175 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2176 .features[FEAT_7_0_EDX] =
2177 CPUID_7_0_EDX_SPEC_CTRL,
2178 .features[FEAT_7_0_EBX] =
2179 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2180 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2181 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2182 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2183 CPUID_7_0_EBX_SMAP,
2184 .features[FEAT_XSAVE] =
2185 CPUID_XSAVE_XSAVEOPT,
2186 .features[FEAT_6_EAX] =
2187 CPUID_6_EAX_ARAT,
2188 .xlevel = 0x80000008,
2189 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
2190 },
ece01354
EH		 2191 {
2192 .name = "Broadwell",
2193 .level = 0xd,
2194 .vendor = CPUID_VENDOR_INTEL,
2195 .family = 6,
2196 .model = 61,
2197 .stepping = 2,
2198 .features[FEAT_1_EDX] =
b3a4f0b1 2199 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2200 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2201 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2202 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2203 CPUID_DE | CPUID_FP87,
2204 .features[FEAT_1_ECX] =
2205 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2206 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2207 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2208 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2209 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2210 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2211 .features[FEAT_8000_0001_EDX] =
2212 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2213 CPUID_EXT2_SYSCALL,
2214 .features[FEAT_8000_0001_ECX] =
becb6667 2215 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2216 .features[FEAT_7_0_EBX] =
2217 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2218 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2219 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2220 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2221 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2222 .features[FEAT_XSAVE] =
2223 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2224 .features[FEAT_6_EAX] =
2225 CPUID_6_EAX_ARAT,
3046bb5d 2226 .xlevel = 0x80000008,
ece01354
EH		 2227 .model_id = "Intel Core Processor (Broadwell)",
2228 },
ac96c413
EH		 2229 {
2230 .name = "Broadwell-IBRS",
2231 .level = 0xd,
2232 .vendor = CPUID_VENDOR_INTEL,
2233 .family = 6,
2234 .model = 61,
2235 .stepping = 2,
2236 .features[FEAT_1_EDX] =
2237 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2238 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2239 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2240 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2241 CPUID_DE | CPUID_FP87,
2242 .features[FEAT_1_ECX] =
2243 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2244 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2245 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2246 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2247 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2248 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2249 .features[FEAT_8000_0001_EDX] =
2250 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2251 CPUID_EXT2_SYSCALL,
2252 .features[FEAT_8000_0001_ECX] =
2253 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2254 .features[FEAT_7_0_EDX] =
2255 CPUID_7_0_EDX_SPEC_CTRL,
2256 .features[FEAT_7_0_EBX] =
2257 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2258 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2259 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2260 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2261 CPUID_7_0_EBX_SMAP,
2262 .features[FEAT_XSAVE] =
2263 CPUID_XSAVE_XSAVEOPT,
2264 .features[FEAT_6_EAX] =
2265 CPUID_6_EAX_ARAT,
2266 .xlevel = 0x80000008,
2267 .model_id = "Intel Core Processor (Broadwell, IBRS)",
2268 },
f6f949e9
EH		 2269 {
2270 .name = "Skylake-Client",
2271 .level = 0xd,
2272 .vendor = CPUID_VENDOR_INTEL,
2273 .family = 6,
2274 .model = 94,
2275 .stepping = 3,
2276 .features[FEAT_1_EDX] =
2277 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2278 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2279 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2280 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2281 CPUID_DE | CPUID_FP87,
2282 .features[FEAT_1_ECX] =
2283 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2284 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2285 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2286 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2287 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2288 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2289 .features[FEAT_8000_0001_EDX] =
2290 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2291 CPUID_EXT2_SYSCALL,
2292 .features[FEAT_8000_0001_ECX] =
2293 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2294 .features[FEAT_7_0_EBX] =
2295 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2296 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2297 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2298 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2299 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
2300 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 2301 * including v4.1 to v4.12).
f6f949e9
EH		 2302 * KVM doesn't yet expose any XSAVES state save component,
2303 * and the only one defined in Skylake (processor tracing)
2304 * probably will block migration anyway.
2305 */
2306 .features[FEAT_XSAVE] =
2307 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2308 CPUID_XSAVE_XGETBV1,
2309 .features[FEAT_6_EAX] =
2310 CPUID_6_EAX_ARAT,
2311 .xlevel = 0x80000008,
2312 .model_id = "Intel Core Processor (Skylake)",
2313 },
ac96c413
EH		 2314 {
2315 .name = "Skylake-Client-IBRS",
2316 .level = 0xd,
2317 .vendor = CPUID_VENDOR_INTEL,
2318 .family = 6,
2319 .model = 94,
2320 .stepping = 3,
2321 .features[FEAT_1_EDX] =
2322 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2323 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2324 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2325 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2326 CPUID_DE | CPUID_FP87,
2327 .features[FEAT_1_ECX] =
2328 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2329 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2330 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2331 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2332 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2333 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2334 .features[FEAT_8000_0001_EDX] =
2335 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2336 CPUID_EXT2_SYSCALL,
2337 .features[FEAT_8000_0001_ECX] =
2338 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2339 .features[FEAT_7_0_EDX] =
2340 CPUID_7_0_EDX_SPEC_CTRL,
2341 .features[FEAT_7_0_EBX] =
2342 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2343 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2344 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2345 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2346 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
2347 /* Missing: XSAVES (not supported by some Linux versions,
2348 * including v4.1 to v4.12).
2349 * KVM doesn't yet expose any XSAVES state save component,
2350 * and the only one defined in Skylake (processor tracing)
2351 * probably will block migration anyway.
2352 */
2353 .features[FEAT_XSAVE] =
2354 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2355 CPUID_XSAVE_XGETBV1,
2356 .features[FEAT_6_EAX] =
2357 CPUID_6_EAX_ARAT,
2358 .xlevel = 0x80000008,
2359 .model_id = "Intel Core Processor (Skylake, IBRS)",
2360 },
53f9a6f4
BF		 2361 {
2362 .name = "Skylake-Server",
2363 .level = 0xd,
2364 .vendor = CPUID_VENDOR_INTEL,
2365 .family = 6,
2366 .model = 85,
2367 .stepping = 4,
2368 .features[FEAT_1_EDX] =
2369 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2370 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2371 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2372 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2373 CPUID_DE | CPUID_FP87,
2374 .features[FEAT_1_ECX] =
2375 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2376 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2377 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2378 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2379 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2380 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2381 .features[FEAT_8000_0001_EDX] =
2382 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2383 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2384 .features[FEAT_8000_0001_ECX] =
2385 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2386 .features[FEAT_7_0_EBX] =
2387 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2388 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2389 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2390 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2391 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2392 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2393 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2394 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
53f9a6f4
BF		 2395 /* Missing: XSAVES (not supported by some Linux versions,
2396 * including v4.1 to v4.12).
2397 * KVM doesn't yet expose any XSAVES state save component,
2398 * and the only one defined in Skylake (processor tracing)
2399 * probably will block migration anyway.
2400 */
2401 .features[FEAT_XSAVE] =
2402 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2403 CPUID_XSAVE_XGETBV1,
2404 .features[FEAT_6_EAX] =
2405 CPUID_6_EAX_ARAT,
2406 .xlevel = 0x80000008,
2407 .model_id = "Intel Xeon Processor (Skylake)",
2408 },
ac96c413
EH		 2409 {
2410 .name = "Skylake-Server-IBRS",
2411 .level = 0xd,
2412 .vendor = CPUID_VENDOR_INTEL,
2413 .family = 6,
2414 .model = 85,
2415 .stepping = 4,
2416 .features[FEAT_1_EDX] =
2417 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2418 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2419 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2420 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2421 CPUID_DE | CPUID_FP87,
2422 .features[FEAT_1_ECX] =
2423 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2424 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2425 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2426 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2427 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2428 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2429 .features[FEAT_8000_0001_EDX] =
2430 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2431 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2432 .features[FEAT_8000_0001_ECX] =
2433 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2434 .features[FEAT_7_0_EDX] =
2435 CPUID_7_0_EDX_SPEC_CTRL,
2436 .features[FEAT_7_0_EBX] =
2437 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2438 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2439 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2440 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2441 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2442 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2443 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2444 CPUID_7_0_EBX_AVX512VL,
2445 /* Missing: XSAVES (not supported by some Linux versions,
2446 * including v4.1 to v4.12).
2447 * KVM doesn't yet expose any XSAVES state save component,
2448 * and the only one defined in Skylake (processor tracing)
2449 * probably will block migration anyway.
2450 */
2451 .features[FEAT_XSAVE] =
2452 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2453 CPUID_XSAVE_XGETBV1,
2454 .features[FEAT_6_EAX] =
2455 CPUID_6_EAX_ARAT,
2456 .xlevel = 0x80000008,
2457 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2458 },
c7a88b52
TX		 2459 {
2460 .name = "Cascadelake-Server",
2461 .level = 0xd,
2462 .vendor = CPUID_VENDOR_INTEL,
2463 .family = 6,
2464 .model = 85,
2465 .stepping = 5,
2466 .features[FEAT_1_EDX] =
2467 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2468 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2469 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2470 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2471 CPUID_DE | CPUID_FP87,
2472 .features[FEAT_1_ECX] =
2473 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2474 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2475 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2476 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2477 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2478 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2479 .features[FEAT_8000_0001_EDX] =
2480 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2481 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2482 .features[FEAT_8000_0001_ECX] =
2483 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2484 .features[FEAT_7_0_EBX] =
2485 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2486 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2487 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2488 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2489 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2490 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2491 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2492 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
2493 CPUID_7_0_EBX_INTEL_PT,
2494 .features[FEAT_7_0_ECX] =
2495 CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE |
2496 CPUID_7_0_ECX_AVX512VNNI,
2497 .features[FEAT_7_0_EDX] =
2498 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2499 /* Missing: XSAVES (not supported by some Linux versions,
2500 * including v4.1 to v4.12).
2501 * KVM doesn't yet expose any XSAVES state save component,
2502 * and the only one defined in Skylake (processor tracing)
2503 * probably will block migration anyway.
2504 */
2505 .features[FEAT_XSAVE] =
2506 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2507 CPUID_XSAVE_XGETBV1,
2508 .features[FEAT_6_EAX] =
2509 CPUID_6_EAX_ARAT,
2510 .xlevel = 0x80000008,
2511 .model_id = "Intel Xeon Processor (Cascadelake)",
2512 },
8a11c62d
RH		 2513 {
2514 .name = "Icelake-Client",
2515 .level = 0xd,
2516 .vendor = CPUID_VENDOR_INTEL,
2517 .family = 6,
2518 .model = 126,
2519 .stepping = 0,
2520 .features[FEAT_1_EDX] =
2521 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2522 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2523 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2524 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2525 CPUID_DE | CPUID_FP87,
2526 .features[FEAT_1_ECX] =
2527 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2528 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2529 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2530 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2531 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2532 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2533 .features[FEAT_8000_0001_EDX] =
2534 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2535 CPUID_EXT2_SYSCALL,
2536 .features[FEAT_8000_0001_ECX] =
2537 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2538 .features[FEAT_8000_0008_EBX] =
2539 CPUID_8000_0008_EBX_WBNOINVD,
2540 .features[FEAT_7_0_EBX] =
2541 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2542 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2543 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2544 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2545 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INTEL_PT,
2546 .features[FEAT_7_0_ECX] =
2547 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2548 CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2549 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2550 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2551 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2552 .features[FEAT_7_0_EDX] =
2553 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2554 /* Missing: XSAVES (not supported by some Linux versions,
2555 * including v4.1 to v4.12).
2556 * KVM doesn't yet expose any XSAVES state save component,
2557 * and the only one defined in Skylake (processor tracing)
2558 * probably will block migration anyway.
2559 */
2560 .features[FEAT_XSAVE] =
2561 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2562 CPUID_XSAVE_XGETBV1,
2563 .features[FEAT_6_EAX] =
2564 CPUID_6_EAX_ARAT,
2565 .xlevel = 0x80000008,
2566 .model_id = "Intel Core Processor (Icelake)",
2567 },
2568 {
2569 .name = "Icelake-Server",
2570 .level = 0xd,
2571 .vendor = CPUID_VENDOR_INTEL,
2572 .family = 6,
2573 .model = 134,
2574 .stepping = 0,
2575 .features[FEAT_1_EDX] =
2576 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2577 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2578 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2579 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2580 CPUID_DE | CPUID_FP87,
2581 .features[FEAT_1_ECX] =
2582 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2583 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2584 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2585 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2586 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2587 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2588 .features[FEAT_8000_0001_EDX] =
2589 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2590 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2591 .features[FEAT_8000_0001_ECX] =
2592 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2593 .features[FEAT_8000_0008_EBX] =
2594 CPUID_8000_0008_EBX_WBNOINVD,
2595 .features[FEAT_7_0_EBX] =
2596 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2597 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2598 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2599 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2600 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2601 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2602 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2603 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
2604 CPUID_7_0_EBX_INTEL_PT,
2605 .features[FEAT_7_0_ECX] =
2606 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2607 CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2608 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2609 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2610 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
2611 .features[FEAT_7_0_EDX] =
2612 CPUID_7_0_EDX_PCONFIG | CPUID_7_0_EDX_SPEC_CTRL |
2613 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2614 /* Missing: XSAVES (not supported by some Linux versions,
2615 * including v4.1 to v4.12).
2616 * KVM doesn't yet expose any XSAVES state save component,
2617 * and the only one defined in Skylake (processor tracing)
2618 * probably will block migration anyway.
2619 */
2620 .features[FEAT_XSAVE] =
2621 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2622 CPUID_XSAVE_XGETBV1,
2623 .features[FEAT_6_EAX] =
2624 CPUID_6_EAX_ARAT,
2625 .xlevel = 0x80000008,
2626 .model_id = "Intel Xeon Processor (Icelake)",
2627 },
a1849515
BF		 2628 {
2629 .name = "KnightsMill",
2630 .level = 0xd,
2631 .vendor = CPUID_VENDOR_INTEL,
2632 .family = 6,
2633 .model = 133,
2634 .stepping = 0,
2635 .features[FEAT_1_EDX] =
2636 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2637 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2638 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2639 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2640 CPUID_PSE | CPUID_DE | CPUID_FP87,
2641 .features[FEAT_1_ECX] =
2642 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2643 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2644 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2645 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2646 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2647 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2648 .features[FEAT_8000_0001_EDX] =
2649 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2650 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2651 .features[FEAT_8000_0001_ECX] =
2652 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2653 .features[FEAT_7_0_EBX] =
2654 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2655 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2656 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2657 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2658 CPUID_7_0_EBX_AVX512ER,
2659 .features[FEAT_7_0_ECX] =
2660 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2661 .features[FEAT_7_0_EDX] =
2662 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2663 .features[FEAT_XSAVE] =
2664 CPUID_XSAVE_XSAVEOPT,
2665 .features[FEAT_6_EAX] =
2666 CPUID_6_EAX_ARAT,
2667 .xlevel = 0x80000008,
2668 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2669 },
3eca4642
EH		 2670 {
2671 .name = "Opteron_G1",
2672 .level = 5,
99b88a17 2673 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2674 .family = 15,
2675 .model = 6,
2676 .stepping = 1,
0514ef2f 2677 .features[FEAT_1_EDX] =
b3a4f0b1 2678 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2679 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2680 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2681 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2682 CPUID_DE | CPUID_FP87,
0514ef2f 2683 .features[FEAT_1_ECX] =
27861ecc 2684 CPUID_EXT_SSE3,
0514ef2f 2685 .features[FEAT_8000_0001_EDX] =
2a923a29 2686 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 2687 .xlevel = 0x80000008,
2688 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2689 },
2690 {
2691 .name = "Opteron_G2",
2692 .level = 5,
99b88a17 2693 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2694 .family = 15,
2695 .model = 6,
2696 .stepping = 1,
0514ef2f 2697 .features[FEAT_1_EDX] =
b3a4f0b1 2698 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2699 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2700 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2701 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2702 CPUID_DE | CPUID_FP87,
0514ef2f 2703 .features[FEAT_1_ECX] =
27861ecc 2704 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 2705 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2706 .features[FEAT_8000_0001_EDX] =
2a923a29 2707 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2708 .features[FEAT_8000_0001_ECX] =
27861ecc 2709 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2710 .xlevel = 0x80000008,
2711 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2712 },
2713 {
2714 .name = "Opteron_G3",
2715 .level = 5,
99b88a17 2716 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 2717 .family = 16,
2718 .model = 2,
2719 .stepping = 3,
0514ef2f 2720 .features[FEAT_1_EDX] =
b3a4f0b1 2721 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2722 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2723 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2724 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2725 CPUID_DE | CPUID_FP87,
0514ef2f 2726 .features[FEAT_1_ECX] =
27861ecc 2727 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 2728 CPUID_EXT_SSE3,
33b5e8c0 2729 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2730 .features[FEAT_8000_0001_EDX] =
2a923a29 2731 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2732 .features[FEAT_8000_0001_ECX] =
27861ecc 2733 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 2734 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2735 .xlevel = 0x80000008,
2736 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2737 },
2738 {
2739 .name = "Opteron_G4",
2740 .level = 0xd,
99b88a17 2741 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2742 .family = 21,
2743 .model = 1,
2744 .stepping = 2,
0514ef2f 2745 .features[FEAT_1_EDX] =
b3a4f0b1 2746 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2747 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2748 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2749 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2750 CPUID_DE | CPUID_FP87,
0514ef2f 2751 .features[FEAT_1_ECX] =
27861ecc 2752 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2753 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2754 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2755 CPUID_EXT_SSE3,
33b5e8c0 2756 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2757 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 2758 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2759 CPUID_EXT2_SYSCALL,
0514ef2f 2760 .features[FEAT_8000_0001_ECX] =
27861ecc 2761 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2762 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2763 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2764 CPUID_EXT3_LAHF_LM,
0bb0b2d2 2765 /* no xsaveopt! */
3eca4642
EH		 2766 .xlevel = 0x8000001A,
2767 .model_id = "AMD Opteron 62xx class CPU",
2768 },
021941b9
AP		 2769 {
2770 .name = "Opteron_G5",
2771 .level = 0xd,
99b88a17 2772 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 2773 .family = 21,
2774 .model = 2,
2775 .stepping = 0,
0514ef2f 2776 .features[FEAT_1_EDX] =
b3a4f0b1 2777 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2778 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2779 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2780 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2781 CPUID_DE | CPUID_FP87,
0514ef2f 2782 .features[FEAT_1_ECX] =
27861ecc 2783 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 2784 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2785 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2786 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 2787 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2788 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 2789 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2790 CPUID_EXT2_SYSCALL,
0514ef2f 2791 .features[FEAT_8000_0001_ECX] =
27861ecc 2792 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2793 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2794 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2795 CPUID_EXT3_LAHF_LM,
0bb0b2d2 2796 /* no xsaveopt! */
021941b9
AP		 2797 .xlevel = 0x8000001A,
2798 .model_id = "AMD Opteron 63xx class CPU",
2799 },
2e2efc7d
BS		 2800 {
2801 .name = "EPYC",
2802 .level = 0xd,
2803 .vendor = CPUID_VENDOR_AMD,
2804 .family = 23,
2805 .model = 1,
2806 .stepping = 2,
2807 .features[FEAT_1_EDX] =
2808 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2809 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2810 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2811 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2812 CPUID_VME | CPUID_FP87,
2813 .features[FEAT_1_ECX] =
2814 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2815 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2816 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2817 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2818 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2819 .features[FEAT_8000_0001_EDX] =
2820 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2821 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2822 CPUID_EXT2_SYSCALL,
2823 .features[FEAT_8000_0001_ECX] =
2824 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2825 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2826 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2827 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 2828 .features[FEAT_7_0_EBX] =
2829 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2830 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2831 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2832 CPUID_7_0_EBX_SHA_NI,
2833 /* Missing: XSAVES (not supported by some Linux versions,
2834 * including v4.1 to v4.12).
2835 * KVM doesn't yet expose any XSAVES state save component.
2836 */
2837 .features[FEAT_XSAVE] =
2838 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2839 CPUID_XSAVE_XGETBV1,
2840 .features[FEAT_6_EAX] =
2841 CPUID_6_EAX_ARAT,
e0051647 2842 .xlevel = 0x8000001E,
2e2efc7d 2843 .model_id = "AMD EPYC Processor",
fe52acd2 2844 .cache_info = &epyc_cache_info,
2e2efc7d 2845 },
6cfbc54e
EH		 2846 {
2847 .name = "EPYC-IBPB",
2848 .level = 0xd,
2849 .vendor = CPUID_VENDOR_AMD,
2850 .family = 23,
2851 .model = 1,
2852 .stepping = 2,
2853 .features[FEAT_1_EDX] =
2854 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2855 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2856 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2857 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2858 CPUID_VME | CPUID_FP87,
2859 .features[FEAT_1_ECX] =
2860 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2861 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2862 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2863 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2864 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2865 .features[FEAT_8000_0001_EDX] =
2866 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2867 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2868 CPUID_EXT2_SYSCALL,
2869 .features[FEAT_8000_0001_ECX] =
2870 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2871 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2872 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2873 CPUID_EXT3_TOPOEXT,
6cfbc54e
EH		 2874 .features[FEAT_8000_0008_EBX] =
2875 CPUID_8000_0008_EBX_IBPB,
2876 .features[FEAT_7_0_EBX] =
2877 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2878 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2879 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2880 CPUID_7_0_EBX_SHA_NI,
2881 /* Missing: XSAVES (not supported by some Linux versions,
2882 * including v4.1 to v4.12).
2883 * KVM doesn't yet expose any XSAVES state save component.
2884 */
2885 .features[FEAT_XSAVE] =
2886 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2887 CPUID_XSAVE_XGETBV1,
2888 .features[FEAT_6_EAX] =
2889 CPUID_6_EAX_ARAT,
e0051647 2890 .xlevel = 0x8000001E,
6cfbc54e 2891 .model_id = "AMD EPYC Processor (with IBPB)",
fe52acd2 2892 .cache_info = &epyc_cache_info,
6cfbc54e 2893 },
c6dc6f63
AP		 2894};
2895
5114e842
EH		 2896typedef struct PropValue {
2897 const char *prop, *value;
2898} PropValue;
2899
2900/* KVM-specific features that are automatically added/removed
2901 * from all CPU models when KVM is enabled.
2902 */
2903static PropValue kvm_default_props[] = {
2904 { "kvmclock", "on" },
2905 { "kvm-nopiodelay", "on" },
2906 { "kvm-asyncpf", "on" },
2907 { "kvm-steal-time", "on" },
2908 { "kvm-pv-eoi", "on" },
2909 { "kvmclock-stable-bit", "on" },
2910 { "x2apic", "on" },
2911 { "acpi", "off" },
2912 { "monitor", "off" },
2913 { "svm", "off" },
2914 { NULL, NULL },
2915};
2916
04d99c3c
EH		 2917/* TCG-specific defaults that override all CPU models when using TCG
2918 */
2919static PropValue tcg_default_props[] = {
2920 { "vme", "off" },
2921 { NULL, NULL },
2922};
2923
2924
5114e842
EH		 2925void x86_cpu_change_kvm_default(const char *prop, const char *value)
2926{
2927 PropValue *pv;
2928 for (pv = kvm_default_props; pv->prop; pv++) {
2929 if (!strcmp(pv->prop, prop)) {
2930 pv->value = value;
2931 break;
2932 }
2933 }
2934
2935 /* It is valid to call this function only for properties that
2936 * are already present in the kvm_default_props table.
2937 */
2938 assert(pv->prop);
2939}
2940
4d1b279b
EH		 2941static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2942 bool migratable_only);
2943
40bfe48f
HZ		 2944static bool lmce_supported(void)
2945{
c62f2630 2946 uint64_t mce_cap = 0;
40bfe48f 2947
c62f2630 2948#ifdef CONFIG_KVM
40bfe48f
HZ		 2949 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
2950 return false;
2951 }
c62f2630 2952#endif
40bfe48f
HZ		 2953
2954 return !!(mce_cap & MCG_LMCE_P);
2955}
2956
7d8050b5
EH		 2957#define CPUID_MODEL_ID_SZ 48
2958
2959/**
2960 * cpu_x86_fill_model_id:
2961 * Get CPUID model ID string from host CPU.
2962 *
2963 * @str should have at least CPUID_MODEL_ID_SZ bytes
2964 *
2965 * The function does NOT add a null terminator to the string
2966 * automatically.
2967 */
c6dc6f63
AP		 2968static int cpu_x86_fill_model_id(char *str)
2969{
2970 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2971 int i;
2972
2973 for (i = 0; i < 3; i++) {
2974 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
2975 memcpy(str + i * 16 + 0, &eax, 4);
2976 memcpy(str + i * 16 + 4, &ebx, 4);
2977 memcpy(str + i * 16 + 8, &ecx, 4);
2978 memcpy(str + i * 16 + 12, &edx, 4);
2979 }
2980 return 0;
2981}
2982
c62f2630 2983static Property max_x86_cpu_properties[] = {
120eee7d 2984 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 2985 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 2986 DEFINE_PROP_END_OF_LIST()
2987};
2988
c62f2630 2989static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 2990{
84f1b92f 2991 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 2992 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 2993
f48c8837 2994 xcc->ordering = 9;
6e746f30 2995
ee465a3e 2996 xcc->model_description =
c62f2630 2997 "Enables all features supported by the accelerator in the current host";
d940ee9b 2998
c62f2630 2999 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 3000}
3001
0bacd8b3
EH		 3002static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
3003
c62f2630 3004static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 3005{
3006 X86CPU *cpu = X86_CPU(obj);
3007 CPUX86State *env = &cpu->env;
3008 KVMState *s = kvm_state;
d940ee9b 3009
4d1b279b
EH		 3010 /* We can't fill the features array here because we don't know yet if
3011 * "migratable" is true or false.
3012 */
44bd8e53 3013 cpu->max_features = true;
4d1b279b 3014
d6dcc558 3015 if (accel_uses_host_cpuid()) {
bd182022
EH		 3016 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
3017 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
3018 int family, model, stepping;
d6dcc558
SAGDR		 3019 X86CPUDefinition host_cpudef = { };
3020 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3021
3022 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
3023 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
0bacd8b3 3024
bd182022 3025 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 3026
bd182022 3027 cpu_x86_fill_model_id(model_id);
0bacd8b3 3028
bd182022
EH		 3029 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
3030 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
3031 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
3032 object_property_set_int(OBJECT(cpu), stepping, "stepping",
3033 &error_abort);
3034 object_property_set_str(OBJECT(cpu), model_id, "model-id",
3035 &error_abort);
0bacd8b3 3036
d6dcc558
SAGDR		 3037 if (kvm_enabled()) {
3038 env->cpuid_min_level =
3039 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
3040 env->cpuid_min_xlevel =
3041 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
3042 env->cpuid_min_xlevel2 =
3043 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
3044 } else {
3045 env->cpuid_min_level =
3046 hvf_get_supported_cpuid(0x0, 0, R_EAX);
3047 env->cpuid_min_xlevel =
3048 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
3049 env->cpuid_min_xlevel2 =
3050 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
3051 }
40bfe48f
HZ		 3052
3053 if (lmce_supported()) {
3054 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
3055 }
6900d1cc
EH		 3056 } else {
3057 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
3058 "vendor", &error_abort);
3059 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
3060 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
3061 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
3062 object_property_set_str(OBJECT(cpu),
3063 "QEMU TCG CPU version " QEMU_HW_VERSION,
3064 "model-id", &error_abort);
e4356010 3065 }
2a573259 3066
d940ee9b 3067 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 3068}
3069
c62f2630
EH		 3070static const TypeInfo max_x86_cpu_type_info = {
3071 .name = X86_CPU_TYPE_NAME("max"),
3072 .parent = TYPE_X86_CPU,
3073 .instance_init = max_x86_cpu_initfn,
3074 .class_init = max_x86_cpu_class_init,
3075};
3076
d6dcc558 3077#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 3078static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
3079{
3080 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3081
d6dcc558 3082 xcc->host_cpuid_required = true;
c62f2630
EH		 3083 xcc->ordering = 8;
3084
02693cc4
GK		 3085#if defined(CONFIG_KVM)
3086 xcc->model_description =
3087 "KVM processor with all supported host features ";
3088#elif defined(CONFIG_HVF)
3089 xcc->model_description =
3090 "HVF processor with all supported host features ";
3091#endif
c62f2630
EH		 3092}
3093
d940ee9b
EH		 3094static const TypeInfo host_x86_cpu_type_info = {
3095 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 3096 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 3097 .class_init = host_x86_cpu_class_init,
3098};
3099
3100#endif
3101
07585923
RH		 3102static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
3103{
3104 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
3105
3106 switch (f->type) {
3107 case CPUID_FEATURE_WORD:
3108 {
3109 const char *reg = get_register_name_32(f->cpuid.reg);
3110 assert(reg);
3111 return g_strdup_printf("CPUID.%02XH:%s",
3112 f->cpuid.eax, reg);
3113 }
3114 case MSR_FEATURE_WORD:
3115 return g_strdup_printf("MSR(%02XH)",
3116 f->msr.index);
3117 }
3118
3119 return NULL;
3120}
3121
8459e396 3122static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 3123{
8459e396 3124 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63 3125 int i;
07585923 3126 char *feat_word_str;
c6dc6f63 3127
857aee33 3128 for (i = 0; i < 32; ++i) {
72370dc1 3129 if ((1UL << i) & mask) {
07585923
RH		 3130 feat_word_str = feature_word_description(f, i);
3131 warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
d6dcc558 3132 accel_uses_host_cpuid() ? "host" : "TCG",
07585923 3133 feat_word_str,
8297be80
AF		 3134 f->feat_names[i] ? "." : "",
3135 f->feat_names[i] ? f->feat_names[i] : "", i);
07585923 3136 g_free(feat_word_str);
c6dc6f63 3137 }
857aee33 3138 }
c6dc6f63
AP		 3139}
3140
d7bce999
EB		 3141static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
3142 const char *name, void *opaque,
3143 Error **errp)
95b8519d
AF		 3144{
3145 X86CPU *cpu = X86_CPU(obj);
3146 CPUX86State *env = &cpu->env;
3147 int64_t value;
3148
3149 value = (env->cpuid_version >> 8) & 0xf;
3150 if (value == 0xf) {
3151 value += (env->cpuid_version >> 20) & 0xff;
3152 }
51e72bc1 3153 visit_type_int(v, name, &value, errp);
95b8519d
AF		 3154}
3155
d7bce999
EB		 3156static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
3157 const char *name, void *opaque,
3158 Error **errp)
ed5e1ec3 3159{
71ad61d3
AF		 3160 X86CPU *cpu = X86_CPU(obj);
3161 CPUX86State *env = &cpu->env;
3162 const int64_t min = 0;
3163 const int64_t max = 0xff + 0xf;
65cd9064 3164 Error *local_err = NULL;
71ad61d3
AF		 3165 int64_t value;
3166
51e72bc1 3167 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3168 if (local_err) {
3169 error_propagate(errp, local_err);
71ad61d3
AF		 3170 return;
3171 }
3172 if (value < min || value > max) {
c6bd8c70
MA		 3173 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3174 name ? name : "null", value, min, max);
71ad61d3
AF		 3175 return;
3176 }
3177
ed5e1ec3 3178 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 3179 if (value > 0x0f) {
3180 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 3181 } else {
71ad61d3 3182 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 3183 }
3184}
3185
d7bce999
EB		 3186static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
3187 const char *name, void *opaque,
3188 Error **errp)
67e30c83
AF		 3189{
3190 X86CPU *cpu = X86_CPU(obj);
3191 CPUX86State *env = &cpu->env;
3192 int64_t value;
3193
3194 value = (env->cpuid_version >> 4) & 0xf;
3195 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 3196 visit_type_int(v, name, &value, errp);
67e30c83
AF		 3197}
3198
d7bce999
EB		 3199static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
3200 const char *name, void *opaque,
3201 Error **errp)
b0704cbd 3202{
c5291a4f
AF		 3203 X86CPU *cpu = X86_CPU(obj);
3204 CPUX86State *env = &cpu->env;
3205 const int64_t min = 0;
3206 const int64_t max = 0xff;
65cd9064 3207 Error *local_err = NULL;
c5291a4f
AF		 3208 int64_t value;
3209
51e72bc1 3210 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3211 if (local_err) {
3212 error_propagate(errp, local_err);
c5291a4f
AF		 3213 return;
3214 }
3215 if (value < min || value > max) {
c6bd8c70
MA		 3216 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3217 name ? name : "null", value, min, max);
c5291a4f
AF		 3218 return;
3219 }
3220
b0704cbd 3221 env->cpuid_version &= ~0xf00f0;
c5291a4f 3222 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 3223}
3224
35112e41 3225static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 3226 const char *name, void *opaque,
35112e41
AF		 3227 Error **errp)
3228{
3229 X86CPU *cpu = X86_CPU(obj);
3230 CPUX86State *env = &cpu->env;
3231 int64_t value;
3232
3233 value = env->cpuid_version & 0xf;
51e72bc1 3234 visit_type_int(v, name, &value, errp);
35112e41
AF		 3235}
3236
036e2222 3237static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 3238 const char *name, void *opaque,
036e2222 3239 Error **errp)
38c3dc46 3240{
036e2222
AF		 3241 X86CPU *cpu = X86_CPU(obj);
3242 CPUX86State *env = &cpu->env;
3243 const int64_t min = 0;
3244 const int64_t max = 0xf;
65cd9064 3245 Error *local_err = NULL;
036e2222
AF		 3246 int64_t value;
3247
51e72bc1 3248 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3249 if (local_err) {
3250 error_propagate(errp, local_err);
036e2222
AF		 3251 return;
3252 }
3253 if (value < min || value > max) {
c6bd8c70
MA		 3254 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3255 name ? name : "null", value, min, max);
036e2222
AF		 3256 return;
3257 }
3258
38c3dc46 3259 env->cpuid_version &= ~0xf;
036e2222 3260 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 3261}
3262
d480e1af
AF		 3263static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
3264{
3265 X86CPU *cpu = X86_CPU(obj);
3266 CPUX86State *env = &cpu->env;
3267 char *value;
d480e1af 3268
e42a92ae 3269 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 3270 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
3271 env->cpuid_vendor3);
d480e1af
AF		 3272 return value;
3273}
3274
3275static void x86_cpuid_set_vendor(Object *obj, const char *value,
3276 Error **errp)
3277{
3278 X86CPU *cpu = X86_CPU(obj);
3279 CPUX86State *env = &cpu->env;
3280 int i;
3281
9df694ee 3282 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 3283 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 3284 return;
3285 }
3286
3287 env->cpuid_vendor1 = 0;
3288 env->cpuid_vendor2 = 0;
3289 env->cpuid_vendor3 = 0;
3290 for (i = 0; i < 4; i++) {
3291 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
3292 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
3293 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
3294 }
d480e1af
AF		 3295}
3296
63e886eb
AF		 3297static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
3298{
3299 X86CPU *cpu = X86_CPU(obj);
3300 CPUX86State *env = &cpu->env;
3301 char *value;
3302 int i;
3303
3304 value = g_malloc(48 + 1);
3305 for (i = 0; i < 48; i++) {
3306 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
3307 }
3308 value[48] = '\0';
3309 return value;
3310}
3311
938d4c25
AF		 3312static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
3313 Error **errp)
dcce6675 3314{
938d4c25
AF		 3315 X86CPU *cpu = X86_CPU(obj);
3316 CPUX86State *env = &cpu->env;
dcce6675
AF		 3317 int c, len, i;
3318
3319 if (model_id == NULL) {
3320 model_id = "";
3321 }
3322 len = strlen(model_id);
d0a6acf4 3323 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 3324 for (i = 0; i < 48; i++) {
3325 if (i >= len) {
3326 c = '\0';
3327 } else {
3328 c = (uint8_t)model_id[i];
3329 }
3330 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
3331 }
3332}
3333
d7bce999
EB		 3334static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
3335 void *opaque, Error **errp)
89e48965
AF		 3336{
3337 X86CPU *cpu = X86_CPU(obj);
3338 int64_t value;
3339
3340 value = cpu->env.tsc_khz * 1000;
51e72bc1 3341 visit_type_int(v, name, &value, errp);
89e48965
AF		 3342}
3343
d7bce999
EB		 3344static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
3345 void *opaque, Error **errp)
89e48965
AF		 3346{
3347 X86CPU *cpu = X86_CPU(obj);
3348 const int64_t min = 0;
2e84849a 3349 const int64_t max = INT64_MAX;
65cd9064 3350 Error *local_err = NULL;
89e48965
AF		 3351 int64_t value;
3352
51e72bc1 3353 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3354 if (local_err) {
3355 error_propagate(errp, local_err);
89e48965
AF		 3356 return;
3357 }
3358 if (value < min || value > max) {
c6bd8c70
MA		 3359 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3360 name ? name : "null", value, min, max);
89e48965
AF		 3361 return;
3362 }
3363
36f96c4b 3364 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 3365}
3366
7e5292b5 3367/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 3368static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
3369 const char *name, void *opaque,
3370 Error **errp)
8e8aba50 3371{
7e5292b5 3372 uint32_t *array = (uint32_t *)opaque;
8e8aba50 3373 FeatureWord w;
8e8aba50
EH		 3374 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
3375 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
3376 X86CPUFeatureWordInfoList *list = NULL;
3377
3378 for (w = 0; w < FEATURE_WORDS; w++) {
3379 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 3380 /*
3381 * We didn't have MSR features when "feature-words" was
3382 * introduced. Therefore skipped other type entries.
3383 */
3384 if (wi->type != CPUID_FEATURE_WORD) {
3385 continue;
3386 }
8e8aba50 3387 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 3388 qwi->cpuid_input_eax = wi->cpuid.eax;
3389 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
3390 qwi->cpuid_input_ecx = wi->cpuid.ecx;
3391 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 3392 qwi->features = array[w];
8e8aba50
EH		 3393
3394 /* List will be in reverse order, but order shouldn't matter */
3395 list_entries[w].next = list;
3396 list_entries[w].value = &word_infos[w];
3397 list = &list_entries[w];
3398 }
3399
6b62d961 3400 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 3401}
3402
d7bce999
EB		 3403static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3404 void *opaque, Error **errp)
c8f0f88e
IM		 3405{
3406 X86CPU *cpu = X86_CPU(obj);
3407 int64_t value = cpu->hyperv_spinlock_attempts;
3408
51e72bc1 3409 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 3410}
3411
d7bce999
EB		 3412static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3413 void *opaque, Error **errp)
c8f0f88e
IM		 3414{
3415 const int64_t min = 0xFFF;
3416 const int64_t max = UINT_MAX;
3417 X86CPU *cpu = X86_CPU(obj);
3418 Error *err = NULL;
3419 int64_t value;
3420
51e72bc1 3421 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 3422 if (err) {
3423 error_propagate(errp, err);
3424 return;
3425 }
3426
3427 if (value < min || value > max) {
3428 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 3429 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
3430 object_get_typename(obj), name ? name : "null",
3431 value, min, max);
c8f0f88e
IM		 3432 return;
3433 }
3434 cpu->hyperv_spinlock_attempts = value;
3435}
3436
1b6b7d10 3437static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 3438 .name = "int",
3439 .get = x86_get_hv_spinlocks,
3440 .set = x86_set_hv_spinlocks,
3441};
3442
72ac2e87
IM		 3443/* Convert all '_' in a feature string option name to '-', to make feature
3444 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3445 */
3446static inline void feat2prop(char *s)
3447{
3448 while ((s = strchr(s, '_'))) {
3449 *s = '-';
3450 }
3451}
3452
b54c9377
EH		 3453/* Return the feature property name for a feature flag bit */
3454static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
3455{
3456 /* XSAVE components are automatically enabled by other features,
3457 * so return the original feature name instead
3458 */
3459 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
3460 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
3461
3462 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
3463 x86_ext_save_areas[comp].bits) {
3464 w = x86_ext_save_areas[comp].feature;
3465 bitnr = ctz32(x86_ext_save_areas[comp].bits);
3466 }
3467 }
3468
3469 assert(bitnr < 32);
3470 assert(w < FEATURE_WORDS);
3471 return feature_word_info[w].feat_names[bitnr];
3472}
3473
dc15c051
IM		 3474/* Compatibily hack to maintain legacy +-feat semantic,
3475 * where +-feat overwrites any feature set by
3476 * feat=on|feat even if the later is parsed after +-feat
3477 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3478 */
2fae0d96 3479static GList *plus_features, *minus_features;
dc15c051 3480
83a00f60
EH		 3481static gint compare_string(gconstpointer a, gconstpointer b)
3482{
3483 return g_strcmp0(a, b);
3484}
3485
8f961357
EH		 3486/* Parse "+feature,-feature,feature=foo" CPU feature string
3487 */
62a48a2a 3488static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 3489 Error **errp)
8f961357 3490{
8f961357 3491 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 3492 static bool cpu_globals_initialized;
83a00f60 3493 bool ambiguous = false;
62a48a2a
IM		 3494
3495 if (cpu_globals_initialized) {
3496 return;
3497 }
3498 cpu_globals_initialized = true;
8f961357 3499
f6750e95
EH		 3500 if (!features) {
3501 return;
3502 }
3503
3504 for (featurestr = strtok(features, ",");
685479bd 3505 featurestr;
f6750e95
EH		 3506 featurestr = strtok(NULL, ",")) {
3507 const char *name;
3508 const char *val = NULL;
3509 char *eq = NULL;
cf2887c9 3510 char num[32];
62a48a2a 3511 GlobalProperty *prop;
c6dc6f63 3512
f6750e95 3513 /* Compatibility syntax: */
c6dc6f63 3514 if (featurestr[0] == '+') {
2fae0d96
EH		 3515 plus_features = g_list_append(plus_features,
3516 g_strdup(featurestr + 1));
f6750e95 3517 continue;
c6dc6f63 3518 } else if (featurestr[0] == '-') {
2fae0d96
EH		 3519 minus_features = g_list_append(minus_features,
3520 g_strdup(featurestr + 1));
f6750e95
EH		 3521 continue;
3522 }
3523
3524 eq = strchr(featurestr, '=');
3525 if (eq) {
3526 *eq++ = 0;
3527 val = eq;
c6dc6f63 3528 } else {
f6750e95 3529 val = "on";
a91987c2 3530 }
f6750e95
EH		 3531
3532 feat2prop(featurestr);
3533 name = featurestr;
3534
83a00f60 3535 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 3536 warn_report("Ambiguous CPU model string. "
3537 "Don't mix both \"+%s\" and \"%s=%s\"",
3538 name, name, val);
83a00f60
EH		 3539 ambiguous = true;
3540 }
3541 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 3542 warn_report("Ambiguous CPU model string. "
3543 "Don't mix both \"-%s\" and \"%s=%s\"",
3544 name, name, val);
83a00f60
EH		 3545 ambiguous = true;
3546 }
3547
f6750e95
EH		 3548 /* Special case: */
3549 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 3550 int ret;
f46bfdbf 3551 uint64_t tsc_freq;
f6750e95 3552
f17fd4fd 3553 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 3554 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 3555 error_setg(errp, "bad numerical value %s", val);
3556 return;
3557 }
3558 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3559 val = num;
3560 name = "tsc-frequency";
c6dc6f63 3561 }
f6750e95 3562
62a48a2a
IM		 3563 prop = g_new0(typeof(*prop), 1);
3564 prop->driver = typename;
3565 prop->property = g_strdup(name);
3566 prop->value = g_strdup(val);
3567 prop->errp = &error_fatal;
3568 qdev_prop_register_global(prop);
f6750e95
EH		 3569 }
3570
83a00f60 3571 if (ambiguous) {
3dc6f869
AF		 3572 warn_report("Compatibility of ambiguous CPU model "
3573 "strings won't be kept on future QEMU versions");
83a00f60 3574 }
c6dc6f63
AP		 3575}
3576
b8d834a0 3577static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 3578static int x86_cpu_filter_features(X86CPU *cpu);
3579
3580/* Check for missing features that may prevent the CPU class from
3581 * running using the current machine and accelerator.
3582 */
3583static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3584 strList **missing_feats)
3585{
3586 X86CPU *xc;
3587 FeatureWord w;
3588 Error *err = NULL;
3589 strList **next = missing_feats;
3590
d6dcc558 3591 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 3592 strList *new = g_new0(strList, 1);
3c254ab8 3593 new->value = g_strdup("kvm");
b54c9377
EH		 3594 *missing_feats = new;
3595 return;
3596 }
3597
3598 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3599
b8d834a0 3600 x86_cpu_expand_features(xc, &err);
b54c9377 3601 if (err) {
b8d834a0 3602 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 3603 * but in case it does, just report the model as not
3604 * runnable at all using the "type" property.
3605 */
3606 strList *new = g_new0(strList, 1);
3607 new->value = g_strdup("type");
3608 *next = new;
3609 next = &new->next;
3610 }
3611
3612 x86_cpu_filter_features(xc);
3613
3614 for (w = 0; w < FEATURE_WORDS; w++) {
3615 uint32_t filtered = xc->filtered_features[w];
3616 int i;
3617 for (i = 0; i < 32; i++) {
3618 if (filtered & (1UL << i)) {
3619 strList *new = g_new0(strList, 1);
3620 new->value = g_strdup(x86_cpu_feature_name(w, i));
3621 *next = new;
3622 next = &new->next;
3623 }
3624 }
3625 }
3626
3627 object_unref(OBJECT(xc));
3628}
3629
8c3329e5 3630/* Print all cpuid feature names in featureset
c6dc6f63 3631 */
cc643b1e 3632static void listflags(FILE *f, fprintf_function print, GList *features)
0856579c 3633{
cc643b1e
DB		 3634 size_t len = 0;
3635 GList *tmp;
3636
3637 for (tmp = features; tmp; tmp = tmp->next) {
3638 const char *name = tmp->data;
3639 if ((len + strlen(name) + 1) >= 75) {
3640 print(f, "\n");
3641 len = 0;
c6dc6f63 3642 }
cc643b1e
DB		 3643 print(f, "%s%s", len == 0 ? " " : " ", name);
3644 len += strlen(name) + 1;
8c3329e5 3645 }
cc643b1e 3646 print(f, "\n");
c6dc6f63
AP		 3647}
3648
f48c8837 3649/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 3650static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3651{
3652 ObjectClass *class_a = (ObjectClass *)a;
3653 ObjectClass *class_b = (ObjectClass *)b;
3654 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3655 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b
DB		 3656 char *name_a, *name_b;
3657 int ret;
ee465a3e 3658
f48c8837 3659 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 3660 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 3661 } else {
c7dbff4b
DB		 3662 name_a = x86_cpu_class_get_model_name(cc_a);
3663 name_b = x86_cpu_class_get_model_name(cc_b);
3664 ret = strcmp(name_a, name_b);
3665 g_free(name_a);
3666 g_free(name_b);
ee465a3e 3667 }
c7dbff4b 3668 return ret;
ee465a3e
EH		 3669}
3670
3671static GSList *get_sorted_cpu_model_list(void)
3672{
3673 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3674 list = g_slist_sort(list, x86_cpu_list_compare);
3675 return list;
3676}
3677
3678static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3679{
3680 ObjectClass *oc = data;
3681 X86CPUClass *cc = X86_CPU_CLASS(oc);
3682 CPUListState *s = user_data;
3683 char *name = x86_cpu_class_get_model_name(cc);
3684 const char *desc = cc->model_description;
0bacd8b3 3685 if (!desc && cc->cpu_def) {
ee465a3e
EH		 3686 desc = cc->cpu_def->model_id;
3687 }
3688
081492ca 3689 (*s->cpu_fprintf)(s->file, "x86 %-20s %-48s\n",
ee465a3e
EH		 3690 name, desc);
3691 g_free(name);
3692}
3693
3694/* list available CPU models and flags */
e916cbf8 3695void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 3696{
cc643b1e 3697 int i, j;
ee465a3e
EH		 3698 CPUListState s = {
3699 .file = f,
3700 .cpu_fprintf = cpu_fprintf,
3701 };
3702 GSList *list;
cc643b1e 3703 GList *names = NULL;
c6dc6f63 3704
ee465a3e
EH		 3705 (*cpu_fprintf)(f, "Available CPUs:\n");
3706 list = get_sorted_cpu_model_list();
3707 g_slist_foreach(list, x86_cpu_list_entry, &s);
3708 g_slist_free(list);
21ad7789 3709
cc643b1e 3710 names = NULL;
3af60be2
JK		 3711 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3712 FeatureWordInfo *fw = &feature_word_info[i];
cc643b1e
DB		 3713 for (j = 0; j < 32; j++) {
3714 if (fw->feat_names[j]) {
3715 names = g_list_append(names, (gpointer)fw->feat_names[j]);
3716 }
3717 }
3af60be2 3718 }
cc643b1e
DB		 3719
3720 names = g_list_sort(names, (GCompareFunc)strcmp);
3721
3722 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3723 listflags(f, cpu_fprintf, names);
3724 (*cpu_fprintf)(f, "\n");
3725 g_list_free(names);
c6dc6f63
AP		 3726}
3727
ee465a3e
EH		 3728static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3729{
3730 ObjectClass *oc = data;
3731 X86CPUClass *cc = X86_CPU_CLASS(oc);
3732 CpuDefinitionInfoList **cpu_list = user_data;
3733 CpuDefinitionInfoList *entry;
3734 CpuDefinitionInfo *info;
3735
3736 info = g_malloc0(sizeof(*info));
3737 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 3738 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3739 info->has_unavailable_features = true;
8ed877b7 3740 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 3741 info->migration_safe = cc->migration_safe;
3742 info->has_migration_safe = true;
5adbed30 3743 info->q_static = cc->static_model;
ee465a3e
EH		 3744
3745 entry = g_malloc0(sizeof(*entry));
3746 entry->value = info;
3747 entry->next = *cpu_list;
3748 *cpu_list = entry;
3749}
3750
76b64a7a 3751CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 3752{
3753 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 3754 GSList *list = get_sorted_cpu_model_list();
3755 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3756 g_slist_free(list);
e3966126
AL		 3757 return cpu_list;
3758}
3759
84f1b92f
EH		 3760static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3761 bool migratable_only)
27418adf
EH		 3762{
3763 FeatureWordInfo *wi = &feature_word_info[w];
07585923 3764 uint32_t r = 0;
27418adf 3765
fefb41bf 3766 if (kvm_enabled()) {
07585923
RH		 3767 switch (wi->type) {
3768 case CPUID_FEATURE_WORD:
3769 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
3770 wi->cpuid.ecx,
3771 wi->cpuid.reg);
3772 break;
3773 case MSR_FEATURE_WORD:
d86f9636
RH		 3774 r = kvm_arch_get_supported_msr_feature(kvm_state,
3775 wi->msr.index);
07585923
RH		 3776 break;
3777 }
d6dcc558 3778 } else if (hvf_enabled()) {
07585923
RH		 3779 if (wi->type != CPUID_FEATURE_WORD) {
3780 return 0;
3781 }
3782 r = hvf_get_supported_cpuid(wi->cpuid.eax,
3783 wi->cpuid.ecx,
3784 wi->cpuid.reg);
fefb41bf 3785 } else if (tcg_enabled()) {
84f1b92f 3786 r = wi->tcg_features;
fefb41bf
EH		 3787 } else {
3788 return ~0;
3789 }
84f1b92f
EH		 3790 if (migratable_only) {
3791 r &= x86_cpu_get_migratable_flags(w);
3792 }
3793 return r;
27418adf
EH		 3794}
3795
8ca30e86
EH		 3796static void x86_cpu_report_filtered_features(X86CPU *cpu)
3797{
3798 FeatureWord w;
3799
3800 for (w = 0; w < FEATURE_WORDS; w++) {
3801 report_unavailable_features(w, cpu->filtered_features[w]);
3802 }
3803}
3804
5114e842
EH		 3805static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3806{
3807 PropValue *pv;
3808 for (pv = props; pv->prop; pv++) {
3809 if (!pv->value) {
3810 continue;
3811 }
3812 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3813 &error_abort);
3814 }
3815}
3816
f99fd7ca 3817/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 3818 */
d940ee9b 3819static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 3820{
61dcd775 3821 CPUX86State *env = &cpu->env;
74f54bc4
EH		 3822 const char *vendor;
3823 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 3824 FeatureWord w;
c6dc6f63 3825
f99fd7ca
EH		 3826 /*NOTE: any property set by this function should be returned by
3827 * x86_cpu_static_props(), so static expansion of
3828 * query-cpu-model-expansion is always complete.
3829 */
3830
c39c0edf 3831 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 3832 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3833 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 3834
2d64255b
AF		 3835 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3836 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3837 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 3838 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 3839 for (w = 0; w < FEATURE_WORDS; w++) {
3840 env->features[w] = def->features[w];
3841 }
82beb536 3842
a9f27ea9
EH		 3843 /* legacy-cache defaults to 'off' if CPU model provides cache info */
3844 cpu->legacy_cache = !def->cache_info;
ab8f992e 3845
9576de75 3846 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 3847 /* TODO: in-kernel irqchip for hvf */
82beb536 3848 if (kvm_enabled()) {
492a4c94
LT		 3849 if (!kvm_irqchip_in_kernel()) {
3850 x86_cpu_change_kvm_default("x2apic", "off");
3851 }
3852
5114e842 3853 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 3854 } else if (tcg_enabled()) {
3855 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 3856 }
5fcca9ff 3857
82beb536 3858 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 3859
3860 /* sysenter isn't supported in compatibility mode on AMD,
3861 * syscall isn't supported in compatibility mode on Intel.
3862 * Normally we advertise the actual CPU vendor, but you can
3863 * override this using the 'vendor' property if you want to use
3864 * KVM's sysenter/syscall emulation in compatibility mode and
3865 * when doing cross vendor migration
3866 */
74f54bc4 3867 vendor = def->vendor;
d6dcc558 3868 if (accel_uses_host_cpuid()) {
7c08db30
EH		 3869 uint32_t ebx = 0, ecx = 0, edx = 0;
3870 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3871 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3872 vendor = host_vendor;
3873 }
3874
3875 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3876
c6dc6f63
AP		 3877}
3878
f99fd7ca
EH		 3879/* Return a QDict containing keys for all properties that can be included
3880 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3881 * must be included in the dictionary.
3882 */
3883static QDict *x86_cpu_static_props(void)
3884{
3885 FeatureWord w;
3886 int i;
3887 static const char *props[] = {
3888 "min-level",
3889 "min-xlevel",
3890 "family",
3891 "model",
3892 "stepping",
3893 "model-id",
3894 "vendor",
3895 "lmce",
3896 NULL,
3897 };
3898 static QDict *d;
3899
3900 if (d) {
3901 return d;
3902 }
3903
3904 d = qdict_new();
3905 for (i = 0; props[i]; i++) {
0f9afc2a 3906 qdict_put_null(d, props[i]);
f99fd7ca
EH		 3907 }
3908
3909 for (w = 0; w < FEATURE_WORDS; w++) {
3910 FeatureWordInfo *fi = &feature_word_info[w];
3911 int bit;
3912 for (bit = 0; bit < 32; bit++) {
3913 if (!fi->feat_names[bit]) {
3914 continue;
3915 }
0f9afc2a 3916 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 3917 }
3918 }
3919
3920 return d;
3921}
3922
3923/* Add an entry to @props dict, with the value for property. */
3924static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
3925{
3926 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
3927 &error_abort);
3928
3929 qdict_put_obj(props, prop, value);
3930}
3931
3932/* Convert CPU model data from X86CPU object to a property dictionary
3933 * that can recreate exactly the same CPU model.
3934 */
3935static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
3936{
3937 QDict *sprops = x86_cpu_static_props();
3938 const QDictEntry *e;
3939
3940 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
3941 const char *prop = qdict_entry_key(e);
3942 x86_cpu_expand_prop(cpu, props, prop);
3943 }
3944}
3945
b8097deb
EH		 3946/* Convert CPU model data from X86CPU object to a property dictionary
3947 * that can recreate exactly the same CPU model, including every
3948 * writeable QOM property.
3949 */
3950static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
3951{
3952 ObjectPropertyIterator iter;
3953 ObjectProperty *prop;
3954
3955 object_property_iter_init(&iter, OBJECT(cpu));
3956 while ((prop = object_property_iter_next(&iter))) {
3957 /* skip read-only or write-only properties */
3958 if (!prop->get || !prop->set) {
3959 continue;
3960 }
3961
3962 /* "hotplugged" is the only property that is configurable
3963 * on the command-line but will be set differently on CPUs
3964 * created using "-cpu ... -smp ..." and by CPUs created
3965 * on the fly by x86_cpu_from_model() for querying. Skip it.
3966 */
3967 if (!strcmp(prop->name, "hotplugged")) {
3968 continue;
3969 }
3970 x86_cpu_expand_prop(cpu, props, prop->name);
3971 }
3972}
3973
f99fd7ca
EH		 3974static void object_apply_props(Object *obj, QDict *props, Error **errp)
3975{
3976 const QDictEntry *prop;
3977 Error *err = NULL;
3978
3979 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
3980 object_property_set_qobject(obj, qdict_entry_value(prop),
3981 qdict_entry_key(prop), &err);
3982 if (err) {
3983 break;
3984 }
3985 }
3986
3987 error_propagate(errp, err);
3988}
3989
3990/* Create X86CPU object according to model+props specification */
3991static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
3992{
3993 X86CPU *xc = NULL;
3994 X86CPUClass *xcc;
3995 Error *err = NULL;
3996
3997 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
3998 if (xcc == NULL) {
3999 error_setg(&err, "CPU model '%s' not found", model);
4000 goto out;
4001 }
4002
4003 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
4004 if (props) {
4005 object_apply_props(OBJECT(xc), props, &err);
4006 if (err) {
4007 goto out;
4008 }
4009 }
4010
4011 x86_cpu_expand_features(xc, &err);
4012 if (err) {
4013 goto out;
4014 }
4015
4016out:
4017 if (err) {
4018 error_propagate(errp, err);
4019 object_unref(OBJECT(xc));
4020 xc = NULL;
4021 }
4022 return xc;
4023}
4024
4025CpuModelExpansionInfo *
4026arch_query_cpu_model_expansion(CpuModelExpansionType type,
4027 CpuModelInfo *model,
4028 Error **errp)
4029{
4030 X86CPU *xc = NULL;
4031 Error *err = NULL;
4032 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
4033 QDict *props = NULL;
4034 const char *base_name;
4035
4036 xc = x86_cpu_from_model(model->name,
4037 model->has_props ?
7dc847eb 4038 qobject_to(QDict, model->props) :
f99fd7ca
EH		 4039 NULL, &err);
4040 if (err) {
4041 goto out;
4042 }
4043
b8097deb 4044 props = qdict_new();
e38bf612
EH		 4045 ret->model = g_new0(CpuModelInfo, 1);
4046 ret->model->props = QOBJECT(props);
4047 ret->model->has_props = true;
f99fd7ca
EH		 4048
4049 switch (type) {
4050 case CPU_MODEL_EXPANSION_TYPE_STATIC:
4051 /* Static expansion will be based on "base" only */
4052 base_name = "base";
b8097deb 4053 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 4054 break;
4055 case CPU_MODEL_EXPANSION_TYPE_FULL:
4056 /* As we don't return every single property, full expansion needs
4057 * to keep the original model name+props, and add extra
4058 * properties on top of that.
4059 */
4060 base_name = model->name;
b8097deb 4061 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 4062 break;
4063 default:
4064 error_setg(&err, "Unsupportted expansion type");
4065 goto out;
4066 }
4067
f99fd7ca
EH		 4068 x86_cpu_to_dict(xc, props);
4069
f99fd7ca 4070 ret->model->name = g_strdup(base_name);
f99fd7ca
EH		 4071
4072out:
4073 object_unref(OBJECT(xc));
4074 if (err) {
4075 error_propagate(errp, err);
4076 qapi_free_CpuModelExpansionInfo(ret);
4077 ret = NULL;
4078 }
4079 return ret;
4080}
4081
00fcd100
AB		 4082static gchar *x86_gdb_arch_name(CPUState *cs)
4083{
4084#ifdef TARGET_X86_64
4085 return g_strdup("i386:x86-64");
4086#else
4087 return g_strdup("i386");
4088#endif
4089}
4090
d940ee9b
EH		 4091static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
4092{
4093 X86CPUDefinition *cpudef = data;
4094 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4095
4096 xcc->cpu_def = cpudef;
bd72159d 4097 xcc->migration_safe = true;
d940ee9b
EH		 4098}
4099
4100static void x86_register_cpudef_type(X86CPUDefinition *def)
4101{
4102 char *typename = x86_cpu_type_name(def->name);
4103 TypeInfo ti = {
4104 .name = typename,
4105 .parent = TYPE_X86_CPU,
4106 .class_init = x86_cpu_cpudef_class_init,
4107 .class_data = def,
4108 };
4109
2a923a29
EH		 4110 /* AMD aliases are handled at runtime based on CPUID vendor, so
4111 * they shouldn't be set on the CPU model table.
4112 */
4113 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 4114 /* catch mistakes instead of silently truncating model_id when too long */
4115 assert(def->model_id && strlen(def->model_id) <= 48);
4116
2a923a29 4117
d940ee9b
EH		 4118 type_register(&ti);
4119 g_free(typename);
4120}
4121
c6dc6f63 4122#if !defined(CONFIG_USER_ONLY)
c6dc6f63 4123
0e26b7b8
BS		 4124void cpu_clear_apic_feature(CPUX86State *env)
4125{
0514ef2f 4126 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 4127}
4128
c6dc6f63
AP		 4129#endif /* !CONFIG_USER_ONLY */
4130
c6dc6f63
AP		 4131void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
4132 uint32_t *eax, uint32_t *ebx,
4133 uint32_t *ecx, uint32_t *edx)
4134{
a60f24b5
AF		 4135 X86CPU *cpu = x86_env_get_cpu(env);
4136 CPUState *cs = CPU(cpu);
14c985cf 4137 uint32_t pkg_offset;
4ed3d478 4138 uint32_t limit;
1ce36bfe 4139 uint32_t signature[3];
a60f24b5 4140
4ed3d478
DB		 4141 /* Calculate & apply limits for different index ranges */
4142 if (index >= 0xC0000000) {
4143 limit = env->cpuid_xlevel2;
4144 } else if (index >= 0x80000000) {
4145 limit = env->cpuid_xlevel;
1ce36bfe
DB		 4146 } else if (index >= 0x40000000) {
4147 limit = 0x40000001;
c6dc6f63 4148 } else {
4ed3d478
DB		 4149 limit = env->cpuid_level;
4150 }
4151
4152 if (index > limit) {
4153 /* Intel documentation states that invalid EAX input will
4154 * return the same information as EAX=cpuid_level
4155 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
4156 */
4157 index = env->cpuid_level;
c6dc6f63
AP		 4158 }
4159
4160 switch(index) {
4161 case 0:
4162 *eax = env->cpuid_level;
5eb2f7a4
EH		 4163 *ebx = env->cpuid_vendor1;
4164 *edx = env->cpuid_vendor2;
4165 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 4166 break;
4167 case 1:
4168 *eax = env->cpuid_version;
7e72a45c
EH		 4169 *ebx = (cpu->apic_id << 24) |
4170 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 4171 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 4172 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
4173 *ecx |= CPUID_EXT_OSXSAVE;
4174 }
0514ef2f 4175 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 4176 if (cs->nr_cores * cs->nr_threads > 1) {
4177 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 4178 *edx |= CPUID_HT;
c6dc6f63
AP		 4179 }
4180 break;
4181 case 2:
4182 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 4183 if (cpu->cache_info_passthrough) {
4184 host_cpuid(index, 0, eax, ebx, ecx, edx);
4185 break;
4186 }
5e891bf8 4187 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 4188 *ebx = 0;
14c985cf
LM		 4189 if (!cpu->enable_l3_cache) {
4190 *ecx = 0;
4191 } else {
a9f27ea9 4192 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 4193 }
a9f27ea9
EH		 4194 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
4195 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
4196 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 4197 break;
4198 case 4:
4199 /* cache info: needed for Core compatibility */
787aaf57
BC		 4200 if (cpu->cache_info_passthrough) {
4201 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 4202 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 4203 *eax &= ~0xFC000000;
7e3482f8
EH		 4204 if ((*eax & 31) && cs->nr_cores > 1) {
4205 *eax |= (cs->nr_cores - 1) << 26;
4206 }
c6dc6f63 4207 } else {
2f7a21c4 4208 *eax = 0;
76c2975a 4209 switch (count) {
c6dc6f63 4210 case 0: /* L1 dcache info */
a9f27ea9
EH		 4211 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
4212 1, cs->nr_cores,
7e3482f8 4213 eax, ebx, ecx, edx);
c6dc6f63
AP		 4214 break;
4215 case 1: /* L1 icache info */
a9f27ea9
EH		 4216 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
4217 1, cs->nr_cores,
7e3482f8 4218 eax, ebx, ecx, edx);
c6dc6f63
AP		 4219 break;
4220 case 2: /* L2 cache info */
a9f27ea9
EH		 4221 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
4222 cs->nr_threads, cs->nr_cores,
7e3482f8 4223 eax, ebx, ecx, edx);
c6dc6f63 4224 break;
14c985cf 4225 case 3: /* L3 cache info */
7e3482f8
EH		 4226 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4227 if (cpu->enable_l3_cache) {
a9f27ea9
EH		 4228 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
4229 (1 << pkg_offset), cs->nr_cores,
7e3482f8 4230 eax, ebx, ecx, edx);
14c985cf
LM		 4231 break;
4232 }
7e3482f8 4233 /* fall through */
c6dc6f63 4234 default: /* end of info */
7e3482f8 4235 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 4236 break;
76c2975a
PB		 4237 }
4238 }
c6dc6f63
AP		 4239 break;
4240 case 5:
2266d443
MT		 4241 /* MONITOR/MWAIT Leaf */
4242 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
4243 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
4244 *ecx = cpu->mwait.ecx; /* flags */
4245 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 4246 break;
4247 case 6:
4248 /* Thermal and Power Leaf */
28b8e4d0 4249 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 4250 *ebx = 0;
4251 *ecx = 0;
4252 *edx = 0;
4253 break;
f7911686 4254 case 7:
13526728
EH		 4255 /* Structured Extended Feature Flags Enumeration Leaf */
4256 if (count == 0) {
4257 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 4258 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 4259 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 4260 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
4261 *ecx |= CPUID_7_0_ECX_OSPKE;
4262 }
95ea69fb 4263 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 4264 } else {
4265 *eax = 0;
4266 *ebx = 0;
4267 *ecx = 0;
4268 *edx = 0;
4269 }
4270 break;
c6dc6f63
AP		 4271 case 9:
4272 /* Direct Cache Access Information Leaf */
4273 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
4274 *ebx = 0;
4275 *ecx = 0;
4276 *edx = 0;
4277 break;
4278 case 0xA:
4279 /* Architectural Performance Monitoring Leaf */
9337e3b6 4280 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 4281 KVMState *s = cs->kvm_state;
a0fa8208
GN		 4282
4283 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
4284 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
4285 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
4286 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 4287 } else if (hvf_enabled() && cpu->enable_pmu) {
4288 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
4289 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
4290 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
4291 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 4292 } else {
4293 *eax = 0;
4294 *ebx = 0;
4295 *ecx = 0;
4296 *edx = 0;
4297 }
c6dc6f63 4298 break;
5232d00a
RK		 4299 case 0xB:
4300 /* Extended Topology Enumeration Leaf */
4301 if (!cpu->enable_cpuid_0xb) {
4302 *eax = *ebx = *ecx = *edx = 0;
4303 break;
4304 }
4305
4306 *ecx = count & 0xff;
4307 *edx = cpu->apic_id;
4308
4309 switch (count) {
4310 case 0:
eab60fb9
MAL		 4311 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
4312 *ebx = cs->nr_threads;
5232d00a
RK		 4313 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
4314 break;
4315 case 1:
eab60fb9
MAL		 4316 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4317 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 4318 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
4319 break;
4320 default:
4321 *eax = 0;
4322 *ebx = 0;
4323 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
4324 }
4325
4326 assert(!(*eax & ~0x1f));
4327 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
4328 break;
2560f19f 4329 case 0xD: {
51e49430 4330 /* Processor Extended State */
2560f19f
PB		 4331 *eax = 0;
4332 *ebx = 0;
4333 *ecx = 0;
4334 *edx = 0;
19dc85db 4335 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 4336 break;
4337 }
4928cd6d 4338
2560f19f 4339 if (count == 0) {
96193c22
EH		 4340 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
4341 *eax = env->features[FEAT_XSAVE_COMP_LO];
4342 *edx = env->features[FEAT_XSAVE_COMP_HI];
de2e68c9 4343 *ebx = xsave_area_size(env->xcr0);
2560f19f 4344 } else if (count == 1) {
0bb0b2d2 4345 *eax = env->features[FEAT_XSAVE];
f4f1110e 4346 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 4347 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
4348 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 4349 *eax = esa->size;
4350 *ebx = esa->offset;
2560f19f 4351 }
51e49430
SY		 4352 }
4353 break;
2560f19f 4354 }
e37a5c7f
CP		 4355 case 0x14: {
4356 /* Intel Processor Trace Enumeration */
4357 *eax = 0;
4358 *ebx = 0;
4359 *ecx = 0;
4360 *edx = 0;
4361 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
4362 !kvm_enabled()) {
4363 break;
4364 }
4365
4366 if (count == 0) {
4367 *eax = INTEL_PT_MAX_SUBLEAF;
4368 *ebx = INTEL_PT_MINIMAL_EBX;
4369 *ecx = INTEL_PT_MINIMAL_ECX;
4370 } else if (count == 1) {
4371 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
4372 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
4373 }
4374 break;
4375 }
1ce36bfe
DB		 4376 case 0x40000000:
4377 /*
4378 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4379 * set here, but we restrict to TCG none the less.
4380 */
4381 if (tcg_enabled() && cpu->expose_tcg) {
4382 memcpy(signature, "TCGTCGTCGTCG", 12);
4383 *eax = 0x40000001;
4384 *ebx = signature[0];
4385 *ecx = signature[1];
4386 *edx = signature[2];
4387 } else {
4388 *eax = 0;
4389 *ebx = 0;
4390 *ecx = 0;
4391 *edx = 0;
4392 }
4393 break;
4394 case 0x40000001:
4395 *eax = 0;
4396 *ebx = 0;
4397 *ecx = 0;
4398 *edx = 0;
4399 break;
c6dc6f63
AP		 4400 case 0x80000000:
4401 *eax = env->cpuid_xlevel;
4402 *ebx = env->cpuid_vendor1;
4403 *edx = env->cpuid_vendor2;
4404 *ecx = env->cpuid_vendor3;
4405 break;
4406 case 0x80000001:
4407 *eax = env->cpuid_version;
4408 *ebx = 0;
0514ef2f
EH		 4409 *ecx = env->features[FEAT_8000_0001_ECX];
4410 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 4411
4412 /* The Linux kernel checks for the CMPLegacy bit and
4413 * discards multiple thread information if it is set.
cb8d4c8f 4414 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 4415 */
ce3960eb 4416 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 4417 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
4418 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
4419 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 4420 *ecx |= 1 << 1; /* CmpLegacy bit */
4421 }
4422 }
c6dc6f63
AP		 4423 break;
4424 case 0x80000002:
4425 case 0x80000003:
4426 case 0x80000004:
4427 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
4428 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
4429 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
4430 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
4431 break;
4432 case 0x80000005:
4433 /* cache info (L1 cache) */
787aaf57
BC		 4434 if (cpu->cache_info_passthrough) {
4435 host_cpuid(index, 0, eax, ebx, ecx, edx);
4436 break;
4437 }
5e891bf8
EH		 4438 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
4439 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
4440 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
4441 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4442 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
4443 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 4444 break;
4445 case 0x80000006:
4446 /* cache info (L2 cache) */
787aaf57
BC		 4447 if (cpu->cache_info_passthrough) {
4448 host_cpuid(index, 0, eax, ebx, ecx, edx);
4449 break;
4450 }
5e891bf8
EH		 4451 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
4452 (L2_DTLB_2M_ENTRIES << 16) | \
4453 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
4454 (L2_ITLB_2M_ENTRIES);
4455 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
4456 (L2_DTLB_4K_ENTRIES << 16) | \
4457 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
4458 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4459 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
4460 cpu->enable_l3_cache ?
4461 env->cache_info_amd.l3_cache : NULL,
4462 ecx, edx);
c6dc6f63 4463 break;
303752a9
MT		 4464 case 0x80000007:
4465 *eax = 0;
4466 *ebx = 0;
4467 *ecx = 0;
4468 *edx = env->features[FEAT_8000_0007_EDX];
4469 break;
c6dc6f63
AP		 4470 case 0x80000008:
4471 /* virtual & phys address size in low 2 bytes. */
0514ef2f 4472 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 4473 /* 64 bit processor */
4474 *eax = cpu->phys_bits; /* configurable physical bits */
4475 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
4476 *eax |= 0x00003900; /* 57 bits virtual */
4477 } else {
4478 *eax |= 0x00003000; /* 48 bits virtual */
4479 }
c6dc6f63 4480 } else {
af45907a 4481 *eax = cpu->phys_bits;
c6dc6f63 4482 }
1b3420e1 4483 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 4484 *ecx = 0;
4485 *edx = 0;
ce3960eb
AF		 4486 if (cs->nr_cores * cs->nr_threads > 1) {
4487 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 4488 }
4489 break;
4490 case 0x8000000A:
0514ef2f 4491 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 4492 *eax = 0x00000001; /* SVM Revision */
4493 *ebx = 0x00000010; /* nr of ASIDs */
4494 *ecx = 0;
0514ef2f 4495 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 4496 } else {
4497 *eax = 0;
4498 *ebx = 0;
4499 *ecx = 0;
4500 *edx = 0;
4501 }
c6dc6f63 4502 break;
8f4202fb
BM		 4503 case 0x8000001D:
4504 *eax = 0;
4505 switch (count) {
4506 case 0: /* L1 dcache info */
4507 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
4508 eax, ebx, ecx, edx);
4509 break;
4510 case 1: /* L1 icache info */
4511 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
4512 eax, ebx, ecx, edx);
4513 break;
4514 case 2: /* L2 cache info */
4515 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
4516 eax, ebx, ecx, edx);
4517 break;
4518 case 3: /* L3 cache info */
4519 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
4520 eax, ebx, ecx, edx);
4521 break;
4522 default: /* end of info */
4523 *eax = *ebx = *ecx = *edx = 0;
4524 break;
4525 }
4526 break;
ed78467a
BM		 4527 case 0x8000001E:
4528 assert(cpu->core_id <= 255);
4529 encode_topo_cpuid8000001e(cs, cpu,
4530 eax, ebx, ecx, edx);
4531 break;
b3baa152
BW		 4532 case 0xC0000000:
4533 *eax = env->cpuid_xlevel2;
4534 *ebx = 0;
4535 *ecx = 0;
4536 *edx = 0;
4537 break;
4538 case 0xC0000001:
4539 /* Support for VIA CPU's CPUID instruction */
4540 *eax = env->cpuid_version;
4541 *ebx = 0;
4542 *ecx = 0;
0514ef2f 4543 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 4544 break;
4545 case 0xC0000002:
4546 case 0xC0000003:
4547 case 0xC0000004:
4548 /* Reserved for the future, and now filled with zero */
4549 *eax = 0;
4550 *ebx = 0;
4551 *ecx = 0;
4552 *edx = 0;
4553 break;
6cb8f2a6
BS		 4554 case 0x8000001F:
4555 *eax = sev_enabled() ? 0x2 : 0;
4556 *ebx = sev_get_cbit_position();
4557 *ebx |= sev_get_reduced_phys_bits() << 6;
4558 *ecx = 0;
4559 *edx = 0;
4560 break;
c6dc6f63
AP		 4561 default:
4562 /* reserved values: zero */
4563 *eax = 0;
4564 *ebx = 0;
4565 *ecx = 0;
4566 *edx = 0;
4567 break;
4568 }
4569}
5fd2087a
AF		 4570
4571/* CPUClass::reset() */
4572static void x86_cpu_reset(CPUState *s)
4573{
4574 X86CPU *cpu = X86_CPU(s);
4575 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
4576 CPUX86State *env = &cpu->env;
a114d25d
RH		 4577 target_ulong cr4;
4578 uint64_t xcr0;
c1958aea
AF		 4579 int i;
4580
5fd2087a
AF		 4581 xcc->parent_reset(s);
4582
5e992a8e 4583 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 4584
c1958aea
AF		 4585 env->old_exception = -1;
4586
4587 /* init to reset state */
4588
c1958aea
AF		 4589 env->hflags2 |= HF2_GIF_MASK;
4590
4591 cpu_x86_update_cr0(env, 0x60000010);
4592 env->a20_mask = ~0x0;
4593 env->smbase = 0x30000;
e13713db 4594 env->msr_smi_count = 0;
c1958aea
AF		 4595
4596 env->idt.limit = 0xffff;
4597 env->gdt.limit = 0xffff;
4598 env->ldt.limit = 0xffff;
4599 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4600 env->tr.limit = 0xffff;
4601 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4602
4603 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4604 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4605 DESC_R_MASK | DESC_A_MASK);
4606 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4607 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4608 DESC_A_MASK);
4609 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4610 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4611 DESC_A_MASK);
4612 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4613 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4614 DESC_A_MASK);
4615 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4616 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4617 DESC_A_MASK);
4618 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4619 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4620 DESC_A_MASK);
4621
4622 env->eip = 0xfff0;
4623 env->regs[R_EDX] = env->cpuid_version;
4624
4625 env->eflags = 0x2;
4626
4627 /* FPU init */
4628 for (i = 0; i < 8; i++) {
4629 env->fptags[i] = 1;
4630 }
5bde1407 4631 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 4632
4633 env->mxcsr = 0x1f80;
a114d25d
RH		 4634 /* All units are in INIT state. */
4635 env->xstate_bv = 0;
c1958aea
AF		 4636
4637 env->pat = 0x0007040600070406ULL;
4638 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4639
4640 memset(env->dr, 0, sizeof(env->dr));
4641 env->dr[6] = DR6_FIXED_1;
4642 env->dr[7] = DR7_FIXED_1;
b3310ab3 4643 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 4644 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 4645
a114d25d 4646 cr4 = 0;
cfc3b074 4647 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 4648
4649#ifdef CONFIG_USER_ONLY
4650 /* Enable all the features for user-mode. */
4651 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 4652 xcr0 |= XSTATE_SSE_MASK;
a114d25d 4653 }
0f70ed47
PB		 4654 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4655 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 4656 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 4657 xcr0 |= 1ull << i;
4658 }
a114d25d 4659 }
0f70ed47 4660
a114d25d
RH		 4661 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4662 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4663 }
07929f2a
RH		 4664 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4665 cr4 |= CR4_FSGSBASE_MASK;
4666 }
a114d25d
RH		 4667#endif
4668
4669 env->xcr0 = xcr0;
4670 cpu_x86_update_cr4(env, cr4);
0522604b 4671
9db2efd9
AW		 4672 /*
4673 * SDM 11.11.5 requires:
4674 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4675 * - IA32_MTRR_PHYSMASKn.V = 0
4676 * All other bits are undefined. For simplification, zero it all.
4677 */
4678 env->mtrr_deftype = 0;
4679 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4680 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4681
b7394c83
SAGDR		 4682 env->interrupt_injected = -1;
4683 env->exception_injected = -1;
4684 env->nmi_injected = false;
dd673288
IM		 4685#if !defined(CONFIG_USER_ONLY)
4686 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 4687 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 4688
259186a7 4689 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 4690
4691 if (kvm_enabled()) {
4692 kvm_arch_reset_vcpu(cpu);
4693 }
d6dcc558
SAGDR		 4694 else if (hvf_enabled()) {
4695 hvf_reset_vcpu(s);
4696 }
dd673288 4697#endif
5fd2087a
AF		 4698}
4699
dd673288
IM		 4700#ifndef CONFIG_USER_ONLY
4701bool cpu_is_bsp(X86CPU *cpu)
4702{
02e51483 4703 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 4704}
65dee380
IM		 4705
4706/* TODO: remove me, when reset over QOM tree is implemented */
4707static void x86_cpu_machine_reset_cb(void *opaque)
4708{
4709 X86CPU *cpu = opaque;
4710 cpu_reset(CPU(cpu));
4711}
dd673288
IM		 4712#endif
4713
de024815
AF		 4714static void mce_init(X86CPU *cpu)
4715{
4716 CPUX86State *cenv = &cpu->env;
4717 unsigned int bank;
4718
4719 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 4720 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 4721 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 4722 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4723 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 4724 cenv->mcg_ctl = ~(uint64_t)0;
4725 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4726 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4727 }
4728 }
4729}
4730
bdeec802 4731#ifndef CONFIG_USER_ONLY
2f114315 4732APICCommonClass *apic_get_class(void)
bdeec802 4733{
bdeec802
IM		 4734 const char *apic_type = "apic";
4735
d6dcc558 4736 /* TODO: in-kernel irqchip for hvf */
15eafc2e 4737 if (kvm_apic_in_kernel()) {
bdeec802
IM		 4738 apic_type = "kvm-apic";
4739 } else if (xen_enabled()) {
4740 apic_type = "xen-apic";
4741 }
4742
2f114315
RK		 4743 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4744}
4745
4746static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4747{
4748 APICCommonState *apic;
4749 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4750
4751 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 4752
6816b1b3
IM		 4753 object_property_add_child(OBJECT(cpu), "lapic",
4754 OBJECT(cpu->apic_state), &error_abort);
67e55caa 4755 object_unref(OBJECT(cpu->apic_state));
6816b1b3 4756
33d7a288 4757 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 4758 /* TODO: convert to link<> */
02e51483 4759 apic = APIC_COMMON(cpu->apic_state);
60671e58 4760 apic->cpu = cpu;
8d42d2d3 4761 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 4762}
4763
4764static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4765{
8d42d2d3
CF		 4766 APICCommonState *apic;
4767 static bool apic_mmio_map_once;
4768
02e51483 4769 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 4770 return;
4771 }
6e8e2651
MA		 4772 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4773 errp);
8d42d2d3
CF		 4774
4775 /* Map APIC MMIO area */
4776 apic = APIC_COMMON(cpu->apic_state);
4777 if (!apic_mmio_map_once) {
4778 memory_region_add_subregion_overlap(get_system_memory(),
4779 apic->apicbase &
4780 MSR_IA32_APICBASE_BASE,
4781 &apic->io_memory,
4782 0x1000);
4783 apic_mmio_map_once = true;
4784 }
bdeec802 4785}
f809c605
PB		 4786
4787static void x86_cpu_machine_done(Notifier *n, void *unused)
4788{
4789 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4790 MemoryRegion *smram =
4791 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4792
4793 if (smram) {
4794 cpu->smram = g_new(MemoryRegion, 1);
4795 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4796 smram, 0, 1ull << 32);
f8c45c65 4797 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 4798 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4799 }
4800}
d3c64d6a
IM		 4801#else
4802static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4803{
4804}
bdeec802
IM		 4805#endif
4806
11f6fee5
DDAG		 4807/* Note: Only safe for use on x86(-64) hosts */
4808static uint32_t x86_host_phys_bits(void)
4809{
4810 uint32_t eax;
4811 uint32_t host_phys_bits;
4812
4813 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4814 if (eax >= 0x80000008) {
4815 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4816 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4817 * at 23:16 that can specify a maximum physical address bits for
4818 * the guest that can override this value; but I've not seen
4819 * anything with that set.
4820 */
4821 host_phys_bits = eax & 0xff;
4822 } else {
4823 /* It's an odd 64 bit machine that doesn't have the leaf for
4824 * physical address bits; fall back to 36 that's most older
4825 * Intel.
4826 */
4827 host_phys_bits = 36;
4828 }
4829
4830 return host_phys_bits;
4831}
e48638fd 4832
c39c0edf
EH		 4833static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4834{
4835 if (*min < value) {
4836 *min = value;
4837 }
4838}
4839
4840/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4841static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4842{
4843 CPUX86State *env = &cpu->env;
4844 FeatureWordInfo *fi = &feature_word_info[w];
07585923 4845 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 4846 uint32_t region = eax & 0xF0000000;
4847
07585923 4848 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 4849 if (!env->features[w]) {
4850 return;
4851 }
4852
4853 switch (region) {
4854 case 0x00000000:
4855 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4856 break;
4857 case 0x80000000:
4858 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4859 break;
4860 case 0xC0000000:
4861 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4862 break;
4863 }
4864}
4865
2ca8a8be
EH		 4866/* Calculate XSAVE components based on the configured CPU feature flags */
4867static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4868{
4869 CPUX86State *env = &cpu->env;
4870 int i;
96193c22 4871 uint64_t mask;
2ca8a8be
EH		 4872
4873 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4874 return;
4875 }
4876
e3c9022b
EH		 4877 mask = 0;
4878 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 4879 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4880 if (env->features[esa->feature] & esa->bits) {
96193c22 4881 mask |= (1ULL << i);
2ca8a8be
EH		 4882 }
4883 }
4884
96193c22
EH		 4885 env->features[FEAT_XSAVE_COMP_LO] = mask;
4886 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 4887}
4888
b8d834a0
EH		 4889/***** Steps involved on loading and filtering CPUID data
4890 *
4891 * When initializing and realizing a CPU object, the steps
4892 * involved in setting up CPUID data are:
4893 *
4894 * 1) Loading CPU model definition (X86CPUDefinition). This is
4895 * implemented by x86_cpu_load_def() and should be completely
4896 * transparent, as it is done automatically by instance_init.
4897 * No code should need to look at X86CPUDefinition structs
4898 * outside instance_init.
4899 *
4900 * 2) CPU expansion. This is done by realize before CPUID
4901 * filtering, and will make sure host/accelerator data is
4902 * loaded for CPU models that depend on host capabilities
4903 * (e.g. "host"). Done by x86_cpu_expand_features().
4904 *
4905 * 3) CPUID filtering. This initializes extra data related to
4906 * CPUID, and checks if the host supports all capabilities
4907 * required by the CPU. Runnability of a CPU model is
4908 * determined at this step. Done by x86_cpu_filter_features().
4909 *
4910 * Some operations don't require all steps to be performed.
4911 * More precisely:
4912 *
4913 * - CPU instance creation (instance_init) will run only CPU
4914 * model loading. CPU expansion can't run at instance_init-time
4915 * because host/accelerator data may be not available yet.
4916 * - CPU realization will perform both CPU model expansion and CPUID
4917 * filtering, and return an error in case one of them fails.
4918 * - query-cpu-definitions needs to run all 3 steps. It needs
4919 * to run CPUID filtering, as the 'unavailable-features'
4920 * field is set based on the filtering results.
4921 * - The query-cpu-model-expansion QMP command only needs to run
4922 * CPU model loading and CPU expansion. It should not filter
4923 * any CPUID data based on host capabilities.
4924 */
4925
4926/* Expand CPU configuration data, based on configured features
4927 * and host/accelerator capabilities when appropriate.
4928 */
4929static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 4930{
b34d12d1 4931 CPUX86State *env = &cpu->env;
dc15c051 4932 FeatureWord w;
2fae0d96 4933 GList *l;
41f3d4d6 4934 Error *local_err = NULL;
9886e834 4935
d4a606b3
EH		 4936 /*TODO: Now cpu->max_features doesn't overwrite features
4937 * set using QOM properties, and we can convert
dc15c051
IM		 4938 * plus_features & minus_features to global properties
4939 * inside x86_cpu_parse_featurestr() too.
4940 */
44bd8e53 4941 if (cpu->max_features) {
dc15c051 4942 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 4943 /* Override only features that weren't set explicitly
4944 * by the user.
4945 */
4946 env->features[w] |=
4947 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
0d914f39
EH		 4948 ~env->user_features[w] & \
4949 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 4950 }
4951 }
4952
2fae0d96
EH		 4953 for (l = plus_features; l; l = l->next) {
4954 const char *prop = l->data;
4955 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
4956 if (local_err) {
4957 goto out;
4958 }
4959 }
4960
4961 for (l = minus_features; l; l = l->next) {
4962 const char *prop = l->data;
4963 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
4964 if (local_err) {
4965 goto out;
4966 }
dc15c051
IM		 4967 }
4968
aec661de
EH		 4969 if (!kvm_enabled() || !cpu->expose_kvm) {
4970 env->features[FEAT_KVM] = 0;
4971 }
4972
2ca8a8be 4973 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 4974
4975 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
4976 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
4977 if (cpu->full_cpuid_auto_level) {
4978 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
4979 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
4980 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
4981 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
4982 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
4983 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
4984 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 4985 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 4986 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
4987 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
4988 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 4989 /* SVM requires CPUID[0x8000000A] */
4990 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
4991 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
4992 }
6cb8f2a6
BS		 4993
4994 /* SEV requires CPUID[0x8000001F] */
4995 if (sev_enabled()) {
4996 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
4997 }
c39c0edf
EH		 4998 }
4999
5000 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
5001 if (env->cpuid_level == UINT32_MAX) {
5002 env->cpuid_level = env->cpuid_min_level;
5003 }
5004 if (env->cpuid_xlevel == UINT32_MAX) {
5005 env->cpuid_xlevel = env->cpuid_min_xlevel;
5006 }
5007 if (env->cpuid_xlevel2 == UINT32_MAX) {
5008 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 5009 }
7a059953 5010
41f3d4d6
EH		 5011out:
5012 if (local_err != NULL) {
5013 error_propagate(errp, local_err);
5014 }
5015}
5016
b8d834a0
EH		 5017/*
5018 * Finishes initialization of CPUID data, filters CPU feature
5019 * words based on host availability of each feature.
5020 *
5021 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
5022 */
5023static int x86_cpu_filter_features(X86CPU *cpu)
5024{
5025 CPUX86State *env = &cpu->env;
5026 FeatureWord w;
5027 int rv = 0;
5028
5029 for (w = 0; w < FEATURE_WORDS; w++) {
5030 uint32_t host_feat =
5031 x86_cpu_get_supported_feature_word(w, false);
5032 uint32_t requested_features = env->features[w];
5033 env->features[w] &= host_feat;
5034 cpu->filtered_features[w] = requested_features & ~env->features[w];
5035 if (cpu->filtered_features[w]) {
5036 rv = 1;
5037 }
5038 }
5039
e37a5c7f
CP		 5040 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5041 kvm_enabled()) {
5042 KVMState *s = CPU(cpu)->kvm_state;
5043 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
5044 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
5045 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
5046 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
5047 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
5048
5049 if (!eax_0 ||
5050 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
5051 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
5052 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
5053 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
5054 INTEL_PT_ADDR_RANGES_NUM) ||
5055 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96
LK		 5056 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
5057 (ecx_0 & INTEL_PT_IP_LIP)) {
e37a5c7f
CP		 5058 /*
5059 * Processor Trace capabilities aren't configurable, so if the
5060 * host can't emulate the capabilities we report on
5061 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
5062 */
5063 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
5064 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
5065 rv = 1;
5066 }
5067 }
5068
b8d834a0
EH		 5069 return rv;
5070}
5071
41f3d4d6
EH		 5072#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
5073 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
5074 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
5075#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
5076 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
5077 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
5078static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
5079{
5080 CPUState *cs = CPU(dev);
5081 X86CPU *cpu = X86_CPU(dev);
5082 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5083 CPUX86State *env = &cpu->env;
5084 Error *local_err = NULL;
5085 static bool ht_warned;
5086
2266d443
MT		 5087 if (xcc->host_cpuid_required) {
5088 if (!accel_uses_host_cpuid()) {
5089 char *name = x86_cpu_class_get_model_name(xcc);
5090 error_setg(&local_err, "CPU model '%s' requires KVM", name);
5091 g_free(name);
5092 goto out;
5093 }
5094
5095 if (enable_cpu_pm) {
5096 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
5097 &cpu->mwait.ecx, &cpu->mwait.edx);
5098 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
5099 }
41f3d4d6
EH		 5100 }
5101
2266d443
MT		 5102 /* mwait extended info: needed for Core compatibility */
5103 /* We always wake on interrupt even if host does not have the capability */
5104 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
5105
41f3d4d6
EH		 5106 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
5107 error_setg(errp, "apic-id property was not initialized properly");
5108 return;
5109 }
5110
b8d834a0 5111 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 5112 if (local_err) {
5113 goto out;
5114 }
5115
8ca30e86
EH		 5116 if (x86_cpu_filter_features(cpu) &&
5117 (cpu->check_cpuid || cpu->enforce_cpuid)) {
5118 x86_cpu_report_filtered_features(cpu);
5119 if (cpu->enforce_cpuid) {
5120 error_setg(&local_err,
d6dcc558 5121 accel_uses_host_cpuid() ?
8ca30e86
EH		 5122 "Host doesn't support requested features" :
5123 "TCG doesn't support requested features");
5124 goto out;
5125 }
9997cf7b
EH		 5126 }
5127
9b15cd9e
IM		 5128 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
5129 * CPUID[1].EDX.
5130 */
e48638fd 5131 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 5132 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
5133 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 5134 & CPUID_EXT2_AMD_ALIASES);
5135 }
5136
11f6fee5
DDAG		 5137 /* For 64bit systems think about the number of physical bits to present.
5138 * ideally this should be the same as the host; anything other than matching
5139 * the host can cause incorrect guest behaviour.
5140 * QEMU used to pick the magic value of 40 bits that corresponds to
5141 * consumer AMD devices but nothing else.
5142 */
af45907a 5143 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 5144 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 5145 uint32_t host_phys_bits = x86_host_phys_bits();
5146 static bool warned;
5147
5148 if (cpu->host_phys_bits) {
5149 /* The user asked for us to use the host physical bits */
5150 cpu->phys_bits = host_phys_bits;
5151 }
5152
5153 /* Print a warning if the user set it to a value that's not the
5154 * host value.
5155 */
5156 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
5157 !warned) {
3dc6f869
AF		 5158 warn_report("Host physical bits (%u)"
5159 " does not match phys-bits property (%u)",
5160 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 5161 warned = true;
5162 }
5163
5164 if (cpu->phys_bits &&
5165 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
5166 cpu->phys_bits < 32)) {
af45907a
DDAG		 5167 error_setg(errp, "phys-bits should be between 32 and %u "
5168 " (but is %u)",
5169 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
5170 return;
5171 }
5172 } else {
11f6fee5 5173 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 5174 error_setg(errp, "TCG only supports phys-bits=%u",
5175 TCG_PHYS_ADDR_BITS);
5176 return;
5177 }
5178 }
11f6fee5
DDAG		 5179 /* 0 means it was not explicitly set by the user (or by machine
5180 * compat_props or by the host code above). In this case, the default
5181 * is the value used by TCG (40).
5182 */
5183 if (cpu->phys_bits == 0) {
5184 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
5185 }
af45907a
DDAG		 5186 } else {
5187 /* For 32 bit systems don't use the user set value, but keep
5188 * phys_bits consistent with what we tell the guest.
5189 */
5190 if (cpu->phys_bits != 0) {
5191 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
5192 return;
5193 }
fefb41bf 5194
af45907a
DDAG		 5195 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
5196 cpu->phys_bits = 36;
5197 } else {
5198 cpu->phys_bits = 32;
5199 }
5200 }
a9f27ea9
EH		 5201
5202 /* Cache information initialization */
5203 if (!cpu->legacy_cache) {
5204 if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
5205 char *name = x86_cpu_class_get_model_name(xcc);
5206 error_setg(errp,
5207 "CPU model '%s' doesn't support legacy-cache=off", name);
5208 g_free(name);
5209 return;
5210 }
5211 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
5212 *xcc->cpu_def->cache_info;
5213 } else {
5214 /* Build legacy cache information */
5215 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
5216 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
5217 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
5218 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
5219
5220 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
5221 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
5222 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
5223 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
5224
5225 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
5226 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
5227 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
5228 env->cache_info_amd.l3_cache = &legacy_l3_cache;
5229 }
5230
5231
ce5b1bbf
LV		 5232 cpu_exec_realizefn(cs, &local_err);
5233 if (local_err != NULL) {
5234 error_propagate(errp, local_err);
5235 return;
5236 }
42ecabaa 5237
65dee380
IM		 5238#ifndef CONFIG_USER_ONLY
5239 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 5240
0514ef2f 5241 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 5242 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 5243 if (local_err != NULL) {
4dc1f449 5244 goto out;
bdeec802
IM		 5245 }
5246 }
65dee380
IM		 5247#endif
5248
7a059953 5249 mce_init(cpu);
2001d0cd
PB		 5250
5251#ifndef CONFIG_USER_ONLY
5252 if (tcg_enabled()) {
f809c605 5253 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 5254 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 5255
5256 /* Outer container... */
5257 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 5258 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 5259
5260 /* ... with two regions inside: normal system memory with low
5261 * priority, and...
5262 */
5263 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
5264 get_system_memory(), 0, ~0ull);
5265 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
5266 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 5267
5268 cs->num_ases = 2;
80ceb07a
PX		 5269 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
5270 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 5271
5272 /* ... SMRAM with higher priority, linked from /machine/smram. */
5273 cpu->machine_done.notify = x86_cpu_machine_done;
5274 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 5275 }
5276#endif
5277
14a10fc3 5278 qemu_init_vcpu(cs);
d3c64d6a 5279
6b2942f9
BM		 5280 /*
5281 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
5282 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
5283 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 5284 * users a warning.
5285 *
5286 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
5287 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
5288 */
0765691e
MA		 5289 if (IS_AMD_CPU(env) &&
5290 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
5291 cs->nr_threads > 1 && !ht_warned) {
5292 warn_report("This family of AMD CPU doesn't support "
5293 "hyperthreading(%d)",
5294 cs->nr_threads);
5295 error_printf("Please configure -smp options properly"
5296 " or try enabling topoext feature.\n");
5297 ht_warned = true;
e48638fd
WH		 5298 }
5299
d3c64d6a
IM		 5300 x86_cpu_apic_realize(cpu, &local_err);
5301 if (local_err != NULL) {
5302 goto out;
5303 }
14a10fc3 5304 cpu_reset(cs);
2b6f294c 5305
4dc1f449 5306 xcc->parent_realize(dev, &local_err);
2001d0cd 5307
4dc1f449
IM		 5308out:
5309 if (local_err != NULL) {
5310 error_propagate(errp, local_err);
5311 return;
5312 }
7a059953
AF		 5313}
5314
c884776e
IM		 5315static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
5316{
5317 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 5318 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5319 Error *local_err = NULL;
c884776e
IM		 5320
5321#ifndef CONFIG_USER_ONLY
5322 cpu_remove_sync(CPU(dev));
5323 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
5324#endif
5325
5326 if (cpu->apic_state) {
5327 object_unparent(OBJECT(cpu->apic_state));
5328 cpu->apic_state = NULL;
5329 }
7bbc124e
LV		 5330
5331 xcc->parent_unrealize(dev, &local_err);
5332 if (local_err != NULL) {
5333 error_propagate(errp, local_err);
5334 return;
5335 }
c884776e
IM		 5336}
5337
38e5c119 5338typedef struct BitProperty {
a7b0ffac 5339 FeatureWord w;
38e5c119
EH		 5340 uint32_t mask;
5341} BitProperty;
5342
d7bce999
EB		 5343static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
5344 void *opaque, Error **errp)
38e5c119 5345{
a7b0ffac 5346 X86CPU *cpu = X86_CPU(obj);
38e5c119 5347 BitProperty *fp = opaque;
a7b0ffac
EH		 5348 uint32_t f = cpu->env.features[fp->w];
5349 bool value = (f & fp->mask) == fp->mask;
51e72bc1 5350 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 5351}
5352
d7bce999
EB		 5353static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
5354 void *opaque, Error **errp)
38e5c119
EH		 5355{
5356 DeviceState *dev = DEVICE(obj);
a7b0ffac 5357 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 5358 BitProperty *fp = opaque;
5359 Error *local_err = NULL;
5360 bool value;
5361
5362 if (dev->realized) {
5363 qdev_prop_set_after_realize(dev, name, errp);
5364 return;
5365 }
5366
51e72bc1 5367 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 5368 if (local_err) {
5369 error_propagate(errp, local_err);
5370 return;
5371 }
5372
5373 if (value) {
a7b0ffac 5374 cpu->env.features[fp->w] |= fp->mask;
38e5c119 5375 } else {
a7b0ffac 5376 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 5377 }
d4a606b3 5378 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 5379}
5380
5381static void x86_cpu_release_bit_prop(Object *obj, const char *name,
5382 void *opaque)
5383{
5384 BitProperty *prop = opaque;
5385 g_free(prop);
5386}
5387
5388/* Register a boolean property to get/set a single bit in a uint32_t field.
5389 *
5390 * The same property name can be registered multiple times to make it affect
5391 * multiple bits in the same FeatureWord. In that case, the getter will return
5392 * true only if all bits are set.
5393 */
5394static void x86_cpu_register_bit_prop(X86CPU *cpu,
5395 const char *prop_name,
a7b0ffac 5396 FeatureWord w,
38e5c119
EH		 5397 int bitnr)
5398{
5399 BitProperty *fp;
5400 ObjectProperty *op;
5401 uint32_t mask = (1UL << bitnr);
5402
5403 op = object_property_find(OBJECT(cpu), prop_name, NULL);
5404 if (op) {
5405 fp = op->opaque;
a7b0ffac 5406 assert(fp->w == w);
38e5c119
EH		 5407 fp->mask |= mask;
5408 } else {
5409 fp = g_new0(BitProperty, 1);
a7b0ffac 5410 fp->w = w;
38e5c119
EH		 5411 fp->mask = mask;
5412 object_property_add(OBJECT(cpu), prop_name, "bool",
5413 x86_cpu_get_bit_prop,
5414 x86_cpu_set_bit_prop,
5415 x86_cpu_release_bit_prop, fp, &error_abort);
5416 }
5417}
5418
5419static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
5420 FeatureWord w,
5421 int bitnr)
5422{
38e5c119 5423 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 5424 const char *name = fi->feat_names[bitnr];
38e5c119 5425
16d2fcaa 5426 if (!name) {
38e5c119
EH		 5427 return;
5428 }
5429
fc7dfd20
EH		 5430 /* Property names should use "-" instead of "_".
5431 * Old names containing underscores are registered as aliases
5432 * using object_property_add_alias()
5433 */
16d2fcaa
EH		 5434 assert(!strchr(name, '_'));
5435 /* aliases don't use "|" delimiters anymore, they are registered
5436 * manually using object_property_add_alias() */
5437 assert(!strchr(name, '|'));
a7b0ffac 5438 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 5439}
5440
d187e08d
AN		 5441static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
5442{
5443 X86CPU *cpu = X86_CPU(cs);
5444 CPUX86State *env = &cpu->env;
5445 GuestPanicInformation *panic_info = NULL;
5446
5e953812 5447 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 5448 panic_info = g_malloc0(sizeof(GuestPanicInformation));
5449
e8ed97a6 5450 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 5451
5e953812 5452 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 5453 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
5454 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
5455 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
5456 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
5457 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 5458 }
5459
5460 return panic_info;
5461}
5462static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
5463 const char *name, void *opaque,
5464 Error **errp)
5465{
5466 CPUState *cs = CPU(obj);
5467 GuestPanicInformation *panic_info;
5468
5469 if (!cs->crash_occurred) {
5470 error_setg(errp, "No crash occured");
5471 return;
5472 }
5473
5474 panic_info = x86_cpu_get_crash_info(cs);
5475 if (panic_info == NULL) {
5476 error_setg(errp, "No crash information");
5477 return;
5478 }
5479
5480 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
5481 errp);
5482 qapi_free_GuestPanicInformation(panic_info);
5483}
5484
de024815
AF		 5485static void x86_cpu_initfn(Object *obj)
5486{
55e5c285 5487 CPUState *cs = CPU(obj);
de024815 5488 X86CPU *cpu = X86_CPU(obj);
d940ee9b 5489 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 5490 CPUX86State *env = &cpu->env;
38e5c119 5491 FeatureWord w;
de024815 5492
c05efcb1 5493 cs->env_ptr = env;
71ad61d3
AF		 5494
5495 object_property_add(obj, "family", "int",
95b8519d 5496 x86_cpuid_version_get_family,
71ad61d3 5497 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 5498 object_property_add(obj, "model", "int",
67e30c83 5499 x86_cpuid_version_get_model,
c5291a4f 5500 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 5501 object_property_add(obj, "stepping", "int",
35112e41 5502 x86_cpuid_version_get_stepping,
036e2222 5503 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 5504 object_property_add_str(obj, "vendor",
5505 x86_cpuid_get_vendor,
5506 x86_cpuid_set_vendor, NULL);
938d4c25 5507 object_property_add_str(obj, "model-id",
63e886eb 5508 x86_cpuid_get_model_id,
938d4c25 5509 x86_cpuid_set_model_id, NULL);
89e48965
AF		 5510 object_property_add(obj, "tsc-frequency", "int",
5511 x86_cpuid_get_tsc_freq,
5512 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 5513 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
5514 x86_cpu_get_feature_words,
7e5292b5
EH		 5515 NULL, NULL, (void *)env->features, NULL);
5516 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
5517 x86_cpu_get_feature_words,
5518 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 5519
d187e08d
AN		 5520 object_property_add(obj, "crash-information", "GuestPanicInformation",
5521 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
5522
92067bf4 5523 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 5524
38e5c119
EH		 5525 for (w = 0; w < FEATURE_WORDS; w++) {
5526 int bitnr;
5527
5528 for (bitnr = 0; bitnr < 32; bitnr++) {
5529 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
5530 }
5531 }
5532
16d2fcaa
EH		 5533 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
5534 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
5535 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
5536 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
5537 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
5538 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
5539 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
5540
54b8dc7c
EH		 5541 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
5542 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
5543 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
5544 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
5545 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
5546 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
5547 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
5548 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
5549 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
5550 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
5551 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
5552 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
5553 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
5554 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
5555 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
5556 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
5557 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
5558 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
5559 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
5560 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
5561 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
5562
0bacd8b3
EH		 5563 if (xcc->cpu_def) {
5564 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
5565 }
de024815
AF		 5566}
5567
997395d3
IM		 5568static int64_t x86_cpu_get_arch_id(CPUState *cs)
5569{
5570 X86CPU *cpu = X86_CPU(cs);
997395d3 5571
7e72a45c 5572 return cpu->apic_id;
997395d3
IM		 5573}
5574
444d5590
AF		 5575static bool x86_cpu_get_paging_enabled(const CPUState *cs)
5576{
5577 X86CPU *cpu = X86_CPU(cs);
5578
5579 return cpu->env.cr[0] & CR0_PG_MASK;
5580}
5581
f45748f1
AF		 5582static void x86_cpu_set_pc(CPUState *cs, vaddr value)
5583{
5584 X86CPU *cpu = X86_CPU(cs);
5585
5586 cpu->env.eip = value;
5587}
5588
bdf7ae5b
AF		 5589static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
5590{
5591 X86CPU *cpu = X86_CPU(cs);
5592
5593 cpu->env.eip = tb->pc - tb->cs_base;
5594}
5595
92d5f1a4 5596int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 5597{
5598 X86CPU *cpu = X86_CPU(cs);
5599 CPUX86State *env = &cpu->env;
5600
92d5f1a4
PB		 5601#if !defined(CONFIG_USER_ONLY)
5602 if (interrupt_request & CPU_INTERRUPT_POLL) {
5603 return CPU_INTERRUPT_POLL;
5604 }
5605#endif
5606 if (interrupt_request & CPU_INTERRUPT_SIPI) {
5607 return CPU_INTERRUPT_SIPI;
5608 }
5609
5610 if (env->hflags2 & HF2_GIF_MASK) {
5611 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
5612 !(env->hflags & HF_SMM_MASK)) {
5613 return CPU_INTERRUPT_SMI;
5614 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
5615 !(env->hflags2 & HF2_NMI_MASK)) {
5616 return CPU_INTERRUPT_NMI;
5617 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
5618 return CPU_INTERRUPT_MCE;
5619 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
5620 (((env->hflags2 & HF2_VINTR_MASK) &&
5621 (env->hflags2 & HF2_HIF_MASK)) ||
5622 (!(env->hflags2 & HF2_VINTR_MASK) &&
5623 (env->eflags & IF_MASK &&
5624 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
5625 return CPU_INTERRUPT_HARD;
5626#if !defined(CONFIG_USER_ONLY)
5627 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
5628 (env->eflags & IF_MASK) &&
5629 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
5630 return CPU_INTERRUPT_VIRQ;
5631#endif
5632 }
5633 }
5634
5635 return 0;
5636}
5637
5638static bool x86_cpu_has_work(CPUState *cs)
5639{
5640 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 5641}
5642
f50f3dd5
RH		 5643static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
5644{
5645 X86CPU *cpu = X86_CPU(cs);
5646 CPUX86State *env = &cpu->env;
5647
5648 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
5649 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
5650 : bfd_mach_i386_i8086);
5651 info->print_insn = print_insn_i386;
b666d2a4
RH		 5652
5653 info->cap_arch = CS_ARCH_X86;
5654 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
5655 : env->hflags & HF_CS32_MASK ? CS_MODE_32
5656 : CS_MODE_16);
15fa1a0a
RH		 5657 info->cap_insn_unit = 1;
5658 info->cap_insn_split = 8;
f50f3dd5
RH		 5659}
5660
35b1b927
TW		 5661void x86_update_hflags(CPUX86State *env)
5662{
5663 uint32_t hflags;
5664#define HFLAG_COPY_MASK \
5665 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5666 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5667 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5668 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5669
5670 hflags = env->hflags & HFLAG_COPY_MASK;
5671 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5672 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5673 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5674 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5675 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5676
5677 if (env->cr[4] & CR4_OSFXSR_MASK) {
5678 hflags |= HF_OSFXSR_MASK;
5679 }
5680
5681 if (env->efer & MSR_EFER_LMA) {
5682 hflags |= HF_LMA_MASK;
5683 }
5684
5685 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5686 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5687 } else {
5688 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5689 (DESC_B_SHIFT - HF_CS32_SHIFT);
5690 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5691 (DESC_B_SHIFT - HF_SS32_SHIFT);
5692 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5693 !(hflags & HF_CS32_MASK)) {
5694 hflags |= HF_ADDSEG_MASK;
5695 } else {
5696 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5697 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5698 }
5699 }
5700 env->hflags = hflags;
5701}
5702
9337e3b6 5703static Property x86_cpu_properties[] = {
2da00e31
IM		 5704#ifdef CONFIG_USER_ONLY
5705 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5706 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 5707 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5708 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5709 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 5710#else
5711 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 5712 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5713 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5714 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 5715#endif
15f8b142 5716 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 5717 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 5718 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 5719 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 5720 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 5721 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 5722 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 5723 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 5724 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 5725 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 5726 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 5727 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
9445597b 5728 DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
ba6a4fd9 5729 DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment, false),
47512009 5730 DEFINE_PROP_BOOL("hv-tlbflush", X86CPU, hyperv_tlbflush, false),
6b7a9830 5731 DEFINE_PROP_BOOL("hv-ipi", X86CPU, hyperv_ipi, false),
15e41345 5732 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 5733 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 5734 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 5735 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 5736 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 5737 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 5738 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5739 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5740 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5741 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5742 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5743 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5744 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 5745 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 5746 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 5747 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 5748 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 5749 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5750 false),
0b564e6f 5751 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 5752 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 5753 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
5754 true),
ab8f992e 5755 /*
a9f27ea9
EH		 5756 * lecacy_cache defaults to true unless the CPU model provides its
5757 * own cache information (see x86_cpu_load_def()).
ab8f992e 5758 */
a9f27ea9 5759 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 5760
5761 /*
5762 * From "Requirements for Implementing the Microsoft
5763 * Hypervisor Interface":
5764 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5765 *
5766 * "Starting with Windows Server 2012 and Windows 8, if
5767 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5768 * the hypervisor imposes no specific limit to the number of VPs.
5769 * In this case, Windows Server 2012 guest VMs may use more than
5770 * 64 VPs, up to the maximum supported number of processors applicable
5771 * to the specific Windows version being used."
5772 */
5773 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 5774 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
5775 false),
9337e3b6
EH		 5776 DEFINE_PROP_END_OF_LIST()
5777};
5778
5fd2087a
AF		 5779static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5780{
5781 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5782 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 5783 DeviceClass *dc = DEVICE_CLASS(oc);
5784
bf853881
PMD		 5785 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5786 &xcc->parent_realize);
5787 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5788 &xcc->parent_unrealize);
9337e3b6 5789 dc->props = x86_cpu_properties;
5fd2087a
AF		 5790
5791 xcc->parent_reset = cc->reset;
5792 cc->reset = x86_cpu_reset;
91b1df8c 5793 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 5794
500050d1 5795 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 5796 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 5797 cc->has_work = x86_cpu_has_work;
79c664f6 5798#ifdef CONFIG_TCG
97a8ea5a 5799 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 5800 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 5801#endif
878096ee 5802 cc->dump_state = x86_cpu_dump_state;
c86f106b 5803 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 5804 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 5805 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 5806 cc->gdb_read_register = x86_cpu_gdb_read_register;
5807 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 5808 cc->get_arch_id = x86_cpu_get_arch_id;
5809 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 5810#ifdef CONFIG_USER_ONLY
5811 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
5812#else
f8c45c65 5813 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 5814 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 5815 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 5816 cc->write_elf64_note = x86_cpu_write_elf64_note;
5817 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5818 cc->write_elf32_note = x86_cpu_write_elf32_note;
5819 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 5820 cc->vmsd = &vmstate_x86_cpu;
c72bf468 5821#endif
00fcd100
AB		 5822 cc->gdb_arch_name = x86_gdb_arch_name;
5823#ifdef TARGET_X86_64
b8158192
AB		 5824 cc->gdb_core_xml_file = "i386-64bit.xml";
5825 cc->gdb_num_core_regs = 57;
00fcd100 5826#else
b8158192
AB		 5827 cc->gdb_core_xml_file = "i386-32bit.xml";
5828 cc->gdb_num_core_regs = 41;
00fcd100 5829#endif
79c664f6 5830#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 5831 cc->debug_excp_handler = breakpoint_handler;
5832#endif
374e0cd4
RH		 5833 cc->cpu_exec_enter = x86_cpu_exec_enter;
5834 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 5835#ifdef CONFIG_TCG
55c3ceef 5836 cc->tcg_initialize = tcg_x86_init;
74d7fc7f 5837#endif
f50f3dd5 5838 cc->disas_set_info = x86_disas_set_info;
4c315c27 5839
e90f2a8c 5840 dc->user_creatable = true;
5fd2087a
AF		 5841}
5842
5843static const TypeInfo x86_cpu_type_info = {
5844 .name = TYPE_X86_CPU,
5845 .parent = TYPE_CPU,
5846 .instance_size = sizeof(X86CPU),
de024815 5847 .instance_init = x86_cpu_initfn,
d940ee9b 5848 .abstract = true,
5fd2087a
AF		 5849 .class_size = sizeof(X86CPUClass),
5850 .class_init = x86_cpu_common_class_init,
5851};
5852
5adbed30
EH		 5853
5854/* "base" CPU model, used by query-cpu-model-expansion */
5855static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
5856{
5857 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5858
5859 xcc->static_model = true;
5860 xcc->migration_safe = true;
5861 xcc->model_description = "base CPU model type with no features enabled";
5862 xcc->ordering = 8;
5863}
5864
5865static const TypeInfo x86_base_cpu_type_info = {
5866 .name = X86_CPU_TYPE_NAME("base"),
5867 .parent = TYPE_X86_CPU,
5868 .class_init = x86_cpu_base_class_init,
5869};
5870
5fd2087a
AF		 5871static void x86_cpu_register_types(void)
5872{
d940ee9b
EH		 5873 int i;
5874
5fd2087a 5875 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 5876 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
5877 x86_register_cpudef_type(&builtin_x86_defs[i]);
5878 }
c62f2630 5879 type_register_static(&max_x86_cpu_type_info);
5adbed30 5880 type_register_static(&x86_base_cpu_type_info);
d6dcc558 5881#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 5882 type_register_static(&host_x86_cpu_type_info);
5883#endif
5fd2087a
AF		 5884}
5885
5886type_init(x86_cpu_register_types)
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